1 | /* $Id: HWACCMInternal.h 11757 2008-08-28 12:30:01Z vboxsync $ */
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2 | /** @file
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3 | * HWACCM - Internal header file.
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4 | */
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5 |
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6 | /*
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7 | * Copyright (C) 2006-2007 Sun Microsystems, Inc.
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8 | *
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9 | * This file is part of VirtualBox Open Source Edition (OSE), as
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10 | * available from http://www.virtualbox.org. This file is free software;
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11 | * you can redistribute it and/or modify it under the terms of the GNU
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12 | * General Public License (GPL) as published by the Free Software
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13 | * Foundation, in version 2 as it comes in the "COPYING" file of the
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14 | * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
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15 | * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
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16 | *
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17 | * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
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18 | * Clara, CA 95054 USA or visit http://www.sun.com if you need
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19 | * additional information or have any questions.
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20 | */
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21 |
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22 | #ifndef ___HWACCMInternal_h
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23 | #define ___HWACCMInternal_h
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24 |
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25 | #include <VBox/cdefs.h>
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26 | #include <VBox/types.h>
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27 | #include <VBox/em.h>
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28 | #include <VBox/stam.h>
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29 | #include <VBox/dis.h>
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30 | #include <VBox/hwaccm.h>
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31 | #include <VBox/pgm.h>
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32 | #include <iprt/memobj.h>
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33 | #include <iprt/cpuset.h>
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34 | #include <iprt/mp.h>
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35 |
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36 | #if HC_ARCH_BITS == 64
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37 | /* Enable 64 bits guest support. */
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38 | # define VBOX_ENABLE_64_BITS_GUESTS
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39 | #endif
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40 |
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41 | __BEGIN_DECLS
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42 |
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43 |
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44 | /** @defgroup grp_hwaccm_int Internal
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45 | * @ingroup grp_hwaccm
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46 | * @internal
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47 | * @{
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48 | */
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49 |
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50 |
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51 | /**
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52 | * Converts a HWACCM pointer into a VM pointer.
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53 | * @returns Pointer to the VM structure the EM is part of.
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54 | * @param pHWACCM Pointer to HWACCM instance data.
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55 | */
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56 | #define HWACCM2VM(pHWACCM) ( (PVM)((char*)pHWACCM - pHWACCM->offVM) )
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57 |
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58 | /** Maximum number of exit reason statistics counters. */
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59 | #define MAX_EXITREASON_STAT 0x100
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60 | #define MASK_EXITREASON_STAT 0xff
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61 |
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62 | /** @name Changed flags
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63 | * These flags are used to keep track of which important registers that
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64 | * have been changed since last they were reset.
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65 | * @{
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66 | */
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67 | #define HWACCM_CHANGED_GUEST_FPU RT_BIT(0)
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68 | #define HWACCM_CHANGED_GUEST_CR0 RT_BIT(1)
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69 | #define HWACCM_CHANGED_GUEST_CR3 RT_BIT(2)
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70 | #define HWACCM_CHANGED_GUEST_CR4 RT_BIT(3)
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71 | #define HWACCM_CHANGED_GUEST_GDTR RT_BIT(4)
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72 | #define HWACCM_CHANGED_GUEST_IDTR RT_BIT(5)
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73 | #define HWACCM_CHANGED_GUEST_LDTR RT_BIT(6)
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74 | #define HWACCM_CHANGED_GUEST_TR RT_BIT(7)
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75 | #define HWACCM_CHANGED_GUEST_SYSENTER_MSR RT_BIT(8)
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76 | #define HWACCM_CHANGED_GUEST_SEGMENT_REGS RT_BIT(9)
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77 | #define HWACCM_CHANGED_GUEST_DEBUG RT_BIT(10)
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78 | #define HWACCM_CHANGED_HOST_CONTEXT RT_BIT(11)
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79 |
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80 | #define HWACCM_CHANGED_ALL ( HWACCM_CHANGED_GUEST_SEGMENT_REGS \
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81 | | HWACCM_CHANGED_GUEST_CR0 \
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82 | | HWACCM_CHANGED_GUEST_CR3 \
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83 | | HWACCM_CHANGED_GUEST_CR4 \
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84 | | HWACCM_CHANGED_GUEST_GDTR \
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85 | | HWACCM_CHANGED_GUEST_IDTR \
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86 | | HWACCM_CHANGED_GUEST_LDTR \
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87 | | HWACCM_CHANGED_GUEST_TR \
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88 | | HWACCM_CHANGED_GUEST_SYSENTER_MSR \
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89 | | HWACCM_CHANGED_GUEST_FPU \
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90 | | HWACCM_CHANGED_GUEST_DEBUG \
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91 | | HWACCM_CHANGED_HOST_CONTEXT)
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92 |
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93 | #define HWACCM_CHANGED_ALL_GUEST ( HWACCM_CHANGED_GUEST_SEGMENT_REGS \
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94 | | HWACCM_CHANGED_GUEST_CR0 \
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95 | | HWACCM_CHANGED_GUEST_CR3 \
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96 | | HWACCM_CHANGED_GUEST_CR4 \
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97 | | HWACCM_CHANGED_GUEST_GDTR \
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98 | | HWACCM_CHANGED_GUEST_IDTR \
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99 | | HWACCM_CHANGED_GUEST_LDTR \
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100 | | HWACCM_CHANGED_GUEST_TR \
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101 | | HWACCM_CHANGED_GUEST_SYSENTER_MSR \
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102 | | HWACCM_CHANGED_GUEST_DEBUG \
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103 | | HWACCM_CHANGED_GUEST_FPU)
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104 |
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105 | /** @} */
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106 |
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107 | /** @name Intercepted traps
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108 | * Traps that need to be intercepted so we can correctly dispatch them to the guest if required.
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109 | * Currently #NM and #PF only
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110 | */
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111 | #ifdef VBOX_STRICT
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112 | #define HWACCM_VMX_TRAP_MASK RT_BIT(X86_XCPT_DE) | RT_BIT(X86_XCPT_NM) | RT_BIT(X86_XCPT_PF) | RT_BIT(X86_XCPT_UD) | RT_BIT(X86_XCPT_NP) | RT_BIT(X86_XCPT_SS) | RT_BIT(X86_XCPT_GP) | RT_BIT(X86_XCPT_MF)
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113 | #define HWACCM_SVM_TRAP_MASK HWACCM_VMX_TRAP_MASK
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114 | #else
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115 | #define HWACCM_VMX_TRAP_MASK RT_BIT(X86_XCPT_NM) | RT_BIT(X86_XCPT_PF)
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116 | #define HWACCM_SVM_TRAP_MASK HWACCM_VMX_TRAP_MASK
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117 | #endif
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118 | /** @} */
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119 |
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120 |
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121 | /** Maxium resume loops allowed in ring 0 (safety precaution) */
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122 | #define HWACCM_MAX_RESUME_LOOPS 1024
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123 |
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124 | /** HWACCM SSM version
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125 | */
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126 | #define HWACCM_SSM_VERSION 3
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127 |
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128 | /* Per-cpu information. */
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129 | typedef struct
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130 | {
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131 | RTCPUID idCpu;
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132 |
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133 | RTR0MEMOBJ pMemObj;
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134 | /* Current ASID (AMD-V only) */
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135 | uint32_t uCurrentASID;
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136 | /* TLB flush count */
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137 | uint32_t cTLBFlushes;
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138 |
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139 | /* Set the first time a cpu is used to make sure we start with a clean TLB. */
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140 | bool fFlushTLB;
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141 |
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142 | bool fConfigured;
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143 | } HWACCM_CPUINFO;
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144 | typedef HWACCM_CPUINFO *PHWACCM_CPUINFO;
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145 |
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146 | /* VT-x capability qword. */
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147 | typedef union
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148 | {
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149 | struct
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150 | {
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151 | uint32_t disallowed0;
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152 | uint32_t allowed1;
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153 | } n;
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154 | uint64_t u;
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155 | } VMX_CAPABILITY;
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156 |
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157 | /**
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158 | * HWACCM VM Instance data.
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159 | * Changes to this must checked against the padding of the cfgm union in VM!
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160 | */
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161 | typedef struct HWACCM
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162 | {
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163 | /** Offset to the VM structure.
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164 | * See HWACCM2VM(). */
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165 | RTUINT offVM;
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166 |
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167 | /** Set when we've initialized VMX or SVM. */
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168 | bool fInitialized;
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169 | /** Set when we're using VMX/SVN at that moment. */
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170 | bool fActive;
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171 |
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172 | /** Set when hardware acceleration is allowed. */
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173 | bool fAllowed;
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174 |
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175 | /** Set if nested paging is enabled. */
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176 | bool fNestedPaging;
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177 |
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178 | /** Set if nested paging is allowed. */
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179 | bool fAllowNestedPaging;
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180 |
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181 | /** HWACCM_CHANGED_* flags. */
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182 | uint32_t fContextUseFlags;
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183 |
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184 | /** Old style FPU reporting trap mask override performed (optimization) */
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185 | uint32_t fFPUOldStyleOverride;
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186 |
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187 | /** And mask for copying register contents. */
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188 | uint64_t u64RegisterMask;
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189 | struct
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190 | {
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191 | /** Set by the ring-0 driver to indicate VMX is supported by the CPU. */
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192 | bool fSupported;
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193 |
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194 | /** Set when we've enabled VMX. */
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195 | bool fEnabled;
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196 |
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197 | /** Set if we can use VMXResume to execute guest code. */
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198 | bool fResumeVM;
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199 |
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200 | /** R0 memory object for the VM control structure (VMCS). */
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201 | RTR0MEMOBJ pMemObjVMCS;
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202 | /** Physical address of the VM control structure (VMCS). */
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203 | RTHCPHYS pVMCSPhys;
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204 | /** Virtual address of the VM control structure (VMCS). */
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205 | R0PTRTYPE(void *) pVMCS;
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206 |
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207 | /** R0 memory object for the TSS page used for real mode emulation. */
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208 | RTR0MEMOBJ pMemObjRealModeTSS;
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209 | /** Physical address of the TSS page used for real mode emulation. */
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210 | RTHCPHYS pRealModeTSSPhys;
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211 | /** Virtual address of the TSS page used for real mode emulation. */
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212 | R0PTRTYPE(PVBOXTSS) pRealModeTSS;
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213 |
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214 | /** R0 memory object for the virtual APIC mmio cache. */
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215 | RTR0MEMOBJ pMemObjAPIC;
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216 | /** Physical address of the virtual APIC mmio cache. */
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217 | RTHCPHYS pAPICPhys;
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218 | /** Virtual address of the virtual APIC mmio cache. */
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219 | R0PTRTYPE(uint8_t *) pAPIC;
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220 |
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221 | /** R0 memory object for the MSR bitmap (1 page). */
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222 | RTR0MEMOBJ pMemObjMSRBitmap;
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223 | /** Physical address of the MSR bitmap (1 page). */
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224 | RTHCPHYS pMSRBitmapPhys;
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225 | /** Virtual address of the MSR bitmap (1 page). */
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226 | R0PTRTYPE(uint8_t *) pMSRBitmap;
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227 |
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228 | /** R0 memory object for the MSR entry load page (guest MSRs). */
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229 | RTR0MEMOBJ pMemObjMSREntryLoad;
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230 | /** Physical address of the MSR entry load page (guest MSRs). */
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231 | RTHCPHYS pMSREntryLoadPhys;
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232 | /** Virtual address of the MSR entry load page (guest MSRs). */
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233 | R0PTRTYPE(uint8_t *) pMSREntryLoad;
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234 |
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235 | /** R0 memory object for the MSR exit store page (guest MSRs). */
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236 | RTR0MEMOBJ pMemObjMSRExitStore;
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237 | /** Physical address of the MSR exit store page (guest MSRs). */
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238 | RTHCPHYS pMSRExitStorePhys;
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239 | /** Virtual address of the MSR exit store page (guest MSRs). */
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240 | R0PTRTYPE(uint8_t *) pMSRExitStore;
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241 |
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242 | /** R0 memory object for the MSR exit load page (host MSRs). */
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243 | RTR0MEMOBJ pMemObjMSRExitLoad;
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244 | /** Physical address of the MSR exit load page (host MSRs). */
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245 | RTHCPHYS pMSRExitLoadPhys;
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246 | /** Virtual address of the MSR exit load page (host MSRs). */
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247 | R0PTRTYPE(uint8_t *) pMSRExitLoad;
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248 |
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249 | /** Ring 0 handlers for VT-x. */
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250 | DECLR0CALLBACKMEMBER(int, pfnStartVM,(RTHCUINT fResume, PCPUMCTX pCtx));
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251 |
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252 | /** Host CR4 value (set by ring-0 VMX init) */
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253 | uint64_t hostCR4;
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254 |
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255 | /** Current VMX_VMCS_CTRL_PROC_EXEC_CONTROLS. */
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256 | uint64_t proc_ctls;
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257 |
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258 | /** Current CR0 mask. */
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259 | uint64_t cr0_mask;
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260 | /** Current CR4 mask. */
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261 | uint64_t cr4_mask;
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262 |
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263 | /** VMX MSR values */
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264 | struct
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265 | {
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266 | uint64_t feature_ctrl;
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267 | uint64_t vmx_basic_info;
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268 | VMX_CAPABILITY vmx_pin_ctls;
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269 | VMX_CAPABILITY vmx_proc_ctls;
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270 | VMX_CAPABILITY vmx_proc_ctls2;
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271 | VMX_CAPABILITY vmx_exit;
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272 | VMX_CAPABILITY vmx_entry;
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273 | uint64_t vmx_misc;
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274 | uint64_t vmx_cr0_fixed0;
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275 | uint64_t vmx_cr0_fixed1;
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276 | uint64_t vmx_cr4_fixed0;
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277 | uint64_t vmx_cr4_fixed1;
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278 | uint64_t vmx_vmcs_enum;
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279 | uint64_t vmx_eptcaps;
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280 | } msr;
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281 |
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282 | /* Last instruction error */
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283 | uint32_t ulLastInstrError;
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284 | } vmx;
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285 |
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286 | struct
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287 | {
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288 | /** Set by the ring-0 driver to indicate SVM is supported by the CPU. */
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289 | bool fSupported;
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290 | /** Set when we've enabled SVM. */
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291 | bool fEnabled;
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292 | /** Set if we don't have to flush the TLB on VM entry. */
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293 | bool fResumeVM;
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294 | /** Set if erratum 170 affects the AMD cpu. */
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295 | bool fAlwaysFlushTLB;
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296 | /** Set if we need to flush the TLB during the world switch. */
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297 | bool fForceTLBFlush;
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298 |
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299 | /* Id of the last cpu we were executing code on (NIL_RTCPUID for the first time) */
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300 | RTCPUID idLastCpu;
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301 |
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302 | /* TLB flush count */
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303 | uint32_t cTLBFlushes;
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304 |
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305 | /* Current ASID in use by the VM */
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306 | uint32_t uCurrentASID;
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307 |
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308 | /** R0 memory object for the VM control block (VMCB). */
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309 | RTR0MEMOBJ pMemObjVMCB;
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310 | /** Physical address of the VM control block (VMCB). */
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311 | RTHCPHYS pVMCBPhys;
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312 | /** Virtual address of the VM control block (VMCB). */
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313 | R0PTRTYPE(void *) pVMCB;
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314 |
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315 | /** R0 memory object for the host VM control block (VMCB). */
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316 | RTR0MEMOBJ pMemObjVMCBHost;
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317 | /** Physical address of the host VM control block (VMCB). */
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318 | RTHCPHYS pVMCBHostPhys;
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319 | /** Virtual address of the host VM control block (VMCB). */
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320 | R0PTRTYPE(void *) pVMCBHost;
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321 |
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322 | /** R0 memory object for the IO bitmap (12kb). */
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323 | RTR0MEMOBJ pMemObjIOBitmap;
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324 | /** Physical address of the IO bitmap (12kb). */
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325 | RTHCPHYS pIOBitmapPhys;
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326 | /** Virtual address of the IO bitmap. */
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327 | R0PTRTYPE(void *) pIOBitmap;
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328 |
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329 | /** R0 memory object for the MSR bitmap (8kb). */
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330 | RTR0MEMOBJ pMemObjMSRBitmap;
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331 | /** Physical address of the MSR bitmap (8kb). */
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332 | RTHCPHYS pMSRBitmapPhys;
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333 | /** Virtual address of the MSR bitmap. */
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334 | R0PTRTYPE(void *) pMSRBitmap;
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335 |
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336 | /** Ring 0 handlers for VT-x. */
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337 | DECLR0CALLBACKMEMBER(int, pfnVMRun,(RTHCPHYS pVMCBHostPhys, RTHCPHYS pVMCBPhys, PCPUMCTX pCtx));
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338 |
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339 | /** SVM revision. */
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340 | uint32_t u32Rev;
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341 |
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342 | /** Maximum ASID allowed. */
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343 | uint32_t u32MaxASID;
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344 |
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345 | /** SVM feature bits from cpuid 0x8000000a */
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346 | uint32_t u32Features;
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347 | } svm;
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348 |
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349 | struct
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350 | {
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351 | uint32_t u32AMDFeatureECX;
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352 | uint32_t u32AMDFeatureEDX;
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353 | } cpuid;
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354 |
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355 | /* Event injection state. */
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356 | struct
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357 | {
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358 | uint32_t fPending;
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359 | uint32_t errCode;
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360 | uint64_t intInfo;
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361 | } Event;
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362 |
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363 | /** Saved error from detection */
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364 | int32_t lLastError;
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365 |
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366 | /** HWACCMR0Init was run */
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367 | bool fHWACCMR0Init;
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368 |
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369 | /** Currenty shadow paging mode. */
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370 | PGMMODE enmShadowMode;
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371 |
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372 | STAMPROFILEADV StatEntry;
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373 | STAMPROFILEADV StatExit;
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374 | STAMPROFILEADV StatInGC;
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375 |
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376 | STAMCOUNTER StatIntInject;
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377 |
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378 | STAMCOUNTER StatExitShadowNM;
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379 | STAMCOUNTER StatExitGuestNM;
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380 | STAMCOUNTER StatExitShadowPF;
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381 | STAMCOUNTER StatExitGuestPF;
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382 | STAMCOUNTER StatExitGuestUD;
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383 | STAMCOUNTER StatExitGuestSS;
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384 | STAMCOUNTER StatExitGuestNP;
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385 | STAMCOUNTER StatExitGuestGP;
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386 | STAMCOUNTER StatExitGuestDE;
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387 | STAMCOUNTER StatExitGuestMF;
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388 | STAMCOUNTER StatExitInvpg;
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389 | STAMCOUNTER StatExitInvd;
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390 | STAMCOUNTER StatExitCpuid;
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391 | STAMCOUNTER StatExitRdtsc;
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392 | STAMCOUNTER StatExitCRxWrite;
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393 | STAMCOUNTER StatExitCRxRead;
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394 | STAMCOUNTER StatExitDRxWrite;
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395 | STAMCOUNTER StatExitDRxRead;
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396 | STAMCOUNTER StatExitCLTS;
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397 | STAMCOUNTER StatExitLMSW;
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398 | STAMCOUNTER StatExitIOWrite;
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399 | STAMCOUNTER StatExitIORead;
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400 | STAMCOUNTER StatExitIOStringWrite;
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401 | STAMCOUNTER StatExitIOStringRead;
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402 | STAMCOUNTER StatExitIrqWindow;
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403 | STAMCOUNTER StatExitMaxResume;
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404 | STAMCOUNTER StatIntReinject;
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405 | STAMCOUNTER StatPendingHostIrq;
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406 |
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407 | STAMCOUNTER StatFlushPageManual;
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408 | STAMCOUNTER StatFlushPhysPageManual;
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409 | STAMCOUNTER StatFlushTLBManual;
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410 | STAMCOUNTER StatFlushPageInvlpg;
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411 | STAMCOUNTER StatFlushTLBWorldSwitch;
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412 | STAMCOUNTER StatNoFlushTLBWorldSwitch;
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413 | STAMCOUNTER StatFlushTLBCRxChange;
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414 | STAMCOUNTER StatFlushASID;
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415 |
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416 | STAMCOUNTER StatSwitchGuestIrq;
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417 | STAMCOUNTER StatSwitchToR3;
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418 |
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419 | STAMCOUNTER StatTSCOffset;
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420 | STAMCOUNTER StatTSCIntercept;
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421 |
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422 | STAMCOUNTER StatExitReasonNPF;
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423 | R3PTRTYPE(PSTAMCOUNTER) pStatExitReason;
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424 | R0PTRTYPE(PSTAMCOUNTER) pStatExitReasonR0;
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425 | } HWACCM;
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426 | /** Pointer to HWACCM VM instance data. */
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427 | typedef HWACCM *PHWACCM;
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428 |
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429 | #ifdef IN_RING0
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430 |
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431 | /**
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432 | * Returns the cpu structure for the current cpu.
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433 | * Keep in mind that there is no guarantee it will stay the same (long jumps to ring 3!!!).
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434 | *
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435 | * @returns cpu structure pointer
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436 | * @param pVM The VM to operate on.
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437 | */
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438 | HWACCMR0DECL(PHWACCM_CPUINFO) HWACCMR0GetCurrentCpu();
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439 |
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440 | #ifdef VBOX_STRICT
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441 | HWACCMR0DECL(void) HWACCMDumpRegs(PVM pVM, PCPUMCTX pCtx);
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442 | HWACCMR0DECL(void) HWACCMR0DumpDescriptor(PX86DESCHC Desc, RTSEL Sel, const char *pszMsg);
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443 | #else
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444 | #define HWACCMDumpRegs(a, b) do { } while (0)
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445 | #define HWACCMR0DumpDescriptor(a, b, c) do { } while (0)
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446 | #endif
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447 |
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448 | /* Dummy callback handlers. */
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449 | HWACCMR0DECL(int) HWACCMR0DummyEnter(PVM pVM, PHWACCM_CPUINFO pCpu);
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450 | HWACCMR0DECL(int) HWACCMR0DummyLeave(PVM pVM);
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451 | HWACCMR0DECL(int) HWACCMR0DummyEnableCpu(PHWACCM_CPUINFO pCpu, PVM pVM, void *pvPageCpu, RTHCPHYS pPageCpuPhys);
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452 | HWACCMR0DECL(int) HWACCMR0DummyDisableCpu(PHWACCM_CPUINFO pCpu, void *pvPageCpu, RTHCPHYS pPageCpuPhys);
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453 | HWACCMR0DECL(int) HWACCMR0DummyInitVM(PVM pVM);
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454 | HWACCMR0DECL(int) HWACCMR0DummyTermVM(PVM pVM);
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455 | HWACCMR0DECL(int) HWACCMR0DummySetupVM(PVM pVM);
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456 | HWACCMR0DECL(int) HWACCMR0DummyRunGuestCode(PVM pVM, CPUMCTX *pCtx);
|
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457 | HWACCMR0DECL(int) HWACCMR0DummySaveHostState(PVM pVM);
|
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458 | HWACCMR0DECL(int) HWACCMR0DummyLoadGuestState(PVM pVM, CPUMCTX *pCtx);
|
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459 |
|
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460 | #endif
|
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461 |
|
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462 | /** @} */
|
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463 |
|
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464 | __END_DECLS
|
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465 |
|
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466 | #endif
|
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467 |
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