VirtualBox

source: vbox/trunk/src/VBox/VMM/HWACCMInternal.h@ 11964

Last change on this file since 11964 was 11757, checked in by vboxsync, 16 years ago

No room for this

  • Property svn:eol-style set to native
  • Property svn:keywords set to Id
File size: 17.6 KB
Line 
1/* $Id: HWACCMInternal.h 11757 2008-08-28 12:30:01Z vboxsync $ */
2/** @file
3 * HWACCM - Internal header file.
4 */
5
6/*
7 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 */
21
22#ifndef ___HWACCMInternal_h
23#define ___HWACCMInternal_h
24
25#include <VBox/cdefs.h>
26#include <VBox/types.h>
27#include <VBox/em.h>
28#include <VBox/stam.h>
29#include <VBox/dis.h>
30#include <VBox/hwaccm.h>
31#include <VBox/pgm.h>
32#include <iprt/memobj.h>
33#include <iprt/cpuset.h>
34#include <iprt/mp.h>
35
36#if HC_ARCH_BITS == 64
37/* Enable 64 bits guest support. */
38# define VBOX_ENABLE_64_BITS_GUESTS
39#endif
40
41__BEGIN_DECLS
42
43
44/** @defgroup grp_hwaccm_int Internal
45 * @ingroup grp_hwaccm
46 * @internal
47 * @{
48 */
49
50
51/**
52 * Converts a HWACCM pointer into a VM pointer.
53 * @returns Pointer to the VM structure the EM is part of.
54 * @param pHWACCM Pointer to HWACCM instance data.
55 */
56#define HWACCM2VM(pHWACCM) ( (PVM)((char*)pHWACCM - pHWACCM->offVM) )
57
58/** Maximum number of exit reason statistics counters. */
59#define MAX_EXITREASON_STAT 0x100
60#define MASK_EXITREASON_STAT 0xff
61
62/** @name Changed flags
63 * These flags are used to keep track of which important registers that
64 * have been changed since last they were reset.
65 * @{
66 */
67#define HWACCM_CHANGED_GUEST_FPU RT_BIT(0)
68#define HWACCM_CHANGED_GUEST_CR0 RT_BIT(1)
69#define HWACCM_CHANGED_GUEST_CR3 RT_BIT(2)
70#define HWACCM_CHANGED_GUEST_CR4 RT_BIT(3)
71#define HWACCM_CHANGED_GUEST_GDTR RT_BIT(4)
72#define HWACCM_CHANGED_GUEST_IDTR RT_BIT(5)
73#define HWACCM_CHANGED_GUEST_LDTR RT_BIT(6)
74#define HWACCM_CHANGED_GUEST_TR RT_BIT(7)
75#define HWACCM_CHANGED_GUEST_SYSENTER_MSR RT_BIT(8)
76#define HWACCM_CHANGED_GUEST_SEGMENT_REGS RT_BIT(9)
77#define HWACCM_CHANGED_GUEST_DEBUG RT_BIT(10)
78#define HWACCM_CHANGED_HOST_CONTEXT RT_BIT(11)
79
80#define HWACCM_CHANGED_ALL ( HWACCM_CHANGED_GUEST_SEGMENT_REGS \
81 | HWACCM_CHANGED_GUEST_CR0 \
82 | HWACCM_CHANGED_GUEST_CR3 \
83 | HWACCM_CHANGED_GUEST_CR4 \
84 | HWACCM_CHANGED_GUEST_GDTR \
85 | HWACCM_CHANGED_GUEST_IDTR \
86 | HWACCM_CHANGED_GUEST_LDTR \
87 | HWACCM_CHANGED_GUEST_TR \
88 | HWACCM_CHANGED_GUEST_SYSENTER_MSR \
89 | HWACCM_CHANGED_GUEST_FPU \
90 | HWACCM_CHANGED_GUEST_DEBUG \
91 | HWACCM_CHANGED_HOST_CONTEXT)
92
93#define HWACCM_CHANGED_ALL_GUEST ( HWACCM_CHANGED_GUEST_SEGMENT_REGS \
94 | HWACCM_CHANGED_GUEST_CR0 \
95 | HWACCM_CHANGED_GUEST_CR3 \
96 | HWACCM_CHANGED_GUEST_CR4 \
97 | HWACCM_CHANGED_GUEST_GDTR \
98 | HWACCM_CHANGED_GUEST_IDTR \
99 | HWACCM_CHANGED_GUEST_LDTR \
100 | HWACCM_CHANGED_GUEST_TR \
101 | HWACCM_CHANGED_GUEST_SYSENTER_MSR \
102 | HWACCM_CHANGED_GUEST_DEBUG \
103 | HWACCM_CHANGED_GUEST_FPU)
104
105/** @} */
106
107/** @name Intercepted traps
108 * Traps that need to be intercepted so we can correctly dispatch them to the guest if required.
109 * Currently #NM and #PF only
110 */
111#ifdef VBOX_STRICT
112#define HWACCM_VMX_TRAP_MASK RT_BIT(X86_XCPT_DE) | RT_BIT(X86_XCPT_NM) | RT_BIT(X86_XCPT_PF) | RT_BIT(X86_XCPT_UD) | RT_BIT(X86_XCPT_NP) | RT_BIT(X86_XCPT_SS) | RT_BIT(X86_XCPT_GP) | RT_BIT(X86_XCPT_MF)
113#define HWACCM_SVM_TRAP_MASK HWACCM_VMX_TRAP_MASK
114#else
115#define HWACCM_VMX_TRAP_MASK RT_BIT(X86_XCPT_NM) | RT_BIT(X86_XCPT_PF)
116#define HWACCM_SVM_TRAP_MASK HWACCM_VMX_TRAP_MASK
117#endif
118/** @} */
119
120
121/** Maxium resume loops allowed in ring 0 (safety precaution) */
122#define HWACCM_MAX_RESUME_LOOPS 1024
123
124/** HWACCM SSM version
125 */
126#define HWACCM_SSM_VERSION 3
127
128/* Per-cpu information. */
129typedef struct
130{
131 RTCPUID idCpu;
132
133 RTR0MEMOBJ pMemObj;
134 /* Current ASID (AMD-V only) */
135 uint32_t uCurrentASID;
136 /* TLB flush count */
137 uint32_t cTLBFlushes;
138
139 /* Set the first time a cpu is used to make sure we start with a clean TLB. */
140 bool fFlushTLB;
141
142 bool fConfigured;
143} HWACCM_CPUINFO;
144typedef HWACCM_CPUINFO *PHWACCM_CPUINFO;
145
146/* VT-x capability qword. */
147typedef union
148{
149 struct
150 {
151 uint32_t disallowed0;
152 uint32_t allowed1;
153 } n;
154 uint64_t u;
155} VMX_CAPABILITY;
156
157/**
158 * HWACCM VM Instance data.
159 * Changes to this must checked against the padding of the cfgm union in VM!
160 */
161typedef struct HWACCM
162{
163 /** Offset to the VM structure.
164 * See HWACCM2VM(). */
165 RTUINT offVM;
166
167 /** Set when we've initialized VMX or SVM. */
168 bool fInitialized;
169 /** Set when we're using VMX/SVN at that moment. */
170 bool fActive;
171
172 /** Set when hardware acceleration is allowed. */
173 bool fAllowed;
174
175 /** Set if nested paging is enabled. */
176 bool fNestedPaging;
177
178 /** Set if nested paging is allowed. */
179 bool fAllowNestedPaging;
180
181 /** HWACCM_CHANGED_* flags. */
182 uint32_t fContextUseFlags;
183
184 /** Old style FPU reporting trap mask override performed (optimization) */
185 uint32_t fFPUOldStyleOverride;
186
187 /** And mask for copying register contents. */
188 uint64_t u64RegisterMask;
189 struct
190 {
191 /** Set by the ring-0 driver to indicate VMX is supported by the CPU. */
192 bool fSupported;
193
194 /** Set when we've enabled VMX. */
195 bool fEnabled;
196
197 /** Set if we can use VMXResume to execute guest code. */
198 bool fResumeVM;
199
200 /** R0 memory object for the VM control structure (VMCS). */
201 RTR0MEMOBJ pMemObjVMCS;
202 /** Physical address of the VM control structure (VMCS). */
203 RTHCPHYS pVMCSPhys;
204 /** Virtual address of the VM control structure (VMCS). */
205 R0PTRTYPE(void *) pVMCS;
206
207 /** R0 memory object for the TSS page used for real mode emulation. */
208 RTR0MEMOBJ pMemObjRealModeTSS;
209 /** Physical address of the TSS page used for real mode emulation. */
210 RTHCPHYS pRealModeTSSPhys;
211 /** Virtual address of the TSS page used for real mode emulation. */
212 R0PTRTYPE(PVBOXTSS) pRealModeTSS;
213
214 /** R0 memory object for the virtual APIC mmio cache. */
215 RTR0MEMOBJ pMemObjAPIC;
216 /** Physical address of the virtual APIC mmio cache. */
217 RTHCPHYS pAPICPhys;
218 /** Virtual address of the virtual APIC mmio cache. */
219 R0PTRTYPE(uint8_t *) pAPIC;
220
221 /** R0 memory object for the MSR bitmap (1 page). */
222 RTR0MEMOBJ pMemObjMSRBitmap;
223 /** Physical address of the MSR bitmap (1 page). */
224 RTHCPHYS pMSRBitmapPhys;
225 /** Virtual address of the MSR bitmap (1 page). */
226 R0PTRTYPE(uint8_t *) pMSRBitmap;
227
228 /** R0 memory object for the MSR entry load page (guest MSRs). */
229 RTR0MEMOBJ pMemObjMSREntryLoad;
230 /** Physical address of the MSR entry load page (guest MSRs). */
231 RTHCPHYS pMSREntryLoadPhys;
232 /** Virtual address of the MSR entry load page (guest MSRs). */
233 R0PTRTYPE(uint8_t *) pMSREntryLoad;
234
235 /** R0 memory object for the MSR exit store page (guest MSRs). */
236 RTR0MEMOBJ pMemObjMSRExitStore;
237 /** Physical address of the MSR exit store page (guest MSRs). */
238 RTHCPHYS pMSRExitStorePhys;
239 /** Virtual address of the MSR exit store page (guest MSRs). */
240 R0PTRTYPE(uint8_t *) pMSRExitStore;
241
242 /** R0 memory object for the MSR exit load page (host MSRs). */
243 RTR0MEMOBJ pMemObjMSRExitLoad;
244 /** Physical address of the MSR exit load page (host MSRs). */
245 RTHCPHYS pMSRExitLoadPhys;
246 /** Virtual address of the MSR exit load page (host MSRs). */
247 R0PTRTYPE(uint8_t *) pMSRExitLoad;
248
249 /** Ring 0 handlers for VT-x. */
250 DECLR0CALLBACKMEMBER(int, pfnStartVM,(RTHCUINT fResume, PCPUMCTX pCtx));
251
252 /** Host CR4 value (set by ring-0 VMX init) */
253 uint64_t hostCR4;
254
255 /** Current VMX_VMCS_CTRL_PROC_EXEC_CONTROLS. */
256 uint64_t proc_ctls;
257
258 /** Current CR0 mask. */
259 uint64_t cr0_mask;
260 /** Current CR4 mask. */
261 uint64_t cr4_mask;
262
263 /** VMX MSR values */
264 struct
265 {
266 uint64_t feature_ctrl;
267 uint64_t vmx_basic_info;
268 VMX_CAPABILITY vmx_pin_ctls;
269 VMX_CAPABILITY vmx_proc_ctls;
270 VMX_CAPABILITY vmx_proc_ctls2;
271 VMX_CAPABILITY vmx_exit;
272 VMX_CAPABILITY vmx_entry;
273 uint64_t vmx_misc;
274 uint64_t vmx_cr0_fixed0;
275 uint64_t vmx_cr0_fixed1;
276 uint64_t vmx_cr4_fixed0;
277 uint64_t vmx_cr4_fixed1;
278 uint64_t vmx_vmcs_enum;
279 uint64_t vmx_eptcaps;
280 } msr;
281
282 /* Last instruction error */
283 uint32_t ulLastInstrError;
284 } vmx;
285
286 struct
287 {
288 /** Set by the ring-0 driver to indicate SVM is supported by the CPU. */
289 bool fSupported;
290 /** Set when we've enabled SVM. */
291 bool fEnabled;
292 /** Set if we don't have to flush the TLB on VM entry. */
293 bool fResumeVM;
294 /** Set if erratum 170 affects the AMD cpu. */
295 bool fAlwaysFlushTLB;
296 /** Set if we need to flush the TLB during the world switch. */
297 bool fForceTLBFlush;
298
299 /* Id of the last cpu we were executing code on (NIL_RTCPUID for the first time) */
300 RTCPUID idLastCpu;
301
302 /* TLB flush count */
303 uint32_t cTLBFlushes;
304
305 /* Current ASID in use by the VM */
306 uint32_t uCurrentASID;
307
308 /** R0 memory object for the VM control block (VMCB). */
309 RTR0MEMOBJ pMemObjVMCB;
310 /** Physical address of the VM control block (VMCB). */
311 RTHCPHYS pVMCBPhys;
312 /** Virtual address of the VM control block (VMCB). */
313 R0PTRTYPE(void *) pVMCB;
314
315 /** R0 memory object for the host VM control block (VMCB). */
316 RTR0MEMOBJ pMemObjVMCBHost;
317 /** Physical address of the host VM control block (VMCB). */
318 RTHCPHYS pVMCBHostPhys;
319 /** Virtual address of the host VM control block (VMCB). */
320 R0PTRTYPE(void *) pVMCBHost;
321
322 /** R0 memory object for the IO bitmap (12kb). */
323 RTR0MEMOBJ pMemObjIOBitmap;
324 /** Physical address of the IO bitmap (12kb). */
325 RTHCPHYS pIOBitmapPhys;
326 /** Virtual address of the IO bitmap. */
327 R0PTRTYPE(void *) pIOBitmap;
328
329 /** R0 memory object for the MSR bitmap (8kb). */
330 RTR0MEMOBJ pMemObjMSRBitmap;
331 /** Physical address of the MSR bitmap (8kb). */
332 RTHCPHYS pMSRBitmapPhys;
333 /** Virtual address of the MSR bitmap. */
334 R0PTRTYPE(void *) pMSRBitmap;
335
336 /** Ring 0 handlers for VT-x. */
337 DECLR0CALLBACKMEMBER(int, pfnVMRun,(RTHCPHYS pVMCBHostPhys, RTHCPHYS pVMCBPhys, PCPUMCTX pCtx));
338
339 /** SVM revision. */
340 uint32_t u32Rev;
341
342 /** Maximum ASID allowed. */
343 uint32_t u32MaxASID;
344
345 /** SVM feature bits from cpuid 0x8000000a */
346 uint32_t u32Features;
347 } svm;
348
349 struct
350 {
351 uint32_t u32AMDFeatureECX;
352 uint32_t u32AMDFeatureEDX;
353 } cpuid;
354
355 /* Event injection state. */
356 struct
357 {
358 uint32_t fPending;
359 uint32_t errCode;
360 uint64_t intInfo;
361 } Event;
362
363 /** Saved error from detection */
364 int32_t lLastError;
365
366 /** HWACCMR0Init was run */
367 bool fHWACCMR0Init;
368
369 /** Currenty shadow paging mode. */
370 PGMMODE enmShadowMode;
371
372 STAMPROFILEADV StatEntry;
373 STAMPROFILEADV StatExit;
374 STAMPROFILEADV StatInGC;
375
376 STAMCOUNTER StatIntInject;
377
378 STAMCOUNTER StatExitShadowNM;
379 STAMCOUNTER StatExitGuestNM;
380 STAMCOUNTER StatExitShadowPF;
381 STAMCOUNTER StatExitGuestPF;
382 STAMCOUNTER StatExitGuestUD;
383 STAMCOUNTER StatExitGuestSS;
384 STAMCOUNTER StatExitGuestNP;
385 STAMCOUNTER StatExitGuestGP;
386 STAMCOUNTER StatExitGuestDE;
387 STAMCOUNTER StatExitGuestMF;
388 STAMCOUNTER StatExitInvpg;
389 STAMCOUNTER StatExitInvd;
390 STAMCOUNTER StatExitCpuid;
391 STAMCOUNTER StatExitRdtsc;
392 STAMCOUNTER StatExitCRxWrite;
393 STAMCOUNTER StatExitCRxRead;
394 STAMCOUNTER StatExitDRxWrite;
395 STAMCOUNTER StatExitDRxRead;
396 STAMCOUNTER StatExitCLTS;
397 STAMCOUNTER StatExitLMSW;
398 STAMCOUNTER StatExitIOWrite;
399 STAMCOUNTER StatExitIORead;
400 STAMCOUNTER StatExitIOStringWrite;
401 STAMCOUNTER StatExitIOStringRead;
402 STAMCOUNTER StatExitIrqWindow;
403 STAMCOUNTER StatExitMaxResume;
404 STAMCOUNTER StatIntReinject;
405 STAMCOUNTER StatPendingHostIrq;
406
407 STAMCOUNTER StatFlushPageManual;
408 STAMCOUNTER StatFlushPhysPageManual;
409 STAMCOUNTER StatFlushTLBManual;
410 STAMCOUNTER StatFlushPageInvlpg;
411 STAMCOUNTER StatFlushTLBWorldSwitch;
412 STAMCOUNTER StatNoFlushTLBWorldSwitch;
413 STAMCOUNTER StatFlushTLBCRxChange;
414 STAMCOUNTER StatFlushASID;
415
416 STAMCOUNTER StatSwitchGuestIrq;
417 STAMCOUNTER StatSwitchToR3;
418
419 STAMCOUNTER StatTSCOffset;
420 STAMCOUNTER StatTSCIntercept;
421
422 STAMCOUNTER StatExitReasonNPF;
423 R3PTRTYPE(PSTAMCOUNTER) pStatExitReason;
424 R0PTRTYPE(PSTAMCOUNTER) pStatExitReasonR0;
425} HWACCM;
426/** Pointer to HWACCM VM instance data. */
427typedef HWACCM *PHWACCM;
428
429#ifdef IN_RING0
430
431/**
432 * Returns the cpu structure for the current cpu.
433 * Keep in mind that there is no guarantee it will stay the same (long jumps to ring 3!!!).
434 *
435 * @returns cpu structure pointer
436 * @param pVM The VM to operate on.
437 */
438HWACCMR0DECL(PHWACCM_CPUINFO) HWACCMR0GetCurrentCpu();
439
440#ifdef VBOX_STRICT
441HWACCMR0DECL(void) HWACCMDumpRegs(PVM pVM, PCPUMCTX pCtx);
442HWACCMR0DECL(void) HWACCMR0DumpDescriptor(PX86DESCHC Desc, RTSEL Sel, const char *pszMsg);
443#else
444#define HWACCMDumpRegs(a, b) do { } while (0)
445#define HWACCMR0DumpDescriptor(a, b, c) do { } while (0)
446#endif
447
448/* Dummy callback handlers. */
449HWACCMR0DECL(int) HWACCMR0DummyEnter(PVM pVM, PHWACCM_CPUINFO pCpu);
450HWACCMR0DECL(int) HWACCMR0DummyLeave(PVM pVM);
451HWACCMR0DECL(int) HWACCMR0DummyEnableCpu(PHWACCM_CPUINFO pCpu, PVM pVM, void *pvPageCpu, RTHCPHYS pPageCpuPhys);
452HWACCMR0DECL(int) HWACCMR0DummyDisableCpu(PHWACCM_CPUINFO pCpu, void *pvPageCpu, RTHCPHYS pPageCpuPhys);
453HWACCMR0DECL(int) HWACCMR0DummyInitVM(PVM pVM);
454HWACCMR0DECL(int) HWACCMR0DummyTermVM(PVM pVM);
455HWACCMR0DECL(int) HWACCMR0DummySetupVM(PVM pVM);
456HWACCMR0DECL(int) HWACCMR0DummyRunGuestCode(PVM pVM, CPUMCTX *pCtx);
457HWACCMR0DECL(int) HWACCMR0DummySaveHostState(PVM pVM);
458HWACCMR0DECL(int) HWACCMR0DummyLoadGuestState(PVM pVM, CPUMCTX *pCtx);
459
460#endif
461
462/** @} */
463
464__END_DECLS
465
466#endif
467
Note: See TracBrowser for help on using the repository browser.

© 2024 Oracle Support Privacy / Do Not Sell My Info Terms of Use Trademark Policy Automated Access Etiquette