HWACCMInternal.h@ 12746

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1	/* $Id: HWACCMInternal.h 12746 2008-09-25 15:18:01Z vboxsync $ */
2	/** @file
3	* HWACCM - Internal header file.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22	#ifndef ___HWACCMInternal_h
23	#define ___HWACCMInternal_h
24
25	#include <VBox/cdefs.h>
26	#include <VBox/types.h>
27	#include <VBox/em.h>
28	#include <VBox/stam.h>
29	#include <VBox/dis.h>
30	#include <VBox/hwaccm.h>
31	#include <VBox/pgm.h>
32	#include <iprt/memobj.h>
33	#include <iprt/cpuset.h>
34	#include <iprt/mp.h>
35
36	#if HC_ARCH_BITS == 64
37	/* Enable 64 bits guest support. */
38	# define VBOX_ENABLE_64_BITS_GUESTS
39	#endif
40
41	__BEGIN_DECLS
42
43
44	/** @defgroup grp_hwaccm_int Internal
45	* @ingroup grp_hwaccm
46	* @internal
47	* @{
48	*/
49
50
51	/**
52	* Converts a HWACCM pointer into a VM pointer.
53	* @returns Pointer to the VM structure the EM is part of.
54	* @param pHWACCM Pointer to HWACCM instance data.
55	*/
56	#define HWACCM2VM(pHWACCM) ( (PVM)((char*)pHWACCM - pHWACCM->offVM) )
57
58	/** Maximum number of exit reason statistics counters. */
59	#define MAX_EXITREASON_STAT 0x100
60	#define MASK_EXITREASON_STAT 0xff
61
62	/** @name Changed flags
63	* These flags are used to keep track of which important registers that
64	* have been changed since last they were reset.
65	* @{
66	*/
67	#define HWACCM_CHANGED_GUEST_FPU RT_BIT(0)
68	#define HWACCM_CHANGED_GUEST_CR0 RT_BIT(1)
69	#define HWACCM_CHANGED_GUEST_CR3 RT_BIT(2)
70	#define HWACCM_CHANGED_GUEST_CR4 RT_BIT(3)
71	#define HWACCM_CHANGED_GUEST_GDTR RT_BIT(4)
72	#define HWACCM_CHANGED_GUEST_IDTR RT_BIT(5)
73	#define HWACCM_CHANGED_GUEST_LDTR RT_BIT(6)
74	#define HWACCM_CHANGED_GUEST_TR RT_BIT(7)
75	#define HWACCM_CHANGED_GUEST_SYSENTER_MSR RT_BIT(8)
76	#define HWACCM_CHANGED_GUEST_SEGMENT_REGS RT_BIT(9)
77	#define HWACCM_CHANGED_GUEST_DEBUG RT_BIT(10)
78	#define HWACCM_CHANGED_HOST_CONTEXT RT_BIT(11)
79
80	#define HWACCM_CHANGED_ALL ( HWACCM_CHANGED_GUEST_SEGMENT_REGS \
81	\| HWACCM_CHANGED_GUEST_CR0 \
82	\| HWACCM_CHANGED_GUEST_CR3 \
83	\| HWACCM_CHANGED_GUEST_CR4 \
84	\| HWACCM_CHANGED_GUEST_GDTR \
85	\| HWACCM_CHANGED_GUEST_IDTR \
86	\| HWACCM_CHANGED_GUEST_LDTR \
87	\| HWACCM_CHANGED_GUEST_TR \
88	\| HWACCM_CHANGED_GUEST_SYSENTER_MSR \
89	\| HWACCM_CHANGED_GUEST_FPU \
90	\| HWACCM_CHANGED_GUEST_DEBUG \
91	\| HWACCM_CHANGED_HOST_CONTEXT)
92
93	#define HWACCM_CHANGED_ALL_GUEST ( HWACCM_CHANGED_GUEST_SEGMENT_REGS \
94	\| HWACCM_CHANGED_GUEST_CR0 \
95	\| HWACCM_CHANGED_GUEST_CR3 \
96	\| HWACCM_CHANGED_GUEST_CR4 \
97	\| HWACCM_CHANGED_GUEST_GDTR \
98	\| HWACCM_CHANGED_GUEST_IDTR \
99	\| HWACCM_CHANGED_GUEST_LDTR \
100	\| HWACCM_CHANGED_GUEST_TR \
101	\| HWACCM_CHANGED_GUEST_SYSENTER_MSR \
102	\| HWACCM_CHANGED_GUEST_DEBUG \
103	\| HWACCM_CHANGED_GUEST_FPU)
104
105	/** @} */
106
107	/** @name Intercepted traps
108	* Traps that need to be intercepted so we can correctly dispatch them to the guest if required.
109	* Currently #NM and #PF only
110	*/
111	#ifdef VBOX_STRICT
112	#define HWACCM_VMX_TRAP_MASK RT_BIT(X86_XCPT_DE) \| RT_BIT(X86_XCPT_NM) \| RT_BIT(X86_XCPT_PF) \| RT_BIT(X86_XCPT_UD) \| RT_BIT(X86_XCPT_NP) \| RT_BIT(X86_XCPT_SS) \| RT_BIT(X86_XCPT_GP) \| RT_BIT(X86_XCPT_MF)
113	#define HWACCM_SVM_TRAP_MASK HWACCM_VMX_TRAP_MASK
114	#else
115	#define HWACCM_VMX_TRAP_MASK RT_BIT(X86_XCPT_NM) \| RT_BIT(X86_XCPT_PF)
116	#define HWACCM_SVM_TRAP_MASK RT_BIT(X86_XCPT_NM) \| RT_BIT(X86_XCPT_PF)
117	#endif
118	/** @} */
119
120
121	/** Maxium resume loops allowed in ring 0 (safety precaution) */
122	#define HWACCM_MAX_RESUME_LOOPS 1024
123
124	/** Size of the TSS structure + 2 pages for the IO bitmap + end byte. */
125	#define HWACCM_VTX_TSS_SIZE (sizeof(VBOXTSS) + 2*PAGE_SIZE + 1)
126
127	/** HWACCM SSM version
128	*/
129	#define HWACCM_SSM_VERSION 3
130
131	/* Per-cpu information. */
132	typedef struct
133	{
134	RTCPUID idCpu;
135
136	RTR0MEMOBJ pMemObj;
137	/* Current ASID (AMD-V only) */
138	uint32_t uCurrentASID;
139	/* TLB flush count */
140	uint32_t cTLBFlushes;
141
142	/* Set the first time a cpu is used to make sure we start with a clean TLB. */
143	bool fFlushTLB;
144
145	bool fConfigured;
146	} HWACCM_CPUINFO;
147	typedef HWACCM_CPUINFO *PHWACCM_CPUINFO;
148
149	/* VT-x capability qword. */
150	typedef union
151	{
152	struct
153	{
154	uint32_t disallowed0;
155	uint32_t allowed1;
156	} n;
157	uint64_t u;
158	} VMX_CAPABILITY;
159
160	/**
161	* HWACCM VM Instance data.
162	* Changes to this must checked against the padding of the cfgm union in VM!
163	*/
164	typedef struct HWACCM
165	{
166	/** Offset to the VM structure.
167	* See HWACCM2VM(). */
168	RTUINT offVM;
169
170	/** Set when we've initialized VMX or SVM. */
171	bool fInitialized;
172	/** Set when we're using VMX/SVN at that moment. */
173	bool fActive;
174
175	/** Set when hardware acceleration is allowed. */
176	bool fAllowed;
177
178	/** Set if nested paging is enabled. */
179	bool fNestedPaging;
180
181	/** Set if nested paging is allowed. */
182	bool fAllowNestedPaging;
183
184	/** Explicit alignment padding to make 32-bit gcc align u64RegisterMask
185	* naturally. */
186	bool padding[3+4];
187
188	/** HWACCM_CHANGED_* flags. */
189	uint32_t fContextUseFlags;
190
191	/** Old style FPU reporting trap mask override performed (optimization) */
192	uint32_t fFPUOldStyleOverride;
193
194	/** And mask for copying register contents. */
195	uint64_t u64RegisterMask;
196	struct
197	{
198	/** Set by the ring-0 driver to indicate VMX is supported by the CPU. */
199	bool fSupported;
200
201	/** Set when we've enabled VMX. */
202	bool fEnabled;
203
204	/** Set if we can use VMXResume to execute guest code. */
205	bool fResumeVM;
206
207	/** R0 memory object for the VM control structure (VMCS). */
208	RTR0MEMOBJ pMemObjVMCS;
209	/** Physical address of the VM control structure (VMCS). */
210	RTHCPHYS pVMCSPhys;
211	/** Virtual address of the VM control structure (VMCS). */
212	R0PTRTYPE(void *) pVMCS;
213
214	/** Virtual address of the TSS page used for real mode emulation. */
215	R3PTRTYPE(PVBOXTSS) pRealModeTSS;
216	#if HC_ARCH_BITS == 32
217	uint32_t padding2; /*< explicit alignment for 32-bit gcc /
218	#endif
219
220	/** R0 memory object for the virtual APIC mmio cache. */
221	RTR0MEMOBJ pMemObjAPIC;
222	/** Physical address of the virtual APIC mmio cache. */
223	RTHCPHYS pAPICPhys;
224	/** Virtual address of the virtual APIC mmio cache. */
225	R0PTRTYPE(uint8_t *) pAPIC;
226
227	/** R0 memory object for the MSR bitmap (1 page). */
228	RTR0MEMOBJ pMemObjMSRBitmap;
229	/** Physical address of the MSR bitmap (1 page). */
230	RTHCPHYS pMSRBitmapPhys;
231	/** Virtual address of the MSR bitmap (1 page). */
232	R0PTRTYPE(uint8_t *) pMSRBitmap;
233
234	/** R0 memory object for the MSR entry load page (guest MSRs). */
235	RTR0MEMOBJ pMemObjMSREntryLoad;
236	/** Physical address of the MSR entry load page (guest MSRs). */
237	RTHCPHYS pMSREntryLoadPhys;
238	/** Virtual address of the MSR entry load page (guest MSRs). */
239	R0PTRTYPE(uint8_t *) pMSREntryLoad;
240
241	/** R0 memory object for the MSR exit store page (guest MSRs). */
242	RTR0MEMOBJ pMemObjMSRExitStore;
243	/** Physical address of the MSR exit store page (guest MSRs). */
244	RTHCPHYS pMSRExitStorePhys;
245	/** Virtual address of the MSR exit store page (guest MSRs). */
246	R0PTRTYPE(uint8_t *) pMSRExitStore;
247
248	/** R0 memory object for the MSR exit load page (host MSRs). */
249	RTR0MEMOBJ pMemObjMSRExitLoad;
250	/** Physical address of the MSR exit load page (host MSRs). */
251	RTHCPHYS pMSRExitLoadPhys;
252	/** Virtual address of the MSR exit load page (host MSRs). */
253	R0PTRTYPE(uint8_t *) pMSRExitLoad;
254
255	/** Ring 0 handlers for VT-x. */
256	DECLR0CALLBACKMEMBER(int, pfnStartVM,(RTHCUINT fResume, PCPUMCTX pCtx));
257
258	/** Host CR4 value (set by ring-0 VMX init) */
259	uint64_t hostCR4;
260
261	/** Current VMX_VMCS_CTRL_PROC_EXEC_CONTROLS. */
262	uint64_t proc_ctls;
263
264	/** Current CR0 mask. */
265	uint64_t cr0_mask;
266	/** Current CR4 mask. */
267	uint64_t cr4_mask;
268
269	/** VMX MSR values */
270	struct
271	{
272	uint64_t feature_ctrl;
273	uint64_t vmx_basic_info;
274	VMX_CAPABILITY vmx_pin_ctls;
275	VMX_CAPABILITY vmx_proc_ctls;
276	VMX_CAPABILITY vmx_proc_ctls2;
277	VMX_CAPABILITY vmx_exit;
278	VMX_CAPABILITY vmx_entry;
279	uint64_t vmx_misc;
280	uint64_t vmx_cr0_fixed0;
281	uint64_t vmx_cr0_fixed1;
282	uint64_t vmx_cr4_fixed0;
283	uint64_t vmx_cr4_fixed1;
284	uint64_t vmx_vmcs_enum;
285	uint64_t vmx_eptcaps;
286	} msr;
287
288	/* Last instruction error */
289	uint32_t ulLastInstrError;
290
291	/** Current trap mask. */
292	uint32_t u32TrapMask;
293
294	struct
295	{
296	uint64_t u64VMCSPhys;
297	uint32_t ulVMCSRevision;
298	} lasterror;
299	} vmx;
300
301	struct
302	{
303	/** Set by the ring-0 driver to indicate SVM is supported by the CPU. */
304	bool fSupported;
305	/** Set when we've enabled SVM. */
306	bool fEnabled;
307	/** Set if we don't have to flush the TLB on VM entry. */
308	bool fResumeVM;
309	/** Set if erratum 170 affects the AMD cpu. */
310	bool fAlwaysFlushTLB;
311	/** Set if we need to flush the TLB during the world switch. */
312	bool fForceTLBFlush;
313
314	/* Id of the last cpu we were executing code on (NIL_RTCPUID for the first time) */
315	RTCPUID idLastCpu;
316
317	/* TLB flush count */
318	uint32_t cTLBFlushes;
319
320	/* Current ASID in use by the VM */
321	uint32_t uCurrentASID;
322
323	/** R0 memory object for the VM control block (VMCB). */
324	RTR0MEMOBJ pMemObjVMCB;
325	/** Physical address of the VM control block (VMCB). */
326	RTHCPHYS pVMCBPhys;
327	/** Virtual address of the VM control block (VMCB). */
328	R0PTRTYPE(void *) pVMCB;
329
330	/** R0 memory object for the host VM control block (VMCB). */
331	RTR0MEMOBJ pMemObjVMCBHost;
332	/** Physical address of the host VM control block (VMCB). */
333	RTHCPHYS pVMCBHostPhys;
334	/** Virtual address of the host VM control block (VMCB). */
335	R0PTRTYPE(void *) pVMCBHost;
336
337	/** R0 memory object for the IO bitmap (12kb). */
338	RTR0MEMOBJ pMemObjIOBitmap;
339	/** Physical address of the IO bitmap (12kb). */
340	RTHCPHYS pIOBitmapPhys;
341	/** Virtual address of the IO bitmap. */
342	R0PTRTYPE(void *) pIOBitmap;
343
344	/** R0 memory object for the MSR bitmap (8kb). */
345	RTR0MEMOBJ pMemObjMSRBitmap;
346	/** Physical address of the MSR bitmap (8kb). */
347	RTHCPHYS pMSRBitmapPhys;
348	/** Virtual address of the MSR bitmap. */
349	R0PTRTYPE(void *) pMSRBitmap;
350
351	/** Ring 0 handlers for VT-x. */
352	DECLR0CALLBACKMEMBER(int, pfnVMRun,(RTHCPHYS pVMCBHostPhys, RTHCPHYS pVMCBPhys, PCPUMCTX pCtx));
353
354	/** SVM revision. */
355	uint32_t u32Rev;
356
357	/** Maximum ASID allowed. */
358	uint32_t u32MaxASID;
359
360	/** SVM feature bits from cpuid 0x8000000a */
361	uint32_t u32Features;
362	} svm;
363
364	struct
365	{
366	uint32_t u32AMDFeatureECX;
367	uint32_t u32AMDFeatureEDX;
368	} cpuid;
369
370	/** Event injection state. */
371	struct
372	{
373	uint32_t fPending;
374	uint32_t errCode;
375	uint64_t intInfo;
376	} Event;
377
378	/** Saved error from detection */
379	int32_t lLastError;
380
381	/** HWACCMR0Init was run */
382	bool fHWACCMR0Init;
383
384	/** Currenty shadow paging mode. */
385	PGMMODE enmShadowMode;
386
387	/** Explicit alignment padding of StatEntry (32-bit g++ again). */
388	int32_t padding2;
389
390	#ifdef VBOX_STRICT
391	/** The CPU ID of the CPU currently owning the VMCS. Set in
392	* HWACCMR0Enter and cleared in HWACCMR0Leave. */
393	RTCPUID idEnteredCpu;
394	# if HC_ARCH_BITS == 32
395	RTCPUID Alignment0;
396	# endif
397	#endif
398
399	STAMPROFILEADV StatEntry;
400	STAMPROFILEADV StatExit;
401	STAMPROFILEADV StatInGC;
402
403	STAMCOUNTER StatIntInject;
404
405	STAMCOUNTER StatExitShadowNM;
406	STAMCOUNTER StatExitGuestNM;
407	STAMCOUNTER StatExitShadowPF;
408	STAMCOUNTER StatExitGuestPF;
409	STAMCOUNTER StatExitGuestUD;
410	STAMCOUNTER StatExitGuestSS;
411	STAMCOUNTER StatExitGuestNP;
412	STAMCOUNTER StatExitGuestGP;
413	STAMCOUNTER StatExitGuestDE;
414	STAMCOUNTER StatExitGuestDB;
415	STAMCOUNTER StatExitGuestMF;
416	STAMCOUNTER StatExitInvpg;
417	STAMCOUNTER StatExitInvd;
418	STAMCOUNTER StatExitCpuid;
419	STAMCOUNTER StatExitRdtsc;
420	STAMCOUNTER StatExitCRxWrite;
421	STAMCOUNTER StatExitCRxRead;
422	STAMCOUNTER StatExitDRxWrite;
423	STAMCOUNTER StatExitDRxRead;
424	STAMCOUNTER StatExitCLTS;
425	STAMCOUNTER StatExitLMSW;
426	STAMCOUNTER StatExitIOWrite;
427	STAMCOUNTER StatExitIORead;
428	STAMCOUNTER StatExitIOStringWrite;
429	STAMCOUNTER StatExitIOStringRead;
430	STAMCOUNTER StatExitIrqWindow;
431	STAMCOUNTER StatExitMaxResume;
432	STAMCOUNTER StatIntReinject;
433	STAMCOUNTER StatPendingHostIrq;
434
435	STAMCOUNTER StatFlushPageManual;
436	STAMCOUNTER StatFlushPhysPageManual;
437	STAMCOUNTER StatFlushTLBManual;
438	STAMCOUNTER StatFlushPageInvlpg;
439	STAMCOUNTER StatFlushTLBWorldSwitch;
440	STAMCOUNTER StatNoFlushTLBWorldSwitch;
441	STAMCOUNTER StatFlushTLBCRxChange;
442	STAMCOUNTER StatFlushASID;
443
444	STAMCOUNTER StatSwitchGuestIrq;
445	STAMCOUNTER StatSwitchToR3;
446
447	STAMCOUNTER StatTSCOffset;
448	STAMCOUNTER StatTSCIntercept;
449
450	STAMCOUNTER StatExitReasonNPF;
451	STAMCOUNTER StatDRxArmed;
452	STAMCOUNTER StatDRxContextSwitch;
453	STAMCOUNTER StatDRxIOCheck;
454
455
456	R3PTRTYPE(PSTAMCOUNTER) paStatExitReason;
457	R0PTRTYPE(PSTAMCOUNTER) paStatExitReasonR0;
458	} HWACCM;
459	/** Pointer to HWACCM VM instance data. */
460	typedef HWACCM *PHWACCM;
461
462	#ifdef IN_RING0
463
464	HWACCMR0DECL(PHWACCM_CPUINFO) HWACCMR0GetCurrentCpu();
465
466	#ifdef VBOX_STRICT
467	HWACCMR0DECL(void) HWACCMDumpRegs(PVM pVM, PCPUMCTX pCtx);
468	HWACCMR0DECL(void) HWACCMR0DumpDescriptor(PX86DESCHC Desc, RTSEL Sel, const char *pszMsg);
469	#else
470	#define HWACCMDumpRegs(a, b) do { } while (0)
471	#define HWACCMR0DumpDescriptor(a, b, c) do { } while (0)
472	#endif
473
474	/* Dummy callback handlers. */
475	HWACCMR0DECL(int) HWACCMR0DummyEnter(PVM pVM, PHWACCM_CPUINFO pCpu);
476	HWACCMR0DECL(int) HWACCMR0DummyLeave(PVM pVM, CPUMCTX *pCtx);
477	HWACCMR0DECL(int) HWACCMR0DummyEnableCpu(PHWACCM_CPUINFO pCpu, PVM pVM, void *pvPageCpu, RTHCPHYS pPageCpuPhys);
478	HWACCMR0DECL(int) HWACCMR0DummyDisableCpu(PHWACCM_CPUINFO pCpu, void *pvPageCpu, RTHCPHYS pPageCpuPhys);
479	HWACCMR0DECL(int) HWACCMR0DummyInitVM(PVM pVM);
480	HWACCMR0DECL(int) HWACCMR0DummyTermVM(PVM pVM);
481	HWACCMR0DECL(int) HWACCMR0DummySetupVM(PVM pVM);
482	HWACCMR0DECL(int) HWACCMR0DummyRunGuestCode(PVM pVM, CPUMCTX *pCtx);
483	HWACCMR0DECL(int) HWACCMR0DummySaveHostState(PVM pVM);
484	HWACCMR0DECL(int) HWACCMR0DummyLoadGuestState(PVM pVM, CPUMCTX *pCtx);
485
486	#endif /* IN_RING0 */
487
488	/** @} */
489
490	__END_DECLS
491
492	#endif
493

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source: vbox/trunk/src/VBox/VMM/HWACCMInternal.h@ 12746

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