VirtualBox

source: vbox/trunk/src/VBox/VMM/HWACCMInternal.h@ 13115

Last change on this file since 13115 was 13115, checked in by vboxsync, 16 years ago

Corrections for the EPTP
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File size: 20.1 KB
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1/* $Id: HWACCMInternal.h 13115 2008-10-09 09:32:28Z vboxsync $ */
2/** @file
3 * HWACCM - Internal header file.
4 */
5
6/*
7 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 */
21
22#ifndef ___HWACCMInternal_h
23#define ___HWACCMInternal_h
24
25#include <VBox/cdefs.h>
26#include <VBox/types.h>
27#include <VBox/em.h>
28#include <VBox/stam.h>
29#include <VBox/dis.h>
30#include <VBox/hwaccm.h>
31#include <VBox/pgm.h>
32#include <VBox/cpum.h>
33#include <iprt/memobj.h>
34#include <iprt/cpuset.h>
35#include <iprt/mp.h>
36
37#if HC_ARCH_BITS == 64
38/* Enable 64 bits guest support. */
39# define VBOX_ENABLE_64_BITS_GUESTS
40#endif
41
42#define HWACCM_VMX_EMULATE_REALMODE
43
44__BEGIN_DECLS
45
46
47/** @defgroup grp_hwaccm_int Internal
48 * @ingroup grp_hwaccm
49 * @internal
50 * @{
51 */
52
53
54/**
55 * Converts a HWACCM pointer into a VM pointer.
56 * @returns Pointer to the VM structure the EM is part of.
57 * @param pHWACCM Pointer to HWACCM instance data.
58 */
59#define HWACCM2VM(pHWACCM) ( (PVM)((char*)pHWACCM - pHWACCM->offVM) )
60
61/** Maximum number of exit reason statistics counters. */
62#define MAX_EXITREASON_STAT 0x100
63#define MASK_EXITREASON_STAT 0xff
64
65/** @name Changed flags
66 * These flags are used to keep track of which important registers that
67 * have been changed since last they were reset.
68 * @{
69 */
70#define HWACCM_CHANGED_GUEST_FPU RT_BIT(0)
71#define HWACCM_CHANGED_GUEST_CR0 RT_BIT(1)
72#define HWACCM_CHANGED_GUEST_CR3 RT_BIT(2)
73#define HWACCM_CHANGED_GUEST_CR4 RT_BIT(3)
74#define HWACCM_CHANGED_GUEST_GDTR RT_BIT(4)
75#define HWACCM_CHANGED_GUEST_IDTR RT_BIT(5)
76#define HWACCM_CHANGED_GUEST_LDTR RT_BIT(6)
77#define HWACCM_CHANGED_GUEST_TR RT_BIT(7)
78#define HWACCM_CHANGED_GUEST_SYSENTER_MSR RT_BIT(8)
79#define HWACCM_CHANGED_GUEST_SEGMENT_REGS RT_BIT(9)
80#define HWACCM_CHANGED_GUEST_DEBUG RT_BIT(10)
81#define HWACCM_CHANGED_HOST_CONTEXT RT_BIT(11)
82
83#define HWACCM_CHANGED_ALL ( HWACCM_CHANGED_GUEST_SEGMENT_REGS \
84 | HWACCM_CHANGED_GUEST_CR0 \
85 | HWACCM_CHANGED_GUEST_CR3 \
86 | HWACCM_CHANGED_GUEST_CR4 \
87 | HWACCM_CHANGED_GUEST_GDTR \
88 | HWACCM_CHANGED_GUEST_IDTR \
89 | HWACCM_CHANGED_GUEST_LDTR \
90 | HWACCM_CHANGED_GUEST_TR \
91 | HWACCM_CHANGED_GUEST_SYSENTER_MSR \
92 | HWACCM_CHANGED_GUEST_FPU \
93 | HWACCM_CHANGED_GUEST_DEBUG \
94 | HWACCM_CHANGED_HOST_CONTEXT)
95
96#define HWACCM_CHANGED_ALL_GUEST ( HWACCM_CHANGED_GUEST_SEGMENT_REGS \
97 | HWACCM_CHANGED_GUEST_CR0 \
98 | HWACCM_CHANGED_GUEST_CR3 \
99 | HWACCM_CHANGED_GUEST_CR4 \
100 | HWACCM_CHANGED_GUEST_GDTR \
101 | HWACCM_CHANGED_GUEST_IDTR \
102 | HWACCM_CHANGED_GUEST_LDTR \
103 | HWACCM_CHANGED_GUEST_TR \
104 | HWACCM_CHANGED_GUEST_SYSENTER_MSR \
105 | HWACCM_CHANGED_GUEST_DEBUG \
106 | HWACCM_CHANGED_GUEST_FPU)
107
108/** @} */
109
110/** @name Intercepted traps
111 * Traps that need to be intercepted so we can correctly dispatch them to the guest if required.
112 * Currently #NM and #PF only
113 */
114#ifdef VBOX_STRICT
115#define HWACCM_VMX_TRAP_MASK RT_BIT(X86_XCPT_DE) | RT_BIT(X86_XCPT_NM) | RT_BIT(X86_XCPT_PF) | RT_BIT(X86_XCPT_UD) | RT_BIT(X86_XCPT_NP) | RT_BIT(X86_XCPT_SS) | RT_BIT(X86_XCPT_GP) | RT_BIT(X86_XCPT_MF)
116#define HWACCM_SVM_TRAP_MASK HWACCM_VMX_TRAP_MASK
117#else
118#define HWACCM_VMX_TRAP_MASK RT_BIT(X86_XCPT_NM) | RT_BIT(X86_XCPT_PF)
119#define HWACCM_SVM_TRAP_MASK RT_BIT(X86_XCPT_NM) | RT_BIT(X86_XCPT_PF)
120#endif
121/** @} */
122
123
124/** Maxium resume loops allowed in ring 0 (safety precaution) */
125#define HWACCM_MAX_RESUME_LOOPS 1024
126
127/** Size for the EPT identity page table (1024 4 MB pages to cover the entire address space). */
128#define HWACCM_EPT_IDENTITY_PG_TABLE_SIZE PAGE_SIZE
129/** Size of the TSS structure + 2 pages for the IO bitmap + end byte. */
130#define HWACCM_VTX_TSS_SIZE (sizeof(VBOXTSS) + 2*PAGE_SIZE + 1)
131/** Total guest mapped memory needed. */
132#define HWACCM_VTX_TOTAL_DEVHEAP_MEM (HWACCM_EPT_IDENTITY_PG_TABLE_SIZE + HWACCM_VTX_TSS_SIZE)
133
134/** HWACCM SSM version
135 */
136#define HWACCM_SSM_VERSION 3
137
138/* Per-cpu information. */
139typedef struct
140{
141 RTCPUID idCpu;
142
143 RTR0MEMOBJ pMemObj;
144 /* Current ASID (AMD-V)/VPID (Intel) */
145 uint32_t uCurrentASID;
146 /* TLB flush count */
147 uint32_t cTLBFlushes;
148
149 /* Set the first time a cpu is used to make sure we start with a clean TLB. */
150 bool fFlushTLB;
151
152 bool fConfigured;
153} HWACCM_CPUINFO;
154typedef HWACCM_CPUINFO *PHWACCM_CPUINFO;
155
156/* VT-x capability qword. */
157typedef union
158{
159 struct
160 {
161 uint32_t disallowed0;
162 uint32_t allowed1;
163 } n;
164 uint64_t u;
165} VMX_CAPABILITY;
166
167/**
168 * HWACCM VM Instance data.
169 * Changes to this must checked against the padding of the cfgm union in VM!
170 */
171typedef struct HWACCM
172{
173 /** Offset to the VM structure.
174 * See HWACCM2VM(). */
175 RTUINT offVM;
176
177 /** Set when we've initialized VMX or SVM. */
178 bool fInitialized;
179 /** Set when we're using VMX/SVN at that moment. */
180 bool fActive;
181
182 /** Set when hardware acceleration is allowed. */
183 bool fAllowed;
184
185 /** Set if nested paging is enabled. */
186 bool fNestedPaging;
187
188 /** Set if nested paging is allowed. */
189 bool fAllowNestedPaging;
190
191 /** Set if we need to flush the TLB during the world switch. */
192 bool fForceTLBFlush;
193
194 /** Old style FPU reporting trap mask override performed (optimization) */
195 bool fFPUOldStyleOverride;
196
197 /** Explicit alignment padding to make 32-bit gcc align u64RegisterMask
198 * naturally. */
199 bool padding[1];
200
201 /** HWACCM_CHANGED_* flags. */
202 RTUINT fContextUseFlags;
203
204 /* Id of the last cpu we were executing code on (NIL_RTCPUID for the first time) */
205 RTCPUID idLastCpu;
206
207 /* TLB flush count */
208 RTUINT cTLBFlushes;
209
210 /* Current ASID in use by the VM */
211 RTUINT uCurrentASID;
212
213 /** Maximum ASID allowed. */
214 RTUINT uMaxASID;
215
216 /** And mask for copying register contents. */
217 uint64_t u64RegisterMask;
218 struct
219 {
220 /** Set by the ring-0 driver to indicate VMX is supported by the CPU. */
221 bool fSupported;
222
223 /** Set when we've enabled VMX. */
224 bool fEnabled;
225
226 /** Set if we can use VMXResume to execute guest code. */
227 bool fResumeVM;
228
229 /** Set if VPID is supported. */
230 bool fVPID;
231
232 /** R0 memory object for the VM control structure (VMCS). */
233 RTR0MEMOBJ pMemObjVMCS;
234 /** Physical address of the VM control structure (VMCS). */
235 RTHCPHYS pVMCSPhys;
236 /** Virtual address of the VM control structure (VMCS). */
237 R0PTRTYPE(void *) pVMCS;
238
239 /** Virtual address of the TSS page used for real mode emulation. */
240 R3PTRTYPE(PVBOXTSS) pRealModeTSS;
241
242 /** Virtual address of the identity page table used for real mode emulation in EPT mode. */
243 R3PTRTYPE(PX86PD) pRealModeEPTPageTable;
244
245 /** R0 memory object for the virtual APIC mmio cache. */
246 RTR0MEMOBJ pMemObjAPIC;
247 /** Physical address of the virtual APIC mmio cache. */
248 RTHCPHYS pAPICPhys;
249 /** Virtual address of the virtual APIC mmio cache. */
250 R0PTRTYPE(uint8_t *) pAPIC;
251
252 /** R0 memory object for the MSR bitmap (1 page). */
253 RTR0MEMOBJ pMemObjMSRBitmap;
254 /** Physical address of the MSR bitmap (1 page). */
255 RTHCPHYS pMSRBitmapPhys;
256 /** Virtual address of the MSR bitmap (1 page). */
257 R0PTRTYPE(uint8_t *) pMSRBitmap;
258
259 /** R0 memory object for the MSR entry load page (guest MSRs). */
260 RTR0MEMOBJ pMemObjMSREntryLoad;
261 /** Physical address of the MSR entry load page (guest MSRs). */
262 RTHCPHYS pMSREntryLoadPhys;
263 /** Virtual address of the MSR entry load page (guest MSRs). */
264 R0PTRTYPE(uint8_t *) pMSREntryLoad;
265
266 /** R0 memory object for the MSR exit store page (guest MSRs). */
267 RTR0MEMOBJ pMemObjMSRExitStore;
268 /** Physical address of the MSR exit store page (guest MSRs). */
269 RTHCPHYS pMSRExitStorePhys;
270 /** Virtual address of the MSR exit store page (guest MSRs). */
271 R0PTRTYPE(uint8_t *) pMSRExitStore;
272
273 /** R0 memory object for the MSR exit load page (host MSRs). */
274 RTR0MEMOBJ pMemObjMSRExitLoad;
275 /** Physical address of the MSR exit load page (host MSRs). */
276 RTHCPHYS pMSRExitLoadPhys;
277 /** Virtual address of the MSR exit load page (host MSRs). */
278 R0PTRTYPE(uint8_t *) pMSRExitLoad;
279
280 /** Ring 0 handlers for VT-x. */
281 DECLR0CALLBACKMEMBER(int, pfnStartVM,(RTHCUINT fResume, PCPUMCTX pCtx));
282 DECLR0CALLBACKMEMBER(void, pfnSetupTaggedTLB, (PVM pVM));
283
284#if HC_ARCH_BITS == 32
285 uint32_t Alignment1;
286#endif
287
288 /** Host CR4 value (set by ring-0 VMX init) */
289 uint64_t hostCR4;
290
291 /** Current VMX_VMCS_CTRL_PROC_EXEC_CONTROLS. */
292 uint64_t proc_ctls;
293
294 /** Current CR0 mask. */
295 uint64_t cr0_mask;
296 /** Current CR4 mask. */
297 uint64_t cr4_mask;
298
299 /** Current EPTP. */
300 RTHCPHYS GCPhysEPTP;
301
302 /** VMX MSR values */
303 struct
304 {
305 uint64_t feature_ctrl;
306 uint64_t vmx_basic_info;
307 VMX_CAPABILITY vmx_pin_ctls;
308 VMX_CAPABILITY vmx_proc_ctls;
309 VMX_CAPABILITY vmx_proc_ctls2;
310 VMX_CAPABILITY vmx_exit;
311 VMX_CAPABILITY vmx_entry;
312 uint64_t vmx_misc;
313 uint64_t vmx_cr0_fixed0;
314 uint64_t vmx_cr0_fixed1;
315 uint64_t vmx_cr4_fixed0;
316 uint64_t vmx_cr4_fixed1;
317 uint64_t vmx_vmcs_enum;
318 uint64_t vmx_eptcaps;
319 } msr;
320
321 /* Last instruction error */
322 uint32_t ulLastInstrError;
323
324 /** Current trap mask. */
325 uint32_t u32TrapMask;
326
327 /** The last known guest paging mode. */
328 PGMMODE enmCurrGuestMode;
329
330 /** Flush types for invept & invvpid; they depend on capabilities. */
331 VMX_FLUSH enmFlushPage;
332 VMX_FLUSH enmFlushContext;
333
334 /** Real-mode emulation state. */
335 struct
336 {
337 struct
338 {
339 uint32_t fPending;
340 uint32_t padding4;
341 uint64_t intInfo;
342 } Event;
343
344 CPUMSELREGHID dsHid;
345 CPUMSELREGHID esHid;
346 CPUMSELREGHID fsHid;
347 CPUMSELREGHID gsHid;
348 CPUMSELREGHID ssHid;
349 RTSEL ds;
350 RTSEL es;
351 RTSEL fs;
352 RTSEL gs;
353 RTSEL ss;
354 RTSEL padding5[3];
355 uint32_t eip;
356 uint32_t fValid;
357 } RealMode;
358
359 struct
360 {
361 uint64_t u64VMCSPhys;
362 uint32_t ulVMCSRevision;
363 } lasterror;
364 } vmx;
365
366 struct
367 {
368 /** Set by the ring-0 driver to indicate SVM is supported by the CPU. */
369 bool fSupported;
370 /** Set when we've enabled SVM. */
371 bool fEnabled;
372 /** Set if we don't have to flush the TLB on VM entry. */
373 bool fResumeVM;
374 /** Set if erratum 170 affects the AMD cpu. */
375 bool fAlwaysFlushTLB;
376
377 /** R0 memory object for the VM control block (VMCB). */
378 RTR0MEMOBJ pMemObjVMCB;
379 /** Physical address of the VM control block (VMCB). */
380 RTHCPHYS pVMCBPhys;
381 /** Virtual address of the VM control block (VMCB). */
382 R0PTRTYPE(void *) pVMCB;
383
384 /** R0 memory object for the host VM control block (VMCB). */
385 RTR0MEMOBJ pMemObjVMCBHost;
386 /** Physical address of the host VM control block (VMCB). */
387 RTHCPHYS pVMCBHostPhys;
388 /** Virtual address of the host VM control block (VMCB). */
389 R0PTRTYPE(void *) pVMCBHost;
390
391 /** R0 memory object for the IO bitmap (12kb). */
392 RTR0MEMOBJ pMemObjIOBitmap;
393 /** Physical address of the IO bitmap (12kb). */
394 RTHCPHYS pIOBitmapPhys;
395 /** Virtual address of the IO bitmap. */
396 R0PTRTYPE(void *) pIOBitmap;
397
398 /** R0 memory object for the MSR bitmap (8kb). */
399 RTR0MEMOBJ pMemObjMSRBitmap;
400 /** Physical address of the MSR bitmap (8kb). */
401 RTHCPHYS pMSRBitmapPhys;
402 /** Virtual address of the MSR bitmap. */
403 R0PTRTYPE(void *) pMSRBitmap;
404
405 /** Ring 0 handlers for VT-x. */
406 DECLR0CALLBACKMEMBER(int, pfnVMRun,(RTHCPHYS pVMCBHostPhys, RTHCPHYS pVMCBPhys, PCPUMCTX pCtx));
407
408 /** SVM revision. */
409 uint32_t u32Rev;
410
411 /** SVM feature bits from cpuid 0x8000000a */
412 uint32_t u32Features;
413 } svm;
414
415 struct
416 {
417 uint32_t u32AMDFeatureECX;
418 uint32_t u32AMDFeatureEDX;
419 } cpuid;
420
421 /** Event injection state. */
422 struct
423 {
424 uint32_t fPending;
425 uint32_t errCode;
426 uint64_t intInfo;
427 } Event;
428
429 /** Saved error from detection */
430 int32_t lLastError;
431
432 /** HWACCMR0Init was run */
433 bool fHWACCMR0Init;
434
435 /** Currenty shadow paging mode. */
436 PGMMODE enmShadowMode;
437
438 /** Explicit alignment padding of StatEntry (32-bit g++ again). */
439 int32_t padding2;
440
441#ifdef VBOX_STRICT
442 /** The CPU ID of the CPU currently owning the VMCS. Set in
443 * HWACCMR0Enter and cleared in HWACCMR0Leave. */
444 RTCPUID idEnteredCpu;
445# if HC_ARCH_BITS == 32
446 RTCPUID Alignment0;
447# endif
448#endif
449
450 STAMPROFILEADV StatEntry;
451 STAMPROFILEADV StatExit;
452 STAMPROFILEADV StatInGC;
453
454 STAMCOUNTER StatIntInject;
455
456 STAMCOUNTER StatExitShadowNM;
457 STAMCOUNTER StatExitGuestNM;
458 STAMCOUNTER StatExitShadowPF;
459 STAMCOUNTER StatExitGuestPF;
460 STAMCOUNTER StatExitGuestUD;
461 STAMCOUNTER StatExitGuestSS;
462 STAMCOUNTER StatExitGuestNP;
463 STAMCOUNTER StatExitGuestGP;
464 STAMCOUNTER StatExitGuestDE;
465 STAMCOUNTER StatExitGuestDB;
466 STAMCOUNTER StatExitGuestMF;
467 STAMCOUNTER StatExitInvpg;
468 STAMCOUNTER StatExitInvd;
469 STAMCOUNTER StatExitCpuid;
470 STAMCOUNTER StatExitRdtsc;
471 STAMCOUNTER StatExitCRxWrite;
472 STAMCOUNTER StatExitCRxRead;
473 STAMCOUNTER StatExitDRxWrite;
474 STAMCOUNTER StatExitDRxRead;
475 STAMCOUNTER StatExitCLTS;
476 STAMCOUNTER StatExitLMSW;
477 STAMCOUNTER StatExitIOWrite;
478 STAMCOUNTER StatExitIORead;
479 STAMCOUNTER StatExitIOStringWrite;
480 STAMCOUNTER StatExitIOStringRead;
481 STAMCOUNTER StatExitIrqWindow;
482 STAMCOUNTER StatExitMaxResume;
483 STAMCOUNTER StatIntReinject;
484 STAMCOUNTER StatPendingHostIrq;
485
486 STAMCOUNTER StatFlushPageManual;
487 STAMCOUNTER StatFlushPhysPageManual;
488 STAMCOUNTER StatFlushTLBManual;
489 STAMCOUNTER StatFlushPageInvlpg;
490 STAMCOUNTER StatFlushTLBWorldSwitch;
491 STAMCOUNTER StatNoFlushTLBWorldSwitch;
492 STAMCOUNTER StatFlushTLBCRxChange;
493 STAMCOUNTER StatFlushASID;
494
495 STAMCOUNTER StatSwitchGuestIrq;
496 STAMCOUNTER StatSwitchToR3;
497
498 STAMCOUNTER StatTSCOffset;
499 STAMCOUNTER StatTSCIntercept;
500
501 STAMCOUNTER StatExitReasonNPF;
502 STAMCOUNTER StatDRxArmed;
503 STAMCOUNTER StatDRxContextSwitch;
504 STAMCOUNTER StatDRxIOCheck;
505
506
507 R3PTRTYPE(PSTAMCOUNTER) paStatExitReason;
508 R0PTRTYPE(PSTAMCOUNTER) paStatExitReasonR0;
509} HWACCM;
510/** Pointer to HWACCM VM instance data. */
511typedef HWACCM *PHWACCM;
512
513#ifdef IN_RING0
514
515VMMR0DECL(PHWACCM_CPUINFO) HWACCMR0GetCurrentCpu();
516
517#ifdef VBOX_STRICT
518VMMR0DECL(void) HWACCMDumpRegs(PVM pVM, PCPUMCTX pCtx);
519VMMR0DECL(void) HWACCMR0DumpDescriptor(PX86DESCHC Desc, RTSEL Sel, const char *pszMsg);
520#else
521#define HWACCMDumpRegs(a, b) do { } while (0)
522#define HWACCMR0DumpDescriptor(a, b, c) do { } while (0)
523#endif
524
525/* Dummy callback handlers. */
526VMMR0DECL(int) HWACCMR0DummyEnter(PVM pVM, PHWACCM_CPUINFO pCpu);
527VMMR0DECL(int) HWACCMR0DummyLeave(PVM pVM, CPUMCTX *pCtx);
528VMMR0DECL(int) HWACCMR0DummyEnableCpu(PHWACCM_CPUINFO pCpu, PVM pVM, void *pvPageCpu, RTHCPHYS pPageCpuPhys);
529VMMR0DECL(int) HWACCMR0DummyDisableCpu(PHWACCM_CPUINFO pCpu, void *pvPageCpu, RTHCPHYS pPageCpuPhys);
530VMMR0DECL(int) HWACCMR0DummyInitVM(PVM pVM);
531VMMR0DECL(int) HWACCMR0DummyTermVM(PVM pVM);
532VMMR0DECL(int) HWACCMR0DummySetupVM(PVM pVM);
533VMMR0DECL(int) HWACCMR0DummyRunGuestCode(PVM pVM, CPUMCTX *pCtx);
534VMMR0DECL(int) HWACCMR0DummySaveHostState(PVM pVM);
535VMMR0DECL(int) HWACCMR0DummyLoadGuestState(PVM pVM, CPUMCTX *pCtx);
536
537#endif /* IN_RING0 */
538
539/** @} */
540
541__END_DECLS
542
543#endif
544
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