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source: vbox/trunk/src/VBox/VMM/HWACCMInternal.h@ 13204

Last change on this file since 13204 was 13204, checked in by vboxsync, 17 years ago

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1/* $Id: HWACCMInternal.h 13204 2008-10-13 10:09:21Z vboxsync $ */
2/** @file
3 * HWACCM - Internal header file.
4 */
5
6/*
7 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 */
21
22#ifndef ___HWACCMInternal_h
23#define ___HWACCMInternal_h
24
25#include <VBox/cdefs.h>
26#include <VBox/types.h>
27#include <VBox/em.h>
28#include <VBox/stam.h>
29#include <VBox/dis.h>
30#include <VBox/hwaccm.h>
31#include <VBox/pgm.h>
32#include <VBox/cpum.h>
33#include <iprt/memobj.h>
34#include <iprt/cpuset.h>
35#include <iprt/mp.h>
36
37#if HC_ARCH_BITS == 64
38/* Enable 64 bits guest support. */
39# define VBOX_ENABLE_64_BITS_GUESTS
40#endif
41
42#define HWACCM_VMX_EMULATE_REALMODE
43#define HWACCM_VTX_WITH_EPT
44
45__BEGIN_DECLS
46
47
48/** @defgroup grp_hwaccm_int Internal
49 * @ingroup grp_hwaccm
50 * @internal
51 * @{
52 */
53
54
55/**
56 * Converts a HWACCM pointer into a VM pointer.
57 * @returns Pointer to the VM structure the EM is part of.
58 * @param pHWACCM Pointer to HWACCM instance data.
59 */
60#define HWACCM2VM(pHWACCM) ( (PVM)((char*)pHWACCM - pHWACCM->offVM) )
61
62/** Maximum number of exit reason statistics counters. */
63#define MAX_EXITREASON_STAT 0x100
64#define MASK_EXITREASON_STAT 0xff
65
66/** @name Changed flags
67 * These flags are used to keep track of which important registers that
68 * have been changed since last they were reset.
69 * @{
70 */
71#define HWACCM_CHANGED_GUEST_FPU RT_BIT(0)
72#define HWACCM_CHANGED_GUEST_CR0 RT_BIT(1)
73#define HWACCM_CHANGED_GUEST_CR3 RT_BIT(2)
74#define HWACCM_CHANGED_GUEST_CR4 RT_BIT(3)
75#define HWACCM_CHANGED_GUEST_GDTR RT_BIT(4)
76#define HWACCM_CHANGED_GUEST_IDTR RT_BIT(5)
77#define HWACCM_CHANGED_GUEST_LDTR RT_BIT(6)
78#define HWACCM_CHANGED_GUEST_TR RT_BIT(7)
79#define HWACCM_CHANGED_GUEST_SYSENTER_MSR RT_BIT(8)
80#define HWACCM_CHANGED_GUEST_SEGMENT_REGS RT_BIT(9)
81#define HWACCM_CHANGED_GUEST_DEBUG RT_BIT(10)
82#define HWACCM_CHANGED_HOST_CONTEXT RT_BIT(11)
83
84#define HWACCM_CHANGED_ALL ( HWACCM_CHANGED_GUEST_SEGMENT_REGS \
85 | HWACCM_CHANGED_GUEST_CR0 \
86 | HWACCM_CHANGED_GUEST_CR3 \
87 | HWACCM_CHANGED_GUEST_CR4 \
88 | HWACCM_CHANGED_GUEST_GDTR \
89 | HWACCM_CHANGED_GUEST_IDTR \
90 | HWACCM_CHANGED_GUEST_LDTR \
91 | HWACCM_CHANGED_GUEST_TR \
92 | HWACCM_CHANGED_GUEST_SYSENTER_MSR \
93 | HWACCM_CHANGED_GUEST_FPU \
94 | HWACCM_CHANGED_GUEST_DEBUG \
95 | HWACCM_CHANGED_HOST_CONTEXT)
96
97#define HWACCM_CHANGED_ALL_GUEST ( HWACCM_CHANGED_GUEST_SEGMENT_REGS \
98 | HWACCM_CHANGED_GUEST_CR0 \
99 | HWACCM_CHANGED_GUEST_CR3 \
100 | HWACCM_CHANGED_GUEST_CR4 \
101 | HWACCM_CHANGED_GUEST_GDTR \
102 | HWACCM_CHANGED_GUEST_IDTR \
103 | HWACCM_CHANGED_GUEST_LDTR \
104 | HWACCM_CHANGED_GUEST_TR \
105 | HWACCM_CHANGED_GUEST_SYSENTER_MSR \
106 | HWACCM_CHANGED_GUEST_DEBUG \
107 | HWACCM_CHANGED_GUEST_FPU)
108
109/** @} */
110
111/** @name Intercepted traps
112 * Traps that need to be intercepted so we can correctly dispatch them to the guest if required.
113 * Currently #NM and #PF only
114 */
115#ifdef VBOX_STRICT
116#define HWACCM_VMX_TRAP_MASK RT_BIT(X86_XCPT_DE) | RT_BIT(X86_XCPT_NM) | RT_BIT(X86_XCPT_PF) | RT_BIT(X86_XCPT_UD) | RT_BIT(X86_XCPT_NP) | RT_BIT(X86_XCPT_SS) | RT_BIT(X86_XCPT_GP) | RT_BIT(X86_XCPT_MF)
117#define HWACCM_SVM_TRAP_MASK HWACCM_VMX_TRAP_MASK
118#else
119#define HWACCM_VMX_TRAP_MASK RT_BIT(X86_XCPT_NM) | RT_BIT(X86_XCPT_PF)
120#define HWACCM_SVM_TRAP_MASK RT_BIT(X86_XCPT_NM) | RT_BIT(X86_XCPT_PF)
121#endif
122/** @} */
123
124
125/** Maxium resume loops allowed in ring 0 (safety precaution) */
126#define HWACCM_MAX_RESUME_LOOPS 1024
127
128/** Size for the EPT identity page table (1024 4 MB pages to cover the entire address space). */
129#define HWACCM_EPT_IDENTITY_PG_TABLE_SIZE PAGE_SIZE
130/** Size of the TSS structure + 2 pages for the IO bitmap + end byte. */
131#define HWACCM_VTX_TSS_SIZE (sizeof(VBOXTSS) + 2*PAGE_SIZE + 1)
132/** Total guest mapped memory needed. */
133#define HWACCM_VTX_TOTAL_DEVHEAP_MEM (HWACCM_EPT_IDENTITY_PG_TABLE_SIZE + HWACCM_VTX_TSS_SIZE)
134
135/** HWACCM SSM version
136 */
137#define HWACCM_SSM_VERSION 3
138
139/* Per-cpu information. */
140typedef struct
141{
142 RTCPUID idCpu;
143
144 RTR0MEMOBJ pMemObj;
145 /* Current ASID (AMD-V)/VPID (Intel) */
146 uint32_t uCurrentASID;
147 /* TLB flush count */
148 uint32_t cTLBFlushes;
149
150 /* Set the first time a cpu is used to make sure we start with a clean TLB. */
151 bool fFlushTLB;
152
153 bool fConfigured;
154} HWACCM_CPUINFO;
155typedef HWACCM_CPUINFO *PHWACCM_CPUINFO;
156
157/* VT-x capability qword. */
158typedef union
159{
160 struct
161 {
162 uint32_t disallowed0;
163 uint32_t allowed1;
164 } n;
165 uint64_t u;
166} VMX_CAPABILITY;
167
168/**
169 * HWACCM VM Instance data.
170 * Changes to this must checked against the padding of the cfgm union in VM!
171 */
172typedef struct HWACCM
173{
174 /** Offset to the VM structure.
175 * See HWACCM2VM(). */
176 RTUINT offVM;
177
178 /** Set when we've initialized VMX or SVM. */
179 bool fInitialized;
180 /** Set when we're using VMX/SVN at that moment. */
181 bool fActive;
182
183 /** Set when hardware acceleration is allowed. */
184 bool fAllowed;
185
186 /** Set if nested paging is enabled. */
187 bool fNestedPaging;
188
189 /** Set if nested paging is allowed. */
190 bool fAllowNestedPaging;
191
192 /** Set if we need to flush the TLB during the world switch. */
193 bool fForceTLBFlush;
194
195 /** Old style FPU reporting trap mask override performed (optimization) */
196 bool fFPUOldStyleOverride;
197
198 /** Explicit alignment padding to make 32-bit gcc align u64RegisterMask
199 * naturally. */
200 bool padding[1];
201
202 /** HWACCM_CHANGED_* flags. */
203 RTUINT fContextUseFlags;
204
205 /* Id of the last cpu we were executing code on (NIL_RTCPUID for the first time) */
206 RTCPUID idLastCpu;
207
208 /* TLB flush count */
209 RTUINT cTLBFlushes;
210
211 /* Current ASID in use by the VM */
212 RTUINT uCurrentASID;
213
214 /** Maximum ASID allowed. */
215 RTUINT uMaxASID;
216
217 /** And mask for copying register contents. */
218 uint64_t u64RegisterMask;
219 struct
220 {
221 /** Set by the ring-0 driver to indicate VMX is supported by the CPU. */
222 bool fSupported;
223
224 /** Set when we've enabled VMX. */
225 bool fEnabled;
226
227 /** Set if we can use VMXResume to execute guest code. */
228 bool fResumeVM;
229
230 /** Set if VPID is supported. */
231 bool fVPID;
232
233 /** R0 memory object for the VM control structure (VMCS). */
234 RTR0MEMOBJ pMemObjVMCS;
235 /** Physical address of the VM control structure (VMCS). */
236 RTHCPHYS pVMCSPhys;
237 /** Virtual address of the VM control structure (VMCS). */
238 R0PTRTYPE(void *) pVMCS;
239
240 /** Virtual address of the TSS page used for real mode emulation. */
241 R3PTRTYPE(PVBOXTSS) pRealModeTSS;
242
243 /** Virtual address of the identity page table used for real mode and protected mode without paging emulation in EPT mode. */
244 R3PTRTYPE(PX86PD) pNonPagingModeEPTPageTable;
245
246 /** R0 memory object for the virtual APIC mmio cache. */
247 RTR0MEMOBJ pMemObjAPIC;
248 /** Physical address of the virtual APIC mmio cache. */
249 RTHCPHYS pAPICPhys;
250 /** Virtual address of the virtual APIC mmio cache. */
251 R0PTRTYPE(uint8_t *) pAPIC;
252
253 /** R0 memory object for the MSR bitmap (1 page). */
254 RTR0MEMOBJ pMemObjMSRBitmap;
255 /** Physical address of the MSR bitmap (1 page). */
256 RTHCPHYS pMSRBitmapPhys;
257 /** Virtual address of the MSR bitmap (1 page). */
258 R0PTRTYPE(uint8_t *) pMSRBitmap;
259
260 /** R0 memory object for the MSR entry load page (guest MSRs). */
261 RTR0MEMOBJ pMemObjMSREntryLoad;
262 /** Physical address of the MSR entry load page (guest MSRs). */
263 RTHCPHYS pMSREntryLoadPhys;
264 /** Virtual address of the MSR entry load page (guest MSRs). */
265 R0PTRTYPE(uint8_t *) pMSREntryLoad;
266
267 /** R0 memory object for the MSR exit store page (guest MSRs). */
268 RTR0MEMOBJ pMemObjMSRExitStore;
269 /** Physical address of the MSR exit store page (guest MSRs). */
270 RTHCPHYS pMSRExitStorePhys;
271 /** Virtual address of the MSR exit store page (guest MSRs). */
272 R0PTRTYPE(uint8_t *) pMSRExitStore;
273
274 /** R0 memory object for the MSR exit load page (host MSRs). */
275 RTR0MEMOBJ pMemObjMSRExitLoad;
276 /** Physical address of the MSR exit load page (host MSRs). */
277 RTHCPHYS pMSRExitLoadPhys;
278 /** Virtual address of the MSR exit load page (host MSRs). */
279 R0PTRTYPE(uint8_t *) pMSRExitLoad;
280
281 /** Ring 0 handlers for VT-x. */
282 DECLR0CALLBACKMEMBER(int, pfnStartVM,(RTHCUINT fResume, PCPUMCTX pCtx));
283 DECLR0CALLBACKMEMBER(void, pfnSetupTaggedTLB, (PVM pVM));
284
285#if HC_ARCH_BITS == 32
286 uint32_t Alignment1;
287#endif
288
289 /** Host CR4 value (set by ring-0 VMX init) */
290 uint64_t hostCR4;
291
292 /** Current VMX_VMCS_CTRL_PROC_EXEC_CONTROLS. */
293 uint64_t proc_ctls;
294
295 /** Current CR0 mask. */
296 uint64_t cr0_mask;
297 /** Current CR4 mask. */
298 uint64_t cr4_mask;
299
300 /** Current EPTP. */
301 RTHCPHYS GCPhysEPTP;
302
303 /** VMX MSR values */
304 struct
305 {
306 uint64_t feature_ctrl;
307 uint64_t vmx_basic_info;
308 VMX_CAPABILITY vmx_pin_ctls;
309 VMX_CAPABILITY vmx_proc_ctls;
310 VMX_CAPABILITY vmx_proc_ctls2;
311 VMX_CAPABILITY vmx_exit;
312 VMX_CAPABILITY vmx_entry;
313 uint64_t vmx_misc;
314 uint64_t vmx_cr0_fixed0;
315 uint64_t vmx_cr0_fixed1;
316 uint64_t vmx_cr4_fixed0;
317 uint64_t vmx_cr4_fixed1;
318 uint64_t vmx_vmcs_enum;
319 uint64_t vmx_eptcaps;
320 } msr;
321
322 /* Last instruction error */
323 uint32_t ulLastInstrError;
324
325 /** Current trap mask. */
326 uint32_t u32TrapMask;
327
328 /** The last known guest paging mode. */
329 PGMMODE enmCurrGuestMode;
330
331 /** Flush types for invept & invvpid; they depend on capabilities. */
332 VMX_FLUSH enmFlushPage;
333 VMX_FLUSH enmFlushContext;
334
335 /** Real-mode emulation state. */
336 struct
337 {
338 struct
339 {
340 uint32_t fPending;
341 uint32_t padding4;
342 uint64_t intInfo;
343 } Event;
344
345 CPUMSELREGHID dsHid;
346 CPUMSELREGHID esHid;
347 CPUMSELREGHID fsHid;
348 CPUMSELREGHID gsHid;
349 CPUMSELREGHID ssHid;
350 RTSEL ds;
351 RTSEL es;
352 RTSEL fs;
353 RTSEL gs;
354 RTSEL ss;
355 RTSEL padding5[3];
356 uint32_t eip;
357 uint32_t fValid;
358 } RealMode;
359
360 struct
361 {
362 uint64_t u64VMCSPhys;
363 uint32_t ulVMCSRevision;
364 } lasterror;
365 } vmx;
366
367 struct
368 {
369 /** Set by the ring-0 driver to indicate SVM is supported by the CPU. */
370 bool fSupported;
371 /** Set when we've enabled SVM. */
372 bool fEnabled;
373 /** Set if we don't have to flush the TLB on VM entry. */
374 bool fResumeVM;
375 /** Set if erratum 170 affects the AMD cpu. */
376 bool fAlwaysFlushTLB;
377
378 /** R0 memory object for the VM control block (VMCB). */
379 RTR0MEMOBJ pMemObjVMCB;
380 /** Physical address of the VM control block (VMCB). */
381 RTHCPHYS pVMCBPhys;
382 /** Virtual address of the VM control block (VMCB). */
383 R0PTRTYPE(void *) pVMCB;
384
385 /** R0 memory object for the host VM control block (VMCB). */
386 RTR0MEMOBJ pMemObjVMCBHost;
387 /** Physical address of the host VM control block (VMCB). */
388 RTHCPHYS pVMCBHostPhys;
389 /** Virtual address of the host VM control block (VMCB). */
390 R0PTRTYPE(void *) pVMCBHost;
391
392 /** R0 memory object for the IO bitmap (12kb). */
393 RTR0MEMOBJ pMemObjIOBitmap;
394 /** Physical address of the IO bitmap (12kb). */
395 RTHCPHYS pIOBitmapPhys;
396 /** Virtual address of the IO bitmap. */
397 R0PTRTYPE(void *) pIOBitmap;
398
399 /** R0 memory object for the MSR bitmap (8kb). */
400 RTR0MEMOBJ pMemObjMSRBitmap;
401 /** Physical address of the MSR bitmap (8kb). */
402 RTHCPHYS pMSRBitmapPhys;
403 /** Virtual address of the MSR bitmap. */
404 R0PTRTYPE(void *) pMSRBitmap;
405
406 /** Ring 0 handlers for VT-x. */
407 DECLR0CALLBACKMEMBER(int, pfnVMRun,(RTHCPHYS pVMCBHostPhys, RTHCPHYS pVMCBPhys, PCPUMCTX pCtx));
408
409 /** SVM revision. */
410 uint32_t u32Rev;
411
412 /** SVM feature bits from cpuid 0x8000000a */
413 uint32_t u32Features;
414 } svm;
415
416 struct
417 {
418 uint32_t u32AMDFeatureECX;
419 uint32_t u32AMDFeatureEDX;
420 } cpuid;
421
422 /** Event injection state. */
423 struct
424 {
425 uint32_t fPending;
426 uint32_t errCode;
427 uint64_t intInfo;
428 } Event;
429
430 /** Saved error from detection */
431 int32_t lLastError;
432
433 /** HWACCMR0Init was run */
434 bool fHWACCMR0Init;
435
436 /** Currenty shadow paging mode. */
437 PGMMODE enmShadowMode;
438
439 /** Explicit alignment padding of StatEntry (32-bit g++ again). */
440 int32_t padding2;
441
442#ifdef VBOX_STRICT
443 /** The CPU ID of the CPU currently owning the VMCS. Set in
444 * HWACCMR0Enter and cleared in HWACCMR0Leave. */
445 RTCPUID idEnteredCpu;
446# if HC_ARCH_BITS == 32
447 RTCPUID Alignment0;
448# endif
449#endif
450
451 STAMPROFILEADV StatEntry;
452 STAMPROFILEADV StatExit;
453 STAMPROFILEADV StatInGC;
454
455 STAMCOUNTER StatIntInject;
456
457 STAMCOUNTER StatExitShadowNM;
458 STAMCOUNTER StatExitGuestNM;
459 STAMCOUNTER StatExitShadowPF;
460 STAMCOUNTER StatExitGuestPF;
461 STAMCOUNTER StatExitGuestUD;
462 STAMCOUNTER StatExitGuestSS;
463 STAMCOUNTER StatExitGuestNP;
464 STAMCOUNTER StatExitGuestGP;
465 STAMCOUNTER StatExitGuestDE;
466 STAMCOUNTER StatExitGuestDB;
467 STAMCOUNTER StatExitGuestMF;
468 STAMCOUNTER StatExitInvpg;
469 STAMCOUNTER StatExitInvd;
470 STAMCOUNTER StatExitCpuid;
471 STAMCOUNTER StatExitRdtsc;
472 STAMCOUNTER StatExitCRxWrite;
473 STAMCOUNTER StatExitCRxRead;
474 STAMCOUNTER StatExitDRxWrite;
475 STAMCOUNTER StatExitDRxRead;
476 STAMCOUNTER StatExitCLTS;
477 STAMCOUNTER StatExitLMSW;
478 STAMCOUNTER StatExitIOWrite;
479 STAMCOUNTER StatExitIORead;
480 STAMCOUNTER StatExitIOStringWrite;
481 STAMCOUNTER StatExitIOStringRead;
482 STAMCOUNTER StatExitIrqWindow;
483 STAMCOUNTER StatExitMaxResume;
484 STAMCOUNTER StatIntReinject;
485 STAMCOUNTER StatPendingHostIrq;
486
487 STAMCOUNTER StatFlushPageManual;
488 STAMCOUNTER StatFlushPhysPageManual;
489 STAMCOUNTER StatFlushTLBManual;
490 STAMCOUNTER StatFlushPageInvlpg;
491 STAMCOUNTER StatFlushTLBWorldSwitch;
492 STAMCOUNTER StatNoFlushTLBWorldSwitch;
493 STAMCOUNTER StatFlushTLBCRxChange;
494 STAMCOUNTER StatFlushASID;
495
496 STAMCOUNTER StatSwitchGuestIrq;
497 STAMCOUNTER StatSwitchToR3;
498
499 STAMCOUNTER StatTSCOffset;
500 STAMCOUNTER StatTSCIntercept;
501
502 STAMCOUNTER StatExitReasonNPF;
503 STAMCOUNTER StatDRxArmed;
504 STAMCOUNTER StatDRxContextSwitch;
505 STAMCOUNTER StatDRxIOCheck;
506
507
508 R3PTRTYPE(PSTAMCOUNTER) paStatExitReason;
509 R0PTRTYPE(PSTAMCOUNTER) paStatExitReasonR0;
510} HWACCM;
511/** Pointer to HWACCM VM instance data. */
512typedef HWACCM *PHWACCM;
513
514#ifdef IN_RING0
515
516VMMR0DECL(PHWACCM_CPUINFO) HWACCMR0GetCurrentCpu();
517
518#ifdef VBOX_STRICT
519VMMR0DECL(void) HWACCMDumpRegs(PVM pVM, PCPUMCTX pCtx);
520VMMR0DECL(void) HWACCMR0DumpDescriptor(PX86DESCHC Desc, RTSEL Sel, const char *pszMsg);
521#else
522#define HWACCMDumpRegs(a, b) do { } while (0)
523#define HWACCMR0DumpDescriptor(a, b, c) do { } while (0)
524#endif
525
526/* Dummy callback handlers. */
527VMMR0DECL(int) HWACCMR0DummyEnter(PVM pVM, PHWACCM_CPUINFO pCpu);
528VMMR0DECL(int) HWACCMR0DummyLeave(PVM pVM, CPUMCTX *pCtx);
529VMMR0DECL(int) HWACCMR0DummyEnableCpu(PHWACCM_CPUINFO pCpu, PVM pVM, void *pvPageCpu, RTHCPHYS pPageCpuPhys);
530VMMR0DECL(int) HWACCMR0DummyDisableCpu(PHWACCM_CPUINFO pCpu, void *pvPageCpu, RTHCPHYS pPageCpuPhys);
531VMMR0DECL(int) HWACCMR0DummyInitVM(PVM pVM);
532VMMR0DECL(int) HWACCMR0DummyTermVM(PVM pVM);
533VMMR0DECL(int) HWACCMR0DummySetupVM(PVM pVM);
534VMMR0DECL(int) HWACCMR0DummyRunGuestCode(PVM pVM, CPUMCTX *pCtx);
535VMMR0DECL(int) HWACCMR0DummySaveHostState(PVM pVM);
536VMMR0DECL(int) HWACCMR0DummyLoadGuestState(PVM pVM, CPUMCTX *pCtx);
537
538#endif /* IN_RING0 */
539
540/** @} */
541
542__END_DECLS
543
544#endif
545
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