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source: vbox/trunk/src/VBox/VMM/HWACCMInternal.h@ 13257

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1/* $Id: HWACCMInternal.h 13257 2008-10-14 12:51:09Z vboxsync $ */
2/** @file
3 * HWACCM - Internal header file.
4 */
5
6/*
7 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 */
21
22#ifndef ___HWACCMInternal_h
23#define ___HWACCMInternal_h
24
25#include <VBox/cdefs.h>
26#include <VBox/types.h>
27#include <VBox/em.h>
28#include <VBox/stam.h>
29#include <VBox/dis.h>
30#include <VBox/hwaccm.h>
31#include <VBox/pgm.h>
32#include <VBox/cpum.h>
33#include <iprt/memobj.h>
34#include <iprt/cpuset.h>
35#include <iprt/mp.h>
36
37#if HC_ARCH_BITS == 64
38/* Enable 64 bits guest support. */
39# define VBOX_ENABLE_64_BITS_GUESTS
40#endif
41
42#define HWACCM_VMX_EMULATE_REALMODE
43#define HWACCM_VTX_WITH_EPT
44#define HWACCM_VTX_WITH_VPID
45
46__BEGIN_DECLS
47
48
49/** @defgroup grp_hwaccm_int Internal
50 * @ingroup grp_hwaccm
51 * @internal
52 * @{
53 */
54
55
56/**
57 * Converts a HWACCM pointer into a VM pointer.
58 * @returns Pointer to the VM structure the EM is part of.
59 * @param pHWACCM Pointer to HWACCM instance data.
60 */
61#define HWACCM2VM(pHWACCM) ( (PVM)((char*)pHWACCM - pHWACCM->offVM) )
62
63/** Maximum number of exit reason statistics counters. */
64#define MAX_EXITREASON_STAT 0x100
65#define MASK_EXITREASON_STAT 0xff
66
67/** @name Changed flags
68 * These flags are used to keep track of which important registers that
69 * have been changed since last they were reset.
70 * @{
71 */
72#define HWACCM_CHANGED_GUEST_FPU RT_BIT(0)
73#define HWACCM_CHANGED_GUEST_CR0 RT_BIT(1)
74#define HWACCM_CHANGED_GUEST_CR3 RT_BIT(2)
75#define HWACCM_CHANGED_GUEST_CR4 RT_BIT(3)
76#define HWACCM_CHANGED_GUEST_GDTR RT_BIT(4)
77#define HWACCM_CHANGED_GUEST_IDTR RT_BIT(5)
78#define HWACCM_CHANGED_GUEST_LDTR RT_BIT(6)
79#define HWACCM_CHANGED_GUEST_TR RT_BIT(7)
80#define HWACCM_CHANGED_GUEST_SYSENTER_MSR RT_BIT(8)
81#define HWACCM_CHANGED_GUEST_SEGMENT_REGS RT_BIT(9)
82#define HWACCM_CHANGED_GUEST_DEBUG RT_BIT(10)
83#define HWACCM_CHANGED_HOST_CONTEXT RT_BIT(11)
84
85#define HWACCM_CHANGED_ALL ( HWACCM_CHANGED_GUEST_SEGMENT_REGS \
86 | HWACCM_CHANGED_GUEST_CR0 \
87 | HWACCM_CHANGED_GUEST_CR3 \
88 | HWACCM_CHANGED_GUEST_CR4 \
89 | HWACCM_CHANGED_GUEST_GDTR \
90 | HWACCM_CHANGED_GUEST_IDTR \
91 | HWACCM_CHANGED_GUEST_LDTR \
92 | HWACCM_CHANGED_GUEST_TR \
93 | HWACCM_CHANGED_GUEST_SYSENTER_MSR \
94 | HWACCM_CHANGED_GUEST_FPU \
95 | HWACCM_CHANGED_GUEST_DEBUG \
96 | HWACCM_CHANGED_HOST_CONTEXT)
97
98#define HWACCM_CHANGED_ALL_GUEST ( HWACCM_CHANGED_GUEST_SEGMENT_REGS \
99 | HWACCM_CHANGED_GUEST_CR0 \
100 | HWACCM_CHANGED_GUEST_CR3 \
101 | HWACCM_CHANGED_GUEST_CR4 \
102 | HWACCM_CHANGED_GUEST_GDTR \
103 | HWACCM_CHANGED_GUEST_IDTR \
104 | HWACCM_CHANGED_GUEST_LDTR \
105 | HWACCM_CHANGED_GUEST_TR \
106 | HWACCM_CHANGED_GUEST_SYSENTER_MSR \
107 | HWACCM_CHANGED_GUEST_DEBUG \
108 | HWACCM_CHANGED_GUEST_FPU)
109
110/** @} */
111
112/** @name Intercepted traps
113 * Traps that need to be intercepted so we can correctly dispatch them to the guest if required.
114 * Currently #NM and #PF only
115 */
116#ifdef VBOX_STRICT
117#define HWACCM_VMX_TRAP_MASK RT_BIT(X86_XCPT_DE) | RT_BIT(X86_XCPT_NM) | RT_BIT(X86_XCPT_PF) | RT_BIT(X86_XCPT_UD) | RT_BIT(X86_XCPT_NP) | RT_BIT(X86_XCPT_SS) | RT_BIT(X86_XCPT_GP) | RT_BIT(X86_XCPT_MF)
118#define HWACCM_SVM_TRAP_MASK HWACCM_VMX_TRAP_MASK
119#else
120#define HWACCM_VMX_TRAP_MASK RT_BIT(X86_XCPT_NM) | RT_BIT(X86_XCPT_PF)
121#define HWACCM_SVM_TRAP_MASK RT_BIT(X86_XCPT_NM) | RT_BIT(X86_XCPT_PF)
122#endif
123/** @} */
124
125
126/** Maxium resume loops allowed in ring 0 (safety precaution) */
127#define HWACCM_MAX_RESUME_LOOPS 1024
128
129/** Size for the EPT identity page table (1024 4 MB pages to cover the entire address space). */
130#define HWACCM_EPT_IDENTITY_PG_TABLE_SIZE PAGE_SIZE
131/** Size of the TSS structure + 2 pages for the IO bitmap + end byte. */
132#define HWACCM_VTX_TSS_SIZE (sizeof(VBOXTSS) + 2*PAGE_SIZE + 1)
133/** Total guest mapped memory needed. */
134#define HWACCM_VTX_TOTAL_DEVHEAP_MEM (HWACCM_EPT_IDENTITY_PG_TABLE_SIZE + HWACCM_VTX_TSS_SIZE)
135
136/** HWACCM SSM version
137 */
138#define HWACCM_SSM_VERSION 3
139
140/* Per-cpu information. */
141typedef struct
142{
143 RTCPUID idCpu;
144
145 RTR0MEMOBJ pMemObj;
146 /* Current ASID (AMD-V)/VPID (Intel) */
147 uint32_t uCurrentASID;
148 /* TLB flush count */
149 uint32_t cTLBFlushes;
150
151 /* Set the first time a cpu is used to make sure we start with a clean TLB. */
152 bool fFlushTLB;
153
154 bool fConfigured;
155} HWACCM_CPUINFO;
156typedef HWACCM_CPUINFO *PHWACCM_CPUINFO;
157
158/* VT-x capability qword. */
159typedef union
160{
161 struct
162 {
163 uint32_t disallowed0;
164 uint32_t allowed1;
165 } n;
166 uint64_t u;
167} VMX_CAPABILITY;
168
169/**
170 * HWACCM VM Instance data.
171 * Changes to this must checked against the padding of the cfgm union in VM!
172 */
173typedef struct HWACCM
174{
175 /** Offset to the VM structure.
176 * See HWACCM2VM(). */
177 RTUINT offVM;
178
179 /** Set when we've initialized VMX or SVM. */
180 bool fInitialized;
181 /** Set when we're using VMX/SVN at that moment. */
182 bool fActive;
183
184 /** Set when hardware acceleration is allowed. */
185 bool fAllowed;
186
187 /** Set if nested paging is enabled. */
188 bool fNestedPaging;
189
190 /** Set if nested paging is allowed. */
191 bool fAllowNestedPaging;
192 /** Set if VT-x VPID is allowed. */
193 bool fAllowVPID;
194
195 /** Set if we need to flush the TLB during the world switch. */
196 bool fForceTLBFlush;
197
198 /** Old style FPU reporting trap mask override performed (optimization) */
199 bool fFPUOldStyleOverride;
200
201#if 0
202 /** Explicit alignment padding to make 32-bit gcc align u64RegisterMask
203 * naturally. */
204 bool padding[1];
205#endif
206
207 /** HWACCM_CHANGED_* flags. */
208 RTUINT fContextUseFlags;
209
210 /* Id of the last cpu we were executing code on (NIL_RTCPUID for the first time) */
211 RTCPUID idLastCpu;
212
213 /* TLB flush count */
214 RTUINT cTLBFlushes;
215
216 /* Current ASID in use by the VM */
217 RTUINT uCurrentASID;
218
219 /** Maximum ASID allowed. */
220 RTUINT uMaxASID;
221
222 /** And mask for copying register contents. */
223 uint64_t u64RegisterMask;
224 struct
225 {
226 /** Set by the ring-0 driver to indicate VMX is supported by the CPU. */
227 bool fSupported;
228
229 /** Set when we've enabled VMX. */
230 bool fEnabled;
231
232 /** Set if we can use VMXResume to execute guest code. */
233 bool fResumeVM;
234
235 /** Set if VPID is supported. */
236 bool fVPID;
237
238 /** R0 memory object for the VM control structure (VMCS). */
239 RTR0MEMOBJ pMemObjVMCS;
240 /** Physical address of the VM control structure (VMCS). */
241 RTHCPHYS pVMCSPhys;
242 /** Virtual address of the VM control structure (VMCS). */
243 R0PTRTYPE(void *) pVMCS;
244
245 /** Virtual address of the TSS page used for real mode emulation. */
246 R3PTRTYPE(PVBOXTSS) pRealModeTSS;
247
248 /** Virtual address of the identity page table used for real mode and protected mode without paging emulation in EPT mode. */
249 R3PTRTYPE(PX86PD) pNonPagingModeEPTPageTable;
250
251 /** R0 memory object for the virtual APIC mmio cache. */
252 RTR0MEMOBJ pMemObjAPIC;
253 /** Physical address of the virtual APIC mmio cache. */
254 RTHCPHYS pAPICPhys;
255 /** Virtual address of the virtual APIC mmio cache. */
256 R0PTRTYPE(uint8_t *) pAPIC;
257
258 /** R0 memory object for the MSR bitmap (1 page). */
259 RTR0MEMOBJ pMemObjMSRBitmap;
260 /** Physical address of the MSR bitmap (1 page). */
261 RTHCPHYS pMSRBitmapPhys;
262 /** Virtual address of the MSR bitmap (1 page). */
263 R0PTRTYPE(uint8_t *) pMSRBitmap;
264
265 /** R0 memory object for the MSR entry load page (guest MSRs). */
266 RTR0MEMOBJ pMemObjMSREntryLoad;
267 /** Physical address of the MSR entry load page (guest MSRs). */
268 RTHCPHYS pMSREntryLoadPhys;
269 /** Virtual address of the MSR entry load page (guest MSRs). */
270 R0PTRTYPE(uint8_t *) pMSREntryLoad;
271
272 /** R0 memory object for the MSR exit store page (guest MSRs). */
273 RTR0MEMOBJ pMemObjMSRExitStore;
274 /** Physical address of the MSR exit store page (guest MSRs). */
275 RTHCPHYS pMSRExitStorePhys;
276 /** Virtual address of the MSR exit store page (guest MSRs). */
277 R0PTRTYPE(uint8_t *) pMSRExitStore;
278
279 /** R0 memory object for the MSR exit load page (host MSRs). */
280 RTR0MEMOBJ pMemObjMSRExitLoad;
281 /** Physical address of the MSR exit load page (host MSRs). */
282 RTHCPHYS pMSRExitLoadPhys;
283 /** Virtual address of the MSR exit load page (host MSRs). */
284 R0PTRTYPE(uint8_t *) pMSRExitLoad;
285
286 /** Ring 0 handlers for VT-x. */
287 DECLR0CALLBACKMEMBER(int, pfnStartVM,(RTHCUINT fResume, PCPUMCTX pCtx));
288 DECLR0CALLBACKMEMBER(void, pfnSetupTaggedTLB, (PVM pVM));
289
290#if HC_ARCH_BITS == 32
291 uint32_t Alignment1;
292#endif
293
294 /** Host CR4 value (set by ring-0 VMX init) */
295 uint64_t hostCR4;
296
297 /** Current VMX_VMCS_CTRL_PROC_EXEC_CONTROLS. */
298 uint64_t proc_ctls;
299
300 /** Current CR0 mask. */
301 uint64_t cr0_mask;
302 /** Current CR4 mask. */
303 uint64_t cr4_mask;
304
305 /** Current EPTP. */
306 RTHCPHYS GCPhysEPTP;
307
308 /** VMX MSR values */
309 struct
310 {
311 uint64_t feature_ctrl;
312 uint64_t vmx_basic_info;
313 VMX_CAPABILITY vmx_pin_ctls;
314 VMX_CAPABILITY vmx_proc_ctls;
315 VMX_CAPABILITY vmx_proc_ctls2;
316 VMX_CAPABILITY vmx_exit;
317 VMX_CAPABILITY vmx_entry;
318 uint64_t vmx_misc;
319 uint64_t vmx_cr0_fixed0;
320 uint64_t vmx_cr0_fixed1;
321 uint64_t vmx_cr4_fixed0;
322 uint64_t vmx_cr4_fixed1;
323 uint64_t vmx_vmcs_enum;
324 uint64_t vmx_eptcaps;
325 } msr;
326
327 /* Last instruction error */
328 uint32_t ulLastInstrError;
329
330 /** Current trap mask. */
331 uint32_t u32TrapMask;
332
333 /** The last known guest paging mode. */
334 PGMMODE enmCurrGuestMode;
335
336 /** Flush types for invept & invvpid; they depend on capabilities. */
337 VMX_FLUSH enmFlushPage;
338 VMX_FLUSH enmFlushContext;
339
340 /** Real-mode emulation state. */
341 struct
342 {
343 struct
344 {
345 uint32_t fPending;
346 uint32_t padding4;
347 uint64_t intInfo;
348 } Event;
349
350 CPUMSELREGHID dsHid;
351 CPUMSELREGHID esHid;
352 CPUMSELREGHID fsHid;
353 CPUMSELREGHID gsHid;
354 CPUMSELREGHID ssHid;
355 RTSEL ds;
356 RTSEL es;
357 RTSEL fs;
358 RTSEL gs;
359 RTSEL ss;
360 RTSEL padding5[1];
361 uint32_t eip;
362 X86EFLAGS eflags;
363 uint32_t fValid;
364 } RealMode;
365
366 struct
367 {
368 uint64_t u64VMCSPhys;
369 uint32_t ulVMCSRevision;
370 } lasterror;
371 } vmx;
372
373 struct
374 {
375 /** Set by the ring-0 driver to indicate SVM is supported by the CPU. */
376 bool fSupported;
377 /** Set when we've enabled SVM. */
378 bool fEnabled;
379 /** Set if we don't have to flush the TLB on VM entry. */
380 bool fResumeVM;
381 /** Set if erratum 170 affects the AMD cpu. */
382 bool fAlwaysFlushTLB;
383
384 /** R0 memory object for the VM control block (VMCB). */
385 RTR0MEMOBJ pMemObjVMCB;
386 /** Physical address of the VM control block (VMCB). */
387 RTHCPHYS pVMCBPhys;
388 /** Virtual address of the VM control block (VMCB). */
389 R0PTRTYPE(void *) pVMCB;
390
391 /** R0 memory object for the host VM control block (VMCB). */
392 RTR0MEMOBJ pMemObjVMCBHost;
393 /** Physical address of the host VM control block (VMCB). */
394 RTHCPHYS pVMCBHostPhys;
395 /** Virtual address of the host VM control block (VMCB). */
396 R0PTRTYPE(void *) pVMCBHost;
397
398 /** R0 memory object for the IO bitmap (12kb). */
399 RTR0MEMOBJ pMemObjIOBitmap;
400 /** Physical address of the IO bitmap (12kb). */
401 RTHCPHYS pIOBitmapPhys;
402 /** Virtual address of the IO bitmap. */
403 R0PTRTYPE(void *) pIOBitmap;
404
405 /** R0 memory object for the MSR bitmap (8kb). */
406 RTR0MEMOBJ pMemObjMSRBitmap;
407 /** Physical address of the MSR bitmap (8kb). */
408 RTHCPHYS pMSRBitmapPhys;
409 /** Virtual address of the MSR bitmap. */
410 R0PTRTYPE(void *) pMSRBitmap;
411
412 /** Ring 0 handlers for VT-x. */
413 DECLR0CALLBACKMEMBER(int, pfnVMRun,(RTHCPHYS pVMCBHostPhys, RTHCPHYS pVMCBPhys, PCPUMCTX pCtx));
414
415 /** SVM revision. */
416 uint32_t u32Rev;
417
418 /** SVM feature bits from cpuid 0x8000000a */
419 uint32_t u32Features;
420 } svm;
421
422 struct
423 {
424 uint32_t u32AMDFeatureECX;
425 uint32_t u32AMDFeatureEDX;
426 } cpuid;
427
428 /** Event injection state. */
429 struct
430 {
431 uint32_t fPending;
432 uint32_t errCode;
433 uint64_t intInfo;
434 } Event;
435
436 /** Saved error from detection */
437 int32_t lLastError;
438
439 /** HWACCMR0Init was run */
440 bool fHWACCMR0Init;
441
442 /** Currenty shadow paging mode. */
443 PGMMODE enmShadowMode;
444
445 /** Explicit alignment padding of StatEntry (32-bit g++ again). */
446 int32_t padding2;
447
448#ifdef VBOX_STRICT
449 /** The CPU ID of the CPU currently owning the VMCS. Set in
450 * HWACCMR0Enter and cleared in HWACCMR0Leave. */
451 RTCPUID idEnteredCpu;
452# if HC_ARCH_BITS == 32
453 RTCPUID Alignment0;
454# endif
455#endif
456
457 STAMPROFILEADV StatEntry;
458 STAMPROFILEADV StatExit;
459 STAMPROFILEADV StatInGC;
460
461 STAMCOUNTER StatIntInject;
462
463 STAMCOUNTER StatExitShadowNM;
464 STAMCOUNTER StatExitGuestNM;
465 STAMCOUNTER StatExitShadowPF;
466 STAMCOUNTER StatExitGuestPF;
467 STAMCOUNTER StatExitGuestUD;
468 STAMCOUNTER StatExitGuestSS;
469 STAMCOUNTER StatExitGuestNP;
470 STAMCOUNTER StatExitGuestGP;
471 STAMCOUNTER StatExitGuestDE;
472 STAMCOUNTER StatExitGuestDB;
473 STAMCOUNTER StatExitGuestMF;
474 STAMCOUNTER StatExitInvpg;
475 STAMCOUNTER StatExitInvd;
476 STAMCOUNTER StatExitCpuid;
477 STAMCOUNTER StatExitRdtsc;
478 STAMCOUNTER StatExitCRxWrite;
479 STAMCOUNTER StatExitCRxRead;
480 STAMCOUNTER StatExitDRxWrite;
481 STAMCOUNTER StatExitDRxRead;
482 STAMCOUNTER StatExitCLTS;
483 STAMCOUNTER StatExitLMSW;
484 STAMCOUNTER StatExitIOWrite;
485 STAMCOUNTER StatExitIORead;
486 STAMCOUNTER StatExitIOStringWrite;
487 STAMCOUNTER StatExitIOStringRead;
488 STAMCOUNTER StatExitIrqWindow;
489 STAMCOUNTER StatExitMaxResume;
490 STAMCOUNTER StatIntReinject;
491 STAMCOUNTER StatPendingHostIrq;
492
493 STAMCOUNTER StatFlushPageManual;
494 STAMCOUNTER StatFlushPhysPageManual;
495 STAMCOUNTER StatFlushTLBManual;
496 STAMCOUNTER StatFlushPageInvlpg;
497 STAMCOUNTER StatFlushTLBWorldSwitch;
498 STAMCOUNTER StatNoFlushTLBWorldSwitch;
499 STAMCOUNTER StatFlushTLBCRxChange;
500 STAMCOUNTER StatFlushASID;
501 STAMCOUNTER StatFlushTLBInvlpga;
502
503 STAMCOUNTER StatSwitchGuestIrq;
504 STAMCOUNTER StatSwitchToR3;
505
506 STAMCOUNTER StatTSCOffset;
507 STAMCOUNTER StatTSCIntercept;
508
509 STAMCOUNTER StatExitReasonNPF;
510 STAMCOUNTER StatDRxArmed;
511 STAMCOUNTER StatDRxContextSwitch;
512 STAMCOUNTER StatDRxIOCheck;
513
514
515 R3PTRTYPE(PSTAMCOUNTER) paStatExitReason;
516 R0PTRTYPE(PSTAMCOUNTER) paStatExitReasonR0;
517} HWACCM;
518/** Pointer to HWACCM VM instance data. */
519typedef HWACCM *PHWACCM;
520
521#ifdef IN_RING0
522
523VMMR0DECL(PHWACCM_CPUINFO) HWACCMR0GetCurrentCpu();
524
525#ifdef VBOX_STRICT
526VMMR0DECL(void) HWACCMDumpRegs(PVM pVM, PCPUMCTX pCtx);
527VMMR0DECL(void) HWACCMR0DumpDescriptor(PX86DESCHC Desc, RTSEL Sel, const char *pszMsg);
528#else
529#define HWACCMDumpRegs(a, b) do { } while (0)
530#define HWACCMR0DumpDescriptor(a, b, c) do { } while (0)
531#endif
532
533/* Dummy callback handlers. */
534VMMR0DECL(int) HWACCMR0DummyEnter(PVM pVM, PHWACCM_CPUINFO pCpu);
535VMMR0DECL(int) HWACCMR0DummyLeave(PVM pVM, CPUMCTX *pCtx);
536VMMR0DECL(int) HWACCMR0DummyEnableCpu(PHWACCM_CPUINFO pCpu, PVM pVM, void *pvPageCpu, RTHCPHYS pPageCpuPhys);
537VMMR0DECL(int) HWACCMR0DummyDisableCpu(PHWACCM_CPUINFO pCpu, void *pvPageCpu, RTHCPHYS pPageCpuPhys);
538VMMR0DECL(int) HWACCMR0DummyInitVM(PVM pVM);
539VMMR0DECL(int) HWACCMR0DummyTermVM(PVM pVM);
540VMMR0DECL(int) HWACCMR0DummySetupVM(PVM pVM);
541VMMR0DECL(int) HWACCMR0DummyRunGuestCode(PVM pVM, CPUMCTX *pCtx);
542VMMR0DECL(int) HWACCMR0DummySaveHostState(PVM pVM);
543VMMR0DECL(int) HWACCMR0DummyLoadGuestState(PVM pVM, CPUMCTX *pCtx);
544
545#endif /* IN_RING0 */
546
547/** @} */
548
549__END_DECLS
550
551#endif
552
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