HWACCMInternal.h@ 13333

Last change on this file since 13333 was 13276, checked in by vboxsync, 16 years ago
Manually inject interrupts in real mode (VT-x). Fixes OS/2 boot issue.
Property svn:eol-style set to `native` Property svn:keywords set to `Id`
File size: 20.6 KB

Line
1	/* $Id: HWACCMInternal.h 13276 2008-10-15 09:57:45Z vboxsync $ */
2	/** @file
3	* HWACCM - Internal header file.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22	#ifndef ___HWACCMInternal_h
23	#define ___HWACCMInternal_h
24
25	#include <VBox/cdefs.h>
26	#include <VBox/types.h>
27	#include <VBox/em.h>
28	#include <VBox/stam.h>
29	#include <VBox/dis.h>
30	#include <VBox/hwaccm.h>
31	#include <VBox/pgm.h>
32	#include <VBox/cpum.h>
33	#include <iprt/memobj.h>
34	#include <iprt/cpuset.h>
35	#include <iprt/mp.h>
36
37	#if HC_ARCH_BITS == 64
38	/* Enable 64 bits guest support. */
39	# define VBOX_ENABLE_64_BITS_GUESTS
40	#endif
41
42	#define HWACCM_VMX_EMULATE_REALMODE
43	#define HWACCM_VTX_WITH_EPT
44	#define HWACCM_VTX_WITH_VPID
45
46	__BEGIN_DECLS
47
48
49	/** @defgroup grp_hwaccm_int Internal
50	* @ingroup grp_hwaccm
51	* @internal
52	* @{
53	*/
54
55
56	/**
57	* Converts a HWACCM pointer into a VM pointer.
58	* @returns Pointer to the VM structure the EM is part of.
59	* @param pHWACCM Pointer to HWACCM instance data.
60	*/
61	#define HWACCM2VM(pHWACCM) ( (PVM)((char*)pHWACCM - pHWACCM->offVM) )
62
63	/** Maximum number of exit reason statistics counters. */
64	#define MAX_EXITREASON_STAT 0x100
65	#define MASK_EXITREASON_STAT 0xff
66
67	/** @name Changed flags
68	* These flags are used to keep track of which important registers that
69	* have been changed since last they were reset.
70	* @{
71	*/
72	#define HWACCM_CHANGED_GUEST_FPU RT_BIT(0)
73	#define HWACCM_CHANGED_GUEST_CR0 RT_BIT(1)
74	#define HWACCM_CHANGED_GUEST_CR3 RT_BIT(2)
75	#define HWACCM_CHANGED_GUEST_CR4 RT_BIT(3)
76	#define HWACCM_CHANGED_GUEST_GDTR RT_BIT(4)
77	#define HWACCM_CHANGED_GUEST_IDTR RT_BIT(5)
78	#define HWACCM_CHANGED_GUEST_LDTR RT_BIT(6)
79	#define HWACCM_CHANGED_GUEST_TR RT_BIT(7)
80	#define HWACCM_CHANGED_GUEST_SYSENTER_MSR RT_BIT(8)
81	#define HWACCM_CHANGED_GUEST_SEGMENT_REGS RT_BIT(9)
82	#define HWACCM_CHANGED_GUEST_DEBUG RT_BIT(10)
83	#define HWACCM_CHANGED_HOST_CONTEXT RT_BIT(11)
84
85	#define HWACCM_CHANGED_ALL ( HWACCM_CHANGED_GUEST_SEGMENT_REGS \
86	\| HWACCM_CHANGED_GUEST_CR0 \
87	\| HWACCM_CHANGED_GUEST_CR3 \
88	\| HWACCM_CHANGED_GUEST_CR4 \
89	\| HWACCM_CHANGED_GUEST_GDTR \
90	\| HWACCM_CHANGED_GUEST_IDTR \
91	\| HWACCM_CHANGED_GUEST_LDTR \
92	\| HWACCM_CHANGED_GUEST_TR \
93	\| HWACCM_CHANGED_GUEST_SYSENTER_MSR \
94	\| HWACCM_CHANGED_GUEST_FPU \
95	\| HWACCM_CHANGED_GUEST_DEBUG \
96	\| HWACCM_CHANGED_HOST_CONTEXT)
97
98	#define HWACCM_CHANGED_ALL_GUEST ( HWACCM_CHANGED_GUEST_SEGMENT_REGS \
99	\| HWACCM_CHANGED_GUEST_CR0 \
100	\| HWACCM_CHANGED_GUEST_CR3 \
101	\| HWACCM_CHANGED_GUEST_CR4 \
102	\| HWACCM_CHANGED_GUEST_GDTR \
103	\| HWACCM_CHANGED_GUEST_IDTR \
104	\| HWACCM_CHANGED_GUEST_LDTR \
105	\| HWACCM_CHANGED_GUEST_TR \
106	\| HWACCM_CHANGED_GUEST_SYSENTER_MSR \
107	\| HWACCM_CHANGED_GUEST_DEBUG \
108	\| HWACCM_CHANGED_GUEST_FPU)
109
110	/** @} */
111
112	/** @name Intercepted traps
113	* Traps that need to be intercepted so we can correctly dispatch them to the guest if required.
114	* Currently #NM and #PF only
115	*/
116	#ifdef VBOX_STRICT
117	#define HWACCM_VMX_TRAP_MASK RT_BIT(X86_XCPT_DE) \| RT_BIT(X86_XCPT_NM) \| RT_BIT(X86_XCPT_PF) \| RT_BIT(X86_XCPT_UD) \| RT_BIT(X86_XCPT_NP) \| RT_BIT(X86_XCPT_SS) \| RT_BIT(X86_XCPT_GP) \| RT_BIT(X86_XCPT_MF)
118	#define HWACCM_SVM_TRAP_MASK HWACCM_VMX_TRAP_MASK
119	#else
120	#define HWACCM_VMX_TRAP_MASK RT_BIT(X86_XCPT_NM) \| RT_BIT(X86_XCPT_PF)
121	#define HWACCM_SVM_TRAP_MASK RT_BIT(X86_XCPT_NM) \| RT_BIT(X86_XCPT_PF)
122	#endif
123	/* All exceptions have to be intercept in emulated real-mode (minues NM & PF as they are always intercepted. */
124	#define HWACCM_VMX_TRAP_MASK_REALMODE RT_BIT(X86_XCPT_DE) \| RT_BIT(X86_XCPT_DB) \| RT_BIT(X86_XCPT_NMI) \| RT_BIT(X86_XCPT_BP) \| RT_BIT(X86_XCPT_OF) \| RT_BIT(X86_XCPT_BR) \| RT_BIT(X86_XCPT_UD) \| RT_BIT(X86_XCPT_DF) \| RT_BIT(X86_XCPT_CO_SEG_OVERRUN) \| RT_BIT(X86_XCPT_TS) \| RT_BIT(X86_XCPT_NP) \| RT_BIT(X86_XCPT_SS) \| RT_BIT(X86_XCPT_GP) \| RT_BIT(X86_XCPT_MF) \| RT_BIT(X86_XCPT_AC) \| RT_BIT(X86_XCPT_MC) \| RT_BIT(X86_XCPT_XF)
125	/** @} */
126
127
128	/** Maxium resume loops allowed in ring 0 (safety precaution) */
129	#define HWACCM_MAX_RESUME_LOOPS 1024
130
131	/** Size for the EPT identity page table (1024 4 MB pages to cover the entire address space). */
132	#define HWACCM_EPT_IDENTITY_PG_TABLE_SIZE PAGE_SIZE
133	/** Size of the TSS structure + 2 pages for the IO bitmap + end byte. */
134	#define HWACCM_VTX_TSS_SIZE (sizeof(VBOXTSS) + 2*PAGE_SIZE + 1)
135	/** Total guest mapped memory needed. */
136	#define HWACCM_VTX_TOTAL_DEVHEAP_MEM (HWACCM_EPT_IDENTITY_PG_TABLE_SIZE + HWACCM_VTX_TSS_SIZE)
137
138	/** HWACCM SSM version
139	*/
140	#define HWACCM_SSM_VERSION 3
141
142	/* Per-cpu information. */
143	typedef struct
144	{
145	RTCPUID idCpu;
146
147	RTR0MEMOBJ pMemObj;
148	/* Current ASID (AMD-V)/VPID (Intel) */
149	uint32_t uCurrentASID;
150	/* TLB flush count */
151	uint32_t cTLBFlushes;
152
153	/* Set the first time a cpu is used to make sure we start with a clean TLB. */
154	bool fFlushTLB;
155
156	bool fConfigured;
157	} HWACCM_CPUINFO;
158	typedef HWACCM_CPUINFO *PHWACCM_CPUINFO;
159
160	/* VT-x capability qword. */
161	typedef union
162	{
163	struct
164	{
165	uint32_t disallowed0;
166	uint32_t allowed1;
167	} n;
168	uint64_t u;
169	} VMX_CAPABILITY;
170
171	/**
172	* HWACCM VM Instance data.
173	* Changes to this must checked against the padding of the cfgm union in VM!
174	*/
175	typedef struct HWACCM
176	{
177	/** Offset to the VM structure.
178	* See HWACCM2VM(). */
179	RTUINT offVM;
180
181	/** Set when we've initialized VMX or SVM. */
182	bool fInitialized;
183	/** Set when we're using VMX/SVN at that moment. */
184	bool fActive;
185
186	/** Set when hardware acceleration is allowed. */
187	bool fAllowed;
188
189	/** Set if nested paging is enabled. */
190	bool fNestedPaging;
191
192	/** Set if nested paging is allowed. */
193	bool fAllowNestedPaging;
194	/** Set if VT-x VPID is allowed. */
195	bool fAllowVPID;
196
197	/** Set if we need to flush the TLB during the world switch. */
198	bool fForceTLBFlush;
199
200	/** Old style FPU reporting trap mask override performed (optimization) */
201	bool fFPUOldStyleOverride;
202
203	#if 0
204	/** Explicit alignment padding to make 32-bit gcc align u64RegisterMask
205	* naturally. */
206	bool padding[1];
207	#endif
208
209	/** HWACCM_CHANGED_* flags. */
210	RTUINT fContextUseFlags;
211
212	/* Id of the last cpu we were executing code on (NIL_RTCPUID for the first time) */
213	RTCPUID idLastCpu;
214
215	/* TLB flush count */
216	RTUINT cTLBFlushes;
217
218	/* Current ASID in use by the VM */
219	RTUINT uCurrentASID;
220
221	/** Maximum ASID allowed. */
222	RTUINT uMaxASID;
223
224	/** And mask for copying register contents. */
225	uint64_t u64RegisterMask;
226	struct
227	{
228	/** Set by the ring-0 driver to indicate VMX is supported by the CPU. */
229	bool fSupported;
230
231	/** Set when we've enabled VMX. */
232	bool fEnabled;
233
234	/** Set if we can use VMXResume to execute guest code. */
235	bool fResumeVM;
236
237	/** Set if VPID is supported. */
238	bool fVPID;
239
240	/** R0 memory object for the VM control structure (VMCS). */
241	RTR0MEMOBJ pMemObjVMCS;
242	/** Physical address of the VM control structure (VMCS). */
243	RTHCPHYS pVMCSPhys;
244	/** Virtual address of the VM control structure (VMCS). */
245	R0PTRTYPE(void *) pVMCS;
246
247	/** Virtual address of the TSS page used for real mode emulation. */
248	R3PTRTYPE(PVBOXTSS) pRealModeTSS;
249
250	/** Virtual address of the identity page table used for real mode and protected mode without paging emulation in EPT mode. */
251	R3PTRTYPE(PX86PD) pNonPagingModeEPTPageTable;
252
253	/** R0 memory object for the virtual APIC mmio cache. */
254	RTR0MEMOBJ pMemObjAPIC;
255	/** Physical address of the virtual APIC mmio cache. */
256	RTHCPHYS pAPICPhys;
257	/** Virtual address of the virtual APIC mmio cache. */
258	R0PTRTYPE(uint8_t *) pAPIC;
259
260	/** R0 memory object for the MSR bitmap (1 page). */
261	RTR0MEMOBJ pMemObjMSRBitmap;
262	/** Physical address of the MSR bitmap (1 page). */
263	RTHCPHYS pMSRBitmapPhys;
264	/** Virtual address of the MSR bitmap (1 page). */
265	R0PTRTYPE(uint8_t *) pMSRBitmap;
266
267	/** R0 memory object for the MSR entry load page (guest MSRs). */
268	RTR0MEMOBJ pMemObjMSREntryLoad;
269	/** Physical address of the MSR entry load page (guest MSRs). */
270	RTHCPHYS pMSREntryLoadPhys;
271	/** Virtual address of the MSR entry load page (guest MSRs). */
272	R0PTRTYPE(uint8_t *) pMSREntryLoad;
273
274	/** R0 memory object for the MSR exit store page (guest MSRs). */
275	RTR0MEMOBJ pMemObjMSRExitStore;
276	/** Physical address of the MSR exit store page (guest MSRs). */
277	RTHCPHYS pMSRExitStorePhys;
278	/** Virtual address of the MSR exit store page (guest MSRs). */
279	R0PTRTYPE(uint8_t *) pMSRExitStore;
280
281	/** R0 memory object for the MSR exit load page (host MSRs). */
282	RTR0MEMOBJ pMemObjMSRExitLoad;
283	/** Physical address of the MSR exit load page (host MSRs). */
284	RTHCPHYS pMSRExitLoadPhys;
285	/** Virtual address of the MSR exit load page (host MSRs). */
286	R0PTRTYPE(uint8_t *) pMSRExitLoad;
287
288	/** Ring 0 handlers for VT-x. */
289	DECLR0CALLBACKMEMBER(int, pfnStartVM,(RTHCUINT fResume, PCPUMCTX pCtx));
290	DECLR0CALLBACKMEMBER(void, pfnSetupTaggedTLB, (PVM pVM));
291
292	#if HC_ARCH_BITS == 32
293	uint32_t Alignment1;
294	#endif
295
296	/** Host CR4 value (set by ring-0 VMX init) */
297	uint64_t hostCR4;
298
299	/** Current VMX_VMCS_CTRL_PROC_EXEC_CONTROLS. */
300	uint64_t proc_ctls;
301
302	/** Current CR0 mask. */
303	uint64_t cr0_mask;
304	/** Current CR4 mask. */
305	uint64_t cr4_mask;
306
307	/** Current EPTP. */
308	RTHCPHYS GCPhysEPTP;
309
310	/** VMX MSR values */
311	struct
312	{
313	uint64_t feature_ctrl;
314	uint64_t vmx_basic_info;
315	VMX_CAPABILITY vmx_pin_ctls;
316	VMX_CAPABILITY vmx_proc_ctls;
317	VMX_CAPABILITY vmx_proc_ctls2;
318	VMX_CAPABILITY vmx_exit;
319	VMX_CAPABILITY vmx_entry;
320	uint64_t vmx_misc;
321	uint64_t vmx_cr0_fixed0;
322	uint64_t vmx_cr0_fixed1;
323	uint64_t vmx_cr4_fixed0;
324	uint64_t vmx_cr4_fixed1;
325	uint64_t vmx_vmcs_enum;
326	uint64_t vmx_eptcaps;
327	} msr;
328
329	/* Last instruction error */
330	uint32_t ulLastInstrError;
331
332	/** The last known guest paging mode. */
333	PGMMODE enmCurrGuestMode;
334
335	/** Flush types for invept & invvpid; they depend on capabilities. */
336	VMX_FLUSH enmFlushPage;
337	VMX_FLUSH enmFlushContext;
338
339	/** Real-mode emulation state. */
340	struct
341	{
342	CPUMSELREGHID dsHid;
343	CPUMSELREGHID esHid;
344	CPUMSELREGHID fsHid;
345	CPUMSELREGHID gsHid;
346	CPUMSELREGHID ssHid;
347	RTSEL ds;
348	RTSEL es;
349	RTSEL fs;
350	RTSEL gs;
351	RTSEL ss;
352	RTSEL padding5[1];
353	X86EFLAGS eflags;
354	uint32_t fValid;
355	} RealMode;
356
357	struct
358	{
359	uint64_t u64VMCSPhys;
360	uint32_t ulVMCSRevision;
361	} lasterror;
362	} vmx;
363
364	struct
365	{
366	/** Set by the ring-0 driver to indicate SVM is supported by the CPU. */
367	bool fSupported;
368	/** Set when we've enabled SVM. */
369	bool fEnabled;
370	/** Set if we don't have to flush the TLB on VM entry. */
371	bool fResumeVM;
372	/** Set if erratum 170 affects the AMD cpu. */
373	bool fAlwaysFlushTLB;
374
375	/** R0 memory object for the VM control block (VMCB). */
376	RTR0MEMOBJ pMemObjVMCB;
377	/** Physical address of the VM control block (VMCB). */
378	RTHCPHYS pVMCBPhys;
379	/** Virtual address of the VM control block (VMCB). */
380	R0PTRTYPE(void *) pVMCB;
381
382	/** R0 memory object for the host VM control block (VMCB). */
383	RTR0MEMOBJ pMemObjVMCBHost;
384	/** Physical address of the host VM control block (VMCB). */
385	RTHCPHYS pVMCBHostPhys;
386	/** Virtual address of the host VM control block (VMCB). */
387	R0PTRTYPE(void *) pVMCBHost;
388
389	/** R0 memory object for the IO bitmap (12kb). */
390	RTR0MEMOBJ pMemObjIOBitmap;
391	/** Physical address of the IO bitmap (12kb). */
392	RTHCPHYS pIOBitmapPhys;
393	/** Virtual address of the IO bitmap. */
394	R0PTRTYPE(void *) pIOBitmap;
395
396	/** R0 memory object for the MSR bitmap (8kb). */
397	RTR0MEMOBJ pMemObjMSRBitmap;
398	/** Physical address of the MSR bitmap (8kb). */
399	RTHCPHYS pMSRBitmapPhys;
400	/** Virtual address of the MSR bitmap. */
401	R0PTRTYPE(void *) pMSRBitmap;
402
403	/** Ring 0 handlers for VT-x. */
404	DECLR0CALLBACKMEMBER(int, pfnVMRun,(RTHCPHYS pVMCBHostPhys, RTHCPHYS pVMCBPhys, PCPUMCTX pCtx));
405
406	/** SVM revision. */
407	uint32_t u32Rev;
408
409	/** SVM feature bits from cpuid 0x8000000a */
410	uint32_t u32Features;
411	} svm;
412
413	struct
414	{
415	uint32_t u32AMDFeatureECX;
416	uint32_t u32AMDFeatureEDX;
417	} cpuid;
418
419	/** Event injection state. */
420	struct
421	{
422	uint32_t fPending;
423	uint32_t errCode;
424	uint64_t intInfo;
425	} Event;
426
427	/** Saved error from detection */
428	int32_t lLastError;
429
430	/** HWACCMR0Init was run */
431	bool fHWACCMR0Init;
432
433	/** Currenty shadow paging mode. */
434	PGMMODE enmShadowMode;
435
436	/** Explicit alignment padding of StatEntry (32-bit g++ again). */
437	int32_t padding2;
438
439	#ifdef VBOX_STRICT
440	/** The CPU ID of the CPU currently owning the VMCS. Set in
441	* HWACCMR0Enter and cleared in HWACCMR0Leave. */
442	RTCPUID idEnteredCpu;
443	# if HC_ARCH_BITS == 32
444	RTCPUID Alignment0;
445	# endif
446	#endif
447
448	STAMPROFILEADV StatEntry;
449	STAMPROFILEADV StatExit;
450	STAMPROFILEADV StatInGC;
451
452	STAMCOUNTER StatIntInject;
453
454	STAMCOUNTER StatExitShadowNM;
455	STAMCOUNTER StatExitGuestNM;
456	STAMCOUNTER StatExitShadowPF;
457	STAMCOUNTER StatExitGuestPF;
458	STAMCOUNTER StatExitGuestUD;
459	STAMCOUNTER StatExitGuestSS;
460	STAMCOUNTER StatExitGuestNP;
461	STAMCOUNTER StatExitGuestGP;
462	STAMCOUNTER StatExitGuestDE;
463	STAMCOUNTER StatExitGuestDB;
464	STAMCOUNTER StatExitGuestMF;
465	STAMCOUNTER StatExitInvpg;
466	STAMCOUNTER StatExitInvd;
467	STAMCOUNTER StatExitCpuid;
468	STAMCOUNTER StatExitRdtsc;
469	STAMCOUNTER StatExitCRxWrite;
470	STAMCOUNTER StatExitCRxRead;
471	STAMCOUNTER StatExitDRxWrite;
472	STAMCOUNTER StatExitDRxRead;
473	STAMCOUNTER StatExitCLTS;
474	STAMCOUNTER StatExitLMSW;
475	STAMCOUNTER StatExitIOWrite;
476	STAMCOUNTER StatExitIORead;
477	STAMCOUNTER StatExitIOStringWrite;
478	STAMCOUNTER StatExitIOStringRead;
479	STAMCOUNTER StatExitIrqWindow;
480	STAMCOUNTER StatExitMaxResume;
481	STAMCOUNTER StatIntReinject;
482	STAMCOUNTER StatPendingHostIrq;
483
484	STAMCOUNTER StatFlushPageManual;
485	STAMCOUNTER StatFlushPhysPageManual;
486	STAMCOUNTER StatFlushTLBManual;
487	STAMCOUNTER StatFlushPageInvlpg;
488	STAMCOUNTER StatFlushTLBWorldSwitch;
489	STAMCOUNTER StatNoFlushTLBWorldSwitch;
490	STAMCOUNTER StatFlushTLBCRxChange;
491	STAMCOUNTER StatFlushASID;
492	STAMCOUNTER StatFlushTLBInvlpga;
493
494	STAMCOUNTER StatSwitchGuestIrq;
495	STAMCOUNTER StatSwitchToR3;
496
497	STAMCOUNTER StatTSCOffset;
498	STAMCOUNTER StatTSCIntercept;
499
500	STAMCOUNTER StatExitReasonNPF;
501	STAMCOUNTER StatDRxArmed;
502	STAMCOUNTER StatDRxContextSwitch;
503	STAMCOUNTER StatDRxIOCheck;
504
505
506	R3PTRTYPE(PSTAMCOUNTER) paStatExitReason;
507	R0PTRTYPE(PSTAMCOUNTER) paStatExitReasonR0;
508	} HWACCM;
509	/** Pointer to HWACCM VM instance data. */
510	typedef HWACCM *PHWACCM;
511
512	#ifdef IN_RING0
513
514	VMMR0DECL(PHWACCM_CPUINFO) HWACCMR0GetCurrentCpu();
515
516	#ifdef VBOX_STRICT
517	VMMR0DECL(void) HWACCMDumpRegs(PVM pVM, PCPUMCTX pCtx);
518	VMMR0DECL(void) HWACCMR0DumpDescriptor(PX86DESCHC Desc, RTSEL Sel, const char *pszMsg);
519	#else
520	#define HWACCMDumpRegs(a, b) do { } while (0)
521	#define HWACCMR0DumpDescriptor(a, b, c) do { } while (0)
522	#endif
523
524	/* Dummy callback handlers. */
525	VMMR0DECL(int) HWACCMR0DummyEnter(PVM pVM, PHWACCM_CPUINFO pCpu);
526	VMMR0DECL(int) HWACCMR0DummyLeave(PVM pVM, CPUMCTX *pCtx);
527	VMMR0DECL(int) HWACCMR0DummyEnableCpu(PHWACCM_CPUINFO pCpu, PVM pVM, void *pvPageCpu, RTHCPHYS pPageCpuPhys);
528	VMMR0DECL(int) HWACCMR0DummyDisableCpu(PHWACCM_CPUINFO pCpu, void *pvPageCpu, RTHCPHYS pPageCpuPhys);
529	VMMR0DECL(int) HWACCMR0DummyInitVM(PVM pVM);
530	VMMR0DECL(int) HWACCMR0DummyTermVM(PVM pVM);
531	VMMR0DECL(int) HWACCMR0DummySetupVM(PVM pVM);
532	VMMR0DECL(int) HWACCMR0DummyRunGuestCode(PVM pVM, CPUMCTX *pCtx);
533	VMMR0DECL(int) HWACCMR0DummySaveHostState(PVM pVM);
534	VMMR0DECL(int) HWACCMR0DummyLoadGuestState(PVM pVM, CPUMCTX *pCtx);
535
536	#endif /* IN_RING0 */
537
538	/** @} */
539
540	__END_DECLS
541
542	#endif
543

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source: vbox/trunk/src/VBox/VMM/HWACCMInternal.h@ 13333

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