HWACCMInternal.h@ 13749

Last change on this file since 13749 was 13749, checked in by vboxsync, 16 years ago
Some cleanup & updates
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1	/* $Id: HWACCMInternal.h 13749 2008-11-03 14:30:40Z vboxsync $ */
2	/** @file
3	* HWACCM - Internal header file.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22	#ifndef ___HWACCMInternal_h
23	#define ___HWACCMInternal_h
24
25	#include <VBox/cdefs.h>
26	#include <VBox/types.h>
27	#include <VBox/em.h>
28	#include <VBox/stam.h>
29	#include <VBox/dis.h>
30	#include <VBox/hwaccm.h>
31	#include <VBox/pgm.h>
32	#include <VBox/cpum.h>
33	#include <iprt/memobj.h>
34	#include <iprt/cpuset.h>
35	#include <iprt/mp.h>
36
37	#if HC_ARCH_BITS == 64
38	/* Enable 64 bits guest support. */
39	# define VBOX_ENABLE_64_BITS_GUESTS
40	#endif
41
42	#define HWACCM_VMX_EMULATE_REALMODE
43	#define HWACCM_VTX_WITH_EPT
44	#define HWACCM_VTX_WITH_VPID
45
46	__BEGIN_DECLS
47
48
49	/** @defgroup grp_hwaccm_int Internal
50	* @ingroup grp_hwaccm
51	* @internal
52	* @{
53	*/
54
55
56	/** Maximum number of exit reason statistics counters. */
57	#define MAX_EXITREASON_STAT 0x100
58	#define MASK_EXITREASON_STAT 0xff
59
60	/** @name Changed flags
61	* These flags are used to keep track of which important registers that
62	* have been changed since last they were reset.
63	* @{
64	*/
65	#define HWACCM_CHANGED_GUEST_FPU RT_BIT(0)
66	#define HWACCM_CHANGED_GUEST_CR0 RT_BIT(1)
67	#define HWACCM_CHANGED_GUEST_CR3 RT_BIT(2)
68	#define HWACCM_CHANGED_GUEST_CR4 RT_BIT(3)
69	#define HWACCM_CHANGED_GUEST_GDTR RT_BIT(4)
70	#define HWACCM_CHANGED_GUEST_IDTR RT_BIT(5)
71	#define HWACCM_CHANGED_GUEST_LDTR RT_BIT(6)
72	#define HWACCM_CHANGED_GUEST_TR RT_BIT(7)
73	#define HWACCM_CHANGED_GUEST_SYSENTER_MSR RT_BIT(8)
74	#define HWACCM_CHANGED_GUEST_SEGMENT_REGS RT_BIT(9)
75	#define HWACCM_CHANGED_GUEST_DEBUG RT_BIT(10)
76	#define HWACCM_CHANGED_HOST_CONTEXT RT_BIT(11)
77
78	#define HWACCM_CHANGED_ALL ( HWACCM_CHANGED_GUEST_SEGMENT_REGS \
79	\| HWACCM_CHANGED_GUEST_CR0 \
80	\| HWACCM_CHANGED_GUEST_CR3 \
81	\| HWACCM_CHANGED_GUEST_CR4 \
82	\| HWACCM_CHANGED_GUEST_GDTR \
83	\| HWACCM_CHANGED_GUEST_IDTR \
84	\| HWACCM_CHANGED_GUEST_LDTR \
85	\| HWACCM_CHANGED_GUEST_TR \
86	\| HWACCM_CHANGED_GUEST_SYSENTER_MSR \
87	\| HWACCM_CHANGED_GUEST_FPU \
88	\| HWACCM_CHANGED_GUEST_DEBUG \
89	\| HWACCM_CHANGED_HOST_CONTEXT)
90
91	#define HWACCM_CHANGED_ALL_GUEST ( HWACCM_CHANGED_GUEST_SEGMENT_REGS \
92	\| HWACCM_CHANGED_GUEST_CR0 \
93	\| HWACCM_CHANGED_GUEST_CR3 \
94	\| HWACCM_CHANGED_GUEST_CR4 \
95	\| HWACCM_CHANGED_GUEST_GDTR \
96	\| HWACCM_CHANGED_GUEST_IDTR \
97	\| HWACCM_CHANGED_GUEST_LDTR \
98	\| HWACCM_CHANGED_GUEST_TR \
99	\| HWACCM_CHANGED_GUEST_SYSENTER_MSR \
100	\| HWACCM_CHANGED_GUEST_DEBUG \
101	\| HWACCM_CHANGED_GUEST_FPU)
102
103	/** @} */
104
105	/** @name Intercepted traps
106	* Traps that need to be intercepted so we can correctly dispatch them to the guest if required.
107	* Currently #NM and #PF only
108	*/
109	#ifdef VBOX_STRICT
110	#define HWACCM_VMX_TRAP_MASK RT_BIT(X86_XCPT_DE) \| RT_BIT(X86_XCPT_NM) \| RT_BIT(X86_XCPT_PF) \| RT_BIT(X86_XCPT_UD) \| RT_BIT(X86_XCPT_NP) \| RT_BIT(X86_XCPT_SS) \| RT_BIT(X86_XCPT_GP) \| RT_BIT(X86_XCPT_MF)
111	#define HWACCM_SVM_TRAP_MASK HWACCM_VMX_TRAP_MASK
112	#else
113	#define HWACCM_VMX_TRAP_MASK RT_BIT(X86_XCPT_NM) \| RT_BIT(X86_XCPT_PF)
114	#define HWACCM_SVM_TRAP_MASK RT_BIT(X86_XCPT_NM) \| RT_BIT(X86_XCPT_PF)
115	#endif
116	/* All exceptions have to be intercept in emulated real-mode (minues NM & PF as they are always intercepted. */
117	#define HWACCM_VMX_TRAP_MASK_REALMODE RT_BIT(X86_XCPT_DE) \| RT_BIT(X86_XCPT_DB) \| RT_BIT(X86_XCPT_NMI) \| RT_BIT(X86_XCPT_BP) \| RT_BIT(X86_XCPT_OF) \| RT_BIT(X86_XCPT_BR) \| RT_BIT(X86_XCPT_UD) \| RT_BIT(X86_XCPT_DF) \| RT_BIT(X86_XCPT_CO_SEG_OVERRUN) \| RT_BIT(X86_XCPT_TS) \| RT_BIT(X86_XCPT_NP) \| RT_BIT(X86_XCPT_SS) \| RT_BIT(X86_XCPT_GP) \| RT_BIT(X86_XCPT_MF) \| RT_BIT(X86_XCPT_AC) \| RT_BIT(X86_XCPT_MC) \| RT_BIT(X86_XCPT_XF)
118	/** @} */
119
120
121	/** Maxium resume loops allowed in ring 0 (safety precaution) */
122	#define HWACCM_MAX_RESUME_LOOPS 1024
123
124	/** Size for the EPT identity page table (1024 4 MB pages to cover the entire address space). */
125	#define HWACCM_EPT_IDENTITY_PG_TABLE_SIZE PAGE_SIZE
126	/** Size of the TSS structure + 2 pages for the IO bitmap + end byte. */
127	#define HWACCM_VTX_TSS_SIZE (sizeof(VBOXTSS) + 2*PAGE_SIZE + 1)
128	/** Total guest mapped memory needed. */
129	#define HWACCM_VTX_TOTAL_DEVHEAP_MEM (HWACCM_EPT_IDENTITY_PG_TABLE_SIZE + HWACCM_VTX_TSS_SIZE)
130
131	/** HWACCM SSM version
132	*/
133	#define HWACCM_SSM_VERSION 3
134
135	/* Per-cpu information. */
136	typedef struct
137	{
138	RTCPUID idCpu;
139
140	RTR0MEMOBJ pMemObj;
141	/* Current ASID (AMD-V)/VPID (Intel) */
142	uint32_t uCurrentASID;
143	/* TLB flush count */
144	uint32_t cTLBFlushes;
145
146	/* Set the first time a cpu is used to make sure we start with a clean TLB. */
147	bool fFlushTLB;
148
149	/** Configured for VT-x or AMD-V. */
150	bool fConfigured;
151
152	/** In use by our code. (for power suspend) */
153	volatile bool fInUse;
154	} HWACCM_CPUINFO;
155	typedef HWACCM_CPUINFO *PHWACCM_CPUINFO;
156
157	/* VT-x capability qword. */
158	typedef union
159	{
160	struct
161	{
162	uint32_t disallowed0;
163	uint32_t allowed1;
164	} n;
165	uint64_t u;
166	} VMX_CAPABILITY;
167
168	/**
169	* HWACCM VM Instance data.
170	* Changes to this must checked against the padding of the cfgm union in VM!
171	*/
172	typedef struct HWACCM
173	{
174	/** Set when we've initialized VMX or SVM. */
175	bool fInitialized;
176	/** Set when we're using VMX/SVN at that moment. */
177	bool fActive;
178
179	/** Set when hardware acceleration is allowed. */
180	bool fAllowed;
181
182	/** Set if nested paging is enabled. */
183	bool fNestedPaging;
184
185	/** Set if nested paging is allowed. */
186	bool fAllowNestedPaging;
187	/** Set if VT-x VPID is allowed. */
188	bool fAllowVPID;
189
190	/** Set if we need to flush the TLB during the world switch. */
191	bool fForceTLBFlush;
192
193	/** Old style FPU reporting trap mask override performed (optimization) */
194	bool fFPUOldStyleOverride;
195
196	#if 0
197	/** Explicit alignment padding to make 32-bit gcc align u64RegisterMask
198	* naturally. */
199	bool padding[1];
200	#endif
201
202	/** HWACCM_CHANGED_* flags. */
203	RTUINT fContextUseFlags;
204
205	/* Id of the last cpu we were executing code on (NIL_RTCPUID for the first time) */
206	RTCPUID idLastCpu;
207
208	/* TLB flush count */
209	RTUINT cTLBFlushes;
210
211	/* Current ASID in use by the VM */
212	RTUINT uCurrentASID;
213
214	/** Maximum ASID allowed. */
215	RTUINT uMaxASID;
216
217	/** And mask for copying register contents. */
218	uint64_t u64RegisterMask;
219	struct
220	{
221	/** Set by the ring-0 driver to indicate VMX is supported by the CPU. */
222	bool fSupported;
223
224	/** Set when we've enabled VMX. */
225	bool fEnabled;
226
227	/** Set if we can use VMXResume to execute guest code. */
228	bool fResumeVM;
229
230	/** Set if VPID is supported. */
231	bool fVPID;
232
233	/** R0 memory object for the VM control structure (VMCS). */
234	RTR0MEMOBJ pMemObjVMCS;
235	/** Physical address of the VM control structure (VMCS). */
236	RTHCPHYS pVMCSPhys;
237	/** Virtual address of the VM control structure (VMCS). */
238	R0PTRTYPE(void *) pVMCS;
239
240	/** Virtual address of the TSS page used for real mode emulation. */
241	R3PTRTYPE(PVBOXTSS) pRealModeTSS;
242
243	/** Virtual address of the identity page table used for real mode and protected mode without paging emulation in EPT mode. */
244	R3PTRTYPE(PX86PD) pNonPagingModeEPTPageTable;
245
246	/** R0 memory object for the virtual APIC mmio cache. */
247	RTR0MEMOBJ pMemObjAPIC;
248	/** Physical address of the virtual APIC mmio cache. */
249	RTHCPHYS pAPICPhys;
250	/** Virtual address of the virtual APIC mmio cache. */
251	R0PTRTYPE(uint8_t *) pAPIC;
252
253	/** R0 memory object for the MSR bitmap (1 page). */
254	RTR0MEMOBJ pMemObjMSRBitmap;
255	/** Physical address of the MSR bitmap (1 page). */
256	RTHCPHYS pMSRBitmapPhys;
257	/** Virtual address of the MSR bitmap (1 page). */
258	R0PTRTYPE(uint8_t *) pMSRBitmap;
259
260	/** R0 memory object for the MSR entry load page (guest MSRs). */
261	RTR0MEMOBJ pMemObjMSREntryLoad;
262	/** Physical address of the MSR entry load page (guest MSRs). */
263	RTHCPHYS pMSREntryLoadPhys;
264	/** Virtual address of the MSR entry load page (guest MSRs). */
265	R0PTRTYPE(uint8_t *) pMSREntryLoad;
266
267	/** R0 memory object for the MSR exit store page (guest MSRs). */
268	RTR0MEMOBJ pMemObjMSRExitStore;
269	/** Physical address of the MSR exit store page (guest MSRs). */
270	RTHCPHYS pMSRExitStorePhys;
271	/** Virtual address of the MSR exit store page (guest MSRs). */
272	R0PTRTYPE(uint8_t *) pMSRExitStore;
273
274	/** R0 memory object for the MSR exit load page (host MSRs). */
275	RTR0MEMOBJ pMemObjMSRExitLoad;
276	/** Physical address of the MSR exit load page (host MSRs). */
277	RTHCPHYS pMSRExitLoadPhys;
278	/** Virtual address of the MSR exit load page (host MSRs). */
279	R0PTRTYPE(uint8_t *) pMSRExitLoad;
280
281	/** Ring 0 handlers for VT-x. */
282	DECLR0CALLBACKMEMBER(int, pfnStartVM,(RTHCUINT fResume, PCPUMCTX pCtx));
283	DECLR0CALLBACKMEMBER(void, pfnSetupTaggedTLB, (PVM pVM));
284
285	#if HC_ARCH_BITS == 32
286	uint32_t Alignment1;
287	#endif
288
289	/** Host CR4 value (set by ring-0 VMX init) */
290	uint64_t hostCR4;
291
292	/** Current VMX_VMCS_CTRL_PROC_EXEC_CONTROLS. */
293	uint64_t proc_ctls;
294
295	/** Current CR0 mask. */
296	uint64_t cr0_mask;
297	/** Current CR4 mask. */
298	uint64_t cr4_mask;
299
300	/** Current EPTP. */
301	RTHCPHYS GCPhysEPTP;
302
303	/** VMX MSR values */
304	struct
305	{
306	uint64_t feature_ctrl;
307	uint64_t vmx_basic_info;
308	VMX_CAPABILITY vmx_pin_ctls;
309	VMX_CAPABILITY vmx_proc_ctls;
310	VMX_CAPABILITY vmx_proc_ctls2;
311	VMX_CAPABILITY vmx_exit;
312	VMX_CAPABILITY vmx_entry;
313	uint64_t vmx_misc;
314	uint64_t vmx_cr0_fixed0;
315	uint64_t vmx_cr0_fixed1;
316	uint64_t vmx_cr4_fixed0;
317	uint64_t vmx_cr4_fixed1;
318	uint64_t vmx_vmcs_enum;
319	uint64_t vmx_eptcaps;
320	} msr;
321
322	/* Last instruction error */
323	uint32_t ulLastInstrError;
324
325	/** The last known guest paging mode. */
326	PGMMODE enmCurrGuestMode;
327
328	/** Flush types for invept & invvpid; they depend on capabilities. */
329	VMX_FLUSH enmFlushPage;
330	VMX_FLUSH enmFlushContext;
331
332	/** Real-mode emulation state. */
333	struct
334	{
335	X86EFLAGS eflags;
336	uint32_t fValid;
337	} RealMode;
338
339	struct
340	{
341	uint64_t u64VMCSPhys;
342	uint32_t ulVMCSRevision;
343	uint32_t ulLastInstrError;
344	uint32_t ulLastExitReason;
345	uint32_t padding;
346	} lasterror;
347	} vmx;
348
349	struct
350	{
351	/** Set by the ring-0 driver to indicate SVM is supported by the CPU. */
352	bool fSupported;
353	/** Set when we've enabled SVM. */
354	bool fEnabled;
355	/** Set if we don't have to flush the TLB on VM entry. */
356	bool fResumeVM;
357	/** Set if erratum 170 affects the AMD cpu. */
358	bool fAlwaysFlushTLB;
359
360	/** R0 memory object for the VM control block (VMCB). */
361	RTR0MEMOBJ pMemObjVMCB;
362	/** Physical address of the VM control block (VMCB). */
363	RTHCPHYS pVMCBPhys;
364	/** Virtual address of the VM control block (VMCB). */
365	R0PTRTYPE(void *) pVMCB;
366
367	/** R0 memory object for the host VM control block (VMCB). */
368	RTR0MEMOBJ pMemObjVMCBHost;
369	/** Physical address of the host VM control block (VMCB). */
370	RTHCPHYS pVMCBHostPhys;
371	/** Virtual address of the host VM control block (VMCB). */
372	R0PTRTYPE(void *) pVMCBHost;
373
374	/** R0 memory object for the IO bitmap (12kb). */
375	RTR0MEMOBJ pMemObjIOBitmap;
376	/** Physical address of the IO bitmap (12kb). */
377	RTHCPHYS pIOBitmapPhys;
378	/** Virtual address of the IO bitmap. */
379	R0PTRTYPE(void *) pIOBitmap;
380
381	/** R0 memory object for the MSR bitmap (8kb). */
382	RTR0MEMOBJ pMemObjMSRBitmap;
383	/** Physical address of the MSR bitmap (8kb). */
384	RTHCPHYS pMSRBitmapPhys;
385	/** Virtual address of the MSR bitmap. */
386	R0PTRTYPE(void *) pMSRBitmap;
387
388	/** Ring 0 handlers for VT-x. */
389	DECLR0CALLBACKMEMBER(int, pfnVMRun,(RTHCPHYS pVMCBHostPhys, RTHCPHYS pVMCBPhys, PCPUMCTX pCtx));
390
391	/** SVM revision. */
392	uint32_t u32Rev;
393
394	/** SVM feature bits from cpuid 0x8000000a */
395	uint32_t u32Features;
396	} svm;
397
398	struct
399	{
400	uint32_t u32AMDFeatureECX;
401	uint32_t u32AMDFeatureEDX;
402	} cpuid;
403
404	/** Event injection state. */
405	struct
406	{
407	uint32_t fPending;
408	uint32_t errCode;
409	uint64_t intInfo;
410	} Event;
411
412	/** Saved error from detection */
413	int32_t lLastError;
414
415	/** HWACCMR0Init was run */
416	bool fHWACCMR0Init;
417
418	/** Currenty shadow paging mode. */
419	PGMMODE enmShadowMode;
420
421	/** Explicit alignment padding of StatEntry (32-bit g++ again). */
422	int32_t padding2;
423
424	#ifdef VBOX_STRICT
425	/** The CPU ID of the CPU currently owning the VMCS. Set in
426	* HWACCMR0Enter and cleared in HWACCMR0Leave. */
427	RTCPUID idEnteredCpu;
428	# if HC_ARCH_BITS == 32
429	RTCPUID Alignment0;
430	# endif
431	#endif
432
433	STAMPROFILEADV StatEntry;
434	STAMPROFILEADV StatExit;
435	STAMPROFILEADV StatInGC;
436
437	STAMCOUNTER StatIntInject;
438
439	STAMCOUNTER StatExitShadowNM;
440	STAMCOUNTER StatExitGuestNM;
441	STAMCOUNTER StatExitShadowPF;
442	STAMCOUNTER StatExitGuestPF;
443	STAMCOUNTER StatExitGuestUD;
444	STAMCOUNTER StatExitGuestSS;
445	STAMCOUNTER StatExitGuestNP;
446	STAMCOUNTER StatExitGuestGP;
447	STAMCOUNTER StatExitGuestDE;
448	STAMCOUNTER StatExitGuestDB;
449	STAMCOUNTER StatExitGuestMF;
450	STAMCOUNTER StatExitInvpg;
451	STAMCOUNTER StatExitInvd;
452	STAMCOUNTER StatExitCpuid;
453	STAMCOUNTER StatExitRdtsc;
454	STAMCOUNTER StatExitCRxWrite;
455	STAMCOUNTER StatExitCRxRead;
456	STAMCOUNTER StatExitDRxWrite;
457	STAMCOUNTER StatExitDRxRead;
458	STAMCOUNTER StatExitCLTS;
459	STAMCOUNTER StatExitLMSW;
460	STAMCOUNTER StatExitIOWrite;
461	STAMCOUNTER StatExitIORead;
462	STAMCOUNTER StatExitIOStringWrite;
463	STAMCOUNTER StatExitIOStringRead;
464	STAMCOUNTER StatExitIrqWindow;
465	STAMCOUNTER StatExitMaxResume;
466	STAMCOUNTER StatIntReinject;
467	STAMCOUNTER StatPendingHostIrq;
468
469	STAMCOUNTER StatFlushPageManual;
470	STAMCOUNTER StatFlushPhysPageManual;
471	STAMCOUNTER StatFlushTLBManual;
472	STAMCOUNTER StatFlushPageInvlpg;
473	STAMCOUNTER StatFlushTLBWorldSwitch;
474	STAMCOUNTER StatNoFlushTLBWorldSwitch;
475	STAMCOUNTER StatFlushTLBCRxChange;
476	STAMCOUNTER StatFlushASID;
477	STAMCOUNTER StatFlushTLBInvlpga;
478
479	STAMCOUNTER StatSwitchGuestIrq;
480	STAMCOUNTER StatSwitchToR3;
481
482	STAMCOUNTER StatTSCOffset;
483	STAMCOUNTER StatTSCIntercept;
484
485	STAMCOUNTER StatExitReasonNPF;
486	STAMCOUNTER StatDRxArmed;
487	STAMCOUNTER StatDRxContextSwitch;
488	STAMCOUNTER StatDRxIOCheck;
489
490
491	R3PTRTYPE(PSTAMCOUNTER) paStatExitReason;
492	R0PTRTYPE(PSTAMCOUNTER) paStatExitReasonR0;
493	} HWACCM;
494	/** Pointer to HWACCM VM instance data. */
495	typedef HWACCM *PHWACCM;
496
497	/**
498	* HWACCM VMCPU Instance data.
499	*/
500	typedef struct HWACCMCPU
501	{
502	/** Offset to the VM structure.
503	* See HWACCMCPU2VM(). */
504	RTUINT offVMCPU;
505	} HWACCMCPU;
506	/** Pointer to HWACCM VM instance data. */
507	typedef HWACCMCPU *PHWACCMCPU;
508
509
510	#ifdef IN_RING0
511
512	VMMR0DECL(PHWACCM_CPUINFO) HWACCMR0GetCurrentCpu();
513
514	#ifdef VBOX_STRICT
515	VMMR0DECL(void) HWACCMDumpRegs(PVM pVM, PCPUMCTX pCtx);
516	VMMR0DECL(void) HWACCMR0DumpDescriptor(PX86DESCHC Desc, RTSEL Sel, const char *pszMsg);
517	#else
518	#define HWACCMDumpRegs(a, b) do { } while (0)
519	#define HWACCMR0DumpDescriptor(a, b, c) do { } while (0)
520	#endif
521
522	/* Dummy callback handlers. */
523	VMMR0DECL(int) HWACCMR0DummyEnter(PVM pVM, PHWACCM_CPUINFO pCpu);
524	VMMR0DECL(int) HWACCMR0DummyLeave(PVM pVM, CPUMCTX *pCtx);
525	VMMR0DECL(int) HWACCMR0DummyEnableCpu(PHWACCM_CPUINFO pCpu, PVM pVM, void *pvPageCpu, RTHCPHYS pPageCpuPhys);
526	VMMR0DECL(int) HWACCMR0DummyDisableCpu(PHWACCM_CPUINFO pCpu, void *pvPageCpu, RTHCPHYS pPageCpuPhys);
527	VMMR0DECL(int) HWACCMR0DummyInitVM(PVM pVM);
528	VMMR0DECL(int) HWACCMR0DummyTermVM(PVM pVM);
529	VMMR0DECL(int) HWACCMR0DummySetupVM(PVM pVM);
530	VMMR0DECL(int) HWACCMR0DummyRunGuestCode(PVM pVM, CPUMCTX *pCtx);
531	VMMR0DECL(int) HWACCMR0DummySaveHostState(PVM pVM);
532	VMMR0DECL(int) HWACCMR0DummyLoadGuestState(PVM pVM, CPUMCTX *pCtx);
533
534	#endif /* IN_RING0 */
535
536	/** @} */
537
538	__END_DECLS
539
540	#endif
541

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source: vbox/trunk/src/VBox/VMM/HWACCMInternal.h@ 13749

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