HWACCMInternal.h@ 13879

Last change on this file since 13879 was 13879, checked in by vboxsync, 16 years ago
SMP updates for VT-x/AMD-V.
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1	/* $Id: HWACCMInternal.h 13879 2008-11-05 16:11:03Z vboxsync $ */
2	/** @file
3	* HWACCM - Internal header file.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22	#ifndef ___HWACCMInternal_h
23	#define ___HWACCMInternal_h
24
25	#include <VBox/cdefs.h>
26	#include <VBox/types.h>
27	#include <VBox/em.h>
28	#include <VBox/stam.h>
29	#include <VBox/dis.h>
30	#include <VBox/hwaccm.h>
31	#include <VBox/pgm.h>
32	#include <VBox/cpum.h>
33	#include <iprt/memobj.h>
34	#include <iprt/cpuset.h>
35	#include <iprt/mp.h>
36
37	#if HC_ARCH_BITS == 64
38	/* Enable 64 bits guest support. */
39	# define VBOX_ENABLE_64_BITS_GUESTS
40	#endif
41
42	#define HWACCM_VMX_EMULATE_REALMODE
43	#define HWACCM_VTX_WITH_EPT
44	#define HWACCM_VTX_WITH_VPID
45
46	__BEGIN_DECLS
47
48
49	/** @defgroup grp_hwaccm_int Internal
50	* @ingroup grp_hwaccm
51	* @internal
52	* @{
53	*/
54
55
56	/** Maximum number of exit reason statistics counters. */
57	#define MAX_EXITREASON_STAT 0x100
58	#define MASK_EXITREASON_STAT 0xff
59
60	/** @name Changed flags
61	* These flags are used to keep track of which important registers that
62	* have been changed since last they were reset.
63	* @{
64	*/
65	#define HWACCM_CHANGED_GUEST_FPU RT_BIT(0)
66	#define HWACCM_CHANGED_GUEST_CR0 RT_BIT(1)
67	#define HWACCM_CHANGED_GUEST_CR3 RT_BIT(2)
68	#define HWACCM_CHANGED_GUEST_CR4 RT_BIT(3)
69	#define HWACCM_CHANGED_GUEST_GDTR RT_BIT(4)
70	#define HWACCM_CHANGED_GUEST_IDTR RT_BIT(5)
71	#define HWACCM_CHANGED_GUEST_LDTR RT_BIT(6)
72	#define HWACCM_CHANGED_GUEST_TR RT_BIT(7)
73	#define HWACCM_CHANGED_GUEST_SYSENTER_MSR RT_BIT(8)
74	#define HWACCM_CHANGED_GUEST_SEGMENT_REGS RT_BIT(9)
75	#define HWACCM_CHANGED_GUEST_DEBUG RT_BIT(10)
76	#define HWACCM_CHANGED_HOST_CONTEXT RT_BIT(11)
77
78	#define HWACCM_CHANGED_ALL ( HWACCM_CHANGED_GUEST_SEGMENT_REGS \
79	\| HWACCM_CHANGED_GUEST_CR0 \
80	\| HWACCM_CHANGED_GUEST_CR3 \
81	\| HWACCM_CHANGED_GUEST_CR4 \
82	\| HWACCM_CHANGED_GUEST_GDTR \
83	\| HWACCM_CHANGED_GUEST_IDTR \
84	\| HWACCM_CHANGED_GUEST_LDTR \
85	\| HWACCM_CHANGED_GUEST_TR \
86	\| HWACCM_CHANGED_GUEST_SYSENTER_MSR \
87	\| HWACCM_CHANGED_GUEST_FPU \
88	\| HWACCM_CHANGED_GUEST_DEBUG \
89	\| HWACCM_CHANGED_HOST_CONTEXT)
90
91	#define HWACCM_CHANGED_ALL_GUEST ( HWACCM_CHANGED_GUEST_SEGMENT_REGS \
92	\| HWACCM_CHANGED_GUEST_CR0 \
93	\| HWACCM_CHANGED_GUEST_CR3 \
94	\| HWACCM_CHANGED_GUEST_CR4 \
95	\| HWACCM_CHANGED_GUEST_GDTR \
96	\| HWACCM_CHANGED_GUEST_IDTR \
97	\| HWACCM_CHANGED_GUEST_LDTR \
98	\| HWACCM_CHANGED_GUEST_TR \
99	\| HWACCM_CHANGED_GUEST_SYSENTER_MSR \
100	\| HWACCM_CHANGED_GUEST_DEBUG \
101	\| HWACCM_CHANGED_GUEST_FPU)
102
103	/** @} */
104
105	/** @name Intercepted traps
106	* Traps that need to be intercepted so we can correctly dispatch them to the guest if required.
107	* Currently #NM and #PF only
108	*/
109	#ifdef VBOX_STRICT
110	#define HWACCM_VMX_TRAP_MASK RT_BIT(X86_XCPT_DE) \| RT_BIT(X86_XCPT_NM) \| RT_BIT(X86_XCPT_PF) \| RT_BIT(X86_XCPT_UD) \| RT_BIT(X86_XCPT_NP) \| RT_BIT(X86_XCPT_SS) \| RT_BIT(X86_XCPT_GP) \| RT_BIT(X86_XCPT_MF)
111	#define HWACCM_SVM_TRAP_MASK HWACCM_VMX_TRAP_MASK
112	#else
113	#define HWACCM_VMX_TRAP_MASK RT_BIT(X86_XCPT_NM) \| RT_BIT(X86_XCPT_PF)
114	#define HWACCM_SVM_TRAP_MASK RT_BIT(X86_XCPT_NM) \| RT_BIT(X86_XCPT_PF)
115	#endif
116	/* All exceptions have to be intercept in emulated real-mode (minues NM & PF as they are always intercepted. */
117	#define HWACCM_VMX_TRAP_MASK_REALMODE RT_BIT(X86_XCPT_DE) \| RT_BIT(X86_XCPT_DB) \| RT_BIT(X86_XCPT_NMI) \| RT_BIT(X86_XCPT_BP) \| RT_BIT(X86_XCPT_OF) \| RT_BIT(X86_XCPT_BR) \| RT_BIT(X86_XCPT_UD) \| RT_BIT(X86_XCPT_DF) \| RT_BIT(X86_XCPT_CO_SEG_OVERRUN) \| RT_BIT(X86_XCPT_TS) \| RT_BIT(X86_XCPT_NP) \| RT_BIT(X86_XCPT_SS) \| RT_BIT(X86_XCPT_GP) \| RT_BIT(X86_XCPT_MF) \| RT_BIT(X86_XCPT_AC) \| RT_BIT(X86_XCPT_MC) \| RT_BIT(X86_XCPT_XF)
118	/** @} */
119
120
121	/** Maxium resume loops allowed in ring 0 (safety precaution) */
122	#define HWACCM_MAX_RESUME_LOOPS 1024
123
124	/** Size for the EPT identity page table (1024 4 MB pages to cover the entire address space). */
125	#define HWACCM_EPT_IDENTITY_PG_TABLE_SIZE PAGE_SIZE
126	/** Size of the TSS structure + 2 pages for the IO bitmap + end byte. */
127	#define HWACCM_VTX_TSS_SIZE (sizeof(VBOXTSS) + 2*PAGE_SIZE + 1)
128	/** Total guest mapped memory needed. */
129	#define HWACCM_VTX_TOTAL_DEVHEAP_MEM (HWACCM_EPT_IDENTITY_PG_TABLE_SIZE + HWACCM_VTX_TSS_SIZE)
130
131	/** HWACCM SSM version
132	*/
133	#define HWACCM_SSM_VERSION 3
134
135	/* Per-cpu information. (host) */
136	typedef struct
137	{
138	RTCPUID idCpu;
139
140	RTR0MEMOBJ pMemObj;
141	/* Current ASID (AMD-V)/VPID (Intel) */
142	uint32_t uCurrentASID;
143	/* TLB flush count */
144	uint32_t cTLBFlushes;
145
146	/* Set the first time a cpu is used to make sure we start with a clean TLB. */
147	bool fFlushTLB;
148
149	/** Configured for VT-x or AMD-V. */
150	bool fConfigured;
151
152	/** In use by our code. (for power suspend) */
153	volatile bool fInUse;
154	} HWACCM_CPUINFO;
155	typedef HWACCM_CPUINFO *PHWACCM_CPUINFO;
156
157	/* VT-x capability qword. */
158	typedef union
159	{
160	struct
161	{
162	uint32_t disallowed0;
163	uint32_t allowed1;
164	} n;
165	uint64_t u;
166	} VMX_CAPABILITY;
167
168	/**
169	* HWACCM VM Instance data.
170	* Changes to this must checked against the padding of the cfgm union in VM!
171	*/
172	typedef struct HWACCM
173	{
174	/** Set when we've initialized VMX or SVM. */
175	bool fInitialized;
176	/** Set when we're using VMX/SVN at that moment. */
177	bool fActive;
178
179	/** Set when hardware acceleration is allowed. */
180	bool fAllowed;
181
182	/** Set if nested paging is enabled. */
183	bool fNestedPaging;
184
185	/** Set if nested paging is allowed. */
186	bool fAllowNestedPaging;
187	/** Set if VT-x VPID is allowed. */
188	bool fAllowVPID;
189
190	/** Set if we need to flush the TLB during the world switch. */
191	bool fForceTLBFlush;
192
193	/** Old style FPU reporting trap mask override performed (optimization) */
194	bool fFPUOldStyleOverride;
195
196	/** Explicit alignment padding to make 32-bit gcc align u64RegisterMask
197	* naturally. */
198	bool padding[1];
199
200	/** HWACCM_CHANGED_* flags. */
201	RTUINT fContextUseFlags;
202
203	/* Id of the last cpu we were executing code on (NIL_RTCPUID for the first time) */
204	RTCPUID idLastCpu;
205
206	/* TLB flush count */
207	RTUINT cTLBFlushes;
208
209	/* Current ASID in use by the VM */
210	RTUINT uCurrentASID;
211
212	/** Maximum ASID allowed. */
213	RTUINT uMaxASID;
214
215	/** And mask for copying register contents. */
216	uint64_t u64RegisterMask;
217	struct
218	{
219	/** Set by the ring-0 driver to indicate VMX is supported by the CPU. */
220	bool fSupported;
221
222	/** Set when we've enabled VMX. */
223	bool fEnabled;
224
225	/** Set if we can use VMXResume to execute guest code. */
226	bool fResumeVM;
227
228	/** Set if VPID is supported. */
229	bool fVPID;
230
231	/** Virtual address of the TSS page used for real mode emulation. */
232	R3PTRTYPE(PVBOXTSS) pRealModeTSS;
233
234	/** Virtual address of the identity page table used for real mode and protected mode without paging emulation in EPT mode. */
235	R3PTRTYPE(PX86PD) pNonPagingModeEPTPageTable;
236
237	/** R0 memory object for the virtual APIC mmio cache. */
238	RTR0MEMOBJ pMemObjAPIC;
239	/** Physical address of the virtual APIC mmio cache. */
240	RTHCPHYS pAPICPhys;
241	/** Virtual address of the virtual APIC mmio cache. */
242	R0PTRTYPE(uint8_t *) pAPIC;
243
244	/** R0 memory object for the MSR bitmap (1 page). */
245	RTR0MEMOBJ pMemObjMSRBitmap;
246	/** Physical address of the MSR bitmap (1 page). */
247	RTHCPHYS pMSRBitmapPhys;
248	/** Virtual address of the MSR bitmap (1 page). */
249	R0PTRTYPE(uint8_t *) pMSRBitmap;
250
251	/** R0 memory object for the MSR entry load page (guest MSRs). */
252	RTR0MEMOBJ pMemObjMSREntryLoad;
253	/** Physical address of the MSR entry load page (guest MSRs). */
254	RTHCPHYS pMSREntryLoadPhys;
255	/** Virtual address of the MSR entry load page (guest MSRs). */
256	R0PTRTYPE(uint8_t *) pMSREntryLoad;
257
258	/** R0 memory object for the MSR exit store page (guest MSRs). */
259	RTR0MEMOBJ pMemObjMSRExitStore;
260	/** Physical address of the MSR exit store page (guest MSRs). */
261	RTHCPHYS pMSRExitStorePhys;
262	/** Virtual address of the MSR exit store page (guest MSRs). */
263	R0PTRTYPE(uint8_t *) pMSRExitStore;
264
265	/** R0 memory object for the MSR exit load page (host MSRs). */
266	RTR0MEMOBJ pMemObjMSRExitLoad;
267	/** Physical address of the MSR exit load page (host MSRs). */
268	RTHCPHYS pMSRExitLoadPhys;
269	/** Virtual address of the MSR exit load page (host MSRs). */
270	R0PTRTYPE(uint8_t *) pMSRExitLoad;
271
272	/** Ring 0 handlers for VT-x. */
273	DECLR0CALLBACKMEMBER(void, pfnSetupTaggedTLB, (PVM pVM));
274
275	#if HC_ARCH_BITS == 32
276	uint32_t Alignment1;
277	#endif
278
279	/** Host CR4 value (set by ring-0 VMX init) */
280	uint64_t hostCR4;
281
282	/** VMX MSR values */
283	struct
284	{
285	uint64_t feature_ctrl;
286	uint64_t vmx_basic_info;
287	VMX_CAPABILITY vmx_pin_ctls;
288	VMX_CAPABILITY vmx_proc_ctls;
289	VMX_CAPABILITY vmx_proc_ctls2;
290	VMX_CAPABILITY vmx_exit;
291	VMX_CAPABILITY vmx_entry;
292	uint64_t vmx_misc;
293	uint64_t vmx_cr0_fixed0;
294	uint64_t vmx_cr0_fixed1;
295	uint64_t vmx_cr4_fixed0;
296	uint64_t vmx_cr4_fixed1;
297	uint64_t vmx_vmcs_enum;
298	uint64_t vmx_eptcaps;
299	} msr;
300
301	/* Last instruction error */
302	uint32_t ulLastInstrError;
303
304	/** The last known guest paging mode. */
305	PGMMODE enmCurrGuestMode;
306
307	/** Flush types for invept & invvpid; they depend on capabilities. */
308	VMX_FLUSH enmFlushPage;
309	VMX_FLUSH enmFlushContext;
310
311	/** Real-mode emulation state. */
312	struct
313	{
314	X86EFLAGS eflags;
315	uint32_t fValid;
316	} RealMode;
317
318	struct
319	{
320	uint64_t u64VMCSPhys;
321	uint32_t ulVMCSRevision;
322	uint32_t ulLastInstrError;
323	uint32_t ulLastExitReason;
324	uint32_t padding;
325	} lasterror;
326	} vmx;
327
328	struct
329	{
330	/** Set by the ring-0 driver to indicate SVM is supported by the CPU. */
331	bool fSupported;
332	/** Set when we've enabled SVM. */
333	bool fEnabled;
334	/** Set if we don't have to flush the TLB on VM entry. */
335	bool fResumeVM;
336	/** Set if erratum 170 affects the AMD cpu. */
337	bool fAlwaysFlushTLB;
338
339	/** R0 memory object for the host VM control block (VMCB). */
340	RTR0MEMOBJ pMemObjVMCBHost;
341	/** Physical address of the host VM control block (VMCB). */
342	RTHCPHYS pVMCBHostPhys;
343	/** Virtual address of the host VM control block (VMCB). */
344	R0PTRTYPE(void *) pVMCBHost;
345
346	/** R0 memory object for the IO bitmap (12kb). */
347	RTR0MEMOBJ pMemObjIOBitmap;
348	/** Physical address of the IO bitmap (12kb). */
349	RTHCPHYS pIOBitmapPhys;
350	/** Virtual address of the IO bitmap. */
351	R0PTRTYPE(void *) pIOBitmap;
352
353	/** R0 memory object for the MSR bitmap (8kb). */
354	RTR0MEMOBJ pMemObjMSRBitmap;
355	/** Physical address of the MSR bitmap (8kb). */
356	RTHCPHYS pMSRBitmapPhys;
357	/** Virtual address of the MSR bitmap. */
358	R0PTRTYPE(void *) pMSRBitmap;
359
360	/** SVM revision. */
361	uint32_t u32Rev;
362
363	/** SVM feature bits from cpuid 0x8000000a */
364	uint32_t u32Features;
365	} svm;
366
367	struct
368	{
369	uint32_t u32AMDFeatureECX;
370	uint32_t u32AMDFeatureEDX;
371	} cpuid;
372
373	/** Event injection state. */
374	struct
375	{
376	uint32_t fPending;
377	uint32_t errCode;
378	uint64_t intInfo;
379	} Event;
380
381	/** Saved error from detection */
382	int32_t lLastError;
383
384	/** HWACCMR0Init was run */
385	bool fHWACCMR0Init;
386
387	/** Currenty shadow paging mode. */
388	PGMMODE enmShadowMode;
389
390	/** Explicit alignment padding of StatEntry (32-bit g++ again). */
391	int32_t padding2;
392
393	#ifdef VBOX_STRICT
394	/** The CPU ID of the CPU currently owning the VMCS. Set in
395	* HWACCMR0Enter and cleared in HWACCMR0Leave. */
396	RTCPUID idEnteredCpu;
397	# if HC_ARCH_BITS == 32
398	RTCPUID Alignment0;
399	# endif
400	#endif
401
402	STAMPROFILEADV StatEntry;
403	STAMPROFILEADV StatExit;
404	STAMPROFILEADV StatInGC;
405
406	STAMCOUNTER StatIntInject;
407
408	STAMCOUNTER StatExitShadowNM;
409	STAMCOUNTER StatExitGuestNM;
410	STAMCOUNTER StatExitShadowPF;
411	STAMCOUNTER StatExitGuestPF;
412	STAMCOUNTER StatExitGuestUD;
413	STAMCOUNTER StatExitGuestSS;
414	STAMCOUNTER StatExitGuestNP;
415	STAMCOUNTER StatExitGuestGP;
416	STAMCOUNTER StatExitGuestDE;
417	STAMCOUNTER StatExitGuestDB;
418	STAMCOUNTER StatExitGuestMF;
419	STAMCOUNTER StatExitInvpg;
420	STAMCOUNTER StatExitInvd;
421	STAMCOUNTER StatExitCpuid;
422	STAMCOUNTER StatExitRdtsc;
423	STAMCOUNTER StatExitCRxWrite;
424	STAMCOUNTER StatExitCRxRead;
425	STAMCOUNTER StatExitDRxWrite;
426	STAMCOUNTER StatExitDRxRead;
427	STAMCOUNTER StatExitCLTS;
428	STAMCOUNTER StatExitLMSW;
429	STAMCOUNTER StatExitIOWrite;
430	STAMCOUNTER StatExitIORead;
431	STAMCOUNTER StatExitIOStringWrite;
432	STAMCOUNTER StatExitIOStringRead;
433	STAMCOUNTER StatExitIrqWindow;
434	STAMCOUNTER StatExitMaxResume;
435	STAMCOUNTER StatIntReinject;
436	STAMCOUNTER StatPendingHostIrq;
437
438	STAMCOUNTER StatFlushPageManual;
439	STAMCOUNTER StatFlushPhysPageManual;
440	STAMCOUNTER StatFlushTLBManual;
441	STAMCOUNTER StatFlushPageInvlpg;
442	STAMCOUNTER StatFlushTLBWorldSwitch;
443	STAMCOUNTER StatNoFlushTLBWorldSwitch;
444	STAMCOUNTER StatFlushTLBCRxChange;
445	STAMCOUNTER StatFlushASID;
446	STAMCOUNTER StatFlushTLBInvlpga;
447
448	STAMCOUNTER StatSwitchGuestIrq;
449	STAMCOUNTER StatSwitchToR3;
450
451	STAMCOUNTER StatTSCOffset;
452	STAMCOUNTER StatTSCIntercept;
453
454	STAMCOUNTER StatExitReasonNPF;
455	STAMCOUNTER StatDRxArmed;
456	STAMCOUNTER StatDRxContextSwitch;
457	STAMCOUNTER StatDRxIOCheck;
458
459
460	R3PTRTYPE(PSTAMCOUNTER) paStatExitReason;
461	R0PTRTYPE(PSTAMCOUNTER) paStatExitReasonR0;
462	} HWACCM;
463	/** Pointer to HWACCM VM instance data. */
464	typedef HWACCM *PHWACCM;
465
466	/**
467	* HWACCM VMCPU Instance data.
468	*/
469	typedef struct HWACCMCPU
470	{
471	/** Offset to the VM structure.
472	* See HWACCMCPU2VM(). */
473	RTUINT offVMCPU;
474
475	struct
476	{
477	/** R0 memory object for the VM control structure (VMCS). */
478	RTR0MEMOBJ pMemObjVMCS;
479	/** Physical address of the VM control structure (VMCS). */
480	RTHCPHYS pVMCSPhys;
481	/** Virtual address of the VM control structure (VMCS). */
482	R0PTRTYPE(void *) pVMCS;
483
484	/** Ring 0 handlers for VT-x. */
485	DECLR0CALLBACKMEMBER(int, pfnStartVM,(RTHCUINT fResume, PCPUMCTX pCtx));
486
487	/** Current VMX_VMCS_CTRL_PROC_EXEC_CONTROLS. */
488	uint64_t proc_ctls;
489
490	/** Current CR0 mask. */
491	uint64_t cr0_mask;
492	/** Current CR4 mask. */
493	uint64_t cr4_mask;
494
495	/** Current EPTP. */
496	RTHCPHYS GCPhysEPTP;
497	} vmx;
498
499	struct
500	{
501	/** R0 memory object for the VM control block (VMCB). */
502	RTR0MEMOBJ pMemObjVMCB;
503	/** Physical address of the VM control block (VMCB). */
504	RTHCPHYS pVMCBPhys;
505	/** Virtual address of the VM control block (VMCB). */
506	R0PTRTYPE(void *) pVMCB;
507
508	/** Ring 0 handlers for VT-x. */
509	DECLR0CALLBACKMEMBER(int, pfnVMRun,(RTHCPHYS pVMCBHostPhys, RTHCPHYS pVMCBPhys, PCPUMCTX pCtx));
510
511	} svm;
512
513	} HWACCMCPU;
514	/** Pointer to HWACCM VM instance data. */
515	typedef HWACCMCPU *PHWACCMCPU;
516
517
518	#ifdef IN_RING0
519
520	VMMR0DECL(PHWACCM_CPUINFO) HWACCMR0GetCurrentCpu();
521
522	#ifdef VBOX_STRICT
523	VMMR0DECL(void) HWACCMDumpRegs(PVM pVM, PCPUMCTX pCtx);
524	VMMR0DECL(void) HWACCMR0DumpDescriptor(PX86DESCHC Desc, RTSEL Sel, const char *pszMsg);
525	#else
526	#define HWACCMDumpRegs(a, b) do { } while (0)
527	#define HWACCMR0DumpDescriptor(a, b, c) do { } while (0)
528	#endif
529
530	/* Dummy callback handlers. */
531	VMMR0DECL(int) HWACCMR0DummyEnter(PVM pVM, PVMCPU pVCpu, PHWACCM_CPUINFO pCpu);
532	VMMR0DECL(int) HWACCMR0DummyLeave(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
533	VMMR0DECL(int) HWACCMR0DummyEnableCpu(PHWACCM_CPUINFO pCpu, PVM pVM, void *pvPageCpu, RTHCPHYS pPageCpuPhys);
534	VMMR0DECL(int) HWACCMR0DummyDisableCpu(PHWACCM_CPUINFO pCpu, void *pvPageCpu, RTHCPHYS pPageCpuPhys);
535	VMMR0DECL(int) HWACCMR0DummyInitVM(PVM pVM);
536	VMMR0DECL(int) HWACCMR0DummyTermVM(PVM pVM);
537	VMMR0DECL(int) HWACCMR0DummySetupVM(PVM pVM);
538	VMMR0DECL(int) HWACCMR0DummyRunGuestCode(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
539	VMMR0DECL(int) HWACCMR0DummySaveHostState(PVM pVM, PVMCPU pVCpu);
540	VMMR0DECL(int) HWACCMR0DummyLoadGuestState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
541
542	#endif /* IN_RING0 */
543
544	/** @} */
545
546	__END_DECLS
547
548	#endif
549

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source: vbox/trunk/src/VBox/VMM/HWACCMInternal.h@ 13879

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