HWACCMInternal.h@ 14845

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1	/* $Id: HWACCMInternal.h 14845 2008-12-01 10:12:25Z vboxsync $ */
2	/** @file
3	* HWACCM - Internal header file.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22	#ifndef ___HWACCMInternal_h
23	#define ___HWACCMInternal_h
24
25	#include <VBox/cdefs.h>
26	#include <VBox/types.h>
27	#include <VBox/em.h>
28	#include <VBox/stam.h>
29	#include <VBox/dis.h>
30	#include <VBox/hwaccm.h>
31	#include <VBox/pgm.h>
32	#include <VBox/cpum.h>
33	#include <iprt/memobj.h>
34	#include <iprt/cpuset.h>
35	#include <iprt/mp.h>
36
37	#if HC_ARCH_BITS == 64
38	/* Enable 64 bits guest support. */
39	# define VBOX_ENABLE_64_BITS_GUESTS
40	#endif
41
42	#define HWACCM_VMX_EMULATE_REALMODE
43	#define HWACCM_VTX_WITH_EPT
44	#define HWACCM_VTX_WITH_VPID
45
46	__BEGIN_DECLS
47
48
49	/** @defgroup grp_hwaccm_int Internal
50	* @ingroup grp_hwaccm
51	* @internal
52	* @{
53	*/
54
55
56	/** Maximum number of exit reason statistics counters. */
57	#define MAX_EXITREASON_STAT 0x100
58	#define MASK_EXITREASON_STAT 0xff
59
60	/** @name Changed flags
61	* These flags are used to keep track of which important registers that
62	* have been changed since last they were reset.
63	* @{
64	*/
65	#define HWACCM_CHANGED_GUEST_FPU RT_BIT(0)
66	#define HWACCM_CHANGED_GUEST_CR0 RT_BIT(1)
67	#define HWACCM_CHANGED_GUEST_CR3 RT_BIT(2)
68	#define HWACCM_CHANGED_GUEST_CR4 RT_BIT(3)
69	#define HWACCM_CHANGED_GUEST_GDTR RT_BIT(4)
70	#define HWACCM_CHANGED_GUEST_IDTR RT_BIT(5)
71	#define HWACCM_CHANGED_GUEST_LDTR RT_BIT(6)
72	#define HWACCM_CHANGED_GUEST_TR RT_BIT(7)
73	#define HWACCM_CHANGED_GUEST_SYSENTER_MSR RT_BIT(8)
74	#define HWACCM_CHANGED_GUEST_SEGMENT_REGS RT_BIT(9)
75	#define HWACCM_CHANGED_GUEST_DEBUG RT_BIT(10)
76	#define HWACCM_CHANGED_HOST_CONTEXT RT_BIT(11)
77
78	#define HWACCM_CHANGED_ALL ( HWACCM_CHANGED_GUEST_SEGMENT_REGS \
79	\| HWACCM_CHANGED_GUEST_CR0 \
80	\| HWACCM_CHANGED_GUEST_CR3 \
81	\| HWACCM_CHANGED_GUEST_CR4 \
82	\| HWACCM_CHANGED_GUEST_GDTR \
83	\| HWACCM_CHANGED_GUEST_IDTR \
84	\| HWACCM_CHANGED_GUEST_LDTR \
85	\| HWACCM_CHANGED_GUEST_TR \
86	\| HWACCM_CHANGED_GUEST_SYSENTER_MSR \
87	\| HWACCM_CHANGED_GUEST_FPU \
88	\| HWACCM_CHANGED_GUEST_DEBUG \
89	\| HWACCM_CHANGED_HOST_CONTEXT)
90
91	#define HWACCM_CHANGED_ALL_GUEST ( HWACCM_CHANGED_GUEST_SEGMENT_REGS \
92	\| HWACCM_CHANGED_GUEST_CR0 \
93	\| HWACCM_CHANGED_GUEST_CR3 \
94	\| HWACCM_CHANGED_GUEST_CR4 \
95	\| HWACCM_CHANGED_GUEST_GDTR \
96	\| HWACCM_CHANGED_GUEST_IDTR \
97	\| HWACCM_CHANGED_GUEST_LDTR \
98	\| HWACCM_CHANGED_GUEST_TR \
99	\| HWACCM_CHANGED_GUEST_SYSENTER_MSR \
100	\| HWACCM_CHANGED_GUEST_DEBUG \
101	\| HWACCM_CHANGED_GUEST_FPU)
102
103	/** @} */
104
105	/** @name Intercepted traps
106	* Traps that need to be intercepted so we can correctly dispatch them to the guest if required.
107	* Currently #NM and #PF only
108	*/
109	#ifdef VBOX_STRICT
110	#define HWACCM_VMX_TRAP_MASK RT_BIT(X86_XCPT_DE) \| RT_BIT(X86_XCPT_NM) \| RT_BIT(X86_XCPT_PF) \| RT_BIT(X86_XCPT_UD) \| RT_BIT(X86_XCPT_NP) \| RT_BIT(X86_XCPT_SS) \| RT_BIT(X86_XCPT_GP) \| RT_BIT(X86_XCPT_MF)
111	#define HWACCM_SVM_TRAP_MASK HWACCM_VMX_TRAP_MASK
112	#else
113	#define HWACCM_VMX_TRAP_MASK RT_BIT(X86_XCPT_NM) \| RT_BIT(X86_XCPT_PF)
114	#define HWACCM_SVM_TRAP_MASK RT_BIT(X86_XCPT_NM) \| RT_BIT(X86_XCPT_PF)
115	#endif
116	/* All exceptions have to be intercept in emulated real-mode (minues NM & PF as they are always intercepted. */
117	#define HWACCM_VMX_TRAP_MASK_REALMODE RT_BIT(X86_XCPT_DE) \| RT_BIT(X86_XCPT_DB) \| RT_BIT(X86_XCPT_NMI) \| RT_BIT(X86_XCPT_BP) \| RT_BIT(X86_XCPT_OF) \| RT_BIT(X86_XCPT_BR) \| RT_BIT(X86_XCPT_UD) \| RT_BIT(X86_XCPT_DF) \| RT_BIT(X86_XCPT_CO_SEG_OVERRUN) \| RT_BIT(X86_XCPT_TS) \| RT_BIT(X86_XCPT_NP) \| RT_BIT(X86_XCPT_SS) \| RT_BIT(X86_XCPT_GP) \| RT_BIT(X86_XCPT_MF) \| RT_BIT(X86_XCPT_AC) \| RT_BIT(X86_XCPT_MC) \| RT_BIT(X86_XCPT_XF)
118	/** @} */
119
120
121	/** Maxium resume loops allowed in ring 0 (safety precaution) */
122	#define HWACCM_MAX_RESUME_LOOPS 1024
123
124	/** Size for the EPT identity page table (1024 4 MB pages to cover the entire address space). */
125	#define HWACCM_EPT_IDENTITY_PG_TABLE_SIZE PAGE_SIZE
126	/** Size of the TSS structure + 2 pages for the IO bitmap + end byte. */
127	#define HWACCM_VTX_TSS_SIZE (sizeof(VBOXTSS) + 2*PAGE_SIZE + 1)
128	/** Total guest mapped memory needed. */
129	#define HWACCM_VTX_TOTAL_DEVHEAP_MEM (HWACCM_EPT_IDENTITY_PG_TABLE_SIZE + HWACCM_VTX_TSS_SIZE)
130
131	/** HWACCM SSM version
132	*/
133	#define HWACCM_SSM_VERSION 3
134
135	/* Per-cpu information. (host) */
136	typedef struct
137	{
138	RTCPUID idCpu;
139
140	RTR0MEMOBJ pMemObj;
141	/* Current ASID (AMD-V)/VPID (Intel) */
142	uint32_t uCurrentASID;
143	/* TLB flush count */
144	uint32_t cTLBFlushes;
145
146	/* Set the first time a cpu is used to make sure we start with a clean TLB. */
147	bool fFlushTLB;
148
149	/** Configured for VT-x or AMD-V. */
150	bool fConfigured;
151
152	/** In use by our code. (for power suspend) */
153	volatile bool fInUse;
154	} HWACCM_CPUINFO;
155	typedef HWACCM_CPUINFO *PHWACCM_CPUINFO;
156
157	/* VT-x capability qword. */
158	typedef union
159	{
160	struct
161	{
162	uint32_t disallowed0;
163	uint32_t allowed1;
164	} n;
165	uint64_t u;
166	} VMX_CAPABILITY;
167
168	/**
169	* HWACCM VM Instance data.
170	* Changes to this must checked against the padding of the cfgm union in VM!
171	*/
172	typedef struct HWACCM
173	{
174	/** Set when we've initialized VMX or SVM. */
175	bool fInitialized;
176	/** Set when we're using VMX/SVN at that moment. */
177	bool fActive;
178
179	/** Set when hardware acceleration is allowed. */
180	bool fAllowed;
181
182	/** Set if nested paging is enabled. */
183	bool fNestedPaging;
184
185	/** Set if nested paging is allowed. */
186	bool fAllowNestedPaging;
187
188	/** Set if we're supposed to inject an NMI. */
189	bool fInjectNMI;
190
191	/** Explicit alignment padding to make 32-bit gcc align u64RegisterMask
192	* naturally. */
193	bool padding[1];
194
195	/** And mask for copying register contents. */
196	uint64_t u64RegisterMask;
197
198	/** Maximum ASID allowed. */
199	RTUINT uMaxASID;
200
201	#if HC_ARCH_BITS == 32
202	/** 32 to 64 bits switcher entrypoint. */
203	RTR0PTR pfnHost32ToGuest64R0;
204
205	/* AMD-V 64 bits vmrun handler */
206	RTRCPTR pfnSVMGCVMRun64;
207
208	/* VT-x 64 bits vmlaunch handler */
209	RTRCPTR pfnVMXGCStartVM64;
210
211	uint32_t Alignment0;
212	#endif
213
214	struct
215	{
216	/** Set by the ring-0 driver to indicate VMX is supported by the CPU. */
217	bool fSupported;
218
219	/** Set when we've enabled VMX. */
220	bool fEnabled;
221
222	/** Set if VPID is supported. */
223	bool fVPID;
224
225	/** Set if VT-x VPID is allowed. */
226	bool fAllowVPID;
227
228	/** Virtual address of the TSS page used for real mode emulation. */
229	R3PTRTYPE(PVBOXTSS) pRealModeTSS;
230
231	/** Virtual address of the identity page table used for real mode and protected mode without paging emulation in EPT mode. */
232	R3PTRTYPE(PX86PD) pNonPagingModeEPTPageTable;
233
234	/** R0 memory object for the virtual APIC mmio cache. */
235	RTR0MEMOBJ pMemObjAPIC;
236	/** Physical address of the virtual APIC mmio cache. */
237	RTHCPHYS pAPICPhys;
238	/** Virtual address of the virtual APIC mmio cache. */
239	R0PTRTYPE(uint8_t *) pAPIC;
240
241	/** R0 memory object for the MSR bitmap (1 page). */
242	RTR0MEMOBJ pMemObjMSRBitmap;
243	/** Physical address of the MSR bitmap (1 page). */
244	RTHCPHYS pMSRBitmapPhys;
245	/** Virtual address of the MSR bitmap (1 page). */
246	R0PTRTYPE(uint8_t *) pMSRBitmap;
247
248	/** R0 memory object for the MSR entry load page (guest MSRs). */
249	RTR0MEMOBJ pMemObjMSREntryLoad;
250	/** Physical address of the MSR entry load page (guest MSRs). */
251	RTHCPHYS pMSREntryLoadPhys;
252	/** Virtual address of the MSR entry load page (guest MSRs). */
253	R0PTRTYPE(uint8_t *) pMSREntryLoad;
254
255	/** R0 memory object for the MSR exit store page (guest MSRs). */
256	RTR0MEMOBJ pMemObjMSRExitStore;
257	/** Physical address of the MSR exit store page (guest MSRs). */
258	RTHCPHYS pMSRExitStorePhys;
259	/** Virtual address of the MSR exit store page (guest MSRs). */
260	R0PTRTYPE(uint8_t *) pMSRExitStore;
261
262	/** R0 memory object for the MSR exit load page (host MSRs). */
263	RTR0MEMOBJ pMemObjMSRExitLoad;
264	/** Physical address of the MSR exit load page (host MSRs). */
265	RTHCPHYS pMSRExitLoadPhys;
266	/** Virtual address of the MSR exit load page (host MSRs). */
267	R0PTRTYPE(uint8_t *) pMSRExitLoad;
268
269	/** Ring 0 handlers for VT-x. */
270	DECLR0CALLBACKMEMBER(void, pfnSetupTaggedTLB, (PVM pVM, PVMCPU pVCpu));
271
272	/** Host CR4 value (set by ring-0 VMX init) */
273	uint64_t hostCR4;
274
275	/** VMX MSR values */
276	struct
277	{
278	uint64_t feature_ctrl;
279	uint64_t vmx_basic_info;
280	VMX_CAPABILITY vmx_pin_ctls;
281	VMX_CAPABILITY vmx_proc_ctls;
282	VMX_CAPABILITY vmx_proc_ctls2;
283	VMX_CAPABILITY vmx_exit;
284	VMX_CAPABILITY vmx_entry;
285	uint64_t vmx_misc;
286	uint64_t vmx_cr0_fixed0;
287	uint64_t vmx_cr0_fixed1;
288	uint64_t vmx_cr4_fixed0;
289	uint64_t vmx_cr4_fixed1;
290	uint64_t vmx_vmcs_enum;
291	uint64_t vmx_eptcaps;
292	} msr;
293
294	/** Flush types for invept & invvpid; they depend on capabilities. */
295	VMX_FLUSH enmFlushPage;
296	VMX_FLUSH enmFlushContext;
297	} vmx;
298
299	struct
300	{
301	/** Set by the ring-0 driver to indicate SVM is supported by the CPU. */
302	bool fSupported;
303	/** Set when we've enabled SVM. */
304	bool fEnabled;
305	/** Set if erratum 170 affects the AMD cpu. */
306	bool fAlwaysFlushTLB;
307	/** Explicit alignment padding to make 32-bit gcc align u64RegisterMask
308	* naturally. */
309	bool padding[1];
310
311	/** R0 memory object for the host VM control block (VMCB). */
312	RTR0MEMOBJ pMemObjVMCBHost;
313	/** Physical address of the host VM control block (VMCB). */
314	RTHCPHYS pVMCBHostPhys;
315	/** Virtual address of the host VM control block (VMCB). */
316	R0PTRTYPE(void *) pVMCBHost;
317
318	/** R0 memory object for the IO bitmap (12kb). */
319	RTR0MEMOBJ pMemObjIOBitmap;
320	/** Physical address of the IO bitmap (12kb). */
321	RTHCPHYS pIOBitmapPhys;
322	/** Virtual address of the IO bitmap. */
323	R0PTRTYPE(void *) pIOBitmap;
324
325	/** R0 memory object for the MSR bitmap (8kb). */
326	RTR0MEMOBJ pMemObjMSRBitmap;
327	/** Physical address of the MSR bitmap (8kb). */
328	RTHCPHYS pMSRBitmapPhys;
329	/** Virtual address of the MSR bitmap. */
330	R0PTRTYPE(void *) pMSRBitmap;
331
332	/** SVM revision. */
333	uint32_t u32Rev;
334
335	/** SVM feature bits from cpuid 0x8000000a */
336	uint32_t u32Features;
337	} svm;
338
339	struct
340	{
341	uint32_t u32AMDFeatureECX;
342	uint32_t u32AMDFeatureEDX;
343	} cpuid;
344
345	/** Saved error from detection */
346	int32_t lLastError;
347
348	/** HWACCMR0Init was run */
349	bool fHWACCMR0Init;
350	} HWACCM;
351	/** Pointer to HWACCM VM instance data. */
352	typedef HWACCM *PHWACCM;
353
354	/**
355	* HWACCM VMCPU Instance data.
356	*/
357	typedef struct HWACCMCPU
358	{
359	/** Old style FPU reporting trap mask override performed (optimization) */
360	bool fFPUOldStyleOverride;
361
362	/** Set if we don't have to flush the TLB on VM entry. */
363	bool fResumeVM;
364
365	/** Set if we need to flush the TLB during the world switch. */
366	bool fForceTLBFlush;
367
368	/** Explicit alignment padding to make 32-bit gcc align u64RegisterMask
369	* naturally. */
370	bool padding[1];
371
372	/** HWACCM_CHANGED_* flags. */
373	RTUINT fContextUseFlags;
374
375	/* Id of the last cpu we were executing code on (NIL_RTCPUID for the first time) */
376	RTCPUID idLastCpu;
377
378	/* TLB flush count */
379	RTUINT cTLBFlushes;
380
381	/* Current ASID in use by the VM */
382	RTUINT uCurrentASID;
383
384	struct
385	{
386	/** R0 memory object for the VM control structure (VMCS). */
387	RTR0MEMOBJ pMemObjVMCS;
388	/** Physical address of the VM control structure (VMCS). */
389	RTHCPHYS pVMCSPhys;
390	/** Virtual address of the VM control structure (VMCS). */
391	R0PTRTYPE(void *) pVMCS;
392
393	/** Ring 0 handlers for VT-x. */
394	DECLR0CALLBACKMEMBER(int, pfnStartVM,(RTHCUINT fResume, PCPUMCTX pCtx, PVM pVM, PVMCPU pVCpu));
395
396	/** Current VMX_VMCS_CTRL_PROC_EXEC_CONTROLS. */
397	uint64_t proc_ctls;
398
399	/** Current CR0 mask. */
400	uint64_t cr0_mask;
401	/** Current CR4 mask. */
402	uint64_t cr4_mask;
403
404	/** Current EPTP. */
405	RTHCPHYS GCPhysEPTP;
406
407	/** Real-mode emulation state. */
408	struct
409	{
410	X86EFLAGS eflags;
411	uint32_t fValid;
412	} RealMode;
413
414	struct
415	{
416	uint64_t u64VMCSPhys;
417	uint32_t ulVMCSRevision;
418	uint32_t ulInstrError;
419	uint32_t ulExitReason;
420	RTCPUID idEnteredCpu;
421	RTCPUID idCurrentCpu;
422	uint32_t padding;
423	} lasterror;
424
425	/** The last known guest paging mode. */
426	PGMMODE enmCurrGuestMode;
427	} vmx;
428
429	struct
430	{
431	/** R0 memory object for the VM control block (VMCB). */
432	RTR0MEMOBJ pMemObjVMCB;
433	/** Physical address of the VM control block (VMCB). */
434	RTHCPHYS pVMCBPhys;
435	/** Virtual address of the VM control block (VMCB). */
436	R0PTRTYPE(void *) pVMCB;
437
438	/** Ring 0 handlers for VT-x. */
439	DECLR0CALLBACKMEMBER(int, pfnVMRun,(RTHCPHYS pVMCBHostPhys, RTHCPHYS pVMCBPhys, PCPUMCTX pCtx));
440
441	} svm;
442
443	/** Event injection state. */
444	struct
445	{
446	uint32_t fPending;
447	uint32_t errCode;
448	uint64_t intInfo;
449	} Event;
450
451	/** Currenty shadow paging mode. */
452	PGMMODE enmShadowMode;
453
454	/** The CPU ID of the CPU currently owning the VMCS. Set in
455	* HWACCMR0Enter and cleared in HWACCMR0Leave. */
456	RTCPUID idEnteredCpu;
457
458	STAMPROFILEADV StatEntry;
459	STAMPROFILEADV StatExit;
460	STAMPROFILEADV StatInGC;
461
462	STAMCOUNTER StatIntInject;
463
464	STAMCOUNTER StatExitShadowNM;
465	STAMCOUNTER StatExitGuestNM;
466	STAMCOUNTER StatExitShadowPF;
467	STAMCOUNTER StatExitGuestPF;
468	STAMCOUNTER StatExitGuestUD;
469	STAMCOUNTER StatExitGuestSS;
470	STAMCOUNTER StatExitGuestNP;
471	STAMCOUNTER StatExitGuestGP;
472	STAMCOUNTER StatExitGuestDE;
473	STAMCOUNTER StatExitGuestDB;
474	STAMCOUNTER StatExitGuestMF;
475	STAMCOUNTER StatExitInvpg;
476	STAMCOUNTER StatExitInvd;
477	STAMCOUNTER StatExitCpuid;
478	STAMCOUNTER StatExitRdtsc;
479	STAMCOUNTER StatExitCRxWrite;
480	STAMCOUNTER StatExitCRxRead;
481	STAMCOUNTER StatExitDRxWrite;
482	STAMCOUNTER StatExitDRxRead;
483	STAMCOUNTER StatExitCLTS;
484	STAMCOUNTER StatExitLMSW;
485	STAMCOUNTER StatExitIOWrite;
486	STAMCOUNTER StatExitIORead;
487	STAMCOUNTER StatExitIOStringWrite;
488	STAMCOUNTER StatExitIOStringRead;
489	STAMCOUNTER StatExitIrqWindow;
490	STAMCOUNTER StatExitMaxResume;
491	STAMCOUNTER StatIntReinject;
492	STAMCOUNTER StatPendingHostIrq;
493
494	STAMCOUNTER StatFlushPageManual;
495	STAMCOUNTER StatFlushPhysPageManual;
496	STAMCOUNTER StatFlushTLBManual;
497	STAMCOUNTER StatFlushPageInvlpg;
498	STAMCOUNTER StatFlushTLBWorldSwitch;
499	STAMCOUNTER StatNoFlushTLBWorldSwitch;
500	STAMCOUNTER StatFlushTLBCRxChange;
501	STAMCOUNTER StatFlushASID;
502	STAMCOUNTER StatFlushTLBInvlpga;
503
504	STAMCOUNTER StatSwitchGuestIrq;
505	STAMCOUNTER StatSwitchToR3;
506
507	STAMCOUNTER StatTSCOffset;
508	STAMCOUNTER StatTSCIntercept;
509
510	STAMCOUNTER StatExitReasonNPF;
511	STAMCOUNTER StatDRxArmed;
512	STAMCOUNTER StatDRxContextSwitch;
513	STAMCOUNTER StatDRxIOCheck;
514
515
516	R3PTRTYPE(PSTAMCOUNTER) paStatExitReason;
517	R0PTRTYPE(PSTAMCOUNTER) paStatExitReasonR0;
518	} HWACCMCPU;
519	/** Pointer to HWACCM VM instance data. */
520	typedef HWACCMCPU *PHWACCMCPU;
521
522
523	#ifdef IN_RING0
524
525	VMMR0DECL(PHWACCM_CPUINFO) HWACCMR0GetCurrentCpu();
526	VMMR0DECL(PHWACCM_CPUINFO) HWACCMR0GetCurrentCpuEx(RTCPUID idCpu);
527
528
529	#ifdef VBOX_STRICT
530	VMMR0DECL(void) HWACCMDumpRegs(PVM pVM, PCPUMCTX pCtx);
531	VMMR0DECL(void) HWACCMR0DumpDescriptor(PX86DESCHC Desc, RTSEL Sel, const char *pszMsg);
532	#else
533	#define HWACCMDumpRegs(a, b) do { } while (0)
534	#define HWACCMR0DumpDescriptor(a, b, c) do { } while (0)
535	#endif
536
537	/* Dummy callback handlers. */
538	VMMR0DECL(int) HWACCMR0DummyEnter(PVM pVM, PVMCPU pVCpu, PHWACCM_CPUINFO pCpu);
539	VMMR0DECL(int) HWACCMR0DummyLeave(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
540	VMMR0DECL(int) HWACCMR0DummyEnableCpu(PHWACCM_CPUINFO pCpu, PVM pVM, void *pvPageCpu, RTHCPHYS pPageCpuPhys);
541	VMMR0DECL(int) HWACCMR0DummyDisableCpu(PHWACCM_CPUINFO pCpu, void *pvPageCpu, RTHCPHYS pPageCpuPhys);
542	VMMR0DECL(int) HWACCMR0DummyInitVM(PVM pVM);
543	VMMR0DECL(int) HWACCMR0DummyTermVM(PVM pVM);
544	VMMR0DECL(int) HWACCMR0DummySetupVM(PVM pVM);
545	VMMR0DECL(int) HWACCMR0DummyRunGuestCode(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
546	VMMR0DECL(int) HWACCMR0DummySaveHostState(PVM pVM, PVMCPU pVCpu);
547	VMMR0DECL(int) HWACCMR0DummyLoadGuestState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
548
549
550	# ifdef VBOX_WITH_HYBIRD_32BIT_KERNEL
551	/**
552	* Gets 64-bit GDTR and IDTR on darwin.
553	* @param pGdtr Where to store the 64-bit GDTR.
554	* @param pIdtr Where to store the 64-bit IDTR.
555	*/
556	DECLASM(void) hwaccmR0Get64bitGDTRandIDTR(PX86XDTR64 pGdtr, PX86XDTR64 pIdtr);
557
558	/**
559	* Gets 64-bit CR3 on darwin.
560	* @returns CR3
561	*/
562	DECLASM(uint64_t) hwaccmR0Get64bitCR3(void);
563	# endif
564
565	#endif /* IN_RING0 */
566
567	/** @} */
568
569	__END_DECLS
570
571	#endif
572

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source: vbox/trunk/src/VBox/VMM/HWACCMInternal.h@ 14845

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