HWACCMInternal.h@ 14867

Last change on this file since 14867 was 14851, checked in by vboxsync, 16 years ago
More switcher target functions for FPU and debug state updates.
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File size: 21.4 KB

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1	/* $Id: HWACCMInternal.h 14851 2008-12-01 11:17:50Z vboxsync $ */
2	/** @file
3	* HWACCM - Internal header file.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22	#ifndef ___HWACCMInternal_h
23	#define ___HWACCMInternal_h
24
25	#include <VBox/cdefs.h>
26	#include <VBox/types.h>
27	#include <VBox/em.h>
28	#include <VBox/stam.h>
29	#include <VBox/dis.h>
30	#include <VBox/hwaccm.h>
31	#include <VBox/pgm.h>
32	#include <VBox/cpum.h>
33	#include <iprt/memobj.h>
34	#include <iprt/cpuset.h>
35	#include <iprt/mp.h>
36
37	#if HC_ARCH_BITS == 64 \|\| defined (VBOX_WITH_64_BITS_GUESTS)
38	/* Enable 64 bits guest support. */
39	# define VBOX_ENABLE_64_BITS_GUESTS
40	#endif
41
42	#define HWACCM_VMX_EMULATE_REALMODE
43	#define HWACCM_VTX_WITH_EPT
44	#define HWACCM_VTX_WITH_VPID
45
46	__BEGIN_DECLS
47
48
49	/** @defgroup grp_hwaccm_int Internal
50	* @ingroup grp_hwaccm
51	* @internal
52	* @{
53	*/
54
55
56	/** Maximum number of exit reason statistics counters. */
57	#define MAX_EXITREASON_STAT 0x100
58	#define MASK_EXITREASON_STAT 0xff
59
60	/** @name Changed flags
61	* These flags are used to keep track of which important registers that
62	* have been changed since last they were reset.
63	* @{
64	*/
65	#define HWACCM_CHANGED_GUEST_FPU RT_BIT(0)
66	#define HWACCM_CHANGED_GUEST_CR0 RT_BIT(1)
67	#define HWACCM_CHANGED_GUEST_CR3 RT_BIT(2)
68	#define HWACCM_CHANGED_GUEST_CR4 RT_BIT(3)
69	#define HWACCM_CHANGED_GUEST_GDTR RT_BIT(4)
70	#define HWACCM_CHANGED_GUEST_IDTR RT_BIT(5)
71	#define HWACCM_CHANGED_GUEST_LDTR RT_BIT(6)
72	#define HWACCM_CHANGED_GUEST_TR RT_BIT(7)
73	#define HWACCM_CHANGED_GUEST_SYSENTER_MSR RT_BIT(8)
74	#define HWACCM_CHANGED_GUEST_SEGMENT_REGS RT_BIT(9)
75	#define HWACCM_CHANGED_GUEST_DEBUG RT_BIT(10)
76	#define HWACCM_CHANGED_HOST_CONTEXT RT_BIT(11)
77
78	#define HWACCM_CHANGED_ALL ( HWACCM_CHANGED_GUEST_SEGMENT_REGS \
79	\| HWACCM_CHANGED_GUEST_CR0 \
80	\| HWACCM_CHANGED_GUEST_CR3 \
81	\| HWACCM_CHANGED_GUEST_CR4 \
82	\| HWACCM_CHANGED_GUEST_GDTR \
83	\| HWACCM_CHANGED_GUEST_IDTR \
84	\| HWACCM_CHANGED_GUEST_LDTR \
85	\| HWACCM_CHANGED_GUEST_TR \
86	\| HWACCM_CHANGED_GUEST_SYSENTER_MSR \
87	\| HWACCM_CHANGED_GUEST_FPU \
88	\| HWACCM_CHANGED_GUEST_DEBUG \
89	\| HWACCM_CHANGED_HOST_CONTEXT)
90
91	#define HWACCM_CHANGED_ALL_GUEST ( HWACCM_CHANGED_GUEST_SEGMENT_REGS \
92	\| HWACCM_CHANGED_GUEST_CR0 \
93	\| HWACCM_CHANGED_GUEST_CR3 \
94	\| HWACCM_CHANGED_GUEST_CR4 \
95	\| HWACCM_CHANGED_GUEST_GDTR \
96	\| HWACCM_CHANGED_GUEST_IDTR \
97	\| HWACCM_CHANGED_GUEST_LDTR \
98	\| HWACCM_CHANGED_GUEST_TR \
99	\| HWACCM_CHANGED_GUEST_SYSENTER_MSR \
100	\| HWACCM_CHANGED_GUEST_DEBUG \
101	\| HWACCM_CHANGED_GUEST_FPU)
102
103	/** @} */
104
105	/** @name Intercepted traps
106	* Traps that need to be intercepted so we can correctly dispatch them to the guest if required.
107	* Currently #NM and #PF only
108	*/
109	#ifdef VBOX_STRICT
110	#define HWACCM_VMX_TRAP_MASK RT_BIT(X86_XCPT_DE) \| RT_BIT(X86_XCPT_NM) \| RT_BIT(X86_XCPT_PF) \| RT_BIT(X86_XCPT_UD) \| RT_BIT(X86_XCPT_NP) \| RT_BIT(X86_XCPT_SS) \| RT_BIT(X86_XCPT_GP) \| RT_BIT(X86_XCPT_MF)
111	#define HWACCM_SVM_TRAP_MASK HWACCM_VMX_TRAP_MASK
112	#else
113	#define HWACCM_VMX_TRAP_MASK RT_BIT(X86_XCPT_NM) \| RT_BIT(X86_XCPT_PF)
114	#define HWACCM_SVM_TRAP_MASK RT_BIT(X86_XCPT_NM) \| RT_BIT(X86_XCPT_PF)
115	#endif
116	/* All exceptions have to be intercept in emulated real-mode (minues NM & PF as they are always intercepted. */
117	#define HWACCM_VMX_TRAP_MASK_REALMODE RT_BIT(X86_XCPT_DE) \| RT_BIT(X86_XCPT_DB) \| RT_BIT(X86_XCPT_NMI) \| RT_BIT(X86_XCPT_BP) \| RT_BIT(X86_XCPT_OF) \| RT_BIT(X86_XCPT_BR) \| RT_BIT(X86_XCPT_UD) \| RT_BIT(X86_XCPT_DF) \| RT_BIT(X86_XCPT_CO_SEG_OVERRUN) \| RT_BIT(X86_XCPT_TS) \| RT_BIT(X86_XCPT_NP) \| RT_BIT(X86_XCPT_SS) \| RT_BIT(X86_XCPT_GP) \| RT_BIT(X86_XCPT_MF) \| RT_BIT(X86_XCPT_AC) \| RT_BIT(X86_XCPT_MC) \| RT_BIT(X86_XCPT_XF)
118	/** @} */
119
120
121	/** Maxium resume loops allowed in ring 0 (safety precaution) */
122	#define HWACCM_MAX_RESUME_LOOPS 1024
123
124	/** Size for the EPT identity page table (1024 4 MB pages to cover the entire address space). */
125	#define HWACCM_EPT_IDENTITY_PG_TABLE_SIZE PAGE_SIZE
126	/** Size of the TSS structure + 2 pages for the IO bitmap + end byte. */
127	#define HWACCM_VTX_TSS_SIZE (sizeof(VBOXTSS) + 2*PAGE_SIZE + 1)
128	/** Total guest mapped memory needed. */
129	#define HWACCM_VTX_TOTAL_DEVHEAP_MEM (HWACCM_EPT_IDENTITY_PG_TABLE_SIZE + HWACCM_VTX_TSS_SIZE)
130
131	/** HWACCM SSM version
132	*/
133	#define HWACCM_SSM_VERSION 3
134
135	/* Per-cpu information. (host) */
136	typedef struct
137	{
138	RTCPUID idCpu;
139
140	RTR0MEMOBJ pMemObj;
141	/* Current ASID (AMD-V)/VPID (Intel) */
142	uint32_t uCurrentASID;
143	/* TLB flush count */
144	uint32_t cTLBFlushes;
145
146	/* Set the first time a cpu is used to make sure we start with a clean TLB. */
147	bool fFlushTLB;
148
149	/** Configured for VT-x or AMD-V. */
150	bool fConfigured;
151
152	/** In use by our code. (for power suspend) */
153	volatile bool fInUse;
154	} HWACCM_CPUINFO;
155	typedef HWACCM_CPUINFO *PHWACCM_CPUINFO;
156
157	/* VT-x capability qword. */
158	typedef union
159	{
160	struct
161	{
162	uint32_t disallowed0;
163	uint32_t allowed1;
164	} n;
165	uint64_t u;
166	} VMX_CAPABILITY;
167
168	/**
169	* HWACCM VM Instance data.
170	* Changes to this must checked against the padding of the cfgm union in VM!
171	*/
172	typedef struct HWACCM
173	{
174	/** Set when we've initialized VMX or SVM. */
175	bool fInitialized;
176
177	/** Set when we're using VMX/SVN at that moment. */
178	bool fActive;
179
180	/** Set when hardware acceleration is allowed. */
181	bool fAllowed;
182
183	/** Set if nested paging is enabled. */
184	bool fNestedPaging;
185
186	/** Set if nested paging is allowed. */
187	bool fAllowNestedPaging;
188
189	/** Set if we're supposed to inject an NMI. */
190	bool fInjectNMI;
191
192	/** Explicit alignment padding to make 32-bit gcc align u64RegisterMask
193	* naturally. */
194	bool padding[2];
195
196	/** And mask for copying register contents. */
197	uint64_t u64RegisterMask;
198
199	/** Maximum ASID allowed. */
200	RTUINT uMaxASID;
201
202	#if HC_ARCH_BITS == 32
203	/** 32 to 64 bits switcher entrypoint. */
204	RTR0PTR pfnHost32ToGuest64R0;
205
206	/* AMD-V 64 bits vmrun handler */
207	RTRCPTR pfnSVMGCVMRun64;
208
209	/* VT-x 64 bits vmlaunch handler */
210	RTRCPTR pfnVMXGCStartVM64;
211
212	/* RC handler to setup the 64 bits FPU state. */
213	RTRCPTR pfnSetupFPU64;
214
215	/* RC handler to setup the 64 bits debug state. */
216	RTRCPTR pfnSetupDebug64;
217	#endif
218
219	struct
220	{
221	/** Set by the ring-0 driver to indicate VMX is supported by the CPU. */
222	bool fSupported;
223
224	/** Set when we've enabled VMX. */
225	bool fEnabled;
226
227	/** Set if VPID is supported. */
228	bool fVPID;
229
230	/** Set if VT-x VPID is allowed. */
231	bool fAllowVPID;
232
233	/** Virtual address of the TSS page used for real mode emulation. */
234	R3PTRTYPE(PVBOXTSS) pRealModeTSS;
235
236	/** Virtual address of the identity page table used for real mode and protected mode without paging emulation in EPT mode. */
237	R3PTRTYPE(PX86PD) pNonPagingModeEPTPageTable;
238
239	/** R0 memory object for the virtual APIC mmio cache. */
240	RTR0MEMOBJ pMemObjAPIC;
241	/** Physical address of the virtual APIC mmio cache. */
242	RTHCPHYS pAPICPhys;
243	/** Virtual address of the virtual APIC mmio cache. */
244	R0PTRTYPE(uint8_t *) pAPIC;
245
246	/** R0 memory object for the MSR bitmap (1 page). */
247	RTR0MEMOBJ pMemObjMSRBitmap;
248	/** Physical address of the MSR bitmap (1 page). */
249	RTHCPHYS pMSRBitmapPhys;
250	/** Virtual address of the MSR bitmap (1 page). */
251	R0PTRTYPE(uint8_t *) pMSRBitmap;
252
253	/** R0 memory object for the MSR entry load page (guest MSRs). */
254	RTR0MEMOBJ pMemObjMSREntryLoad;
255	/** Physical address of the MSR entry load page (guest MSRs). */
256	RTHCPHYS pMSREntryLoadPhys;
257	/** Virtual address of the MSR entry load page (guest MSRs). */
258	R0PTRTYPE(uint8_t *) pMSREntryLoad;
259
260	/** R0 memory object for the MSR exit store page (guest MSRs). */
261	RTR0MEMOBJ pMemObjMSRExitStore;
262	/** Physical address of the MSR exit store page (guest MSRs). */
263	RTHCPHYS pMSRExitStorePhys;
264	/** Virtual address of the MSR exit store page (guest MSRs). */
265	R0PTRTYPE(uint8_t *) pMSRExitStore;
266
267	/** R0 memory object for the MSR exit load page (host MSRs). */
268	RTR0MEMOBJ pMemObjMSRExitLoad;
269	/** Physical address of the MSR exit load page (host MSRs). */
270	RTHCPHYS pMSRExitLoadPhys;
271	/** Virtual address of the MSR exit load page (host MSRs). */
272	R0PTRTYPE(uint8_t *) pMSRExitLoad;
273
274	/** Ring 0 handlers for VT-x. */
275	DECLR0CALLBACKMEMBER(void, pfnSetupTaggedTLB, (PVM pVM, PVMCPU pVCpu));
276
277	/** Host CR4 value (set by ring-0 VMX init) */
278	uint64_t hostCR4;
279
280	/** VMX MSR values */
281	struct
282	{
283	uint64_t feature_ctrl;
284	uint64_t vmx_basic_info;
285	VMX_CAPABILITY vmx_pin_ctls;
286	VMX_CAPABILITY vmx_proc_ctls;
287	VMX_CAPABILITY vmx_proc_ctls2;
288	VMX_CAPABILITY vmx_exit;
289	VMX_CAPABILITY vmx_entry;
290	uint64_t vmx_misc;
291	uint64_t vmx_cr0_fixed0;
292	uint64_t vmx_cr0_fixed1;
293	uint64_t vmx_cr4_fixed0;
294	uint64_t vmx_cr4_fixed1;
295	uint64_t vmx_vmcs_enum;
296	uint64_t vmx_eptcaps;
297	} msr;
298
299	/** Flush types for invept & invvpid; they depend on capabilities. */
300	VMX_FLUSH enmFlushPage;
301	VMX_FLUSH enmFlushContext;
302	} vmx;
303
304	struct
305	{
306	/** Set by the ring-0 driver to indicate SVM is supported by the CPU. */
307	bool fSupported;
308	/** Set when we've enabled SVM. */
309	bool fEnabled;
310	/** Set if erratum 170 affects the AMD cpu. */
311	bool fAlwaysFlushTLB;
312	/** Explicit alignment padding to make 32-bit gcc align u64RegisterMask
313	* naturally. */
314	bool padding[1];
315
316	/** R0 memory object for the host VM control block (VMCB). */
317	RTR0MEMOBJ pMemObjVMCBHost;
318	/** Physical address of the host VM control block (VMCB). */
319	RTHCPHYS pVMCBHostPhys;
320	/** Virtual address of the host VM control block (VMCB). */
321	R0PTRTYPE(void *) pVMCBHost;
322
323	/** R0 memory object for the IO bitmap (12kb). */
324	RTR0MEMOBJ pMemObjIOBitmap;
325	/** Physical address of the IO bitmap (12kb). */
326	RTHCPHYS pIOBitmapPhys;
327	/** Virtual address of the IO bitmap. */
328	R0PTRTYPE(void *) pIOBitmap;
329
330	/** R0 memory object for the MSR bitmap (8kb). */
331	RTR0MEMOBJ pMemObjMSRBitmap;
332	/** Physical address of the MSR bitmap (8kb). */
333	RTHCPHYS pMSRBitmapPhys;
334	/** Virtual address of the MSR bitmap. */
335	R0PTRTYPE(void *) pMSRBitmap;
336
337	/** SVM revision. */
338	uint32_t u32Rev;
339
340	/** SVM feature bits from cpuid 0x8000000a */
341	uint32_t u32Features;
342	} svm;
343
344	struct
345	{
346	uint32_t u32AMDFeatureECX;
347	uint32_t u32AMDFeatureEDX;
348	} cpuid;
349
350	/** Saved error from detection */
351	int32_t lLastError;
352
353	/** HWACCMR0Init was run */
354	bool fHWACCMR0Init;
355	} HWACCM;
356	/** Pointer to HWACCM VM instance data. */
357	typedef HWACCM *PHWACCM;
358
359	/**
360	* HWACCM VMCPU Instance data.
361	*/
362	typedef struct HWACCMCPU
363	{
364	/** Old style FPU reporting trap mask override performed (optimization) */
365	bool fFPUOldStyleOverride;
366
367	/** Set if we don't have to flush the TLB on VM entry. */
368	bool fResumeVM;
369
370	/** Set if we need to flush the TLB during the world switch. */
371	bool fForceTLBFlush;
372
373	/** Explicit alignment padding to make 32-bit gcc align u64RegisterMask
374	* naturally. */
375	bool padding[1];
376
377	/** HWACCM_CHANGED_* flags. */
378	RTUINT fContextUseFlags;
379
380	/* Id of the last cpu we were executing code on (NIL_RTCPUID for the first time) */
381	RTCPUID idLastCpu;
382
383	/* TLB flush count */
384	RTUINT cTLBFlushes;
385
386	/* Current ASID in use by the VM */
387	RTUINT uCurrentASID;
388
389	struct
390	{
391	/** R0 memory object for the VM control structure (VMCS). */
392	RTR0MEMOBJ pMemObjVMCS;
393	/** Physical address of the VM control structure (VMCS). */
394	RTHCPHYS pVMCSPhys;
395	/** Virtual address of the VM control structure (VMCS). */
396	R0PTRTYPE(void *) pVMCS;
397
398	/** Ring 0 handlers for VT-x. */
399	DECLR0CALLBACKMEMBER(int, pfnStartVM,(RTHCUINT fResume, PCPUMCTX pCtx, PVM pVM, PVMCPU pVCpu));
400
401	/** Current VMX_VMCS_CTRL_PROC_EXEC_CONTROLS. */
402	uint64_t proc_ctls;
403
404	/** Current CR0 mask. */
405	uint64_t cr0_mask;
406	/** Current CR4 mask. */
407	uint64_t cr4_mask;
408
409	/** Current EPTP. */
410	RTHCPHYS GCPhysEPTP;
411
412	/** Real-mode emulation state. */
413	struct
414	{
415	X86EFLAGS eflags;
416	uint32_t fValid;
417	} RealMode;
418
419	struct
420	{
421	uint64_t u64VMCSPhys;
422	uint32_t ulVMCSRevision;
423	uint32_t ulInstrError;
424	uint32_t ulExitReason;
425	RTCPUID idEnteredCpu;
426	RTCPUID idCurrentCpu;
427	uint32_t padding;
428	} lasterror;
429
430	/** The last known guest paging mode. */
431	PGMMODE enmCurrGuestMode;
432	} vmx;
433
434	struct
435	{
436	/** R0 memory object for the VM control block (VMCB). */
437	RTR0MEMOBJ pMemObjVMCB;
438	/** Physical address of the VM control block (VMCB). */
439	RTHCPHYS pVMCBPhys;
440	/** Virtual address of the VM control block (VMCB). */
441	R0PTRTYPE(void *) pVMCB;
442
443	/** Ring 0 handlers for VT-x. */
444	DECLR0CALLBACKMEMBER(int, pfnVMRun,(RTHCPHYS pVMCBHostPhys, RTHCPHYS pVMCBPhys, PCPUMCTX pCtx));
445
446	} svm;
447
448	/** Event injection state. */
449	struct
450	{
451	uint32_t fPending;
452	uint32_t errCode;
453	uint64_t intInfo;
454	} Event;
455
456	/** Currenty shadow paging mode. */
457	PGMMODE enmShadowMode;
458
459	/** The CPU ID of the CPU currently owning the VMCS. Set in
460	* HWACCMR0Enter and cleared in HWACCMR0Leave. */
461	RTCPUID idEnteredCpu;
462
463	STAMPROFILEADV StatEntry;
464	STAMPROFILEADV StatExit;
465	STAMPROFILEADV StatInGC;
466
467	STAMCOUNTER StatIntInject;
468
469	STAMCOUNTER StatExitShadowNM;
470	STAMCOUNTER StatExitGuestNM;
471	STAMCOUNTER StatExitShadowPF;
472	STAMCOUNTER StatExitGuestPF;
473	STAMCOUNTER StatExitGuestUD;
474	STAMCOUNTER StatExitGuestSS;
475	STAMCOUNTER StatExitGuestNP;
476	STAMCOUNTER StatExitGuestGP;
477	STAMCOUNTER StatExitGuestDE;
478	STAMCOUNTER StatExitGuestDB;
479	STAMCOUNTER StatExitGuestMF;
480	STAMCOUNTER StatExitInvpg;
481	STAMCOUNTER StatExitInvd;
482	STAMCOUNTER StatExitCpuid;
483	STAMCOUNTER StatExitRdtsc;
484	STAMCOUNTER StatExitCRxWrite;
485	STAMCOUNTER StatExitCRxRead;
486	STAMCOUNTER StatExitDRxWrite;
487	STAMCOUNTER StatExitDRxRead;
488	STAMCOUNTER StatExitCLTS;
489	STAMCOUNTER StatExitLMSW;
490	STAMCOUNTER StatExitIOWrite;
491	STAMCOUNTER StatExitIORead;
492	STAMCOUNTER StatExitIOStringWrite;
493	STAMCOUNTER StatExitIOStringRead;
494	STAMCOUNTER StatExitIrqWindow;
495	STAMCOUNTER StatExitMaxResume;
496	STAMCOUNTER StatIntReinject;
497	STAMCOUNTER StatPendingHostIrq;
498
499	STAMCOUNTER StatFlushPageManual;
500	STAMCOUNTER StatFlushPhysPageManual;
501	STAMCOUNTER StatFlushTLBManual;
502	STAMCOUNTER StatFlushPageInvlpg;
503	STAMCOUNTER StatFlushTLBWorldSwitch;
504	STAMCOUNTER StatNoFlushTLBWorldSwitch;
505	STAMCOUNTER StatFlushTLBCRxChange;
506	STAMCOUNTER StatFlushASID;
507	STAMCOUNTER StatFlushTLBInvlpga;
508
509	STAMCOUNTER StatSwitchGuestIrq;
510	STAMCOUNTER StatSwitchToR3;
511
512	STAMCOUNTER StatTSCOffset;
513	STAMCOUNTER StatTSCIntercept;
514
515	STAMCOUNTER StatExitReasonNPF;
516	STAMCOUNTER StatDRxArmed;
517	STAMCOUNTER StatDRxContextSwitch;
518	STAMCOUNTER StatDRxIOCheck;
519
520
521	R3PTRTYPE(PSTAMCOUNTER) paStatExitReason;
522	R0PTRTYPE(PSTAMCOUNTER) paStatExitReasonR0;
523	} HWACCMCPU;
524	/** Pointer to HWACCM VM instance data. */
525	typedef HWACCMCPU *PHWACCMCPU;
526
527
528	#ifdef IN_RING0
529
530	VMMR0DECL(PHWACCM_CPUINFO) HWACCMR0GetCurrentCpu();
531	VMMR0DECL(PHWACCM_CPUINFO) HWACCMR0GetCurrentCpuEx(RTCPUID idCpu);
532
533
534	#ifdef VBOX_STRICT
535	VMMR0DECL(void) HWACCMDumpRegs(PVM pVM, PCPUMCTX pCtx);
536	VMMR0DECL(void) HWACCMR0DumpDescriptor(PX86DESCHC Desc, RTSEL Sel, const char *pszMsg);
537	#else
538	#define HWACCMDumpRegs(a, b) do { } while (0)
539	#define HWACCMR0DumpDescriptor(a, b, c) do { } while (0)
540	#endif
541
542	/* Dummy callback handlers. */
543	VMMR0DECL(int) HWACCMR0DummyEnter(PVM pVM, PVMCPU pVCpu, PHWACCM_CPUINFO pCpu);
544	VMMR0DECL(int) HWACCMR0DummyLeave(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
545	VMMR0DECL(int) HWACCMR0DummyEnableCpu(PHWACCM_CPUINFO pCpu, PVM pVM, void *pvPageCpu, RTHCPHYS pPageCpuPhys);
546	VMMR0DECL(int) HWACCMR0DummyDisableCpu(PHWACCM_CPUINFO pCpu, void *pvPageCpu, RTHCPHYS pPageCpuPhys);
547	VMMR0DECL(int) HWACCMR0DummyInitVM(PVM pVM);
548	VMMR0DECL(int) HWACCMR0DummyTermVM(PVM pVM);
549	VMMR0DECL(int) HWACCMR0DummySetupVM(PVM pVM);
550	VMMR0DECL(int) HWACCMR0DummyRunGuestCode(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
551	VMMR0DECL(int) HWACCMR0DummySaveHostState(PVM pVM, PVMCPU pVCpu);
552	VMMR0DECL(int) HWACCMR0DummyLoadGuestState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
553
554
555	# ifdef VBOX_WITH_HYBIRD_32BIT_KERNEL
556	/**
557	* Gets 64-bit GDTR and IDTR on darwin.
558	* @param pGdtr Where to store the 64-bit GDTR.
559	* @param pIdtr Where to store the 64-bit IDTR.
560	*/
561	DECLASM(void) hwaccmR0Get64bitGDTRandIDTR(PX86XDTR64 pGdtr, PX86XDTR64 pIdtr);
562
563	/**
564	* Gets 64-bit CR3 on darwin.
565	* @returns CR3
566	*/
567	DECLASM(uint64_t) hwaccmR0Get64bitCR3(void);
568	# endif
569
570	#endif /* IN_RING0 */
571
572	/** @} */
573
574	__END_DECLS
575
576	#endif
577

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source: vbox/trunk/src/VBox/VMM/HWACCMInternal.h@ 14867

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