HWACCMInternal.h@ 15371

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1	/* $Id: HWACCMInternal.h 15371 2008-12-12 14:41:28Z vboxsync $ */
2	/** @file
3	* HWACCM - Internal header file.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22	#ifndef ___HWACCMInternal_h
23	#define ___HWACCMInternal_h
24
25	#include <VBox/cdefs.h>
26	#include <VBox/types.h>
27	#include <VBox/em.h>
28	#include <VBox/stam.h>
29	#include <VBox/dis.h>
30	#include <VBox/hwaccm.h>
31	#include <VBox/pgm.h>
32	#include <VBox/cpum.h>
33	#include <iprt/memobj.h>
34	#include <iprt/cpuset.h>
35	#include <iprt/mp.h>
36
37	#if HC_ARCH_BITS == 64 // \|\| defined (VBOX_WITH_64_BITS_GUESTS)
38	/* Enable 64 bits guest support. */
39	# define VBOX_ENABLE_64_BITS_GUESTS
40	#endif
41
42	#define VMX_USE_CACHED_VMCS_ACCESSES
43	#define HWACCM_VMX_EMULATE_REALMODE
44	#define HWACCM_VTX_WITH_EPT
45	#define HWACCM_VTX_WITH_VPID
46
47	__BEGIN_DECLS
48
49
50	/** @defgroup grp_hwaccm_int Internal
51	* @ingroup grp_hwaccm
52	* @internal
53	* @{
54	*/
55
56
57	/** Maximum number of exit reason statistics counters. */
58	#define MAX_EXITREASON_STAT 0x100
59	#define MASK_EXITREASON_STAT 0xff
60
61	/** @name Changed flags
62	* These flags are used to keep track of which important registers that
63	* have been changed since last they were reset.
64	* @{
65	*/
66	#define HWACCM_CHANGED_GUEST_FPU RT_BIT(0)
67	#define HWACCM_CHANGED_GUEST_CR0 RT_BIT(1)
68	#define HWACCM_CHANGED_GUEST_CR3 RT_BIT(2)
69	#define HWACCM_CHANGED_GUEST_CR4 RT_BIT(3)
70	#define HWACCM_CHANGED_GUEST_GDTR RT_BIT(4)
71	#define HWACCM_CHANGED_GUEST_IDTR RT_BIT(5)
72	#define HWACCM_CHANGED_GUEST_LDTR RT_BIT(6)
73	#define HWACCM_CHANGED_GUEST_TR RT_BIT(7)
74	#define HWACCM_CHANGED_GUEST_SYSENTER_MSR RT_BIT(8)
75	#define HWACCM_CHANGED_GUEST_SEGMENT_REGS RT_BIT(9)
76	#define HWACCM_CHANGED_GUEST_DEBUG RT_BIT(10)
77	#define HWACCM_CHANGED_HOST_CONTEXT RT_BIT(11)
78
79	#define HWACCM_CHANGED_ALL ( HWACCM_CHANGED_GUEST_SEGMENT_REGS \
80	\| HWACCM_CHANGED_GUEST_CR0 \
81	\| HWACCM_CHANGED_GUEST_CR3 \
82	\| HWACCM_CHANGED_GUEST_CR4 \
83	\| HWACCM_CHANGED_GUEST_GDTR \
84	\| HWACCM_CHANGED_GUEST_IDTR \
85	\| HWACCM_CHANGED_GUEST_LDTR \
86	\| HWACCM_CHANGED_GUEST_TR \
87	\| HWACCM_CHANGED_GUEST_SYSENTER_MSR \
88	\| HWACCM_CHANGED_GUEST_FPU \
89	\| HWACCM_CHANGED_GUEST_DEBUG \
90	\| HWACCM_CHANGED_HOST_CONTEXT)
91
92	#define HWACCM_CHANGED_ALL_GUEST ( HWACCM_CHANGED_GUEST_SEGMENT_REGS \
93	\| HWACCM_CHANGED_GUEST_CR0 \
94	\| HWACCM_CHANGED_GUEST_CR3 \
95	\| HWACCM_CHANGED_GUEST_CR4 \
96	\| HWACCM_CHANGED_GUEST_GDTR \
97	\| HWACCM_CHANGED_GUEST_IDTR \
98	\| HWACCM_CHANGED_GUEST_LDTR \
99	\| HWACCM_CHANGED_GUEST_TR \
100	\| HWACCM_CHANGED_GUEST_SYSENTER_MSR \
101	\| HWACCM_CHANGED_GUEST_DEBUG \
102	\| HWACCM_CHANGED_GUEST_FPU)
103
104	/** @} */
105
106	/** @name Intercepted traps
107	* Traps that need to be intercepted so we can correctly dispatch them to the guest if required.
108	* Currently #NM and #PF only
109	*/
110	#ifdef VBOX_STRICT
111	#define HWACCM_VMX_TRAP_MASK RT_BIT(X86_XCPT_DE) \| RT_BIT(X86_XCPT_NM) \| RT_BIT(X86_XCPT_PF) \| RT_BIT(X86_XCPT_UD) \| RT_BIT(X86_XCPT_NP) \| RT_BIT(X86_XCPT_SS) \| RT_BIT(X86_XCPT_GP) \| RT_BIT(X86_XCPT_MF)
112	#define HWACCM_SVM_TRAP_MASK HWACCM_VMX_TRAP_MASK
113	#else
114	#define HWACCM_VMX_TRAP_MASK RT_BIT(X86_XCPT_NM) \| RT_BIT(X86_XCPT_PF)
115	#define HWACCM_SVM_TRAP_MASK RT_BIT(X86_XCPT_NM) \| RT_BIT(X86_XCPT_PF)
116	#endif
117	/* All exceptions have to be intercept in emulated real-mode (minues NM & PF as they are always intercepted. */
118	#define HWACCM_VMX_TRAP_MASK_REALMODE RT_BIT(X86_XCPT_DE) \| RT_BIT(X86_XCPT_DB) \| RT_BIT(X86_XCPT_NMI) \| RT_BIT(X86_XCPT_BP) \| RT_BIT(X86_XCPT_OF) \| RT_BIT(X86_XCPT_BR) \| RT_BIT(X86_XCPT_UD) \| RT_BIT(X86_XCPT_DF) \| RT_BIT(X86_XCPT_CO_SEG_OVERRUN) \| RT_BIT(X86_XCPT_TS) \| RT_BIT(X86_XCPT_NP) \| RT_BIT(X86_XCPT_SS) \| RT_BIT(X86_XCPT_GP) \| RT_BIT(X86_XCPT_MF) \| RT_BIT(X86_XCPT_AC) \| RT_BIT(X86_XCPT_MC) \| RT_BIT(X86_XCPT_XF)
119	/** @} */
120
121
122	/** Maxium resume loops allowed in ring 0 (safety precaution) */
123	#define HWACCM_MAX_RESUME_LOOPS 1024
124
125	/** Size for the EPT identity page table (1024 4 MB pages to cover the entire address space). */
126	#define HWACCM_EPT_IDENTITY_PG_TABLE_SIZE PAGE_SIZE
127	/** Size of the TSS structure + 2 pages for the IO bitmap + end byte. */
128	#define HWACCM_VTX_TSS_SIZE (sizeof(VBOXTSS) + 2*PAGE_SIZE + 1)
129	/** Total guest mapped memory needed. */
130	#define HWACCM_VTX_TOTAL_DEVHEAP_MEM (HWACCM_EPT_IDENTITY_PG_TABLE_SIZE + HWACCM_VTX_TSS_SIZE)
131
132	/** HWACCM SSM version
133	*/
134	#define HWACCM_SSM_VERSION 3
135
136	/* Per-cpu information. (host) */
137	typedef struct
138	{
139	RTCPUID idCpu;
140
141	RTR0MEMOBJ pMemObj;
142	/* Current ASID (AMD-V)/VPID (Intel) */
143	uint32_t uCurrentASID;
144	/* TLB flush count */
145	uint32_t cTLBFlushes;
146
147	/* Set the first time a cpu is used to make sure we start with a clean TLB. */
148	bool fFlushTLB;
149
150	/** Configured for VT-x or AMD-V. */
151	bool fConfigured;
152
153	/** In use by our code. (for power suspend) */
154	volatile bool fInUse;
155	} HWACCM_CPUINFO;
156	typedef HWACCM_CPUINFO *PHWACCM_CPUINFO;
157
158	/* VT-x capability qword. */
159	typedef union
160	{
161	struct
162	{
163	uint32_t disallowed0;
164	uint32_t allowed1;
165	} n;
166	uint64_t u;
167	} VMX_CAPABILITY;
168
169	/**
170	* Switcher function, HC to RC.
171	*
172	* @param pVM The VM handle.
173	* @returns Return code indicating the action to take.
174	*/
175	typedef DECLASMTYPE(int) FNHWACCMSWITCHERHC(PVM pVM);
176	/** Pointer to switcher function. */
177	typedef FNHWACCMSWITCHERHC *PFNHWACCMSWITCHERHC;
178
179	/**
180	* HWACCM VM Instance data.
181	* Changes to this must checked against the padding of the cfgm union in VM!
182	*/
183	typedef struct HWACCM
184	{
185	/** Set when we've initialized VMX or SVM. */
186	bool fInitialized;
187
188	/** Set when we're using VMX/SVN at that moment. */
189	bool fActive;
190
191	/** Set when hardware acceleration is allowed. */
192	bool fAllowed;
193
194	/** Set if nested paging is enabled. */
195	bool fNestedPaging;
196
197	/** Set if nested paging is allowed. */
198	bool fAllowNestedPaging;
199
200	/** Set if we're supposed to inject an NMI. */
201	bool fInjectNMI;
202
203	/** Explicit alignment padding to make 32-bit gcc align u64RegisterMask
204	* naturally. */
205	bool padding[2];
206
207	/** And mask for copying register contents. */
208	uint64_t u64RegisterMask;
209
210	/** Maximum ASID allowed. */
211	RTUINT uMaxASID;
212
213	#if HC_ARCH_BITS == 32
214	/** 32 to 64 bits switcher entrypoint. */
215	R0PTRTYPE(PFNHWACCMSWITCHERHC) pfnHost32ToGuest64R0;
216
217	/* AMD-V 64 bits vmrun handler */
218	RTRCPTR pfnSVMGCVMRun64;
219
220	/* VT-x 64 bits vmlaunch handler */
221	RTRCPTR pfnVMXGCStartVM64;
222
223	/* RC handler to setup the 64 bits FPU state. */
224	RTRCPTR pfnSaveGuestFPU64;
225
226	/* RC handler to setup the 64 bits debug state. */
227	RTRCPTR pfnSaveGuestDebug64;
228
229	# ifdef DEBUG
230	/* Test handler */
231	RTRCPTR pfnTest64;
232
233	RTRCPTR uAlignment[1];
234	# endif
235	#endif
236
237	struct
238	{
239	/** Set by the ring-0 driver to indicate VMX is supported by the CPU. */
240	bool fSupported;
241
242	/** Set when we've enabled VMX. */
243	bool fEnabled;
244
245	/** Set if VPID is supported. */
246	bool fVPID;
247
248	/** Set if VT-x VPID is allowed. */
249	bool fAllowVPID;
250
251	/** Virtual address of the TSS page used for real mode emulation. */
252	R3PTRTYPE(PVBOXTSS) pRealModeTSS;
253
254	/** Virtual address of the identity page table used for real mode and protected mode without paging emulation in EPT mode. */
255	R3PTRTYPE(PX86PD) pNonPagingModeEPTPageTable;
256
257	/** R0 memory object for the virtual APIC mmio cache. */
258	RTR0MEMOBJ pMemObjAPIC;
259	/** Physical address of the virtual APIC mmio cache. */
260	RTHCPHYS pAPICPhys;
261	/** Virtual address of the virtual APIC mmio cache. */
262	R0PTRTYPE(uint8_t *) pAPIC;
263
264	/** R0 memory object for the MSR bitmap (1 page). */
265	RTR0MEMOBJ pMemObjMSRBitmap;
266	/** Physical address of the MSR bitmap (1 page). */
267	RTHCPHYS pMSRBitmapPhys;
268	/** Virtual address of the MSR bitmap (1 page). */
269	R0PTRTYPE(uint8_t *) pMSRBitmap;
270
271	/** R0 memory object for the MSR entry load page (guest MSRs). */
272	RTR0MEMOBJ pMemObjMSREntryLoad;
273	/** Physical address of the MSR entry load page (guest MSRs). */
274	RTHCPHYS pMSREntryLoadPhys;
275	/** Virtual address of the MSR entry load page (guest MSRs). */
276	R0PTRTYPE(uint8_t *) pMSREntryLoad;
277
278	/** R0 memory object for the MSR exit store page (guest MSRs). */
279	RTR0MEMOBJ pMemObjMSRExitStore;
280	/** Physical address of the MSR exit store page (guest MSRs). */
281	RTHCPHYS pMSRExitStorePhys;
282	/** Virtual address of the MSR exit store page (guest MSRs). */
283	R0PTRTYPE(uint8_t *) pMSRExitStore;
284
285	/** R0 memory object for the MSR exit load page (host MSRs). */
286	RTR0MEMOBJ pMemObjMSRExitLoad;
287	/** Physical address of the MSR exit load page (host MSRs). */
288	RTHCPHYS pMSRExitLoadPhys;
289	/** Virtual address of the MSR exit load page (host MSRs). */
290	R0PTRTYPE(uint8_t *) pMSRExitLoad;
291
292	/** Ring 0 handlers for VT-x. */
293	DECLR0CALLBACKMEMBER(void, pfnSetupTaggedTLB, (PVM pVM, PVMCPU pVCpu));
294
295	/** Host CR4 value (set by ring-0 VMX init) */
296	uint64_t hostCR4;
297
298	/** VMX MSR values */
299	struct
300	{
301	uint64_t feature_ctrl;
302	uint64_t vmx_basic_info;
303	VMX_CAPABILITY vmx_pin_ctls;
304	VMX_CAPABILITY vmx_proc_ctls;
305	VMX_CAPABILITY vmx_proc_ctls2;
306	VMX_CAPABILITY vmx_exit;
307	VMX_CAPABILITY vmx_entry;
308	uint64_t vmx_misc;
309	uint64_t vmx_cr0_fixed0;
310	uint64_t vmx_cr0_fixed1;
311	uint64_t vmx_cr4_fixed0;
312	uint64_t vmx_cr4_fixed1;
313	uint64_t vmx_vmcs_enum;
314	uint64_t vmx_eptcaps;
315	} msr;
316
317	/** Flush types for invept & invvpid; they depend on capabilities. */
318	VMX_FLUSH enmFlushPage;
319	VMX_FLUSH enmFlushContext;
320	} vmx;
321
322	struct
323	{
324	/** Set by the ring-0 driver to indicate SVM is supported by the CPU. */
325	bool fSupported;
326	/** Set when we've enabled SVM. */
327	bool fEnabled;
328	/** Set if erratum 170 affects the AMD cpu. */
329	bool fAlwaysFlushTLB;
330	/** Explicit alignment padding to make 32-bit gcc align u64RegisterMask
331	* naturally. */
332	bool padding[1];
333
334	/** R0 memory object for the host VM control block (VMCB). */
335	RTR0MEMOBJ pMemObjVMCBHost;
336	/** Physical address of the host VM control block (VMCB). */
337	RTHCPHYS pVMCBHostPhys;
338	/** Virtual address of the host VM control block (VMCB). */
339	R0PTRTYPE(void *) pVMCBHost;
340
341	/** R0 memory object for the IO bitmap (12kb). */
342	RTR0MEMOBJ pMemObjIOBitmap;
343	/** Physical address of the IO bitmap (12kb). */
344	RTHCPHYS pIOBitmapPhys;
345	/** Virtual address of the IO bitmap. */
346	R0PTRTYPE(void *) pIOBitmap;
347
348	/** R0 memory object for the MSR bitmap (8kb). */
349	RTR0MEMOBJ pMemObjMSRBitmap;
350	/** Physical address of the MSR bitmap (8kb). */
351	RTHCPHYS pMSRBitmapPhys;
352	/** Virtual address of the MSR bitmap. */
353	R0PTRTYPE(void *) pMSRBitmap;
354
355	/** SVM revision. */
356	uint32_t u32Rev;
357
358	/** SVM feature bits from cpuid 0x8000000a */
359	uint32_t u32Features;
360	} svm;
361
362	struct
363	{
364	uint32_t u32AMDFeatureECX;
365	uint32_t u32AMDFeatureEDX;
366	} cpuid;
367
368	/** Saved error from detection */
369	int32_t lLastError;
370
371	/** HWACCMR0Init was run */
372	bool fHWACCMR0Init;
373	} HWACCM;
374	/** Pointer to HWACCM VM instance data. */
375	typedef HWACCM *PHWACCM;
376
377	/* Maximum number of cached entries. */
378	#define VMCSCACHE_MAX_ENTRY 256
379
380	/* Structure for storing read and write VMCS actions. */
381	typedef struct VMCSCACHE
382	{
383	struct
384	{
385	uint32_t cValidEntries;
386	uint32_t uAlignment[3];
387	uint32_t aField[VMCSCACHE_MAX_ENTRY];
388	uint64_t aFieldVal[VMCSCACHE_MAX_ENTRY];
389	} Write;
390	struct
391	{
392	uint32_t cValidEntries;
393	uint32_t uAlignment[3];
394	uint32_t aField[VMCSCACHE_MAX_ENTRY];
395	uint64_t aFieldVal[VMCSCACHE_MAX_ENTRY];
396	} Read;
397	#ifdef DEBUG
398	struct
399	{
400	RTHCPHYS pPageCpuPhys;
401	RTHCPHYS pVMCSPhys;
402	RTGCPTR pCache;
403	RTGCPTR pCtx;
404	} TestIn;
405	struct
406	{
407	RTHCPHYS pVMCSPhys;
408	RTGCPTR pCache;
409	RTGCPTR pCtx;
410	} TestOut;
411	#endif
412	} VMCSCACHE;
413	/** Pointer to VMCSCACHE. */
414	typedef VMCSCACHE *PVMCSCACHE;
415
416	/**
417	* HWACCM VMCPU Instance data.
418	*/
419	typedef struct HWACCMCPU
420	{
421	/** Old style FPU reporting trap mask override performed (optimization) */
422	bool fFPUOldStyleOverride;
423
424	/** Set if we don't have to flush the TLB on VM entry. */
425	bool fResumeVM;
426
427	/** Set if we need to flush the TLB during the world switch. */
428	bool fForceTLBFlush;
429
430	/** Explicit alignment padding to make 32-bit gcc align u64RegisterMask
431	* naturally. */
432	bool padding[1];
433
434	/** HWACCM_CHANGED_* flags. */
435	RTUINT fContextUseFlags;
436
437	/* Id of the last cpu we were executing code on (NIL_RTCPUID for the first time) */
438	RTCPUID idLastCpu;
439
440	/* TLB flush count */
441	RTUINT cTLBFlushes;
442
443	/* Current ASID in use by the VM */
444	RTUINT uCurrentASID;
445
446	struct
447	{
448	/** R0 memory object for the VM control structure (VMCS). */
449	RTR0MEMOBJ pMemObjVMCS;
450	/** Physical address of the VM control structure (VMCS). */
451	RTHCPHYS pVMCSPhys;
452	/** Virtual address of the VM control structure (VMCS). */
453	R0PTRTYPE(void *) pVMCS;
454
455	/** Ring 0 handlers for VT-x. */
456	DECLR0CALLBACKMEMBER(int, pfnStartVM,(RTHCUINT fResume, PCPUMCTX pCtx, PVMCSCACHE pCache, PVM pVM, PVMCPU pVCpu));
457
458	/** Current VMX_VMCS_CTRL_PROC_EXEC_CONTROLS. */
459	uint64_t proc_ctls;
460
461	/** Current CR0 mask. */
462	uint64_t cr0_mask;
463	/** Current CR4 mask. */
464	uint64_t cr4_mask;
465
466	/** Current EPTP. */
467	RTHCPHYS GCPhysEPTP;
468
469	/** VMCS cache. */
470	VMCSCACHE VMCSCache;
471
472	/** Real-mode emulation state. */
473	struct
474	{
475	X86EFLAGS eflags;
476	uint32_t fValid;
477	} RealMode;
478
479	struct
480	{
481	uint64_t u64VMCSPhys;
482	uint32_t ulVMCSRevision;
483	uint32_t ulInstrError;
484	uint32_t ulExitReason;
485	RTCPUID idEnteredCpu;
486	RTCPUID idCurrentCpu;
487	uint32_t padding;
488	} lasterror;
489
490	/** The last known guest paging mode. */
491	PGMMODE enmCurrGuestMode;
492	} vmx;
493
494	struct
495	{
496	/** R0 memory object for the VM control block (VMCB). */
497	RTR0MEMOBJ pMemObjVMCB;
498	/** Physical address of the VM control block (VMCB). */
499	RTHCPHYS pVMCBPhys;
500	/** Virtual address of the VM control block (VMCB). */
501	R0PTRTYPE(void *) pVMCB;
502
503	/** Ring 0 handlers for VT-x. */
504	DECLR0CALLBACKMEMBER(int, pfnVMRun,(RTHCPHYS pVMCBHostPhys, RTHCPHYS pVMCBPhys, PCPUMCTX pCtx, PVM pVM, PVMCPU pVCpu));
505
506	} svm;
507
508	/** Event injection state. */
509	struct
510	{
511	uint32_t fPending;
512	uint32_t errCode;
513	uint64_t intInfo;
514	} Event;
515
516	/** Currenty shadow paging mode. */
517	PGMMODE enmShadowMode;
518
519	/** The CPU ID of the CPU currently owning the VMCS. Set in
520	* HWACCMR0Enter and cleared in HWACCMR0Leave. */
521	RTCPUID idEnteredCpu;
522
523	STAMPROFILEADV StatEntry;
524	STAMPROFILEADV StatExit1;
525	STAMPROFILEADV StatExit2;
526	#if 1 /* temporary for tracking down darwin issues. */
527	STAMPROFILEADV StatExit2Sub1;
528	STAMPROFILEADV StatExit2Sub2;
529	STAMPROFILEADV StatExit2Sub3;
530	#endif
531	STAMPROFILEADV StatInGC;
532
533	STAMCOUNTER StatIntInject;
534
535	STAMCOUNTER StatExitShadowNM;
536	STAMCOUNTER StatExitGuestNM;
537	STAMCOUNTER StatExitShadowPF;
538	STAMCOUNTER StatExitGuestPF;
539	STAMCOUNTER StatExitGuestUD;
540	STAMCOUNTER StatExitGuestSS;
541	STAMCOUNTER StatExitGuestNP;
542	STAMCOUNTER StatExitGuestGP;
543	STAMCOUNTER StatExitGuestDE;
544	STAMCOUNTER StatExitGuestDB;
545	STAMCOUNTER StatExitGuestMF;
546	STAMCOUNTER StatExitInvpg;
547	STAMCOUNTER StatExitInvd;
548	STAMCOUNTER StatExitCpuid;
549	STAMCOUNTER StatExitRdtsc;
550	STAMCOUNTER StatExitCRxWrite[8];
551	STAMCOUNTER StatExitCRxRead[8];
552	STAMCOUNTER StatExitDRxWrite;
553	STAMCOUNTER StatExitDRxRead;
554	STAMCOUNTER StatExitCLTS;
555	STAMCOUNTER StatExitLMSW;
556	STAMCOUNTER StatExitIOWrite;
557	STAMCOUNTER StatExitIORead;
558	STAMCOUNTER StatExitIOStringWrite;
559	STAMCOUNTER StatExitIOStringRead;
560	STAMCOUNTER StatExitIrqWindow;
561	STAMCOUNTER StatExitMaxResume;
562	STAMCOUNTER StatIntReinject;
563	STAMCOUNTER StatPendingHostIrq;
564
565	STAMCOUNTER StatFlushPageManual;
566	STAMCOUNTER StatFlushPhysPageManual;
567	STAMCOUNTER StatFlushTLBManual;
568	STAMCOUNTER StatFlushPageInvlpg;
569	STAMCOUNTER StatFlushTLBWorldSwitch;
570	STAMCOUNTER StatNoFlushTLBWorldSwitch;
571	STAMCOUNTER StatFlushTLBCRxChange;
572	STAMCOUNTER StatFlushASID;
573	STAMCOUNTER StatFlushTLBInvlpga;
574
575	STAMCOUNTER StatSwitchGuestIrq;
576	STAMCOUNTER StatSwitchToR3;
577
578	STAMCOUNTER StatTSCOffset;
579	STAMCOUNTER StatTSCIntercept;
580
581	STAMCOUNTER StatExitReasonNPF;
582	STAMCOUNTER StatDRxArmed;
583	STAMCOUNTER StatDRxContextSwitch;
584	STAMCOUNTER StatDRxIOCheck;
585
586
587	R3PTRTYPE(PSTAMCOUNTER) paStatExitReason;
588	R0PTRTYPE(PSTAMCOUNTER) paStatExitReasonR0;
589	} HWACCMCPU;
590	/** Pointer to HWACCM VM instance data. */
591	typedef HWACCMCPU *PHWACCMCPU;
592
593
594	#ifdef IN_RING0
595
596	VMMR0DECL(PHWACCM_CPUINFO) HWACCMR0GetCurrentCpu();
597	VMMR0DECL(PHWACCM_CPUINFO) HWACCMR0GetCurrentCpuEx(RTCPUID idCpu);
598
599
600	#ifdef VBOX_STRICT
601	VMMR0DECL(void) HWACCMDumpRegs(PVM pVM, PCPUMCTX pCtx);
602	VMMR0DECL(void) HWACCMR0DumpDescriptor(PX86DESCHC Desc, RTSEL Sel, const char *pszMsg);
603	#else
604	#define HWACCMDumpRegs(a, b) do { } while (0)
605	#define HWACCMR0DumpDescriptor(a, b, c) do { } while (0)
606	#endif
607
608	/* Dummy callback handlers. */
609	VMMR0DECL(int) HWACCMR0DummyEnter(PVM pVM, PVMCPU pVCpu, PHWACCM_CPUINFO pCpu);
610	VMMR0DECL(int) HWACCMR0DummyLeave(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
611	VMMR0DECL(int) HWACCMR0DummyEnableCpu(PHWACCM_CPUINFO pCpu, PVM pVM, void *pvPageCpu, RTHCPHYS pPageCpuPhys);
612	VMMR0DECL(int) HWACCMR0DummyDisableCpu(PHWACCM_CPUINFO pCpu, void *pvPageCpu, RTHCPHYS pPageCpuPhys);
613	VMMR0DECL(int) HWACCMR0DummyInitVM(PVM pVM);
614	VMMR0DECL(int) HWACCMR0DummyTermVM(PVM pVM);
615	VMMR0DECL(int) HWACCMR0DummySetupVM(PVM pVM);
616	VMMR0DECL(int) HWACCMR0DummyRunGuestCode(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
617	VMMR0DECL(int) HWACCMR0DummySaveHostState(PVM pVM, PVMCPU pVCpu);
618	VMMR0DECL(int) HWACCMR0DummyLoadGuestState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
619
620
621	# ifdef VBOX_WITH_HYBIRD_32BIT_KERNEL
622	/**
623	* Gets 64-bit GDTR and IDTR on darwin.
624	* @param pGdtr Where to store the 64-bit GDTR.
625	* @param pIdtr Where to store the 64-bit IDTR.
626	*/
627	DECLASM(void) hwaccmR0Get64bitGDTRandIDTR(PX86XDTR64 pGdtr, PX86XDTR64 pIdtr);
628
629	/**
630	* Gets 64-bit CR3 on darwin.
631	* @returns CR3
632	*/
633	DECLASM(uint64_t) hwaccmR0Get64bitCR3(void);
634	# endif
635
636	#endif /* IN_RING0 */
637
638	/** @} */
639
640	__END_DECLS
641
642	#endif
643

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source: vbox/trunk/src/VBox/VMM/HWACCMInternal.h@ 15371

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