HWACCMInternal.h@ 15439

Last change on this file since 15439 was 15439, checked in by vboxsync, 16 years ago
Enable 64 bits guest support on 32 bits hosts. Only use rem64 if the guest OS type is 64 bits.
Property svn:eol-style set to `native` Property svn:keywords set to `Id`
File size: 23.6 KB

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1	/* $Id: HWACCMInternal.h 15439 2008-12-13 12:48:22Z vboxsync $ */
2	/** @file
3	* HWACCM - Internal header file.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22	#ifndef ___HWACCMInternal_h
23	#define ___HWACCMInternal_h
24
25	#include <VBox/cdefs.h>
26	#include <VBox/types.h>
27	#include <VBox/em.h>
28	#include <VBox/stam.h>
29	#include <VBox/dis.h>
30	#include <VBox/hwaccm.h>
31	#include <VBox/pgm.h>
32	#include <VBox/cpum.h>
33	#include <iprt/memobj.h>
34	#include <iprt/cpuset.h>
35	#include <iprt/mp.h>
36
37	#if HC_ARCH_BITS == 64 \|\| defined(VBOX_WITH_HYBRID_32BIT_KERNEL) \|\| defined (VBOX_WITH_64_BITS_GUESTS)
38	/* Enable 64 bits guest support. */
39	# define VBOX_ENABLE_64_BITS_GUESTS
40	#endif
41
42	#define VMX_USE_CACHED_VMCS_ACCESSES
43	#define HWACCM_VMX_EMULATE_REALMODE
44	#define HWACCM_VTX_WITH_EPT
45	#define HWACCM_VTX_WITH_VPID
46
47	__BEGIN_DECLS
48
49
50	/** @defgroup grp_hwaccm_int Internal
51	* @ingroup grp_hwaccm
52	* @internal
53	* @{
54	*/
55
56
57	/** Maximum number of exit reason statistics counters. */
58	#define MAX_EXITREASON_STAT 0x100
59	#define MASK_EXITREASON_STAT 0xff
60
61	/** @name Changed flags
62	* These flags are used to keep track of which important registers that
63	* have been changed since last they were reset.
64	* @{
65	*/
66	#define HWACCM_CHANGED_GUEST_FPU RT_BIT(0)
67	#define HWACCM_CHANGED_GUEST_CR0 RT_BIT(1)
68	#define HWACCM_CHANGED_GUEST_CR3 RT_BIT(2)
69	#define HWACCM_CHANGED_GUEST_CR4 RT_BIT(3)
70	#define HWACCM_CHANGED_GUEST_GDTR RT_BIT(4)
71	#define HWACCM_CHANGED_GUEST_IDTR RT_BIT(5)
72	#define HWACCM_CHANGED_GUEST_LDTR RT_BIT(6)
73	#define HWACCM_CHANGED_GUEST_TR RT_BIT(7)
74	#define HWACCM_CHANGED_GUEST_SYSENTER_MSR RT_BIT(8)
75	#define HWACCM_CHANGED_GUEST_SEGMENT_REGS RT_BIT(9)
76	#define HWACCM_CHANGED_GUEST_DEBUG RT_BIT(10)
77	#define HWACCM_CHANGED_HOST_CONTEXT RT_BIT(11)
78
79	#define HWACCM_CHANGED_ALL ( HWACCM_CHANGED_GUEST_SEGMENT_REGS \
80	\| HWACCM_CHANGED_GUEST_CR0 \
81	\| HWACCM_CHANGED_GUEST_CR3 \
82	\| HWACCM_CHANGED_GUEST_CR4 \
83	\| HWACCM_CHANGED_GUEST_GDTR \
84	\| HWACCM_CHANGED_GUEST_IDTR \
85	\| HWACCM_CHANGED_GUEST_LDTR \
86	\| HWACCM_CHANGED_GUEST_TR \
87	\| HWACCM_CHANGED_GUEST_SYSENTER_MSR \
88	\| HWACCM_CHANGED_GUEST_FPU \
89	\| HWACCM_CHANGED_GUEST_DEBUG \
90	\| HWACCM_CHANGED_HOST_CONTEXT)
91
92	#define HWACCM_CHANGED_ALL_GUEST ( HWACCM_CHANGED_GUEST_SEGMENT_REGS \
93	\| HWACCM_CHANGED_GUEST_CR0 \
94	\| HWACCM_CHANGED_GUEST_CR3 \
95	\| HWACCM_CHANGED_GUEST_CR4 \
96	\| HWACCM_CHANGED_GUEST_GDTR \
97	\| HWACCM_CHANGED_GUEST_IDTR \
98	\| HWACCM_CHANGED_GUEST_LDTR \
99	\| HWACCM_CHANGED_GUEST_TR \
100	\| HWACCM_CHANGED_GUEST_SYSENTER_MSR \
101	\| HWACCM_CHANGED_GUEST_DEBUG \
102	\| HWACCM_CHANGED_GUEST_FPU)
103
104	/** @} */
105
106	/** @name Intercepted traps
107	* Traps that need to be intercepted so we can correctly dispatch them to the guest if required.
108	* Currently #NM and #PF only
109	*/
110	#ifdef VBOX_STRICT
111	#define HWACCM_VMX_TRAP_MASK RT_BIT(X86_XCPT_DE) \| RT_BIT(X86_XCPT_NM) \| RT_BIT(X86_XCPT_PF) \| RT_BIT(X86_XCPT_UD) \| RT_BIT(X86_XCPT_NP) \| RT_BIT(X86_XCPT_SS) \| RT_BIT(X86_XCPT_GP) \| RT_BIT(X86_XCPT_MF)
112	#define HWACCM_SVM_TRAP_MASK HWACCM_VMX_TRAP_MASK
113	#else
114	#define HWACCM_VMX_TRAP_MASK RT_BIT(X86_XCPT_NM) \| RT_BIT(X86_XCPT_PF)
115	#define HWACCM_SVM_TRAP_MASK RT_BIT(X86_XCPT_NM) \| RT_BIT(X86_XCPT_PF)
116	#endif
117	/* All exceptions have to be intercept in emulated real-mode (minues NM & PF as they are always intercepted. */
118	#define HWACCM_VMX_TRAP_MASK_REALMODE RT_BIT(X86_XCPT_DE) \| RT_BIT(X86_XCPT_DB) \| RT_BIT(X86_XCPT_NMI) \| RT_BIT(X86_XCPT_BP) \| RT_BIT(X86_XCPT_OF) \| RT_BIT(X86_XCPT_BR) \| RT_BIT(X86_XCPT_UD) \| RT_BIT(X86_XCPT_DF) \| RT_BIT(X86_XCPT_CO_SEG_OVERRUN) \| RT_BIT(X86_XCPT_TS) \| RT_BIT(X86_XCPT_NP) \| RT_BIT(X86_XCPT_SS) \| RT_BIT(X86_XCPT_GP) \| RT_BIT(X86_XCPT_MF) \| RT_BIT(X86_XCPT_AC) \| RT_BIT(X86_XCPT_MC) \| RT_BIT(X86_XCPT_XF)
119	/** @} */
120
121
122	/** Maxium resume loops allowed in ring 0 (safety precaution) */
123	#define HWACCM_MAX_RESUME_LOOPS 1024
124
125	/** Size for the EPT identity page table (1024 4 MB pages to cover the entire address space). */
126	#define HWACCM_EPT_IDENTITY_PG_TABLE_SIZE PAGE_SIZE
127	/** Size of the TSS structure + 2 pages for the IO bitmap + end byte. */
128	#define HWACCM_VTX_TSS_SIZE (sizeof(VBOXTSS) + 2*PAGE_SIZE + 1)
129	/** Total guest mapped memory needed. */
130	#define HWACCM_VTX_TOTAL_DEVHEAP_MEM (HWACCM_EPT_IDENTITY_PG_TABLE_SIZE + HWACCM_VTX_TSS_SIZE)
131
132	/** HWACCM SSM version
133	*/
134	#define HWACCM_SSM_VERSION 3
135
136	/* Per-cpu information. (host) */
137	typedef struct
138	{
139	RTCPUID idCpu;
140
141	RTR0MEMOBJ pMemObj;
142	/* Current ASID (AMD-V)/VPID (Intel) */
143	uint32_t uCurrentASID;
144	/* TLB flush count */
145	uint32_t cTLBFlushes;
146
147	/* Set the first time a cpu is used to make sure we start with a clean TLB. */
148	bool fFlushTLB;
149
150	/** Configured for VT-x or AMD-V. */
151	bool fConfigured;
152
153	/** In use by our code. (for power suspend) */
154	volatile bool fInUse;
155	} HWACCM_CPUINFO;
156	typedef HWACCM_CPUINFO *PHWACCM_CPUINFO;
157
158	/* VT-x capability qword. */
159	typedef union
160	{
161	struct
162	{
163	uint32_t disallowed0;
164	uint32_t allowed1;
165	} n;
166	uint64_t u;
167	} VMX_CAPABILITY;
168
169	/**
170	* Switcher function, HC to RC.
171	*
172	* @param pVM The VM handle.
173	* @returns Return code indicating the action to take.
174	*/
175	typedef DECLASMTYPE(int) FNHWACCMSWITCHERHC(PVM pVM);
176	/** Pointer to switcher function. */
177	typedef FNHWACCMSWITCHERHC *PFNHWACCMSWITCHERHC;
178
179	/**
180	* HWACCM VM Instance data.
181	* Changes to this must checked against the padding of the cfgm union in VM!
182	*/
183	typedef struct HWACCM
184	{
185	/** Set when we've initialized VMX or SVM. */
186	bool fInitialized;
187
188	/** Set when we're using VMX/SVN at that moment. */
189	bool fActive;
190
191	/** Set when hardware acceleration is allowed. */
192	bool fAllowed;
193
194	/** Set if nested paging is enabled. */
195	bool fNestedPaging;
196
197	/** Set if nested paging is allowed. */
198	bool fAllowNestedPaging;
199
200	/** Set if we're supposed to inject an NMI. */
201	bool fInjectNMI;
202
203	/** Set if we can support 64-bit guests or not. */
204	bool fAllow64BitGuests;
205
206	/** Explicit alignment padding to make 32-bit gcc align u64RegisterMask
207	* naturally. */
208	bool padding[1];
209
210	/** And mask for copying register contents. */
211	uint64_t u64RegisterMask;
212
213	/** Maximum ASID allowed. */
214	RTUINT uMaxASID;
215
216	#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
217	/** 32 to 64 bits switcher entrypoint. */
218	R0PTRTYPE(PFNHWACCMSWITCHERHC) pfnHost32ToGuest64R0;
219
220	/* AMD-V 64 bits vmrun handler */
221	RTRCPTR pfnSVMGCVMRun64;
222
223	/* VT-x 64 bits vmlaunch handler */
224	RTRCPTR pfnVMXGCStartVM64;
225
226	/* RC handler to setup the 64 bits FPU state. */
227	RTRCPTR pfnSaveGuestFPU64;
228
229	/* RC handler to setup the 64 bits debug state. */
230	RTRCPTR pfnSaveGuestDebug64;
231
232	# ifdef DEBUG
233	/* Test handler */
234	RTRCPTR pfnTest64;
235
236	RTRCPTR uAlignment[1];
237	# endif
238	#elif defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
239	uint32_t u32Alignment[1];
240	#endif
241
242	struct
243	{
244	/** Set by the ring-0 driver to indicate VMX is supported by the CPU. */
245	bool fSupported;
246
247	/** Set when we've enabled VMX. */
248	bool fEnabled;
249
250	/** Set if VPID is supported. */
251	bool fVPID;
252
253	/** Set if VT-x VPID is allowed. */
254	bool fAllowVPID;
255
256	/** Virtual address of the TSS page used for real mode emulation. */
257	R3PTRTYPE(PVBOXTSS) pRealModeTSS;
258
259	/** Virtual address of the identity page table used for real mode and protected mode without paging emulation in EPT mode. */
260	R3PTRTYPE(PX86PD) pNonPagingModeEPTPageTable;
261
262	/** R0 memory object for the virtual APIC mmio cache. */
263	RTR0MEMOBJ pMemObjAPIC;
264	/** Physical address of the virtual APIC mmio cache. */
265	RTHCPHYS pAPICPhys;
266	/** Virtual address of the virtual APIC mmio cache. */
267	R0PTRTYPE(uint8_t *) pAPIC;
268
269	/** R0 memory object for the MSR bitmap (1 page). */
270	RTR0MEMOBJ pMemObjMSRBitmap;
271	/** Physical address of the MSR bitmap (1 page). */
272	RTHCPHYS pMSRBitmapPhys;
273	/** Virtual address of the MSR bitmap (1 page). */
274	R0PTRTYPE(uint8_t *) pMSRBitmap;
275
276	/** R0 memory object for the MSR entry load page (guest MSRs). */
277	RTR0MEMOBJ pMemObjMSREntryLoad;
278	/** Physical address of the MSR entry load page (guest MSRs). */
279	RTHCPHYS pMSREntryLoadPhys;
280	/** Virtual address of the MSR entry load page (guest MSRs). */
281	R0PTRTYPE(uint8_t *) pMSREntryLoad;
282
283	/** R0 memory object for the MSR exit store page (guest MSRs). */
284	RTR0MEMOBJ pMemObjMSRExitStore;
285	/** Physical address of the MSR exit store page (guest MSRs). */
286	RTHCPHYS pMSRExitStorePhys;
287	/** Virtual address of the MSR exit store page (guest MSRs). */
288	R0PTRTYPE(uint8_t *) pMSRExitStore;
289
290	/** R0 memory object for the MSR exit load page (host MSRs). */
291	RTR0MEMOBJ pMemObjMSRExitLoad;
292	/** Physical address of the MSR exit load page (host MSRs). */
293	RTHCPHYS pMSRExitLoadPhys;
294	/** Virtual address of the MSR exit load page (host MSRs). */
295	R0PTRTYPE(uint8_t *) pMSRExitLoad;
296
297	/** Ring 0 handlers for VT-x. */
298	DECLR0CALLBACKMEMBER(void, pfnSetupTaggedTLB, (PVM pVM, PVMCPU pVCpu));
299
300	/** Host CR4 value (set by ring-0 VMX init) */
301	uint64_t hostCR4;
302
303	/** VMX MSR values */
304	struct
305	{
306	uint64_t feature_ctrl;
307	uint64_t vmx_basic_info;
308	VMX_CAPABILITY vmx_pin_ctls;
309	VMX_CAPABILITY vmx_proc_ctls;
310	VMX_CAPABILITY vmx_proc_ctls2;
311	VMX_CAPABILITY vmx_exit;
312	VMX_CAPABILITY vmx_entry;
313	uint64_t vmx_misc;
314	uint64_t vmx_cr0_fixed0;
315	uint64_t vmx_cr0_fixed1;
316	uint64_t vmx_cr4_fixed0;
317	uint64_t vmx_cr4_fixed1;
318	uint64_t vmx_vmcs_enum;
319	uint64_t vmx_eptcaps;
320	} msr;
321
322	/** Flush types for invept & invvpid; they depend on capabilities. */
323	VMX_FLUSH enmFlushPage;
324	VMX_FLUSH enmFlushContext;
325	} vmx;
326
327	struct
328	{
329	/** Set by the ring-0 driver to indicate SVM is supported by the CPU. */
330	bool fSupported;
331	/** Set when we've enabled SVM. */
332	bool fEnabled;
333	/** Set if erratum 170 affects the AMD cpu. */
334	bool fAlwaysFlushTLB;
335	/** Explicit alignment padding to make 32-bit gcc align u64RegisterMask
336	* naturally. */
337	bool padding[1];
338
339	/** R0 memory object for the host VM control block (VMCB). */
340	RTR0MEMOBJ pMemObjVMCBHost;
341	/** Physical address of the host VM control block (VMCB). */
342	RTHCPHYS pVMCBHostPhys;
343	/** Virtual address of the host VM control block (VMCB). */
344	R0PTRTYPE(void *) pVMCBHost;
345
346	/** R0 memory object for the IO bitmap (12kb). */
347	RTR0MEMOBJ pMemObjIOBitmap;
348	/** Physical address of the IO bitmap (12kb). */
349	RTHCPHYS pIOBitmapPhys;
350	/** Virtual address of the IO bitmap. */
351	R0PTRTYPE(void *) pIOBitmap;
352
353	/** R0 memory object for the MSR bitmap (8kb). */
354	RTR0MEMOBJ pMemObjMSRBitmap;
355	/** Physical address of the MSR bitmap (8kb). */
356	RTHCPHYS pMSRBitmapPhys;
357	/** Virtual address of the MSR bitmap. */
358	R0PTRTYPE(void *) pMSRBitmap;
359
360	/** SVM revision. */
361	uint32_t u32Rev;
362
363	/** SVM feature bits from cpuid 0x8000000a */
364	uint32_t u32Features;
365	} svm;
366
367	struct
368	{
369	uint32_t u32AMDFeatureECX;
370	uint32_t u32AMDFeatureEDX;
371	} cpuid;
372
373	/** Saved error from detection */
374	int32_t lLastError;
375
376	/** HWACCMR0Init was run */
377	bool fHWACCMR0Init;
378	} HWACCM;
379	/** Pointer to HWACCM VM instance data. */
380	typedef HWACCM *PHWACCM;
381
382	/* Maximum number of cached entries. */
383	#define VMCSCACHE_MAX_ENTRY 256
384
385	/* Structure for storing read and write VMCS actions. */
386	typedef struct VMCSCACHE
387	{
388	struct
389	{
390	uint32_t cValidEntries;
391	uint32_t uAlignment[3];
392	uint32_t aField[VMCSCACHE_MAX_ENTRY];
393	uint64_t aFieldVal[VMCSCACHE_MAX_ENTRY];
394	} Write;
395	struct
396	{
397	uint32_t cValidEntries;
398	uint32_t uAlignment[3];
399	uint32_t aField[VMCSCACHE_MAX_ENTRY];
400	uint64_t aFieldVal[VMCSCACHE_MAX_ENTRY];
401	} Read;
402	#ifdef DEBUG
403	struct
404	{
405	RTHCPHYS pPageCpuPhys;
406	RTHCPHYS pVMCSPhys;
407	RTGCPTR pCache;
408	RTGCPTR pCtx;
409	} TestIn;
410	struct
411	{
412	RTHCPHYS pVMCSPhys;
413	RTGCPTR pCache;
414	RTGCPTR pCtx;
415	} TestOut;
416	struct
417	{
418	uint64_t param1;
419	uint64_t param2;
420	uint64_t param3;
421	uint64_t param4;
422	} ScratchPad;
423	#endif
424	} VMCSCACHE;
425	/** Pointer to VMCSCACHE. */
426	typedef VMCSCACHE *PVMCSCACHE;
427
428	/**
429	* HWACCM VMCPU Instance data.
430	*/
431	typedef struct HWACCMCPU
432	{
433	/** Old style FPU reporting trap mask override performed (optimization) */
434	bool fFPUOldStyleOverride;
435
436	/** Set if we don't have to flush the TLB on VM entry. */
437	bool fResumeVM;
438
439	/** Set if we need to flush the TLB during the world switch. */
440	bool fForceTLBFlush;
441
442	/** Explicit alignment padding to make 32-bit gcc align u64RegisterMask
443	* naturally. */
444	bool padding[1];
445
446	/** HWACCM_CHANGED_* flags. */
447	RTUINT fContextUseFlags;
448
449	/* Id of the last cpu we were executing code on (NIL_RTCPUID for the first time) */
450	RTCPUID idLastCpu;
451
452	/* TLB flush count */
453	RTUINT cTLBFlushes;
454
455	/* Current ASID in use by the VM */
456	RTUINT uCurrentASID;
457
458	struct
459	{
460	/** R0 memory object for the VM control structure (VMCS). */
461	RTR0MEMOBJ pMemObjVMCS;
462	/** Physical address of the VM control structure (VMCS). */
463	RTHCPHYS pVMCSPhys;
464	/** Virtual address of the VM control structure (VMCS). */
465	R0PTRTYPE(void *) pVMCS;
466
467	/** Ring 0 handlers for VT-x. */
468	DECLR0CALLBACKMEMBER(int, pfnStartVM,(RTHCUINT fResume, PCPUMCTX pCtx, PVMCSCACHE pCache, PVM pVM, PVMCPU pVCpu));
469
470	/** Current VMX_VMCS_CTRL_PROC_EXEC_CONTROLS. */
471	uint64_t proc_ctls;
472
473	/** Current CR0 mask. */
474	uint64_t cr0_mask;
475	/** Current CR4 mask. */
476	uint64_t cr4_mask;
477
478	/** Current EPTP. */
479	RTHCPHYS GCPhysEPTP;
480
481	/** VMCS cache. */
482	VMCSCACHE VMCSCache;
483
484	/** Real-mode emulation state. */
485	struct
486	{
487	X86EFLAGS eflags;
488	uint32_t fValid;
489	} RealMode;
490
491	struct
492	{
493	uint64_t u64VMCSPhys;
494	uint32_t ulVMCSRevision;
495	uint32_t ulInstrError;
496	uint32_t ulExitReason;
497	RTCPUID idEnteredCpu;
498	RTCPUID idCurrentCpu;
499	uint32_t padding;
500	} lasterror;
501
502	/** The last known guest paging mode. */
503	PGMMODE enmCurrGuestMode;
504	} vmx;
505
506	struct
507	{
508	/** R0 memory object for the VM control block (VMCB). */
509	RTR0MEMOBJ pMemObjVMCB;
510	/** Physical address of the VM control block (VMCB). */
511	RTHCPHYS pVMCBPhys;
512	/** Virtual address of the VM control block (VMCB). */
513	R0PTRTYPE(void *) pVMCB;
514
515	/** Ring 0 handlers for VT-x. */
516	DECLR0CALLBACKMEMBER(int, pfnVMRun,(RTHCPHYS pVMCBHostPhys, RTHCPHYS pVMCBPhys, PCPUMCTX pCtx, PVM pVM, PVMCPU pVCpu));
517
518	} svm;
519
520	/** Event injection state. */
521	struct
522	{
523	uint32_t fPending;
524	uint32_t errCode;
525	uint64_t intInfo;
526	} Event;
527
528	/** Currenty shadow paging mode. */
529	PGMMODE enmShadowMode;
530
531	/** The CPU ID of the CPU currently owning the VMCS. Set in
532	* HWACCMR0Enter and cleared in HWACCMR0Leave. */
533	RTCPUID idEnteredCpu;
534
535	STAMPROFILEADV StatEntry;
536	STAMPROFILEADV StatExit1;
537	STAMPROFILEADV StatExit2;
538	#if 1 /* temporary for tracking down darwin issues. */
539	STAMPROFILEADV StatExit2Sub1;
540	STAMPROFILEADV StatExit2Sub2;
541	STAMPROFILEADV StatExit2Sub3;
542	#endif
543	STAMPROFILEADV StatInGC;
544
545	STAMCOUNTER StatIntInject;
546
547	STAMCOUNTER StatExitShadowNM;
548	STAMCOUNTER StatExitGuestNM;
549	STAMCOUNTER StatExitShadowPF;
550	STAMCOUNTER StatExitGuestPF;
551	STAMCOUNTER StatExitGuestUD;
552	STAMCOUNTER StatExitGuestSS;
553	STAMCOUNTER StatExitGuestNP;
554	STAMCOUNTER StatExitGuestGP;
555	STAMCOUNTER StatExitGuestDE;
556	STAMCOUNTER StatExitGuestDB;
557	STAMCOUNTER StatExitGuestMF;
558	STAMCOUNTER StatExitInvpg;
559	STAMCOUNTER StatExitInvd;
560	STAMCOUNTER StatExitCpuid;
561	STAMCOUNTER StatExitRdtsc;
562	STAMCOUNTER StatExitCRxWrite[8];
563	STAMCOUNTER StatExitCRxRead[8];
564	STAMCOUNTER StatExitDRxWrite;
565	STAMCOUNTER StatExitDRxRead;
566	STAMCOUNTER StatExitCLTS;
567	STAMCOUNTER StatExitLMSW;
568	STAMCOUNTER StatExitIOWrite;
569	STAMCOUNTER StatExitIORead;
570	STAMCOUNTER StatExitIOStringWrite;
571	STAMCOUNTER StatExitIOStringRead;
572	STAMCOUNTER StatExitIrqWindow;
573	STAMCOUNTER StatExitMaxResume;
574	STAMCOUNTER StatIntReinject;
575	STAMCOUNTER StatPendingHostIrq;
576
577	STAMCOUNTER StatFlushPageManual;
578	STAMCOUNTER StatFlushPhysPageManual;
579	STAMCOUNTER StatFlushTLBManual;
580	STAMCOUNTER StatFlushPageInvlpg;
581	STAMCOUNTER StatFlushTLBWorldSwitch;
582	STAMCOUNTER StatNoFlushTLBWorldSwitch;
583	STAMCOUNTER StatFlushTLBCRxChange;
584	STAMCOUNTER StatFlushASID;
585	STAMCOUNTER StatFlushTLBInvlpga;
586
587	STAMCOUNTER StatSwitchGuestIrq;
588	STAMCOUNTER StatSwitchToR3;
589
590	STAMCOUNTER StatTSCOffset;
591	STAMCOUNTER StatTSCIntercept;
592
593	STAMCOUNTER StatExitReasonNPF;
594	STAMCOUNTER StatDRxArmed;
595	STAMCOUNTER StatDRxContextSwitch;
596	STAMCOUNTER StatDRxIOCheck;
597
598
599	R3PTRTYPE(PSTAMCOUNTER) paStatExitReason;
600	R0PTRTYPE(PSTAMCOUNTER) paStatExitReasonR0;
601	} HWACCMCPU;
602	/** Pointer to HWACCM VM instance data. */
603	typedef HWACCMCPU *PHWACCMCPU;
604
605
606	#ifdef IN_RING0
607
608	VMMR0DECL(PHWACCM_CPUINFO) HWACCMR0GetCurrentCpu();
609	VMMR0DECL(PHWACCM_CPUINFO) HWACCMR0GetCurrentCpuEx(RTCPUID idCpu);
610
611
612	#ifdef VBOX_STRICT
613	VMMR0DECL(void) HWACCMDumpRegs(PVM pVM, PCPUMCTX pCtx);
614	VMMR0DECL(void) HWACCMR0DumpDescriptor(PX86DESCHC Desc, RTSEL Sel, const char *pszMsg);
615	#else
616	#define HWACCMDumpRegs(a, b) do { } while (0)
617	#define HWACCMR0DumpDescriptor(a, b, c) do { } while (0)
618	#endif
619
620	/* Dummy callback handlers. */
621	VMMR0DECL(int) HWACCMR0DummyEnter(PVM pVM, PVMCPU pVCpu, PHWACCM_CPUINFO pCpu);
622	VMMR0DECL(int) HWACCMR0DummyLeave(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
623	VMMR0DECL(int) HWACCMR0DummyEnableCpu(PHWACCM_CPUINFO pCpu, PVM pVM, void *pvPageCpu, RTHCPHYS pPageCpuPhys);
624	VMMR0DECL(int) HWACCMR0DummyDisableCpu(PHWACCM_CPUINFO pCpu, void *pvPageCpu, RTHCPHYS pPageCpuPhys);
625	VMMR0DECL(int) HWACCMR0DummyInitVM(PVM pVM);
626	VMMR0DECL(int) HWACCMR0DummyTermVM(PVM pVM);
627	VMMR0DECL(int) HWACCMR0DummySetupVM(PVM pVM);
628	VMMR0DECL(int) HWACCMR0DummyRunGuestCode(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
629	VMMR0DECL(int) HWACCMR0DummySaveHostState(PVM pVM, PVMCPU pVCpu);
630	VMMR0DECL(int) HWACCMR0DummyLoadGuestState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
631
632
633	# ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
634	/**
635	* Gets 64-bit GDTR and IDTR on darwin.
636	* @param pGdtr Where to store the 64-bit GDTR.
637	* @param pIdtr Where to store the 64-bit IDTR.
638	*/
639	DECLASM(void) hwaccmR0Get64bitGDTRandIDTR(PX86XDTR64 pGdtr, PX86XDTR64 pIdtr);
640
641	/**
642	* Gets 64-bit CR3 on darwin.
643	* @returns CR3
644	*/
645	DECLASM(uint64_t) hwaccmR0Get64bitCR3(void);
646	# endif
647
648	#endif /* IN_RING0 */
649
650	/** @} */
651
652	__END_DECLS
653
654	#endif
655

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source: vbox/trunk/src/VBox/VMM/HWACCMInternal.h@ 15439

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