HWACCMInternal.h@ 15440

Last change on this file since 15440 was 15440, checked in by vboxsync, 16 years ago
Sync CR2 properly for VT-x EPT (unable to access the 64 bits cr2 from 32 bits mode).
Property svn:eol-style set to `native` Property svn:keywords set to `Id`
File size: 23.6 KB

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1	/* $Id: HWACCMInternal.h 15440 2008-12-13 13:09:30Z vboxsync $ */
2	/** @file
3	* HWACCM - Internal header file.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22	#ifndef ___HWACCMInternal_h
23	#define ___HWACCMInternal_h
24
25	#include <VBox/cdefs.h>
26	#include <VBox/types.h>
27	#include <VBox/em.h>
28	#include <VBox/stam.h>
29	#include <VBox/dis.h>
30	#include <VBox/hwaccm.h>
31	#include <VBox/pgm.h>
32	#include <VBox/cpum.h>
33	#include <iprt/memobj.h>
34	#include <iprt/cpuset.h>
35	#include <iprt/mp.h>
36
37	#if HC_ARCH_BITS == 64 \|\| defined(VBOX_WITH_HYBRID_32BIT_KERNEL) \|\| defined (VBOX_WITH_64_BITS_GUESTS)
38	/* Enable 64 bits guest support. */
39	# define VBOX_ENABLE_64_BITS_GUESTS
40	#endif
41
42	#define VMX_USE_CACHED_VMCS_ACCESSES
43	#define HWACCM_VMX_EMULATE_REALMODE
44	#define HWACCM_VTX_WITH_EPT
45	#define HWACCM_VTX_WITH_VPID
46
47	__BEGIN_DECLS
48
49
50	/** @defgroup grp_hwaccm_int Internal
51	* @ingroup grp_hwaccm
52	* @internal
53	* @{
54	*/
55
56
57	/** Maximum number of exit reason statistics counters. */
58	#define MAX_EXITREASON_STAT 0x100
59	#define MASK_EXITREASON_STAT 0xff
60
61	/** @name Changed flags
62	* These flags are used to keep track of which important registers that
63	* have been changed since last they were reset.
64	* @{
65	*/
66	#define HWACCM_CHANGED_GUEST_FPU RT_BIT(0)
67	#define HWACCM_CHANGED_GUEST_CR0 RT_BIT(1)
68	#define HWACCM_CHANGED_GUEST_CR3 RT_BIT(2)
69	#define HWACCM_CHANGED_GUEST_CR4 RT_BIT(3)
70	#define HWACCM_CHANGED_GUEST_GDTR RT_BIT(4)
71	#define HWACCM_CHANGED_GUEST_IDTR RT_BIT(5)
72	#define HWACCM_CHANGED_GUEST_LDTR RT_BIT(6)
73	#define HWACCM_CHANGED_GUEST_TR RT_BIT(7)
74	#define HWACCM_CHANGED_GUEST_SYSENTER_MSR RT_BIT(8)
75	#define HWACCM_CHANGED_GUEST_SEGMENT_REGS RT_BIT(9)
76	#define HWACCM_CHANGED_GUEST_DEBUG RT_BIT(10)
77	#define HWACCM_CHANGED_HOST_CONTEXT RT_BIT(11)
78
79	#define HWACCM_CHANGED_ALL ( HWACCM_CHANGED_GUEST_SEGMENT_REGS \
80	\| HWACCM_CHANGED_GUEST_CR0 \
81	\| HWACCM_CHANGED_GUEST_CR3 \
82	\| HWACCM_CHANGED_GUEST_CR4 \
83	\| HWACCM_CHANGED_GUEST_GDTR \
84	\| HWACCM_CHANGED_GUEST_IDTR \
85	\| HWACCM_CHANGED_GUEST_LDTR \
86	\| HWACCM_CHANGED_GUEST_TR \
87	\| HWACCM_CHANGED_GUEST_SYSENTER_MSR \
88	\| HWACCM_CHANGED_GUEST_FPU \
89	\| HWACCM_CHANGED_GUEST_DEBUG \
90	\| HWACCM_CHANGED_HOST_CONTEXT)
91
92	#define HWACCM_CHANGED_ALL_GUEST ( HWACCM_CHANGED_GUEST_SEGMENT_REGS \
93	\| HWACCM_CHANGED_GUEST_CR0 \
94	\| HWACCM_CHANGED_GUEST_CR3 \
95	\| HWACCM_CHANGED_GUEST_CR4 \
96	\| HWACCM_CHANGED_GUEST_GDTR \
97	\| HWACCM_CHANGED_GUEST_IDTR \
98	\| HWACCM_CHANGED_GUEST_LDTR \
99	\| HWACCM_CHANGED_GUEST_TR \
100	\| HWACCM_CHANGED_GUEST_SYSENTER_MSR \
101	\| HWACCM_CHANGED_GUEST_DEBUG \
102	\| HWACCM_CHANGED_GUEST_FPU)
103
104	/** @} */
105
106	/** @name Intercepted traps
107	* Traps that need to be intercepted so we can correctly dispatch them to the guest if required.
108	* Currently #NM and #PF only
109	*/
110	#ifdef VBOX_STRICT
111	#define HWACCM_VMX_TRAP_MASK RT_BIT(X86_XCPT_DE) \| RT_BIT(X86_XCPT_NM) \| RT_BIT(X86_XCPT_PF) \| RT_BIT(X86_XCPT_UD) \| RT_BIT(X86_XCPT_NP) \| RT_BIT(X86_XCPT_SS) \| RT_BIT(X86_XCPT_GP) \| RT_BIT(X86_XCPT_MF)
112	#define HWACCM_SVM_TRAP_MASK HWACCM_VMX_TRAP_MASK
113	#else
114	#define HWACCM_VMX_TRAP_MASK RT_BIT(X86_XCPT_NM) \| RT_BIT(X86_XCPT_PF)
115	#define HWACCM_SVM_TRAP_MASK RT_BIT(X86_XCPT_NM) \| RT_BIT(X86_XCPT_PF)
116	#endif
117	/* All exceptions have to be intercept in emulated real-mode (minues NM & PF as they are always intercepted. */
118	#define HWACCM_VMX_TRAP_MASK_REALMODE RT_BIT(X86_XCPT_DE) \| RT_BIT(X86_XCPT_DB) \| RT_BIT(X86_XCPT_NMI) \| RT_BIT(X86_XCPT_BP) \| RT_BIT(X86_XCPT_OF) \| RT_BIT(X86_XCPT_BR) \| RT_BIT(X86_XCPT_UD) \| RT_BIT(X86_XCPT_DF) \| RT_BIT(X86_XCPT_CO_SEG_OVERRUN) \| RT_BIT(X86_XCPT_TS) \| RT_BIT(X86_XCPT_NP) \| RT_BIT(X86_XCPT_SS) \| RT_BIT(X86_XCPT_GP) \| RT_BIT(X86_XCPT_MF) \| RT_BIT(X86_XCPT_AC) \| RT_BIT(X86_XCPT_MC) \| RT_BIT(X86_XCPT_XF)
119	/** @} */
120
121
122	/** Maxium resume loops allowed in ring 0 (safety precaution) */
123	#define HWACCM_MAX_RESUME_LOOPS 1024
124
125	/** Size for the EPT identity page table (1024 4 MB pages to cover the entire address space). */
126	#define HWACCM_EPT_IDENTITY_PG_TABLE_SIZE PAGE_SIZE
127	/** Size of the TSS structure + 2 pages for the IO bitmap + end byte. */
128	#define HWACCM_VTX_TSS_SIZE (sizeof(VBOXTSS) + 2*PAGE_SIZE + 1)
129	/** Total guest mapped memory needed. */
130	#define HWACCM_VTX_TOTAL_DEVHEAP_MEM (HWACCM_EPT_IDENTITY_PG_TABLE_SIZE + HWACCM_VTX_TSS_SIZE)
131
132	/** HWACCM SSM version
133	*/
134	#define HWACCM_SSM_VERSION 3
135
136	/* Per-cpu information. (host) */
137	typedef struct
138	{
139	RTCPUID idCpu;
140
141	RTR0MEMOBJ pMemObj;
142	/* Current ASID (AMD-V)/VPID (Intel) */
143	uint32_t uCurrentASID;
144	/* TLB flush count */
145	uint32_t cTLBFlushes;
146
147	/* Set the first time a cpu is used to make sure we start with a clean TLB. */
148	bool fFlushTLB;
149
150	/** Configured for VT-x or AMD-V. */
151	bool fConfigured;
152
153	/** In use by our code. (for power suspend) */
154	volatile bool fInUse;
155	} HWACCM_CPUINFO;
156	typedef HWACCM_CPUINFO *PHWACCM_CPUINFO;
157
158	/* VT-x capability qword. */
159	typedef union
160	{
161	struct
162	{
163	uint32_t disallowed0;
164	uint32_t allowed1;
165	} n;
166	uint64_t u;
167	} VMX_CAPABILITY;
168
169	/**
170	* Switcher function, HC to RC.
171	*
172	* @param pVM The VM handle.
173	* @returns Return code indicating the action to take.
174	*/
175	typedef DECLASMTYPE(int) FNHWACCMSWITCHERHC(PVM pVM);
176	/** Pointer to switcher function. */
177	typedef FNHWACCMSWITCHERHC *PFNHWACCMSWITCHERHC;
178
179	/**
180	* HWACCM VM Instance data.
181	* Changes to this must checked against the padding of the cfgm union in VM!
182	*/
183	typedef struct HWACCM
184	{
185	/** Set when we've initialized VMX or SVM. */
186	bool fInitialized;
187
188	/** Set when we're using VMX/SVN at that moment. */
189	bool fActive;
190
191	/** Set when hardware acceleration is allowed. */
192	bool fAllowed;
193
194	/** Set if nested paging is enabled. */
195	bool fNestedPaging;
196
197	/** Set if nested paging is allowed. */
198	bool fAllowNestedPaging;
199
200	/** Set if we're supposed to inject an NMI. */
201	bool fInjectNMI;
202
203	/** Set if we can support 64-bit guests or not. */
204	bool fAllow64BitGuests;
205
206	/** Explicit alignment padding to make 32-bit gcc align u64RegisterMask
207	* naturally. */
208	bool padding[1];
209
210	/** And mask for copying register contents. */
211	uint64_t u64RegisterMask;
212
213	/** Maximum ASID allowed. */
214	RTUINT uMaxASID;
215
216	#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
217	/** 32 to 64 bits switcher entrypoint. */
218	R0PTRTYPE(PFNHWACCMSWITCHERHC) pfnHost32ToGuest64R0;
219
220	/* AMD-V 64 bits vmrun handler */
221	RTRCPTR pfnSVMGCVMRun64;
222
223	/* VT-x 64 bits vmlaunch handler */
224	RTRCPTR pfnVMXGCStartVM64;
225
226	/* RC handler to setup the 64 bits FPU state. */
227	RTRCPTR pfnSaveGuestFPU64;
228
229	/* RC handler to setup the 64 bits debug state. */
230	RTRCPTR pfnSaveGuestDebug64;
231
232	# ifdef DEBUG
233	/* Test handler */
234	RTRCPTR pfnTest64;
235
236	RTRCPTR uAlignment[1];
237	# endif
238	#elif defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
239	uint32_t u32Alignment[1];
240	#endif
241
242	struct
243	{
244	/** Set by the ring-0 driver to indicate VMX is supported by the CPU. */
245	bool fSupported;
246
247	/** Set when we've enabled VMX. */
248	bool fEnabled;
249
250	/** Set if VPID is supported. */
251	bool fVPID;
252
253	/** Set if VT-x VPID is allowed. */
254	bool fAllowVPID;
255
256	/** Virtual address of the TSS page used for real mode emulation. */
257	R3PTRTYPE(PVBOXTSS) pRealModeTSS;
258
259	/** Virtual address of the identity page table used for real mode and protected mode without paging emulation in EPT mode. */
260	R3PTRTYPE(PX86PD) pNonPagingModeEPTPageTable;
261
262	/** R0 memory object for the virtual APIC mmio cache. */
263	RTR0MEMOBJ pMemObjAPIC;
264	/** Physical address of the virtual APIC mmio cache. */
265	RTHCPHYS pAPICPhys;
266	/** Virtual address of the virtual APIC mmio cache. */
267	R0PTRTYPE(uint8_t *) pAPIC;
268
269	/** R0 memory object for the MSR bitmap (1 page). */
270	RTR0MEMOBJ pMemObjMSRBitmap;
271	/** Physical address of the MSR bitmap (1 page). */
272	RTHCPHYS pMSRBitmapPhys;
273	/** Virtual address of the MSR bitmap (1 page). */
274	R0PTRTYPE(uint8_t *) pMSRBitmap;
275
276	/** R0 memory object for the MSR entry load page (guest MSRs). */
277	RTR0MEMOBJ pMemObjMSREntryLoad;
278	/** Physical address of the MSR entry load page (guest MSRs). */
279	RTHCPHYS pMSREntryLoadPhys;
280	/** Virtual address of the MSR entry load page (guest MSRs). */
281	R0PTRTYPE(uint8_t *) pMSREntryLoad;
282
283	/** R0 memory object for the MSR exit store page (guest MSRs). */
284	RTR0MEMOBJ pMemObjMSRExitStore;
285	/** Physical address of the MSR exit store page (guest MSRs). */
286	RTHCPHYS pMSRExitStorePhys;
287	/** Virtual address of the MSR exit store page (guest MSRs). */
288	R0PTRTYPE(uint8_t *) pMSRExitStore;
289
290	/** R0 memory object for the MSR exit load page (host MSRs). */
291	RTR0MEMOBJ pMemObjMSRExitLoad;
292	/** Physical address of the MSR exit load page (host MSRs). */
293	RTHCPHYS pMSRExitLoadPhys;
294	/** Virtual address of the MSR exit load page (host MSRs). */
295	R0PTRTYPE(uint8_t *) pMSRExitLoad;
296
297	/** Ring 0 handlers for VT-x. */
298	DECLR0CALLBACKMEMBER(void, pfnSetupTaggedTLB, (PVM pVM, PVMCPU pVCpu));
299
300	/** Host CR4 value (set by ring-0 VMX init) */
301	uint64_t hostCR4;
302
303	/** VMX MSR values */
304	struct
305	{
306	uint64_t feature_ctrl;
307	uint64_t vmx_basic_info;
308	VMX_CAPABILITY vmx_pin_ctls;
309	VMX_CAPABILITY vmx_proc_ctls;
310	VMX_CAPABILITY vmx_proc_ctls2;
311	VMX_CAPABILITY vmx_exit;
312	VMX_CAPABILITY vmx_entry;
313	uint64_t vmx_misc;
314	uint64_t vmx_cr0_fixed0;
315	uint64_t vmx_cr0_fixed1;
316	uint64_t vmx_cr4_fixed0;
317	uint64_t vmx_cr4_fixed1;
318	uint64_t vmx_vmcs_enum;
319	uint64_t vmx_eptcaps;
320	} msr;
321
322	/** Flush types for invept & invvpid; they depend on capabilities. */
323	VMX_FLUSH enmFlushPage;
324	VMX_FLUSH enmFlushContext;
325	} vmx;
326
327	struct
328	{
329	/** Set by the ring-0 driver to indicate SVM is supported by the CPU. */
330	bool fSupported;
331	/** Set when we've enabled SVM. */
332	bool fEnabled;
333	/** Set if erratum 170 affects the AMD cpu. */
334	bool fAlwaysFlushTLB;
335	/** Explicit alignment padding to make 32-bit gcc align u64RegisterMask
336	* naturally. */
337	bool padding[1];
338
339	/** R0 memory object for the host VM control block (VMCB). */
340	RTR0MEMOBJ pMemObjVMCBHost;
341	/** Physical address of the host VM control block (VMCB). */
342	RTHCPHYS pVMCBHostPhys;
343	/** Virtual address of the host VM control block (VMCB). */
344	R0PTRTYPE(void *) pVMCBHost;
345
346	/** R0 memory object for the IO bitmap (12kb). */
347	RTR0MEMOBJ pMemObjIOBitmap;
348	/** Physical address of the IO bitmap (12kb). */
349	RTHCPHYS pIOBitmapPhys;
350	/** Virtual address of the IO bitmap. */
351	R0PTRTYPE(void *) pIOBitmap;
352
353	/** R0 memory object for the MSR bitmap (8kb). */
354	RTR0MEMOBJ pMemObjMSRBitmap;
355	/** Physical address of the MSR bitmap (8kb). */
356	RTHCPHYS pMSRBitmapPhys;
357	/** Virtual address of the MSR bitmap. */
358	R0PTRTYPE(void *) pMSRBitmap;
359
360	/** SVM revision. */
361	uint32_t u32Rev;
362
363	/** SVM feature bits from cpuid 0x8000000a */
364	uint32_t u32Features;
365	} svm;
366
367	struct
368	{
369	uint32_t u32AMDFeatureECX;
370	uint32_t u32AMDFeatureEDX;
371	} cpuid;
372
373	/** Saved error from detection */
374	int32_t lLastError;
375
376	/** HWACCMR0Init was run */
377	bool fHWACCMR0Init;
378	} HWACCM;
379	/** Pointer to HWACCM VM instance data. */
380	typedef HWACCM *PHWACCM;
381
382	/* Maximum number of cached entries. */
383	#define VMCSCACHE_MAX_ENTRY 256
384
385	/* Structure for storing read and write VMCS actions. */
386	typedef struct VMCSCACHE
387	{
388	/* CR2 is saved here for EPT syncing. */
389	uint64_t cr2;
390	struct
391	{
392	uint32_t cValidEntries;
393	uint32_t uAlignment;
394	uint32_t aField[VMCSCACHE_MAX_ENTRY];
395	uint64_t aFieldVal[VMCSCACHE_MAX_ENTRY];
396	} Write;
397	struct
398	{
399	uint32_t cValidEntries;
400	uint32_t uAlignment;
401	uint32_t aField[VMCSCACHE_MAX_ENTRY];
402	uint64_t aFieldVal[VMCSCACHE_MAX_ENTRY];
403	} Read;
404	#ifdef DEBUG
405	struct
406	{
407	RTHCPHYS pPageCpuPhys;
408	RTHCPHYS pVMCSPhys;
409	RTGCPTR pCache;
410	RTGCPTR pCtx;
411	} TestIn;
412	struct
413	{
414	RTHCPHYS pVMCSPhys;
415	RTGCPTR pCache;
416	RTGCPTR pCtx;
417	} TestOut;
418	struct
419	{
420	uint64_t param1;
421	uint64_t param2;
422	uint64_t param3;
423	uint64_t param4;
424	} ScratchPad;
425	#endif
426	} VMCSCACHE;
427	/** Pointer to VMCSCACHE. */
428	typedef VMCSCACHE *PVMCSCACHE;
429
430	/**
431	* HWACCM VMCPU Instance data.
432	*/
433	typedef struct HWACCMCPU
434	{
435	/** Old style FPU reporting trap mask override performed (optimization) */
436	bool fFPUOldStyleOverride;
437
438	/** Set if we don't have to flush the TLB on VM entry. */
439	bool fResumeVM;
440
441	/** Set if we need to flush the TLB during the world switch. */
442	bool fForceTLBFlush;
443
444	/** Explicit alignment padding to make 32-bit gcc align u64RegisterMask
445	* naturally. */
446	bool padding[1];
447
448	/** HWACCM_CHANGED_* flags. */
449	RTUINT fContextUseFlags;
450
451	/* Id of the last cpu we were executing code on (NIL_RTCPUID for the first time) */
452	RTCPUID idLastCpu;
453
454	/* TLB flush count */
455	RTUINT cTLBFlushes;
456
457	/* Current ASID in use by the VM */
458	RTUINT uCurrentASID;
459
460	struct
461	{
462	/** R0 memory object for the VM control structure (VMCS). */
463	RTR0MEMOBJ pMemObjVMCS;
464	/** Physical address of the VM control structure (VMCS). */
465	RTHCPHYS pVMCSPhys;
466	/** Virtual address of the VM control structure (VMCS). */
467	R0PTRTYPE(void *) pVMCS;
468
469	/** Ring 0 handlers for VT-x. */
470	DECLR0CALLBACKMEMBER(int, pfnStartVM,(RTHCUINT fResume, PCPUMCTX pCtx, PVMCSCACHE pCache, PVM pVM, PVMCPU pVCpu));
471
472	/** Current VMX_VMCS_CTRL_PROC_EXEC_CONTROLS. */
473	uint64_t proc_ctls;
474
475	/** Current CR0 mask. */
476	uint64_t cr0_mask;
477	/** Current CR4 mask. */
478	uint64_t cr4_mask;
479
480	/** Current EPTP. */
481	RTHCPHYS GCPhysEPTP;
482
483	/** VMCS cache. */
484	VMCSCACHE VMCSCache;
485
486	/** Real-mode emulation state. */
487	struct
488	{
489	X86EFLAGS eflags;
490	uint32_t fValid;
491	} RealMode;
492
493	struct
494	{
495	uint64_t u64VMCSPhys;
496	uint32_t ulVMCSRevision;
497	uint32_t ulInstrError;
498	uint32_t ulExitReason;
499	RTCPUID idEnteredCpu;
500	RTCPUID idCurrentCpu;
501	uint32_t padding;
502	} lasterror;
503
504	/** The last known guest paging mode. */
505	PGMMODE enmCurrGuestMode;
506	} vmx;
507
508	struct
509	{
510	/** R0 memory object for the VM control block (VMCB). */
511	RTR0MEMOBJ pMemObjVMCB;
512	/** Physical address of the VM control block (VMCB). */
513	RTHCPHYS pVMCBPhys;
514	/** Virtual address of the VM control block (VMCB). */
515	R0PTRTYPE(void *) pVMCB;
516
517	/** Ring 0 handlers for VT-x. */
518	DECLR0CALLBACKMEMBER(int, pfnVMRun,(RTHCPHYS pVMCBHostPhys, RTHCPHYS pVMCBPhys, PCPUMCTX pCtx, PVM pVM, PVMCPU pVCpu));
519
520	} svm;
521
522	/** Event injection state. */
523	struct
524	{
525	uint32_t fPending;
526	uint32_t errCode;
527	uint64_t intInfo;
528	} Event;
529
530	/** Currenty shadow paging mode. */
531	PGMMODE enmShadowMode;
532
533	/** The CPU ID of the CPU currently owning the VMCS. Set in
534	* HWACCMR0Enter and cleared in HWACCMR0Leave. */
535	RTCPUID idEnteredCpu;
536
537	STAMPROFILEADV StatEntry;
538	STAMPROFILEADV StatExit1;
539	STAMPROFILEADV StatExit2;
540	#if 1 /* temporary for tracking down darwin issues. */
541	STAMPROFILEADV StatExit2Sub1;
542	STAMPROFILEADV StatExit2Sub2;
543	STAMPROFILEADV StatExit2Sub3;
544	#endif
545	STAMPROFILEADV StatInGC;
546
547	STAMCOUNTER StatIntInject;
548
549	STAMCOUNTER StatExitShadowNM;
550	STAMCOUNTER StatExitGuestNM;
551	STAMCOUNTER StatExitShadowPF;
552	STAMCOUNTER StatExitGuestPF;
553	STAMCOUNTER StatExitGuestUD;
554	STAMCOUNTER StatExitGuestSS;
555	STAMCOUNTER StatExitGuestNP;
556	STAMCOUNTER StatExitGuestGP;
557	STAMCOUNTER StatExitGuestDE;
558	STAMCOUNTER StatExitGuestDB;
559	STAMCOUNTER StatExitGuestMF;
560	STAMCOUNTER StatExitInvpg;
561	STAMCOUNTER StatExitInvd;
562	STAMCOUNTER StatExitCpuid;
563	STAMCOUNTER StatExitRdtsc;
564	STAMCOUNTER StatExitCRxWrite[8];
565	STAMCOUNTER StatExitCRxRead[8];
566	STAMCOUNTER StatExitDRxWrite;
567	STAMCOUNTER StatExitDRxRead;
568	STAMCOUNTER StatExitCLTS;
569	STAMCOUNTER StatExitLMSW;
570	STAMCOUNTER StatExitIOWrite;
571	STAMCOUNTER StatExitIORead;
572	STAMCOUNTER StatExitIOStringWrite;
573	STAMCOUNTER StatExitIOStringRead;
574	STAMCOUNTER StatExitIrqWindow;
575	STAMCOUNTER StatExitMaxResume;
576	STAMCOUNTER StatIntReinject;
577	STAMCOUNTER StatPendingHostIrq;
578
579	STAMCOUNTER StatFlushPageManual;
580	STAMCOUNTER StatFlushPhysPageManual;
581	STAMCOUNTER StatFlushTLBManual;
582	STAMCOUNTER StatFlushPageInvlpg;
583	STAMCOUNTER StatFlushTLBWorldSwitch;
584	STAMCOUNTER StatNoFlushTLBWorldSwitch;
585	STAMCOUNTER StatFlushTLBCRxChange;
586	STAMCOUNTER StatFlushASID;
587	STAMCOUNTER StatFlushTLBInvlpga;
588
589	STAMCOUNTER StatSwitchGuestIrq;
590	STAMCOUNTER StatSwitchToR3;
591
592	STAMCOUNTER StatTSCOffset;
593	STAMCOUNTER StatTSCIntercept;
594
595	STAMCOUNTER StatExitReasonNPF;
596	STAMCOUNTER StatDRxArmed;
597	STAMCOUNTER StatDRxContextSwitch;
598	STAMCOUNTER StatDRxIOCheck;
599
600
601	R3PTRTYPE(PSTAMCOUNTER) paStatExitReason;
602	R0PTRTYPE(PSTAMCOUNTER) paStatExitReasonR0;
603	} HWACCMCPU;
604	/** Pointer to HWACCM VM instance data. */
605	typedef HWACCMCPU *PHWACCMCPU;
606
607
608	#ifdef IN_RING0
609
610	VMMR0DECL(PHWACCM_CPUINFO) HWACCMR0GetCurrentCpu();
611	VMMR0DECL(PHWACCM_CPUINFO) HWACCMR0GetCurrentCpuEx(RTCPUID idCpu);
612
613
614	#ifdef VBOX_STRICT
615	VMMR0DECL(void) HWACCMDumpRegs(PVM pVM, PCPUMCTX pCtx);
616	VMMR0DECL(void) HWACCMR0DumpDescriptor(PX86DESCHC Desc, RTSEL Sel, const char *pszMsg);
617	#else
618	#define HWACCMDumpRegs(a, b) do { } while (0)
619	#define HWACCMR0DumpDescriptor(a, b, c) do { } while (0)
620	#endif
621
622	/* Dummy callback handlers. */
623	VMMR0DECL(int) HWACCMR0DummyEnter(PVM pVM, PVMCPU pVCpu, PHWACCM_CPUINFO pCpu);
624	VMMR0DECL(int) HWACCMR0DummyLeave(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
625	VMMR0DECL(int) HWACCMR0DummyEnableCpu(PHWACCM_CPUINFO pCpu, PVM pVM, void *pvPageCpu, RTHCPHYS pPageCpuPhys);
626	VMMR0DECL(int) HWACCMR0DummyDisableCpu(PHWACCM_CPUINFO pCpu, void *pvPageCpu, RTHCPHYS pPageCpuPhys);
627	VMMR0DECL(int) HWACCMR0DummyInitVM(PVM pVM);
628	VMMR0DECL(int) HWACCMR0DummyTermVM(PVM pVM);
629	VMMR0DECL(int) HWACCMR0DummySetupVM(PVM pVM);
630	VMMR0DECL(int) HWACCMR0DummyRunGuestCode(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
631	VMMR0DECL(int) HWACCMR0DummySaveHostState(PVM pVM, PVMCPU pVCpu);
632	VMMR0DECL(int) HWACCMR0DummyLoadGuestState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
633
634
635	# ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
636	/**
637	* Gets 64-bit GDTR and IDTR on darwin.
638	* @param pGdtr Where to store the 64-bit GDTR.
639	* @param pIdtr Where to store the 64-bit IDTR.
640	*/
641	DECLASM(void) hwaccmR0Get64bitGDTRandIDTR(PX86XDTR64 pGdtr, PX86XDTR64 pIdtr);
642
643	/**
644	* Gets 64-bit CR3 on darwin.
645	* @returns CR3
646	*/
647	DECLASM(uint64_t) hwaccmR0Get64bitCR3(void);
648	# endif
649
650	#endif /* IN_RING0 */
651
652	/** @} */
653
654	__END_DECLS
655
656	#endif
657

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source: vbox/trunk/src/VBox/VMM/HWACCMInternal.h@ 15440

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