HWACCMInternal.h@ 19335

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1	/* $Id: HWACCMInternal.h 19335 2009-05-04 16:04:42Z vboxsync $ */
2	/** @file
3	* HWACCM - Internal header file.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22	#ifndef ___HWACCMInternal_h
23	#define ___HWACCMInternal_h
24
25	#include <VBox/cdefs.h>
26	#include <VBox/types.h>
27	#include <VBox/em.h>
28	#include <VBox/stam.h>
29	#include <VBox/dis.h>
30	#include <VBox/hwaccm.h>
31	#include <VBox/pgm.h>
32	#include <VBox/cpum.h>
33	#include <iprt/memobj.h>
34	#include <iprt/cpuset.h>
35	#include <iprt/mp.h>
36
37	#if HC_ARCH_BITS == 64 \|\| defined(VBOX_WITH_HYBRID_32BIT_KERNEL) \|\| defined (VBOX_WITH_64_BITS_GUESTS)
38	/* Enable 64 bits guest support. */
39	# define VBOX_ENABLE_64_BITS_GUESTS
40	#endif
41
42	#define VMX_USE_CACHED_VMCS_ACCESSES
43	#define HWACCM_VMX_EMULATE_REALMODE
44	#define HWACCM_VTX_WITH_EPT
45	#define HWACCM_VTX_WITH_VPID
46
47	__BEGIN_DECLS
48
49
50	/** @defgroup grp_hwaccm_int Internal
51	* @ingroup grp_hwaccm
52	* @internal
53	* @{
54	*/
55
56
57	/** Maximum number of exit reason statistics counters. */
58	#define MAX_EXITREASON_STAT 0x100
59	#define MASK_EXITREASON_STAT 0xff
60
61	/** @name Changed flags
62	* These flags are used to keep track of which important registers that
63	* have been changed since last they were reset.
64	* @{
65	*/
66	#define HWACCM_CHANGED_GUEST_FPU RT_BIT(0)
67	#define HWACCM_CHANGED_GUEST_CR0 RT_BIT(1)
68	#define HWACCM_CHANGED_GUEST_CR3 RT_BIT(2)
69	#define HWACCM_CHANGED_GUEST_CR4 RT_BIT(3)
70	#define HWACCM_CHANGED_GUEST_GDTR RT_BIT(4)
71	#define HWACCM_CHANGED_GUEST_IDTR RT_BIT(5)
72	#define HWACCM_CHANGED_GUEST_LDTR RT_BIT(6)
73	#define HWACCM_CHANGED_GUEST_TR RT_BIT(7)
74	#define HWACCM_CHANGED_GUEST_SYSENTER_MSR RT_BIT(8)
75	#define HWACCM_CHANGED_GUEST_SEGMENT_REGS RT_BIT(9)
76	#define HWACCM_CHANGED_GUEST_DEBUG RT_BIT(10)
77	#define HWACCM_CHANGED_HOST_CONTEXT RT_BIT(11)
78
79	#define HWACCM_CHANGED_ALL ( HWACCM_CHANGED_GUEST_SEGMENT_REGS \
80	\| HWACCM_CHANGED_GUEST_CR0 \
81	\| HWACCM_CHANGED_GUEST_CR3 \
82	\| HWACCM_CHANGED_GUEST_CR4 \
83	\| HWACCM_CHANGED_GUEST_GDTR \
84	\| HWACCM_CHANGED_GUEST_IDTR \
85	\| HWACCM_CHANGED_GUEST_LDTR \
86	\| HWACCM_CHANGED_GUEST_TR \
87	\| HWACCM_CHANGED_GUEST_SYSENTER_MSR \
88	\| HWACCM_CHANGED_GUEST_FPU \
89	\| HWACCM_CHANGED_GUEST_DEBUG \
90	\| HWACCM_CHANGED_HOST_CONTEXT)
91
92	#define HWACCM_CHANGED_ALL_GUEST ( HWACCM_CHANGED_GUEST_SEGMENT_REGS \
93	\| HWACCM_CHANGED_GUEST_CR0 \
94	\| HWACCM_CHANGED_GUEST_CR3 \
95	\| HWACCM_CHANGED_GUEST_CR4 \
96	\| HWACCM_CHANGED_GUEST_GDTR \
97	\| HWACCM_CHANGED_GUEST_IDTR \
98	\| HWACCM_CHANGED_GUEST_LDTR \
99	\| HWACCM_CHANGED_GUEST_TR \
100	\| HWACCM_CHANGED_GUEST_SYSENTER_MSR \
101	\| HWACCM_CHANGED_GUEST_DEBUG \
102	\| HWACCM_CHANGED_GUEST_FPU)
103
104	/** @} */
105
106	/** @name Intercepted traps
107	* Traps that need to be intercepted so we can correctly dispatch them to the guest if required.
108	* Currently #NM and #PF only
109	*/
110	#ifdef VBOX_STRICT
111	#define HWACCM_VMX_TRAP_MASK RT_BIT(X86_XCPT_DE) \| RT_BIT(X86_XCPT_NM) \| RT_BIT(X86_XCPT_PF) \| RT_BIT(X86_XCPT_UD) \| RT_BIT(X86_XCPT_NP) \| RT_BIT(X86_XCPT_SS) \| RT_BIT(X86_XCPT_GP) \| RT_BIT(X86_XCPT_MF)
112	#define HWACCM_SVM_TRAP_MASK HWACCM_VMX_TRAP_MASK
113	#else
114	#define HWACCM_VMX_TRAP_MASK RT_BIT(X86_XCPT_NM) \| RT_BIT(X86_XCPT_PF)
115	#define HWACCM_SVM_TRAP_MASK RT_BIT(X86_XCPT_NM) \| RT_BIT(X86_XCPT_PF)
116	#endif
117	/* All exceptions have to be intercept in emulated real-mode (minues NM & PF as they are always intercepted. */
118	#define HWACCM_VMX_TRAP_MASK_REALMODE RT_BIT(X86_XCPT_DE) \| RT_BIT(X86_XCPT_DB) \| RT_BIT(X86_XCPT_NMI) \| RT_BIT(X86_XCPT_BP) \| RT_BIT(X86_XCPT_OF) \| RT_BIT(X86_XCPT_BR) \| RT_BIT(X86_XCPT_UD) \| RT_BIT(X86_XCPT_DF) \| RT_BIT(X86_XCPT_CO_SEG_OVERRUN) \| RT_BIT(X86_XCPT_TS) \| RT_BIT(X86_XCPT_NP) \| RT_BIT(X86_XCPT_SS) \| RT_BIT(X86_XCPT_GP) \| RT_BIT(X86_XCPT_MF) \| RT_BIT(X86_XCPT_AC) \| RT_BIT(X86_XCPT_MC) \| RT_BIT(X86_XCPT_XF)
119	/** @} */
120
121
122	/** Maxium resume loops allowed in ring 0 (safety precaution) */
123	#define HWACCM_MAX_RESUME_LOOPS 1024
124
125	/** Maximum number of page flushes we are willing to remember before considering a full TLB flush. */
126	#define HWACCM_MAX_TLB_SHOOTDOWN_PAGES 16
127
128	/** Size for the EPT identity page table (1024 4 MB pages to cover the entire address space). */
129	#define HWACCM_EPT_IDENTITY_PG_TABLE_SIZE PAGE_SIZE
130	/** Size of the TSS structure + 2 pages for the IO bitmap + end byte. */
131	#define HWACCM_VTX_TSS_SIZE (sizeof(VBOXTSS) + 2*PAGE_SIZE + 1)
132	/** Total guest mapped memory needed. */
133	#define HWACCM_VTX_TOTAL_DEVHEAP_MEM (HWACCM_EPT_IDENTITY_PG_TABLE_SIZE + HWACCM_VTX_TSS_SIZE)
134
135	/** HWACCM SSM version
136	*/
137	#define HWACCM_SSM_VERSION 4
138	#define HWACCM_SSM_VERSION_2_0_X 3
139
140	/* Per-cpu information. (host) */
141	typedef struct
142	{
143	RTCPUID idCpu;
144
145	RTR0MEMOBJ pMemObj;
146	/* Current ASID (AMD-V)/VPID (Intel) */
147	uint32_t uCurrentASID;
148	/* TLB flush count */
149	uint32_t cTLBFlushes;
150
151	/* Set the first time a cpu is used to make sure we start with a clean TLB. */
152	bool fFlushTLB;
153
154	/** Configured for VT-x or AMD-V. */
155	bool fConfigured;
156
157	/** In use by our code. (for power suspend) */
158	volatile bool fInUse;
159	} HWACCM_CPUINFO;
160	typedef HWACCM_CPUINFO *PHWACCM_CPUINFO;
161
162	/* VT-x capability qword. */
163	typedef union
164	{
165	struct
166	{
167	uint32_t disallowed0;
168	uint32_t allowed1;
169	} n;
170	uint64_t u;
171	} VMX_CAPABILITY;
172
173	/**
174	* Switcher function, HC to RC.
175	*
176	* @param pVM The VM handle.
177	* @returns Return code indicating the action to take.
178	*/
179	typedef DECLASMTYPE(int) FNHWACCMSWITCHERHC(PVM pVM);
180	/** Pointer to switcher function. */
181	typedef FNHWACCMSWITCHERHC *PFNHWACCMSWITCHERHC;
182
183	/**
184	* HWACCM VM Instance data.
185	* Changes to this must checked against the padding of the cfgm union in VM!
186	*/
187	typedef struct HWACCM
188	{
189	/** Set when we've initialized VMX or SVM. */
190	bool fInitialized;
191
192	/** Set when we're using VMX/SVN at that moment. */
193	bool fActive;
194
195	/** Set when hardware acceleration is allowed. */
196	bool fAllowed;
197
198	/** Set if nested paging is enabled. */
199	bool fNestedPaging;
200
201	/** Set if nested paging is allowed. */
202	bool fAllowNestedPaging;
203
204	/** Set if we're supposed to inject an NMI. */
205	bool fInjectNMI;
206
207	/** Set if we can support 64-bit guests or not. */
208	bool fAllow64BitGuests;
209
210	/** Explicit alignment padding to make 32-bit gcc align u64RegisterMask
211	* naturally. */
212	bool padding[1];
213
214	/** And mask for copying register contents. */
215	uint64_t u64RegisterMask;
216
217	/** Maximum ASID allowed. */
218	RTUINT uMaxASID;
219
220	#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
221	/** 32 to 64 bits switcher entrypoint. */
222	R0PTRTYPE(PFNHWACCMSWITCHERHC) pfnHost32ToGuest64R0;
223
224	/* AMD-V 64 bits vmrun handler */
225	RTRCPTR pfnSVMGCVMRun64;
226
227	/* VT-x 64 bits vmlaunch handler */
228	RTRCPTR pfnVMXGCStartVM64;
229
230	/* RC handler to setup the 64 bits FPU state. */
231	RTRCPTR pfnSaveGuestFPU64;
232
233	/* RC handler to setup the 64 bits debug state. */
234	RTRCPTR pfnSaveGuestDebug64;
235
236	/* Test handler */
237	RTRCPTR pfnTest64;
238
239	RTRCPTR uAlignment[1];
240	#elif defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
241	uint32_t u32Alignment[1];
242	#endif
243
244	struct
245	{
246	/** Set by the ring-0 driver to indicate VMX is supported by the CPU. */
247	bool fSupported;
248
249	/** Set when we've enabled VMX. */
250	bool fEnabled;
251
252	/** Set if VPID is supported. */
253	bool fVPID;
254
255	/** Set if VT-x VPID is allowed. */
256	bool fAllowVPID;
257
258	/** Virtual address of the TSS page used for real mode emulation. */
259	R3PTRTYPE(PVBOXTSS) pRealModeTSS;
260
261	/** Virtual address of the identity page table used for real mode and protected mode without paging emulation in EPT mode. */
262	R3PTRTYPE(PX86PD) pNonPagingModeEPTPageTable;
263
264	/** R0 memory object for the virtual APIC mmio cache. */
265	RTR0MEMOBJ pMemObjAPIC;
266	/** Physical address of the virtual APIC mmio cache. */
267	RTHCPHYS pAPICPhys;
268	/** Virtual address of the virtual APIC mmio cache. */
269	R0PTRTYPE(uint8_t *) pAPIC;
270
271	/** R0 memory object for the MSR bitmap (1 page). */
272	RTR0MEMOBJ pMemObjMSRBitmap;
273	/** Physical address of the MSR bitmap (1 page). */
274	RTHCPHYS pMSRBitmapPhys;
275	/** Virtual address of the MSR bitmap (1 page). */
276	R0PTRTYPE(uint8_t *) pMSRBitmap;
277
278	/** R0 memory object for the MSR entry load page (guest MSRs). */
279	RTR0MEMOBJ pMemObjMSREntryLoad;
280	/** Physical address of the MSR entry load page (guest MSRs). */
281	RTHCPHYS pMSREntryLoadPhys;
282	/** Virtual address of the MSR entry load page (guest MSRs). */
283	R0PTRTYPE(uint8_t *) pMSREntryLoad;
284
285	#ifdef VBOX_WITH_CRASHDUMP_MAGIC
286	RTR0MEMOBJ pMemObjScratch;
287	RTHCPHYS pScratchPhys;
288	R0PTRTYPE(uint8_t *) pScratch;
289	#endif
290	/** R0 memory object for the MSR exit store page (guest MSRs). */
291	RTR0MEMOBJ pMemObjMSRExitStore;
292	/** Physical address of the MSR exit store page (guest MSRs). */
293	RTHCPHYS pMSRExitStorePhys;
294	/** Virtual address of the MSR exit store page (guest MSRs). */
295	R0PTRTYPE(uint8_t *) pMSRExitStore;
296
297	/** R0 memory object for the MSR exit load page (host MSRs). */
298	RTR0MEMOBJ pMemObjMSRExitLoad;
299	/** Physical address of the MSR exit load page (host MSRs). */
300	RTHCPHYS pMSRExitLoadPhys;
301	/** Virtual address of the MSR exit load page (host MSRs). */
302	R0PTRTYPE(uint8_t *) pMSRExitLoad;
303
304	/** Ring 0 handlers for VT-x. */
305	DECLR0CALLBACKMEMBER(void, pfnSetupTaggedTLB, (PVM pVM, PVMCPU pVCpu));
306
307	/** Host CR4 value (set by ring-0 VMX init) */
308	uint64_t hostCR4;
309
310	/** VMX MSR values */
311	struct
312	{
313	uint64_t feature_ctrl;
314	uint64_t vmx_basic_info;
315	VMX_CAPABILITY vmx_pin_ctls;
316	VMX_CAPABILITY vmx_proc_ctls;
317	VMX_CAPABILITY vmx_proc_ctls2;
318	VMX_CAPABILITY vmx_exit;
319	VMX_CAPABILITY vmx_entry;
320	uint64_t vmx_misc;
321	uint64_t vmx_cr0_fixed0;
322	uint64_t vmx_cr0_fixed1;
323	uint64_t vmx_cr4_fixed0;
324	uint64_t vmx_cr4_fixed1;
325	uint64_t vmx_vmcs_enum;
326	uint64_t vmx_eptcaps;
327	} msr;
328
329	/** Flush types for invept & invvpid; they depend on capabilities. */
330	VMX_FLUSH enmFlushPage;
331	VMX_FLUSH enmFlushContext;
332	} vmx;
333
334	struct
335	{
336	/** Set by the ring-0 driver to indicate SVM is supported by the CPU. */
337	bool fSupported;
338	/** Set when we've enabled SVM. */
339	bool fEnabled;
340	/** Set if erratum 170 affects the AMD cpu. */
341	bool fAlwaysFlushTLB;
342	/** Explicit alignment padding to make 32-bit gcc align u64RegisterMask
343	* naturally. */
344	bool padding[1];
345
346	/** R0 memory object for the host VM control block (VMCB). */
347	RTR0MEMOBJ pMemObjVMCBHost;
348	/** Physical address of the host VM control block (VMCB). */
349	RTHCPHYS pVMCBHostPhys;
350	/** Virtual address of the host VM control block (VMCB). */
351	R0PTRTYPE(void *) pVMCBHost;
352
353	/** R0 memory object for the IO bitmap (12kb). */
354	RTR0MEMOBJ pMemObjIOBitmap;
355	/** Physical address of the IO bitmap (12kb). */
356	RTHCPHYS pIOBitmapPhys;
357	/** Virtual address of the IO bitmap. */
358	R0PTRTYPE(void *) pIOBitmap;
359
360	/** R0 memory object for the MSR bitmap (8kb). */
361	RTR0MEMOBJ pMemObjMSRBitmap;
362	/** Physical address of the MSR bitmap (8kb). */
363	RTHCPHYS pMSRBitmapPhys;
364	/** Virtual address of the MSR bitmap. */
365	R0PTRTYPE(void *) pMSRBitmap;
366
367	/** SVM revision. */
368	uint32_t u32Rev;
369
370	/** SVM feature bits from cpuid 0x8000000a */
371	uint32_t u32Features;
372	} svm;
373
374	struct
375	{
376	uint32_t u32AMDFeatureECX;
377	uint32_t u32AMDFeatureEDX;
378	} cpuid;
379
380	/** Saved error from detection */
381	int32_t lLastError;
382
383	/** HWACCMR0Init was run */
384	bool fHWACCMR0Init;
385	} HWACCM;
386	/** Pointer to HWACCM VM instance data. */
387	typedef HWACCM *PHWACCM;
388
389	/* Maximum number of cached entries. */
390	#define VMCSCACHE_MAX_ENTRY 128
391
392	/* Structure for storing read and write VMCS actions. */
393	typedef struct VMCSCACHE
394	{
395	#ifdef VBOX_WITH_CRASHDUMP_MAGIC
396	/* Magic marker for searching in crash dumps. */
397	uint8_t aMagic[16];
398	uint64_t uMagic;
399	uint64_t u64TimeEntry;
400	uint64_t u64TimeSwitch;
401	uint64_t cResume;
402	uint64_t interPD;
403	uint64_t pSwitcher;
404	uint32_t uPos;
405	uint32_t idCpu;
406	#endif
407	/* CR2 is saved here for EPT syncing. */
408	uint64_t cr2;
409	struct
410	{
411	uint32_t cValidEntries;
412	uint32_t uAlignment;
413	uint32_t aField[VMCSCACHE_MAX_ENTRY];
414	uint64_t aFieldVal[VMCSCACHE_MAX_ENTRY];
415	} Write;
416	struct
417	{
418	uint32_t cValidEntries;
419	uint32_t uAlignment;
420	uint32_t aField[VMCSCACHE_MAX_ENTRY];
421	uint64_t aFieldVal[VMCSCACHE_MAX_ENTRY];
422	} Read;
423	#ifdef DEBUG
424	struct
425	{
426	RTHCPHYS pPageCpuPhys;
427	RTHCPHYS pVMCSPhys;
428	RTGCPTR pCache;
429	RTGCPTR pCtx;
430	} TestIn;
431	struct
432	{
433	RTHCPHYS pVMCSPhys;
434	RTGCPTR pCache;
435	RTGCPTR pCtx;
436	uint64_t eflags;
437	uint64_t cr8;
438	} TestOut;
439	struct
440	{
441	uint64_t param1;
442	uint64_t param2;
443	uint64_t param3;
444	uint64_t param4;
445	} ScratchPad;
446	#endif
447	} VMCSCACHE;
448	/** Pointer to VMCSCACHE. */
449	typedef VMCSCACHE *PVMCSCACHE;
450
451	/**
452	* HWACCM VMCPU Instance data.
453	*/
454	typedef struct HWACCMCPU
455	{
456	/** Old style FPU reporting trap mask override performed (optimization) */
457	bool fFPUOldStyleOverride;
458
459	/** Set if we don't have to flush the TLB on VM entry. */
460	bool fResumeVM;
461
462	/** Set if we need to flush the TLB during the world switch. */
463	bool fForceTLBFlush;
464
465	/** Explicit alignment padding to make 32-bit gcc align u64RegisterMask
466	* naturally. */
467	bool padding[1];
468
469	/** HWACCM_CHANGED_* flags. */
470	RTUINT fContextUseFlags;
471
472	/* Id of the last cpu we were executing code on (NIL_RTCPUID for the first time) */
473	RTCPUID idLastCpu;
474
475	/* TLB flush count */
476	RTUINT cTLBFlushes;
477
478	/* Current ASID in use by the VM */
479	RTUINT uCurrentASID;
480
481	/** To keep track of pending TLB shootdown pages. (SMP guest only) */
482	RTGCPTR aTlbShootdownPages[HWACCM_MAX_TLB_SHOOTDOWN_PAGES];
483	RTUINT cTlbShootdownPages;
484
485	struct
486	{
487	/** R0 memory object for the VM control structure (VMCS). */
488	RTR0MEMOBJ pMemObjVMCS;
489	/** Physical address of the VM control structure (VMCS). */
490	RTHCPHYS pVMCSPhys;
491	/** Virtual address of the VM control structure (VMCS). */
492	R0PTRTYPE(void *) pVMCS;
493
494	/** Ring 0 handlers for VT-x. */
495	DECLR0CALLBACKMEMBER(int, pfnStartVM,(RTHCUINT fResume, PCPUMCTX pCtx, PVMCSCACHE pCache, PVM pVM, PVMCPU pVCpu));
496
497	/** Current VMX_VMCS_CTRL_PROC_EXEC_CONTROLS. */
498	uint64_t proc_ctls;
499
500	/** Current CR0 mask. */
501	uint64_t cr0_mask;
502	/** Current CR4 mask. */
503	uint64_t cr4_mask;
504
505	/** Current EPTP. */
506	RTHCPHYS GCPhysEPTP;
507
508	/** VMCS cache. */
509	VMCSCACHE VMCSCache;
510
511	/** Real-mode emulation state. */
512	struct
513	{
514	X86EFLAGS eflags;
515	uint32_t fValid;
516	} RealMode;
517
518	struct
519	{
520	uint64_t u64VMCSPhys;
521	uint32_t ulVMCSRevision;
522	uint32_t ulInstrError;
523	uint32_t ulExitReason;
524	RTCPUID idEnteredCpu;
525	RTCPUID idCurrentCpu;
526	uint32_t padding;
527	} lasterror;
528
529	/** The last seen guest paging mode (by VT-x). */
530	PGMMODE enmLastSeenGuestMode;
531	/** Current guest paging mode (as seen by HWACCMR3PagingModeChanged). */
532	PGMMODE enmCurrGuestMode;
533	/** Previous guest paging mode (as seen by HWACCMR3PagingModeChanged). */
534	PGMMODE enmPrevGuestMode;
535	} vmx;
536
537	struct
538	{
539	/** R0 memory object for the VM control block (VMCB). */
540	RTR0MEMOBJ pMemObjVMCB;
541	/** Physical address of the VM control block (VMCB). */
542	RTHCPHYS pVMCBPhys;
543	/** Virtual address of the VM control block (VMCB). */
544	R0PTRTYPE(void *) pVMCB;
545
546	/** Ring 0 handlers for VT-x. */
547	DECLR0CALLBACKMEMBER(int, pfnVMRun,(RTHCPHYS pVMCBHostPhys, RTHCPHYS pVMCBPhys, PCPUMCTX pCtx, PVM pVM, PVMCPU pVCpu));
548
549	} svm;
550
551	/** Event injection state. */
552	struct
553	{
554	uint32_t fPending;
555	uint32_t errCode;
556	uint64_t intInfo;
557	} Event;
558
559	/** IO Block emulation state. */
560	struct
561	{
562	bool fEnabled;
563	uint8_t u8Align[7];
564
565	/** RIP at the start of the io code we wish to emulate in the recompiler. */
566	RTGCPTR GCPtrFunctionEip;
567
568	uint64_t cr0;
569	} EmulateIoBlock;
570
571	/** Currenty shadow paging mode. */
572	PGMMODE enmShadowMode;
573
574	/** The CPU ID of the CPU currently owning the VMCS. Set in
575	* HWACCMR0Enter and cleared in HWACCMR0Leave. */
576	RTCPUID idEnteredCpu;
577	RTUINT padding2[1];
578
579	STAMPROFILEADV StatEntry;
580	STAMPROFILEADV StatExit1;
581	STAMPROFILEADV StatExit2;
582	#if 1 /* temporary for tracking down darwin issues. */
583	STAMPROFILEADV StatExit2Sub1;
584	STAMPROFILEADV StatExit2Sub2;
585	STAMPROFILEADV StatExit2Sub3;
586	#endif
587	STAMPROFILEADV StatInGC;
588
589	#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
590	STAMPROFILEADV StatWorldSwitch3264;
591	#endif
592
593	STAMCOUNTER StatIntInject;
594
595	STAMCOUNTER StatExitShadowNM;
596	STAMCOUNTER StatExitGuestNM;
597	STAMCOUNTER StatExitShadowPF;
598	STAMCOUNTER StatExitGuestPF;
599	STAMCOUNTER StatExitGuestUD;
600	STAMCOUNTER StatExitGuestSS;
601	STAMCOUNTER StatExitGuestNP;
602	STAMCOUNTER StatExitGuestGP;
603	STAMCOUNTER StatExitGuestDE;
604	STAMCOUNTER StatExitGuestDB;
605	STAMCOUNTER StatExitGuestMF;
606	STAMCOUNTER StatExitInvpg;
607	STAMCOUNTER StatExitInvd;
608	STAMCOUNTER StatExitCpuid;
609	STAMCOUNTER StatExitRdtsc;
610	STAMCOUNTER StatExitRdpmc;
611	STAMCOUNTER StatExitCli;
612	STAMCOUNTER StatExitSti;
613	STAMCOUNTER StatExitPushf;
614	STAMCOUNTER StatExitPopf;
615	STAMCOUNTER StatExitIret;
616	STAMCOUNTER StatExitInt;
617	STAMCOUNTER StatExitCRxWrite[16];
618	STAMCOUNTER StatExitCRxRead[16];
619	STAMCOUNTER StatExitDRxWrite;
620	STAMCOUNTER StatExitDRxRead;
621	STAMCOUNTER StatExitCLTS;
622	STAMCOUNTER StatExitHlt;
623	STAMCOUNTER StatExitLMSW;
624	STAMCOUNTER StatExitIOWrite;
625	STAMCOUNTER StatExitIORead;
626	STAMCOUNTER StatExitIOStringWrite;
627	STAMCOUNTER StatExitIOStringRead;
628	STAMCOUNTER StatExitIrqWindow;
629	STAMCOUNTER StatExitMaxResume;
630	STAMCOUNTER StatIntReinject;
631	STAMCOUNTER StatPendingHostIrq;
632
633	STAMCOUNTER StatFlushPageManual;
634	STAMCOUNTER StatFlushPhysPageManual;
635	STAMCOUNTER StatFlushTLBManual;
636	STAMCOUNTER StatFlushPageInvlpg;
637	STAMCOUNTER StatFlushTLBWorldSwitch;
638	STAMCOUNTER StatNoFlushTLBWorldSwitch;
639	STAMCOUNTER StatFlushTLBCRxChange;
640	STAMCOUNTER StatFlushASID;
641	STAMCOUNTER StatFlushTLBInvlpga;
642	STAMCOUNTER StatTlbShootdown;
643
644	STAMCOUNTER StatSwitchGuestIrq;
645	STAMCOUNTER StatSwitchToR3;
646
647	STAMCOUNTER StatTSCOffset;
648	STAMCOUNTER StatTSCIntercept;
649
650	STAMCOUNTER StatExitReasonNPF;
651	STAMCOUNTER StatDRxArmed;
652	STAMCOUNTER StatDRxContextSwitch;
653	STAMCOUNTER StatDRxIOCheck;
654
655
656	R3PTRTYPE(PSTAMCOUNTER) paStatExitReason;
657	R0PTRTYPE(PSTAMCOUNTER) paStatExitReasonR0;
658	} HWACCMCPU;
659	/** Pointer to HWACCM VM instance data. */
660	typedef HWACCMCPU *PHWACCMCPU;
661
662
663	#ifdef IN_RING0
664
665	VMMR0DECL(PHWACCM_CPUINFO) HWACCMR0GetCurrentCpu();
666	VMMR0DECL(PHWACCM_CPUINFO) HWACCMR0GetCurrentCpuEx(RTCPUID idCpu);
667
668
669	#ifdef VBOX_STRICT
670	VMMR0DECL(void) HWACCMDumpRegs(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
671	VMMR0DECL(void) HWACCMR0DumpDescriptor(PX86DESCHC Desc, RTSEL Sel, const char *pszMsg);
672	#else
673	#define HWACCMDumpRegs(a, b ,c) do { } while (0)
674	#define HWACCMR0DumpDescriptor(a, b, c) do { } while (0)
675	#endif
676
677	/* Dummy callback handlers. */
678	VMMR0DECL(int) HWACCMR0DummyEnter(PVM pVM, PVMCPU pVCpu, PHWACCM_CPUINFO pCpu);
679	VMMR0DECL(int) HWACCMR0DummyLeave(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
680	VMMR0DECL(int) HWACCMR0DummyEnableCpu(PHWACCM_CPUINFO pCpu, PVM pVM, void *pvPageCpu, RTHCPHYS pPageCpuPhys);
681	VMMR0DECL(int) HWACCMR0DummyDisableCpu(PHWACCM_CPUINFO pCpu, void *pvPageCpu, RTHCPHYS pPageCpuPhys);
682	VMMR0DECL(int) HWACCMR0DummyInitVM(PVM pVM);
683	VMMR0DECL(int) HWACCMR0DummyTermVM(PVM pVM);
684	VMMR0DECL(int) HWACCMR0DummySetupVM(PVM pVM);
685	VMMR0DECL(int) HWACCMR0DummyRunGuestCode(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
686	VMMR0DECL(int) HWACCMR0DummySaveHostState(PVM pVM, PVMCPU pVCpu);
687	VMMR0DECL(int) HWACCMR0DummyLoadGuestState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
688
689
690	# ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
691	/**
692	* Gets 64-bit GDTR and IDTR on darwin.
693	* @param pGdtr Where to store the 64-bit GDTR.
694	* @param pIdtr Where to store the 64-bit IDTR.
695	*/
696	DECLASM(void) hwaccmR0Get64bitGDTRandIDTR(PX86XDTR64 pGdtr, PX86XDTR64 pIdtr);
697
698	/**
699	* Gets 64-bit CR3 on darwin.
700	* @returns CR3
701	*/
702	DECLASM(uint64_t) hwaccmR0Get64bitCR3(void);
703	# endif
704
705	#endif /* IN_RING0 */
706
707	/** @} */
708
709	__END_DECLS
710
711	#endif
712

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source: vbox/trunk/src/VBox/VMM/HWACCMInternal.h@ 19335

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