VirtualBox

source: vbox/trunk/src/VBox/VMM/HWACCMInternal.h@ 20376

Last change on this file since 20376 was 20374, checked in by vboxsync, 15 years ago

*: s/RT_\(BEGIN|END\)_DECLS/RT_C_DECLS_\1/g
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1/* $Id: HWACCMInternal.h 20374 2009-06-08 00:43:21Z vboxsync $ */
2/** @file
3 * HWACCM - Internal header file.
4 */
5
6/*
7 * Copyright (C) 2006-2007 Sun Microsystems, Inc.
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 *
17 * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18 * Clara, CA 95054 USA or visit http://www.sun.com if you need
19 * additional information or have any questions.
20 */
21
22#ifndef ___HWACCMInternal_h
23#define ___HWACCMInternal_h
24
25#include <VBox/cdefs.h>
26#include <VBox/types.h>
27#include <VBox/em.h>
28#include <VBox/stam.h>
29#include <VBox/dis.h>
30#include <VBox/hwaccm.h>
31#include <VBox/pgm.h>
32#include <VBox/cpum.h>
33#include <iprt/memobj.h>
34#include <iprt/cpuset.h>
35#include <iprt/mp.h>
36
37#if HC_ARCH_BITS == 64 || defined(VBOX_WITH_HYBRID_32BIT_KERNEL) || defined (VBOX_WITH_64_BITS_GUESTS)
38/* Enable 64 bits guest support. */
39# define VBOX_ENABLE_64_BITS_GUESTS
40#endif
41
42#define VMX_USE_CACHED_VMCS_ACCESSES
43#define HWACCM_VMX_EMULATE_REALMODE
44#define HWACCM_VTX_WITH_EPT
45#define HWACCM_VTX_WITH_VPID
46
47RT_C_DECLS_BEGIN
48
49
50/** @defgroup grp_hwaccm_int Internal
51 * @ingroup grp_hwaccm
52 * @internal
53 * @{
54 */
55
56
57/** Maximum number of exit reason statistics counters. */
58#define MAX_EXITREASON_STAT 0x100
59#define MASK_EXITREASON_STAT 0xff
60#define MASK_INJECT_IRQ_STAT 0xff
61
62/** @name Changed flags
63 * These flags are used to keep track of which important registers that
64 * have been changed since last they were reset.
65 * @{
66 */
67#define HWACCM_CHANGED_GUEST_FPU RT_BIT(0)
68#define HWACCM_CHANGED_GUEST_CR0 RT_BIT(1)
69#define HWACCM_CHANGED_GUEST_CR3 RT_BIT(2)
70#define HWACCM_CHANGED_GUEST_CR4 RT_BIT(3)
71#define HWACCM_CHANGED_GUEST_GDTR RT_BIT(4)
72#define HWACCM_CHANGED_GUEST_IDTR RT_BIT(5)
73#define HWACCM_CHANGED_GUEST_LDTR RT_BIT(6)
74#define HWACCM_CHANGED_GUEST_TR RT_BIT(7)
75#define HWACCM_CHANGED_GUEST_SYSENTER_MSR RT_BIT(8)
76#define HWACCM_CHANGED_GUEST_SEGMENT_REGS RT_BIT(9)
77#define HWACCM_CHANGED_GUEST_DEBUG RT_BIT(10)
78#define HWACCM_CHANGED_HOST_CONTEXT RT_BIT(11)
79
80#define HWACCM_CHANGED_ALL ( HWACCM_CHANGED_GUEST_SEGMENT_REGS \
81 | HWACCM_CHANGED_GUEST_CR0 \
82 | HWACCM_CHANGED_GUEST_CR3 \
83 | HWACCM_CHANGED_GUEST_CR4 \
84 | HWACCM_CHANGED_GUEST_GDTR \
85 | HWACCM_CHANGED_GUEST_IDTR \
86 | HWACCM_CHANGED_GUEST_LDTR \
87 | HWACCM_CHANGED_GUEST_TR \
88 | HWACCM_CHANGED_GUEST_SYSENTER_MSR \
89 | HWACCM_CHANGED_GUEST_FPU \
90 | HWACCM_CHANGED_GUEST_DEBUG \
91 | HWACCM_CHANGED_HOST_CONTEXT)
92
93#define HWACCM_CHANGED_ALL_GUEST ( HWACCM_CHANGED_GUEST_SEGMENT_REGS \
94 | HWACCM_CHANGED_GUEST_CR0 \
95 | HWACCM_CHANGED_GUEST_CR3 \
96 | HWACCM_CHANGED_GUEST_CR4 \
97 | HWACCM_CHANGED_GUEST_GDTR \
98 | HWACCM_CHANGED_GUEST_IDTR \
99 | HWACCM_CHANGED_GUEST_LDTR \
100 | HWACCM_CHANGED_GUEST_TR \
101 | HWACCM_CHANGED_GUEST_SYSENTER_MSR \
102 | HWACCM_CHANGED_GUEST_DEBUG \
103 | HWACCM_CHANGED_GUEST_FPU)
104
105/** @} */
106
107/** @name Intercepted traps
108 * Traps that need to be intercepted so we can correctly dispatch them to the guest if required.
109 * Currently #NM and #PF only
110 */
111#ifdef VBOX_STRICT
112#define HWACCM_VMX_TRAP_MASK RT_BIT(X86_XCPT_DE) | RT_BIT(X86_XCPT_NM) | RT_BIT(X86_XCPT_PF) | RT_BIT(X86_XCPT_UD) | RT_BIT(X86_XCPT_NP) | RT_BIT(X86_XCPT_SS) | RT_BIT(X86_XCPT_GP) | RT_BIT(X86_XCPT_MF)
113#define HWACCM_SVM_TRAP_MASK HWACCM_VMX_TRAP_MASK
114#else
115#define HWACCM_VMX_TRAP_MASK RT_BIT(X86_XCPT_NM) | RT_BIT(X86_XCPT_PF)
116#define HWACCM_SVM_TRAP_MASK RT_BIT(X86_XCPT_NM) | RT_BIT(X86_XCPT_PF)
117#endif
118/* All exceptions have to be intercept in emulated real-mode (minues NM & PF as they are always intercepted. */
119#define HWACCM_VMX_TRAP_MASK_REALMODE RT_BIT(X86_XCPT_DE) | RT_BIT(X86_XCPT_DB) | RT_BIT(X86_XCPT_NMI) | RT_BIT(X86_XCPT_BP) | RT_BIT(X86_XCPT_OF) | RT_BIT(X86_XCPT_BR) | RT_BIT(X86_XCPT_UD) | RT_BIT(X86_XCPT_DF) | RT_BIT(X86_XCPT_CO_SEG_OVERRUN) | RT_BIT(X86_XCPT_TS) | RT_BIT(X86_XCPT_NP) | RT_BIT(X86_XCPT_SS) | RT_BIT(X86_XCPT_GP) | RT_BIT(X86_XCPT_MF) | RT_BIT(X86_XCPT_AC) | RT_BIT(X86_XCPT_MC) | RT_BIT(X86_XCPT_XF)
120/** @} */
121
122
123/** Maximum number of page flushes we are willing to remember before considering a full TLB flush. */
124#define HWACCM_MAX_TLB_SHOOTDOWN_PAGES 8
125
126/** Size for the EPT identity page table (1024 4 MB pages to cover the entire address space). */
127#define HWACCM_EPT_IDENTITY_PG_TABLE_SIZE PAGE_SIZE
128/** Size of the TSS structure + 2 pages for the IO bitmap + end byte. */
129#define HWACCM_VTX_TSS_SIZE (sizeof(VBOXTSS) + 2*PAGE_SIZE + 1)
130/** Total guest mapped memory needed. */
131#define HWACCM_VTX_TOTAL_DEVHEAP_MEM (HWACCM_EPT_IDENTITY_PG_TABLE_SIZE + HWACCM_VTX_TSS_SIZE)
132
133/** HWACCM SSM version
134 */
135#define HWACCM_SSM_VERSION 4
136#define HWACCM_SSM_VERSION_2_0_X 3
137
138/* Per-cpu information. (host) */
139typedef struct
140{
141 RTCPUID idCpu;
142
143 RTR0MEMOBJ pMemObj;
144 /* Current ASID (AMD-V)/VPID (Intel) */
145 uint32_t uCurrentASID;
146 /* TLB flush count */
147 uint32_t cTLBFlushes;
148
149 /* Set the first time a cpu is used to make sure we start with a clean TLB. */
150 bool fFlushTLB;
151
152 /** Configured for VT-x or AMD-V. */
153 bool fConfigured;
154
155 /** In use by our code. (for power suspend) */
156 volatile bool fInUse;
157} HWACCM_CPUINFO;
158typedef HWACCM_CPUINFO *PHWACCM_CPUINFO;
159
160/* VT-x capability qword. */
161typedef union
162{
163 struct
164 {
165 uint32_t disallowed0;
166 uint32_t allowed1;
167 } n;
168 uint64_t u;
169} VMX_CAPABILITY;
170
171/**
172 * Switcher function, HC to RC.
173 *
174 * @param pVM The VM handle.
175 * @returns Return code indicating the action to take.
176 */
177typedef DECLASMTYPE(int) FNHWACCMSWITCHERHC(PVM pVM);
178/** Pointer to switcher function. */
179typedef FNHWACCMSWITCHERHC *PFNHWACCMSWITCHERHC;
180
181/**
182 * HWACCM VM Instance data.
183 * Changes to this must checked against the padding of the cfgm union in VM!
184 */
185typedef struct HWACCM
186{
187 /** Set when we've initialized VMX or SVM. */
188 bool fInitialized;
189
190 /** Set when hardware acceleration is allowed. */
191 bool fAllowed;
192
193 /** Set if nested paging is enabled. */
194 bool fNestedPaging;
195
196 /** Set if nested paging is allowed. */
197 bool fAllowNestedPaging;
198
199 /** Set if we're supposed to inject an NMI. */
200 bool fInjectNMI;
201
202 /** Set if we can support 64-bit guests or not. */
203 bool fAllow64BitGuests;
204
205 /** Set if an IO-APIC is configured for this VM. */
206 bool fHasIoApic;
207
208 /** Explicit alignment padding to make 32-bit gcc align u64RegisterMask
209 * naturally. */
210 bool padding[1];
211
212 /** And mask for copying register contents. */
213 uint64_t u64RegisterMask;
214
215 /** Maximum ASID allowed. */
216 RTUINT uMaxASID;
217
218 /** The maximum number of resumes loops allowed in ring-0 (safety precaution).
219 * This number is set much higher when RTThreadPreemptIsPending is reliable. */
220 uint32_t cMaxResumeLoops;
221
222#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
223 /** 32 to 64 bits switcher entrypoint. */
224 R0PTRTYPE(PFNHWACCMSWITCHERHC) pfnHost32ToGuest64R0;
225
226 /* AMD-V 64 bits vmrun handler */
227 RTRCPTR pfnSVMGCVMRun64;
228
229 /* VT-x 64 bits vmlaunch handler */
230 RTRCPTR pfnVMXGCStartVM64;
231
232 /* RC handler to setup the 64 bits FPU state. */
233 RTRCPTR pfnSaveGuestFPU64;
234
235 /* RC handler to setup the 64 bits debug state. */
236 RTRCPTR pfnSaveGuestDebug64;
237
238 /* Test handler */
239 RTRCPTR pfnTest64;
240
241 RTRCPTR uAlignment[2];
242/*#elif defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
243 uint32_t u32Alignment[1]; */
244#endif
245
246 struct
247 {
248 /** Set by the ring-0 driver to indicate VMX is supported by the CPU. */
249 bool fSupported;
250
251 /** Set when we've enabled VMX. */
252 bool fEnabled;
253
254 /** Set if VPID is supported. */
255 bool fVPID;
256
257 /** Set if VT-x VPID is allowed. */
258 bool fAllowVPID;
259
260 /** Virtual address of the TSS page used for real mode emulation. */
261 R3PTRTYPE(PVBOXTSS) pRealModeTSS;
262
263 /** Virtual address of the identity page table used for real mode and protected mode without paging emulation in EPT mode. */
264 R3PTRTYPE(PX86PD) pNonPagingModeEPTPageTable;
265
266 /** R0 memory object for the APIC physical page (serves for filtering accesses). */
267 RTR0MEMOBJ pMemObjAPIC;
268 /** Physical address of the APIC physical page (serves for filtering accesses). */
269 RTHCPHYS pAPICPhys;
270 /** Virtual address of the APIC physical page (serves for filtering accesses). */
271 R0PTRTYPE(uint8_t *) pAPIC;
272
273 /** R0 memory object for the MSR bitmap (1 page). */
274 RTR0MEMOBJ pMemObjMSRBitmap;
275 /** Physical address of the MSR bitmap (1 page). */
276 RTHCPHYS pMSRBitmapPhys;
277 /** Virtual address of the MSR bitmap (1 page). */
278 R0PTRTYPE(uint8_t *) pMSRBitmap;
279
280 /** R0 memory object for the MSR entry load page (guest MSRs). */
281 RTR0MEMOBJ pMemObjMSREntryLoad;
282 /** Physical address of the MSR entry load page (guest MSRs). */
283 RTHCPHYS pMSREntryLoadPhys;
284 /** Virtual address of the MSR entry load page (guest MSRs). */
285 R0PTRTYPE(uint8_t *) pMSREntryLoad;
286
287#ifdef VBOX_WITH_CRASHDUMP_MAGIC
288 RTR0MEMOBJ pMemObjScratch;
289 RTHCPHYS pScratchPhys;
290 R0PTRTYPE(uint8_t *) pScratch;
291#endif
292 /** R0 memory object for the MSR exit store page (guest MSRs). */
293 RTR0MEMOBJ pMemObjMSRExitStore;
294 /** Physical address of the MSR exit store page (guest MSRs). */
295 RTHCPHYS pMSRExitStorePhys;
296 /** Virtual address of the MSR exit store page (guest MSRs). */
297 R0PTRTYPE(uint8_t *) pMSRExitStore;
298
299 /** R0 memory object for the MSR exit load page (host MSRs). */
300 RTR0MEMOBJ pMemObjMSRExitLoad;
301 /** Physical address of the MSR exit load page (host MSRs). */
302 RTHCPHYS pMSRExitLoadPhys;
303 /** Virtual address of the MSR exit load page (host MSRs). */
304 R0PTRTYPE(uint8_t *) pMSRExitLoad;
305
306 /** Ring 0 handlers for VT-x. */
307 DECLR0CALLBACKMEMBER(void, pfnSetupTaggedTLB, (PVM pVM, PVMCPU pVCpu));
308
309 /** Host CR4 value (set by ring-0 VMX init) */
310 uint64_t hostCR4;
311
312 /** VMX MSR values */
313 struct
314 {
315 uint64_t feature_ctrl;
316 uint64_t vmx_basic_info;
317 VMX_CAPABILITY vmx_pin_ctls;
318 VMX_CAPABILITY vmx_proc_ctls;
319 VMX_CAPABILITY vmx_proc_ctls2;
320 VMX_CAPABILITY vmx_exit;
321 VMX_CAPABILITY vmx_entry;
322 uint64_t vmx_misc;
323 uint64_t vmx_cr0_fixed0;
324 uint64_t vmx_cr0_fixed1;
325 uint64_t vmx_cr4_fixed0;
326 uint64_t vmx_cr4_fixed1;
327 uint64_t vmx_vmcs_enum;
328 uint64_t vmx_eptcaps;
329 } msr;
330
331 /** Flush types for invept & invvpid; they depend on capabilities. */
332 VMX_FLUSH enmFlushPage;
333 VMX_FLUSH enmFlushContext;
334 } vmx;
335
336 struct
337 {
338 /** Set by the ring-0 driver to indicate SVM is supported by the CPU. */
339 bool fSupported;
340 /** Set when we've enabled SVM. */
341 bool fEnabled;
342 /** Set if erratum 170 affects the AMD cpu. */
343 bool fAlwaysFlushTLB;
344 /** Explicit alignment padding to make 32-bit gcc align u64RegisterMask
345 * naturally. */
346 bool padding[1];
347
348 /** R0 memory object for the IO bitmap (12kb). */
349 RTR0MEMOBJ pMemObjIOBitmap;
350 /** Physical address of the IO bitmap (12kb). */
351 RTHCPHYS pIOBitmapPhys;
352 /** Virtual address of the IO bitmap. */
353 R0PTRTYPE(void *) pIOBitmap;
354
355 /** R0 memory object for the MSR bitmap (8kb). */
356 RTR0MEMOBJ pMemObjMSRBitmap;
357 /** Physical address of the MSR bitmap (8kb). */
358 RTHCPHYS pMSRBitmapPhys;
359 /** Virtual address of the MSR bitmap. */
360 R0PTRTYPE(void *) pMSRBitmap;
361
362 /** SVM revision. */
363 uint32_t u32Rev;
364
365 /** SVM feature bits from cpuid 0x8000000a */
366 uint32_t u32Features;
367 } svm;
368
369 struct
370 {
371 uint32_t u32AMDFeatureECX;
372 uint32_t u32AMDFeatureEDX;
373 } cpuid;
374
375 /** Saved error from detection */
376 int32_t lLastError;
377
378 /** HWACCMR0Init was run */
379 bool fHWACCMR0Init;
380} HWACCM;
381/** Pointer to HWACCM VM instance data. */
382typedef HWACCM *PHWACCM;
383
384/* Maximum number of cached entries. */
385#define VMCSCACHE_MAX_ENTRY 128
386
387/* Structure for storing read and write VMCS actions. */
388typedef struct VMCSCACHE
389{
390#ifdef VBOX_WITH_CRASHDUMP_MAGIC
391 /* Magic marker for searching in crash dumps. */
392 uint8_t aMagic[16];
393 uint64_t uMagic;
394 uint64_t u64TimeEntry;
395 uint64_t u64TimeSwitch;
396 uint64_t cResume;
397 uint64_t interPD;
398 uint64_t pSwitcher;
399 uint32_t uPos;
400 uint32_t idCpu;
401#endif
402 /* CR2 is saved here for EPT syncing. */
403 uint64_t cr2;
404 struct
405 {
406 uint32_t cValidEntries;
407 uint32_t uAlignment;
408 uint32_t aField[VMCSCACHE_MAX_ENTRY];
409 uint64_t aFieldVal[VMCSCACHE_MAX_ENTRY];
410 } Write;
411 struct
412 {
413 uint32_t cValidEntries;
414 uint32_t uAlignment;
415 uint32_t aField[VMCSCACHE_MAX_ENTRY];
416 uint64_t aFieldVal[VMCSCACHE_MAX_ENTRY];
417 } Read;
418#ifdef DEBUG
419 struct
420 {
421 RTHCPHYS pPageCpuPhys;
422 RTHCPHYS pVMCSPhys;
423 RTGCPTR pCache;
424 RTGCPTR pCtx;
425 } TestIn;
426 struct
427 {
428 RTHCPHYS pVMCSPhys;
429 RTGCPTR pCache;
430 RTGCPTR pCtx;
431 uint64_t eflags;
432 uint64_t cr8;
433 } TestOut;
434 struct
435 {
436 uint64_t param1;
437 uint64_t param2;
438 uint64_t param3;
439 uint64_t param4;
440 } ScratchPad;
441#endif
442} VMCSCACHE;
443/** Pointer to VMCSCACHE. */
444typedef VMCSCACHE *PVMCSCACHE;
445
446/**
447 * HWACCM VMCPU Instance data.
448 */
449typedef struct HWACCMCPU
450{
451 /** Old style FPU reporting trap mask override performed (optimization) */
452 bool fFPUOldStyleOverride;
453
454 /** Set if we don't have to flush the TLB on VM entry. */
455 bool fResumeVM;
456
457 /** Set if we need to flush the TLB during the world switch. */
458 bool fForceTLBFlush;
459
460 /** Set when we're using VT-x or AMD-V at that moment. */
461 bool fActive;
462
463 /** HWACCM_CHANGED_* flags. */
464 RTUINT fContextUseFlags;
465
466 /* Id of the last cpu we were executing code on (NIL_RTCPUID for the first time) */
467 RTCPUID idLastCpu;
468
469 /* TLB flush count */
470 RTUINT cTLBFlushes;
471
472 /* Current ASID in use by the VM */
473 RTUINT uCurrentASID;
474
475 struct
476 {
477 /** R0 memory object for the VM control structure (VMCS). */
478 RTR0MEMOBJ pMemObjVMCS;
479 /** Physical address of the VM control structure (VMCS). */
480 RTHCPHYS pVMCSPhys;
481 /** Virtual address of the VM control structure (VMCS). */
482 R0PTRTYPE(void *) pVMCS;
483
484 /** Ring 0 handlers for VT-x. */
485 DECLR0CALLBACKMEMBER(int, pfnStartVM,(RTHCUINT fResume, PCPUMCTX pCtx, PVMCSCACHE pCache, PVM pVM, PVMCPU pVCpu));
486
487 /** Current VMX_VMCS_CTRL_PROC_EXEC_CONTROLS. */
488 uint64_t proc_ctls;
489
490 /** Current VMX_VMCS_CTRL_PROC_EXEC2_CONTROLS. */
491 uint64_t proc_ctls2;
492
493 /** R0 memory object for the virtual APIC page for TPR caching. */
494 RTR0MEMOBJ pMemObjVAPIC;
495 /** Physical address of the virtual APIC page for TPR caching. */
496 RTHCPHYS pVAPICPhys;
497 /** Virtual address of the virtual APIC page for TPR caching. */
498 R0PTRTYPE(uint8_t *) pVAPIC;
499
500 /** Current CR0 mask. */
501 uint64_t cr0_mask;
502 /** Current CR4 mask. */
503 uint64_t cr4_mask;
504
505 /** Current EPTP. */
506 RTHCPHYS GCPhysEPTP;
507
508 /** VMCS cache. */
509 VMCSCACHE VMCSCache;
510
511 /** Real-mode emulation state. */
512 struct
513 {
514 X86EFLAGS eflags;
515 uint32_t fValid;
516 } RealMode;
517
518 struct
519 {
520 uint64_t u64VMCSPhys;
521 uint32_t ulVMCSRevision;
522 uint32_t ulInstrError;
523 uint32_t ulExitReason;
524 RTCPUID idEnteredCpu;
525 RTCPUID idCurrentCpu;
526 uint32_t padding;
527 } lasterror;
528
529 /** The last seen guest paging mode (by VT-x). */
530 PGMMODE enmLastSeenGuestMode;
531 /** Current guest paging mode (as seen by HWACCMR3PagingModeChanged). */
532 PGMMODE enmCurrGuestMode;
533 /** Previous guest paging mode (as seen by HWACCMR3PagingModeChanged). */
534 PGMMODE enmPrevGuestMode;
535 } vmx;
536
537 struct
538 {
539 /** R0 memory object for the host VM control block (VMCB). */
540 RTR0MEMOBJ pMemObjVMCBHost;
541 /** Physical address of the host VM control block (VMCB). */
542 RTHCPHYS pVMCBHostPhys;
543 /** Virtual address of the host VM control block (VMCB). */
544 R0PTRTYPE(void *) pVMCBHost;
545
546 /** R0 memory object for the VM control block (VMCB). */
547 RTR0MEMOBJ pMemObjVMCB;
548 /** Physical address of the VM control block (VMCB). */
549 RTHCPHYS pVMCBPhys;
550 /** Virtual address of the VM control block (VMCB). */
551 R0PTRTYPE(void *) pVMCB;
552
553 /** Ring 0 handlers for VT-x. */
554 DECLR0CALLBACKMEMBER(int, pfnVMRun,(RTHCPHYS pVMCBHostPhys, RTHCPHYS pVMCBPhys, PCPUMCTX pCtx, PVM pVM, PVMCPU pVCpu));
555
556 } svm;
557
558 /** Event injection state. */
559 struct
560 {
561 uint32_t fPending;
562 uint32_t errCode;
563 uint64_t intInfo;
564 } Event;
565
566 /** IO Block emulation state. */
567 struct
568 {
569 bool fEnabled;
570 uint8_t u8Align[7];
571
572 /** RIP at the start of the io code we wish to emulate in the recompiler. */
573 RTGCPTR GCPtrFunctionEip;
574
575 uint64_t cr0;
576 } EmulateIoBlock;
577
578 /** Currenty shadow paging mode. */
579 PGMMODE enmShadowMode;
580
581 /** The CPU ID of the CPU currently owning the VMCS. Set in
582 * HWACCMR0Enter and cleared in HWACCMR0Leave. */
583 RTCPUID idEnteredCpu;
584
585 /** To keep track of pending TLB shootdown pages. (SMP guest only) */
586 struct
587 {
588 RTGCPTR aPages[HWACCM_MAX_TLB_SHOOTDOWN_PAGES];
589 unsigned cPages;
590 } TlbShootdown;
591
592 RTUINT padding2[1];
593
594 STAMPROFILEADV StatEntry;
595 STAMPROFILEADV StatExit1;
596 STAMPROFILEADV StatExit2;
597#if 1 /* temporary for tracking down darwin issues. */
598 STAMPROFILEADV StatExit2Sub1;
599 STAMPROFILEADV StatExit2Sub2;
600 STAMPROFILEADV StatExit2Sub3;
601#endif
602 STAMPROFILEADV StatInGC;
603
604#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
605 STAMPROFILEADV StatWorldSwitch3264;
606#endif
607
608 STAMCOUNTER StatIntInject;
609
610 STAMCOUNTER StatExitShadowNM;
611 STAMCOUNTER StatExitGuestNM;
612 STAMCOUNTER StatExitShadowPF;
613 STAMCOUNTER StatExitGuestPF;
614 STAMCOUNTER StatExitGuestUD;
615 STAMCOUNTER StatExitGuestSS;
616 STAMCOUNTER StatExitGuestNP;
617 STAMCOUNTER StatExitGuestGP;
618 STAMCOUNTER StatExitGuestDE;
619 STAMCOUNTER StatExitGuestDB;
620 STAMCOUNTER StatExitGuestMF;
621 STAMCOUNTER StatExitInvpg;
622 STAMCOUNTER StatExitInvd;
623 STAMCOUNTER StatExitCpuid;
624 STAMCOUNTER StatExitRdtsc;
625 STAMCOUNTER StatExitRdpmc;
626 STAMCOUNTER StatExitCli;
627 STAMCOUNTER StatExitSti;
628 STAMCOUNTER StatExitPushf;
629 STAMCOUNTER StatExitPopf;
630 STAMCOUNTER StatExitIret;
631 STAMCOUNTER StatExitInt;
632 STAMCOUNTER StatExitCRxWrite[16];
633 STAMCOUNTER StatExitCRxRead[16];
634 STAMCOUNTER StatExitDRxWrite;
635 STAMCOUNTER StatExitDRxRead;
636 STAMCOUNTER StatExitRdmsr;
637 STAMCOUNTER StatExitWrmsr;
638 STAMCOUNTER StatExitCLTS;
639 STAMCOUNTER StatExitHlt;
640 STAMCOUNTER StatExitMwait;
641 STAMCOUNTER StatExitLMSW;
642 STAMCOUNTER StatExitIOWrite;
643 STAMCOUNTER StatExitIORead;
644 STAMCOUNTER StatExitIOStringWrite;
645 STAMCOUNTER StatExitIOStringRead;
646 STAMCOUNTER StatExitIrqWindow;
647 STAMCOUNTER StatExitMaxResume;
648 STAMCOUNTER StatExitPreemptPending;
649 STAMCOUNTER StatIntReinject;
650 STAMCOUNTER StatPendingHostIrq;
651
652 STAMCOUNTER StatFlushPageManual;
653 STAMCOUNTER StatFlushPhysPageManual;
654 STAMCOUNTER StatFlushTLBManual;
655 STAMCOUNTER StatFlushPageInvlpg;
656 STAMCOUNTER StatFlushTLBWorldSwitch;
657 STAMCOUNTER StatNoFlushTLBWorldSwitch;
658 STAMCOUNTER StatFlushTLBCRxChange;
659 STAMCOUNTER StatFlushASID;
660 STAMCOUNTER StatFlushTLBInvlpga;
661 STAMCOUNTER StatTlbShootdown;
662 STAMCOUNTER StatTlbShootdownFlush;
663
664 STAMCOUNTER StatSwitchGuestIrq;
665 STAMCOUNTER StatSwitchToR3;
666
667 STAMCOUNTER StatTSCOffset;
668 STAMCOUNTER StatTSCIntercept;
669
670 STAMCOUNTER StatExitReasonNPF;
671 STAMCOUNTER StatDRxArmed;
672 STAMCOUNTER StatDRxContextSwitch;
673 STAMCOUNTER StatDRxIOCheck;
674
675
676#ifdef VBOX_WITH_STATISTICS
677 R3PTRTYPE(PSTAMCOUNTER) paStatExitReason;
678 R0PTRTYPE(PSTAMCOUNTER) paStatExitReasonR0;
679 R3PTRTYPE(PSTAMCOUNTER) paStatInjectedIrqs;
680 R0PTRTYPE(PSTAMCOUNTER) paStatInjectedIrqsR0;
681#endif
682} HWACCMCPU;
683/** Pointer to HWACCM VM instance data. */
684typedef HWACCMCPU *PHWACCMCPU;
685
686
687#ifdef IN_RING0
688
689VMMR0DECL(PHWACCM_CPUINFO) HWACCMR0GetCurrentCpu();
690VMMR0DECL(PHWACCM_CPUINFO) HWACCMR0GetCurrentCpuEx(RTCPUID idCpu);
691
692
693#ifdef VBOX_STRICT
694VMMR0DECL(void) HWACCMDumpRegs(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
695VMMR0DECL(void) HWACCMR0DumpDescriptor(PX86DESCHC Desc, RTSEL Sel, const char *pszMsg);
696#else
697#define HWACCMDumpRegs(a, b ,c) do { } while (0)
698#define HWACCMR0DumpDescriptor(a, b, c) do { } while (0)
699#endif
700
701/* Dummy callback handlers. */
702VMMR0DECL(int) HWACCMR0DummyEnter(PVM pVM, PVMCPU pVCpu, PHWACCM_CPUINFO pCpu);
703VMMR0DECL(int) HWACCMR0DummyLeave(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
704VMMR0DECL(int) HWACCMR0DummyEnableCpu(PHWACCM_CPUINFO pCpu, PVM pVM, void *pvPageCpu, RTHCPHYS pPageCpuPhys);
705VMMR0DECL(int) HWACCMR0DummyDisableCpu(PHWACCM_CPUINFO pCpu, void *pvPageCpu, RTHCPHYS pPageCpuPhys);
706VMMR0DECL(int) HWACCMR0DummyInitVM(PVM pVM);
707VMMR0DECL(int) HWACCMR0DummyTermVM(PVM pVM);
708VMMR0DECL(int) HWACCMR0DummySetupVM(PVM pVM);
709VMMR0DECL(int) HWACCMR0DummyRunGuestCode(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
710VMMR0DECL(int) HWACCMR0DummySaveHostState(PVM pVM, PVMCPU pVCpu);
711VMMR0DECL(int) HWACCMR0DummyLoadGuestState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
712
713
714# ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
715/**
716 * Gets 64-bit GDTR and IDTR on darwin.
717 * @param pGdtr Where to store the 64-bit GDTR.
718 * @param pIdtr Where to store the 64-bit IDTR.
719 */
720DECLASM(void) hwaccmR0Get64bitGDTRandIDTR(PX86XDTR64 pGdtr, PX86XDTR64 pIdtr);
721
722/**
723 * Gets 64-bit CR3 on darwin.
724 * @returns CR3
725 */
726DECLASM(uint64_t) hwaccmR0Get64bitCR3(void);
727# endif
728
729#endif /* IN_RING0 */
730
731/** @} */
732
733RT_C_DECLS_END
734
735#endif
736
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