HWACCMInternal.h@ 21209

Last change on this file since 21209 was 21209, checked in by vboxsync, 15 years ago
Updates for io instruction restarts
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1	/* $Id: HWACCMInternal.h 21209 2009-07-03 14:50:36Z vboxsync $ */
2	/** @file
3	* HWACCM - Internal header file.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22	#ifndef ___HWACCMInternal_h
23	#define ___HWACCMInternal_h
24
25	#include <VBox/cdefs.h>
26	#include <VBox/types.h>
27	#include <VBox/em.h>
28	#include <VBox/stam.h>
29	#include <VBox/dis.h>
30	#include <VBox/hwaccm.h>
31	#include <VBox/pgm.h>
32	#include <VBox/cpum.h>
33	#include <iprt/memobj.h>
34	#include <iprt/cpuset.h>
35	#include <iprt/mp.h>
36
37	#if HC_ARCH_BITS == 64 \|\| defined(VBOX_WITH_HYBRID_32BIT_KERNEL) \|\| defined (VBOX_WITH_64_BITS_GUESTS)
38	/* Enable 64 bits guest support. */
39	# define VBOX_ENABLE_64_BITS_GUESTS
40	#endif
41
42	#define VMX_USE_CACHED_VMCS_ACCESSES
43	#define HWACCM_VMX_EMULATE_REALMODE
44	#define HWACCM_VTX_WITH_EPT
45	#define HWACCM_VTX_WITH_VPID
46
47	RT_C_DECLS_BEGIN
48
49
50	/** @defgroup grp_hwaccm_int Internal
51	* @ingroup grp_hwaccm
52	* @internal
53	* @{
54	*/
55
56
57	/** Maximum number of exit reason statistics counters. */
58	#define MAX_EXITREASON_STAT 0x100
59	#define MASK_EXITREASON_STAT 0xff
60	#define MASK_INJECT_IRQ_STAT 0xff
61
62	/** @name Changed flags
63	* These flags are used to keep track of which important registers that
64	* have been changed since last they were reset.
65	* @{
66	*/
67	#define HWACCM_CHANGED_GUEST_FPU RT_BIT(0)
68	#define HWACCM_CHANGED_GUEST_CR0 RT_BIT(1)
69	#define HWACCM_CHANGED_GUEST_CR3 RT_BIT(2)
70	#define HWACCM_CHANGED_GUEST_CR4 RT_BIT(3)
71	#define HWACCM_CHANGED_GUEST_GDTR RT_BIT(4)
72	#define HWACCM_CHANGED_GUEST_IDTR RT_BIT(5)
73	#define HWACCM_CHANGED_GUEST_LDTR RT_BIT(6)
74	#define HWACCM_CHANGED_GUEST_TR RT_BIT(7)
75	#define HWACCM_CHANGED_GUEST_SYSENTER_MSR RT_BIT(8)
76	#define HWACCM_CHANGED_GUEST_SEGMENT_REGS RT_BIT(9)
77	#define HWACCM_CHANGED_GUEST_DEBUG RT_BIT(10)
78	#define HWACCM_CHANGED_HOST_CONTEXT RT_BIT(11)
79
80	#define HWACCM_CHANGED_ALL ( HWACCM_CHANGED_GUEST_SEGMENT_REGS \
81	\| HWACCM_CHANGED_GUEST_CR0 \
82	\| HWACCM_CHANGED_GUEST_CR3 \
83	\| HWACCM_CHANGED_GUEST_CR4 \
84	\| HWACCM_CHANGED_GUEST_GDTR \
85	\| HWACCM_CHANGED_GUEST_IDTR \
86	\| HWACCM_CHANGED_GUEST_LDTR \
87	\| HWACCM_CHANGED_GUEST_TR \
88	\| HWACCM_CHANGED_GUEST_SYSENTER_MSR \
89	\| HWACCM_CHANGED_GUEST_FPU \
90	\| HWACCM_CHANGED_GUEST_DEBUG \
91	\| HWACCM_CHANGED_HOST_CONTEXT)
92
93	#define HWACCM_CHANGED_ALL_GUEST ( HWACCM_CHANGED_GUEST_SEGMENT_REGS \
94	\| HWACCM_CHANGED_GUEST_CR0 \
95	\| HWACCM_CHANGED_GUEST_CR3 \
96	\| HWACCM_CHANGED_GUEST_CR4 \
97	\| HWACCM_CHANGED_GUEST_GDTR \
98	\| HWACCM_CHANGED_GUEST_IDTR \
99	\| HWACCM_CHANGED_GUEST_LDTR \
100	\| HWACCM_CHANGED_GUEST_TR \
101	\| HWACCM_CHANGED_GUEST_SYSENTER_MSR \
102	\| HWACCM_CHANGED_GUEST_DEBUG \
103	\| HWACCM_CHANGED_GUEST_FPU)
104
105	/** @} */
106
107	/** @name Intercepted traps
108	* Traps that need to be intercepted so we can correctly dispatch them to the guest if required.
109	* Currently #NM and #PF only
110	*/
111	#ifdef VBOX_STRICT
112	#define HWACCM_VMX_TRAP_MASK RT_BIT(X86_XCPT_DE) \| RT_BIT(X86_XCPT_NM) \| RT_BIT(X86_XCPT_PF) \| RT_BIT(X86_XCPT_UD) \| RT_BIT(X86_XCPT_NP) \| RT_BIT(X86_XCPT_SS) \| RT_BIT(X86_XCPT_GP) \| RT_BIT(X86_XCPT_MF)
113	#define HWACCM_SVM_TRAP_MASK HWACCM_VMX_TRAP_MASK
114	#else
115	#define HWACCM_VMX_TRAP_MASK RT_BIT(X86_XCPT_NM) \| RT_BIT(X86_XCPT_PF)
116	#define HWACCM_SVM_TRAP_MASK RT_BIT(X86_XCPT_NM) \| RT_BIT(X86_XCPT_PF)
117	#endif
118	/* All exceptions have to be intercept in emulated real-mode (minues NM & PF as they are always intercepted. */
119	#define HWACCM_VMX_TRAP_MASK_REALMODE RT_BIT(X86_XCPT_DE) \| RT_BIT(X86_XCPT_DB) \| RT_BIT(X86_XCPT_NMI) \| RT_BIT(X86_XCPT_BP) \| RT_BIT(X86_XCPT_OF) \| RT_BIT(X86_XCPT_BR) \| RT_BIT(X86_XCPT_UD) \| RT_BIT(X86_XCPT_DF) \| RT_BIT(X86_XCPT_CO_SEG_OVERRUN) \| RT_BIT(X86_XCPT_TS) \| RT_BIT(X86_XCPT_NP) \| RT_BIT(X86_XCPT_SS) \| RT_BIT(X86_XCPT_GP) \| RT_BIT(X86_XCPT_MF) \| RT_BIT(X86_XCPT_AC) \| RT_BIT(X86_XCPT_MC) \| RT_BIT(X86_XCPT_XF)
120	/** @} */
121
122
123	/** Maximum number of page flushes we are willing to remember before considering a full TLB flush. */
124	#define HWACCM_MAX_TLB_SHOOTDOWN_PAGES 8
125
126	/** Size for the EPT identity page table (1024 4 MB pages to cover the entire address space). */
127	#define HWACCM_EPT_IDENTITY_PG_TABLE_SIZE PAGE_SIZE
128	/** Size of the TSS structure + 2 pages for the IO bitmap + end byte. */
129	#define HWACCM_VTX_TSS_SIZE (sizeof(VBOXTSS) + 2*PAGE_SIZE + 1)
130	/** Total guest mapped memory needed. */
131	#define HWACCM_VTX_TOTAL_DEVHEAP_MEM (HWACCM_EPT_IDENTITY_PG_TABLE_SIZE + HWACCM_VTX_TSS_SIZE)
132
133	/** HWACCM SSM version
134	*/
135	#define HWACCM_SSM_VERSION 4
136	#define HWACCM_SSM_VERSION_2_0_X 3
137
138	/* Per-cpu information. (host) */
139	typedef struct
140	{
141	RTCPUID idCpu;
142
143	RTR0MEMOBJ pMemObj;
144	/* Current ASID (AMD-V)/VPID (Intel) */
145	uint32_t uCurrentASID;
146	/* TLB flush count */
147	uint32_t cTLBFlushes;
148
149	/* Set the first time a cpu is used to make sure we start with a clean TLB. */
150	bool fFlushTLB;
151
152	/** Configured for VT-x or AMD-V. */
153	bool fConfigured;
154
155	/** In use by our code. (for power suspend) */
156	volatile bool fInUse;
157	} HWACCM_CPUINFO;
158	typedef HWACCM_CPUINFO *PHWACCM_CPUINFO;
159
160	/* VT-x capability qword. */
161	typedef union
162	{
163	struct
164	{
165	uint32_t disallowed0;
166	uint32_t allowed1;
167	} n;
168	uint64_t u;
169	} VMX_CAPABILITY;
170
171	typedef enum
172	{
173	HWACCMPENDINGIO_INVALID = 0,
174	HWACCMPENDINGIO_PORT_READ,
175	HWACCMPENDINGIO_PORT_WRITE,
176	HWACCMPENDINGIO_STRING_READ,
177	HWACCMPENDINGIO_STRING_WRITE,
178	/** The usual 32-bit paranoia. */
179	HWACCMPENDINGIO_32BIT_HACK = 0x7fffffff
180	} HWACCMPENDINGIO;
181
182	/**
183	* Switcher function, HC to RC.
184	*
185	* @param pVM The VM handle.
186	* @returns Return code indicating the action to take.
187	*/
188	typedef DECLASMTYPE(int) FNHWACCMSWITCHERHC(PVM pVM);
189	/** Pointer to switcher function. */
190	typedef FNHWACCMSWITCHERHC *PFNHWACCMSWITCHERHC;
191
192	/**
193	* HWACCM VM Instance data.
194	* Changes to this must checked against the padding of the cfgm union in VM!
195	*/
196	typedef struct HWACCM
197	{
198	/** Set when we've initialized VMX or SVM. */
199	bool fInitialized;
200
201	/** Set when hardware acceleration is allowed. */
202	bool fAllowed;
203
204	/** Set if nested paging is enabled. */
205	bool fNestedPaging;
206
207	/** Set if nested paging is allowed. */
208	bool fAllowNestedPaging;
209
210	/** Set if we can support 64-bit guests or not. */
211	bool fAllow64BitGuests;
212
213	/** Set if an IO-APIC is configured for this VM. */
214	bool fHasIoApic;
215
216	/** Explicit alignment padding to make 32-bit gcc align u64RegisterMask
217	* naturally. */
218	bool padding[2];
219
220	/** And mask for copying register contents. */
221	uint64_t u64RegisterMask;
222
223	/** Maximum ASID allowed. */
224	RTUINT uMaxASID;
225
226	/** The maximum number of resumes loops allowed in ring-0 (safety precaution).
227	* This number is set much higher when RTThreadPreemptIsPending is reliable. */
228	uint32_t cMaxResumeLoops;
229
230	#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
231	/** 32 to 64 bits switcher entrypoint. */
232	R0PTRTYPE(PFNHWACCMSWITCHERHC) pfnHost32ToGuest64R0;
233
234	/* AMD-V 64 bits vmrun handler */
235	RTRCPTR pfnSVMGCVMRun64;
236
237	/* VT-x 64 bits vmlaunch handler */
238	RTRCPTR pfnVMXGCStartVM64;
239
240	/* RC handler to setup the 64 bits FPU state. */
241	RTRCPTR pfnSaveGuestFPU64;
242
243	/* RC handler to setup the 64 bits debug state. */
244	RTRCPTR pfnSaveGuestDebug64;
245
246	/* Test handler */
247	RTRCPTR pfnTest64;
248
249	RTRCPTR uAlignment[2];
250	/*#elif defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
251	uint32_t u32Alignment[1]; */
252	#endif
253
254	struct
255	{
256	/** Set by the ring-0 driver to indicate VMX is supported by the CPU. */
257	bool fSupported;
258
259	/** Set when we've enabled VMX. */
260	bool fEnabled;
261
262	/** Set if VPID is supported. */
263	bool fVPID;
264
265	/** Set if VT-x VPID is allowed. */
266	bool fAllowVPID;
267
268	/** Virtual address of the TSS page used for real mode emulation. */
269	R3PTRTYPE(PVBOXTSS) pRealModeTSS;
270
271	/** Virtual address of the identity page table used for real mode and protected mode without paging emulation in EPT mode. */
272	R3PTRTYPE(PX86PD) pNonPagingModeEPTPageTable;
273
274	/** R0 memory object for the APIC physical page (serves for filtering accesses). */
275	RTR0MEMOBJ pMemObjAPIC;
276	/** Physical address of the APIC physical page (serves for filtering accesses). */
277	RTHCPHYS pAPICPhys;
278	/** Virtual address of the APIC physical page (serves for filtering accesses). */
279	R0PTRTYPE(uint8_t *) pAPIC;
280
281	/** R0 memory object for the MSR bitmap (1 page). */
282	RTR0MEMOBJ pMemObjMSRBitmap;
283	/** Physical address of the MSR bitmap (1 page). */
284	RTHCPHYS pMSRBitmapPhys;
285	/** Virtual address of the MSR bitmap (1 page). */
286	R0PTRTYPE(uint8_t *) pMSRBitmap;
287
288	/** R0 memory object for the MSR entry load page (guest MSRs). */
289	RTR0MEMOBJ pMemObjMSREntryLoad;
290	/** Physical address of the MSR entry load page (guest MSRs). */
291	RTHCPHYS pMSREntryLoadPhys;
292	/** Virtual address of the MSR entry load page (guest MSRs). */
293	R0PTRTYPE(uint8_t *) pMSREntryLoad;
294
295	#ifdef VBOX_WITH_CRASHDUMP_MAGIC
296	RTR0MEMOBJ pMemObjScratch;
297	RTHCPHYS pScratchPhys;
298	R0PTRTYPE(uint8_t *) pScratch;
299	#endif
300	/** R0 memory object for the MSR exit store page (guest MSRs). */
301	RTR0MEMOBJ pMemObjMSRExitStore;
302	/** Physical address of the MSR exit store page (guest MSRs). */
303	RTHCPHYS pMSRExitStorePhys;
304	/** Virtual address of the MSR exit store page (guest MSRs). */
305	R0PTRTYPE(uint8_t *) pMSRExitStore;
306
307	/** R0 memory object for the MSR exit load page (host MSRs). */
308	RTR0MEMOBJ pMemObjMSRExitLoad;
309	/** Physical address of the MSR exit load page (host MSRs). */
310	RTHCPHYS pMSRExitLoadPhys;
311	/** Virtual address of the MSR exit load page (host MSRs). */
312	R0PTRTYPE(uint8_t *) pMSRExitLoad;
313
314	/** Ring 0 handlers for VT-x. */
315	DECLR0CALLBACKMEMBER(void, pfnSetupTaggedTLB, (PVM pVM, PVMCPU pVCpu));
316
317	/** Host CR4 value (set by ring-0 VMX init) */
318	uint64_t hostCR4;
319
320	/** VMX MSR values */
321	struct
322	{
323	uint64_t feature_ctrl;
324	uint64_t vmx_basic_info;
325	VMX_CAPABILITY vmx_pin_ctls;
326	VMX_CAPABILITY vmx_proc_ctls;
327	VMX_CAPABILITY vmx_proc_ctls2;
328	VMX_CAPABILITY vmx_exit;
329	VMX_CAPABILITY vmx_entry;
330	uint64_t vmx_misc;
331	uint64_t vmx_cr0_fixed0;
332	uint64_t vmx_cr0_fixed1;
333	uint64_t vmx_cr4_fixed0;
334	uint64_t vmx_cr4_fixed1;
335	uint64_t vmx_vmcs_enum;
336	uint64_t vmx_eptcaps;
337	} msr;
338
339	/** Flush types for invept & invvpid; they depend on capabilities. */
340	VMX_FLUSH enmFlushPage;
341	VMX_FLUSH enmFlushContext;
342	} vmx;
343
344	struct
345	{
346	/** Set by the ring-0 driver to indicate SVM is supported by the CPU. */
347	bool fSupported;
348	/** Set when we've enabled SVM. */
349	bool fEnabled;
350	/** Set if erratum 170 affects the AMD cpu. */
351	bool fAlwaysFlushTLB;
352	/** Explicit alignment padding to make 32-bit gcc align u64RegisterMask
353	* naturally. */
354	bool padding[1];
355
356	/** R0 memory object for the IO bitmap (12kb). */
357	RTR0MEMOBJ pMemObjIOBitmap;
358	/** Physical address of the IO bitmap (12kb). */
359	RTHCPHYS pIOBitmapPhys;
360	/** Virtual address of the IO bitmap. */
361	R0PTRTYPE(void *) pIOBitmap;
362
363	/** R0 memory object for the MSR bitmap (8kb). */
364	RTR0MEMOBJ pMemObjMSRBitmap;
365	/** Physical address of the MSR bitmap (8kb). */
366	RTHCPHYS pMSRBitmapPhys;
367	/** Virtual address of the MSR bitmap. */
368	R0PTRTYPE(void *) pMSRBitmap;
369
370	/** SVM revision. */
371	uint32_t u32Rev;
372
373	/** SVM feature bits from cpuid 0x8000000a */
374	uint32_t u32Features;
375	} svm;
376
377	struct
378	{
379	uint32_t u32AMDFeatureECX;
380	uint32_t u32AMDFeatureEDX;
381	} cpuid;
382
383	/** Saved error from detection */
384	int32_t lLastError;
385
386	/** HWACCMR0Init was run */
387	bool fHWACCMR0Init;
388	} HWACCM;
389	/** Pointer to HWACCM VM instance data. */
390	typedef HWACCM *PHWACCM;
391
392	/* Maximum number of cached entries. */
393	#define VMCSCACHE_MAX_ENTRY 128
394
395	/* Structure for storing read and write VMCS actions. */
396	typedef struct VMCSCACHE
397	{
398	#ifdef VBOX_WITH_CRASHDUMP_MAGIC
399	/* Magic marker for searching in crash dumps. */
400	uint8_t aMagic[16];
401	uint64_t uMagic;
402	uint64_t u64TimeEntry;
403	uint64_t u64TimeSwitch;
404	uint64_t cResume;
405	uint64_t interPD;
406	uint64_t pSwitcher;
407	uint32_t uPos;
408	uint32_t idCpu;
409	#endif
410	/* CR2 is saved here for EPT syncing. */
411	uint64_t cr2;
412	struct
413	{
414	uint32_t cValidEntries;
415	uint32_t uAlignment;
416	uint32_t aField[VMCSCACHE_MAX_ENTRY];
417	uint64_t aFieldVal[VMCSCACHE_MAX_ENTRY];
418	} Write;
419	struct
420	{
421	uint32_t cValidEntries;
422	uint32_t uAlignment;
423	uint32_t aField[VMCSCACHE_MAX_ENTRY];
424	uint64_t aFieldVal[VMCSCACHE_MAX_ENTRY];
425	} Read;
426	#ifdef DEBUG
427	struct
428	{
429	RTHCPHYS pPageCpuPhys;
430	RTHCPHYS pVMCSPhys;
431	RTGCPTR pCache;
432	RTGCPTR pCtx;
433	} TestIn;
434	struct
435	{
436	RTHCPHYS pVMCSPhys;
437	RTGCPTR pCache;
438	RTGCPTR pCtx;
439	uint64_t eflags;
440	uint64_t cr8;
441	} TestOut;
442	struct
443	{
444	uint64_t param1;
445	uint64_t param2;
446	uint64_t param3;
447	uint64_t param4;
448	} ScratchPad;
449	#endif
450	} VMCSCACHE;
451	/** Pointer to VMCSCACHE. */
452	typedef VMCSCACHE *PVMCSCACHE;
453
454	/** VMX StartVM function. */
455	typedef DECLCALLBACK(int) FNHWACCMVMXSTARTVM(RTHCUINT fResume, PCPUMCTX pCtx, PVMCSCACHE pCache, PVM pVM, PVMCPU pVCpu);
456	/** Pointer to a VMX StartVM function. */
457	typedef R0PTRTYPE(FNHWACCMVMXSTARTVM *) PFNHWACCMVMXSTARTVM;
458
459	/** SVM VMRun function. */
460	typedef DECLCALLBACK(int) FNHWACCMSVMVMRUN(RTHCPHYS pVMCBHostPhys, RTHCPHYS pVMCBPhys, PCPUMCTX pCtx, PVM pVM, PVMCPU pVCpu);
461	/** Pointer to a SVM VMRun function. */
462	typedef R0PTRTYPE(FNHWACCMSVMVMRUN *) PFNHWACCMSVMVMRUN;
463
464	/**
465	* HWACCM VMCPU Instance data.
466	*/
467	typedef struct HWACCMCPU
468	{
469	/** Old style FPU reporting trap mask override performed (optimization) */
470	bool fFPUOldStyleOverride;
471
472	/** Set if we don't have to flush the TLB on VM entry. */
473	bool fResumeVM;
474
475	/** Set if we need to flush the TLB during the world switch. */
476	bool fForceTLBFlush;
477
478	/** Set when we're using VT-x or AMD-V at that moment. */
479	bool fActive;
480
481	/** HWACCM_CHANGED_* flags. */
482	RTUINT fContextUseFlags;
483
484	/* Id of the last cpu we were executing code on (NIL_RTCPUID for the first time) */
485	RTCPUID idLastCpu;
486
487	/* TLB flush count */
488	RTUINT cTLBFlushes;
489
490	/* Current ASID in use by the VM */
491	RTUINT uCurrentASID;
492
493	struct
494	{
495	/** R0 memory object for the VM control structure (VMCS). */
496	RTR0MEMOBJ pMemObjVMCS;
497	/** Physical address of the VM control structure (VMCS). */
498	RTHCPHYS pVMCSPhys;
499	/** Virtual address of the VM control structure (VMCS). */
500	R0PTRTYPE(void *) pVMCS;
501
502	/** Ring 0 handlers for VT-x. */
503	PFNHWACCMVMXSTARTVM pfnStartVM;
504
505	/** Current VMX_VMCS_CTRL_PROC_EXEC_CONTROLS. */
506	uint64_t proc_ctls;
507
508	/** Current VMX_VMCS_CTRL_PROC_EXEC2_CONTROLS. */
509	uint64_t proc_ctls2;
510
511	/** R0 memory object for the virtual APIC page for TPR caching. */
512	RTR0MEMOBJ pMemObjVAPIC;
513	/** Physical address of the virtual APIC page for TPR caching. */
514	RTHCPHYS pVAPICPhys;
515	/** Virtual address of the virtual APIC page for TPR caching. */
516	R0PTRTYPE(uint8_t *) pVAPIC;
517
518	/** Current CR0 mask. */
519	uint64_t cr0_mask;
520	/** Current CR4 mask. */
521	uint64_t cr4_mask;
522
523	/** Current EPTP. */
524	RTHCPHYS GCPhysEPTP;
525
526	/** VMCS cache. */
527	VMCSCACHE VMCSCache;
528
529	/** Real-mode emulation state. */
530	struct
531	{
532	X86EFLAGS eflags;
533	uint32_t fValid;
534	} RealMode;
535
536	struct
537	{
538	uint64_t u64VMCSPhys;
539	uint32_t ulVMCSRevision;
540	uint32_t ulInstrError;
541	uint32_t ulExitReason;
542	RTCPUID idEnteredCpu;
543	RTCPUID idCurrentCpu;
544	uint32_t padding;
545	} lasterror;
546
547	/** The last seen guest paging mode (by VT-x). */
548	PGMMODE enmLastSeenGuestMode;
549	/** Current guest paging mode (as seen by HWACCMR3PagingModeChanged). */
550	PGMMODE enmCurrGuestMode;
551	/** Previous guest paging mode (as seen by HWACCMR3PagingModeChanged). */
552	PGMMODE enmPrevGuestMode;
553	} vmx;
554
555	struct
556	{
557	/** R0 memory object for the host VM control block (VMCB). */
558	RTR0MEMOBJ pMemObjVMCBHost;
559	/** Physical address of the host VM control block (VMCB). */
560	RTHCPHYS pVMCBHostPhys;
561	/** Virtual address of the host VM control block (VMCB). */
562	R0PTRTYPE(void *) pVMCBHost;
563
564	/** R0 memory object for the VM control block (VMCB). */
565	RTR0MEMOBJ pMemObjVMCB;
566	/** Physical address of the VM control block (VMCB). */
567	RTHCPHYS pVMCBPhys;
568	/** Virtual address of the VM control block (VMCB). */
569	R0PTRTYPE(void *) pVMCB;
570
571	/** Ring 0 handlers for VT-x. */
572	PFNHWACCMSVMVMRUN pfnVMRun;
573
574	} svm;
575
576	/** Event injection state. */
577	struct
578	{
579	uint32_t fPending;
580	uint32_t errCode;
581	uint64_t intInfo;
582	} Event;
583
584	/** IO Block emulation state. */
585	struct
586	{
587	bool fEnabled;
588	uint8_t u8Align[7];
589
590	/** RIP at the start of the io code we wish to emulate in the recompiler. */
591	RTGCPTR GCPtrFunctionEip;
592
593	uint64_t cr0;
594	} EmulateIoBlock;
595
596	struct
597	{
598	/* Pending IO operation type. */
599	HWACCMPENDINGIO enmType;
600	uint32_t uPadding;
601	RTGCPTR GCPtrRip;
602	RTGCPTR GCPtrRipNext;
603	union
604	{
605	struct
606	{
607	unsigned uPort;
608	unsigned uAndVal;
609	unsigned cbSize;
610	} Read;
611	struct
612	{
613	unsigned uPort;
614	unsigned uValue;
615	unsigned cbSize;
616	} Write;
617	uint64_t aRaw[2];
618	} Port;
619	} PendingIO;
620
621	/** Currenty shadow paging mode. */
622	PGMMODE enmShadowMode;
623
624	/** The CPU ID of the CPU currently owning the VMCS. Set in
625	* HWACCMR0Enter and cleared in HWACCMR0Leave. */
626	RTCPUID idEnteredCpu;
627
628	/** To keep track of pending TLB shootdown pages. (SMP guest only) */
629	struct
630	{
631	RTGCPTR aPages[HWACCM_MAX_TLB_SHOOTDOWN_PAGES];
632	unsigned cPages;
633	} TlbShootdown;
634
635	/** For saving stack space, the disassembler state is allocated here instead of
636	* on the stack.
637	* @note The DISCPUSTATE structure is not R3/R0/RZ clean! */
638	union
639	{
640	/** The disassembler scratch space. */
641	DISCPUSTATE DisState;
642	/** Padding. */
643	uint8_t abDisStatePadding[DISCPUSTATE_PADDING_SIZE];
644	};
645
646	RTUINT padding2[1];
647
648	STAMPROFILEADV StatEntry;
649	STAMPROFILEADV StatExit1;
650	STAMPROFILEADV StatExit2;
651	#if 1 /* temporary for tracking down darwin issues. */
652	STAMPROFILEADV StatExit2Sub1;
653	STAMPROFILEADV StatExit2Sub2;
654	STAMPROFILEADV StatExit2Sub3;
655	#endif
656	STAMPROFILEADV StatInGC;
657
658	#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
659	STAMPROFILEADV StatWorldSwitch3264;
660	#endif
661
662	STAMCOUNTER StatIntInject;
663
664	STAMCOUNTER StatExitShadowNM;
665	STAMCOUNTER StatExitGuestNM;
666	STAMCOUNTER StatExitShadowPF;
667	STAMCOUNTER StatExitGuestPF;
668	STAMCOUNTER StatExitGuestUD;
669	STAMCOUNTER StatExitGuestSS;
670	STAMCOUNTER StatExitGuestNP;
671	STAMCOUNTER StatExitGuestGP;
672	STAMCOUNTER StatExitGuestDE;
673	STAMCOUNTER StatExitGuestDB;
674	STAMCOUNTER StatExitGuestMF;
675	STAMCOUNTER StatExitInvpg;
676	STAMCOUNTER StatExitInvd;
677	STAMCOUNTER StatExitCpuid;
678	STAMCOUNTER StatExitRdtsc;
679	STAMCOUNTER StatExitRdpmc;
680	STAMCOUNTER StatExitCli;
681	STAMCOUNTER StatExitSti;
682	STAMCOUNTER StatExitPushf;
683	STAMCOUNTER StatExitPopf;
684	STAMCOUNTER StatExitIret;
685	STAMCOUNTER StatExitInt;
686	STAMCOUNTER StatExitCRxWrite[16];
687	STAMCOUNTER StatExitCRxRead[16];
688	STAMCOUNTER StatExitDRxWrite;
689	STAMCOUNTER StatExitDRxRead;
690	STAMCOUNTER StatExitRdmsr;
691	STAMCOUNTER StatExitWrmsr;
692	STAMCOUNTER StatExitCLTS;
693	STAMCOUNTER StatExitHlt;
694	STAMCOUNTER StatExitMwait;
695	STAMCOUNTER StatExitLMSW;
696	STAMCOUNTER StatExitIOWrite;
697	STAMCOUNTER StatExitIORead;
698	STAMCOUNTER StatExitIOStringWrite;
699	STAMCOUNTER StatExitIOStringRead;
700	STAMCOUNTER StatExitIrqWindow;
701	STAMCOUNTER StatExitMaxResume;
702	STAMCOUNTER StatExitPreemptPending;
703	STAMCOUNTER StatIntReinject;
704	STAMCOUNTER StatPendingHostIrq;
705
706	STAMCOUNTER StatFlushPageManual;
707	STAMCOUNTER StatFlushPhysPageManual;
708	STAMCOUNTER StatFlushTLBManual;
709	STAMCOUNTER StatFlushPageInvlpg;
710	STAMCOUNTER StatFlushTLBWorldSwitch;
711	STAMCOUNTER StatNoFlushTLBWorldSwitch;
712	STAMCOUNTER StatFlushTLBCRxChange;
713	STAMCOUNTER StatFlushASID;
714	STAMCOUNTER StatFlushTLBInvlpga;
715	STAMCOUNTER StatTlbShootdown;
716	STAMCOUNTER StatTlbShootdownFlush;
717
718	STAMCOUNTER StatSwitchGuestIrq;
719	STAMCOUNTER StatSwitchToR3;
720
721	STAMCOUNTER StatTSCOffset;
722	STAMCOUNTER StatTSCIntercept;
723
724	STAMCOUNTER StatExitReasonNPF;
725	STAMCOUNTER StatDRxArmed;
726	STAMCOUNTER StatDRxContextSwitch;
727	STAMCOUNTER StatDRxIOCheck;
728
729
730	#ifdef VBOX_WITH_STATISTICS
731	R3PTRTYPE(PSTAMCOUNTER) paStatExitReason;
732	R0PTRTYPE(PSTAMCOUNTER) paStatExitReasonR0;
733	R3PTRTYPE(PSTAMCOUNTER) paStatInjectedIrqs;
734	R0PTRTYPE(PSTAMCOUNTER) paStatInjectedIrqsR0;
735	#endif
736	} HWACCMCPU;
737	/** Pointer to HWACCM VM instance data. */
738	typedef HWACCMCPU *PHWACCMCPU;
739
740
741	#ifdef IN_RING0
742
743	VMMR0DECL(PHWACCM_CPUINFO) HWACCMR0GetCurrentCpu();
744	VMMR0DECL(PHWACCM_CPUINFO) HWACCMR0GetCurrentCpuEx(RTCPUID idCpu);
745
746
747	#ifdef VBOX_STRICT
748	VMMR0DECL(void) HWACCMDumpRegs(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
749	VMMR0DECL(void) HWACCMR0DumpDescriptor(PX86DESCHC Desc, RTSEL Sel, const char *pszMsg);
750	#else
751	#define HWACCMDumpRegs(a, b ,c) do { } while (0)
752	#define HWACCMR0DumpDescriptor(a, b, c) do { } while (0)
753	#endif
754
755	/* Dummy callback handlers. */
756	VMMR0DECL(int) HWACCMR0DummyEnter(PVM pVM, PVMCPU pVCpu, PHWACCM_CPUINFO pCpu);
757	VMMR0DECL(int) HWACCMR0DummyLeave(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
758	VMMR0DECL(int) HWACCMR0DummyEnableCpu(PHWACCM_CPUINFO pCpu, PVM pVM, void *pvPageCpu, RTHCPHYS pPageCpuPhys);
759	VMMR0DECL(int) HWACCMR0DummyDisableCpu(PHWACCM_CPUINFO pCpu, void *pvPageCpu, RTHCPHYS pPageCpuPhys);
760	VMMR0DECL(int) HWACCMR0DummyInitVM(PVM pVM);
761	VMMR0DECL(int) HWACCMR0DummyTermVM(PVM pVM);
762	VMMR0DECL(int) HWACCMR0DummySetupVM(PVM pVM);
763	VMMR0DECL(int) HWACCMR0DummyRunGuestCode(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
764	VMMR0DECL(int) HWACCMR0DummySaveHostState(PVM pVM, PVMCPU pVCpu);
765	VMMR0DECL(int) HWACCMR0DummyLoadGuestState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
766
767	# ifdef VBOX_WITH_KERNEL_USING_XMM
768	DECLASM(int) hwaccmR0VMXStartVMWrapXMM(RTHCUINT fResume, PCPUMCTX pCtx, PVMCSCACHE pCache, PVM pVM, PVMCPU pVCpu, PFNHWACCMVMXSTARTVM pfnStartVM);
769	DECLASM(int) hwaccmR0SVMRunWrapXMM(RTHCPHYS pVMCBHostPhys, RTHCPHYS pVMCBPhys, PCPUMCTX pCtx, PVM pVM, PVMCPU pVCpu, PFNHWACCMSVMVMRUN pfnVMRun);
770	# endif
771
772	# ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
773	/**
774	* Gets 64-bit GDTR and IDTR on darwin.
775	* @param pGdtr Where to store the 64-bit GDTR.
776	* @param pIdtr Where to store the 64-bit IDTR.
777	*/
778	DECLASM(void) hwaccmR0Get64bitGDTRandIDTR(PX86XDTR64 pGdtr, PX86XDTR64 pIdtr);
779
780	/**
781	* Gets 64-bit CR3 on darwin.
782	* @returns CR3
783	*/
784	DECLASM(uint64_t) hwaccmR0Get64bitCR3(void);
785	# endif
786
787	#endif /* IN_RING0 */
788
789	/** @} */
790
791	RT_C_DECLS_END
792
793	#endif
794

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source: vbox/trunk/src/VBox/VMM/HWACCMInternal.h@ 21209

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