HWACCMInternal.h@ 22041

Last change on this file since 22041 was 22040, checked in by vboxsync, 15 years ago
VT-x: use MSR bitmaps and automatic load/store (risky change).
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File size: 31.4 KB

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1	/* $Id: HWACCMInternal.h 22040 2009-08-06 16:33:21Z vboxsync $ */
2	/** @file
3	* HWACCM - Internal header file.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22	#ifndef ___HWACCMInternal_h
23	#define ___HWACCMInternal_h
24
25	#include <VBox/cdefs.h>
26	#include <VBox/types.h>
27	#include <VBox/em.h>
28	#include <VBox/stam.h>
29	#include <VBox/dis.h>
30	#include <VBox/hwaccm.h>
31	#include <VBox/pgm.h>
32	#include <VBox/cpum.h>
33	#include <iprt/memobj.h>
34	#include <iprt/cpuset.h>
35	#include <iprt/mp.h>
36	#include <iprt/avl.h>
37
38	#if HC_ARCH_BITS == 64 \|\| defined(VBOX_WITH_HYBRID_32BIT_KERNEL) \|\| defined (VBOX_WITH_64_BITS_GUESTS)
39	/* Enable 64 bits guest support. */
40	# define VBOX_ENABLE_64_BITS_GUESTS
41	#endif
42
43	#define VMX_USE_CACHED_VMCS_ACCESSES
44	#define HWACCM_VMX_EMULATE_REALMODE
45	#define HWACCM_VTX_WITH_EPT
46	#define HWACCM_VTX_WITH_VPID
47
48	RT_C_DECLS_BEGIN
49
50
51	/** @defgroup grp_hwaccm_int Internal
52	* @ingroup grp_hwaccm
53	* @internal
54	* @{
55	*/
56
57
58	/** Maximum number of exit reason statistics counters. */
59	#define MAX_EXITREASON_STAT 0x100
60	#define MASK_EXITREASON_STAT 0xff
61	#define MASK_INJECT_IRQ_STAT 0xff
62
63	/** @name Changed flags
64	* These flags are used to keep track of which important registers that
65	* have been changed since last they were reset.
66	* @{
67	*/
68	#define HWACCM_CHANGED_GUEST_FPU RT_BIT(0)
69	#define HWACCM_CHANGED_GUEST_CR0 RT_BIT(1)
70	#define HWACCM_CHANGED_GUEST_CR3 RT_BIT(2)
71	#define HWACCM_CHANGED_GUEST_CR4 RT_BIT(3)
72	#define HWACCM_CHANGED_GUEST_GDTR RT_BIT(4)
73	#define HWACCM_CHANGED_GUEST_IDTR RT_BIT(5)
74	#define HWACCM_CHANGED_GUEST_LDTR RT_BIT(6)
75	#define HWACCM_CHANGED_GUEST_TR RT_BIT(7)
76	#define HWACCM_CHANGED_GUEST_SYSENTER_MSR RT_BIT(8)
77	#define HWACCM_CHANGED_GUEST_SEGMENT_REGS RT_BIT(9)
78	#define HWACCM_CHANGED_GUEST_DEBUG RT_BIT(10)
79	#define HWACCM_CHANGED_HOST_CONTEXT RT_BIT(11)
80
81	#define HWACCM_CHANGED_ALL ( HWACCM_CHANGED_GUEST_SEGMENT_REGS \
82	\| HWACCM_CHANGED_GUEST_CR0 \
83	\| HWACCM_CHANGED_GUEST_CR3 \
84	\| HWACCM_CHANGED_GUEST_CR4 \
85	\| HWACCM_CHANGED_GUEST_GDTR \
86	\| HWACCM_CHANGED_GUEST_IDTR \
87	\| HWACCM_CHANGED_GUEST_LDTR \
88	\| HWACCM_CHANGED_GUEST_TR \
89	\| HWACCM_CHANGED_GUEST_SYSENTER_MSR \
90	\| HWACCM_CHANGED_GUEST_FPU \
91	\| HWACCM_CHANGED_GUEST_DEBUG \
92	\| HWACCM_CHANGED_HOST_CONTEXT)
93
94	#define HWACCM_CHANGED_ALL_GUEST ( HWACCM_CHANGED_GUEST_SEGMENT_REGS \
95	\| HWACCM_CHANGED_GUEST_CR0 \
96	\| HWACCM_CHANGED_GUEST_CR3 \
97	\| HWACCM_CHANGED_GUEST_CR4 \
98	\| HWACCM_CHANGED_GUEST_GDTR \
99	\| HWACCM_CHANGED_GUEST_IDTR \
100	\| HWACCM_CHANGED_GUEST_LDTR \
101	\| HWACCM_CHANGED_GUEST_TR \
102	\| HWACCM_CHANGED_GUEST_SYSENTER_MSR \
103	\| HWACCM_CHANGED_GUEST_DEBUG \
104	\| HWACCM_CHANGED_GUEST_FPU)
105
106	/** @} */
107
108	/** @name Intercepted traps
109	* Traps that need to be intercepted so we can correctly dispatch them to the guest if required.
110	* Currently #NM and #PF only
111	*/
112	#ifdef VBOX_STRICT
113	#define HWACCM_VMX_TRAP_MASK RT_BIT(X86_XCPT_DE) \| RT_BIT(X86_XCPT_NM) \| RT_BIT(X86_XCPT_PF) \| RT_BIT(X86_XCPT_UD) \| RT_BIT(X86_XCPT_NP) \| RT_BIT(X86_XCPT_SS) \| RT_BIT(X86_XCPT_GP) \| RT_BIT(X86_XCPT_MF)
114	#define HWACCM_SVM_TRAP_MASK HWACCM_VMX_TRAP_MASK
115	#else
116	#define HWACCM_VMX_TRAP_MASK RT_BIT(X86_XCPT_NM) \| RT_BIT(X86_XCPT_PF)
117	#define HWACCM_SVM_TRAP_MASK RT_BIT(X86_XCPT_NM) \| RT_BIT(X86_XCPT_PF)
118	#endif
119	/* All exceptions have to be intercept in emulated real-mode (minues NM & PF as they are always intercepted. */
120	#define HWACCM_VMX_TRAP_MASK_REALMODE RT_BIT(X86_XCPT_DE) \| RT_BIT(X86_XCPT_DB) \| RT_BIT(X86_XCPT_NMI) \| RT_BIT(X86_XCPT_BP) \| RT_BIT(X86_XCPT_OF) \| RT_BIT(X86_XCPT_BR) \| RT_BIT(X86_XCPT_UD) \| RT_BIT(X86_XCPT_DF) \| RT_BIT(X86_XCPT_CO_SEG_OVERRUN) \| RT_BIT(X86_XCPT_TS) \| RT_BIT(X86_XCPT_NP) \| RT_BIT(X86_XCPT_SS) \| RT_BIT(X86_XCPT_GP) \| RT_BIT(X86_XCPT_MF) \| RT_BIT(X86_XCPT_AC) \| RT_BIT(X86_XCPT_MC) \| RT_BIT(X86_XCPT_XF)
121	/** @} */
122
123
124	/** Maximum number of page flushes we are willing to remember before considering a full TLB flush. */
125	#define HWACCM_MAX_TLB_SHOOTDOWN_PAGES 8
126
127	/** Size for the EPT identity page table (1024 4 MB pages to cover the entire address space). */
128	#define HWACCM_EPT_IDENTITY_PG_TABLE_SIZE PAGE_SIZE
129	/** Size of the TSS structure + 2 pages for the IO bitmap + end byte. */
130	#define HWACCM_VTX_TSS_SIZE (sizeof(VBOXTSS) + 2*PAGE_SIZE + 1)
131	/** Total guest mapped memory needed. */
132	#define HWACCM_VTX_TOTAL_DEVHEAP_MEM (HWACCM_EPT_IDENTITY_PG_TABLE_SIZE + HWACCM_VTX_TSS_SIZE)
133
134	/* Enable for TPR guest patching. */
135	//#define VBOX_HWACCM_WITH_GUEST_PATCHING
136
137	/** HWACCM SSM version
138	*/
139	#ifdef VBOX_HWACCM_WITH_GUEST_PATCHING
140	#define HWACCM_SSM_VERSION 5
141	#define HWACCM_SSM_VERSION_NO_PATCHING 4
142	#else
143	#define HWACCM_SSM_VERSION 4
144	#define HWACCM_SSM_VERSION_NO_PATCHING 4
145	#endif
146	#define HWACCM_SSM_VERSION_2_0_X 3
147
148	/* Per-cpu information. (host) */
149	typedef struct
150	{
151	RTCPUID idCpu;
152
153	RTR0MEMOBJ pMemObj;
154	/* Current ASID (AMD-V)/VPID (Intel) */
155	uint32_t uCurrentASID;
156	/* TLB flush count */
157	uint32_t cTLBFlushes;
158
159	/* Set the first time a cpu is used to make sure we start with a clean TLB. */
160	bool fFlushTLB;
161
162	/** Configured for VT-x or AMD-V. */
163	bool fConfigured;
164
165	/** In use by our code. (for power suspend) */
166	volatile bool fInUse;
167	} HWACCM_CPUINFO;
168	typedef HWACCM_CPUINFO *PHWACCM_CPUINFO;
169
170	/* VT-x capability qword. */
171	typedef union
172	{
173	struct
174	{
175	uint32_t disallowed0;
176	uint32_t allowed1;
177	} n;
178	uint64_t u;
179	} VMX_CAPABILITY;
180
181	typedef enum
182	{
183	HWACCMPENDINGIO_INVALID = 0,
184	HWACCMPENDINGIO_PORT_READ,
185	HWACCMPENDINGIO_PORT_WRITE,
186	HWACCMPENDINGIO_STRING_READ,
187	HWACCMPENDINGIO_STRING_WRITE,
188	/** The usual 32-bit paranoia. */
189	HWACCMPENDINGIO_32BIT_HACK = 0x7fffffff
190	} HWACCMPENDINGIO;
191
192
193	typedef enum
194	{
195	HWACCMTPRINSTR_INVALID,
196	HWACCMTPRINSTR_READ,
197	HWACCMTPRINSTR_READ_SHR4,
198	HWACCMTPRINSTR_WRITE_REG,
199	HWACCMTPRINSTR_WRITE_IMM,
200	HWACCMTPRINSTR_JUMP_REPLACEMENT,
201	/** The usual 32-bit paranoia. */
202	HWACCMTPRINSTR_32BIT_HACK = 0x7fffffff
203	} HWACCMTPRINSTR;
204
205	typedef struct
206	{
207	/** The key is the address of patched instruction. (32 bits GC ptr) */
208	AVLOU32NODECORE Core;
209	/** Original opcode. */
210	uint8_t aOpcode[16];
211	/** Instruction size. */
212	uint32_t cbOp;
213	/** Replacement opcode. */
214	uint8_t aNewOpcode[16];
215	/** Replacement instruction size. */
216	uint32_t cbNewOp;
217	/** Instruction type. */
218	HWACCMTPRINSTR enmType;
219	/** Source operand. */
220	uint32_t uSrcOperand;
221	/** Destination operand. */
222	uint32_t uDstOperand;
223	/** Number of times the instruction caused a fault. */
224	uint32_t cFaults;
225	/** Patch address of the jump replacement. */
226	RTGCPTR32 pJumpTarget;
227	} HWACCMTPRPATCH;
228	/** Pointer to HWACCMTPRPATCH. */
229	typedef HWACCMTPRPATCH *PHWACCMTPRPATCH;
230
231	/**
232	* Switcher function, HC to RC.
233	*
234	* @param pVM The VM handle.
235	* @returns Return code indicating the action to take.
236	*/
237	typedef DECLASMTYPE(int) FNHWACCMSWITCHERHC(PVM pVM);
238	/** Pointer to switcher function. */
239	typedef FNHWACCMSWITCHERHC *PFNHWACCMSWITCHERHC;
240
241	/**
242	* HWACCM VM Instance data.
243	* Changes to this must checked against the padding of the cfgm union in VM!
244	*/
245	typedef struct HWACCM
246	{
247	/** Set when we've initialized VMX or SVM. */
248	bool fInitialized;
249
250	/** Set when hardware acceleration is allowed. */
251	bool fAllowed;
252
253	/** Set if nested paging is enabled. */
254	bool fNestedPaging;
255
256	/** Set if nested paging is allowed. */
257	bool fAllowNestedPaging;
258
259	/** Set if we can support 64-bit guests or not. */
260	bool fAllow64BitGuests;
261
262	/** Set if an IO-APIC is configured for this VM. */
263	bool fHasIoApic;
264
265	/** Explicit alignment padding to make 32-bit gcc align u64RegisterMask
266	* naturally. */
267	bool padding[2];
268
269	/** And mask for copying register contents. */
270	uint64_t u64RegisterMask;
271
272	/** Maximum ASID allowed. */
273	RTUINT uMaxASID;
274
275	/** The maximum number of resumes loops allowed in ring-0 (safety precaution).
276	* This number is set much higher when RTThreadPreemptIsPending is reliable. */
277	uint32_t cMaxResumeLoops;
278
279	/** Guest allocated memory for patching purposes. */
280	RTGCPTR pGuestPatchMem;
281	/** Current free pointer inside the patch block. */
282	RTGCPTR pFreeGuestPatchMem;
283	/** Size of the guest patch memory block. */
284	uint32_t cbGuestPatchMem;
285	uint32_t uPadding1;
286
287	#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
288	/** 32 to 64 bits switcher entrypoint. */
289	R0PTRTYPE(PFNHWACCMSWITCHERHC) pfnHost32ToGuest64R0;
290
291	/* AMD-V 64 bits vmrun handler */
292	RTRCPTR pfnSVMGCVMRun64;
293
294	/* VT-x 64 bits vmlaunch handler */
295	RTRCPTR pfnVMXGCStartVM64;
296
297	/* RC handler to setup the 64 bits FPU state. */
298	RTRCPTR pfnSaveGuestFPU64;
299
300	/* RC handler to setup the 64 bits debug state. */
301	RTRCPTR pfnSaveGuestDebug64;
302
303	/* Test handler */
304	RTRCPTR pfnTest64;
305
306	RTRCPTR uAlignment[2];
307	/*#elif defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
308	uint32_t u32Alignment[1]; */
309	#endif
310
311	struct
312	{
313	/** Set by the ring-0 driver to indicate VMX is supported by the CPU. */
314	bool fSupported;
315
316	/** Set when we've enabled VMX. */
317	bool fEnabled;
318
319	/** Set if VPID is supported. */
320	bool fVPID;
321
322	/** Set if VT-x VPID is allowed. */
323	bool fAllowVPID;
324
325	/** Virtual address of the TSS page used for real mode emulation. */
326	R3PTRTYPE(PVBOXTSS) pRealModeTSS;
327
328	/** Virtual address of the identity page table used for real mode and protected mode without paging emulation in EPT mode. */
329	R3PTRTYPE(PX86PD) pNonPagingModeEPTPageTable;
330
331	/** R0 memory object for the APIC physical page (serves for filtering accesses). */
332	RTR0MEMOBJ pMemObjAPIC;
333	/** Physical address of the APIC physical page (serves for filtering accesses). */
334	RTHCPHYS pAPICPhys;
335	/** Virtual address of the APIC physical page (serves for filtering accesses). */
336	R0PTRTYPE(uint8_t *) pAPIC;
337
338	/** R0 memory object for the MSR entry load page (guest MSRs). */
339	RTR0MEMOBJ pMemObjMSREntryLoad;
340	/** Physical address of the MSR entry load page (guest MSRs). */
341	RTHCPHYS pMSREntryLoadPhys;
342	/** Virtual address of the MSR entry load page (guest MSRs). */
343	R0PTRTYPE(uint8_t *) pMSREntryLoad;
344
345	#ifdef VBOX_WITH_CRASHDUMP_MAGIC
346	RTR0MEMOBJ pMemObjScratch;
347	RTHCPHYS pScratchPhys;
348	R0PTRTYPE(uint8_t *) pScratch;
349	#endif
350	/** R0 memory object for the MSR exit store page (guest MSRs). */
351	RTR0MEMOBJ pMemObjMSRExitStore;
352	/** Physical address of the MSR exit store page (guest MSRs). */
353	RTHCPHYS pMSRExitStorePhys;
354	/** Virtual address of the MSR exit store page (guest MSRs). */
355	R0PTRTYPE(uint8_t *) pMSRExitStore;
356
357	/** R0 memory object for the MSR exit load page (host MSRs). */
358	RTR0MEMOBJ pMemObjMSRExitLoad;
359	/** Physical address of the MSR exit load page (host MSRs). */
360	RTHCPHYS pMSRExitLoadPhys;
361	/** Virtual address of the MSR exit load page (host MSRs). */
362	R0PTRTYPE(uint8_t *) pMSRExitLoad;
363
364	/** Ring 0 handlers for VT-x. */
365	DECLR0CALLBACKMEMBER(void, pfnSetupTaggedTLB, (PVM pVM, PVMCPU pVCpu));
366
367	/** Host CR4 value (set by ring-0 VMX init) */
368	uint64_t hostCR4;
369
370	/** VMX MSR values */
371	struct
372	{
373	uint64_t feature_ctrl;
374	uint64_t vmx_basic_info;
375	VMX_CAPABILITY vmx_pin_ctls;
376	VMX_CAPABILITY vmx_proc_ctls;
377	VMX_CAPABILITY vmx_proc_ctls2;
378	VMX_CAPABILITY vmx_exit;
379	VMX_CAPABILITY vmx_entry;
380	uint64_t vmx_misc;
381	uint64_t vmx_cr0_fixed0;
382	uint64_t vmx_cr0_fixed1;
383	uint64_t vmx_cr4_fixed0;
384	uint64_t vmx_cr4_fixed1;
385	uint64_t vmx_vmcs_enum;
386	uint64_t vmx_eptcaps;
387	} msr;
388
389	/** Flush types for invept & invvpid; they depend on capabilities. */
390	VMX_FLUSH enmFlushPage;
391	VMX_FLUSH enmFlushContext;
392	} vmx;
393
394	struct
395	{
396	/** Set by the ring-0 driver to indicate SVM is supported by the CPU. */
397	bool fSupported;
398	/** Set when we've enabled SVM. */
399	bool fEnabled;
400	/** Set if erratum 170 affects the AMD cpu. */
401	bool fAlwaysFlushTLB;
402	/** Set when TPR patching is active. */
403	bool fTPRPatchingActive;
404
405	/** R0 memory object for the IO bitmap (12kb). */
406	RTR0MEMOBJ pMemObjIOBitmap;
407	/** Physical address of the IO bitmap (12kb). */
408	RTHCPHYS pIOBitmapPhys;
409	/** Virtual address of the IO bitmap. */
410	R0PTRTYPE(void *) pIOBitmap;
411
412	/** SVM revision. */
413	uint32_t u32Rev;
414
415	/** SVM feature bits from cpuid 0x8000000a */
416	uint32_t u32Features;
417
418	/**
419	* AVL tree with all patches (active or disabled) sorted by guest instruction address
420	*/
421	AVLOU32TREE PatchTree;
422	uint32_t cPatches;
423	HWACCMTPRPATCH aPatches[64];
424	} svm;
425
426	struct
427	{
428	uint32_t u32AMDFeatureECX;
429	uint32_t u32AMDFeatureEDX;
430	} cpuid;
431
432	/** Saved error from detection */
433	int32_t lLastError;
434
435	/** HWACCMR0Init was run */
436	bool fHWACCMR0Init;
437	bool u8Alignment[7];
438
439	STAMCOUNTER StatTPRPatchSuccess;
440	STAMCOUNTER StatTPRPatchFailure;
441	STAMCOUNTER StatTPRReplaceSuccess;
442	STAMCOUNTER StatTPRReplaceFailure;
443	} HWACCM;
444	/** Pointer to HWACCM VM instance data. */
445	typedef HWACCM *PHWACCM;
446
447	/* Maximum number of cached entries. */
448	#define VMCSCACHE_MAX_ENTRY 128
449
450	/* Structure for storing read and write VMCS actions. */
451	typedef struct VMCSCACHE
452	{
453	#ifdef VBOX_WITH_CRASHDUMP_MAGIC
454	/* Magic marker for searching in crash dumps. */
455	uint8_t aMagic[16];
456	uint64_t uMagic;
457	uint64_t u64TimeEntry;
458	uint64_t u64TimeSwitch;
459	uint64_t cResume;
460	uint64_t interPD;
461	uint64_t pSwitcher;
462	uint32_t uPos;
463	uint32_t idCpu;
464	#endif
465	/* CR2 is saved here for EPT syncing. */
466	uint64_t cr2;
467	struct
468	{
469	uint32_t cValidEntries;
470	uint32_t uAlignment;
471	uint32_t aField[VMCSCACHE_MAX_ENTRY];
472	uint64_t aFieldVal[VMCSCACHE_MAX_ENTRY];
473	} Write;
474	struct
475	{
476	uint32_t cValidEntries;
477	uint32_t uAlignment;
478	uint32_t aField[VMCSCACHE_MAX_ENTRY];
479	uint64_t aFieldVal[VMCSCACHE_MAX_ENTRY];
480	} Read;
481	#ifdef DEBUG
482	struct
483	{
484	RTHCPHYS pPageCpuPhys;
485	RTHCPHYS pVMCSPhys;
486	RTGCPTR pCache;
487	RTGCPTR pCtx;
488	} TestIn;
489	struct
490	{
491	RTHCPHYS pVMCSPhys;
492	RTGCPTR pCache;
493	RTGCPTR pCtx;
494	uint64_t eflags;
495	uint64_t cr8;
496	} TestOut;
497	struct
498	{
499	uint64_t param1;
500	uint64_t param2;
501	uint64_t param3;
502	uint64_t param4;
503	} ScratchPad;
504	#endif
505	} VMCSCACHE;
506	/** Pointer to VMCSCACHE. */
507	typedef VMCSCACHE *PVMCSCACHE;
508
509	/** VMX StartVM function. */
510	typedef DECLCALLBACK(int) FNHWACCMVMXSTARTVM(RTHCUINT fResume, PCPUMCTX pCtx, PVMCSCACHE pCache, PVM pVM, PVMCPU pVCpu);
511	/** Pointer to a VMX StartVM function. */
512	typedef R0PTRTYPE(FNHWACCMVMXSTARTVM *) PFNHWACCMVMXSTARTVM;
513
514	/** SVM VMRun function. */
515	typedef DECLCALLBACK(int) FNHWACCMSVMVMRUN(RTHCPHYS pVMCBHostPhys, RTHCPHYS pVMCBPhys, PCPUMCTX pCtx, PVM pVM, PVMCPU pVCpu);
516	/** Pointer to a SVM VMRun function. */
517	typedef R0PTRTYPE(FNHWACCMSVMVMRUN *) PFNHWACCMSVMVMRUN;
518
519	/**
520	* HWACCM VMCPU Instance data.
521	*/
522	typedef struct HWACCMCPU
523	{
524	/** Old style FPU reporting trap mask override performed (optimization) */
525	bool fFPUOldStyleOverride;
526
527	/** Set if we don't have to flush the TLB on VM entry. */
528	bool fResumeVM;
529
530	/** Set if we need to flush the TLB during the world switch. */
531	bool fForceTLBFlush;
532
533	/** Set when we're using VT-x or AMD-V at that moment. */
534	bool fActive;
535
536	/** HWACCM_CHANGED_* flags. */
537	RTUINT fContextUseFlags;
538
539	/* Id of the last cpu we were executing code on (NIL_RTCPUID for the first time) */
540	RTCPUID idLastCpu;
541
542	/* TLB flush count */
543	RTUINT cTLBFlushes;
544
545	/* Current ASID in use by the VM */
546	RTUINT uCurrentASID;
547
548	struct
549	{
550	/** R0 memory object for the VM control structure (VMCS). */
551	RTR0MEMOBJ pMemObjVMCS;
552	/** Physical address of the VM control structure (VMCS). */
553	RTHCPHYS pVMCSPhys;
554	/** Virtual address of the VM control structure (VMCS). */
555	R0PTRTYPE(void *) pVMCS;
556
557	/** Ring 0 handlers for VT-x. */
558	PFNHWACCMVMXSTARTVM pfnStartVM;
559
560	/** Current VMX_VMCS_CTRL_PROC_EXEC_CONTROLS. */
561	uint64_t proc_ctls;
562
563	/** Current VMX_VMCS_CTRL_PROC_EXEC2_CONTROLS. */
564	uint64_t proc_ctls2;
565
566	/** R0 memory object for the virtual APIC page for TPR caching. */
567	RTR0MEMOBJ pMemObjVAPIC;
568	/** Physical address of the virtual APIC page for TPR caching. */
569	RTHCPHYS pVAPICPhys;
570	/** Virtual address of the virtual APIC page for TPR caching. */
571	R0PTRTYPE(uint8_t *) pVAPIC;
572
573	/** Current CR0 mask. */
574	uint64_t cr0_mask;
575	/** Current CR4 mask. */
576	uint64_t cr4_mask;
577
578	/** Current EPTP. */
579	RTHCPHYS GCPhysEPTP;
580
581	/** R0 memory object for the MSR bitmap (1 page). */
582	RTR0MEMOBJ pMemObjMSRBitmap;
583	/** Physical address of the MSR bitmap (1 page). */
584	RTHCPHYS pMSRBitmapPhys;
585	/** Virtual address of the MSR bitmap (1 page). */
586	R0PTRTYPE(uint8_t *) pMSRBitmap;
587
588	/** R0 memory object for the guest MSR load area (1 page). */
589	RTR0MEMOBJ pMemObjGuestMSR;
590	/** Physical address of the guest MSR load area (1 page). */
591	RTHCPHYS pGuestMSRPhys;
592	/** Virtual address of the guest MSR load area (1 page). */
593	R0PTRTYPE(uint8_t *) pGuestMSR;
594
595	/** R0 memory object for the MSR load area (1 page). */
596	RTR0MEMOBJ pMemObjHostMSR;
597	/** Physical address of the MSR load area (1 page). */
598	RTHCPHYS pHostMSRPhys;
599	/** Virtual address of the MSR load area (1 page). */
600	R0PTRTYPE(uint8_t *) pHostMSR;
601
602	/** VMCS cache. */
603	VMCSCACHE VMCSCache;
604
605	/** Real-mode emulation state. */
606	struct
607	{
608	X86EFLAGS eflags;
609	uint32_t fValid;
610	} RealMode;
611
612	struct
613	{
614	uint64_t u64VMCSPhys;
615	uint32_t ulVMCSRevision;
616	uint32_t ulInstrError;
617	uint32_t ulExitReason;
618	RTCPUID idEnteredCpu;
619	RTCPUID idCurrentCpu;
620	uint32_t padding;
621	} lasterror;
622
623	/** The last seen guest paging mode (by VT-x). */
624	PGMMODE enmLastSeenGuestMode;
625	/** Current guest paging mode (as seen by HWACCMR3PagingModeChanged). */
626	PGMMODE enmCurrGuestMode;
627	/** Previous guest paging mode (as seen by HWACCMR3PagingModeChanged). */
628	PGMMODE enmPrevGuestMode;
629	} vmx;
630
631	struct
632	{
633	/** R0 memory object for the host VM control block (VMCB). */
634	RTR0MEMOBJ pMemObjVMCBHost;
635	/** Physical address of the host VM control block (VMCB). */
636	RTHCPHYS pVMCBHostPhys;
637	/** Virtual address of the host VM control block (VMCB). */
638	R0PTRTYPE(void *) pVMCBHost;
639
640	/** R0 memory object for the VM control block (VMCB). */
641	RTR0MEMOBJ pMemObjVMCB;
642	/** Physical address of the VM control block (VMCB). */
643	RTHCPHYS pVMCBPhys;
644	/** Virtual address of the VM control block (VMCB). */
645	R0PTRTYPE(void *) pVMCB;
646
647	/** Ring 0 handlers for VT-x. */
648	PFNHWACCMSVMVMRUN pfnVMRun;
649
650	/** R0 memory object for the MSR bitmap (8kb). */
651	RTR0MEMOBJ pMemObjMSRBitmap;
652	/** Physical address of the MSR bitmap (8kb). */
653	RTHCPHYS pMSRBitmapPhys;
654	/** Virtual address of the MSR bitmap. */
655	R0PTRTYPE(void *) pMSRBitmap;
656	} svm;
657
658	/** Event injection state. */
659	struct
660	{
661	uint32_t fPending;
662	uint32_t errCode;
663	uint64_t intInfo;
664	} Event;
665
666	/** IO Block emulation state. */
667	struct
668	{
669	bool fEnabled;
670	uint8_t u8Align[7];
671
672	/** RIP at the start of the io code we wish to emulate in the recompiler. */
673	RTGCPTR GCPtrFunctionEip;
674
675	uint64_t cr0;
676	} EmulateIoBlock;
677
678	struct
679	{
680	/* Pending IO operation type. */
681	HWACCMPENDINGIO enmType;
682	uint32_t uPadding;
683	RTGCPTR GCPtrRip;
684	RTGCPTR GCPtrRipNext;
685	union
686	{
687	struct
688	{
689	unsigned uPort;
690	unsigned uAndVal;
691	unsigned cbSize;
692	} Port;
693	uint64_t aRaw[2];
694	} s;
695	} PendingIO;
696
697	/** Currenty shadow paging mode. */
698	PGMMODE enmShadowMode;
699
700	/** The CPU ID of the CPU currently owning the VMCS. Set in
701	* HWACCMR0Enter and cleared in HWACCMR0Leave. */
702	RTCPUID idEnteredCpu;
703
704	/** To keep track of pending TLB shootdown pages. (SMP guest only) */
705	struct
706	{
707	RTGCPTR aPages[HWACCM_MAX_TLB_SHOOTDOWN_PAGES];
708	unsigned cPages;
709	} TlbShootdown;
710
711	/** For saving stack space, the disassembler state is allocated here instead of
712	* on the stack.
713	* @note The DISCPUSTATE structure is not R3/R0/RZ clean! */
714	union
715	{
716	/** The disassembler scratch space. */
717	DISCPUSTATE DisState;
718	/** Padding. */
719	uint8_t abDisStatePadding[DISCPUSTATE_PADDING_SIZE];
720	};
721
722	RTUINT padding2[1];
723
724	STAMPROFILEADV StatEntry;
725	STAMPROFILEADV StatExit1;
726	STAMPROFILEADV StatExit2;
727	#if 1 /* temporary for tracking down darwin issues. */
728	STAMPROFILEADV StatExit2Sub1;
729	STAMPROFILEADV StatExit2Sub2;
730	STAMPROFILEADV StatExit2Sub3;
731	#endif
732	STAMPROFILEADV StatInGC;
733
734	#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
735	STAMPROFILEADV StatWorldSwitch3264;
736	#endif
737
738	STAMCOUNTER StatIntInject;
739
740	STAMCOUNTER StatExitShadowNM;
741	STAMCOUNTER StatExitGuestNM;
742	STAMCOUNTER StatExitShadowPF;
743	STAMCOUNTER StatExitGuestPF;
744	STAMCOUNTER StatExitGuestUD;
745	STAMCOUNTER StatExitGuestSS;
746	STAMCOUNTER StatExitGuestNP;
747	STAMCOUNTER StatExitGuestGP;
748	STAMCOUNTER StatExitGuestDE;
749	STAMCOUNTER StatExitGuestDB;
750	STAMCOUNTER StatExitGuestMF;
751	STAMCOUNTER StatExitInvpg;
752	STAMCOUNTER StatExitInvd;
753	STAMCOUNTER StatExitCpuid;
754	STAMCOUNTER StatExitRdtsc;
755	STAMCOUNTER StatExitRdpmc;
756	STAMCOUNTER StatExitCli;
757	STAMCOUNTER StatExitSti;
758	STAMCOUNTER StatExitPushf;
759	STAMCOUNTER StatExitPopf;
760	STAMCOUNTER StatExitIret;
761	STAMCOUNTER StatExitInt;
762	STAMCOUNTER StatExitCRxWrite[16];
763	STAMCOUNTER StatExitCRxRead[16];
764	STAMCOUNTER StatExitDRxWrite;
765	STAMCOUNTER StatExitDRxRead;
766	STAMCOUNTER StatExitRdmsr;
767	STAMCOUNTER StatExitWrmsr;
768	STAMCOUNTER StatExitCLTS;
769	STAMCOUNTER StatExitHlt;
770	STAMCOUNTER StatExitMwait;
771	STAMCOUNTER StatExitLMSW;
772	STAMCOUNTER StatExitIOWrite;
773	STAMCOUNTER StatExitIORead;
774	STAMCOUNTER StatExitIOStringWrite;
775	STAMCOUNTER StatExitIOStringRead;
776	STAMCOUNTER StatExitIrqWindow;
777	STAMCOUNTER StatExitMaxResume;
778	STAMCOUNTER StatExitPreemptPending;
779	STAMCOUNTER StatIntReinject;
780	STAMCOUNTER StatPendingHostIrq;
781
782	STAMCOUNTER StatFlushPageManual;
783	STAMCOUNTER StatFlushPhysPageManual;
784	STAMCOUNTER StatFlushTLBManual;
785	STAMCOUNTER StatFlushPageInvlpg;
786	STAMCOUNTER StatFlushTLBWorldSwitch;
787	STAMCOUNTER StatNoFlushTLBWorldSwitch;
788	STAMCOUNTER StatFlushTLBCRxChange;
789	STAMCOUNTER StatFlushASID;
790	STAMCOUNTER StatFlushTLBInvlpga;
791	STAMCOUNTER StatTlbShootdown;
792	STAMCOUNTER StatTlbShootdownFlush;
793
794	STAMCOUNTER StatSwitchGuestIrq;
795	STAMCOUNTER StatSwitchToR3;
796
797	STAMCOUNTER StatTSCOffset;
798	STAMCOUNTER StatTSCIntercept;
799
800	STAMCOUNTER StatExitReasonNPF;
801	STAMCOUNTER StatDRxArmed;
802	STAMCOUNTER StatDRxContextSwitch;
803	STAMCOUNTER StatDRxIOCheck;
804
805
806	#ifdef VBOX_WITH_STATISTICS
807	R3PTRTYPE(PSTAMCOUNTER) paStatExitReason;
808	R0PTRTYPE(PSTAMCOUNTER) paStatExitReasonR0;
809	R3PTRTYPE(PSTAMCOUNTER) paStatInjectedIrqs;
810	R0PTRTYPE(PSTAMCOUNTER) paStatInjectedIrqsR0;
811	#endif
812	} HWACCMCPU;
813	/** Pointer to HWACCM VM instance data. */
814	typedef HWACCMCPU *PHWACCMCPU;
815
816
817	#ifdef IN_RING0
818
819	VMMR0DECL(PHWACCM_CPUINFO) HWACCMR0GetCurrentCpu();
820	VMMR0DECL(PHWACCM_CPUINFO) HWACCMR0GetCurrentCpuEx(RTCPUID idCpu);
821
822
823	#ifdef VBOX_STRICT
824	VMMR0DECL(void) HWACCMDumpRegs(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
825	VMMR0DECL(void) HWACCMR0DumpDescriptor(PX86DESCHC Desc, RTSEL Sel, const char *pszMsg);
826	#else
827	#define HWACCMDumpRegs(a, b ,c) do { } while (0)
828	#define HWACCMR0DumpDescriptor(a, b, c) do { } while (0)
829	#endif
830
831	/* Dummy callback handlers. */
832	VMMR0DECL(int) HWACCMR0DummyEnter(PVM pVM, PVMCPU pVCpu, PHWACCM_CPUINFO pCpu);
833	VMMR0DECL(int) HWACCMR0DummyLeave(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
834	VMMR0DECL(int) HWACCMR0DummyEnableCpu(PHWACCM_CPUINFO pCpu, PVM pVM, void *pvPageCpu, RTHCPHYS pPageCpuPhys);
835	VMMR0DECL(int) HWACCMR0DummyDisableCpu(PHWACCM_CPUINFO pCpu, void *pvPageCpu, RTHCPHYS pPageCpuPhys);
836	VMMR0DECL(int) HWACCMR0DummyInitVM(PVM pVM);
837	VMMR0DECL(int) HWACCMR0DummyTermVM(PVM pVM);
838	VMMR0DECL(int) HWACCMR0DummySetupVM(PVM pVM);
839	VMMR0DECL(int) HWACCMR0DummyRunGuestCode(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
840	VMMR0DECL(int) HWACCMR0DummySaveHostState(PVM pVM, PVMCPU pVCpu);
841	VMMR0DECL(int) HWACCMR0DummyLoadGuestState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
842
843	# ifdef VBOX_WITH_KERNEL_USING_XMM
844	DECLASM(int) hwaccmR0VMXStartVMWrapXMM(RTHCUINT fResume, PCPUMCTX pCtx, PVMCSCACHE pCache, PVM pVM, PVMCPU pVCpu, PFNHWACCMVMXSTARTVM pfnStartVM);
845	DECLASM(int) hwaccmR0SVMRunWrapXMM(RTHCPHYS pVMCBHostPhys, RTHCPHYS pVMCBPhys, PCPUMCTX pCtx, PVM pVM, PVMCPU pVCpu, PFNHWACCMSVMVMRUN pfnVMRun);
846	# endif
847
848	# ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
849	/**
850	* Gets 64-bit GDTR and IDTR on darwin.
851	* @param pGdtr Where to store the 64-bit GDTR.
852	* @param pIdtr Where to store the 64-bit IDTR.
853	*/
854	DECLASM(void) hwaccmR0Get64bitGDTRandIDTR(PX86XDTR64 pGdtr, PX86XDTR64 pIdtr);
855
856	/**
857	* Gets 64-bit CR3 on darwin.
858	* @returns CR3
859	*/
860	DECLASM(uint64_t) hwaccmR0Get64bitCR3(void);
861	# endif
862
863	#endif /* IN_RING0 */
864
865	/** @} */
866
867	RT_C_DECLS_END
868
869	#endif
870

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source: vbox/trunk/src/VBox/VMM/HWACCMInternal.h@ 22041

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