HWACCMInternal.h@ 24760

Last change on this file since 24760 was 24243, checked in by vboxsync, 15 years ago
TPR patching for VT-x without VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC. Untested.
Property svn:eol-style set to `native` Property svn:keywords set to `Id`
File size: 32.7 KB

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1	/* $Id: HWACCMInternal.h 24243 2009-11-02 10:24:15Z vboxsync $ */
2	/** @file
3	* HWACCM - Internal header file.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22	#ifndef ___HWACCMInternal_h
23	#define ___HWACCMInternal_h
24
25	#include <VBox/cdefs.h>
26	#include <VBox/types.h>
27	#include <VBox/em.h>
28	#include <VBox/stam.h>
29	#include <VBox/dis.h>
30	#include <VBox/hwaccm.h>
31	#include <VBox/pgm.h>
32	#include <VBox/cpum.h>
33	#include <iprt/memobj.h>
34	#include <iprt/cpuset.h>
35	#include <iprt/mp.h>
36	#include <iprt/avl.h>
37
38	#if HC_ARCH_BITS == 64 \|\| defined(VBOX_WITH_HYBRID_32BIT_KERNEL) \|\| defined (VBOX_WITH_64_BITS_GUESTS)
39	/* Enable 64 bits guest support. */
40	# define VBOX_ENABLE_64_BITS_GUESTS
41	#endif
42
43	#define VMX_USE_CACHED_VMCS_ACCESSES
44	#define HWACCM_VMX_EMULATE_REALMODE
45	#define HWACCM_VTX_WITH_EPT
46	#define HWACCM_VTX_WITH_VPID
47
48
49	#if 0
50	/* Seeing somewhat random behaviour on my Nehalem system with auto-save of guest MSRs;
51	* for some strange reason the CPU doesn't save the MSRs during the VM-exit.
52	* Clearly visible with a dual VCPU configured OpenSolaris 200906 live cd VM.
53	*
54	* Note: change the assembly files when enabling this! (remove the manual auto load/save)
55	*/
56	#define VBOX_WITH_AUTO_MSR_LOAD_RESTORE
57	#endif
58
59	RT_C_DECLS_BEGIN
60
61
62	/** @defgroup grp_hwaccm_int Internal
63	* @ingroup grp_hwaccm
64	* @internal
65	* @{
66	*/
67
68
69	/** Maximum number of exit reason statistics counters. */
70	#define MAX_EXITREASON_STAT 0x100
71	#define MASK_EXITREASON_STAT 0xff
72	#define MASK_INJECT_IRQ_STAT 0xff
73
74	/** @name Changed flags
75	* These flags are used to keep track of which important registers that
76	* have been changed since last they were reset.
77	* @{
78	*/
79	#define HWACCM_CHANGED_GUEST_FPU RT_BIT(0)
80	#define HWACCM_CHANGED_GUEST_CR0 RT_BIT(1)
81	#define HWACCM_CHANGED_GUEST_CR3 RT_BIT(2)
82	#define HWACCM_CHANGED_GUEST_CR4 RT_BIT(3)
83	#define HWACCM_CHANGED_GUEST_GDTR RT_BIT(4)
84	#define HWACCM_CHANGED_GUEST_IDTR RT_BIT(5)
85	#define HWACCM_CHANGED_GUEST_LDTR RT_BIT(6)
86	#define HWACCM_CHANGED_GUEST_TR RT_BIT(7)
87	#define HWACCM_CHANGED_GUEST_SYSENTER_MSR RT_BIT(8)
88	#define HWACCM_CHANGED_GUEST_SEGMENT_REGS RT_BIT(9)
89	#define HWACCM_CHANGED_GUEST_DEBUG RT_BIT(10)
90	#define HWACCM_CHANGED_HOST_CONTEXT RT_BIT(11)
91
92	#define HWACCM_CHANGED_ALL ( HWACCM_CHANGED_GUEST_SEGMENT_REGS \
93	\| HWACCM_CHANGED_GUEST_CR0 \
94	\| HWACCM_CHANGED_GUEST_CR3 \
95	\| HWACCM_CHANGED_GUEST_CR4 \
96	\| HWACCM_CHANGED_GUEST_GDTR \
97	\| HWACCM_CHANGED_GUEST_IDTR \
98	\| HWACCM_CHANGED_GUEST_LDTR \
99	\| HWACCM_CHANGED_GUEST_TR \
100	\| HWACCM_CHANGED_GUEST_SYSENTER_MSR \
101	\| HWACCM_CHANGED_GUEST_FPU \
102	\| HWACCM_CHANGED_GUEST_DEBUG \
103	\| HWACCM_CHANGED_HOST_CONTEXT)
104
105	#define HWACCM_CHANGED_ALL_GUEST ( HWACCM_CHANGED_GUEST_SEGMENT_REGS \
106	\| HWACCM_CHANGED_GUEST_CR0 \
107	\| HWACCM_CHANGED_GUEST_CR3 \
108	\| HWACCM_CHANGED_GUEST_CR4 \
109	\| HWACCM_CHANGED_GUEST_GDTR \
110	\| HWACCM_CHANGED_GUEST_IDTR \
111	\| HWACCM_CHANGED_GUEST_LDTR \
112	\| HWACCM_CHANGED_GUEST_TR \
113	\| HWACCM_CHANGED_GUEST_SYSENTER_MSR \
114	\| HWACCM_CHANGED_GUEST_DEBUG \
115	\| HWACCM_CHANGED_GUEST_FPU)
116
117	/** @} */
118
119	/** @name Intercepted traps
120	* Traps that need to be intercepted so we can correctly dispatch them to the guest if required.
121	* Currently #NM and #PF only
122	*/
123	#ifdef VBOX_STRICT
124	#define HWACCM_VMX_TRAP_MASK RT_BIT(X86_XCPT_DE) \| RT_BIT(X86_XCPT_NM) \| RT_BIT(X86_XCPT_PF) \| RT_BIT(X86_XCPT_UD) \| RT_BIT(X86_XCPT_NP) \| RT_BIT(X86_XCPT_SS) \| RT_BIT(X86_XCPT_GP) \| RT_BIT(X86_XCPT_MF)
125	#define HWACCM_SVM_TRAP_MASK HWACCM_VMX_TRAP_MASK
126	#else
127	#define HWACCM_VMX_TRAP_MASK RT_BIT(X86_XCPT_NM) \| RT_BIT(X86_XCPT_PF)
128	#define HWACCM_SVM_TRAP_MASK RT_BIT(X86_XCPT_NM) \| RT_BIT(X86_XCPT_PF)
129	#endif
130	/* All exceptions have to be intercept in emulated real-mode (minues NM & PF as they are always intercepted. */
131	#define HWACCM_VMX_TRAP_MASK_REALMODE RT_BIT(X86_XCPT_DE) \| RT_BIT(X86_XCPT_DB) \| RT_BIT(X86_XCPT_NMI) \| RT_BIT(X86_XCPT_BP) \| RT_BIT(X86_XCPT_OF) \| RT_BIT(X86_XCPT_BR) \| RT_BIT(X86_XCPT_UD) \| RT_BIT(X86_XCPT_DF) \| RT_BIT(X86_XCPT_CO_SEG_OVERRUN) \| RT_BIT(X86_XCPT_TS) \| RT_BIT(X86_XCPT_NP) \| RT_BIT(X86_XCPT_SS) \| RT_BIT(X86_XCPT_GP) \| RT_BIT(X86_XCPT_MF) \| RT_BIT(X86_XCPT_AC) \| RT_BIT(X86_XCPT_MC) \| RT_BIT(X86_XCPT_XF)
132	/** @} */
133
134
135	/** Maximum number of page flushes we are willing to remember before considering a full TLB flush. */
136	#define HWACCM_MAX_TLB_SHOOTDOWN_PAGES 8
137
138	/** Size for the EPT identity page table (1024 4 MB pages to cover the entire address space). */
139	#define HWACCM_EPT_IDENTITY_PG_TABLE_SIZE PAGE_SIZE
140	/** Size of the TSS structure + 2 pages for the IO bitmap + end byte. */
141	#define HWACCM_VTX_TSS_SIZE (sizeof(VBOXTSS) + 2*PAGE_SIZE + 1)
142	/** Total guest mapped memory needed. */
143	#define HWACCM_VTX_TOTAL_DEVHEAP_MEM (HWACCM_EPT_IDENTITY_PG_TABLE_SIZE + HWACCM_VTX_TSS_SIZE)
144
145	/* Enable for TPR guest patching. */
146	#define VBOX_HWACCM_WITH_GUEST_PATCHING
147
148	/** HWACCM SSM version
149	*/
150	#ifdef VBOX_HWACCM_WITH_GUEST_PATCHING
151	#define HWACCM_SSM_VERSION 5
152	#define HWACCM_SSM_VERSION_NO_PATCHING 4
153	#else
154	#define HWACCM_SSM_VERSION 4
155	#define HWACCM_SSM_VERSION_NO_PATCHING 4
156	#endif
157	#define HWACCM_SSM_VERSION_2_0_X 3
158
159	/* Per-cpu information. (host) */
160	typedef struct
161	{
162	RTCPUID idCpu;
163
164	RTR0MEMOBJ pMemObj;
165	/* Current ASID (AMD-V)/VPID (Intel) */
166	uint32_t uCurrentASID;
167	/* TLB flush count */
168	uint32_t cTLBFlushes;
169
170	/* Set the first time a cpu is used to make sure we start with a clean TLB. */
171	bool fFlushTLB;
172
173	/** Configured for VT-x or AMD-V. */
174	bool fConfigured;
175
176	/** In use by our code. (for power suspend) */
177	volatile bool fInUse;
178	} HWACCM_CPUINFO;
179	typedef HWACCM_CPUINFO *PHWACCM_CPUINFO;
180
181	typedef enum
182	{
183	HWACCMPENDINGIO_INVALID = 0,
184	HWACCMPENDINGIO_PORT_READ,
185	HWACCMPENDINGIO_PORT_WRITE,
186	HWACCMPENDINGIO_STRING_READ,
187	HWACCMPENDINGIO_STRING_WRITE,
188	/** The usual 32-bit paranoia. */
189	HWACCMPENDINGIO_32BIT_HACK = 0x7fffffff
190	} HWACCMPENDINGIO;
191
192
193	typedef enum
194	{
195	HWACCMTPRINSTR_INVALID,
196	HWACCMTPRINSTR_READ,
197	HWACCMTPRINSTR_READ_SHR4,
198	HWACCMTPRINSTR_WRITE_REG,
199	HWACCMTPRINSTR_WRITE_IMM,
200	HWACCMTPRINSTR_JUMP_REPLACEMENT,
201	/** The usual 32-bit paranoia. */
202	HWACCMTPRINSTR_32BIT_HACK = 0x7fffffff
203	} HWACCMTPRINSTR;
204
205	typedef struct
206	{
207	/** The key is the address of patched instruction. (32 bits GC ptr) */
208	AVLOU32NODECORE Core;
209	/** Original opcode. */
210	uint8_t aOpcode[16];
211	/** Instruction size. */
212	uint32_t cbOp;
213	/** Replacement opcode. */
214	uint8_t aNewOpcode[16];
215	/** Replacement instruction size. */
216	uint32_t cbNewOp;
217	/** Instruction type. */
218	HWACCMTPRINSTR enmType;
219	/** Source operand. */
220	uint32_t uSrcOperand;
221	/** Destination operand. */
222	uint32_t uDstOperand;
223	/** Number of times the instruction caused a fault. */
224	uint32_t cFaults;
225	/** Patch address of the jump replacement. */
226	RTGCPTR32 pJumpTarget;
227	} HWACCMTPRPATCH;
228	/** Pointer to HWACCMTPRPATCH. */
229	typedef HWACCMTPRPATCH *PHWACCMTPRPATCH;
230
231	/**
232	* Switcher function, HC to RC.
233	*
234	* @param pVM The VM handle.
235	* @returns Return code indicating the action to take.
236	*/
237	typedef DECLASMTYPE(int) FNHWACCMSWITCHERHC(PVM pVM);
238	/** Pointer to switcher function. */
239	typedef FNHWACCMSWITCHERHC *PFNHWACCMSWITCHERHC;
240
241	/**
242	* HWACCM VM Instance data.
243	* Changes to this must checked against the padding of the cfgm union in VM!
244	*/
245	typedef struct HWACCM
246	{
247	/** Set when we've initialized VMX or SVM. */
248	bool fInitialized;
249
250	/** Set when hardware acceleration is allowed. */
251	bool fAllowed;
252
253	/** Set if nested paging is enabled. */
254	bool fNestedPaging;
255
256	/** Set if nested paging is allowed. */
257	bool fAllowNestedPaging;
258
259	/** Set if we can support 64-bit guests or not. */
260	bool fAllow64BitGuests;
261
262	/** Set if an IO-APIC is configured for this VM. */
263	bool fHasIoApic;
264
265	/** Set when TPR patching is allowed. */
266	bool fTRPPatchingAllowed;
267
268	/** Set when we initialize VT-x or AMD-V once for all CPUs. */
269	bool fGlobalInit;
270
271	/** Set when TPR patching is active. */
272	bool fTPRPatchingActive;
273	bool u8Alignment[7];
274
275	/** And mask for copying register contents. */
276	uint64_t u64RegisterMask;
277
278	/** Maximum ASID allowed. */
279	RTUINT uMaxASID;
280
281	/** The maximum number of resumes loops allowed in ring-0 (safety precaution).
282	* This number is set much higher when RTThreadPreemptIsPending is reliable. */
283	uint32_t cMaxResumeLoops;
284
285	/** Guest allocated memory for patching purposes. */
286	RTGCPTR pGuestPatchMem;
287	/** Current free pointer inside the patch block. */
288	RTGCPTR pFreeGuestPatchMem;
289	/** Size of the guest patch memory block. */
290	uint32_t cbGuestPatchMem;
291	uint32_t uPadding1;
292
293	#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
294	/** 32 to 64 bits switcher entrypoint. */
295	R0PTRTYPE(PFNHWACCMSWITCHERHC) pfnHost32ToGuest64R0;
296
297	/* AMD-V 64 bits vmrun handler */
298	RTRCPTR pfnSVMGCVMRun64;
299
300	/* VT-x 64 bits vmlaunch handler */
301	RTRCPTR pfnVMXGCStartVM64;
302
303	/* RC handler to setup the 64 bits FPU state. */
304	RTRCPTR pfnSaveGuestFPU64;
305
306	/* RC handler to setup the 64 bits debug state. */
307	RTRCPTR pfnSaveGuestDebug64;
308
309	/* Test handler */
310	RTRCPTR pfnTest64;
311
312	RTRCPTR uAlignment[2];
313	/*#elif defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
314	uint32_t u32Alignment[1]; */
315	#endif
316
317	struct
318	{
319	/** Set by the ring-0 driver to indicate VMX is supported by the CPU. */
320	bool fSupported;
321
322	/** Set when we've enabled VMX. */
323	bool fEnabled;
324
325	/** Set if VPID is supported. */
326	bool fVPID;
327
328	/** Set if VT-x VPID is allowed. */
329	bool fAllowVPID;
330
331	/** Virtual address of the TSS page used for real mode emulation. */
332	R3PTRTYPE(PVBOXTSS) pRealModeTSS;
333
334	/** Virtual address of the identity page table used for real mode and protected mode without paging emulation in EPT mode. */
335	R3PTRTYPE(PX86PD) pNonPagingModeEPTPageTable;
336
337	/** R0 memory object for the APIC physical page (serves for filtering accesses). */
338	RTR0MEMOBJ pMemObjAPIC;
339	/** Physical address of the APIC physical page (serves for filtering accesses). */
340	RTHCPHYS pAPICPhys;
341	/** Virtual address of the APIC physical page (serves for filtering accesses). */
342	R0PTRTYPE(uint8_t *) pAPIC;
343
344	/** R0 memory object for the MSR entry load page (guest MSRs). */
345	RTR0MEMOBJ pMemObjMSREntryLoad;
346	/** Physical address of the MSR entry load page (guest MSRs). */
347	RTHCPHYS pMSREntryLoadPhys;
348	/** Virtual address of the MSR entry load page (guest MSRs). */
349	R0PTRTYPE(uint8_t *) pMSREntryLoad;
350
351	#ifdef VBOX_WITH_CRASHDUMP_MAGIC
352	RTR0MEMOBJ pMemObjScratch;
353	RTHCPHYS pScratchPhys;
354	R0PTRTYPE(uint8_t *) pScratch;
355	#endif
356	/** R0 memory object for the MSR exit store page (guest MSRs). */
357	RTR0MEMOBJ pMemObjMSRExitStore;
358	/** Physical address of the MSR exit store page (guest MSRs). */
359	RTHCPHYS pMSRExitStorePhys;
360	/** Virtual address of the MSR exit store page (guest MSRs). */
361	R0PTRTYPE(uint8_t *) pMSRExitStore;
362
363	/** R0 memory object for the MSR exit load page (host MSRs). */
364	RTR0MEMOBJ pMemObjMSRExitLoad;
365	/** Physical address of the MSR exit load page (host MSRs). */
366	RTHCPHYS pMSRExitLoadPhys;
367	/** Virtual address of the MSR exit load page (host MSRs). */
368	R0PTRTYPE(uint8_t *) pMSRExitLoad;
369
370	/** Ring 0 handlers for VT-x. */
371	DECLR0CALLBACKMEMBER(void, pfnSetupTaggedTLB, (PVM pVM, PVMCPU pVCpu));
372
373	/** Host CR4 value (set by ring-0 VMX init) */
374	uint64_t hostCR4;
375
376	/** VMX MSR values */
377	struct
378	{
379	uint64_t feature_ctrl;
380	uint64_t vmx_basic_info;
381	VMX_CAPABILITY vmx_pin_ctls;
382	VMX_CAPABILITY vmx_proc_ctls;
383	VMX_CAPABILITY vmx_proc_ctls2;
384	VMX_CAPABILITY vmx_exit;
385	VMX_CAPABILITY vmx_entry;
386	uint64_t vmx_misc;
387	uint64_t vmx_cr0_fixed0;
388	uint64_t vmx_cr0_fixed1;
389	uint64_t vmx_cr4_fixed0;
390	uint64_t vmx_cr4_fixed1;
391	uint64_t vmx_vmcs_enum;
392	uint64_t vmx_eptcaps;
393	} msr;
394
395	/** Flush types for invept & invvpid; they depend on capabilities. */
396	VMX_FLUSH enmFlushPage;
397	VMX_FLUSH enmFlushContext;
398	} vmx;
399
400	struct
401	{
402	/** Set by the ring-0 driver to indicate SVM is supported by the CPU. */
403	bool fSupported;
404	/** Set when we've enabled SVM. */
405	bool fEnabled;
406	/** Set if erratum 170 affects the AMD cpu. */
407	bool fAlwaysFlushTLB;
408	bool u8Alignment;
409
410	/** R0 memory object for the IO bitmap (12kb). */
411	RTR0MEMOBJ pMemObjIOBitmap;
412	/** Physical address of the IO bitmap (12kb). */
413	RTHCPHYS pIOBitmapPhys;
414	/** Virtual address of the IO bitmap. */
415	R0PTRTYPE(void *) pIOBitmap;
416
417	/** SVM revision. */
418	uint32_t u32Rev;
419
420	/** SVM feature bits from cpuid 0x8000000a */
421	uint32_t u32Features;
422	} svm;
423
424	/**
425	* AVL tree with all patches (active or disabled) sorted by guest instruction address
426	*/
427	AVLOU32TREE PatchTree;
428	uint32_t cPatches;
429	HWACCMTPRPATCH aPatches[64];
430
431	struct
432	{
433	uint32_t u32AMDFeatureECX;
434	uint32_t u32AMDFeatureEDX;
435	} cpuid;
436
437	/** Saved error from detection */
438	int32_t lLastError;
439
440	/** HWACCMR0Init was run */
441	bool fHWACCMR0Init;
442	bool u8Alignment1[7];
443
444	STAMCOUNTER StatTPRPatchSuccess;
445	STAMCOUNTER StatTPRPatchFailure;
446	STAMCOUNTER StatTPRReplaceSuccess;
447	STAMCOUNTER StatTPRReplaceFailure;
448	} HWACCM;
449	/** Pointer to HWACCM VM instance data. */
450	typedef HWACCM *PHWACCM;
451
452	/* Maximum number of cached entries. */
453	#define VMCSCACHE_MAX_ENTRY 128
454
455	/* Structure for storing read and write VMCS actions. */
456	typedef struct VMCSCACHE
457	{
458	#ifdef VBOX_WITH_CRASHDUMP_MAGIC
459	/* Magic marker for searching in crash dumps. */
460	uint8_t aMagic[16];
461	uint64_t uMagic;
462	uint64_t u64TimeEntry;
463	uint64_t u64TimeSwitch;
464	uint64_t cResume;
465	uint64_t interPD;
466	uint64_t pSwitcher;
467	uint32_t uPos;
468	uint32_t idCpu;
469	#endif
470	/* CR2 is saved here for EPT syncing. */
471	uint64_t cr2;
472	struct
473	{
474	uint32_t cValidEntries;
475	uint32_t uAlignment;
476	uint32_t aField[VMCSCACHE_MAX_ENTRY];
477	uint64_t aFieldVal[VMCSCACHE_MAX_ENTRY];
478	} Write;
479	struct
480	{
481	uint32_t cValidEntries;
482	uint32_t uAlignment;
483	uint32_t aField[VMCSCACHE_MAX_ENTRY];
484	uint64_t aFieldVal[VMCSCACHE_MAX_ENTRY];
485	} Read;
486	#ifdef DEBUG
487	struct
488	{
489	RTHCPHYS pPageCpuPhys;
490	RTHCPHYS pVMCSPhys;
491	RTGCPTR pCache;
492	RTGCPTR pCtx;
493	} TestIn;
494	struct
495	{
496	RTHCPHYS pVMCSPhys;
497	RTGCPTR pCache;
498	RTGCPTR pCtx;
499	uint64_t eflags;
500	uint64_t cr8;
501	} TestOut;
502	struct
503	{
504	uint64_t param1;
505	uint64_t param2;
506	uint64_t param3;
507	uint64_t param4;
508	} ScratchPad;
509	#endif
510	} VMCSCACHE;
511	/** Pointer to VMCSCACHE. */
512	typedef VMCSCACHE *PVMCSCACHE;
513
514	/** VMX StartVM function. */
515	typedef DECLCALLBACK(int) FNHWACCMVMXSTARTVM(RTHCUINT fResume, PCPUMCTX pCtx, PVMCSCACHE pCache, PVM pVM, PVMCPU pVCpu);
516	/** Pointer to a VMX StartVM function. */
517	typedef R0PTRTYPE(FNHWACCMVMXSTARTVM *) PFNHWACCMVMXSTARTVM;
518
519	/** SVM VMRun function. */
520	typedef DECLCALLBACK(int) FNHWACCMSVMVMRUN(RTHCPHYS pVMCBHostPhys, RTHCPHYS pVMCBPhys, PCPUMCTX pCtx, PVM pVM, PVMCPU pVCpu);
521	/** Pointer to a SVM VMRun function. */
522	typedef R0PTRTYPE(FNHWACCMSVMVMRUN *) PFNHWACCMSVMVMRUN;
523
524	/**
525	* HWACCM VMCPU Instance data.
526	*/
527	typedef struct HWACCMCPU
528	{
529	/** Old style FPU reporting trap mask override performed (optimization) */
530	bool fFPUOldStyleOverride;
531
532	/** Set if we don't have to flush the TLB on VM entry. */
533	bool fResumeVM;
534
535	/** Set if we need to flush the TLB during the world switch. */
536	bool fForceTLBFlush;
537
538	/** Set when we're using VT-x or AMD-V at that moment. */
539	bool fActive;
540
541	/** Set when the TLB has been checked until we return from the world switch. */
542	volatile uint8_t fCheckedTLBFlush;
543	uint8_t bAlignment[3];
544
545	/** HWACCM_CHANGED_* flags. */
546	RTUINT fContextUseFlags;
547
548	/** Id of the last cpu we were executing code on (NIL_RTCPUID for the first time) */
549	RTCPUID idLastCpu;
550
551	/** TLB flush count */
552	RTUINT cTLBFlushes;
553
554	/** Current ASID in use by the VM */
555	RTUINT uCurrentASID;
556
557	/** World switch exit counter. */
558	volatile uint32_t cWorldSwitchExit;
559	uint32_t u32Alignment;
560
561	struct
562	{
563	/** Physical address of the VM control structure (VMCS). */
564	RTHCPHYS pVMCSPhys;
565	/** R0 memory object for the VM control structure (VMCS). */
566	RTR0MEMOBJ pMemObjVMCS;
567	/** Virtual address of the VM control structure (VMCS). */
568	R0PTRTYPE(void *) pVMCS;
569
570	/** Ring 0 handlers for VT-x. */
571	PFNHWACCMVMXSTARTVM pfnStartVM;
572
573	#if HC_ARCH_BITS == 32
574	uint32_t u32Alignment;
575	#endif
576
577	/** Current VMX_VMCS_CTRL_PROC_EXEC_CONTROLS. */
578	uint64_t proc_ctls;
579
580	/** Current VMX_VMCS_CTRL_PROC_EXEC2_CONTROLS. */
581	uint64_t proc_ctls2;
582
583	/** Physical address of the virtual APIC page for TPR caching. */
584	RTHCPHYS pVAPICPhys;
585	/** R0 memory object for the virtual APIC page for TPR caching. */
586	RTR0MEMOBJ pMemObjVAPIC;
587	/** Virtual address of the virtual APIC page for TPR caching. */
588	R0PTRTYPE(uint8_t *) pVAPIC;
589
590	/** Current CR0 mask. */
591	uint64_t cr0_mask;
592	/** Current CR4 mask. */
593	uint64_t cr4_mask;
594
595	/** Current EPTP. */
596	RTHCPHYS GCPhysEPTP;
597
598	/** Physical address of the MSR bitmap (1 page). */
599	RTHCPHYS pMSRBitmapPhys;
600	/** R0 memory object for the MSR bitmap (1 page). */
601	RTR0MEMOBJ pMemObjMSRBitmap;
602	/** Virtual address of the MSR bitmap (1 page). */
603	R0PTRTYPE(uint8_t *) pMSRBitmap;
604
605	#ifdef VBOX_WITH_AUTO_MSR_LOAD_RESTORE
606	/** Physical address of the guest MSR load area (1 page). */
607	RTHCPHYS pGuestMSRPhys;
608	/** R0 memory object for the guest MSR load area (1 page). */
609	RTR0MEMOBJ pMemObjGuestMSR;
610	/** Virtual address of the guest MSR load area (1 page). */
611	R0PTRTYPE(uint8_t *) pGuestMSR;
612
613	/** Physical address of the MSR load area (1 page). */
614	RTHCPHYS pHostMSRPhys;
615	/** R0 memory object for the MSR load area (1 page). */
616	RTR0MEMOBJ pMemObjHostMSR;
617	/** Virtual address of the MSR load area (1 page). */
618	R0PTRTYPE(uint8_t *) pHostMSR;
619	#endif /* VBOX_WITH_AUTO_MSR_LOAD_RESTORE */
620
621	/* Number of automatically loaded/restored MSRs. */
622	uint32_t cCachedMSRs;
623	uint32_t uAlignement;
624
625	/* Last use TSC offset value. (cached) */
626	uint64_t u64TSCOffset;
627
628	/** VMCS cache. */
629	VMCSCACHE VMCSCache;
630
631	/** Real-mode emulation state. */
632	struct
633	{
634	X86EFLAGS eflags;
635	uint32_t fValid;
636	} RealMode;
637
638	struct
639	{
640	uint64_t u64VMCSPhys;
641	uint32_t ulVMCSRevision;
642	uint32_t ulInstrError;
643	uint32_t ulExitReason;
644	RTCPUID idEnteredCpu;
645	RTCPUID idCurrentCpu;
646	uint32_t padding;
647	} lasterror;
648
649	/** The last seen guest paging mode (by VT-x). */
650	PGMMODE enmLastSeenGuestMode;
651	/** Current guest paging mode (as seen by HWACCMR3PagingModeChanged). */
652	PGMMODE enmCurrGuestMode;
653	/** Previous guest paging mode (as seen by HWACCMR3PagingModeChanged). */
654	PGMMODE enmPrevGuestMode;
655	} vmx;
656
657	struct
658	{
659	/** R0 memory object for the host VM control block (VMCB). */
660	RTR0MEMOBJ pMemObjVMCBHost;
661	/** Physical address of the host VM control block (VMCB). */
662	RTHCPHYS pVMCBHostPhys;
663	/** Virtual address of the host VM control block (VMCB). */
664	R0PTRTYPE(void *) pVMCBHost;
665
666	/** R0 memory object for the VM control block (VMCB). */
667	RTR0MEMOBJ pMemObjVMCB;
668	/** Physical address of the VM control block (VMCB). */
669	RTHCPHYS pVMCBPhys;
670	/** Virtual address of the VM control block (VMCB). */
671	R0PTRTYPE(void *) pVMCB;
672
673	/** Ring 0 handlers for VT-x. */
674	PFNHWACCMSVMVMRUN pfnVMRun;
675
676	/** R0 memory object for the MSR bitmap (8kb). */
677	RTR0MEMOBJ pMemObjMSRBitmap;
678	/** Physical address of the MSR bitmap (8kb). */
679	RTHCPHYS pMSRBitmapPhys;
680	/** Virtual address of the MSR bitmap. */
681	R0PTRTYPE(void *) pMSRBitmap;
682	} svm;
683
684	/** Event injection state. */
685	struct
686	{
687	uint32_t fPending;
688	uint32_t errCode;
689	uint64_t intInfo;
690	} Event;
691
692	/** IO Block emulation state. */
693	struct
694	{
695	bool fEnabled;
696	uint8_t u8Align[7];
697
698	/** RIP at the start of the io code we wish to emulate in the recompiler. */
699	RTGCPTR GCPtrFunctionEip;
700
701	uint64_t cr0;
702	} EmulateIoBlock;
703
704	struct
705	{
706	/* Pending IO operation type. */
707	HWACCMPENDINGIO enmType;
708	uint32_t uPadding;
709	RTGCPTR GCPtrRip;
710	RTGCPTR GCPtrRipNext;
711	union
712	{
713	struct
714	{
715	unsigned uPort;
716	unsigned uAndVal;
717	unsigned cbSize;
718	} Port;
719	uint64_t aRaw[2];
720	} s;
721	} PendingIO;
722
723	/** Currenty shadow paging mode. */
724	PGMMODE enmShadowMode;
725
726	/** The CPU ID of the CPU currently owning the VMCS. Set in
727	* HWACCMR0Enter and cleared in HWACCMR0Leave. */
728	RTCPUID idEnteredCpu;
729
730	/** To keep track of pending TLB shootdown pages. (SMP guest only) */
731	struct
732	{
733	RTGCPTR aPages[HWACCM_MAX_TLB_SHOOTDOWN_PAGES];
734	unsigned cPages;
735	} TlbShootdown;
736
737	/** For saving stack space, the disassembler state is allocated here instead of
738	* on the stack.
739	* @note The DISCPUSTATE structure is not R3/R0/RZ clean! */
740	union
741	{
742	/** The disassembler scratch space. */
743	DISCPUSTATE DisState;
744	/** Padding. */
745	uint8_t abDisStatePadding[DISCPUSTATE_PADDING_SIZE];
746	};
747
748	RTUINT padding2[1];
749
750	STAMPROFILEADV StatEntry;
751	STAMPROFILEADV StatExit1;
752	STAMPROFILEADV StatExit2;
753	#if 1 /* temporary for tracking down darwin issues. */
754	STAMPROFILEADV StatExit2Sub1;
755	STAMPROFILEADV StatExit2Sub2;
756	STAMPROFILEADV StatExit2Sub3;
757	#endif
758	STAMPROFILEADV StatInGC;
759
760	#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
761	STAMPROFILEADV StatWorldSwitch3264;
762	#endif
763	STAMPROFILEADV StatPoke;
764	STAMPROFILEADV StatSpinPoke;
765	STAMPROFILEADV StatSpinPokeFailed;
766
767	STAMCOUNTER StatIntInject;
768
769	STAMCOUNTER StatExitShadowNM;
770	STAMCOUNTER StatExitGuestNM;
771	STAMCOUNTER StatExitShadowPF;
772	STAMCOUNTER StatExitGuestPF;
773	STAMCOUNTER StatExitGuestUD;
774	STAMCOUNTER StatExitGuestSS;
775	STAMCOUNTER StatExitGuestNP;
776	STAMCOUNTER StatExitGuestGP;
777	STAMCOUNTER StatExitGuestDE;
778	STAMCOUNTER StatExitGuestDB;
779	STAMCOUNTER StatExitGuestMF;
780	STAMCOUNTER StatExitInvpg;
781	STAMCOUNTER StatExitInvd;
782	STAMCOUNTER StatExitCpuid;
783	STAMCOUNTER StatExitRdtsc;
784	STAMCOUNTER StatExitRdpmc;
785	STAMCOUNTER StatExitCli;
786	STAMCOUNTER StatExitSti;
787	STAMCOUNTER StatExitPushf;
788	STAMCOUNTER StatExitPopf;
789	STAMCOUNTER StatExitIret;
790	STAMCOUNTER StatExitInt;
791	STAMCOUNTER StatExitCRxWrite[16];
792	STAMCOUNTER StatExitCRxRead[16];
793	STAMCOUNTER StatExitDRxWrite;
794	STAMCOUNTER StatExitDRxRead;
795	STAMCOUNTER StatExitRdmsr;
796	STAMCOUNTER StatExitWrmsr;
797	STAMCOUNTER StatExitCLTS;
798	STAMCOUNTER StatExitHlt;
799	STAMCOUNTER StatExitMwait;
800	STAMCOUNTER StatExitLMSW;
801	STAMCOUNTER StatExitIOWrite;
802	STAMCOUNTER StatExitIORead;
803	STAMCOUNTER StatExitIOStringWrite;
804	STAMCOUNTER StatExitIOStringRead;
805	STAMCOUNTER StatExitIrqWindow;
806	STAMCOUNTER StatExitMaxResume;
807	STAMCOUNTER StatExitPreemptPending;
808	STAMCOUNTER StatIntReinject;
809	STAMCOUNTER StatPendingHostIrq;
810
811	STAMCOUNTER StatFlushPageManual;
812	STAMCOUNTER StatFlushPhysPageManual;
813	STAMCOUNTER StatFlushTLBManual;
814	STAMCOUNTER StatFlushPageInvlpg;
815	STAMCOUNTER StatFlushTLBWorldSwitch;
816	STAMCOUNTER StatNoFlushTLBWorldSwitch;
817	STAMCOUNTER StatFlushTLBCRxChange;
818	STAMCOUNTER StatFlushASID;
819	STAMCOUNTER StatFlushTLBInvlpga;
820	STAMCOUNTER StatTlbShootdown;
821	STAMCOUNTER StatTlbShootdownFlush;
822
823	STAMCOUNTER StatSwitchGuestIrq;
824	STAMCOUNTER StatSwitchToR3;
825
826	STAMCOUNTER StatTSCOffset;
827	STAMCOUNTER StatTSCIntercept;
828	STAMCOUNTER StatTSCInterceptOverFlow;
829
830	STAMCOUNTER StatExitReasonNPF;
831	STAMCOUNTER StatDRxArmed;
832	STAMCOUNTER StatDRxContextSwitch;
833	STAMCOUNTER StatDRxIOCheck;
834
835
836	#ifdef VBOX_WITH_STATISTICS
837	R3PTRTYPE(PSTAMCOUNTER) paStatExitReason;
838	R0PTRTYPE(PSTAMCOUNTER) paStatExitReasonR0;
839	R3PTRTYPE(PSTAMCOUNTER) paStatInjectedIrqs;
840	R0PTRTYPE(PSTAMCOUNTER) paStatInjectedIrqsR0;
841	#endif
842	} HWACCMCPU;
843	/** Pointer to HWACCM VM instance data. */
844	typedef HWACCMCPU *PHWACCMCPU;
845
846
847	#ifdef IN_RING0
848
849	VMMR0DECL(PHWACCM_CPUINFO) HWACCMR0GetCurrentCpu();
850	VMMR0DECL(PHWACCM_CPUINFO) HWACCMR0GetCurrentCpuEx(RTCPUID idCpu);
851
852
853	#ifdef VBOX_STRICT
854	VMMR0DECL(void) HWACCMDumpRegs(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
855	VMMR0DECL(void) HWACCMR0DumpDescriptor(PCX86DESCHC pDesc, RTSEL Sel, const char *pszMsg);
856	#else
857	# define HWACCMDumpRegs(a, b ,c) do { } while (0)
858	# define HWACCMR0DumpDescriptor(a, b, c) do { } while (0)
859	#endif
860
861	/* Dummy callback handlers. */
862	VMMR0DECL(int) HWACCMR0DummyEnter(PVM pVM, PVMCPU pVCpu, PHWACCM_CPUINFO pCpu);
863	VMMR0DECL(int) HWACCMR0DummyLeave(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
864	VMMR0DECL(int) HWACCMR0DummyEnableCpu(PHWACCM_CPUINFO pCpu, PVM pVM, void *pvPageCpu, RTHCPHYS pPageCpuPhys);
865	VMMR0DECL(int) HWACCMR0DummyDisableCpu(PHWACCM_CPUINFO pCpu, void *pvPageCpu, RTHCPHYS pPageCpuPhys);
866	VMMR0DECL(int) HWACCMR0DummyInitVM(PVM pVM);
867	VMMR0DECL(int) HWACCMR0DummyTermVM(PVM pVM);
868	VMMR0DECL(int) HWACCMR0DummySetupVM(PVM pVM);
869	VMMR0DECL(int) HWACCMR0DummyRunGuestCode(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
870	VMMR0DECL(int) HWACCMR0DummySaveHostState(PVM pVM, PVMCPU pVCpu);
871	VMMR0DECL(int) HWACCMR0DummyLoadGuestState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
872
873	# ifdef VBOX_WITH_KERNEL_USING_XMM
874	DECLASM(int) hwaccmR0VMXStartVMWrapXMM(RTHCUINT fResume, PCPUMCTX pCtx, PVMCSCACHE pCache, PVM pVM, PVMCPU pVCpu, PFNHWACCMVMXSTARTVM pfnStartVM);
875	DECLASM(int) hwaccmR0SVMRunWrapXMM(RTHCPHYS pVMCBHostPhys, RTHCPHYS pVMCBPhys, PCPUMCTX pCtx, PVM pVM, PVMCPU pVCpu, PFNHWACCMSVMVMRUN pfnVMRun);
876	# endif
877
878	# ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
879	/**
880	* Gets 64-bit GDTR and IDTR on darwin.
881	* @param pGdtr Where to store the 64-bit GDTR.
882	* @param pIdtr Where to store the 64-bit IDTR.
883	*/
884	DECLASM(void) hwaccmR0Get64bitGDTRandIDTR(PX86XDTR64 pGdtr, PX86XDTR64 pIdtr);
885
886	/**
887	* Gets 64-bit CR3 on darwin.
888	* @returns CR3
889	*/
890	DECLASM(uint64_t) hwaccmR0Get64bitCR3(void);
891	# endif
892
893	#endif /* IN_RING0 */
894
895	/** @} */
896
897	RT_C_DECLS_END
898
899	#endif
900

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source: vbox/trunk/src/VBox/VMM/HWACCMInternal.h@ 24760

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