HWACCMInternal.h@ 30757

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1	/* $Id: HWACCMInternal.h 30183 2010-06-14 14:28:04Z vboxsync $ */
2	/** @file
3	* HWACCM - Internal header file.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	#ifndef ___HWACCMInternal_h
19	#define ___HWACCMInternal_h
20
21	#include <VBox/cdefs.h>
22	#include <VBox/types.h>
23	#include <VBox/em.h>
24	#include <VBox/stam.h>
25	#include <VBox/dis.h>
26	#include <VBox/hwaccm.h>
27	#include <VBox/pgm.h>
28	#include <VBox/cpum.h>
29	#include <iprt/memobj.h>
30	#include <iprt/cpuset.h>
31	#include <iprt/mp.h>
32	#include <iprt/avl.h>
33
34	#if HC_ARCH_BITS == 64 \|\| defined(VBOX_WITH_HYBRID_32BIT_KERNEL) \|\| defined (VBOX_WITH_64_BITS_GUESTS)
35	/* Enable 64 bits guest support. */
36	# define VBOX_ENABLE_64_BITS_GUESTS
37	#endif
38
39	#define VMX_USE_CACHED_VMCS_ACCESSES
40	#define HWACCM_VMX_EMULATE_REALMODE
41	#define HWACCM_VTX_WITH_EPT
42	#define HWACCM_VTX_WITH_VPID
43
44
45	#if 0
46	/* Seeing somewhat random behaviour on my Nehalem system with auto-save of guest MSRs;
47	* for some strange reason the CPU doesn't save the MSRs during the VM-exit.
48	* Clearly visible with a dual VCPU configured OpenSolaris 200906 live cd VM.
49	*
50	* Note: change the assembly files when enabling this! (remove the manual auto load/save)
51	*/
52	#define VBOX_WITH_AUTO_MSR_LOAD_RESTORE
53	#endif
54
55	RT_C_DECLS_BEGIN
56
57
58	/** @defgroup grp_hwaccm_int Internal
59	* @ingroup grp_hwaccm
60	* @internal
61	* @{
62	*/
63
64
65	/** Maximum number of exit reason statistics counters. */
66	#define MAX_EXITREASON_STAT 0x100
67	#define MASK_EXITREASON_STAT 0xff
68	#define MASK_INJECT_IRQ_STAT 0xff
69
70	/** @name Changed flags
71	* These flags are used to keep track of which important registers that
72	* have been changed since last they were reset.
73	* @{
74	*/
75	#define HWACCM_CHANGED_GUEST_FPU RT_BIT(0)
76	#define HWACCM_CHANGED_GUEST_CR0 RT_BIT(1)
77	#define HWACCM_CHANGED_GUEST_CR3 RT_BIT(2)
78	#define HWACCM_CHANGED_GUEST_CR4 RT_BIT(3)
79	#define HWACCM_CHANGED_GUEST_GDTR RT_BIT(4)
80	#define HWACCM_CHANGED_GUEST_IDTR RT_BIT(5)
81	#define HWACCM_CHANGED_GUEST_LDTR RT_BIT(6)
82	#define HWACCM_CHANGED_GUEST_TR RT_BIT(7)
83	#define HWACCM_CHANGED_GUEST_SYSENTER_MSR RT_BIT(8)
84	#define HWACCM_CHANGED_GUEST_SEGMENT_REGS RT_BIT(9)
85	#define HWACCM_CHANGED_GUEST_DEBUG RT_BIT(10)
86	#define HWACCM_CHANGED_HOST_CONTEXT RT_BIT(11)
87
88	#define HWACCM_CHANGED_ALL ( HWACCM_CHANGED_GUEST_SEGMENT_REGS \
89	\| HWACCM_CHANGED_GUEST_CR0 \
90	\| HWACCM_CHANGED_GUEST_CR3 \
91	\| HWACCM_CHANGED_GUEST_CR4 \
92	\| HWACCM_CHANGED_GUEST_GDTR \
93	\| HWACCM_CHANGED_GUEST_IDTR \
94	\| HWACCM_CHANGED_GUEST_LDTR \
95	\| HWACCM_CHANGED_GUEST_TR \
96	\| HWACCM_CHANGED_GUEST_SYSENTER_MSR \
97	\| HWACCM_CHANGED_GUEST_FPU \
98	\| HWACCM_CHANGED_GUEST_DEBUG \
99	\| HWACCM_CHANGED_HOST_CONTEXT)
100
101	#define HWACCM_CHANGED_ALL_GUEST ( HWACCM_CHANGED_GUEST_SEGMENT_REGS \
102	\| HWACCM_CHANGED_GUEST_CR0 \
103	\| HWACCM_CHANGED_GUEST_CR3 \
104	\| HWACCM_CHANGED_GUEST_CR4 \
105	\| HWACCM_CHANGED_GUEST_GDTR \
106	\| HWACCM_CHANGED_GUEST_IDTR \
107	\| HWACCM_CHANGED_GUEST_LDTR \
108	\| HWACCM_CHANGED_GUEST_TR \
109	\| HWACCM_CHANGED_GUEST_SYSENTER_MSR \
110	\| HWACCM_CHANGED_GUEST_DEBUG \
111	\| HWACCM_CHANGED_GUEST_FPU)
112
113	/** @} */
114
115	/** @name Intercepted traps
116	* Traps that need to be intercepted so we can correctly dispatch them to the guest if required.
117	* Currently #NM and #PF only
118	*/
119	#ifdef VBOX_STRICT
120	#define HWACCM_VMX_TRAP_MASK RT_BIT(X86_XCPT_BP) \| RT_BIT(X86_XCPT_DB) \| RT_BIT(X86_XCPT_DE) \| RT_BIT(X86_XCPT_NM) \| RT_BIT(X86_XCPT_PF) \| RT_BIT(X86_XCPT_UD) \| RT_BIT(X86_XCPT_NP) \| RT_BIT(X86_XCPT_SS) \| RT_BIT(X86_XCPT_GP) \| RT_BIT(X86_XCPT_MF)
121	#define HWACCM_SVM_TRAP_MASK HWACCM_VMX_TRAP_MASK
122	#else
123	#define HWACCM_VMX_TRAP_MASK RT_BIT(X86_XCPT_DB) \| RT_BIT(X86_XCPT_NM) \| RT_BIT(X86_XCPT_PF)
124	#define HWACCM_SVM_TRAP_MASK RT_BIT(X86_XCPT_NM) \| RT_BIT(X86_XCPT_PF)
125	#endif
126	/* All exceptions have to be intercept in emulated real-mode (minues NM & PF as they are always intercepted. */
127	#define HWACCM_VMX_TRAP_MASK_REALMODE RT_BIT(X86_XCPT_DE) \| RT_BIT(X86_XCPT_DB) \| RT_BIT(X86_XCPT_NMI) \| RT_BIT(X86_XCPT_BP) \| RT_BIT(X86_XCPT_OF) \| RT_BIT(X86_XCPT_BR) \| RT_BIT(X86_XCPT_UD) \| RT_BIT(X86_XCPT_DF) \| RT_BIT(X86_XCPT_CO_SEG_OVERRUN) \| RT_BIT(X86_XCPT_TS) \| RT_BIT(X86_XCPT_NP) \| RT_BIT(X86_XCPT_SS) \| RT_BIT(X86_XCPT_GP) \| RT_BIT(X86_XCPT_MF) \| RT_BIT(X86_XCPT_AC) \| RT_BIT(X86_XCPT_MC) \| RT_BIT(X86_XCPT_XF)
128	/** @} */
129
130
131	/** Maximum number of page flushes we are willing to remember before considering a full TLB flush. */
132	#define HWACCM_MAX_TLB_SHOOTDOWN_PAGES 8
133
134	/** Size for the EPT identity page table (1024 4 MB pages to cover the entire address space). */
135	#define HWACCM_EPT_IDENTITY_PG_TABLE_SIZE PAGE_SIZE
136	/** Size of the TSS structure + 2 pages for the IO bitmap + end byte. */
137	#define HWACCM_VTX_TSS_SIZE (sizeof(VBOXTSS) + 2*PAGE_SIZE + 1)
138	/** Total guest mapped memory needed. */
139	#define HWACCM_VTX_TOTAL_DEVHEAP_MEM (HWACCM_EPT_IDENTITY_PG_TABLE_SIZE + HWACCM_VTX_TSS_SIZE)
140
141	/* Enable for TPR guest patching. */
142	#define VBOX_HWACCM_WITH_GUEST_PATCHING
143
144	/** HWACCM SSM version
145	*/
146	#ifdef VBOX_HWACCM_WITH_GUEST_PATCHING
147	#define HWACCM_SSM_VERSION 5
148	#define HWACCM_SSM_VERSION_NO_PATCHING 4
149	#else
150	#define HWACCM_SSM_VERSION 4
151	#define HWACCM_SSM_VERSION_NO_PATCHING 4
152	#endif
153	#define HWACCM_SSM_VERSION_2_0_X 3
154
155	/* Per-cpu information. (host) */
156	typedef struct
157	{
158	RTCPUID idCpu;
159
160	RTR0MEMOBJ pMemObj;
161	/* Current ASID (AMD-V)/VPID (Intel) */
162	uint32_t uCurrentASID;
163	/* TLB flush count */
164	uint32_t cTLBFlushes;
165
166	/* Set the first time a cpu is used to make sure we start with a clean TLB. */
167	bool fFlushTLB;
168
169	/** Configured for VT-x or AMD-V. */
170	bool fConfigured;
171
172	/** Set if the VBOX_HWVIRTEX_IGNORE_SVM_IN_USE hack is active. */
173	bool fIgnoreAMDVInUseError;
174
175	/** In use by our code. (for power suspend) */
176	volatile bool fInUse;
177	} HWACCM_CPUINFO;
178	typedef HWACCM_CPUINFO *PHWACCM_CPUINFO;
179
180	typedef enum
181	{
182	HWACCMPENDINGIO_INVALID = 0,
183	HWACCMPENDINGIO_PORT_READ,
184	HWACCMPENDINGIO_PORT_WRITE,
185	HWACCMPENDINGIO_STRING_READ,
186	HWACCMPENDINGIO_STRING_WRITE,
187	/** The usual 32-bit paranoia. */
188	HWACCMPENDINGIO_32BIT_HACK = 0x7fffffff
189	} HWACCMPENDINGIO;
190
191
192	typedef enum
193	{
194	HWACCMTPRINSTR_INVALID,
195	HWACCMTPRINSTR_READ,
196	HWACCMTPRINSTR_READ_SHR4,
197	HWACCMTPRINSTR_WRITE_REG,
198	HWACCMTPRINSTR_WRITE_IMM,
199	HWACCMTPRINSTR_JUMP_REPLACEMENT,
200	/** The usual 32-bit paranoia. */
201	HWACCMTPRINSTR_32BIT_HACK = 0x7fffffff
202	} HWACCMTPRINSTR;
203
204	typedef struct
205	{
206	/** The key is the address of patched instruction. (32 bits GC ptr) */
207	AVLOU32NODECORE Core;
208	/** Original opcode. */
209	uint8_t aOpcode[16];
210	/** Instruction size. */
211	uint32_t cbOp;
212	/** Replacement opcode. */
213	uint8_t aNewOpcode[16];
214	/** Replacement instruction size. */
215	uint32_t cbNewOp;
216	/** Instruction type. */
217	HWACCMTPRINSTR enmType;
218	/** Source operand. */
219	uint32_t uSrcOperand;
220	/** Destination operand. */
221	uint32_t uDstOperand;
222	/** Number of times the instruction caused a fault. */
223	uint32_t cFaults;
224	/** Patch address of the jump replacement. */
225	RTGCPTR32 pJumpTarget;
226	} HWACCMTPRPATCH;
227	/** Pointer to HWACCMTPRPATCH. */
228	typedef HWACCMTPRPATCH *PHWACCMTPRPATCH;
229
230	/**
231	* Switcher function, HC to RC.
232	*
233	* @param pVM The VM handle.
234	* @param uOffsetVMCPU VMCPU offset from pVM
235	* @returns Return code indicating the action to take.
236	*/
237	typedef DECLCALLBACK (int) FNHWACCMSWITCHERHC(PVM pVM, uint32_t uOffsetVMCPU);
238	/** Pointer to switcher function. */
239	typedef FNHWACCMSWITCHERHC *PFNHWACCMSWITCHERHC;
240
241	/**
242	* HWACCM VM Instance data.
243	* Changes to this must checked against the padding of the cfgm union in VM!
244	*/
245	typedef struct HWACCM
246	{
247	/** Set when we've initialized VMX or SVM. */
248	bool fInitialized;
249
250	/** Set when hardware acceleration is allowed. */
251	bool fAllowed;
252
253	/** Set if nested paging is enabled. */
254	bool fNestedPaging;
255
256	/** Set if nested paging is allowed. */
257	bool fAllowNestedPaging;
258
259	/** Set if large pages are enabled (requires nested paging). */
260	bool fLargePages;
261
262	/** Set if we can support 64-bit guests or not. */
263	bool fAllow64BitGuests;
264
265	/** Set if an IO-APIC is configured for this VM. */
266	bool fHasIoApic;
267
268	/** Set when TPR patching is allowed. */
269	bool fTRPPatchingAllowed;
270
271	/** Set when we initialize VT-x or AMD-V once for all CPUs. */
272	bool fGlobalInit;
273
274	/** Set when TPR patching is active. */
275	bool fTPRPatchingActive;
276	bool u8Alignment[6];
277
278	/** And mask for copying register contents. */
279	uint64_t u64RegisterMask;
280
281	/** Maximum ASID allowed. */
282	RTUINT uMaxASID;
283
284	/** The maximum number of resumes loops allowed in ring-0 (safety precaution).
285	* This number is set much higher when RTThreadPreemptIsPending is reliable. */
286	uint32_t cMaxResumeLoops;
287
288	/** Guest allocated memory for patching purposes. */
289	RTGCPTR pGuestPatchMem;
290	/** Current free pointer inside the patch block. */
291	RTGCPTR pFreeGuestPatchMem;
292	/** Size of the guest patch memory block. */
293	uint32_t cbGuestPatchMem;
294	uint32_t uPadding1;
295
296	#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
297	/** 32 to 64 bits switcher entrypoint. */
298	R0PTRTYPE(PFNHWACCMSWITCHERHC) pfnHost32ToGuest64R0;
299
300	/* AMD-V 64 bits vmrun handler */
301	RTRCPTR pfnSVMGCVMRun64;
302
303	/* VT-x 64 bits vmlaunch handler */
304	RTRCPTR pfnVMXGCStartVM64;
305
306	/* RC handler to setup the 64 bits FPU state. */
307	RTRCPTR pfnSaveGuestFPU64;
308
309	/* RC handler to setup the 64 bits debug state. */
310	RTRCPTR pfnSaveGuestDebug64;
311
312	/* Test handler */
313	RTRCPTR pfnTest64;
314
315	RTRCPTR uAlignment[2];
316	/*#elif defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
317	uint32_t u32Alignment[1]; */
318	#endif
319
320	struct
321	{
322	/** Set by the ring-0 driver to indicate VMX is supported by the CPU. */
323	bool fSupported;
324
325	/** Set when we've enabled VMX. */
326	bool fEnabled;
327
328	/** Set if VPID is supported. */
329	bool fVPID;
330
331	/** Set if VT-x VPID is allowed. */
332	bool fAllowVPID;
333
334	/** Set if unrestricted guest execution is allowed (real and protected mode without paging). */
335	bool fUnrestrictedGuest;
336	bool uAlignment[3];
337
338	/** Virtual address of the TSS page used for real mode emulation. */
339	R3PTRTYPE(PVBOXTSS) pRealModeTSS;
340
341	/** Virtual address of the identity page table used for real mode and protected mode without paging emulation in EPT mode. */
342	R3PTRTYPE(PX86PD) pNonPagingModeEPTPageTable;
343
344	/** R0 memory object for the APIC physical page (serves for filtering accesses). */
345	RTR0MEMOBJ pMemObjAPIC;
346	/** Physical address of the APIC physical page (serves for filtering accesses). */
347	RTHCPHYS pAPICPhys;
348	/** Virtual address of the APIC physical page (serves for filtering accesses). */
349	R0PTRTYPE(uint8_t *) pAPIC;
350
351	/** R0 memory object for the MSR entry load page (guest MSRs). */
352	RTR0MEMOBJ pMemObjMSREntryLoad;
353	/** Physical address of the MSR entry load page (guest MSRs). */
354	RTHCPHYS pMSREntryLoadPhys;
355	/** Virtual address of the MSR entry load page (guest MSRs). */
356	R0PTRTYPE(uint8_t *) pMSREntryLoad;
357
358	#ifdef VBOX_WITH_CRASHDUMP_MAGIC
359	RTR0MEMOBJ pMemObjScratch;
360	RTHCPHYS pScratchPhys;
361	R0PTRTYPE(uint8_t *) pScratch;
362	#endif
363	/** R0 memory object for the MSR exit store page (guest MSRs). */
364	RTR0MEMOBJ pMemObjMSRExitStore;
365	/** Physical address of the MSR exit store page (guest MSRs). */
366	RTHCPHYS pMSRExitStorePhys;
367	/** Virtual address of the MSR exit store page (guest MSRs). */
368	R0PTRTYPE(uint8_t *) pMSRExitStore;
369
370	/** R0 memory object for the MSR exit load page (host MSRs). */
371	RTR0MEMOBJ pMemObjMSRExitLoad;
372	/** Physical address of the MSR exit load page (host MSRs). */
373	RTHCPHYS pMSRExitLoadPhys;
374	/** Virtual address of the MSR exit load page (host MSRs). */
375	R0PTRTYPE(uint8_t *) pMSRExitLoad;
376
377	/** Ring 0 handlers for VT-x. */
378	DECLR0CALLBACKMEMBER(void, pfnSetupTaggedTLB, (PVM pVM, PVMCPU pVCpu));
379
380	#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
381	uint32_t u32Alignment;
382	#endif
383	/** Host CR4 value (set by ring-0 VMX init) */
384	uint64_t hostCR4;
385
386	/** Host EFER value (set by ring-0 VMX init) */
387	uint64_t hostEFER;
388
389	/** VMX MSR values */
390	struct
391	{
392	uint64_t feature_ctrl;
393	uint64_t vmx_basic_info;
394	VMX_CAPABILITY vmx_pin_ctls;
395	VMX_CAPABILITY vmx_proc_ctls;
396	VMX_CAPABILITY vmx_proc_ctls2;
397	VMX_CAPABILITY vmx_exit;
398	VMX_CAPABILITY vmx_entry;
399	uint64_t vmx_misc;
400	uint64_t vmx_cr0_fixed0;
401	uint64_t vmx_cr0_fixed1;
402	uint64_t vmx_cr4_fixed0;
403	uint64_t vmx_cr4_fixed1;
404	uint64_t vmx_vmcs_enum;
405	uint64_t vmx_eptcaps;
406	} msr;
407
408	/** Flush types for invept & invvpid; they depend on capabilities. */
409	VMX_FLUSH enmFlushPage;
410	VMX_FLUSH enmFlushContext;
411	} vmx;
412
413	struct
414	{
415	/** Set by the ring-0 driver to indicate SVM is supported by the CPU. */
416	bool fSupported;
417	/** Set when we've enabled SVM. */
418	bool fEnabled;
419	/** Set if erratum 170 affects the AMD cpu. */
420	bool fAlwaysFlushTLB;
421	/** Set when the hack to ignore VERR_SVM_IN_USE is active. */
422	bool fIgnoreInUseError;
423
424	/** R0 memory object for the IO bitmap (12kb). */
425	RTR0MEMOBJ pMemObjIOBitmap;
426	/** Physical address of the IO bitmap (12kb). */
427	RTHCPHYS pIOBitmapPhys;
428	/** Virtual address of the IO bitmap. */
429	R0PTRTYPE(void *) pIOBitmap;
430
431	/* HWCR msr (for diagnostics) */
432	uint64_t msrHWCR;
433
434	/** SVM revision. */
435	uint32_t u32Rev;
436
437	/** SVM feature bits from cpuid 0x8000000a */
438	uint32_t u32Features;
439	} svm;
440
441	/**
442	* AVL tree with all patches (active or disabled) sorted by guest instruction address
443	*/
444	AVLOU32TREE PatchTree;
445	uint32_t cPatches;
446	HWACCMTPRPATCH aPatches[64];
447
448	struct
449	{
450	uint32_t u32AMDFeatureECX;
451	uint32_t u32AMDFeatureEDX;
452	} cpuid;
453
454	/** Saved error from detection */
455	int32_t lLastError;
456
457	/** HWACCMR0Init was run */
458	bool fHWACCMR0Init;
459	bool u8Alignment1[7];
460
461	STAMCOUNTER StatTPRPatchSuccess;
462	STAMCOUNTER StatTPRPatchFailure;
463	STAMCOUNTER StatTPRReplaceSuccess;
464	STAMCOUNTER StatTPRReplaceFailure;
465	} HWACCM;
466	/** Pointer to HWACCM VM instance data. */
467	typedef HWACCM *PHWACCM;
468
469	/* Maximum number of cached entries. */
470	#define VMCSCACHE_MAX_ENTRY 128
471
472	/* Structure for storing read and write VMCS actions. */
473	typedef struct VMCSCACHE
474	{
475	#ifdef VBOX_WITH_CRASHDUMP_MAGIC
476	/* Magic marker for searching in crash dumps. */
477	uint8_t aMagic[16];
478	uint64_t uMagic;
479	uint64_t u64TimeEntry;
480	uint64_t u64TimeSwitch;
481	uint64_t cResume;
482	uint64_t interPD;
483	uint64_t pSwitcher;
484	uint32_t uPos;
485	uint32_t idCpu;
486	#endif
487	/* CR2 is saved here for EPT syncing. */
488	uint64_t cr2;
489	struct
490	{
491	uint32_t cValidEntries;
492	uint32_t uAlignment;
493	uint32_t aField[VMCSCACHE_MAX_ENTRY];
494	uint64_t aFieldVal[VMCSCACHE_MAX_ENTRY];
495	} Write;
496	struct
497	{
498	uint32_t cValidEntries;
499	uint32_t uAlignment;
500	uint32_t aField[VMCSCACHE_MAX_ENTRY];
501	uint64_t aFieldVal[VMCSCACHE_MAX_ENTRY];
502	} Read;
503	#ifdef DEBUG
504	struct
505	{
506	RTHCPHYS pPageCpuPhys;
507	RTHCPHYS pVMCSPhys;
508	RTGCPTR pCache;
509	RTGCPTR pCtx;
510	} TestIn;
511	struct
512	{
513	RTHCPHYS pVMCSPhys;
514	RTGCPTR pCache;
515	RTGCPTR pCtx;
516	uint64_t eflags;
517	uint64_t cr8;
518	} TestOut;
519	struct
520	{
521	uint64_t param1;
522	uint64_t param2;
523	uint64_t param3;
524	uint64_t param4;
525	} ScratchPad;
526	#endif
527	} VMCSCACHE;
528	/** Pointer to VMCSCACHE. */
529	typedef VMCSCACHE *PVMCSCACHE;
530
531	/** VMX StartVM function. */
532	typedef DECLCALLBACK(int) FNHWACCMVMXSTARTVM(RTHCUINT fResume, PCPUMCTX pCtx, PVMCSCACHE pCache, PVM pVM, PVMCPU pVCpu);
533	/** Pointer to a VMX StartVM function. */
534	typedef R0PTRTYPE(FNHWACCMVMXSTARTVM *) PFNHWACCMVMXSTARTVM;
535
536	/** SVM VMRun function. */
537	typedef DECLCALLBACK(int) FNHWACCMSVMVMRUN(RTHCPHYS pVMCBHostPhys, RTHCPHYS pVMCBPhys, PCPUMCTX pCtx, PVM pVM, PVMCPU pVCpu);
538	/** Pointer to a SVM VMRun function. */
539	typedef R0PTRTYPE(FNHWACCMSVMVMRUN *) PFNHWACCMSVMVMRUN;
540
541	/**
542	* HWACCM VMCPU Instance data.
543	*/
544	typedef struct HWACCMCPU
545	{
546	/** Old style FPU reporting trap mask override performed (optimization) */
547	bool fFPUOldStyleOverride;
548
549	/** Set if we don't have to flush the TLB on VM entry. */
550	bool fResumeVM;
551
552	/** Set if we need to flush the TLB during the world switch. */
553	bool fForceTLBFlush;
554
555	/** Set when we're using VT-x or AMD-V at that moment. */
556	bool fActive;
557
558	/** Set when the TLB has been checked until we return from the world switch. */
559	volatile uint8_t fCheckedTLBFlush;
560	uint8_t bAlignment[3];
561
562	/** HWACCM_CHANGED_* flags. */
563	RTUINT fContextUseFlags;
564
565	/** Id of the last cpu we were executing code on (NIL_RTCPUID for the first time) */
566	RTCPUID idLastCpu;
567
568	/** TLB flush count */
569	RTUINT cTLBFlushes;
570
571	/** Current ASID in use by the VM */
572	RTUINT uCurrentASID;
573
574	/** World switch exit counter. */
575	volatile uint32_t cWorldSwitchExit;
576	uint32_t u32Alignment;
577
578	struct
579	{
580	/** Physical address of the VM control structure (VMCS). */
581	RTHCPHYS pVMCSPhys;
582	/** R0 memory object for the VM control structure (VMCS). */
583	RTR0MEMOBJ pMemObjVMCS;
584	/** Virtual address of the VM control structure (VMCS). */
585	R0PTRTYPE(void *) pVMCS;
586
587	/** Ring 0 handlers for VT-x. */
588	PFNHWACCMVMXSTARTVM pfnStartVM;
589
590	#if HC_ARCH_BITS == 32
591	uint32_t u32Alignment;
592	#endif
593
594	/** Current VMX_VMCS_CTRL_PROC_EXEC_CONTROLS. */
595	uint64_t proc_ctls;
596
597	/** Current VMX_VMCS_CTRL_PROC_EXEC2_CONTROLS. */
598	uint64_t proc_ctls2;
599
600	/** Physical address of the virtual APIC page for TPR caching. */
601	RTHCPHYS pVAPICPhys;
602	/** R0 memory object for the virtual APIC page for TPR caching. */
603	RTR0MEMOBJ pMemObjVAPIC;
604	/** Virtual address of the virtual APIC page for TPR caching. */
605	R0PTRTYPE(uint8_t *) pVAPIC;
606
607	/** Current CR0 mask. */
608	uint64_t cr0_mask;
609	/** Current CR4 mask. */
610	uint64_t cr4_mask;
611
612	/** Current EPTP. */
613	RTHCPHYS GCPhysEPTP;
614
615	/** Physical address of the MSR bitmap (1 page). */
616	RTHCPHYS pMSRBitmapPhys;
617	/** R0 memory object for the MSR bitmap (1 page). */
618	RTR0MEMOBJ pMemObjMSRBitmap;
619	/** Virtual address of the MSR bitmap (1 page). */
620	R0PTRTYPE(uint8_t *) pMSRBitmap;
621
622	#ifdef VBOX_WITH_AUTO_MSR_LOAD_RESTORE
623	/** Physical address of the guest MSR load area (1 page). */
624	RTHCPHYS pGuestMSRPhys;
625	/** R0 memory object for the guest MSR load area (1 page). */
626	RTR0MEMOBJ pMemObjGuestMSR;
627	/** Virtual address of the guest MSR load area (1 page). */
628	R0PTRTYPE(uint8_t *) pGuestMSR;
629
630	/** Physical address of the MSR load area (1 page). */
631	RTHCPHYS pHostMSRPhys;
632	/** R0 memory object for the MSR load area (1 page). */
633	RTR0MEMOBJ pMemObjHostMSR;
634	/** Virtual address of the MSR load area (1 page). */
635	R0PTRTYPE(uint8_t *) pHostMSR;
636	#endif /* VBOX_WITH_AUTO_MSR_LOAD_RESTORE */
637
638	/* Number of automatically loaded/restored MSRs. */
639	uint32_t cCachedMSRs;
640	uint32_t uAlignement;
641
642	/* Last use TSC offset value. (cached) */
643	uint64_t u64TSCOffset;
644
645	/** VMCS cache. */
646	VMCSCACHE VMCSCache;
647
648	/** Real-mode emulation state. */
649	struct
650	{
651	X86EFLAGS eflags;
652	uint32_t fValid;
653	} RealMode;
654
655	struct
656	{
657	uint64_t u64VMCSPhys;
658	uint32_t ulVMCSRevision;
659	uint32_t ulInstrError;
660	uint32_t ulExitReason;
661	RTCPUID idEnteredCpu;
662	RTCPUID idCurrentCpu;
663	uint32_t padding;
664	} lasterror;
665
666	/** The last seen guest paging mode (by VT-x). */
667	PGMMODE enmLastSeenGuestMode;
668	/** Current guest paging mode (as seen by HWACCMR3PagingModeChanged). */
669	PGMMODE enmCurrGuestMode;
670	/** Previous guest paging mode (as seen by HWACCMR3PagingModeChanged). */
671	PGMMODE enmPrevGuestMode;
672	} vmx;
673
674	struct
675	{
676	/** R0 memory object for the host VM control block (VMCB). */
677	RTR0MEMOBJ pMemObjVMCBHost;
678	/** Physical address of the host VM control block (VMCB). */
679	RTHCPHYS pVMCBHostPhys;
680	/** Virtual address of the host VM control block (VMCB). */
681	R0PTRTYPE(void *) pVMCBHost;
682
683	/** R0 memory object for the VM control block (VMCB). */
684	RTR0MEMOBJ pMemObjVMCB;
685	/** Physical address of the VM control block (VMCB). */
686	RTHCPHYS pVMCBPhys;
687	/** Virtual address of the VM control block (VMCB). */
688	R0PTRTYPE(void *) pVMCB;
689
690	/** Ring 0 handlers for VT-x. */
691	PFNHWACCMSVMVMRUN pfnVMRun;
692
693	/** R0 memory object for the MSR bitmap (8kb). */
694	RTR0MEMOBJ pMemObjMSRBitmap;
695	/** Physical address of the MSR bitmap (8kb). */
696	RTHCPHYS pMSRBitmapPhys;
697	/** Virtual address of the MSR bitmap. */
698	R0PTRTYPE(void *) pMSRBitmap;
699	} svm;
700
701	/** Event injection state. */
702	struct
703	{
704	uint32_t fPending;
705	uint32_t errCode;
706	uint64_t intInfo;
707	} Event;
708
709	/** IO Block emulation state. */
710	struct
711	{
712	bool fEnabled;
713	uint8_t u8Align[7];
714
715	/** RIP at the start of the io code we wish to emulate in the recompiler. */
716	RTGCPTR GCPtrFunctionEip;
717
718	uint64_t cr0;
719	} EmulateIoBlock;
720
721	struct
722	{
723	/* Pending IO operation type. */
724	HWACCMPENDINGIO enmType;
725	uint32_t uPadding;
726	RTGCPTR GCPtrRip;
727	RTGCPTR GCPtrRipNext;
728	union
729	{
730	struct
731	{
732	unsigned uPort;
733	unsigned uAndVal;
734	unsigned cbSize;
735	} Port;
736	uint64_t aRaw[2];
737	} s;
738	} PendingIO;
739
740	/** Currenty shadow paging mode. */
741	PGMMODE enmShadowMode;
742
743	/** The CPU ID of the CPU currently owning the VMCS. Set in
744	* HWACCMR0Enter and cleared in HWACCMR0Leave. */
745	RTCPUID idEnteredCpu;
746
747	/** To keep track of pending TLB shootdown pages. (SMP guest only) */
748	struct
749	{
750	RTGCPTR aPages[HWACCM_MAX_TLB_SHOOTDOWN_PAGES];
751	unsigned cPages;
752	} TlbShootdown;
753
754	/** For saving stack space, the disassembler state is allocated here instead of
755	* on the stack.
756	* @note The DISCPUSTATE structure is not R3/R0/RZ clean! */
757	union
758	{
759	/** The disassembler scratch space. */
760	DISCPUSTATE DisState;
761	/** Padding. */
762	uint8_t abDisStatePadding[DISCPUSTATE_PADDING_SIZE];
763	};
764
765	RTUINT padding2[1];
766
767	STAMPROFILEADV StatEntry;
768	STAMPROFILEADV StatExit1;
769	STAMPROFILEADV StatExit2;
770	#if 1 /* temporary for tracking down darwin issues. */
771	STAMPROFILEADV StatExit2Sub1;
772	STAMPROFILEADV StatExit2Sub2;
773	STAMPROFILEADV StatExit2Sub3;
774	#endif
775	STAMPROFILEADV StatInGC;
776
777	#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
778	STAMPROFILEADV StatWorldSwitch3264;
779	#endif
780	STAMPROFILEADV StatPoke;
781	STAMPROFILEADV StatSpinPoke;
782	STAMPROFILEADV StatSpinPokeFailed;
783
784	STAMCOUNTER StatIntInject;
785
786	STAMCOUNTER StatExitShadowNM;
787	STAMCOUNTER StatExitGuestNM;
788	STAMCOUNTER StatExitShadowPF;
789	STAMCOUNTER StatExitGuestPF;
790	STAMCOUNTER StatExitGuestUD;
791	STAMCOUNTER StatExitGuestSS;
792	STAMCOUNTER StatExitGuestNP;
793	STAMCOUNTER StatExitGuestGP;
794	STAMCOUNTER StatExitGuestDE;
795	STAMCOUNTER StatExitGuestDB;
796	STAMCOUNTER StatExitGuestMF;
797	STAMCOUNTER StatExitInvpg;
798	STAMCOUNTER StatExitInvd;
799	STAMCOUNTER StatExitCpuid;
800	STAMCOUNTER StatExitRdtsc;
801	STAMCOUNTER StatExitRdpmc;
802	STAMCOUNTER StatExitCli;
803	STAMCOUNTER StatExitSti;
804	STAMCOUNTER StatExitPushf;
805	STAMCOUNTER StatExitPopf;
806	STAMCOUNTER StatExitIret;
807	STAMCOUNTER StatExitInt;
808	STAMCOUNTER StatExitCRxWrite[16];
809	STAMCOUNTER StatExitCRxRead[16];
810	STAMCOUNTER StatExitDRxWrite;
811	STAMCOUNTER StatExitDRxRead;
812	STAMCOUNTER StatExitRdmsr;
813	STAMCOUNTER StatExitWrmsr;
814	STAMCOUNTER StatExitCLTS;
815	STAMCOUNTER StatExitHlt;
816	STAMCOUNTER StatExitMwait;
817	STAMCOUNTER StatExitMonitor;
818	STAMCOUNTER StatExitLMSW;
819	STAMCOUNTER StatExitIOWrite;
820	STAMCOUNTER StatExitIORead;
821	STAMCOUNTER StatExitIOStringWrite;
822	STAMCOUNTER StatExitIOStringRead;
823	STAMCOUNTER StatExitIrqWindow;
824	STAMCOUNTER StatExitMaxResume;
825	STAMCOUNTER StatExitPreemptPending;
826	STAMCOUNTER StatIntReinject;
827	STAMCOUNTER StatPendingHostIrq;
828
829	STAMCOUNTER StatFlushPage;
830	STAMCOUNTER StatFlushPageManual;
831	STAMCOUNTER StatFlushPhysPageManual;
832	STAMCOUNTER StatFlushTLB;
833	STAMCOUNTER StatFlushTLBManual;
834	STAMCOUNTER StatFlushPageInvlpg;
835	STAMCOUNTER StatFlushTLBWorldSwitch;
836	STAMCOUNTER StatNoFlushTLBWorldSwitch;
837	STAMCOUNTER StatFlushTLBCRxChange;
838	STAMCOUNTER StatFlushASID;
839	STAMCOUNTER StatFlushTLBInvlpga;
840	STAMCOUNTER StatTlbShootdown;
841	STAMCOUNTER StatTlbShootdownFlush;
842
843	STAMCOUNTER StatSwitchGuestIrq;
844	STAMCOUNTER StatSwitchToR3;
845
846	STAMCOUNTER StatTSCOffset;
847	STAMCOUNTER StatTSCIntercept;
848	STAMCOUNTER StatTSCInterceptOverFlow;
849
850	STAMCOUNTER StatExitReasonNPF;
851	STAMCOUNTER StatDRxArmed;
852	STAMCOUNTER StatDRxContextSwitch;
853	STAMCOUNTER StatDRxIOCheck;
854
855	#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
856	STAMCOUNTER StatFpu64SwitchBack;
857	STAMCOUNTER StatDebug64SwitchBack;
858	#endif
859
860	#ifdef VBOX_WITH_STATISTICS
861	R3PTRTYPE(PSTAMCOUNTER) paStatExitReason;
862	R0PTRTYPE(PSTAMCOUNTER) paStatExitReasonR0;
863	R3PTRTYPE(PSTAMCOUNTER) paStatInjectedIrqs;
864	R0PTRTYPE(PSTAMCOUNTER) paStatInjectedIrqsR0;
865	#endif
866	} HWACCMCPU;
867	/** Pointer to HWACCM VM instance data. */
868	typedef HWACCMCPU *PHWACCMCPU;
869
870
871	#ifdef IN_RING0
872
873	VMMR0DECL(PHWACCM_CPUINFO) HWACCMR0GetCurrentCpu();
874	VMMR0DECL(PHWACCM_CPUINFO) HWACCMR0GetCurrentCpuEx(RTCPUID idCpu);
875
876
877	#ifdef VBOX_STRICT
878	VMMR0DECL(void) HWACCMDumpRegs(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
879	VMMR0DECL(void) HWACCMR0DumpDescriptor(PCX86DESCHC pDesc, RTSEL Sel, const char *pszMsg);
880	#else
881	# define HWACCMDumpRegs(a, b ,c) do { } while (0)
882	# define HWACCMR0DumpDescriptor(a, b, c) do { } while (0)
883	#endif
884
885	/* Dummy callback handlers. */
886	VMMR0DECL(int) HWACCMR0DummyEnter(PVM pVM, PVMCPU pVCpu, PHWACCM_CPUINFO pCpu);
887	VMMR0DECL(int) HWACCMR0DummyLeave(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
888	VMMR0DECL(int) HWACCMR0DummyEnableCpu(PHWACCM_CPUINFO pCpu, PVM pVM, void *pvPageCpu, RTHCPHYS pPageCpuPhys);
889	VMMR0DECL(int) HWACCMR0DummyDisableCpu(PHWACCM_CPUINFO pCpu, void *pvPageCpu, RTHCPHYS pPageCpuPhys);
890	VMMR0DECL(int) HWACCMR0DummyInitVM(PVM pVM);
891	VMMR0DECL(int) HWACCMR0DummyTermVM(PVM pVM);
892	VMMR0DECL(int) HWACCMR0DummySetupVM(PVM pVM);
893	VMMR0DECL(int) HWACCMR0DummyRunGuestCode(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
894	VMMR0DECL(int) HWACCMR0DummySaveHostState(PVM pVM, PVMCPU pVCpu);
895	VMMR0DECL(int) HWACCMR0DummyLoadGuestState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
896
897	# ifdef VBOX_WITH_KERNEL_USING_XMM
898	DECLASM(int) hwaccmR0VMXStartVMWrapXMM(RTHCUINT fResume, PCPUMCTX pCtx, PVMCSCACHE pCache, PVM pVM, PVMCPU pVCpu, PFNHWACCMVMXSTARTVM pfnStartVM);
899	DECLASM(int) hwaccmR0SVMRunWrapXMM(RTHCPHYS pVMCBHostPhys, RTHCPHYS pVMCBPhys, PCPUMCTX pCtx, PVM pVM, PVMCPU pVCpu, PFNHWACCMSVMVMRUN pfnVMRun);
900	# endif
901
902	# ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
903	/**
904	* Gets 64-bit GDTR and IDTR on darwin.
905	* @param pGdtr Where to store the 64-bit GDTR.
906	* @param pIdtr Where to store the 64-bit IDTR.
907	*/
908	DECLASM(void) hwaccmR0Get64bitGDTRandIDTR(PX86XDTR64 pGdtr, PX86XDTR64 pIdtr);
909
910	/**
911	* Gets 64-bit CR3 on darwin.
912	* @returns CR3
913	*/
914	DECLASM(uint64_t) hwaccmR0Get64bitCR3(void);
915	# endif
916
917	#endif /* IN_RING0 */
918
919	/** @} */
920
921	RT_C_DECLS_END
922
923	#endif
924

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source: vbox/trunk/src/VBox/VMM/HWACCMInternal.h@ 30757

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