HWACCMInternal.h@ 34079

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*: spelling fixes, thanks Timeless!
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1	/* $Id: HWACCMInternal.h 33540 2010-10-28 09:27:05Z vboxsync $ */
2	/** @file
3	* HWACCM - Internal header file.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	#ifndef ___HWACCMInternal_h
19	#define ___HWACCMInternal_h
20
21	#include <VBox/cdefs.h>
22	#include <VBox/types.h>
23	#include <VBox/em.h>
24	#include <VBox/stam.h>
25	#include <VBox/dis.h>
26	#include <VBox/hwaccm.h>
27	#include <VBox/hwacc_vmx.h>
28	#include <VBox/pgm.h>
29	#include <VBox/cpum.h>
30	#include <iprt/memobj.h>
31	#include <iprt/cpuset.h>
32	#include <iprt/mp.h>
33	#include <iprt/avl.h>
34
35	#if HC_ARCH_BITS == 64 \|\| defined(VBOX_WITH_HYBRID_32BIT_KERNEL) \|\| defined (VBOX_WITH_64_BITS_GUESTS)
36	/* Enable 64 bits guest support. */
37	# define VBOX_ENABLE_64_BITS_GUESTS
38	#endif
39
40	#define VMX_USE_CACHED_VMCS_ACCESSES
41	#define HWACCM_VMX_EMULATE_REALMODE
42	#define HWACCM_VTX_WITH_EPT
43	#define HWACCM_VTX_WITH_VPID
44
45
46	#if 0
47	/* Seeing somewhat random behaviour on my Nehalem system with auto-save of guest MSRs;
48	* for some strange reason the CPU doesn't save the MSRs during the VM-exit.
49	* Clearly visible with a dual VCPU configured OpenSolaris 200906 live cd VM.
50	*
51	* Note: change the assembly files when enabling this! (remove the manual auto load/save)
52	*/
53	#define VBOX_WITH_AUTO_MSR_LOAD_RESTORE
54	#endif
55
56	RT_C_DECLS_BEGIN
57
58
59	/** @defgroup grp_hwaccm_int Internal
60	* @ingroup grp_hwaccm
61	* @internal
62	* @{
63	*/
64
65
66	/** Maximum number of exit reason statistics counters. */
67	#define MAX_EXITREASON_STAT 0x100
68	#define MASK_EXITREASON_STAT 0xff
69	#define MASK_INJECT_IRQ_STAT 0xff
70
71	/** @name Changed flags
72	* These flags are used to keep track of which important registers that
73	* have been changed since last they were reset.
74	* @{
75	*/
76	#define HWACCM_CHANGED_GUEST_FPU RT_BIT(0)
77	#define HWACCM_CHANGED_GUEST_CR0 RT_BIT(1)
78	#define HWACCM_CHANGED_GUEST_CR3 RT_BIT(2)
79	#define HWACCM_CHANGED_GUEST_CR4 RT_BIT(3)
80	#define HWACCM_CHANGED_GUEST_GDTR RT_BIT(4)
81	#define HWACCM_CHANGED_GUEST_IDTR RT_BIT(5)
82	#define HWACCM_CHANGED_GUEST_LDTR RT_BIT(6)
83	#define HWACCM_CHANGED_GUEST_TR RT_BIT(7)
84	#define HWACCM_CHANGED_GUEST_MSR RT_BIT(8)
85	#define HWACCM_CHANGED_GUEST_SEGMENT_REGS RT_BIT(9)
86	#define HWACCM_CHANGED_GUEST_DEBUG RT_BIT(10)
87	#define HWACCM_CHANGED_HOST_CONTEXT RT_BIT(11)
88
89	#define HWACCM_CHANGED_ALL ( HWACCM_CHANGED_GUEST_SEGMENT_REGS \
90	\| HWACCM_CHANGED_GUEST_CR0 \
91	\| HWACCM_CHANGED_GUEST_CR3 \
92	\| HWACCM_CHANGED_GUEST_CR4 \
93	\| HWACCM_CHANGED_GUEST_GDTR \
94	\| HWACCM_CHANGED_GUEST_IDTR \
95	\| HWACCM_CHANGED_GUEST_LDTR \
96	\| HWACCM_CHANGED_GUEST_TR \
97	\| HWACCM_CHANGED_GUEST_MSR \
98	\| HWACCM_CHANGED_GUEST_FPU \
99	\| HWACCM_CHANGED_GUEST_DEBUG \
100	\| HWACCM_CHANGED_HOST_CONTEXT)
101
102	#define HWACCM_CHANGED_ALL_GUEST ( HWACCM_CHANGED_GUEST_SEGMENT_REGS \
103	\| HWACCM_CHANGED_GUEST_CR0 \
104	\| HWACCM_CHANGED_GUEST_CR3 \
105	\| HWACCM_CHANGED_GUEST_CR4 \
106	\| HWACCM_CHANGED_GUEST_GDTR \
107	\| HWACCM_CHANGED_GUEST_IDTR \
108	\| HWACCM_CHANGED_GUEST_LDTR \
109	\| HWACCM_CHANGED_GUEST_TR \
110	\| HWACCM_CHANGED_GUEST_MSR \
111	\| HWACCM_CHANGED_GUEST_DEBUG \
112	\| HWACCM_CHANGED_GUEST_FPU)
113
114	/** @} */
115
116	/** @name Intercepted traps
117	* Traps that need to be intercepted so we can correctly dispatch them to the guest if required.
118	* Currently #NM and #PF only
119	*/
120	#ifdef VBOX_STRICT
121	#define HWACCM_VMX_TRAP_MASK RT_BIT(X86_XCPT_BP) \| RT_BIT(X86_XCPT_DB) \| RT_BIT(X86_XCPT_DE) \| RT_BIT(X86_XCPT_NM) \| RT_BIT(X86_XCPT_PF) \| RT_BIT(X86_XCPT_UD) \| RT_BIT(X86_XCPT_NP) \| RT_BIT(X86_XCPT_SS) \| RT_BIT(X86_XCPT_GP) \| RT_BIT(X86_XCPT_MF)
122	#define HWACCM_SVM_TRAP_MASK HWACCM_VMX_TRAP_MASK
123	#else
124	#define HWACCM_VMX_TRAP_MASK RT_BIT(X86_XCPT_DB) \| RT_BIT(X86_XCPT_NM) \| RT_BIT(X86_XCPT_PF)
125	#define HWACCM_SVM_TRAP_MASK RT_BIT(X86_XCPT_NM) \| RT_BIT(X86_XCPT_PF)
126	#endif
127	/* All exceptions have to be intercept in emulated real-mode (minus NM & PF as they are always intercepted. */
128	#define HWACCM_VMX_TRAP_MASK_REALMODE RT_BIT(X86_XCPT_DE) \| RT_BIT(X86_XCPT_DB) \| RT_BIT(X86_XCPT_NMI) \| RT_BIT(X86_XCPT_BP) \| RT_BIT(X86_XCPT_OF) \| RT_BIT(X86_XCPT_BR) \| RT_BIT(X86_XCPT_UD) \| RT_BIT(X86_XCPT_DF) \| RT_BIT(X86_XCPT_CO_SEG_OVERRUN) \| RT_BIT(X86_XCPT_TS) \| RT_BIT(X86_XCPT_NP) \| RT_BIT(X86_XCPT_SS) \| RT_BIT(X86_XCPT_GP) \| RT_BIT(X86_XCPT_MF) \| RT_BIT(X86_XCPT_AC) \| RT_BIT(X86_XCPT_MC) \| RT_BIT(X86_XCPT_XF)
129	/** @} */
130
131
132	/** Maximum number of page flushes we are willing to remember before considering a full TLB flush. */
133	#define HWACCM_MAX_TLB_SHOOTDOWN_PAGES 8
134
135	/** Size for the EPT identity page table (1024 4 MB pages to cover the entire address space). */
136	#define HWACCM_EPT_IDENTITY_PG_TABLE_SIZE PAGE_SIZE
137	/** Size of the TSS structure + 2 pages for the IO bitmap + end byte. */
138	#define HWACCM_VTX_TSS_SIZE (sizeof(VBOXTSS) + 2*PAGE_SIZE + 1)
139	/** Total guest mapped memory needed. */
140	#define HWACCM_VTX_TOTAL_DEVHEAP_MEM (HWACCM_EPT_IDENTITY_PG_TABLE_SIZE + HWACCM_VTX_TSS_SIZE)
141
142	/* Enable for TPR guest patching. */
143	#define VBOX_HWACCM_WITH_GUEST_PATCHING
144
145	/** HWACCM SSM version
146	*/
147	#ifdef VBOX_HWACCM_WITH_GUEST_PATCHING
148	#define HWACCM_SSM_VERSION 5
149	#define HWACCM_SSM_VERSION_NO_PATCHING 4
150	#else
151	#define HWACCM_SSM_VERSION 4
152	#define HWACCM_SSM_VERSION_NO_PATCHING 4
153	#endif
154	#define HWACCM_SSM_VERSION_2_0_X 3
155
156	/* Per-cpu information. (host) */
157	typedef struct
158	{
159	RTCPUID idCpu;
160
161	RTR0MEMOBJ pMemObj;
162	/* Current ASID (AMD-V)/VPID (Intel) */
163	uint32_t uCurrentASID;
164	/* TLB flush count */
165	uint32_t cTLBFlushes;
166
167	/* Set the first time a cpu is used to make sure we start with a clean TLB. */
168	bool fFlushTLB;
169
170	/** Configured for VT-x or AMD-V. */
171	bool fConfigured;
172
173	/** Set if the VBOX_HWVIRTEX_IGNORE_SVM_IN_USE hack is active. */
174	bool fIgnoreAMDVInUseError;
175
176	/** In use by our code. (for power suspend) */
177	volatile bool fInUse;
178	} HWACCM_CPUINFO;
179	typedef HWACCM_CPUINFO *PHWACCM_CPUINFO;
180
181	typedef enum
182	{
183	HWACCMPENDINGIO_INVALID = 0,
184	HWACCMPENDINGIO_PORT_READ,
185	HWACCMPENDINGIO_PORT_WRITE,
186	HWACCMPENDINGIO_STRING_READ,
187	HWACCMPENDINGIO_STRING_WRITE,
188	/** The usual 32-bit paranoia. */
189	HWACCMPENDINGIO_32BIT_HACK = 0x7fffffff
190	} HWACCMPENDINGIO;
191
192
193	typedef enum
194	{
195	HWACCMTPRINSTR_INVALID,
196	HWACCMTPRINSTR_READ,
197	HWACCMTPRINSTR_READ_SHR4,
198	HWACCMTPRINSTR_WRITE_REG,
199	HWACCMTPRINSTR_WRITE_IMM,
200	HWACCMTPRINSTR_JUMP_REPLACEMENT,
201	/** The usual 32-bit paranoia. */
202	HWACCMTPRINSTR_32BIT_HACK = 0x7fffffff
203	} HWACCMTPRINSTR;
204
205	typedef struct
206	{
207	/** The key is the address of patched instruction. (32 bits GC ptr) */
208	AVLOU32NODECORE Core;
209	/** Original opcode. */
210	uint8_t aOpcode[16];
211	/** Instruction size. */
212	uint32_t cbOp;
213	/** Replacement opcode. */
214	uint8_t aNewOpcode[16];
215	/** Replacement instruction size. */
216	uint32_t cbNewOp;
217	/** Instruction type. */
218	HWACCMTPRINSTR enmType;
219	/** Source operand. */
220	uint32_t uSrcOperand;
221	/** Destination operand. */
222	uint32_t uDstOperand;
223	/** Number of times the instruction caused a fault. */
224	uint32_t cFaults;
225	/** Patch address of the jump replacement. */
226	RTGCPTR32 pJumpTarget;
227	} HWACCMTPRPATCH;
228	/** Pointer to HWACCMTPRPATCH. */
229	typedef HWACCMTPRPATCH *PHWACCMTPRPATCH;
230
231	/**
232	* Switcher function, HC to RC.
233	*
234	* @param pVM The VM handle.
235	* @param uOffsetVMCPU VMCPU offset from pVM
236	* @returns Return code indicating the action to take.
237	*/
238	typedef DECLCALLBACK (int) FNHWACCMSWITCHERHC(PVM pVM, uint32_t uOffsetVMCPU);
239	/** Pointer to switcher function. */
240	typedef FNHWACCMSWITCHERHC *PFNHWACCMSWITCHERHC;
241
242	/**
243	* HWACCM VM Instance data.
244	* Changes to this must checked against the padding of the cfgm union in VM!
245	*/
246	typedef struct HWACCM
247	{
248	/** Set when we've initialized VMX or SVM. */
249	bool fInitialized;
250
251	/** Set when hardware acceleration is allowed. */
252	bool fAllowed;
253
254	/** Set if nested paging is enabled. */
255	bool fNestedPaging;
256
257	/** Set if nested paging is allowed. */
258	bool fAllowNestedPaging;
259
260	/** Set if large pages are enabled (requires nested paging). */
261	bool fLargePages;
262
263	/** Set if we can support 64-bit guests or not. */
264	bool fAllow64BitGuests;
265
266	/** Set if an IO-APIC is configured for this VM. */
267	bool fHasIoApic;
268
269	/** Set when TPR patching is allowed. */
270	bool fTRPPatchingAllowed;
271
272	/** Set when we initialize VT-x or AMD-V once for all CPUs. */
273	bool fGlobalInit;
274
275	/** Set when TPR patching is active. */
276	bool fTPRPatchingActive;
277	bool u8Alignment[6];
278
279	/** And mask for copying register contents. */
280	uint64_t u64RegisterMask;
281
282	/** Maximum ASID allowed. */
283	RTUINT uMaxASID;
284
285	/** The maximum number of resumes loops allowed in ring-0 (safety precaution).
286	* This number is set much higher when RTThreadPreemptIsPending is reliable. */
287	uint32_t cMaxResumeLoops;
288
289	/** Guest allocated memory for patching purposes. */
290	RTGCPTR pGuestPatchMem;
291	/** Current free pointer inside the patch block. */
292	RTGCPTR pFreeGuestPatchMem;
293	/** Size of the guest patch memory block. */
294	uint32_t cbGuestPatchMem;
295	uint32_t uPadding1;
296
297	#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
298	/** 32 to 64 bits switcher entrypoint. */
299	R0PTRTYPE(PFNHWACCMSWITCHERHC) pfnHost32ToGuest64R0;
300
301	/* AMD-V 64 bits vmrun handler */
302	RTRCPTR pfnSVMGCVMRun64;
303
304	/* VT-x 64 bits vmlaunch handler */
305	RTRCPTR pfnVMXGCStartVM64;
306
307	/* RC handler to setup the 64 bits FPU state. */
308	RTRCPTR pfnSaveGuestFPU64;
309
310	/* RC handler to setup the 64 bits debug state. */
311	RTRCPTR pfnSaveGuestDebug64;
312
313	/* Test handler */
314	RTRCPTR pfnTest64;
315
316	RTRCPTR uAlignment[2];
317	/*#elif defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
318	uint32_t u32Alignment[1]; */
319	#endif
320
321	struct
322	{
323	/** Set by the ring-0 driver to indicate VMX is supported by the CPU. */
324	bool fSupported;
325
326	/** Set when we've enabled VMX. */
327	bool fEnabled;
328
329	/** Set if VPID is supported. */
330	bool fVPID;
331
332	/** Set if VT-x VPID is allowed. */
333	bool fAllowVPID;
334
335	/** Set if unrestricted guest execution is allowed (real and protected mode without paging). */
336	bool fUnrestrictedGuest;
337
338	/** Whether we're using the preemption timer or not. */
339	bool fUsePreemptTimer;
340	/** The shift mask employed by the VMX-Preemption timer. */
341	uint8_t cPreemptTimerShift;
342
343	bool uAlignment[1];
344
345	/** Virtual address of the TSS page used for real mode emulation. */
346	R3PTRTYPE(PVBOXTSS) pRealModeTSS;
347
348	/** Virtual address of the identity page table used for real mode and protected mode without paging emulation in EPT mode. */
349	R3PTRTYPE(PX86PD) pNonPagingModeEPTPageTable;
350
351	/** R0 memory object for the APIC physical page (serves for filtering accesses). */
352	RTR0MEMOBJ pMemObjAPIC;
353	/** Physical address of the APIC physical page (serves for filtering accesses). */
354	RTHCPHYS pAPICPhys;
355	/** Virtual address of the APIC physical page (serves for filtering accesses). */
356	R0PTRTYPE(uint8_t *) pAPIC;
357
358	/** R0 memory object for the MSR entry load page (guest MSRs). */
359	RTR0MEMOBJ pMemObjMSREntryLoad;
360	/** Physical address of the MSR entry load page (guest MSRs). */
361	RTHCPHYS pMSREntryLoadPhys;
362	/** Virtual address of the MSR entry load page (guest MSRs). */
363	R0PTRTYPE(uint8_t *) pMSREntryLoad;
364
365	#ifdef VBOX_WITH_CRASHDUMP_MAGIC
366	RTR0MEMOBJ pMemObjScratch;
367	RTHCPHYS pScratchPhys;
368	R0PTRTYPE(uint8_t *) pScratch;
369	#endif
370	/** R0 memory object for the MSR exit store page (guest MSRs). */
371	RTR0MEMOBJ pMemObjMSRExitStore;
372	/** Physical address of the MSR exit store page (guest MSRs). */
373	RTHCPHYS pMSRExitStorePhys;
374	/** Virtual address of the MSR exit store page (guest MSRs). */
375	R0PTRTYPE(uint8_t *) pMSRExitStore;
376
377	/** R0 memory object for the MSR exit load page (host MSRs). */
378	RTR0MEMOBJ pMemObjMSRExitLoad;
379	/** Physical address of the MSR exit load page (host MSRs). */
380	RTHCPHYS pMSRExitLoadPhys;
381	/** Virtual address of the MSR exit load page (host MSRs). */
382	R0PTRTYPE(uint8_t *) pMSRExitLoad;
383
384	/** Ring 0 handlers for VT-x. */
385	DECLR0CALLBACKMEMBER(void, pfnSetupTaggedTLB, (PVM pVM, PVMCPU pVCpu));
386
387	#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
388	uint32_t u32Alignment;
389	#endif
390	/** Host CR4 value (set by ring-0 VMX init) */
391	uint64_t hostCR4;
392
393	/** Host EFER value (set by ring-0 VMX init) */
394	uint64_t hostEFER;
395
396	/** VMX MSR values */
397	struct
398	{
399	uint64_t feature_ctrl;
400	uint64_t vmx_basic_info;
401	VMX_CAPABILITY vmx_pin_ctls;
402	VMX_CAPABILITY vmx_proc_ctls;
403	VMX_CAPABILITY vmx_proc_ctls2;
404	VMX_CAPABILITY vmx_exit;
405	VMX_CAPABILITY vmx_entry;
406	uint64_t vmx_misc;
407	uint64_t vmx_cr0_fixed0;
408	uint64_t vmx_cr0_fixed1;
409	uint64_t vmx_cr4_fixed0;
410	uint64_t vmx_cr4_fixed1;
411	uint64_t vmx_vmcs_enum;
412	uint64_t vmx_eptcaps;
413	} msr;
414
415	/** Flush types for invept & invvpid; they depend on capabilities. */
416	VMX_FLUSH enmFlushPage;
417	VMX_FLUSH enmFlushContext;
418	} vmx;
419
420	struct
421	{
422	/** Set by the ring-0 driver to indicate SVM is supported by the CPU. */
423	bool fSupported;
424	/** Set when we've enabled SVM. */
425	bool fEnabled;
426	/** Set if erratum 170 affects the AMD cpu. */
427	bool fAlwaysFlushTLB;
428	/** Set when the hack to ignore VERR_SVM_IN_USE is active. */
429	bool fIgnoreInUseError;
430
431	/** R0 memory object for the IO bitmap (12kb). */
432	RTR0MEMOBJ pMemObjIOBitmap;
433	/** Physical address of the IO bitmap (12kb). */
434	RTHCPHYS pIOBitmapPhys;
435	/** Virtual address of the IO bitmap. */
436	R0PTRTYPE(void *) pIOBitmap;
437
438	/* HWCR msr (for diagnostics) */
439	uint64_t msrHWCR;
440
441	/** SVM revision. */
442	uint32_t u32Rev;
443
444	/** SVM feature bits from cpuid 0x8000000a */
445	uint32_t u32Features;
446	} svm;
447
448	/**
449	* AVL tree with all patches (active or disabled) sorted by guest instruction address
450	*/
451	AVLOU32TREE PatchTree;
452	uint32_t cPatches;
453	HWACCMTPRPATCH aPatches[64];
454
455	struct
456	{
457	uint32_t u32AMDFeatureECX;
458	uint32_t u32AMDFeatureEDX;
459	} cpuid;
460
461	/** Saved error from detection */
462	int32_t lLastError;
463
464	/** HWACCMR0Init was run */
465	bool fHWACCMR0Init;
466	bool u8Alignment1[7];
467
468	STAMCOUNTER StatTPRPatchSuccess;
469	STAMCOUNTER StatTPRPatchFailure;
470	STAMCOUNTER StatTPRReplaceSuccess;
471	STAMCOUNTER StatTPRReplaceFailure;
472	} HWACCM;
473	/** Pointer to HWACCM VM instance data. */
474	typedef HWACCM *PHWACCM;
475
476	/* Maximum number of cached entries. */
477	#define VMCSCACHE_MAX_ENTRY 128
478
479	/* Structure for storing read and write VMCS actions. */
480	typedef struct VMCSCACHE
481	{
482	#ifdef VBOX_WITH_CRASHDUMP_MAGIC
483	/* Magic marker for searching in crash dumps. */
484	uint8_t aMagic[16];
485	uint64_t uMagic;
486	uint64_t u64TimeEntry;
487	uint64_t u64TimeSwitch;
488	uint64_t cResume;
489	uint64_t interPD;
490	uint64_t pSwitcher;
491	uint32_t uPos;
492	uint32_t idCpu;
493	#endif
494	/* CR2 is saved here for EPT syncing. */
495	uint64_t cr2;
496	struct
497	{
498	uint32_t cValidEntries;
499	uint32_t uAlignment;
500	uint32_t aField[VMCSCACHE_MAX_ENTRY];
501	uint64_t aFieldVal[VMCSCACHE_MAX_ENTRY];
502	} Write;
503	struct
504	{
505	uint32_t cValidEntries;
506	uint32_t uAlignment;
507	uint32_t aField[VMCSCACHE_MAX_ENTRY];
508	uint64_t aFieldVal[VMCSCACHE_MAX_ENTRY];
509	} Read;
510	#ifdef DEBUG
511	struct
512	{
513	RTHCPHYS pPageCpuPhys;
514	RTHCPHYS pVMCSPhys;
515	RTGCPTR pCache;
516	RTGCPTR pCtx;
517	} TestIn;
518	struct
519	{
520	RTHCPHYS pVMCSPhys;
521	RTGCPTR pCache;
522	RTGCPTR pCtx;
523	uint64_t eflags;
524	uint64_t cr8;
525	} TestOut;
526	struct
527	{
528	uint64_t param1;
529	uint64_t param2;
530	uint64_t param3;
531	uint64_t param4;
532	} ScratchPad;
533	#endif
534	} VMCSCACHE;
535	/** Pointer to VMCSCACHE. */
536	typedef VMCSCACHE *PVMCSCACHE;
537
538	/** VMX StartVM function. */
539	typedef DECLCALLBACK(int) FNHWACCMVMXSTARTVM(RTHCUINT fResume, PCPUMCTX pCtx, PVMCSCACHE pCache, PVM pVM, PVMCPU pVCpu);
540	/** Pointer to a VMX StartVM function. */
541	typedef R0PTRTYPE(FNHWACCMVMXSTARTVM *) PFNHWACCMVMXSTARTVM;
542
543	/** SVM VMRun function. */
544	typedef DECLCALLBACK(int) FNHWACCMSVMVMRUN(RTHCPHYS pVMCBHostPhys, RTHCPHYS pVMCBPhys, PCPUMCTX pCtx, PVM pVM, PVMCPU pVCpu);
545	/** Pointer to a SVM VMRun function. */
546	typedef R0PTRTYPE(FNHWACCMSVMVMRUN *) PFNHWACCMSVMVMRUN;
547
548	/**
549	* HWACCM VMCPU Instance data.
550	*/
551	typedef struct HWACCMCPU
552	{
553	/** Old style FPU reporting trap mask override performed (optimization) */
554	bool fFPUOldStyleOverride;
555
556	/** Set if we don't have to flush the TLB on VM entry. */
557	bool fResumeVM;
558
559	/** Set if we need to flush the TLB during the world switch. */
560	bool fForceTLBFlush;
561
562	/** Set when we're using VT-x or AMD-V at that moment. */
563	bool fActive;
564
565	/** Set when the TLB has been checked until we return from the world switch. */
566	volatile uint8_t fCheckedTLBFlush;
567	uint8_t bAlignment[3];
568
569	/** HWACCM_CHANGED_* flags. */
570	RTUINT fContextUseFlags;
571
572	/** Id of the last cpu we were executing code on (NIL_RTCPUID for the first time) */
573	RTCPUID idLastCpu;
574
575	/** TLB flush count */
576	RTUINT cTLBFlushes;
577
578	/** Current ASID in use by the VM */
579	RTUINT uCurrentASID;
580
581	/** World switch exit counter. */
582	volatile uint32_t cWorldSwitchExit;
583	uint32_t u32Alignment;
584
585	struct
586	{
587	/** Physical address of the VM control structure (VMCS). */
588	RTHCPHYS pVMCSPhys;
589	/** R0 memory object for the VM control structure (VMCS). */
590	RTR0MEMOBJ pMemObjVMCS;
591	/** Virtual address of the VM control structure (VMCS). */
592	R0PTRTYPE(void *) pVMCS;
593
594	/** Ring 0 handlers for VT-x. */
595	PFNHWACCMVMXSTARTVM pfnStartVM;
596
597	#if HC_ARCH_BITS == 32
598	uint32_t u32Alignment;
599	#endif
600
601	/** Current VMX_VMCS_CTRL_PROC_EXEC_CONTROLS. */
602	uint64_t proc_ctls;
603
604	/** Current VMX_VMCS_CTRL_PROC_EXEC2_CONTROLS. */
605	uint64_t proc_ctls2;
606
607	/** Physical address of the virtual APIC page for TPR caching. */
608	RTHCPHYS pVAPICPhys;
609	/** R0 memory object for the virtual APIC page for TPR caching. */
610	RTR0MEMOBJ pMemObjVAPIC;
611	/** Virtual address of the virtual APIC page for TPR caching. */
612	R0PTRTYPE(uint8_t *) pVAPIC;
613
614	/** Current CR0 mask. */
615	uint64_t cr0_mask;
616	/** Current CR4 mask. */
617	uint64_t cr4_mask;
618
619	/** Current EPTP. */
620	RTHCPHYS GCPhysEPTP;
621
622	/** Physical address of the MSR bitmap (1 page). */
623	RTHCPHYS pMSRBitmapPhys;
624	/** R0 memory object for the MSR bitmap (1 page). */
625	RTR0MEMOBJ pMemObjMSRBitmap;
626	/** Virtual address of the MSR bitmap (1 page). */
627	R0PTRTYPE(uint8_t *) pMSRBitmap;
628
629	#ifdef VBOX_WITH_AUTO_MSR_LOAD_RESTORE
630	/** Physical address of the guest MSR load area (1 page). */
631	RTHCPHYS pGuestMSRPhys;
632	/** R0 memory object for the guest MSR load area (1 page). */
633	RTR0MEMOBJ pMemObjGuestMSR;
634	/** Virtual address of the guest MSR load area (1 page). */
635	R0PTRTYPE(uint8_t *) pGuestMSR;
636
637	/** Physical address of the MSR load area (1 page). */
638	RTHCPHYS pHostMSRPhys;
639	/** R0 memory object for the MSR load area (1 page). */
640	RTR0MEMOBJ pMemObjHostMSR;
641	/** Virtual address of the MSR load area (1 page). */
642	R0PTRTYPE(uint8_t *) pHostMSR;
643	#endif /* VBOX_WITH_AUTO_MSR_LOAD_RESTORE */
644
645	/* Number of automatically loaded/restored MSRs. */
646	uint32_t cCachedMSRs;
647	uint32_t uAlignement;
648
649	/* Last use TSC offset value. (cached) */
650	uint64_t u64TSCOffset;
651
652	/** VMCS cache. */
653	VMCSCACHE VMCSCache;
654
655	/** Real-mode emulation state. */
656	struct
657	{
658	X86EFLAGS eflags;
659	uint32_t fValid;
660	} RealMode;
661
662	struct
663	{
664	uint64_t u64VMCSPhys;
665	uint32_t ulVMCSRevision;
666	uint32_t ulInstrError;
667	uint32_t ulExitReason;
668	RTCPUID idEnteredCpu;
669	RTCPUID idCurrentCpu;
670	uint32_t padding;
671	} lasterror;
672
673	/** The last seen guest paging mode (by VT-x). */
674	PGMMODE enmLastSeenGuestMode;
675	/** Current guest paging mode (as seen by HWACCMR3PagingModeChanged). */
676	PGMMODE enmCurrGuestMode;
677	/** Previous guest paging mode (as seen by HWACCMR3PagingModeChanged). */
678	PGMMODE enmPrevGuestMode;
679	} vmx;
680
681	struct
682	{
683	/** R0 memory object for the host VM control block (VMCB). */
684	RTR0MEMOBJ pMemObjVMCBHost;
685	/** Physical address of the host VM control block (VMCB). */
686	RTHCPHYS pVMCBHostPhys;
687	/** Virtual address of the host VM control block (VMCB). */
688	R0PTRTYPE(void *) pVMCBHost;
689
690	/** R0 memory object for the VM control block (VMCB). */
691	RTR0MEMOBJ pMemObjVMCB;
692	/** Physical address of the VM control block (VMCB). */
693	RTHCPHYS pVMCBPhys;
694	/** Virtual address of the VM control block (VMCB). */
695	R0PTRTYPE(void *) pVMCB;
696
697	/** Ring 0 handlers for VT-x. */
698	PFNHWACCMSVMVMRUN pfnVMRun;
699
700	/** R0 memory object for the MSR bitmap (8kb). */
701	RTR0MEMOBJ pMemObjMSRBitmap;
702	/** Physical address of the MSR bitmap (8kb). */
703	RTHCPHYS pMSRBitmapPhys;
704	/** Virtual address of the MSR bitmap. */
705	R0PTRTYPE(void *) pMSRBitmap;
706	} svm;
707
708	/** Event injection state. */
709	struct
710	{
711	uint32_t fPending;
712	uint32_t errCode;
713	uint64_t intInfo;
714	} Event;
715
716	/** IO Block emulation state. */
717	struct
718	{
719	bool fEnabled;
720	uint8_t u8Align[7];
721
722	/** RIP at the start of the io code we wish to emulate in the recompiler. */
723	RTGCPTR GCPtrFunctionEip;
724
725	uint64_t cr0;
726	} EmulateIoBlock;
727
728	struct
729	{
730	/* Pending IO operation type. */
731	HWACCMPENDINGIO enmType;
732	uint32_t uPadding;
733	RTGCPTR GCPtrRip;
734	RTGCPTR GCPtrRipNext;
735	union
736	{
737	struct
738	{
739	unsigned uPort;
740	unsigned uAndVal;
741	unsigned cbSize;
742	} Port;
743	uint64_t aRaw[2];
744	} s;
745	} PendingIO;
746
747	/** Currently shadow paging mode. */
748	PGMMODE enmShadowMode;
749
750	/** The CPU ID of the CPU currently owning the VMCS. Set in
751	* HWACCMR0Enter and cleared in HWACCMR0Leave. */
752	RTCPUID idEnteredCpu;
753
754	/** To keep track of pending TLB shootdown pages. (SMP guest only) */
755	struct
756	{
757	RTGCPTR aPages[HWACCM_MAX_TLB_SHOOTDOWN_PAGES];
758	unsigned cPages;
759	} TlbShootdown;
760
761	/** For saving stack space, the disassembler state is allocated here instead of
762	* on the stack.
763	* @note The DISCPUSTATE structure is not R3/R0/RZ clean! */
764	union
765	{
766	/** The disassembler scratch space. */
767	DISCPUSTATE DisState;
768	/** Padding. */
769	uint8_t abDisStatePadding[DISCPUSTATE_PADDING_SIZE];
770	};
771
772	RTUINT padding2[1];
773
774	STAMPROFILEADV StatEntry;
775	STAMPROFILEADV StatExit1;
776	STAMPROFILEADV StatExit2;
777	#if 1 /* temporary for tracking down darwin issues. */
778	STAMPROFILEADV StatExit2Sub1;
779	STAMPROFILEADV StatExit2Sub2;
780	STAMPROFILEADV StatExit2Sub3;
781	#endif
782	STAMPROFILEADV StatInGC;
783
784	#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
785	STAMPROFILEADV StatWorldSwitch3264;
786	#endif
787	STAMPROFILEADV StatPoke;
788	STAMPROFILEADV StatSpinPoke;
789	STAMPROFILEADV StatSpinPokeFailed;
790
791	STAMCOUNTER StatIntInject;
792
793	STAMCOUNTER StatExitShadowNM;
794	STAMCOUNTER StatExitGuestNM;
795	STAMCOUNTER StatExitShadowPF;
796	STAMCOUNTER StatExitGuestPF;
797	STAMCOUNTER StatExitGuestUD;
798	STAMCOUNTER StatExitGuestSS;
799	STAMCOUNTER StatExitGuestNP;
800	STAMCOUNTER StatExitGuestGP;
801	STAMCOUNTER StatExitGuestDE;
802	STAMCOUNTER StatExitGuestDB;
803	STAMCOUNTER StatExitGuestMF;
804	STAMCOUNTER StatExitInvpg;
805	STAMCOUNTER StatExitInvd;
806	STAMCOUNTER StatExitCpuid;
807	STAMCOUNTER StatExitRdtsc;
808	STAMCOUNTER StatExitRdpmc;
809	STAMCOUNTER StatExitCli;
810	STAMCOUNTER StatExitSti;
811	STAMCOUNTER StatExitPushf;
812	STAMCOUNTER StatExitPopf;
813	STAMCOUNTER StatExitIret;
814	STAMCOUNTER StatExitInt;
815	STAMCOUNTER StatExitCRxWrite[16];
816	STAMCOUNTER StatExitCRxRead[16];
817	STAMCOUNTER StatExitDRxWrite;
818	STAMCOUNTER StatExitDRxRead;
819	STAMCOUNTER StatExitRdmsr;
820	STAMCOUNTER StatExitWrmsr;
821	STAMCOUNTER StatExitCLTS;
822	STAMCOUNTER StatExitHlt;
823	STAMCOUNTER StatExitMwait;
824	STAMCOUNTER StatExitMonitor;
825	STAMCOUNTER StatExitLMSW;
826	STAMCOUNTER StatExitIOWrite;
827	STAMCOUNTER StatExitIORead;
828	STAMCOUNTER StatExitIOStringWrite;
829	STAMCOUNTER StatExitIOStringRead;
830	STAMCOUNTER StatExitIrqWindow;
831	STAMCOUNTER StatExitMaxResume;
832	STAMCOUNTER StatExitPreemptPending;
833	STAMCOUNTER StatIntReinject;
834	STAMCOUNTER StatPendingHostIrq;
835
836	STAMCOUNTER StatFlushPage;
837	STAMCOUNTER StatFlushPageManual;
838	STAMCOUNTER StatFlushPhysPageManual;
839	STAMCOUNTER StatFlushTLB;
840	STAMCOUNTER StatFlushTLBManual;
841	STAMCOUNTER StatFlushPageInvlpg;
842	STAMCOUNTER StatFlushTLBWorldSwitch;
843	STAMCOUNTER StatNoFlushTLBWorldSwitch;
844	STAMCOUNTER StatFlushTLBCRxChange;
845	STAMCOUNTER StatFlushASID;
846	STAMCOUNTER StatFlushTLBInvlpga;
847	STAMCOUNTER StatTlbShootdown;
848	STAMCOUNTER StatTlbShootdownFlush;
849
850	STAMCOUNTER StatSwitchGuestIrq;
851	STAMCOUNTER StatSwitchToR3;
852
853	STAMCOUNTER StatTSCOffset;
854	STAMCOUNTER StatTSCIntercept;
855	STAMCOUNTER StatTSCInterceptOverFlow;
856
857	STAMCOUNTER StatExitReasonNPF;
858	STAMCOUNTER StatDRxArmed;
859	STAMCOUNTER StatDRxContextSwitch;
860	STAMCOUNTER StatDRxIOCheck;
861
862	STAMCOUNTER StatLoadMinimal;
863	STAMCOUNTER StatLoadFull;
864
865	#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
866	STAMCOUNTER StatFpu64SwitchBack;
867	STAMCOUNTER StatDebug64SwitchBack;
868	#endif
869
870	#ifdef VBOX_WITH_STATISTICS
871	R3PTRTYPE(PSTAMCOUNTER) paStatExitReason;
872	R0PTRTYPE(PSTAMCOUNTER) paStatExitReasonR0;
873	R3PTRTYPE(PSTAMCOUNTER) paStatInjectedIrqs;
874	R0PTRTYPE(PSTAMCOUNTER) paStatInjectedIrqsR0;
875	#endif
876	} HWACCMCPU;
877	/** Pointer to HWACCM VM instance data. */
878	typedef HWACCMCPU *PHWACCMCPU;
879
880
881	#ifdef IN_RING0
882
883	VMMR0DECL(PHWACCM_CPUINFO) HWACCMR0GetCurrentCpu();
884	VMMR0DECL(PHWACCM_CPUINFO) HWACCMR0GetCurrentCpuEx(RTCPUID idCpu);
885
886
887	#ifdef VBOX_STRICT
888	VMMR0DECL(void) HWACCMDumpRegs(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
889	VMMR0DECL(void) HWACCMR0DumpDescriptor(PCX86DESCHC pDesc, RTSEL Sel, const char *pszMsg);
890	#else
891	# define HWACCMDumpRegs(a, b ,c) do { } while (0)
892	# define HWACCMR0DumpDescriptor(a, b, c) do { } while (0)
893	#endif
894
895	/* Dummy callback handlers. */
896	VMMR0DECL(int) HWACCMR0DummyEnter(PVM pVM, PVMCPU pVCpu, PHWACCM_CPUINFO pCpu);
897	VMMR0DECL(int) HWACCMR0DummyLeave(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
898	VMMR0DECL(int) HWACCMR0DummyEnableCpu(PHWACCM_CPUINFO pCpu, PVM pVM, void *pvPageCpu, RTHCPHYS pPageCpuPhys);
899	VMMR0DECL(int) HWACCMR0DummyDisableCpu(PHWACCM_CPUINFO pCpu, void *pvPageCpu, RTHCPHYS pPageCpuPhys);
900	VMMR0DECL(int) HWACCMR0DummyInitVM(PVM pVM);
901	VMMR0DECL(int) HWACCMR0DummyTermVM(PVM pVM);
902	VMMR0DECL(int) HWACCMR0DummySetupVM(PVM pVM);
903	VMMR0DECL(int) HWACCMR0DummyRunGuestCode(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
904	VMMR0DECL(int) HWACCMR0DummySaveHostState(PVM pVM, PVMCPU pVCpu);
905	VMMR0DECL(int) HWACCMR0DummyLoadGuestState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
906
907	# ifdef VBOX_WITH_KERNEL_USING_XMM
908	DECLASM(int) hwaccmR0VMXStartVMWrapXMM(RTHCUINT fResume, PCPUMCTX pCtx, PVMCSCACHE pCache, PVM pVM, PVMCPU pVCpu, PFNHWACCMVMXSTARTVM pfnStartVM);
909	DECLASM(int) hwaccmR0SVMRunWrapXMM(RTHCPHYS pVMCBHostPhys, RTHCPHYS pVMCBPhys, PCPUMCTX pCtx, PVM pVM, PVMCPU pVCpu, PFNHWACCMSVMVMRUN pfnVMRun);
910	# endif
911
912	# ifdef VBOX_WITH_HYBRID_32BIT_KERNEL
913	/**
914	* Gets 64-bit GDTR and IDTR on darwin.
915	* @param pGdtr Where to store the 64-bit GDTR.
916	* @param pIdtr Where to store the 64-bit IDTR.
917	*/
918	DECLASM(void) hwaccmR0Get64bitGDTRandIDTR(PX86XDTR64 pGdtr, PX86XDTR64 pIdtr);
919
920	/**
921	* Gets 64-bit CR3 on darwin.
922	* @returns CR3
923	*/
924	DECLASM(uint64_t) hwaccmR0Get64bitCR3(void);
925	# endif
926
927	#endif /* IN_RING0 */
928
929	/** @} */
930
931	RT_C_DECLS_END
932
933	#endif
934

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source: vbox/trunk/src/VBox/VMM/HWACCMInternal.h@ 34079

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