HWACCMInternal.h@ 8889

Last change on this file since 8889 was 8878, checked in by vboxsync, 17 years ago
Don't automatically flush the TLB when we remain on the same cpu (on entry).
Property svn:eol-style set to `native` Property svn:keywords set to `Id`
File size: 13.3 KB

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1	/* $Id: HWACCMInternal.h 8878 2008-05-16 10:59:52Z vboxsync $ */
2	/** @file
3	* HWACCM - Internal header file.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22	#ifndef ___HWACCMInternal_h
23	#define ___HWACCMInternal_h
24
25	#include <VBox/cdefs.h>
26	#include <VBox/types.h>
27	#include <VBox/em.h>
28	#include <VBox/stam.h>
29	#include <VBox/dis.h>
30	#include <VBox/hwaccm.h>
31	#include <VBox/pgm.h>
32	#include <iprt/memobj.h>
33	#include <iprt/cpuset.h>
34	#include <iprt/mp.h>
35
36	__BEGIN_DECLS
37
38
39	/** @defgroup grp_hwaccm_int Internal
40	* @ingroup grp_hwaccm
41	* @internal
42	* @{
43	*/
44
45
46	/**
47	* Converts a HWACCM pointer into a VM pointer.
48	* @returns Pointer to the VM structure the EM is part of.
49	* @param pHWACCM Pointer to HWACCM instance data.
50	*/
51	#define HWACCM2VM(pHWACCM) ( (PVM)((char*)pHWACCM - pHWACCM->offVM) )
52
53	/** Maximum number of exit reason statistics counters. */
54	#define MAX_EXITREASON_STAT 0x100
55	#define MASK_EXITREASON_STAT 0xff
56
57	/** @name Changed flags
58	* These flags are used to keep track of which important registers that
59	* have been changed since last they were reset.
60	* @{
61	*/
62	#define HWACCM_CHANGED_GUEST_FPU RT_BIT(0)
63	#define HWACCM_CHANGED_GUEST_CR0 RT_BIT(1)
64	#define HWACCM_CHANGED_GUEST_CR3 RT_BIT(2)
65	#define HWACCM_CHANGED_GUEST_CR4 RT_BIT(3)
66	#define HWACCM_CHANGED_GUEST_GDTR RT_BIT(4)
67	#define HWACCM_CHANGED_GUEST_IDTR RT_BIT(5)
68	#define HWACCM_CHANGED_GUEST_LDTR RT_BIT(6)
69	#define HWACCM_CHANGED_GUEST_TR RT_BIT(7)
70	#define HWACCM_CHANGED_GUEST_SYSENTER_MSR RT_BIT(8)
71	#define HWACCM_CHANGED_GUEST_SEGMENT_REGS RT_BIT(9)
72	#define HWACCM_CHANGED_GUEST_DEBUG RT_BIT(10)
73	#define HWACCM_CHANGED_HOST_CONTEXT RT_BIT(11)
74
75	#define HWACCM_CHANGED_ALL ( HWACCM_CHANGED_GUEST_SEGMENT_REGS \
76	\| HWACCM_CHANGED_GUEST_CR0 \
77	\| HWACCM_CHANGED_GUEST_CR3 \
78	\| HWACCM_CHANGED_GUEST_CR4 \
79	\| HWACCM_CHANGED_GUEST_GDTR \
80	\| HWACCM_CHANGED_GUEST_IDTR \
81	\| HWACCM_CHANGED_GUEST_LDTR \
82	\| HWACCM_CHANGED_GUEST_TR \
83	\| HWACCM_CHANGED_GUEST_SYSENTER_MSR \
84	\| HWACCM_CHANGED_GUEST_FPU \
85	\| HWACCM_CHANGED_GUEST_DEBUG \
86	\| HWACCM_CHANGED_HOST_CONTEXT)
87
88	#define HWACCM_CHANGED_ALL_GUEST ( HWACCM_CHANGED_GUEST_SEGMENT_REGS \
89	\| HWACCM_CHANGED_GUEST_CR0 \
90	\| HWACCM_CHANGED_GUEST_CR3 \
91	\| HWACCM_CHANGED_GUEST_CR4 \
92	\| HWACCM_CHANGED_GUEST_GDTR \
93	\| HWACCM_CHANGED_GUEST_IDTR \
94	\| HWACCM_CHANGED_GUEST_LDTR \
95	\| HWACCM_CHANGED_GUEST_TR \
96	\| HWACCM_CHANGED_GUEST_SYSENTER_MSR \
97	\| HWACCM_CHANGED_GUEST_DEBUG \
98	\| HWACCM_CHANGED_GUEST_FPU)
99
100	/** @} */
101
102	/** @name Intercepted traps
103	* Traps that need to be intercepted so we can correctly dispatch them to the guest if required.
104	* Currently #NM and #PF only
105	*/
106	#ifdef VBOX_STRICT
107	#define HWACCM_VMX_TRAP_MASK RT_BIT(0) \| RT_BIT(7) \| RT_BIT(14) \| RT_BIT(6) \| RT_BIT(11) \| RT_BIT(12) \| RT_BIT(13) \| RT_BIT(16)
108	#define HWACCM_SVM_TRAP_MASK HWACCM_VMX_TRAP_MASK
109	#else
110	#define HWACCM_VMX_TRAP_MASK RT_BIT(7) \| RT_BIT(14)
111	#define HWACCM_SVM_TRAP_MASK HWACCM_VMX_TRAP_MASK
112	#endif
113	/** @} */
114
115
116	/** Maxium resume loops allowed in ring 0 (safety precaution) */
117	#define HWACCM_MAX_RESUME_LOOPS 1024
118
119	/** HWACCM SSM version
120	*/
121	#define HWACCM_SSM_VERSION 3
122
123	/**
124	* HWACCM VM Instance data.
125	* Changes to this must checked against the padding of the cfgm union in VM!
126	*/
127	typedef struct HWACCM
128	{
129	/** Offset to the VM structure.
130	* See HWACCM2VM(). */
131	RTUINT offVM;
132
133	/** Set when we've initialized VMX or SVM. */
134	bool fInitialized;
135	/** Set when we're using VMX/SVN at that moment. */
136	bool fActive;
137
138	/** Set when hardware acceleration is allowed. */
139	bool fAllowed;
140
141	/** HWACCM_CHANGED_* flags. */
142	uint32_t fContextUseFlags;
143
144	/** Old style FPU reporting trap mask override performed (optimization) */
145	uint32_t fFPUOldStyleOverride;
146
147	struct
148	{
149	/** Set by the ring-0 driver to indicate VMX is supported by the CPU. */
150	bool fSupported;
151
152	/** Set when we've enabled VMX. */
153	bool fEnabled;
154
155	/** Set if we can use VMXResume to execute guest code. */
156	bool fResumeVM;
157
158	/** R0 memory object for the VM control structure (VMCS). */
159	RTR0MEMOBJ pMemObjVMCS;
160	/** Physical address of the VM control structure (VMCS). */
161	RTHCPHYS pVMCSPhys;
162	/** Virtual address of the VM control structure (VMCS). */
163	R0PTRTYPE(void *) pVMCS;
164
165	/** R0 memory object for the TSS page used for real mode emulation. */
166	RTR0MEMOBJ pMemObjRealModeTSS;
167	/** Physical address of the TSS page used for real mode emulation. */
168	RTHCPHYS pRealModeTSSPhys;
169	/** Virtual address of the TSS page used for real mode emulation. */
170	R0PTRTYPE(PVBOXTSS) pRealModeTSS;
171
172	/** Host CR4 value (set by ring-0 VMX init) */
173	uint64_t hostCR4;
174
175	/** Current VMX_VMCS_CTRL_PROC_EXEC_CONTROLS. */
176	uint64_t proc_ctls;
177
178	/** Current CR0 mask. */
179	uint64_t cr0_mask;
180	/** Current CR4 mask. */
181	uint64_t cr4_mask;
182
183	/** VMX MSR values */
184	struct
185	{
186	uint64_t feature_ctrl;
187	uint64_t vmx_basic_info;
188	uint64_t vmx_pin_ctls;
189	uint64_t vmx_proc_ctls;
190	uint64_t vmx_exit;
191	uint64_t vmx_entry;
192	uint64_t vmx_misc;
193	uint64_t vmx_cr0_fixed0;
194	uint64_t vmx_cr0_fixed1;
195	uint64_t vmx_cr4_fixed0;
196	uint64_t vmx_cr4_fixed1;
197	uint64_t vmx_vmcs_enum;
198	} msr;
199
200	/* Last instruction error */
201	uint32_t ulLastInstrError;
202	} vmx;
203
204	struct
205	{
206	/** Set by the ring-0 driver to indicate SVM is supported by the CPU. */
207	bool fSupported;
208	/** Set when we've enabled SVM. */
209	bool fEnabled;
210	/** Set if we don't have to flush the TLB on VM entry. */
211	bool fResumeVM;
212	/** Set if erratum 170 affects the AMD cpu. */
213	bool fAlwaysFlushTLB;
214	/** Set if we need to flush the TLB during the world switch. */
215	bool fForceTLBFlush;
216
217	/* Id of the last cpu we were executing code on (NIL_RTCPUID for the first time) */
218	RTCPUID idLastCpu;
219
220	/** R0 memory object for the VM control block (VMCB). */
221	RTR0MEMOBJ pMemObjVMCB;
222	/** Physical address of the VM control block (VMCB). */
223	RTHCPHYS pVMCBPhys;
224	/** Virtual address of the VM control block (VMCB). */
225	R0PTRTYPE(void *) pVMCB;
226
227	/** R0 memory object for the host VM control block (VMCB). */
228	RTR0MEMOBJ pMemObjVMCBHost;
229	/** Physical address of the host VM control block (VMCB). */
230	RTHCPHYS pVMCBHostPhys;
231	/** Virtual address of the host VM control block (VMCB). */
232	R0PTRTYPE(void *) pVMCBHost;
233
234	/** R0 memory object for the IO bitmap (12kb). */
235	RTR0MEMOBJ pMemObjIOBitmap;
236	/** Physical address of the IO bitmap (12kb). */
237	RTHCPHYS pIOBitmapPhys;
238	/** Virtual address of the IO bitmap. */
239	R0PTRTYPE(void *) pIOBitmap;
240
241	/** R0 memory object for the MSR bitmap (8kb). */
242	RTR0MEMOBJ pMemObjMSRBitmap;
243	/** Physical address of the MSR bitmap (8kb). */
244	RTHCPHYS pMSRBitmapPhys;
245	/** Virtual address of the MSR bitmap. */
246	R0PTRTYPE(void *) pMSRBitmap;
247
248	/** SVM revision. */
249	uint32_t u32Rev;
250
251	/** Maximum ASID allowed. */
252	uint32_t u32MaxASID;
253
254	/** SVM feature bits from cpuid 0x8000000a */
255	uint32_t u32Features;
256	} svm;
257
258	struct
259	{
260	uint32_t u32AMDFeatureECX;
261	uint32_t u32AMDFeatureEDX;
262	} cpuid;
263
264	/* Event injection state. */
265	struct
266	{
267	uint32_t fPending;
268	uint32_t errCode;
269	uint64_t intInfo;
270	} Event;
271
272	/** Saved error from detection */
273	int32_t lLastError;
274
275	/** HWACCMR0Init was run */
276	bool fHWACCMR0Init;
277
278	/** Currenty shadow paging mode. */
279	PGMMODE enmShadowMode;
280
281	STAMPROFILEADV StatEntry;
282	STAMPROFILEADV StatExit;
283	STAMPROFILEADV StatInGC;
284
285	STAMCOUNTER StatIntInject;
286
287	STAMCOUNTER StatExitShadowNM;
288	STAMCOUNTER StatExitGuestNM;
289	STAMCOUNTER StatExitShadowPF;
290	STAMCOUNTER StatExitGuestPF;
291	STAMCOUNTER StatExitGuestUD;
292	STAMCOUNTER StatExitGuestSS;
293	STAMCOUNTER StatExitGuestNP;
294	STAMCOUNTER StatExitGuestGP;
295	STAMCOUNTER StatExitGuestDE;
296	STAMCOUNTER StatExitGuestMF;
297	STAMCOUNTER StatExitInvpg;
298	STAMCOUNTER StatExitInvd;
299	STAMCOUNTER StatExitCpuid;
300	STAMCOUNTER StatExitRdtsc;
301	STAMCOUNTER StatExitCRxWrite;
302	STAMCOUNTER StatExitCRxRead;
303	STAMCOUNTER StatExitDRxWrite;
304	STAMCOUNTER StatExitDRxRead;
305	STAMCOUNTER StatExitCLTS;
306	STAMCOUNTER StatExitLMSW;
307	STAMCOUNTER StatExitIOWrite;
308	STAMCOUNTER StatExitIORead;
309	STAMCOUNTER StatExitIOStringWrite;
310	STAMCOUNTER StatExitIOStringRead;
311	STAMCOUNTER StatExitIrqWindow;
312	STAMCOUNTER StatExitMaxResume;
313	STAMCOUNTER StatIntReinject;
314	STAMCOUNTER StatPendingHostIrq;
315
316	STAMCOUNTER StatFlushPageManual;
317	STAMCOUNTER StatFlushTLBManual;
318	STAMCOUNTER StatFlushPageInvlpg;
319	STAMCOUNTER StatFlushTLBWorldSwitch;
320	STAMCOUNTER StatNoFlushTLBWorldSwitch;
321	STAMCOUNTER StatFlushTLBCRxChange;
322	STAMCOUNTER StatFlushASID;
323
324	STAMCOUNTER StatSwitchGuestIrq;
325	STAMCOUNTER StatSwitchToR3;
326
327	R3PTRTYPE(PSTAMCOUNTER) pStatExitReason;
328	R0PTRTYPE(PSTAMCOUNTER) pStatExitReasonR0;
329	} HWACCM;
330	/** Pointer to HWACCM VM instance data. */
331	typedef HWACCM *PHWACCM;
332
333	typedef struct
334	{
335	RTCPUID idCpu;
336
337	RTR0MEMOBJ pMemObj;
338	/* Current ASID (AMD-V only) */
339	uint32_t uCurrentASID;
340
341	bool fVMXConfigured;
342	bool fSVMConfigured;
343	} HWACCM_CPUINFO;
344	typedef HWACCM_CPUINFO *PHWACCM_CPUINFO;
345
346	#ifdef IN_RING0
347
348	#ifdef VBOX_STRICT
349	HWACCMR0DECL(void) HWACCMDumpRegs(PCPUMCTX pCtx);
350	HWACCMR0DECL(void) HWACCMR0DumpDescriptor(PX86DESCHC Desc, RTSEL Sel, const char *pszMsg);
351	#else
352	#define HWACCMDumpRegs(a) do { } while (0)
353	#define HWACCMR0DumpDescriptor(a, b, c) do { } while (0)
354	#endif
355
356	#endif
357
358	/** @} */
359
360	__END_DECLS
361
362	#endif
363

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source: vbox/trunk/src/VBox/VMM/HWACCMInternal.h@ 8889

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