| 1 | /* $Id: HWACCMInternal.h 8943 2008-05-20 09:15:53Z vboxsync $ */
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| 2 | /** @file
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| 3 | * HWACCM - Internal header file.
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| 4 | */
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| 5 |
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| 6 | /*
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| 7 | * Copyright (C) 2006-2007 Sun Microsystems, Inc.
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| 8 | *
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| 9 | * This file is part of VirtualBox Open Source Edition (OSE), as
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| 10 | * available from http://www.virtualbox.org. This file is free software;
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| 11 | * you can redistribute it and/or modify it under the terms of the GNU
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| 12 | * General Public License (GPL) as published by the Free Software
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| 13 | * Foundation, in version 2 as it comes in the "COPYING" file of the
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| 14 | * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
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| 15 | * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
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| 16 | *
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| 17 | * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
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| 18 | * Clara, CA 95054 USA or visit http://www.sun.com if you need
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| 19 | * additional information or have any questions.
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| 20 | */
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| 21 |
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| 22 | #ifndef ___HWACCMInternal_h
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| 23 | #define ___HWACCMInternal_h
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| 24 |
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| 25 | #include <VBox/cdefs.h>
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| 26 | #include <VBox/types.h>
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| 27 | #include <VBox/em.h>
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| 28 | #include <VBox/stam.h>
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| 29 | #include <VBox/dis.h>
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| 30 | #include <VBox/hwaccm.h>
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| 31 | #include <VBox/pgm.h>
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| 32 | #include <iprt/memobj.h>
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| 33 | #include <iprt/cpuset.h>
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| 34 | #include <iprt/mp.h>
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| 35 |
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| 36 | __BEGIN_DECLS
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| 37 |
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| 38 |
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| 39 | /** @defgroup grp_hwaccm_int Internal
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| 40 | * @ingroup grp_hwaccm
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| 41 | * @internal
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| 42 | * @{
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| 43 | */
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| 44 |
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| 45 |
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| 46 | /**
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| 47 | * Converts a HWACCM pointer into a VM pointer.
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| 48 | * @returns Pointer to the VM structure the EM is part of.
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| 49 | * @param pHWACCM Pointer to HWACCM instance data.
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| 50 | */
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| 51 | #define HWACCM2VM(pHWACCM) ( (PVM)((char*)pHWACCM - pHWACCM->offVM) )
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| 52 |
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| 53 | /** Maximum number of exit reason statistics counters. */
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| 54 | #define MAX_EXITREASON_STAT 0x100
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| 55 | #define MASK_EXITREASON_STAT 0xff
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| 56 |
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| 57 | /** @name Changed flags
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| 58 | * These flags are used to keep track of which important registers that
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| 59 | * have been changed since last they were reset.
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| 60 | * @{
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| 61 | */
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| 62 | #define HWACCM_CHANGED_GUEST_FPU RT_BIT(0)
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| 63 | #define HWACCM_CHANGED_GUEST_CR0 RT_BIT(1)
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| 64 | #define HWACCM_CHANGED_GUEST_CR3 RT_BIT(2)
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| 65 | #define HWACCM_CHANGED_GUEST_CR4 RT_BIT(3)
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| 66 | #define HWACCM_CHANGED_GUEST_GDTR RT_BIT(4)
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| 67 | #define HWACCM_CHANGED_GUEST_IDTR RT_BIT(5)
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| 68 | #define HWACCM_CHANGED_GUEST_LDTR RT_BIT(6)
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| 69 | #define HWACCM_CHANGED_GUEST_TR RT_BIT(7)
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| 70 | #define HWACCM_CHANGED_GUEST_SYSENTER_MSR RT_BIT(8)
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| 71 | #define HWACCM_CHANGED_GUEST_SEGMENT_REGS RT_BIT(9)
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| 72 | #define HWACCM_CHANGED_GUEST_DEBUG RT_BIT(10)
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| 73 | #define HWACCM_CHANGED_HOST_CONTEXT RT_BIT(11)
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| 74 |
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| 75 | #define HWACCM_CHANGED_ALL ( HWACCM_CHANGED_GUEST_SEGMENT_REGS \
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| 76 | | HWACCM_CHANGED_GUEST_CR0 \
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| 77 | | HWACCM_CHANGED_GUEST_CR3 \
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| 78 | | HWACCM_CHANGED_GUEST_CR4 \
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| 79 | | HWACCM_CHANGED_GUEST_GDTR \
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| 80 | | HWACCM_CHANGED_GUEST_IDTR \
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| 81 | | HWACCM_CHANGED_GUEST_LDTR \
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| 82 | | HWACCM_CHANGED_GUEST_TR \
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| 83 | | HWACCM_CHANGED_GUEST_SYSENTER_MSR \
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| 84 | | HWACCM_CHANGED_GUEST_FPU \
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| 85 | | HWACCM_CHANGED_GUEST_DEBUG \
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| 86 | | HWACCM_CHANGED_HOST_CONTEXT)
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| 87 |
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| 88 | #define HWACCM_CHANGED_ALL_GUEST ( HWACCM_CHANGED_GUEST_SEGMENT_REGS \
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| 89 | | HWACCM_CHANGED_GUEST_CR0 \
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| 90 | | HWACCM_CHANGED_GUEST_CR3 \
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| 91 | | HWACCM_CHANGED_GUEST_CR4 \
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| 92 | | HWACCM_CHANGED_GUEST_GDTR \
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| 93 | | HWACCM_CHANGED_GUEST_IDTR \
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| 94 | | HWACCM_CHANGED_GUEST_LDTR \
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| 95 | | HWACCM_CHANGED_GUEST_TR \
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| 96 | | HWACCM_CHANGED_GUEST_SYSENTER_MSR \
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| 97 | | HWACCM_CHANGED_GUEST_DEBUG \
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| 98 | | HWACCM_CHANGED_GUEST_FPU)
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| 99 |
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| 100 | /** @} */
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| 101 |
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| 102 | /** @name Intercepted traps
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| 103 | * Traps that need to be intercepted so we can correctly dispatch them to the guest if required.
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| 104 | * Currently #NM and #PF only
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| 105 | */
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| 106 | #ifdef VBOX_STRICT
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| 107 | #define HWACCM_VMX_TRAP_MASK RT_BIT(0) | RT_BIT(7) | RT_BIT(14) | RT_BIT(6) | RT_BIT(11) | RT_BIT(12) | RT_BIT(13) | RT_BIT(16)
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| 108 | #define HWACCM_SVM_TRAP_MASK HWACCM_VMX_TRAP_MASK
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| 109 | #else
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| 110 | #define HWACCM_VMX_TRAP_MASK RT_BIT(7) | RT_BIT(14)
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| 111 | #define HWACCM_SVM_TRAP_MASK HWACCM_VMX_TRAP_MASK
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| 112 | #endif
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| 113 | /** @} */
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| 114 |
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| 115 |
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| 116 | /** Maxium resume loops allowed in ring 0 (safety precaution) */
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| 117 | #define HWACCM_MAX_RESUME_LOOPS 1024
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| 118 |
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| 119 | /** HWACCM SSM version
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| 120 | */
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| 121 | #define HWACCM_SSM_VERSION 3
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| 122 |
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| 123 | /**
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| 124 | * HWACCM VM Instance data.
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| 125 | * Changes to this must checked against the padding of the cfgm union in VM!
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| 126 | */
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| 127 | typedef struct HWACCM
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| 128 | {
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| 129 | /** Offset to the VM structure.
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| 130 | * See HWACCM2VM(). */
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| 131 | RTUINT offVM;
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| 132 |
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| 133 | /** Set when we've initialized VMX or SVM. */
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| 134 | bool fInitialized;
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| 135 | /** Set when we're using VMX/SVN at that moment. */
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| 136 | bool fActive;
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| 137 |
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| 138 | /** Set when hardware acceleration is allowed. */
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| 139 | bool fAllowed;
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| 140 |
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| 141 | /** HWACCM_CHANGED_* flags. */
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| 142 | uint32_t fContextUseFlags;
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| 143 |
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| 144 | /** Old style FPU reporting trap mask override performed (optimization) */
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| 145 | uint32_t fFPUOldStyleOverride;
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| 146 |
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| 147 | struct
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| 148 | {
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| 149 | /** Set by the ring-0 driver to indicate VMX is supported by the CPU. */
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| 150 | bool fSupported;
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| 151 |
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| 152 | /** Set when we've enabled VMX. */
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| 153 | bool fEnabled;
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| 154 |
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| 155 | /** Set if we can use VMXResume to execute guest code. */
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| 156 | bool fResumeVM;
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| 157 |
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| 158 | /** R0 memory object for the VM control structure (VMCS). */
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| 159 | RTR0MEMOBJ pMemObjVMCS;
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| 160 | /** Physical address of the VM control structure (VMCS). */
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| 161 | RTHCPHYS pVMCSPhys;
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| 162 | /** Virtual address of the VM control structure (VMCS). */
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| 163 | R0PTRTYPE(void *) pVMCS;
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| 164 |
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| 165 | /** R0 memory object for the TSS page used for real mode emulation. */
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| 166 | RTR0MEMOBJ pMemObjRealModeTSS;
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| 167 | /** Physical address of the TSS page used for real mode emulation. */
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| 168 | RTHCPHYS pRealModeTSSPhys;
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| 169 | /** Virtual address of the TSS page used for real mode emulation. */
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| 170 | R0PTRTYPE(PVBOXTSS) pRealModeTSS;
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| 171 |
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| 172 | /** Host CR4 value (set by ring-0 VMX init) */
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| 173 | uint64_t hostCR4;
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| 174 |
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| 175 | /** Current VMX_VMCS_CTRL_PROC_EXEC_CONTROLS. */
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| 176 | uint64_t proc_ctls;
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| 177 |
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| 178 | /** Current CR0 mask. */
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| 179 | uint64_t cr0_mask;
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| 180 | /** Current CR4 mask. */
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| 181 | uint64_t cr4_mask;
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| 182 |
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| 183 | /** VMX MSR values */
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| 184 | struct
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| 185 | {
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| 186 | uint64_t feature_ctrl;
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| 187 | uint64_t vmx_basic_info;
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| 188 | uint64_t vmx_pin_ctls;
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| 189 | uint64_t vmx_proc_ctls;
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| 190 | uint64_t vmx_exit;
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| 191 | uint64_t vmx_entry;
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| 192 | uint64_t vmx_misc;
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| 193 | uint64_t vmx_cr0_fixed0;
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| 194 | uint64_t vmx_cr0_fixed1;
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| 195 | uint64_t vmx_cr4_fixed0;
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| 196 | uint64_t vmx_cr4_fixed1;
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| 197 | uint64_t vmx_vmcs_enum;
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| 198 | } msr;
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| 199 |
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| 200 | /* Last instruction error */
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| 201 | uint32_t ulLastInstrError;
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| 202 | } vmx;
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| 203 |
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| 204 | struct
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| 205 | {
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| 206 | /** Set by the ring-0 driver to indicate SVM is supported by the CPU. */
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| 207 | bool fSupported;
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| 208 | /** Set when we've enabled SVM. */
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| 209 | bool fEnabled;
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| 210 | /** Set if we don't have to flush the TLB on VM entry. */
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| 211 | bool fResumeVM;
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| 212 | /** Set if erratum 170 affects the AMD cpu. */
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| 213 | bool fAlwaysFlushTLB;
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| 214 | /** Set if we need to flush the TLB during the world switch. */
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| 215 | bool fForceTLBFlush;
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| 216 | /** Set if nested paging is enabled. */
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| 217 | bool fNestedPaging;
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| 218 |
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| 219 | /* Id of the last cpu we were executing code on (NIL_RTCPUID for the first time) */
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| 220 | RTCPUID idLastCpu;
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| 221 |
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| 222 | /* TLB flush count */
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| 223 | uint32_t cTLBFlushes;
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| 224 |
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| 225 | /** R0 memory object for the VM control block (VMCB). */
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| 226 | RTR0MEMOBJ pMemObjVMCB;
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| 227 | /** Physical address of the VM control block (VMCB). */
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| 228 | RTHCPHYS pVMCBPhys;
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| 229 | /** Virtual address of the VM control block (VMCB). */
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| 230 | R0PTRTYPE(void *) pVMCB;
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| 231 |
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| 232 | /** R0 memory object for the host VM control block (VMCB). */
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| 233 | RTR0MEMOBJ pMemObjVMCBHost;
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| 234 | /** Physical address of the host VM control block (VMCB). */
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| 235 | RTHCPHYS pVMCBHostPhys;
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| 236 | /** Virtual address of the host VM control block (VMCB). */
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| 237 | R0PTRTYPE(void *) pVMCBHost;
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| 238 |
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| 239 | /** R0 memory object for the IO bitmap (12kb). */
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| 240 | RTR0MEMOBJ pMemObjIOBitmap;
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| 241 | /** Physical address of the IO bitmap (12kb). */
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| 242 | RTHCPHYS pIOBitmapPhys;
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| 243 | /** Virtual address of the IO bitmap. */
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| 244 | R0PTRTYPE(void *) pIOBitmap;
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| 245 |
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| 246 | /** R0 memory object for the MSR bitmap (8kb). */
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| 247 | RTR0MEMOBJ pMemObjMSRBitmap;
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| 248 | /** Physical address of the MSR bitmap (8kb). */
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| 249 | RTHCPHYS pMSRBitmapPhys;
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| 250 | /** Virtual address of the MSR bitmap. */
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| 251 | R0PTRTYPE(void *) pMSRBitmap;
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| 252 |
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| 253 | /** SVM revision. */
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| 254 | uint32_t u32Rev;
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| 255 |
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| 256 | /** Maximum ASID allowed. */
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| 257 | uint32_t u32MaxASID;
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| 258 |
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| 259 | /** SVM feature bits from cpuid 0x8000000a */
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| 260 | uint32_t u32Features;
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| 261 | } svm;
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| 262 |
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| 263 | struct
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| 264 | {
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| 265 | uint32_t u32AMDFeatureECX;
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| 266 | uint32_t u32AMDFeatureEDX;
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| 267 | } cpuid;
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| 268 |
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| 269 | /* Event injection state. */
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| 270 | struct
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| 271 | {
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| 272 | uint32_t fPending;
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| 273 | uint32_t errCode;
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| 274 | uint64_t intInfo;
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| 275 | } Event;
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| 276 |
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| 277 | /** Saved error from detection */
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| 278 | int32_t lLastError;
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| 279 |
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| 280 | /** HWACCMR0Init was run */
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| 281 | bool fHWACCMR0Init;
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| 282 |
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| 283 | /** Currenty shadow paging mode. */
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| 284 | PGMMODE enmShadowMode;
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| 285 |
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| 286 | STAMPROFILEADV StatEntry;
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| 287 | STAMPROFILEADV StatExit;
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| 288 | STAMPROFILEADV StatInGC;
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| 289 |
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| 290 | STAMCOUNTER StatIntInject;
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| 291 |
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| 292 | STAMCOUNTER StatExitShadowNM;
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| 293 | STAMCOUNTER StatExitGuestNM;
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| 294 | STAMCOUNTER StatExitShadowPF;
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| 295 | STAMCOUNTER StatExitGuestPF;
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| 296 | STAMCOUNTER StatExitGuestUD;
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| 297 | STAMCOUNTER StatExitGuestSS;
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| 298 | STAMCOUNTER StatExitGuestNP;
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| 299 | STAMCOUNTER StatExitGuestGP;
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| 300 | STAMCOUNTER StatExitGuestDE;
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| 301 | STAMCOUNTER StatExitGuestMF;
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| 302 | STAMCOUNTER StatExitInvpg;
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| 303 | STAMCOUNTER StatExitInvd;
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| 304 | STAMCOUNTER StatExitCpuid;
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| 305 | STAMCOUNTER StatExitRdtsc;
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| 306 | STAMCOUNTER StatExitCRxWrite;
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| 307 | STAMCOUNTER StatExitCRxRead;
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| 308 | STAMCOUNTER StatExitDRxWrite;
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| 309 | STAMCOUNTER StatExitDRxRead;
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| 310 | STAMCOUNTER StatExitCLTS;
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| 311 | STAMCOUNTER StatExitLMSW;
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| 312 | STAMCOUNTER StatExitIOWrite;
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| 313 | STAMCOUNTER StatExitIORead;
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| 314 | STAMCOUNTER StatExitIOStringWrite;
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| 315 | STAMCOUNTER StatExitIOStringRead;
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| 316 | STAMCOUNTER StatExitIrqWindow;
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| 317 | STAMCOUNTER StatExitMaxResume;
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| 318 | STAMCOUNTER StatIntReinject;
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| 319 | STAMCOUNTER StatPendingHostIrq;
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| 320 |
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| 321 | STAMCOUNTER StatFlushPageManual;
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| 322 | STAMCOUNTER StatFlushTLBManual;
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| 323 | STAMCOUNTER StatFlushPageInvlpg;
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| 324 | STAMCOUNTER StatFlushTLBWorldSwitch;
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| 325 | STAMCOUNTER StatNoFlushTLBWorldSwitch;
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| 326 | STAMCOUNTER StatFlushTLBCRxChange;
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| 327 | STAMCOUNTER StatFlushASID;
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| 328 |
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| 329 | STAMCOUNTER StatSwitchGuestIrq;
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| 330 | STAMCOUNTER StatSwitchToR3;
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| 331 |
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| 332 | R3PTRTYPE(PSTAMCOUNTER) pStatExitReason;
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| 333 | R0PTRTYPE(PSTAMCOUNTER) pStatExitReasonR0;
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| 334 | } HWACCM;
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| 335 | /** Pointer to HWACCM VM instance data. */
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| 336 | typedef HWACCM *PHWACCM;
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| 337 |
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| 338 | typedef struct
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| 339 | {
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| 340 | RTCPUID idCpu;
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| 341 |
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| 342 | RTR0MEMOBJ pMemObj;
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| 343 | /* Current ASID (AMD-V only) */
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| 344 | uint32_t uCurrentASID;
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| 345 | /* TLB flush count */
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| 346 | uint32_t cTLBFlushes;
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| 347 |
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| 348 | bool fVMXConfigured;
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| 349 | bool fSVMConfigured;
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| 350 | } HWACCM_CPUINFO;
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| 351 | typedef HWACCM_CPUINFO *PHWACCM_CPUINFO;
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| 352 |
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| 353 | #ifdef IN_RING0
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| 354 |
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| 355 | #ifdef VBOX_STRICT
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| 356 | HWACCMR0DECL(void) HWACCMDumpRegs(PCPUMCTX pCtx);
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| 357 | HWACCMR0DECL(void) HWACCMR0DumpDescriptor(PX86DESCHC Desc, RTSEL Sel, const char *pszMsg);
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| 358 | #else
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| 359 | #define HWACCMDumpRegs(a) do { } while (0)
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| 360 | #define HWACCMR0DumpDescriptor(a, b, c) do { } while (0)
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| 361 | #endif
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| 362 |
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| 363 | #endif
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| 364 |
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| 365 | /** @} */
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| 366 |
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| 367 | __END_DECLS
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| 368 |
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| 369 | #endif
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| 370 |
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