PDMDevHlp.cpp@ 20927

Last change on this file since 20927 was 20927, checked in by vboxsync, 15 years ago
pdmR3DevHlp_VMPowerOff: Set the VCPU state to stopped here as well to make sure no inconsistency with the EM state occurs.
Property svn:eol-style set to `native` Property svn:keywords set to `Id`
File size: 136.0 KB

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1	/* $Id: PDMDevHlp.cpp 20927 2009-06-25 11:41:35Z vboxsync $ */
2	/** @file
3	* PDM - Pluggable Device and Driver Manager, Device Helpers.
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22
23	/*******************************************************************************
24	* Header Files *
25	*******************************************************************************/
26	#define LOG_GROUP LOG_GROUP_PDM_DEVICE
27	#include "PDMInternal.h"
28	#include <VBox/pdm.h>
29	#include <VBox/mm.h>
30	#include <VBox/pgm.h>
31	#include <VBox/iom.h>
32	#include <VBox/rem.h>
33	#include <VBox/dbgf.h>
34	#include <VBox/vm.h>
35	#include <VBox/vmm.h>
36
37	#include <VBox/version.h>
38	#include <VBox/log.h>
39	#include <VBox/err.h>
40	#include <iprt/asm.h>
41	#include <iprt/assert.h>
42	#include <iprt/string.h>
43	#include <iprt/thread.h>
44
45
46	/*******************************************************************************
47	* Defined Constants And Macros *
48	*******************************************************************************/
49	/** @def PDM_DEVHLP_DEADLOCK_DETECTION
50	* Define this to enable the deadlock detection when accessing physical memory.
51	*/
52	#if /defined(DEBUG_bird) \|\|/ defined(DOXYGEN_RUNNING)
53	# define PDM_DEVHLP_DEADLOCK_DETECTION
54	#endif
55
56
57	/*******************************************************************************
58	* Defined Constants And Macros *
59	*******************************************************************************/
60	/** @name R3 DevHlp
61	* @{
62	*/
63
64
65	/** @copydoc PDMDEVHLPR3::pfnIOPortRegister */
66	static DECLCALLBACK(int) pdmR3DevHlp_IOPortRegister(PPDMDEVINS pDevIns, RTIOPORT Port, RTUINT cPorts, RTHCPTR pvUser, PFNIOMIOPORTOUT pfnOut, PFNIOMIOPORTIN pfnIn,
67	PFNIOMIOPORTOUTSTRING pfnOutStr, PFNIOMIOPORTINSTRING pfnInStr, const char *pszDesc)
68	{
69	PDMDEV_ASSERT_DEVINS(pDevIns);
70	LogFlow(("pdmR3DevHlp_IOPortRegister: caller='%s'/%d: Port=%#x cPorts=%#x pvUser=%p pfnOut=%p pfnIn=%p pfnOutStr=%p pfnInStr=%p p32_tszDesc=%p:{%s}\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance,
71	Port, cPorts, pvUser, pfnOut, pfnIn, pfnOutStr, pfnInStr, pszDesc, pszDesc));
72	VM_ASSERT_EMT(pDevIns->Internal.s.pVMR3);
73
74	#if 0 /** @todo needs a real string cache for this */
75	if (pDevIns->iInstance > 0)
76	{
77	char *pszDesc2 = MMR3HeapAPrintf(pVM, MM_TAG_PDM_DEVICE_DESC, "%s [%u]", pszDesc, pDevIns->iInstance);
78	if (pszDesc2)
79	pszDesc = pszDesc2;
80	}
81	#endif
82
83	int rc = IOMR3IOPortRegisterR3(pDevIns->Internal.s.pVMR3, pDevIns, Port, cPorts, pvUser, pfnOut, pfnIn, pfnOutStr, pfnInStr, pszDesc);
84
85	LogFlow(("pdmR3DevHlp_IOPortRegister: caller='%s'/%d: returns %Rrc\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, rc));
86	return rc;
87	}
88
89
90	/** @copydoc PDMDEVHLPR3::pfnIOPortRegisterGC */
91	static DECLCALLBACK(int) pdmR3DevHlp_IOPortRegisterGC(PPDMDEVINS pDevIns, RTIOPORT Port, RTUINT cPorts, RTRCPTR pvUser,
92	const char pszOut, const char pszIn,
93	const char pszOutStr, const char pszInStr, const char *pszDesc)
94	{
95	PDMDEV_ASSERT_DEVINS(pDevIns);
96	VM_ASSERT_EMT(pDevIns->Internal.s.pVMR3);
97	LogFlow(("pdmR3DevHlp_IOPortRegister: caller='%s'/%d: Port=%#x cPorts=%#x pvUser=%p pszOut=%p:{%s} pszIn=%p:{%s} pszOutStr=%p:{%s} pszInStr=%p:{%s} pszDesc=%p:{%s}\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance,
98	Port, cPorts, pvUser, pszOut, pszOut, pszIn, pszIn, pszOutStr, pszOutStr, pszInStr, pszInStr, pszDesc, pszDesc));
99
100	/*
101	* Resolve the functions (one of the can be NULL).
102	*/
103	int rc = VINF_SUCCESS;
104	if ( pDevIns->pDevReg->szRCMod[0]
105	&& (pDevIns->pDevReg->fFlags & PDM_DEVREG_FLAGS_RC))
106	{
107	RTRCPTR RCPtrIn = NIL_RTRCPTR;
108	if (pszIn)
109	{
110	rc = PDMR3LdrGetSymbolRCLazy(pDevIns->Internal.s.pVMR3, pDevIns->pDevReg->szRCMod, pszIn, &RCPtrIn);
111	AssertMsgRC(rc, ("Failed to resolve %s.%s (pszIn)\n", pDevIns->pDevReg->szRCMod, pszIn));
112	}
113	RTRCPTR RCPtrOut = NIL_RTRCPTR;
114	if (pszOut && RT_SUCCESS(rc))
115	{
116	rc = PDMR3LdrGetSymbolRCLazy(pDevIns->Internal.s.pVMR3, pDevIns->pDevReg->szRCMod, pszOut, &RCPtrOut);
117	AssertMsgRC(rc, ("Failed to resolve %s.%s (pszOut)\n", pDevIns->pDevReg->szRCMod, pszOut));
118	}
119	RTRCPTR RCPtrInStr = NIL_RTRCPTR;
120	if (pszInStr && RT_SUCCESS(rc))
121	{
122	rc = PDMR3LdrGetSymbolRCLazy(pDevIns->Internal.s.pVMR3, pDevIns->pDevReg->szRCMod, pszInStr, &RCPtrInStr);
123	AssertMsgRC(rc, ("Failed to resolve %s.%s (pszInStr)\n", pDevIns->pDevReg->szRCMod, pszInStr));
124	}
125	RTRCPTR RCPtrOutStr = NIL_RTRCPTR;
126	if (pszOutStr && RT_SUCCESS(rc))
127	{
128	rc = PDMR3LdrGetSymbolRCLazy(pDevIns->Internal.s.pVMR3, pDevIns->pDevReg->szRCMod, pszOutStr, &RCPtrOutStr);
129	AssertMsgRC(rc, ("Failed to resolve %s.%s (pszOutStr)\n", pDevIns->pDevReg->szRCMod, pszOutStr));
130	}
131
132	if (RT_SUCCESS(rc))
133	{
134	#if 0 /** @todo needs a real string cache for this */
135	if (pDevIns->iInstance > 0)
136	{
137	char *pszDesc2 = MMR3HeapAPrintf(pVM, MM_TAG_PDM_DEVICE_DESC, "%s [%u]", pszDesc, pDevIns->iInstance);
138	if (pszDesc2)
139	pszDesc = pszDesc2;
140	}
141	#endif
142
143	rc = IOMR3IOPortRegisterRC(pDevIns->Internal.s.pVMR3, pDevIns, Port, cPorts, pvUser, RCPtrOut, RCPtrIn, RCPtrOutStr, RCPtrInStr, pszDesc);
144	}
145	}
146	else
147	{
148	AssertMsgFailed(("No GC module for this driver!\n"));
149	rc = VERR_INVALID_PARAMETER;
150	}
151
152	LogFlow(("pdmR3DevHlp_IOPortRegisterGC: caller='%s'/%d: returns %Rrc\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, rc));
153	return rc;
154	}
155
156
157	/** @copydoc PDMDEVHLPR3::pfnIOPortRegisterR0 */
158	static DECLCALLBACK(int) pdmR3DevHlp_IOPortRegisterR0(PPDMDEVINS pDevIns, RTIOPORT Port, RTUINT cPorts, RTR0PTR pvUser,
159	const char pszOut, const char pszIn,
160	const char pszOutStr, const char pszInStr, const char *pszDesc)
161	{
162	PDMDEV_ASSERT_DEVINS(pDevIns);
163	VM_ASSERT_EMT(pDevIns->Internal.s.pVMR3);
164	LogFlow(("pdmR3DevHlp_IOPortRegisterR0: caller='%s'/%d: Port=%#x cPorts=%#x pvUser=%p pszOut=%p:{%s} pszIn=%p:{%s} pszOutStr=%p:{%s} pszInStr=%p:{%s} pszDesc=%p:{%s}\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance,
165	Port, cPorts, pvUser, pszOut, pszOut, pszIn, pszIn, pszOutStr, pszOutStr, pszInStr, pszInStr, pszDesc, pszDesc));
166
167	/*
168	* Resolve the functions (one of the can be NULL).
169	*/
170	int rc = VINF_SUCCESS;
171	if ( pDevIns->pDevReg->szR0Mod[0]
172	&& (pDevIns->pDevReg->fFlags & PDM_DEVREG_FLAGS_R0))
173	{
174	R0PTRTYPE(PFNIOMIOPORTIN) pfnR0PtrIn = 0;
175	if (pszIn)
176	{
177	rc = PDMR3LdrGetSymbolR0Lazy(pDevIns->Internal.s.pVMR3, pDevIns->pDevReg->szR0Mod, pszIn, &pfnR0PtrIn);
178	AssertMsgRC(rc, ("Failed to resolve %s.%s (pszIn)\n", pDevIns->pDevReg->szR0Mod, pszIn));
179	}
180	R0PTRTYPE(PFNIOMIOPORTOUT) pfnR0PtrOut = 0;
181	if (pszOut && RT_SUCCESS(rc))
182	{
183	rc = PDMR3LdrGetSymbolR0Lazy(pDevIns->Internal.s.pVMR3, pDevIns->pDevReg->szR0Mod, pszOut, &pfnR0PtrOut);
184	AssertMsgRC(rc, ("Failed to resolve %s.%s (pszOut)\n", pDevIns->pDevReg->szR0Mod, pszOut));
185	}
186	R0PTRTYPE(PFNIOMIOPORTINSTRING) pfnR0PtrInStr = 0;
187	if (pszInStr && RT_SUCCESS(rc))
188	{
189	rc = PDMR3LdrGetSymbolR0Lazy(pDevIns->Internal.s.pVMR3, pDevIns->pDevReg->szR0Mod, pszInStr, &pfnR0PtrInStr);
190	AssertMsgRC(rc, ("Failed to resolve %s.%s (pszInStr)\n", pDevIns->pDevReg->szR0Mod, pszInStr));
191	}
192	R0PTRTYPE(PFNIOMIOPORTOUTSTRING) pfnR0PtrOutStr = 0;
193	if (pszOutStr && RT_SUCCESS(rc))
194	{
195	rc = PDMR3LdrGetSymbolR0Lazy(pDevIns->Internal.s.pVMR3, pDevIns->pDevReg->szR0Mod, pszOutStr, &pfnR0PtrOutStr);
196	AssertMsgRC(rc, ("Failed to resolve %s.%s (pszOutStr)\n", pDevIns->pDevReg->szR0Mod, pszOutStr));
197	}
198
199	if (RT_SUCCESS(rc))
200	{
201	#if 0 /** @todo needs a real string cache for this */
202	if (pDevIns->iInstance > 0)
203	{
204	char *pszDesc2 = MMR3HeapAPrintf(pVM, MM_TAG_PDM_DEVICE_DESC, "%s [%u]", pszDesc, pDevIns->iInstance);
205	if (pszDesc2)
206	pszDesc = pszDesc2;
207	}
208	#endif
209
210	rc = IOMR3IOPortRegisterR0(pDevIns->Internal.s.pVMR3, pDevIns, Port, cPorts, pvUser, pfnR0PtrOut, pfnR0PtrIn, pfnR0PtrOutStr, pfnR0PtrInStr, pszDesc);
211	}
212	}
213	else
214	{
215	AssertMsgFailed(("No R0 module for this driver!\n"));
216	rc = VERR_INVALID_PARAMETER;
217	}
218
219	LogFlow(("pdmR3DevHlp_IOPortRegisterR0: caller='%s'/%d: returns %Rrc\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, rc));
220	return rc;
221	}
222
223
224	/** @copydoc PDMDEVHLPR3::pfnIOPortDeregister */
225	static DECLCALLBACK(int) pdmR3DevHlp_IOPortDeregister(PPDMDEVINS pDevIns, RTIOPORT Port, RTUINT cPorts)
226	{
227	PDMDEV_ASSERT_DEVINS(pDevIns);
228	VM_ASSERT_EMT(pDevIns->Internal.s.pVMR3);
229	LogFlow(("pdmR3DevHlp_IOPortDeregister: caller='%s'/%d: Port=%#x cPorts=%#x\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance,
230	Port, cPorts));
231
232	int rc = IOMR3IOPortDeregister(pDevIns->Internal.s.pVMR3, pDevIns, Port, cPorts);
233
234	LogFlow(("pdmR3DevHlp_IOPortDeregister: caller='%s'/%d: returns %Rrc\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, rc));
235	return rc;
236	}
237
238
239	/** @copydoc PDMDEVHLPR3::pfnMMIORegister */
240	static DECLCALLBACK(int) pdmR3DevHlp_MMIORegister(PPDMDEVINS pDevIns, RTGCPHYS GCPhysStart, RTUINT cbRange, RTHCPTR pvUser,
241	PFNIOMMMIOWRITE pfnWrite, PFNIOMMMIOREAD pfnRead, PFNIOMMMIOFILL pfnFill,
242	const char *pszDesc)
243	{
244	PDMDEV_ASSERT_DEVINS(pDevIns);
245	VM_ASSERT_EMT(pDevIns->Internal.s.pVMR3);
246	LogFlow(("pdmR3DevHlp_MMIORegister: caller='%s'/%d: GCPhysStart=%RGp cbRange=%#x pvUser=%p pfnWrite=%p pfnRead=%p pfnFill=%p pszDesc=%p:{%s}\n",
247	pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, GCPhysStart, cbRange, pvUser, pfnWrite, pfnRead, pfnFill, pszDesc, pszDesc));
248
249	/** @todo IOMR3MMIORegisterR3 mangles the description, move it here. */
250	int rc = IOMR3MMIORegisterR3(pDevIns->Internal.s.pVMR3, pDevIns, GCPhysStart, cbRange, pvUser, pfnWrite, pfnRead, pfnFill, pszDesc);
251
252	LogFlow(("pdmR3DevHlp_MMIORegister: caller='%s'/%d: returns %Rrc\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, rc));
253	return rc;
254	}
255
256
257	/** @copydoc PDMDEVHLPR3::pfnMMIORegisterGC */
258	static DECLCALLBACK(int) pdmR3DevHlp_MMIORegisterGC(PPDMDEVINS pDevIns, RTGCPHYS GCPhysStart, RTUINT cbRange, RTGCPTR pvUser,
259	const char pszWrite, const char pszRead, const char *pszFill,
260	const char *pszDesc)
261	{
262	PDMDEV_ASSERT_DEVINS(pDevIns);
263	VM_ASSERT_EMT(pDevIns->Internal.s.pVMR3);
264	LogFlow(("pdmR3DevHlp_MMIORegisterGC: caller='%s'/%d: GCPhysStart=%RGp cbRange=%#x pvUser=%p pszWrite=%p:{%s} pszRead=%p:{%s} pszFill=%p:{%s}\n",
265	pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, GCPhysStart, cbRange, pvUser, pszWrite, pszWrite, pszRead, pszRead, pszFill, pszFill));
266
267	/** @todo pszDesc is unused here, drop it. */
268
269	/*
270	* Resolve the functions.
271	* Not all function have to present, leave it to IOM to enforce this.
272	*/
273	int rc = VINF_SUCCESS;
274	if ( pDevIns->pDevReg->szRCMod[0]
275	&& (pDevIns->pDevReg->fFlags & PDM_DEVREG_FLAGS_RC))
276	{
277	RTRCPTR RCPtrWrite = NIL_RTRCPTR;
278	if (pszWrite)
279	rc = PDMR3LdrGetSymbolRCLazy(pDevIns->Internal.s.pVMR3, pDevIns->pDevReg->szRCMod, pszWrite, &RCPtrWrite);
280
281	RTRCPTR RCPtrRead = NIL_RTRCPTR;
282	int rc2 = VINF_SUCCESS;
283	if (pszRead)
284	rc2 = PDMR3LdrGetSymbolRCLazy(pDevIns->Internal.s.pVMR3, pDevIns->pDevReg->szRCMod, pszRead, &RCPtrRead);
285
286	RTRCPTR RCPtrFill = NIL_RTRCPTR;
287	int rc3 = VINF_SUCCESS;
288	if (pszFill)
289	rc3 = PDMR3LdrGetSymbolRCLazy(pDevIns->Internal.s.pVMR3, pDevIns->pDevReg->szRCMod, pszFill, &RCPtrFill);
290
291	if (RT_SUCCESS(rc) && RT_SUCCESS(rc2) && RT_SUCCESS(rc3))
292	rc = IOMR3MMIORegisterRC(pDevIns->Internal.s.pVMR3, pDevIns, GCPhysStart, cbRange, pvUser, RCPtrWrite, RCPtrRead, RCPtrFill);
293	else
294	{
295	AssertMsgRC(rc, ("Failed to resolve %s.%s (pszWrite)\n", pDevIns->pDevReg->szRCMod, pszWrite));
296	AssertMsgRC(rc2, ("Failed to resolve %s.%s (pszRead)\n", pDevIns->pDevReg->szRCMod, pszRead));
297	AssertMsgRC(rc3, ("Failed to resolve %s.%s (pszFill)\n", pDevIns->pDevReg->szRCMod, pszFill));
298	if (RT_FAILURE(rc2) && RT_SUCCESS(rc))
299	rc = rc2;
300	if (RT_FAILURE(rc3) && RT_SUCCESS(rc))
301	rc = rc3;
302	}
303	}
304	else
305	{
306	AssertMsgFailed(("No GC module for this driver!\n"));
307	rc = VERR_INVALID_PARAMETER;
308	}
309
310	LogFlow(("pdmR3DevHlp_MMIORegisterGC: caller='%s'/%d: returns %Rrc\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, rc));
311	return rc;
312	}
313
314	/** @copydoc PDMDEVHLPR3::pfnMMIORegisterR0 */
315	static DECLCALLBACK(int) pdmR3DevHlp_MMIORegisterR0(PPDMDEVINS pDevIns, RTGCPHYS GCPhysStart, RTUINT cbRange, RTR0PTR pvUser,
316	const char pszWrite, const char pszRead, const char *pszFill,
317	const char *pszDesc)
318	{
319	PDMDEV_ASSERT_DEVINS(pDevIns);
320	VM_ASSERT_EMT(pDevIns->Internal.s.pVMR3);
321	LogFlow(("pdmR3DevHlp_MMIORegisterHC: caller='%s'/%d: GCPhysStart=%RGp cbRange=%#x pvUser=%p pszWrite=%p:{%s} pszRead=%p:{%s} pszFill=%p:{%s}\n",
322	pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, GCPhysStart, cbRange, pvUser, pszWrite, pszWrite, pszRead, pszRead, pszFill, pszFill));
323
324	/** @todo pszDesc is unused here, remove it. */
325
326	/*
327	* Resolve the functions.
328	* Not all function have to present, leave it to IOM to enforce this.
329	*/
330	int rc = VINF_SUCCESS;
331	if ( pDevIns->pDevReg->szR0Mod[0]
332	&& (pDevIns->pDevReg->fFlags & PDM_DEVREG_FLAGS_R0))
333	{
334	R0PTRTYPE(PFNIOMMMIOWRITE) pfnR0PtrWrite = 0;
335	if (pszWrite)
336	rc = PDMR3LdrGetSymbolR0Lazy(pDevIns->Internal.s.pVMR3, pDevIns->pDevReg->szR0Mod, pszWrite, &pfnR0PtrWrite);
337	R0PTRTYPE(PFNIOMMMIOREAD) pfnR0PtrRead = 0;
338	int rc2 = VINF_SUCCESS;
339	if (pszRead)
340	rc2 = PDMR3LdrGetSymbolR0Lazy(pDevIns->Internal.s.pVMR3, pDevIns->pDevReg->szR0Mod, pszRead, &pfnR0PtrRead);
341	R0PTRTYPE(PFNIOMMMIOFILL) pfnR0PtrFill = 0;
342	int rc3 = VINF_SUCCESS;
343	if (pszFill)
344	rc3 = PDMR3LdrGetSymbolR0Lazy(pDevIns->Internal.s.pVMR3, pDevIns->pDevReg->szR0Mod, pszFill, &pfnR0PtrFill);
345	if (RT_SUCCESS(rc) && RT_SUCCESS(rc2) && RT_SUCCESS(rc3))
346	rc = IOMR3MMIORegisterR0(pDevIns->Internal.s.pVMR3, pDevIns, GCPhysStart, cbRange, pvUser, pfnR0PtrWrite, pfnR0PtrRead, pfnR0PtrFill);
347	else
348	{
349	AssertMsgRC(rc, ("Failed to resolve %s.%s (pszWrite)\n", pDevIns->pDevReg->szR0Mod, pszWrite));
350	AssertMsgRC(rc2, ("Failed to resolve %s.%s (pszRead)\n", pDevIns->pDevReg->szR0Mod, pszRead));
351	AssertMsgRC(rc3, ("Failed to resolve %s.%s (pszFill)\n", pDevIns->pDevReg->szR0Mod, pszFill));
352	if (RT_FAILURE(rc2) && RT_SUCCESS(rc))
353	rc = rc2;
354	if (RT_FAILURE(rc3) && RT_SUCCESS(rc))
355	rc = rc3;
356	}
357	}
358	else
359	{
360	AssertMsgFailed(("No R0 module for this driver!\n"));
361	rc = VERR_INVALID_PARAMETER;
362	}
363
364	LogFlow(("pdmR3DevHlp_MMIORegisterR0: caller='%s'/%d: returns %Rrc\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, rc));
365	return rc;
366	}
367
368
369	/** @copydoc PDMDEVHLPR3::pfnMMIODeregister */
370	static DECLCALLBACK(int) pdmR3DevHlp_MMIODeregister(PPDMDEVINS pDevIns, RTGCPHYS GCPhysStart, RTUINT cbRange)
371	{
372	PDMDEV_ASSERT_DEVINS(pDevIns);
373	VM_ASSERT_EMT(pDevIns->Internal.s.pVMR3);
374	LogFlow(("pdmR3DevHlp_MMIODeregister: caller='%s'/%d: GCPhysStart=%RGp cbRange=%#x\n",
375	pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, GCPhysStart, cbRange));
376
377	int rc = IOMR3MMIODeregister(pDevIns->Internal.s.pVMR3, pDevIns, GCPhysStart, cbRange);
378
379	LogFlow(("pdmR3DevHlp_MMIODeregister: caller='%s'/%d: returns %Rrc\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, rc));
380	return rc;
381	}
382
383
384	/** @copydoc PDMDEVHLPR3::pfnROMRegister */
385	static DECLCALLBACK(int) pdmR3DevHlp_ROMRegister(PPDMDEVINS pDevIns, RTGCPHYS GCPhysStart, RTUINT cbRange, const void pvBinary, uint32_t fFlags, const char pszDesc)
386	{
387	PDMDEV_ASSERT_DEVINS(pDevIns);
388	VM_ASSERT_EMT(pDevIns->Internal.s.pVMR3);
389	LogFlow(("pdmR3DevHlp_ROMRegister: caller='%s'/%d: GCPhysStart=%RGp cbRange=%#x pvBinary=%p fFlags=%#RX32 pszDesc=%p:{%s}\n",
390	pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, GCPhysStart, cbRange, pvBinary, fFlags, pszDesc, pszDesc));
391
392	/** @todo can we mangle pszDesc? */
393	int rc = PGMR3PhysRomRegister(pDevIns->Internal.s.pVMR3, pDevIns, GCPhysStart, cbRange, pvBinary, fFlags, pszDesc);
394
395	LogFlow(("pdmR3DevHlp_ROMRegister: caller='%s'/%d: returns %Rrc\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, rc));
396	return rc;
397	}
398
399
400	/** @copydoc PDMDEVHLPR3::pfnSSMRegister */
401	static DECLCALLBACK(int) pdmR3DevHlp_SSMRegister(PPDMDEVINS pDevIns, const char *pszName, uint32_t u32Instance, uint32_t u32Version, size_t cbGuess,
402	PFNSSMDEVSAVEPREP pfnSavePrep, PFNSSMDEVSAVEEXEC pfnSaveExec, PFNSSMDEVSAVEDONE pfnSaveDone,
403	PFNSSMDEVLOADPREP pfnLoadPrep, PFNSSMDEVLOADEXEC pfnLoadExec, PFNSSMDEVLOADDONE pfnLoadDone)
404	{
405	PDMDEV_ASSERT_DEVINS(pDevIns);
406	VM_ASSERT_EMT(pDevIns->Internal.s.pVMR3);
407	LogFlow(("pdmR3DevHlp_SSMRegister: caller='%s'/%d: pszName=%p:{%s} u32Instance=%#x u32Version=#x cbGuess=%#x pfnSavePrep=%p pfnSaveExec=%p pfnSaveDone=%p pszLoadPrep=%p pfnLoadExec=%p pfnLoaddone=%p\n",
408	pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, pszName, pszName, u32Instance, u32Version, cbGuess, pfnSavePrep, pfnSaveExec, pfnSaveDone, pfnLoadPrep, pfnLoadExec, pfnLoadDone));
409
410	int rc = SSMR3RegisterDevice(pDevIns->Internal.s.pVMR3, pDevIns, pszName, u32Instance, u32Version, cbGuess, NULL,
411	pfnSavePrep, pfnSaveExec, pfnSaveDone,
412	pfnLoadPrep, pfnLoadExec, pfnLoadDone);
413
414	LogFlow(("pdmR3DevHlp_SSMRegister: caller='%s'/%d: returns %Rrc\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, rc));
415	return rc;
416	}
417
418
419	/** @copydoc PDMDEVHLPR3::pfnTMTimerCreate */
420	static DECLCALLBACK(int) pdmR3DevHlp_TMTimerCreate(PPDMDEVINS pDevIns, TMCLOCK enmClock, PFNTMTIMERDEV pfnCallback, void pvUser, uint32_t fFlags, const char pszDesc, PPTMTIMERR3 ppTimer)
421	{
422	PDMDEV_ASSERT_DEVINS(pDevIns);
423	PVM pVM = pDevIns->Internal.s.pVMR3;
424	VM_ASSERT_EMT(pVM);
425	LogFlow(("pdmR3DevHlp_TMTimerCreate: caller='%s'/%d: enmClock=%d pfnCallback=%p pvUser=%p fFlags=%#x pszDesc=%p:{%s} ppTimer=%p\n",
426	pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, enmClock, pfnCallback, pvUser, fFlags, pszDesc, pszDesc, ppTimer));
427
428	if (pDevIns->iInstance > 0) /** @todo use a string cache here later. */
429	{
430	char *pszDesc2 = MMR3HeapAPrintf(pVM, MM_TAG_PDM_DEVICE_DESC, "%s [%u]", pszDesc, pDevIns->iInstance);
431	if (pszDesc2)
432	pszDesc = pszDesc2;
433	}
434
435	int rc = TMR3TimerCreateDevice(pVM, pDevIns, enmClock, pfnCallback, pvUser, fFlags, pszDesc, ppTimer);
436
437	LogFlow(("pdmR3DevHlp_TMTimerCreate: caller='%s'/%d: returns %Rrc\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, rc));
438	return rc;
439	}
440
441
442	/** @copydoc PDMDEVHLPR3::pfnPCIRegister */
443	static DECLCALLBACK(int) pdmR3DevHlp_PCIRegister(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev)
444	{
445	PDMDEV_ASSERT_DEVINS(pDevIns);
446	PVM pVM = pDevIns->Internal.s.pVMR3;
447	VM_ASSERT_EMT(pVM);
448	LogFlow(("pdmR3DevHlp_PCIRegister: caller='%s'/%d: pPciDev=%p:{.config={%#.256Rhxs}\n",
449	pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, pPciDev, pPciDev->config));
450
451	/*
452	* Validate input.
453	*/
454	if (!pPciDev)
455	{
456	Assert(pPciDev);
457	LogFlow(("pdmR3DevHlp_PCIRegister: caller='%s'/%d: returns %Rrc (pPciDev)\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
458	return VERR_INVALID_PARAMETER;
459	}
460	if (!pPciDev->config[0] && !pPciDev->config[1])
461	{
462	Assert(pPciDev->config[0] \|\| pPciDev->config[1]);
463	LogFlow(("pdmR3DevHlp_PCIRegister: caller='%s'/%d: returns %Rrc (vendor)\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
464	return VERR_INVALID_PARAMETER;
465	}
466	if (pDevIns->Internal.s.pPciDeviceR3)
467	{
468	/** @todo the PCI device vs. PDM device designed is a bit flawed if we have to
469	* support a PDM device with multiple PCI devices. This might become a problem
470	* when upgrading the chipset for instance because of multiple functions in some
471	* devices...
472	*/
473	AssertMsgFailed(("Only one PCI device per device is currently implemented!\n"));
474	return VERR_INTERNAL_ERROR;
475	}
476
477	/*
478	* Choose the PCI bus for the device.
479	*
480	* This is simple. If the device was configured for a particular bus, the PCIBusNo
481	* configuration value will be set. If not the default bus is 0.
482	*/
483	int rc;
484	PPDMPCIBUS pBus = pDevIns->Internal.s.pPciBusR3;
485	if (!pBus)
486	{
487	uint8_t u8Bus;
488	rc = CFGMR3QueryU8Def(pDevIns->Internal.s.pCfgHandle, "PCIBusNo", &u8Bus, 0);
489	AssertLogRelMsgRCReturn(rc, ("Configuration error: PCIBusNo query failed with rc=%Rrc (%s/%d)\n",
490	rc, pDevIns->pDevReg->szDeviceName, pDevIns->iInstance), rc);
491	AssertLogRelMsgReturn(u8Bus < RT_ELEMENTS(pVM->pdm.s.aPciBuses),
492	("Configuration error: PCIBusNo=%d, max is %d. (%s/%d)\n", u8Bus,
493	RT_ELEMENTS(pVM->pdm.s.aPciBuses), pDevIns->pDevReg->szDeviceName, pDevIns->iInstance),
494	VERR_PDM_NO_PCI_BUS);
495	pBus = pDevIns->Internal.s.pPciBusR3 = &pVM->pdm.s.aPciBuses[u8Bus];
496	}
497	if (pBus->pDevInsR3)
498	{
499	if (pDevIns->pDevReg->fFlags & PDM_DEVREG_FLAGS_RC)
500	pDevIns->Internal.s.pPciBusR0 = MMHyperR3ToR0(pVM, pDevIns->Internal.s.pPciBusR3);
501	else
502	pDevIns->Internal.s.pPciBusR0 = NIL_RTR0PTR;
503
504	if (pDevIns->pDevReg->fFlags & PDM_DEVREG_FLAGS_RC)
505	pDevIns->Internal.s.pPciBusRC = MMHyperR3ToRC(pVM, pDevIns->Internal.s.pPciBusR3);
506	else
507	pDevIns->Internal.s.pPciBusRC = NIL_RTRCPTR;
508
509	/*
510	* Check the configuration for PCI device and function assignment.
511	*/
512	int iDev = -1;
513	uint8_t u8Device;
514	rc = CFGMR3QueryU8(pDevIns->Internal.s.pCfgHandle, "PCIDeviceNo", &u8Device);
515	if (RT_SUCCESS(rc))
516	{
517	if (u8Device > 31)
518	{
519	AssertMsgFailed(("Configuration error: PCIDeviceNo=%d, max is 31. (%s/%d)\n",
520	u8Device, pDevIns->pDevReg->szDeviceName, pDevIns->iInstance));
521	return VERR_INTERNAL_ERROR;
522	}
523
524	uint8_t u8Function;
525	rc = CFGMR3QueryU8(pDevIns->Internal.s.pCfgHandle, "PCIFunctionNo", &u8Function);
526	if (RT_FAILURE(rc))
527	{
528	AssertMsgFailed(("Configuration error: PCIDeviceNo, but PCIFunctionNo query failed with rc=%Rrc (%s/%d)\n",
529	rc, pDevIns->pDevReg->szDeviceName, pDevIns->iInstance));
530	return rc;
531	}
532	if (u8Function > 7)
533	{
534	AssertMsgFailed(("Configuration error: PCIFunctionNo=%d, max is 7. (%s/%d)\n",
535	u8Function, pDevIns->pDevReg->szDeviceName, pDevIns->iInstance));
536	return VERR_INTERNAL_ERROR;
537	}
538	iDev = (u8Device << 3) \| u8Function;
539	}
540	else if (rc != VERR_CFGM_VALUE_NOT_FOUND)
541	{
542	AssertMsgFailed(("Configuration error: PCIDeviceNo query failed with rc=%Rrc (%s/%d)\n",
543	rc, pDevIns->pDevReg->szDeviceName, pDevIns->iInstance));
544	return rc;
545	}
546
547	/*
548	* Call the pci bus device to do the actual registration.
549	*/
550	pdmLock(pVM);
551	rc = pBus->pfnRegisterR3(pBus->pDevInsR3, pPciDev, pDevIns->pDevReg->szDeviceName, iDev);
552	pdmUnlock(pVM);
553	if (RT_SUCCESS(rc))
554	{
555	pPciDev->pDevIns = pDevIns;
556
557	pDevIns->Internal.s.pPciDeviceR3 = pPciDev;
558	if (pDevIns->pDevReg->fFlags & PDM_DEVREG_FLAGS_R0)
559	pDevIns->Internal.s.pPciDeviceR0 = MMHyperR3ToR0(pVM, pPciDev);
560	else
561	pDevIns->Internal.s.pPciDeviceR0 = NIL_RTR0PTR;
562
563	if (pDevIns->pDevReg->fFlags & PDM_DEVREG_FLAGS_RC)
564	pDevIns->Internal.s.pPciDeviceRC = MMHyperR3ToRC(pVM, pPciDev);
565	else
566	pDevIns->Internal.s.pPciDeviceRC = NIL_RTRCPTR;
567
568	Log(("PDM: Registered device '%s'/%d as PCI device %d on bus %d\n",
569	pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, pPciDev->devfn, pDevIns->Internal.s.pPciBusR3->iBus));
570	}
571	}
572	else
573	{
574	AssertLogRelMsgFailed(("Configuration error: No PCI bus available. This could be related to init order too!\n"));
575	rc = VERR_PDM_NO_PCI_BUS;
576	}
577
578	LogFlow(("pdmR3DevHlp_PCIRegister: caller='%s'/%d: returns %Rrc\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, rc));
579	return rc;
580	}
581
582
583	/** @copydoc PDMDEVHLPR3::pfnPCIIORegionRegister */
584	static DECLCALLBACK(int) pdmR3DevHlp_PCIIORegionRegister(PPDMDEVINS pDevIns, int iRegion, uint32_t cbRegion, PCIADDRESSSPACE enmType, PFNPCIIOREGIONMAP pfnCallback)
585	{
586	PDMDEV_ASSERT_DEVINS(pDevIns);
587	PVM pVM = pDevIns->Internal.s.pVMR3;
588	VM_ASSERT_EMT(pVM);
589	LogFlow(("pdmR3DevHlp_PCIIORegionRegister: caller='%s'/%d: iRegion=%d cbRegion=%#x enmType=%d pfnCallback=%p\n",
590	pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, iRegion, cbRegion, enmType, pfnCallback));
591
592	/*
593	* Validate input.
594	*/
595	if (iRegion < 0 \|\| iRegion >= PCI_NUM_REGIONS)
596	{
597	Assert(iRegion >= 0 && iRegion < PCI_NUM_REGIONS);
598	LogFlow(("pdmR3DevHlp_PCIIORegionRegister: caller='%s'/%d: returns %Rrc (iRegion)\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
599	return VERR_INVALID_PARAMETER;
600	}
601	switch (enmType)
602	{
603	case PCI_ADDRESS_SPACE_IO:
604	/*
605	* Sanity check: don't allow to register more than 32K of the PCI I/O space.
606	*/
607	AssertMsgReturn(cbRegion <= _32K,
608	("caller='%s'/%d: %#x\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, cbRegion),
609	VERR_INVALID_PARAMETER);
610	break;
611
612	case PCI_ADDRESS_SPACE_MEM:
613	case PCI_ADDRESS_SPACE_MEM_PREFETCH:
614	/*
615	* Sanity check: don't allow to register more than 512MB of the PCI MMIO space for
616	* now. If this limit is increased beyond 2GB, adapt the aligned check below as well!
617	*/
618	AssertMsgReturn(cbRegion <= 512 * _1M,
619	("caller='%s'/%d: %#x\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, cbRegion),
620	VERR_INVALID_PARAMETER);
621	break;
622	default:
623	AssertMsgFailed(("enmType=%#x is unknown\n", enmType));
624	LogFlow(("pdmR3DevHlp_PCIIORegionRegister: caller='%s'/%d: returns %Rrc (enmType)\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
625	return VERR_INVALID_PARAMETER;
626	}
627	if (!pfnCallback)
628	{
629	Assert(pfnCallback);
630	LogFlow(("pdmR3DevHlp_PCIIORegionRegister: caller='%s'/%d: returns %Rrc (callback)\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
631	return VERR_INVALID_PARAMETER;
632	}
633	AssertRelease(VMR3GetState(pVM) != VMSTATE_RUNNING);
634
635	/*
636	* Must have a PCI device registered!
637	*/
638	int rc;
639	PPCIDEVICE pPciDev = pDevIns->Internal.s.pPciDeviceR3;
640	if (pPciDev)
641	{
642	/*
643	* We're currently restricted to page aligned MMIO regions.
644	*/
645	if ( (enmType == PCI_ADDRESS_SPACE_MEM \|\| enmType == PCI_ADDRESS_SPACE_MEM_PREFETCH)
646	&& cbRegion != RT_ALIGN_32(cbRegion, PAGE_SIZE))
647	{
648	Log(("pdmR3DevHlp_PCIIORegionRegister: caller='%s'/%d: aligning cbRegion %#x -> %#x\n",
649	pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, cbRegion, RT_ALIGN_32(cbRegion, PAGE_SIZE)));
650	cbRegion = RT_ALIGN_32(cbRegion, PAGE_SIZE);
651	}
652
653	/*
654	* For registering PCI MMIO memory or PCI I/O memory, the size of the region must be a power of 2!
655	*/
656	int iLastSet = ASMBitLastSetU32(cbRegion);
657	Assert(iLastSet > 0);
658	uint32_t cbRegionAligned = RT_BIT_32(iLastSet - 1);
659	if (cbRegion > cbRegionAligned)
660	cbRegion = cbRegionAligned * 2; /* round up */
661
662	PPDMPCIBUS pBus = pDevIns->Internal.s.pPciBusR3;
663	Assert(pBus);
664	pdmLock(pVM);
665	rc = pBus->pfnIORegionRegisterR3(pBus->pDevInsR3, pPciDev, iRegion, cbRegion, enmType, pfnCallback);
666	pdmUnlock(pVM);
667	}
668	else
669	{
670	AssertMsgFailed(("No PCI device registered!\n"));
671	rc = VERR_PDM_NOT_PCI_DEVICE;
672	}
673
674	LogFlow(("pdmR3DevHlp_PCIIORegionRegister: caller='%s'/%d: returns %Rrc\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, rc));
675	return rc;
676	}
677
678
679	/** @copydoc PDMDEVHLPR3::pfnPCISetConfigCallbacks */
680	static DECLCALLBACK(void) pdmR3DevHlp_PCISetConfigCallbacks(PPDMDEVINS pDevIns, PPCIDEVICE pPciDev, PFNPCICONFIGREAD pfnRead, PPFNPCICONFIGREAD ppfnReadOld,
681	PFNPCICONFIGWRITE pfnWrite, PPFNPCICONFIGWRITE ppfnWriteOld)
682	{
683	PDMDEV_ASSERT_DEVINS(pDevIns);
684	PVM pVM = pDevIns->Internal.s.pVMR3;
685	VM_ASSERT_EMT(pVM);
686	LogFlow(("pdmR3DevHlp_PCISetConfigCallbacks: caller='%s'/%d: pPciDev=%p pfnRead=%p ppfnReadOld=%p pfnWrite=%p ppfnWriteOld=%p\n",
687	pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, pPciDev, pfnRead, ppfnReadOld, pfnWrite, ppfnWriteOld));
688
689	/*
690	* Validate input and resolve defaults.
691	*/
692	AssertPtr(pfnRead);
693	AssertPtr(pfnWrite);
694	AssertPtrNull(ppfnReadOld);
695	AssertPtrNull(ppfnWriteOld);
696	AssertPtrNull(pPciDev);
697
698	if (!pPciDev)
699	pPciDev = pDevIns->Internal.s.pPciDeviceR3;
700	AssertReleaseMsg(pPciDev, ("You must register your device first!\n"));
701	PPDMPCIBUS pBus = pDevIns->Internal.s.pPciBusR3;
702	AssertRelease(pBus);
703	AssertRelease(VMR3GetState(pVM) != VMSTATE_RUNNING);
704
705	/*
706	* Do the job.
707	*/
708	pdmLock(pVM);
709	pBus->pfnSetConfigCallbacksR3(pBus->pDevInsR3, pPciDev, pfnRead, ppfnReadOld, pfnWrite, ppfnWriteOld);
710	pdmUnlock(pVM);
711
712	LogFlow(("pdmR3DevHlp_PCISetConfigCallbacks: caller='%s'/%d: returns void\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance));
713	}
714
715
716	/** @copydoc PDMDEVHLPR3::pfnPCISetIrq */
717	static DECLCALLBACK(void) pdmR3DevHlp_PCISetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel)
718	{
719	PDMDEV_ASSERT_DEVINS(pDevIns);
720	LogFlow(("pdmR3DevHlp_PCISetIrq: caller='%s'/%d: iIrq=%d iLevel=%d\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, iIrq, iLevel));
721
722	/*
723	* Validate input.
724	*/
725	/** @todo iIrq and iLevel checks. */
726
727	/*
728	* Must have a PCI device registered!
729	*/
730	PPCIDEVICE pPciDev = pDevIns->Internal.s.pPciDeviceR3;
731	if (pPciDev)
732	{
733	PPDMPCIBUS pBus = pDevIns->Internal.s.pPciBusR3; /** @todo the bus should be associated with the PCI device not the PDM device. */
734	Assert(pBus);
735	PVM pVM = pDevIns->Internal.s.pVMR3;
736	pdmLock(pVM);
737	pBus->pfnSetIrqR3(pBus->pDevInsR3, pPciDev, iIrq, iLevel);
738	pdmUnlock(pVM);
739	}
740	else
741	AssertReleaseMsgFailed(("No PCI device registered!\n"));
742
743	LogFlow(("pdmR3DevHlp_PCISetIrq: caller='%s'/%d: returns void\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance));
744	}
745
746
747	/** @copydoc PDMDEVHLPR3::pfnPCISetIrqNoWait */
748	static DECLCALLBACK(void) pdmR3DevHlp_PCISetIrqNoWait(PPDMDEVINS pDevIns, int iIrq, int iLevel)
749	{
750	pdmR3DevHlp_PCISetIrq(pDevIns, iIrq, iLevel);
751	}
752
753
754	/** @copydoc PDMDEVHLPR3::pfnISASetIrq */
755	static DECLCALLBACK(void) pdmR3DevHlp_ISASetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel)
756	{
757	PDMDEV_ASSERT_DEVINS(pDevIns);
758	LogFlow(("pdmR3DevHlp_ISASetIrq: caller='%s'/%d: iIrq=%d iLevel=%d\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, iIrq, iLevel));
759
760	/*
761	* Validate input.
762	*/
763	/** @todo iIrq and iLevel checks. */
764
765	PVM pVM = pDevIns->Internal.s.pVMR3;
766	PDMIsaSetIrq(pVM, iIrq, iLevel); /* (The API takes the lock.) */
767
768	LogFlow(("pdmR3DevHlp_ISASetIrq: caller='%s'/%d: returns void\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance));
769	}
770
771
772	/** @copydoc PDMDEVHLPR3::pfnISASetIrqNoWait */
773	static DECLCALLBACK(void) pdmR3DevHlp_ISASetIrqNoWait(PPDMDEVINS pDevIns, int iIrq, int iLevel)
774	{
775	pdmR3DevHlp_ISASetIrq(pDevIns, iIrq, iLevel);
776	}
777
778
779	/** @copydoc PDMDEVHLPR3::pfnDriverAttach */
780	static DECLCALLBACK(int) pdmR3DevHlp_DriverAttach(PPDMDEVINS pDevIns, RTUINT iLun, PPDMIBASE pBaseInterface, PPDMIBASE ppBaseInterface, const char pszDesc)
781	{
782	PDMDEV_ASSERT_DEVINS(pDevIns);
783	PVM pVM = pDevIns->Internal.s.pVMR3;
784	VM_ASSERT_EMT(pVM);
785	LogFlow(("pdmR3DevHlp_DriverAttach: caller='%s'/%d: iLun=%d pBaseInterface=%p ppBaseInterface=%p pszDesc=%p:{%s}\n",
786	pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, iLun, pBaseInterface, ppBaseInterface, pszDesc, pszDesc));
787
788	/*
789	* Lookup the LUN, it might already be registered.
790	*/
791	PPDMLUN pLunPrev = NULL;
792	PPDMLUN pLun = pDevIns->Internal.s.pLunsR3;
793	for (; pLun; pLunPrev = pLun, pLun = pLun->pNext)
794	if (pLun->iLun == iLun)
795	break;
796
797	/*
798	* Create the LUN if if wasn't found, else check if driver is already attached to it.
799	*/
800	if (!pLun)
801	{
802	if ( !pBaseInterface
803	\|\| !pszDesc
804	\|\| !*pszDesc)
805	{
806	Assert(pBaseInterface);
807	Assert(pszDesc \|\| *pszDesc);
808	return VERR_INVALID_PARAMETER;
809	}
810
811	pLun = (PPDMLUN)MMR3HeapAlloc(pVM, MM_TAG_PDM_LUN, sizeof(*pLun));
812	if (!pLun)
813	return VERR_NO_MEMORY;
814
815	pLun->iLun = iLun;
816	pLun->pNext = pLunPrev ? pLunPrev->pNext : NULL;
817	pLun->pTop = NULL;
818	pLun->pBottom = NULL;
819	pLun->pDevIns = pDevIns;
820	pLun->pszDesc = pszDesc;
821	pLun->pBase = pBaseInterface;
822	if (!pLunPrev)
823	pDevIns->Internal.s.pLunsR3 = pLun;
824	else
825	pLunPrev->pNext = pLun;
826	Log(("pdmR3DevHlp_DriverAttach: Registered LUN#%d '%s' with device '%s'/%d.\n",
827	iLun, pszDesc, pDevIns->pDevReg->szDeviceName, pDevIns->iInstance));
828	}
829	else if (pLun->pTop)
830	{
831	AssertMsgFailed(("Already attached! The device should keep track of such things!\n"));
832	LogFlow(("pdmR3DevHlp_DriverAttach: caller='%s'/%d: returns %Rrc\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, VERR_PDM_DRIVER_ALREADY_ATTACHED));
833	return VERR_PDM_DRIVER_ALREADY_ATTACHED;
834	}
835	Assert(pLun->pBase == pBaseInterface);
836
837
838	/*
839	* Get the attached driver configuration.
840	*/
841	int rc;
842	char szNode[48];
843	RTStrPrintf(szNode, sizeof(szNode), "LUN#%d", iLun);
844	PCFGMNODE pNode = CFGMR3GetChild(pDevIns->Internal.s.pCfgHandle, szNode);
845	if (pNode)
846	{
847	char *pszName;
848	rc = CFGMR3QueryStringAlloc(pNode, "Driver", &pszName);
849	if (RT_SUCCESS(rc))
850	{
851	/*
852	* Find the driver.
853	*/
854	PPDMDRV pDrv = pdmR3DrvLookup(pVM, pszName);
855	if (pDrv)
856	{
857	/* config node */
858	PCFGMNODE pConfigNode = CFGMR3GetChild(pNode, "Config");
859	if (!pConfigNode)
860	rc = CFGMR3InsertNode(pNode, "Config", &pConfigNode);
861	if (RT_SUCCESS(rc))
862	{
863	CFGMR3SetRestrictedRoot(pConfigNode);
864
865	/*
866	* Allocate the driver instance.
867	*/
868	size_t cb = RT_OFFSETOF(PDMDRVINS, achInstanceData[pDrv->pDrvReg->cbInstance]);
869	cb = RT_ALIGN_Z(cb, 16);
870	PPDMDRVINS pNew = (PPDMDRVINS)MMR3HeapAllocZ(pVM, MM_TAG_PDM_DRIVER, cb);
871	if (pNew)
872	{
873	/*
874	* Initialize the instance structure (declaration order).
875	*/
876	pNew->u32Version = PDM_DRVINS_VERSION;
877	//pNew->Internal.s.pUp = NULL;
878	//pNew->Internal.s.pDown = NULL;
879	pNew->Internal.s.pLun = pLun;
880	pNew->Internal.s.pDrv = pDrv;
881	pNew->Internal.s.pVM = pVM;
882	//pNew->Internal.s.fDetaching = false;
883	pNew->Internal.s.pCfgHandle = pNode;
884	pNew->pDrvHlp = &g_pdmR3DrvHlp;
885	pNew->pDrvReg = pDrv->pDrvReg;
886	pNew->pCfgHandle = pConfigNode;
887	pNew->iInstance = pDrv->cInstances++;
888	pNew->pUpBase = pBaseInterface;
889	//pNew->pDownBase = NULL;
890	//pNew->IBase.pfnQueryInterface = NULL;
891	pNew->pvInstanceData = &pNew->achInstanceData[0];
892
893	/*
894	* Link with LUN and call the constructor.
895	*/
896	pLun->pTop = pLun->pBottom = pNew;
897	rc = pDrv->pDrvReg->pfnConstruct(pNew, pNew->pCfgHandle);
898	if (RT_SUCCESS(rc))
899	{
900	MMR3HeapFree(pszName);
901	*ppBaseInterface = &pNew->IBase;
902	Log(("PDM: Attached driver '%s'/%d to LUN#%d on device '%s'/%d.\n",
903	pDrv->pDrvReg->szDriverName, pNew->iInstance, iLun, pDevIns->pDevReg->szDeviceName, pDevIns->iInstance));
904	LogFlow(("pdmR3DevHlp_DriverAttach: caller '%s'/%d: returns %Rrc\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, VINF_SUCCESS));
905
906	return rc; /* Might return != VINF_SUCCESS (e.g. VINF_NAT_DNS). */
907	}
908
909	/*
910	* Free the driver.
911	*/
912	pLun->pTop = pLun->pBottom = NULL;
913	ASMMemFill32(pNew, cb, 0xdeadd0d0);
914	MMR3HeapFree(pNew);
915	pDrv->cInstances--;
916	}
917	else
918	{
919	AssertMsgFailed(("Failed to allocate %d bytes for instantiating driver '%s'\n", cb, pszName));
920	rc = VERR_NO_MEMORY;
921	}
922	}
923	else
924	AssertMsgFailed(("Failed to create Config node! rc=%Rrc\n", rc));
925	}
926	else
927	{
928	AssertMsgFailed(("Driver '%s' wasn't found!\n", pszName));
929	rc = VERR_PDM_DRIVER_NOT_FOUND;
930	}
931	MMR3HeapFree(pszName);
932	}
933	else
934	{
935	AssertMsgFailed(("Query for string value of \"Driver\" -> %Rrc\n", rc));
936	if (rc == VERR_CFGM_VALUE_NOT_FOUND)
937	rc = VERR_PDM_CFG_MISSING_DRIVER_NAME;
938	}
939	}
940	else
941	rc = VERR_PDM_NO_ATTACHED_DRIVER;
942
943
944	LogFlow(("pdmR3DevHlp_DriverAttach: caller='%s'/%d: returns %Rrc\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, rc));
945	return rc;
946	}
947
948
949	/** @copydoc PDMDEVHLPR3::pfnMMHeapAlloc */
950	static DECLCALLBACK(void *) pdmR3DevHlp_MMHeapAlloc(PPDMDEVINS pDevIns, size_t cb)
951	{
952	PDMDEV_ASSERT_DEVINS(pDevIns);
953	LogFlow(("pdmR3DevHlp_MMHeapAlloc: caller='%s'/%d: cb=%#x\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, cb));
954
955	void *pv = MMR3HeapAlloc(pDevIns->Internal.s.pVMR3, MM_TAG_PDM_DEVICE_USER, cb);
956
957	LogFlow(("pdmR3DevHlp_MMHeapAlloc: caller='%s'/%d: returns %p\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, pv));
958	return pv;
959	}
960
961
962	/** @copydoc PDMDEVHLPR3::pfnMMHeapAllocZ */
963	static DECLCALLBACK(void *) pdmR3DevHlp_MMHeapAllocZ(PPDMDEVINS pDevIns, size_t cb)
964	{
965	PDMDEV_ASSERT_DEVINS(pDevIns);
966	LogFlow(("pdmR3DevHlp_MMHeapAllocZ: caller='%s'/%d: cb=%#x\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, cb));
967
968	void *pv = MMR3HeapAllocZ(pDevIns->Internal.s.pVMR3, MM_TAG_PDM_DEVICE_USER, cb);
969
970	LogFlow(("pdmR3DevHlp_MMHeapAllocZ: caller='%s'/%d: returns %p\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, pv));
971	return pv;
972	}
973
974
975	/** @copydoc PDMDEVHLPR3::pfnMMHeapFree */
976	static DECLCALLBACK(void) pdmR3DevHlp_MMHeapFree(PPDMDEVINS pDevIns, void *pv)
977	{
978	PDMDEV_ASSERT_DEVINS(pDevIns);
979	LogFlow(("pdmR3DevHlp_MMHeapFree: caller='%s'/%d: pv=%p\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, pv));
980
981	MMR3HeapFree(pv);
982
983	LogFlow(("pdmR3DevHlp_MMHeapAlloc: caller='%s'/%d: returns void\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance));
984	}
985
986
987	/** @copydoc PDMDEVHLPR3::pfnVMSetError */
988	static DECLCALLBACK(int) pdmR3DevHlp_VMSetError(PPDMDEVINS pDevIns, int rc, RT_SRC_POS_DECL, const char *pszFormat, ...)
989	{
990	PDMDEV_ASSERT_DEVINS(pDevIns);
991	va_list args;
992	va_start(args, pszFormat);
993	int rc2 = VMSetErrorV(pDevIns->Internal.s.pVMR3, rc, RT_SRC_POS_ARGS, pszFormat, args); Assert(rc2 == rc); NOREF(rc2);
994	va_end(args);
995	return rc;
996	}
997
998
999	/** @copydoc PDMDEVHLPR3::pfnVMSetErrorV */
1000	static DECLCALLBACK(int) pdmR3DevHlp_VMSetErrorV(PPDMDEVINS pDevIns, int rc, RT_SRC_POS_DECL, const char *pszFormat, va_list va)
1001	{
1002	PDMDEV_ASSERT_DEVINS(pDevIns);
1003	int rc2 = VMSetErrorV(pDevIns->Internal.s.pVMR3, rc, RT_SRC_POS_ARGS, pszFormat, va); Assert(rc2 == rc); NOREF(rc2);
1004	return rc;
1005	}
1006
1007
1008	/** @copydoc PDMDEVHLPR3::pfnVMSetRuntimeError */
1009	static DECLCALLBACK(int) pdmR3DevHlp_VMSetRuntimeError(PPDMDEVINS pDevIns, uint32_t fFlags, const char pszErrorId, const char pszFormat, ...)
1010	{
1011	PDMDEV_ASSERT_DEVINS(pDevIns);
1012	va_list args;
1013	va_start(args, pszFormat);
1014	int rc = VMSetRuntimeErrorV(pDevIns->Internal.s.pVMR3, fFlags, pszErrorId, pszFormat, args);
1015	va_end(args);
1016	return rc;
1017	}
1018
1019
1020	/** @copydoc PDMDEVHLPR3::pfnVMSetRuntimeErrorV */
1021	static DECLCALLBACK(int) pdmR3DevHlp_VMSetRuntimeErrorV(PPDMDEVINS pDevIns, uint32_t fFlags, const char pszErrorId, const char pszFormat, va_list va)
1022	{
1023	PDMDEV_ASSERT_DEVINS(pDevIns);
1024	int rc = VMSetRuntimeErrorV(pDevIns->Internal.s.pVMR3, fFlags, pszErrorId, pszFormat, va);
1025	return rc;
1026	}
1027
1028
1029	/** @copydoc PDMDEVHLPR3::pfnAssertEMT */
1030	static DECLCALLBACK(bool) pdmR3DevHlp_AssertEMT(PPDMDEVINS pDevIns, const char pszFile, unsigned iLine, const char pszFunction)
1031	{
1032	PDMDEV_ASSERT_DEVINS(pDevIns);
1033	if (VM_IS_EMT(pDevIns->Internal.s.pVMR3))
1034	return true;
1035
1036	char szMsg[100];
1037	RTStrPrintf(szMsg, sizeof(szMsg), "AssertEMT '%s'/%d\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance);
1038	AssertMsg1(szMsg, iLine, pszFile, pszFunction);
1039	AssertBreakpoint();
1040	return false;
1041	}
1042
1043
1044	/** @copydoc PDMDEVHLPR3::pfnAssertOther */
1045	static DECLCALLBACK(bool) pdmR3DevHlp_AssertOther(PPDMDEVINS pDevIns, const char pszFile, unsigned iLine, const char pszFunction)
1046	{
1047	PDMDEV_ASSERT_DEVINS(pDevIns);
1048	if (!VM_IS_EMT(pDevIns->Internal.s.pVMR3))
1049	return true;
1050
1051	char szMsg[100];
1052	RTStrPrintf(szMsg, sizeof(szMsg), "AssertOther '%s'/%d\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance);
1053	AssertMsg1(szMsg, iLine, pszFile, pszFunction);
1054	AssertBreakpoint();
1055	return false;
1056	}
1057
1058
1059	/** @copydoc PDMDEVHLPR3::pfnDBGFStopV */
1060	static DECLCALLBACK(int) pdmR3DevHlp_DBGFStopV(PPDMDEVINS pDevIns, const char pszFile, unsigned iLine, const char pszFunction, const char *pszFormat, va_list args)
1061	{
1062	PDMDEV_ASSERT_DEVINS(pDevIns);
1063	#ifdef LOG_ENABLED
1064	va_list va2;
1065	va_copy(va2, args);
1066	LogFlow(("pdmR3DevHlp_DBGFStopV: caller='%s'/%d: pszFile=%p:{%s} iLine=%d pszFunction=%p:{%s} pszFormat=%p:{%s} (%N)\n",
1067	pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, pszFile, pszFile, iLine, pszFunction, pszFunction, pszFormat, pszFormat, pszFormat, &va2));
1068	va_end(va2);
1069	#endif
1070
1071	PVM pVM = pDevIns->Internal.s.pVMR3;
1072	VM_ASSERT_EMT(pVM);
1073	int rc = DBGFR3EventSrcV(pVM, DBGFEVENT_DEV_STOP, pszFile, iLine, pszFunction, pszFormat, args);
1074
1075	LogFlow(("pdmR3DevHlp_DBGFStopV: caller='%s'/%d: returns %Rrc\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, rc));
1076	return rc;
1077	}
1078
1079
1080	/** @copydoc PDMDEVHLPR3::pfnDBGFInfoRegister */
1081	static DECLCALLBACK(int) pdmR3DevHlp_DBGFInfoRegister(PPDMDEVINS pDevIns, const char pszName, const char pszDesc, PFNDBGFHANDLERDEV pfnHandler)
1082	{
1083	PDMDEV_ASSERT_DEVINS(pDevIns);
1084	LogFlow(("pdmR3DevHlp_DBGFInfoRegister: caller='%s'/%d: pszName=%p:{%s} pszDesc=%p:{%s} pfnHandler=%p\n",
1085	pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, pszName, pszName, pszDesc, pszDesc, pfnHandler));
1086
1087	PVM pVM = pDevIns->Internal.s.pVMR3;
1088	VM_ASSERT_EMT(pVM);
1089	int rc = DBGFR3InfoRegisterDevice(pVM, pszName, pszDesc, pfnHandler, pDevIns);
1090
1091	LogFlow(("pdmR3DevHlp_DBGFInfoRegister: caller='%s'/%d: returns %Rrc\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, rc));
1092	return rc;
1093	}
1094
1095
1096	/** @copydoc PDMDEVHLPR3::pfnSTAMRegister */
1097	static DECLCALLBACK(void) pdmR3DevHlp_STAMRegister(PPDMDEVINS pDevIns, void pvSample, STAMTYPE enmType, const char pszName, STAMUNIT enmUnit, const char *pszDesc)
1098	{
1099	PDMDEV_ASSERT_DEVINS(pDevIns);
1100	PVM pVM = pDevIns->Internal.s.pVMR3;
1101	VM_ASSERT_EMT(pVM);
1102
1103	STAM_REG(pVM, pvSample, enmType, pszName, enmUnit, pszDesc);
1104	NOREF(pVM);
1105	}
1106
1107
1108
1109	/** @copydoc PDMDEVHLPR3::pfnSTAMRegisterF */
1110	static DECLCALLBACK(void) pdmR3DevHlp_STAMRegisterF(PPDMDEVINS pDevIns, void *pvSample, STAMTYPE enmType, STAMVISIBILITY enmVisibility,
1111	STAMUNIT enmUnit, const char pszDesc, const char pszName, ...)
1112	{
1113	PDMDEV_ASSERT_DEVINS(pDevIns);
1114	PVM pVM = pDevIns->Internal.s.pVMR3;
1115	VM_ASSERT_EMT(pVM);
1116
1117	va_list args;
1118	va_start(args, pszName);
1119	int rc = STAMR3RegisterV(pVM, pvSample, enmType, enmVisibility, enmUnit, pszDesc, pszName, args);
1120	va_end(args);
1121	AssertRC(rc);
1122
1123	NOREF(pVM);
1124	}
1125
1126
1127	/** @copydoc PDMDEVHLPR3::pfnSTAMRegisterV */
1128	static DECLCALLBACK(void) pdmR3DevHlp_STAMRegisterV(PPDMDEVINS pDevIns, void *pvSample, STAMTYPE enmType, STAMVISIBILITY enmVisibility,
1129	STAMUNIT enmUnit, const char pszDesc, const char pszName, va_list args)
1130	{
1131	PDMDEV_ASSERT_DEVINS(pDevIns);
1132	PVM pVM = pDevIns->Internal.s.pVMR3;
1133	VM_ASSERT_EMT(pVM);
1134
1135	int rc = STAMR3RegisterV(pVM, pvSample, enmType, enmVisibility, enmUnit, pszDesc, pszName, args);
1136	AssertRC(rc);
1137
1138	NOREF(pVM);
1139	}
1140
1141
1142	/** @copydoc PDMDEVHLPR3::pfnRTCRegister */
1143	static DECLCALLBACK(int) pdmR3DevHlp_RTCRegister(PPDMDEVINS pDevIns, PCPDMRTCREG pRtcReg, PCPDMRTCHLP *ppRtcHlp)
1144	{
1145	PDMDEV_ASSERT_DEVINS(pDevIns);
1146	VM_ASSERT_EMT(pDevIns->Internal.s.pVMR3);
1147	LogFlow(("pdmR3DevHlp_RTCRegister: caller='%s'/%d: pRtcReg=%p:{.u32Version=%#x, .pfnWrite=%p, .pfnRead=%p} ppRtcHlp=%p\n",
1148	pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, pRtcReg, pRtcReg->u32Version, pRtcReg->pfnWrite,
1149	pRtcReg->pfnWrite, ppRtcHlp));
1150
1151	/*
1152	* Validate input.
1153	*/
1154	if (pRtcReg->u32Version != PDM_RTCREG_VERSION)
1155	{
1156	AssertMsgFailed(("u32Version=%#x expected %#x\n", pRtcReg->u32Version,
1157	PDM_RTCREG_VERSION));
1158	LogFlow(("pdmR3DevHlp_RTCRegister: caller='%s'/%d: returns %Rrc (version)\n",
1159	pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
1160	return VERR_INVALID_PARAMETER;
1161	}
1162	if ( !pRtcReg->pfnWrite
1163	\|\| !pRtcReg->pfnRead)
1164	{
1165	Assert(pRtcReg->pfnWrite);
1166	Assert(pRtcReg->pfnRead);
1167	LogFlow(("pdmR3DevHlp_RTCRegister: caller='%s'/%d: returns %Rrc (callbacks)\n",
1168	pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
1169	return VERR_INVALID_PARAMETER;
1170	}
1171
1172	if (!ppRtcHlp)
1173	{
1174	Assert(ppRtcHlp);
1175	LogFlow(("pdmR3DevHlp_RTCRegister: caller='%s'/%d: returns %Rrc (ppRtcHlp)\n",
1176	pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
1177	return VERR_INVALID_PARAMETER;
1178	}
1179
1180	/*
1181	* Only one DMA device.
1182	*/
1183	PVM pVM = pDevIns->Internal.s.pVMR3;
1184	if (pVM->pdm.s.pRtc)
1185	{
1186	AssertMsgFailed(("Only one RTC device is supported!\n"));
1187	LogFlow(("pdmR3DevHlp_RTCRegister: caller='%s'/%d: returns %Rrc\n",
1188	pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
1189	return VERR_INVALID_PARAMETER;
1190	}
1191
1192	/*
1193	* Allocate and initialize pci bus structure.
1194	*/
1195	int rc = VINF_SUCCESS;
1196	PPDMRTC pRtc = (PPDMRTC)MMR3HeapAlloc(pDevIns->Internal.s.pVMR3, MM_TAG_PDM_DEVICE, sizeof(*pRtc));
1197	if (pRtc)
1198	{
1199	pRtc->pDevIns = pDevIns;
1200	pRtc->Reg = *pRtcReg;
1201	pVM->pdm.s.pRtc = pRtc;
1202
1203	/* set the helper pointer. */
1204	*ppRtcHlp = &g_pdmR3DevRtcHlp;
1205	Log(("PDM: Registered RTC device '%s'/%d pDevIns=%p\n",
1206	pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, pDevIns));
1207	}
1208	else
1209	rc = VERR_NO_MEMORY;
1210
1211	LogFlow(("pdmR3DevHlp_RTCRegister: caller='%s'/%d: returns %Rrc\n",
1212	pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, rc));
1213	return rc;
1214	}
1215
1216
1217	/** @copydoc PDMDEVHLPR3::pfnPDMQueueCreate */
1218	static DECLCALLBACK(int) pdmR3DevHlp_PDMQueueCreate(PPDMDEVINS pDevIns, RTUINT cbItem, RTUINT cItems, uint32_t cMilliesInterval,
1219	PFNPDMQUEUEDEV pfnCallback, bool fGCEnabled, PPDMQUEUE *ppQueue)
1220	{
1221	PDMDEV_ASSERT_DEVINS(pDevIns);
1222	LogFlow(("pdmR3DevHlp_PDMQueueCreate: caller='%s'/%d: cbItem=%#x cItems=%#x cMilliesInterval=%u pfnCallback=%p fGCEnabled=%RTbool ppQueue=%p\n",
1223	pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, cbItem, cItems, cMilliesInterval, pfnCallback, fGCEnabled, ppQueue));
1224
1225	PVM pVM = pDevIns->Internal.s.pVMR3;
1226	VM_ASSERT_EMT(pVM);
1227	int rc = PDMR3QueueCreateDevice(pVM, pDevIns, cbItem, cItems, cMilliesInterval, pfnCallback, fGCEnabled, ppQueue);
1228
1229	LogFlow(("pdmR3DevHlp_PDMQueueCreate: caller='%s'/%d: returns %Rrc ppQueue=%p\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, rc, ppQueue));
1230	return rc;
1231	}
1232
1233
1234	/** @copydoc PDMDEVHLPR3::pfnCritSectInit */
1235	static DECLCALLBACK(int) pdmR3DevHlp_CritSectInit(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, const char *pszName)
1236	{
1237	PDMDEV_ASSERT_DEVINS(pDevIns);
1238	LogFlow(("pdmR3DevHlp_CritSectInit: caller='%s'/%d: pCritSect=%p pszName=%p:{%s}\n",
1239	pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, pCritSect, pszName, pszName));
1240
1241	PVM pVM = pDevIns->Internal.s.pVMR3;
1242	VM_ASSERT_EMT(pVM);
1243	int rc = pdmR3CritSectInitDevice(pVM, pDevIns, pCritSect, pszName);
1244
1245	LogFlow(("pdmR3DevHlp_CritSectInit: caller='%s'/%d: returns %Rrc\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, rc));
1246	return rc;
1247	}
1248
1249
1250	/** @copydoc PDMDEVHLPR3::pfnUTCNow */
1251	static DECLCALLBACK(PRTTIMESPEC) pdmR3DevHlp_UTCNow(PPDMDEVINS pDevIns, PRTTIMESPEC pTime)
1252	{
1253	PDMDEV_ASSERT_DEVINS(pDevIns);
1254	LogFlow(("pdmR3DevHlp_UTCNow: caller='%s'/%d: pTime=%p\n",
1255	pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, pTime));
1256
1257	pTime = TMR3UTCNow(pDevIns->Internal.s.pVMR3, pTime);
1258
1259	LogFlow(("pdmR3DevHlp_UTCNow: caller='%s'/%d: returns %RU64\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, RTTimeSpecGetNano(pTime)));
1260	return pTime;
1261	}
1262
1263
1264	/** @copydoc PDMDEVHLPR3::pfnPDMThreadCreate */
1265	static DECLCALLBACK(int) pdmR3DevHlp_PDMThreadCreate(PPDMDEVINS pDevIns, PPPDMTHREAD ppThread, void *pvUser, PFNPDMTHREADDEV pfnThread,
1266	PFNPDMTHREADWAKEUPDEV pfnWakeup, size_t cbStack, RTTHREADTYPE enmType, const char *pszName)
1267	{
1268	PDMDEV_ASSERT_DEVINS(pDevIns);
1269	VM_ASSERT_EMT(pDevIns->Internal.s.pVMR3);
1270	LogFlow(("pdmR3DevHlp_PDMThreadCreate: caller='%s'/%d: ppThread=%p pvUser=%p pfnThread=%p pfnWakeup=%p cbStack=%#zx enmType=%d pszName=%p:{%s}\n",
1271	pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, ppThread, pvUser, pfnThread, pfnWakeup, cbStack, enmType, pszName, pszName));
1272
1273	int rc = pdmR3ThreadCreateDevice(pDevIns->Internal.s.pVMR3, pDevIns, ppThread, pvUser, pfnThread, pfnWakeup, cbStack, enmType, pszName);
1274
1275	LogFlow(("pdmR3DevHlp_PDMThreadCreate: caller='%s'/%d: returns %Rrc *ppThread=%RTthrd\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance,
1276	rc, *ppThread));
1277	return rc;
1278	}
1279
1280
1281	/** @copydoc PDMDEVHLPR3::pfnGetVM */
1282	static DECLCALLBACK(PVM) pdmR3DevHlp_GetVM(PPDMDEVINS pDevIns)
1283	{
1284	PDMDEV_ASSERT_DEVINS(pDevIns);
1285	LogFlow(("pdmR3DevHlp_GetVM: caller='%s'/%d: returns %p\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, pDevIns->Internal.s.pVMR3));
1286	return pDevIns->Internal.s.pVMR3;
1287	}
1288
1289
1290	/** @copydoc PDMDEVHLPR3::pfnGetVMCPU */
1291	static DECLCALLBACK(PVMCPU) pdmR3DevHlp_GetVMCPU(PPDMDEVINS pDevIns)
1292	{
1293	PDMDEV_ASSERT_DEVINS(pDevIns);
1294	VM_ASSERT_EMT(pDevIns->Internal.s.pVMR3);
1295	LogFlow(("pdmR3DevHlp_GetVMCPU: caller='%s'/%d for CPU %u\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, VMMGetCpuId(pDevIns->Internal.s.pVMR3)));
1296	return VMMGetCpu(pDevIns->Internal.s.pVMR3);
1297	}
1298
1299
1300	/** @copydoc PDMDEVHLPR3::pfnPCIBusRegister */
1301	static DECLCALLBACK(int) pdmR3DevHlp_PCIBusRegister(PPDMDEVINS pDevIns, PPDMPCIBUSREG pPciBusReg, PCPDMPCIHLPR3 *ppPciHlpR3)
1302	{
1303	PDMDEV_ASSERT_DEVINS(pDevIns);
1304	PVM pVM = pDevIns->Internal.s.pVMR3;
1305	VM_ASSERT_EMT(pVM);
1306	LogFlow(("pdmR3DevHlp_PCIBusRegister: caller='%s'/%d: pPciBusReg=%p:{.u32Version=%#x, .pfnRegisterR3=%p, .pfnIORegionRegisterR3=%p, .pfnSetIrqR3=%p, "
1307	".pfnSaveExecR3=%p, .pfnLoadExecR3=%p, .pfnFakePCIBIOSR3=%p, .pszSetIrqRC=%p:{%s}, .pszSetIrqR0=%p:{%s}} ppPciHlpR3=%p\n",
1308	pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, pPciBusReg, pPciBusReg->u32Version, pPciBusReg->pfnRegisterR3,
1309	pPciBusReg->pfnIORegionRegisterR3, pPciBusReg->pfnSetIrqR3, pPciBusReg->pfnSaveExecR3, pPciBusReg->pfnLoadExecR3,
1310	pPciBusReg->pfnFakePCIBIOSR3, pPciBusReg->pszSetIrqRC, pPciBusReg->pszSetIrqRC, pPciBusReg->pszSetIrqR0, pPciBusReg->pszSetIrqR0, ppPciHlpR3));
1311
1312	/*
1313	* Validate the structure.
1314	*/
1315	if (pPciBusReg->u32Version != PDM_PCIBUSREG_VERSION)
1316	{
1317	AssertMsgFailed(("u32Version=%#x expected %#x\n", pPciBusReg->u32Version, PDM_PCIBUSREG_VERSION));
1318	LogFlow(("pdmR3DevHlp_PCIRegister: caller='%s'/%d: returns %Rrc (version)\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
1319	return VERR_INVALID_PARAMETER;
1320	}
1321	if ( !pPciBusReg->pfnRegisterR3
1322	\|\| !pPciBusReg->pfnIORegionRegisterR3
1323	\|\| !pPciBusReg->pfnSetIrqR3
1324	\|\| !pPciBusReg->pfnSaveExecR3
1325	\|\| !pPciBusReg->pfnLoadExecR3
1326	\|\| (!pPciBusReg->pfnFakePCIBIOSR3 && !pVM->pdm.s.aPciBuses[0].pDevInsR3)) /* Only the first bus needs to do the BIOS work. */
1327	{
1328	Assert(pPciBusReg->pfnRegisterR3);
1329	Assert(pPciBusReg->pfnIORegionRegisterR3);
1330	Assert(pPciBusReg->pfnSetIrqR3);
1331	Assert(pPciBusReg->pfnSaveExecR3);
1332	Assert(pPciBusReg->pfnLoadExecR3);
1333	Assert(pPciBusReg->pfnFakePCIBIOSR3);
1334	LogFlow(("pdmR3DevHlp_PCIBusRegister: caller='%s'/%d: returns %Rrc (R3 callbacks)\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
1335	return VERR_INVALID_PARAMETER;
1336	}
1337	if ( pPciBusReg->pszSetIrqRC
1338	&& !VALID_PTR(pPciBusReg->pszSetIrqRC))
1339	{
1340	Assert(VALID_PTR(pPciBusReg->pszSetIrqRC));
1341	LogFlow(("pdmR3DevHlp_PCIBusRegister: caller='%s'/%d: returns %Rrc (GC callbacks)\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
1342	return VERR_INVALID_PARAMETER;
1343	}
1344	if ( pPciBusReg->pszSetIrqR0
1345	&& !VALID_PTR(pPciBusReg->pszSetIrqR0))
1346	{
1347	Assert(VALID_PTR(pPciBusReg->pszSetIrqR0));
1348	LogFlow(("pdmR3DevHlp_PCIBusRegister: caller='%s'/%d: returns %Rrc (GC callbacks)\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
1349	return VERR_INVALID_PARAMETER;
1350	}
1351	if (!ppPciHlpR3)
1352	{
1353	Assert(ppPciHlpR3);
1354	LogFlow(("pdmR3DevHlp_PCIBusRegister: caller='%s'/%d: returns %Rrc (ppPciHlpR3)\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
1355	return VERR_INVALID_PARAMETER;
1356	}
1357
1358	/*
1359	* Find free PCI bus entry.
1360	*/
1361	unsigned iBus = 0;
1362	for (iBus = 0; iBus < RT_ELEMENTS(pVM->pdm.s.aPciBuses); iBus++)
1363	if (!pVM->pdm.s.aPciBuses[iBus].pDevInsR3)
1364	break;
1365	if (iBus >= RT_ELEMENTS(pVM->pdm.s.aPciBuses))
1366	{
1367	AssertMsgFailed(("Too many PCI buses. Max=%u\n", RT_ELEMENTS(pVM->pdm.s.aPciBuses)));
1368	LogFlow(("pdmR3DevHlp_PCIBusRegister: caller='%s'/%d: returns %Rrc (pci bus)\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
1369	return VERR_INVALID_PARAMETER;
1370	}
1371	PPDMPCIBUS pPciBus = &pVM->pdm.s.aPciBuses[iBus];
1372
1373	/*
1374	* Resolve and init the RC bits.
1375	*/
1376	if (pPciBusReg->pszSetIrqRC)
1377	{
1378	int rc = PDMR3LdrGetSymbolRCLazy(pVM, pDevIns->pDevReg->szRCMod, pPciBusReg->pszSetIrqRC, &pPciBus->pfnSetIrqRC);
1379	AssertMsgRC(rc, ("%s::%s rc=%Rrc\n", pDevIns->pDevReg->szRCMod, pPciBusReg->pszSetIrqRC, rc));
1380	if (RT_FAILURE(rc))
1381	{
1382	LogFlow(("pdmR3DevHlp_PCIRegister: caller='%s'/%d: returns %Rrc\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, rc));
1383	return rc;
1384	}
1385	pPciBus->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
1386	}
1387	else
1388	{
1389	pPciBus->pfnSetIrqRC = 0;
1390	pPciBus->pDevInsRC = 0;
1391	}
1392
1393	/*
1394	* Resolve and init the R0 bits.
1395	*/
1396	if (pPciBusReg->pszSetIrqR0)
1397	{
1398	int rc = PDMR3LdrGetSymbolR0Lazy(pVM, pDevIns->pDevReg->szR0Mod, pPciBusReg->pszSetIrqR0, &pPciBus->pfnSetIrqR0);
1399	AssertMsgRC(rc, ("%s::%s rc=%Rrc\n", pDevIns->pDevReg->szR0Mod, pPciBusReg->pszSetIrqR0, rc));
1400	if (RT_FAILURE(rc))
1401	{
1402	LogFlow(("pdmR3DevHlp_PCIRegister: caller='%s'/%d: returns %Rrc\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, rc));
1403	return rc;
1404	}
1405	pPciBus->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
1406	}
1407	else
1408	{
1409	pPciBus->pfnSetIrqR0 = 0;
1410	pPciBus->pDevInsR0 = 0;
1411	}
1412
1413	/*
1414	* Init the R3 bits.
1415	*/
1416	pPciBus->iBus = iBus;
1417	pPciBus->pDevInsR3 = pDevIns;
1418	pPciBus->pfnRegisterR3 = pPciBusReg->pfnRegisterR3;
1419	pPciBus->pfnIORegionRegisterR3 = pPciBusReg->pfnIORegionRegisterR3;
1420	pPciBus->pfnSetConfigCallbacksR3 = pPciBusReg->pfnSetConfigCallbacksR3;
1421	pPciBus->pfnSetIrqR3 = pPciBusReg->pfnSetIrqR3;
1422	pPciBus->pfnSaveExecR3 = pPciBusReg->pfnSaveExecR3;
1423	pPciBus->pfnLoadExecR3 = pPciBusReg->pfnLoadExecR3;
1424	pPciBus->pfnFakePCIBIOSR3 = pPciBusReg->pfnFakePCIBIOSR3;
1425
1426	Log(("PDM: Registered PCI bus device '%s'/%d pDevIns=%p\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, pDevIns));
1427
1428	/* set the helper pointer and return. */
1429	*ppPciHlpR3 = &g_pdmR3DevPciHlp;
1430	LogFlow(("pdmR3DevHlp_PCIBusRegister: caller='%s'/%d: returns %Rrc\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, VINF_SUCCESS));
1431	return VINF_SUCCESS;
1432	}
1433
1434
1435	/** @copydoc PDMDEVHLPR3::pfnPICRegister */
1436	static DECLCALLBACK(int) pdmR3DevHlp_PICRegister(PPDMDEVINS pDevIns, PPDMPICREG pPicReg, PCPDMPICHLPR3 *ppPicHlpR3)
1437	{
1438	PDMDEV_ASSERT_DEVINS(pDevIns);
1439	VM_ASSERT_EMT(pDevIns->Internal.s.pVMR3);
1440	LogFlow(("pdmR3DevHlp_PICRegister: caller='%s'/%d: pPicReg=%p:{.u32Version=%#x, .pfnSetIrqR3=%p, .pfnGetInterruptR3=%p, .pszGetIrqRC=%p:{%s}, .pszGetInterruptRC=%p:{%s}, .pszGetIrqR0=%p:{%s}, .pszGetInterruptR0=%p:{%s} } ppPicHlpR3=%p\n",
1441	pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, pPicReg, pPicReg->u32Version, pPicReg->pfnSetIrqR3, pPicReg->pfnGetInterruptR3,
1442	pPicReg->pszSetIrqRC, pPicReg->pszSetIrqRC, pPicReg->pszGetInterruptRC, pPicReg->pszGetInterruptRC,
1443	pPicReg->pszSetIrqR0, pPicReg->pszSetIrqR0, pPicReg->pszGetInterruptR0, pPicReg->pszGetInterruptR0,
1444	ppPicHlpR3));
1445
1446	/*
1447	* Validate input.
1448	*/
1449	if (pPicReg->u32Version != PDM_PICREG_VERSION)
1450	{
1451	AssertMsgFailed(("u32Version=%#x expected %#x\n", pPicReg->u32Version, PDM_PICREG_VERSION));
1452	LogFlow(("pdmR3DevHlp_PICRegister: caller='%s'/%d: returns %Rrc (version)\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
1453	return VERR_INVALID_PARAMETER;
1454	}
1455	if ( !pPicReg->pfnSetIrqR3
1456	\|\| !pPicReg->pfnGetInterruptR3)
1457	{
1458	Assert(pPicReg->pfnSetIrqR3);
1459	Assert(pPicReg->pfnGetInterruptR3);
1460	LogFlow(("pdmR3DevHlp_PICRegister: caller='%s'/%d: returns %Rrc (R3 callbacks)\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
1461	return VERR_INVALID_PARAMETER;
1462	}
1463	if ( ( pPicReg->pszSetIrqRC
1464	\|\| pPicReg->pszGetInterruptRC)
1465	&& ( !VALID_PTR(pPicReg->pszSetIrqRC)
1466	\|\| !VALID_PTR(pPicReg->pszGetInterruptRC))
1467	)
1468	{
1469	Assert(VALID_PTR(pPicReg->pszSetIrqRC));
1470	Assert(VALID_PTR(pPicReg->pszGetInterruptRC));
1471	LogFlow(("pdmR3DevHlp_PICRegister: caller='%s'/%d: returns %Rrc (RC callbacks)\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
1472	return VERR_INVALID_PARAMETER;
1473	}
1474	if ( pPicReg->pszSetIrqRC
1475	&& !(pDevIns->pDevReg->fFlags & PDM_DEVREG_FLAGS_RC))
1476	{
1477	Assert(pDevIns->pDevReg->fFlags & PDM_DEVREG_FLAGS_RC);
1478	LogFlow(("pdmR3DevHlp_PICRegister: caller='%s'/%d: returns %Rrc (RC flag)\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
1479	return VERR_INVALID_PARAMETER;
1480	}
1481	if ( pPicReg->pszSetIrqR0
1482	&& !(pDevIns->pDevReg->fFlags & PDM_DEVREG_FLAGS_R0))
1483	{
1484	Assert(pDevIns->pDevReg->fFlags & PDM_DEVREG_FLAGS_R0);
1485	LogFlow(("pdmR3DevHlp_PICRegister: caller='%s'/%d: returns %Rrc (R0 flag)\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
1486	return VERR_INVALID_PARAMETER;
1487	}
1488	if (!ppPicHlpR3)
1489	{
1490	Assert(ppPicHlpR3);
1491	LogFlow(("pdmR3DevHlp_PICRegister: caller='%s'/%d: returns %Rrc (ppPicHlpR3)\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
1492	return VERR_INVALID_PARAMETER;
1493	}
1494
1495	/*
1496	* Only one PIC device.
1497	*/
1498	PVM pVM = pDevIns->Internal.s.pVMR3;
1499	if (pVM->pdm.s.Pic.pDevInsR3)
1500	{
1501	AssertMsgFailed(("Only one pic device is supported!\n"));
1502	LogFlow(("pdmR3DevHlp_PICRegister: caller='%s'/%d: returns %Rrc\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
1503	return VERR_INVALID_PARAMETER;
1504	}
1505
1506	/*
1507	* RC stuff.
1508	*/
1509	if (pPicReg->pszSetIrqRC)
1510	{
1511	int rc = PDMR3LdrGetSymbolRCLazy(pVM, pDevIns->pDevReg->szRCMod, pPicReg->pszSetIrqRC, &pVM->pdm.s.Pic.pfnSetIrqRC);
1512	AssertMsgRC(rc, ("%s::%s rc=%Rrc\n", pDevIns->pDevReg->szRCMod, pPicReg->pszSetIrqRC, rc));
1513	if (RT_SUCCESS(rc))
1514	{
1515	rc = PDMR3LdrGetSymbolRCLazy(pVM, pDevIns->pDevReg->szRCMod, pPicReg->pszGetInterruptRC, &pVM->pdm.s.Pic.pfnGetInterruptRC);
1516	AssertMsgRC(rc, ("%s::%s rc=%Rrc\n", pDevIns->pDevReg->szRCMod, pPicReg->pszGetInterruptRC, rc));
1517	}
1518	if (RT_FAILURE(rc))
1519	{
1520	LogFlow(("pdmR3DevHlp_PICRegister: caller='%s'/%d: returns %Rrc\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, rc));
1521	return rc;
1522	}
1523	pVM->pdm.s.Pic.pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
1524	}
1525	else
1526	{
1527	pVM->pdm.s.Pic.pDevInsRC = 0;
1528	pVM->pdm.s.Pic.pfnSetIrqRC = 0;
1529	pVM->pdm.s.Pic.pfnGetInterruptRC = 0;
1530	}
1531
1532	/*
1533	* R0 stuff.
1534	*/
1535	if (pPicReg->pszSetIrqR0)
1536	{
1537	int rc = PDMR3LdrGetSymbolR0Lazy(pVM, pDevIns->pDevReg->szR0Mod, pPicReg->pszSetIrqR0, &pVM->pdm.s.Pic.pfnSetIrqR0);
1538	AssertMsgRC(rc, ("%s::%s rc=%Rrc\n", pDevIns->pDevReg->szR0Mod, pPicReg->pszSetIrqR0, rc));
1539	if (RT_SUCCESS(rc))
1540	{
1541	rc = PDMR3LdrGetSymbolR0Lazy(pVM, pDevIns->pDevReg->szR0Mod, pPicReg->pszGetInterruptR0, &pVM->pdm.s.Pic.pfnGetInterruptR0);
1542	AssertMsgRC(rc, ("%s::%s rc=%Rrc\n", pDevIns->pDevReg->szR0Mod, pPicReg->pszGetInterruptR0, rc));
1543	}
1544	if (RT_FAILURE(rc))
1545	{
1546	LogFlow(("pdmR3DevHlp_PICRegister: caller='%s'/%d: returns %Rrc\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, rc));
1547	return rc;
1548	}
1549	pVM->pdm.s.Pic.pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
1550	Assert(pVM->pdm.s.Pic.pDevInsR0);
1551	}
1552	else
1553	{
1554	pVM->pdm.s.Pic.pfnSetIrqR0 = 0;
1555	pVM->pdm.s.Pic.pfnGetInterruptR0 = 0;
1556	pVM->pdm.s.Pic.pDevInsR0 = 0;
1557	}
1558
1559	/*
1560	* R3 stuff.
1561	*/
1562	pVM->pdm.s.Pic.pDevInsR3 = pDevIns;
1563	pVM->pdm.s.Pic.pfnSetIrqR3 = pPicReg->pfnSetIrqR3;
1564	pVM->pdm.s.Pic.pfnGetInterruptR3 = pPicReg->pfnGetInterruptR3;
1565	Log(("PDM: Registered PIC device '%s'/%d pDevIns=%p\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, pDevIns));
1566
1567	/* set the helper pointer and return. */
1568	*ppPicHlpR3 = &g_pdmR3DevPicHlp;
1569	LogFlow(("pdmR3DevHlp_PICRegister: caller='%s'/%d: returns %Rrc\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, VINF_SUCCESS));
1570	return VINF_SUCCESS;
1571	}
1572
1573
1574	/** @copydoc PDMDEVHLPR3::pfnAPICRegister */
1575	static DECLCALLBACK(int) pdmR3DevHlp_APICRegister(PPDMDEVINS pDevIns, PPDMAPICREG pApicReg, PCPDMAPICHLPR3 *ppApicHlpR3)
1576	{
1577	PDMDEV_ASSERT_DEVINS(pDevIns);
1578	VM_ASSERT_EMT(pDevIns->Internal.s.pVMR3);
1579	LogFlow(("pdmR3DevHlp_APICRegister: caller='%s'/%d: pApicReg=%p:{.u32Version=%#x, .pfnGetInterruptR3=%p, .pfnSetBaseR3=%p, .pfnGetBaseR3=%p, "
1580	".pfnSetTPRR3=%p, .pfnGetTPRR3=%p, .pfnWriteMSR3=%p, .pfnReadMSR3=%p, .pfnBusDeliverR3=%p, pszGetInterruptRC=%p:{%s}, pszSetBaseRC=%p:{%s}, pszGetBaseRC=%p:{%s}, "
1581	".pszSetTPRRC=%p:{%s}, .pszGetTPRRC=%p:{%s}, .pszWriteMSRRC=%p:{%s}, .pszReadMSRRC=%p:{%s}, .pszBusDeliverRC=%p:{%s}} ppApicHlpR3=%p\n",
1582	pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, pApicReg, pApicReg->u32Version, pApicReg->pfnGetInterruptR3, pApicReg->pfnSetBaseR3,
1583	pApicReg->pfnGetBaseR3, pApicReg->pfnSetTPRR3, pApicReg->pfnGetTPRR3, pApicReg->pfnWriteMSRR3, pApicReg->pfnReadMSRR3, pApicReg->pfnBusDeliverR3, pApicReg->pszGetInterruptRC,
1584	pApicReg->pszGetInterruptRC, pApicReg->pszSetBaseRC, pApicReg->pszSetBaseRC, pApicReg->pszGetBaseRC, pApicReg->pszGetBaseRC,
1585	pApicReg->pszSetTPRRC, pApicReg->pszSetTPRRC, pApicReg->pszGetTPRRC, pApicReg->pszGetTPRRC, pApicReg->pszWriteMSRRC, pApicReg->pszWriteMSRRC, pApicReg->pszReadMSRRC, pApicReg->pszReadMSRRC, pApicReg->pszBusDeliverRC,
1586	pApicReg->pszBusDeliverRC, ppApicHlpR3));
1587
1588	/*
1589	* Validate input.
1590	*/
1591	if (pApicReg->u32Version != PDM_APICREG_VERSION)
1592	{
1593	AssertMsgFailed(("u32Version=%#x expected %#x\n", pApicReg->u32Version, PDM_APICREG_VERSION));
1594	LogFlow(("pdmR3DevHlp_APICRegister: caller='%s'/%d: returns %Rrc (version)\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
1595	return VERR_INVALID_PARAMETER;
1596	}
1597	if ( !pApicReg->pfnGetInterruptR3
1598	\|\| !pApicReg->pfnHasPendingIrqR3
1599	\|\| !pApicReg->pfnSetBaseR3
1600	\|\| !pApicReg->pfnGetBaseR3
1601	\|\| !pApicReg->pfnSetTPRR3
1602	\|\| !pApicReg->pfnGetTPRR3
1603	\|\| !pApicReg->pfnWriteMSRR3
1604	\|\| !pApicReg->pfnReadMSRR3
1605	\|\| !pApicReg->pfnBusDeliverR3)
1606	{
1607	Assert(pApicReg->pfnGetInterruptR3);
1608	Assert(pApicReg->pfnHasPendingIrqR3);
1609	Assert(pApicReg->pfnSetBaseR3);
1610	Assert(pApicReg->pfnGetBaseR3);
1611	Assert(pApicReg->pfnSetTPRR3);
1612	Assert(pApicReg->pfnGetTPRR3);
1613	Assert(pApicReg->pfnWriteMSRR3);
1614	Assert(pApicReg->pfnReadMSRR3);
1615	Assert(pApicReg->pfnBusDeliverR3);
1616	LogFlow(("pdmR3DevHlp_APICRegister: caller='%s'/%d: returns %Rrc (R3 callbacks)\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
1617	return VERR_INVALID_PARAMETER;
1618	}
1619	if ( ( pApicReg->pszGetInterruptRC
1620	\|\| pApicReg->pszHasPendingIrqRC
1621	\|\| pApicReg->pszSetBaseRC
1622	\|\| pApicReg->pszGetBaseRC
1623	\|\| pApicReg->pszSetTPRRC
1624	\|\| pApicReg->pszGetTPRRC
1625	\|\| pApicReg->pszWriteMSRRC
1626	\|\| pApicReg->pszReadMSRRC
1627	\|\| pApicReg->pszBusDeliverRC)
1628	&& ( !VALID_PTR(pApicReg->pszGetInterruptRC)
1629	\|\| !VALID_PTR(pApicReg->pszHasPendingIrqRC)
1630	\|\| !VALID_PTR(pApicReg->pszSetBaseRC)
1631	\|\| !VALID_PTR(pApicReg->pszGetBaseRC)
1632	\|\| !VALID_PTR(pApicReg->pszSetTPRRC)
1633	\|\| !VALID_PTR(pApicReg->pszGetTPRRC)
1634	\|\| !VALID_PTR(pApicReg->pszWriteMSRRC)
1635	\|\| !VALID_PTR(pApicReg->pszReadMSRRC)
1636	\|\| !VALID_PTR(pApicReg->pszBusDeliverRC))
1637	)
1638	{
1639	Assert(VALID_PTR(pApicReg->pszGetInterruptRC));
1640	Assert(VALID_PTR(pApicReg->pszHasPendingIrqRC));
1641	Assert(VALID_PTR(pApicReg->pszSetBaseRC));
1642	Assert(VALID_PTR(pApicReg->pszGetBaseRC));
1643	Assert(VALID_PTR(pApicReg->pszSetTPRRC));
1644	Assert(VALID_PTR(pApicReg->pszGetTPRRC));
1645	Assert(VALID_PTR(pApicReg->pszReadMSRRC));
1646	Assert(VALID_PTR(pApicReg->pszWriteMSRRC));
1647	Assert(VALID_PTR(pApicReg->pszBusDeliverRC));
1648	LogFlow(("pdmR3DevHlp_APICRegister: caller='%s'/%d: returns %Rrc (RC callbacks)\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
1649	return VERR_INVALID_PARAMETER;
1650	}
1651	if ( ( pApicReg->pszGetInterruptR0
1652	\|\| pApicReg->pszHasPendingIrqR0
1653	\|\| pApicReg->pszSetBaseR0
1654	\|\| pApicReg->pszGetBaseR0
1655	\|\| pApicReg->pszSetTPRR0
1656	\|\| pApicReg->pszGetTPRR0
1657	\|\| pApicReg->pszWriteMSRR0
1658	\|\| pApicReg->pszReadMSRR0
1659	\|\| pApicReg->pszBusDeliverR0)
1660	&& ( !VALID_PTR(pApicReg->pszGetInterruptR0)
1661	\|\| !VALID_PTR(pApicReg->pszHasPendingIrqR0)
1662	\|\| !VALID_PTR(pApicReg->pszSetBaseR0)
1663	\|\| !VALID_PTR(pApicReg->pszGetBaseR0)
1664	\|\| !VALID_PTR(pApicReg->pszSetTPRR0)
1665	\|\| !VALID_PTR(pApicReg->pszGetTPRR0)
1666	\|\| !VALID_PTR(pApicReg->pszReadMSRR0)
1667	\|\| !VALID_PTR(pApicReg->pszWriteMSRR0)
1668	\|\| !VALID_PTR(pApicReg->pszBusDeliverR0))
1669	)
1670	{
1671	Assert(VALID_PTR(pApicReg->pszGetInterruptR0));
1672	Assert(VALID_PTR(pApicReg->pszHasPendingIrqR0));
1673	Assert(VALID_PTR(pApicReg->pszSetBaseR0));
1674	Assert(VALID_PTR(pApicReg->pszGetBaseR0));
1675	Assert(VALID_PTR(pApicReg->pszSetTPRR0));
1676	Assert(VALID_PTR(pApicReg->pszGetTPRR0));
1677	Assert(VALID_PTR(pApicReg->pszReadMSRR0));
1678	Assert(VALID_PTR(pApicReg->pszWriteMSRR0));
1679	Assert(VALID_PTR(pApicReg->pszBusDeliverR0));
1680	LogFlow(("pdmR3DevHlp_APICRegister: caller='%s'/%d: returns %Rrc (R0 callbacks)\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
1681	return VERR_INVALID_PARAMETER;
1682	}
1683	if (!ppApicHlpR3)
1684	{
1685	Assert(ppApicHlpR3);
1686	LogFlow(("pdmR3DevHlp_APICRegister: caller='%s'/%d: returns %Rrc (ppApicHlpR3)\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
1687	return VERR_INVALID_PARAMETER;
1688	}
1689
1690	/*
1691	* Only one APIC device. On SMP we have single logical device covering all LAPICs,
1692	* as they need to communicate and share state easily.
1693	*/
1694	PVM pVM = pDevIns->Internal.s.pVMR3;
1695	if (pVM->pdm.s.Apic.pDevInsR3)
1696	{
1697	AssertMsgFailed(("Only one apic device is supported!\n"));
1698	LogFlow(("pdmR3DevHlp_APICRegister: caller='%s'/%d: returns %Rrc\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
1699	return VERR_INVALID_PARAMETER;
1700	}
1701
1702	/*
1703	* Resolve & initialize the RC bits.
1704	*/
1705	if (pApicReg->pszGetInterruptRC)
1706	{
1707	int rc = PDMR3LdrGetSymbolRCLazy(pVM, pDevIns->pDevReg->szRCMod, pApicReg->pszGetInterruptRC, &pVM->pdm.s.Apic.pfnGetInterruptRC);
1708	AssertMsgRC(rc, ("%s::%s rc=%Rrc\n", pDevIns->pDevReg->szRCMod, pApicReg->pszGetInterruptRC, rc));
1709	if (RT_SUCCESS(rc))
1710	{
1711	rc = PDMR3LdrGetSymbolRCLazy(pVM, pDevIns->pDevReg->szRCMod, pApicReg->pszHasPendingIrqRC, &pVM->pdm.s.Apic.pfnHasPendingIrqRC);
1712	AssertMsgRC(rc, ("%s::%s rc=%Rrc\n", pDevIns->pDevReg->szRCMod, pApicReg->pszHasPendingIrqRC, rc));
1713	}
1714	if (RT_SUCCESS(rc))
1715	{
1716	rc = PDMR3LdrGetSymbolRCLazy(pVM, pDevIns->pDevReg->szRCMod, pApicReg->pszSetBaseRC, &pVM->pdm.s.Apic.pfnSetBaseRC);
1717	AssertMsgRC(rc, ("%s::%s rc=%Rrc\n", pDevIns->pDevReg->szRCMod, pApicReg->pszSetBaseRC, rc));
1718	}
1719	if (RT_SUCCESS(rc))
1720	{
1721	rc = PDMR3LdrGetSymbolRCLazy(pVM, pDevIns->pDevReg->szRCMod, pApicReg->pszGetBaseRC, &pVM->pdm.s.Apic.pfnGetBaseRC);
1722	AssertMsgRC(rc, ("%s::%s rc=%Rrc\n", pDevIns->pDevReg->szRCMod, pApicReg->pszGetBaseRC, rc));
1723	}
1724	if (RT_SUCCESS(rc))
1725	{
1726	rc = PDMR3LdrGetSymbolRCLazy(pVM, pDevIns->pDevReg->szRCMod, pApicReg->pszSetTPRRC, &pVM->pdm.s.Apic.pfnSetTPRRC);
1727	AssertMsgRC(rc, ("%s::%s rc=%Rrc\n", pDevIns->pDevReg->szRCMod, pApicReg->pszSetTPRRC, rc));
1728	}
1729	if (RT_SUCCESS(rc))
1730	{
1731	rc = PDMR3LdrGetSymbolRCLazy(pVM, pDevIns->pDevReg->szRCMod, pApicReg->pszGetTPRRC, &pVM->pdm.s.Apic.pfnGetTPRRC);
1732	AssertMsgRC(rc, ("%s::%s rc=%Rrc\n", pDevIns->pDevReg->szRCMod, pApicReg->pszGetTPRRC, rc));
1733	}
1734	if (RT_SUCCESS(rc))
1735	{
1736	rc = PDMR3LdrGetSymbolRCLazy(pVM, pDevIns->pDevReg->szRCMod, pApicReg->pszWriteMSRRC, &pVM->pdm.s.Apic.pfnWriteMSRRC);
1737	AssertMsgRC(rc, ("%s::%s rc=%Rrc\n", pDevIns->pDevReg->szRCMod, pApicReg->pszWriteMSRRC, rc));
1738	}
1739	if (RT_SUCCESS(rc))
1740	{
1741	rc = PDMR3LdrGetSymbolRCLazy(pVM, pDevIns->pDevReg->szRCMod, pApicReg->pszReadMSRRC, &pVM->pdm.s.Apic.pfnReadMSRRC);
1742	AssertMsgRC(rc, ("%s::%s rc=%Rrc\n", pDevIns->pDevReg->szRCMod, pApicReg->pszReadMSRRC, rc));
1743	}
1744	if (RT_SUCCESS(rc))
1745	{
1746	rc = PDMR3LdrGetSymbolRCLazy(pVM, pDevIns->pDevReg->szRCMod, pApicReg->pszBusDeliverRC, &pVM->pdm.s.Apic.pfnBusDeliverRC);
1747	AssertMsgRC(rc, ("%s::%s rc=%Rrc\n", pDevIns->pDevReg->szRCMod, pApicReg->pszBusDeliverRC, rc));
1748	}
1749	if (RT_FAILURE(rc))
1750	{
1751	LogFlow(("pdmR3DevHlp_IOAPICRegister: caller='%s'/%d: returns %Rrc\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, rc));
1752	return rc;
1753	}
1754	pVM->pdm.s.Apic.pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
1755	}
1756	else
1757	{
1758	pVM->pdm.s.Apic.pDevInsRC = 0;
1759	pVM->pdm.s.Apic.pfnGetInterruptRC = 0;
1760	pVM->pdm.s.Apic.pfnHasPendingIrqRC = 0;
1761	pVM->pdm.s.Apic.pfnSetBaseRC = 0;
1762	pVM->pdm.s.Apic.pfnGetBaseRC = 0;
1763	pVM->pdm.s.Apic.pfnSetTPRRC = 0;
1764	pVM->pdm.s.Apic.pfnGetTPRRC = 0;
1765	pVM->pdm.s.Apic.pfnWriteMSRRC = 0;
1766	pVM->pdm.s.Apic.pfnReadMSRRC = 0;
1767	pVM->pdm.s.Apic.pfnBusDeliverRC = 0;
1768	}
1769
1770	/*
1771	* Resolve & initialize the R0 bits.
1772	*/
1773	if (pApicReg->pszGetInterruptR0)
1774	{
1775	int rc = PDMR3LdrGetSymbolR0Lazy(pVM, pDevIns->pDevReg->szR0Mod, pApicReg->pszGetInterruptR0, &pVM->pdm.s.Apic.pfnGetInterruptR0);
1776	AssertMsgRC(rc, ("%s::%s rc=%Rrc\n", pDevIns->pDevReg->szR0Mod, pApicReg->pszGetInterruptR0, rc));
1777	if (RT_SUCCESS(rc))
1778	{
1779	rc = PDMR3LdrGetSymbolR0Lazy(pVM, pDevIns->pDevReg->szR0Mod, pApicReg->pszHasPendingIrqR0, &pVM->pdm.s.Apic.pfnHasPendingIrqR0);
1780	AssertMsgRC(rc, ("%s::%s rc=%Rrc\n", pDevIns->pDevReg->szR0Mod, pApicReg->pszHasPendingIrqR0, rc));
1781	}
1782	if (RT_SUCCESS(rc))
1783	{
1784	rc = PDMR3LdrGetSymbolR0Lazy(pVM, pDevIns->pDevReg->szR0Mod, pApicReg->pszSetBaseR0, &pVM->pdm.s.Apic.pfnSetBaseR0);
1785	AssertMsgRC(rc, ("%s::%s rc=%Rrc\n", pDevIns->pDevReg->szR0Mod, pApicReg->pszSetBaseR0, rc));
1786	}
1787	if (RT_SUCCESS(rc))
1788	{
1789	rc = PDMR3LdrGetSymbolR0Lazy(pVM, pDevIns->pDevReg->szR0Mod, pApicReg->pszGetBaseR0, &pVM->pdm.s.Apic.pfnGetBaseR0);
1790	AssertMsgRC(rc, ("%s::%s rc=%Rrc\n", pDevIns->pDevReg->szR0Mod, pApicReg->pszGetBaseR0, rc));
1791	}
1792	if (RT_SUCCESS(rc))
1793	{
1794	rc = PDMR3LdrGetSymbolR0Lazy(pVM, pDevIns->pDevReg->szR0Mod, pApicReg->pszSetTPRR0, &pVM->pdm.s.Apic.pfnSetTPRR0);
1795	AssertMsgRC(rc, ("%s::%s rc=%Rrc\n", pDevIns->pDevReg->szR0Mod, pApicReg->pszSetTPRR0, rc));
1796	}
1797	if (RT_SUCCESS(rc))
1798	{
1799	rc = PDMR3LdrGetSymbolR0Lazy(pVM, pDevIns->pDevReg->szR0Mod, pApicReg->pszGetTPRR0, &pVM->pdm.s.Apic.pfnGetTPRR0);
1800	AssertMsgRC(rc, ("%s::%s rc=%Rrc\n", pDevIns->pDevReg->szR0Mod, pApicReg->pszGetTPRR0, rc));
1801	}
1802	if (RT_SUCCESS(rc))
1803	{
1804	rc = PDMR3LdrGetSymbolR0Lazy(pVM, pDevIns->pDevReg->szR0Mod, pApicReg->pszWriteMSRR0, &pVM->pdm.s.Apic.pfnWriteMSRR0);
1805	AssertMsgRC(rc, ("%s::%s rc=%Rrc\n", pDevIns->pDevReg->szR0Mod, pApicReg->pszWriteMSRR0, rc));
1806	}
1807	if (RT_SUCCESS(rc))
1808	{
1809	rc = PDMR3LdrGetSymbolR0Lazy(pVM, pDevIns->pDevReg->szR0Mod, pApicReg->pszReadMSRR0, &pVM->pdm.s.Apic.pfnReadMSRR0);
1810	AssertMsgRC(rc, ("%s::%s rc=%Rrc\n", pDevIns->pDevReg->szR0Mod, pApicReg->pszReadMSRR0, rc));
1811	}
1812	if (RT_SUCCESS(rc))
1813	{
1814	rc = PDMR3LdrGetSymbolR0Lazy(pVM, pDevIns->pDevReg->szR0Mod, pApicReg->pszBusDeliverR0, &pVM->pdm.s.Apic.pfnBusDeliverR0);
1815	AssertMsgRC(rc, ("%s::%s rc=%Rrc\n", pDevIns->pDevReg->szR0Mod, pApicReg->pszBusDeliverR0, rc));
1816	}
1817	if (RT_FAILURE(rc))
1818	{
1819	LogFlow(("pdmR3DevHlp_IOAPICRegister: caller='%s'/%d: returns %Rrc\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, rc));
1820	return rc;
1821	}
1822	pVM->pdm.s.Apic.pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
1823	Assert(pVM->pdm.s.Apic.pDevInsR0);
1824	}
1825	else
1826	{
1827	pVM->pdm.s.Apic.pfnGetInterruptR0 = 0;
1828	pVM->pdm.s.Apic.pfnHasPendingIrqR0 = 0;
1829	pVM->pdm.s.Apic.pfnSetBaseR0 = 0;
1830	pVM->pdm.s.Apic.pfnGetBaseR0 = 0;
1831	pVM->pdm.s.Apic.pfnSetTPRR0 = 0;
1832	pVM->pdm.s.Apic.pfnGetTPRR0 = 0;
1833	pVM->pdm.s.Apic.pfnWriteMSRR0 = 0;
1834	pVM->pdm.s.Apic.pfnReadMSRR0 = 0;
1835	pVM->pdm.s.Apic.pfnBusDeliverR0 = 0;
1836	pVM->pdm.s.Apic.pDevInsR0 = 0;
1837	}
1838
1839	/*
1840	* Initialize the HC bits.
1841	*/
1842	pVM->pdm.s.Apic.pDevInsR3 = pDevIns;
1843	pVM->pdm.s.Apic.pfnGetInterruptR3 = pApicReg->pfnGetInterruptR3;
1844	pVM->pdm.s.Apic.pfnHasPendingIrqR3 = pApicReg->pfnHasPendingIrqR3;
1845	pVM->pdm.s.Apic.pfnSetBaseR3 = pApicReg->pfnSetBaseR3;
1846	pVM->pdm.s.Apic.pfnGetBaseR3 = pApicReg->pfnGetBaseR3;
1847	pVM->pdm.s.Apic.pfnSetTPRR3 = pApicReg->pfnSetTPRR3;
1848	pVM->pdm.s.Apic.pfnGetTPRR3 = pApicReg->pfnGetTPRR3;
1849	pVM->pdm.s.Apic.pfnWriteMSRR3 = pApicReg->pfnWriteMSRR3;
1850	pVM->pdm.s.Apic.pfnReadMSRR3 = pApicReg->pfnReadMSRR3;
1851	pVM->pdm.s.Apic.pfnBusDeliverR3 = pApicReg->pfnBusDeliverR3;
1852	Log(("PDM: Registered APIC device '%s'/%d pDevIns=%p\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, pDevIns));
1853
1854	/* set the helper pointer and return. */
1855	*ppApicHlpR3 = &g_pdmR3DevApicHlp;
1856	LogFlow(("pdmR3DevHlp_APICRegister: caller='%s'/%d: returns %Rrc\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, VINF_SUCCESS));
1857	return VINF_SUCCESS;
1858	}
1859
1860
1861	/** @copydoc PDMDEVHLPR3::pfnIOAPICRegister */
1862	static DECLCALLBACK(int) pdmR3DevHlp_IOAPICRegister(PPDMDEVINS pDevIns, PPDMIOAPICREG pIoApicReg, PCPDMIOAPICHLPR3 *ppIoApicHlpR3)
1863	{
1864	PDMDEV_ASSERT_DEVINS(pDevIns);
1865	VM_ASSERT_EMT(pDevIns->Internal.s.pVMR3);
1866	LogFlow(("pdmR3DevHlp_IOAPICRegister: caller='%s'/%d: pIoApicReg=%p:{.u32Version=%#x, .pfnSetIrqR3=%p, .pszSetIrqRC=%p:{%s}, .pszSetIrqR0=%p:{%s}} ppIoApicHlpR3=%p\n",
1867	pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, pIoApicReg, pIoApicReg->u32Version, pIoApicReg->pfnSetIrqR3,
1868	pIoApicReg->pszSetIrqRC, pIoApicReg->pszSetIrqRC, pIoApicReg->pszSetIrqR0, pIoApicReg->pszSetIrqR0, ppIoApicHlpR3));
1869
1870	/*
1871	* Validate input.
1872	*/
1873	if (pIoApicReg->u32Version != PDM_IOAPICREG_VERSION)
1874	{
1875	AssertMsgFailed(("u32Version=%#x expected %#x\n", pIoApicReg->u32Version, PDM_IOAPICREG_VERSION));
1876	LogFlow(("pdmR3DevHlp_IOAPICRegister: caller='%s'/%d: returns %Rrc (version)\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
1877	return VERR_INVALID_PARAMETER;
1878	}
1879	if (!pIoApicReg->pfnSetIrqR3)
1880	{
1881	Assert(pIoApicReg->pfnSetIrqR3);
1882	LogFlow(("pdmR3DevHlp_IOAPICRegister: caller='%s'/%d: returns %Rrc (R3 callbacks)\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
1883	return VERR_INVALID_PARAMETER;
1884	}
1885	if ( pIoApicReg->pszSetIrqRC
1886	&& !VALID_PTR(pIoApicReg->pszSetIrqRC))
1887	{
1888	Assert(VALID_PTR(pIoApicReg->pszSetIrqRC));
1889	LogFlow(("pdmR3DevHlp_IOAPICRegister: caller='%s'/%d: returns %Rrc (GC callbacks)\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
1890	return VERR_INVALID_PARAMETER;
1891	}
1892	if ( pIoApicReg->pszSetIrqR0
1893	&& !VALID_PTR(pIoApicReg->pszSetIrqR0))
1894	{
1895	Assert(VALID_PTR(pIoApicReg->pszSetIrqR0));
1896	LogFlow(("pdmR3DevHlp_IOAPICRegister: caller='%s'/%d: returns %Rrc (GC callbacks)\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
1897	return VERR_INVALID_PARAMETER;
1898	}
1899	if (!ppIoApicHlpR3)
1900	{
1901	Assert(ppIoApicHlpR3);
1902	LogFlow(("pdmR3DevHlp_IOAPICRegister: caller='%s'/%d: returns %Rrc (ppApicHlp)\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
1903	return VERR_INVALID_PARAMETER;
1904	}
1905
1906	/*
1907	* The I/O APIC requires the APIC to be present (hacks++).
1908	* If the I/O APIC does GC stuff so must the APIC.
1909	*/
1910	PVM pVM = pDevIns->Internal.s.pVMR3;
1911	if (!pVM->pdm.s.Apic.pDevInsR3)
1912	{
1913	AssertMsgFailed(("Configuration error / Init order error! No APIC!\n"));
1914	LogFlow(("pdmR3DevHlp_IOAPICRegister: caller='%s'/%d: returns %Rrc (no APIC)\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
1915	return VERR_INVALID_PARAMETER;
1916	}
1917	if ( pIoApicReg->pszSetIrqRC
1918	&& !pVM->pdm.s.Apic.pDevInsRC)
1919	{
1920	AssertMsgFailed(("Configuration error! APIC doesn't do GC, I/O APIC does!\n"));
1921	LogFlow(("pdmR3DevHlp_IOAPICRegister: caller='%s'/%d: returns %Rrc (no GC APIC)\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
1922	return VERR_INVALID_PARAMETER;
1923	}
1924
1925	/*
1926	* Only one I/O APIC device.
1927	*/
1928	if (pVM->pdm.s.IoApic.pDevInsR3)
1929	{
1930	AssertMsgFailed(("Only one ioapic device is supported!\n"));
1931	LogFlow(("pdmR3DevHlp_IOAPICRegister: caller='%s'/%d: returns %Rrc (only one)\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
1932	return VERR_INVALID_PARAMETER;
1933	}
1934
1935	/*
1936	* Resolve & initialize the GC bits.
1937	*/
1938	if (pIoApicReg->pszSetIrqRC)
1939	{
1940	int rc = PDMR3LdrGetSymbolRCLazy(pVM, pDevIns->pDevReg->szRCMod, pIoApicReg->pszSetIrqRC, &pVM->pdm.s.IoApic.pfnSetIrqRC);
1941	AssertMsgRC(rc, ("%s::%s rc=%Rrc\n", pDevIns->pDevReg->szRCMod, pIoApicReg->pszSetIrqRC, rc));
1942	if (RT_FAILURE(rc))
1943	{
1944	LogFlow(("pdmR3DevHlp_IOAPICRegister: caller='%s'/%d: returns %Rrc\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, rc));
1945	return rc;
1946	}
1947	pVM->pdm.s.IoApic.pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
1948	}
1949	else
1950	{
1951	pVM->pdm.s.IoApic.pDevInsRC = 0;
1952	pVM->pdm.s.IoApic.pfnSetIrqRC = 0;
1953	}
1954
1955	/*
1956	* Resolve & initialize the R0 bits.
1957	*/
1958	if (pIoApicReg->pszSetIrqR0)
1959	{
1960	int rc = PDMR3LdrGetSymbolR0Lazy(pVM, pDevIns->pDevReg->szR0Mod, pIoApicReg->pszSetIrqR0, &pVM->pdm.s.IoApic.pfnSetIrqR0);
1961	AssertMsgRC(rc, ("%s::%s rc=%Rrc\n", pDevIns->pDevReg->szR0Mod, pIoApicReg->pszSetIrqR0, rc));
1962	if (RT_FAILURE(rc))
1963	{
1964	LogFlow(("pdmR3DevHlp_IOAPICRegister: caller='%s'/%d: returns %Rrc\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, rc));
1965	return rc;
1966	}
1967	pVM->pdm.s.IoApic.pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
1968	Assert(pVM->pdm.s.IoApic.pDevInsR0);
1969	}
1970	else
1971	{
1972	pVM->pdm.s.IoApic.pfnSetIrqR0 = 0;
1973	pVM->pdm.s.IoApic.pDevInsR0 = 0;
1974	}
1975
1976	/*
1977	* Initialize the R3 bits.
1978	*/
1979	pVM->pdm.s.IoApic.pDevInsR3 = pDevIns;
1980	pVM->pdm.s.IoApic.pfnSetIrqR3 = pIoApicReg->pfnSetIrqR3;
1981	Log(("PDM: Registered I/O APIC device '%s'/%d pDevIns=%p\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, pDevIns));
1982
1983	/* set the helper pointer and return. */
1984	*ppIoApicHlpR3 = &g_pdmR3DevIoApicHlp;
1985	LogFlow(("pdmR3DevHlp_IOAPICRegister: caller='%s'/%d: returns %Rrc\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, VINF_SUCCESS));
1986	return VINF_SUCCESS;
1987	}
1988
1989
1990	/** @copydoc PDMDEVHLPR3::pfnDMACRegister */
1991	static DECLCALLBACK(int) pdmR3DevHlp_DMACRegister(PPDMDEVINS pDevIns, PPDMDMACREG pDmacReg, PCPDMDMACHLP *ppDmacHlp)
1992	{
1993	PDMDEV_ASSERT_DEVINS(pDevIns);
1994	VM_ASSERT_EMT(pDevIns->Internal.s.pVMR3);
1995	LogFlow(("pdmR3DevHlp_DMACRegister: caller='%s'/%d: pDmacReg=%p:{.u32Version=%#x, .pfnRun=%p, .pfnRegister=%p, .pfnReadMemory=%p, .pfnWriteMemory=%p, .pfnSetDREQ=%p, .pfnGetChannelMode=%p} ppDmacHlp=%p\n",
1996	pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, pDmacReg, pDmacReg->u32Version, pDmacReg->pfnRun, pDmacReg->pfnRegister,
1997	pDmacReg->pfnReadMemory, pDmacReg->pfnWriteMemory, pDmacReg->pfnSetDREQ, pDmacReg->pfnGetChannelMode, ppDmacHlp));
1998
1999	/*
2000	* Validate input.
2001	*/
2002	if (pDmacReg->u32Version != PDM_DMACREG_VERSION)
2003	{
2004	AssertMsgFailed(("u32Version=%#x expected %#x\n", pDmacReg->u32Version,
2005	PDM_DMACREG_VERSION));
2006	LogFlow(("pdmR3DevHlp_DMACRegister: caller='%s'/%d: returns %Rrc (version)\n",
2007	pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
2008	return VERR_INVALID_PARAMETER;
2009	}
2010	if ( !pDmacReg->pfnRun
2011	\|\| !pDmacReg->pfnRegister
2012	\|\| !pDmacReg->pfnReadMemory
2013	\|\| !pDmacReg->pfnWriteMemory
2014	\|\| !pDmacReg->pfnSetDREQ
2015	\|\| !pDmacReg->pfnGetChannelMode)
2016	{
2017	Assert(pDmacReg->pfnRun);
2018	Assert(pDmacReg->pfnRegister);
2019	Assert(pDmacReg->pfnReadMemory);
2020	Assert(pDmacReg->pfnWriteMemory);
2021	Assert(pDmacReg->pfnSetDREQ);
2022	Assert(pDmacReg->pfnGetChannelMode);
2023	LogFlow(("pdmR3DevHlp_DMACRegister: caller='%s'/%d: returns %Rrc (callbacks)\n",
2024	pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
2025	return VERR_INVALID_PARAMETER;
2026	}
2027
2028	if (!ppDmacHlp)
2029	{
2030	Assert(ppDmacHlp);
2031	LogFlow(("pdmR3DevHlp_DMACRegister: caller='%s'/%d: returns %Rrc (ppDmacHlp)\n",
2032	pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
2033	return VERR_INVALID_PARAMETER;
2034	}
2035
2036	/*
2037	* Only one DMA device.
2038	*/
2039	PVM pVM = pDevIns->Internal.s.pVMR3;
2040	if (pVM->pdm.s.pDmac)
2041	{
2042	AssertMsgFailed(("Only one DMA device is supported!\n"));
2043	LogFlow(("pdmR3DevHlp_DMACRegister: caller='%s'/%d: returns %Rrc\n",
2044	pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
2045	return VERR_INVALID_PARAMETER;
2046	}
2047
2048	/*
2049	* Allocate and initialize pci bus structure.
2050	*/
2051	int rc = VINF_SUCCESS;
2052	PPDMDMAC pDmac = (PPDMDMAC)MMR3HeapAlloc(pDevIns->Internal.s.pVMR3, MM_TAG_PDM_DEVICE, sizeof(*pDmac));
2053	if (pDmac)
2054	{
2055	pDmac->pDevIns = pDevIns;
2056	pDmac->Reg = *pDmacReg;
2057	pVM->pdm.s.pDmac = pDmac;
2058
2059	/* set the helper pointer. */
2060	*ppDmacHlp = &g_pdmR3DevDmacHlp;
2061	Log(("PDM: Registered DMAC device '%s'/%d pDevIns=%p\n",
2062	pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, pDevIns));
2063	}
2064	else
2065	rc = VERR_NO_MEMORY;
2066
2067	LogFlow(("pdmR3DevHlp_DMACRegister: caller='%s'/%d: returns %Rrc\n",
2068	pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, rc));
2069	return rc;
2070	}
2071
2072
2073	/** @copydoc PDMDEVHLPR3::pfnPhysRead */
2074	static DECLCALLBACK(int) pdmR3DevHlp_PhysRead(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead)
2075	{
2076	PDMDEV_ASSERT_DEVINS(pDevIns);
2077	PVM pVM = pDevIns->Internal.s.pVMR3;
2078	LogFlow(("pdmR3DevHlp_PhysRead: caller='%s'/%d: GCPhys=%RGp pvBuf=%p cbRead=%#x\n",
2079	pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, GCPhys, pvBuf, cbRead));
2080
2081	#if defined(VBOX_STRICT) && defined(PDM_DEVHLP_DEADLOCK_DETECTION)
2082	if (!VM_IS_EMT(pVM)) /** @todo not true for SMP. oh joy! */
2083	{
2084	char szNames[128];
2085	uint32_t cLocks = PDMR3CritSectCountOwned(pVM, szNames, sizeof(szNames));
2086	AssertMsg(cLocks == 0, ("cLocks=%u %s\n", cLocks, szNames));
2087	}
2088	#endif
2089
2090	int rc;
2091	if (VM_IS_EMT(pVM))
2092	rc = PGMPhysRead(pVM, GCPhys, pvBuf, cbRead);
2093	else
2094	rc = PGMR3PhysReadExternal(pVM, GCPhys, pvBuf, cbRead);
2095
2096	Log(("pdmR3DevHlp_PhysRead: caller='%s'/%d: returns %Rrc\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, rc));
2097	return rc;
2098	}
2099
2100
2101	/** @copydoc PDMDEVHLPR3::pfnPhysWrite */
2102	static DECLCALLBACK(int) pdmR3DevHlp_PhysWrite(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite)
2103	{
2104	PDMDEV_ASSERT_DEVINS(pDevIns);
2105	PVM pVM = pDevIns->Internal.s.pVMR3;
2106	LogFlow(("pdmR3DevHlp_PhysWrite: caller='%s'/%d: GCPhys=%RGp pvBuf=%p cbWrite=%#x\n",
2107	pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, GCPhys, pvBuf, cbWrite));
2108
2109	#if defined(VBOX_STRICT) && defined(PDM_DEVHLP_DEADLOCK_DETECTION)
2110	if (!VM_IS_EMT(pVM)) /** @todo not true for SMP. oh joy! */
2111	{
2112	char szNames[128];
2113	uint32_t cLocks = PDMR3CritSectCountOwned(pVM, szNames, sizeof(szNames));
2114	AssertMsg(cLocks == 0, ("cLocks=%u %s\n", cLocks, szNames));
2115	}
2116	#endif
2117
2118	int rc;
2119	if (VM_IS_EMT(pVM))
2120	rc = PGMPhysWrite(pVM, GCPhys, pvBuf, cbWrite);
2121	else
2122	rc = PGMR3PhysWriteExternal(pVM, GCPhys, pvBuf, cbWrite);
2123
2124	Log(("pdmR3DevHlp_PhysWrite: caller='%s'/%d: returns %Rrc\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, rc));
2125	return rc;
2126	}
2127
2128
2129	/** @copydoc PDMDEVHLPR3::pfnPhysGCPhys2CCPtr */
2130	static DECLCALLBACK(int) pdmR3DevHlp_PhysGCPhys2CCPtr(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, uint32_t fFlags, void **ppv, PPGMPAGEMAPLOCK pLock)
2131	{
2132	PDMDEV_ASSERT_DEVINS(pDevIns);
2133	PVM pVM = pDevIns->Internal.s.pVMR3;
2134	LogFlow(("pdmR3DevHlp_PhysGCPhys2CCPtr: caller='%s'/%d: GCPhys=%RGp fFlags=%#x ppv=%p pLock=%p\n",
2135	pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, GCPhys, fFlags, ppv, pLock));
2136	AssertReturn(!fFlags, VERR_INVALID_PARAMETER);
2137
2138	#if defined(VBOX_STRICT) && defined(PDM_DEVHLP_DEADLOCK_DETECTION)
2139	if (!VM_IS_EMT(pVM)) /** @todo not true for SMP. oh joy! */
2140	{
2141	char szNames[128];
2142	uint32_t cLocks = PDMR3CritSectCountOwned(pVM, szNames, sizeof(szNames));
2143	AssertMsg(cLocks == 0, ("cLocks=%u %s\n", cLocks, szNames));
2144	}
2145	#endif
2146
2147	int rc = PGMR3PhysGCPhys2CCPtrExternal(pVM, GCPhys, ppv, pLock);
2148
2149	Log(("pdmR3DevHlp_PhysGCPhys2CCPtr: caller='%s'/%d: returns %Rrc\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, rc));
2150	return rc;
2151	}
2152
2153
2154	/** @copydoc PDMDEVHLPR3::pfnPhysGCPhys2CCPtrReadOnly */
2155	static DECLCALLBACK(int) pdmR3DevHlp_PhysGCPhys2CCPtrReadOnly(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, uint32_t fFlags, const void **ppv, PPGMPAGEMAPLOCK pLock)
2156	{
2157	PDMDEV_ASSERT_DEVINS(pDevIns);
2158	PVM pVM = pDevIns->Internal.s.pVMR3;
2159	LogFlow(("pdmR3DevHlp_PhysGCPhys2CCPtrReadOnly: caller='%s'/%d: GCPhys=%RGp fFlags=%#x ppv=%p pLock=%p\n",
2160	pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, GCPhys, fFlags, ppv, pLock));
2161	AssertReturn(!fFlags, VERR_INVALID_PARAMETER);
2162
2163	#if defined(VBOX_STRICT) && defined(PDM_DEVHLP_DEADLOCK_DETECTION)
2164	if (!VM_IS_EMT(pVM)) /** @todo not true for SMP. oh joy! */
2165	{
2166	char szNames[128];
2167	uint32_t cLocks = PDMR3CritSectCountOwned(pVM, szNames, sizeof(szNames));
2168	AssertMsg(cLocks == 0, ("cLocks=%u %s\n", cLocks, szNames));
2169	}
2170	#endif
2171
2172	int rc = PGMR3PhysGCPhys2CCPtrReadOnlyExternal(pVM, GCPhys, ppv, pLock);
2173
2174	Log(("pdmR3DevHlp_PhysGCPhys2CCPtrReadOnly: caller='%s'/%d: returns %Rrc\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, rc));
2175	return rc;
2176	}
2177
2178
2179	/** @copydoc PDMDEVHLPR3::pfnPhysReleasePageMappingLock */
2180	static DECLCALLBACK(void) pdmR3DevHlp_PhysReleasePageMappingLock(PPDMDEVINS pDevIns, PPGMPAGEMAPLOCK pLock)
2181	{
2182	PDMDEV_ASSERT_DEVINS(pDevIns);
2183	PVM pVM = pDevIns->Internal.s.pVMR3;
2184	LogFlow(("pdmR3DevHlp_PhysReleasePageMappingLock: caller='%s'/%d: pLock=%p\n",
2185	pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, pLock));
2186
2187	PGMPhysReleasePageMappingLock(pVM, pLock);
2188
2189	Log(("pdmR3DevHlp_PhysReleasePageMappingLock: caller='%s'/%d: returns void\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance));
2190	}
2191
2192
2193	/** @copydoc PDMDEVHLPR3::pfnPhysReadGCVirt */
2194	static DECLCALLBACK(int) pdmR3DevHlp_PhysReadGCVirt(PPDMDEVINS pDevIns, void *pvDst, RTGCPTR GCVirtSrc, size_t cb)
2195	{
2196	PDMDEV_ASSERT_DEVINS(pDevIns);
2197	PVM pVM = pDevIns->Internal.s.pVMR3;
2198	VM_ASSERT_EMT(pVM);
2199	LogFlow(("pdmR3DevHlp_PhysReadGCVirt: caller='%s'/%d: pvDst=%p GCVirt=%RGv cb=%#x\n",
2200	pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, pvDst, GCVirtSrc, cb));
2201
2202	PVMCPU pVCpu = VMMGetCpu(pVM);
2203	if (!pVCpu)
2204	return VERR_ACCESS_DENIED;
2205	#if defined(VBOX_STRICT) && defined(PDM_DEVHLP_DEADLOCK_DETECTION)
2206	/** @todo SMP. */
2207	#endif
2208
2209	int rc = PGMPhysSimpleReadGCPtr(pVCpu, pvDst, GCVirtSrc, cb);
2210
2211	LogFlow(("pdmR3DevHlp_PhysReadGCVirt: caller='%s'/%d: returns %Rrc\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, rc));
2212
2213	return rc;
2214	}
2215
2216
2217	/** @copydoc PDMDEVHLPR3::pfnPhysWriteGCVirt */
2218	static DECLCALLBACK(int) pdmR3DevHlp_PhysWriteGCVirt(PPDMDEVINS pDevIns, RTGCPTR GCVirtDst, const void *pvSrc, size_t cb)
2219	{
2220	PDMDEV_ASSERT_DEVINS(pDevIns);
2221	PVM pVM = pDevIns->Internal.s.pVMR3;
2222	VM_ASSERT_EMT(pVM);
2223	LogFlow(("pdmR3DevHlp_PhysWriteGCVirt: caller='%s'/%d: GCVirtDst=%RGv pvSrc=%p cb=%#x\n",
2224	pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, GCVirtDst, pvSrc, cb));
2225
2226	PVMCPU pVCpu = VMMGetCpu(pVM);
2227	if (!pVCpu)
2228	return VERR_ACCESS_DENIED;
2229	#if defined(VBOX_STRICT) && defined(PDM_DEVHLP_DEADLOCK_DETECTION)
2230	/** @todo SMP. */
2231	#endif
2232
2233	int rc = PGMPhysSimpleWriteGCPtr(pVCpu, GCVirtDst, pvSrc, cb);
2234
2235	LogFlow(("pdmR3DevHlp_PhysWriteGCVirt: caller='%s'/%d: returns %Rrc\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, rc));
2236
2237	return rc;
2238	}
2239
2240
2241	/** @copydoc PDMDEVHLPR3::pfnPhysGCPtr2GCPhys */
2242	static DECLCALLBACK(int) pdmR3DevHlp_PhysGCPtr2GCPhys(PPDMDEVINS pDevIns, RTGCPTR GCPtr, PRTGCPHYS pGCPhys)
2243	{
2244	PDMDEV_ASSERT_DEVINS(pDevIns);
2245	PVM pVM = pDevIns->Internal.s.pVMR3;
2246	VM_ASSERT_EMT(pVM);
2247	LogFlow(("pdmR3DevHlp_PhysGCPtr2GCPhys: caller='%s'/%d: GCPtr=%RGv pGCPhys=%p\n",
2248	pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, GCPtr, pGCPhys));
2249
2250	PVMCPU pVCpu = VMMGetCpu(pVM);
2251	if (!pVCpu)
2252	return VERR_ACCESS_DENIED;
2253	#if defined(VBOX_STRICT) && defined(PDM_DEVHLP_DEADLOCK_DETECTION)
2254	/** @todo SMP. */
2255	#endif
2256
2257	int rc = PGMPhysGCPtr2GCPhys(pVCpu, GCPtr, pGCPhys);
2258
2259	LogFlow(("pdmR3DevHlp_PhysGCPtr2GCPhys: caller='%s'/%d: returns %Rrc pGCPhys=%RGp\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, rc, pGCPhys));
2260
2261	return rc;
2262	}
2263
2264
2265	/** @copydoc PDMDEVHLPR3::pfnVMState */
2266	static DECLCALLBACK(VMSTATE) pdmR3DevHlp_VMState(PPDMDEVINS pDevIns)
2267	{
2268	PDMDEV_ASSERT_DEVINS(pDevIns);
2269
2270	VMSTATE enmVMState = VMR3GetState(pDevIns->Internal.s.pVMR3);
2271
2272	LogFlow(("pdmR3DevHlp_VMState: caller='%s'/%d: returns %d (%s)\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance,
2273	enmVMState, VMR3GetStateName(enmVMState)));
2274	return enmVMState;
2275	}
2276
2277
2278	/** @copydoc PDMDEVHLPR3::pfnA20IsEnabled */
2279	static DECLCALLBACK(bool) pdmR3DevHlp_A20IsEnabled(PPDMDEVINS pDevIns)
2280	{
2281	PDMDEV_ASSERT_DEVINS(pDevIns);
2282	VM_ASSERT_EMT(pDevIns->Internal.s.pVMR3);
2283
2284	bool fRc = PGMPhysIsA20Enabled(VMMGetCpu(pDevIns->Internal.s.pVMR3));
2285
2286	LogFlow(("pdmR3DevHlp_A20IsEnabled: caller='%s'/%d: returns %d\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, fRc));
2287	return fRc;
2288	}
2289
2290
2291	/** @copydoc PDMDEVHLPR3::pfnA20Set */
2292	static DECLCALLBACK(void) pdmR3DevHlp_A20Set(PPDMDEVINS pDevIns, bool fEnable)
2293	{
2294	PDMDEV_ASSERT_DEVINS(pDevIns);
2295	VM_ASSERT_EMT(pDevIns->Internal.s.pVMR3);
2296	LogFlow(("pdmR3DevHlp_A20Set: caller='%s'/%d: fEnable=%d\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, fEnable));
2297	PGMR3PhysSetA20(VMMGetCpu(pDevIns->Internal.s.pVMR3), fEnable);
2298	}
2299
2300
2301	/** @copydoc PDMDEVHLPR3::pfnVMReset */
2302	static DECLCALLBACK(int) pdmR3DevHlp_VMReset(PPDMDEVINS pDevIns)
2303	{
2304	PDMDEV_ASSERT_DEVINS(pDevIns);
2305	PVM pVM = pDevIns->Internal.s.pVMR3;
2306	VM_ASSERT_EMT(pVM);
2307	LogFlow(("pdmR3DevHlp_VMReset: caller='%s'/%d: VM_FF_RESET %d -> 1\n",
2308	pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, VM_FF_ISSET(pVM, VM_FF_RESET)));
2309
2310	/*
2311	* We postpone this operation because we're likely to be inside a I/O instruction
2312	* and the EIP will be updated when we return.
2313	* We still return VINF_EM_RESET to break out of any execution loops and force FF evaluation.
2314	*/
2315	bool fHaltOnReset;
2316	int rc = CFGMR3QueryBool(CFGMR3GetChild(CFGMR3GetRoot(pVM), "PDM"), "HaltOnReset", &fHaltOnReset);
2317	if (RT_SUCCESS(rc) && fHaltOnReset)
2318	{
2319	Log(("pdmR3DevHlp_VMReset: Halt On Reset!\n"));
2320	rc = VINF_EM_HALT;
2321	}
2322	else
2323	{
2324	VM_FF_SET(pVM, VM_FF_RESET);
2325	rc = VINF_EM_RESET;
2326	}
2327
2328	LogFlow(("pdmR3DevHlp_VMReset: caller='%s'/%d: returns %Rrc\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, rc));
2329	return rc;
2330	}
2331
2332
2333	/** @copydoc PDMDEVHLPR3::pfnVMSuspend */
2334	static DECLCALLBACK(int) pdmR3DevHlp_VMSuspend(PPDMDEVINS pDevIns)
2335	{
2336	int rc;
2337	PDMDEV_ASSERT_DEVINS(pDevIns);
2338	PVM pVM = pDevIns->Internal.s.pVMR3;
2339	VM_ASSERT_EMT(pVM);
2340	LogFlow(("pdmR3DevHlp_VMSuspend: caller='%s'/%d:\n",
2341	pDevIns->pDevReg->szDeviceName, pDevIns->iInstance));
2342
2343	if (pVM->cCPUs > 1)
2344	{
2345	/* We own the IOM lock here and could cause a deadlock by waiting for a VCPU that is blocking on the IOM lock. */
2346	PVMREQ pReq;
2347	rc = VMR3ReqCallU(pVM->pUVM, VMCPUID_ANY_QUEUE, &pReq, 0, VMREQFLAGS_NO_WAIT,
2348	(PFNRT)VMR3Suspend, 1, pVM);
2349	AssertRC(rc);
2350	rc = VINF_EM_SUSPEND;
2351	}
2352	else
2353	rc = VMR3Suspend(pVM);
2354
2355	LogFlow(("pdmR3DevHlp_VMSuspend: caller='%s'/%d: returns %Rrc\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, rc));
2356	return rc;
2357	}
2358
2359
2360	/** @copydoc PDMDEVHLPR3::pfnVMPowerOff */
2361	static DECLCALLBACK(int) pdmR3DevHlp_VMPowerOff(PPDMDEVINS pDevIns)
2362	{
2363	int rc;
2364	PDMDEV_ASSERT_DEVINS(pDevIns);
2365	PVM pVM = pDevIns->Internal.s.pVMR3;
2366	VM_ASSERT_EMT(pVM);
2367	LogFlow(("pdmR3DevHlp_VMPowerOff: caller='%s'/%d:\n",
2368	pDevIns->pDevReg->szDeviceName, pDevIns->iInstance));
2369
2370	if (pVM->cCPUs > 1)
2371	{
2372	/* We own the IOM lock here and could cause a deadlock by waiting for a VCPU that is blocking on the IOM lock. */
2373	PVMREQ pReq;
2374	rc = VMR3ReqCallU(pVM->pUVM, VMCPUID_ANY_QUEUE, &pReq, 0, VMREQFLAGS_NO_WAIT,
2375	(PFNRT)VMR3PowerOff, 1, pVM);
2376	AssertRC(rc);
2377	/* Set the VCPU state to stopped here as well to make sure no
2378	* inconsistency with the EM state occurs.
2379	*/
2380	VMCPU_SET_STATE(VMMGetCpu(pVM), VMCPUSTATE_STOPPED);
2381	rc = VINF_EM_OFF;
2382	}
2383	else
2384	rc = VMR3PowerOff(pVM);
2385
2386	LogFlow(("pdmR3DevHlp_VMPowerOff: caller='%s'/%d: returns %Rrc\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, rc));
2387	return rc;
2388	}
2389
2390	/** @copydoc PDMDEVHLPR3::pfnDMARegister */
2391	static DECLCALLBACK(int) pdmR3DevHlp_DMARegister(PPDMDEVINS pDevIns, unsigned uChannel, PFNDMATRANSFERHANDLER pfnTransferHandler, void *pvUser)
2392	{
2393	PDMDEV_ASSERT_DEVINS(pDevIns);
2394	PVM pVM = pDevIns->Internal.s.pVMR3;
2395	VM_ASSERT_EMT(pVM);
2396	LogFlow(("pdmR3DevHlp_DMARegister: caller='%s'/%d: uChannel=%d pfnTransferHandler=%p pvUser=%p\n",
2397	pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, uChannel, pfnTransferHandler, pvUser));
2398	int rc = VINF_SUCCESS;
2399	if (pVM->pdm.s.pDmac)
2400	pVM->pdm.s.pDmac->Reg.pfnRegister(pVM->pdm.s.pDmac->pDevIns, uChannel, pfnTransferHandler, pvUser);
2401	else
2402	{
2403	AssertMsgFailed(("Configuration error: No DMAC controller available. This could be related to init order too!\n"));
2404	rc = VERR_PDM_NO_DMAC_INSTANCE;
2405	}
2406	LogFlow(("pdmR3DevHlp_DMARegister: caller='%s'/%d: returns %Rrc\n",
2407	pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, rc));
2408	return rc;
2409	}
2410
2411	/** @copydoc PDMDEVHLPR3::pfnDMAReadMemory */
2412	static DECLCALLBACK(int) pdmR3DevHlp_DMAReadMemory(PPDMDEVINS pDevIns, unsigned uChannel, void pvBuffer, uint32_t off, uint32_t cbBlock, uint32_t pcbRead)
2413	{
2414	PDMDEV_ASSERT_DEVINS(pDevIns);
2415	PVM pVM = pDevIns->Internal.s.pVMR3;
2416	VM_ASSERT_EMT(pVM);
2417	LogFlow(("pdmR3DevHlp_DMAReadMemory: caller='%s'/%d: uChannel=%d pvBuffer=%p off=%#x cbBlock=%#x pcbRead=%p\n",
2418	pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, uChannel, pvBuffer, off, cbBlock, pcbRead));
2419	int rc = VINF_SUCCESS;
2420	if (pVM->pdm.s.pDmac)
2421	{
2422	uint32_t cb = pVM->pdm.s.pDmac->Reg.pfnReadMemory(pVM->pdm.s.pDmac->pDevIns, uChannel, pvBuffer, off, cbBlock);
2423	if (pcbRead)
2424	*pcbRead = cb;
2425	}
2426	else
2427	{
2428	AssertMsgFailed(("Configuration error: No DMAC controller available. This could be related to init order too!\n"));
2429	rc = VERR_PDM_NO_DMAC_INSTANCE;
2430	}
2431	LogFlow(("pdmR3DevHlp_DMAReadMemory: caller='%s'/%d: returns %Rrc\n",
2432	pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, rc));
2433	return rc;
2434	}
2435
2436	/** @copydoc PDMDEVHLPR3::pfnDMAWriteMemory */
2437	static DECLCALLBACK(int) pdmR3DevHlp_DMAWriteMemory(PPDMDEVINS pDevIns, unsigned uChannel, const void pvBuffer, uint32_t off, uint32_t cbBlock, uint32_t pcbWritten)
2438	{
2439	PDMDEV_ASSERT_DEVINS(pDevIns);
2440	PVM pVM = pDevIns->Internal.s.pVMR3;
2441	VM_ASSERT_EMT(pVM);
2442	LogFlow(("pdmR3DevHlp_DMAWriteMemory: caller='%s'/%d: uChannel=%d pvBuffer=%p off=%#x cbBlock=%#x pcbWritten=%p\n",
2443	pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, uChannel, pvBuffer, off, cbBlock, pcbWritten));
2444	int rc = VINF_SUCCESS;
2445	if (pVM->pdm.s.pDmac)
2446	{
2447	uint32_t cb = pVM->pdm.s.pDmac->Reg.pfnWriteMemory(pVM->pdm.s.pDmac->pDevIns, uChannel, pvBuffer, off, cbBlock);
2448	if (pcbWritten)
2449	*pcbWritten = cb;
2450	}
2451	else
2452	{
2453	AssertMsgFailed(("Configuration error: No DMAC controller available. This could be related to init order too!\n"));
2454	rc = VERR_PDM_NO_DMAC_INSTANCE;
2455	}
2456	LogFlow(("pdmR3DevHlp_DMAWriteMemory: caller='%s'/%d: returns %Rrc\n",
2457	pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, rc));
2458	return rc;
2459	}
2460
2461	/** @copydoc PDMDEVHLPR3::pfnDMASetDREQ */
2462	static DECLCALLBACK(int) pdmR3DevHlp_DMASetDREQ(PPDMDEVINS pDevIns, unsigned uChannel, unsigned uLevel)
2463	{
2464	PDMDEV_ASSERT_DEVINS(pDevIns);
2465	PVM pVM = pDevIns->Internal.s.pVMR3;
2466	VM_ASSERT_EMT(pVM);
2467	LogFlow(("pdmR3DevHlp_DMASetDREQ: caller='%s'/%d: uChannel=%d uLevel=%d\n",
2468	pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, uChannel, uLevel));
2469	int rc = VINF_SUCCESS;
2470	if (pVM->pdm.s.pDmac)
2471	pVM->pdm.s.pDmac->Reg.pfnSetDREQ(pVM->pdm.s.pDmac->pDevIns, uChannel, uLevel);
2472	else
2473	{
2474	AssertMsgFailed(("Configuration error: No DMAC controller available. This could be related to init order too!\n"));
2475	rc = VERR_PDM_NO_DMAC_INSTANCE;
2476	}
2477	LogFlow(("pdmR3DevHlp_DMASetDREQ: caller='%s'/%d: returns %Rrc\n",
2478	pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, rc));
2479	return rc;
2480	}
2481
2482	/** @copydoc PDMDEVHLPR3::pfnDMAGetChannelMode */
2483	static DECLCALLBACK(uint8_t) pdmR3DevHlp_DMAGetChannelMode(PPDMDEVINS pDevIns, unsigned uChannel)
2484	{
2485	PDMDEV_ASSERT_DEVINS(pDevIns);
2486	PVM pVM = pDevIns->Internal.s.pVMR3;
2487	VM_ASSERT_EMT(pVM);
2488	LogFlow(("pdmR3DevHlp_DMAGetChannelMode: caller='%s'/%d: uChannel=%d\n",
2489	pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, uChannel));
2490	uint8_t u8Mode;
2491	if (pVM->pdm.s.pDmac)
2492	u8Mode = pVM->pdm.s.pDmac->Reg.pfnGetChannelMode(pVM->pdm.s.pDmac->pDevIns, uChannel);
2493	else
2494	{
2495	AssertMsgFailed(("Configuration error: No DMAC controller available. This could be related to init order too!\n"));
2496	u8Mode = 3 << 2 /* illegal mode type */;
2497	}
2498	LogFlow(("pdmR3DevHlp_DMAGetChannelMode: caller='%s'/%d: returns %#04x\n",
2499	pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, u8Mode));
2500	return u8Mode;
2501	}
2502
2503	/** @copydoc PDMDEVHLPR3::pfnDMASchedule */
2504	static DECLCALLBACK(void) pdmR3DevHlp_DMASchedule(PPDMDEVINS pDevIns)
2505	{
2506	PDMDEV_ASSERT_DEVINS(pDevIns);
2507	PVM pVM = pDevIns->Internal.s.pVMR3;
2508	VM_ASSERT_EMT(pVM);
2509	LogFlow(("pdmR3DevHlp_DMASchedule: caller='%s'/%d: VM_FF_PDM_DMA %d -> 1\n",
2510	pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, VM_FF_ISSET(pVM, VM_FF_PDM_DMA)));
2511
2512	AssertMsg(pVM->pdm.s.pDmac, ("Configuration error: No DMAC controller available. This could be related to init order too!\n"));
2513	VM_FF_SET(pVM, VM_FF_PDM_DMA);
2514	REMR3NotifyDmaPending(pVM);
2515	VMR3NotifyGlobalFFU(pVM->pUVM, VMNOTIFYFF_FLAGS_DONE_REM);
2516	}
2517
2518
2519	/** @copydoc PDMDEVHLPR3::pfnCMOSWrite */
2520	static DECLCALLBACK(int) pdmR3DevHlp_CMOSWrite(PPDMDEVINS pDevIns, unsigned iReg, uint8_t u8Value)
2521	{
2522	PDMDEV_ASSERT_DEVINS(pDevIns);
2523	PVM pVM = pDevIns->Internal.s.pVMR3;
2524	VM_ASSERT_EMT(pVM);
2525
2526	LogFlow(("pdmR3DevHlp_CMOSWrite: caller='%s'/%d: iReg=%#04x u8Value=%#04x\n",
2527	pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, iReg, u8Value));
2528	int rc;
2529	if (pVM->pdm.s.pRtc)
2530	rc = pVM->pdm.s.pRtc->Reg.pfnWrite(pVM->pdm.s.pRtc->pDevIns, iReg, u8Value);
2531	else
2532	rc = VERR_PDM_NO_RTC_INSTANCE;
2533
2534	LogFlow(("pdmR3DevHlp_CMOSWrite: caller='%s'/%d: return %Rrc\n",
2535	pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, rc));
2536	return rc;
2537	}
2538
2539
2540	/** @copydoc PDMDEVHLPR3::pfnCMOSRead */
2541	static DECLCALLBACK(int) pdmR3DevHlp_CMOSRead(PPDMDEVINS pDevIns, unsigned iReg, uint8_t *pu8Value)
2542	{
2543	PDMDEV_ASSERT_DEVINS(pDevIns);
2544	PVM pVM = pDevIns->Internal.s.pVMR3;
2545	VM_ASSERT_EMT(pVM);
2546
2547	LogFlow(("pdmR3DevHlp_CMOSWrite: caller='%s'/%d: iReg=%#04x pu8Value=%p\n",
2548	pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, iReg, pu8Value));
2549	int rc;
2550	if (pVM->pdm.s.pRtc)
2551	rc = pVM->pdm.s.pRtc->Reg.pfnRead(pVM->pdm.s.pRtc->pDevIns, iReg, pu8Value);
2552	else
2553	rc = VERR_PDM_NO_RTC_INSTANCE;
2554
2555	LogFlow(("pdmR3DevHlp_CMOSWrite: caller='%s'/%d: return %Rrc\n",
2556	pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, rc));
2557	return rc;
2558	}
2559
2560
2561	/** @copydoc PDMDEVHLPR3::pfnGetCpuId */
2562	static DECLCALLBACK(void) pdmR3DevHlp_GetCpuId(PPDMDEVINS pDevIns, uint32_t iLeaf,
2563	uint32_t pEax, uint32_t pEbx, uint32_t pEcx, uint32_t pEdx)
2564	{
2565	PDMDEV_ASSERT_DEVINS(pDevIns);
2566	VM_ASSERT_EMT(pDevIns->Internal.s.pVMR3);
2567
2568	LogFlow(("pdmR3DevHlp_GetCpuId: caller='%s'/%d: iLeaf=%d pEax=%p pEbx=%p pEcx=%p pEdx=%p\n",
2569	pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, iLeaf, pEax, pEbx, pEcx, pEdx));
2570	AssertPtr(pEax); AssertPtr(pEbx); AssertPtr(pEcx); AssertPtr(pEdx);
2571
2572	CPUMGetGuestCpuId(VMMGetCpu(pDevIns->Internal.s.pVMR3), iLeaf, pEax, pEbx, pEcx, pEdx);
2573
2574	LogFlow(("pdmR3DevHlp_GetCpuId: caller='%s'/%d: returns void - pEax=%#x pEbx=%#x pEcx=%#x pEdx=%#x\n",
2575	pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, pEax, pEbx, pEcx, pEdx));
2576	}
2577
2578
2579	/** @copydoc PDMDEVHLPR3::pfnROMProtectShadow */
2580	static DECLCALLBACK(int) pdmR3DevHlp_ROMProtectShadow(PPDMDEVINS pDevIns, RTGCPHYS GCPhysStart, RTUINT cbRange, PGMROMPROT enmProt)
2581	{
2582	PDMDEV_ASSERT_DEVINS(pDevIns);
2583	LogFlow(("pdmR3DevHlp_ROMProtectShadow: caller='%s'/%d: GCPhysStart=%RGp cbRange=%#x enmProt=%d\n",
2584	pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, GCPhysStart, cbRange, enmProt));
2585
2586	int rc = PGMR3PhysRomProtect(pDevIns->Internal.s.pVMR3, GCPhysStart, cbRange, enmProt);
2587
2588	LogFlow(("pdmR3DevHlp_ROMProtectShadow: caller='%s'/%d: returns %Rrc\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, rc));
2589	return rc;
2590	}
2591
2592
2593	/**
2594	* @copydoc PDMDEVHLPR3::pfnMMIO2Register
2595	*/
2596	static DECLCALLBACK(int) pdmR3DevHlp_MMIO2Register(PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS cb, uint32_t fFlags, void *ppv, const char pszDesc)
2597	{
2598	PDMDEV_ASSERT_DEVINS(pDevIns);
2599	VM_ASSERT_EMT(pDevIns->Internal.s.pVMR3);
2600	LogFlow(("pdmR3DevHlp_MMIO2Register: caller='%s'/%d: iRegion=#x cb=%#RGp fFlags=%RX32 ppv=%p pszDescp=%p:{%s}\n",
2601	pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, iRegion, cb, fFlags, ppv, pszDesc, pszDesc));
2602
2603	/** @todo PGMR3PhysMMIO2Register mangles the description, move it here and
2604	* use a real string cache. */
2605	int rc = PGMR3PhysMMIO2Register(pDevIns->Internal.s.pVMR3, pDevIns, iRegion, cb, fFlags, ppv, pszDesc);
2606
2607	LogFlow(("pdmR3DevHlp_MMIO2Register: caller='%s'/%d: returns %Rrc\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, rc));
2608	return rc;
2609	}
2610
2611
2612	/**
2613	* @copydoc PDMDEVHLPR3::pfnMMIO2Deregister
2614	*/
2615	static DECLCALLBACK(int) pdmR3DevHlp_MMIO2Deregister(PPDMDEVINS pDevIns, uint32_t iRegion)
2616	{
2617	PDMDEV_ASSERT_DEVINS(pDevIns);
2618	VM_ASSERT_EMT(pDevIns->Internal.s.pVMR3);
2619	LogFlow(("pdmR3DevHlp_MMIO2Deregister: caller='%s'/%d: iRegion=#x\n",
2620	pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, iRegion));
2621
2622	AssertReturn(iRegion == UINT32_MAX, VERR_INVALID_PARAMETER);
2623
2624	int rc = PGMR3PhysMMIO2Deregister(pDevIns->Internal.s.pVMR3, pDevIns, iRegion);
2625
2626	LogFlow(("pdmR3DevHlp_MMIO2Deregister: caller='%s'/%d: returns %Rrc\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, rc));
2627	return rc;
2628	}
2629
2630
2631	/**
2632	* @copydoc PDMDEVHLPR3::pfnMMIO2Map
2633	*/
2634	static DECLCALLBACK(int) pdmR3DevHlp_MMIO2Map(PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS GCPhys)
2635	{
2636	PDMDEV_ASSERT_DEVINS(pDevIns);
2637	VM_ASSERT_EMT(pDevIns->Internal.s.pVMR3);
2638	LogFlow(("pdmR3DevHlp_MMIO2Map: caller='%s'/%d: iRegion=#x GCPhys=%#RGp\n",
2639	pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, iRegion, GCPhys));
2640
2641	int rc = PGMR3PhysMMIO2Map(pDevIns->Internal.s.pVMR3, pDevIns, iRegion, GCPhys);
2642
2643	LogFlow(("pdmR3DevHlp_MMIO2Map: caller='%s'/%d: returns %Rrc\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, rc));
2644	return rc;
2645	}
2646
2647
2648	/**
2649	* @copydoc PDMDEVHLPR3::pfnMMIO2Unmap
2650	*/
2651	static DECLCALLBACK(int) pdmR3DevHlp_MMIO2Unmap(PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS GCPhys)
2652	{
2653	PDMDEV_ASSERT_DEVINS(pDevIns);
2654	VM_ASSERT_EMT(pDevIns->Internal.s.pVMR3);
2655	LogFlow(("pdmR3DevHlp_MMIO2Unmap: caller='%s'/%d: iRegion=#x GCPhys=%#RGp\n",
2656	pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, iRegion, GCPhys));
2657
2658	int rc = PGMR3PhysMMIO2Unmap(pDevIns->Internal.s.pVMR3, pDevIns, iRegion, GCPhys);
2659
2660	LogFlow(("pdmR3DevHlp_MMIO2Unmap: caller='%s'/%d: returns %Rrc\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, rc));
2661	return rc;
2662	}
2663
2664
2665	/**
2666	* @copydoc PDMDEVHLPR3::pfnMMHyperMapMMIO2
2667	*/
2668	static DECLCALLBACK(int) pdmR3DevHlp_MMHyperMapMMIO2(PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS off, RTGCPHYS cb,
2669	const char *pszDesc, PRTRCPTR pRCPtr)
2670	{
2671	PDMDEV_ASSERT_DEVINS(pDevIns);
2672	PVM pVM = pDevIns->Internal.s.pVMR3;
2673	VM_ASSERT_EMT(pVM);
2674	LogFlow(("pdmR3DevHlp_MMHyperMapMMIO2: caller='%s'/%d: iRegion=#x off=%RGp cb=%RGp pszDesc=%p:{%s} pRCPtr=%p\n",
2675	pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, iRegion, off, cb, pszDesc, pszDesc, pRCPtr));
2676
2677	if (pDevIns->iInstance > 0)
2678	{
2679	char *pszDesc2 = MMR3HeapAPrintf(pVM, MM_TAG_PDM_DEVICE_DESC, "%s [%u]", pszDesc, pDevIns->iInstance);
2680	if (pszDesc2)
2681	pszDesc = pszDesc2;
2682	}
2683
2684	int rc = MMR3HyperMapMMIO2(pVM, pDevIns, iRegion, off, cb, pszDesc, pRCPtr);
2685
2686	LogFlow(("pdmR3DevHlp_MMHyperMapMMIO2: caller='%s'/%d: returns %Rrc pRCPtr=%RRv\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, rc, pRCPtr));
2687	return rc;
2688	}
2689
2690
2691	/**
2692	* @copydoc PDMDEVHLPR3::pfnMMIO2MapKernel
2693	*/
2694	static DECLCALLBACK(int) pdmR3DevHlp_MMIO2MapKernel(PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS off, RTGCPHYS cb,
2695	const char *pszDesc, PRTR0PTR pR0Ptr)
2696	{
2697	PDMDEV_ASSERT_DEVINS(pDevIns);
2698	PVM pVM = pDevIns->Internal.s.pVMR3;
2699	VM_ASSERT_EMT(pVM);
2700	LogFlow(("pdmR3DevHlp_MMIO2MapKernel: caller='%s'/%d: iRegion=#x off=%RGp cb=%RGp pszDesc=%p:{%s} pR0Ptr=%p\n",
2701	pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, iRegion, off, cb, pszDesc, pszDesc, pR0Ptr));
2702
2703	if (pDevIns->iInstance > 0)
2704	{
2705	char *pszDesc2 = MMR3HeapAPrintf(pVM, MM_TAG_PDM_DEVICE_DESC, "%s [%u]", pszDesc, pDevIns->iInstance);
2706	if (pszDesc2)
2707	pszDesc = pszDesc2;
2708	}
2709
2710	int rc = PGMR3PhysMMIO2MapKernel(pVM, pDevIns, iRegion, off, cb, pszDesc, pR0Ptr);
2711
2712	LogFlow(("pdmR3DevHlp_MMIO2MapKernel: caller='%s'/%d: returns %Rrc pR0Ptr=%RHv\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance, rc, pR0Ptr));
2713	return rc;
2714	}
2715
2716
2717	/**
2718	* @copydoc PDMDEVHLPR3::pfnRegisterVMMDevHeap
2719	*/
2720	static DECLCALLBACK(int) pdmR3DevHlp_RegisterVMMDevHeap(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, RTR3PTR pvHeap, unsigned cbSize)
2721	{
2722	PDMDEV_ASSERT_DEVINS(pDevIns);
2723	VM_ASSERT_EMT(pDevIns->Internal.s.pVMR3);
2724
2725	int rc = PDMR3RegisterVMMDevHeap(pDevIns->Internal.s.pVMR3, GCPhys, pvHeap, cbSize);
2726	return rc;
2727	}
2728
2729
2730	/**
2731	* @copydoc PDMDEVHLPR3::pfnUnregisterVMMDevHeap
2732	*/
2733	static DECLCALLBACK(int) pdmR3DevHlp_UnregisterVMMDevHeap(PPDMDEVINS pDevIns, RTGCPHYS GCPhys)
2734	{
2735	PDMDEV_ASSERT_DEVINS(pDevIns);
2736	VM_ASSERT_EMT(pDevIns->Internal.s.pVMR3);
2737
2738	int rc = PDMR3UnregisterVMMDevHeap(pDevIns->Internal.s.pVMR3, GCPhys);
2739	return rc;
2740	}
2741
2742
2743	/**
2744	* The device helper structure for trusted devices.
2745	*/
2746	const PDMDEVHLPR3 g_pdmR3DevHlpTrusted =
2747	{
2748	PDM_DEVHLP_VERSION,
2749	pdmR3DevHlp_IOPortRegister,
2750	pdmR3DevHlp_IOPortRegisterGC,
2751	pdmR3DevHlp_IOPortRegisterR0,
2752	pdmR3DevHlp_IOPortDeregister,
2753	pdmR3DevHlp_MMIORegister,
2754	pdmR3DevHlp_MMIORegisterGC,
2755	pdmR3DevHlp_MMIORegisterR0,
2756	pdmR3DevHlp_MMIODeregister,
2757	pdmR3DevHlp_ROMRegister,
2758	pdmR3DevHlp_SSMRegister,
2759	pdmR3DevHlp_TMTimerCreate,
2760	pdmR3DevHlp_PCIRegister,
2761	pdmR3DevHlp_PCIIORegionRegister,
2762	pdmR3DevHlp_PCISetConfigCallbacks,
2763	pdmR3DevHlp_PCISetIrq,
2764	pdmR3DevHlp_PCISetIrqNoWait,
2765	pdmR3DevHlp_ISASetIrq,
2766	pdmR3DevHlp_ISASetIrqNoWait,
2767	pdmR3DevHlp_DriverAttach,
2768	pdmR3DevHlp_MMHeapAlloc,
2769	pdmR3DevHlp_MMHeapAllocZ,
2770	pdmR3DevHlp_MMHeapFree,
2771	pdmR3DevHlp_VMSetError,
2772	pdmR3DevHlp_VMSetErrorV,
2773	pdmR3DevHlp_VMSetRuntimeError,
2774	pdmR3DevHlp_VMSetRuntimeErrorV,
2775	pdmR3DevHlp_AssertEMT,
2776	pdmR3DevHlp_AssertOther,
2777	pdmR3DevHlp_DBGFStopV,
2778	pdmR3DevHlp_DBGFInfoRegister,
2779	pdmR3DevHlp_STAMRegister,
2780	pdmR3DevHlp_STAMRegisterF,
2781	pdmR3DevHlp_STAMRegisterV,
2782	pdmR3DevHlp_RTCRegister,
2783	pdmR3DevHlp_PDMQueueCreate,
2784	pdmR3DevHlp_CritSectInit,
2785	pdmR3DevHlp_UTCNow,
2786	pdmR3DevHlp_PDMThreadCreate,
2787	pdmR3DevHlp_PhysGCPtr2GCPhys,
2788	pdmR3DevHlp_VMState,
2789	0,
2790	0,
2791	0,
2792	0,
2793	0,
2794	0,
2795	0,
2796	pdmR3DevHlp_GetVM,
2797	pdmR3DevHlp_PCIBusRegister,
2798	pdmR3DevHlp_PICRegister,
2799	pdmR3DevHlp_APICRegister,
2800	pdmR3DevHlp_IOAPICRegister,
2801	pdmR3DevHlp_DMACRegister,
2802	pdmR3DevHlp_PhysRead,
2803	pdmR3DevHlp_PhysWrite,
2804	pdmR3DevHlp_PhysGCPhys2CCPtr,
2805	pdmR3DevHlp_PhysGCPhys2CCPtrReadOnly,
2806	pdmR3DevHlp_PhysReleasePageMappingLock,
2807	pdmR3DevHlp_PhysReadGCVirt,
2808	pdmR3DevHlp_PhysWriteGCVirt,
2809	pdmR3DevHlp_A20IsEnabled,
2810	pdmR3DevHlp_A20Set,
2811	pdmR3DevHlp_VMReset,
2812	pdmR3DevHlp_VMSuspend,
2813	pdmR3DevHlp_VMPowerOff,
2814	pdmR3DevHlp_DMARegister,
2815	pdmR3DevHlp_DMAReadMemory,
2816	pdmR3DevHlp_DMAWriteMemory,
2817	pdmR3DevHlp_DMASetDREQ,
2818	pdmR3DevHlp_DMAGetChannelMode,
2819	pdmR3DevHlp_DMASchedule,
2820	pdmR3DevHlp_CMOSWrite,
2821	pdmR3DevHlp_CMOSRead,
2822	pdmR3DevHlp_GetCpuId,
2823	pdmR3DevHlp_ROMProtectShadow,
2824	pdmR3DevHlp_MMIO2Register,
2825	pdmR3DevHlp_MMIO2Deregister,
2826	pdmR3DevHlp_MMIO2Map,
2827	pdmR3DevHlp_MMIO2Unmap,
2828	pdmR3DevHlp_MMHyperMapMMIO2,
2829	pdmR3DevHlp_MMIO2MapKernel,
2830	pdmR3DevHlp_RegisterVMMDevHeap,
2831	pdmR3DevHlp_UnregisterVMMDevHeap,
2832	pdmR3DevHlp_GetVMCPU,
2833	PDM_DEVHLP_VERSION /* the end */
2834	};
2835
2836
2837
2838
2839	/** @copydoc PDMDEVHLPR3::pfnGetVM */
2840	static DECLCALLBACK(PVM) pdmR3DevHlp_Untrusted_GetVM(PPDMDEVINS pDevIns)
2841	{
2842	PDMDEV_ASSERT_DEVINS(pDevIns);
2843	AssertReleaseMsgFailed(("Untrusted device called trusted helper! '%s'/%d\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance));
2844	return NULL;
2845	}
2846
2847
2848	/** @copydoc PDMDEVHLPR3::pfnPCIBusRegister */
2849	static DECLCALLBACK(int) pdmR3DevHlp_Untrusted_PCIBusRegister(PPDMDEVINS pDevIns, PPDMPCIBUSREG pPciBusReg, PCPDMPCIHLPR3 *ppPciHlpR3)
2850	{
2851	PDMDEV_ASSERT_DEVINS(pDevIns);
2852	AssertReleaseMsgFailed(("Untrusted device called trusted helper! '%s'/%d\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance));
2853	NOREF(pPciBusReg);
2854	NOREF(ppPciHlpR3);
2855	return VERR_ACCESS_DENIED;
2856	}
2857
2858
2859	/** @copydoc PDMDEVHLPR3::pfnPICRegister */
2860	static DECLCALLBACK(int) pdmR3DevHlp_Untrusted_PICRegister(PPDMDEVINS pDevIns, PPDMPICREG pPicReg, PCPDMPICHLPR3 *ppPicHlpR3)
2861	{
2862	PDMDEV_ASSERT_DEVINS(pDevIns);
2863	AssertReleaseMsgFailed(("Untrusted device called trusted helper! '%s'/%d\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance));
2864	NOREF(pPicReg);
2865	NOREF(ppPicHlpR3);
2866	return VERR_ACCESS_DENIED;
2867	}
2868
2869
2870	/** @copydoc PDMDEVHLPR3::pfnAPICRegister */
2871	static DECLCALLBACK(int) pdmR3DevHlp_Untrusted_APICRegister(PPDMDEVINS pDevIns, PPDMAPICREG pApicReg, PCPDMAPICHLPR3 *ppApicHlpR3)
2872	{
2873	PDMDEV_ASSERT_DEVINS(pDevIns);
2874	AssertReleaseMsgFailed(("Untrusted device called trusted helper! '%s'/%d\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance));
2875	NOREF(pApicReg);
2876	NOREF(ppApicHlpR3);
2877	return VERR_ACCESS_DENIED;
2878	}
2879
2880
2881	/** @copydoc PDMDEVHLPR3::pfnIOAPICRegister */
2882	static DECLCALLBACK(int) pdmR3DevHlp_Untrusted_IOAPICRegister(PPDMDEVINS pDevIns, PPDMIOAPICREG pIoApicReg, PCPDMIOAPICHLPR3 *ppIoApicHlpR3)
2883	{
2884	PDMDEV_ASSERT_DEVINS(pDevIns);
2885	AssertReleaseMsgFailed(("Untrusted device called trusted helper! '%s'/%d\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance));
2886	NOREF(pIoApicReg);
2887	NOREF(ppIoApicHlpR3);
2888	return VERR_ACCESS_DENIED;
2889	}
2890
2891
2892	/** @copydoc PDMDEVHLPR3::pfnDMACRegister */
2893	static DECLCALLBACK(int) pdmR3DevHlp_Untrusted_DMACRegister(PPDMDEVINS pDevIns, PPDMDMACREG pDmacReg, PCPDMDMACHLP *ppDmacHlp)
2894	{
2895	PDMDEV_ASSERT_DEVINS(pDevIns);
2896	AssertReleaseMsgFailed(("Untrusted device called trusted helper! '%s'/%d\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance));
2897	NOREF(pDmacReg);
2898	NOREF(ppDmacHlp);
2899	return VERR_ACCESS_DENIED;
2900	}
2901
2902
2903	/** @copydoc PDMDEVHLPR3::pfnPhysRead */
2904	static DECLCALLBACK(int) pdmR3DevHlp_Untrusted_PhysRead(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead)
2905	{
2906	PDMDEV_ASSERT_DEVINS(pDevIns);
2907	AssertReleaseMsgFailed(("Untrusted device called trusted helper! '%s'/%d\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance));
2908	NOREF(GCPhys);
2909	NOREF(pvBuf);
2910	NOREF(cbRead);
2911	return VERR_ACCESS_DENIED;
2912	}
2913
2914
2915	/** @copydoc PDMDEVHLPR3::pfnPhysWrite */
2916	static DECLCALLBACK(int) pdmR3DevHlp_Untrusted_PhysWrite(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite)
2917	{
2918	PDMDEV_ASSERT_DEVINS(pDevIns);
2919	AssertReleaseMsgFailed(("Untrusted device called trusted helper! '%s'/%d\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance));
2920	NOREF(GCPhys);
2921	NOREF(pvBuf);
2922	NOREF(cbWrite);
2923	return VERR_ACCESS_DENIED;
2924	}
2925
2926
2927	/** @copydoc PDMDEVHLPR3::pfnPhysGCPhys2CCPtr */
2928	static DECLCALLBACK(int) pdmR3DevHlp_Untrusted_PhysGCPhys2CCPtr(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, uint32_t fFlags, void **ppv, PPGMPAGEMAPLOCK pLock)
2929	{
2930	PDMDEV_ASSERT_DEVINS(pDevIns);
2931	AssertReleaseMsgFailed(("Untrusted device called trusted helper! '%s'/%d\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance));
2932	NOREF(GCPhys);
2933	NOREF(fFlags);
2934	NOREF(ppv);
2935	NOREF(pLock);
2936	return VERR_ACCESS_DENIED;
2937	}
2938
2939
2940	/** @copydoc PDMDEVHLPR3::pfnPhysGCPhys2CCPtrReadOnly */
2941	static DECLCALLBACK(int) pdmR3DevHlp_Untrusted_PhysGCPhys2CCPtrReadOnly(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, uint32_t fFlags, const void **ppv, PPGMPAGEMAPLOCK pLock)
2942	{
2943	PDMDEV_ASSERT_DEVINS(pDevIns);
2944	AssertReleaseMsgFailed(("Untrusted device called trusted helper! '%s'/%d\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance));
2945	NOREF(GCPhys);
2946	NOREF(fFlags);
2947	NOREF(ppv);
2948	NOREF(pLock);
2949	return VERR_ACCESS_DENIED;
2950	}
2951
2952
2953	/** @copydoc PDMDEVHLPR3::pfnPhysReleasePageMappingLock */
2954	static DECLCALLBACK(void) pdmR3DevHlp_Untrusted_PhysReleasePageMappingLock(PPDMDEVINS pDevIns, PPGMPAGEMAPLOCK pLock)
2955	{
2956	PDMDEV_ASSERT_DEVINS(pDevIns);
2957	AssertReleaseMsgFailed(("Untrusted device called trusted helper! '%s'/%d\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance));
2958	NOREF(pLock);
2959	}
2960
2961
2962	/** @copydoc PDMDEVHLPR3::pfnPhysReadGCVirt */
2963	static DECLCALLBACK(int) pdmR3DevHlp_Untrusted_PhysReadGCVirt(PPDMDEVINS pDevIns, void *pvDst, RTGCPTR GCVirtSrc, size_t cb)
2964	{
2965	PDMDEV_ASSERT_DEVINS(pDevIns);
2966	AssertReleaseMsgFailed(("Untrusted device called trusted helper! '%s'/%d\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance));
2967	NOREF(pvDst);
2968	NOREF(GCVirtSrc);
2969	NOREF(cb);
2970	return VERR_ACCESS_DENIED;
2971	}
2972
2973
2974	/** @copydoc PDMDEVHLPR3::pfnPhysWriteGCVirt */
2975	static DECLCALLBACK(int) pdmR3DevHlp_Untrusted_PhysWriteGCVirt(PPDMDEVINS pDevIns, RTGCPTR GCVirtDst, const void *pvSrc, size_t cb)
2976	{
2977	PDMDEV_ASSERT_DEVINS(pDevIns);
2978	AssertReleaseMsgFailed(("Untrusted device called trusted helper! '%s'/%d\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance));
2979	NOREF(GCVirtDst);
2980	NOREF(pvSrc);
2981	NOREF(cb);
2982	return VERR_ACCESS_DENIED;
2983	}
2984
2985
2986	/** @copydoc PDMDEVHLPR3::pfnA20IsEnabled */
2987	static DECLCALLBACK(bool) pdmR3DevHlp_Untrusted_A20IsEnabled(PPDMDEVINS pDevIns)
2988	{
2989	PDMDEV_ASSERT_DEVINS(pDevIns);
2990	AssertReleaseMsgFailed(("Untrusted device called trusted helper! '%s'/%d\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance));
2991	return false;
2992	}
2993
2994
2995	/** @copydoc PDMDEVHLPR3::pfnA20Set */
2996	static DECLCALLBACK(void) pdmR3DevHlp_Untrusted_A20Set(PPDMDEVINS pDevIns, bool fEnable)
2997	{
2998	PDMDEV_ASSERT_DEVINS(pDevIns);
2999	AssertReleaseMsgFailed(("Untrusted device called trusted helper! '%s'/%d\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance));
3000	NOREF(fEnable);
3001	}
3002
3003
3004	/** @copydoc PDMDEVHLPR3::pfnVMReset */
3005	static DECLCALLBACK(int) pdmR3DevHlp_Untrusted_VMReset(PPDMDEVINS pDevIns)
3006	{
3007	PDMDEV_ASSERT_DEVINS(pDevIns);
3008	AssertReleaseMsgFailed(("Untrusted device called trusted helper! '%s'/%d\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance));
3009	return VERR_ACCESS_DENIED;
3010	}
3011
3012
3013	/** @copydoc PDMDEVHLPR3::pfnVMSuspend */
3014	static DECLCALLBACK(int) pdmR3DevHlp_Untrusted_VMSuspend(PPDMDEVINS pDevIns)
3015	{
3016	PDMDEV_ASSERT_DEVINS(pDevIns);
3017	AssertReleaseMsgFailed(("Untrusted device called trusted helper! '%s'/%d\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance));
3018	return VERR_ACCESS_DENIED;
3019	}
3020
3021
3022	/** @copydoc PDMDEVHLPR3::pfnVMPowerOff */
3023	static DECLCALLBACK(int) pdmR3DevHlp_Untrusted_VMPowerOff(PPDMDEVINS pDevIns)
3024	{
3025	PDMDEV_ASSERT_DEVINS(pDevIns);
3026	AssertReleaseMsgFailed(("Untrusted device called trusted helper! '%s'/%d\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance));
3027	return VERR_ACCESS_DENIED;
3028	}
3029
3030	/** @copydoc PDMDEVHLPR3::pfnDMARegister */
3031	static DECLCALLBACK(int) pdmR3DevHlp_Untrusted_DMARegister(PPDMDEVINS pDevIns, unsigned uChannel, PFNDMATRANSFERHANDLER pfnTransferHandler, void *pvUser)
3032	{
3033	PDMDEV_ASSERT_DEVINS(pDevIns);
3034	AssertReleaseMsgFailed(("Untrusted device called trusted helper! '%s'/%d\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance));
3035	return VERR_ACCESS_DENIED;
3036	}
3037
3038
3039	/** @copydoc PDMDEVHLPR3::pfnDMAReadMemory */
3040	static DECLCALLBACK(int) pdmR3DevHlp_Untrusted_DMAReadMemory(PPDMDEVINS pDevIns, unsigned uChannel, void pvBuffer, uint32_t off, uint32_t cbBlock, uint32_t pcbRead)
3041	{
3042	PDMDEV_ASSERT_DEVINS(pDevIns);
3043	AssertReleaseMsgFailed(("Untrusted device called trusted helper! '%s'/%d\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance));
3044	if (pcbRead)
3045	*pcbRead = 0;
3046	return VERR_ACCESS_DENIED;
3047	}
3048
3049
3050	/** @copydoc PDMDEVHLPR3::pfnDMAWriteMemory */
3051	static DECLCALLBACK(int) pdmR3DevHlp_Untrusted_DMAWriteMemory(PPDMDEVINS pDevIns, unsigned uChannel, const void pvBuffer, uint32_t off, uint32_t cbBlock, uint32_t pcbWritten)
3052	{
3053	PDMDEV_ASSERT_DEVINS(pDevIns);
3054	AssertReleaseMsgFailed(("Untrusted device called trusted helper! '%s'/%d\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance));
3055	if (pcbWritten)
3056	*pcbWritten = 0;
3057	return VERR_ACCESS_DENIED;
3058	}
3059
3060
3061	/** @copydoc PDMDEVHLPR3::pfnDMASetDREQ */
3062	static DECLCALLBACK(int) pdmR3DevHlp_Untrusted_DMASetDREQ(PPDMDEVINS pDevIns, unsigned uChannel, unsigned uLevel)
3063	{
3064	PDMDEV_ASSERT_DEVINS(pDevIns);
3065	AssertReleaseMsgFailed(("Untrusted device called trusted helper! '%s'/%d\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance));
3066	return VERR_ACCESS_DENIED;
3067	}
3068
3069
3070	/** @copydoc PDMDEVHLPR3::pfnDMAGetChannelMode */
3071	static DECLCALLBACK(uint8_t) pdmR3DevHlp_Untrusted_DMAGetChannelMode(PPDMDEVINS pDevIns, unsigned uChannel)
3072	{
3073	PDMDEV_ASSERT_DEVINS(pDevIns);
3074	AssertReleaseMsgFailed(("Untrusted device called trusted helper! '%s'/%d\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance));
3075	return 3 << 2 /* illegal mode type */;
3076	}
3077
3078
3079	/** @copydoc PDMDEVHLPR3::pfnDMASchedule */
3080	static DECLCALLBACK(void) pdmR3DevHlp_Untrusted_DMASchedule(PPDMDEVINS pDevIns)
3081	{
3082	PDMDEV_ASSERT_DEVINS(pDevIns);
3083	AssertReleaseMsgFailed(("Untrusted device called trusted helper! '%s'/%d\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance));
3084	}
3085
3086
3087	/** @copydoc PDMDEVHLPR3::pfnCMOSWrite */
3088	static DECLCALLBACK(int) pdmR3DevHlp_Untrusted_CMOSWrite(PPDMDEVINS pDevIns, unsigned iReg, uint8_t u8Value)
3089	{
3090	PDMDEV_ASSERT_DEVINS(pDevIns);
3091	AssertReleaseMsgFailed(("Untrusted device called trusted helper! '%s'/%d\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance));
3092	return VERR_ACCESS_DENIED;
3093	}
3094
3095
3096	/** @copydoc PDMDEVHLPR3::pfnCMOSRead */
3097	static DECLCALLBACK(int) pdmR3DevHlp_Untrusted_CMOSRead(PPDMDEVINS pDevIns, unsigned iReg, uint8_t *pu8Value)
3098	{
3099	PDMDEV_ASSERT_DEVINS(pDevIns);
3100	AssertReleaseMsgFailed(("Untrusted device called trusted helper! '%s'/%d\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance));
3101	return VERR_ACCESS_DENIED;
3102	}
3103
3104
3105	/** @copydoc PDMDEVHLPR3::pfnGetCpuId */
3106	static DECLCALLBACK(void) pdmR3DevHlp_Untrusted_GetCpuId(PPDMDEVINS pDevIns, uint32_t iLeaf,
3107	uint32_t pEax, uint32_t pEbx, uint32_t pEcx, uint32_t pEdx)
3108	{
3109	PDMDEV_ASSERT_DEVINS(pDevIns);
3110	AssertReleaseMsgFailed(("Untrusted device called trusted helper! '%s'/%d\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance));
3111	}
3112
3113
3114	/** @copydoc PDMDEVHLPR3::pfnROMProtectShadow */
3115	static DECLCALLBACK(int) pdmR3DevHlp_Untrusted_ROMProtectShadow(PPDMDEVINS pDevIns, RTGCPHYS GCPhysStart, RTUINT cbRange, PGMROMPROT enmProt)
3116	{
3117	PDMDEV_ASSERT_DEVINS(pDevIns);
3118	AssertReleaseMsgFailed(("Untrusted device called trusted helper! '%s'/%d\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance));
3119	return VERR_ACCESS_DENIED;
3120	}
3121
3122
3123	/** @copydoc PDMDEVHLPR3::pfnMMIO2Register */
3124	static DECLCALLBACK(int) pdmR3DevHlp_Untrusted_MMIO2Register(PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS cb, uint32_t fFlags, void *ppv, const char pszDesc)
3125	{
3126	PDMDEV_ASSERT_DEVINS(pDevIns);
3127	AssertReleaseMsgFailed(("Untrusted device called trusted helper! '%s'/%d\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance));
3128	return VERR_ACCESS_DENIED;
3129	}
3130
3131
3132	/** @copydoc PDMDEVHLPR3::pfnMMIO2Deregister */
3133	static DECLCALLBACK(int) pdmR3DevHlp_Untrusted_MMIO2Deregister(PPDMDEVINS pDevIns, uint32_t iRegion)
3134	{
3135	PDMDEV_ASSERT_DEVINS(pDevIns);
3136	AssertReleaseMsgFailed(("Untrusted device called trusted helper! '%s'/%d\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance));
3137	return VERR_ACCESS_DENIED;
3138	}
3139
3140
3141	/** @copydoc PDMDEVHLPR3::pfnMMIO2Map */
3142	static DECLCALLBACK(int) pdmR3DevHlp_Untrusted_MMIO2Map(PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS GCPhys)
3143	{
3144	PDMDEV_ASSERT_DEVINS(pDevIns);
3145	AssertReleaseMsgFailed(("Untrusted device called trusted helper! '%s'/%d\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance));
3146	return VERR_ACCESS_DENIED;
3147	}
3148
3149
3150	/** @copydoc PDMDEVHLPR3::pfnMMIO2Unmap */
3151	static DECLCALLBACK(int) pdmR3DevHlp_Untrusted_MMIO2Unmap(PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS GCPhys)
3152	{
3153	PDMDEV_ASSERT_DEVINS(pDevIns);
3154	AssertReleaseMsgFailed(("Untrusted device called trusted helper! '%s'/%d\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance));
3155	return VERR_ACCESS_DENIED;
3156	}
3157
3158
3159	/** @copydoc PDMDEVHLPR3::pfnMMHyperMapMMIO2 */
3160	static DECLCALLBACK(int) pdmR3DevHlp_Untrusted_MMHyperMapMMIO2(PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS off, RTGCPHYS cb, const char *pszDesc, PRTRCPTR pRCPtr)
3161	{
3162	PDMDEV_ASSERT_DEVINS(pDevIns);
3163	AssertReleaseMsgFailed(("Untrusted device called trusted helper! '%s'/%d\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance));
3164	return VERR_ACCESS_DENIED;
3165	}
3166
3167
3168	/** @copydoc PDMDEVHLPR3::pfnMMIO2MapKernel */
3169	static DECLCALLBACK(int) pdmR3DevHlp_Untrusted_MMIO2MapKernel(PPDMDEVINS pDevIns, uint32_t iRegion, RTGCPHYS off, RTGCPHYS cb, const char *pszDesc, PRTR0PTR pR0Ptr)
3170	{
3171	PDMDEV_ASSERT_DEVINS(pDevIns);
3172	AssertReleaseMsgFailed(("Untrusted device called trusted helper! '%s'/%d\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance));
3173	return VERR_ACCESS_DENIED;
3174	}
3175
3176
3177	/** @copydoc PDMDEVHLPR3::pfnRegisterVMMDevHeap */
3178	static DECLCALLBACK(int) pdmR3DevHlp_Untrusted_RegisterVMMDevHeap(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, RTR3PTR pvHeap, unsigned cbSize)
3179	{
3180	PDMDEV_ASSERT_DEVINS(pDevIns);
3181	AssertReleaseMsgFailed(("Untrusted device called trusted helper! '%s'/%d\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance));
3182	return VERR_ACCESS_DENIED;
3183	}
3184
3185
3186	/** @copydoc PDMDEVHLPR3::pfnUnregisterVMMDevHeap */
3187	static DECLCALLBACK(int) pdmR3DevHlp_Untrusted_UnregisterVMMDevHeap(PPDMDEVINS pDevIns, RTGCPHYS GCPhys)
3188	{
3189	PDMDEV_ASSERT_DEVINS(pDevIns);
3190	AssertReleaseMsgFailed(("Untrusted device called trusted helper! '%s'/%d\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance));
3191	return VERR_ACCESS_DENIED;
3192	}
3193
3194
3195	/** @copydoc PDMDEVHLPR3::pfnGetVMCPU */
3196	static DECLCALLBACK(PVMCPU) pdmR3DevHlp_Untrusted_GetVMCPU(PPDMDEVINS pDevIns)
3197	{
3198	PDMDEV_ASSERT_DEVINS(pDevIns);
3199	AssertReleaseMsgFailed(("Untrusted device called trusted helper! '%s'/%d\n", pDevIns->pDevReg->szDeviceName, pDevIns->iInstance));
3200	return NULL;
3201	}
3202
3203
3204	/**
3205	* The device helper structure for non-trusted devices.
3206	*/
3207	const PDMDEVHLPR3 g_pdmR3DevHlpUnTrusted =
3208	{
3209	PDM_DEVHLP_VERSION,
3210	pdmR3DevHlp_IOPortRegister,
3211	pdmR3DevHlp_IOPortRegisterGC,
3212	pdmR3DevHlp_IOPortRegisterR0,
3213	pdmR3DevHlp_IOPortDeregister,
3214	pdmR3DevHlp_MMIORegister,
3215	pdmR3DevHlp_MMIORegisterGC,
3216	pdmR3DevHlp_MMIORegisterR0,
3217	pdmR3DevHlp_MMIODeregister,
3218	pdmR3DevHlp_ROMRegister,
3219	pdmR3DevHlp_SSMRegister,
3220	pdmR3DevHlp_TMTimerCreate,
3221	pdmR3DevHlp_PCIRegister,
3222	pdmR3DevHlp_PCIIORegionRegister,
3223	pdmR3DevHlp_PCISetConfigCallbacks,
3224	pdmR3DevHlp_PCISetIrq,
3225	pdmR3DevHlp_PCISetIrqNoWait,
3226	pdmR3DevHlp_ISASetIrq,
3227	pdmR3DevHlp_ISASetIrqNoWait,
3228	pdmR3DevHlp_DriverAttach,
3229	pdmR3DevHlp_MMHeapAlloc,
3230	pdmR3DevHlp_MMHeapAllocZ,
3231	pdmR3DevHlp_MMHeapFree,
3232	pdmR3DevHlp_VMSetError,
3233	pdmR3DevHlp_VMSetErrorV,
3234	pdmR3DevHlp_VMSetRuntimeError,
3235	pdmR3DevHlp_VMSetRuntimeErrorV,
3236	pdmR3DevHlp_AssertEMT,
3237	pdmR3DevHlp_AssertOther,
3238	pdmR3DevHlp_DBGFStopV,
3239	pdmR3DevHlp_DBGFInfoRegister,
3240	pdmR3DevHlp_STAMRegister,
3241	pdmR3DevHlp_STAMRegisterF,
3242	pdmR3DevHlp_STAMRegisterV,
3243	pdmR3DevHlp_RTCRegister,
3244	pdmR3DevHlp_PDMQueueCreate,
3245	pdmR3DevHlp_CritSectInit,
3246	pdmR3DevHlp_UTCNow,
3247	pdmR3DevHlp_PDMThreadCreate,
3248	pdmR3DevHlp_PhysGCPtr2GCPhys,
3249	pdmR3DevHlp_VMState,
3250	0,
3251	0,
3252	0,
3253	0,
3254	0,
3255	0,
3256	0,
3257	pdmR3DevHlp_Untrusted_GetVM,
3258	pdmR3DevHlp_Untrusted_PCIBusRegister,
3259	pdmR3DevHlp_Untrusted_PICRegister,
3260	pdmR3DevHlp_Untrusted_APICRegister,
3261	pdmR3DevHlp_Untrusted_IOAPICRegister,
3262	pdmR3DevHlp_Untrusted_DMACRegister,
3263	pdmR3DevHlp_Untrusted_PhysRead,
3264	pdmR3DevHlp_Untrusted_PhysWrite,
3265	pdmR3DevHlp_Untrusted_PhysGCPhys2CCPtr,
3266	pdmR3DevHlp_Untrusted_PhysGCPhys2CCPtrReadOnly,
3267	pdmR3DevHlp_Untrusted_PhysReleasePageMappingLock,
3268	pdmR3DevHlp_Untrusted_PhysReadGCVirt,
3269	pdmR3DevHlp_Untrusted_PhysWriteGCVirt,
3270	pdmR3DevHlp_Untrusted_A20IsEnabled,
3271	pdmR3DevHlp_Untrusted_A20Set,
3272	pdmR3DevHlp_Untrusted_VMReset,
3273	pdmR3DevHlp_Untrusted_VMSuspend,
3274	pdmR3DevHlp_Untrusted_VMPowerOff,
3275	pdmR3DevHlp_Untrusted_DMARegister,
3276	pdmR3DevHlp_Untrusted_DMAReadMemory,
3277	pdmR3DevHlp_Untrusted_DMAWriteMemory,
3278	pdmR3DevHlp_Untrusted_DMASetDREQ,
3279	pdmR3DevHlp_Untrusted_DMAGetChannelMode,
3280	pdmR3DevHlp_Untrusted_DMASchedule,
3281	pdmR3DevHlp_Untrusted_CMOSWrite,
3282	pdmR3DevHlp_Untrusted_CMOSRead,
3283	pdmR3DevHlp_Untrusted_GetCpuId,
3284	pdmR3DevHlp_Untrusted_ROMProtectShadow,
3285	pdmR3DevHlp_Untrusted_MMIO2Register,
3286	pdmR3DevHlp_Untrusted_MMIO2Deregister,
3287	pdmR3DevHlp_Untrusted_MMIO2Map,
3288	pdmR3DevHlp_Untrusted_MMIO2Unmap,
3289	pdmR3DevHlp_Untrusted_MMHyperMapMMIO2,
3290	pdmR3DevHlp_Untrusted_MMIO2MapKernel,
3291	pdmR3DevHlp_Untrusted_RegisterVMMDevHeap,
3292	pdmR3DevHlp_Untrusted_UnregisterVMMDevHeap,
3293	pdmR3DevHlp_Untrusted_GetVMCPU,
3294	PDM_DEVHLP_VERSION /* the end */
3295	};
3296
3297
3298
3299	/**
3300	* Queue consumer callback for internal component.
3301	*
3302	* @returns Success indicator.
3303	* If false the item will not be removed and the flushing will stop.
3304	* @param pVM The VM handle.
3305	* @param pItem The item to consume. Upon return this item will be freed.
3306	*/
3307	DECLCALLBACK(bool) pdmR3DevHlpQueueConsumer(PVM pVM, PPDMQUEUEITEMCORE pItem)
3308	{
3309	PPDMDEVHLPTASK pTask = (PPDMDEVHLPTASK)pItem;
3310	LogFlow(("pdmR3DevHlpQueueConsumer: enmOp=%d pDevIns=%p\n", pTask->enmOp, pTask->pDevInsR3));
3311	switch (pTask->enmOp)
3312	{
3313	case PDMDEVHLPTASKOP_ISA_SET_IRQ:
3314	PDMIsaSetIrq(pVM, pTask->u.SetIRQ.iIrq, pTask->u.SetIRQ.iLevel);
3315	break;
3316
3317	case PDMDEVHLPTASKOP_PCI_SET_IRQ:
3318	pdmR3DevHlp_PCISetIrq(pTask->pDevInsR3, pTask->u.SetIRQ.iIrq, pTask->u.SetIRQ.iLevel);
3319	break;
3320
3321	case PDMDEVHLPTASKOP_IOAPIC_SET_IRQ:
3322	PDMIoApicSetIrq(pVM, pTask->u.SetIRQ.iIrq, pTask->u.SetIRQ.iLevel);
3323	break;
3324
3325	default:
3326	AssertReleaseMsgFailed(("Invalid operation %d\n", pTask->enmOp));
3327	break;
3328	}
3329	return true;
3330	}
3331
3332	/** @} */
3333

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source: vbox/trunk/src/VBox/VMM/PDMDevHlp.cpp@ 20927

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