PGM.cpp@ 10700

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1	/* $Id: PGM.cpp 10507 2008-07-11 09:51:47Z vboxsync $ */
2	/** @file
3	* PGM - Page Manager and Monitor. (Mixing stuff here, not good?)
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22
23	/** @page pg_pgm PGM - The Page Manager and Monitor
24	*
25	*
26	*
27	* @section sec_pgm_modes Paging Modes
28	*
29	* There are three memory contexts: Host Context (HC), Guest Context (GC)
30	* and intermediate context. When talking about paging HC can also be refered to
31	* as "host paging", and GC refered to as "shadow paging".
32	*
33	* We define three basic paging modes: 32-bit, PAE and AMD64. The host paging mode
34	* is defined by the host operating system. The mode used in the shadow paging mode
35	* depends on the host paging mode and what the mode the guest is currently in. The
36	* following relation between the two is defined:
37	*
38	* @verbatim
39	Host > 32-bit \| PAE \| AMD64 \|
40	Guest \| \| \| \|
41	==v================================
42	32-bit 32-bit PAE PAE
43	-------\|--------\|--------\|--------\|
44	PAE PAE PAE PAE
45	-------\|--------\|--------\|--------\|
46	AMD64 AMD64 AMD64 AMD64
47	-------\|--------\|--------\|--------\| @endverbatim
48	*
49	* All configuration except those in the diagonal (upper left) are expected to
50	* require special effort from the switcher (i.e. a bit slower).
51	*
52	*
53	*
54	*
55	* @section sec_pgm_shw The Shadow Memory Context
56	*
57	*
58	* [..]
59	*
60	* Because of guest context mappings requires PDPT and PML4 entries to allow
61	* writing on AMD64, the two upper levels will have fixed flags whatever the
62	* guest is thinking of using there. So, when shadowing the PD level we will
63	* calculate the effective flags of PD and all the higher levels. In legacy
64	* PAE mode this only applies to the PWT and PCD bits (the rest are
65	* ignored/reserved/MBZ). We will ignore those bits for the present.
66	*
67	*
68	*
69	* @section sec_pgm_int The Intermediate Memory Context
70	*
71	* The world switch goes thru an intermediate memory context which purpose it is
72	* to provide different mappings of the switcher code. All guest mappings are also
73	* present in this context.
74	*
75	* The switcher code is mapped at the same location as on the host, at an
76	* identity mapped location (physical equals virtual address), and at the
77	* hypervisor location.
78	*
79	* PGM maintain page tables for 32-bit, PAE and AMD64 paging modes. This
80	* simplifies switching guest CPU mode and consistency at the cost of more
81	* code to do the work. All memory use for those page tables is located below
82	* 4GB (this includes page tables for guest context mappings).
83	*
84	*
85	* @subsection subsec_pgm_int_gc Guest Context Mappings
86	*
87	* During assignment and relocation of a guest context mapping the intermediate
88	* memory context is used to verify the new location.
89	*
90	* Guest context mappings are currently restricted to below 4GB, for reasons
91	* of simplicity. This may change when we implement AMD64 support.
92	*
93	*
94	*
95	*
96	* @section sec_pgm_misc Misc
97	*
98	* @subsection subsec_pgm_misc_diff Differences Between Legacy PAE and Long Mode PAE
99	*
100	* The differences between legacy PAE and long mode PAE are:
101	* -# PDPE bits 1, 2, 5 and 6 are defined differently. In leagcy mode they are
102	* all marked down as must-be-zero, while in long mode 1, 2 and 5 have the
103	* usual meanings while 6 is ignored (AMD). This means that upon switching to
104	* legacy PAE mode we'll have to clear these bits and when going to long mode
105	* they must be set. This applies to both intermediate and shadow contexts,
106	* however we don't need to do it for the intermediate one since we're
107	* executing with CR0.WP at that time.
108	* -# CR3 allows a 32-byte aligned address in legacy mode, while in long mode
109	* a page aligned one is required.
110	*
111	*
112	* @section sec_pgm_handlers Access Handlers
113	*
114	* Placeholder.
115	*
116	*
117	* @subsection sec_pgm_handlers_virt Virtual Access Handlers
118	*
119	* Placeholder.
120	*
121	*
122	* @subsection sec_pgm_handlers_virt Virtual Access Handlers
123	*
124	* We currently implement three types of virtual access handlers: ALL, WRITE
125	* and HYPERVISOR (WRITE). See PGMVIRTHANDLERTYPE for some more details.
126	*
127	* The HYPERVISOR access handlers is kept in a separate tree since it doesn't apply
128	* to physical pages (PGMTREES::HyperVirtHandlers) and only needs to be consulted in
129	* a special \#PF case. The ALL and WRITE are in the PGMTREES::VirtHandlers tree, the
130	* rest of this section is going to be about these handlers.
131	*
132	* We'll go thru the life cycle of a handler and try make sense of it all, don't know
133	* how successfull this is gonna be...
134	*
135	* 1. A handler is registered thru the PGMR3HandlerVirtualRegister and
136	* PGMHandlerVirtualRegisterEx APIs. We check for conflicting virtual handlers
137	* and create a new node that is inserted into the AVL tree (range key). Then
138	* a full PGM resync is flagged (clear pool, sync cr3, update virtual bit of PGMPAGE).
139	*
140	* 2. The following PGMSyncCR3/SyncCR3 operation will first make invoke HandlerVirtualUpdate.
141	*
142	* 2a. HandlerVirtualUpdate will will lookup all the pages covered by virtual handlers
143	* via the current guest CR3 and update the physical page -> virtual handler
144	* translation. Needless to say, this doesn't exactly scale very well. If any changes
145	* are detected, it will flag a virtual bit update just like we did on registration.
146	* PGMPHYS pages with changes will have their virtual handler state reset to NONE.
147	*
148	* 2b. The virtual bit update process will iterate all the pages covered by all the
149	* virtual handlers and update the PGMPAGE virtual handler state to the max of all
150	* virtual handlers on that page.
151	*
152	* 2c. Back in SyncCR3 we will now flush the entire shadow page cache to make sure
153	* we don't miss any alias mappings of the monitored pages.
154	*
155	* 2d. SyncCR3 will then proceed with syncing the CR3 table.
156	*
157	* 3. \#PF(np,read) on a page in the range. This will cause it to be synced
158	* read-only and resumed if it's a WRITE handler. If it's an ALL handler we
159	* will call the handlers like in the next step. If the physical mapping has
160	* changed we will - some time in the future - perform a handler callback
161	* (optional) and update the physical -> virtual handler cache.
162	*
163	* 4. \#PF(,write) on a page in the range. This will cause the handler to
164	* be invoked.
165	*
166	* 5. The guest invalidates the page and changes the physical backing or
167	* unmaps it. This should cause the invalidation callback to be invoked
168	* (it might not yet be 100% perfect). Exactly what happens next... is
169	* this where we mess up and end up out of sync for a while?
170	*
171	* 6. The handler is deregistered by the client via PGMHandlerVirtualDeregister.
172	* We will then set all PGMPAGEs in the physical -> virtual handler cache for
173	* this handler to NONE and trigger a full PGM resync (basically the same
174	* as int step 1). Which means 2 is executed again.
175	*
176	*
177	* @subsubsection sub_sec_pgm_handler_virt_todo TODOs
178	*
179	* There is a bunch of things that needs to be done to make the virtual handlers
180	* work 100% correctly and work more efficiently.
181	*
182	* The first bit hasn't been implemented yet because it's going to slow the
183	* whole mess down even more, and besides it seems to be working reliably for
184	* our current uses. OTOH, some of the optimizations might end up more or less
185	* implementing the missing bits, so we'll see.
186	*
187	* On the optimization side, the first thing to do is to try avoid unnecessary
188	* cache flushing. Then try team up with the shadowing code to track changes
189	* in mappings by means of access to them (shadow in), updates to shadows pages,
190	* invlpg, and shadow PT discarding (perhaps).
191	*
192	* Some idea that have popped up for optimization for current and new features:
193	* - bitmap indicating where there are virtual handlers installed.
194	* (4KB => 220 pages, page 212 => covers 32-bit address space 1:1!)
195	* - Further optimize this by min/max (needs min/max avl getters).
196	* - Shadow page table entry bit (if any left)?
197	*
198	*/
199
200
201	/** @page pg_pgmPhys PGMPhys - Physical Guest Memory Management.
202	*
203	*
204	* Objectives:
205	* - Guest RAM over-commitment using memory ballooning,
206	* zero pages and general page sharing.
207	* - Moving or mirroring a VM onto a different physical machine.
208	*
209	*
210	* @subsection subsec_pgmPhys_Definitions Definitions
211	*
212	* Allocation chunk - A RTR0MemObjAllocPhysNC object and the tracking
213	* machinery assoicated with it.
214	*
215	*
216	*
217	*
218	* @subsection subsec_pgmPhys_AllocPage Allocating a page.
219	*
220	* Initially we map all guest memory to the (per VM) zero page, which
221	* means that none of the read functions will cause pages to be allocated.
222	*
223	* Exception, access bit in page tables that have been shared. This must
224	* be handled, but we must also make sure PGMGst*Modify doesn't make
225	* unnecessary modifications.
226	*
227	* Allocation points:
228	* - PGMPhysWriteGCPhys and PGMPhysWrite.
229	* - Replacing a zero page mapping at \#PF.
230	* - Replacing a shared page mapping at \#PF.
231	* - ROM registration (currently MMR3RomRegister).
232	* - VM restore (pgmR3Load).
233	*
234	* For the first three it would make sense to keep a few pages handy
235	* until we've reached the max memory commitment for the VM.
236	*
237	* For the ROM registration, we know exactly how many pages we need
238	* and will request these from ring-0. For restore, we will save
239	* the number of non-zero pages in the saved state and allocate
240	* them up front. This would allow the ring-0 component to refuse
241	* the request if the isn't sufficient memory available for VM use.
242	*
243	* Btw. for both ROM and restore allocations we won't be requiring
244	* zeroed pages as they are going to be filled instantly.
245	*
246	*
247	* @subsection subsec_pgmPhys_FreePage Freeing a page
248	*
249	* There are a few points where a page can be freed:
250	* - After being replaced by the zero page.
251	* - After being replaced by a shared page.
252	* - After being ballooned by the guest additions.
253	* - At reset.
254	* - At restore.
255	*
256	* When freeing one or more pages they will be returned to the ring-0
257	* component and replaced by the zero page.
258	*
259	* The reasoning for clearing out all the pages on reset is that it will
260	* return us to the exact same state as on power on, and may thereby help
261	* us reduce the memory load on the system. Further it might have a
262	* (temporary) positive influence on memory fragmentation (@see subsec_pgmPhys_Fragmentation).
263	*
264	* On restore, as mention under the allocation topic, pages should be
265	* freed / allocated depending on how many is actually required by the
266	* new VM state. The simplest approach is to do like on reset, and free
267	* all non-ROM pages and then allocate what we need.
268	*
269	* A measure to prevent some fragmentation, would be to let each allocation
270	* chunk have some affinity towards the VM having allocated the most pages
271	* from it. Also, try make sure to allocate from allocation chunks that
272	* are almost full. Admittedly, both these measures might work counter to
273	* our intentions and its probably not worth putting a lot of effort,
274	* cpu time or memory into this.
275	*
276	*
277	* @subsection subsec_pgmPhys_SharePage Sharing a page
278	*
279	* The basic idea is that there there will be a idle priority kernel
280	* thread walking the non-shared VM pages hashing them and looking for
281	* pages with the same checksum. If such pages are found, it will compare
282	* them byte-by-byte to see if they actually are identical. If found to be
283	* identical it will allocate a shared page, copy the content, check that
284	* the page didn't change while doing this, and finally request both the
285	* VMs to use the shared page instead. If the page is all zeros (special
286	* checksum and byte-by-byte check) it will request the VM that owns it
287	* to replace it with the zero page.
288	*
289	* To make this efficient, we will have to make sure not to try share a page
290	* that will change its contents soon. This part requires the most work.
291	* A simple idea would be to request the VM to write monitor the page for
292	* a while to make sure it isn't modified any time soon. Also, it may
293	* make sense to skip pages that are being write monitored since this
294	* information is readily available to the thread if it works on the
295	* per-VM guest memory structures (presently called PGMRAMRANGE).
296	*
297	*
298	* @subsection subsec_pgmPhys_Fragmentation Fragmentation Concerns and Counter Measures
299	*
300	* The pages are organized in allocation chunks in ring-0, this is a necessity
301	* if we wish to have an OS agnostic approach to this whole thing. (On Linux we
302	* could easily work on a page-by-page basis if we liked. Whether this is possible
303	* or efficient on NT I don't quite know.) Fragmentation within these chunks may
304	* become a problem as part of the idea here is that we wish to return memory to
305	* the host system.
306	*
307	* For instance, starting two VMs at the same time, they will both allocate the
308	* guest memory on-demand and if permitted their page allocations will be
309	* intermixed. Shut down one of the two VMs and it will be difficult to return
310	* any memory to the host system because the page allocation for the two VMs are
311	* mixed up in the same allocation chunks.
312	*
313	* To further complicate matters, when pages are freed because they have been
314	* ballooned or become shared/zero the whole idea is that the page is supposed
315	* to be reused by another VM or returned to the host system. This will cause
316	* allocation chunks to contain pages belonging to different VMs and prevent
317	* returning memory to the host when one of those VM shuts down.
318	*
319	* The only way to really deal with this problem is to move pages. This can
320	* either be done at VM shutdown and or by the idle priority worker thread
321	* that will be responsible for finding sharable/zero pages. The mechanisms
322	* involved for coercing a VM to move a page (or to do it for it) will be
323	* the same as when telling it to share/zero a page.
324	*
325	*
326	* @subsection subsec_pgmPhys_Tracking Tracking Structures And Their Cost
327	*
328	* There's a difficult balance between keeping the per-page tracking structures
329	* (global and guest page) easy to use and keeping them from eating too much
330	* memory. We have limited virtual memory resources available when operating in
331	* 32-bit kernel space (on 64-bit there'll it's quite a different story). The
332	* tracking structures will be attemted designed such that we can deal with up
333	* to 32GB of memory on a 32-bit system and essentially unlimited on 64-bit ones.
334	*
335	*
336	* @subsubsection subsubsec_pgmPhys_Tracking_Kernel Kernel Space
337	*
338	* @see pg_GMM
339	*
340	* @subsubsection subsubsec_pgmPhys_Tracking_PerVM Per-VM
341	*
342	* Fixed info is the physical address of the page (HCPhys) and the page id
343	* (described above). Theoretically we'll need 48(-12) bits for the HCPhys part.
344	* Today we've restricting ourselves to 40(-12) bits because this is the current
345	* restrictions of all AMD64 implementations (I think Barcelona will up this
346	* to 48(-12) bits, not that it really matters) and I needed the bits for
347	* tracking mappings of a page. 48-12 = 36. That leaves 28 bits, which means a
348	* decent range for the page id: 2^(28+12) = 1024TB.
349	*
350	* In additions to these, we'll have to keep maintaining the page flags as we
351	* currently do. Although it wouldn't harm to optimize these quite a bit, like
352	* for instance the ROM shouldn't depend on having a write handler installed
353	* in order for it to become read-only. A RO/RW bit should be considered so
354	* that the page syncing code doesn't have to mess about checking multiple
355	* flag combinations (ROM \|\| RW handler \|\| write monitored) in order to
356	* figure out how to setup a shadow PTE. But this of course, is second
357	* priority at present. Current this requires 12 bits, but could probably
358	* be optimized to ~8.
359	*
360	* Then there's the 24 bits used to track which shadow page tables are
361	* currently mapping a page for the purpose of speeding up physical
362	* access handlers, and thereby the page pool cache. More bit for this
363	* purpose wouldn't hurt IIRC.
364	*
365	* Then there is a new bit in which we need to record what kind of page
366	* this is, shared, zero, normal or write-monitored-normal. This'll
367	* require 2 bits. One bit might be needed for indicating whether a
368	* write monitored page has been written to. And yet another one or
369	* two for tracking migration status. 3-4 bits total then.
370	*
371	* Whatever is left will can be used to record the sharabilitiy of a
372	* page. The page checksum will not be stored in the per-VM table as
373	* the idle thread will not be permitted to do modifications to it.
374	* It will instead have to keep its own working set of potentially
375	* shareable pages and their check sums and stuff.
376	*
377	* For the present we'll keep the current packing of the
378	* PGMRAMRANGE::aHCPhys to keep the changes simple, only of course,
379	* we'll have to change it to a struct with a total of 128-bits at
380	* our disposal.
381	*
382	* The initial layout will be like this:
383	* @verbatim
384	RTHCPHYS HCPhys; The current stuff.
385	63:40 Current shadow PT tracking stuff.
386	39:12 The physical page frame number.
387	11:0 The current flags.
388	uint32_t u28PageId : 28; The page id.
389	uint32_t u2State : 2; The page state { zero, shared, normal, write monitored }.
390	uint32_t fWrittenTo : 1; Whether a write monitored page was written to.
391	uint32_t u1Reserved : 1; Reserved for later.
392	uint32_t u32Reserved; Reserved for later, mostly sharing stats.
393	@endverbatim
394	*
395	* The final layout will be something like this:
396	* @verbatim
397	RTHCPHYS HCPhys; The current stuff.
398	63:48 High page id (12+).
399	47:12 The physical page frame number.
400	11:0 Low page id.
401	uint32_t fReadOnly : 1; Whether it's readonly page (rom or monitored in some way).
402	uint32_t u3Type : 3; The page type {RESERVED, MMIO, MMIO2, ROM, shadowed ROM, RAM}.
403	uint32_t u2PhysMon : 2; Physical access handler type {none, read, write, all}.
404	uint32_t u2VirtMon : 2; Virtual access handler type {none, read, write, all}..
405	uint32_t u2State : 2; The page state { zero, shared, normal, write monitored }.
406	uint32_t fWrittenTo : 1; Whether a write monitored page was written to.
407	uint32_t u20Reserved : 20; Reserved for later, mostly sharing stats.
408	uint32_t u32Tracking; The shadow PT tracking stuff, roughly.
409	@endverbatim
410	*
411	* Cost wise, this means we'll double the cost for guest memory. There isn't anyway
412	* around that I'm afraid. It means that the cost of dealing out 32GB of memory
413	* to one or more VMs is: (32GB >> PAGE_SHIFT) * 16 bytes, or 128MBs. Or another
414	* example, the VM heap cost when assigning 1GB to a VM will be: 4MB.
415	*
416	* A couple of cost examples for the total cost per-VM + kernel.
417	* 32-bit Windows and 32-bit linux:
418	* 1GB guest ram, 256K pages: 4MB + 2MB(+) = 6MB
419	* 4GB guest ram, 1M pages: 16MB + 8MB(+) = 24MB
420	* 32GB guest ram, 8M pages: 128MB + 64MB(+) = 192MB
421	* 64-bit Windows and 64-bit linux:
422	* 1GB guest ram, 256K pages: 4MB + 3MB(+) = 7MB
423	* 4GB guest ram, 1M pages: 16MB + 12MB(+) = 28MB
424	* 32GB guest ram, 8M pages: 128MB + 96MB(+) = 224MB
425	*
426	* UPDATE - 2007-09-27:
427	* Will need a ballooned flag/state too because we cannot
428	* trust the guest 100% and reporting the same page as ballooned more
429	* than once will put the GMM off balance.
430	*
431	*
432	* @subsection subsec_pgmPhys_Serializing Serializing Access
433	*
434	* Initially, we'll try a simple scheme:
435	*
436	* - The per-VM RAM tracking structures (PGMRAMRANGE) is only modified
437	* by the EMT thread of that VM while in the pgm critsect.
438	* - Other threads in the VM process that needs to make reliable use of
439	* the per-VM RAM tracking structures will enter the critsect.
440	* - No process external thread or kernel thread will ever try enter
441	* the pgm critical section, as that just won't work.
442	* - The idle thread (and similar threads) doesn't not need 100% reliable
443	* data when performing it tasks as the EMT thread will be the one to
444	* do the actual changes later anyway. So, as long as it only accesses
445	* the main ram range, it can do so by somehow preventing the VM from
446	* being destroyed while it works on it...
447	*
448	* - The over-commitment management, including the allocating/freeing
449	* chunks, is serialized by a ring-0 mutex lock (a fast one since the
450	* more mundane mutex implementation is broken on Linux).
451	* - A separeate mutex is protecting the set of allocation chunks so
452	* that pages can be shared or/and freed up while some other VM is
453	* allocating more chunks. This mutex can be take from under the other
454	* one, but not the otherway around.
455	*
456	*
457	* @subsection subsec_pgmPhys_Request VM Request interface
458	*
459	* When in ring-0 it will become necessary to send requests to a VM so it can
460	* for instance move a page while defragmenting during VM destroy. The idle
461	* thread will make use of this interface to request VMs to setup shared
462	* pages and to perform write monitoring of pages.
463	*
464	* I would propose an interface similar to the current VMReq interface, similar
465	* in that it doesn't require locking and that the one sending the request may
466	* wait for completion if it wishes to. This shouldn't be very difficult to
467	* realize.
468	*
469	* The requests themselves are also pretty simple. They are basically:
470	* -# Check that some precondition is still true.
471	* -# Do the update.
472	* -# Update all shadow page tables involved with the page.
473	*
474	* The 3rd step is identical to what we're already doing when updating a
475	* physical handler, see pgmHandlerPhysicalSetRamFlagsAndFlushShadowPTs.
476	*
477	*
478	*
479	* @section sec_pgmPhys_MappingCaches Mapping Caches
480	*
481	* In order to be able to map in and out memory and to be able to support
482	* guest with more RAM than we've got virtual address space, we'll employing
483	* a mapping cache. There is already a tiny one for GC (see PGMGCDynMapGCPageEx)
484	* and we'll create a similar one for ring-0 unless we decide to setup a dedicate
485	* memory context for the HWACCM execution.
486	*
487	*
488	* @subsection subsec_pgmPhys_MappingCaches_R3 Ring-3
489	*
490	* We've considered implementing the ring-3 mapping cache page based but found
491	* that this was bother some when one had to take into account TLBs+SMP and
492	* portability (missing the necessary APIs on several platforms). There were
493	* also some performance concerns with this approach which hadn't quite been
494	* worked out.
495	*
496	* Instead, we'll be mapping allocation chunks into the VM process. This simplifies
497	* matters greatly quite a bit since we don't need to invent any new ring-0 stuff,
498	* only some minor RTR0MEMOBJ mapping stuff. The main concern here is that mapping
499	* compared to the previous idea is that mapping or unmapping a 1MB chunk is more
500	* costly than a single page, although how much more costly is uncertain. We'll
501	* try address this by using a very big cache, preferably bigger than the actual
502	* VM RAM size if possible. The current VM RAM sizes should give some idea for
503	* 32-bit boxes, while on 64-bit we can probably get away with employing an
504	* unlimited cache.
505	*
506	* The cache have to parts, as already indicated, the ring-3 side and the
507	* ring-0 side.
508	*
509	* The ring-0 will be tied to the page allocator since it will operate on the
510	* memory objects it contains. It will therefore require the first ring-0 mutex
511	* discussed in @ref subsec_pgmPhys_Serializing. We
512	* some double house keeping wrt to who has mapped what I think, since both
513	* VMMR0.r0 and RTR0MemObj will keep track of mapping relataions
514	*
515	* The ring-3 part will be protected by the pgm critsect. For simplicity, we'll
516	* require anyone that desires to do changes to the mapping cache to do that
517	* from within this critsect. Alternatively, we could employ a separate critsect
518	* for serializing changes to the mapping cache as this would reduce potential
519	* contention with other threads accessing mappings unrelated to the changes
520	* that are in process. We can see about this later, contention will show
521	* up in the statistics anyway, so it'll be simple to tell.
522	*
523	* The organization of the ring-3 part will be very much like how the allocation
524	* chunks are organized in ring-0, that is in an AVL tree by chunk id. To avoid
525	* having to walk the tree all the time, we'll have a couple of lookaside entries
526	* like in we do for I/O ports and MMIO in IOM.
527	*
528	* The simplified flow of a PGMPhysRead/Write function:
529	* -# Enter the PGM critsect.
530	* -# Lookup GCPhys in the ram ranges and get the Page ID.
531	* -# Calc the Allocation Chunk ID from the Page ID.
532	* -# Check the lookaside entries and then the AVL tree for the Chunk ID.
533	* If not found in cache:
534	* -# Call ring-0 and request it to be mapped and supply
535	* a chunk to be unmapped if the cache is maxed out already.
536	* -# Insert the new mapping into the AVL tree (id + R3 address).
537	* -# Update the relevant lookaside entry and return the mapping address.
538	* -# Do the read/write according to monitoring flags and everything.
539	* -# Leave the critsect.
540	*
541	*
542	* @section sec_pgmPhys_Fallback Fallback
543	*
544	* Current all the "second tier" hosts will not support the RTR0MemObjAllocPhysNC
545	* API and thus require a fallback.
546	*
547	* So, when RTR0MemObjAllocPhysNC returns VERR_NOT_SUPPORTED the page allocator
548	* will return to the ring-3 caller (and later ring-0) and asking it to seed
549	* the page allocator with some fresh pages (VERR_GMM_SEED_ME). Ring-3 will
550	* then perform an SUPPageAlloc(cbChunk >> PAGE_SHIFT) call and make a
551	* "SeededAllocPages" call to ring-0.
552	*
553	* The first time ring-0 sees the VERR_NOT_SUPPORTED failure it will disable
554	* all page sharing (zero page detection will continue). It will also force
555	* all allocations to come from the VM which seeded the page. Both these
556	* measures are taken to make sure that there will never be any need for
557	* mapping anything into ring-3 - everything will be mapped already.
558	*
559	* Whether we'll continue to use the current MM locked memory management
560	* for this I don't quite know (I'd prefer not to and just ditch that all
561	* togther), we'll see what's simplest to do.
562	*
563	*
564	*
565	* @section sec_pgmPhys_Changes Changes
566	*
567	* Breakdown of the changes involved?
568	*/
569
570
571	/** Saved state data unit version. */
572	#define PGM_SAVED_STATE_VERSION 6
573
574	/*******************************************************************************
575	* Header Files *
576	*******************************************************************************/
577	#define LOG_GROUP LOG_GROUP_PGM
578	#include <VBox/dbgf.h>
579	#include <VBox/pgm.h>
580	#include <VBox/cpum.h>
581	#include <VBox/iom.h>
582	#include <VBox/sup.h>
583	#include <VBox/mm.h>
584	#include <VBox/em.h>
585	#include <VBox/stam.h>
586	#include <VBox/rem.h>
587	#include <VBox/dbgf.h>
588	#include <VBox/rem.h>
589	#include <VBox/selm.h>
590	#include <VBox/ssm.h>
591	#include "PGMInternal.h"
592	#include <VBox/vm.h>
593	#include <VBox/dbg.h>
594	#include <VBox/hwaccm.h>
595
596	#include <iprt/assert.h>
597	#include <iprt/alloc.h>
598	#include <iprt/asm.h>
599	#include <iprt/thread.h>
600	#include <iprt/string.h>
601	#include <VBox/param.h>
602	#include <VBox/err.h>
603
604
605
606	/*******************************************************************************
607	* Internal Functions *
608	*******************************************************************************/
609	static int pgmR3InitPaging(PVM pVM);
610	static DECLCALLBACK(void) pgmR3PhysInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
611	static DECLCALLBACK(void) pgmR3InfoMode(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
612	static DECLCALLBACK(void) pgmR3InfoCr3(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
613	static DECLCALLBACK(int) pgmR3RelocatePhysHandler(PAVLROGCPHYSNODECORE pNode, void *pvUser);
614	static DECLCALLBACK(int) pgmR3RelocateVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser);
615	static DECLCALLBACK(int) pgmR3RelocateHyperVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser);
616	#ifdef VBOX_STRICT
617	static DECLCALLBACK(void) pgmR3ResetNoMorePhysWritesFlag(PVM pVM, VMSTATE enmState, VMSTATE enmOldState, void *pvUser);
618	#endif
619	static DECLCALLBACK(int) pgmR3Save(PVM pVM, PSSMHANDLE pSSM);
620	static DECLCALLBACK(int) pgmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version);
621	static int pgmR3ModeDataInit(PVM pVM, bool fResolveGCAndR0);
622	static void pgmR3ModeDataSwitch(PVM pVM, PGMMODE enmShw, PGMMODE enmGst);
623	static PGMMODE pgmR3CalcShadowMode(PVM pVM, PGMMODE enmGuestMode, SUPPAGINGMODE enmHostMode, PGMMODE enmShadowMode, VMMSWITCHER *penmSwitcher);
624
625	#ifdef VBOX_WITH_STATISTICS
626	static void pgmR3InitStats(PVM pVM);
627	#endif
628
629	#ifdef VBOX_WITH_DEBUGGER
630	/** @todo all but the two last commands must be converted to 'info'. */
631	static DECLCALLBACK(int) pgmR3CmdRam(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
632	static DECLCALLBACK(int) pgmR3CmdMap(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
633	static DECLCALLBACK(int) pgmR3CmdSync(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
634	static DECLCALLBACK(int) pgmR3CmdSyncAlways(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
635	static DECLCALLBACK(int) pgmR3CmdAssertCR3(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
636	#endif
637
638
639	/*******************************************************************************
640	* Global Variables *
641	*******************************************************************************/
642	#ifdef VBOX_WITH_DEBUGGER
643	/** Command descriptors. */
644	static const DBGCCMD g_aCmds[] =
645	{
646	/* pszCmd, cArgsMin, cArgsMax, paArgDesc, cArgDescs, pResultDesc, fFlags, pfnHandler pszSyntax, ....pszDescription */
647	{ "pgmram", 0, 0, NULL, 0, NULL, 0, pgmR3CmdRam, "", "Display the ram ranges." },
648	{ "pgmmap", 0, 0, NULL, 0, NULL, 0, pgmR3CmdMap, "", "Display the mapping ranges." },
649	{ "pgmsync", 0, 0, NULL, 0, NULL, 0, pgmR3CmdSync, "", "Sync the CR3 page." },
650	#ifdef VBOX_STRICT
651	{ "pgmassertcr3", 0, 0, NULL, 0, NULL, 0, pgmR3CmdAssertCR3, "", "Check the shadow CR3 mapping." },
652	#endif
653	{ "pgmsyncalways", 0, 0, NULL, 0, NULL, 0, pgmR3CmdSyncAlways, "", "Toggle permanent CR3 syncing." },
654	};
655	#endif
656
657
658
659
660	/*
661	* Shadow - 32-bit mode
662	*/
663	#define PGM_SHW_TYPE PGM_TYPE_32BIT
664	#define PGM_SHW_NAME(name) PGM_SHW_NAME_32BIT(name)
665	#define PGM_SHW_NAME_GC_STR(name) PGM_SHW_NAME_GC_32BIT_STR(name)
666	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_32BIT_STR(name)
667	#include "PGMShw.h"
668
669	/* Guest - real mode */
670	#define PGM_GST_TYPE PGM_TYPE_REAL
671	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
672	#define PGM_GST_NAME_GC_STR(name) PGM_GST_NAME_GC_REAL_STR(name)
673	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
674	#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_REAL(name)
675	#define PGM_BTH_NAME_GC_STR(name) PGM_BTH_NAME_GC_32BIT_REAL_STR(name)
676	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_32BIT_REAL_STR(name)
677	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_PHYS
678	#include "PGMGst.h"
679	#include "PGMBth.h"
680	#undef BTH_PGMPOOLKIND_PT_FOR_PT
681	#undef PGM_BTH_NAME
682	#undef PGM_BTH_NAME_GC_STR
683	#undef PGM_BTH_NAME_R0_STR
684	#undef PGM_GST_TYPE
685	#undef PGM_GST_NAME
686	#undef PGM_GST_NAME_GC_STR
687	#undef PGM_GST_NAME_R0_STR
688
689	/* Guest - protected mode */
690	#define PGM_GST_TYPE PGM_TYPE_PROT
691	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
692	#define PGM_GST_NAME_GC_STR(name) PGM_GST_NAME_GC_PROT_STR(name)
693	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
694	#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_PROT(name)
695	#define PGM_BTH_NAME_GC_STR(name) PGM_BTH_NAME_GC_32BIT_PROT_STR(name)
696	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_32BIT_PROT_STR(name)
697	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_PHYS
698	#include "PGMGst.h"
699	#include "PGMBth.h"
700	#undef BTH_PGMPOOLKIND_PT_FOR_PT
701	#undef PGM_BTH_NAME
702	#undef PGM_BTH_NAME_GC_STR
703	#undef PGM_BTH_NAME_R0_STR
704	#undef PGM_GST_TYPE
705	#undef PGM_GST_NAME
706	#undef PGM_GST_NAME_GC_STR
707	#undef PGM_GST_NAME_R0_STR
708
709	/* Guest - 32-bit mode */
710	#define PGM_GST_TYPE PGM_TYPE_32BIT
711	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
712	#define PGM_GST_NAME_GC_STR(name) PGM_GST_NAME_GC_32BIT_STR(name)
713	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
714	#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_32BIT(name)
715	#define PGM_BTH_NAME_GC_STR(name) PGM_BTH_NAME_GC_32BIT_32BIT_STR(name)
716	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_32BIT_32BIT_STR(name)
717	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT
718	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB
719	#include "PGMGst.h"
720	#include "PGMBth.h"
721	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
722	#undef BTH_PGMPOOLKIND_PT_FOR_PT
723	#undef PGM_BTH_NAME
724	#undef PGM_BTH_NAME_GC_STR
725	#undef PGM_BTH_NAME_R0_STR
726	#undef PGM_GST_TYPE
727	#undef PGM_GST_NAME
728	#undef PGM_GST_NAME_GC_STR
729	#undef PGM_GST_NAME_R0_STR
730
731	#undef PGM_SHW_TYPE
732	#undef PGM_SHW_NAME
733	#undef PGM_SHW_NAME_GC_STR
734	#undef PGM_SHW_NAME_R0_STR
735
736
737	/*
738	* Shadow - PAE mode
739	*/
740	#define PGM_SHW_TYPE PGM_TYPE_PAE
741	#define PGM_SHW_NAME(name) PGM_SHW_NAME_PAE(name)
742	#define PGM_SHW_NAME_GC_STR(name) PGM_SHW_NAME_GC_PAE_STR(name)
743	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_PAE_STR(name)
744	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_REAL(name)
745	#include "PGMShw.h"
746
747	/* Guest - real mode */
748	#define PGM_GST_TYPE PGM_TYPE_REAL
749	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
750	#define PGM_GST_NAME_GC_STR(name) PGM_GST_NAME_GC_REAL_STR(name)
751	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
752	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_REAL(name)
753	#define PGM_BTH_NAME_GC_STR(name) PGM_BTH_NAME_GC_PAE_REAL_STR(name)
754	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_REAL_STR(name)
755	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
756	#include "PGMBth.h"
757	#undef BTH_PGMPOOLKIND_PT_FOR_PT
758	#undef PGM_BTH_NAME
759	#undef PGM_BTH_NAME_GC_STR
760	#undef PGM_BTH_NAME_R0_STR
761	#undef PGM_GST_TYPE
762	#undef PGM_GST_NAME
763	#undef PGM_GST_NAME_GC_STR
764	#undef PGM_GST_NAME_R0_STR
765
766	/* Guest - protected mode */
767	#define PGM_GST_TYPE PGM_TYPE_PROT
768	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
769	#define PGM_GST_NAME_GC_STR(name) PGM_GST_NAME_GC_PROT_STR(name)
770	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
771	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_PROT(name)
772	#define PGM_BTH_NAME_GC_STR(name) PGM_BTH_NAME_GC_PAE_PROT_STR(name)
773	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_PROT_STR(name)
774	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
775	#include "PGMBth.h"
776	#undef BTH_PGMPOOLKIND_PT_FOR_PT
777	#undef PGM_BTH_NAME
778	#undef PGM_BTH_NAME_GC_STR
779	#undef PGM_BTH_NAME_R0_STR
780	#undef PGM_GST_TYPE
781	#undef PGM_GST_NAME
782	#undef PGM_GST_NAME_GC_STR
783	#undef PGM_GST_NAME_R0_STR
784
785	/* Guest - 32-bit mode */
786	#define PGM_GST_TYPE PGM_TYPE_32BIT
787	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
788	#define PGM_GST_NAME_GC_STR(name) PGM_GST_NAME_GC_32BIT_STR(name)
789	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
790	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_32BIT(name)
791	#define PGM_BTH_NAME_GC_STR(name) PGM_BTH_NAME_GC_PAE_32BIT_STR(name)
792	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_32BIT_STR(name)
793	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_32BIT_PT
794	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB
795	#include "PGMBth.h"
796	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
797	#undef BTH_PGMPOOLKIND_PT_FOR_PT
798	#undef PGM_BTH_NAME
799	#undef PGM_BTH_NAME_GC_STR
800	#undef PGM_BTH_NAME_R0_STR
801	#undef PGM_GST_TYPE
802	#undef PGM_GST_NAME
803	#undef PGM_GST_NAME_GC_STR
804	#undef PGM_GST_NAME_R0_STR
805
806	/* Guest - PAE mode */
807	#define PGM_GST_TYPE PGM_TYPE_PAE
808	#define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
809	#define PGM_GST_NAME_GC_STR(name) PGM_GST_NAME_GC_PAE_STR(name)
810	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PAE_STR(name)
811	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_PAE(name)
812	#define PGM_BTH_NAME_GC_STR(name) PGM_BTH_NAME_GC_PAE_PAE_STR(name)
813	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_PAE_STR(name)
814	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
815	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
816	#include "PGMGst.h"
817	#include "PGMBth.h"
818	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
819	#undef BTH_PGMPOOLKIND_PT_FOR_PT
820	#undef PGM_BTH_NAME
821	#undef PGM_BTH_NAME_GC_STR
822	#undef PGM_BTH_NAME_R0_STR
823	#undef PGM_GST_TYPE
824	#undef PGM_GST_NAME
825	#undef PGM_GST_NAME_GC_STR
826	#undef PGM_GST_NAME_R0_STR
827
828	#undef PGM_SHW_TYPE
829	#undef PGM_SHW_NAME
830	#undef PGM_SHW_NAME_GC_STR
831	#undef PGM_SHW_NAME_R0_STR
832
833
834	/*
835	* Shadow - AMD64 mode
836	*/
837	#define PGM_SHW_TYPE PGM_TYPE_AMD64
838	#define PGM_SHW_NAME(name) PGM_SHW_NAME_AMD64(name)
839	#define PGM_SHW_NAME_GC_STR(name) PGM_SHW_NAME_GC_AMD64_STR(name)
840	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_AMD64_STR(name)
841	#include "PGMShw.h"
842
843	/* Guest - AMD64 mode */
844	#define PGM_GST_TYPE PGM_TYPE_AMD64
845	#define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
846	#define PGM_GST_NAME_GC_STR(name) PGM_GST_NAME_GC_AMD64_STR(name)
847	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_AMD64_STR(name)
848	#define PGM_BTH_NAME(name) PGM_BTH_NAME_AMD64_AMD64(name)
849	#define PGM_BTH_NAME_GC_STR(name) PGM_BTH_NAME_GC_AMD64_AMD64_STR(name)
850	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_AMD64_AMD64_STR(name)
851	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
852	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
853	#include "PGMGst.h"
854	#include "PGMBth.h"
855	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
856	#undef BTH_PGMPOOLKIND_PT_FOR_PT
857	#undef PGM_BTH_NAME
858	#undef PGM_BTH_NAME_GC_STR
859	#undef PGM_BTH_NAME_R0_STR
860	#undef PGM_GST_TYPE
861	#undef PGM_GST_NAME
862	#undef PGM_GST_NAME_GC_STR
863	#undef PGM_GST_NAME_R0_STR
864
865	#undef PGM_SHW_TYPE
866	#undef PGM_SHW_NAME
867	#undef PGM_SHW_NAME_GC_STR
868	#undef PGM_SHW_NAME_R0_STR
869
870	/*
871	* Shadow - Nested paging mode
872	*/
873	#define PGM_SHW_TYPE PGM_TYPE_NESTED
874	#define PGM_SHW_NAME(name) PGM_SHW_NAME_NESTED(name)
875	#define PGM_SHW_NAME_GC_STR(name) PGM_SHW_NAME_GC_NESTED_STR(name)
876	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_NESTED_STR(name)
877	#include "PGMShw.h"
878
879	/* Guest - real mode */
880	#define PGM_GST_TYPE PGM_TYPE_REAL
881	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
882	#define PGM_GST_NAME_GC_STR(name) PGM_GST_NAME_GC_REAL_STR(name)
883	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
884	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_REAL(name)
885	#define PGM_BTH_NAME_GC_STR(name) PGM_BTH_NAME_GC_NESTED_REAL_STR(name)
886	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_REAL_STR(name)
887	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
888	#include "PGMBth.h"
889	#undef BTH_PGMPOOLKIND_PT_FOR_PT
890	#undef PGM_BTH_NAME
891	#undef PGM_BTH_NAME_GC_STR
892	#undef PGM_BTH_NAME_R0_STR
893	#undef PGM_GST_TYPE
894	#undef PGM_GST_NAME
895	#undef PGM_GST_NAME_GC_STR
896	#undef PGM_GST_NAME_R0_STR
897
898	/* Guest - protected mode */
899	#define PGM_GST_TYPE PGM_TYPE_PROT
900	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
901	#define PGM_GST_NAME_GC_STR(name) PGM_GST_NAME_GC_PROT_STR(name)
902	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
903	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_PROT(name)
904	#define PGM_BTH_NAME_GC_STR(name) PGM_BTH_NAME_GC_NESTED_PROT_STR(name)
905	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_PROT_STR(name)
906	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
907	#include "PGMBth.h"
908	#undef BTH_PGMPOOLKIND_PT_FOR_PT
909	#undef PGM_BTH_NAME
910	#undef PGM_BTH_NAME_GC_STR
911	#undef PGM_BTH_NAME_R0_STR
912	#undef PGM_GST_TYPE
913	#undef PGM_GST_NAME
914	#undef PGM_GST_NAME_GC_STR
915	#undef PGM_GST_NAME_R0_STR
916
917	/* Guest - 32-bit mode */
918	#define PGM_GST_TYPE PGM_TYPE_32BIT
919	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
920	#define PGM_GST_NAME_GC_STR(name) PGM_GST_NAME_GC_32BIT_STR(name)
921	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
922	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_32BIT(name)
923	#define PGM_BTH_NAME_GC_STR(name) PGM_BTH_NAME_GC_NESTED_32BIT_STR(name)
924	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_32BIT_STR(name)
925	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_32BIT_PT
926	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB
927	#include "PGMBth.h"
928	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
929	#undef BTH_PGMPOOLKIND_PT_FOR_PT
930	#undef PGM_BTH_NAME
931	#undef PGM_BTH_NAME_GC_STR
932	#undef PGM_BTH_NAME_R0_STR
933	#undef PGM_GST_TYPE
934	#undef PGM_GST_NAME
935	#undef PGM_GST_NAME_GC_STR
936	#undef PGM_GST_NAME_R0_STR
937
938	/* Guest - PAE mode */
939	#define PGM_GST_TYPE PGM_TYPE_PAE
940	#define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
941	#define PGM_GST_NAME_GC_STR(name) PGM_GST_NAME_GC_PAE_STR(name)
942	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PAE_STR(name)
943	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_PAE(name)
944	#define PGM_BTH_NAME_GC_STR(name) PGM_BTH_NAME_GC_NESTED_PAE_STR(name)
945	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_PAE_STR(name)
946	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
947	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
948	#include "PGMBth.h"
949	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
950	#undef BTH_PGMPOOLKIND_PT_FOR_PT
951	#undef PGM_BTH_NAME
952	#undef PGM_BTH_NAME_GC_STR
953	#undef PGM_BTH_NAME_R0_STR
954	#undef PGM_GST_TYPE
955	#undef PGM_GST_NAME
956	#undef PGM_GST_NAME_GC_STR
957	#undef PGM_GST_NAME_R0_STR
958
959	/* Guest - AMD64 mode */
960	#define PGM_GST_TYPE PGM_TYPE_AMD64
961	#define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
962	#define PGM_GST_NAME_GC_STR(name) PGM_GST_NAME_GC_AMD64_STR(name)
963	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_AMD64_STR(name)
964	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_AMD64(name)
965	#define PGM_BTH_NAME_GC_STR(name) PGM_BTH_NAME_GC_NESTED_AMD64_STR(name)
966	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_AMD64_STR(name)
967	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
968	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
969	#include "PGMBth.h"
970	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
971	#undef BTH_PGMPOOLKIND_PT_FOR_PT
972	#undef PGM_BTH_NAME
973	#undef PGM_BTH_NAME_GC_STR
974	#undef PGM_BTH_NAME_R0_STR
975	#undef PGM_GST_TYPE
976	#undef PGM_GST_NAME
977	#undef PGM_GST_NAME_GC_STR
978	#undef PGM_GST_NAME_R0_STR
979
980	#undef PGM_SHW_TYPE
981	#undef PGM_SHW_NAME
982	#undef PGM_SHW_NAME_GC_STR
983	#undef PGM_SHW_NAME_R0_STR
984
985
986	/**
987	* Initiates the paging of VM.
988	*
989	* @returns VBox status code.
990	* @param pVM Pointer to VM structure.
991	*/
992	PGMR3DECL(int) PGMR3Init(PVM pVM)
993	{
994	LogFlow(("PGMR3Init:\n"));
995
996	/*
997	* Assert alignment and sizes.
998	*/
999	AssertRelease(sizeof(pVM->pgm.s) <= sizeof(pVM->pgm.padding));
1000
1001	/*
1002	* Init the structure.
1003	*/
1004	pVM->pgm.s.offVM = RT_OFFSETOF(VM, pgm.s);
1005	pVM->pgm.s.enmShadowMode = PGMMODE_INVALID;
1006	pVM->pgm.s.enmGuestMode = PGMMODE_INVALID;
1007	pVM->pgm.s.enmHostMode = SUPPAGINGMODE_INVALID;
1008	pVM->pgm.s.GCPhysCR3 = NIL_RTGCPHYS;
1009	pVM->pgm.s.GCPhysGstCR3Monitored = NIL_RTGCPHYS;
1010	pVM->pgm.s.fA20Enabled = true;
1011	pVM->pgm.s.pGstPaePDPTHC = NULL;
1012	pVM->pgm.s.pGstPaePDPTGC = 0;
1013	for (unsigned i = 0; i < ELEMENTS(pVM->pgm.s.apGstPaePDsHC); i++)
1014	{
1015	pVM->pgm.s.apGstPaePDsHC[i] = NULL;
1016	pVM->pgm.s.apGstPaePDsGC[i] = 0;
1017	pVM->pgm.s.aGCPhysGstPaePDs[i] = NIL_RTGCPHYS;
1018	pVM->pgm.s.aGCPhysGstPaePDsMonitored[i] = NIL_RTGCPHYS;
1019	}
1020
1021	#ifdef VBOX_STRICT
1022	VMR3AtStateRegister(pVM, pgmR3ResetNoMorePhysWritesFlag, NULL);
1023	#endif
1024
1025	/*
1026	* Get the configured RAM size - to estimate saved state size.
1027	*/
1028	uint64_t cbRam;
1029	int rc = CFGMR3QueryU64(CFGMR3GetRoot(pVM), "RamSize", &cbRam);
1030	if (rc == VERR_CFGM_VALUE_NOT_FOUND)
1031	cbRam = pVM->pgm.s.cbRamSize = 0;
1032	else if (VBOX_SUCCESS(rc))
1033	{
1034	if (cbRam < PAGE_SIZE)
1035	cbRam = 0;
1036	cbRam = RT_ALIGN_64(cbRam, PAGE_SIZE);
1037	pVM->pgm.s.cbRamSize = (RTUINT)cbRam;
1038	}
1039	else
1040	{
1041	AssertMsgFailed(("Configuration error: Failed to query integer \"RamSize\", rc=%Vrc.\n", rc));
1042	return rc;
1043	}
1044
1045	/*
1046	* Register saved state data unit.
1047	*/
1048	rc = SSMR3RegisterInternal(pVM, "pgm", 1, PGM_SAVED_STATE_VERSION, (size_t)cbRam + sizeof(PGM),
1049	NULL, pgmR3Save, NULL,
1050	NULL, pgmR3Load, NULL);
1051	if (VBOX_FAILURE(rc))
1052	return rc;
1053
1054	/*
1055	* Initialize the PGM critical section and flush the phys TLBs
1056	*/
1057	rc = PDMR3CritSectInit(pVM, &pVM->pgm.s.CritSect, "PGM");
1058	AssertRCReturn(rc, rc);
1059
1060	PGMR3PhysChunkInvalidateTLB(pVM);
1061	PGMPhysInvalidatePageR3MapTLB(pVM);
1062	PGMPhysInvalidatePageR0MapTLB(pVM);
1063	PGMPhysInvalidatePageGCMapTLB(pVM);
1064
1065	/*
1066	* Trees
1067	*/
1068	rc = MMHyperAlloc(pVM, sizeof(PGMTREES), 0, MM_TAG_PGM, (void **)&pVM->pgm.s.pTreesHC);
1069	if (VBOX_SUCCESS(rc))
1070	{
1071	pVM->pgm.s.pTreesGC = MMHyperHC2GC(pVM, pVM->pgm.s.pTreesHC);
1072
1073	/*
1074	* Alocate the zero page.
1075	*/
1076	rc = MMHyperAlloc(pVM, PAGE_SIZE, PAGE_SIZE, MM_TAG_PGM, &pVM->pgm.s.pvZeroPgR3);
1077	}
1078	if (VBOX_SUCCESS(rc))
1079	{
1080	pVM->pgm.s.pvZeroPgGC = MMHyperR3ToGC(pVM, pVM->pgm.s.pvZeroPgR3);
1081	pVM->pgm.s.pvZeroPgR0 = MMHyperR3ToR0(pVM, pVM->pgm.s.pvZeroPgR3);
1082	AssertRelease(pVM->pgm.s.pvZeroPgR0 != NIL_RTHCPHYS);
1083	pVM->pgm.s.HCPhysZeroPg = MMR3HyperHCVirt2HCPhys(pVM, pVM->pgm.s.pvZeroPgR3);
1084	AssertRelease(pVM->pgm.s.HCPhysZeroPg != NIL_RTHCPHYS);
1085
1086	/*
1087	* Init the paging.
1088	*/
1089	rc = pgmR3InitPaging(pVM);
1090	}
1091	if (VBOX_SUCCESS(rc))
1092	{
1093	/*
1094	* Init the page pool.
1095	*/
1096	rc = pgmR3PoolInit(pVM);
1097	}
1098	if (VBOX_SUCCESS(rc))
1099	{
1100	/*
1101	* Info & statistics
1102	*/
1103	DBGFR3InfoRegisterInternal(pVM, "mode",
1104	"Shows the current paging mode. "
1105	"Recognizes 'all', 'guest', 'shadow' and 'host' as arguments, defaulting to 'all' if nothing's given.",
1106	pgmR3InfoMode);
1107	DBGFR3InfoRegisterInternal(pVM, "pgmcr3",
1108	"Dumps all the entries in the top level paging table. No arguments.",
1109	pgmR3InfoCr3);
1110	DBGFR3InfoRegisterInternal(pVM, "phys",
1111	"Dumps all the physical address ranges. No arguments.",
1112	pgmR3PhysInfo);
1113	DBGFR3InfoRegisterInternal(pVM, "handlers",
1114	"Dumps physical, virtual and hyper virtual handlers. "
1115	"Pass 'phys', 'virt', 'hyper' as argument if only one kind is wanted."
1116	"Add 'nost' if the statistics are unwanted, use together with 'all' or explicit selection.",
1117	pgmR3InfoHandlers);
1118	DBGFR3InfoRegisterInternal(pVM, "mappings",
1119	"Dumps guest mappings.",
1120	pgmR3MapInfo);
1121
1122	STAM_REL_REG(pVM, &pVM->pgm.s.cGuestModeChanges, STAMTYPE_COUNTER, "/PGM/cGuestModeChanges", STAMUNIT_OCCURENCES, "Number of guest mode changes.");
1123	#ifdef VBOX_WITH_STATISTICS
1124	pgmR3InitStats(pVM);
1125	#endif
1126	#ifdef VBOX_WITH_DEBUGGER
1127	/*
1128	* Debugger commands.
1129	*/
1130	static bool fRegisteredCmds = false;
1131	if (!fRegisteredCmds)
1132	{
1133	int rc = DBGCRegisterCommands(&g_aCmds[0], ELEMENTS(g_aCmds));
1134	if (VBOX_SUCCESS(rc))
1135	fRegisteredCmds = true;
1136	}
1137	#endif
1138	return VINF_SUCCESS;
1139	}
1140
1141	/* Almost no cleanup necessary, MM frees all memory. */
1142	PDMR3CritSectDelete(&pVM->pgm.s.CritSect);
1143
1144	return rc;
1145	}
1146
1147
1148	/**
1149	* Init paging.
1150	*
1151	* Since we need to check what mode the host is operating in before we can choose
1152	* the right paging functions for the host we have to delay this until R0 has
1153	* been initialized.
1154	*
1155	* @returns VBox status code.
1156	* @param pVM VM handle.
1157	*/
1158	static int pgmR3InitPaging(PVM pVM)
1159	{
1160	/*
1161	* Force a recalculation of modes and switcher so everyone gets notified.
1162	*/
1163	pVM->pgm.s.enmShadowMode = PGMMODE_INVALID;
1164	pVM->pgm.s.enmGuestMode = PGMMODE_INVALID;
1165	pVM->pgm.s.enmHostMode = SUPPAGINGMODE_INVALID;
1166
1167	/*
1168	* Allocate static mapping space for whatever the cr3 register
1169	* points to and in the case of PAE mode to the 4 PDs.
1170	*/
1171	int rc = MMR3HyperReserve(pVM, PAGE_SIZE * 5, "CR3 mapping", &pVM->pgm.s.GCPtrCR3Mapping);
1172	if (VBOX_FAILURE(rc))
1173	{
1174	AssertMsgFailed(("Failed to reserve two pages for cr mapping in HMA, rc=%Vrc\n", rc));
1175	return rc;
1176	}
1177	MMR3HyperReserve(pVM, PAGE_SIZE, "fence", NULL);
1178
1179	/*
1180	* Allocate pages for the three possible intermediate contexts
1181	* (AMD64, PAE and plain 32-Bit). We maintain all three contexts
1182	* for the sake of simplicity. The AMD64 uses the PAE for the
1183	* lower levels, making the total number of pages 11 (3 + 7 + 1).
1184	*
1185	* We assume that two page tables will be enought for the core code
1186	* mappings (HC virtual and identity).
1187	*/
1188	pVM->pgm.s.pInterPD = (PX86PD)MMR3PageAllocLow(pVM);
1189	pVM->pgm.s.apInterPTs[0] = (PX86PT)MMR3PageAllocLow(pVM);
1190	pVM->pgm.s.apInterPTs[1] = (PX86PT)MMR3PageAllocLow(pVM);
1191	pVM->pgm.s.apInterPaePTs[0] = (PX86PTPAE)MMR3PageAlloc(pVM);
1192	pVM->pgm.s.apInterPaePTs[1] = (PX86PTPAE)MMR3PageAlloc(pVM);
1193	pVM->pgm.s.apInterPaePDs[0] = (PX86PDPAE)MMR3PageAlloc(pVM);
1194	pVM->pgm.s.apInterPaePDs[1] = (PX86PDPAE)MMR3PageAlloc(pVM);
1195	pVM->pgm.s.apInterPaePDs[2] = (PX86PDPAE)MMR3PageAlloc(pVM);
1196	pVM->pgm.s.apInterPaePDs[3] = (PX86PDPAE)MMR3PageAlloc(pVM);
1197	pVM->pgm.s.pInterPaePDPT = (PX86PDPT)MMR3PageAllocLow(pVM);
1198	pVM->pgm.s.pInterPaePDPT64 = (PX86PDPT)MMR3PageAllocLow(pVM);
1199	pVM->pgm.s.pInterPaePML4 = (PX86PML4)MMR3PageAllocLow(pVM);
1200	if ( !pVM->pgm.s.pInterPD
1201	\|\| !pVM->pgm.s.apInterPTs[0]
1202	\|\| !pVM->pgm.s.apInterPTs[1]
1203	\|\| !pVM->pgm.s.apInterPaePTs[0]
1204	\|\| !pVM->pgm.s.apInterPaePTs[1]
1205	\|\| !pVM->pgm.s.apInterPaePDs[0]
1206	\|\| !pVM->pgm.s.apInterPaePDs[1]
1207	\|\| !pVM->pgm.s.apInterPaePDs[2]
1208	\|\| !pVM->pgm.s.apInterPaePDs[3]
1209	\|\| !pVM->pgm.s.pInterPaePDPT
1210	\|\| !pVM->pgm.s.pInterPaePDPT64
1211	\|\| !pVM->pgm.s.pInterPaePML4)
1212	{
1213	AssertMsgFailed(("Failed to allocate pages for the intermediate context!\n"));
1214	return VERR_NO_PAGE_MEMORY;
1215	}
1216
1217	pVM->pgm.s.HCPhysInterPD = MMPage2Phys(pVM, pVM->pgm.s.pInterPD);
1218	AssertRelease(pVM->pgm.s.HCPhysInterPD != NIL_RTHCPHYS && !(pVM->pgm.s.HCPhysInterPD & PAGE_OFFSET_MASK));
1219	pVM->pgm.s.HCPhysInterPaePDPT = MMPage2Phys(pVM, pVM->pgm.s.pInterPaePDPT);
1220	AssertRelease(pVM->pgm.s.HCPhysInterPaePDPT != NIL_RTHCPHYS && !(pVM->pgm.s.HCPhysInterPaePDPT & PAGE_OFFSET_MASK));
1221	pVM->pgm.s.HCPhysInterPaePML4 = MMPage2Phys(pVM, pVM->pgm.s.pInterPaePML4);
1222	AssertRelease(pVM->pgm.s.HCPhysInterPaePML4 != NIL_RTHCPHYS && !(pVM->pgm.s.HCPhysInterPaePML4 & PAGE_OFFSET_MASK));
1223
1224	/*
1225	* Initialize the pages, setting up the PML4 and PDPT for repetitive 4GB action.
1226	*/
1227	ASMMemZeroPage(pVM->pgm.s.pInterPD);
1228	ASMMemZeroPage(pVM->pgm.s.apInterPTs[0]);
1229	ASMMemZeroPage(pVM->pgm.s.apInterPTs[1]);
1230
1231	ASMMemZeroPage(pVM->pgm.s.apInterPaePTs[0]);
1232	ASMMemZeroPage(pVM->pgm.s.apInterPaePTs[1]);
1233
1234	ASMMemZeroPage(pVM->pgm.s.pInterPaePDPT);
1235	for (unsigned i = 0; i < ELEMENTS(pVM->pgm.s.apInterPaePDs); i++)
1236	{
1237	ASMMemZeroPage(pVM->pgm.s.apInterPaePDs[i]);
1238	pVM->pgm.s.pInterPaePDPT->a[i].u = X86_PDPE_P \| PGM_PLXFLAGS_PERMANENT
1239	\| MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[i]);
1240	}
1241
1242	for (unsigned i = 0; i < ELEMENTS(pVM->pgm.s.pInterPaePDPT64->a); i++)
1243	{
1244	const unsigned iPD = i % ELEMENTS(pVM->pgm.s.apInterPaePDs);
1245	pVM->pgm.s.pInterPaePDPT64->a[i].u = X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_A \| PGM_PLXFLAGS_PERMANENT
1246	\| MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[iPD]);
1247	}
1248
1249	RTHCPHYS HCPhysInterPaePDPT64 = MMPage2Phys(pVM, pVM->pgm.s.pInterPaePDPT64);
1250	for (unsigned i = 0; i < ELEMENTS(pVM->pgm.s.pInterPaePML4->a); i++)
1251	pVM->pgm.s.pInterPaePML4->a[i].u = X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_A \| PGM_PLXFLAGS_PERMANENT
1252	\| HCPhysInterPaePDPT64;
1253
1254	/*
1255	* Allocate pages for the three possible guest contexts (AMD64, PAE and plain 32-Bit).
1256	* We allocate pages for all three posibilities to in order to simplify mappings and
1257	* avoid resource failure during mode switches. So, we need to cover all levels of the
1258	* of the first 4GB down to PD level.
1259	* As with the intermediate context, AMD64 uses the PAE PDPT and PDs.
1260	*/
1261	pVM->pgm.s.pHC32BitPD = (PX86PD)MMR3PageAllocLow(pVM);
1262	pVM->pgm.s.apHCPaePDs[0] = (PX86PDPAE)MMR3PageAlloc(pVM);
1263	pVM->pgm.s.apHCPaePDs[1] = (PX86PDPAE)MMR3PageAlloc(pVM);
1264	AssertRelease((uintptr_t)pVM->pgm.s.apHCPaePDs[0] + PAGE_SIZE == (uintptr_t)pVM->pgm.s.apHCPaePDs[1]);
1265	pVM->pgm.s.apHCPaePDs[2] = (PX86PDPAE)MMR3PageAlloc(pVM);
1266	AssertRelease((uintptr_t)pVM->pgm.s.apHCPaePDs[1] + PAGE_SIZE == (uintptr_t)pVM->pgm.s.apHCPaePDs[2]);
1267	pVM->pgm.s.apHCPaePDs[3] = (PX86PDPAE)MMR3PageAlloc(pVM);
1268	AssertRelease((uintptr_t)pVM->pgm.s.apHCPaePDs[2] + PAGE_SIZE == (uintptr_t)pVM->pgm.s.apHCPaePDs[3]);
1269	pVM->pgm.s.pHCPaePDPT = (PX86PDPT)MMR3PageAllocLow(pVM);
1270	pVM->pgm.s.pHCNestedRoot = MMR3PageAllocLow(pVM);
1271
1272	if ( !pVM->pgm.s.pHC32BitPD
1273	\|\| !pVM->pgm.s.apHCPaePDs[0]
1274	\|\| !pVM->pgm.s.apHCPaePDs[1]
1275	\|\| !pVM->pgm.s.apHCPaePDs[2]
1276	\|\| !pVM->pgm.s.apHCPaePDs[3]
1277	\|\| !pVM->pgm.s.pHCPaePDPT
1278	\|\| !pVM->pgm.s.pHCNestedRoot)
1279	{
1280	AssertMsgFailed(("Failed to allocate pages for the intermediate context!\n"));
1281	return VERR_NO_PAGE_MEMORY;
1282	}
1283
1284	/* get physical addresses. */
1285	pVM->pgm.s.HCPhys32BitPD = MMPage2Phys(pVM, pVM->pgm.s.pHC32BitPD);
1286	Assert(MMPagePhys2Page(pVM, pVM->pgm.s.HCPhys32BitPD) == pVM->pgm.s.pHC32BitPD);
1287	pVM->pgm.s.aHCPhysPaePDs[0] = MMPage2Phys(pVM, pVM->pgm.s.apHCPaePDs[0]);
1288	pVM->pgm.s.aHCPhysPaePDs[1] = MMPage2Phys(pVM, pVM->pgm.s.apHCPaePDs[1]);
1289	pVM->pgm.s.aHCPhysPaePDs[2] = MMPage2Phys(pVM, pVM->pgm.s.apHCPaePDs[2]);
1290	pVM->pgm.s.aHCPhysPaePDs[3] = MMPage2Phys(pVM, pVM->pgm.s.apHCPaePDs[3]);
1291	pVM->pgm.s.HCPhysPaePDPT = MMPage2Phys(pVM, pVM->pgm.s.pHCPaePDPT);
1292	pVM->pgm.s.HCPhysNestedRoot = MMPage2Phys(pVM, pVM->pgm.s.pHCNestedRoot);
1293
1294	/*
1295	* Initialize the pages, setting up the PML4 and PDPT for action below 4GB.
1296	*/
1297	ASMMemZero32(pVM->pgm.s.pHC32BitPD, PAGE_SIZE);
1298	ASMMemZero32(pVM->pgm.s.pHCPaePDPT, PAGE_SIZE);
1299	ASMMemZero32(pVM->pgm.s.pHCNestedRoot, PAGE_SIZE);
1300	for (unsigned i = 0; i < ELEMENTS(pVM->pgm.s.apHCPaePDs); i++)
1301	{
1302	ASMMemZero32(pVM->pgm.s.apHCPaePDs[i], PAGE_SIZE);
1303	pVM->pgm.s.pHCPaePDPT->a[i].u = X86_PDPE_P \| PGM_PLXFLAGS_PERMANENT \| pVM->pgm.s.aHCPhysPaePDs[i];
1304	/* The flags will be corrected when entering and leaving long mode. */
1305	}
1306
1307	CPUMSetHyperCR3(pVM, (uint32_t)pVM->pgm.s.HCPhys32BitPD);
1308
1309	/*
1310	* Initialize paging workers and mode from current host mode
1311	* and the guest running in real mode.
1312	*/
1313	pVM->pgm.s.enmHostMode = SUPGetPagingMode();
1314	switch (pVM->pgm.s.enmHostMode)
1315	{
1316	case SUPPAGINGMODE_32_BIT:
1317	case SUPPAGINGMODE_32_BIT_GLOBAL:
1318	case SUPPAGINGMODE_PAE:
1319	case SUPPAGINGMODE_PAE_GLOBAL:
1320	case SUPPAGINGMODE_PAE_NX:
1321	case SUPPAGINGMODE_PAE_GLOBAL_NX:
1322	break;
1323
1324	case SUPPAGINGMODE_AMD64:
1325	case SUPPAGINGMODE_AMD64_GLOBAL:
1326	case SUPPAGINGMODE_AMD64_NX:
1327	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
1328	#ifndef VBOX_WITH_HYBIRD_32BIT_KERNEL
1329	if (ARCH_BITS != 64)
1330	{
1331	AssertMsgFailed(("Host mode %d (64-bit) is not supported by non-64bit builds\n", pVM->pgm.s.enmHostMode));
1332	LogRel(("Host mode %d (64-bit) is not supported by non-64bit builds\n", pVM->pgm.s.enmHostMode));
1333	return VERR_PGM_UNSUPPORTED_HOST_PAGING_MODE;
1334	}
1335	#endif
1336	break;
1337	default:
1338	AssertMsgFailed(("Host mode %d is not supported\n", pVM->pgm.s.enmHostMode));
1339	return VERR_PGM_UNSUPPORTED_HOST_PAGING_MODE;
1340	}
1341	rc = pgmR3ModeDataInit(pVM, false /* don't resolve GC and R0 syms yet */);
1342	if (VBOX_SUCCESS(rc))
1343	rc = PGMR3ChangeMode(pVM, PGMMODE_REAL);
1344	if (VBOX_SUCCESS(rc))
1345	{
1346	LogFlow(("pgmR3InitPaging: returns successfully\n"));
1347	#if HC_ARCH_BITS == 64
1348	LogRel(("Debug: HCPhys32BitPD=%VHp aHCPhysPaePDs={%VHp,%VHp,%VHp,%VHp} HCPhysPaePDPT=%VHp HCPhysPaePML4=%VHp\n",
1349	pVM->pgm.s.HCPhys32BitPD, pVM->pgm.s.aHCPhysPaePDs[0], pVM->pgm.s.aHCPhysPaePDs[1], pVM->pgm.s.aHCPhysPaePDs[2], pVM->pgm.s.aHCPhysPaePDs[3],
1350	pVM->pgm.s.HCPhysPaePDPT, pVM->pgm.s.HCPhysPaePML4));
1351	LogRel(("Debug: HCPhysInterPD=%VHp HCPhysInterPaePDPT=%VHp HCPhysInterPaePML4=%VHp\n",
1352	pVM->pgm.s.HCPhysInterPD, pVM->pgm.s.HCPhysInterPaePDPT, pVM->pgm.s.HCPhysInterPaePML4));
1353	LogRel(("Debug: apInterPTs={%VHp,%VHp} apInterPaePTs={%VHp,%VHp} apInterPaePDs={%VHp,%VHp,%VHp,%VHp} pInterPaePDPT64=%VHp\n",
1354	MMPage2Phys(pVM, pVM->pgm.s.apInterPTs[0]), MMPage2Phys(pVM, pVM->pgm.s.apInterPTs[1]),
1355	MMPage2Phys(pVM, pVM->pgm.s.apInterPaePTs[0]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePTs[1]),
1356	MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[0]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[1]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[2]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[3]),
1357	MMPage2Phys(pVM, pVM->pgm.s.pInterPaePDPT64)));
1358	#endif
1359
1360	return VINF_SUCCESS;
1361	}
1362
1363	LogFlow(("pgmR3InitPaging: returns %Vrc\n", rc));
1364	return rc;
1365	}
1366
1367
1368	#ifdef VBOX_WITH_STATISTICS
1369	/**
1370	* Init statistics
1371	*/
1372	static void pgmR3InitStats(PVM pVM)
1373	{
1374	PPGM pPGM = &pVM->pgm.s;
1375	STAM_REG(pVM, &pPGM->StatGCInvalidatePage, STAMTYPE_PROFILE, "/PGM/GC/InvalidatePage", STAMUNIT_TICKS_PER_CALL, "PGMGCInvalidatePage() profiling.");
1376	STAM_REG(pVM, &pPGM->StatGCInvalidatePage4KBPages, STAMTYPE_COUNTER, "/PGM/GC/InvalidatePage/4KBPages", STAMUNIT_OCCURENCES, "The number of times PGMGCInvalidatePage() was called for a 4KB page.");
1377	STAM_REG(pVM, &pPGM->StatGCInvalidatePage4MBPages, STAMTYPE_COUNTER, "/PGM/GC/InvalidatePage/4MBPages", STAMUNIT_OCCURENCES, "The number of times PGMGCInvalidatePage() was called for a 4MB page.");
1378	STAM_REG(pVM, &pPGM->StatGCInvalidatePage4MBPagesSkip, STAMTYPE_COUNTER, "/PGM/GC/InvalidatePage/4MBPagesSkip",STAMUNIT_OCCURENCES, "The number of times PGMGCInvalidatePage() skipped a 4MB page.");
1379	STAM_REG(pVM, &pPGM->StatGCInvalidatePagePDMappings, STAMTYPE_COUNTER, "/PGM/GC/InvalidatePage/PDMappings", STAMUNIT_OCCURENCES, "The number of times PGMGCInvalidatePage() was called for a page directory containing mappings (no conflict).");
1380	STAM_REG(pVM, &pPGM->StatGCInvalidatePagePDNAs, STAMTYPE_COUNTER, "/PGM/GC/InvalidatePage/PDNAs", STAMUNIT_OCCURENCES, "The number of times PGMGCInvalidatePage() was called for a not accessed page directory.");
1381	STAM_REG(pVM, &pPGM->StatGCInvalidatePagePDNPs, STAMTYPE_COUNTER, "/PGM/GC/InvalidatePage/PDNPs", STAMUNIT_OCCURENCES, "The number of times PGMGCInvalidatePage() was called for a not present page directory.");
1382	STAM_REG(pVM, &pPGM->StatGCInvalidatePagePDOutOfSync, STAMTYPE_COUNTER, "/PGM/GC/InvalidatePage/PDOutOfSync", STAMUNIT_OCCURENCES, "The number of times PGMGCInvalidatePage() was called for an out of sync page directory.");
1383	STAM_REG(pVM, &pPGM->StatGCInvalidatePageSkipped, STAMTYPE_COUNTER, "/PGM/GC/InvalidatePage/Skipped", STAMUNIT_OCCURENCES, "The number of times PGMGCInvalidatePage() was skipped due to not present shw or pending pending SyncCR3.");
1384	STAM_REG(pVM, &pPGM->StatGCSyncPT, STAMTYPE_PROFILE, "/PGM/GC/SyncPT", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMGCSyncPT() body.");
1385	STAM_REG(pVM, &pPGM->StatGCAccessedPage, STAMTYPE_COUNTER, "/PGM/GC/AccessedPage", STAMUNIT_OCCURENCES, "The number of pages marked not present for accessed bit emulation.");
1386	STAM_REG(pVM, &pPGM->StatGCDirtyPage, STAMTYPE_COUNTER, "/PGM/GC/DirtyPage/Mark", STAMUNIT_OCCURENCES, "The number of pages marked read-only for dirty bit tracking.");
1387	STAM_REG(pVM, &pPGM->StatGCDirtyPageBig, STAMTYPE_COUNTER, "/PGM/GC/DirtyPage/MarkBig", STAMUNIT_OCCURENCES, "The number of 4MB pages marked read-only for dirty bit tracking.");
1388	STAM_REG(pVM, &pPGM->StatGCDirtyPageTrap, STAMTYPE_COUNTER, "/PGM/GC/DirtyPage/Trap", STAMUNIT_OCCURENCES, "The number of traps generated for dirty bit tracking.");
1389	STAM_REG(pVM, &pPGM->StatGCDirtyPageSkipped, STAMTYPE_COUNTER, "/PGM/GC/DirtyPage/Skipped", STAMUNIT_OCCURENCES, "The number of pages already dirty or readonly.");
1390	STAM_REG(pVM, &pPGM->StatGCDirtiedPage, STAMTYPE_COUNTER, "/PGM/GC/DirtyPage/SetDirty", STAMUNIT_OCCURENCES, "The number of pages marked dirty because of write accesses.");
1391	STAM_REG(pVM, &pPGM->StatGCDirtyTrackRealPF, STAMTYPE_COUNTER, "/PGM/GC/DirtyPage/RealPF", STAMUNIT_OCCURENCES, "The number of real pages faults during dirty bit tracking.");
1392	STAM_REG(pVM, &pPGM->StatGCPageAlreadyDirty, STAMTYPE_COUNTER, "/PGM/GC/DirtyPage/AlreadySet", STAMUNIT_OCCURENCES, "The number of pages already marked dirty because of write accesses.");
1393	STAM_REG(pVM, &pPGM->StatGCDirtyBitTracking, STAMTYPE_PROFILE, "/PGM/GC/DirtyPage", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMTrackDirtyBit() body.");
1394	STAM_REG(pVM, &pPGM->StatGCSyncPTAlloc, STAMTYPE_COUNTER, "/PGM/GC/SyncPT/Alloc", STAMUNIT_OCCURENCES, "The number of times PGMGCSyncPT() needed to allocate page tables.");
1395	STAM_REG(pVM, &pPGM->StatGCSyncPTConflict, STAMTYPE_COUNTER, "/PGM/GC/SyncPT/Conflicts", STAMUNIT_OCCURENCES, "The number of times PGMGCSyncPT() detected conflicts.");
1396	STAM_REG(pVM, &pPGM->StatGCSyncPTFailed, STAMTYPE_COUNTER, "/PGM/GC/SyncPT/Failed", STAMUNIT_OCCURENCES, "The number of times PGMGCSyncPT() failed.");
1397
1398	STAM_REG(pVM, &pPGM->StatGCTrap0e, STAMTYPE_PROFILE, "/PGM/GC/Trap0e", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMGCTrap0eHandler() body.");
1399	STAM_REG(pVM, &pPGM->StatCheckPageFault, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time/CheckPageFault", STAMUNIT_TICKS_PER_CALL, "Profiling of checking for dirty/access emulation faults.");
1400	STAM_REG(pVM, &pPGM->StatLazySyncPT, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time/SyncPT", STAMUNIT_TICKS_PER_CALL, "Profiling of lazy page table syncing.");
1401	STAM_REG(pVM, &pPGM->StatMapping, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time/Mapping", STAMUNIT_TICKS_PER_CALL, "Profiling of checking virtual mappings.");
1402	STAM_REG(pVM, &pPGM->StatOutOfSync, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time/OutOfSync", STAMUNIT_TICKS_PER_CALL, "Profiling of out of sync page handling.");
1403	STAM_REG(pVM, &pPGM->StatHandlers, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time/Handlers", STAMUNIT_TICKS_PER_CALL, "Profiling of checking handlers.");
1404	STAM_REG(pVM, &pPGM->StatEIPHandlers, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time/EIPHandlers", STAMUNIT_TICKS_PER_CALL, "Profiling of checking eip handlers.");
1405	STAM_REG(pVM, &pPGM->StatTrap0eCSAM, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time2/CSAM", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is CSAM.");
1406	STAM_REG(pVM, &pPGM->StatTrap0eDirtyAndAccessedBits, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time2/DirtyAndAccessedBits", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is dirty and/or accessed bit emulation.");
1407	STAM_REG(pVM, &pPGM->StatTrap0eGuestTrap, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time2/GuestTrap", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is a guest trap.");
1408	STAM_REG(pVM, &pPGM->StatTrap0eHndPhys, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time2/HandlerPhysical", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is a physical handler.");
1409	STAM_REG(pVM, &pPGM->StatTrap0eHndVirt, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time2/HandlerVirtual",STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is a virtual handler.");
1410	STAM_REG(pVM, &pPGM->StatTrap0eHndUnhandled, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time2/HandlerUnhandled", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is access outside the monitored areas of a monitored page.");
1411	STAM_REG(pVM, &pPGM->StatTrap0eMisc, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time2/Misc", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is not known.");
1412	STAM_REG(pVM, &pPGM->StatTrap0eOutOfSync, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time2/OutOfSync", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is an out-of-sync page.");
1413	STAM_REG(pVM, &pPGM->StatTrap0eOutOfSyncHndPhys, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time2/OutOfSyncHndPhys", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is an out-of-sync physical handler page.");
1414	STAM_REG(pVM, &pPGM->StatTrap0eOutOfSyncHndVirt, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time2/OutOfSyncHndVirt", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is an out-of-sync virtual handler page.");
1415	STAM_REG(pVM, &pPGM->StatTrap0eOutOfSyncObsHnd, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time2/OutOfSyncObsHnd", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is an obsolete handler page.");
1416	STAM_REG(pVM, &pPGM->StatTrap0eSyncPT, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time2/SyncPT", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is lazy syncing of a PT.");
1417
1418	STAM_REG(pVM, &pPGM->StatTrap0eMapHandler, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/Handlers/Mapping", STAMUNIT_OCCURENCES, "Number of traps due to access handlers in mappings.");
1419	STAM_REG(pVM, &pPGM->StatHandlersOutOfSync, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/Handlers/OutOfSync", STAMUNIT_OCCURENCES, "Number of traps due to out-of-sync handled pages.");
1420	STAM_REG(pVM, &pPGM->StatHandlersPhysical, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/Handlers/Physical", STAMUNIT_OCCURENCES, "Number of traps due to physical access handlers.");
1421	STAM_REG(pVM, &pPGM->StatHandlersVirtual, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/Handlers/Virtual", STAMUNIT_OCCURENCES, "Number of traps due to virtual access handlers.");
1422	STAM_REG(pVM, &pPGM->StatHandlersVirtualByPhys, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/Handlers/VirtualByPhys", STAMUNIT_OCCURENCES, "Number of traps due to virtual access handlers by physical address.");
1423	STAM_REG(pVM, &pPGM->StatHandlersVirtualUnmarked, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/Handlers/VirtualUnmarked", STAMUNIT_OCCURENCES,"Number of traps due to virtual access handlers by virtual address (without proper physical flags).");
1424	STAM_REG(pVM, &pPGM->StatHandlersUnhandled, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/Handlers/Unhandled", STAMUNIT_OCCURENCES, "Number of traps due to access outside range of monitored page(s).");
1425	STAM_REG(pVM, &pPGM->StatHandlersInvalid, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/Handlers/Invalid", STAMUNIT_OCCURENCES, "Number of traps due to access to invalid physical memory.");
1426
1427	STAM_REG(pVM, &pPGM->StatGCTrap0eConflicts, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/Conflicts", STAMUNIT_OCCURENCES, "The number of times #PF was caused by an undetected conflict.");
1428	STAM_REG(pVM, &pPGM->StatGCTrap0eUSNotPresentRead, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/User/NPRead", STAMUNIT_OCCURENCES, "Number of user mode not present read page faults.");
1429	STAM_REG(pVM, &pPGM->StatGCTrap0eUSNotPresentWrite, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/User/NPWrite", STAMUNIT_OCCURENCES, "Number of user mode not present write page faults.");
1430	STAM_REG(pVM, &pPGM->StatGCTrap0eUSWrite, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/User/Write", STAMUNIT_OCCURENCES, "Number of user mode write page faults.");
1431	STAM_REG(pVM, &pPGM->StatGCTrap0eUSReserved, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/User/Reserved", STAMUNIT_OCCURENCES, "Number of user mode reserved bit page faults.");
1432	STAM_REG(pVM, &pPGM->StatGCTrap0eUSNXE, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/User/NXE", STAMUNIT_OCCURENCES, "Number of user mode NXE page faults.");
1433	STAM_REG(pVM, &pPGM->StatGCTrap0eUSRead, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/User/Read", STAMUNIT_OCCURENCES, "Number of user mode read page faults.");
1434
1435	STAM_REG(pVM, &pPGM->StatGCTrap0eSVNotPresentRead, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/Supervisor/NPRead", STAMUNIT_OCCURENCES, "Number of supervisor mode not present read page faults.");
1436	STAM_REG(pVM, &pPGM->StatGCTrap0eSVNotPresentWrite, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/Supervisor/NPWrite", STAMUNIT_OCCURENCES, "Number of supervisor mode not present write page faults.");
1437	STAM_REG(pVM, &pPGM->StatGCTrap0eSVWrite, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/Supervisor/Write", STAMUNIT_OCCURENCES, "Number of supervisor mode write page faults.");
1438	STAM_REG(pVM, &pPGM->StatGCTrap0eSVReserved, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/Supervisor/Reserved", STAMUNIT_OCCURENCES, "Number of supervisor mode reserved bit page faults.");
1439	STAM_REG(pVM, &pPGM->StatGCTrap0eSNXE, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/Supervisor/NXE", STAMUNIT_OCCURENCES, "Number of supervisor mode NXE page faults.");
1440	STAM_REG(pVM, &pPGM->StatGCTrap0eUnhandled, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/GuestPF/Unhandled", STAMUNIT_OCCURENCES, "Number of guest real page faults.");
1441	STAM_REG(pVM, &pPGM->StatGCTrap0eMap, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/GuestPF/Map", STAMUNIT_OCCURENCES, "Number of guest page faults due to map accesses.");
1442
1443	STAM_REG(pVM, &pPGM->StatTrap0eWPEmulGC, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/WP/InGC", STAMUNIT_OCCURENCES, "Number of guest page faults due to X86_CR0_WP emulation.");
1444	STAM_REG(pVM, &pPGM->StatTrap0eWPEmulR3, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/WP/ToR3", STAMUNIT_OCCURENCES, "Number of guest page faults due to X86_CR0_WP emulation (forward to R3 for emulation).");
1445
1446	STAM_REG(pVM, &pPGM->StatGCGuestCR3WriteHandled, STAMTYPE_COUNTER, "/PGM/GC/CR3WriteInt", STAMUNIT_OCCURENCES, "The number of times the Guest CR3 change was successfully handled.");
1447	STAM_REG(pVM, &pPGM->StatGCGuestCR3WriteUnhandled, STAMTYPE_COUNTER, "/PGM/GC/CR3WriteEmu", STAMUNIT_OCCURENCES, "The number of times the Guest CR3 change was passed back to the recompiler.");
1448	STAM_REG(pVM, &pPGM->StatGCGuestCR3WriteConflict, STAMTYPE_COUNTER, "/PGM/GC/CR3WriteConflict", STAMUNIT_OCCURENCES, "The number of times the Guest CR3 monitoring detected a conflict.");
1449
1450	STAM_REG(pVM, &pPGM->StatGCPageOutOfSyncSupervisor, STAMTYPE_COUNTER, "/PGM/GC/OutOfSync/SuperVisor", STAMUNIT_OCCURENCES, "Number of traps due to pages out of sync.");
1451	STAM_REG(pVM, &pPGM->StatGCPageOutOfSyncUser, STAMTYPE_COUNTER, "/PGM/GC/OutOfSync/User", STAMUNIT_OCCURENCES, "Number of traps due to pages out of sync.");
1452
1453	STAM_REG(pVM, &pPGM->StatGCGuestROMWriteHandled, STAMTYPE_COUNTER, "/PGM/GC/ROMWriteInt", STAMUNIT_OCCURENCES, "The number of times the Guest ROM change was successfully handled.");
1454	STAM_REG(pVM, &pPGM->StatGCGuestROMWriteUnhandled, STAMTYPE_COUNTER, "/PGM/GC/ROMWriteEmu", STAMUNIT_OCCURENCES, "The number of times the Guest ROM change was passed back to the recompiler.");
1455
1456	STAM_REG(pVM, &pPGM->StatDynMapCacheHits, STAMTYPE_COUNTER, "/PGM/GC/DynMapCache/Hits" , STAMUNIT_OCCURENCES, "Number of dynamic page mapping cache hits.");
1457	STAM_REG(pVM, &pPGM->StatDynMapCacheMisses, STAMTYPE_COUNTER, "/PGM/GC/DynMapCache/Misses" , STAMUNIT_OCCURENCES, "Number of dynamic page mapping cache misses.");
1458
1459	STAM_REG(pVM, &pPGM->StatHCDetectedConflicts, STAMTYPE_COUNTER, "/PGM/HC/DetectedConflicts", STAMUNIT_OCCURENCES, "The number of times PGMR3CheckMappingConflicts() detected a conflict.");
1460	STAM_REG(pVM, &pPGM->StatHCGuestPDWrite, STAMTYPE_COUNTER, "/PGM/HC/PDWrite", STAMUNIT_OCCURENCES, "The total number of times pgmHCGuestPDWriteHandler() was called.");
1461	STAM_REG(pVM, &pPGM->StatHCGuestPDWriteConflict, STAMTYPE_COUNTER, "/PGM/HC/PDWriteConflict", STAMUNIT_OCCURENCES, "The number of times pgmHCGuestPDWriteHandler() detected a conflict.");
1462
1463	STAM_REG(pVM, &pPGM->StatHCInvalidatePage, STAMTYPE_PROFILE, "/PGM/HC/InvalidatePage", STAMUNIT_TICKS_PER_CALL, "PGMHCInvalidatePage() profiling.");
1464	STAM_REG(pVM, &pPGM->StatHCInvalidatePage4KBPages, STAMTYPE_COUNTER, "/PGM/HC/InvalidatePage/4KBPages", STAMUNIT_OCCURENCES, "The number of times PGMHCInvalidatePage() was called for a 4KB page.");
1465	STAM_REG(pVM, &pPGM->StatHCInvalidatePage4MBPages, STAMTYPE_COUNTER, "/PGM/HC/InvalidatePage/4MBPages", STAMUNIT_OCCURENCES, "The number of times PGMHCInvalidatePage() was called for a 4MB page.");
1466	STAM_REG(pVM, &pPGM->StatHCInvalidatePage4MBPagesSkip, STAMTYPE_COUNTER, "/PGM/HC/InvalidatePage/4MBPagesSkip",STAMUNIT_OCCURENCES, "The number of times PGMHCInvalidatePage() skipped a 4MB page.");
1467	STAM_REG(pVM, &pPGM->StatHCInvalidatePagePDMappings, STAMTYPE_COUNTER, "/PGM/HC/InvalidatePage/PDMappings", STAMUNIT_OCCURENCES, "The number of times PGMHCInvalidatePage() was called for a page directory containing mappings (no conflict).");
1468	STAM_REG(pVM, &pPGM->StatHCInvalidatePagePDNAs, STAMTYPE_COUNTER, "/PGM/HC/InvalidatePage/PDNAs", STAMUNIT_OCCURENCES, "The number of times PGMHCInvalidatePage() was called for a not accessed page directory.");
1469	STAM_REG(pVM, &pPGM->StatHCInvalidatePagePDNPs, STAMTYPE_COUNTER, "/PGM/HC/InvalidatePage/PDNPs", STAMUNIT_OCCURENCES, "The number of times PGMHCInvalidatePage() was called for a not present page directory.");
1470	STAM_REG(pVM, &pPGM->StatHCInvalidatePagePDOutOfSync, STAMTYPE_COUNTER, "/PGM/HC/InvalidatePage/PDOutOfSync", STAMUNIT_OCCURENCES, "The number of times PGMGCInvalidatePage() was called for an out of sync page directory.");
1471	STAM_REG(pVM, &pPGM->StatHCInvalidatePageSkipped, STAMTYPE_COUNTER, "/PGM/HC/InvalidatePage/Skipped", STAMUNIT_OCCURENCES, "The number of times PGMHCInvalidatePage() was skipped due to not present shw or pending pending SyncCR3.");
1472	STAM_REG(pVM, &pPGM->StatHCResolveConflict, STAMTYPE_PROFILE, "/PGM/HC/ResolveConflict", STAMUNIT_TICKS_PER_CALL, "pgmR3SyncPTResolveConflict() profiling (includes the entire relocation).");
1473	STAM_REG(pVM, &pPGM->StatHCPrefetch, STAMTYPE_PROFILE, "/PGM/HC/Prefetch", STAMUNIT_TICKS_PER_CALL, "PGMR3PrefetchPage profiling.");
1474
1475	STAM_REG(pVM, &pPGM->StatHCSyncPT, STAMTYPE_PROFILE, "/PGM/HC/SyncPT", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMR3SyncPT() body.");
1476	STAM_REG(pVM, &pPGM->StatHCAccessedPage, STAMTYPE_COUNTER, "/PGM/HC/AccessedPage", STAMUNIT_OCCURENCES, "The number of pages marked not present for accessed bit emulation.");
1477	STAM_REG(pVM, &pPGM->StatHCDirtyPage, STAMTYPE_COUNTER, "/PGM/HC/DirtyPage/Mark", STAMUNIT_OCCURENCES, "The number of pages marked read-only for dirty bit tracking.");
1478	STAM_REG(pVM, &pPGM->StatHCDirtyPageBig, STAMTYPE_COUNTER, "/PGM/HC/DirtyPage/MarkBig", STAMUNIT_OCCURENCES, "The number of 4MB pages marked read-only for dirty bit tracking.");
1479	STAM_REG(pVM, &pPGM->StatHCDirtyPageTrap, STAMTYPE_COUNTER, "/PGM/HC/DirtyPage/Trap", STAMUNIT_OCCURENCES, "The number of traps generated for dirty bit tracking.");
1480	STAM_REG(pVM, &pPGM->StatHCDirtyPageSkipped, STAMTYPE_COUNTER, "/PGM/HC/DirtyPage/Skipped", STAMUNIT_OCCURENCES, "The number of pages already dirty or readonly.");
1481	STAM_REG(pVM, &pPGM->StatHCDirtyBitTracking, STAMTYPE_PROFILE, "/PGM/HC/DirtyPage", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMTrackDirtyBit() body.");
1482
1483	STAM_REG(pVM, &pPGM->StatGCSyncPagePDNAs, STAMTYPE_COUNTER, "/PGM/GC/SyncPagePDNAs", STAMUNIT_OCCURENCES, "The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit.");
1484	STAM_REG(pVM, &pPGM->StatGCSyncPagePDOutOfSync, STAMTYPE_COUNTER, "/PGM/GC/SyncPagePDOutOfSync", STAMUNIT_OCCURENCES, "The number of time we've encountered an out-of-sync PD in SyncPage.");
1485	STAM_REG(pVM, &pPGM->StatHCSyncPagePDNAs, STAMTYPE_COUNTER, "/PGM/HC/SyncPagePDNAs", STAMUNIT_OCCURENCES, "The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit.");
1486	STAM_REG(pVM, &pPGM->StatHCSyncPagePDOutOfSync, STAMTYPE_COUNTER, "/PGM/HC/SyncPagePDOutOfSync", STAMUNIT_OCCURENCES, "The number of time we've encountered an out-of-sync PD in SyncPage.");
1487
1488	STAM_REG(pVM, &pPGM->StatFlushTLB, STAMTYPE_PROFILE, "/PGM/FlushTLB", STAMUNIT_OCCURENCES, "Profiling of the PGMFlushTLB() body.");
1489	STAM_REG(pVM, &pPGM->StatFlushTLBNewCR3, STAMTYPE_COUNTER, "/PGM/FlushTLB/NewCR3", STAMUNIT_OCCURENCES, "The number of times PGMFlushTLB was called with a new CR3, non-global. (switch)");
1490	STAM_REG(pVM, &pPGM->StatFlushTLBNewCR3Global, STAMTYPE_COUNTER, "/PGM/FlushTLB/NewCR3Global", STAMUNIT_OCCURENCES, "The number of times PGMFlushTLB was called with a new CR3, global. (switch)");
1491	STAM_REG(pVM, &pPGM->StatFlushTLBSameCR3, STAMTYPE_COUNTER, "/PGM/FlushTLB/SameCR3", STAMUNIT_OCCURENCES, "The number of times PGMFlushTLB was called with the same CR3, non-global. (flush)");
1492	STAM_REG(pVM, &pPGM->StatFlushTLBSameCR3Global, STAMTYPE_COUNTER, "/PGM/FlushTLB/SameCR3Global", STAMUNIT_OCCURENCES, "The number of times PGMFlushTLB was called with the same CR3, global. (flush)");
1493
1494	STAM_REG(pVM, &pPGM->StatGCSyncCR3, STAMTYPE_PROFILE, "/PGM/GC/SyncCR3", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMSyncCR3() body.");
1495	STAM_REG(pVM, &pPGM->StatGCSyncCR3Handlers, STAMTYPE_PROFILE, "/PGM/GC/SyncCR3/Handlers", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMSyncCR3() update handler section.");
1496	STAM_REG(pVM, &pPGM->StatGCSyncCR3HandlerVirtualUpdate, STAMTYPE_PROFILE, "/PGM/GC/SyncCR3/Handlers/VirtualUpdate",STAMUNIT_TICKS_PER_CALL, "Profiling of the virtual handler updates.");
1497	STAM_REG(pVM, &pPGM->StatGCSyncCR3HandlerVirtualReset, STAMTYPE_PROFILE, "/PGM/GC/SyncCR3/Handlers/VirtualReset", STAMUNIT_TICKS_PER_CALL, "Profiling of the virtual handler resets.");
1498	STAM_REG(pVM, &pPGM->StatGCSyncCR3Global, STAMTYPE_COUNTER, "/PGM/GC/SyncCR3/Global", STAMUNIT_OCCURENCES, "The number of global CR3 syncs.");
1499	STAM_REG(pVM, &pPGM->StatGCSyncCR3NotGlobal, STAMTYPE_COUNTER, "/PGM/GC/SyncCR3/NotGlobal", STAMUNIT_OCCURENCES, "The number of non-global CR3 syncs.");
1500	STAM_REG(pVM, &pPGM->StatGCSyncCR3DstCacheHit, STAMTYPE_COUNTER, "/PGM/GC/SyncCR3/DstChacheHit", STAMUNIT_OCCURENCES, "The number of times we got some kind of a cache hit.");
1501	STAM_REG(pVM, &pPGM->StatGCSyncCR3DstFreed, STAMTYPE_COUNTER, "/PGM/GC/SyncCR3/DstFreed", STAMUNIT_OCCURENCES, "The number of times we've had to free a shadow entry.");
1502	STAM_REG(pVM, &pPGM->StatGCSyncCR3DstFreedSrcNP, STAMTYPE_COUNTER, "/PGM/GC/SyncCR3/DstFreedSrcNP", STAMUNIT_OCCURENCES, "The number of times we've had to free a shadow entry for which the source entry was not present.");
1503	STAM_REG(pVM, &pPGM->StatGCSyncCR3DstNotPresent, STAMTYPE_COUNTER, "/PGM/GC/SyncCR3/DstNotPresent", STAMUNIT_OCCURENCES, "The number of times we've encountered a not present shadow entry for a present guest entry.");
1504	STAM_REG(pVM, &pPGM->StatGCSyncCR3DstSkippedGlobalPD, STAMTYPE_COUNTER, "/PGM/GC/SyncCR3/DstSkippedGlobalPD", STAMUNIT_OCCURENCES, "The number of times a global page directory wasn't flushed.");
1505	STAM_REG(pVM, &pPGM->StatGCSyncCR3DstSkippedGlobalPT, STAMTYPE_COUNTER, "/PGM/GC/SyncCR3/DstSkippedGlobalPT", STAMUNIT_OCCURENCES, "The number of times a page table with only global entries wasn't flushed.");
1506
1507	STAM_REG(pVM, &pPGM->StatHCSyncCR3, STAMTYPE_PROFILE, "/PGM/HC/SyncCR3", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMSyncCR3() body.");
1508	STAM_REG(pVM, &pPGM->StatHCSyncCR3Handlers, STAMTYPE_PROFILE, "/PGM/HC/SyncCR3/Handlers", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMSyncCR3() update handler section.");
1509	STAM_REG(pVM, &pPGM->StatHCSyncCR3HandlerVirtualUpdate, STAMTYPE_PROFILE, "/PGM/HC/SyncCR3/Handlers/VirtualUpdate",STAMUNIT_TICKS_PER_CALL, "Profiling of the virtual handler updates.");
1510	STAM_REG(pVM, &pPGM->StatHCSyncCR3HandlerVirtualReset, STAMTYPE_PROFILE, "/PGM/HC/SyncCR3/Handlers/VirtualReset", STAMUNIT_TICKS_PER_CALL, "Profiling of the virtual handler resets.");
1511	STAM_REG(pVM, &pPGM->StatHCSyncCR3Global, STAMTYPE_COUNTER, "/PGM/HC/SyncCR3/Global", STAMUNIT_OCCURENCES, "The number of global CR3 syncs.");
1512	STAM_REG(pVM, &pPGM->StatHCSyncCR3NotGlobal, STAMTYPE_COUNTER, "/PGM/HC/SyncCR3/NotGlobal", STAMUNIT_OCCURENCES, "The number of non-global CR3 syncs.");
1513	STAM_REG(pVM, &pPGM->StatHCSyncCR3DstCacheHit, STAMTYPE_COUNTER, "/PGM/HC/SyncCR3/DstChacheHit", STAMUNIT_OCCURENCES, "The number of times we got some kind of a cache hit.");
1514	STAM_REG(pVM, &pPGM->StatHCSyncCR3DstFreed, STAMTYPE_COUNTER, "/PGM/HC/SyncCR3/DstFreed", STAMUNIT_OCCURENCES, "The number of times we've had to free a shadow entry.");
1515	STAM_REG(pVM, &pPGM->StatHCSyncCR3DstFreedSrcNP, STAMTYPE_COUNTER, "/PGM/HC/SyncCR3/DstFreedSrcNP", STAMUNIT_OCCURENCES, "The number of times we've had to free a shadow entry for which the source entry was not present.");
1516	STAM_REG(pVM, &pPGM->StatHCSyncCR3DstNotPresent, STAMTYPE_COUNTER, "/PGM/HC/SyncCR3/DstNotPresent", STAMUNIT_OCCURENCES, "The number of times we've encountered a not present shadow entry for a present guest entry.");
1517	STAM_REG(pVM, &pPGM->StatHCSyncCR3DstSkippedGlobalPD, STAMTYPE_COUNTER, "/PGM/HC/SyncCR3/DstSkippedGlobalPD", STAMUNIT_OCCURENCES, "The number of times a global page directory wasn't flushed.");
1518	STAM_REG(pVM, &pPGM->StatHCSyncCR3DstSkippedGlobalPT, STAMTYPE_COUNTER, "/PGM/HC/SyncCR3/DstSkippedGlobalPT", STAMUNIT_OCCURENCES, "The number of times a page table with only global entries wasn't flushed.");
1519
1520	STAM_REG(pVM, &pPGM->StatVirtHandleSearchByPhysGC, STAMTYPE_PROFILE, "/PGM/VirtHandler/SearchByPhys/GC", STAMUNIT_TICKS_PER_CALL, "Profiling of pgmHandlerVirtualFindByPhysAddr in GC.");
1521	STAM_REG(pVM, &pPGM->StatVirtHandleSearchByPhysHC, STAMTYPE_PROFILE, "/PGM/VirtHandler/SearchByPhys/HC", STAMUNIT_TICKS_PER_CALL, "Profiling of pgmHandlerVirtualFindByPhysAddr in HC.");
1522	STAM_REG(pVM, &pPGM->StatHandlePhysicalReset, STAMTYPE_COUNTER, "/PGM/HC/HandlerPhysicalReset", STAMUNIT_OCCURENCES, "The number of times PGMR3HandlerPhysicalReset is called.");
1523
1524	STAM_REG(pVM, &pPGM->StatHCGstModifyPage, STAMTYPE_PROFILE, "/PGM/HC/GstModifyPage", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMGstModifyPage() body.");
1525	STAM_REG(pVM, &pPGM->StatGCGstModifyPage, STAMTYPE_PROFILE, "/PGM/GC/GstModifyPage", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMGstModifyPage() body.");
1526
1527	STAM_REG(pVM, &pPGM->StatSynPT4kGC, STAMTYPE_COUNTER, "/PGM/GC/SyncPT/4k", STAMUNIT_OCCURENCES, "Nr of 4k PT syncs");
1528	STAM_REG(pVM, &pPGM->StatSynPT4kHC, STAMTYPE_COUNTER, "/PGM/HC/SyncPT/4k", STAMUNIT_OCCURENCES, "Nr of 4k PT syncs");
1529	STAM_REG(pVM, &pPGM->StatSynPT4MGC, STAMTYPE_COUNTER, "/PGM/GC/SyncPT/4M", STAMUNIT_OCCURENCES, "Nr of 4M PT syncs");
1530	STAM_REG(pVM, &pPGM->StatSynPT4MHC, STAMTYPE_COUNTER, "/PGM/HC/SyncPT/4M", STAMUNIT_OCCURENCES, "Nr of 4M PT syncs");
1531
1532	STAM_REG(pVM, &pPGM->StatDynRamTotal, STAMTYPE_COUNTER, "/PGM/RAM/TotalAlloc", STAMUNIT_MEGABYTES, "Allocated mbs of guest ram.");
1533	STAM_REG(pVM, &pPGM->StatDynRamGrow, STAMTYPE_COUNTER, "/PGM/RAM/Grow", STAMUNIT_OCCURENCES, "Nr of pgmr3PhysGrowRange calls.");
1534
1535	STAM_REG(pVM, &pPGM->StatPageHCMapTlbHits, STAMTYPE_COUNTER, "/PGM/PageHCMap/TlbHits", STAMUNIT_OCCURENCES, "TLB hits.");
1536	STAM_REG(pVM, &pPGM->StatPageHCMapTlbMisses, STAMTYPE_COUNTER, "/PGM/PageHCMap/TlbMisses", STAMUNIT_OCCURENCES, "TLB misses.");
1537	STAM_REG(pVM, &pPGM->ChunkR3Map.c, STAMTYPE_U32, "/PGM/ChunkR3Map/c", STAMUNIT_OCCURENCES, "Number of mapped chunks.");
1538	STAM_REG(pVM, &pPGM->ChunkR3Map.cMax, STAMTYPE_U32, "/PGM/ChunkR3Map/cMax", STAMUNIT_OCCURENCES, "Maximum number of mapped chunks.");
1539	STAM_REG(pVM, &pPGM->StatChunkR3MapTlbHits, STAMTYPE_COUNTER, "/PGM/ChunkR3Map/TlbHits", STAMUNIT_OCCURENCES, "TLB hits.");
1540	STAM_REG(pVM, &pPGM->StatChunkR3MapTlbMisses, STAMTYPE_COUNTER, "/PGM/ChunkR3Map/TlbMisses", STAMUNIT_OCCURENCES, "TLB misses.");
1541	STAM_REG(pVM, &pPGM->StatPageReplaceShared, STAMTYPE_COUNTER, "/PGM/Page/ReplacedShared", STAMUNIT_OCCURENCES, "Times a shared page was replaced.");
1542	STAM_REG(pVM, &pPGM->StatPageReplaceZero, STAMTYPE_COUNTER, "/PGM/Page/ReplacedZero", STAMUNIT_OCCURENCES, "Times the zero page was replaced.");
1543	STAM_REG(pVM, &pPGM->StatPageHandyAllocs, STAMTYPE_COUNTER, "/PGM/Page/HandyAllocs", STAMUNIT_OCCURENCES, "Number of times we've allocated more handy pages.");
1544	STAM_REG(pVM, &pPGM->cAllPages, STAMTYPE_U32, "/PGM/Page/cAllPages", STAMUNIT_OCCURENCES, "The total number of pages.");
1545	STAM_REG(pVM, &pPGM->cPrivatePages, STAMTYPE_U32, "/PGM/Page/cPrivatePages", STAMUNIT_OCCURENCES, "The number of private pages.");
1546	STAM_REG(pVM, &pPGM->cSharedPages, STAMTYPE_U32, "/PGM/Page/cSharedPages", STAMUNIT_OCCURENCES, "The number of shared pages.");
1547	STAM_REG(pVM, &pPGM->cZeroPages, STAMTYPE_U32, "/PGM/Page/cZeroPages", STAMUNIT_OCCURENCES, "The number of zero backed pages.");
1548
1549	#ifdef PGMPOOL_WITH_GCPHYS_TRACKING
1550	STAM_REG(pVM, &pPGM->StatTrackVirgin, STAMTYPE_COUNTER, "/PGM/Track/Virgin", STAMUNIT_OCCURENCES, "The number of first time shadowings");
1551	STAM_REG(pVM, &pPGM->StatTrackAliased, STAMTYPE_COUNTER, "/PGM/Track/Aliased", STAMUNIT_OCCURENCES, "The number of times switching to cRef2, i.e. the page is being shadowed by two PTs.");
1552	STAM_REG(pVM, &pPGM->StatTrackAliasedMany, STAMTYPE_COUNTER, "/PGM/Track/AliasedMany", STAMUNIT_OCCURENCES, "The number of times we're tracking using cRef2.");
1553	STAM_REG(pVM, &pPGM->StatTrackAliasedLots, STAMTYPE_COUNTER, "/PGM/Track/AliasedLots", STAMUNIT_OCCURENCES, "The number of times we're hitting pages which has overflowed cRef2");
1554	STAM_REG(pVM, &pPGM->StatTrackOverflows, STAMTYPE_COUNTER, "/PGM/Track/Overflows", STAMUNIT_OCCURENCES, "The number of times the extent list grows to long.");
1555	STAM_REG(pVM, &pPGM->StatTrackDeref, STAMTYPE_PROFILE, "/PGM/Track/Deref", STAMUNIT_OCCURENCES, "Profiling of SyncPageWorkerTrackDeref (expensive).");
1556	#endif
1557
1558	for (unsigned i = 0; i < X86_PG_ENTRIES; i++)
1559	{
1560	/** @todo r=bird: We need a STAMR3RegisterF()! */
1561	char szName[32];
1562
1563	RTStrPrintf(szName, sizeof(szName), "/PGM/GC/PD/Trap0e/%04X", i);
1564	int rc = STAMR3Register(pVM, &pPGM->StatGCTrap0ePD[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, szName, STAMUNIT_OCCURENCES, "The number of traps in page directory n.");
1565	AssertRC(rc);
1566
1567	RTStrPrintf(szName, sizeof(szName), "/PGM/GC/PD/SyncPt/%04X", i);
1568	rc = STAMR3Register(pVM, &pPGM->StatGCSyncPtPD[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, szName, STAMUNIT_OCCURENCES, "The number of syncs per PD n.");
1569	AssertRC(rc);
1570
1571	RTStrPrintf(szName, sizeof(szName), "/PGM/GC/PD/SyncPage/%04X", i);
1572	rc = STAMR3Register(pVM, &pPGM->StatGCSyncPagePD[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, szName, STAMUNIT_OCCURENCES, "The number of out of sync pages per page directory n.");
1573	AssertRC(rc);
1574	}
1575	}
1576	#endif /* VBOX_WITH_STATISTICS */
1577
1578	/**
1579	* Init the PGM bits that rely on VMMR0 and MM to be fully initialized.
1580	*
1581	* The dynamic mapping area will also be allocated and initialized at this
1582	* time. We could allocate it during PGMR3Init of course, but the mapping
1583	* wouldn't be allocated at that time preventing us from setting up the
1584	* page table entries with the dummy page.
1585	*
1586	* @returns VBox status code.
1587	* @param pVM VM handle.
1588	*/
1589	PGMR3DECL(int) PGMR3InitDynMap(PVM pVM)
1590	{
1591	RTGCPTR GCPtr;
1592	/*
1593	* Reserve space for mapping the paging pages into guest context.
1594	*/
1595	int rc = MMR3HyperReserve(pVM, PAGE_SIZE * (2 + ELEMENTS(pVM->pgm.s.apHCPaePDs) + 1 + 2 + 2), "Paging", &GCPtr);
1596	AssertRCReturn(rc, rc);
1597	pVM->pgm.s.pGC32BitPD = GCPtr;
1598	MMR3HyperReserve(pVM, PAGE_SIZE, "fence", NULL);
1599
1600	/*
1601	* Reserve space for the dynamic mappings.
1602	*/
1603	/** @todo r=bird: Need to verify that the checks for crossing PTs are correct here. They seems to be assuming 4MB PTs.. */
1604	rc = MMR3HyperReserve(pVM, MM_HYPER_DYNAMIC_SIZE, "Dynamic mapping", &GCPtr);
1605	if (VBOX_SUCCESS(rc))
1606	pVM->pgm.s.pbDynPageMapBaseGC = GCPtr;
1607
1608	if ( VBOX_SUCCESS(rc)
1609	&& (pVM->pgm.s.pbDynPageMapBaseGC >> X86_PD_SHIFT) != ((pVM->pgm.s.pbDynPageMapBaseGC + MM_HYPER_DYNAMIC_SIZE - 1) >> X86_PD_SHIFT))
1610	{
1611	rc = MMR3HyperReserve(pVM, MM_HYPER_DYNAMIC_SIZE, "Dynamic mapping not crossing", &GCPtr);
1612	if (VBOX_SUCCESS(rc))
1613	pVM->pgm.s.pbDynPageMapBaseGC = GCPtr;
1614	}
1615	if (VBOX_SUCCESS(rc))
1616	{
1617	AssertRelease((pVM->pgm.s.pbDynPageMapBaseGC >> X86_PD_SHIFT) == ((pVM->pgm.s.pbDynPageMapBaseGC + MM_HYPER_DYNAMIC_SIZE - 1) >> X86_PD_SHIFT));
1618	MMR3HyperReserve(pVM, PAGE_SIZE, "fence", NULL);
1619	}
1620	return rc;
1621	}
1622
1623
1624	/**
1625	* Ring-3 init finalizing.
1626	*
1627	* @returns VBox status code.
1628	* @param pVM The VM handle.
1629	*/
1630	PGMR3DECL(int) PGMR3InitFinalize(PVM pVM)
1631	{
1632	/*
1633	* Map the paging pages into the guest context.
1634	*/
1635	RTGCPTR GCPtr = pVM->pgm.s.pGC32BitPD;
1636	AssertReleaseReturn(GCPtr, VERR_INTERNAL_ERROR);
1637
1638	int rc = PGMMap(pVM, GCPtr, pVM->pgm.s.HCPhys32BitPD, PAGE_SIZE, 0);
1639	AssertRCReturn(rc, rc);
1640	pVM->pgm.s.pGC32BitPD = GCPtr;
1641	GCPtr += PAGE_SIZE;
1642	GCPtr += PAGE_SIZE; /* reserved page */
1643
1644	for (unsigned i = 0; i < ELEMENTS(pVM->pgm.s.apHCPaePDs); i++)
1645	{
1646	rc = PGMMap(pVM, GCPtr, pVM->pgm.s.aHCPhysPaePDs[i], PAGE_SIZE, 0);
1647	AssertRCReturn(rc, rc);
1648	pVM->pgm.s.apGCPaePDs[i] = GCPtr;
1649	GCPtr += PAGE_SIZE;
1650	}
1651	/* A bit of paranoia is justified. */
1652	AssertRelease((RTGCUINTPTR)pVM->pgm.s.apGCPaePDs[0] + PAGE_SIZE == (RTGCUINTPTR)pVM->pgm.s.apGCPaePDs[1]);
1653	AssertRelease((RTGCUINTPTR)pVM->pgm.s.apGCPaePDs[1] + PAGE_SIZE == (RTGCUINTPTR)pVM->pgm.s.apGCPaePDs[2]);
1654	AssertRelease((RTGCUINTPTR)pVM->pgm.s.apGCPaePDs[2] + PAGE_SIZE == (RTGCUINTPTR)pVM->pgm.s.apGCPaePDs[3]);
1655	GCPtr += PAGE_SIZE; /* reserved page */
1656
1657	rc = PGMMap(pVM, GCPtr, pVM->pgm.s.HCPhysPaePDPT, PAGE_SIZE, 0);
1658	AssertRCReturn(rc, rc);
1659	pVM->pgm.s.pGCPaePDPT = GCPtr;
1660	GCPtr += PAGE_SIZE;
1661	GCPtr += PAGE_SIZE; /* reserved page */
1662
1663
1664	/*
1665	* Reserve space for the dynamic mappings.
1666	* Initialize the dynamic mapping pages with dummy pages to simply the cache.
1667	*/
1668	/* get the pointer to the page table entries. */
1669	PPGMMAPPING pMapping = pgmGetMapping(pVM, pVM->pgm.s.pbDynPageMapBaseGC);
1670	AssertRelease(pMapping);
1671	const uintptr_t off = pVM->pgm.s.pbDynPageMapBaseGC - pMapping->GCPtr;
1672	const unsigned iPT = off >> X86_PD_SHIFT;
1673	const unsigned iPG = (off >> X86_PT_SHIFT) & X86_PT_MASK;
1674	pVM->pgm.s.paDynPageMap32BitPTEsGC = pMapping->aPTs[iPT].pPTGC + iPG * sizeof(pMapping->aPTs[0].pPTR3->a[0]);
1675	pVM->pgm.s.paDynPageMapPaePTEsGC = pMapping->aPTs[iPT].paPaePTsGC + iPG * sizeof(pMapping->aPTs[0].paPaePTsR3->a[0]);
1676
1677	/* init cache */
1678	RTHCPHYS HCPhysDummy = MMR3PageDummyHCPhys(pVM);
1679	for (unsigned i = 0; i < ELEMENTS(pVM->pgm.s.aHCPhysDynPageMapCache); i++)
1680	pVM->pgm.s.aHCPhysDynPageMapCache[i] = HCPhysDummy;
1681
1682	for (unsigned i = 0; i < MM_HYPER_DYNAMIC_SIZE; i += PAGE_SIZE)
1683	{
1684	rc = PGMMap(pVM, pVM->pgm.s.pbDynPageMapBaseGC + i, HCPhysDummy, PAGE_SIZE, 0);
1685	AssertRCReturn(rc, rc);
1686	}
1687
1688	return rc;
1689	}
1690
1691
1692	/**
1693	* Applies relocations to data and code managed by this
1694	* component. This function will be called at init and
1695	* whenever the VMM need to relocate it self inside the GC.
1696	*
1697	* @param pVM The VM.
1698	* @param offDelta Relocation delta relative to old location.
1699	*/
1700	PGMR3DECL(void) PGMR3Relocate(PVM pVM, RTGCINTPTR offDelta)
1701	{
1702	LogFlow(("PGMR3Relocate\n"));
1703
1704	/*
1705	* Paging stuff.
1706	*/
1707	pVM->pgm.s.GCPtrCR3Mapping += offDelta;
1708	/** @todo move this into shadow and guest specific relocation functions. */
1709	AssertMsg(pVM->pgm.s.pGC32BitPD, ("Init order, no relocation before paging is initialized!\n"));
1710	pVM->pgm.s.pGC32BitPD += offDelta;
1711	pVM->pgm.s.pGuestPDGC += offDelta;
1712	AssertCompile(ELEMENTS(pVM->pgm.s.apGCPaePDs) == ELEMENTS(pVM->pgm.s.apGstPaePDsGC));
1713	for (unsigned i = 0; i < ELEMENTS(pVM->pgm.s.apGCPaePDs); i++)
1714	{
1715	pVM->pgm.s.apGCPaePDs[i] += offDelta;
1716	pVM->pgm.s.apGstPaePDsGC[i] += offDelta;
1717	}
1718	pVM->pgm.s.pGstPaePDPTGC += offDelta;
1719	pVM->pgm.s.pGCPaePDPT += offDelta;
1720
1721	pgmR3ModeDataInit(pVM, true /* resolve GC/R0 symbols */);
1722	pgmR3ModeDataSwitch(pVM, pVM->pgm.s.enmShadowMode, pVM->pgm.s.enmGuestMode);
1723
1724	PGM_SHW_PFN(Relocate, pVM)(pVM, offDelta);
1725	PGM_GST_PFN(Relocate, pVM)(pVM, offDelta);
1726	PGM_BTH_PFN(Relocate, pVM)(pVM, offDelta);
1727
1728	/*
1729	* Trees.
1730	*/
1731	pVM->pgm.s.pTreesGC = MMHyperHC2GC(pVM, pVM->pgm.s.pTreesHC);
1732
1733	/*
1734	* Ram ranges.
1735	*/
1736	if (pVM->pgm.s.pRamRangesR3)
1737	{
1738	pVM->pgm.s.pRamRangesGC = MMHyperHC2GC(pVM, pVM->pgm.s.pRamRangesR3);
1739	for (PPGMRAMRANGE pCur = pVM->pgm.s.pRamRangesR3; pCur->pNextR3; pCur = pCur->pNextR3)
1740	#ifdef VBOX_WITH_NEW_PHYS_CODE
1741	pCur->pNextGC = MMHyperR3ToGC(pVM, pCur->pNextR3);
1742	#else
1743	{
1744	pCur->pNextGC = MMHyperR3ToGC(pVM, pCur->pNextR3);
1745	if (pCur->pavHCChunkGC)
1746	pCur->pavHCChunkGC = MMHyperHC2GC(pVM, pCur->pavHCChunkHC);
1747	}
1748	#endif
1749	}
1750
1751	/*
1752	* Update the two page directories with all page table mappings.
1753	* (One or more of them have changed, that's why we're here.)
1754	*/
1755	pVM->pgm.s.pMappingsGC = MMHyperHC2GC(pVM, pVM->pgm.s.pMappingsR3);
1756	for (PPGMMAPPING pCur = pVM->pgm.s.pMappingsR3; pCur->pNextR3; pCur = pCur->pNextR3)
1757	pCur->pNextGC = MMHyperHC2GC(pVM, pCur->pNextR3);
1758
1759	/* Relocate GC addresses of Page Tables. */
1760	for (PPGMMAPPING pCur = pVM->pgm.s.pMappingsR3; pCur; pCur = pCur->pNextR3)
1761	{
1762	for (RTHCUINT i = 0; i < pCur->cPTs; i++)
1763	{
1764	pCur->aPTs[i].pPTGC = MMHyperR3ToGC(pVM, pCur->aPTs[i].pPTR3);
1765	pCur->aPTs[i].paPaePTsGC = MMHyperR3ToGC(pVM, pCur->aPTs[i].paPaePTsR3);
1766	}
1767	}
1768
1769	/*
1770	* Dynamic page mapping area.
1771	*/
1772	pVM->pgm.s.paDynPageMap32BitPTEsGC += offDelta;
1773	pVM->pgm.s.paDynPageMapPaePTEsGC += offDelta;
1774	pVM->pgm.s.pbDynPageMapBaseGC += offDelta;
1775
1776	/*
1777	* The Zero page.
1778	*/
1779	pVM->pgm.s.pvZeroPgR0 = MMHyperR3ToR0(pVM, pVM->pgm.s.pvZeroPgR3);
1780	AssertRelease(pVM->pgm.s.pvZeroPgR0);
1781
1782	/*
1783	* Physical and virtual handlers.
1784	*/
1785	RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesHC->PhysHandlers, true, pgmR3RelocatePhysHandler, &offDelta);
1786	RTAvlroGCPtrDoWithAll(&pVM->pgm.s.pTreesHC->VirtHandlers, true, pgmR3RelocateVirtHandler, &offDelta);
1787	RTAvlroGCPtrDoWithAll(&pVM->pgm.s.pTreesHC->HyperVirtHandlers, true, pgmR3RelocateHyperVirtHandler, &offDelta);
1788
1789	/*
1790	* The page pool.
1791	*/
1792	pgmR3PoolRelocate(pVM);
1793	}
1794
1795
1796	/**
1797	* Callback function for relocating a physical access handler.
1798	*
1799	* @returns 0 (continue enum)
1800	* @param pNode Pointer to a PGMPHYSHANDLER node.
1801	* @param pvUser Pointer to the offDelta. This is a pointer to the delta since we're
1802	* not certain the delta will fit in a void pointer for all possible configs.
1803	*/
1804	static DECLCALLBACK(int) pgmR3RelocatePhysHandler(PAVLROGCPHYSNODECORE pNode, void *pvUser)
1805	{
1806	PPGMPHYSHANDLER pHandler = (PPGMPHYSHANDLER)pNode;
1807	RTGCINTPTR offDelta = *(PRTGCINTPTR)pvUser;
1808	if (pHandler->pfnHandlerGC)
1809	pHandler->pfnHandlerGC += offDelta;
1810	if ((RTGCUINTPTR)pHandler->pvUserGC >= 0x10000)
1811	pHandler->pvUserGC += offDelta;
1812	return 0;
1813	}
1814
1815
1816	/**
1817	* Callback function for relocating a virtual access handler.
1818	*
1819	* @returns 0 (continue enum)
1820	* @param pNode Pointer to a PGMVIRTHANDLER node.
1821	* @param pvUser Pointer to the offDelta. This is a pointer to the delta since we're
1822	* not certain the delta will fit in a void pointer for all possible configs.
1823	*/
1824	static DECLCALLBACK(int) pgmR3RelocateVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser)
1825	{
1826	PPGMVIRTHANDLER pHandler = (PPGMVIRTHANDLER)pNode;
1827	RTGCINTPTR offDelta = *(PRTGCINTPTR)pvUser;
1828	Assert( pHandler->enmType == PGMVIRTHANDLERTYPE_ALL
1829	\|\| pHandler->enmType == PGMVIRTHANDLERTYPE_WRITE);
1830	Assert(pHandler->pfnHandlerGC);
1831	pHandler->pfnHandlerGC += offDelta;
1832	return 0;
1833	}
1834
1835
1836	/**
1837	* Callback function for relocating a virtual access handler for the hypervisor mapping.
1838	*
1839	* @returns 0 (continue enum)
1840	* @param pNode Pointer to a PGMVIRTHANDLER node.
1841	* @param pvUser Pointer to the offDelta. This is a pointer to the delta since we're
1842	* not certain the delta will fit in a void pointer for all possible configs.
1843	*/
1844	static DECLCALLBACK(int) pgmR3RelocateHyperVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser)
1845	{
1846	PPGMVIRTHANDLER pHandler = (PPGMVIRTHANDLER)pNode;
1847	RTGCINTPTR offDelta = *(PRTGCINTPTR)pvUser;
1848	Assert(pHandler->enmType == PGMVIRTHANDLERTYPE_HYPERVISOR);
1849	Assert(pHandler->pfnHandlerGC);
1850	pHandler->pfnHandlerGC += offDelta;
1851	return 0;
1852	}
1853
1854
1855	/**
1856	* The VM is being reset.
1857	*
1858	* For the PGM component this means that any PD write monitors
1859	* needs to be removed.
1860	*
1861	* @param pVM VM handle.
1862	*/
1863	PGMR3DECL(void) PGMR3Reset(PVM pVM)
1864	{
1865	LogFlow(("PGMR3Reset:\n"));
1866	VM_ASSERT_EMT(pVM);
1867
1868	pgmLock(pVM);
1869
1870	/*
1871	* Unfix any fixed mappings and disable CR3 monitoring.
1872	*/
1873	pVM->pgm.s.fMappingsFixed = false;
1874	pVM->pgm.s.GCPtrMappingFixed = 0;
1875	pVM->pgm.s.cbMappingFixed = 0;
1876
1877	/* Exit the guest paging mode before the pgm pool gets reset.
1878	* Important to clean up the amd64 case.
1879	*/
1880	int rc = PGM_GST_PFN(Exit, pVM)(pVM);
1881	AssertRC(rc);
1882	#ifdef DEBUG
1883	DBGFR3InfoLog(pVM, "mappings", NULL);
1884	DBGFR3InfoLog(pVM, "handlers", "all nostat");
1885	#endif
1886
1887	/*
1888	* Reset the shadow page pool.
1889	*/
1890	pgmR3PoolReset(pVM);
1891
1892	/*
1893	* Re-init other members.
1894	*/
1895	pVM->pgm.s.fA20Enabled = true;
1896
1897	/*
1898	* Clear the FFs PGM owns.
1899	*/
1900	VM_FF_CLEAR(pVM, VM_FF_PGM_SYNC_CR3);
1901	VM_FF_CLEAR(pVM, VM_FF_PGM_SYNC_CR3_NON_GLOBAL);
1902
1903	/*
1904	* Reset (zero) RAM pages.
1905	*/
1906	rc = pgmR3PhysRamReset(pVM);
1907	if (RT_SUCCESS(rc))
1908	{
1909	#ifdef VBOX_WITH_NEW_PHYS_CODE
1910	/*
1911	* Reset (zero) shadow ROM pages.
1912	*/
1913	rc = pgmR3PhysRomReset(pVM);
1914	#endif
1915	if (RT_SUCCESS(rc))
1916	{
1917	/*
1918	* Switch mode back to real mode.
1919	*/
1920	rc = PGMR3ChangeMode(pVM, PGMMODE_REAL);
1921	STAM_REL_COUNTER_RESET(&pVM->pgm.s.cGuestModeChanges);
1922	}
1923	}
1924
1925	pgmUnlock(pVM);
1926	//return rc;
1927	AssertReleaseRC(rc);
1928	}
1929
1930
1931	#ifdef VBOX_STRICT
1932	/**
1933	* VM state change callback for clearing fNoMorePhysWrites after
1934	* a snapshot has been created.
1935	*/
1936	static DECLCALLBACK(void) pgmR3ResetNoMorePhysWritesFlag(PVM pVM, VMSTATE enmState, VMSTATE enmOldState, void *pvUser)
1937	{
1938	if (enmState == VMSTATE_RUNNING)
1939	pVM->pgm.s.fNoMorePhysWrites = false;
1940	}
1941	#endif
1942
1943
1944	/**
1945	* Terminates the PGM.
1946	*
1947	* @returns VBox status code.
1948	* @param pVM Pointer to VM structure.
1949	*/
1950	PGMR3DECL(int) PGMR3Term(PVM pVM)
1951	{
1952	return PDMR3CritSectDelete(&pVM->pgm.s.CritSect);
1953	}
1954
1955
1956	/**
1957	* Execute state save operation.
1958	*
1959	* @returns VBox status code.
1960	* @param pVM VM Handle.
1961	* @param pSSM SSM operation handle.
1962	*/
1963	static DECLCALLBACK(int) pgmR3Save(PVM pVM, PSSMHANDLE pSSM)
1964	{
1965	PPGM pPGM = &pVM->pgm.s;
1966
1967	/* No more writes to physical memory after this point! */
1968	pVM->pgm.s.fNoMorePhysWrites = true;
1969
1970	/*
1971	* Save basic data (required / unaffected by relocation).
1972	*/
1973	#if 1
1974	SSMR3PutBool(pSSM, pPGM->fMappingsFixed);
1975	#else
1976	SSMR3PutUInt(pSSM, pPGM->fMappingsFixed);
1977	#endif
1978	SSMR3PutGCPtr(pSSM, pPGM->GCPtrMappingFixed);
1979	SSMR3PutU32(pSSM, pPGM->cbMappingFixed);
1980	SSMR3PutUInt(pSSM, pPGM->cbRamSize);
1981	SSMR3PutGCPhys(pSSM, pPGM->GCPhysA20Mask);
1982	SSMR3PutUInt(pSSM, pPGM->fA20Enabled);
1983	SSMR3PutUInt(pSSM, pPGM->fSyncFlags);
1984	SSMR3PutUInt(pSSM, pPGM->enmGuestMode);
1985	SSMR3PutU32(pSSM, ~0); /* Separator. */
1986
1987	/*
1988	* The guest mappings.
1989	*/
1990	uint32_t i = 0;
1991	for (PPGMMAPPING pMapping = pPGM->pMappingsR3; pMapping; pMapping = pMapping->pNextR3, i++)
1992	{
1993	SSMR3PutU32(pSSM, i);
1994	SSMR3PutStrZ(pSSM, pMapping->pszDesc); /* This is the best unique id we have... */
1995	SSMR3PutGCPtr(pSSM, pMapping->GCPtr);
1996	SSMR3PutGCUIntPtr(pSSM, pMapping->cPTs);
1997	/* flags are done by the mapping owners! */
1998	}
1999	SSMR3PutU32(pSSM, ~0); /* terminator. */
2000
2001	/*
2002	* Ram range flags and bits.
2003	*/
2004	i = 0;
2005	for (PPGMRAMRANGE pRam = pPGM->pRamRangesR3; pRam; pRam = pRam->pNextR3, i++)
2006	{
2007	/** @todo MMIO ranges may move (PCI reconfig), we currently assume they don't. */
2008
2009	SSMR3PutU32(pSSM, i);
2010	SSMR3PutGCPhys(pSSM, pRam->GCPhys);
2011	SSMR3PutGCPhys(pSSM, pRam->GCPhysLast);
2012	SSMR3PutGCPhys(pSSM, pRam->cb);
2013	SSMR3PutU8(pSSM, !!pRam->pvHC); /* boolean indicating memory or not. */
2014
2015	/* Flags. */
2016	const unsigned cPages = pRam->cb >> PAGE_SHIFT;
2017	for (unsigned iPage = 0; iPage < cPages; iPage++)
2018	SSMR3PutU16(pSSM, (uint16_t)(pRam->aPages[iPage].HCPhys & ~X86_PTE_PAE_PG_MASK)); /** @todo PAGE FLAGS */
2019
2020	/* any memory associated with the range. */
2021	if (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)
2022	{
2023	for (unsigned iChunk = 0; iChunk < (pRam->cb >> PGM_DYNAMIC_CHUNK_SHIFT); iChunk++)
2024	{
2025	if (pRam->pavHCChunkHC[iChunk])
2026	{
2027	SSMR3PutU8(pSSM, 1); /* chunk present */
2028	SSMR3PutMem(pSSM, pRam->pavHCChunkHC[iChunk], PGM_DYNAMIC_CHUNK_SIZE);
2029	}
2030	else
2031	SSMR3PutU8(pSSM, 0); /* no chunk present */
2032	}
2033	}
2034	else if (pRam->pvHC)
2035	{
2036	int rc = SSMR3PutMem(pSSM, pRam->pvHC, pRam->cb);
2037	if (VBOX_FAILURE(rc))
2038	{
2039	Log(("pgmR3Save: SSMR3PutMem(, %p, %#x) -> %Vrc\n", pRam->pvHC, pRam->cb, rc));
2040	return rc;
2041	}
2042	}
2043	}
2044	return SSMR3PutU32(pSSM, ~0); /* terminator. */
2045	}
2046
2047
2048	/**
2049	* Execute state load operation.
2050	*
2051	* @returns VBox status code.
2052	* @param pVM VM Handle.
2053	* @param pSSM SSM operation handle.
2054	* @param u32Version Data layout version.
2055	*/
2056	static DECLCALLBACK(int) pgmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version)
2057	{
2058	/*
2059	* Validate version.
2060	*/
2061	if (u32Version != PGM_SAVED_STATE_VERSION)
2062	{
2063	Log(("pgmR3Load: Invalid version u32Version=%d (current %d)!\n", u32Version, PGM_SAVED_STATE_VERSION));
2064	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
2065	}
2066
2067	/*
2068	* Call the reset function to make sure all the memory is cleared.
2069	*/
2070	PGMR3Reset(pVM);
2071
2072	/*
2073	* Load basic data (required / unaffected by relocation).
2074	*/
2075	PPGM pPGM = &pVM->pgm.s;
2076	#if 1
2077	SSMR3GetBool(pSSM, &pPGM->fMappingsFixed);
2078	#else
2079	uint32_t u;
2080	SSMR3GetU32(pSSM, &u);
2081	pPGM->fMappingsFixed = u;
2082	#endif
2083	SSMR3GetGCPtr(pSSM, &pPGM->GCPtrMappingFixed);
2084	SSMR3GetU32(pSSM, &pPGM->cbMappingFixed);
2085
2086	RTUINT cbRamSize;
2087	int rc = SSMR3GetU32(pSSM, &cbRamSize);
2088	if (VBOX_FAILURE(rc))
2089	return rc;
2090	if (cbRamSize != pPGM->cbRamSize)
2091	return VERR_SSM_LOAD_MEMORY_SIZE_MISMATCH;
2092	SSMR3GetGCPhys(pSSM, &pPGM->GCPhysA20Mask);
2093	SSMR3GetUInt(pSSM, &pPGM->fA20Enabled);
2094	SSMR3GetUInt(pSSM, &pPGM->fSyncFlags);
2095	RTUINT uGuestMode;
2096	SSMR3GetUInt(pSSM, &uGuestMode);
2097	pPGM->enmGuestMode = (PGMMODE)uGuestMode;
2098
2099	/* check separator. */
2100	uint32_t u32Sep;
2101	SSMR3GetU32(pSSM, &u32Sep);
2102	if (VBOX_FAILURE(rc))
2103	return rc;
2104	if (u32Sep != (uint32_t)~0)
2105	{
2106	AssertMsgFailed(("u32Sep=%#x (first)\n", u32Sep));
2107	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2108	}
2109
2110	/*
2111	* The guest mappings.
2112	*/
2113	uint32_t i = 0;
2114	for (;; i++)
2115	{
2116	/* Check the seqence number / separator. */
2117	rc = SSMR3GetU32(pSSM, &u32Sep);
2118	if (VBOX_FAILURE(rc))
2119	return rc;
2120	if (u32Sep == ~0U)
2121	break;
2122	if (u32Sep != i)
2123	{
2124	AssertMsgFailed(("u32Sep=%#x (last)\n", u32Sep));
2125	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2126	}
2127
2128	/* get the mapping details. */
2129	char szDesc[256];
2130	szDesc[0] = '\0';
2131	rc = SSMR3GetStrZ(pSSM, szDesc, sizeof(szDesc));
2132	if (VBOX_FAILURE(rc))
2133	return rc;
2134	RTGCPTR GCPtr;
2135	SSMR3GetGCPtr(pSSM, &GCPtr);
2136	RTGCUINTPTR cPTs;
2137	rc = SSMR3GetGCUIntPtr(pSSM, &cPTs);
2138	if (VBOX_FAILURE(rc))
2139	return rc;
2140
2141	/* find matching range. */
2142	PPGMMAPPING pMapping;
2143	for (pMapping = pPGM->pMappingsR3; pMapping; pMapping = pMapping->pNextR3)
2144	if ( pMapping->cPTs == cPTs
2145	&& !strcmp(pMapping->pszDesc, szDesc))
2146	break;
2147	if (!pMapping)
2148	{
2149	LogRel(("Couldn't find mapping: cPTs=%#x szDesc=%s (GCPtr=%VGv)\n",
2150	cPTs, szDesc, GCPtr));
2151	AssertFailed();
2152	return VERR_SSM_LOAD_CONFIG_MISMATCH;
2153	}
2154
2155	/* relocate it. */
2156	if (pMapping->GCPtr != GCPtr)
2157	{
2158	AssertMsg((GCPtr >> X86_PD_SHIFT << X86_PD_SHIFT) == GCPtr, ("GCPtr=%VGv\n", GCPtr));
2159	#if HC_ARCH_BITS == 64
2160	LogRel(("Mapping: %VGv -> %VGv %s\n", pMapping->GCPtr, GCPtr, pMapping->pszDesc));
2161	#endif
2162	pgmR3MapRelocate(pVM, pMapping, pMapping->GCPtr, GCPtr);
2163	}
2164	else
2165	Log(("pgmR3Load: '%s' needed no relocation (%VGv)\n", szDesc, GCPtr));
2166	}
2167
2168	/*
2169	* Ram range flags and bits.
2170	*/
2171	i = 0;
2172	for (PPGMRAMRANGE pRam = pPGM->pRamRangesR3; pRam; pRam = pRam->pNextR3, i++)
2173	{
2174	/** @todo MMIO ranges may move (PCI reconfig), we currently assume they don't. */
2175	/* Check the seqence number / separator. */
2176	rc = SSMR3GetU32(pSSM, &u32Sep);
2177	if (VBOX_FAILURE(rc))
2178	return rc;
2179	if (u32Sep == ~0U)
2180	break;
2181	if (u32Sep != i)
2182	{
2183	AssertMsgFailed(("u32Sep=%#x (last)\n", u32Sep));
2184	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2185	}
2186
2187	/* Get the range details. */
2188	RTGCPHYS GCPhys;
2189	SSMR3GetGCPhys(pSSM, &GCPhys);
2190	RTGCPHYS GCPhysLast;
2191	SSMR3GetGCPhys(pSSM, &GCPhysLast);
2192	RTGCPHYS cb;
2193	SSMR3GetGCPhys(pSSM, &cb);
2194	uint8_t fHaveBits;
2195	rc = SSMR3GetU8(pSSM, &fHaveBits);
2196	if (VBOX_FAILURE(rc))
2197	return rc;
2198	if (fHaveBits & ~1)
2199	{
2200	AssertMsgFailed(("u32Sep=%#x (last)\n", u32Sep));
2201	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2202	}
2203
2204	/* Match it up with the current range. */
2205	if ( GCPhys != pRam->GCPhys
2206	\|\| GCPhysLast != pRam->GCPhysLast
2207	\|\| cb != pRam->cb
2208	\|\| fHaveBits != !!pRam->pvHC)
2209	{
2210	LogRel(("Ram range: %VGp-%VGp %VGp bytes %s\n"
2211	"State : %VGp-%VGp %VGp bytes %s\n",
2212	pRam->GCPhys, pRam->GCPhysLast, pRam->cb, pRam->pvHC ? "bits" : "nobits",
2213	GCPhys, GCPhysLast, cb, fHaveBits ? "bits" : "nobits"));
2214	/*
2215	* If we're loading a state for debugging purpose, don't make a fuss if
2216	* the MMIO[2] and ROM stuff isn't 100% right, just skip the mismatches.
2217	*/
2218	if ( SSMR3HandleGetAfter(pSSM) != SSMAFTER_DEBUG_IT
2219	\|\| GCPhys < 8 * _1M)
2220	AssertFailedReturn(VERR_SSM_LOAD_CONFIG_MISMATCH);
2221
2222	RTGCPHYS cPages = ((GCPhysLast - GCPhys) + 1) >> PAGE_SHIFT;
2223	while (cPages-- > 0)
2224	{
2225	uint16_t u16Ignore;
2226	SSMR3GetU16(pSSM, &u16Ignore);
2227	}
2228	continue;
2229	}
2230
2231	/* Flags. */
2232	const unsigned cPages = pRam->cb >> PAGE_SHIFT;
2233	for (unsigned iPage = 0; iPage < cPages; iPage++)
2234	{
2235	uint16_t u16 = 0;
2236	SSMR3GetU16(pSSM, &u16);
2237	u16 &= PAGE_OFFSET_MASK & ~( RT_BIT(4) \| RT_BIT(5) \| RT_BIT(6)
2238	\| RT_BIT(7) \| RT_BIT(8) \| RT_BIT(9) \| RT_BIT(10) );
2239	// &= MM_RAM_FLAGS_DYNAMIC_ALLOC \| MM_RAM_FLAGS_RESERVED \| MM_RAM_FLAGS_ROM \| MM_RAM_FLAGS_MMIO \| MM_RAM_FLAGS_MMIO2
2240	pRam->aPages[iPage].HCPhys = PGM_PAGE_GET_HCPHYS(&pRam->aPages[iPage]) \| (RTHCPHYS)u16; /** @todo PAGE FLAGS */
2241	}
2242
2243	/* any memory associated with the range. */
2244	if (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)
2245	{
2246	for (unsigned iChunk = 0; iChunk < (pRam->cb >> PGM_DYNAMIC_CHUNK_SHIFT); iChunk++)
2247	{
2248	uint8_t fValidChunk;
2249
2250	rc = SSMR3GetU8(pSSM, &fValidChunk);
2251	if (VBOX_FAILURE(rc))
2252	return rc;
2253	if (fValidChunk > 1)
2254	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2255
2256	if (fValidChunk)
2257	{
2258	if (!pRam->pavHCChunkHC[iChunk])
2259	{
2260	rc = pgmr3PhysGrowRange(pVM, pRam->GCPhys + iChunk * PGM_DYNAMIC_CHUNK_SIZE);
2261	if (VBOX_FAILURE(rc))
2262	return rc;
2263	}
2264	Assert(pRam->pavHCChunkHC[iChunk]);
2265
2266	SSMR3GetMem(pSSM, pRam->pavHCChunkHC[iChunk], PGM_DYNAMIC_CHUNK_SIZE);
2267	}
2268	/* else nothing to do */
2269	}
2270	}
2271	else if (pRam->pvHC)
2272	{
2273	int rc = SSMR3GetMem(pSSM, pRam->pvHC, pRam->cb);
2274	if (VBOX_FAILURE(rc))
2275	{
2276	Log(("pgmR3Save: SSMR3GetMem(, %p, %#x) -> %Vrc\n", pRam->pvHC, pRam->cb, rc));
2277	return rc;
2278	}
2279	}
2280	}
2281
2282	/*
2283	* We require a full resync now.
2284	*/
2285	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3_NON_GLOBAL);
2286	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
2287	pPGM->fSyncFlags \|= PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL;
2288	pPGM->fPhysCacheFlushPending = true;
2289	pgmR3HandlerPhysicalUpdateAll(pVM);
2290
2291	/*
2292	* Change the paging mode.
2293	*/
2294	rc = PGMR3ChangeMode(pVM, pPGM->enmGuestMode);
2295
2296	/* Restore pVM->pgm.s.GCPhysCR3. */
2297	Assert(pVM->pgm.s.GCPhysCR3 == NIL_RTGCPHYS);
2298	RTGCPHYS GCPhysCR3 = CPUMGetGuestCR3(pVM);
2299	if ( pVM->pgm.s.enmGuestMode == PGMMODE_PAE
2300	\|\| pVM->pgm.s.enmGuestMode == PGMMODE_PAE_NX
2301	\|\| pVM->pgm.s.enmGuestMode == PGMMODE_AMD64
2302	\|\| pVM->pgm.s.enmGuestMode == PGMMODE_AMD64_NX)
2303	GCPhysCR3 = (GCPhysCR3 & X86_CR3_PAE_PAGE_MASK);
2304	else
2305	GCPhysCR3 = (GCPhysCR3 & X86_CR3_PAGE_MASK);
2306	pVM->pgm.s.GCPhysCR3 = GCPhysCR3;
2307
2308	return rc;
2309	}
2310
2311
2312	/**
2313	* Show paging mode.
2314	*
2315	* @param pVM VM Handle.
2316	* @param pHlp The info helpers.
2317	* @param pszArgs "all" (default), "guest", "shadow" or "host".
2318	*/
2319	static DECLCALLBACK(void) pgmR3InfoMode(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2320	{
2321	/* digest argument. */
2322	bool fGuest, fShadow, fHost;
2323	if (pszArgs)
2324	pszArgs = RTStrStripL(pszArgs);
2325	if (!pszArgs \|\| !*pszArgs \|\| strstr(pszArgs, "all"))
2326	fShadow = fHost = fGuest = true;
2327	else
2328	{
2329	fShadow = fHost = fGuest = false;
2330	if (strstr(pszArgs, "guest"))
2331	fGuest = true;
2332	if (strstr(pszArgs, "shadow"))
2333	fShadow = true;
2334	if (strstr(pszArgs, "host"))
2335	fHost = true;
2336	}
2337
2338	/* print info. */
2339	if (fGuest)
2340	pHlp->pfnPrintf(pHlp, "Guest paging mode: %s, changed %RU64 times, A20 %s\n",
2341	PGMGetModeName(pVM->pgm.s.enmGuestMode), pVM->pgm.s.cGuestModeChanges.c,
2342	pVM->pgm.s.fA20Enabled ? "enabled" : "disabled");
2343	if (fShadow)
2344	pHlp->pfnPrintf(pHlp, "Shadow paging mode: %s\n", PGMGetModeName(pVM->pgm.s.enmShadowMode));
2345	if (fHost)
2346	{
2347	const char *psz;
2348	switch (pVM->pgm.s.enmHostMode)
2349	{
2350	case SUPPAGINGMODE_INVALID: psz = "invalid"; break;
2351	case SUPPAGINGMODE_32_BIT: psz = "32-bit"; break;
2352	case SUPPAGINGMODE_32_BIT_GLOBAL: psz = "32-bit+G"; break;
2353	case SUPPAGINGMODE_PAE: psz = "PAE"; break;
2354	case SUPPAGINGMODE_PAE_GLOBAL: psz = "PAE+G"; break;
2355	case SUPPAGINGMODE_PAE_NX: psz = "PAE+NX"; break;
2356	case SUPPAGINGMODE_PAE_GLOBAL_NX: psz = "PAE+G+NX"; break;
2357	case SUPPAGINGMODE_AMD64: psz = "AMD64"; break;
2358	case SUPPAGINGMODE_AMD64_GLOBAL: psz = "AMD64+G"; break;
2359	case SUPPAGINGMODE_AMD64_NX: psz = "AMD64+NX"; break;
2360	case SUPPAGINGMODE_AMD64_GLOBAL_NX: psz = "AMD64+G+NX"; break;
2361	default: psz = "unknown"; break;
2362	}
2363	pHlp->pfnPrintf(pHlp, "Host paging mode: %s\n", psz);
2364	}
2365	}
2366
2367
2368	/**
2369	* Dump registered MMIO ranges to the log.
2370	*
2371	* @param pVM VM Handle.
2372	* @param pHlp The info helpers.
2373	* @param pszArgs Arguments, ignored.
2374	*/
2375	static DECLCALLBACK(void) pgmR3PhysInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2376	{
2377	NOREF(pszArgs);
2378	pHlp->pfnPrintf(pHlp,
2379	"RAM ranges (pVM=%p)\n"
2380	"%.s %.s\n",
2381	pVM,
2382	sizeof(RTGCPHYS) * 4 + 1, "GC Phys Range ",
2383	sizeof(RTHCPTR) * 2, "pvHC ");
2384
2385	for (PPGMRAMRANGE pCur = pVM->pgm.s.pRamRangesR3; pCur; pCur = pCur->pNextR3)
2386	pHlp->pfnPrintf(pHlp,
2387	"%RGp-%RGp %RHv %s\n",
2388	pCur->GCPhys,
2389	pCur->GCPhysLast,
2390	pCur->pvHC,
2391	pCur->pszDesc);
2392	}
2393
2394	/**
2395	* Dump the page directory to the log.
2396	*
2397	* @param pVM VM Handle.
2398	* @param pHlp The info helpers.
2399	* @param pszArgs Arguments, ignored.
2400	*/
2401	static DECLCALLBACK(void) pgmR3InfoCr3(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2402	{
2403	/** @todo fix this! Convert the PGMR3DumpHierarchyHC functions to do guest stuff. */
2404	/* Big pages supported? */
2405	const bool fPSE = !!(CPUMGetGuestCR4(pVM) & X86_CR4_PSE);
2406
2407	/* Global pages supported? */
2408	const bool fPGE = !!(CPUMGetGuestCR4(pVM) & X86_CR4_PGE);
2409
2410	NOREF(pszArgs);
2411
2412	/*
2413	* Get page directory addresses.
2414	*/
2415	PX86PD pPDSrc = pVM->pgm.s.pGuestPDHC;
2416	Assert(pPDSrc);
2417	Assert(MMPhysGCPhys2HCVirt(pVM, (RTGCPHYS)(CPUMGetGuestCR3(pVM) & X86_CR3_PAGE_MASK), sizeof(*pPDSrc)) == pPDSrc);
2418
2419	/*
2420	* Iterate the page directory.
2421	*/
2422	for (unsigned iPD = 0; iPD < ELEMENTS(pPDSrc->a); iPD++)
2423	{
2424	X86PDE PdeSrc = pPDSrc->a[iPD];
2425	if (PdeSrc.n.u1Present)
2426	{
2427	if (PdeSrc.b.u1Size && fPSE)
2428	{
2429	pHlp->pfnPrintf(pHlp,
2430	"%04X - %VGp P=%d U=%d RW=%d G=%d - BIG\n",
2431	iPD,
2432	PdeSrc.u & X86_PDE_PG_MASK,
2433	PdeSrc.b.u1Present, PdeSrc.b.u1User, PdeSrc.b.u1Write, PdeSrc.b.u1Global && fPGE);
2434	}
2435	else
2436	{
2437	pHlp->pfnPrintf(pHlp,
2438	"%04X - %VGp P=%d U=%d RW=%d [G=%d]\n",
2439	iPD,
2440	PdeSrc.u & X86_PDE4M_PG_MASK,
2441	PdeSrc.n.u1Present, PdeSrc.n.u1User, PdeSrc.n.u1Write, PdeSrc.b.u1Global && fPGE);
2442	}
2443	}
2444	}
2445	}
2446
2447
2448	/**
2449	* Serivce a VMMCALLHOST_PGM_LOCK call.
2450	*
2451	* @returns VBox status code.
2452	* @param pVM The VM handle.
2453	*/
2454	PDMR3DECL(int) PGMR3LockCall(PVM pVM)
2455	{
2456	int rc = PDMR3CritSectEnterEx(&pVM->pgm.s.CritSect, true /* fHostCall */);
2457	AssertRC(rc);
2458	return rc;
2459	}
2460
2461
2462	/**
2463	* Converts a PGMMODE value to a PGM_TYPE_* \#define.
2464	*
2465	* @returns PGM_TYPE_*.
2466	* @param pgmMode The mode value to convert.
2467	*/
2468	DECLINLINE(unsigned) pgmModeToType(PGMMODE pgmMode)
2469	{
2470	switch (pgmMode)
2471	{
2472	case PGMMODE_REAL: return PGM_TYPE_REAL;
2473	case PGMMODE_PROTECTED: return PGM_TYPE_PROT;
2474	case PGMMODE_32_BIT: return PGM_TYPE_32BIT;
2475	case PGMMODE_PAE:
2476	case PGMMODE_PAE_NX: return PGM_TYPE_PAE;
2477	case PGMMODE_AMD64:
2478	case PGMMODE_AMD64_NX: return PGM_TYPE_AMD64;
2479	case PGMMODE_NESTED: return PGM_TYPE_NESTED;
2480	default:
2481	AssertFatalMsgFailed(("pgmMode=%d\n", pgmMode));
2482	}
2483	}
2484
2485
2486	/**
2487	* Gets the index into the paging mode data array of a SHW+GST mode.
2488	*
2489	* @returns PGM::paPagingData index.
2490	* @param uShwType The shadow paging mode type.
2491	* @param uGstType The guest paging mode type.
2492	*/
2493	DECLINLINE(unsigned) pgmModeDataIndex(unsigned uShwType, unsigned uGstType)
2494	{
2495	Assert(uShwType >= PGM_TYPE_32BIT && uShwType <= PGM_TYPE_NESTED);
2496	Assert(uGstType >= PGM_TYPE_REAL && uGstType <= PGM_TYPE_AMD64);
2497	return (uShwType - PGM_TYPE_32BIT) * (PGM_TYPE_AMD64 - PGM_TYPE_REAL + 1)
2498	+ (uGstType - PGM_TYPE_REAL);
2499	}
2500
2501
2502	/**
2503	* Gets the index into the paging mode data array of a SHW+GST mode.
2504	*
2505	* @returns PGM::paPagingData index.
2506	* @param enmShw The shadow paging mode.
2507	* @param enmGst The guest paging mode.
2508	*/
2509	DECLINLINE(unsigned) pgmModeDataIndexByMode(PGMMODE enmShw, PGMMODE enmGst)
2510	{
2511	Assert(enmShw >= PGMMODE_32_BIT && enmShw <= PGMMODE_MAX);
2512	Assert(enmGst > PGMMODE_INVALID && enmGst < PGMMODE_MAX);
2513	return pgmModeDataIndex(pgmModeToType(enmShw), pgmModeToType(enmGst));
2514	}
2515
2516
2517	/**
2518	* Calculates the max data index.
2519	* @returns The number of entries in the paging data array.
2520	*/
2521	DECLINLINE(unsigned) pgmModeDataMaxIndex(void)
2522	{
2523	return pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_AMD64) + 1;
2524	}
2525
2526
2527	/**
2528	* Initializes the paging mode data kept in PGM::paModeData.
2529	*
2530	* @param pVM The VM handle.
2531	* @param fResolveGCAndR0 Indicate whether or not GC and Ring-0 symbols can be resolved now.
2532	* This is used early in the init process to avoid trouble with PDM
2533	* not being initialized yet.
2534	*/
2535	static int pgmR3ModeDataInit(PVM pVM, bool fResolveGCAndR0)
2536	{
2537	PPGMMODEDATA pModeData;
2538	int rc;
2539
2540	/*
2541	* Allocate the array on the first call.
2542	*/
2543	if (!pVM->pgm.s.paModeData)
2544	{
2545	pVM->pgm.s.paModeData = (PPGMMODEDATA)MMR3HeapAllocZ(pVM, MM_TAG_PGM, sizeof(PGMMODEDATA) * pgmModeDataMaxIndex());
2546	AssertReturn(pVM->pgm.s.paModeData, VERR_NO_MEMORY);
2547	}
2548
2549	/*
2550	* Initialize the array entries.
2551	*/
2552	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_32BIT, PGM_TYPE_REAL)];
2553	pModeData->uShwType = PGM_TYPE_32BIT;
2554	pModeData->uGstType = PGM_TYPE_REAL;
2555	rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2556	rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2557	rc = PGM_BTH_NAME_32BIT_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2558
2559	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_32BIT, PGMMODE_PROTECTED)];
2560	pModeData->uShwType = PGM_TYPE_32BIT;
2561	pModeData->uGstType = PGM_TYPE_PROT;
2562	rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2563	rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2564	rc = PGM_BTH_NAME_32BIT_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2565
2566	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_32BIT, PGM_TYPE_32BIT)];
2567	pModeData->uShwType = PGM_TYPE_32BIT;
2568	pModeData->uGstType = PGM_TYPE_32BIT;
2569	rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2570	rc = PGM_GST_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2571	rc = PGM_BTH_NAME_32BIT_32BIT(InitData)(pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2572
2573	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_REAL)];
2574	pModeData->uShwType = PGM_TYPE_PAE;
2575	pModeData->uGstType = PGM_TYPE_REAL;
2576	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2577	rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2578	rc = PGM_BTH_NAME_PAE_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2579
2580	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_PROT)];
2581	pModeData->uShwType = PGM_TYPE_PAE;
2582	pModeData->uGstType = PGM_TYPE_PROT;
2583	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2584	rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2585	rc = PGM_BTH_NAME_PAE_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2586
2587	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_32BIT)];
2588	pModeData->uShwType = PGM_TYPE_PAE;
2589	pModeData->uGstType = PGM_TYPE_32BIT;
2590	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2591	rc = PGM_GST_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2592	rc = PGM_BTH_NAME_PAE_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2593
2594	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_PAE)];
2595	pModeData->uShwType = PGM_TYPE_PAE;
2596	pModeData->uGstType = PGM_TYPE_PAE;
2597	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2598	rc = PGM_GST_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2599	rc = PGM_BTH_NAME_PAE_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2600
2601	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_AMD64, PGM_TYPE_AMD64)];
2602	pModeData->uShwType = PGM_TYPE_AMD64;
2603	pModeData->uGstType = PGM_TYPE_AMD64;
2604	rc = PGM_SHW_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2605	rc = PGM_GST_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2606	rc = PGM_BTH_NAME_AMD64_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2607
2608	/* The nested paging mode. */
2609	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_REAL)];
2610	pModeData->uShwType = PGM_TYPE_NESTED;
2611	pModeData->uGstType = PGM_TYPE_REAL;
2612	rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2613	rc = PGM_BTH_NAME_NESTED_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2614
2615	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGMMODE_PROTECTED)];
2616	pModeData->uShwType = PGM_TYPE_NESTED;
2617	pModeData->uGstType = PGM_TYPE_PROT;
2618	rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2619	rc = PGM_BTH_NAME_NESTED_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2620
2621	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_32BIT)];
2622	pModeData->uShwType = PGM_TYPE_NESTED;
2623	pModeData->uGstType = PGM_TYPE_32BIT;
2624	rc = PGM_GST_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2625	rc = PGM_BTH_NAME_NESTED_32BIT(InitData)(pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2626
2627	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_PAE)];
2628	pModeData->uShwType = PGM_TYPE_NESTED;
2629	pModeData->uGstType = PGM_TYPE_PAE;
2630	rc = PGM_GST_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2631	rc = PGM_BTH_NAME_NESTED_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2632
2633	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_AMD64)];
2634	pModeData->uShwType = PGM_TYPE_NESTED;
2635	pModeData->uGstType = PGM_TYPE_AMD64;
2636	rc = PGM_GST_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2637	rc = PGM_BTH_NAME_NESTED_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2638
2639	/* The shadow part of the nested callback mode depends on the host paging mode (AMD-V only). */
2640	switch(pVM->pgm.s.enmHostMode)
2641	{
2642	case SUPPAGINGMODE_32_BIT:
2643	case SUPPAGINGMODE_32_BIT_GLOBAL:
2644	for (unsigned i=PGM_TYPE_REAL;i<=PGM_TYPE_AMD64;i++)
2645	{
2646	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, i)];
2647	rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2648	}
2649	break;
2650
2651	case SUPPAGINGMODE_PAE:
2652	case SUPPAGINGMODE_PAE_NX:
2653	case SUPPAGINGMODE_PAE_GLOBAL:
2654	case SUPPAGINGMODE_PAE_GLOBAL_NX:
2655	for (unsigned i=PGM_TYPE_REAL;i<=PGM_TYPE_AMD64;i++)
2656	{
2657	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, i)];
2658	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2659	}
2660	break;
2661
2662	case SUPPAGINGMODE_AMD64:
2663	case SUPPAGINGMODE_AMD64_GLOBAL:
2664	case SUPPAGINGMODE_AMD64_NX:
2665	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
2666	for (unsigned i=PGM_TYPE_REAL;i<=PGM_TYPE_AMD64;i++)
2667	{
2668	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, i)];
2669	rc = PGM_SHW_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2670	}
2671	break;
2672	default:
2673	AssertFailed();
2674	break;
2675	}
2676	return VINF_SUCCESS;
2677	}
2678
2679
2680	/**
2681	* Switch to different (or relocated in the relocate case) mode data.
2682	*
2683	* @param pVM The VM handle.
2684	* @param enmShw The the shadow paging mode.
2685	* @param enmGst The the guest paging mode.
2686	*/
2687	static void pgmR3ModeDataSwitch(PVM pVM, PGMMODE enmShw, PGMMODE enmGst)
2688	{
2689	PPGMMODEDATA pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndexByMode(enmShw, enmGst)];
2690
2691	Assert(pModeData->uGstType == pgmModeToType(enmGst));
2692	Assert(pModeData->uShwType == pgmModeToType(enmShw));
2693
2694	/* shadow */
2695	pVM->pgm.s.pfnR3ShwRelocate = pModeData->pfnR3ShwRelocate;
2696	pVM->pgm.s.pfnR3ShwExit = pModeData->pfnR3ShwExit;
2697	pVM->pgm.s.pfnR3ShwGetPage = pModeData->pfnR3ShwGetPage;
2698	Assert(pVM->pgm.s.pfnR3ShwGetPage);
2699	pVM->pgm.s.pfnR3ShwModifyPage = pModeData->pfnR3ShwModifyPage;
2700
2701	pVM->pgm.s.pfnGCShwGetPage = pModeData->pfnGCShwGetPage;
2702	pVM->pgm.s.pfnGCShwModifyPage = pModeData->pfnGCShwModifyPage;
2703
2704	pVM->pgm.s.pfnR0ShwGetPage = pModeData->pfnR0ShwGetPage;
2705	pVM->pgm.s.pfnR0ShwModifyPage = pModeData->pfnR0ShwModifyPage;
2706
2707
2708	/* guest */
2709	pVM->pgm.s.pfnR3GstRelocate = pModeData->pfnR3GstRelocate;
2710	pVM->pgm.s.pfnR3GstExit = pModeData->pfnR3GstExit;
2711	pVM->pgm.s.pfnR3GstGetPage = pModeData->pfnR3GstGetPage;
2712	Assert(pVM->pgm.s.pfnR3GstGetPage);
2713	pVM->pgm.s.pfnR3GstModifyPage = pModeData->pfnR3GstModifyPage;
2714	pVM->pgm.s.pfnR3GstGetPDE = pModeData->pfnR3GstGetPDE;
2715	pVM->pgm.s.pfnR3GstMonitorCR3 = pModeData->pfnR3GstMonitorCR3;
2716	pVM->pgm.s.pfnR3GstUnmonitorCR3 = pModeData->pfnR3GstUnmonitorCR3;
2717	pVM->pgm.s.pfnR3GstMapCR3 = pModeData->pfnR3GstMapCR3;
2718	pVM->pgm.s.pfnR3GstUnmapCR3 = pModeData->pfnR3GstUnmapCR3;
2719	pVM->pgm.s.pfnR3GstWriteHandlerCR3 = pModeData->pfnR3GstWriteHandlerCR3;
2720	pVM->pgm.s.pszR3GstWriteHandlerCR3 = pModeData->pszR3GstWriteHandlerCR3;
2721	pVM->pgm.s.pfnR3GstPAEWriteHandlerCR3 = pModeData->pfnR3GstPAEWriteHandlerCR3;
2722	pVM->pgm.s.pszR3GstPAEWriteHandlerCR3 = pModeData->pszR3GstPAEWriteHandlerCR3;
2723
2724	pVM->pgm.s.pfnGCGstGetPage = pModeData->pfnGCGstGetPage;
2725	pVM->pgm.s.pfnGCGstModifyPage = pModeData->pfnGCGstModifyPage;
2726	pVM->pgm.s.pfnGCGstGetPDE = pModeData->pfnGCGstGetPDE;
2727	pVM->pgm.s.pfnGCGstMonitorCR3 = pModeData->pfnGCGstMonitorCR3;
2728	pVM->pgm.s.pfnGCGstUnmonitorCR3 = pModeData->pfnGCGstUnmonitorCR3;
2729	pVM->pgm.s.pfnGCGstMapCR3 = pModeData->pfnGCGstMapCR3;
2730	pVM->pgm.s.pfnGCGstUnmapCR3 = pModeData->pfnGCGstUnmapCR3;
2731	pVM->pgm.s.pfnGCGstWriteHandlerCR3 = pModeData->pfnGCGstWriteHandlerCR3;
2732	pVM->pgm.s.pfnGCGstPAEWriteHandlerCR3 = pModeData->pfnGCGstPAEWriteHandlerCR3;
2733
2734	pVM->pgm.s.pfnR0GstGetPage = pModeData->pfnR0GstGetPage;
2735	pVM->pgm.s.pfnR0GstModifyPage = pModeData->pfnR0GstModifyPage;
2736	pVM->pgm.s.pfnR0GstGetPDE = pModeData->pfnR0GstGetPDE;
2737	pVM->pgm.s.pfnR0GstMonitorCR3 = pModeData->pfnR0GstMonitorCR3;
2738	pVM->pgm.s.pfnR0GstUnmonitorCR3 = pModeData->pfnR0GstUnmonitorCR3;
2739	pVM->pgm.s.pfnR0GstMapCR3 = pModeData->pfnR0GstMapCR3;
2740	pVM->pgm.s.pfnR0GstUnmapCR3 = pModeData->pfnR0GstUnmapCR3;
2741	pVM->pgm.s.pfnR0GstWriteHandlerCR3 = pModeData->pfnR0GstWriteHandlerCR3;
2742	pVM->pgm.s.pfnR0GstPAEWriteHandlerCR3 = pModeData->pfnR0GstPAEWriteHandlerCR3;
2743
2744
2745	/* both */
2746	pVM->pgm.s.pfnR3BthRelocate = pModeData->pfnR3BthRelocate;
2747	pVM->pgm.s.pfnR3BthTrap0eHandler = pModeData->pfnR3BthTrap0eHandler;
2748	pVM->pgm.s.pfnR3BthInvalidatePage = pModeData->pfnR3BthInvalidatePage;
2749	pVM->pgm.s.pfnR3BthSyncCR3 = pModeData->pfnR3BthSyncCR3;
2750	Assert(pVM->pgm.s.pfnR3BthSyncCR3);
2751	pVM->pgm.s.pfnR3BthSyncPage = pModeData->pfnR3BthSyncPage;
2752	pVM->pgm.s.pfnR3BthPrefetchPage = pModeData->pfnR3BthPrefetchPage;
2753	pVM->pgm.s.pfnR3BthVerifyAccessSyncPage = pModeData->pfnR3BthVerifyAccessSyncPage;
2754	#ifdef VBOX_STRICT
2755	pVM->pgm.s.pfnR3BthAssertCR3 = pModeData->pfnR3BthAssertCR3;
2756	#endif
2757
2758	pVM->pgm.s.pfnGCBthTrap0eHandler = pModeData->pfnGCBthTrap0eHandler;
2759	pVM->pgm.s.pfnGCBthInvalidatePage = pModeData->pfnGCBthInvalidatePage;
2760	pVM->pgm.s.pfnGCBthSyncCR3 = pModeData->pfnGCBthSyncCR3;
2761	pVM->pgm.s.pfnGCBthSyncPage = pModeData->pfnGCBthSyncPage;
2762	pVM->pgm.s.pfnGCBthPrefetchPage = pModeData->pfnGCBthPrefetchPage;
2763	pVM->pgm.s.pfnGCBthVerifyAccessSyncPage = pModeData->pfnGCBthVerifyAccessSyncPage;
2764	#ifdef VBOX_STRICT
2765	pVM->pgm.s.pfnGCBthAssertCR3 = pModeData->pfnGCBthAssertCR3;
2766	#endif
2767
2768	pVM->pgm.s.pfnR0BthTrap0eHandler = pModeData->pfnR0BthTrap0eHandler;
2769	pVM->pgm.s.pfnR0BthInvalidatePage = pModeData->pfnR0BthInvalidatePage;
2770	pVM->pgm.s.pfnR0BthSyncCR3 = pModeData->pfnR0BthSyncCR3;
2771	pVM->pgm.s.pfnR0BthSyncPage = pModeData->pfnR0BthSyncPage;
2772	pVM->pgm.s.pfnR0BthPrefetchPage = pModeData->pfnR0BthPrefetchPage;
2773	pVM->pgm.s.pfnR0BthVerifyAccessSyncPage = pModeData->pfnR0BthVerifyAccessSyncPage;
2774	#ifdef VBOX_STRICT
2775	pVM->pgm.s.pfnR0BthAssertCR3 = pModeData->pfnR0BthAssertCR3;
2776	#endif
2777	}
2778
2779
2780	#ifdef DEBUG_bird
2781	#include <stdlib.h> /* getenv() remove me! */
2782	#endif
2783
2784	/**
2785	* Calculates the shadow paging mode.
2786	*
2787	* @returns The shadow paging mode.
2788	* @param pVM VM handle.
2789	* @param enmGuestMode The guest mode.
2790	* @param enmHostMode The host mode.
2791	* @param enmShadowMode The current shadow mode.
2792	* @param penmSwitcher Where to store the switcher to use.
2793	* VMMSWITCHER_INVALID means no change.
2794	*/
2795	static PGMMODE pgmR3CalcShadowMode(PVM pVM, PGMMODE enmGuestMode, SUPPAGINGMODE enmHostMode, PGMMODE enmShadowMode, VMMSWITCHER *penmSwitcher)
2796	{
2797	VMMSWITCHER enmSwitcher = VMMSWITCHER_INVALID;
2798	switch (enmGuestMode)
2799	{
2800	/*
2801	* When switching to real or protected mode we don't change
2802	* anything since it's likely that we'll switch back pretty soon.
2803	*
2804	* During pgmR3InitPaging we'll end up here with PGMMODE_INVALID
2805	* and is supposed to determine which shadow paging and switcher to
2806	* use during init.
2807	*/
2808	case PGMMODE_REAL:
2809	case PGMMODE_PROTECTED:
2810	if ( enmShadowMode != PGMMODE_INVALID
2811	&& !HWACCMIsEnabled(pVM) /* always switch in hwaccm mode! */)
2812	break; /* (no change) */
2813
2814	switch (enmHostMode)
2815	{
2816	case SUPPAGINGMODE_32_BIT:
2817	case SUPPAGINGMODE_32_BIT_GLOBAL:
2818	enmShadowMode = PGMMODE_32_BIT;
2819	enmSwitcher = VMMSWITCHER_32_TO_32;
2820	break;
2821
2822	case SUPPAGINGMODE_PAE:
2823	case SUPPAGINGMODE_PAE_NX:
2824	case SUPPAGINGMODE_PAE_GLOBAL:
2825	case SUPPAGINGMODE_PAE_GLOBAL_NX:
2826	enmShadowMode = PGMMODE_PAE;
2827	enmSwitcher = VMMSWITCHER_PAE_TO_PAE;
2828	#ifdef DEBUG_bird
2829	if (getenv("VBOX_32BIT"))
2830	{
2831	enmShadowMode = PGMMODE_32_BIT;
2832	enmSwitcher = VMMSWITCHER_PAE_TO_32;
2833	}
2834	#endif
2835	break;
2836
2837	case SUPPAGINGMODE_AMD64:
2838	case SUPPAGINGMODE_AMD64_GLOBAL:
2839	case SUPPAGINGMODE_AMD64_NX:
2840	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
2841	enmShadowMode = PGMMODE_PAE;
2842	enmSwitcher = VMMSWITCHER_AMD64_TO_PAE;
2843	break;
2844
2845	default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
2846	}
2847	break;
2848
2849	case PGMMODE_32_BIT:
2850	switch (enmHostMode)
2851	{
2852	case SUPPAGINGMODE_32_BIT:
2853	case SUPPAGINGMODE_32_BIT_GLOBAL:
2854	enmShadowMode = PGMMODE_32_BIT;
2855	enmSwitcher = VMMSWITCHER_32_TO_32;
2856	break;
2857
2858	case SUPPAGINGMODE_PAE:
2859	case SUPPAGINGMODE_PAE_NX:
2860	case SUPPAGINGMODE_PAE_GLOBAL:
2861	case SUPPAGINGMODE_PAE_GLOBAL_NX:
2862	enmShadowMode = PGMMODE_PAE;
2863	enmSwitcher = VMMSWITCHER_PAE_TO_PAE;
2864	#ifdef DEBUG_bird
2865	if (getenv("VBOX_32BIT"))
2866	{
2867	enmShadowMode = PGMMODE_32_BIT;
2868	enmSwitcher = VMMSWITCHER_PAE_TO_32;
2869	}
2870	#endif
2871	break;
2872
2873	case SUPPAGINGMODE_AMD64:
2874	case SUPPAGINGMODE_AMD64_GLOBAL:
2875	case SUPPAGINGMODE_AMD64_NX:
2876	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
2877	enmShadowMode = PGMMODE_PAE;
2878	enmSwitcher = VMMSWITCHER_AMD64_TO_PAE;
2879	break;
2880
2881	default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
2882	}
2883	break;
2884
2885	case PGMMODE_PAE:
2886	case PGMMODE_PAE_NX: /** @todo This might require more switchers and guest+both modes. */
2887	switch (enmHostMode)
2888	{
2889	case SUPPAGINGMODE_32_BIT:
2890	case SUPPAGINGMODE_32_BIT_GLOBAL:
2891	enmShadowMode = PGMMODE_PAE;
2892	enmSwitcher = VMMSWITCHER_32_TO_PAE;
2893	break;
2894
2895	case SUPPAGINGMODE_PAE:
2896	case SUPPAGINGMODE_PAE_NX:
2897	case SUPPAGINGMODE_PAE_GLOBAL:
2898	case SUPPAGINGMODE_PAE_GLOBAL_NX:
2899	enmShadowMode = PGMMODE_PAE;
2900	enmSwitcher = VMMSWITCHER_PAE_TO_PAE;
2901	break;
2902
2903	case SUPPAGINGMODE_AMD64:
2904	case SUPPAGINGMODE_AMD64_GLOBAL:
2905	case SUPPAGINGMODE_AMD64_NX:
2906	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
2907	enmShadowMode = PGMMODE_PAE;
2908	enmSwitcher = VMMSWITCHER_AMD64_TO_PAE;
2909	break;
2910
2911	default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
2912	}
2913	break;
2914
2915	case PGMMODE_AMD64:
2916	case PGMMODE_AMD64_NX:
2917	switch (enmHostMode)
2918	{
2919	case SUPPAGINGMODE_32_BIT:
2920	case SUPPAGINGMODE_32_BIT_GLOBAL:
2921	enmShadowMode = PGMMODE_PAE;
2922	enmSwitcher = VMMSWITCHER_32_TO_AMD64;
2923	break;
2924
2925	case SUPPAGINGMODE_PAE:
2926	case SUPPAGINGMODE_PAE_NX:
2927	case SUPPAGINGMODE_PAE_GLOBAL:
2928	case SUPPAGINGMODE_PAE_GLOBAL_NX:
2929	enmShadowMode = PGMMODE_PAE;
2930	enmSwitcher = VMMSWITCHER_PAE_TO_AMD64;
2931	break;
2932
2933	case SUPPAGINGMODE_AMD64:
2934	case SUPPAGINGMODE_AMD64_GLOBAL:
2935	case SUPPAGINGMODE_AMD64_NX:
2936	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
2937	enmShadowMode = PGMMODE_AMD64;
2938	enmSwitcher = VMMSWITCHER_AMD64_TO_AMD64;
2939	break;
2940
2941	default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
2942	}
2943	break;
2944
2945
2946	default:
2947	AssertReleaseMsgFailed(("enmGuestMode=%d\n", enmGuestMode));
2948	return PGMMODE_INVALID;
2949	}
2950	/* Override the shadow mode is nested paging is active. */
2951	if (HWACCMIsNestedPagingActive(pVM))
2952	enmShadowMode = PGMMODE_NESTED;
2953
2954	*penmSwitcher = enmSwitcher;
2955	return enmShadowMode;
2956	}
2957
2958	#ifdef LOG_ENABLED
2959	/**
2960	* Return the string corresponding to the guest mode
2961	*
2962	* @returns string
2963	* @param enmGuestMode The guest mode.
2964	*/
2965	const char *pgmr3GuestModeString(PGMMODE enmGuestMode)
2966	{
2967	switch(enmGuestMode)
2968	{
2969	case PGMMODE_REAL:
2970	return "Real mode";
2971
2972	case PGMMODE_PROTECTED:
2973	return "Protected mode without paging";
2974
2975	case PGMMODE_32_BIT:
2976	return "32 bits protected mode";
2977
2978	case PGMMODE_PAE:
2979	return "PAE";
2980
2981	case PGMMODE_PAE_NX:
2982	return "PAE + NX";
2983
2984	case PGMMODE_AMD64:
2985	return "AMD64";
2986
2987	case PGMMODE_AMD64_NX:
2988	return "AMD64 + NX";
2989
2990	case PGMMODE_NESTED:
2991	return "Nested";
2992
2993	default:
2994	return "Unknown";
2995	}
2996	}
2997	#endif
2998
2999	/**
3000	* Performs the actual mode change.
3001	* This is called by PGMChangeMode and pgmR3InitPaging().
3002	*
3003	* @returns VBox status code.
3004	* @param pVM VM handle.
3005	* @param enmGuestMode The new guest mode. This is assumed to be different from
3006	* the current mode.
3007	*/
3008	PGMR3DECL(int) PGMR3ChangeMode(PVM pVM, PGMMODE enmGuestMode)
3009	{
3010	LogFlow(("PGMR3ChangeMode: Guest mode: %s -> %s\n", pgmr3GuestModeString(pVM->pgm.s.enmGuestMode), pgmr3GuestModeString(enmGuestMode)));
3011	STAM_REL_COUNTER_INC(&pVM->pgm.s.cGuestModeChanges);
3012
3013	/*
3014	* Calc the shadow mode and switcher.
3015	*/
3016	VMMSWITCHER enmSwitcher;
3017	PGMMODE enmShadowMode = pgmR3CalcShadowMode(pVM, enmGuestMode, pVM->pgm.s.enmHostMode, pVM->pgm.s.enmShadowMode, &enmSwitcher);
3018	if (enmSwitcher != VMMSWITCHER_INVALID)
3019	{
3020	/*
3021	* Select new switcher.
3022	*/
3023	int rc = VMMR3SelectSwitcher(pVM, enmSwitcher);
3024	if (VBOX_FAILURE(rc))
3025	{
3026	AssertReleaseMsgFailed(("VMMR3SelectSwitcher(%d) -> %Vrc\n", enmSwitcher, rc));
3027	return rc;
3028	}
3029	}
3030
3031	/*
3032	* Exit old mode(s).
3033	*/
3034	/* shadow */
3035	if (enmShadowMode != pVM->pgm.s.enmShadowMode)
3036	{
3037	LogFlow(("PGMR3ChangeMode: Shadow mode: %s -> %s\n", pgmr3GuestModeString(pVM->pgm.s.enmShadowMode), pgmr3GuestModeString(enmShadowMode)));
3038	if (PGM_SHW_PFN(Exit, pVM))
3039	{
3040	int rc = PGM_SHW_PFN(Exit, pVM)(pVM);
3041	if (VBOX_FAILURE(rc))
3042	{
3043	AssertMsgFailed(("Exit failed for shadow mode %d: %Vrc\n", pVM->pgm.s.enmShadowMode, rc));
3044	return rc;
3045	}
3046	}
3047
3048	}
3049
3050	/* guest */
3051	if (PGM_GST_PFN(Exit, pVM))
3052	{
3053	int rc = PGM_GST_PFN(Exit, pVM)(pVM);
3054	if (VBOX_FAILURE(rc))
3055	{
3056	AssertMsgFailed(("Exit failed for guest mode %d: %Vrc\n", pVM->pgm.s.enmGuestMode, rc));
3057	return rc;
3058	}
3059	}
3060
3061	/*
3062	* Load new paging mode data.
3063	*/
3064	pgmR3ModeDataSwitch(pVM, enmShadowMode, enmGuestMode);
3065
3066	/*
3067	* Enter new shadow mode (if changed).
3068	*/
3069	if (enmShadowMode != pVM->pgm.s.enmShadowMode)
3070	{
3071	int rc;
3072	pVM->pgm.s.enmShadowMode = enmShadowMode;
3073	switch (enmShadowMode)
3074	{
3075	case PGMMODE_32_BIT:
3076	rc = PGM_SHW_NAME_32BIT(Enter)(pVM);
3077	break;
3078	case PGMMODE_PAE:
3079	case PGMMODE_PAE_NX:
3080	rc = PGM_SHW_NAME_PAE(Enter)(pVM);
3081	break;
3082	case PGMMODE_AMD64:
3083	case PGMMODE_AMD64_NX:
3084	rc = PGM_SHW_NAME_AMD64(Enter)(pVM);
3085	break;
3086	case PGMMODE_NESTED:
3087	rc = PGM_SHW_NAME_NESTED(Enter)(pVM);
3088	break;
3089	case PGMMODE_REAL:
3090	case PGMMODE_PROTECTED:
3091	default:
3092	AssertReleaseMsgFailed(("enmShadowMode=%d\n", enmShadowMode));
3093	return VERR_INTERNAL_ERROR;
3094	}
3095	if (VBOX_FAILURE(rc))
3096	{
3097	AssertReleaseMsgFailed(("Entering enmShadowMode=%d failed: %Vrc\n", enmShadowMode, rc));
3098	pVM->pgm.s.enmShadowMode = PGMMODE_INVALID;
3099	return rc;
3100	}
3101	}
3102
3103	/*
3104	* Enter the new guest and shadow+guest modes.
3105	*/
3106	int rc = -1;
3107	int rc2 = -1;
3108	RTGCPHYS GCPhysCR3 = NIL_RTGCPHYS;
3109	pVM->pgm.s.enmGuestMode = enmGuestMode;
3110	switch (enmGuestMode)
3111	{
3112	case PGMMODE_REAL:
3113	rc = PGM_GST_NAME_REAL(Enter)(pVM, NIL_RTGCPHYS);
3114	switch (pVM->pgm.s.enmShadowMode)
3115	{
3116	case PGMMODE_32_BIT:
3117	rc2 = PGM_BTH_NAME_32BIT_REAL(Enter)(pVM, NIL_RTGCPHYS);
3118	break;
3119	case PGMMODE_PAE:
3120	case PGMMODE_PAE_NX:
3121	rc2 = PGM_BTH_NAME_PAE_REAL(Enter)(pVM, NIL_RTGCPHYS);
3122	break;
3123	case PGMMODE_NESTED:
3124	rc2 = PGM_BTH_NAME_NESTED_REAL(Enter)(pVM, NIL_RTGCPHYS);
3125	break;
3126	case PGMMODE_AMD64:
3127	case PGMMODE_AMD64_NX:
3128	AssertMsgFailed(("Should use PAE shadow mode!\n"));
3129	default: AssertFailed(); break;
3130	}
3131	break;
3132
3133	case PGMMODE_PROTECTED:
3134	rc = PGM_GST_NAME_PROT(Enter)(pVM, NIL_RTGCPHYS);
3135	switch (pVM->pgm.s.enmShadowMode)
3136	{
3137	case PGMMODE_32_BIT:
3138	rc2 = PGM_BTH_NAME_32BIT_PROT(Enter)(pVM, NIL_RTGCPHYS);
3139	break;
3140	case PGMMODE_PAE:
3141	case PGMMODE_PAE_NX:
3142	rc2 = PGM_BTH_NAME_PAE_PROT(Enter)(pVM, NIL_RTGCPHYS);
3143	break;
3144	case PGMMODE_NESTED:
3145	rc2 = PGM_BTH_NAME_NESTED_PROT(Enter)(pVM, NIL_RTGCPHYS);
3146	break;
3147	case PGMMODE_AMD64:
3148	case PGMMODE_AMD64_NX:
3149	AssertMsgFailed(("Should use PAE shadow mode!\n"));
3150	default: AssertFailed(); break;
3151	}
3152	break;
3153
3154	case PGMMODE_32_BIT:
3155	GCPhysCR3 = CPUMGetGuestCR3(pVM) & X86_CR3_PAGE_MASK;
3156	rc = PGM_GST_NAME_32BIT(Enter)(pVM, GCPhysCR3);
3157	switch (pVM->pgm.s.enmShadowMode)
3158	{
3159	case PGMMODE_32_BIT:
3160	rc2 = PGM_BTH_NAME_32BIT_32BIT(Enter)(pVM, GCPhysCR3);
3161	break;
3162	case PGMMODE_PAE:
3163	case PGMMODE_PAE_NX:
3164	rc2 = PGM_BTH_NAME_PAE_32BIT(Enter)(pVM, GCPhysCR3);
3165	break;
3166	case PGMMODE_NESTED:
3167	rc2 = PGM_BTH_NAME_NESTED_32BIT(Enter)(pVM, GCPhysCR3);
3168	break;
3169	case PGMMODE_AMD64:
3170	case PGMMODE_AMD64_NX:
3171	AssertMsgFailed(("Should use PAE shadow mode!\n"));
3172	default: AssertFailed(); break;
3173	}
3174	break;
3175
3176	case PGMMODE_PAE_NX: /* VT-x/AMD-V only */
3177	Assert(HWACCMIsEnabled(pVM));
3178	/* no break */
3179
3180	case PGMMODE_PAE:
3181	{
3182	uint32_t u32Dummy, u32Features;
3183
3184	CPUMGetGuestCpuId(pVM, 1, &u32Dummy, &u32Dummy, &u32Dummy, &u32Features);
3185	if (!(u32Features & X86_CPUID_FEATURE_EDX_PAE))
3186	{
3187	/* Pause first, then inform Main. */
3188	rc = VMR3SuspendNoSave(pVM);
3189	AssertRC(rc);
3190
3191	VMSetRuntimeError(pVM, true, "PAEmode",
3192	N_("The guest is trying to switch to the PAE mode which is currently disabled by default in VirtualBox. Experimental PAE support can be enabled using the -pae option with VBoxManage."));
3193	/* we must return TRUE here otherwise the recompiler will assert */
3194	return VINF_SUCCESS;
3195	}
3196	GCPhysCR3 = CPUMGetGuestCR3(pVM) & X86_CR3_PAE_PAGE_MASK;
3197	rc = PGM_GST_NAME_PAE(Enter)(pVM, GCPhysCR3);
3198	switch (pVM->pgm.s.enmShadowMode)
3199	{
3200	case PGMMODE_PAE:
3201	case PGMMODE_PAE_NX:
3202	rc2 = PGM_BTH_NAME_PAE_PAE(Enter)(pVM, GCPhysCR3);
3203	break;
3204	case PGMMODE_NESTED:
3205	rc2 = PGM_BTH_NAME_NESTED_PAE(Enter)(pVM, GCPhysCR3);
3206	break;
3207	case PGMMODE_32_BIT:
3208	case PGMMODE_AMD64:
3209	case PGMMODE_AMD64_NX:
3210	AssertMsgFailed(("Should use PAE shadow mode!\n"));
3211	default: AssertFailed(); break;
3212	}
3213	break;
3214	}
3215
3216	case PGMMODE_AMD64_NX:
3217	case PGMMODE_AMD64:
3218	GCPhysCR3 = CPUMGetGuestCR3(pVM) & 0xfffffffffffff000ULL; /** @todo define this mask! */
3219	rc = PGM_GST_NAME_AMD64(Enter)(pVM, GCPhysCR3);
3220	switch (pVM->pgm.s.enmShadowMode)
3221	{
3222	case PGMMODE_AMD64:
3223	case PGMMODE_AMD64_NX:
3224	rc2 = PGM_BTH_NAME_AMD64_AMD64(Enter)(pVM, GCPhysCR3);
3225	break;
3226	case PGMMODE_NESTED:
3227	rc2 = PGM_BTH_NAME_NESTED_AMD64(Enter)(pVM, GCPhysCR3);
3228	break;
3229	case PGMMODE_32_BIT:
3230	case PGMMODE_PAE:
3231	case PGMMODE_PAE_NX:
3232	AssertMsgFailed(("Should use AMD64 shadow mode!\n"));
3233	default: AssertFailed(); break;
3234	}
3235	break;
3236
3237	default:
3238	AssertReleaseMsgFailed(("enmGuestMode=%d\n", enmGuestMode));
3239	rc = VERR_NOT_IMPLEMENTED;
3240	break;
3241	}
3242
3243	/* status codes. */
3244	AssertRC(rc);
3245	AssertRC(rc2);
3246	if (VBOX_SUCCESS(rc))
3247	{
3248	rc = rc2;
3249	if (VBOX_SUCCESS(rc)) /* no informational status codes. */
3250	rc = VINF_SUCCESS;
3251	}
3252
3253	/*
3254	* Notify SELM so it can update the TSSes with correct CR3s.
3255	*/
3256	SELMR3PagingModeChanged(pVM);
3257
3258	/* Notify HWACCM as well. */
3259	HWACCMR3PagingModeChanged(pVM, pVM->pgm.s.enmShadowMode);
3260	return rc;
3261	}
3262
3263
3264	/**
3265	* Dumps a PAE shadow page table.
3266	*
3267	* @returns VBox status code (VINF_SUCCESS).
3268	* @param pVM The VM handle.
3269	* @param pPT Pointer to the page table.
3270	* @param u64Address The virtual address of the page table starts.
3271	* @param fLongMode Set if this a long mode table; clear if it's a legacy mode table.
3272	* @param cMaxDepth The maxium depth.
3273	* @param pHlp Pointer to the output functions.
3274	*/
3275	static int pgmR3DumpHierarchyHCPaePT(PVM pVM, PX86PTPAE pPT, uint64_t u64Address, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
3276	{
3277	for (unsigned i = 0; i < ELEMENTS(pPT->a); i++)
3278	{
3279	X86PTEPAE Pte = pPT->a[i];
3280	if (Pte.n.u1Present)
3281	{
3282	pHlp->pfnPrintf(pHlp,
3283	fLongMode /P R S A D G WT CD AT NX 4M a p ? /
3284	? "%016llx 3 \| P %c %c %c %c %c %s %s %s %s 4K %c%c%c %016llx\n"
3285	: "%08llx 2 \| P %c %c %c %c %c %s %s %s %s 4K %c%c%c %016llx\n",
3286	u64Address + ((uint64_t)i << X86_PT_PAE_SHIFT),
3287	Pte.n.u1Write ? 'W' : 'R',
3288	Pte.n.u1User ? 'U' : 'S',
3289	Pte.n.u1Accessed ? 'A' : '-',
3290	Pte.n.u1Dirty ? 'D' : '-',
3291	Pte.n.u1Global ? 'G' : '-',
3292	Pte.n.u1WriteThru ? "WT" : "--",
3293	Pte.n.u1CacheDisable? "CD" : "--",
3294	Pte.n.u1PAT ? "AT" : "--",
3295	Pte.n.u1NoExecute ? "NX" : "--",
3296	Pte.u & PGM_PTFLAGS_TRACK_DIRTY ? 'd' : '-',
3297	Pte.u & RT_BIT(10) ? '1' : '0',
3298	Pte.u & PGM_PTFLAGS_CSAM_VALIDATED? 'v' : '-',
3299	Pte.u & X86_PTE_PAE_PG_MASK);
3300	}
3301	}
3302	return VINF_SUCCESS;
3303	}
3304
3305
3306	/**
3307	* Dumps a PAE shadow page directory table.
3308	*
3309	* @returns VBox status code (VINF_SUCCESS).
3310	* @param pVM The VM handle.
3311	* @param HCPhys The physical address of the page directory table.
3312	* @param u64Address The virtual address of the page table starts.
3313	* @param cr4 The CR4, PSE is currently used.
3314	* @param fLongMode Set if this a long mode table; clear if it's a legacy mode table.
3315	* @param cMaxDepth The maxium depth.
3316	* @param pHlp Pointer to the output functions.
3317	*/
3318	static int pgmR3DumpHierarchyHCPaePD(PVM pVM, RTHCPHYS HCPhys, uint64_t u64Address, uint32_t cr4, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
3319	{
3320	PX86PDPAE pPD = (PX86PDPAE)MMPagePhys2Page(pVM, HCPhys);
3321	if (!pPD)
3322	{
3323	pHlp->pfnPrintf(pHlp, "%0*llx error! Page directory at HCPhys=%#VHp was not found in the page pool!\n",
3324	fLongMode ? 16 : 8, u64Address, HCPhys);
3325	return VERR_INVALID_PARAMETER;
3326	}
3327	const bool fBigPagesSupported = fLongMode \|\| !!(cr4 & X86_CR4_PSE);
3328
3329	int rc = VINF_SUCCESS;
3330	for (unsigned i = 0; i < ELEMENTS(pPD->a); i++)
3331	{
3332	X86PDEPAE Pde = pPD->a[i];
3333	if (Pde.n.u1Present)
3334	{
3335	if (fBigPagesSupported && Pde.b.u1Size)
3336	pHlp->pfnPrintf(pHlp,
3337	fLongMode /P R S A D G WT CD AT NX 4M a p ? /
3338	? "%016llx 2 \| P %c %c %c %c %c %s %s %s %s 4M %c%c%c %016llx\n"
3339	: "%08llx 1 \| P %c %c %c %c %c %s %s %s %s 4M %c%c%c %016llx\n",
3340	u64Address + ((uint64_t)i << X86_PD_PAE_SHIFT),
3341	Pde.b.u1Write ? 'W' : 'R',
3342	Pde.b.u1User ? 'U' : 'S',
3343	Pde.b.u1Accessed ? 'A' : '-',
3344	Pde.b.u1Dirty ? 'D' : '-',
3345	Pde.b.u1Global ? 'G' : '-',
3346	Pde.b.u1WriteThru ? "WT" : "--",
3347	Pde.b.u1CacheDisable? "CD" : "--",
3348	Pde.b.u1PAT ? "AT" : "--",
3349	Pde.b.u1NoExecute ? "NX" : "--",
3350	Pde.u & RT_BIT_64(9) ? '1' : '0',
3351	Pde.u & PGM_PDFLAGS_MAPPING ? 'm' : '-',
3352	Pde.u & PGM_PDFLAGS_TRACK_DIRTY ? 'd' : '-',
3353	Pde.u & X86_PDE_PAE_PG_MASK);
3354	else
3355	{
3356	pHlp->pfnPrintf(pHlp,
3357	fLongMode /P R S A D G WT CD AT NX 4M a p ? /
3358	? "%016llx 2 \| P %c %c %c %c %c %s %s .. %s 4K %c%c%c %016llx\n"
3359	: "%08llx 1 \| P %c %c %c %c %c %s %s .. %s 4K %c%c%c %016llx\n",
3360	u64Address + ((uint64_t)i << X86_PD_PAE_SHIFT),
3361	Pde.n.u1Write ? 'W' : 'R',
3362	Pde.n.u1User ? 'U' : 'S',
3363	Pde.n.u1Accessed ? 'A' : '-',
3364	Pde.n.u1Reserved0 ? '?' : '.', /* ignored */
3365	Pde.n.u1Reserved1 ? '?' : '.', /* ignored */
3366	Pde.n.u1WriteThru ? "WT" : "--",
3367	Pde.n.u1CacheDisable? "CD" : "--",
3368	Pde.n.u1NoExecute ? "NX" : "--",
3369	Pde.u & RT_BIT_64(9) ? '1' : '0',
3370	Pde.u & PGM_PDFLAGS_MAPPING ? 'm' : '-',
3371	Pde.u & PGM_PDFLAGS_TRACK_DIRTY ? 'd' : '-',
3372	Pde.u & X86_PDE_PAE_PG_MASK);
3373	if (cMaxDepth >= 1)
3374	{
3375	/** @todo what about using the page pool for mapping PTs? */
3376	uint64_t u64AddressPT = u64Address + ((uint64_t)i << X86_PD_PAE_SHIFT);
3377	RTHCPHYS HCPhysPT = Pde.u & X86_PDE_PAE_PG_MASK;
3378	PX86PTPAE pPT = NULL;
3379	if (!(Pde.u & PGM_PDFLAGS_MAPPING))
3380	pPT = (PX86PTPAE)MMPagePhys2Page(pVM, HCPhysPT);
3381	else
3382	{
3383	for (PPGMMAPPING pMap = pVM->pgm.s.pMappingsR3; pMap; pMap = pMap->pNextR3)
3384	{
3385	uint64_t off = u64AddressPT - pMap->GCPtr;
3386	if (off < pMap->cb)
3387	{
3388	const int iPDE = (uint32_t)(off >> X86_PD_SHIFT);
3389	const int iSub = (int)((off >> X86_PD_PAE_SHIFT) & 1); /* MSC is a pain sometimes */
3390	if ((iSub ? pMap->aPTs[iPDE].HCPhysPaePT1 : pMap->aPTs[iPDE].HCPhysPaePT0) != HCPhysPT)
3391	pHlp->pfnPrintf(pHlp, "%0*llx error! Mapping error! PT %d has HCPhysPT=%VHp not %VHp is in the PD.\n",
3392	fLongMode ? 16 : 8, u64AddressPT, iPDE,
3393	iSub ? pMap->aPTs[iPDE].HCPhysPaePT1 : pMap->aPTs[iPDE].HCPhysPaePT0, HCPhysPT);
3394	pPT = &pMap->aPTs[iPDE].paPaePTsR3[iSub];
3395	}
3396	}
3397	}
3398	int rc2 = VERR_INVALID_PARAMETER;
3399	if (pPT)
3400	rc2 = pgmR3DumpHierarchyHCPaePT(pVM, pPT, u64AddressPT, fLongMode, cMaxDepth - 1, pHlp);
3401	else
3402	pHlp->pfnPrintf(pHlp, "%0*llx error! Page table at HCPhys=%#VHp was not found in the page pool!\n",
3403	fLongMode ? 16 : 8, u64AddressPT, HCPhysPT);
3404	if (rc2 < rc && VBOX_SUCCESS(rc))
3405	rc = rc2;
3406	}
3407	}
3408	}
3409	}
3410	return rc;
3411	}
3412
3413
3414	/**
3415	* Dumps a PAE shadow page directory pointer table.
3416	*
3417	* @returns VBox status code (VINF_SUCCESS).
3418	* @param pVM The VM handle.
3419	* @param HCPhys The physical address of the page directory pointer table.
3420	* @param u64Address The virtual address of the page table starts.
3421	* @param cr4 The CR4, PSE is currently used.
3422	* @param fLongMode Set if this a long mode table; clear if it's a legacy mode table.
3423	* @param cMaxDepth The maxium depth.
3424	* @param pHlp Pointer to the output functions.
3425	*/
3426	static int pgmR3DumpHierarchyHCPaePDPT(PVM pVM, RTHCPHYS HCPhys, uint64_t u64Address, uint32_t cr4, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
3427	{
3428	PX86PDPT pPDPT = (PX86PDPT)MMPagePhys2Page(pVM, HCPhys);
3429	if (!pPDPT)
3430	{
3431	pHlp->pfnPrintf(pHlp, "%0*llx error! Page directory pointer table at HCPhys=%#VHp was not found in the page pool!\n",
3432	fLongMode ? 16 : 8, u64Address, HCPhys);
3433	return VERR_INVALID_PARAMETER;
3434	}
3435
3436	int rc = VINF_SUCCESS;
3437	const unsigned c = fLongMode ? ELEMENTS(pPDPT->a) : X86_PG_PAE_PDPE_ENTRIES;
3438	for (unsigned i = 0; i < c; i++)
3439	{
3440	X86PDPE Pdpe = pPDPT->a[i];
3441	if (Pdpe.n.u1Present)
3442	{
3443	if (fLongMode)
3444	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a p ? /
3445	"%016llx 1 \| P %c %c %c %c %c %s %s %s %s .. %c%c%c %016llx\n",
3446	u64Address + ((uint64_t)i << X86_PDPT_SHIFT),
3447	Pdpe.lm.u1Write ? 'W' : 'R',
3448	Pdpe.lm.u1User ? 'U' : 'S',
3449	Pdpe.lm.u1Accessed ? 'A' : '-',
3450	Pdpe.lm.u3Reserved & 1? '?' : '.', /* ignored */
3451	Pdpe.lm.u3Reserved & 4? '!' : '.', /* mbz */
3452	Pdpe.lm.u1WriteThru ? "WT" : "--",
3453	Pdpe.lm.u1CacheDisable? "CD" : "--",
3454	Pdpe.lm.u3Reserved & 2? "!" : "..",/* mbz */
3455	Pdpe.lm.u1NoExecute ? "NX" : "--",
3456	Pdpe.u & RT_BIT(9) ? '1' : '0',
3457	Pdpe.u & PGM_PLXFLAGS_PERMANENT ? 'p' : '-',
3458	Pdpe.u & RT_BIT(11) ? '1' : '0',
3459	Pdpe.u & X86_PDPE_PG_MASK);
3460	else
3461	pHlp->pfnPrintf(pHlp, /P G WT CD AT NX 4M a p ? /
3462	"%08x 0 \| P %c %s %s %s %s .. %c%c%c %016llx\n",
3463	i << X86_PDPT_SHIFT,
3464	Pdpe.n.u4Reserved & 1? '!' : '.', /* mbz */
3465	Pdpe.n.u4Reserved & 4? '!' : '.', /* mbz */
3466	Pdpe.n.u1WriteThru ? "WT" : "--",
3467	Pdpe.n.u1CacheDisable? "CD" : "--",
3468	Pdpe.n.u4Reserved & 2? "!" : "..",/* mbz */
3469	Pdpe.u & RT_BIT(9) ? '1' : '0',
3470	Pdpe.u & PGM_PLXFLAGS_PERMANENT ? 'p' : '-',
3471	Pdpe.u & RT_BIT(11) ? '1' : '0',
3472	Pdpe.u & X86_PDPE_PG_MASK);
3473	if (cMaxDepth >= 1)
3474	{
3475	int rc2 = pgmR3DumpHierarchyHCPaePD(pVM, Pdpe.u & X86_PDPE_PG_MASK, u64Address + ((uint64_t)i << X86_PDPT_SHIFT),
3476	cr4, fLongMode, cMaxDepth - 1, pHlp);
3477	if (rc2 < rc && VBOX_SUCCESS(rc))
3478	rc = rc2;
3479	}
3480	}
3481	}
3482	return rc;
3483	}
3484
3485
3486	/**
3487	* Dumps a 32-bit shadow page table.
3488	*
3489	* @returns VBox status code (VINF_SUCCESS).
3490	* @param pVM The VM handle.
3491	* @param HCPhys The physical address of the table.
3492	* @param cr4 The CR4, PSE is currently used.
3493	* @param cMaxDepth The maxium depth.
3494	* @param pHlp Pointer to the output functions.
3495	*/
3496	static int pgmR3DumpHierarchyHcPaePML4(PVM pVM, RTHCPHYS HCPhys, uint32_t cr4, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
3497	{
3498	PX86PML4 pPML4 = (PX86PML4)MMPagePhys2Page(pVM, HCPhys);
3499	if (!pPML4)
3500	{
3501	pHlp->pfnPrintf(pHlp, "Page map level 4 at HCPhys=%#VHp was not found in the page pool!\n", HCPhys);
3502	return VERR_INVALID_PARAMETER;
3503	}
3504
3505	int rc = VINF_SUCCESS;
3506	for (unsigned i = 0; i < ELEMENTS(pPML4->a); i++)
3507	{
3508	X86PML4E Pml4e = pPML4->a[i];
3509	if (Pml4e.n.u1Present)
3510	{
3511	uint64_t u64Address = ((uint64_t)i << X86_PML4_SHIFT) \| (((uint64_t)i >> (X86_PML4_SHIFT - X86_PDPT_SHIFT - 1)) * 0xffff000000000000ULL);
3512	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a p ? /
3513	"%016llx 0 \| P %c %c %c %c %c %s %s %s %s .. %c%c%c %016llx\n",
3514	u64Address,
3515	Pml4e.n.u1Write ? 'W' : 'R',
3516	Pml4e.n.u1User ? 'U' : 'S',
3517	Pml4e.n.u1Accessed ? 'A' : '-',
3518	Pml4e.n.u3Reserved & 1? '?' : '.', /* ignored */
3519	Pml4e.n.u3Reserved & 4? '!' : '.', /* mbz */
3520	Pml4e.n.u1WriteThru ? "WT" : "--",
3521	Pml4e.n.u1CacheDisable? "CD" : "--",
3522	Pml4e.n.u3Reserved & 2? "!" : "..",/* mbz */
3523	Pml4e.n.u1NoExecute ? "NX" : "--",
3524	Pml4e.u & RT_BIT(9) ? '1' : '0',
3525	Pml4e.u & PGM_PLXFLAGS_PERMANENT ? 'p' : '-',
3526	Pml4e.u & RT_BIT(11) ? '1' : '0',
3527	Pml4e.u & X86_PML4E_PG_MASK);
3528
3529	if (cMaxDepth >= 1)
3530	{
3531	int rc2 = pgmR3DumpHierarchyHCPaePDPT(pVM, Pml4e.u & X86_PML4E_PG_MASK, u64Address, cr4, true, cMaxDepth - 1, pHlp);
3532	if (rc2 < rc && VBOX_SUCCESS(rc))
3533	rc = rc2;
3534	}
3535	}
3536	}
3537	return rc;
3538	}
3539
3540
3541	/**
3542	* Dumps a 32-bit shadow page table.
3543	*
3544	* @returns VBox status code (VINF_SUCCESS).
3545	* @param pVM The VM handle.
3546	* @param pPT Pointer to the page table.
3547	* @param u32Address The virtual address this table starts at.
3548	* @param pHlp Pointer to the output functions.
3549	*/
3550	int pgmR3DumpHierarchyHC32BitPT(PVM pVM, PX86PT pPT, uint32_t u32Address, PCDBGFINFOHLP pHlp)
3551	{
3552	for (unsigned i = 0; i < ELEMENTS(pPT->a); i++)
3553	{
3554	X86PTE Pte = pPT->a[i];
3555	if (Pte.n.u1Present)
3556	{
3557	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a m d /
3558	"%08x 1 \| P %c %c %c %c %c %s %s %s .. 4K %c%c%c %08x\n",
3559	u32Address + (i << X86_PT_SHIFT),
3560	Pte.n.u1Write ? 'W' : 'R',
3561	Pte.n.u1User ? 'U' : 'S',
3562	Pte.n.u1Accessed ? 'A' : '-',
3563	Pte.n.u1Dirty ? 'D' : '-',
3564	Pte.n.u1Global ? 'G' : '-',
3565	Pte.n.u1WriteThru ? "WT" : "--",
3566	Pte.n.u1CacheDisable? "CD" : "--",
3567	Pte.n.u1PAT ? "AT" : "--",
3568	Pte.u & PGM_PTFLAGS_TRACK_DIRTY ? 'd' : '-',
3569	Pte.u & RT_BIT(10) ? '1' : '0',
3570	Pte.u & PGM_PTFLAGS_CSAM_VALIDATED ? 'v' : '-',
3571	Pte.u & X86_PDE_PG_MASK);
3572	}
3573	}
3574	return VINF_SUCCESS;
3575	}
3576
3577
3578	/**
3579	* Dumps a 32-bit shadow page directory and page tables.
3580	*
3581	* @returns VBox status code (VINF_SUCCESS).
3582	* @param pVM The VM handle.
3583	* @param cr3 The root of the hierarchy.
3584	* @param cr4 The CR4, PSE is currently used.
3585	* @param cMaxDepth How deep into the hierarchy the dumper should go.
3586	* @param pHlp Pointer to the output functions.
3587	*/
3588	int pgmR3DumpHierarchyHC32BitPD(PVM pVM, uint32_t cr3, uint32_t cr4, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
3589	{
3590	PX86PD pPD = (PX86PD)MMPagePhys2Page(pVM, cr3 & X86_CR3_PAGE_MASK);
3591	if (!pPD)
3592	{
3593	pHlp->pfnPrintf(pHlp, "Page directory at %#x was not found in the page pool!\n", cr3 & X86_CR3_PAGE_MASK);
3594	return VERR_INVALID_PARAMETER;
3595	}
3596
3597	int rc = VINF_SUCCESS;
3598	for (unsigned i = 0; i < ELEMENTS(pPD->a); i++)
3599	{
3600	X86PDE Pde = pPD->a[i];
3601	if (Pde.n.u1Present)
3602	{
3603	const uint32_t u32Address = i << X86_PD_SHIFT;
3604	if ((cr4 & X86_CR4_PSE) && Pde.b.u1Size)
3605	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a m d /
3606	"%08x 0 \| P %c %c %c %c %c %s %s %s .. 4M %c%c%c %08x\n",
3607	u32Address,
3608	Pde.b.u1Write ? 'W' : 'R',
3609	Pde.b.u1User ? 'U' : 'S',
3610	Pde.b.u1Accessed ? 'A' : '-',
3611	Pde.b.u1Dirty ? 'D' : '-',
3612	Pde.b.u1Global ? 'G' : '-',
3613	Pde.b.u1WriteThru ? "WT" : "--",
3614	Pde.b.u1CacheDisable? "CD" : "--",
3615	Pde.b.u1PAT ? "AT" : "--",
3616	Pde.u & RT_BIT_64(9) ? '1' : '0',
3617	Pde.u & PGM_PDFLAGS_MAPPING ? 'm' : '-',
3618	Pde.u & PGM_PDFLAGS_TRACK_DIRTY ? 'd' : '-',
3619	Pde.u & X86_PDE4M_PG_MASK);
3620	else
3621	{
3622	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a m d /
3623	"%08x 0 \| P %c %c %c %c %c %s %s .. .. 4K %c%c%c %08x\n",
3624	u32Address,
3625	Pde.n.u1Write ? 'W' : 'R',
3626	Pde.n.u1User ? 'U' : 'S',
3627	Pde.n.u1Accessed ? 'A' : '-',
3628	Pde.n.u1Reserved0 ? '?' : '.', /* ignored */
3629	Pde.n.u1Reserved1 ? '?' : '.', /* ignored */
3630	Pde.n.u1WriteThru ? "WT" : "--",
3631	Pde.n.u1CacheDisable? "CD" : "--",
3632	Pde.u & RT_BIT_64(9) ? '1' : '0',
3633	Pde.u & PGM_PDFLAGS_MAPPING ? 'm' : '-',
3634	Pde.u & PGM_PDFLAGS_TRACK_DIRTY ? 'd' : '-',
3635	Pde.u & X86_PDE_PG_MASK);
3636	if (cMaxDepth >= 1)
3637	{
3638	/** @todo what about using the page pool for mapping PTs? */
3639	RTHCPHYS HCPhys = Pde.u & X86_PDE_PG_MASK;
3640	PX86PT pPT = NULL;
3641	if (!(Pde.u & PGM_PDFLAGS_MAPPING))
3642	pPT = (PX86PT)MMPagePhys2Page(pVM, HCPhys);
3643	else
3644	{
3645	for (PPGMMAPPING pMap = pVM->pgm.s.pMappingsR3; pMap; pMap = pMap->pNextR3)
3646	if (u32Address - pMap->GCPtr < pMap->cb)
3647	{
3648	int iPDE = (u32Address - pMap->GCPtr) >> X86_PD_SHIFT;
3649	if (pMap->aPTs[iPDE].HCPhysPT != HCPhys)
3650	pHlp->pfnPrintf(pHlp, "%08x error! Mapping error! PT %d has HCPhysPT=%VHp not %VHp is in the PD.\n",
3651	u32Address, iPDE, pMap->aPTs[iPDE].HCPhysPT, HCPhys);
3652	pPT = pMap->aPTs[iPDE].pPTR3;
3653	}
3654	}
3655	int rc2 = VERR_INVALID_PARAMETER;
3656	if (pPT)
3657	rc2 = pgmR3DumpHierarchyHC32BitPT(pVM, pPT, u32Address, pHlp);
3658	else
3659	pHlp->pfnPrintf(pHlp, "%08x error! Page table at %#x was not found in the page pool!\n", u32Address, HCPhys);
3660	if (rc2 < rc && VBOX_SUCCESS(rc))
3661	rc = rc2;
3662	}
3663	}
3664	}
3665	}
3666
3667	return rc;
3668	}
3669
3670
3671	/**
3672	* Dumps a 32-bit shadow page table.
3673	*
3674	* @returns VBox status code (VINF_SUCCESS).
3675	* @param pVM The VM handle.
3676	* @param pPT Pointer to the page table.
3677	* @param u32Address The virtual address this table starts at.
3678	* @param PhysSearch Address to search for.
3679	*/
3680	int pgmR3DumpHierarchyGC32BitPT(PVM pVM, PX86PT pPT, uint32_t u32Address, RTGCPHYS PhysSearch)
3681	{
3682	for (unsigned i = 0; i < ELEMENTS(pPT->a); i++)
3683	{
3684	X86PTE Pte = pPT->a[i];
3685	if (Pte.n.u1Present)
3686	{
3687	Log(( /P R S A D G WT CD AT NX 4M a m d /
3688	"%08x 1 \| P %c %c %c %c %c %s %s %s .. 4K %c%c%c %08x\n",
3689	u32Address + (i << X86_PT_SHIFT),
3690	Pte.n.u1Write ? 'W' : 'R',
3691	Pte.n.u1User ? 'U' : 'S',
3692	Pte.n.u1Accessed ? 'A' : '-',
3693	Pte.n.u1Dirty ? 'D' : '-',
3694	Pte.n.u1Global ? 'G' : '-',
3695	Pte.n.u1WriteThru ? "WT" : "--",
3696	Pte.n.u1CacheDisable? "CD" : "--",
3697	Pte.n.u1PAT ? "AT" : "--",
3698	Pte.u & PGM_PTFLAGS_TRACK_DIRTY ? 'd' : '-',
3699	Pte.u & RT_BIT(10) ? '1' : '0',
3700	Pte.u & PGM_PTFLAGS_CSAM_VALIDATED ? 'v' : '-',
3701	Pte.u & X86_PDE_PG_MASK));
3702
3703	if ((Pte.u & X86_PDE_PG_MASK) == PhysSearch)
3704	{
3705	uint64_t fPageShw = 0;
3706	RTHCPHYS pPhysHC = 0;
3707
3708	PGMShwGetPage(pVM, (RTGCPTR)(u32Address + (i << X86_PT_SHIFT)), &fPageShw, &pPhysHC);
3709	Log(("Found %VGp at %VGv -> flags=%llx\n", PhysSearch, (RTGCPTR)(u32Address + (i << X86_PT_SHIFT)), fPageShw));
3710	}
3711	}
3712	}
3713	return VINF_SUCCESS;
3714	}
3715
3716
3717	/**
3718	* Dumps a 32-bit guest page directory and page tables.
3719	*
3720	* @returns VBox status code (VINF_SUCCESS).
3721	* @param pVM The VM handle.
3722	* @param cr3 The root of the hierarchy.
3723	* @param cr4 The CR4, PSE is currently used.
3724	* @param PhysSearch Address to search for.
3725	*/
3726	PGMR3DECL(int) PGMR3DumpHierarchyGC(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCPHYS PhysSearch)
3727	{
3728	bool fLongMode = false;
3729	const unsigned cch = fLongMode ? 16 : 8; NOREF(cch);
3730	PX86PD pPD = 0;
3731
3732	int rc = PGM_GCPHYS_2_PTR(pVM, cr3 & X86_CR3_PAGE_MASK, &pPD);
3733	if (VBOX_FAILURE(rc) \|\| !pPD)
3734	{
3735	Log(("Page directory at %#x was not found in the page pool!\n", cr3 & X86_CR3_PAGE_MASK));
3736	return VERR_INVALID_PARAMETER;
3737	}
3738
3739	Log(("cr3=%08x cr4=%08x%s\n"
3740	"%-*s P - Present\n"
3741	"%-*s \| R/W - Read (0) / Write (1)\n"
3742	"%-*s \| \| U/S - User (1) / Supervisor (0)\n"
3743	"%-*s \| \| \| A - Accessed\n"
3744	"%-*s \| \| \| \| D - Dirty\n"
3745	"%-*s \| \| \| \| \| G - Global\n"
3746	"%-*s \| \| \| \| \| \| WT - Write thru\n"
3747	"%-*s \| \| \| \| \| \| \| CD - Cache disable\n"
3748	"%-*s \| \| \| \| \| \| \| \| AT - Attribute table (PAT)\n"
3749	"%-*s \| \| \| \| \| \| \| \| \| NX - No execute (K8)\n"
3750	"%-*s \| \| \| \| \| \| \| \| \| \| 4K/4M/2M - Page size.\n"
3751	"%-*s \| \| \| \| \| \| \| \| \| \| \| AVL - a=allocated; m=mapping; d=track dirty;\n"
3752	"%-*s \| \| \| \| \| \| \| \| \| \| \| \| p=permanent; v=validated;\n"
3753	"%-*s Level \| \| \| \| \| \| \| \| \| \| \| \| Page\n"
3754	/* xxxx n **** P R S A D G WT CD AT NX 4M AVL xxxxxxxxxxxxx
3755	- W U - - - -- -- -- -- -- 010 */
3756	, cr3, cr4, fLongMode ? " Long Mode" : "",
3757	cch, "", cch, "", cch, "", cch, "", cch, "", cch, "", cch, "",
3758	cch, "", cch, "", cch, "", cch, "", cch, "", cch, "", cch, "Address"));
3759
3760	for (unsigned i = 0; i < ELEMENTS(pPD->a); i++)
3761	{
3762	X86PDE Pde = pPD->a[i];
3763	if (Pde.n.u1Present)
3764	{
3765	const uint32_t u32Address = i << X86_PD_SHIFT;
3766
3767	if ((cr4 & X86_CR4_PSE) && Pde.b.u1Size)
3768	Log(( /P R S A D G WT CD AT NX 4M a m d /
3769	"%08x 0 \| P %c %c %c %c %c %s %s %s .. 4M %c%c%c %08x\n",
3770	u32Address,
3771	Pde.b.u1Write ? 'W' : 'R',
3772	Pde.b.u1User ? 'U' : 'S',
3773	Pde.b.u1Accessed ? 'A' : '-',
3774	Pde.b.u1Dirty ? 'D' : '-',
3775	Pde.b.u1Global ? 'G' : '-',
3776	Pde.b.u1WriteThru ? "WT" : "--",
3777	Pde.b.u1CacheDisable? "CD" : "--",
3778	Pde.b.u1PAT ? "AT" : "--",
3779	Pde.u & RT_BIT(9) ? '1' : '0',
3780	Pde.u & RT_BIT(10) ? '1' : '0',
3781	Pde.u & RT_BIT(11) ? '1' : '0',
3782	Pde.u & X86_PDE4M_PG_MASK));
3783	/** @todo PhysSearch */
3784	else
3785	{
3786	Log(( /P R S A D G WT CD AT NX 4M a m d /
3787	"%08x 0 \| P %c %c %c %c %c %s %s .. .. 4K %c%c%c %08x\n",
3788	u32Address,
3789	Pde.n.u1Write ? 'W' : 'R',
3790	Pde.n.u1User ? 'U' : 'S',
3791	Pde.n.u1Accessed ? 'A' : '-',
3792	Pde.n.u1Reserved0 ? '?' : '.', /* ignored */
3793	Pde.n.u1Reserved1 ? '?' : '.', /* ignored */
3794	Pde.n.u1WriteThru ? "WT" : "--",
3795	Pde.n.u1CacheDisable? "CD" : "--",
3796	Pde.u & RT_BIT(9) ? '1' : '0',
3797	Pde.u & RT_BIT(10) ? '1' : '0',
3798	Pde.u & RT_BIT(11) ? '1' : '0',
3799	Pde.u & X86_PDE_PG_MASK));
3800	////if (cMaxDepth >= 1)
3801	{
3802	/** @todo what about using the page pool for mapping PTs? */
3803	RTGCPHYS GCPhys = Pde.u & X86_PDE_PG_MASK;
3804	PX86PT pPT = NULL;
3805
3806	rc = PGM_GCPHYS_2_PTR(pVM, GCPhys, &pPT);
3807
3808	int rc2 = VERR_INVALID_PARAMETER;
3809	if (pPT)
3810	rc2 = pgmR3DumpHierarchyGC32BitPT(pVM, pPT, u32Address, PhysSearch);
3811	else
3812	Log(("%08x error! Page table at %#x was not found in the page pool!\n", u32Address, GCPhys));
3813	if (rc2 < rc && VBOX_SUCCESS(rc))
3814	rc = rc2;
3815	}
3816	}
3817	}
3818	}
3819
3820	return rc;
3821	}
3822
3823
3824	/**
3825	* Dumps a page table hierarchy use only physical addresses and cr4/lm flags.
3826	*
3827	* @returns VBox status code (VINF_SUCCESS).
3828	* @param pVM The VM handle.
3829	* @param cr3 The root of the hierarchy.
3830	* @param cr4 The cr4, only PAE and PSE is currently used.
3831	* @param fLongMode Set if long mode, false if not long mode.
3832	* @param cMaxDepth Number of levels to dump.
3833	* @param pHlp Pointer to the output functions.
3834	*/
3835	PGMR3DECL(int) PGMR3DumpHierarchyHC(PVM pVM, uint64_t cr3, uint64_t cr4, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
3836	{
3837	if (!pHlp)
3838	pHlp = DBGFR3InfoLogHlp();
3839	if (!cMaxDepth)
3840	return VINF_SUCCESS;
3841	const unsigned cch = fLongMode ? 16 : 8;
3842	pHlp->pfnPrintf(pHlp,
3843	"cr3=%08x cr4=%08x%s\n"
3844	"%-*s P - Present\n"
3845	"%-*s \| R/W - Read (0) / Write (1)\n"
3846	"%-*s \| \| U/S - User (1) / Supervisor (0)\n"
3847	"%-*s \| \| \| A - Accessed\n"
3848	"%-*s \| \| \| \| D - Dirty\n"
3849	"%-*s \| \| \| \| \| G - Global\n"
3850	"%-*s \| \| \| \| \| \| WT - Write thru\n"
3851	"%-*s \| \| \| \| \| \| \| CD - Cache disable\n"
3852	"%-*s \| \| \| \| \| \| \| \| AT - Attribute table (PAT)\n"
3853	"%-*s \| \| \| \| \| \| \| \| \| NX - No execute (K8)\n"
3854	"%-*s \| \| \| \| \| \| \| \| \| \| 4K/4M/2M - Page size.\n"
3855	"%-*s \| \| \| \| \| \| \| \| \| \| \| AVL - a=allocated; m=mapping; d=track dirty;\n"
3856	"%-*s \| \| \| \| \| \| \| \| \| \| \| \| p=permanent; v=validated;\n"
3857	"%-*s Level \| \| \| \| \| \| \| \| \| \| \| \| Page\n"
3858	/* xxxx n **** P R S A D G WT CD AT NX 4M AVL xxxxxxxxxxxxx
3859	- W U - - - -- -- -- -- -- 010 */
3860	, cr3, cr4, fLongMode ? " Long Mode" : "",
3861	cch, "", cch, "", cch, "", cch, "", cch, "", cch, "", cch, "",
3862	cch, "", cch, "", cch, "", cch, "", cch, "", cch, "", cch, "Address");
3863	if (cr4 & X86_CR4_PAE)
3864	{
3865	if (fLongMode)
3866	return pgmR3DumpHierarchyHcPaePML4(pVM, cr3 & X86_CR3_PAGE_MASK, cr4, cMaxDepth, pHlp);
3867	return pgmR3DumpHierarchyHCPaePDPT(pVM, cr3 & X86_CR3_PAE_PAGE_MASK, 0, cr4, false, cMaxDepth, pHlp);
3868	}
3869	return pgmR3DumpHierarchyHC32BitPD(pVM, cr3 & X86_CR3_PAGE_MASK, cr4, cMaxDepth, pHlp);
3870	}
3871
3872
3873
3874	#ifdef VBOX_WITH_DEBUGGER
3875	/**
3876	* The '.pgmram' command.
3877	*
3878	* @returns VBox status.
3879	* @param pCmd Pointer to the command descriptor (as registered).
3880	* @param pCmdHlp Pointer to command helper functions.
3881	* @param pVM Pointer to the current VM (if any).
3882	* @param paArgs Pointer to (readonly) array of arguments.
3883	* @param cArgs Number of arguments in the array.
3884	*/
3885	static DECLCALLBACK(int) pgmR3CmdRam(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
3886	{
3887	/*
3888	* Validate input.
3889	*/
3890	if (!pVM)
3891	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
3892	if (!pVM->pgm.s.pRamRangesGC)
3893	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Sorry, no Ram is registered.\n");
3894
3895	/*
3896	* Dump the ranges.
3897	*/
3898	int rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL, "From - To (incl) pvHC\n");
3899	PPGMRAMRANGE pRam;
3900	for (pRam = pVM->pgm.s.pRamRangesR3; pRam; pRam = pRam->pNextR3)
3901	{
3902	rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL,
3903	"%VGp - %VGp %p\n",
3904	pRam->GCPhys, pRam->GCPhysLast, pRam->pvHC);
3905	if (VBOX_FAILURE(rc))
3906	return rc;
3907	}
3908
3909	return VINF_SUCCESS;
3910	}
3911
3912
3913	/**
3914	* The '.pgmmap' command.
3915	*
3916	* @returns VBox status.
3917	* @param pCmd Pointer to the command descriptor (as registered).
3918	* @param pCmdHlp Pointer to command helper functions.
3919	* @param pVM Pointer to the current VM (if any).
3920	* @param paArgs Pointer to (readonly) array of arguments.
3921	* @param cArgs Number of arguments in the array.
3922	*/
3923	static DECLCALLBACK(int) pgmR3CmdMap(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
3924	{
3925	/*
3926	* Validate input.
3927	*/
3928	if (!pVM)
3929	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
3930	if (!pVM->pgm.s.pMappingsR3)
3931	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Sorry, no mappings are registered.\n");
3932
3933	/*
3934	* Print message about the fixedness of the mappings.
3935	*/
3936	int rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL, pVM->pgm.s.fMappingsFixed ? "The mappings are FIXED.\n" : "The mappings are FLOATING.\n");
3937	if (VBOX_FAILURE(rc))
3938	return rc;
3939
3940	/*
3941	* Dump the ranges.
3942	*/
3943	PPGMMAPPING pCur;
3944	for (pCur = pVM->pgm.s.pMappingsR3; pCur; pCur = pCur->pNextR3)
3945	{
3946	rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL,
3947	"%08x - %08x %s\n",
3948	pCur->GCPtr, pCur->GCPtrLast, pCur->pszDesc);
3949	if (VBOX_FAILURE(rc))
3950	return rc;
3951	}
3952
3953	return VINF_SUCCESS;
3954	}
3955
3956
3957	/**
3958	* The '.pgmsync' command.
3959	*
3960	* @returns VBox status.
3961	* @param pCmd Pointer to the command descriptor (as registered).
3962	* @param pCmdHlp Pointer to command helper functions.
3963	* @param pVM Pointer to the current VM (if any).
3964	* @param paArgs Pointer to (readonly) array of arguments.
3965	* @param cArgs Number of arguments in the array.
3966	*/
3967	static DECLCALLBACK(int) pgmR3CmdSync(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
3968	{
3969	/*
3970	* Validate input.
3971	*/
3972	if (!pVM)
3973	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
3974
3975	/*
3976	* Force page directory sync.
3977	*/
3978	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
3979
3980	int rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Forcing page directory sync.\n");
3981	if (VBOX_FAILURE(rc))
3982	return rc;
3983
3984	return VINF_SUCCESS;
3985	}
3986
3987
3988	#ifdef VBOX_STRICT
3989	/**
3990	* The '.pgmassertcr3' command.
3991	*
3992	* @returns VBox status.
3993	* @param pCmd Pointer to the command descriptor (as registered).
3994	* @param pCmdHlp Pointer to command helper functions.
3995	* @param pVM Pointer to the current VM (if any).
3996	* @param paArgs Pointer to (readonly) array of arguments.
3997	* @param cArgs Number of arguments in the array.
3998	*/
3999	static DECLCALLBACK(int) pgmR3CmdAssertCR3(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4000	{
4001	/*
4002	* Validate input.
4003	*/
4004	if (!pVM)
4005	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4006
4007	int rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Checking shadow CR3 page tables for consistency.\n");
4008	if (VBOX_FAILURE(rc))
4009	return rc;
4010
4011	PGMAssertCR3(pVM, CPUMGetGuestCR3(pVM), CPUMGetGuestCR4(pVM));
4012
4013	return VINF_SUCCESS;
4014	}
4015	#endif
4016
4017	/**
4018	* The '.pgmsyncalways' command.
4019	*
4020	* @returns VBox status.
4021	* @param pCmd Pointer to the command descriptor (as registered).
4022	* @param pCmdHlp Pointer to command helper functions.
4023	* @param pVM Pointer to the current VM (if any).
4024	* @param paArgs Pointer to (readonly) array of arguments.
4025	* @param cArgs Number of arguments in the array.
4026	*/
4027	static DECLCALLBACK(int) pgmR3CmdSyncAlways(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4028	{
4029	/*
4030	* Validate input.
4031	*/
4032	if (!pVM)
4033	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4034
4035	/*
4036	* Force page directory sync.
4037	*/
4038	if (pVM->pgm.s.fSyncFlags & PGM_SYNC_ALWAYS)
4039	{
4040	ASMAtomicAndU32(&pVM->pgm.s.fSyncFlags, ~PGM_SYNC_ALWAYS);
4041	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Disabled permanent forced page directory syncing.\n");
4042	}
4043	else
4044	{
4045	ASMAtomicOrU32(&pVM->pgm.s.fSyncFlags, PGM_SYNC_ALWAYS);
4046	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
4047	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Enabled permanent forced page directory syncing.\n");
4048	}
4049	}
4050
4051	#endif
4052
4053	/**
4054	* pvUser argument of the pgmR3CheckIntegrity*Node callbacks.
4055	*/
4056	typedef struct PGMCHECKINTARGS
4057	{
4058	bool fLeftToRight; /*< true: left-to-right; false: right-to-left. /
4059	PPGMPHYSHANDLER pPrevPhys;
4060	PPGMVIRTHANDLER pPrevVirt;
4061	PPGMPHYS2VIRTHANDLER pPrevPhys2Virt;
4062	PVM pVM;
4063	} PGMCHECKINTARGS, *PPGMCHECKINTARGS;
4064
4065	/**
4066	* Validate a node in the physical handler tree.
4067	*
4068	* @returns 0 on if ok, other wise 1.
4069	* @param pNode The handler node.
4070	* @param pvUser pVM.
4071	*/
4072	static DECLCALLBACK(int) pgmR3CheckIntegrityPhysHandlerNode(PAVLROGCPHYSNODECORE pNode, void *pvUser)
4073	{
4074	PPGMCHECKINTARGS pArgs = (PPGMCHECKINTARGS)pvUser;
4075	PPGMPHYSHANDLER pCur = (PPGMPHYSHANDLER)pNode;
4076	AssertReleaseReturn(!((uintptr_t)pCur & 7), 1);
4077	AssertReleaseMsg(pCur->Core.Key <= pCur->Core.KeyLast,("pCur=%p %VGp-%VGp %s\n", pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
4078	AssertReleaseMsg( !pArgs->pPrevPhys
4079	\|\| (pArgs->fLeftToRight ? pArgs->pPrevPhys->Core.KeyLast < pCur->Core.Key : pArgs->pPrevPhys->Core.KeyLast > pCur->Core.Key),
4080	("pPrevPhys=%p %VGp-%VGp %s\n"
4081	" pCur=%p %VGp-%VGp %s\n",
4082	pArgs->pPrevPhys, pArgs->pPrevPhys->Core.Key, pArgs->pPrevPhys->Core.KeyLast, pArgs->pPrevPhys->pszDesc,
4083	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
4084	pArgs->pPrevPhys = pCur;
4085	return 0;
4086	}
4087
4088
4089	/**
4090	* Validate a node in the virtual handler tree.
4091	*
4092	* @returns 0 on if ok, other wise 1.
4093	* @param pNode The handler node.
4094	* @param pvUser pVM.
4095	*/
4096	static DECLCALLBACK(int) pgmR3CheckIntegrityVirtHandlerNode(PAVLROGCPTRNODECORE pNode, void *pvUser)
4097	{
4098	PPGMCHECKINTARGS pArgs = (PPGMCHECKINTARGS)pvUser;
4099	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)pNode;
4100	AssertReleaseReturn(!((uintptr_t)pCur & 7), 1);
4101	AssertReleaseMsg(pCur->Core.Key <= pCur->Core.KeyLast,("pCur=%p %VGv-%VGv %s\n", pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
4102	AssertReleaseMsg( !pArgs->pPrevVirt
4103	\|\| (pArgs->fLeftToRight ? pArgs->pPrevVirt->Core.KeyLast < pCur->Core.Key : pArgs->pPrevVirt->Core.KeyLast > pCur->Core.Key),
4104	("pPrevVirt=%p %VGv-%VGv %s\n"
4105	" pCur=%p %VGv-%VGv %s\n",
4106	pArgs->pPrevVirt, pArgs->pPrevVirt->Core.Key, pArgs->pPrevVirt->Core.KeyLast, pArgs->pPrevVirt->pszDesc,
4107	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
4108	for (unsigned iPage = 0; iPage < pCur->cPages; iPage++)
4109	{
4110	AssertReleaseMsg(pCur->aPhysToVirt[iPage].offVirtHandler == -RT_OFFSETOF(PGMVIRTHANDLER, aPhysToVirt[iPage]),
4111	("pCur=%p %VGv-%VGv %s\n"
4112	"iPage=%d offVirtHandle=%#x expected %#x\n",
4113	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc,
4114	iPage, pCur->aPhysToVirt[iPage].offVirtHandler, -RT_OFFSETOF(PGMVIRTHANDLER, aPhysToVirt[iPage])));
4115	}
4116	pArgs->pPrevVirt = pCur;
4117	return 0;
4118	}
4119
4120
4121	/**
4122	* Validate a node in the virtual handler tree.
4123	*
4124	* @returns 0 on if ok, other wise 1.
4125	* @param pNode The handler node.
4126	* @param pvUser pVM.
4127	*/
4128	static DECLCALLBACK(int) pgmR3CheckIntegrityPhysToVirtHandlerNode(PAVLROGCPHYSNODECORE pNode, void *pvUser)
4129	{
4130	PPGMCHECKINTARGS pArgs = (PPGMCHECKINTARGS)pvUser;
4131	PPGMPHYS2VIRTHANDLER pCur = (PPGMPHYS2VIRTHANDLER)pNode;
4132	AssertReleaseMsgReturn(!((uintptr_t)pCur & 3), ("\n"), 1);
4133	AssertReleaseMsgReturn(!(pCur->offVirtHandler & 3), ("\n"), 1);
4134	AssertReleaseMsg(pCur->Core.Key <= pCur->Core.KeyLast,("pCur=%p %VGp-%VGp\n", pCur, pCur->Core.Key, pCur->Core.KeyLast));
4135	AssertReleaseMsg( !pArgs->pPrevPhys2Virt
4136	\|\| (pArgs->fLeftToRight ? pArgs->pPrevPhys2Virt->Core.KeyLast < pCur->Core.Key : pArgs->pPrevPhys2Virt->Core.KeyLast > pCur->Core.Key),
4137	("pPrevPhys2Virt=%p %VGp-%VGp\n"
4138	" pCur=%p %VGp-%VGp\n",
4139	pArgs->pPrevPhys2Virt, pArgs->pPrevPhys2Virt->Core.Key, pArgs->pPrevPhys2Virt->Core.KeyLast,
4140	pCur, pCur->Core.Key, pCur->Core.KeyLast));
4141	AssertReleaseMsg( !pArgs->pPrevPhys2Virt
4142	\|\| (pArgs->fLeftToRight ? pArgs->pPrevPhys2Virt->Core.KeyLast < pCur->Core.Key : pArgs->pPrevPhys2Virt->Core.KeyLast > pCur->Core.Key),
4143	("pPrevPhys2Virt=%p %VGp-%VGp\n"
4144	" pCur=%p %VGp-%VGp\n",
4145	pArgs->pPrevPhys2Virt, pArgs->pPrevPhys2Virt->Core.Key, pArgs->pPrevPhys2Virt->Core.KeyLast,
4146	pCur, pCur->Core.Key, pCur->Core.KeyLast));
4147	AssertReleaseMsg((pCur->offNextAlias & (PGMPHYS2VIRTHANDLER_IN_TREE \| PGMPHYS2VIRTHANDLER_IS_HEAD)) == (PGMPHYS2VIRTHANDLER_IN_TREE \| PGMPHYS2VIRTHANDLER_IS_HEAD),
4148	("pCur=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4149	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias));
4150	if (pCur->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK)
4151	{
4152	PPGMPHYS2VIRTHANDLER pCur2 = pCur;
4153	for (;;)
4154	{
4155	pCur2 = (PPGMPHYS2VIRTHANDLER)((intptr_t)pCur + (pCur->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK));
4156	AssertReleaseMsg(pCur2 != pCur,
4157	(" pCur=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4158	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias));
4159	AssertReleaseMsg((pCur2->offNextAlias & (PGMPHYS2VIRTHANDLER_IN_TREE \| PGMPHYS2VIRTHANDLER_IS_HEAD)) == PGMPHYS2VIRTHANDLER_IN_TREE,
4160	(" pCur=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
4161	"pCur2=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4162	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias,
4163	pCur2, pCur2->Core.Key, pCur2->Core.KeyLast, pCur2->offVirtHandler, pCur2->offNextAlias));
4164	AssertReleaseMsg((pCur2->Core.Key ^ pCur->Core.Key) < PAGE_SIZE,
4165	(" pCur=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
4166	"pCur2=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4167	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias,
4168	pCur2, pCur2->Core.Key, pCur2->Core.KeyLast, pCur2->offVirtHandler, pCur2->offNextAlias));
4169	AssertReleaseMsg((pCur2->Core.KeyLast ^ pCur->Core.KeyLast) < PAGE_SIZE,
4170	(" pCur=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
4171	"pCur2=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4172	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias,
4173	pCur2, pCur2->Core.Key, pCur2->Core.KeyLast, pCur2->offVirtHandler, pCur2->offNextAlias));
4174	if (!(pCur2->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK))
4175	break;
4176	}
4177	}
4178
4179	pArgs->pPrevPhys2Virt = pCur;
4180	return 0;
4181	}
4182
4183
4184	/**
4185	* Perform an integrity check on the PGM component.
4186	*
4187	* @returns VINF_SUCCESS if everything is fine.
4188	* @returns VBox error status after asserting on integrity breach.
4189	* @param pVM The VM handle.
4190	*/
4191	PDMR3DECL(int) PGMR3CheckIntegrity(PVM pVM)
4192	{
4193	AssertReleaseReturn(pVM->pgm.s.offVM, VERR_INTERNAL_ERROR);
4194
4195	/*
4196	* Check the trees.
4197	*/
4198	int cErrors = 0;
4199	const static PGMCHECKINTARGS s_LeftToRight = { true, NULL, NULL, NULL, pVM };
4200	const static PGMCHECKINTARGS s_RightToLeft = { false, NULL, NULL, NULL, pVM };
4201	PGMCHECKINTARGS Args = s_LeftToRight;
4202	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesHC->PhysHandlers, true, pgmR3CheckIntegrityPhysHandlerNode, &Args);
4203	Args = s_RightToLeft;
4204	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesHC->PhysHandlers, false, pgmR3CheckIntegrityPhysHandlerNode, &Args);
4205	Args = s_LeftToRight;
4206	cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesHC->VirtHandlers, true, pgmR3CheckIntegrityVirtHandlerNode, &Args);
4207	Args = s_RightToLeft;
4208	cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesHC->VirtHandlers, false, pgmR3CheckIntegrityVirtHandlerNode, &Args);
4209	Args = s_LeftToRight;
4210	cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesHC->HyperVirtHandlers, true, pgmR3CheckIntegrityVirtHandlerNode, &Args);
4211	Args = s_RightToLeft;
4212	cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesHC->HyperVirtHandlers, false, pgmR3CheckIntegrityVirtHandlerNode, &Args);
4213	Args = s_LeftToRight;
4214	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesHC->PhysToVirtHandlers, true, pgmR3CheckIntegrityPhysToVirtHandlerNode, &Args);
4215	Args = s_RightToLeft;
4216	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesHC->PhysToVirtHandlers, false, pgmR3CheckIntegrityPhysToVirtHandlerNode, &Args);
4217
4218	return !cErrors ? VINF_SUCCESS : VERR_INTERNAL_ERROR;
4219	}
4220
4221
4222	/**
4223	* Inform PGM if we want all mappings to be put into the shadow page table. (necessary for e.g. VMX)
4224	*
4225	* @returns VBox status code.
4226	* @param pVM VM handle.
4227	* @param fEnable Enable or disable shadow mappings
4228	*/
4229	PGMR3DECL(int) PGMR3ChangeShwPDMappings(PVM pVM, bool fEnable)
4230	{
4231	pVM->pgm.s.fDisableMappings = !fEnable;
4232
4233	uint32_t cb;
4234	int rc = PGMR3MappingsSize(pVM, &cb);
4235	AssertRCReturn(rc, rc);
4236
4237	/* Pretend the mappings are now fixed; to force a refresh of the reserved PDEs. */
4238	rc = PGMR3MappingsFix(pVM, MM_HYPER_AREA_ADDRESS, cb);
4239	AssertRCReturn(rc, rc);
4240
4241	return VINF_SUCCESS;
4242	}

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source: vbox/trunk/src/VBox/VMM/PGM.cpp@ 10700

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