PGM.cpp@ 13050

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1	/* $Id: PGM.cpp 13045 2008-10-07 13:04:43Z vboxsync $ */
2	/** @file
3	* PGM - Page Manager and Monitor. (Mixing stuff here, not good?)
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22
23	/** @page pg_pgm PGM - The Page Manager and Monitor
24	*
25	* @see grp_pgm,
26	* @ref pg_pgm_pool,
27	* @ref pg_pgm_phys.
28	*
29	*
30	* @section sec_pgm_modes Paging Modes
31	*
32	* There are three memory contexts: Host Context (HC), Guest Context (GC)
33	* and intermediate context. When talking about paging HC can also be refered to
34	* as "host paging", and GC refered to as "shadow paging".
35	*
36	* We define three basic paging modes: 32-bit, PAE and AMD64. The host paging mode
37	* is defined by the host operating system. The mode used in the shadow paging mode
38	* depends on the host paging mode and what the mode the guest is currently in. The
39	* following relation between the two is defined:
40	*
41	* @verbatim
42	Host > 32-bit \| PAE \| AMD64 \|
43	Guest \| \| \| \|
44	==v================================
45	32-bit 32-bit PAE PAE
46	-------\|--------\|--------\|--------\|
47	PAE PAE PAE PAE
48	-------\|--------\|--------\|--------\|
49	AMD64 AMD64 AMD64 AMD64
50	-------\|--------\|--------\|--------\| @endverbatim
51	*
52	* All configuration except those in the diagonal (upper left) are expected to
53	* require special effort from the switcher (i.e. a bit slower).
54	*
55	*
56	*
57	*
58	* @section sec_pgm_shw The Shadow Memory Context
59	*
60	*
61	* [..]
62	*
63	* Because of guest context mappings requires PDPT and PML4 entries to allow
64	* writing on AMD64, the two upper levels will have fixed flags whatever the
65	* guest is thinking of using there. So, when shadowing the PD level we will
66	* calculate the effective flags of PD and all the higher levels. In legacy
67	* PAE mode this only applies to the PWT and PCD bits (the rest are
68	* ignored/reserved/MBZ). We will ignore those bits for the present.
69	*
70	*
71	*
72	* @section sec_pgm_int The Intermediate Memory Context
73	*
74	* The world switch goes thru an intermediate memory context which purpose it is
75	* to provide different mappings of the switcher code. All guest mappings are also
76	* present in this context.
77	*
78	* The switcher code is mapped at the same location as on the host, at an
79	* identity mapped location (physical equals virtual address), and at the
80	* hypervisor location.
81	*
82	* PGM maintain page tables for 32-bit, PAE and AMD64 paging modes. This
83	* simplifies switching guest CPU mode and consistency at the cost of more
84	* code to do the work. All memory use for those page tables is located below
85	* 4GB (this includes page tables for guest context mappings).
86	*
87	*
88	* @subsection subsec_pgm_int_gc Guest Context Mappings
89	*
90	* During assignment and relocation of a guest context mapping the intermediate
91	* memory context is used to verify the new location.
92	*
93	* Guest context mappings are currently restricted to below 4GB, for reasons
94	* of simplicity. This may change when we implement AMD64 support.
95	*
96	*
97	*
98	*
99	* @section sec_pgm_misc Misc
100	*
101	* @subsection subsec_pgm_misc_diff Differences Between Legacy PAE and Long Mode PAE
102	*
103	* The differences between legacy PAE and long mode PAE are:
104	* -# PDPE bits 1, 2, 5 and 6 are defined differently. In leagcy mode they are
105	* all marked down as must-be-zero, while in long mode 1, 2 and 5 have the
106	* usual meanings while 6 is ignored (AMD). This means that upon switching to
107	* legacy PAE mode we'll have to clear these bits and when going to long mode
108	* they must be set. This applies to both intermediate and shadow contexts,
109	* however we don't need to do it for the intermediate one since we're
110	* executing with CR0.WP at that time.
111	* -# CR3 allows a 32-byte aligned address in legacy mode, while in long mode
112	* a page aligned one is required.
113	*
114	*
115	* @section sec_pgm_handlers Access Handlers
116	*
117	* Placeholder.
118	*
119	*
120	* @subsection sec_pgm_handlers_virt Virtual Access Handlers
121	*
122	* Placeholder.
123	*
124	*
125	* @subsection sec_pgm_handlers_virt Virtual Access Handlers
126	*
127	* We currently implement three types of virtual access handlers: ALL, WRITE
128	* and HYPERVISOR (WRITE). See PGMVIRTHANDLERTYPE for some more details.
129	*
130	* The HYPERVISOR access handlers is kept in a separate tree since it doesn't apply
131	* to physical pages (PGMTREES::HyperVirtHandlers) and only needs to be consulted in
132	* a special \#PF case. The ALL and WRITE are in the PGMTREES::VirtHandlers tree, the
133	* rest of this section is going to be about these handlers.
134	*
135	* We'll go thru the life cycle of a handler and try make sense of it all, don't know
136	* how successfull this is gonna be...
137	*
138	* 1. A handler is registered thru the PGMR3HandlerVirtualRegister and
139	* PGMHandlerVirtualRegisterEx APIs. We check for conflicting virtual handlers
140	* and create a new node that is inserted into the AVL tree (range key). Then
141	* a full PGM resync is flagged (clear pool, sync cr3, update virtual bit of PGMPAGE).
142	*
143	* 2. The following PGMSyncCR3/SyncCR3 operation will first make invoke HandlerVirtualUpdate.
144	*
145	* 2a. HandlerVirtualUpdate will will lookup all the pages covered by virtual handlers
146	* via the current guest CR3 and update the physical page -> virtual handler
147	* translation. Needless to say, this doesn't exactly scale very well. If any changes
148	* are detected, it will flag a virtual bit update just like we did on registration.
149	* PGMPHYS pages with changes will have their virtual handler state reset to NONE.
150	*
151	* 2b. The virtual bit update process will iterate all the pages covered by all the
152	* virtual handlers and update the PGMPAGE virtual handler state to the max of all
153	* virtual handlers on that page.
154	*
155	* 2c. Back in SyncCR3 we will now flush the entire shadow page cache to make sure
156	* we don't miss any alias mappings of the monitored pages.
157	*
158	* 2d. SyncCR3 will then proceed with syncing the CR3 table.
159	*
160	* 3. \#PF(np,read) on a page in the range. This will cause it to be synced
161	* read-only and resumed if it's a WRITE handler. If it's an ALL handler we
162	* will call the handlers like in the next step. If the physical mapping has
163	* changed we will - some time in the future - perform a handler callback
164	* (optional) and update the physical -> virtual handler cache.
165	*
166	* 4. \#PF(,write) on a page in the range. This will cause the handler to
167	* be invoked.
168	*
169	* 5. The guest invalidates the page and changes the physical backing or
170	* unmaps it. This should cause the invalidation callback to be invoked
171	* (it might not yet be 100% perfect). Exactly what happens next... is
172	* this where we mess up and end up out of sync for a while?
173	*
174	* 6. The handler is deregistered by the client via PGMHandlerVirtualDeregister.
175	* We will then set all PGMPAGEs in the physical -> virtual handler cache for
176	* this handler to NONE and trigger a full PGM resync (basically the same
177	* as int step 1). Which means 2 is executed again.
178	*
179	*
180	* @subsubsection sub_sec_pgm_handler_virt_todo TODOs
181	*
182	* There is a bunch of things that needs to be done to make the virtual handlers
183	* work 100% correctly and work more efficiently.
184	*
185	* The first bit hasn't been implemented yet because it's going to slow the
186	* whole mess down even more, and besides it seems to be working reliably for
187	* our current uses. OTOH, some of the optimizations might end up more or less
188	* implementing the missing bits, so we'll see.
189	*
190	* On the optimization side, the first thing to do is to try avoid unnecessary
191	* cache flushing. Then try team up with the shadowing code to track changes
192	* in mappings by means of access to them (shadow in), updates to shadows pages,
193	* invlpg, and shadow PT discarding (perhaps).
194	*
195	* Some idea that have popped up for optimization for current and new features:
196	* - bitmap indicating where there are virtual handlers installed.
197	* (4KB => 220 pages, page 212 => covers 32-bit address space 1:1!)
198	* - Further optimize this by min/max (needs min/max avl getters).
199	* - Shadow page table entry bit (if any left)?
200	*
201	*/
202
203
204	/** @page pg_pgm_phys PGM Physical Guest Memory Management
205	*
206	*
207	* Objectives:
208	* - Guest RAM over-commitment using memory ballooning,
209	* zero pages and general page sharing.
210	* - Moving or mirroring a VM onto a different physical machine.
211	*
212	*
213	* @subsection subsec_pgmPhys_Definitions Definitions
214	*
215	* Allocation chunk - A RTR0MemObjAllocPhysNC object and the tracking
216	* machinery assoicated with it.
217	*
218	*
219	*
220	*
221	* @subsection subsec_pgmPhys_AllocPage Allocating a page.
222	*
223	* Initially we map all guest memory to the (per VM) zero page, which
224	* means that none of the read functions will cause pages to be allocated.
225	*
226	* Exception, access bit in page tables that have been shared. This must
227	* be handled, but we must also make sure PGMGst*Modify doesn't make
228	* unnecessary modifications.
229	*
230	* Allocation points:
231	* - PGMPhysWriteGCPhys and PGMPhysWrite.
232	* - Replacing a zero page mapping at \#PF.
233	* - Replacing a shared page mapping at \#PF.
234	* - ROM registration (currently MMR3RomRegister).
235	* - VM restore (pgmR3Load).
236	*
237	* For the first three it would make sense to keep a few pages handy
238	* until we've reached the max memory commitment for the VM.
239	*
240	* For the ROM registration, we know exactly how many pages we need
241	* and will request these from ring-0. For restore, we will save
242	* the number of non-zero pages in the saved state and allocate
243	* them up front. This would allow the ring-0 component to refuse
244	* the request if the isn't sufficient memory available for VM use.
245	*
246	* Btw. for both ROM and restore allocations we won't be requiring
247	* zeroed pages as they are going to be filled instantly.
248	*
249	*
250	* @subsection subsec_pgmPhys_FreePage Freeing a page
251	*
252	* There are a few points where a page can be freed:
253	* - After being replaced by the zero page.
254	* - After being replaced by a shared page.
255	* - After being ballooned by the guest additions.
256	* - At reset.
257	* - At restore.
258	*
259	* When freeing one or more pages they will be returned to the ring-0
260	* component and replaced by the zero page.
261	*
262	* The reasoning for clearing out all the pages on reset is that it will
263	* return us to the exact same state as on power on, and may thereby help
264	* us reduce the memory load on the system. Further it might have a
265	* (temporary) positive influence on memory fragmentation (@see subsec_pgmPhys_Fragmentation).
266	*
267	* On restore, as mention under the allocation topic, pages should be
268	* freed / allocated depending on how many is actually required by the
269	* new VM state. The simplest approach is to do like on reset, and free
270	* all non-ROM pages and then allocate what we need.
271	*
272	* A measure to prevent some fragmentation, would be to let each allocation
273	* chunk have some affinity towards the VM having allocated the most pages
274	* from it. Also, try make sure to allocate from allocation chunks that
275	* are almost full. Admittedly, both these measures might work counter to
276	* our intentions and its probably not worth putting a lot of effort,
277	* cpu time or memory into this.
278	*
279	*
280	* @subsection subsec_pgmPhys_SharePage Sharing a page
281	*
282	* The basic idea is that there there will be a idle priority kernel
283	* thread walking the non-shared VM pages hashing them and looking for
284	* pages with the same checksum. If such pages are found, it will compare
285	* them byte-by-byte to see if they actually are identical. If found to be
286	* identical it will allocate a shared page, copy the content, check that
287	* the page didn't change while doing this, and finally request both the
288	* VMs to use the shared page instead. If the page is all zeros (special
289	* checksum and byte-by-byte check) it will request the VM that owns it
290	* to replace it with the zero page.
291	*
292	* To make this efficient, we will have to make sure not to try share a page
293	* that will change its contents soon. This part requires the most work.
294	* A simple idea would be to request the VM to write monitor the page for
295	* a while to make sure it isn't modified any time soon. Also, it may
296	* make sense to skip pages that are being write monitored since this
297	* information is readily available to the thread if it works on the
298	* per-VM guest memory structures (presently called PGMRAMRANGE).
299	*
300	*
301	* @subsection subsec_pgmPhys_Fragmentation Fragmentation Concerns and Counter Measures
302	*
303	* The pages are organized in allocation chunks in ring-0, this is a necessity
304	* if we wish to have an OS agnostic approach to this whole thing. (On Linux we
305	* could easily work on a page-by-page basis if we liked. Whether this is possible
306	* or efficient on NT I don't quite know.) Fragmentation within these chunks may
307	* become a problem as part of the idea here is that we wish to return memory to
308	* the host system.
309	*
310	* For instance, starting two VMs at the same time, they will both allocate the
311	* guest memory on-demand and if permitted their page allocations will be
312	* intermixed. Shut down one of the two VMs and it will be difficult to return
313	* any memory to the host system because the page allocation for the two VMs are
314	* mixed up in the same allocation chunks.
315	*
316	* To further complicate matters, when pages are freed because they have been
317	* ballooned or become shared/zero the whole idea is that the page is supposed
318	* to be reused by another VM or returned to the host system. This will cause
319	* allocation chunks to contain pages belonging to different VMs and prevent
320	* returning memory to the host when one of those VM shuts down.
321	*
322	* The only way to really deal with this problem is to move pages. This can
323	* either be done at VM shutdown and or by the idle priority worker thread
324	* that will be responsible for finding sharable/zero pages. The mechanisms
325	* involved for coercing a VM to move a page (or to do it for it) will be
326	* the same as when telling it to share/zero a page.
327	*
328	*
329	* @subsection subsec_pgmPhys_Tracking Tracking Structures And Their Cost
330	*
331	* There's a difficult balance between keeping the per-page tracking structures
332	* (global and guest page) easy to use and keeping them from eating too much
333	* memory. We have limited virtual memory resources available when operating in
334	* 32-bit kernel space (on 64-bit there'll it's quite a different story). The
335	* tracking structures will be attemted designed such that we can deal with up
336	* to 32GB of memory on a 32-bit system and essentially unlimited on 64-bit ones.
337	*
338	*
339	* @subsubsection subsubsec_pgmPhys_Tracking_Kernel Kernel Space
340	*
341	* @see pg_GMM
342	*
343	* @subsubsection subsubsec_pgmPhys_Tracking_PerVM Per-VM
344	*
345	* Fixed info is the physical address of the page (HCPhys) and the page id
346	* (described above). Theoretically we'll need 48(-12) bits for the HCPhys part.
347	* Today we've restricting ourselves to 40(-12) bits because this is the current
348	* restrictions of all AMD64 implementations (I think Barcelona will up this
349	* to 48(-12) bits, not that it really matters) and I needed the bits for
350	* tracking mappings of a page. 48-12 = 36. That leaves 28 bits, which means a
351	* decent range for the page id: 2^(28+12) = 1024TB.
352	*
353	* In additions to these, we'll have to keep maintaining the page flags as we
354	* currently do. Although it wouldn't harm to optimize these quite a bit, like
355	* for instance the ROM shouldn't depend on having a write handler installed
356	* in order for it to become read-only. A RO/RW bit should be considered so
357	* that the page syncing code doesn't have to mess about checking multiple
358	* flag combinations (ROM \|\| RW handler \|\| write monitored) in order to
359	* figure out how to setup a shadow PTE. But this of course, is second
360	* priority at present. Current this requires 12 bits, but could probably
361	* be optimized to ~8.
362	*
363	* Then there's the 24 bits used to track which shadow page tables are
364	* currently mapping a page for the purpose of speeding up physical
365	* access handlers, and thereby the page pool cache. More bit for this
366	* purpose wouldn't hurt IIRC.
367	*
368	* Then there is a new bit in which we need to record what kind of page
369	* this is, shared, zero, normal or write-monitored-normal. This'll
370	* require 2 bits. One bit might be needed for indicating whether a
371	* write monitored page has been written to. And yet another one or
372	* two for tracking migration status. 3-4 bits total then.
373	*
374	* Whatever is left will can be used to record the sharabilitiy of a
375	* page. The page checksum will not be stored in the per-VM table as
376	* the idle thread will not be permitted to do modifications to it.
377	* It will instead have to keep its own working set of potentially
378	* shareable pages and their check sums and stuff.
379	*
380	* For the present we'll keep the current packing of the
381	* PGMRAMRANGE::aHCPhys to keep the changes simple, only of course,
382	* we'll have to change it to a struct with a total of 128-bits at
383	* our disposal.
384	*
385	* The initial layout will be like this:
386	* @verbatim
387	RTHCPHYS HCPhys; The current stuff.
388	63:40 Current shadow PT tracking stuff.
389	39:12 The physical page frame number.
390	11:0 The current flags.
391	uint32_t u28PageId : 28; The page id.
392	uint32_t u2State : 2; The page state { zero, shared, normal, write monitored }.
393	uint32_t fWrittenTo : 1; Whether a write monitored page was written to.
394	uint32_t u1Reserved : 1; Reserved for later.
395	uint32_t u32Reserved; Reserved for later, mostly sharing stats.
396	@endverbatim
397	*
398	* The final layout will be something like this:
399	* @verbatim
400	RTHCPHYS HCPhys; The current stuff.
401	63:48 High page id (12+).
402	47:12 The physical page frame number.
403	11:0 Low page id.
404	uint32_t fReadOnly : 1; Whether it's readonly page (rom or monitored in some way).
405	uint32_t u3Type : 3; The page type {RESERVED, MMIO, MMIO2, ROM, shadowed ROM, RAM}.
406	uint32_t u2PhysMon : 2; Physical access handler type {none, read, write, all}.
407	uint32_t u2VirtMon : 2; Virtual access handler type {none, read, write, all}..
408	uint32_t u2State : 2; The page state { zero, shared, normal, write monitored }.
409	uint32_t fWrittenTo : 1; Whether a write monitored page was written to.
410	uint32_t u20Reserved : 20; Reserved for later, mostly sharing stats.
411	uint32_t u32Tracking; The shadow PT tracking stuff, roughly.
412	@endverbatim
413	*
414	* Cost wise, this means we'll double the cost for guest memory. There isn't anyway
415	* around that I'm afraid. It means that the cost of dealing out 32GB of memory
416	* to one or more VMs is: (32GB >> PAGE_SHIFT) * 16 bytes, or 128MBs. Or another
417	* example, the VM heap cost when assigning 1GB to a VM will be: 4MB.
418	*
419	* A couple of cost examples for the total cost per-VM + kernel.
420	* 32-bit Windows and 32-bit linux:
421	* 1GB guest ram, 256K pages: 4MB + 2MB(+) = 6MB
422	* 4GB guest ram, 1M pages: 16MB + 8MB(+) = 24MB
423	* 32GB guest ram, 8M pages: 128MB + 64MB(+) = 192MB
424	* 64-bit Windows and 64-bit linux:
425	* 1GB guest ram, 256K pages: 4MB + 3MB(+) = 7MB
426	* 4GB guest ram, 1M pages: 16MB + 12MB(+) = 28MB
427	* 32GB guest ram, 8M pages: 128MB + 96MB(+) = 224MB
428	*
429	* UPDATE - 2007-09-27:
430	* Will need a ballooned flag/state too because we cannot
431	* trust the guest 100% and reporting the same page as ballooned more
432	* than once will put the GMM off balance.
433	*
434	*
435	* @subsection subsec_pgmPhys_Serializing Serializing Access
436	*
437	* Initially, we'll try a simple scheme:
438	*
439	* - The per-VM RAM tracking structures (PGMRAMRANGE) is only modified
440	* by the EMT thread of that VM while in the pgm critsect.
441	* - Other threads in the VM process that needs to make reliable use of
442	* the per-VM RAM tracking structures will enter the critsect.
443	* - No process external thread or kernel thread will ever try enter
444	* the pgm critical section, as that just won't work.
445	* - The idle thread (and similar threads) doesn't not need 100% reliable
446	* data when performing it tasks as the EMT thread will be the one to
447	* do the actual changes later anyway. So, as long as it only accesses
448	* the main ram range, it can do so by somehow preventing the VM from
449	* being destroyed while it works on it...
450	*
451	* - The over-commitment management, including the allocating/freeing
452	* chunks, is serialized by a ring-0 mutex lock (a fast one since the
453	* more mundane mutex implementation is broken on Linux).
454	* - A separeate mutex is protecting the set of allocation chunks so
455	* that pages can be shared or/and freed up while some other VM is
456	* allocating more chunks. This mutex can be take from under the other
457	* one, but not the otherway around.
458	*
459	*
460	* @subsection subsec_pgmPhys_Request VM Request interface
461	*
462	* When in ring-0 it will become necessary to send requests to a VM so it can
463	* for instance move a page while defragmenting during VM destroy. The idle
464	* thread will make use of this interface to request VMs to setup shared
465	* pages and to perform write monitoring of pages.
466	*
467	* I would propose an interface similar to the current VMReq interface, similar
468	* in that it doesn't require locking and that the one sending the request may
469	* wait for completion if it wishes to. This shouldn't be very difficult to
470	* realize.
471	*
472	* The requests themselves are also pretty simple. They are basically:
473	* -# Check that some precondition is still true.
474	* -# Do the update.
475	* -# Update all shadow page tables involved with the page.
476	*
477	* The 3rd step is identical to what we're already doing when updating a
478	* physical handler, see pgmHandlerPhysicalSetRamFlagsAndFlushShadowPTs.
479	*
480	*
481	*
482	* @section sec_pgmPhys_MappingCaches Mapping Caches
483	*
484	* In order to be able to map in and out memory and to be able to support
485	* guest with more RAM than we've got virtual address space, we'll employing
486	* a mapping cache. There is already a tiny one for GC (see PGMGCDynMapGCPageEx)
487	* and we'll create a similar one for ring-0 unless we decide to setup a dedicate
488	* memory context for the HWACCM execution.
489	*
490	*
491	* @subsection subsec_pgmPhys_MappingCaches_R3 Ring-3
492	*
493	* We've considered implementing the ring-3 mapping cache page based but found
494	* that this was bother some when one had to take into account TLBs+SMP and
495	* portability (missing the necessary APIs on several platforms). There were
496	* also some performance concerns with this approach which hadn't quite been
497	* worked out.
498	*
499	* Instead, we'll be mapping allocation chunks into the VM process. This simplifies
500	* matters greatly quite a bit since we don't need to invent any new ring-0 stuff,
501	* only some minor RTR0MEMOBJ mapping stuff. The main concern here is that mapping
502	* compared to the previous idea is that mapping or unmapping a 1MB chunk is more
503	* costly than a single page, although how much more costly is uncertain. We'll
504	* try address this by using a very big cache, preferably bigger than the actual
505	* VM RAM size if possible. The current VM RAM sizes should give some idea for
506	* 32-bit boxes, while on 64-bit we can probably get away with employing an
507	* unlimited cache.
508	*
509	* The cache have to parts, as already indicated, the ring-3 side and the
510	* ring-0 side.
511	*
512	* The ring-0 will be tied to the page allocator since it will operate on the
513	* memory objects it contains. It will therefore require the first ring-0 mutex
514	* discussed in @ref subsec_pgmPhys_Serializing. We
515	* some double house keeping wrt to who has mapped what I think, since both
516	* VMMR0.r0 and RTR0MemObj will keep track of mapping relataions
517	*
518	* The ring-3 part will be protected by the pgm critsect. For simplicity, we'll
519	* require anyone that desires to do changes to the mapping cache to do that
520	* from within this critsect. Alternatively, we could employ a separate critsect
521	* for serializing changes to the mapping cache as this would reduce potential
522	* contention with other threads accessing mappings unrelated to the changes
523	* that are in process. We can see about this later, contention will show
524	* up in the statistics anyway, so it'll be simple to tell.
525	*
526	* The organization of the ring-3 part will be very much like how the allocation
527	* chunks are organized in ring-0, that is in an AVL tree by chunk id. To avoid
528	* having to walk the tree all the time, we'll have a couple of lookaside entries
529	* like in we do for I/O ports and MMIO in IOM.
530	*
531	* The simplified flow of a PGMPhysRead/Write function:
532	* -# Enter the PGM critsect.
533	* -# Lookup GCPhys in the ram ranges and get the Page ID.
534	* -# Calc the Allocation Chunk ID from the Page ID.
535	* -# Check the lookaside entries and then the AVL tree for the Chunk ID.
536	* If not found in cache:
537	* -# Call ring-0 and request it to be mapped and supply
538	* a chunk to be unmapped if the cache is maxed out already.
539	* -# Insert the new mapping into the AVL tree (id + R3 address).
540	* -# Update the relevant lookaside entry and return the mapping address.
541	* -# Do the read/write according to monitoring flags and everything.
542	* -# Leave the critsect.
543	*
544	*
545	* @section sec_pgmPhys_Fallback Fallback
546	*
547	* Current all the "second tier" hosts will not support the RTR0MemObjAllocPhysNC
548	* API and thus require a fallback.
549	*
550	* So, when RTR0MemObjAllocPhysNC returns VERR_NOT_SUPPORTED the page allocator
551	* will return to the ring-3 caller (and later ring-0) and asking it to seed
552	* the page allocator with some fresh pages (VERR_GMM_SEED_ME). Ring-3 will
553	* then perform an SUPPageAlloc(cbChunk >> PAGE_SHIFT) call and make a
554	* "SeededAllocPages" call to ring-0.
555	*
556	* The first time ring-0 sees the VERR_NOT_SUPPORTED failure it will disable
557	* all page sharing (zero page detection will continue). It will also force
558	* all allocations to come from the VM which seeded the page. Both these
559	* measures are taken to make sure that there will never be any need for
560	* mapping anything into ring-3 - everything will be mapped already.
561	*
562	* Whether we'll continue to use the current MM locked memory management
563	* for this I don't quite know (I'd prefer not to and just ditch that all
564	* togther), we'll see what's simplest to do.
565	*
566	*
567	*
568	* @section sec_pgmPhys_Changes Changes
569	*
570	* Breakdown of the changes involved?
571	*/
572
573
574	/** Saved state data unit version. */
575	#define PGM_SAVED_STATE_VERSION 6
576
577	/*******************************************************************************
578	* Header Files *
579	*******************************************************************************/
580	#define LOG_GROUP LOG_GROUP_PGM
581	#include <VBox/dbgf.h>
582	#include <VBox/pgm.h>
583	#include <VBox/cpum.h>
584	#include <VBox/iom.h>
585	#include <VBox/sup.h>
586	#include <VBox/mm.h>
587	#include <VBox/em.h>
588	#include <VBox/stam.h>
589	#include <VBox/rem.h>
590	#include <VBox/dbgf.h>
591	#include <VBox/rem.h>
592	#include <VBox/selm.h>
593	#include <VBox/ssm.h>
594	#include "PGMInternal.h"
595	#include <VBox/vm.h>
596	#include <VBox/dbg.h>
597	#include <VBox/hwaccm.h>
598
599	#include <iprt/assert.h>
600	#include <iprt/alloc.h>
601	#include <iprt/asm.h>
602	#include <iprt/thread.h>
603	#include <iprt/string.h>
604	#include <VBox/param.h>
605	#include <VBox/err.h>
606
607
608
609	/*******************************************************************************
610	* Internal Functions *
611	*******************************************************************************/
612	static int pgmR3InitPaging(PVM pVM);
613	static DECLCALLBACK(void) pgmR3PhysInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
614	static DECLCALLBACK(void) pgmR3InfoMode(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
615	static DECLCALLBACK(void) pgmR3InfoCr3(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
616	static DECLCALLBACK(int) pgmR3RelocatePhysHandler(PAVLROGCPHYSNODECORE pNode, void *pvUser);
617	static DECLCALLBACK(int) pgmR3RelocateVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser);
618	static DECLCALLBACK(int) pgmR3RelocateHyperVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser);
619	#ifdef VBOX_STRICT
620	static DECLCALLBACK(void) pgmR3ResetNoMorePhysWritesFlag(PVM pVM, VMSTATE enmState, VMSTATE enmOldState, void *pvUser);
621	#endif
622	static DECLCALLBACK(int) pgmR3Save(PVM pVM, PSSMHANDLE pSSM);
623	static DECLCALLBACK(int) pgmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version);
624	static int pgmR3ModeDataInit(PVM pVM, bool fResolveGCAndR0);
625	static void pgmR3ModeDataSwitch(PVM pVM, PGMMODE enmShw, PGMMODE enmGst);
626	static PGMMODE pgmR3CalcShadowMode(PVM pVM, PGMMODE enmGuestMode, SUPPAGINGMODE enmHostMode, PGMMODE enmShadowMode, VMMSWITCHER *penmSwitcher);
627
628	#ifdef VBOX_WITH_STATISTICS
629	static void pgmR3InitStats(PVM pVM);
630	#endif
631
632	#ifdef VBOX_WITH_DEBUGGER
633	/** @todo all but the two last commands must be converted to 'info'. */
634	static DECLCALLBACK(int) pgmR3CmdRam(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
635	static DECLCALLBACK(int) pgmR3CmdMap(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
636	static DECLCALLBACK(int) pgmR3CmdSync(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
637	static DECLCALLBACK(int) pgmR3CmdSyncAlways(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
638	# ifdef VBOX_STRICT
639	static DECLCALLBACK(int) pgmR3CmdAssertCR3(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
640	# endif
641	#endif
642
643
644	/*******************************************************************************
645	* Global Variables *
646	*******************************************************************************/
647	#ifdef VBOX_WITH_DEBUGGER
648	/** Command descriptors. */
649	static const DBGCCMD g_aCmds[] =
650	{
651	/* pszCmd, cArgsMin, cArgsMax, paArgDesc, cArgDescs, pResultDesc, fFlags, pfnHandler pszSyntax, ....pszDescription */
652	{ "pgmram", 0, 0, NULL, 0, NULL, 0, pgmR3CmdRam, "", "Display the ram ranges." },
653	{ "pgmmap", 0, 0, NULL, 0, NULL, 0, pgmR3CmdMap, "", "Display the mapping ranges." },
654	{ "pgmsync", 0, 0, NULL, 0, NULL, 0, pgmR3CmdSync, "", "Sync the CR3 page." },
655	#ifdef VBOX_STRICT
656	{ "pgmassertcr3", 0, 0, NULL, 0, NULL, 0, pgmR3CmdAssertCR3, "", "Check the shadow CR3 mapping." },
657	#endif
658	{ "pgmsyncalways", 0, 0, NULL, 0, NULL, 0, pgmR3CmdSyncAlways, "", "Toggle permanent CR3 syncing." },
659	};
660	#endif
661
662
663
664
665	/*
666	* Shadow - 32-bit mode
667	*/
668	#define PGM_SHW_TYPE PGM_TYPE_32BIT
669	#define PGM_SHW_NAME(name) PGM_SHW_NAME_32BIT(name)
670	#define PGM_SHW_NAME_GC_STR(name) PGM_SHW_NAME_GC_32BIT_STR(name)
671	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_32BIT_STR(name)
672	#include "PGMShw.h"
673
674	/* Guest - real mode */
675	#define PGM_GST_TYPE PGM_TYPE_REAL
676	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
677	#define PGM_GST_NAME_GC_STR(name) PGM_GST_NAME_GC_REAL_STR(name)
678	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
679	#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_REAL(name)
680	#define PGM_BTH_NAME_GC_STR(name) PGM_BTH_NAME_GC_32BIT_REAL_STR(name)
681	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_32BIT_REAL_STR(name)
682	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_PHYS
683	#include "PGMGst.h"
684	#include "PGMBth.h"
685	#undef BTH_PGMPOOLKIND_PT_FOR_PT
686	#undef PGM_BTH_NAME
687	#undef PGM_BTH_NAME_GC_STR
688	#undef PGM_BTH_NAME_R0_STR
689	#undef PGM_GST_TYPE
690	#undef PGM_GST_NAME
691	#undef PGM_GST_NAME_GC_STR
692	#undef PGM_GST_NAME_R0_STR
693
694	/* Guest - protected mode */
695	#define PGM_GST_TYPE PGM_TYPE_PROT
696	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
697	#define PGM_GST_NAME_GC_STR(name) PGM_GST_NAME_GC_PROT_STR(name)
698	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
699	#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_PROT(name)
700	#define PGM_BTH_NAME_GC_STR(name) PGM_BTH_NAME_GC_32BIT_PROT_STR(name)
701	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_32BIT_PROT_STR(name)
702	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_PHYS
703	#include "PGMGst.h"
704	#include "PGMBth.h"
705	#undef BTH_PGMPOOLKIND_PT_FOR_PT
706	#undef PGM_BTH_NAME
707	#undef PGM_BTH_NAME_GC_STR
708	#undef PGM_BTH_NAME_R0_STR
709	#undef PGM_GST_TYPE
710	#undef PGM_GST_NAME
711	#undef PGM_GST_NAME_GC_STR
712	#undef PGM_GST_NAME_R0_STR
713
714	/* Guest - 32-bit mode */
715	#define PGM_GST_TYPE PGM_TYPE_32BIT
716	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
717	#define PGM_GST_NAME_GC_STR(name) PGM_GST_NAME_GC_32BIT_STR(name)
718	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
719	#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_32BIT(name)
720	#define PGM_BTH_NAME_GC_STR(name) PGM_BTH_NAME_GC_32BIT_32BIT_STR(name)
721	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_32BIT_32BIT_STR(name)
722	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT
723	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB
724	#include "PGMGst.h"
725	#include "PGMBth.h"
726	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
727	#undef BTH_PGMPOOLKIND_PT_FOR_PT
728	#undef PGM_BTH_NAME
729	#undef PGM_BTH_NAME_GC_STR
730	#undef PGM_BTH_NAME_R0_STR
731	#undef PGM_GST_TYPE
732	#undef PGM_GST_NAME
733	#undef PGM_GST_NAME_GC_STR
734	#undef PGM_GST_NAME_R0_STR
735
736	#undef PGM_SHW_TYPE
737	#undef PGM_SHW_NAME
738	#undef PGM_SHW_NAME_GC_STR
739	#undef PGM_SHW_NAME_R0_STR
740
741
742	/*
743	* Shadow - PAE mode
744	*/
745	#define PGM_SHW_TYPE PGM_TYPE_PAE
746	#define PGM_SHW_NAME(name) PGM_SHW_NAME_PAE(name)
747	#define PGM_SHW_NAME_GC_STR(name) PGM_SHW_NAME_GC_PAE_STR(name)
748	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_PAE_STR(name)
749	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_REAL(name)
750	#include "PGMShw.h"
751
752	/* Guest - real mode */
753	#define PGM_GST_TYPE PGM_TYPE_REAL
754	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
755	#define PGM_GST_NAME_GC_STR(name) PGM_GST_NAME_GC_REAL_STR(name)
756	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
757	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_REAL(name)
758	#define PGM_BTH_NAME_GC_STR(name) PGM_BTH_NAME_GC_PAE_REAL_STR(name)
759	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_REAL_STR(name)
760	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
761	#include "PGMBth.h"
762	#undef BTH_PGMPOOLKIND_PT_FOR_PT
763	#undef PGM_BTH_NAME
764	#undef PGM_BTH_NAME_GC_STR
765	#undef PGM_BTH_NAME_R0_STR
766	#undef PGM_GST_TYPE
767	#undef PGM_GST_NAME
768	#undef PGM_GST_NAME_GC_STR
769	#undef PGM_GST_NAME_R0_STR
770
771	/* Guest - protected mode */
772	#define PGM_GST_TYPE PGM_TYPE_PROT
773	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
774	#define PGM_GST_NAME_GC_STR(name) PGM_GST_NAME_GC_PROT_STR(name)
775	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
776	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_PROT(name)
777	#define PGM_BTH_NAME_GC_STR(name) PGM_BTH_NAME_GC_PAE_PROT_STR(name)
778	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_PROT_STR(name)
779	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
780	#include "PGMBth.h"
781	#undef BTH_PGMPOOLKIND_PT_FOR_PT
782	#undef PGM_BTH_NAME
783	#undef PGM_BTH_NAME_GC_STR
784	#undef PGM_BTH_NAME_R0_STR
785	#undef PGM_GST_TYPE
786	#undef PGM_GST_NAME
787	#undef PGM_GST_NAME_GC_STR
788	#undef PGM_GST_NAME_R0_STR
789
790	/* Guest - 32-bit mode */
791	#define PGM_GST_TYPE PGM_TYPE_32BIT
792	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
793	#define PGM_GST_NAME_GC_STR(name) PGM_GST_NAME_GC_32BIT_STR(name)
794	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
795	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_32BIT(name)
796	#define PGM_BTH_NAME_GC_STR(name) PGM_BTH_NAME_GC_PAE_32BIT_STR(name)
797	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_32BIT_STR(name)
798	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_32BIT_PT
799	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB
800	#include "PGMBth.h"
801	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
802	#undef BTH_PGMPOOLKIND_PT_FOR_PT
803	#undef PGM_BTH_NAME
804	#undef PGM_BTH_NAME_GC_STR
805	#undef PGM_BTH_NAME_R0_STR
806	#undef PGM_GST_TYPE
807	#undef PGM_GST_NAME
808	#undef PGM_GST_NAME_GC_STR
809	#undef PGM_GST_NAME_R0_STR
810
811	/* Guest - PAE mode */
812	#define PGM_GST_TYPE PGM_TYPE_PAE
813	#define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
814	#define PGM_GST_NAME_GC_STR(name) PGM_GST_NAME_GC_PAE_STR(name)
815	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PAE_STR(name)
816	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_PAE(name)
817	#define PGM_BTH_NAME_GC_STR(name) PGM_BTH_NAME_GC_PAE_PAE_STR(name)
818	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_PAE_STR(name)
819	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
820	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
821	#include "PGMGst.h"
822	#include "PGMBth.h"
823	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
824	#undef BTH_PGMPOOLKIND_PT_FOR_PT
825	#undef PGM_BTH_NAME
826	#undef PGM_BTH_NAME_GC_STR
827	#undef PGM_BTH_NAME_R0_STR
828	#undef PGM_GST_TYPE
829	#undef PGM_GST_NAME
830	#undef PGM_GST_NAME_GC_STR
831	#undef PGM_GST_NAME_R0_STR
832
833	#undef PGM_SHW_TYPE
834	#undef PGM_SHW_NAME
835	#undef PGM_SHW_NAME_GC_STR
836	#undef PGM_SHW_NAME_R0_STR
837
838
839	/*
840	* Shadow - AMD64 mode
841	*/
842	#define PGM_SHW_TYPE PGM_TYPE_AMD64
843	#define PGM_SHW_NAME(name) PGM_SHW_NAME_AMD64(name)
844	#define PGM_SHW_NAME_GC_STR(name) PGM_SHW_NAME_GC_AMD64_STR(name)
845	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_AMD64_STR(name)
846	#include "PGMShw.h"
847
848	/* Guest - AMD64 mode */
849	#define PGM_GST_TYPE PGM_TYPE_AMD64
850	#define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
851	#define PGM_GST_NAME_GC_STR(name) PGM_GST_NAME_GC_AMD64_STR(name)
852	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_AMD64_STR(name)
853	#define PGM_BTH_NAME(name) PGM_BTH_NAME_AMD64_AMD64(name)
854	#define PGM_BTH_NAME_GC_STR(name) PGM_BTH_NAME_GC_AMD64_AMD64_STR(name)
855	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_AMD64_AMD64_STR(name)
856	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
857	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
858	#include "PGMGst.h"
859	#include "PGMBth.h"
860	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
861	#undef BTH_PGMPOOLKIND_PT_FOR_PT
862	#undef PGM_BTH_NAME
863	#undef PGM_BTH_NAME_GC_STR
864	#undef PGM_BTH_NAME_R0_STR
865	#undef PGM_GST_TYPE
866	#undef PGM_GST_NAME
867	#undef PGM_GST_NAME_GC_STR
868	#undef PGM_GST_NAME_R0_STR
869
870	#undef PGM_SHW_TYPE
871	#undef PGM_SHW_NAME
872	#undef PGM_SHW_NAME_GC_STR
873	#undef PGM_SHW_NAME_R0_STR
874
875	/*
876	* Shadow - Nested paging mode
877	*/
878	#define PGM_SHW_TYPE PGM_TYPE_NESTED
879	#define PGM_SHW_NAME(name) PGM_SHW_NAME_NESTED(name)
880	#define PGM_SHW_NAME_GC_STR(name) PGM_SHW_NAME_GC_NESTED_STR(name)
881	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_NESTED_STR(name)
882	#include "PGMShw.h"
883
884	/* Guest - real mode */
885	#define PGM_GST_TYPE PGM_TYPE_REAL
886	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
887	#define PGM_GST_NAME_GC_STR(name) PGM_GST_NAME_GC_REAL_STR(name)
888	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
889	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_REAL(name)
890	#define PGM_BTH_NAME_GC_STR(name) PGM_BTH_NAME_GC_NESTED_REAL_STR(name)
891	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_REAL_STR(name)
892	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
893	#include "PGMBth.h"
894	#undef BTH_PGMPOOLKIND_PT_FOR_PT
895	#undef PGM_BTH_NAME
896	#undef PGM_BTH_NAME_GC_STR
897	#undef PGM_BTH_NAME_R0_STR
898	#undef PGM_GST_TYPE
899	#undef PGM_GST_NAME
900	#undef PGM_GST_NAME_GC_STR
901	#undef PGM_GST_NAME_R0_STR
902
903	/* Guest - protected mode */
904	#define PGM_GST_TYPE PGM_TYPE_PROT
905	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
906	#define PGM_GST_NAME_GC_STR(name) PGM_GST_NAME_GC_PROT_STR(name)
907	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
908	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_PROT(name)
909	#define PGM_BTH_NAME_GC_STR(name) PGM_BTH_NAME_GC_NESTED_PROT_STR(name)
910	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_PROT_STR(name)
911	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
912	#include "PGMBth.h"
913	#undef BTH_PGMPOOLKIND_PT_FOR_PT
914	#undef PGM_BTH_NAME
915	#undef PGM_BTH_NAME_GC_STR
916	#undef PGM_BTH_NAME_R0_STR
917	#undef PGM_GST_TYPE
918	#undef PGM_GST_NAME
919	#undef PGM_GST_NAME_GC_STR
920	#undef PGM_GST_NAME_R0_STR
921
922	/* Guest - 32-bit mode */
923	#define PGM_GST_TYPE PGM_TYPE_32BIT
924	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
925	#define PGM_GST_NAME_GC_STR(name) PGM_GST_NAME_GC_32BIT_STR(name)
926	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
927	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_32BIT(name)
928	#define PGM_BTH_NAME_GC_STR(name) PGM_BTH_NAME_GC_NESTED_32BIT_STR(name)
929	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_32BIT_STR(name)
930	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_32BIT_PT
931	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB
932	#include "PGMBth.h"
933	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
934	#undef BTH_PGMPOOLKIND_PT_FOR_PT
935	#undef PGM_BTH_NAME
936	#undef PGM_BTH_NAME_GC_STR
937	#undef PGM_BTH_NAME_R0_STR
938	#undef PGM_GST_TYPE
939	#undef PGM_GST_NAME
940	#undef PGM_GST_NAME_GC_STR
941	#undef PGM_GST_NAME_R0_STR
942
943	/* Guest - PAE mode */
944	#define PGM_GST_TYPE PGM_TYPE_PAE
945	#define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
946	#define PGM_GST_NAME_GC_STR(name) PGM_GST_NAME_GC_PAE_STR(name)
947	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PAE_STR(name)
948	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_PAE(name)
949	#define PGM_BTH_NAME_GC_STR(name) PGM_BTH_NAME_GC_NESTED_PAE_STR(name)
950	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_PAE_STR(name)
951	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
952	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
953	#include "PGMBth.h"
954	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
955	#undef BTH_PGMPOOLKIND_PT_FOR_PT
956	#undef PGM_BTH_NAME
957	#undef PGM_BTH_NAME_GC_STR
958	#undef PGM_BTH_NAME_R0_STR
959	#undef PGM_GST_TYPE
960	#undef PGM_GST_NAME
961	#undef PGM_GST_NAME_GC_STR
962	#undef PGM_GST_NAME_R0_STR
963
964	/* Guest - AMD64 mode */
965	#define PGM_GST_TYPE PGM_TYPE_AMD64
966	#define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
967	#define PGM_GST_NAME_GC_STR(name) PGM_GST_NAME_GC_AMD64_STR(name)
968	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_AMD64_STR(name)
969	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_AMD64(name)
970	#define PGM_BTH_NAME_GC_STR(name) PGM_BTH_NAME_GC_NESTED_AMD64_STR(name)
971	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_AMD64_STR(name)
972	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
973	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
974	#include "PGMBth.h"
975	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
976	#undef BTH_PGMPOOLKIND_PT_FOR_PT
977	#undef PGM_BTH_NAME
978	#undef PGM_BTH_NAME_GC_STR
979	#undef PGM_BTH_NAME_R0_STR
980	#undef PGM_GST_TYPE
981	#undef PGM_GST_NAME
982	#undef PGM_GST_NAME_GC_STR
983	#undef PGM_GST_NAME_R0_STR
984
985	#undef PGM_SHW_TYPE
986	#undef PGM_SHW_NAME
987	#undef PGM_SHW_NAME_GC_STR
988	#undef PGM_SHW_NAME_R0_STR
989
990	/*
991	* Shadow - EPT
992	*/
993	#define PGM_SHW_TYPE PGM_TYPE_EPT
994	#define PGM_SHW_NAME(name) PGM_SHW_NAME_EPT(name)
995	#define PGM_SHW_NAME_GC_STR(name) PGM_SHW_NAME_GC_EPT_STR(name)
996	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_EPT_STR(name)
997	#include "PGMShw.h"
998
999	/* Guest - real mode */
1000	#define PGM_GST_TYPE PGM_TYPE_REAL
1001	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
1002	#define PGM_GST_NAME_GC_STR(name) PGM_GST_NAME_GC_REAL_STR(name)
1003	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
1004	#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_REAL(name)
1005	#define PGM_BTH_NAME_GC_STR(name) PGM_BTH_NAME_GC_EPT_REAL_STR(name)
1006	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_REAL_STR(name)
1007	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
1008	#include "PGMBth.h"
1009	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1010	#undef PGM_BTH_NAME
1011	#undef PGM_BTH_NAME_GC_STR
1012	#undef PGM_BTH_NAME_R0_STR
1013	#undef PGM_GST_TYPE
1014	#undef PGM_GST_NAME
1015	#undef PGM_GST_NAME_GC_STR
1016	#undef PGM_GST_NAME_R0_STR
1017
1018	/* Guest - protected mode */
1019	#define PGM_GST_TYPE PGM_TYPE_PROT
1020	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
1021	#define PGM_GST_NAME_GC_STR(name) PGM_GST_NAME_GC_PROT_STR(name)
1022	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
1023	#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_PROT(name)
1024	#define PGM_BTH_NAME_GC_STR(name) PGM_BTH_NAME_GC_EPT_PROT_STR(name)
1025	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_PROT_STR(name)
1026	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
1027	#include "PGMBth.h"
1028	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1029	#undef PGM_BTH_NAME
1030	#undef PGM_BTH_NAME_GC_STR
1031	#undef PGM_BTH_NAME_R0_STR
1032	#undef PGM_GST_TYPE
1033	#undef PGM_GST_NAME
1034	#undef PGM_GST_NAME_GC_STR
1035	#undef PGM_GST_NAME_R0_STR
1036
1037	/* Guest - 32-bit mode */
1038	#define PGM_GST_TYPE PGM_TYPE_32BIT
1039	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
1040	#define PGM_GST_NAME_GC_STR(name) PGM_GST_NAME_GC_32BIT_STR(name)
1041	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
1042	#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_32BIT(name)
1043	#define PGM_BTH_NAME_GC_STR(name) PGM_BTH_NAME_GC_EPT_32BIT_STR(name)
1044	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_32BIT_STR(name)
1045	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_32BIT_PT
1046	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB
1047	#include "PGMBth.h"
1048	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
1049	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1050	#undef PGM_BTH_NAME
1051	#undef PGM_BTH_NAME_GC_STR
1052	#undef PGM_BTH_NAME_R0_STR
1053	#undef PGM_GST_TYPE
1054	#undef PGM_GST_NAME
1055	#undef PGM_GST_NAME_GC_STR
1056	#undef PGM_GST_NAME_R0_STR
1057
1058	/* Guest - PAE mode */
1059	#define PGM_GST_TYPE PGM_TYPE_PAE
1060	#define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
1061	#define PGM_GST_NAME_GC_STR(name) PGM_GST_NAME_GC_PAE_STR(name)
1062	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PAE_STR(name)
1063	#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_PAE(name)
1064	#define PGM_BTH_NAME_GC_STR(name) PGM_BTH_NAME_GC_EPT_PAE_STR(name)
1065	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_PAE_STR(name)
1066	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
1067	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
1068	#include "PGMBth.h"
1069	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
1070	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1071	#undef PGM_BTH_NAME
1072	#undef PGM_BTH_NAME_GC_STR
1073	#undef PGM_BTH_NAME_R0_STR
1074	#undef PGM_GST_TYPE
1075	#undef PGM_GST_NAME
1076	#undef PGM_GST_NAME_GC_STR
1077	#undef PGM_GST_NAME_R0_STR
1078
1079	/* Guest - AMD64 mode */
1080	#define PGM_GST_TYPE PGM_TYPE_AMD64
1081	#define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
1082	#define PGM_GST_NAME_GC_STR(name) PGM_GST_NAME_GC_AMD64_STR(name)
1083	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_AMD64_STR(name)
1084	#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_AMD64(name)
1085	#define PGM_BTH_NAME_GC_STR(name) PGM_BTH_NAME_GC_EPT_AMD64_STR(name)
1086	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_AMD64_STR(name)
1087	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
1088	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
1089	#include "PGMBth.h"
1090	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
1091	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1092	#undef PGM_BTH_NAME
1093	#undef PGM_BTH_NAME_GC_STR
1094	#undef PGM_BTH_NAME_R0_STR
1095	#undef PGM_GST_TYPE
1096	#undef PGM_GST_NAME
1097	#undef PGM_GST_NAME_GC_STR
1098	#undef PGM_GST_NAME_R0_STR
1099
1100	#undef PGM_SHW_TYPE
1101	#undef PGM_SHW_NAME
1102	#undef PGM_SHW_NAME_GC_STR
1103	#undef PGM_SHW_NAME_R0_STR
1104
1105	/**
1106	* Initiates the paging of VM.
1107	*
1108	* @returns VBox status code.
1109	* @param pVM Pointer to VM structure.
1110	*/
1111	VMMR3DECL(int) PGMR3Init(PVM pVM)
1112	{
1113	LogFlow(("PGMR3Init:\n"));
1114
1115	/*
1116	* Assert alignment and sizes.
1117	*/
1118	AssertRelease(sizeof(pVM->pgm.s) <= sizeof(pVM->pgm.padding));
1119
1120	/*
1121	* Init the structure.
1122	*/
1123	pVM->pgm.s.offVM = RT_OFFSETOF(VM, pgm.s);
1124	pVM->pgm.s.enmShadowMode = PGMMODE_INVALID;
1125	pVM->pgm.s.enmGuestMode = PGMMODE_INVALID;
1126	pVM->pgm.s.enmHostMode = SUPPAGINGMODE_INVALID;
1127	pVM->pgm.s.GCPhysCR3 = NIL_RTGCPHYS;
1128	pVM->pgm.s.GCPhysGstCR3Monitored = NIL_RTGCPHYS;
1129	pVM->pgm.s.fA20Enabled = true;
1130	pVM->pgm.s.GCPhys4MBPSEMask = RT_BIT_64(32) - 1; /* default; checked later */
1131	pVM->pgm.s.pGstPaePDPTHC = NULL;
1132	pVM->pgm.s.pGstPaePDPTGC = 0;
1133	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.apGstPaePDsHC); i++)
1134	{
1135	pVM->pgm.s.apGstPaePDsHC[i] = NULL;
1136	pVM->pgm.s.apGstPaePDsGC[i] = 0;
1137	pVM->pgm.s.aGCPhysGstPaePDs[i] = NIL_RTGCPHYS;
1138	pVM->pgm.s.aGCPhysGstPaePDsMonitored[i] = NIL_RTGCPHYS;
1139	}
1140
1141	#ifdef VBOX_STRICT
1142	VMR3AtStateRegister(pVM, pgmR3ResetNoMorePhysWritesFlag, NULL);
1143	#endif
1144
1145	/*
1146	* Get the configured RAM size - to estimate saved state size.
1147	*/
1148	uint64_t cbRam;
1149	int rc = CFGMR3QueryU64(CFGMR3GetRoot(pVM), "RamSize", &cbRam);
1150	if (rc == VERR_CFGM_VALUE_NOT_FOUND)
1151	cbRam = pVM->pgm.s.cbRamSize = 0;
1152	else if (VBOX_SUCCESS(rc))
1153	{
1154	if (cbRam < PAGE_SIZE)
1155	cbRam = 0;
1156	cbRam = RT_ALIGN_64(cbRam, PAGE_SIZE);
1157	pVM->pgm.s.cbRamSize = (RTUINT)cbRam;
1158	}
1159	else
1160	{
1161	AssertMsgFailed(("Configuration error: Failed to query integer \"RamSize\", rc=%Vrc.\n", rc));
1162	return rc;
1163	}
1164
1165	/*
1166	* Register saved state data unit.
1167	*/
1168	rc = SSMR3RegisterInternal(pVM, "pgm", 1, PGM_SAVED_STATE_VERSION, (size_t)cbRam + sizeof(PGM),
1169	NULL, pgmR3Save, NULL,
1170	NULL, pgmR3Load, NULL);
1171	if (VBOX_FAILURE(rc))
1172	return rc;
1173
1174	/*
1175	* Initialize the PGM critical section and flush the phys TLBs
1176	*/
1177	rc = PDMR3CritSectInit(pVM, &pVM->pgm.s.CritSect, "PGM");
1178	AssertRCReturn(rc, rc);
1179
1180	PGMR3PhysChunkInvalidateTLB(pVM);
1181	PGMPhysInvalidatePageR3MapTLB(pVM);
1182	PGMPhysInvalidatePageR0MapTLB(pVM);
1183	PGMPhysInvalidatePageGCMapTLB(pVM);
1184
1185	/*
1186	* Trees
1187	*/
1188	rc = MMHyperAlloc(pVM, sizeof(PGMTREES), 0, MM_TAG_PGM, (void **)&pVM->pgm.s.pTreesHC);
1189	if (VBOX_SUCCESS(rc))
1190	{
1191	pVM->pgm.s.pTreesGC = MMHyperHC2GC(pVM, pVM->pgm.s.pTreesHC);
1192
1193	/*
1194	* Alocate the zero page.
1195	*/
1196	rc = MMHyperAlloc(pVM, PAGE_SIZE, PAGE_SIZE, MM_TAG_PGM, &pVM->pgm.s.pvZeroPgR3);
1197	}
1198	if (VBOX_SUCCESS(rc))
1199	{
1200	pVM->pgm.s.pvZeroPgGC = MMHyperR3ToRC(pVM, pVM->pgm.s.pvZeroPgR3);
1201	pVM->pgm.s.pvZeroPgR0 = MMHyperR3ToR0(pVM, pVM->pgm.s.pvZeroPgR3);
1202	AssertRelease(pVM->pgm.s.pvZeroPgR0 != NIL_RTHCPHYS);
1203	pVM->pgm.s.HCPhysZeroPg = MMR3HyperHCVirt2HCPhys(pVM, pVM->pgm.s.pvZeroPgR3);
1204	AssertRelease(pVM->pgm.s.HCPhysZeroPg != NIL_RTHCPHYS);
1205
1206	/*
1207	* Init the paging.
1208	*/
1209	rc = pgmR3InitPaging(pVM);
1210	}
1211	if (VBOX_SUCCESS(rc))
1212	{
1213	/*
1214	* Init the page pool.
1215	*/
1216	rc = pgmR3PoolInit(pVM);
1217	}
1218	if (VBOX_SUCCESS(rc))
1219	{
1220	/*
1221	* Info & statistics
1222	*/
1223	DBGFR3InfoRegisterInternal(pVM, "mode",
1224	"Shows the current paging mode. "
1225	"Recognizes 'all', 'guest', 'shadow' and 'host' as arguments, defaulting to 'all' if nothing's given.",
1226	pgmR3InfoMode);
1227	DBGFR3InfoRegisterInternal(pVM, "pgmcr3",
1228	"Dumps all the entries in the top level paging table. No arguments.",
1229	pgmR3InfoCr3);
1230	DBGFR3InfoRegisterInternal(pVM, "phys",
1231	"Dumps all the physical address ranges. No arguments.",
1232	pgmR3PhysInfo);
1233	DBGFR3InfoRegisterInternal(pVM, "handlers",
1234	"Dumps physical, virtual and hyper virtual handlers. "
1235	"Pass 'phys', 'virt', 'hyper' as argument if only one kind is wanted."
1236	"Add 'nost' if the statistics are unwanted, use together with 'all' or explicit selection.",
1237	pgmR3InfoHandlers);
1238	DBGFR3InfoRegisterInternal(pVM, "mappings",
1239	"Dumps guest mappings.",
1240	pgmR3MapInfo);
1241
1242	STAM_REL_REG(pVM, &pVM->pgm.s.cGuestModeChanges, STAMTYPE_COUNTER, "/PGM/cGuestModeChanges", STAMUNIT_OCCURENCES, "Number of guest mode changes.");
1243	#ifdef VBOX_WITH_STATISTICS
1244	pgmR3InitStats(pVM);
1245	#endif
1246	#ifdef VBOX_WITH_DEBUGGER
1247	/*
1248	* Debugger commands.
1249	*/
1250	static bool fRegisteredCmds = false;
1251	if (!fRegisteredCmds)
1252	{
1253	int rc = DBGCRegisterCommands(&g_aCmds[0], RT_ELEMENTS(g_aCmds));
1254	if (VBOX_SUCCESS(rc))
1255	fRegisteredCmds = true;
1256	}
1257	#endif
1258	return VINF_SUCCESS;
1259	}
1260
1261	/* Almost no cleanup necessary, MM frees all memory. */
1262	PDMR3CritSectDelete(&pVM->pgm.s.CritSect);
1263
1264	return rc;
1265	}
1266
1267
1268	/**
1269	* Init paging.
1270	*
1271	* Since we need to check what mode the host is operating in before we can choose
1272	* the right paging functions for the host we have to delay this until R0 has
1273	* been initialized.
1274	*
1275	* @returns VBox status code.
1276	* @param pVM VM handle.
1277	*/
1278	static int pgmR3InitPaging(PVM pVM)
1279	{
1280	/*
1281	* Force a recalculation of modes and switcher so everyone gets notified.
1282	*/
1283	pVM->pgm.s.enmShadowMode = PGMMODE_INVALID;
1284	pVM->pgm.s.enmGuestMode = PGMMODE_INVALID;
1285	pVM->pgm.s.enmHostMode = SUPPAGINGMODE_INVALID;
1286
1287	/*
1288	* Allocate static mapping space for whatever the cr3 register
1289	* points to and in the case of PAE mode to the 4 PDs.
1290	*/
1291	int rc = MMR3HyperReserve(pVM, PAGE_SIZE * 5, "CR3 mapping", &pVM->pgm.s.GCPtrCR3Mapping);
1292	if (VBOX_FAILURE(rc))
1293	{
1294	AssertMsgFailed(("Failed to reserve two pages for cr mapping in HMA, rc=%Vrc\n", rc));
1295	return rc;
1296	}
1297	MMR3HyperReserve(pVM, PAGE_SIZE, "fence", NULL);
1298
1299	/*
1300	* Allocate pages for the three possible intermediate contexts
1301	* (AMD64, PAE and plain 32-Bit). We maintain all three contexts
1302	* for the sake of simplicity. The AMD64 uses the PAE for the
1303	* lower levels, making the total number of pages 11 (3 + 7 + 1).
1304	*
1305	* We assume that two page tables will be enought for the core code
1306	* mappings (HC virtual and identity).
1307	*/
1308	pVM->pgm.s.pInterPD = (PX86PD)MMR3PageAllocLow(pVM);
1309	pVM->pgm.s.apInterPTs[0] = (PX86PT)MMR3PageAllocLow(pVM);
1310	pVM->pgm.s.apInterPTs[1] = (PX86PT)MMR3PageAllocLow(pVM);
1311	pVM->pgm.s.apInterPaePTs[0] = (PX86PTPAE)MMR3PageAlloc(pVM);
1312	pVM->pgm.s.apInterPaePTs[1] = (PX86PTPAE)MMR3PageAlloc(pVM);
1313	pVM->pgm.s.apInterPaePDs[0] = (PX86PDPAE)MMR3PageAlloc(pVM);
1314	pVM->pgm.s.apInterPaePDs[1] = (PX86PDPAE)MMR3PageAlloc(pVM);
1315	pVM->pgm.s.apInterPaePDs[2] = (PX86PDPAE)MMR3PageAlloc(pVM);
1316	pVM->pgm.s.apInterPaePDs[3] = (PX86PDPAE)MMR3PageAlloc(pVM);
1317	pVM->pgm.s.pInterPaePDPT = (PX86PDPT)MMR3PageAllocLow(pVM);
1318	pVM->pgm.s.pInterPaePDPT64 = (PX86PDPT)MMR3PageAllocLow(pVM);
1319	pVM->pgm.s.pInterPaePML4 = (PX86PML4)MMR3PageAllocLow(pVM);
1320	if ( !pVM->pgm.s.pInterPD
1321	\|\| !pVM->pgm.s.apInterPTs[0]
1322	\|\| !pVM->pgm.s.apInterPTs[1]
1323	\|\| !pVM->pgm.s.apInterPaePTs[0]
1324	\|\| !pVM->pgm.s.apInterPaePTs[1]
1325	\|\| !pVM->pgm.s.apInterPaePDs[0]
1326	\|\| !pVM->pgm.s.apInterPaePDs[1]
1327	\|\| !pVM->pgm.s.apInterPaePDs[2]
1328	\|\| !pVM->pgm.s.apInterPaePDs[3]
1329	\|\| !pVM->pgm.s.pInterPaePDPT
1330	\|\| !pVM->pgm.s.pInterPaePDPT64
1331	\|\| !pVM->pgm.s.pInterPaePML4)
1332	{
1333	AssertMsgFailed(("Failed to allocate pages for the intermediate context!\n"));
1334	return VERR_NO_PAGE_MEMORY;
1335	}
1336
1337	pVM->pgm.s.HCPhysInterPD = MMPage2Phys(pVM, pVM->pgm.s.pInterPD);
1338	AssertRelease(pVM->pgm.s.HCPhysInterPD != NIL_RTHCPHYS && !(pVM->pgm.s.HCPhysInterPD & PAGE_OFFSET_MASK));
1339	pVM->pgm.s.HCPhysInterPaePDPT = MMPage2Phys(pVM, pVM->pgm.s.pInterPaePDPT);
1340	AssertRelease(pVM->pgm.s.HCPhysInterPaePDPT != NIL_RTHCPHYS && !(pVM->pgm.s.HCPhysInterPaePDPT & PAGE_OFFSET_MASK));
1341	pVM->pgm.s.HCPhysInterPaePML4 = MMPage2Phys(pVM, pVM->pgm.s.pInterPaePML4);
1342	AssertRelease(pVM->pgm.s.HCPhysInterPaePML4 != NIL_RTHCPHYS && !(pVM->pgm.s.HCPhysInterPaePML4 & PAGE_OFFSET_MASK));
1343
1344	/*
1345	* Initialize the pages, setting up the PML4 and PDPT for repetitive 4GB action.
1346	*/
1347	ASMMemZeroPage(pVM->pgm.s.pInterPD);
1348	ASMMemZeroPage(pVM->pgm.s.apInterPTs[0]);
1349	ASMMemZeroPage(pVM->pgm.s.apInterPTs[1]);
1350
1351	ASMMemZeroPage(pVM->pgm.s.apInterPaePTs[0]);
1352	ASMMemZeroPage(pVM->pgm.s.apInterPaePTs[1]);
1353
1354	ASMMemZeroPage(pVM->pgm.s.pInterPaePDPT);
1355	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.apInterPaePDs); i++)
1356	{
1357	ASMMemZeroPage(pVM->pgm.s.apInterPaePDs[i]);
1358	pVM->pgm.s.pInterPaePDPT->a[i].u = X86_PDPE_P \| PGM_PLXFLAGS_PERMANENT
1359	\| MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[i]);
1360	}
1361
1362	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.pInterPaePDPT64->a); i++)
1363	{
1364	const unsigned iPD = i % RT_ELEMENTS(pVM->pgm.s.apInterPaePDs);
1365	pVM->pgm.s.pInterPaePDPT64->a[i].u = X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_A \| PGM_PLXFLAGS_PERMANENT
1366	\| MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[iPD]);
1367	}
1368
1369	RTHCPHYS HCPhysInterPaePDPT64 = MMPage2Phys(pVM, pVM->pgm.s.pInterPaePDPT64);
1370	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.pInterPaePML4->a); i++)
1371	pVM->pgm.s.pInterPaePML4->a[i].u = X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_A \| PGM_PLXFLAGS_PERMANENT
1372	\| HCPhysInterPaePDPT64;
1373
1374	/*
1375	* Allocate pages for the three possible guest contexts (AMD64, PAE and plain 32-Bit).
1376	* We allocate pages for all three posibilities to in order to simplify mappings and
1377	* avoid resource failure during mode switches. So, we need to cover all levels of the
1378	* of the first 4GB down to PD level.
1379	* As with the intermediate context, AMD64 uses the PAE PDPT and PDs.
1380	*/
1381	pVM->pgm.s.pHC32BitPD = (PX86PD)MMR3PageAllocLow(pVM);
1382	pVM->pgm.s.apHCPaePDs[0] = (PX86PDPAE)MMR3PageAlloc(pVM);
1383	pVM->pgm.s.apHCPaePDs[1] = (PX86PDPAE)MMR3PageAlloc(pVM);
1384	AssertRelease((uintptr_t)pVM->pgm.s.apHCPaePDs[0] + PAGE_SIZE == (uintptr_t)pVM->pgm.s.apHCPaePDs[1]);
1385	pVM->pgm.s.apHCPaePDs[2] = (PX86PDPAE)MMR3PageAlloc(pVM);
1386	AssertRelease((uintptr_t)pVM->pgm.s.apHCPaePDs[1] + PAGE_SIZE == (uintptr_t)pVM->pgm.s.apHCPaePDs[2]);
1387	pVM->pgm.s.apHCPaePDs[3] = (PX86PDPAE)MMR3PageAlloc(pVM);
1388	AssertRelease((uintptr_t)pVM->pgm.s.apHCPaePDs[2] + PAGE_SIZE == (uintptr_t)pVM->pgm.s.apHCPaePDs[3]);
1389	pVM->pgm.s.pHCPaePDPT = (PX86PDPT)MMR3PageAllocLow(pVM);
1390	pVM->pgm.s.pHCNestedRoot = MMR3PageAllocLow(pVM);
1391
1392	if ( !pVM->pgm.s.pHC32BitPD
1393	\|\| !pVM->pgm.s.apHCPaePDs[0]
1394	\|\| !pVM->pgm.s.apHCPaePDs[1]
1395	\|\| !pVM->pgm.s.apHCPaePDs[2]
1396	\|\| !pVM->pgm.s.apHCPaePDs[3]
1397	\|\| !pVM->pgm.s.pHCPaePDPT
1398	\|\| !pVM->pgm.s.pHCNestedRoot)
1399	{
1400	AssertMsgFailed(("Failed to allocate pages for the intermediate context!\n"));
1401	return VERR_NO_PAGE_MEMORY;
1402	}
1403
1404	/* get physical addresses. */
1405	pVM->pgm.s.HCPhys32BitPD = MMPage2Phys(pVM, pVM->pgm.s.pHC32BitPD);
1406	Assert(MMPagePhys2Page(pVM, pVM->pgm.s.HCPhys32BitPD) == pVM->pgm.s.pHC32BitPD);
1407	pVM->pgm.s.aHCPhysPaePDs[0] = MMPage2Phys(pVM, pVM->pgm.s.apHCPaePDs[0]);
1408	pVM->pgm.s.aHCPhysPaePDs[1] = MMPage2Phys(pVM, pVM->pgm.s.apHCPaePDs[1]);
1409	pVM->pgm.s.aHCPhysPaePDs[2] = MMPage2Phys(pVM, pVM->pgm.s.apHCPaePDs[2]);
1410	pVM->pgm.s.aHCPhysPaePDs[3] = MMPage2Phys(pVM, pVM->pgm.s.apHCPaePDs[3]);
1411	pVM->pgm.s.HCPhysPaePDPT = MMPage2Phys(pVM, pVM->pgm.s.pHCPaePDPT);
1412	pVM->pgm.s.HCPhysNestedRoot = MMPage2Phys(pVM, pVM->pgm.s.pHCNestedRoot);
1413
1414	/*
1415	* Initialize the pages, setting up the PML4 and PDPT for action below 4GB.
1416	*/
1417	ASMMemZero32(pVM->pgm.s.pHC32BitPD, PAGE_SIZE);
1418	ASMMemZero32(pVM->pgm.s.pHCPaePDPT, PAGE_SIZE);
1419	ASMMemZero32(pVM->pgm.s.pHCNestedRoot, PAGE_SIZE);
1420	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.apHCPaePDs); i++)
1421	{
1422	ASMMemZero32(pVM->pgm.s.apHCPaePDs[i], PAGE_SIZE);
1423	pVM->pgm.s.pHCPaePDPT->a[i].u = X86_PDPE_P \| PGM_PLXFLAGS_PERMANENT \| pVM->pgm.s.aHCPhysPaePDs[i];
1424	/* The flags will be corrected when entering and leaving long mode. */
1425	}
1426
1427	CPUMSetHyperCR3(pVM, (uint32_t)pVM->pgm.s.HCPhys32BitPD);
1428
1429	/*
1430	* Initialize paging workers and mode from current host mode
1431	* and the guest running in real mode.
1432	*/
1433	pVM->pgm.s.enmHostMode = SUPGetPagingMode();
1434	switch (pVM->pgm.s.enmHostMode)
1435	{
1436	case SUPPAGINGMODE_32_BIT:
1437	case SUPPAGINGMODE_32_BIT_GLOBAL:
1438	case SUPPAGINGMODE_PAE:
1439	case SUPPAGINGMODE_PAE_GLOBAL:
1440	case SUPPAGINGMODE_PAE_NX:
1441	case SUPPAGINGMODE_PAE_GLOBAL_NX:
1442	break;
1443
1444	case SUPPAGINGMODE_AMD64:
1445	case SUPPAGINGMODE_AMD64_GLOBAL:
1446	case SUPPAGINGMODE_AMD64_NX:
1447	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
1448	#ifndef VBOX_WITH_HYBIRD_32BIT_KERNEL
1449	if (ARCH_BITS != 64)
1450	{
1451	AssertMsgFailed(("Host mode %d (64-bit) is not supported by non-64bit builds\n", pVM->pgm.s.enmHostMode));
1452	LogRel(("Host mode %d (64-bit) is not supported by non-64bit builds\n", pVM->pgm.s.enmHostMode));
1453	return VERR_PGM_UNSUPPORTED_HOST_PAGING_MODE;
1454	}
1455	#endif
1456	break;
1457	default:
1458	AssertMsgFailed(("Host mode %d is not supported\n", pVM->pgm.s.enmHostMode));
1459	return VERR_PGM_UNSUPPORTED_HOST_PAGING_MODE;
1460	}
1461	rc = pgmR3ModeDataInit(pVM, false /* don't resolve GC and R0 syms yet */);
1462	if (VBOX_SUCCESS(rc))
1463	rc = PGMR3ChangeMode(pVM, PGMMODE_REAL);
1464	if (VBOX_SUCCESS(rc))
1465	{
1466	LogFlow(("pgmR3InitPaging: returns successfully\n"));
1467	#if HC_ARCH_BITS == 64
1468	LogRel(("Debug: HCPhys32BitPD=%VHp aHCPhysPaePDs={%VHp,%VHp,%VHp,%VHp} HCPhysPaePDPT=%VHp HCPhysPaePML4=%VHp\n",
1469	pVM->pgm.s.HCPhys32BitPD, pVM->pgm.s.aHCPhysPaePDs[0], pVM->pgm.s.aHCPhysPaePDs[1], pVM->pgm.s.aHCPhysPaePDs[2], pVM->pgm.s.aHCPhysPaePDs[3],
1470	pVM->pgm.s.HCPhysPaePDPT, pVM->pgm.s.HCPhysPaePML4));
1471	LogRel(("Debug: HCPhysInterPD=%VHp HCPhysInterPaePDPT=%VHp HCPhysInterPaePML4=%VHp\n",
1472	pVM->pgm.s.HCPhysInterPD, pVM->pgm.s.HCPhysInterPaePDPT, pVM->pgm.s.HCPhysInterPaePML4));
1473	LogRel(("Debug: apInterPTs={%VHp,%VHp} apInterPaePTs={%VHp,%VHp} apInterPaePDs={%VHp,%VHp,%VHp,%VHp} pInterPaePDPT64=%VHp\n",
1474	MMPage2Phys(pVM, pVM->pgm.s.apInterPTs[0]), MMPage2Phys(pVM, pVM->pgm.s.apInterPTs[1]),
1475	MMPage2Phys(pVM, pVM->pgm.s.apInterPaePTs[0]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePTs[1]),
1476	MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[0]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[1]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[2]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[3]),
1477	MMPage2Phys(pVM, pVM->pgm.s.pInterPaePDPT64)));
1478	#endif
1479
1480	return VINF_SUCCESS;
1481	}
1482
1483	LogFlow(("pgmR3InitPaging: returns %Vrc\n", rc));
1484	return rc;
1485	}
1486
1487
1488	#ifdef VBOX_WITH_STATISTICS
1489	/**
1490	* Init statistics
1491	*/
1492	static void pgmR3InitStats(PVM pVM)
1493	{
1494	PPGM pPGM = &pVM->pgm.s;
1495	STAM_REG(pVM, &pPGM->StatGCInvalidatePage, STAMTYPE_PROFILE, "/PGM/GC/InvalidatePage", STAMUNIT_TICKS_PER_CALL, "PGMGCInvalidatePage() profiling.");
1496	STAM_REG(pVM, &pPGM->StatGCInvalidatePage4KBPages, STAMTYPE_COUNTER, "/PGM/GC/InvalidatePage/4KBPages", STAMUNIT_OCCURENCES, "The number of times PGMGCInvalidatePage() was called for a 4KB page.");
1497	STAM_REG(pVM, &pPGM->StatGCInvalidatePage4MBPages, STAMTYPE_COUNTER, "/PGM/GC/InvalidatePage/4MBPages", STAMUNIT_OCCURENCES, "The number of times PGMGCInvalidatePage() was called for a 4MB page.");
1498	STAM_REG(pVM, &pPGM->StatGCInvalidatePage4MBPagesSkip, STAMTYPE_COUNTER, "/PGM/GC/InvalidatePage/4MBPagesSkip",STAMUNIT_OCCURENCES, "The number of times PGMGCInvalidatePage() skipped a 4MB page.");
1499	STAM_REG(pVM, &pPGM->StatGCInvalidatePagePDMappings, STAMTYPE_COUNTER, "/PGM/GC/InvalidatePage/PDMappings", STAMUNIT_OCCURENCES, "The number of times PGMGCInvalidatePage() was called for a page directory containing mappings (no conflict).");
1500	STAM_REG(pVM, &pPGM->StatGCInvalidatePagePDNAs, STAMTYPE_COUNTER, "/PGM/GC/InvalidatePage/PDNAs", STAMUNIT_OCCURENCES, "The number of times PGMGCInvalidatePage() was called for a not accessed page directory.");
1501	STAM_REG(pVM, &pPGM->StatGCInvalidatePagePDNPs, STAMTYPE_COUNTER, "/PGM/GC/InvalidatePage/PDNPs", STAMUNIT_OCCURENCES, "The number of times PGMGCInvalidatePage() was called for a not present page directory.");
1502	STAM_REG(pVM, &pPGM->StatGCInvalidatePagePDOutOfSync, STAMTYPE_COUNTER, "/PGM/GC/InvalidatePage/PDOutOfSync", STAMUNIT_OCCURENCES, "The number of times PGMGCInvalidatePage() was called for an out of sync page directory.");
1503	STAM_REG(pVM, &pPGM->StatGCInvalidatePageSkipped, STAMTYPE_COUNTER, "/PGM/GC/InvalidatePage/Skipped", STAMUNIT_OCCURENCES, "The number of times PGMGCInvalidatePage() was skipped due to not present shw or pending pending SyncCR3.");
1504	STAM_REG(pVM, &pPGM->StatGCSyncPT, STAMTYPE_PROFILE, "/PGM/GC/SyncPT", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMGCSyncPT() body.");
1505	STAM_REG(pVM, &pPGM->StatGCAccessedPage, STAMTYPE_COUNTER, "/PGM/GC/AccessedPage", STAMUNIT_OCCURENCES, "The number of pages marked not present for accessed bit emulation.");
1506	STAM_REG(pVM, &pPGM->StatGCDirtyPage, STAMTYPE_COUNTER, "/PGM/GC/DirtyPage/Mark", STAMUNIT_OCCURENCES, "The number of pages marked read-only for dirty bit tracking.");
1507	STAM_REG(pVM, &pPGM->StatGCDirtyPageBig, STAMTYPE_COUNTER, "/PGM/GC/DirtyPage/MarkBig", STAMUNIT_OCCURENCES, "The number of 4MB pages marked read-only for dirty bit tracking.");
1508	STAM_REG(pVM, &pPGM->StatGCDirtyPageTrap, STAMTYPE_COUNTER, "/PGM/GC/DirtyPage/Trap", STAMUNIT_OCCURENCES, "The number of traps generated for dirty bit tracking.");
1509	STAM_REG(pVM, &pPGM->StatGCDirtyPageSkipped, STAMTYPE_COUNTER, "/PGM/GC/DirtyPage/Skipped", STAMUNIT_OCCURENCES, "The number of pages already dirty or readonly.");
1510	STAM_REG(pVM, &pPGM->StatGCDirtiedPage, STAMTYPE_COUNTER, "/PGM/GC/DirtyPage/SetDirty", STAMUNIT_OCCURENCES, "The number of pages marked dirty because of write accesses.");
1511	STAM_REG(pVM, &pPGM->StatGCDirtyTrackRealPF, STAMTYPE_COUNTER, "/PGM/GC/DirtyPage/RealPF", STAMUNIT_OCCURENCES, "The number of real pages faults during dirty bit tracking.");
1512	STAM_REG(pVM, &pPGM->StatGCPageAlreadyDirty, STAMTYPE_COUNTER, "/PGM/GC/DirtyPage/AlreadySet", STAMUNIT_OCCURENCES, "The number of pages already marked dirty because of write accesses.");
1513	STAM_REG(pVM, &pPGM->StatGCDirtyBitTracking, STAMTYPE_PROFILE, "/PGM/GC/DirtyPage", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMTrackDirtyBit() body.");
1514	STAM_REG(pVM, &pPGM->StatGCSyncPTAlloc, STAMTYPE_COUNTER, "/PGM/GC/SyncPT/Alloc", STAMUNIT_OCCURENCES, "The number of times PGMGCSyncPT() needed to allocate page tables.");
1515	STAM_REG(pVM, &pPGM->StatGCSyncPTConflict, STAMTYPE_COUNTER, "/PGM/GC/SyncPT/Conflicts", STAMUNIT_OCCURENCES, "The number of times PGMGCSyncPT() detected conflicts.");
1516	STAM_REG(pVM, &pPGM->StatGCSyncPTFailed, STAMTYPE_COUNTER, "/PGM/GC/SyncPT/Failed", STAMUNIT_OCCURENCES, "The number of times PGMGCSyncPT() failed.");
1517
1518	STAM_REG(pVM, &pPGM->StatGCTrap0e, STAMTYPE_PROFILE, "/PGM/GC/Trap0e", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMGCTrap0eHandler() body.");
1519	STAM_REG(pVM, &pPGM->StatCheckPageFault, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time/CheckPageFault", STAMUNIT_TICKS_PER_CALL, "Profiling of checking for dirty/access emulation faults.");
1520	STAM_REG(pVM, &pPGM->StatLazySyncPT, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time/SyncPT", STAMUNIT_TICKS_PER_CALL, "Profiling of lazy page table syncing.");
1521	STAM_REG(pVM, &pPGM->StatMapping, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time/Mapping", STAMUNIT_TICKS_PER_CALL, "Profiling of checking virtual mappings.");
1522	STAM_REG(pVM, &pPGM->StatOutOfSync, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time/OutOfSync", STAMUNIT_TICKS_PER_CALL, "Profiling of out of sync page handling.");
1523	STAM_REG(pVM, &pPGM->StatHandlers, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time/Handlers", STAMUNIT_TICKS_PER_CALL, "Profiling of checking handlers.");
1524	STAM_REG(pVM, &pPGM->StatEIPHandlers, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time/EIPHandlers", STAMUNIT_TICKS_PER_CALL, "Profiling of checking eip handlers.");
1525	STAM_REG(pVM, &pPGM->StatTrap0eCSAM, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time2/CSAM", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is CSAM.");
1526	STAM_REG(pVM, &pPGM->StatTrap0eDirtyAndAccessedBits, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time2/DirtyAndAccessedBits", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is dirty and/or accessed bit emulation.");
1527	STAM_REG(pVM, &pPGM->StatTrap0eGuestTrap, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time2/GuestTrap", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is a guest trap.");
1528	STAM_REG(pVM, &pPGM->StatTrap0eHndPhys, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time2/HandlerPhysical", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is a physical handler.");
1529	STAM_REG(pVM, &pPGM->StatTrap0eHndVirt, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time2/HandlerVirtual",STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is a virtual handler.");
1530	STAM_REG(pVM, &pPGM->StatTrap0eHndUnhandled, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time2/HandlerUnhandled", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is access outside the monitored areas of a monitored page.");
1531	STAM_REG(pVM, &pPGM->StatTrap0eMisc, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time2/Misc", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is not known.");
1532	STAM_REG(pVM, &pPGM->StatTrap0eOutOfSync, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time2/OutOfSync", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is an out-of-sync page.");
1533	STAM_REG(pVM, &pPGM->StatTrap0eOutOfSyncHndPhys, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time2/OutOfSyncHndPhys", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is an out-of-sync physical handler page.");
1534	STAM_REG(pVM, &pPGM->StatTrap0eOutOfSyncHndVirt, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time2/OutOfSyncHndVirt", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is an out-of-sync virtual handler page.");
1535	STAM_REG(pVM, &pPGM->StatTrap0eOutOfSyncObsHnd, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time2/OutOfSyncObsHnd", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is an obsolete handler page.");
1536	STAM_REG(pVM, &pPGM->StatTrap0eSyncPT, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time2/SyncPT", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is lazy syncing of a PT.");
1537
1538	STAM_REG(pVM, &pPGM->StatTrap0eMapHandler, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/Handlers/Mapping", STAMUNIT_OCCURENCES, "Number of traps due to access handlers in mappings.");
1539	STAM_REG(pVM, &pPGM->StatHandlersOutOfSync, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/Handlers/OutOfSync", STAMUNIT_OCCURENCES, "Number of traps due to out-of-sync handled pages.");
1540	STAM_REG(pVM, &pPGM->StatHandlersPhysical, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/Handlers/Physical", STAMUNIT_OCCURENCES, "Number of traps due to physical access handlers.");
1541	STAM_REG(pVM, &pPGM->StatHandlersVirtual, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/Handlers/Virtual", STAMUNIT_OCCURENCES, "Number of traps due to virtual access handlers.");
1542	STAM_REG(pVM, &pPGM->StatHandlersVirtualByPhys, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/Handlers/VirtualByPhys", STAMUNIT_OCCURENCES, "Number of traps due to virtual access handlers by physical address.");
1543	STAM_REG(pVM, &pPGM->StatHandlersVirtualUnmarked, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/Handlers/VirtualUnmarked", STAMUNIT_OCCURENCES,"Number of traps due to virtual access handlers by virtual address (without proper physical flags).");
1544	STAM_REG(pVM, &pPGM->StatHandlersUnhandled, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/Handlers/Unhandled", STAMUNIT_OCCURENCES, "Number of traps due to access outside range of monitored page(s).");
1545	STAM_REG(pVM, &pPGM->StatHandlersInvalid, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/Handlers/Invalid", STAMUNIT_OCCURENCES, "Number of traps due to access to invalid physical memory.");
1546
1547	STAM_REG(pVM, &pPGM->StatGCTrap0eConflicts, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/Conflicts", STAMUNIT_OCCURENCES, "The number of times #PF was caused by an undetected conflict.");
1548	STAM_REG(pVM, &pPGM->StatGCTrap0eUSNotPresentRead, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/User/NPRead", STAMUNIT_OCCURENCES, "Number of user mode not present read page faults.");
1549	STAM_REG(pVM, &pPGM->StatGCTrap0eUSNotPresentWrite, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/User/NPWrite", STAMUNIT_OCCURENCES, "Number of user mode not present write page faults.");
1550	STAM_REG(pVM, &pPGM->StatGCTrap0eUSWrite, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/User/Write", STAMUNIT_OCCURENCES, "Number of user mode write page faults.");
1551	STAM_REG(pVM, &pPGM->StatGCTrap0eUSReserved, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/User/Reserved", STAMUNIT_OCCURENCES, "Number of user mode reserved bit page faults.");
1552	STAM_REG(pVM, &pPGM->StatGCTrap0eUSNXE, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/User/NXE", STAMUNIT_OCCURENCES, "Number of user mode NXE page faults.");
1553	STAM_REG(pVM, &pPGM->StatGCTrap0eUSRead, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/User/Read", STAMUNIT_OCCURENCES, "Number of user mode read page faults.");
1554
1555	STAM_REG(pVM, &pPGM->StatGCTrap0eSVNotPresentRead, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/Supervisor/NPRead", STAMUNIT_OCCURENCES, "Number of supervisor mode not present read page faults.");
1556	STAM_REG(pVM, &pPGM->StatGCTrap0eSVNotPresentWrite, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/Supervisor/NPWrite", STAMUNIT_OCCURENCES, "Number of supervisor mode not present write page faults.");
1557	STAM_REG(pVM, &pPGM->StatGCTrap0eSVWrite, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/Supervisor/Write", STAMUNIT_OCCURENCES, "Number of supervisor mode write page faults.");
1558	STAM_REG(pVM, &pPGM->StatGCTrap0eSVReserved, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/Supervisor/Reserved", STAMUNIT_OCCURENCES, "Number of supervisor mode reserved bit page faults.");
1559	STAM_REG(pVM, &pPGM->StatGCTrap0eSNXE, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/Supervisor/NXE", STAMUNIT_OCCURENCES, "Number of supervisor mode NXE page faults.");
1560	STAM_REG(pVM, &pPGM->StatGCTrap0eUnhandled, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/GuestPF/Unhandled", STAMUNIT_OCCURENCES, "Number of guest real page faults.");
1561	STAM_REG(pVM, &pPGM->StatGCTrap0eMap, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/GuestPF/Map", STAMUNIT_OCCURENCES, "Number of guest page faults due to map accesses.");
1562
1563	STAM_REG(pVM, &pPGM->StatTrap0eWPEmulGC, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/WP/InGC", STAMUNIT_OCCURENCES, "Number of guest page faults due to X86_CR0_WP emulation.");
1564	STAM_REG(pVM, &pPGM->StatTrap0eWPEmulR3, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/WP/ToR3", STAMUNIT_OCCURENCES, "Number of guest page faults due to X86_CR0_WP emulation (forward to R3 for emulation).");
1565
1566	STAM_REG(pVM, &pPGM->StatGCGuestCR3WriteHandled, STAMTYPE_COUNTER, "/PGM/GC/CR3WriteInt", STAMUNIT_OCCURENCES, "The number of times the Guest CR3 change was successfully handled.");
1567	STAM_REG(pVM, &pPGM->StatGCGuestCR3WriteUnhandled, STAMTYPE_COUNTER, "/PGM/GC/CR3WriteEmu", STAMUNIT_OCCURENCES, "The number of times the Guest CR3 change was passed back to the recompiler.");
1568	STAM_REG(pVM, &pPGM->StatGCGuestCR3WriteConflict, STAMTYPE_COUNTER, "/PGM/GC/CR3WriteConflict", STAMUNIT_OCCURENCES, "The number of times the Guest CR3 monitoring detected a conflict.");
1569
1570	STAM_REG(pVM, &pPGM->StatGCPageOutOfSyncSupervisor, STAMTYPE_COUNTER, "/PGM/GC/OutOfSync/SuperVisor", STAMUNIT_OCCURENCES, "Number of traps due to pages out of sync.");
1571	STAM_REG(pVM, &pPGM->StatGCPageOutOfSyncUser, STAMTYPE_COUNTER, "/PGM/GC/OutOfSync/User", STAMUNIT_OCCURENCES, "Number of traps due to pages out of sync.");
1572
1573	STAM_REG(pVM, &pPGM->StatGCGuestROMWriteHandled, STAMTYPE_COUNTER, "/PGM/GC/ROMWriteInt", STAMUNIT_OCCURENCES, "The number of times the Guest ROM change was successfully handled.");
1574	STAM_REG(pVM, &pPGM->StatGCGuestROMWriteUnhandled, STAMTYPE_COUNTER, "/PGM/GC/ROMWriteEmu", STAMUNIT_OCCURENCES, "The number of times the Guest ROM change was passed back to the recompiler.");
1575
1576	STAM_REG(pVM, &pPGM->StatDynMapCacheHits, STAMTYPE_COUNTER, "/PGM/GC/DynMapCache/Hits" , STAMUNIT_OCCURENCES, "Number of dynamic page mapping cache hits.");
1577	STAM_REG(pVM, &pPGM->StatDynMapCacheMisses, STAMTYPE_COUNTER, "/PGM/GC/DynMapCache/Misses" , STAMUNIT_OCCURENCES, "Number of dynamic page mapping cache misses.");
1578
1579	STAM_REG(pVM, &pPGM->StatHCDetectedConflicts, STAMTYPE_COUNTER, "/PGM/HC/DetectedConflicts", STAMUNIT_OCCURENCES, "The number of times PGMR3CheckMappingConflicts() detected a conflict.");
1580	STAM_REG(pVM, &pPGM->StatHCGuestPDWrite, STAMTYPE_COUNTER, "/PGM/HC/PDWrite", STAMUNIT_OCCURENCES, "The total number of times pgmHCGuestPDWriteHandler() was called.");
1581	STAM_REG(pVM, &pPGM->StatHCGuestPDWriteConflict, STAMTYPE_COUNTER, "/PGM/HC/PDWriteConflict", STAMUNIT_OCCURENCES, "The number of times pgmHCGuestPDWriteHandler() detected a conflict.");
1582
1583	STAM_REG(pVM, &pPGM->StatHCInvalidatePage, STAMTYPE_PROFILE, "/PGM/HC/InvalidatePage", STAMUNIT_TICKS_PER_CALL, "PGMHCInvalidatePage() profiling.");
1584	STAM_REG(pVM, &pPGM->StatHCInvalidatePage4KBPages, STAMTYPE_COUNTER, "/PGM/HC/InvalidatePage/4KBPages", STAMUNIT_OCCURENCES, "The number of times PGMHCInvalidatePage() was called for a 4KB page.");
1585	STAM_REG(pVM, &pPGM->StatHCInvalidatePage4MBPages, STAMTYPE_COUNTER, "/PGM/HC/InvalidatePage/4MBPages", STAMUNIT_OCCURENCES, "The number of times PGMHCInvalidatePage() was called for a 4MB page.");
1586	STAM_REG(pVM, &pPGM->StatHCInvalidatePage4MBPagesSkip, STAMTYPE_COUNTER, "/PGM/HC/InvalidatePage/4MBPagesSkip",STAMUNIT_OCCURENCES, "The number of times PGMHCInvalidatePage() skipped a 4MB page.");
1587	STAM_REG(pVM, &pPGM->StatHCInvalidatePagePDMappings, STAMTYPE_COUNTER, "/PGM/HC/InvalidatePage/PDMappings", STAMUNIT_OCCURENCES, "The number of times PGMHCInvalidatePage() was called for a page directory containing mappings (no conflict).");
1588	STAM_REG(pVM, &pPGM->StatHCInvalidatePagePDNAs, STAMTYPE_COUNTER, "/PGM/HC/InvalidatePage/PDNAs", STAMUNIT_OCCURENCES, "The number of times PGMHCInvalidatePage() was called for a not accessed page directory.");
1589	STAM_REG(pVM, &pPGM->StatHCInvalidatePagePDNPs, STAMTYPE_COUNTER, "/PGM/HC/InvalidatePage/PDNPs", STAMUNIT_OCCURENCES, "The number of times PGMHCInvalidatePage() was called for a not present page directory.");
1590	STAM_REG(pVM, &pPGM->StatHCInvalidatePagePDOutOfSync, STAMTYPE_COUNTER, "/PGM/HC/InvalidatePage/PDOutOfSync", STAMUNIT_OCCURENCES, "The number of times PGMGCInvalidatePage() was called for an out of sync page directory.");
1591	STAM_REG(pVM, &pPGM->StatHCInvalidatePageSkipped, STAMTYPE_COUNTER, "/PGM/HC/InvalidatePage/Skipped", STAMUNIT_OCCURENCES, "The number of times PGMHCInvalidatePage() was skipped due to not present shw or pending pending SyncCR3.");
1592	STAM_REG(pVM, &pPGM->StatHCResolveConflict, STAMTYPE_PROFILE, "/PGM/HC/ResolveConflict", STAMUNIT_TICKS_PER_CALL, "pgmR3SyncPTResolveConflict() profiling (includes the entire relocation).");
1593	STAM_REG(pVM, &pPGM->StatHCPrefetch, STAMTYPE_PROFILE, "/PGM/HC/Prefetch", STAMUNIT_TICKS_PER_CALL, "PGMR3PrefetchPage profiling.");
1594
1595	STAM_REG(pVM, &pPGM->StatHCSyncPT, STAMTYPE_PROFILE, "/PGM/HC/SyncPT", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMR3SyncPT() body.");
1596	STAM_REG(pVM, &pPGM->StatHCAccessedPage, STAMTYPE_COUNTER, "/PGM/HC/AccessedPage", STAMUNIT_OCCURENCES, "The number of pages marked not present for accessed bit emulation.");
1597	STAM_REG(pVM, &pPGM->StatHCDirtyPage, STAMTYPE_COUNTER, "/PGM/HC/DirtyPage/Mark", STAMUNIT_OCCURENCES, "The number of pages marked read-only for dirty bit tracking.");
1598	STAM_REG(pVM, &pPGM->StatHCDirtyPageBig, STAMTYPE_COUNTER, "/PGM/HC/DirtyPage/MarkBig", STAMUNIT_OCCURENCES, "The number of 4MB pages marked read-only for dirty bit tracking.");
1599	STAM_REG(pVM, &pPGM->StatHCDirtyPageTrap, STAMTYPE_COUNTER, "/PGM/HC/DirtyPage/Trap", STAMUNIT_OCCURENCES, "The number of traps generated for dirty bit tracking.");
1600	STAM_REG(pVM, &pPGM->StatHCDirtyPageSkipped, STAMTYPE_COUNTER, "/PGM/HC/DirtyPage/Skipped", STAMUNIT_OCCURENCES, "The number of pages already dirty or readonly.");
1601	STAM_REG(pVM, &pPGM->StatHCDirtyBitTracking, STAMTYPE_PROFILE, "/PGM/HC/DirtyPage", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMTrackDirtyBit() body.");
1602
1603	STAM_REG(pVM, &pPGM->StatGCSyncPagePDNAs, STAMTYPE_COUNTER, "/PGM/GC/SyncPagePDNAs", STAMUNIT_OCCURENCES, "The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit.");
1604	STAM_REG(pVM, &pPGM->StatGCSyncPagePDOutOfSync, STAMTYPE_COUNTER, "/PGM/GC/SyncPagePDOutOfSync", STAMUNIT_OCCURENCES, "The number of time we've encountered an out-of-sync PD in SyncPage.");
1605	STAM_REG(pVM, &pPGM->StatHCSyncPagePDNAs, STAMTYPE_COUNTER, "/PGM/HC/SyncPagePDNAs", STAMUNIT_OCCURENCES, "The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit.");
1606	STAM_REG(pVM, &pPGM->StatHCSyncPagePDOutOfSync, STAMTYPE_COUNTER, "/PGM/HC/SyncPagePDOutOfSync", STAMUNIT_OCCURENCES, "The number of time we've encountered an out-of-sync PD in SyncPage.");
1607
1608	STAM_REG(pVM, &pPGM->StatFlushTLB, STAMTYPE_PROFILE, "/PGM/FlushTLB", STAMUNIT_OCCURENCES, "Profiling of the PGMFlushTLB() body.");
1609	STAM_REG(pVM, &pPGM->StatFlushTLBNewCR3, STAMTYPE_COUNTER, "/PGM/FlushTLB/NewCR3", STAMUNIT_OCCURENCES, "The number of times PGMFlushTLB was called with a new CR3, non-global. (switch)");
1610	STAM_REG(pVM, &pPGM->StatFlushTLBNewCR3Global, STAMTYPE_COUNTER, "/PGM/FlushTLB/NewCR3Global", STAMUNIT_OCCURENCES, "The number of times PGMFlushTLB was called with a new CR3, global. (switch)");
1611	STAM_REG(pVM, &pPGM->StatFlushTLBSameCR3, STAMTYPE_COUNTER, "/PGM/FlushTLB/SameCR3", STAMUNIT_OCCURENCES, "The number of times PGMFlushTLB was called with the same CR3, non-global. (flush)");
1612	STAM_REG(pVM, &pPGM->StatFlushTLBSameCR3Global, STAMTYPE_COUNTER, "/PGM/FlushTLB/SameCR3Global", STAMUNIT_OCCURENCES, "The number of times PGMFlushTLB was called with the same CR3, global. (flush)");
1613
1614	STAM_REG(pVM, &pPGM->StatGCSyncCR3, STAMTYPE_PROFILE, "/PGM/GC/SyncCR3", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMSyncCR3() body.");
1615	STAM_REG(pVM, &pPGM->StatGCSyncCR3Handlers, STAMTYPE_PROFILE, "/PGM/GC/SyncCR3/Handlers", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMSyncCR3() update handler section.");
1616	STAM_REG(pVM, &pPGM->StatGCSyncCR3HandlerVirtualUpdate, STAMTYPE_PROFILE, "/PGM/GC/SyncCR3/Handlers/VirtualUpdate",STAMUNIT_TICKS_PER_CALL, "Profiling of the virtual handler updates.");
1617	STAM_REG(pVM, &pPGM->StatGCSyncCR3HandlerVirtualReset, STAMTYPE_PROFILE, "/PGM/GC/SyncCR3/Handlers/VirtualReset", STAMUNIT_TICKS_PER_CALL, "Profiling of the virtual handler resets.");
1618	STAM_REG(pVM, &pPGM->StatGCSyncCR3Global, STAMTYPE_COUNTER, "/PGM/GC/SyncCR3/Global", STAMUNIT_OCCURENCES, "The number of global CR3 syncs.");
1619	STAM_REG(pVM, &pPGM->StatGCSyncCR3NotGlobal, STAMTYPE_COUNTER, "/PGM/GC/SyncCR3/NotGlobal", STAMUNIT_OCCURENCES, "The number of non-global CR3 syncs.");
1620	STAM_REG(pVM, &pPGM->StatGCSyncCR3DstCacheHit, STAMTYPE_COUNTER, "/PGM/GC/SyncCR3/DstChacheHit", STAMUNIT_OCCURENCES, "The number of times we got some kind of a cache hit.");
1621	STAM_REG(pVM, &pPGM->StatGCSyncCR3DstFreed, STAMTYPE_COUNTER, "/PGM/GC/SyncCR3/DstFreed", STAMUNIT_OCCURENCES, "The number of times we've had to free a shadow entry.");
1622	STAM_REG(pVM, &pPGM->StatGCSyncCR3DstFreedSrcNP, STAMTYPE_COUNTER, "/PGM/GC/SyncCR3/DstFreedSrcNP", STAMUNIT_OCCURENCES, "The number of times we've had to free a shadow entry for which the source entry was not present.");
1623	STAM_REG(pVM, &pPGM->StatGCSyncCR3DstNotPresent, STAMTYPE_COUNTER, "/PGM/GC/SyncCR3/DstNotPresent", STAMUNIT_OCCURENCES, "The number of times we've encountered a not present shadow entry for a present guest entry.");
1624	STAM_REG(pVM, &pPGM->StatGCSyncCR3DstSkippedGlobalPD, STAMTYPE_COUNTER, "/PGM/GC/SyncCR3/DstSkippedGlobalPD", STAMUNIT_OCCURENCES, "The number of times a global page directory wasn't flushed.");
1625	STAM_REG(pVM, &pPGM->StatGCSyncCR3DstSkippedGlobalPT, STAMTYPE_COUNTER, "/PGM/GC/SyncCR3/DstSkippedGlobalPT", STAMUNIT_OCCURENCES, "The number of times a page table with only global entries wasn't flushed.");
1626
1627	STAM_REG(pVM, &pPGM->StatHCSyncCR3, STAMTYPE_PROFILE, "/PGM/HC/SyncCR3", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMSyncCR3() body.");
1628	STAM_REG(pVM, &pPGM->StatHCSyncCR3Handlers, STAMTYPE_PROFILE, "/PGM/HC/SyncCR3/Handlers", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMSyncCR3() update handler section.");
1629	STAM_REG(pVM, &pPGM->StatHCSyncCR3HandlerVirtualUpdate, STAMTYPE_PROFILE, "/PGM/HC/SyncCR3/Handlers/VirtualUpdate",STAMUNIT_TICKS_PER_CALL, "Profiling of the virtual handler updates.");
1630	STAM_REG(pVM, &pPGM->StatHCSyncCR3HandlerVirtualReset, STAMTYPE_PROFILE, "/PGM/HC/SyncCR3/Handlers/VirtualReset", STAMUNIT_TICKS_PER_CALL, "Profiling of the virtual handler resets.");
1631	STAM_REG(pVM, &pPGM->StatHCSyncCR3Global, STAMTYPE_COUNTER, "/PGM/HC/SyncCR3/Global", STAMUNIT_OCCURENCES, "The number of global CR3 syncs.");
1632	STAM_REG(pVM, &pPGM->StatHCSyncCR3NotGlobal, STAMTYPE_COUNTER, "/PGM/HC/SyncCR3/NotGlobal", STAMUNIT_OCCURENCES, "The number of non-global CR3 syncs.");
1633	STAM_REG(pVM, &pPGM->StatHCSyncCR3DstCacheHit, STAMTYPE_COUNTER, "/PGM/HC/SyncCR3/DstChacheHit", STAMUNIT_OCCURENCES, "The number of times we got some kind of a cache hit.");
1634	STAM_REG(pVM, &pPGM->StatHCSyncCR3DstFreed, STAMTYPE_COUNTER, "/PGM/HC/SyncCR3/DstFreed", STAMUNIT_OCCURENCES, "The number of times we've had to free a shadow entry.");
1635	STAM_REG(pVM, &pPGM->StatHCSyncCR3DstFreedSrcNP, STAMTYPE_COUNTER, "/PGM/HC/SyncCR3/DstFreedSrcNP", STAMUNIT_OCCURENCES, "The number of times we've had to free a shadow entry for which the source entry was not present.");
1636	STAM_REG(pVM, &pPGM->StatHCSyncCR3DstNotPresent, STAMTYPE_COUNTER, "/PGM/HC/SyncCR3/DstNotPresent", STAMUNIT_OCCURENCES, "The number of times we've encountered a not present shadow entry for a present guest entry.");
1637	STAM_REG(pVM, &pPGM->StatHCSyncCR3DstSkippedGlobalPD, STAMTYPE_COUNTER, "/PGM/HC/SyncCR3/DstSkippedGlobalPD", STAMUNIT_OCCURENCES, "The number of times a global page directory wasn't flushed.");
1638	STAM_REG(pVM, &pPGM->StatHCSyncCR3DstSkippedGlobalPT, STAMTYPE_COUNTER, "/PGM/HC/SyncCR3/DstSkippedGlobalPT", STAMUNIT_OCCURENCES, "The number of times a page table with only global entries wasn't flushed.");
1639
1640	STAM_REG(pVM, &pPGM->StatVirtHandleSearchByPhysGC, STAMTYPE_PROFILE, "/PGM/VirtHandler/SearchByPhys/GC", STAMUNIT_TICKS_PER_CALL, "Profiling of pgmHandlerVirtualFindByPhysAddr in GC.");
1641	STAM_REG(pVM, &pPGM->StatVirtHandleSearchByPhysHC, STAMTYPE_PROFILE, "/PGM/VirtHandler/SearchByPhys/HC", STAMUNIT_TICKS_PER_CALL, "Profiling of pgmHandlerVirtualFindByPhysAddr in HC.");
1642	STAM_REG(pVM, &pPGM->StatHandlePhysicalReset, STAMTYPE_COUNTER, "/PGM/HC/HandlerPhysicalReset", STAMUNIT_OCCURENCES, "The number of times PGMR3HandlerPhysicalReset is called.");
1643
1644	STAM_REG(pVM, &pPGM->StatHCGstModifyPage, STAMTYPE_PROFILE, "/PGM/HC/GstModifyPage", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMGstModifyPage() body.");
1645	STAM_REG(pVM, &pPGM->StatGCGstModifyPage, STAMTYPE_PROFILE, "/PGM/GC/GstModifyPage", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMGstModifyPage() body.");
1646
1647	STAM_REG(pVM, &pPGM->StatSynPT4kGC, STAMTYPE_COUNTER, "/PGM/GC/SyncPT/4k", STAMUNIT_OCCURENCES, "Nr of 4k PT syncs");
1648	STAM_REG(pVM, &pPGM->StatSynPT4kHC, STAMTYPE_COUNTER, "/PGM/HC/SyncPT/4k", STAMUNIT_OCCURENCES, "Nr of 4k PT syncs");
1649	STAM_REG(pVM, &pPGM->StatSynPT4MGC, STAMTYPE_COUNTER, "/PGM/GC/SyncPT/4M", STAMUNIT_OCCURENCES, "Nr of 4M PT syncs");
1650	STAM_REG(pVM, &pPGM->StatSynPT4MHC, STAMTYPE_COUNTER, "/PGM/HC/SyncPT/4M", STAMUNIT_OCCURENCES, "Nr of 4M PT syncs");
1651
1652	STAM_REG(pVM, &pPGM->StatDynRamTotal, STAMTYPE_COUNTER, "/PGM/RAM/TotalAlloc", STAMUNIT_MEGABYTES, "Allocated mbs of guest ram.");
1653	STAM_REG(pVM, &pPGM->StatDynRamGrow, STAMTYPE_COUNTER, "/PGM/RAM/Grow", STAMUNIT_OCCURENCES, "Nr of pgmr3PhysGrowRange calls.");
1654
1655	STAM_REG(pVM, &pPGM->StatPageHCMapTlbHits, STAMTYPE_COUNTER, "/PGM/PageHCMap/TlbHits", STAMUNIT_OCCURENCES, "TLB hits.");
1656	STAM_REG(pVM, &pPGM->StatPageHCMapTlbMisses, STAMTYPE_COUNTER, "/PGM/PageHCMap/TlbMisses", STAMUNIT_OCCURENCES, "TLB misses.");
1657	STAM_REG(pVM, &pPGM->ChunkR3Map.c, STAMTYPE_U32, "/PGM/ChunkR3Map/c", STAMUNIT_OCCURENCES, "Number of mapped chunks.");
1658	STAM_REG(pVM, &pPGM->ChunkR3Map.cMax, STAMTYPE_U32, "/PGM/ChunkR3Map/cMax", STAMUNIT_OCCURENCES, "Maximum number of mapped chunks.");
1659	STAM_REG(pVM, &pPGM->StatChunkR3MapTlbHits, STAMTYPE_COUNTER, "/PGM/ChunkR3Map/TlbHits", STAMUNIT_OCCURENCES, "TLB hits.");
1660	STAM_REG(pVM, &pPGM->StatChunkR3MapTlbMisses, STAMTYPE_COUNTER, "/PGM/ChunkR3Map/TlbMisses", STAMUNIT_OCCURENCES, "TLB misses.");
1661	STAM_REG(pVM, &pPGM->StatPageReplaceShared, STAMTYPE_COUNTER, "/PGM/Page/ReplacedShared", STAMUNIT_OCCURENCES, "Times a shared page was replaced.");
1662	STAM_REG(pVM, &pPGM->StatPageReplaceZero, STAMTYPE_COUNTER, "/PGM/Page/ReplacedZero", STAMUNIT_OCCURENCES, "Times the zero page was replaced.");
1663	STAM_REG(pVM, &pPGM->StatPageHandyAllocs, STAMTYPE_COUNTER, "/PGM/Page/HandyAllocs", STAMUNIT_OCCURENCES, "Number of times we've allocated more handy pages.");
1664	STAM_REG(pVM, &pPGM->cAllPages, STAMTYPE_U32, "/PGM/Page/cAllPages", STAMUNIT_OCCURENCES, "The total number of pages.");
1665	STAM_REG(pVM, &pPGM->cPrivatePages, STAMTYPE_U32, "/PGM/Page/cPrivatePages", STAMUNIT_OCCURENCES, "The number of private pages.");
1666	STAM_REG(pVM, &pPGM->cSharedPages, STAMTYPE_U32, "/PGM/Page/cSharedPages", STAMUNIT_OCCURENCES, "The number of shared pages.");
1667	STAM_REG(pVM, &pPGM->cZeroPages, STAMTYPE_U32, "/PGM/Page/cZeroPages", STAMUNIT_OCCURENCES, "The number of zero backed pages.");
1668
1669	#ifdef PGMPOOL_WITH_GCPHYS_TRACKING
1670	STAM_REG(pVM, &pPGM->StatTrackVirgin, STAMTYPE_COUNTER, "/PGM/Track/Virgin", STAMUNIT_OCCURENCES, "The number of first time shadowings");
1671	STAM_REG(pVM, &pPGM->StatTrackAliased, STAMTYPE_COUNTER, "/PGM/Track/Aliased", STAMUNIT_OCCURENCES, "The number of times switching to cRef2, i.e. the page is being shadowed by two PTs.");
1672	STAM_REG(pVM, &pPGM->StatTrackAliasedMany, STAMTYPE_COUNTER, "/PGM/Track/AliasedMany", STAMUNIT_OCCURENCES, "The number of times we're tracking using cRef2.");
1673	STAM_REG(pVM, &pPGM->StatTrackAliasedLots, STAMTYPE_COUNTER, "/PGM/Track/AliasedLots", STAMUNIT_OCCURENCES, "The number of times we're hitting pages which has overflowed cRef2");
1674	STAM_REG(pVM, &pPGM->StatTrackOverflows, STAMTYPE_COUNTER, "/PGM/Track/Overflows", STAMUNIT_OCCURENCES, "The number of times the extent list grows to long.");
1675	STAM_REG(pVM, &pPGM->StatTrackDeref, STAMTYPE_PROFILE, "/PGM/Track/Deref", STAMUNIT_OCCURENCES, "Profiling of SyncPageWorkerTrackDeref (expensive).");
1676	#endif
1677
1678	for (unsigned i = 0; i < X86_PG_ENTRIES; i++)
1679	{
1680	/** @todo r=bird: We need a STAMR3RegisterF()! */
1681	char szName[32];
1682
1683	RTStrPrintf(szName, sizeof(szName), "/PGM/GC/PD/Trap0e/%04X", i);
1684	int rc = STAMR3Register(pVM, &pPGM->StatGCTrap0ePD[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, szName, STAMUNIT_OCCURENCES, "The number of traps in page directory n.");
1685	AssertRC(rc);
1686
1687	RTStrPrintf(szName, sizeof(szName), "/PGM/GC/PD/SyncPt/%04X", i);
1688	rc = STAMR3Register(pVM, &pPGM->StatGCSyncPtPD[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, szName, STAMUNIT_OCCURENCES, "The number of syncs per PD n.");
1689	AssertRC(rc);
1690
1691	RTStrPrintf(szName, sizeof(szName), "/PGM/GC/PD/SyncPage/%04X", i);
1692	rc = STAMR3Register(pVM, &pPGM->StatGCSyncPagePD[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, szName, STAMUNIT_OCCURENCES, "The number of out of sync pages per page directory n.");
1693	AssertRC(rc);
1694	}
1695	}
1696	#endif /* VBOX_WITH_STATISTICS */
1697
1698	/**
1699	* Init the PGM bits that rely on VMMR0 and MM to be fully initialized.
1700	*
1701	* The dynamic mapping area will also be allocated and initialized at this
1702	* time. We could allocate it during PGMR3Init of course, but the mapping
1703	* wouldn't be allocated at that time preventing us from setting up the
1704	* page table entries with the dummy page.
1705	*
1706	* @returns VBox status code.
1707	* @param pVM VM handle.
1708	*/
1709	VMMR3DECL(int) PGMR3InitDynMap(PVM pVM)
1710	{
1711	RTGCPTR GCPtr;
1712	/*
1713	* Reserve space for mapping the paging pages into guest context.
1714	*/
1715	int rc = MMR3HyperReserve(pVM, PAGE_SIZE * (2 + RT_ELEMENTS(pVM->pgm.s.apHCPaePDs) + 1 + 2 + 2), "Paging", &GCPtr);
1716	AssertRCReturn(rc, rc);
1717	pVM->pgm.s.pGC32BitPD = GCPtr;
1718	MMR3HyperReserve(pVM, PAGE_SIZE, "fence", NULL);
1719
1720	/*
1721	* Reserve space for the dynamic mappings.
1722	*/
1723	/** @todo r=bird: Need to verify that the checks for crossing PTs are correct here. They seems to be assuming 4MB PTs.. */
1724	rc = MMR3HyperReserve(pVM, MM_HYPER_DYNAMIC_SIZE, "Dynamic mapping", &GCPtr);
1725	if (VBOX_SUCCESS(rc))
1726	pVM->pgm.s.pbDynPageMapBaseGC = GCPtr;
1727
1728	if ( VBOX_SUCCESS(rc)
1729	&& (pVM->pgm.s.pbDynPageMapBaseGC >> X86_PD_SHIFT) != ((pVM->pgm.s.pbDynPageMapBaseGC + MM_HYPER_DYNAMIC_SIZE - 1) >> X86_PD_SHIFT))
1730	{
1731	rc = MMR3HyperReserve(pVM, MM_HYPER_DYNAMIC_SIZE, "Dynamic mapping not crossing", &GCPtr);
1732	if (VBOX_SUCCESS(rc))
1733	pVM->pgm.s.pbDynPageMapBaseGC = GCPtr;
1734	}
1735	if (VBOX_SUCCESS(rc))
1736	{
1737	AssertRelease((pVM->pgm.s.pbDynPageMapBaseGC >> X86_PD_SHIFT) == ((pVM->pgm.s.pbDynPageMapBaseGC + MM_HYPER_DYNAMIC_SIZE - 1) >> X86_PD_SHIFT));
1738	MMR3HyperReserve(pVM, PAGE_SIZE, "fence", NULL);
1739	}
1740	return rc;
1741	}
1742
1743
1744	/**
1745	* Ring-3 init finalizing.
1746	*
1747	* @returns VBox status code.
1748	* @param pVM The VM handle.
1749	*/
1750	VMMR3DECL(int) PGMR3InitFinalize(PVM pVM)
1751	{
1752	/*
1753	* Map the paging pages into the guest context.
1754	*/
1755	RTGCPTR GCPtr = pVM->pgm.s.pGC32BitPD;
1756	AssertReleaseReturn(GCPtr, VERR_INTERNAL_ERROR);
1757
1758	int rc = PGMMap(pVM, GCPtr, pVM->pgm.s.HCPhys32BitPD, PAGE_SIZE, 0);
1759	AssertRCReturn(rc, rc);
1760	pVM->pgm.s.pGC32BitPD = GCPtr;
1761	GCPtr += PAGE_SIZE;
1762	GCPtr += PAGE_SIZE; /* reserved page */
1763
1764	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.apHCPaePDs); i++)
1765	{
1766	rc = PGMMap(pVM, GCPtr, pVM->pgm.s.aHCPhysPaePDs[i], PAGE_SIZE, 0);
1767	AssertRCReturn(rc, rc);
1768	pVM->pgm.s.apGCPaePDs[i] = GCPtr;
1769	GCPtr += PAGE_SIZE;
1770	}
1771	/* A bit of paranoia is justified. */
1772	AssertRelease((RTGCUINTPTR)pVM->pgm.s.apGCPaePDs[0] + PAGE_SIZE == (RTGCUINTPTR)pVM->pgm.s.apGCPaePDs[1]);
1773	AssertRelease((RTGCUINTPTR)pVM->pgm.s.apGCPaePDs[1] + PAGE_SIZE == (RTGCUINTPTR)pVM->pgm.s.apGCPaePDs[2]);
1774	AssertRelease((RTGCUINTPTR)pVM->pgm.s.apGCPaePDs[2] + PAGE_SIZE == (RTGCUINTPTR)pVM->pgm.s.apGCPaePDs[3]);
1775	GCPtr += PAGE_SIZE; /* reserved page */
1776
1777	rc = PGMMap(pVM, GCPtr, pVM->pgm.s.HCPhysPaePDPT, PAGE_SIZE, 0);
1778	AssertRCReturn(rc, rc);
1779	pVM->pgm.s.pGCPaePDPT = GCPtr;
1780	GCPtr += PAGE_SIZE;
1781	GCPtr += PAGE_SIZE; /* reserved page */
1782
1783
1784	/*
1785	* Reserve space for the dynamic mappings.
1786	* Initialize the dynamic mapping pages with dummy pages to simply the cache.
1787	*/
1788	/* get the pointer to the page table entries. */
1789	PPGMMAPPING pMapping = pgmGetMapping(pVM, pVM->pgm.s.pbDynPageMapBaseGC);
1790	AssertRelease(pMapping);
1791	const uintptr_t off = pVM->pgm.s.pbDynPageMapBaseGC - pMapping->GCPtr;
1792	const unsigned iPT = off >> X86_PD_SHIFT;
1793	const unsigned iPG = (off >> X86_PT_SHIFT) & X86_PT_MASK;
1794	pVM->pgm.s.paDynPageMap32BitPTEsGC = pMapping->aPTs[iPT].pPTRC + iPG * sizeof(pMapping->aPTs[0].pPTR3->a[0]);
1795	pVM->pgm.s.paDynPageMapPaePTEsGC = pMapping->aPTs[iPT].paPaePTsRC + iPG * sizeof(pMapping->aPTs[0].paPaePTsR3->a[0]);
1796
1797	/* init cache */
1798	RTHCPHYS HCPhysDummy = MMR3PageDummyHCPhys(pVM);
1799	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.aHCPhysDynPageMapCache); i++)
1800	pVM->pgm.s.aHCPhysDynPageMapCache[i] = HCPhysDummy;
1801
1802	for (unsigned i = 0; i < MM_HYPER_DYNAMIC_SIZE; i += PAGE_SIZE)
1803	{
1804	rc = PGMMap(pVM, pVM->pgm.s.pbDynPageMapBaseGC + i, HCPhysDummy, PAGE_SIZE, 0);
1805	AssertRCReturn(rc, rc);
1806	}
1807
1808	/* Note that AMD uses all the 8 reserved bits for the address (so 40 bits in total); Intel only goes up to 36 bits, so
1809	* we stick to 36 as well.
1810	*
1811	* @todo How to test for the 40 bits support? Long mode seems to be the test criterium.
1812	*/
1813	uint32_t u32Dummy, u32Features;
1814	CPUMGetGuestCpuId(pVM, 1, &u32Dummy, &u32Dummy, &u32Dummy, &u32Features);
1815
1816	if (u32Features & X86_CPUID_FEATURE_EDX_PSE36)
1817	pVM->pgm.s.GCPhys4MBPSEMask = RT_BIT_64(36) - 1;
1818	else
1819	pVM->pgm.s.GCPhys4MBPSEMask = RT_BIT_64(32) - 1;
1820
1821	LogRel(("PGMR3InitFinalize: 4 MB PSE mask %VGp\n", pVM->pgm.s.GCPhys4MBPSEMask));
1822
1823	return rc;
1824	}
1825
1826
1827	/**
1828	* Applies relocations to data and code managed by this
1829	* component. This function will be called at init and
1830	* whenever the VMM need to relocate it self inside the GC.
1831	*
1832	* @param pVM The VM.
1833	* @param offDelta Relocation delta relative to old location.
1834	*/
1835	VMMR3DECL(void) PGMR3Relocate(PVM pVM, RTGCINTPTR offDelta)
1836	{
1837	LogFlow(("PGMR3Relocate\n"));
1838
1839	/*
1840	* Paging stuff.
1841	*/
1842	pVM->pgm.s.GCPtrCR3Mapping += offDelta;
1843	/** @todo move this into shadow and guest specific relocation functions. */
1844	AssertMsg(pVM->pgm.s.pGC32BitPD, ("Init order, no relocation before paging is initialized!\n"));
1845	pVM->pgm.s.pGC32BitPD += offDelta;
1846	pVM->pgm.s.pGuestPDGC += offDelta;
1847	AssertCompile(RT_ELEMENTS(pVM->pgm.s.apGCPaePDs) == RT_ELEMENTS(pVM->pgm.s.apGstPaePDsGC));
1848	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.apGCPaePDs); i++)
1849	{
1850	pVM->pgm.s.apGCPaePDs[i] += offDelta;
1851	pVM->pgm.s.apGstPaePDsGC[i] += offDelta;
1852	}
1853	pVM->pgm.s.pGstPaePDPTGC += offDelta;
1854	pVM->pgm.s.pGCPaePDPT += offDelta;
1855
1856	pgmR3ModeDataInit(pVM, true /* resolve GC/R0 symbols */);
1857	pgmR3ModeDataSwitch(pVM, pVM->pgm.s.enmShadowMode, pVM->pgm.s.enmGuestMode);
1858
1859	PGM_SHW_PFN(Relocate, pVM)(pVM, offDelta);
1860	PGM_GST_PFN(Relocate, pVM)(pVM, offDelta);
1861	PGM_BTH_PFN(Relocate, pVM)(pVM, offDelta);
1862
1863	/*
1864	* Trees.
1865	*/
1866	pVM->pgm.s.pTreesGC = MMHyperHC2GC(pVM, pVM->pgm.s.pTreesHC);
1867
1868	/*
1869	* Ram ranges.
1870	*/
1871	if (pVM->pgm.s.pRamRangesR3)
1872	{
1873	pVM->pgm.s.pRamRangesRC = MMHyperR3ToRC(pVM, pVM->pgm.s.pRamRangesR3);
1874	for (PPGMRAMRANGE pCur = pVM->pgm.s.pRamRangesR3; pCur->pNextR3; pCur = pCur->pNextR3)
1875	pCur->pNextRC = MMHyperR3ToRC(pVM, pCur->pNextR3);
1876	}
1877
1878	/*
1879	* Update the two page directories with all page table mappings.
1880	* (One or more of them have changed, that's why we're here.)
1881	*/
1882	pVM->pgm.s.pMappingsRC = MMHyperHC2GC(pVM, pVM->pgm.s.pMappingsR3);
1883	for (PPGMMAPPING pCur = pVM->pgm.s.pMappingsR3; pCur->pNextR3; pCur = pCur->pNextR3)
1884	pCur->pNextRC = MMHyperR3ToRC(pVM, pCur->pNextR3);
1885
1886	/* Relocate GC addresses of Page Tables. */
1887	for (PPGMMAPPING pCur = pVM->pgm.s.pMappingsR3; pCur; pCur = pCur->pNextR3)
1888	{
1889	for (RTHCUINT i = 0; i < pCur->cPTs; i++)
1890	{
1891	pCur->aPTs[i].pPTRC = MMHyperR3ToRC(pVM, pCur->aPTs[i].pPTR3);
1892	pCur->aPTs[i].paPaePTsRC = MMHyperR3ToRC(pVM, pCur->aPTs[i].paPaePTsR3);
1893	}
1894	}
1895
1896	/*
1897	* Dynamic page mapping area.
1898	*/
1899	pVM->pgm.s.paDynPageMap32BitPTEsGC += offDelta;
1900	pVM->pgm.s.paDynPageMapPaePTEsGC += offDelta;
1901	pVM->pgm.s.pbDynPageMapBaseGC += offDelta;
1902
1903	/*
1904	* The Zero page.
1905	*/
1906	pVM->pgm.s.pvZeroPgR0 = MMHyperR3ToR0(pVM, pVM->pgm.s.pvZeroPgR3);
1907	AssertRelease(pVM->pgm.s.pvZeroPgR0);
1908
1909	/*
1910	* Physical and virtual handlers.
1911	*/
1912	RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesHC->PhysHandlers, true, pgmR3RelocatePhysHandler, &offDelta);
1913	RTAvlroGCPtrDoWithAll(&pVM->pgm.s.pTreesHC->VirtHandlers, true, pgmR3RelocateVirtHandler, &offDelta);
1914	RTAvlroGCPtrDoWithAll(&pVM->pgm.s.pTreesHC->HyperVirtHandlers, true, pgmR3RelocateHyperVirtHandler, &offDelta);
1915
1916	/*
1917	* The page pool.
1918	*/
1919	pgmR3PoolRelocate(pVM);
1920	}
1921
1922
1923	/**
1924	* Callback function for relocating a physical access handler.
1925	*
1926	* @returns 0 (continue enum)
1927	* @param pNode Pointer to a PGMPHYSHANDLER node.
1928	* @param pvUser Pointer to the offDelta. This is a pointer to the delta since we're
1929	* not certain the delta will fit in a void pointer for all possible configs.
1930	*/
1931	static DECLCALLBACK(int) pgmR3RelocatePhysHandler(PAVLROGCPHYSNODECORE pNode, void *pvUser)
1932	{
1933	PPGMPHYSHANDLER pHandler = (PPGMPHYSHANDLER)pNode;
1934	RTGCINTPTR offDelta = *(PRTGCINTPTR)pvUser;
1935	if (pHandler->pfnHandlerRC)
1936	pHandler->pfnHandlerRC += offDelta;
1937	if (pHandler->pvUserRC >= 0x10000)
1938	pHandler->pvUserRC += offDelta;
1939	return 0;
1940	}
1941
1942
1943	/**
1944	* Callback function for relocating a virtual access handler.
1945	*
1946	* @returns 0 (continue enum)
1947	* @param pNode Pointer to a PGMVIRTHANDLER node.
1948	* @param pvUser Pointer to the offDelta. This is a pointer to the delta since we're
1949	* not certain the delta will fit in a void pointer for all possible configs.
1950	*/
1951	static DECLCALLBACK(int) pgmR3RelocateVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser)
1952	{
1953	PPGMVIRTHANDLER pHandler = (PPGMVIRTHANDLER)pNode;
1954	RTGCINTPTR offDelta = *(PRTGCINTPTR)pvUser;
1955	Assert( pHandler->enmType == PGMVIRTHANDLERTYPE_ALL
1956	\|\| pHandler->enmType == PGMVIRTHANDLERTYPE_WRITE);
1957	Assert(pHandler->pfnHandlerRC);
1958	pHandler->pfnHandlerRC += offDelta;
1959	return 0;
1960	}
1961
1962
1963	/**
1964	* Callback function for relocating a virtual access handler for the hypervisor mapping.
1965	*
1966	* @returns 0 (continue enum)
1967	* @param pNode Pointer to a PGMVIRTHANDLER node.
1968	* @param pvUser Pointer to the offDelta. This is a pointer to the delta since we're
1969	* not certain the delta will fit in a void pointer for all possible configs.
1970	*/
1971	static DECLCALLBACK(int) pgmR3RelocateHyperVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser)
1972	{
1973	PPGMVIRTHANDLER pHandler = (PPGMVIRTHANDLER)pNode;
1974	RTGCINTPTR offDelta = *(PRTGCINTPTR)pvUser;
1975	Assert(pHandler->enmType == PGMVIRTHANDLERTYPE_HYPERVISOR);
1976	Assert(pHandler->pfnHandlerRC);
1977	pHandler->pfnHandlerRC += offDelta;
1978	return 0;
1979	}
1980
1981
1982	/**
1983	* The VM is being reset.
1984	*
1985	* For the PGM component this means that any PD write monitors
1986	* needs to be removed.
1987	*
1988	* @param pVM VM handle.
1989	*/
1990	VMMR3DECL(void) PGMR3Reset(PVM pVM)
1991	{
1992	LogFlow(("PGMR3Reset:\n"));
1993	VM_ASSERT_EMT(pVM);
1994
1995	pgmLock(pVM);
1996
1997	/*
1998	* Unfix any fixed mappings and disable CR3 monitoring.
1999	*/
2000	pVM->pgm.s.fMappingsFixed = false;
2001	pVM->pgm.s.GCPtrMappingFixed = 0;
2002	pVM->pgm.s.cbMappingFixed = 0;
2003
2004	/* Exit the guest paging mode before the pgm pool gets reset.
2005	* Important to clean up the amd64 case.
2006	*/
2007	int rc = PGM_GST_PFN(Exit, pVM)(pVM);
2008	AssertRC(rc);
2009	#ifdef DEBUG
2010	DBGFR3InfoLog(pVM, "mappings", NULL);
2011	DBGFR3InfoLog(pVM, "handlers", "all nostat");
2012	#endif
2013
2014	/*
2015	* Reset the shadow page pool.
2016	*/
2017	pgmR3PoolReset(pVM);
2018
2019	/*
2020	* Re-init other members.
2021	*/
2022	pVM->pgm.s.fA20Enabled = true;
2023
2024	/*
2025	* Clear the FFs PGM owns.
2026	*/
2027	VM_FF_CLEAR(pVM, VM_FF_PGM_SYNC_CR3);
2028	VM_FF_CLEAR(pVM, VM_FF_PGM_SYNC_CR3_NON_GLOBAL);
2029
2030	/*
2031	* Reset (zero) RAM pages.
2032	*/
2033	rc = pgmR3PhysRamReset(pVM);
2034	if (RT_SUCCESS(rc))
2035	{
2036	#ifdef VBOX_WITH_NEW_PHYS_CODE
2037	/*
2038	* Reset (zero) shadow ROM pages.
2039	*/
2040	rc = pgmR3PhysRomReset(pVM);
2041	#endif
2042	if (RT_SUCCESS(rc))
2043	{
2044	/*
2045	* Switch mode back to real mode.
2046	*/
2047	rc = PGMR3ChangeMode(pVM, PGMMODE_REAL);
2048	STAM_REL_COUNTER_RESET(&pVM->pgm.s.cGuestModeChanges);
2049	}
2050	}
2051
2052	pgmUnlock(pVM);
2053	//return rc;
2054	AssertReleaseRC(rc);
2055	}
2056
2057
2058	#ifdef VBOX_STRICT
2059	/**
2060	* VM state change callback for clearing fNoMorePhysWrites after
2061	* a snapshot has been created.
2062	*/
2063	static DECLCALLBACK(void) pgmR3ResetNoMorePhysWritesFlag(PVM pVM, VMSTATE enmState, VMSTATE enmOldState, void *pvUser)
2064	{
2065	if (enmState == VMSTATE_RUNNING)
2066	pVM->pgm.s.fNoMorePhysWrites = false;
2067	}
2068	#endif
2069
2070
2071	/**
2072	* Terminates the PGM.
2073	*
2074	* @returns VBox status code.
2075	* @param pVM Pointer to VM structure.
2076	*/
2077	VMMR3DECL(int) PGMR3Term(PVM pVM)
2078	{
2079	return PDMR3CritSectDelete(&pVM->pgm.s.CritSect);
2080	}
2081
2082
2083	/**
2084	* Execute state save operation.
2085	*
2086	* @returns VBox status code.
2087	* @param pVM VM Handle.
2088	* @param pSSM SSM operation handle.
2089	*/
2090	static DECLCALLBACK(int) pgmR3Save(PVM pVM, PSSMHANDLE pSSM)
2091	{
2092	PPGM pPGM = &pVM->pgm.s;
2093
2094	/* No more writes to physical memory after this point! */
2095	pVM->pgm.s.fNoMorePhysWrites = true;
2096
2097	/*
2098	* Save basic data (required / unaffected by relocation).
2099	*/
2100	#if 1
2101	SSMR3PutBool(pSSM, pPGM->fMappingsFixed);
2102	#else
2103	SSMR3PutUInt(pSSM, pPGM->fMappingsFixed);
2104	#endif
2105	SSMR3PutGCPtr(pSSM, pPGM->GCPtrMappingFixed);
2106	SSMR3PutU32(pSSM, pPGM->cbMappingFixed);
2107	SSMR3PutUInt(pSSM, pPGM->cbRamSize);
2108	SSMR3PutGCPhys(pSSM, pPGM->GCPhysA20Mask);
2109	SSMR3PutUInt(pSSM, pPGM->fA20Enabled);
2110	SSMR3PutUInt(pSSM, pPGM->fSyncFlags);
2111	SSMR3PutUInt(pSSM, pPGM->enmGuestMode);
2112	SSMR3PutU32(pSSM, ~0); /* Separator. */
2113
2114	/*
2115	* The guest mappings.
2116	*/
2117	uint32_t i = 0;
2118	for (PPGMMAPPING pMapping = pPGM->pMappingsR3; pMapping; pMapping = pMapping->pNextR3, i++)
2119	{
2120	SSMR3PutU32(pSSM, i);
2121	SSMR3PutStrZ(pSSM, pMapping->pszDesc); /* This is the best unique id we have... */
2122	SSMR3PutGCPtr(pSSM, pMapping->GCPtr);
2123	SSMR3PutGCUIntPtr(pSSM, pMapping->cPTs);
2124	/* flags are done by the mapping owners! */
2125	}
2126	SSMR3PutU32(pSSM, ~0); /* terminator. */
2127
2128	/*
2129	* Ram range flags and bits.
2130	*/
2131	i = 0;
2132	for (PPGMRAMRANGE pRam = pPGM->pRamRangesR3; pRam; pRam = pRam->pNextR3, i++)
2133	{
2134	/** @todo MMIO ranges may move (PCI reconfig), we currently assume they don't. */
2135
2136	SSMR3PutU32(pSSM, i);
2137	SSMR3PutGCPhys(pSSM, pRam->GCPhys);
2138	SSMR3PutGCPhys(pSSM, pRam->GCPhysLast);
2139	SSMR3PutGCPhys(pSSM, pRam->cb);
2140	SSMR3PutU8(pSSM, !!pRam->pvR3); /* boolean indicating memory or not. */
2141
2142	/* Flags. */
2143	const unsigned cPages = pRam->cb >> PAGE_SHIFT;
2144	for (unsigned iPage = 0; iPage < cPages; iPage++)
2145	SSMR3PutU16(pSSM, (uint16_t)(pRam->aPages[iPage].HCPhys & ~X86_PTE_PAE_PG_MASK)); /** @todo PAGE FLAGS */
2146
2147	/* any memory associated with the range. */
2148	if (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)
2149	{
2150	for (unsigned iChunk = 0; iChunk < (pRam->cb >> PGM_DYNAMIC_CHUNK_SHIFT); iChunk++)
2151	{
2152	if (pRam->paChunkR3Ptrs[iChunk])
2153	{
2154	SSMR3PutU8(pSSM, 1); /* chunk present */
2155	SSMR3PutMem(pSSM, (void *)pRam->paChunkR3Ptrs[iChunk], PGM_DYNAMIC_CHUNK_SIZE);
2156	}
2157	else
2158	SSMR3PutU8(pSSM, 0); /* no chunk present */
2159	}
2160	}
2161	else if (pRam->pvR3)
2162	{
2163	int rc = SSMR3PutMem(pSSM, pRam->pvR3, pRam->cb);
2164	if (VBOX_FAILURE(rc))
2165	{
2166	Log(("pgmR3Save: SSMR3PutMem(, %p, %#x) -> %Vrc\n", pRam->pvR3, pRam->cb, rc));
2167	return rc;
2168	}
2169	}
2170	}
2171	return SSMR3PutU32(pSSM, ~0); /* terminator. */
2172	}
2173
2174
2175	/**
2176	* Execute state load operation.
2177	*
2178	* @returns VBox status code.
2179	* @param pVM VM Handle.
2180	* @param pSSM SSM operation handle.
2181	* @param u32Version Data layout version.
2182	*/
2183	static DECLCALLBACK(int) pgmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version)
2184	{
2185	/*
2186	* Validate version.
2187	*/
2188	if (u32Version != PGM_SAVED_STATE_VERSION)
2189	{
2190	AssertMsgFailed(("pgmR3Load: Invalid version u32Version=%d (current %d)!\n", u32Version, PGM_SAVED_STATE_VERSION));
2191	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
2192	}
2193
2194	/*
2195	* Call the reset function to make sure all the memory is cleared.
2196	*/
2197	PGMR3Reset(pVM);
2198
2199	/*
2200	* Load basic data (required / unaffected by relocation).
2201	*/
2202	PPGM pPGM = &pVM->pgm.s;
2203	#if 1
2204	SSMR3GetBool(pSSM, &pPGM->fMappingsFixed);
2205	#else
2206	uint32_t u;
2207	SSMR3GetU32(pSSM, &u);
2208	pPGM->fMappingsFixed = u;
2209	#endif
2210	SSMR3GetGCPtr(pSSM, &pPGM->GCPtrMappingFixed);
2211	SSMR3GetU32(pSSM, &pPGM->cbMappingFixed);
2212
2213	RTUINT cbRamSize;
2214	int rc = SSMR3GetU32(pSSM, &cbRamSize);
2215	if (VBOX_FAILURE(rc))
2216	return rc;
2217	if (cbRamSize != pPGM->cbRamSize)
2218	return VERR_SSM_LOAD_MEMORY_SIZE_MISMATCH;
2219	SSMR3GetGCPhys(pSSM, &pPGM->GCPhysA20Mask);
2220	SSMR3GetUInt(pSSM, &pPGM->fA20Enabled);
2221	SSMR3GetUInt(pSSM, &pPGM->fSyncFlags);
2222	RTUINT uGuestMode;
2223	SSMR3GetUInt(pSSM, &uGuestMode);
2224	pPGM->enmGuestMode = (PGMMODE)uGuestMode;
2225
2226	/* check separator. */
2227	uint32_t u32Sep;
2228	SSMR3GetU32(pSSM, &u32Sep);
2229	if (VBOX_FAILURE(rc))
2230	return rc;
2231	if (u32Sep != (uint32_t)~0)
2232	{
2233	AssertMsgFailed(("u32Sep=%#x (first)\n", u32Sep));
2234	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2235	}
2236
2237	/*
2238	* The guest mappings.
2239	*/
2240	uint32_t i = 0;
2241	for (;; i++)
2242	{
2243	/* Check the seqence number / separator. */
2244	rc = SSMR3GetU32(pSSM, &u32Sep);
2245	if (VBOX_FAILURE(rc))
2246	return rc;
2247	if (u32Sep == ~0U)
2248	break;
2249	if (u32Sep != i)
2250	{
2251	AssertMsgFailed(("u32Sep=%#x (last)\n", u32Sep));
2252	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2253	}
2254
2255	/* get the mapping details. */
2256	char szDesc[256];
2257	szDesc[0] = '\0';
2258	rc = SSMR3GetStrZ(pSSM, szDesc, sizeof(szDesc));
2259	if (VBOX_FAILURE(rc))
2260	return rc;
2261	RTGCPTR GCPtr;
2262	SSMR3GetGCPtr(pSSM, &GCPtr);
2263	RTGCUINTPTR cPTs;
2264	rc = SSMR3GetGCUIntPtr(pSSM, &cPTs);
2265	if (VBOX_FAILURE(rc))
2266	return rc;
2267
2268	/* find matching range. */
2269	PPGMMAPPING pMapping;
2270	for (pMapping = pPGM->pMappingsR3; pMapping; pMapping = pMapping->pNextR3)
2271	if ( pMapping->cPTs == cPTs
2272	&& !strcmp(pMapping->pszDesc, szDesc))
2273	break;
2274	if (!pMapping)
2275	{
2276	LogRel(("Couldn't find mapping: cPTs=%#x szDesc=%s (GCPtr=%VGv)\n",
2277	cPTs, szDesc, GCPtr));
2278	AssertFailed();
2279	return VERR_SSM_LOAD_CONFIG_MISMATCH;
2280	}
2281
2282	/* relocate it. */
2283	if (pMapping->GCPtr != GCPtr)
2284	{
2285	AssertMsg((GCPtr >> X86_PD_SHIFT << X86_PD_SHIFT) == GCPtr, ("GCPtr=%VGv\n", GCPtr));
2286	#if HC_ARCH_BITS == 64
2287	LogRel(("Mapping: %VGv -> %VGv %s\n", pMapping->GCPtr, GCPtr, pMapping->pszDesc));
2288	#endif
2289	pgmR3MapRelocate(pVM, pMapping, pMapping->GCPtr, GCPtr);
2290	}
2291	else
2292	Log(("pgmR3Load: '%s' needed no relocation (%VGv)\n", szDesc, GCPtr));
2293	}
2294
2295	/*
2296	* Ram range flags and bits.
2297	*/
2298	i = 0;
2299	for (PPGMRAMRANGE pRam = pPGM->pRamRangesR3; pRam; pRam = pRam->pNextR3, i++)
2300	{
2301	/** @todo MMIO ranges may move (PCI reconfig), we currently assume they don't. */
2302	/* Check the seqence number / separator. */
2303	rc = SSMR3GetU32(pSSM, &u32Sep);
2304	if (VBOX_FAILURE(rc))
2305	return rc;
2306	if (u32Sep == ~0U)
2307	break;
2308	if (u32Sep != i)
2309	{
2310	AssertMsgFailed(("u32Sep=%#x (last)\n", u32Sep));
2311	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2312	}
2313
2314	/* Get the range details. */
2315	RTGCPHYS GCPhys;
2316	SSMR3GetGCPhys(pSSM, &GCPhys);
2317	RTGCPHYS GCPhysLast;
2318	SSMR3GetGCPhys(pSSM, &GCPhysLast);
2319	RTGCPHYS cb;
2320	SSMR3GetGCPhys(pSSM, &cb);
2321	uint8_t fHaveBits;
2322	rc = SSMR3GetU8(pSSM, &fHaveBits);
2323	if (VBOX_FAILURE(rc))
2324	return rc;
2325	if (fHaveBits & ~1)
2326	{
2327	AssertMsgFailed(("u32Sep=%#x (last)\n", u32Sep));
2328	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2329	}
2330
2331	/* Match it up with the current range. */
2332	if ( GCPhys != pRam->GCPhys
2333	\|\| GCPhysLast != pRam->GCPhysLast
2334	\|\| cb != pRam->cb
2335	\|\| fHaveBits != !!pRam->pvR3)
2336	{
2337	LogRel(("Ram range: %RGp-%RGp %RGp bytes %s\n"
2338	"State : %RGp-%RGp %RGp bytes %s\n",
2339	pRam->GCPhys, pRam->GCPhysLast, pRam->cb, pRam->pvR3 ? "bits" : "nobits",
2340	GCPhys, GCPhysLast, cb, fHaveBits ? "bits" : "nobits"));
2341	/*
2342	* If we're loading a state for debugging purpose, don't make a fuss if
2343	* the MMIO[2] and ROM stuff isn't 100% right, just skip the mismatches.
2344	*/
2345	if ( SSMR3HandleGetAfter(pSSM) != SSMAFTER_DEBUG_IT
2346	\|\| GCPhys < 8 * _1M)
2347	AssertFailedReturn(VERR_SSM_LOAD_CONFIG_MISMATCH);
2348
2349	RTGCPHYS cPages = ((GCPhysLast - GCPhys) + 1) >> PAGE_SHIFT;
2350	while (cPages-- > 0)
2351	{
2352	uint16_t u16Ignore;
2353	SSMR3GetU16(pSSM, &u16Ignore);
2354	}
2355	continue;
2356	}
2357
2358	/* Flags. */
2359	const unsigned cPages = pRam->cb >> PAGE_SHIFT;
2360	for (unsigned iPage = 0; iPage < cPages; iPage++)
2361	{
2362	uint16_t u16 = 0;
2363	SSMR3GetU16(pSSM, &u16);
2364	u16 &= PAGE_OFFSET_MASK & ~( RT_BIT(4) \| RT_BIT(5) \| RT_BIT(6)
2365	\| RT_BIT(7) \| RT_BIT(8) \| RT_BIT(9) \| RT_BIT(10) );
2366	// &= MM_RAM_FLAGS_DYNAMIC_ALLOC \| MM_RAM_FLAGS_RESERVED \| MM_RAM_FLAGS_ROM \| MM_RAM_FLAGS_MMIO \| MM_RAM_FLAGS_MMIO2
2367	pRam->aPages[iPage].HCPhys = PGM_PAGE_GET_HCPHYS(&pRam->aPages[iPage]) \| (RTHCPHYS)u16; /** @todo PAGE FLAGS */
2368	}
2369
2370	/* any memory associated with the range. */
2371	if (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)
2372	{
2373	for (unsigned iChunk = 0; iChunk < (pRam->cb >> PGM_DYNAMIC_CHUNK_SHIFT); iChunk++)
2374	{
2375	uint8_t fValidChunk;
2376
2377	rc = SSMR3GetU8(pSSM, &fValidChunk);
2378	if (VBOX_FAILURE(rc))
2379	return rc;
2380	if (fValidChunk > 1)
2381	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2382
2383	if (fValidChunk)
2384	{
2385	if (!pRam->paChunkR3Ptrs[iChunk])
2386	{
2387	rc = pgmr3PhysGrowRange(pVM, pRam->GCPhys + iChunk * PGM_DYNAMIC_CHUNK_SIZE);
2388	if (VBOX_FAILURE(rc))
2389	return rc;
2390	}
2391	Assert(pRam->paChunkR3Ptrs[iChunk]);
2392
2393	SSMR3GetMem(pSSM, (void *)pRam->paChunkR3Ptrs[iChunk], PGM_DYNAMIC_CHUNK_SIZE);
2394	}
2395	/* else nothing to do */
2396	}
2397	}
2398	else if (pRam->pvR3)
2399	{
2400	int rc = SSMR3GetMem(pSSM, pRam->pvR3, pRam->cb);
2401	if (VBOX_FAILURE(rc))
2402	{
2403	Log(("pgmR3Save: SSMR3GetMem(, %p, %#x) -> %Vrc\n", pRam->pvR3, pRam->cb, rc));
2404	return rc;
2405	}
2406	}
2407	}
2408
2409	/*
2410	* We require a full resync now.
2411	*/
2412	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3_NON_GLOBAL);
2413	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
2414	pPGM->fSyncFlags \|= PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL;
2415	pPGM->fPhysCacheFlushPending = true;
2416	pgmR3HandlerPhysicalUpdateAll(pVM);
2417
2418	/*
2419	* Change the paging mode.
2420	*/
2421	rc = PGMR3ChangeMode(pVM, pPGM->enmGuestMode);
2422
2423	/* Restore pVM->pgm.s.GCPhysCR3. */
2424	Assert(pVM->pgm.s.GCPhysCR3 == NIL_RTGCPHYS);
2425	RTGCPHYS GCPhysCR3 = CPUMGetGuestCR3(pVM);
2426	if ( pVM->pgm.s.enmGuestMode == PGMMODE_PAE
2427	\|\| pVM->pgm.s.enmGuestMode == PGMMODE_PAE_NX
2428	\|\| pVM->pgm.s.enmGuestMode == PGMMODE_AMD64
2429	\|\| pVM->pgm.s.enmGuestMode == PGMMODE_AMD64_NX)
2430	GCPhysCR3 = (GCPhysCR3 & X86_CR3_PAE_PAGE_MASK);
2431	else
2432	GCPhysCR3 = (GCPhysCR3 & X86_CR3_PAGE_MASK);
2433	pVM->pgm.s.GCPhysCR3 = GCPhysCR3;
2434
2435	return rc;
2436	}
2437
2438
2439	/**
2440	* Show paging mode.
2441	*
2442	* @param pVM VM Handle.
2443	* @param pHlp The info helpers.
2444	* @param pszArgs "all" (default), "guest", "shadow" or "host".
2445	*/
2446	static DECLCALLBACK(void) pgmR3InfoMode(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2447	{
2448	/* digest argument. */
2449	bool fGuest, fShadow, fHost;
2450	if (pszArgs)
2451	pszArgs = RTStrStripL(pszArgs);
2452	if (!pszArgs \|\| !*pszArgs \|\| strstr(pszArgs, "all"))
2453	fShadow = fHost = fGuest = true;
2454	else
2455	{
2456	fShadow = fHost = fGuest = false;
2457	if (strstr(pszArgs, "guest"))
2458	fGuest = true;
2459	if (strstr(pszArgs, "shadow"))
2460	fShadow = true;
2461	if (strstr(pszArgs, "host"))
2462	fHost = true;
2463	}
2464
2465	/* print info. */
2466	if (fGuest)
2467	pHlp->pfnPrintf(pHlp, "Guest paging mode: %s, changed %RU64 times, A20 %s\n",
2468	PGMGetModeName(pVM->pgm.s.enmGuestMode), pVM->pgm.s.cGuestModeChanges.c,
2469	pVM->pgm.s.fA20Enabled ? "enabled" : "disabled");
2470	if (fShadow)
2471	pHlp->pfnPrintf(pHlp, "Shadow paging mode: %s\n", PGMGetModeName(pVM->pgm.s.enmShadowMode));
2472	if (fHost)
2473	{
2474	const char *psz;
2475	switch (pVM->pgm.s.enmHostMode)
2476	{
2477	case SUPPAGINGMODE_INVALID: psz = "invalid"; break;
2478	case SUPPAGINGMODE_32_BIT: psz = "32-bit"; break;
2479	case SUPPAGINGMODE_32_BIT_GLOBAL: psz = "32-bit+G"; break;
2480	case SUPPAGINGMODE_PAE: psz = "PAE"; break;
2481	case SUPPAGINGMODE_PAE_GLOBAL: psz = "PAE+G"; break;
2482	case SUPPAGINGMODE_PAE_NX: psz = "PAE+NX"; break;
2483	case SUPPAGINGMODE_PAE_GLOBAL_NX: psz = "PAE+G+NX"; break;
2484	case SUPPAGINGMODE_AMD64: psz = "AMD64"; break;
2485	case SUPPAGINGMODE_AMD64_GLOBAL: psz = "AMD64+G"; break;
2486	case SUPPAGINGMODE_AMD64_NX: psz = "AMD64+NX"; break;
2487	case SUPPAGINGMODE_AMD64_GLOBAL_NX: psz = "AMD64+G+NX"; break;
2488	default: psz = "unknown"; break;
2489	}
2490	pHlp->pfnPrintf(pHlp, "Host paging mode: %s\n", psz);
2491	}
2492	}
2493
2494
2495	/**
2496	* Dump registered MMIO ranges to the log.
2497	*
2498	* @param pVM VM Handle.
2499	* @param pHlp The info helpers.
2500	* @param pszArgs Arguments, ignored.
2501	*/
2502	static DECLCALLBACK(void) pgmR3PhysInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2503	{
2504	NOREF(pszArgs);
2505	pHlp->pfnPrintf(pHlp,
2506	"RAM ranges (pVM=%p)\n"
2507	"%.s %.s\n",
2508	pVM,
2509	sizeof(RTGCPHYS) * 4 + 1, "GC Phys Range ",
2510	sizeof(RTHCPTR) * 2, "pvHC ");
2511
2512	for (PPGMRAMRANGE pCur = pVM->pgm.s.pRamRangesR3; pCur; pCur = pCur->pNextR3)
2513	pHlp->pfnPrintf(pHlp,
2514	"%RGp-%RGp %RHv %s\n",
2515	pCur->GCPhys,
2516	pCur->GCPhysLast,
2517	pCur->pvR3,
2518	pCur->pszDesc);
2519	}
2520
2521	/**
2522	* Dump the page directory to the log.
2523	*
2524	* @param pVM VM Handle.
2525	* @param pHlp The info helpers.
2526	* @param pszArgs Arguments, ignored.
2527	*/
2528	static DECLCALLBACK(void) pgmR3InfoCr3(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2529	{
2530	/** @todo fix this! Convert the PGMR3DumpHierarchyHC functions to do guest stuff. */
2531	/* Big pages supported? */
2532	const bool fPSE = !!(CPUMGetGuestCR4(pVM) & X86_CR4_PSE);
2533
2534	/* Global pages supported? */
2535	const bool fPGE = !!(CPUMGetGuestCR4(pVM) & X86_CR4_PGE);
2536
2537	NOREF(pszArgs);
2538
2539	/*
2540	* Get page directory addresses.
2541	*/
2542	PX86PD pPDSrc = pVM->pgm.s.pGuestPDHC;
2543	Assert(pPDSrc);
2544	Assert(PGMPhysGCPhys2HCPtrAssert(pVM, (RTGCPHYS)(CPUMGetGuestCR3(pVM) & X86_CR3_PAGE_MASK), sizeof(*pPDSrc)) == pPDSrc);
2545
2546	/*
2547	* Iterate the page directory.
2548	*/
2549	for (unsigned iPD = 0; iPD < RT_ELEMENTS(pPDSrc->a); iPD++)
2550	{
2551	X86PDE PdeSrc = pPDSrc->a[iPD];
2552	if (PdeSrc.n.u1Present)
2553	{
2554	if (PdeSrc.b.u1Size && fPSE)
2555	{
2556	pHlp->pfnPrintf(pHlp,
2557	"%04X - %VGp P=%d U=%d RW=%d G=%d - BIG\n",
2558	iPD,
2559	pgmGstGet4MBPhysPage(&pVM->pgm.s, PdeSrc),
2560	PdeSrc.b.u1Present, PdeSrc.b.u1User, PdeSrc.b.u1Write, PdeSrc.b.u1Global && fPGE);
2561	}
2562	else
2563	{
2564	pHlp->pfnPrintf(pHlp,
2565	"%04X - %VGp P=%d U=%d RW=%d [G=%d]\n",
2566	iPD,
2567	PdeSrc.u & X86_PDE_PG_MASK,
2568	PdeSrc.n.u1Present, PdeSrc.n.u1User, PdeSrc.n.u1Write, PdeSrc.b.u1Global && fPGE);
2569	}
2570	}
2571	}
2572	}
2573
2574
2575	/**
2576	* Serivce a VMMCALLHOST_PGM_LOCK call.
2577	*
2578	* @returns VBox status code.
2579	* @param pVM The VM handle.
2580	*/
2581	VMMR3DECL(int) PGMR3LockCall(PVM pVM)
2582	{
2583	int rc = PDMR3CritSectEnterEx(&pVM->pgm.s.CritSect, true /* fHostCall */);
2584	AssertRC(rc);
2585	return rc;
2586	}
2587
2588
2589	/**
2590	* Converts a PGMMODE value to a PGM_TYPE_* \#define.
2591	*
2592	* @returns PGM_TYPE_*.
2593	* @param pgmMode The mode value to convert.
2594	*/
2595	DECLINLINE(unsigned) pgmModeToType(PGMMODE pgmMode)
2596	{
2597	switch (pgmMode)
2598	{
2599	case PGMMODE_REAL: return PGM_TYPE_REAL;
2600	case PGMMODE_PROTECTED: return PGM_TYPE_PROT;
2601	case PGMMODE_32_BIT: return PGM_TYPE_32BIT;
2602	case PGMMODE_PAE:
2603	case PGMMODE_PAE_NX: return PGM_TYPE_PAE;
2604	case PGMMODE_AMD64:
2605	case PGMMODE_AMD64_NX: return PGM_TYPE_AMD64;
2606	case PGMMODE_NESTED: return PGM_TYPE_NESTED;
2607	case PGMMODE_EPT: return PGM_TYPE_EPT;
2608	default:
2609	AssertFatalMsgFailed(("pgmMode=%d\n", pgmMode));
2610	}
2611	}
2612
2613
2614	/**
2615	* Gets the index into the paging mode data array of a SHW+GST mode.
2616	*
2617	* @returns PGM::paPagingData index.
2618	* @param uShwType The shadow paging mode type.
2619	* @param uGstType The guest paging mode type.
2620	*/
2621	DECLINLINE(unsigned) pgmModeDataIndex(unsigned uShwType, unsigned uGstType)
2622	{
2623	Assert(uShwType >= PGM_TYPE_32BIT && uShwType <= PGM_TYPE_MAX);
2624	Assert(uGstType >= PGM_TYPE_REAL && uGstType <= PGM_TYPE_AMD64);
2625	return (uShwType - PGM_TYPE_32BIT) * (PGM_TYPE_AMD64 - PGM_TYPE_REAL + 1)
2626	+ (uGstType - PGM_TYPE_REAL);
2627	}
2628
2629
2630	/**
2631	* Gets the index into the paging mode data array of a SHW+GST mode.
2632	*
2633	* @returns PGM::paPagingData index.
2634	* @param enmShw The shadow paging mode.
2635	* @param enmGst The guest paging mode.
2636	*/
2637	DECLINLINE(unsigned) pgmModeDataIndexByMode(PGMMODE enmShw, PGMMODE enmGst)
2638	{
2639	Assert(enmShw >= PGMMODE_32_BIT && enmShw <= PGMMODE_MAX);
2640	Assert(enmGst > PGMMODE_INVALID && enmGst < PGMMODE_MAX);
2641	return pgmModeDataIndex(pgmModeToType(enmShw), pgmModeToType(enmGst));
2642	}
2643
2644
2645	/**
2646	* Calculates the max data index.
2647	* @returns The number of entries in the paging data array.
2648	*/
2649	DECLINLINE(unsigned) pgmModeDataMaxIndex(void)
2650	{
2651	return pgmModeDataIndex(PGM_TYPE_MAX, PGM_TYPE_AMD64) + 1;
2652	}
2653
2654
2655	/**
2656	* Initializes the paging mode data kept in PGM::paModeData.
2657	*
2658	* @param pVM The VM handle.
2659	* @param fResolveGCAndR0 Indicate whether or not GC and Ring-0 symbols can be resolved now.
2660	* This is used early in the init process to avoid trouble with PDM
2661	* not being initialized yet.
2662	*/
2663	static int pgmR3ModeDataInit(PVM pVM, bool fResolveGCAndR0)
2664	{
2665	PPGMMODEDATA pModeData;
2666	int rc;
2667
2668	/*
2669	* Allocate the array on the first call.
2670	*/
2671	if (!pVM->pgm.s.paModeData)
2672	{
2673	pVM->pgm.s.paModeData = (PPGMMODEDATA)MMR3HeapAllocZ(pVM, MM_TAG_PGM, sizeof(PGMMODEDATA) * pgmModeDataMaxIndex());
2674	AssertReturn(pVM->pgm.s.paModeData, VERR_NO_MEMORY);
2675	}
2676
2677	/*
2678	* Initialize the array entries.
2679	*/
2680	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_32BIT, PGM_TYPE_REAL)];
2681	pModeData->uShwType = PGM_TYPE_32BIT;
2682	pModeData->uGstType = PGM_TYPE_REAL;
2683	rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2684	rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2685	rc = PGM_BTH_NAME_32BIT_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2686
2687	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_32BIT, PGMMODE_PROTECTED)];
2688	pModeData->uShwType = PGM_TYPE_32BIT;
2689	pModeData->uGstType = PGM_TYPE_PROT;
2690	rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2691	rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2692	rc = PGM_BTH_NAME_32BIT_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2693
2694	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_32BIT, PGM_TYPE_32BIT)];
2695	pModeData->uShwType = PGM_TYPE_32BIT;
2696	pModeData->uGstType = PGM_TYPE_32BIT;
2697	rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2698	rc = PGM_GST_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2699	rc = PGM_BTH_NAME_32BIT_32BIT(InitData)(pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2700
2701	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_REAL)];
2702	pModeData->uShwType = PGM_TYPE_PAE;
2703	pModeData->uGstType = PGM_TYPE_REAL;
2704	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2705	rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2706	rc = PGM_BTH_NAME_PAE_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2707
2708	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_PROT)];
2709	pModeData->uShwType = PGM_TYPE_PAE;
2710	pModeData->uGstType = PGM_TYPE_PROT;
2711	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2712	rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2713	rc = PGM_BTH_NAME_PAE_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2714
2715	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_32BIT)];
2716	pModeData->uShwType = PGM_TYPE_PAE;
2717	pModeData->uGstType = PGM_TYPE_32BIT;
2718	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2719	rc = PGM_GST_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2720	rc = PGM_BTH_NAME_PAE_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2721
2722	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_PAE)];
2723	pModeData->uShwType = PGM_TYPE_PAE;
2724	pModeData->uGstType = PGM_TYPE_PAE;
2725	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2726	rc = PGM_GST_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2727	rc = PGM_BTH_NAME_PAE_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2728
2729	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_AMD64, PGM_TYPE_AMD64)];
2730	pModeData->uShwType = PGM_TYPE_AMD64;
2731	pModeData->uGstType = PGM_TYPE_AMD64;
2732	rc = PGM_SHW_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2733	rc = PGM_GST_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2734	rc = PGM_BTH_NAME_AMD64_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2735
2736	/* The nested paging mode. */
2737	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_REAL)];
2738	pModeData->uShwType = PGM_TYPE_NESTED;
2739	pModeData->uGstType = PGM_TYPE_REAL;
2740	rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2741	rc = PGM_BTH_NAME_NESTED_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2742
2743	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGMMODE_PROTECTED)];
2744	pModeData->uShwType = PGM_TYPE_NESTED;
2745	pModeData->uGstType = PGM_TYPE_PROT;
2746	rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2747	rc = PGM_BTH_NAME_NESTED_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2748
2749	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_32BIT)];
2750	pModeData->uShwType = PGM_TYPE_NESTED;
2751	pModeData->uGstType = PGM_TYPE_32BIT;
2752	rc = PGM_GST_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2753	rc = PGM_BTH_NAME_NESTED_32BIT(InitData)(pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2754
2755	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_PAE)];
2756	pModeData->uShwType = PGM_TYPE_NESTED;
2757	pModeData->uGstType = PGM_TYPE_PAE;
2758	rc = PGM_GST_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2759	rc = PGM_BTH_NAME_NESTED_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2760
2761	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_AMD64)];
2762	pModeData->uShwType = PGM_TYPE_NESTED;
2763	pModeData->uGstType = PGM_TYPE_AMD64;
2764	rc = PGM_GST_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2765	rc = PGM_BTH_NAME_NESTED_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2766
2767	/* The shadow part of the nested callback mode depends on the host paging mode (AMD-V only). */
2768	switch(pVM->pgm.s.enmHostMode)
2769	{
2770	case SUPPAGINGMODE_32_BIT:
2771	case SUPPAGINGMODE_32_BIT_GLOBAL:
2772	for (unsigned i=PGM_TYPE_REAL;i<=PGM_TYPE_AMD64;i++)
2773	{
2774	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, i)];
2775	rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2776	}
2777	break;
2778
2779	case SUPPAGINGMODE_PAE:
2780	case SUPPAGINGMODE_PAE_NX:
2781	case SUPPAGINGMODE_PAE_GLOBAL:
2782	case SUPPAGINGMODE_PAE_GLOBAL_NX:
2783	for (unsigned i=PGM_TYPE_REAL;i<=PGM_TYPE_AMD64;i++)
2784	{
2785	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, i)];
2786	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2787	}
2788	break;
2789
2790	case SUPPAGINGMODE_AMD64:
2791	case SUPPAGINGMODE_AMD64_GLOBAL:
2792	case SUPPAGINGMODE_AMD64_NX:
2793	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
2794	for (unsigned i=PGM_TYPE_REAL;i<=PGM_TYPE_AMD64;i++)
2795	{
2796	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, i)];
2797	rc = PGM_SHW_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2798	}
2799	break;
2800	default:
2801	AssertFailed();
2802	break;
2803	}
2804
2805	/* Extended paging (EPT) / Intel VT-x */
2806	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_REAL)];
2807	pModeData->uShwType = PGM_TYPE_EPT;
2808	pModeData->uGstType = PGM_TYPE_REAL;
2809	rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2810	rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2811	rc = PGM_BTH_NAME_EPT_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2812
2813	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_PROT)];
2814	pModeData->uShwType = PGM_TYPE_EPT;
2815	pModeData->uGstType = PGM_TYPE_PROT;
2816	rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2817	rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2818	rc = PGM_BTH_NAME_EPT_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2819
2820	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_32BIT)];
2821	pModeData->uShwType = PGM_TYPE_EPT;
2822	pModeData->uGstType = PGM_TYPE_32BIT;
2823	rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2824	rc = PGM_GST_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2825	rc = PGM_BTH_NAME_EPT_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2826
2827	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_PAE)];
2828	pModeData->uShwType = PGM_TYPE_EPT;
2829	pModeData->uGstType = PGM_TYPE_PAE;
2830	rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2831	rc = PGM_GST_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2832	rc = PGM_BTH_NAME_EPT_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2833
2834	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_AMD64)];
2835	pModeData->uShwType = PGM_TYPE_EPT;
2836	pModeData->uGstType = PGM_TYPE_AMD64;
2837	rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2838	rc = PGM_GST_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2839	rc = PGM_BTH_NAME_EPT_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2840	return VINF_SUCCESS;
2841	}
2842
2843
2844	/**
2845	* Switch to different (or relocated in the relocate case) mode data.
2846	*
2847	* @param pVM The VM handle.
2848	* @param enmShw The the shadow paging mode.
2849	* @param enmGst The the guest paging mode.
2850	*/
2851	static void pgmR3ModeDataSwitch(PVM pVM, PGMMODE enmShw, PGMMODE enmGst)
2852	{
2853	PPGMMODEDATA pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndexByMode(enmShw, enmGst)];
2854
2855	Assert(pModeData->uGstType == pgmModeToType(enmGst));
2856	Assert(pModeData->uShwType == pgmModeToType(enmShw));
2857
2858	/* shadow */
2859	pVM->pgm.s.pfnR3ShwRelocate = pModeData->pfnR3ShwRelocate;
2860	pVM->pgm.s.pfnR3ShwExit = pModeData->pfnR3ShwExit;
2861	pVM->pgm.s.pfnR3ShwGetPage = pModeData->pfnR3ShwGetPage;
2862	Assert(pVM->pgm.s.pfnR3ShwGetPage);
2863	pVM->pgm.s.pfnR3ShwModifyPage = pModeData->pfnR3ShwModifyPage;
2864
2865	pVM->pgm.s.pfnGCShwGetPage = pModeData->pfnGCShwGetPage;
2866	pVM->pgm.s.pfnGCShwModifyPage = pModeData->pfnGCShwModifyPage;
2867
2868	pVM->pgm.s.pfnR0ShwGetPage = pModeData->pfnR0ShwGetPage;
2869	pVM->pgm.s.pfnR0ShwModifyPage = pModeData->pfnR0ShwModifyPage;
2870
2871
2872	/* guest */
2873	pVM->pgm.s.pfnR3GstRelocate = pModeData->pfnR3GstRelocate;
2874	pVM->pgm.s.pfnR3GstExit = pModeData->pfnR3GstExit;
2875	pVM->pgm.s.pfnR3GstGetPage = pModeData->pfnR3GstGetPage;
2876	Assert(pVM->pgm.s.pfnR3GstGetPage);
2877	pVM->pgm.s.pfnR3GstModifyPage = pModeData->pfnR3GstModifyPage;
2878	pVM->pgm.s.pfnR3GstGetPDE = pModeData->pfnR3GstGetPDE;
2879	pVM->pgm.s.pfnR3GstMonitorCR3 = pModeData->pfnR3GstMonitorCR3;
2880	pVM->pgm.s.pfnR3GstUnmonitorCR3 = pModeData->pfnR3GstUnmonitorCR3;
2881	pVM->pgm.s.pfnR3GstMapCR3 = pModeData->pfnR3GstMapCR3;
2882	pVM->pgm.s.pfnR3GstUnmapCR3 = pModeData->pfnR3GstUnmapCR3;
2883	pVM->pgm.s.pfnR3GstWriteHandlerCR3 = pModeData->pfnR3GstWriteHandlerCR3;
2884	pVM->pgm.s.pszR3GstWriteHandlerCR3 = pModeData->pszR3GstWriteHandlerCR3;
2885	pVM->pgm.s.pfnR3GstPAEWriteHandlerCR3 = pModeData->pfnR3GstPAEWriteHandlerCR3;
2886	pVM->pgm.s.pszR3GstPAEWriteHandlerCR3 = pModeData->pszR3GstPAEWriteHandlerCR3;
2887
2888	pVM->pgm.s.pfnGCGstGetPage = pModeData->pfnGCGstGetPage;
2889	pVM->pgm.s.pfnGCGstModifyPage = pModeData->pfnGCGstModifyPage;
2890	pVM->pgm.s.pfnGCGstGetPDE = pModeData->pfnGCGstGetPDE;
2891	pVM->pgm.s.pfnGCGstMonitorCR3 = pModeData->pfnGCGstMonitorCR3;
2892	pVM->pgm.s.pfnGCGstUnmonitorCR3 = pModeData->pfnGCGstUnmonitorCR3;
2893	pVM->pgm.s.pfnGCGstMapCR3 = pModeData->pfnGCGstMapCR3;
2894	pVM->pgm.s.pfnGCGstUnmapCR3 = pModeData->pfnGCGstUnmapCR3;
2895	pVM->pgm.s.pfnGCGstWriteHandlerCR3 = pModeData->pfnGCGstWriteHandlerCR3;
2896	pVM->pgm.s.pfnGCGstPAEWriteHandlerCR3 = pModeData->pfnGCGstPAEWriteHandlerCR3;
2897
2898	pVM->pgm.s.pfnR0GstGetPage = pModeData->pfnR0GstGetPage;
2899	pVM->pgm.s.pfnR0GstModifyPage = pModeData->pfnR0GstModifyPage;
2900	pVM->pgm.s.pfnR0GstGetPDE = pModeData->pfnR0GstGetPDE;
2901	pVM->pgm.s.pfnR0GstMonitorCR3 = pModeData->pfnR0GstMonitorCR3;
2902	pVM->pgm.s.pfnR0GstUnmonitorCR3 = pModeData->pfnR0GstUnmonitorCR3;
2903	pVM->pgm.s.pfnR0GstMapCR3 = pModeData->pfnR0GstMapCR3;
2904	pVM->pgm.s.pfnR0GstUnmapCR3 = pModeData->pfnR0GstUnmapCR3;
2905	pVM->pgm.s.pfnR0GstWriteHandlerCR3 = pModeData->pfnR0GstWriteHandlerCR3;
2906	pVM->pgm.s.pfnR0GstPAEWriteHandlerCR3 = pModeData->pfnR0GstPAEWriteHandlerCR3;
2907
2908
2909	/* both */
2910	pVM->pgm.s.pfnR3BthRelocate = pModeData->pfnR3BthRelocate;
2911	pVM->pgm.s.pfnR3BthTrap0eHandler = pModeData->pfnR3BthTrap0eHandler;
2912	pVM->pgm.s.pfnR3BthInvalidatePage = pModeData->pfnR3BthInvalidatePage;
2913	pVM->pgm.s.pfnR3BthSyncCR3 = pModeData->pfnR3BthSyncCR3;
2914	Assert(pVM->pgm.s.pfnR3BthSyncCR3);
2915	pVM->pgm.s.pfnR3BthSyncPage = pModeData->pfnR3BthSyncPage;
2916	pVM->pgm.s.pfnR3BthPrefetchPage = pModeData->pfnR3BthPrefetchPage;
2917	pVM->pgm.s.pfnR3BthVerifyAccessSyncPage = pModeData->pfnR3BthVerifyAccessSyncPage;
2918	#ifdef VBOX_STRICT
2919	pVM->pgm.s.pfnR3BthAssertCR3 = pModeData->pfnR3BthAssertCR3;
2920	#endif
2921
2922	pVM->pgm.s.pfnGCBthTrap0eHandler = pModeData->pfnGCBthTrap0eHandler;
2923	pVM->pgm.s.pfnGCBthInvalidatePage = pModeData->pfnGCBthInvalidatePage;
2924	pVM->pgm.s.pfnGCBthSyncCR3 = pModeData->pfnGCBthSyncCR3;
2925	pVM->pgm.s.pfnGCBthSyncPage = pModeData->pfnGCBthSyncPage;
2926	pVM->pgm.s.pfnGCBthPrefetchPage = pModeData->pfnGCBthPrefetchPage;
2927	pVM->pgm.s.pfnGCBthVerifyAccessSyncPage = pModeData->pfnGCBthVerifyAccessSyncPage;
2928	#ifdef VBOX_STRICT
2929	pVM->pgm.s.pfnGCBthAssertCR3 = pModeData->pfnGCBthAssertCR3;
2930	#endif
2931
2932	pVM->pgm.s.pfnR0BthTrap0eHandler = pModeData->pfnR0BthTrap0eHandler;
2933	pVM->pgm.s.pfnR0BthInvalidatePage = pModeData->pfnR0BthInvalidatePage;
2934	pVM->pgm.s.pfnR0BthSyncCR3 = pModeData->pfnR0BthSyncCR3;
2935	pVM->pgm.s.pfnR0BthSyncPage = pModeData->pfnR0BthSyncPage;
2936	pVM->pgm.s.pfnR0BthPrefetchPage = pModeData->pfnR0BthPrefetchPage;
2937	pVM->pgm.s.pfnR0BthVerifyAccessSyncPage = pModeData->pfnR0BthVerifyAccessSyncPage;
2938	#ifdef VBOX_STRICT
2939	pVM->pgm.s.pfnR0BthAssertCR3 = pModeData->pfnR0BthAssertCR3;
2940	#endif
2941	}
2942
2943
2944	#ifdef DEBUG_bird
2945	#include <stdlib.h> /* getenv() remove me! */
2946	#endif
2947
2948	/**
2949	* Calculates the shadow paging mode.
2950	*
2951	* @returns The shadow paging mode.
2952	* @param pVM VM handle.
2953	* @param enmGuestMode The guest mode.
2954	* @param enmHostMode The host mode.
2955	* @param enmShadowMode The current shadow mode.
2956	* @param penmSwitcher Where to store the switcher to use.
2957	* VMMSWITCHER_INVALID means no change.
2958	*/
2959	static PGMMODE pgmR3CalcShadowMode(PVM pVM, PGMMODE enmGuestMode, SUPPAGINGMODE enmHostMode, PGMMODE enmShadowMode, VMMSWITCHER *penmSwitcher)
2960	{
2961	VMMSWITCHER enmSwitcher = VMMSWITCHER_INVALID;
2962	switch (enmGuestMode)
2963	{
2964	/*
2965	* When switching to real or protected mode we don't change
2966	* anything since it's likely that we'll switch back pretty soon.
2967	*
2968	* During pgmR3InitPaging we'll end up here with PGMMODE_INVALID
2969	* and is supposed to determine which shadow paging and switcher to
2970	* use during init.
2971	*/
2972	case PGMMODE_REAL:
2973	case PGMMODE_PROTECTED:
2974	if ( enmShadowMode != PGMMODE_INVALID
2975	&& !HWACCMIsEnabled(pVM) /* always switch in hwaccm mode! */)
2976	break; /* (no change) */
2977
2978	switch (enmHostMode)
2979	{
2980	case SUPPAGINGMODE_32_BIT:
2981	case SUPPAGINGMODE_32_BIT_GLOBAL:
2982	enmShadowMode = PGMMODE_32_BIT;
2983	enmSwitcher = VMMSWITCHER_32_TO_32;
2984	break;
2985
2986	case SUPPAGINGMODE_PAE:
2987	case SUPPAGINGMODE_PAE_NX:
2988	case SUPPAGINGMODE_PAE_GLOBAL:
2989	case SUPPAGINGMODE_PAE_GLOBAL_NX:
2990	enmShadowMode = PGMMODE_PAE;
2991	enmSwitcher = VMMSWITCHER_PAE_TO_PAE;
2992	#ifdef DEBUG_bird
2993	if (getenv("VBOX_32BIT"))
2994	{
2995	enmShadowMode = PGMMODE_32_BIT;
2996	enmSwitcher = VMMSWITCHER_PAE_TO_32;
2997	}
2998	#endif
2999	break;
3000
3001	case SUPPAGINGMODE_AMD64:
3002	case SUPPAGINGMODE_AMD64_GLOBAL:
3003	case SUPPAGINGMODE_AMD64_NX:
3004	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
3005	enmShadowMode = PGMMODE_PAE;
3006	enmSwitcher = VMMSWITCHER_AMD64_TO_PAE;
3007	break;
3008
3009	default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
3010	}
3011	break;
3012
3013	case PGMMODE_32_BIT:
3014	switch (enmHostMode)
3015	{
3016	case SUPPAGINGMODE_32_BIT:
3017	case SUPPAGINGMODE_32_BIT_GLOBAL:
3018	enmShadowMode = PGMMODE_32_BIT;
3019	enmSwitcher = VMMSWITCHER_32_TO_32;
3020	break;
3021
3022	case SUPPAGINGMODE_PAE:
3023	case SUPPAGINGMODE_PAE_NX:
3024	case SUPPAGINGMODE_PAE_GLOBAL:
3025	case SUPPAGINGMODE_PAE_GLOBAL_NX:
3026	enmShadowMode = PGMMODE_PAE;
3027	enmSwitcher = VMMSWITCHER_PAE_TO_PAE;
3028	#ifdef DEBUG_bird
3029	if (getenv("VBOX_32BIT"))
3030	{
3031	enmShadowMode = PGMMODE_32_BIT;
3032	enmSwitcher = VMMSWITCHER_PAE_TO_32;
3033	}
3034	#endif
3035	break;
3036
3037	case SUPPAGINGMODE_AMD64:
3038	case SUPPAGINGMODE_AMD64_GLOBAL:
3039	case SUPPAGINGMODE_AMD64_NX:
3040	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
3041	enmShadowMode = PGMMODE_PAE;
3042	enmSwitcher = VMMSWITCHER_AMD64_TO_PAE;
3043	break;
3044
3045	default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
3046	}
3047	break;
3048
3049	case PGMMODE_PAE:
3050	case PGMMODE_PAE_NX: /** @todo This might require more switchers and guest+both modes. */
3051	switch (enmHostMode)
3052	{
3053	case SUPPAGINGMODE_32_BIT:
3054	case SUPPAGINGMODE_32_BIT_GLOBAL:
3055	enmShadowMode = PGMMODE_PAE;
3056	enmSwitcher = VMMSWITCHER_32_TO_PAE;
3057	break;
3058
3059	case SUPPAGINGMODE_PAE:
3060	case SUPPAGINGMODE_PAE_NX:
3061	case SUPPAGINGMODE_PAE_GLOBAL:
3062	case SUPPAGINGMODE_PAE_GLOBAL_NX:
3063	enmShadowMode = PGMMODE_PAE;
3064	enmSwitcher = VMMSWITCHER_PAE_TO_PAE;
3065	break;
3066
3067	case SUPPAGINGMODE_AMD64:
3068	case SUPPAGINGMODE_AMD64_GLOBAL:
3069	case SUPPAGINGMODE_AMD64_NX:
3070	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
3071	enmShadowMode = PGMMODE_PAE;
3072	enmSwitcher = VMMSWITCHER_AMD64_TO_PAE;
3073	break;
3074
3075	default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
3076	}
3077	break;
3078
3079	case PGMMODE_AMD64:
3080	case PGMMODE_AMD64_NX:
3081	switch (enmHostMode)
3082	{
3083	case SUPPAGINGMODE_32_BIT:
3084	case SUPPAGINGMODE_32_BIT_GLOBAL:
3085	enmShadowMode = PGMMODE_PAE;
3086	enmSwitcher = VMMSWITCHER_32_TO_AMD64;
3087	break;
3088
3089	case SUPPAGINGMODE_PAE:
3090	case SUPPAGINGMODE_PAE_NX:
3091	case SUPPAGINGMODE_PAE_GLOBAL:
3092	case SUPPAGINGMODE_PAE_GLOBAL_NX:
3093	enmShadowMode = PGMMODE_PAE;
3094	enmSwitcher = VMMSWITCHER_PAE_TO_AMD64;
3095	break;
3096
3097	case SUPPAGINGMODE_AMD64:
3098	case SUPPAGINGMODE_AMD64_GLOBAL:
3099	case SUPPAGINGMODE_AMD64_NX:
3100	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
3101	enmShadowMode = PGMMODE_AMD64;
3102	enmSwitcher = VMMSWITCHER_AMD64_TO_AMD64;
3103	break;
3104
3105	default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
3106	}
3107	break;
3108
3109
3110	default:
3111	AssertReleaseMsgFailed(("enmGuestMode=%d\n", enmGuestMode));
3112	return PGMMODE_INVALID;
3113	}
3114	/* Override the shadow mode is nested paging is active. */
3115	if (HWACCMIsNestedPagingActive(pVM))
3116	enmShadowMode = HWACCMGetPagingMode(pVM);
3117
3118	*penmSwitcher = enmSwitcher;
3119	return enmShadowMode;
3120	}
3121
3122	/**
3123	* Performs the actual mode change.
3124	* This is called by PGMChangeMode and pgmR3InitPaging().
3125	*
3126	* @returns VBox status code.
3127	* @param pVM VM handle.
3128	* @param enmGuestMode The new guest mode. This is assumed to be different from
3129	* the current mode.
3130	*/
3131	VMMR3DECL(int) PGMR3ChangeMode(PVM pVM, PGMMODE enmGuestMode)
3132	{
3133	Log(("PGMR3ChangeMode: Guest mode: %s -> %s\n", PGMGetModeName(pVM->pgm.s.enmGuestMode), PGMGetModeName(enmGuestMode)));
3134	STAM_REL_COUNTER_INC(&pVM->pgm.s.cGuestModeChanges);
3135
3136	/*
3137	* Calc the shadow mode and switcher.
3138	*/
3139	VMMSWITCHER enmSwitcher;
3140	PGMMODE enmShadowMode = pgmR3CalcShadowMode(pVM, enmGuestMode, pVM->pgm.s.enmHostMode, pVM->pgm.s.enmShadowMode, &enmSwitcher);
3141	if (enmSwitcher != VMMSWITCHER_INVALID)
3142	{
3143	/*
3144	* Select new switcher.
3145	*/
3146	int rc = VMMR3SelectSwitcher(pVM, enmSwitcher);
3147	if (VBOX_FAILURE(rc))
3148	{
3149	AssertReleaseMsgFailed(("VMMR3SelectSwitcher(%d) -> %Vrc\n", enmSwitcher, rc));
3150	return rc;
3151	}
3152	}
3153
3154	/*
3155	* Exit old mode(s).
3156	*/
3157	/* shadow */
3158	if (enmShadowMode != pVM->pgm.s.enmShadowMode)
3159	{
3160	LogFlow(("PGMR3ChangeMode: Shadow mode: %s -> %s\n", PGMGetModeName(pVM->pgm.s.enmShadowMode), PGMGetModeName(enmShadowMode)));
3161	if (PGM_SHW_PFN(Exit, pVM))
3162	{
3163	int rc = PGM_SHW_PFN(Exit, pVM)(pVM);
3164	if (VBOX_FAILURE(rc))
3165	{
3166	AssertMsgFailed(("Exit failed for shadow mode %d: %Vrc\n", pVM->pgm.s.enmShadowMode, rc));
3167	return rc;
3168	}
3169	}
3170
3171	}
3172	else
3173	LogFlow(("PGMR3ChangeMode: Shadow mode remains: %s\n", PGMGetModeName(pVM->pgm.s.enmShadowMode)));
3174
3175	/* guest */
3176	if (PGM_GST_PFN(Exit, pVM))
3177	{
3178	int rc = PGM_GST_PFN(Exit, pVM)(pVM);
3179	if (VBOX_FAILURE(rc))
3180	{
3181	AssertMsgFailed(("Exit failed for guest mode %d: %Vrc\n", pVM->pgm.s.enmGuestMode, rc));
3182	return rc;
3183	}
3184	}
3185
3186	/*
3187	* Load new paging mode data.
3188	*/
3189	pgmR3ModeDataSwitch(pVM, enmShadowMode, enmGuestMode);
3190
3191	/*
3192	* Enter new shadow mode (if changed).
3193	*/
3194	if (enmShadowMode != pVM->pgm.s.enmShadowMode)
3195	{
3196	int rc;
3197	pVM->pgm.s.enmShadowMode = enmShadowMode;
3198	switch (enmShadowMode)
3199	{
3200	case PGMMODE_32_BIT:
3201	rc = PGM_SHW_NAME_32BIT(Enter)(pVM);
3202	break;
3203	case PGMMODE_PAE:
3204	case PGMMODE_PAE_NX:
3205	rc = PGM_SHW_NAME_PAE(Enter)(pVM);
3206	break;
3207	case PGMMODE_AMD64:
3208	case PGMMODE_AMD64_NX:
3209	rc = PGM_SHW_NAME_AMD64(Enter)(pVM);
3210	break;
3211	case PGMMODE_NESTED:
3212	rc = PGM_SHW_NAME_NESTED(Enter)(pVM);
3213	break;
3214	case PGMMODE_EPT:
3215	rc = PGM_SHW_NAME_EPT(Enter)(pVM);
3216	break;
3217	case PGMMODE_REAL:
3218	case PGMMODE_PROTECTED:
3219	default:
3220	AssertReleaseMsgFailed(("enmShadowMode=%d\n", enmShadowMode));
3221	return VERR_INTERNAL_ERROR;
3222	}
3223	if (VBOX_FAILURE(rc))
3224	{
3225	AssertReleaseMsgFailed(("Entering enmShadowMode=%d failed: %Vrc\n", enmShadowMode, rc));
3226	pVM->pgm.s.enmShadowMode = PGMMODE_INVALID;
3227	return rc;
3228	}
3229	}
3230
3231	/* We must flush the PGM pool cache if the guest mode changes; we don't always
3232	* switch shadow paging mode (e.g. protected->32-bit) and shouldn't reuse
3233	* the shadow page tables.
3234	*
3235	* That only applies when switching between paging and non-paging modes.
3236	*
3237	* @todo A20 setting
3238	*/
3239	if ( pVM->pgm.s.CTXSUFF(pPool)
3240	&& !HWACCMIsNestedPagingActive(pVM)
3241	&& PGMMODE_WITH_PAGING(pVM->pgm.s.enmGuestMode) != PGMMODE_WITH_PAGING(enmGuestMode))
3242	{
3243	Log(("PGMR3ChangeMode: changing guest paging mode -> flush pgm pool cache!\n"));
3244	pgmPoolFlushAll(pVM);
3245	}
3246
3247	/*
3248	* Enter the new guest and shadow+guest modes.
3249	*/
3250	int rc = -1;
3251	int rc2 = -1;
3252	RTGCPHYS GCPhysCR3 = NIL_RTGCPHYS;
3253	pVM->pgm.s.enmGuestMode = enmGuestMode;
3254	switch (enmGuestMode)
3255	{
3256	case PGMMODE_REAL:
3257	rc = PGM_GST_NAME_REAL(Enter)(pVM, NIL_RTGCPHYS);
3258	switch (pVM->pgm.s.enmShadowMode)
3259	{
3260	case PGMMODE_32_BIT:
3261	rc2 = PGM_BTH_NAME_32BIT_REAL(Enter)(pVM, NIL_RTGCPHYS);
3262	break;
3263	case PGMMODE_PAE:
3264	case PGMMODE_PAE_NX:
3265	rc2 = PGM_BTH_NAME_PAE_REAL(Enter)(pVM, NIL_RTGCPHYS);
3266	break;
3267	case PGMMODE_NESTED:
3268	rc2 = PGM_BTH_NAME_NESTED_REAL(Enter)(pVM, NIL_RTGCPHYS);
3269	break;
3270	case PGMMODE_EPT:
3271	rc2 = PGM_BTH_NAME_EPT_REAL(Enter)(pVM, NIL_RTGCPHYS);
3272	break;
3273	case PGMMODE_AMD64:
3274	case PGMMODE_AMD64_NX:
3275	AssertMsgFailed(("Should use PAE shadow mode!\n"));
3276	default: AssertFailed(); break;
3277	}
3278	break;
3279
3280	case PGMMODE_PROTECTED:
3281	rc = PGM_GST_NAME_PROT(Enter)(pVM, NIL_RTGCPHYS);
3282	switch (pVM->pgm.s.enmShadowMode)
3283	{
3284	case PGMMODE_32_BIT:
3285	rc2 = PGM_BTH_NAME_32BIT_PROT(Enter)(pVM, NIL_RTGCPHYS);
3286	break;
3287	case PGMMODE_PAE:
3288	case PGMMODE_PAE_NX:
3289	rc2 = PGM_BTH_NAME_PAE_PROT(Enter)(pVM, NIL_RTGCPHYS);
3290	break;
3291	case PGMMODE_NESTED:
3292	rc2 = PGM_BTH_NAME_NESTED_PROT(Enter)(pVM, NIL_RTGCPHYS);
3293	break;
3294	case PGMMODE_EPT:
3295	rc2 = PGM_BTH_NAME_EPT_PROT(Enter)(pVM, NIL_RTGCPHYS);
3296	break;
3297	case PGMMODE_AMD64:
3298	case PGMMODE_AMD64_NX:
3299	AssertMsgFailed(("Should use PAE shadow mode!\n"));
3300	default: AssertFailed(); break;
3301	}
3302	break;
3303
3304	case PGMMODE_32_BIT:
3305	GCPhysCR3 = CPUMGetGuestCR3(pVM) & X86_CR3_PAGE_MASK;
3306	rc = PGM_GST_NAME_32BIT(Enter)(pVM, GCPhysCR3);
3307	switch (pVM->pgm.s.enmShadowMode)
3308	{
3309	case PGMMODE_32_BIT:
3310	rc2 = PGM_BTH_NAME_32BIT_32BIT(Enter)(pVM, GCPhysCR3);
3311	break;
3312	case PGMMODE_PAE:
3313	case PGMMODE_PAE_NX:
3314	rc2 = PGM_BTH_NAME_PAE_32BIT(Enter)(pVM, GCPhysCR3);
3315	break;
3316	case PGMMODE_NESTED:
3317	rc2 = PGM_BTH_NAME_NESTED_32BIT(Enter)(pVM, GCPhysCR3);
3318	break;
3319	case PGMMODE_EPT:
3320	rc2 = PGM_BTH_NAME_EPT_32BIT(Enter)(pVM, GCPhysCR3);
3321	break;
3322	case PGMMODE_AMD64:
3323	case PGMMODE_AMD64_NX:
3324	AssertMsgFailed(("Should use PAE shadow mode!\n"));
3325	default: AssertFailed(); break;
3326	}
3327	break;
3328
3329	case PGMMODE_PAE_NX:
3330	case PGMMODE_PAE:
3331	{
3332	uint32_t u32Dummy, u32Features;
3333
3334	CPUMGetGuestCpuId(pVM, 1, &u32Dummy, &u32Dummy, &u32Dummy, &u32Features);
3335	if (!(u32Features & X86_CPUID_FEATURE_EDX_PAE))
3336	{
3337	/* Pause first, then inform Main. */
3338	rc = VMR3SuspendNoSave(pVM);
3339	AssertRC(rc);
3340
3341	VMSetRuntimeError(pVM, true, "PAEmode",
3342	N_("The guest is trying to switch to the PAE mode which is currently disabled by default in VirtualBox. Experimental PAE support can be enabled using the -pae option with VBoxManage"));
3343	/* we must return TRUE here otherwise the recompiler will assert */
3344	return VINF_SUCCESS;
3345	}
3346	GCPhysCR3 = CPUMGetGuestCR3(pVM) & X86_CR3_PAE_PAGE_MASK;
3347	rc = PGM_GST_NAME_PAE(Enter)(pVM, GCPhysCR3);
3348	switch (pVM->pgm.s.enmShadowMode)
3349	{
3350	case PGMMODE_PAE:
3351	case PGMMODE_PAE_NX:
3352	rc2 = PGM_BTH_NAME_PAE_PAE(Enter)(pVM, GCPhysCR3);
3353	break;
3354	case PGMMODE_NESTED:
3355	rc2 = PGM_BTH_NAME_NESTED_PAE(Enter)(pVM, GCPhysCR3);
3356	break;
3357	case PGMMODE_EPT:
3358	rc2 = PGM_BTH_NAME_EPT_PAE(Enter)(pVM, GCPhysCR3);
3359	break;
3360	case PGMMODE_32_BIT:
3361	case PGMMODE_AMD64:
3362	case PGMMODE_AMD64_NX:
3363	AssertMsgFailed(("Should use PAE shadow mode!\n"));
3364	default: AssertFailed(); break;
3365	}
3366	break;
3367	}
3368
3369	case PGMMODE_AMD64_NX:
3370	case PGMMODE_AMD64:
3371	GCPhysCR3 = CPUMGetGuestCR3(pVM) & 0xfffffffffffff000ULL; /** @todo define this mask! */
3372	rc = PGM_GST_NAME_AMD64(Enter)(pVM, GCPhysCR3);
3373	switch (pVM->pgm.s.enmShadowMode)
3374	{
3375	case PGMMODE_AMD64:
3376	case PGMMODE_AMD64_NX:
3377	rc2 = PGM_BTH_NAME_AMD64_AMD64(Enter)(pVM, GCPhysCR3);
3378	break;
3379	case PGMMODE_NESTED:
3380	rc2 = PGM_BTH_NAME_NESTED_AMD64(Enter)(pVM, GCPhysCR3);
3381	break;
3382	case PGMMODE_EPT:
3383	rc2 = PGM_BTH_NAME_EPT_AMD64(Enter)(pVM, GCPhysCR3);
3384	break;
3385	case PGMMODE_32_BIT:
3386	case PGMMODE_PAE:
3387	case PGMMODE_PAE_NX:
3388	AssertMsgFailed(("Should use AMD64 shadow mode!\n"));
3389	default: AssertFailed(); break;
3390	}
3391	break;
3392
3393	default:
3394	AssertReleaseMsgFailed(("enmGuestMode=%d\n", enmGuestMode));
3395	rc = VERR_NOT_IMPLEMENTED;
3396	break;
3397	}
3398
3399	/* status codes. */
3400	AssertRC(rc);
3401	AssertRC(rc2);
3402	if (VBOX_SUCCESS(rc))
3403	{
3404	rc = rc2;
3405	if (VBOX_SUCCESS(rc)) /* no informational status codes. */
3406	rc = VINF_SUCCESS;
3407	}
3408
3409	/*
3410	* Notify SELM so it can update the TSSes with correct CR3s.
3411	*/
3412	SELMR3PagingModeChanged(pVM);
3413
3414	/* Notify HWACCM as well. */
3415	HWACCMR3PagingModeChanged(pVM, pVM->pgm.s.enmShadowMode);
3416	return rc;
3417	}
3418
3419
3420	/**
3421	* Dumps a PAE shadow page table.
3422	*
3423	* @returns VBox status code (VINF_SUCCESS).
3424	* @param pVM The VM handle.
3425	* @param pPT Pointer to the page table.
3426	* @param u64Address The virtual address of the page table starts.
3427	* @param fLongMode Set if this a long mode table; clear if it's a legacy mode table.
3428	* @param cMaxDepth The maxium depth.
3429	* @param pHlp Pointer to the output functions.
3430	*/
3431	static int pgmR3DumpHierarchyHCPaePT(PVM pVM, PX86PTPAE pPT, uint64_t u64Address, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
3432	{
3433	for (unsigned i = 0; i < RT_ELEMENTS(pPT->a); i++)
3434	{
3435	X86PTEPAE Pte = pPT->a[i];
3436	if (Pte.n.u1Present)
3437	{
3438	pHlp->pfnPrintf(pHlp,
3439	fLongMode /P R S A D G WT CD AT NX 4M a p ? /
3440	? "%016llx 3 \| P %c %c %c %c %c %s %s %s %s 4K %c%c%c %016llx\n"
3441	: "%08llx 2 \| P %c %c %c %c %c %s %s %s %s 4K %c%c%c %016llx\n",
3442	u64Address + ((uint64_t)i << X86_PT_PAE_SHIFT),
3443	Pte.n.u1Write ? 'W' : 'R',
3444	Pte.n.u1User ? 'U' : 'S',
3445	Pte.n.u1Accessed ? 'A' : '-',
3446	Pte.n.u1Dirty ? 'D' : '-',
3447	Pte.n.u1Global ? 'G' : '-',
3448	Pte.n.u1WriteThru ? "WT" : "--",
3449	Pte.n.u1CacheDisable? "CD" : "--",
3450	Pte.n.u1PAT ? "AT" : "--",
3451	Pte.n.u1NoExecute ? "NX" : "--",
3452	Pte.u & PGM_PTFLAGS_TRACK_DIRTY ? 'd' : '-',
3453	Pte.u & RT_BIT(10) ? '1' : '0',
3454	Pte.u & PGM_PTFLAGS_CSAM_VALIDATED? 'v' : '-',
3455	Pte.u & X86_PTE_PAE_PG_MASK);
3456	}
3457	}
3458	return VINF_SUCCESS;
3459	}
3460
3461
3462	/**
3463	* Dumps a PAE shadow page directory table.
3464	*
3465	* @returns VBox status code (VINF_SUCCESS).
3466	* @param pVM The VM handle.
3467	* @param HCPhys The physical address of the page directory table.
3468	* @param u64Address The virtual address of the page table starts.
3469	* @param cr4 The CR4, PSE is currently used.
3470	* @param fLongMode Set if this a long mode table; clear if it's a legacy mode table.
3471	* @param cMaxDepth The maxium depth.
3472	* @param pHlp Pointer to the output functions.
3473	*/
3474	static int pgmR3DumpHierarchyHCPaePD(PVM pVM, RTHCPHYS HCPhys, uint64_t u64Address, uint32_t cr4, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
3475	{
3476	PX86PDPAE pPD = (PX86PDPAE)MMPagePhys2Page(pVM, HCPhys);
3477	if (!pPD)
3478	{
3479	pHlp->pfnPrintf(pHlp, "%0*llx error! Page directory at HCPhys=%#VHp was not found in the page pool!\n",
3480	fLongMode ? 16 : 8, u64Address, HCPhys);
3481	return VERR_INVALID_PARAMETER;
3482	}
3483	const bool fBigPagesSupported = fLongMode \|\| !!(cr4 & X86_CR4_PSE);
3484
3485	int rc = VINF_SUCCESS;
3486	for (unsigned i = 0; i < RT_ELEMENTS(pPD->a); i++)
3487	{
3488	X86PDEPAE Pde = pPD->a[i];
3489	if (Pde.n.u1Present)
3490	{
3491	if (fBigPagesSupported && Pde.b.u1Size)
3492	pHlp->pfnPrintf(pHlp,
3493	fLongMode /P R S A D G WT CD AT NX 4M a p ? /
3494	? "%016llx 2 \| P %c %c %c %c %c %s %s %s %s 4M %c%c%c %016llx\n"
3495	: "%08llx 1 \| P %c %c %c %c %c %s %s %s %s 4M %c%c%c %016llx\n",
3496	u64Address + ((uint64_t)i << X86_PD_PAE_SHIFT),
3497	Pde.b.u1Write ? 'W' : 'R',
3498	Pde.b.u1User ? 'U' : 'S',
3499	Pde.b.u1Accessed ? 'A' : '-',
3500	Pde.b.u1Dirty ? 'D' : '-',
3501	Pde.b.u1Global ? 'G' : '-',
3502	Pde.b.u1WriteThru ? "WT" : "--",
3503	Pde.b.u1CacheDisable? "CD" : "--",
3504	Pde.b.u1PAT ? "AT" : "--",
3505	Pde.b.u1NoExecute ? "NX" : "--",
3506	Pde.u & RT_BIT_64(9) ? '1' : '0',
3507	Pde.u & PGM_PDFLAGS_MAPPING ? 'm' : '-',
3508	Pde.u & PGM_PDFLAGS_TRACK_DIRTY ? 'd' : '-',
3509	Pde.u & X86_PDE_PAE_PG_MASK);
3510	else
3511	{
3512	pHlp->pfnPrintf(pHlp,
3513	fLongMode /P R S A D G WT CD AT NX 4M a p ? /
3514	? "%016llx 2 \| P %c %c %c %c %c %s %s .. %s 4K %c%c%c %016llx\n"
3515	: "%08llx 1 \| P %c %c %c %c %c %s %s .. %s 4K %c%c%c %016llx\n",
3516	u64Address + ((uint64_t)i << X86_PD_PAE_SHIFT),
3517	Pde.n.u1Write ? 'W' : 'R',
3518	Pde.n.u1User ? 'U' : 'S',
3519	Pde.n.u1Accessed ? 'A' : '-',
3520	Pde.n.u1Reserved0 ? '?' : '.', /* ignored */
3521	Pde.n.u1Reserved1 ? '?' : '.', /* ignored */
3522	Pde.n.u1WriteThru ? "WT" : "--",
3523	Pde.n.u1CacheDisable? "CD" : "--",
3524	Pde.n.u1NoExecute ? "NX" : "--",
3525	Pde.u & RT_BIT_64(9) ? '1' : '0',
3526	Pde.u & PGM_PDFLAGS_MAPPING ? 'm' : '-',
3527	Pde.u & PGM_PDFLAGS_TRACK_DIRTY ? 'd' : '-',
3528	Pde.u & X86_PDE_PAE_PG_MASK);
3529	if (cMaxDepth >= 1)
3530	{
3531	/** @todo what about using the page pool for mapping PTs? */
3532	uint64_t u64AddressPT = u64Address + ((uint64_t)i << X86_PD_PAE_SHIFT);
3533	RTHCPHYS HCPhysPT = Pde.u & X86_PDE_PAE_PG_MASK;
3534	PX86PTPAE pPT = NULL;
3535	if (!(Pde.u & PGM_PDFLAGS_MAPPING))
3536	pPT = (PX86PTPAE)MMPagePhys2Page(pVM, HCPhysPT);
3537	else
3538	{
3539	for (PPGMMAPPING pMap = pVM->pgm.s.pMappingsR3; pMap; pMap = pMap->pNextR3)
3540	{
3541	uint64_t off = u64AddressPT - pMap->GCPtr;
3542	if (off < pMap->cb)
3543	{
3544	const int iPDE = (uint32_t)(off >> X86_PD_SHIFT);
3545	const int iSub = (int)((off >> X86_PD_PAE_SHIFT) & 1); /* MSC is a pain sometimes */
3546	if ((iSub ? pMap->aPTs[iPDE].HCPhysPaePT1 : pMap->aPTs[iPDE].HCPhysPaePT0) != HCPhysPT)
3547	pHlp->pfnPrintf(pHlp, "%0*llx error! Mapping error! PT %d has HCPhysPT=%VHp not %VHp is in the PD.\n",
3548	fLongMode ? 16 : 8, u64AddressPT, iPDE,
3549	iSub ? pMap->aPTs[iPDE].HCPhysPaePT1 : pMap->aPTs[iPDE].HCPhysPaePT0, HCPhysPT);
3550	pPT = &pMap->aPTs[iPDE].paPaePTsR3[iSub];
3551	}
3552	}
3553	}
3554	int rc2 = VERR_INVALID_PARAMETER;
3555	if (pPT)
3556	rc2 = pgmR3DumpHierarchyHCPaePT(pVM, pPT, u64AddressPT, fLongMode, cMaxDepth - 1, pHlp);
3557	else
3558	pHlp->pfnPrintf(pHlp, "%0*llx error! Page table at HCPhys=%#VHp was not found in the page pool!\n",
3559	fLongMode ? 16 : 8, u64AddressPT, HCPhysPT);
3560	if (rc2 < rc && VBOX_SUCCESS(rc))
3561	rc = rc2;
3562	}
3563	}
3564	}
3565	}
3566	return rc;
3567	}
3568
3569
3570	/**
3571	* Dumps a PAE shadow page directory pointer table.
3572	*
3573	* @returns VBox status code (VINF_SUCCESS).
3574	* @param pVM The VM handle.
3575	* @param HCPhys The physical address of the page directory pointer table.
3576	* @param u64Address The virtual address of the page table starts.
3577	* @param cr4 The CR4, PSE is currently used.
3578	* @param fLongMode Set if this a long mode table; clear if it's a legacy mode table.
3579	* @param cMaxDepth The maxium depth.
3580	* @param pHlp Pointer to the output functions.
3581	*/
3582	static int pgmR3DumpHierarchyHCPaePDPT(PVM pVM, RTHCPHYS HCPhys, uint64_t u64Address, uint32_t cr4, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
3583	{
3584	PX86PDPT pPDPT = (PX86PDPT)MMPagePhys2Page(pVM, HCPhys);
3585	if (!pPDPT)
3586	{
3587	pHlp->pfnPrintf(pHlp, "%0*llx error! Page directory pointer table at HCPhys=%#VHp was not found in the page pool!\n",
3588	fLongMode ? 16 : 8, u64Address, HCPhys);
3589	return VERR_INVALID_PARAMETER;
3590	}
3591
3592	int rc = VINF_SUCCESS;
3593	const unsigned c = fLongMode ? RT_ELEMENTS(pPDPT->a) : X86_PG_PAE_PDPE_ENTRIES;
3594	for (unsigned i = 0; i < c; i++)
3595	{
3596	X86PDPE Pdpe = pPDPT->a[i];
3597	if (Pdpe.n.u1Present)
3598	{
3599	if (fLongMode)
3600	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a p ? /
3601	"%016llx 1 \| P %c %c %c %c %c %s %s %s %s .. %c%c%c %016llx\n",
3602	u64Address + ((uint64_t)i << X86_PDPT_SHIFT),
3603	Pdpe.lm.u1Write ? 'W' : 'R',
3604	Pdpe.lm.u1User ? 'U' : 'S',
3605	Pdpe.lm.u1Accessed ? 'A' : '-',
3606	Pdpe.lm.u3Reserved & 1? '?' : '.', /* ignored */
3607	Pdpe.lm.u3Reserved & 4? '!' : '.', /* mbz */
3608	Pdpe.lm.u1WriteThru ? "WT" : "--",
3609	Pdpe.lm.u1CacheDisable? "CD" : "--",
3610	Pdpe.lm.u3Reserved & 2? "!" : "..",/* mbz */
3611	Pdpe.lm.u1NoExecute ? "NX" : "--",
3612	Pdpe.u & RT_BIT(9) ? '1' : '0',
3613	Pdpe.u & PGM_PLXFLAGS_PERMANENT ? 'p' : '-',
3614	Pdpe.u & RT_BIT(11) ? '1' : '0',
3615	Pdpe.u & X86_PDPE_PG_MASK);
3616	else
3617	pHlp->pfnPrintf(pHlp, /P G WT CD AT NX 4M a p ? /
3618	"%08x 0 \| P %c %s %s %s %s .. %c%c%c %016llx\n",
3619	i << X86_PDPT_SHIFT,
3620	Pdpe.n.u4Reserved & 1? '!' : '.', /* mbz */
3621	Pdpe.n.u4Reserved & 4? '!' : '.', /* mbz */
3622	Pdpe.n.u1WriteThru ? "WT" : "--",
3623	Pdpe.n.u1CacheDisable? "CD" : "--",
3624	Pdpe.n.u4Reserved & 2? "!" : "..",/* mbz */
3625	Pdpe.u & RT_BIT(9) ? '1' : '0',
3626	Pdpe.u & PGM_PLXFLAGS_PERMANENT ? 'p' : '-',
3627	Pdpe.u & RT_BIT(11) ? '1' : '0',
3628	Pdpe.u & X86_PDPE_PG_MASK);
3629	if (cMaxDepth >= 1)
3630	{
3631	int rc2 = pgmR3DumpHierarchyHCPaePD(pVM, Pdpe.u & X86_PDPE_PG_MASK, u64Address + ((uint64_t)i << X86_PDPT_SHIFT),
3632	cr4, fLongMode, cMaxDepth - 1, pHlp);
3633	if (rc2 < rc && VBOX_SUCCESS(rc))
3634	rc = rc2;
3635	}
3636	}
3637	}
3638	return rc;
3639	}
3640
3641
3642	/**
3643	* Dumps a 32-bit shadow page table.
3644	*
3645	* @returns VBox status code (VINF_SUCCESS).
3646	* @param pVM The VM handle.
3647	* @param HCPhys The physical address of the table.
3648	* @param cr4 The CR4, PSE is currently used.
3649	* @param cMaxDepth The maxium depth.
3650	* @param pHlp Pointer to the output functions.
3651	*/
3652	static int pgmR3DumpHierarchyHcPaePML4(PVM pVM, RTHCPHYS HCPhys, uint32_t cr4, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
3653	{
3654	PX86PML4 pPML4 = (PX86PML4)MMPagePhys2Page(pVM, HCPhys);
3655	if (!pPML4)
3656	{
3657	pHlp->pfnPrintf(pHlp, "Page map level 4 at HCPhys=%#VHp was not found in the page pool!\n", HCPhys);
3658	return VERR_INVALID_PARAMETER;
3659	}
3660
3661	int rc = VINF_SUCCESS;
3662	for (unsigned i = 0; i < RT_ELEMENTS(pPML4->a); i++)
3663	{
3664	X86PML4E Pml4e = pPML4->a[i];
3665	if (Pml4e.n.u1Present)
3666	{
3667	uint64_t u64Address = ((uint64_t)i << X86_PML4_SHIFT) \| (((uint64_t)i >> (X86_PML4_SHIFT - X86_PDPT_SHIFT - 1)) * 0xffff000000000000ULL);
3668	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a p ? /
3669	"%016llx 0 \| P %c %c %c %c %c %s %s %s %s .. %c%c%c %016llx\n",
3670	u64Address,
3671	Pml4e.n.u1Write ? 'W' : 'R',
3672	Pml4e.n.u1User ? 'U' : 'S',
3673	Pml4e.n.u1Accessed ? 'A' : '-',
3674	Pml4e.n.u3Reserved & 1? '?' : '.', /* ignored */
3675	Pml4e.n.u3Reserved & 4? '!' : '.', /* mbz */
3676	Pml4e.n.u1WriteThru ? "WT" : "--",
3677	Pml4e.n.u1CacheDisable? "CD" : "--",
3678	Pml4e.n.u3Reserved & 2? "!" : "..",/* mbz */
3679	Pml4e.n.u1NoExecute ? "NX" : "--",
3680	Pml4e.u & RT_BIT(9) ? '1' : '0',
3681	Pml4e.u & PGM_PLXFLAGS_PERMANENT ? 'p' : '-',
3682	Pml4e.u & RT_BIT(11) ? '1' : '0',
3683	Pml4e.u & X86_PML4E_PG_MASK);
3684
3685	if (cMaxDepth >= 1)
3686	{
3687	int rc2 = pgmR3DumpHierarchyHCPaePDPT(pVM, Pml4e.u & X86_PML4E_PG_MASK, u64Address, cr4, true, cMaxDepth - 1, pHlp);
3688	if (rc2 < rc && VBOX_SUCCESS(rc))
3689	rc = rc2;
3690	}
3691	}
3692	}
3693	return rc;
3694	}
3695
3696
3697	/**
3698	* Dumps a 32-bit shadow page table.
3699	*
3700	* @returns VBox status code (VINF_SUCCESS).
3701	* @param pVM The VM handle.
3702	* @param pPT Pointer to the page table.
3703	* @param u32Address The virtual address this table starts at.
3704	* @param pHlp Pointer to the output functions.
3705	*/
3706	int pgmR3DumpHierarchyHC32BitPT(PVM pVM, PX86PT pPT, uint32_t u32Address, PCDBGFINFOHLP pHlp)
3707	{
3708	for (unsigned i = 0; i < RT_ELEMENTS(pPT->a); i++)
3709	{
3710	X86PTE Pte = pPT->a[i];
3711	if (Pte.n.u1Present)
3712	{
3713	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a m d /
3714	"%08x 1 \| P %c %c %c %c %c %s %s %s .. 4K %c%c%c %08x\n",
3715	u32Address + (i << X86_PT_SHIFT),
3716	Pte.n.u1Write ? 'W' : 'R',
3717	Pte.n.u1User ? 'U' : 'S',
3718	Pte.n.u1Accessed ? 'A' : '-',
3719	Pte.n.u1Dirty ? 'D' : '-',
3720	Pte.n.u1Global ? 'G' : '-',
3721	Pte.n.u1WriteThru ? "WT" : "--",
3722	Pte.n.u1CacheDisable? "CD" : "--",
3723	Pte.n.u1PAT ? "AT" : "--",
3724	Pte.u & PGM_PTFLAGS_TRACK_DIRTY ? 'd' : '-',
3725	Pte.u & RT_BIT(10) ? '1' : '0',
3726	Pte.u & PGM_PTFLAGS_CSAM_VALIDATED ? 'v' : '-',
3727	Pte.u & X86_PDE_PG_MASK);
3728	}
3729	}
3730	return VINF_SUCCESS;
3731	}
3732
3733
3734	/**
3735	* Dumps a 32-bit shadow page directory and page tables.
3736	*
3737	* @returns VBox status code (VINF_SUCCESS).
3738	* @param pVM The VM handle.
3739	* @param cr3 The root of the hierarchy.
3740	* @param cr4 The CR4, PSE is currently used.
3741	* @param cMaxDepth How deep into the hierarchy the dumper should go.
3742	* @param pHlp Pointer to the output functions.
3743	*/
3744	int pgmR3DumpHierarchyHC32BitPD(PVM pVM, uint32_t cr3, uint32_t cr4, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
3745	{
3746	PX86PD pPD = (PX86PD)MMPagePhys2Page(pVM, cr3 & X86_CR3_PAGE_MASK);
3747	if (!pPD)
3748	{
3749	pHlp->pfnPrintf(pHlp, "Page directory at %#x was not found in the page pool!\n", cr3 & X86_CR3_PAGE_MASK);
3750	return VERR_INVALID_PARAMETER;
3751	}
3752
3753	int rc = VINF_SUCCESS;
3754	for (unsigned i = 0; i < RT_ELEMENTS(pPD->a); i++)
3755	{
3756	X86PDE Pde = pPD->a[i];
3757	if (Pde.n.u1Present)
3758	{
3759	const uint32_t u32Address = i << X86_PD_SHIFT;
3760	if ((cr4 & X86_CR4_PSE) && Pde.b.u1Size)
3761	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a m d /
3762	"%08x 0 \| P %c %c %c %c %c %s %s %s .. 4M %c%c%c %08x\n",
3763	u32Address,
3764	Pde.b.u1Write ? 'W' : 'R',
3765	Pde.b.u1User ? 'U' : 'S',
3766	Pde.b.u1Accessed ? 'A' : '-',
3767	Pde.b.u1Dirty ? 'D' : '-',
3768	Pde.b.u1Global ? 'G' : '-',
3769	Pde.b.u1WriteThru ? "WT" : "--",
3770	Pde.b.u1CacheDisable? "CD" : "--",
3771	Pde.b.u1PAT ? "AT" : "--",
3772	Pde.u & RT_BIT_64(9) ? '1' : '0',
3773	Pde.u & PGM_PDFLAGS_MAPPING ? 'm' : '-',
3774	Pde.u & PGM_PDFLAGS_TRACK_DIRTY ? 'd' : '-',
3775	Pde.u & X86_PDE4M_PG_MASK);
3776	else
3777	{
3778	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a m d /
3779	"%08x 0 \| P %c %c %c %c %c %s %s .. .. 4K %c%c%c %08x\n",
3780	u32Address,
3781	Pde.n.u1Write ? 'W' : 'R',
3782	Pde.n.u1User ? 'U' : 'S',
3783	Pde.n.u1Accessed ? 'A' : '-',
3784	Pde.n.u1Reserved0 ? '?' : '.', /* ignored */
3785	Pde.n.u1Reserved1 ? '?' : '.', /* ignored */
3786	Pde.n.u1WriteThru ? "WT" : "--",
3787	Pde.n.u1CacheDisable? "CD" : "--",
3788	Pde.u & RT_BIT_64(9) ? '1' : '0',
3789	Pde.u & PGM_PDFLAGS_MAPPING ? 'm' : '-',
3790	Pde.u & PGM_PDFLAGS_TRACK_DIRTY ? 'd' : '-',
3791	Pde.u & X86_PDE_PG_MASK);
3792	if (cMaxDepth >= 1)
3793	{
3794	/** @todo what about using the page pool for mapping PTs? */
3795	RTHCPHYS HCPhys = Pde.u & X86_PDE_PG_MASK;
3796	PX86PT pPT = NULL;
3797	if (!(Pde.u & PGM_PDFLAGS_MAPPING))
3798	pPT = (PX86PT)MMPagePhys2Page(pVM, HCPhys);
3799	else
3800	{
3801	for (PPGMMAPPING pMap = pVM->pgm.s.pMappingsR3; pMap; pMap = pMap->pNextR3)
3802	if (u32Address - pMap->GCPtr < pMap->cb)
3803	{
3804	int iPDE = (u32Address - pMap->GCPtr) >> X86_PD_SHIFT;
3805	if (pMap->aPTs[iPDE].HCPhysPT != HCPhys)
3806	pHlp->pfnPrintf(pHlp, "%08x error! Mapping error! PT %d has HCPhysPT=%VHp not %VHp is in the PD.\n",
3807	u32Address, iPDE, pMap->aPTs[iPDE].HCPhysPT, HCPhys);
3808	pPT = pMap->aPTs[iPDE].pPTR3;
3809	}
3810	}
3811	int rc2 = VERR_INVALID_PARAMETER;
3812	if (pPT)
3813	rc2 = pgmR3DumpHierarchyHC32BitPT(pVM, pPT, u32Address, pHlp);
3814	else
3815	pHlp->pfnPrintf(pHlp, "%08x error! Page table at %#x was not found in the page pool!\n", u32Address, HCPhys);
3816	if (rc2 < rc && VBOX_SUCCESS(rc))
3817	rc = rc2;
3818	}
3819	}
3820	}
3821	}
3822
3823	return rc;
3824	}
3825
3826
3827	/**
3828	* Dumps a 32-bit shadow page table.
3829	*
3830	* @returns VBox status code (VINF_SUCCESS).
3831	* @param pVM The VM handle.
3832	* @param pPT Pointer to the page table.
3833	* @param u32Address The virtual address this table starts at.
3834	* @param PhysSearch Address to search for.
3835	*/
3836	int pgmR3DumpHierarchyGC32BitPT(PVM pVM, PX86PT pPT, uint32_t u32Address, RTGCPHYS PhysSearch)
3837	{
3838	for (unsigned i = 0; i < RT_ELEMENTS(pPT->a); i++)
3839	{
3840	X86PTE Pte = pPT->a[i];
3841	if (Pte.n.u1Present)
3842	{
3843	Log(( /P R S A D G WT CD AT NX 4M a m d /
3844	"%08x 1 \| P %c %c %c %c %c %s %s %s .. 4K %c%c%c %08x\n",
3845	u32Address + (i << X86_PT_SHIFT),
3846	Pte.n.u1Write ? 'W' : 'R',
3847	Pte.n.u1User ? 'U' : 'S',
3848	Pte.n.u1Accessed ? 'A' : '-',
3849	Pte.n.u1Dirty ? 'D' : '-',
3850	Pte.n.u1Global ? 'G' : '-',
3851	Pte.n.u1WriteThru ? "WT" : "--",
3852	Pte.n.u1CacheDisable? "CD" : "--",
3853	Pte.n.u1PAT ? "AT" : "--",
3854	Pte.u & PGM_PTFLAGS_TRACK_DIRTY ? 'd' : '-',
3855	Pte.u & RT_BIT(10) ? '1' : '0',
3856	Pte.u & PGM_PTFLAGS_CSAM_VALIDATED ? 'v' : '-',
3857	Pte.u & X86_PDE_PG_MASK));
3858
3859	if ((Pte.u & X86_PDE_PG_MASK) == PhysSearch)
3860	{
3861	uint64_t fPageShw = 0;
3862	RTHCPHYS pPhysHC = 0;
3863
3864	PGMShwGetPage(pVM, (RTGCPTR)(u32Address + (i << X86_PT_SHIFT)), &fPageShw, &pPhysHC);
3865	Log(("Found %VGp at %VGv -> flags=%llx\n", PhysSearch, (RTGCPTR)(u32Address + (i << X86_PT_SHIFT)), fPageShw));
3866	}
3867	}
3868	}
3869	return VINF_SUCCESS;
3870	}
3871
3872
3873	/**
3874	* Dumps a 32-bit guest page directory and page tables.
3875	*
3876	* @returns VBox status code (VINF_SUCCESS).
3877	* @param pVM The VM handle.
3878	* @param cr3 The root of the hierarchy.
3879	* @param cr4 The CR4, PSE is currently used.
3880	* @param PhysSearch Address to search for.
3881	*/
3882	VMMR3DECL(int) PGMR3DumpHierarchyGC(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCPHYS PhysSearch)
3883	{
3884	bool fLongMode = false;
3885	const unsigned cch = fLongMode ? 16 : 8; NOREF(cch);
3886	PX86PD pPD = 0;
3887
3888	int rc = PGM_GCPHYS_2_PTR(pVM, cr3 & X86_CR3_PAGE_MASK, &pPD);
3889	if (VBOX_FAILURE(rc) \|\| !pPD)
3890	{
3891	Log(("Page directory at %#x was not found in the page pool!\n", cr3 & X86_CR3_PAGE_MASK));
3892	return VERR_INVALID_PARAMETER;
3893	}
3894
3895	Log(("cr3=%08x cr4=%08x%s\n"
3896	"%-*s P - Present\n"
3897	"%-*s \| R/W - Read (0) / Write (1)\n"
3898	"%-*s \| \| U/S - User (1) / Supervisor (0)\n"
3899	"%-*s \| \| \| A - Accessed\n"
3900	"%-*s \| \| \| \| D - Dirty\n"
3901	"%-*s \| \| \| \| \| G - Global\n"
3902	"%-*s \| \| \| \| \| \| WT - Write thru\n"
3903	"%-*s \| \| \| \| \| \| \| CD - Cache disable\n"
3904	"%-*s \| \| \| \| \| \| \| \| AT - Attribute table (PAT)\n"
3905	"%-*s \| \| \| \| \| \| \| \| \| NX - No execute (K8)\n"
3906	"%-*s \| \| \| \| \| \| \| \| \| \| 4K/4M/2M - Page size.\n"
3907	"%-*s \| \| \| \| \| \| \| \| \| \| \| AVL - a=allocated; m=mapping; d=track dirty;\n"
3908	"%-*s \| \| \| \| \| \| \| \| \| \| \| \| p=permanent; v=validated;\n"
3909	"%-*s Level \| \| \| \| \| \| \| \| \| \| \| \| Page\n"
3910	/* xxxx n **** P R S A D G WT CD AT NX 4M AVL xxxxxxxxxxxxx
3911	- W U - - - -- -- -- -- -- 010 */
3912	, cr3, cr4, fLongMode ? " Long Mode" : "",
3913	cch, "", cch, "", cch, "", cch, "", cch, "", cch, "", cch, "",
3914	cch, "", cch, "", cch, "", cch, "", cch, "", cch, "", cch, "Address"));
3915
3916	for (unsigned i = 0; i < RT_ELEMENTS(pPD->a); i++)
3917	{
3918	X86PDE Pde = pPD->a[i];
3919	if (Pde.n.u1Present)
3920	{
3921	const uint32_t u32Address = i << X86_PD_SHIFT;
3922
3923	if ((cr4 & X86_CR4_PSE) && Pde.b.u1Size)
3924	Log(( /P R S A D G WT CD AT NX 4M a m d /
3925	"%08x 0 \| P %c %c %c %c %c %s %s %s .. 4M %c%c%c %08x\n",
3926	u32Address,
3927	Pde.b.u1Write ? 'W' : 'R',
3928	Pde.b.u1User ? 'U' : 'S',
3929	Pde.b.u1Accessed ? 'A' : '-',
3930	Pde.b.u1Dirty ? 'D' : '-',
3931	Pde.b.u1Global ? 'G' : '-',
3932	Pde.b.u1WriteThru ? "WT" : "--",
3933	Pde.b.u1CacheDisable? "CD" : "--",
3934	Pde.b.u1PAT ? "AT" : "--",
3935	Pde.u & RT_BIT(9) ? '1' : '0',
3936	Pde.u & RT_BIT(10) ? '1' : '0',
3937	Pde.u & RT_BIT(11) ? '1' : '0',
3938	pgmGstGet4MBPhysPage(&pVM->pgm.s, Pde)));
3939	/** @todo PhysSearch */
3940	else
3941	{
3942	Log(( /P R S A D G WT CD AT NX 4M a m d /
3943	"%08x 0 \| P %c %c %c %c %c %s %s .. .. 4K %c%c%c %08x\n",
3944	u32Address,
3945	Pde.n.u1Write ? 'W' : 'R',
3946	Pde.n.u1User ? 'U' : 'S',
3947	Pde.n.u1Accessed ? 'A' : '-',
3948	Pde.n.u1Reserved0 ? '?' : '.', /* ignored */
3949	Pde.n.u1Reserved1 ? '?' : '.', /* ignored */
3950	Pde.n.u1WriteThru ? "WT" : "--",
3951	Pde.n.u1CacheDisable? "CD" : "--",
3952	Pde.u & RT_BIT(9) ? '1' : '0',
3953	Pde.u & RT_BIT(10) ? '1' : '0',
3954	Pde.u & RT_BIT(11) ? '1' : '0',
3955	Pde.u & X86_PDE_PG_MASK));
3956	////if (cMaxDepth >= 1)
3957	{
3958	/** @todo what about using the page pool for mapping PTs? */
3959	RTGCPHYS GCPhys = Pde.u & X86_PDE_PG_MASK;
3960	PX86PT pPT = NULL;
3961
3962	rc = PGM_GCPHYS_2_PTR(pVM, GCPhys, &pPT);
3963
3964	int rc2 = VERR_INVALID_PARAMETER;
3965	if (pPT)
3966	rc2 = pgmR3DumpHierarchyGC32BitPT(pVM, pPT, u32Address, PhysSearch);
3967	else
3968	Log(("%08x error! Page table at %#x was not found in the page pool!\n", u32Address, GCPhys));
3969	if (rc2 < rc && VBOX_SUCCESS(rc))
3970	rc = rc2;
3971	}
3972	}
3973	}
3974	}
3975
3976	return rc;
3977	}
3978
3979
3980	/**
3981	* Dumps a page table hierarchy use only physical addresses and cr4/lm flags.
3982	*
3983	* @returns VBox status code (VINF_SUCCESS).
3984	* @param pVM The VM handle.
3985	* @param cr3 The root of the hierarchy.
3986	* @param cr4 The cr4, only PAE and PSE is currently used.
3987	* @param fLongMode Set if long mode, false if not long mode.
3988	* @param cMaxDepth Number of levels to dump.
3989	* @param pHlp Pointer to the output functions.
3990	*/
3991	VMMR3DECL(int) PGMR3DumpHierarchyHC(PVM pVM, uint64_t cr3, uint64_t cr4, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
3992	{
3993	if (!pHlp)
3994	pHlp = DBGFR3InfoLogHlp();
3995	if (!cMaxDepth)
3996	return VINF_SUCCESS;
3997	const unsigned cch = fLongMode ? 16 : 8;
3998	pHlp->pfnPrintf(pHlp,
3999	"cr3=%08x cr4=%08x%s\n"
4000	"%-*s P - Present\n"
4001	"%-*s \| R/W - Read (0) / Write (1)\n"
4002	"%-*s \| \| U/S - User (1) / Supervisor (0)\n"
4003	"%-*s \| \| \| A - Accessed\n"
4004	"%-*s \| \| \| \| D - Dirty\n"
4005	"%-*s \| \| \| \| \| G - Global\n"
4006	"%-*s \| \| \| \| \| \| WT - Write thru\n"
4007	"%-*s \| \| \| \| \| \| \| CD - Cache disable\n"
4008	"%-*s \| \| \| \| \| \| \| \| AT - Attribute table (PAT)\n"
4009	"%-*s \| \| \| \| \| \| \| \| \| NX - No execute (K8)\n"
4010	"%-*s \| \| \| \| \| \| \| \| \| \| 4K/4M/2M - Page size.\n"
4011	"%-*s \| \| \| \| \| \| \| \| \| \| \| AVL - a=allocated; m=mapping; d=track dirty;\n"
4012	"%-*s \| \| \| \| \| \| \| \| \| \| \| \| p=permanent; v=validated;\n"
4013	"%-*s Level \| \| \| \| \| \| \| \| \| \| \| \| Page\n"
4014	/* xxxx n **** P R S A D G WT CD AT NX 4M AVL xxxxxxxxxxxxx
4015	- W U - - - -- -- -- -- -- 010 */
4016	, cr3, cr4, fLongMode ? " Long Mode" : "",
4017	cch, "", cch, "", cch, "", cch, "", cch, "", cch, "", cch, "",
4018	cch, "", cch, "", cch, "", cch, "", cch, "", cch, "", cch, "Address");
4019	if (cr4 & X86_CR4_PAE)
4020	{
4021	if (fLongMode)
4022	return pgmR3DumpHierarchyHcPaePML4(pVM, cr3 & X86_CR3_PAGE_MASK, cr4, cMaxDepth, pHlp);
4023	return pgmR3DumpHierarchyHCPaePDPT(pVM, cr3 & X86_CR3_PAE_PAGE_MASK, 0, cr4, false, cMaxDepth, pHlp);
4024	}
4025	return pgmR3DumpHierarchyHC32BitPD(pVM, cr3 & X86_CR3_PAGE_MASK, cr4, cMaxDepth, pHlp);
4026	}
4027
4028
4029
4030	#ifdef VBOX_WITH_DEBUGGER
4031	/**
4032	* The '.pgmram' command.
4033	*
4034	* @returns VBox status.
4035	* @param pCmd Pointer to the command descriptor (as registered).
4036	* @param pCmdHlp Pointer to command helper functions.
4037	* @param pVM Pointer to the current VM (if any).
4038	* @param paArgs Pointer to (readonly) array of arguments.
4039	* @param cArgs Number of arguments in the array.
4040	*/
4041	static DECLCALLBACK(int) pgmR3CmdRam(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4042	{
4043	/*
4044	* Validate input.
4045	*/
4046	if (!pVM)
4047	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4048	if (!pVM->pgm.s.pRamRangesRC)
4049	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Sorry, no Ram is registered.\n");
4050
4051	/*
4052	* Dump the ranges.
4053	*/
4054	int rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL, "From - To (incl) pvHC\n");
4055	PPGMRAMRANGE pRam;
4056	for (pRam = pVM->pgm.s.pRamRangesR3; pRam; pRam = pRam->pNextR3)
4057	{
4058	rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL,
4059	"%RGp - %RGp %p\n",
4060	pRam->GCPhys, pRam->GCPhysLast, pRam->pvR3);
4061	if (VBOX_FAILURE(rc))
4062	return rc;
4063	}
4064
4065	return VINF_SUCCESS;
4066	}
4067
4068
4069	/**
4070	* The '.pgmmap' command.
4071	*
4072	* @returns VBox status.
4073	* @param pCmd Pointer to the command descriptor (as registered).
4074	* @param pCmdHlp Pointer to command helper functions.
4075	* @param pVM Pointer to the current VM (if any).
4076	* @param paArgs Pointer to (readonly) array of arguments.
4077	* @param cArgs Number of arguments in the array.
4078	*/
4079	static DECLCALLBACK(int) pgmR3CmdMap(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4080	{
4081	/*
4082	* Validate input.
4083	*/
4084	if (!pVM)
4085	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4086	if (!pVM->pgm.s.pMappingsR3)
4087	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Sorry, no mappings are registered.\n");
4088
4089	/*
4090	* Print message about the fixedness of the mappings.
4091	*/
4092	int rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL, pVM->pgm.s.fMappingsFixed ? "The mappings are FIXED.\n" : "The mappings are FLOATING.\n");
4093	if (VBOX_FAILURE(rc))
4094	return rc;
4095
4096	/*
4097	* Dump the ranges.
4098	*/
4099	PPGMMAPPING pCur;
4100	for (pCur = pVM->pgm.s.pMappingsR3; pCur; pCur = pCur->pNextR3)
4101	{
4102	rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL,
4103	"%08x - %08x %s\n",
4104	pCur->GCPtr, pCur->GCPtrLast, pCur->pszDesc);
4105	if (VBOX_FAILURE(rc))
4106	return rc;
4107	}
4108
4109	return VINF_SUCCESS;
4110	}
4111
4112
4113	/**
4114	* The '.pgmsync' command.
4115	*
4116	* @returns VBox status.
4117	* @param pCmd Pointer to the command descriptor (as registered).
4118	* @param pCmdHlp Pointer to command helper functions.
4119	* @param pVM Pointer to the current VM (if any).
4120	* @param paArgs Pointer to (readonly) array of arguments.
4121	* @param cArgs Number of arguments in the array.
4122	*/
4123	static DECLCALLBACK(int) pgmR3CmdSync(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4124	{
4125	/*
4126	* Validate input.
4127	*/
4128	if (!pVM)
4129	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4130
4131	/*
4132	* Force page directory sync.
4133	*/
4134	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
4135
4136	int rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Forcing page directory sync.\n");
4137	if (VBOX_FAILURE(rc))
4138	return rc;
4139
4140	return VINF_SUCCESS;
4141	}
4142
4143
4144	#ifdef VBOX_STRICT
4145	/**
4146	* The '.pgmassertcr3' command.
4147	*
4148	* @returns VBox status.
4149	* @param pCmd Pointer to the command descriptor (as registered).
4150	* @param pCmdHlp Pointer to command helper functions.
4151	* @param pVM Pointer to the current VM (if any).
4152	* @param paArgs Pointer to (readonly) array of arguments.
4153	* @param cArgs Number of arguments in the array.
4154	*/
4155	static DECLCALLBACK(int) pgmR3CmdAssertCR3(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4156	{
4157	/*
4158	* Validate input.
4159	*/
4160	if (!pVM)
4161	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4162
4163	int rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Checking shadow CR3 page tables for consistency.\n");
4164	if (VBOX_FAILURE(rc))
4165	return rc;
4166
4167	PGMAssertCR3(pVM, CPUMGetGuestCR3(pVM), CPUMGetGuestCR4(pVM));
4168
4169	return VINF_SUCCESS;
4170	}
4171	#endif
4172
4173	/**
4174	* The '.pgmsyncalways' command.
4175	*
4176	* @returns VBox status.
4177	* @param pCmd Pointer to the command descriptor (as registered).
4178	* @param pCmdHlp Pointer to command helper functions.
4179	* @param pVM Pointer to the current VM (if any).
4180	* @param paArgs Pointer to (readonly) array of arguments.
4181	* @param cArgs Number of arguments in the array.
4182	*/
4183	static DECLCALLBACK(int) pgmR3CmdSyncAlways(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4184	{
4185	/*
4186	* Validate input.
4187	*/
4188	if (!pVM)
4189	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4190
4191	/*
4192	* Force page directory sync.
4193	*/
4194	if (pVM->pgm.s.fSyncFlags & PGM_SYNC_ALWAYS)
4195	{
4196	ASMAtomicAndU32(&pVM->pgm.s.fSyncFlags, ~PGM_SYNC_ALWAYS);
4197	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Disabled permanent forced page directory syncing.\n");
4198	}
4199	else
4200	{
4201	ASMAtomicOrU32(&pVM->pgm.s.fSyncFlags, PGM_SYNC_ALWAYS);
4202	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
4203	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Enabled permanent forced page directory syncing.\n");
4204	}
4205	}
4206
4207	#endif
4208
4209	/**
4210	* pvUser argument of the pgmR3CheckIntegrity*Node callbacks.
4211	*/
4212	typedef struct PGMCHECKINTARGS
4213	{
4214	bool fLeftToRight; /*< true: left-to-right; false: right-to-left. /
4215	PPGMPHYSHANDLER pPrevPhys;
4216	PPGMVIRTHANDLER pPrevVirt;
4217	PPGMPHYS2VIRTHANDLER pPrevPhys2Virt;
4218	PVM pVM;
4219	} PGMCHECKINTARGS, *PPGMCHECKINTARGS;
4220
4221	/**
4222	* Validate a node in the physical handler tree.
4223	*
4224	* @returns 0 on if ok, other wise 1.
4225	* @param pNode The handler node.
4226	* @param pvUser pVM.
4227	*/
4228	static DECLCALLBACK(int) pgmR3CheckIntegrityPhysHandlerNode(PAVLROGCPHYSNODECORE pNode, void *pvUser)
4229	{
4230	PPGMCHECKINTARGS pArgs = (PPGMCHECKINTARGS)pvUser;
4231	PPGMPHYSHANDLER pCur = (PPGMPHYSHANDLER)pNode;
4232	AssertReleaseReturn(!((uintptr_t)pCur & 7), 1);
4233	AssertReleaseMsg(pCur->Core.Key <= pCur->Core.KeyLast,("pCur=%p %VGp-%VGp %s\n", pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
4234	AssertReleaseMsg( !pArgs->pPrevPhys
4235	\|\| (pArgs->fLeftToRight ? pArgs->pPrevPhys->Core.KeyLast < pCur->Core.Key : pArgs->pPrevPhys->Core.KeyLast > pCur->Core.Key),
4236	("pPrevPhys=%p %VGp-%VGp %s\n"
4237	" pCur=%p %VGp-%VGp %s\n",
4238	pArgs->pPrevPhys, pArgs->pPrevPhys->Core.Key, pArgs->pPrevPhys->Core.KeyLast, pArgs->pPrevPhys->pszDesc,
4239	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
4240	pArgs->pPrevPhys = pCur;
4241	return 0;
4242	}
4243
4244
4245	/**
4246	* Validate a node in the virtual handler tree.
4247	*
4248	* @returns 0 on if ok, other wise 1.
4249	* @param pNode The handler node.
4250	* @param pvUser pVM.
4251	*/
4252	static DECLCALLBACK(int) pgmR3CheckIntegrityVirtHandlerNode(PAVLROGCPTRNODECORE pNode, void *pvUser)
4253	{
4254	PPGMCHECKINTARGS pArgs = (PPGMCHECKINTARGS)pvUser;
4255	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)pNode;
4256	AssertReleaseReturn(!((uintptr_t)pCur & 7), 1);
4257	AssertReleaseMsg(pCur->Core.Key <= pCur->Core.KeyLast,("pCur=%p %VGv-%VGv %s\n", pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
4258	AssertReleaseMsg( !pArgs->pPrevVirt
4259	\|\| (pArgs->fLeftToRight ? pArgs->pPrevVirt->Core.KeyLast < pCur->Core.Key : pArgs->pPrevVirt->Core.KeyLast > pCur->Core.Key),
4260	("pPrevVirt=%p %VGv-%VGv %s\n"
4261	" pCur=%p %VGv-%VGv %s\n",
4262	pArgs->pPrevVirt, pArgs->pPrevVirt->Core.Key, pArgs->pPrevVirt->Core.KeyLast, pArgs->pPrevVirt->pszDesc,
4263	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
4264	for (unsigned iPage = 0; iPage < pCur->cPages; iPage++)
4265	{
4266	AssertReleaseMsg(pCur->aPhysToVirt[iPage].offVirtHandler == -RT_OFFSETOF(PGMVIRTHANDLER, aPhysToVirt[iPage]),
4267	("pCur=%p %VGv-%VGv %s\n"
4268	"iPage=%d offVirtHandle=%#x expected %#x\n",
4269	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc,
4270	iPage, pCur->aPhysToVirt[iPage].offVirtHandler, -RT_OFFSETOF(PGMVIRTHANDLER, aPhysToVirt[iPage])));
4271	}
4272	pArgs->pPrevVirt = pCur;
4273	return 0;
4274	}
4275
4276
4277	/**
4278	* Validate a node in the virtual handler tree.
4279	*
4280	* @returns 0 on if ok, other wise 1.
4281	* @param pNode The handler node.
4282	* @param pvUser pVM.
4283	*/
4284	static DECLCALLBACK(int) pgmR3CheckIntegrityPhysToVirtHandlerNode(PAVLROGCPHYSNODECORE pNode, void *pvUser)
4285	{
4286	PPGMCHECKINTARGS pArgs = (PPGMCHECKINTARGS)pvUser;
4287	PPGMPHYS2VIRTHANDLER pCur = (PPGMPHYS2VIRTHANDLER)pNode;
4288	AssertReleaseMsgReturn(!((uintptr_t)pCur & 3), ("\n"), 1);
4289	AssertReleaseMsgReturn(!(pCur->offVirtHandler & 3), ("\n"), 1);
4290	AssertReleaseMsg(pCur->Core.Key <= pCur->Core.KeyLast,("pCur=%p %VGp-%VGp\n", pCur, pCur->Core.Key, pCur->Core.KeyLast));
4291	AssertReleaseMsg( !pArgs->pPrevPhys2Virt
4292	\|\| (pArgs->fLeftToRight ? pArgs->pPrevPhys2Virt->Core.KeyLast < pCur->Core.Key : pArgs->pPrevPhys2Virt->Core.KeyLast > pCur->Core.Key),
4293	("pPrevPhys2Virt=%p %VGp-%VGp\n"
4294	" pCur=%p %VGp-%VGp\n",
4295	pArgs->pPrevPhys2Virt, pArgs->pPrevPhys2Virt->Core.Key, pArgs->pPrevPhys2Virt->Core.KeyLast,
4296	pCur, pCur->Core.Key, pCur->Core.KeyLast));
4297	AssertReleaseMsg( !pArgs->pPrevPhys2Virt
4298	\|\| (pArgs->fLeftToRight ? pArgs->pPrevPhys2Virt->Core.KeyLast < pCur->Core.Key : pArgs->pPrevPhys2Virt->Core.KeyLast > pCur->Core.Key),
4299	("pPrevPhys2Virt=%p %VGp-%VGp\n"
4300	" pCur=%p %VGp-%VGp\n",
4301	pArgs->pPrevPhys2Virt, pArgs->pPrevPhys2Virt->Core.Key, pArgs->pPrevPhys2Virt->Core.KeyLast,
4302	pCur, pCur->Core.Key, pCur->Core.KeyLast));
4303	AssertReleaseMsg((pCur->offNextAlias & (PGMPHYS2VIRTHANDLER_IN_TREE \| PGMPHYS2VIRTHANDLER_IS_HEAD)) == (PGMPHYS2VIRTHANDLER_IN_TREE \| PGMPHYS2VIRTHANDLER_IS_HEAD),
4304	("pCur=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4305	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias));
4306	if (pCur->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK)
4307	{
4308	PPGMPHYS2VIRTHANDLER pCur2 = pCur;
4309	for (;;)
4310	{
4311	pCur2 = (PPGMPHYS2VIRTHANDLER)((intptr_t)pCur + (pCur->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK));
4312	AssertReleaseMsg(pCur2 != pCur,
4313	(" pCur=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4314	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias));
4315	AssertReleaseMsg((pCur2->offNextAlias & (PGMPHYS2VIRTHANDLER_IN_TREE \| PGMPHYS2VIRTHANDLER_IS_HEAD)) == PGMPHYS2VIRTHANDLER_IN_TREE,
4316	(" pCur=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
4317	"pCur2=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4318	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias,
4319	pCur2, pCur2->Core.Key, pCur2->Core.KeyLast, pCur2->offVirtHandler, pCur2->offNextAlias));
4320	AssertReleaseMsg((pCur2->Core.Key ^ pCur->Core.Key) < PAGE_SIZE,
4321	(" pCur=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
4322	"pCur2=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4323	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias,
4324	pCur2, pCur2->Core.Key, pCur2->Core.KeyLast, pCur2->offVirtHandler, pCur2->offNextAlias));
4325	AssertReleaseMsg((pCur2->Core.KeyLast ^ pCur->Core.KeyLast) < PAGE_SIZE,
4326	(" pCur=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
4327	"pCur2=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4328	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias,
4329	pCur2, pCur2->Core.Key, pCur2->Core.KeyLast, pCur2->offVirtHandler, pCur2->offNextAlias));
4330	if (!(pCur2->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK))
4331	break;
4332	}
4333	}
4334
4335	pArgs->pPrevPhys2Virt = pCur;
4336	return 0;
4337	}
4338
4339
4340	/**
4341	* Perform an integrity check on the PGM component.
4342	*
4343	* @returns VINF_SUCCESS if everything is fine.
4344	* @returns VBox error status after asserting on integrity breach.
4345	* @param pVM The VM handle.
4346	*/
4347	VMMR3DECL(int) PGMR3CheckIntegrity(PVM pVM)
4348	{
4349	AssertReleaseReturn(pVM->pgm.s.offVM, VERR_INTERNAL_ERROR);
4350
4351	/*
4352	* Check the trees.
4353	*/
4354	int cErrors = 0;
4355	const static PGMCHECKINTARGS s_LeftToRight = { true, NULL, NULL, NULL, pVM };
4356	const static PGMCHECKINTARGS s_RightToLeft = { false, NULL, NULL, NULL, pVM };
4357	PGMCHECKINTARGS Args = s_LeftToRight;
4358	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesHC->PhysHandlers, true, pgmR3CheckIntegrityPhysHandlerNode, &Args);
4359	Args = s_RightToLeft;
4360	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesHC->PhysHandlers, false, pgmR3CheckIntegrityPhysHandlerNode, &Args);
4361	Args = s_LeftToRight;
4362	cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesHC->VirtHandlers, true, pgmR3CheckIntegrityVirtHandlerNode, &Args);
4363	Args = s_RightToLeft;
4364	cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesHC->VirtHandlers, false, pgmR3CheckIntegrityVirtHandlerNode, &Args);
4365	Args = s_LeftToRight;
4366	cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesHC->HyperVirtHandlers, true, pgmR3CheckIntegrityVirtHandlerNode, &Args);
4367	Args = s_RightToLeft;
4368	cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesHC->HyperVirtHandlers, false, pgmR3CheckIntegrityVirtHandlerNode, &Args);
4369	Args = s_LeftToRight;
4370	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesHC->PhysToVirtHandlers, true, pgmR3CheckIntegrityPhysToVirtHandlerNode, &Args);
4371	Args = s_RightToLeft;
4372	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesHC->PhysToVirtHandlers, false, pgmR3CheckIntegrityPhysToVirtHandlerNode, &Args);
4373
4374	return !cErrors ? VINF_SUCCESS : VERR_INTERNAL_ERROR;
4375	}
4376
4377
4378	/**
4379	* Inform PGM if we want all mappings to be put into the shadow page table. (necessary for e.g. VMX)
4380	*
4381	* @returns VBox status code.
4382	* @param pVM VM handle.
4383	* @param fEnable Enable or disable shadow mappings
4384	*/
4385	VMMR3DECL(int) PGMR3ChangeShwPDMappings(PVM pVM, bool fEnable)
4386	{
4387	pVM->pgm.s.fDisableMappings = !fEnable;
4388
4389	uint32_t cb;
4390	int rc = PGMR3MappingsSize(pVM, &cb);
4391	AssertRCReturn(rc, rc);
4392
4393	/* Pretend the mappings are now fixed; to force a refresh of the reserved PDEs. */
4394	rc = PGMR3MappingsFix(pVM, MM_HYPER_AREA_ADDRESS, cb);
4395	AssertRCReturn(rc, rc);
4396
4397	return VINF_SUCCESS;
4398	}

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source: vbox/trunk/src/VBox/VMM/PGM.cpp@ 13050

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