PGM.cpp@ 17049

Last change on this file since 17049 was 16918, checked in by vboxsync, 16 years ago
Backed out r43029
Property svn:eol-style set to `native` Property svn:keywords set to `Id`
File size: 219.0 KB

Line
1	/* $Id: PGM.cpp 16918 2009-02-18 15:58:38Z vboxsync $ */
2	/** @file
3	* PGM - Page Manager and Monitor. (Mixing stuff here, not good?)
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22
23	/** @page pg_pgm PGM - The Page Manager and Monitor
24	*
25	* @see grp_pgm,
26	* @ref pg_pgm_pool,
27	* @ref pg_pgm_phys.
28	*
29	*
30	* @section sec_pgm_modes Paging Modes
31	*
32	* There are three memory contexts: Host Context (HC), Guest Context (GC)
33	* and intermediate context. When talking about paging HC can also be refered to
34	* as "host paging", and GC refered to as "shadow paging".
35	*
36	* We define three basic paging modes: 32-bit, PAE and AMD64. The host paging mode
37	* is defined by the host operating system. The mode used in the shadow paging mode
38	* depends on the host paging mode and what the mode the guest is currently in. The
39	* following relation between the two is defined:
40	*
41	* @verbatim
42	Host > 32-bit \| PAE \| AMD64 \|
43	Guest \| \| \| \|
44	==v================================
45	32-bit 32-bit PAE PAE
46	-------\|--------\|--------\|--------\|
47	PAE PAE PAE PAE
48	-------\|--------\|--------\|--------\|
49	AMD64 AMD64 AMD64 AMD64
50	-------\|--------\|--------\|--------\| @endverbatim
51	*
52	* All configuration except those in the diagonal (upper left) are expected to
53	* require special effort from the switcher (i.e. a bit slower).
54	*
55	*
56	*
57	*
58	* @section sec_pgm_shw The Shadow Memory Context
59	*
60	*
61	* [..]
62	*
63	* Because of guest context mappings requires PDPT and PML4 entries to allow
64	* writing on AMD64, the two upper levels will have fixed flags whatever the
65	* guest is thinking of using there. So, when shadowing the PD level we will
66	* calculate the effective flags of PD and all the higher levels. In legacy
67	* PAE mode this only applies to the PWT and PCD bits (the rest are
68	* ignored/reserved/MBZ). We will ignore those bits for the present.
69	*
70	*
71	*
72	* @section sec_pgm_int The Intermediate Memory Context
73	*
74	* The world switch goes thru an intermediate memory context which purpose it is
75	* to provide different mappings of the switcher code. All guest mappings are also
76	* present in this context.
77	*
78	* The switcher code is mapped at the same location as on the host, at an
79	* identity mapped location (physical equals virtual address), and at the
80	* hypervisor location. The identity mapped location is for when the world
81	* switches that involves disabling paging.
82	*
83	* PGM maintain page tables for 32-bit, PAE and AMD64 paging modes. This
84	* simplifies switching guest CPU mode and consistency at the cost of more
85	* code to do the work. All memory use for those page tables is located below
86	* 4GB (this includes page tables for guest context mappings).
87	*
88	*
89	* @subsection subsec_pgm_int_gc Guest Context Mappings
90	*
91	* During assignment and relocation of a guest context mapping the intermediate
92	* memory context is used to verify the new location.
93	*
94	* Guest context mappings are currently restricted to below 4GB, for reasons
95	* of simplicity. This may change when we implement AMD64 support.
96	*
97	*
98	*
99	*
100	* @section sec_pgm_misc Misc
101	*
102	* @subsection subsec_pgm_misc_diff Differences Between Legacy PAE and Long Mode PAE
103	*
104	* The differences between legacy PAE and long mode PAE are:
105	* -# PDPE bits 1, 2, 5 and 6 are defined differently. In leagcy mode they are
106	* all marked down as must-be-zero, while in long mode 1, 2 and 5 have the
107	* usual meanings while 6 is ignored (AMD). This means that upon switching to
108	* legacy PAE mode we'll have to clear these bits and when going to long mode
109	* they must be set. This applies to both intermediate and shadow contexts,
110	* however we don't need to do it for the intermediate one since we're
111	* executing with CR0.WP at that time.
112	* -# CR3 allows a 32-byte aligned address in legacy mode, while in long mode
113	* a page aligned one is required.
114	*
115	*
116	* @section sec_pgm_handlers Access Handlers
117	*
118	* Placeholder.
119	*
120	*
121	* @subsection sec_pgm_handlers_virt Virtual Access Handlers
122	*
123	* Placeholder.
124	*
125	*
126	* @subsection sec_pgm_handlers_virt Virtual Access Handlers
127	*
128	* We currently implement three types of virtual access handlers: ALL, WRITE
129	* and HYPERVISOR (WRITE). See PGMVIRTHANDLERTYPE for some more details.
130	*
131	* The HYPERVISOR access handlers is kept in a separate tree since it doesn't apply
132	* to physical pages (PGMTREES::HyperVirtHandlers) and only needs to be consulted in
133	* a special \#PF case. The ALL and WRITE are in the PGMTREES::VirtHandlers tree, the
134	* rest of this section is going to be about these handlers.
135	*
136	* We'll go thru the life cycle of a handler and try make sense of it all, don't know
137	* how successfull this is gonna be...
138	*
139	* 1. A handler is registered thru the PGMR3HandlerVirtualRegister and
140	* PGMHandlerVirtualRegisterEx APIs. We check for conflicting virtual handlers
141	* and create a new node that is inserted into the AVL tree (range key). Then
142	* a full PGM resync is flagged (clear pool, sync cr3, update virtual bit of PGMPAGE).
143	*
144	* 2. The following PGMSyncCR3/SyncCR3 operation will first make invoke HandlerVirtualUpdate.
145	*
146	* 2a. HandlerVirtualUpdate will will lookup all the pages covered by virtual handlers
147	* via the current guest CR3 and update the physical page -> virtual handler
148	* translation. Needless to say, this doesn't exactly scale very well. If any changes
149	* are detected, it will flag a virtual bit update just like we did on registration.
150	* PGMPHYS pages with changes will have their virtual handler state reset to NONE.
151	*
152	* 2b. The virtual bit update process will iterate all the pages covered by all the
153	* virtual handlers and update the PGMPAGE virtual handler state to the max of all
154	* virtual handlers on that page.
155	*
156	* 2c. Back in SyncCR3 we will now flush the entire shadow page cache to make sure
157	* we don't miss any alias mappings of the monitored pages.
158	*
159	* 2d. SyncCR3 will then proceed with syncing the CR3 table.
160	*
161	* 3. \#PF(np,read) on a page in the range. This will cause it to be synced
162	* read-only and resumed if it's a WRITE handler. If it's an ALL handler we
163	* will call the handlers like in the next step. If the physical mapping has
164	* changed we will - some time in the future - perform a handler callback
165	* (optional) and update the physical -> virtual handler cache.
166	*
167	* 4. \#PF(,write) on a page in the range. This will cause the handler to
168	* be invoked.
169	*
170	* 5. The guest invalidates the page and changes the physical backing or
171	* unmaps it. This should cause the invalidation callback to be invoked
172	* (it might not yet be 100% perfect). Exactly what happens next... is
173	* this where we mess up and end up out of sync for a while?
174	*
175	* 6. The handler is deregistered by the client via PGMHandlerVirtualDeregister.
176	* We will then set all PGMPAGEs in the physical -> virtual handler cache for
177	* this handler to NONE and trigger a full PGM resync (basically the same
178	* as int step 1). Which means 2 is executed again.
179	*
180	*
181	* @subsubsection sub_sec_pgm_handler_virt_todo TODOs
182	*
183	* There is a bunch of things that needs to be done to make the virtual handlers
184	* work 100% correctly and work more efficiently.
185	*
186	* The first bit hasn't been implemented yet because it's going to slow the
187	* whole mess down even more, and besides it seems to be working reliably for
188	* our current uses. OTOH, some of the optimizations might end up more or less
189	* implementing the missing bits, so we'll see.
190	*
191	* On the optimization side, the first thing to do is to try avoid unnecessary
192	* cache flushing. Then try team up with the shadowing code to track changes
193	* in mappings by means of access to them (shadow in), updates to shadows pages,
194	* invlpg, and shadow PT discarding (perhaps).
195	*
196	* Some idea that have popped up for optimization for current and new features:
197	* - bitmap indicating where there are virtual handlers installed.
198	* (4KB => 220 pages, page 212 => covers 32-bit address space 1:1!)
199	* - Further optimize this by min/max (needs min/max avl getters).
200	* - Shadow page table entry bit (if any left)?
201	*
202	*/
203
204
205	/** @page pg_pgm_phys PGM Physical Guest Memory Management
206	*
207	*
208	* Objectives:
209	* - Guest RAM over-commitment using memory ballooning,
210	* zero pages and general page sharing.
211	* - Moving or mirroring a VM onto a different physical machine.
212	*
213	*
214	* @subsection subsec_pgmPhys_Definitions Definitions
215	*
216	* Allocation chunk - A RTR0MemObjAllocPhysNC object and the tracking
217	* machinery assoicated with it.
218	*
219	*
220	*
221	*
222	* @subsection subsec_pgmPhys_AllocPage Allocating a page.
223	*
224	* Initially we map all guest memory to the (per VM) zero page, which
225	* means that none of the read functions will cause pages to be allocated.
226	*
227	* Exception, access bit in page tables that have been shared. This must
228	* be handled, but we must also make sure PGMGst*Modify doesn't make
229	* unnecessary modifications.
230	*
231	* Allocation points:
232	* - PGMPhysSimpleWriteGCPhys and PGMPhysWrite.
233	* - Replacing a zero page mapping at \#PF.
234	* - Replacing a shared page mapping at \#PF.
235	* - ROM registration (currently MMR3RomRegister).
236	* - VM restore (pgmR3Load).
237	*
238	* For the first three it would make sense to keep a few pages handy
239	* until we've reached the max memory commitment for the VM.
240	*
241	* For the ROM registration, we know exactly how many pages we need
242	* and will request these from ring-0. For restore, we will save
243	* the number of non-zero pages in the saved state and allocate
244	* them up front. This would allow the ring-0 component to refuse
245	* the request if the isn't sufficient memory available for VM use.
246	*
247	* Btw. for both ROM and restore allocations we won't be requiring
248	* zeroed pages as they are going to be filled instantly.
249	*
250	*
251	* @subsection subsec_pgmPhys_FreePage Freeing a page
252	*
253	* There are a few points where a page can be freed:
254	* - After being replaced by the zero page.
255	* - After being replaced by a shared page.
256	* - After being ballooned by the guest additions.
257	* - At reset.
258	* - At restore.
259	*
260	* When freeing one or more pages they will be returned to the ring-0
261	* component and replaced by the zero page.
262	*
263	* The reasoning for clearing out all the pages on reset is that it will
264	* return us to the exact same state as on power on, and may thereby help
265	* us reduce the memory load on the system. Further it might have a
266	* (temporary) positive influence on memory fragmentation (@see subsec_pgmPhys_Fragmentation).
267	*
268	* On restore, as mention under the allocation topic, pages should be
269	* freed / allocated depending on how many is actually required by the
270	* new VM state. The simplest approach is to do like on reset, and free
271	* all non-ROM pages and then allocate what we need.
272	*
273	* A measure to prevent some fragmentation, would be to let each allocation
274	* chunk have some affinity towards the VM having allocated the most pages
275	* from it. Also, try make sure to allocate from allocation chunks that
276	* are almost full. Admittedly, both these measures might work counter to
277	* our intentions and its probably not worth putting a lot of effort,
278	* cpu time or memory into this.
279	*
280	*
281	* @subsection subsec_pgmPhys_SharePage Sharing a page
282	*
283	* The basic idea is that there there will be a idle priority kernel
284	* thread walking the non-shared VM pages hashing them and looking for
285	* pages with the same checksum. If such pages are found, it will compare
286	* them byte-by-byte to see if they actually are identical. If found to be
287	* identical it will allocate a shared page, copy the content, check that
288	* the page didn't change while doing this, and finally request both the
289	* VMs to use the shared page instead. If the page is all zeros (special
290	* checksum and byte-by-byte check) it will request the VM that owns it
291	* to replace it with the zero page.
292	*
293	* To make this efficient, we will have to make sure not to try share a page
294	* that will change its contents soon. This part requires the most work.
295	* A simple idea would be to request the VM to write monitor the page for
296	* a while to make sure it isn't modified any time soon. Also, it may
297	* make sense to skip pages that are being write monitored since this
298	* information is readily available to the thread if it works on the
299	* per-VM guest memory structures (presently called PGMRAMRANGE).
300	*
301	*
302	* @subsection subsec_pgmPhys_Fragmentation Fragmentation Concerns and Counter Measures
303	*
304	* The pages are organized in allocation chunks in ring-0, this is a necessity
305	* if we wish to have an OS agnostic approach to this whole thing. (On Linux we
306	* could easily work on a page-by-page basis if we liked. Whether this is possible
307	* or efficient on NT I don't quite know.) Fragmentation within these chunks may
308	* become a problem as part of the idea here is that we wish to return memory to
309	* the host system.
310	*
311	* For instance, starting two VMs at the same time, they will both allocate the
312	* guest memory on-demand and if permitted their page allocations will be
313	* intermixed. Shut down one of the two VMs and it will be difficult to return
314	* any memory to the host system because the page allocation for the two VMs are
315	* mixed up in the same allocation chunks.
316	*
317	* To further complicate matters, when pages are freed because they have been
318	* ballooned or become shared/zero the whole idea is that the page is supposed
319	* to be reused by another VM or returned to the host system. This will cause
320	* allocation chunks to contain pages belonging to different VMs and prevent
321	* returning memory to the host when one of those VM shuts down.
322	*
323	* The only way to really deal with this problem is to move pages. This can
324	* either be done at VM shutdown and or by the idle priority worker thread
325	* that will be responsible for finding sharable/zero pages. The mechanisms
326	* involved for coercing a VM to move a page (or to do it for it) will be
327	* the same as when telling it to share/zero a page.
328	*
329	*
330	* @subsection subsec_pgmPhys_Tracking Tracking Structures And Their Cost
331	*
332	* There's a difficult balance between keeping the per-page tracking structures
333	* (global and guest page) easy to use and keeping them from eating too much
334	* memory. We have limited virtual memory resources available when operating in
335	* 32-bit kernel space (on 64-bit there'll it's quite a different story). The
336	* tracking structures will be attemted designed such that we can deal with up
337	* to 32GB of memory on a 32-bit system and essentially unlimited on 64-bit ones.
338	*
339	*
340	* @subsubsection subsubsec_pgmPhys_Tracking_Kernel Kernel Space
341	*
342	* @see pg_GMM
343	*
344	* @subsubsection subsubsec_pgmPhys_Tracking_PerVM Per-VM
345	*
346	* Fixed info is the physical address of the page (HCPhys) and the page id
347	* (described above). Theoretically we'll need 48(-12) bits for the HCPhys part.
348	* Today we've restricting ourselves to 40(-12) bits because this is the current
349	* restrictions of all AMD64 implementations (I think Barcelona will up this
350	* to 48(-12) bits, not that it really matters) and I needed the bits for
351	* tracking mappings of a page. 48-12 = 36. That leaves 28 bits, which means a
352	* decent range for the page id: 2^(28+12) = 1024TB.
353	*
354	* In additions to these, we'll have to keep maintaining the page flags as we
355	* currently do. Although it wouldn't harm to optimize these quite a bit, like
356	* for instance the ROM shouldn't depend on having a write handler installed
357	* in order for it to become read-only. A RO/RW bit should be considered so
358	* that the page syncing code doesn't have to mess about checking multiple
359	* flag combinations (ROM \|\| RW handler \|\| write monitored) in order to
360	* figure out how to setup a shadow PTE. But this of course, is second
361	* priority at present. Current this requires 12 bits, but could probably
362	* be optimized to ~8.
363	*
364	* Then there's the 24 bits used to track which shadow page tables are
365	* currently mapping a page for the purpose of speeding up physical
366	* access handlers, and thereby the page pool cache. More bit for this
367	* purpose wouldn't hurt IIRC.
368	*
369	* Then there is a new bit in which we need to record what kind of page
370	* this is, shared, zero, normal or write-monitored-normal. This'll
371	* require 2 bits. One bit might be needed for indicating whether a
372	* write monitored page has been written to. And yet another one or
373	* two for tracking migration status. 3-4 bits total then.
374	*
375	* Whatever is left will can be used to record the sharabilitiy of a
376	* page. The page checksum will not be stored in the per-VM table as
377	* the idle thread will not be permitted to do modifications to it.
378	* It will instead have to keep its own working set of potentially
379	* shareable pages and their check sums and stuff.
380	*
381	* For the present we'll keep the current packing of the
382	* PGMRAMRANGE::aHCPhys to keep the changes simple, only of course,
383	* we'll have to change it to a struct with a total of 128-bits at
384	* our disposal.
385	*
386	* The initial layout will be like this:
387	* @verbatim
388	RTHCPHYS HCPhys; The current stuff.
389	63:40 Current shadow PT tracking stuff.
390	39:12 The physical page frame number.
391	11:0 The current flags.
392	uint32_t u28PageId : 28; The page id.
393	uint32_t u2State : 2; The page state { zero, shared, normal, write monitored }.
394	uint32_t fWrittenTo : 1; Whether a write monitored page was written to.
395	uint32_t u1Reserved : 1; Reserved for later.
396	uint32_t u32Reserved; Reserved for later, mostly sharing stats.
397	@endverbatim
398	*
399	* The final layout will be something like this:
400	* @verbatim
401	RTHCPHYS HCPhys; The current stuff.
402	63:48 High page id (12+).
403	47:12 The physical page frame number.
404	11:0 Low page id.
405	uint32_t fReadOnly : 1; Whether it's readonly page (rom or monitored in some way).
406	uint32_t u3Type : 3; The page type {RESERVED, MMIO, MMIO2, ROM, shadowed ROM, RAM}.
407	uint32_t u2PhysMon : 2; Physical access handler type {none, read, write, all}.
408	uint32_t u2VirtMon : 2; Virtual access handler type {none, read, write, all}..
409	uint32_t u2State : 2; The page state { zero, shared, normal, write monitored }.
410	uint32_t fWrittenTo : 1; Whether a write monitored page was written to.
411	uint32_t u20Reserved : 20; Reserved for later, mostly sharing stats.
412	uint32_t u32Tracking; The shadow PT tracking stuff, roughly.
413	@endverbatim
414	*
415	* Cost wise, this means we'll double the cost for guest memory. There isn't anyway
416	* around that I'm afraid. It means that the cost of dealing out 32GB of memory
417	* to one or more VMs is: (32GB >> PAGE_SHIFT) * 16 bytes, or 128MBs. Or another
418	* example, the VM heap cost when assigning 1GB to a VM will be: 4MB.
419	*
420	* A couple of cost examples for the total cost per-VM + kernel.
421	* 32-bit Windows and 32-bit linux:
422	* 1GB guest ram, 256K pages: 4MB + 2MB(+) = 6MB
423	* 4GB guest ram, 1M pages: 16MB + 8MB(+) = 24MB
424	* 32GB guest ram, 8M pages: 128MB + 64MB(+) = 192MB
425	* 64-bit Windows and 64-bit linux:
426	* 1GB guest ram, 256K pages: 4MB + 3MB(+) = 7MB
427	* 4GB guest ram, 1M pages: 16MB + 12MB(+) = 28MB
428	* 32GB guest ram, 8M pages: 128MB + 96MB(+) = 224MB
429	*
430	* UPDATE - 2007-09-27:
431	* Will need a ballooned flag/state too because we cannot
432	* trust the guest 100% and reporting the same page as ballooned more
433	* than once will put the GMM off balance.
434	*
435	*
436	* @subsection subsec_pgmPhys_Serializing Serializing Access
437	*
438	* Initially, we'll try a simple scheme:
439	*
440	* - The per-VM RAM tracking structures (PGMRAMRANGE) is only modified
441	* by the EMT thread of that VM while in the pgm critsect.
442	* - Other threads in the VM process that needs to make reliable use of
443	* the per-VM RAM tracking structures will enter the critsect.
444	* - No process external thread or kernel thread will ever try enter
445	* the pgm critical section, as that just won't work.
446	* - The idle thread (and similar threads) doesn't not need 100% reliable
447	* data when performing it tasks as the EMT thread will be the one to
448	* do the actual changes later anyway. So, as long as it only accesses
449	* the main ram range, it can do so by somehow preventing the VM from
450	* being destroyed while it works on it...
451	*
452	* - The over-commitment management, including the allocating/freeing
453	* chunks, is serialized by a ring-0 mutex lock (a fast one since the
454	* more mundane mutex implementation is broken on Linux).
455	* - A separeate mutex is protecting the set of allocation chunks so
456	* that pages can be shared or/and freed up while some other VM is
457	* allocating more chunks. This mutex can be take from under the other
458	* one, but not the otherway around.
459	*
460	*
461	* @subsection subsec_pgmPhys_Request VM Request interface
462	*
463	* When in ring-0 it will become necessary to send requests to a VM so it can
464	* for instance move a page while defragmenting during VM destroy. The idle
465	* thread will make use of this interface to request VMs to setup shared
466	* pages and to perform write monitoring of pages.
467	*
468	* I would propose an interface similar to the current VMReq interface, similar
469	* in that it doesn't require locking and that the one sending the request may
470	* wait for completion if it wishes to. This shouldn't be very difficult to
471	* realize.
472	*
473	* The requests themselves are also pretty simple. They are basically:
474	* -# Check that some precondition is still true.
475	* -# Do the update.
476	* -# Update all shadow page tables involved with the page.
477	*
478	* The 3rd step is identical to what we're already doing when updating a
479	* physical handler, see pgmHandlerPhysicalSetRamFlagsAndFlushShadowPTs.
480	*
481	*
482	*
483	* @section sec_pgmPhys_MappingCaches Mapping Caches
484	*
485	* In order to be able to map in and out memory and to be able to support
486	* guest with more RAM than we've got virtual address space, we'll employing
487	* a mapping cache. There is already a tiny one for GC (see PGMGCDynMapGCPageEx)
488	* and we'll create a similar one for ring-0 unless we decide to setup a dedicate
489	* memory context for the HWACCM execution.
490	*
491	*
492	* @subsection subsec_pgmPhys_MappingCaches_R3 Ring-3
493	*
494	* We've considered implementing the ring-3 mapping cache page based but found
495	* that this was bother some when one had to take into account TLBs+SMP and
496	* portability (missing the necessary APIs on several platforms). There were
497	* also some performance concerns with this approach which hadn't quite been
498	* worked out.
499	*
500	* Instead, we'll be mapping allocation chunks into the VM process. This simplifies
501	* matters greatly quite a bit since we don't need to invent any new ring-0 stuff,
502	* only some minor RTR0MEMOBJ mapping stuff. The main concern here is that mapping
503	* compared to the previous idea is that mapping or unmapping a 1MB chunk is more
504	* costly than a single page, although how much more costly is uncertain. We'll
505	* try address this by using a very big cache, preferably bigger than the actual
506	* VM RAM size if possible. The current VM RAM sizes should give some idea for
507	* 32-bit boxes, while on 64-bit we can probably get away with employing an
508	* unlimited cache.
509	*
510	* The cache have to parts, as already indicated, the ring-3 side and the
511	* ring-0 side.
512	*
513	* The ring-0 will be tied to the page allocator since it will operate on the
514	* memory objects it contains. It will therefore require the first ring-0 mutex
515	* discussed in @ref subsec_pgmPhys_Serializing. We
516	* some double house keeping wrt to who has mapped what I think, since both
517	* VMMR0.r0 and RTR0MemObj will keep track of mapping relataions
518	*
519	* The ring-3 part will be protected by the pgm critsect. For simplicity, we'll
520	* require anyone that desires to do changes to the mapping cache to do that
521	* from within this critsect. Alternatively, we could employ a separate critsect
522	* for serializing changes to the mapping cache as this would reduce potential
523	* contention with other threads accessing mappings unrelated to the changes
524	* that are in process. We can see about this later, contention will show
525	* up in the statistics anyway, so it'll be simple to tell.
526	*
527	* The organization of the ring-3 part will be very much like how the allocation
528	* chunks are organized in ring-0, that is in an AVL tree by chunk id. To avoid
529	* having to walk the tree all the time, we'll have a couple of lookaside entries
530	* like in we do for I/O ports and MMIO in IOM.
531	*
532	* The simplified flow of a PGMPhysRead/Write function:
533	* -# Enter the PGM critsect.
534	* -# Lookup GCPhys in the ram ranges and get the Page ID.
535	* -# Calc the Allocation Chunk ID from the Page ID.
536	* -# Check the lookaside entries and then the AVL tree for the Chunk ID.
537	* If not found in cache:
538	* -# Call ring-0 and request it to be mapped and supply
539	* a chunk to be unmapped if the cache is maxed out already.
540	* -# Insert the new mapping into the AVL tree (id + R3 address).
541	* -# Update the relevant lookaside entry and return the mapping address.
542	* -# Do the read/write according to monitoring flags and everything.
543	* -# Leave the critsect.
544	*
545	*
546	* @section sec_pgmPhys_Fallback Fallback
547	*
548	* Current all the "second tier" hosts will not support the RTR0MemObjAllocPhysNC
549	* API and thus require a fallback.
550	*
551	* So, when RTR0MemObjAllocPhysNC returns VERR_NOT_SUPPORTED the page allocator
552	* will return to the ring-3 caller (and later ring-0) and asking it to seed
553	* the page allocator with some fresh pages (VERR_GMM_SEED_ME). Ring-3 will
554	* then perform an SUPPageAlloc(cbChunk >> PAGE_SHIFT) call and make a
555	* "SeededAllocPages" call to ring-0.
556	*
557	* The first time ring-0 sees the VERR_NOT_SUPPORTED failure it will disable
558	* all page sharing (zero page detection will continue). It will also force
559	* all allocations to come from the VM which seeded the page. Both these
560	* measures are taken to make sure that there will never be any need for
561	* mapping anything into ring-3 - everything will be mapped already.
562	*
563	* Whether we'll continue to use the current MM locked memory management
564	* for this I don't quite know (I'd prefer not to and just ditch that all
565	* togther), we'll see what's simplest to do.
566	*
567	*
568	*
569	* @section sec_pgmPhys_Changes Changes
570	*
571	* Breakdown of the changes involved?
572	*/
573
574
575	/** Saved state data unit version. */
576	#define PGM_SAVED_STATE_VERSION 6
577
578	/*******************************************************************************
579	* Header Files *
580	*******************************************************************************/
581	#define LOG_GROUP LOG_GROUP_PGM
582	#include <VBox/dbgf.h>
583	#include <VBox/pgm.h>
584	#include <VBox/cpum.h>
585	#include <VBox/iom.h>
586	#include <VBox/sup.h>
587	#include <VBox/mm.h>
588	#include <VBox/em.h>
589	#include <VBox/stam.h>
590	#include <VBox/rem.h>
591	#include <VBox/dbgf.h>
592	#include <VBox/rem.h>
593	#include <VBox/selm.h>
594	#include <VBox/ssm.h>
595	#include "PGMInternal.h"
596	#include <VBox/vm.h>
597	#include <VBox/dbg.h>
598	#include <VBox/hwaccm.h>
599
600	#include <iprt/assert.h>
601	#include <iprt/alloc.h>
602	#include <iprt/asm.h>
603	#include <iprt/thread.h>
604	#include <iprt/string.h>
605	#ifdef DEBUG_bird
606	# include <iprt/env.h>
607	#endif
608	#include <VBox/param.h>
609	#include <VBox/err.h>
610
611
612
613	/*******************************************************************************
614	* Internal Functions *
615	*******************************************************************************/
616	static int pgmR3InitPaging(PVM pVM);
617	static DECLCALLBACK(void) pgmR3PhysInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
618	static DECLCALLBACK(void) pgmR3InfoMode(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
619	static DECLCALLBACK(void) pgmR3InfoCr3(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
620	static DECLCALLBACK(int) pgmR3RelocatePhysHandler(PAVLROGCPHYSNODECORE pNode, void *pvUser);
621	static DECLCALLBACK(int) pgmR3RelocateVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser);
622	static DECLCALLBACK(int) pgmR3RelocateHyperVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser);
623	#ifdef VBOX_STRICT
624	static DECLCALLBACK(void) pgmR3ResetNoMorePhysWritesFlag(PVM pVM, VMSTATE enmState, VMSTATE enmOldState, void *pvUser);
625	#endif
626	static DECLCALLBACK(int) pgmR3Save(PVM pVM, PSSMHANDLE pSSM);
627	static DECLCALLBACK(int) pgmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version);
628	static int pgmR3ModeDataInit(PVM pVM, bool fResolveGCAndR0);
629	static void pgmR3ModeDataSwitch(PVM pVM, PGMMODE enmShw, PGMMODE enmGst);
630	static PGMMODE pgmR3CalcShadowMode(PVM pVM, PGMMODE enmGuestMode, SUPPAGINGMODE enmHostMode, PGMMODE enmShadowMode, VMMSWITCHER *penmSwitcher);
631
632	#ifdef VBOX_WITH_STATISTICS
633	static void pgmR3InitStats(PVM pVM);
634	#endif
635
636	#ifdef VBOX_WITH_DEBUGGER
637	/** @todo all but the two last commands must be converted to 'info'. */
638	static DECLCALLBACK(int) pgmR3CmdRam(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
639	static DECLCALLBACK(int) pgmR3CmdMap(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
640	static DECLCALLBACK(int) pgmR3CmdSync(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
641	static DECLCALLBACK(int) pgmR3CmdSyncAlways(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
642	# ifdef VBOX_STRICT
643	static DECLCALLBACK(int) pgmR3CmdAssertCR3(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
644	# endif
645	#endif
646
647
648	/*******************************************************************************
649	* Global Variables *
650	*******************************************************************************/
651	#ifdef VBOX_WITH_DEBUGGER
652	/** Command descriptors. */
653	static const DBGCCMD g_aCmds[] =
654	{
655	/* pszCmd, cArgsMin, cArgsMax, paArgDesc, cArgDescs, pResultDesc, fFlags, pfnHandler pszSyntax, ....pszDescription */
656	{ "pgmram", 0, 0, NULL, 0, NULL, 0, pgmR3CmdRam, "", "Display the ram ranges." },
657	{ "pgmmap", 0, 0, NULL, 0, NULL, 0, pgmR3CmdMap, "", "Display the mapping ranges." },
658	{ "pgmsync", 0, 0, NULL, 0, NULL, 0, pgmR3CmdSync, "", "Sync the CR3 page." },
659	#ifdef VBOX_STRICT
660	{ "pgmassertcr3", 0, 0, NULL, 0, NULL, 0, pgmR3CmdAssertCR3, "", "Check the shadow CR3 mapping." },
661	#endif
662	{ "pgmsyncalways", 0, 0, NULL, 0, NULL, 0, pgmR3CmdSyncAlways, "", "Toggle permanent CR3 syncing." },
663	};
664	#endif
665
666
667
668
669	/*
670	* Shadow - 32-bit mode
671	*/
672	#define PGM_SHW_TYPE PGM_TYPE_32BIT
673	#define PGM_SHW_NAME(name) PGM_SHW_NAME_32BIT(name)
674	#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_32BIT_STR(name)
675	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_32BIT_STR(name)
676	#include "PGMShw.h"
677
678	/* Guest - real mode */
679	#define PGM_GST_TYPE PGM_TYPE_REAL
680	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
681	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_REAL_STR(name)
682	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
683	#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_REAL(name)
684	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_32BIT_REAL_STR(name)
685	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_32BIT_REAL_STR(name)
686	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_PHYS
687	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_32BIT_PD_PHYS
688	#include "PGMBth.h"
689	#include "PGMGst.h"
690	#undef BTH_PGMPOOLKIND_PT_FOR_PT
691	#undef BTH_PGMPOOLKIND_ROOT
692	#undef PGM_BTH_NAME
693	#undef PGM_BTH_NAME_RC_STR
694	#undef PGM_BTH_NAME_R0_STR
695	#undef PGM_GST_TYPE
696	#undef PGM_GST_NAME
697	#undef PGM_GST_NAME_RC_STR
698	#undef PGM_GST_NAME_R0_STR
699
700	/* Guest - protected mode */
701	#define PGM_GST_TYPE PGM_TYPE_PROT
702	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
703	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PROT_STR(name)
704	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
705	#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_PROT(name)
706	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_32BIT_PROT_STR(name)
707	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_32BIT_PROT_STR(name)
708	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_PHYS
709	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_32BIT_PD_PHYS
710	#include "PGMBth.h"
711	#include "PGMGst.h"
712	#undef BTH_PGMPOOLKIND_PT_FOR_PT
713	#undef BTH_PGMPOOLKIND_ROOT
714	#undef PGM_BTH_NAME
715	#undef PGM_BTH_NAME_RC_STR
716	#undef PGM_BTH_NAME_R0_STR
717	#undef PGM_GST_TYPE
718	#undef PGM_GST_NAME
719	#undef PGM_GST_NAME_RC_STR
720	#undef PGM_GST_NAME_R0_STR
721
722	/* Guest - 32-bit mode */
723	#define PGM_GST_TYPE PGM_TYPE_32BIT
724	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
725	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_32BIT_STR(name)
726	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
727	#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_32BIT(name)
728	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_32BIT_32BIT_STR(name)
729	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_32BIT_32BIT_STR(name)
730	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT
731	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB
732	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_32BIT_PD
733	#include "PGMBth.h"
734	#include "PGMGst.h"
735	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
736	#undef BTH_PGMPOOLKIND_PT_FOR_PT
737	#undef BTH_PGMPOOLKIND_ROOT
738	#undef PGM_BTH_NAME
739	#undef PGM_BTH_NAME_RC_STR
740	#undef PGM_BTH_NAME_R0_STR
741	#undef PGM_GST_TYPE
742	#undef PGM_GST_NAME
743	#undef PGM_GST_NAME_RC_STR
744	#undef PGM_GST_NAME_R0_STR
745
746	#undef PGM_SHW_TYPE
747	#undef PGM_SHW_NAME
748	#undef PGM_SHW_NAME_RC_STR
749	#undef PGM_SHW_NAME_R0_STR
750
751
752	/*
753	* Shadow - PAE mode
754	*/
755	#define PGM_SHW_TYPE PGM_TYPE_PAE
756	#define PGM_SHW_NAME(name) PGM_SHW_NAME_PAE(name)
757	#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_PAE_STR(name)
758	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_PAE_STR(name)
759	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_REAL(name)
760	#include "PGMShw.h"
761
762	/* Guest - real mode */
763	#define PGM_GST_TYPE PGM_TYPE_REAL
764	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
765	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_REAL_STR(name)
766	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
767	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_REAL(name)
768	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_PAE_REAL_STR(name)
769	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_REAL_STR(name)
770	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
771	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT_PHYS
772	#include "PGMBth.h"
773	#undef BTH_PGMPOOLKIND_PT_FOR_PT
774	#undef BTH_PGMPOOLKIND_ROOT
775	#undef PGM_BTH_NAME
776	#undef PGM_BTH_NAME_RC_STR
777	#undef PGM_BTH_NAME_R0_STR
778	#undef PGM_GST_TYPE
779	#undef PGM_GST_NAME
780	#undef PGM_GST_NAME_RC_STR
781	#undef PGM_GST_NAME_R0_STR
782
783	/* Guest - protected mode */
784	#define PGM_GST_TYPE PGM_TYPE_PROT
785	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
786	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PROT_STR(name)
787	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
788	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_PROT(name)
789	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_PAE_PROT_STR(name)
790	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_PROT_STR(name)
791	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
792	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT_PHYS
793	#include "PGMBth.h"
794	#undef BTH_PGMPOOLKIND_PT_FOR_PT
795	#undef BTH_PGMPOOLKIND_ROOT
796	#undef PGM_BTH_NAME
797	#undef PGM_BTH_NAME_RC_STR
798	#undef PGM_BTH_NAME_R0_STR
799	#undef PGM_GST_TYPE
800	#undef PGM_GST_NAME
801	#undef PGM_GST_NAME_RC_STR
802	#undef PGM_GST_NAME_R0_STR
803
804	/* Guest - 32-bit mode */
805	#define PGM_GST_TYPE PGM_TYPE_32BIT
806	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
807	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_32BIT_STR(name)
808	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
809	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_32BIT(name)
810	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_PAE_32BIT_STR(name)
811	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_32BIT_STR(name)
812	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_32BIT_PT
813	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB
814	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT_FOR_32BIT
815	#include "PGMBth.h"
816	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
817	#undef BTH_PGMPOOLKIND_PT_FOR_PT
818	#undef BTH_PGMPOOLKIND_ROOT
819	#undef PGM_BTH_NAME
820	#undef PGM_BTH_NAME_RC_STR
821	#undef PGM_BTH_NAME_R0_STR
822	#undef PGM_GST_TYPE
823	#undef PGM_GST_NAME
824	#undef PGM_GST_NAME_RC_STR
825	#undef PGM_GST_NAME_R0_STR
826
827	/* Guest - PAE mode */
828	#define PGM_GST_TYPE PGM_TYPE_PAE
829	#define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
830	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PAE_STR(name)
831	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PAE_STR(name)
832	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_PAE(name)
833	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_PAE_PAE_STR(name)
834	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_PAE_STR(name)
835	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
836	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
837	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT
838	#include "PGMBth.h"
839	#include "PGMGst.h"
840	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
841	#undef BTH_PGMPOOLKIND_PT_FOR_PT
842	#undef BTH_PGMPOOLKIND_ROOT
843	#undef PGM_BTH_NAME
844	#undef PGM_BTH_NAME_RC_STR
845	#undef PGM_BTH_NAME_R0_STR
846	#undef PGM_GST_TYPE
847	#undef PGM_GST_NAME
848	#undef PGM_GST_NAME_RC_STR
849	#undef PGM_GST_NAME_R0_STR
850
851	#undef PGM_SHW_TYPE
852	#undef PGM_SHW_NAME
853	#undef PGM_SHW_NAME_RC_STR
854	#undef PGM_SHW_NAME_R0_STR
855
856
857	/*
858	* Shadow - AMD64 mode
859	*/
860	#define PGM_SHW_TYPE PGM_TYPE_AMD64
861	#define PGM_SHW_NAME(name) PGM_SHW_NAME_AMD64(name)
862	#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_AMD64_STR(name)
863	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_AMD64_STR(name)
864	#include "PGMShw.h"
865
866	#ifdef VBOX_WITH_64_BITS_GUESTS
867	/* Guest - AMD64 mode */
868	# define PGM_GST_TYPE PGM_TYPE_AMD64
869	# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
870	# define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_AMD64_STR(name)
871	# define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_AMD64_STR(name)
872	# define PGM_BTH_NAME(name) PGM_BTH_NAME_AMD64_AMD64(name)
873	# define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_AMD64_AMD64_STR(name)
874	# define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_AMD64_AMD64_STR(name)
875	# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
876	# define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
877	# define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_64BIT_PML4
878	# include "PGMBth.h"
879	# include "PGMGst.h"
880	# undef BTH_PGMPOOLKIND_PT_FOR_BIG
881	# undef BTH_PGMPOOLKIND_PT_FOR_PT
882	# undef BTH_PGMPOOLKIND_ROOT
883	# undef PGM_BTH_NAME
884	# undef PGM_BTH_NAME_RC_STR
885	# undef PGM_BTH_NAME_R0_STR
886	# undef PGM_GST_TYPE
887	# undef PGM_GST_NAME
888	# undef PGM_GST_NAME_RC_STR
889	# undef PGM_GST_NAME_R0_STR
890	#endif /* VBOX_WITH_64_BITS_GUESTS */
891
892	#undef PGM_SHW_TYPE
893	#undef PGM_SHW_NAME
894	#undef PGM_SHW_NAME_RC_STR
895	#undef PGM_SHW_NAME_R0_STR
896
897
898	/*
899	* Shadow - Nested paging mode
900	*/
901	#define PGM_SHW_TYPE PGM_TYPE_NESTED
902	#define PGM_SHW_NAME(name) PGM_SHW_NAME_NESTED(name)
903	#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_NESTED_STR(name)
904	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_NESTED_STR(name)
905	#include "PGMShw.h"
906
907	/* Guest - real mode */
908	#define PGM_GST_TYPE PGM_TYPE_REAL
909	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
910	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_REAL_STR(name)
911	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
912	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_REAL(name)
913	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_REAL_STR(name)
914	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_REAL_STR(name)
915	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
916	#include "PGMBth.h"
917	#undef BTH_PGMPOOLKIND_PT_FOR_PT
918	#undef PGM_BTH_NAME
919	#undef PGM_BTH_NAME_RC_STR
920	#undef PGM_BTH_NAME_R0_STR
921	#undef PGM_GST_TYPE
922	#undef PGM_GST_NAME
923	#undef PGM_GST_NAME_RC_STR
924	#undef PGM_GST_NAME_R0_STR
925
926	/* Guest - protected mode */
927	#define PGM_GST_TYPE PGM_TYPE_PROT
928	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
929	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PROT_STR(name)
930	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
931	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_PROT(name)
932	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_PROT_STR(name)
933	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_PROT_STR(name)
934	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
935	#include "PGMBth.h"
936	#undef BTH_PGMPOOLKIND_PT_FOR_PT
937	#undef PGM_BTH_NAME
938	#undef PGM_BTH_NAME_RC_STR
939	#undef PGM_BTH_NAME_R0_STR
940	#undef PGM_GST_TYPE
941	#undef PGM_GST_NAME
942	#undef PGM_GST_NAME_RC_STR
943	#undef PGM_GST_NAME_R0_STR
944
945	/* Guest - 32-bit mode */
946	#define PGM_GST_TYPE PGM_TYPE_32BIT
947	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
948	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_32BIT_STR(name)
949	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
950	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_32BIT(name)
951	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_32BIT_STR(name)
952	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_32BIT_STR(name)
953	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_32BIT_PT
954	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB
955	#include "PGMBth.h"
956	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
957	#undef BTH_PGMPOOLKIND_PT_FOR_PT
958	#undef PGM_BTH_NAME
959	#undef PGM_BTH_NAME_RC_STR
960	#undef PGM_BTH_NAME_R0_STR
961	#undef PGM_GST_TYPE
962	#undef PGM_GST_NAME
963	#undef PGM_GST_NAME_RC_STR
964	#undef PGM_GST_NAME_R0_STR
965
966	/* Guest - PAE mode */
967	#define PGM_GST_TYPE PGM_TYPE_PAE
968	#define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
969	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PAE_STR(name)
970	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PAE_STR(name)
971	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_PAE(name)
972	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_PAE_STR(name)
973	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_PAE_STR(name)
974	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
975	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
976	#include "PGMBth.h"
977	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
978	#undef BTH_PGMPOOLKIND_PT_FOR_PT
979	#undef PGM_BTH_NAME
980	#undef PGM_BTH_NAME_RC_STR
981	#undef PGM_BTH_NAME_R0_STR
982	#undef PGM_GST_TYPE
983	#undef PGM_GST_NAME
984	#undef PGM_GST_NAME_RC_STR
985	#undef PGM_GST_NAME_R0_STR
986
987	#ifdef VBOX_WITH_64_BITS_GUESTS
988	/* Guest - AMD64 mode */
989	# define PGM_GST_TYPE PGM_TYPE_AMD64
990	# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
991	# define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_AMD64_STR(name)
992	# define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_AMD64_STR(name)
993	# define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_AMD64(name)
994	# define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_AMD64_STR(name)
995	# define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_AMD64_STR(name)
996	# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
997	# define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
998	# include "PGMBth.h"
999	# undef BTH_PGMPOOLKIND_PT_FOR_BIG
1000	# undef BTH_PGMPOOLKIND_PT_FOR_PT
1001	# undef PGM_BTH_NAME
1002	# undef PGM_BTH_NAME_RC_STR
1003	# undef PGM_BTH_NAME_R0_STR
1004	# undef PGM_GST_TYPE
1005	# undef PGM_GST_NAME
1006	# undef PGM_GST_NAME_RC_STR
1007	# undef PGM_GST_NAME_R0_STR
1008	#endif /* VBOX_WITH_64_BITS_GUESTS */
1009
1010	#undef PGM_SHW_TYPE
1011	#undef PGM_SHW_NAME
1012	#undef PGM_SHW_NAME_RC_STR
1013	#undef PGM_SHW_NAME_R0_STR
1014
1015
1016	/*
1017	* Shadow - EPT
1018	*/
1019	#define PGM_SHW_TYPE PGM_TYPE_EPT
1020	#define PGM_SHW_NAME(name) PGM_SHW_NAME_EPT(name)
1021	#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_EPT_STR(name)
1022	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_EPT_STR(name)
1023	#include "PGMShw.h"
1024
1025	/* Guest - real mode */
1026	#define PGM_GST_TYPE PGM_TYPE_REAL
1027	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
1028	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_REAL_STR(name)
1029	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
1030	#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_REAL(name)
1031	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_REAL_STR(name)
1032	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_REAL_STR(name)
1033	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
1034	#include "PGMBth.h"
1035	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1036	#undef PGM_BTH_NAME
1037	#undef PGM_BTH_NAME_RC_STR
1038	#undef PGM_BTH_NAME_R0_STR
1039	#undef PGM_GST_TYPE
1040	#undef PGM_GST_NAME
1041	#undef PGM_GST_NAME_RC_STR
1042	#undef PGM_GST_NAME_R0_STR
1043
1044	/* Guest - protected mode */
1045	#define PGM_GST_TYPE PGM_TYPE_PROT
1046	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
1047	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PROT_STR(name)
1048	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
1049	#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_PROT(name)
1050	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_PROT_STR(name)
1051	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_PROT_STR(name)
1052	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
1053	#include "PGMBth.h"
1054	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1055	#undef PGM_BTH_NAME
1056	#undef PGM_BTH_NAME_RC_STR
1057	#undef PGM_BTH_NAME_R0_STR
1058	#undef PGM_GST_TYPE
1059	#undef PGM_GST_NAME
1060	#undef PGM_GST_NAME_RC_STR
1061	#undef PGM_GST_NAME_R0_STR
1062
1063	/* Guest - 32-bit mode */
1064	#define PGM_GST_TYPE PGM_TYPE_32BIT
1065	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
1066	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_32BIT_STR(name)
1067	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
1068	#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_32BIT(name)
1069	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_32BIT_STR(name)
1070	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_32BIT_STR(name)
1071	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_32BIT_PT
1072	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB
1073	#include "PGMBth.h"
1074	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
1075	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1076	#undef PGM_BTH_NAME
1077	#undef PGM_BTH_NAME_RC_STR
1078	#undef PGM_BTH_NAME_R0_STR
1079	#undef PGM_GST_TYPE
1080	#undef PGM_GST_NAME
1081	#undef PGM_GST_NAME_RC_STR
1082	#undef PGM_GST_NAME_R0_STR
1083
1084	/* Guest - PAE mode */
1085	#define PGM_GST_TYPE PGM_TYPE_PAE
1086	#define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
1087	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PAE_STR(name)
1088	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PAE_STR(name)
1089	#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_PAE(name)
1090	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_PAE_STR(name)
1091	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_PAE_STR(name)
1092	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
1093	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
1094	#include "PGMBth.h"
1095	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
1096	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1097	#undef PGM_BTH_NAME
1098	#undef PGM_BTH_NAME_RC_STR
1099	#undef PGM_BTH_NAME_R0_STR
1100	#undef PGM_GST_TYPE
1101	#undef PGM_GST_NAME
1102	#undef PGM_GST_NAME_RC_STR
1103	#undef PGM_GST_NAME_R0_STR
1104
1105	#ifdef VBOX_WITH_64_BITS_GUESTS
1106	/* Guest - AMD64 mode */
1107	# define PGM_GST_TYPE PGM_TYPE_AMD64
1108	# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
1109	# define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_AMD64_STR(name)
1110	# define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_AMD64_STR(name)
1111	# define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_AMD64(name)
1112	# define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_AMD64_STR(name)
1113	# define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_AMD64_STR(name)
1114	# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
1115	# define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
1116	# include "PGMBth.h"
1117	# undef BTH_PGMPOOLKIND_PT_FOR_BIG
1118	# undef BTH_PGMPOOLKIND_PT_FOR_PT
1119	# undef PGM_BTH_NAME
1120	# undef PGM_BTH_NAME_RC_STR
1121	# undef PGM_BTH_NAME_R0_STR
1122	# undef PGM_GST_TYPE
1123	# undef PGM_GST_NAME
1124	# undef PGM_GST_NAME_RC_STR
1125	# undef PGM_GST_NAME_R0_STR
1126	#endif /* VBOX_WITH_64_BITS_GUESTS */
1127
1128	#undef PGM_SHW_TYPE
1129	#undef PGM_SHW_NAME
1130	#undef PGM_SHW_NAME_RC_STR
1131	#undef PGM_SHW_NAME_R0_STR
1132
1133
1134
1135	/**
1136	* Initiates the paging of VM.
1137	*
1138	* @returns VBox status code.
1139	* @param pVM Pointer to VM structure.
1140	*/
1141	VMMR3DECL(int) PGMR3Init(PVM pVM)
1142	{
1143	LogFlow(("PGMR3Init:\n"));
1144
1145	/*
1146	* Assert alignment and sizes.
1147	*/
1148	AssertRelease(sizeof(pVM->pgm.s) <= sizeof(pVM->pgm.padding));
1149
1150	/*
1151	* Init the structure.
1152	*/
1153	pVM->pgm.s.offVM = RT_OFFSETOF(VM, pgm.s);
1154	pVM->pgm.s.offVCpu = RT_OFFSETOF(VMCPU, pgm.s);
1155	pVM->pgm.s.enmShadowMode = PGMMODE_INVALID;
1156	pVM->pgm.s.enmGuestMode = PGMMODE_INVALID;
1157	pVM->pgm.s.enmHostMode = SUPPAGINGMODE_INVALID;
1158	pVM->pgm.s.GCPhysCR3 = NIL_RTGCPHYS;
1159	#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
1160	pVM->pgm.s.GCPhysGstCR3Monitored = NIL_RTGCPHYS;
1161	#endif
1162	pVM->pgm.s.fA20Enabled = true;
1163	pVM->pgm.s.GCPhys4MBPSEMask = RT_BIT_64(32) - 1; /* default; checked later */
1164	pVM->pgm.s.pGstPaePdptR3 = NULL;
1165	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
1166	pVM->pgm.s.pGstPaePdptR0 = NIL_RTR0PTR;
1167	#endif
1168	pVM->pgm.s.pGstPaePdptRC = NIL_RTRCPTR;
1169	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.apGstPaePDsR3); i++)
1170	{
1171	pVM->pgm.s.apGstPaePDsR3[i] = NULL;
1172	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
1173	pVM->pgm.s.apGstPaePDsR0[i] = NIL_RTR0PTR;
1174	#endif
1175	pVM->pgm.s.apGstPaePDsRC[i] = NIL_RTRCPTR;
1176	pVM->pgm.s.aGCPhysGstPaePDs[i] = NIL_RTGCPHYS;
1177	pVM->pgm.s.aGCPhysGstPaePDsMonitored[i] = NIL_RTGCPHYS;
1178	}
1179
1180	#ifdef VBOX_STRICT
1181	VMR3AtStateRegister(pVM, pgmR3ResetNoMorePhysWritesFlag, NULL);
1182	#endif
1183
1184	/*
1185	* Get the configured RAM size - to estimate saved state size.
1186	*/
1187	uint64_t cbRam;
1188	int rc = CFGMR3QueryU64(CFGMR3GetRoot(pVM), "RamSize", &cbRam);
1189	if (rc == VERR_CFGM_VALUE_NOT_FOUND)
1190	cbRam = pVM->pgm.s.cbRamSize = 0;
1191	else if (RT_SUCCESS(rc))
1192	{
1193	if (cbRam < PAGE_SIZE)
1194	cbRam = 0;
1195	cbRam = RT_ALIGN_64(cbRam, PAGE_SIZE);
1196	pVM->pgm.s.cbRamSize = (RTUINT)cbRam;
1197	}
1198	else
1199	{
1200	AssertMsgFailed(("Configuration error: Failed to query integer \"RamSize\", rc=%Rrc.\n", rc));
1201	return rc;
1202	}
1203
1204	/*
1205	* Register saved state data unit.
1206	*/
1207	rc = SSMR3RegisterInternal(pVM, "pgm", 1, PGM_SAVED_STATE_VERSION, (size_t)cbRam + sizeof(PGM),
1208	NULL, pgmR3Save, NULL,
1209	NULL, pgmR3Load, NULL);
1210	if (RT_FAILURE(rc))
1211	return rc;
1212
1213	/*
1214	* Initialize the PGM critical section and flush the phys TLBs
1215	*/
1216	rc = PDMR3CritSectInit(pVM, &pVM->pgm.s.CritSect, "PGM");
1217	AssertRCReturn(rc, rc);
1218
1219	PGMR3PhysChunkInvalidateTLB(pVM);
1220	PGMPhysInvalidatePageR3MapTLB(pVM);
1221	PGMPhysInvalidatePageR0MapTLB(pVM);
1222	PGMPhysInvalidatePageGCMapTLB(pVM);
1223
1224	/*
1225	* Trees
1226	*/
1227	rc = MMHyperAlloc(pVM, sizeof(PGMTREES), 0, MM_TAG_PGM, (void **)&pVM->pgm.s.pTreesR3);
1228	if (RT_SUCCESS(rc))
1229	{
1230	pVM->pgm.s.pTreesR0 = MMHyperR3ToR0(pVM, pVM->pgm.s.pTreesR3);
1231	pVM->pgm.s.pTreesRC = MMHyperR3ToRC(pVM, pVM->pgm.s.pTreesR3);
1232
1233	/*
1234	* Alocate the zero page.
1235	*/
1236	rc = MMHyperAlloc(pVM, PAGE_SIZE, PAGE_SIZE, MM_TAG_PGM, &pVM->pgm.s.pvZeroPgR3);
1237	}
1238	if (RT_SUCCESS(rc))
1239	{
1240	pVM->pgm.s.pvZeroPgGC = MMHyperR3ToRC(pVM, pVM->pgm.s.pvZeroPgR3);
1241	pVM->pgm.s.pvZeroPgR0 = MMHyperR3ToR0(pVM, pVM->pgm.s.pvZeroPgR3);
1242	AssertRelease(pVM->pgm.s.pvZeroPgR0 != NIL_RTHCPHYS);
1243	pVM->pgm.s.HCPhysZeroPg = MMR3HyperHCVirt2HCPhys(pVM, pVM->pgm.s.pvZeroPgR3);
1244	AssertRelease(pVM->pgm.s.HCPhysZeroPg != NIL_RTHCPHYS);
1245
1246	/*
1247	* Init the paging.
1248	*/
1249	rc = pgmR3InitPaging(pVM);
1250	}
1251	if (RT_SUCCESS(rc))
1252	{
1253	/*
1254	* Init the page pool.
1255	*/
1256	rc = pgmR3PoolInit(pVM);
1257	}
1258	#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
1259	if (RT_SUCCESS(rc))
1260	rc = PGMR3ChangeMode(pVM, PGMMODE_REAL);
1261	#endif
1262	if (RT_SUCCESS(rc))
1263	{
1264	/*
1265	* Info & statistics
1266	*/
1267	DBGFR3InfoRegisterInternal(pVM, "mode",
1268	"Shows the current paging mode. "
1269	"Recognizes 'all', 'guest', 'shadow' and 'host' as arguments, defaulting to 'all' if nothing's given.",
1270	pgmR3InfoMode);
1271	DBGFR3InfoRegisterInternal(pVM, "pgmcr3",
1272	"Dumps all the entries in the top level paging table. No arguments.",
1273	pgmR3InfoCr3);
1274	DBGFR3InfoRegisterInternal(pVM, "phys",
1275	"Dumps all the physical address ranges. No arguments.",
1276	pgmR3PhysInfo);
1277	DBGFR3InfoRegisterInternal(pVM, "handlers",
1278	"Dumps physical, virtual and hyper virtual handlers. "
1279	"Pass 'phys', 'virt', 'hyper' as argument if only one kind is wanted."
1280	"Add 'nost' if the statistics are unwanted, use together with 'all' or explicit selection.",
1281	pgmR3InfoHandlers);
1282	DBGFR3InfoRegisterInternal(pVM, "mappings",
1283	"Dumps guest mappings.",
1284	pgmR3MapInfo);
1285
1286	STAM_REL_REG(pVM, &pVM->pgm.s.cGuestModeChanges, STAMTYPE_COUNTER, "/PGM/cGuestModeChanges", STAMUNIT_OCCURENCES, "Number of guest mode changes.");
1287	STAM_REL_REG(pVM, &pVM->pgm.s.cRelocations, STAMTYPE_COUNTER, "/PGM/cRelocations", STAMUNIT_OCCURENCES, "Number of hypervisor relocations.");
1288	#ifdef VBOX_WITH_STATISTICS
1289	pgmR3InitStats(pVM);
1290	#endif
1291	#ifdef VBOX_WITH_DEBUGGER
1292	/*
1293	* Debugger commands.
1294	*/
1295	static bool fRegisteredCmds = false;
1296	if (!fRegisteredCmds)
1297	{
1298	int rc = DBGCRegisterCommands(&g_aCmds[0], RT_ELEMENTS(g_aCmds));
1299	if (RT_SUCCESS(rc))
1300	fRegisteredCmds = true;
1301	}
1302	#endif
1303	return VINF_SUCCESS;
1304	}
1305
1306	/* Almost no cleanup necessary, MM frees all memory. */
1307	PDMR3CritSectDelete(&pVM->pgm.s.CritSect);
1308
1309	return rc;
1310	}
1311
1312
1313	/**
1314	* Initializes the per-VCPU PGM.
1315	*
1316	* @returns VBox status code.
1317	* @param pVM The VM to operate on.
1318	*/
1319	VMMR3DECL(int) PGMR3InitCPU(PVM pVM)
1320	{
1321	LogFlow(("PGMR3InitCPU\n"));
1322	return VINF_SUCCESS;
1323	}
1324
1325
1326	/**
1327	* Init paging.
1328	*
1329	* Since we need to check what mode the host is operating in before we can choose
1330	* the right paging functions for the host we have to delay this until R0 has
1331	* been initialized.
1332	*
1333	* @returns VBox status code.
1334	* @param pVM VM handle.
1335	*/
1336	static int pgmR3InitPaging(PVM pVM)
1337	{
1338	/*
1339	* Force a recalculation of modes and switcher so everyone gets notified.
1340	*/
1341	pVM->pgm.s.enmShadowMode = PGMMODE_INVALID;
1342	pVM->pgm.s.enmGuestMode = PGMMODE_INVALID;
1343	pVM->pgm.s.enmHostMode = SUPPAGINGMODE_INVALID;
1344
1345	/*
1346	* Allocate static mapping space for whatever the cr3 register
1347	* points to and in the case of PAE mode to the 4 PDs.
1348	*/
1349	int rc = MMR3HyperReserve(pVM, PAGE_SIZE * 5, "CR3 mapping", &pVM->pgm.s.GCPtrCR3Mapping);
1350	if (RT_FAILURE(rc))
1351	{
1352	AssertMsgFailed(("Failed to reserve two pages for cr mapping in HMA, rc=%Rrc\n", rc));
1353	return rc;
1354	}
1355	MMR3HyperReserve(pVM, PAGE_SIZE, "fence", NULL);
1356
1357	/*
1358	* Allocate pages for the three possible intermediate contexts
1359	* (AMD64, PAE and plain 32-Bit). We maintain all three contexts
1360	* for the sake of simplicity. The AMD64 uses the PAE for the
1361	* lower levels, making the total number of pages 11 (3 + 7 + 1).
1362	*
1363	* We assume that two page tables will be enought for the core code
1364	* mappings (HC virtual and identity).
1365	*/
1366	pVM->pgm.s.pInterPD = (PX86PD)MMR3PageAllocLow(pVM);
1367	pVM->pgm.s.apInterPTs[0] = (PX86PT)MMR3PageAllocLow(pVM);
1368	pVM->pgm.s.apInterPTs[1] = (PX86PT)MMR3PageAllocLow(pVM);
1369	pVM->pgm.s.apInterPaePTs[0] = (PX86PTPAE)MMR3PageAlloc(pVM);
1370	pVM->pgm.s.apInterPaePTs[1] = (PX86PTPAE)MMR3PageAlloc(pVM);
1371	pVM->pgm.s.apInterPaePDs[0] = (PX86PDPAE)MMR3PageAlloc(pVM);
1372	pVM->pgm.s.apInterPaePDs[1] = (PX86PDPAE)MMR3PageAlloc(pVM);
1373	pVM->pgm.s.apInterPaePDs[2] = (PX86PDPAE)MMR3PageAlloc(pVM);
1374	pVM->pgm.s.apInterPaePDs[3] = (PX86PDPAE)MMR3PageAlloc(pVM);
1375	pVM->pgm.s.pInterPaePDPT = (PX86PDPT)MMR3PageAllocLow(pVM);
1376	pVM->pgm.s.pInterPaePDPT64 = (PX86PDPT)MMR3PageAllocLow(pVM);
1377	pVM->pgm.s.pInterPaePML4 = (PX86PML4)MMR3PageAllocLow(pVM);
1378	if ( !pVM->pgm.s.pInterPD
1379	\|\| !pVM->pgm.s.apInterPTs[0]
1380	\|\| !pVM->pgm.s.apInterPTs[1]
1381	\|\| !pVM->pgm.s.apInterPaePTs[0]
1382	\|\| !pVM->pgm.s.apInterPaePTs[1]
1383	\|\| !pVM->pgm.s.apInterPaePDs[0]
1384	\|\| !pVM->pgm.s.apInterPaePDs[1]
1385	\|\| !pVM->pgm.s.apInterPaePDs[2]
1386	\|\| !pVM->pgm.s.apInterPaePDs[3]
1387	\|\| !pVM->pgm.s.pInterPaePDPT
1388	\|\| !pVM->pgm.s.pInterPaePDPT64
1389	\|\| !pVM->pgm.s.pInterPaePML4)
1390	{
1391	AssertMsgFailed(("Failed to allocate pages for the intermediate context!\n"));
1392	return VERR_NO_PAGE_MEMORY;
1393	}
1394
1395	pVM->pgm.s.HCPhysInterPD = MMPage2Phys(pVM, pVM->pgm.s.pInterPD);
1396	AssertRelease(pVM->pgm.s.HCPhysInterPD != NIL_RTHCPHYS && !(pVM->pgm.s.HCPhysInterPD & PAGE_OFFSET_MASK));
1397	pVM->pgm.s.HCPhysInterPaePDPT = MMPage2Phys(pVM, pVM->pgm.s.pInterPaePDPT);
1398	AssertRelease(pVM->pgm.s.HCPhysInterPaePDPT != NIL_RTHCPHYS && !(pVM->pgm.s.HCPhysInterPaePDPT & PAGE_OFFSET_MASK));
1399	pVM->pgm.s.HCPhysInterPaePML4 = MMPage2Phys(pVM, pVM->pgm.s.pInterPaePML4);
1400	AssertRelease(pVM->pgm.s.HCPhysInterPaePML4 != NIL_RTHCPHYS && !(pVM->pgm.s.HCPhysInterPaePML4 & PAGE_OFFSET_MASK) && pVM->pgm.s.HCPhysInterPaePML4 < 0xffffffff);
1401
1402	/*
1403	* Initialize the pages, setting up the PML4 and PDPT for repetitive 4GB action.
1404	*/
1405	ASMMemZeroPage(pVM->pgm.s.pInterPD);
1406	ASMMemZeroPage(pVM->pgm.s.apInterPTs[0]);
1407	ASMMemZeroPage(pVM->pgm.s.apInterPTs[1]);
1408
1409	ASMMemZeroPage(pVM->pgm.s.apInterPaePTs[0]);
1410	ASMMemZeroPage(pVM->pgm.s.apInterPaePTs[1]);
1411
1412	ASMMemZeroPage(pVM->pgm.s.pInterPaePDPT);
1413	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.apInterPaePDs); i++)
1414	{
1415	ASMMemZeroPage(pVM->pgm.s.apInterPaePDs[i]);
1416	pVM->pgm.s.pInterPaePDPT->a[i].u = X86_PDPE_P \| PGM_PLXFLAGS_PERMANENT
1417	\| MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[i]);
1418	}
1419
1420	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.pInterPaePDPT64->a); i++)
1421	{
1422	const unsigned iPD = i % RT_ELEMENTS(pVM->pgm.s.apInterPaePDs);
1423	pVM->pgm.s.pInterPaePDPT64->a[i].u = X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_A \| PGM_PLXFLAGS_PERMANENT
1424	\| MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[iPD]);
1425	}
1426
1427	RTHCPHYS HCPhysInterPaePDPT64 = MMPage2Phys(pVM, pVM->pgm.s.pInterPaePDPT64);
1428	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.pInterPaePML4->a); i++)
1429	pVM->pgm.s.pInterPaePML4->a[i].u = X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_A \| PGM_PLXFLAGS_PERMANENT
1430	\| HCPhysInterPaePDPT64;
1431
1432	/*
1433	* Allocate pages for the three possible guest contexts (AMD64, PAE and plain 32-Bit).
1434	* We allocate pages for all three posibilities in order to simplify mappings and
1435	* avoid resource failure during mode switches. So, we need to cover all levels of the
1436	* of the first 4GB down to PD level.
1437	* As with the intermediate context, AMD64 uses the PAE PDPT and PDs.
1438	*/
1439	#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
1440	pVM->pgm.s.pShw32BitPdR3 = (PX86PD)MMR3PageAllocLow(pVM);
1441	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
1442	pVM->pgm.s.pShw32BitPdR0 = (uintptr_t)pVM->pgm.s.pShw32BitPdR3;
1443	# endif
1444	pVM->pgm.s.apShwPaePDsR3[0] = (PX86PDPAE)MMR3PageAlloc(pVM);
1445	pVM->pgm.s.apShwPaePDsR3[1] = (PX86PDPAE)MMR3PageAlloc(pVM);
1446	AssertRelease((uintptr_t)pVM->pgm.s.apShwPaePDsR3[0] + PAGE_SIZE == (uintptr_t)pVM->pgm.s.apShwPaePDsR3[1]);
1447	pVM->pgm.s.apShwPaePDsR3[2] = (PX86PDPAE)MMR3PageAlloc(pVM);
1448	AssertRelease((uintptr_t)pVM->pgm.s.apShwPaePDsR3[1] + PAGE_SIZE == (uintptr_t)pVM->pgm.s.apShwPaePDsR3[2]);
1449	pVM->pgm.s.apShwPaePDsR3[3] = (PX86PDPAE)MMR3PageAlloc(pVM);
1450	AssertRelease((uintptr_t)pVM->pgm.s.apShwPaePDsR3[2] + PAGE_SIZE == (uintptr_t)pVM->pgm.s.apShwPaePDsR3[3]);
1451	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
1452	pVM->pgm.s.apShwPaePDsR0[0] = (uintptr_t)pVM->pgm.s.apShwPaePDsR3[0];
1453	pVM->pgm.s.apShwPaePDsR0[1] = (uintptr_t)pVM->pgm.s.apShwPaePDsR3[1];
1454	pVM->pgm.s.apShwPaePDsR0[2] = (uintptr_t)pVM->pgm.s.apShwPaePDsR3[2];
1455	pVM->pgm.s.apShwPaePDsR0[3] = (uintptr_t)pVM->pgm.s.apShwPaePDsR3[3];
1456	# endif
1457	pVM->pgm.s.pShwPaePdptR3 = (PX86PDPT)MMR3PageAllocLow(pVM);
1458	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
1459	pVM->pgm.s.pShwPaePdptR0 = (uintptr_t)pVM->pgm.s.pShwPaePdptR3;
1460	# endif
1461	#endif /* VBOX_WITH_PGMPOOL_PAGING_ONLY */
1462	pVM->pgm.s.pShwNestedRootR3 = MMR3PageAllocLow(pVM);
1463	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
1464	pVM->pgm.s.pShwNestedRootR0 = (uintptr_t)pVM->pgm.s.pShwNestedRootR3;
1465	#endif
1466
1467	#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
1468	if (!pVM->pgm.s.pShwNestedRootR3)
1469	#else
1470	if ( !pVM->pgm.s.pShw32BitPdR3
1471	\|\| !pVM->pgm.s.apShwPaePDsR3[0]
1472	\|\| !pVM->pgm.s.apShwPaePDsR3[1]
1473	\|\| !pVM->pgm.s.apShwPaePDsR3[2]
1474	\|\| !pVM->pgm.s.apShwPaePDsR3[3]
1475	\|\| !pVM->pgm.s.pShwPaePdptR3
1476	\|\| !pVM->pgm.s.pShwNestedRootR3)
1477	#endif
1478	{
1479	AssertMsgFailed(("Failed to allocate pages for the intermediate context!\n"));
1480	return VERR_NO_PAGE_MEMORY;
1481	}
1482
1483	/* get physical addresses. */
1484	#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
1485	pVM->pgm.s.HCPhysShw32BitPD = MMPage2Phys(pVM, pVM->pgm.s.pShw32BitPdR3);
1486	Assert(MMPagePhys2Page(pVM, pVM->pgm.s.HCPhysShw32BitPD) == pVM->pgm.s.pShw32BitPdR3);
1487	pVM->pgm.s.aHCPhysPaePDs[0] = MMPage2Phys(pVM, pVM->pgm.s.apShwPaePDsR3[0]);
1488	pVM->pgm.s.aHCPhysPaePDs[1] = MMPage2Phys(pVM, pVM->pgm.s.apShwPaePDsR3[1]);
1489	pVM->pgm.s.aHCPhysPaePDs[2] = MMPage2Phys(pVM, pVM->pgm.s.apShwPaePDsR3[2]);
1490	pVM->pgm.s.aHCPhysPaePDs[3] = MMPage2Phys(pVM, pVM->pgm.s.apShwPaePDsR3[3]);
1491	pVM->pgm.s.HCPhysShwPaePdpt = MMPage2Phys(pVM, pVM->pgm.s.pShwPaePdptR3);
1492	#endif
1493	pVM->pgm.s.HCPhysShwNestedRoot = MMPage2Phys(pVM, pVM->pgm.s.pShwNestedRootR3);
1494
1495	/*
1496	* Initialize the pages, setting up the PML4 and PDPT for action below 4GB.
1497	*/
1498	#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
1499	ASMMemZero32(pVM->pgm.s.pShw32BitPdR3, PAGE_SIZE);
1500	ASMMemZero32(pVM->pgm.s.pShwPaePdptR3, PAGE_SIZE);
1501	#endif
1502	ASMMemZero32(pVM->pgm.s.pShwNestedRootR3, PAGE_SIZE);
1503	#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
1504	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.apShwPaePDsR3); i++)
1505	{
1506	ASMMemZero32(pVM->pgm.s.apShwPaePDsR3[i], PAGE_SIZE);
1507	pVM->pgm.s.pShwPaePdptR3->a[i].u = X86_PDPE_P \| PGM_PLXFLAGS_PERMANENT \| pVM->pgm.s.aHCPhysPaePDs[i];
1508	/* The flags will be corrected when entering and leaving long mode. */
1509	}
1510	#endif
1511
1512	/*
1513	* Initialize paging workers and mode from current host mode
1514	* and the guest running in real mode.
1515	*/
1516	pVM->pgm.s.enmHostMode = SUPGetPagingMode();
1517	switch (pVM->pgm.s.enmHostMode)
1518	{
1519	case SUPPAGINGMODE_32_BIT:
1520	case SUPPAGINGMODE_32_BIT_GLOBAL:
1521	case SUPPAGINGMODE_PAE:
1522	case SUPPAGINGMODE_PAE_GLOBAL:
1523	case SUPPAGINGMODE_PAE_NX:
1524	case SUPPAGINGMODE_PAE_GLOBAL_NX:
1525	break;
1526
1527	case SUPPAGINGMODE_AMD64:
1528	case SUPPAGINGMODE_AMD64_GLOBAL:
1529	case SUPPAGINGMODE_AMD64_NX:
1530	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
1531	#ifndef VBOX_WITH_HYBRID_32BIT_KERNEL
1532	if (ARCH_BITS != 64)
1533	{
1534	AssertMsgFailed(("Host mode %d (64-bit) is not supported by non-64bit builds\n", pVM->pgm.s.enmHostMode));
1535	LogRel(("Host mode %d (64-bit) is not supported by non-64bit builds\n", pVM->pgm.s.enmHostMode));
1536	return VERR_PGM_UNSUPPORTED_HOST_PAGING_MODE;
1537	}
1538	#endif
1539	break;
1540	default:
1541	AssertMsgFailed(("Host mode %d is not supported\n", pVM->pgm.s.enmHostMode));
1542	return VERR_PGM_UNSUPPORTED_HOST_PAGING_MODE;
1543	}
1544	rc = pgmR3ModeDataInit(pVM, false /* don't resolve GC and R0 syms yet */);
1545	#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
1546	if (RT_SUCCESS(rc))
1547	rc = PGMR3ChangeMode(pVM, PGMMODE_REAL);
1548	#endif
1549	if (RT_SUCCESS(rc))
1550	{
1551	LogFlow(("pgmR3InitPaging: returns successfully\n"));
1552	#if HC_ARCH_BITS == 64
1553	# ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
1554	LogRel(("Debug: HCPhysShw32BitPD=%RHp aHCPhysPaePDs={%RHp,%RHp,%RHp,%RHp} HCPhysShwPaePdpt=%RHp\n",
1555	pVM->pgm.s.HCPhysShw32BitPD,
1556	pVM->pgm.s.aHCPhysPaePDs[0], pVM->pgm.s.aHCPhysPaePDs[1], pVM->pgm.s.aHCPhysPaePDs[2], pVM->pgm.s.aHCPhysPaePDs[3],
1557	pVM->pgm.s.HCPhysShwPaePdpt));
1558	# endif
1559	LogRel(("Debug: HCPhysInterPD=%RHp HCPhysInterPaePDPT=%RHp HCPhysInterPaePML4=%RHp\n",
1560	pVM->pgm.s.HCPhysInterPD, pVM->pgm.s.HCPhysInterPaePDPT, pVM->pgm.s.HCPhysInterPaePML4));
1561	LogRel(("Debug: apInterPTs={%RHp,%RHp} apInterPaePTs={%RHp,%RHp} apInterPaePDs={%RHp,%RHp,%RHp,%RHp} pInterPaePDPT64=%RHp\n",
1562	MMPage2Phys(pVM, pVM->pgm.s.apInterPTs[0]), MMPage2Phys(pVM, pVM->pgm.s.apInterPTs[1]),
1563	MMPage2Phys(pVM, pVM->pgm.s.apInterPaePTs[0]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePTs[1]),
1564	MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[0]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[1]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[2]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[3]),
1565	MMPage2Phys(pVM, pVM->pgm.s.pInterPaePDPT64)));
1566	#endif
1567
1568	return VINF_SUCCESS;
1569	}
1570
1571	LogFlow(("pgmR3InitPaging: returns %Rrc\n", rc));
1572	return rc;
1573	}
1574
1575
1576	#ifdef VBOX_WITH_STATISTICS
1577	/**
1578	* Init statistics
1579	*/
1580	static void pgmR3InitStats(PVM pVM)
1581	{
1582	PPGM pPGM = &pVM->pgm.s;
1583	unsigned i;
1584
1585	/*
1586	* Note! The layout of this function matches the member layout exactly!
1587	*/
1588
1589	/* Common - misc variables */
1590	STAM_REG(pVM, &pPGM->cAllPages, STAMTYPE_U32, "/PGM/Page/cAllPages", STAMUNIT_OCCURENCES, "The total number of pages.");
1591	STAM_REG(pVM, &pPGM->cPrivatePages, STAMTYPE_U32, "/PGM/Page/cPrivatePages", STAMUNIT_OCCURENCES, "The number of private pages.");
1592	STAM_REG(pVM, &pPGM->cSharedPages, STAMTYPE_U32, "/PGM/Page/cSharedPages", STAMUNIT_OCCURENCES, "The number of shared pages.");
1593	STAM_REG(pVM, &pPGM->cZeroPages, STAMTYPE_U32, "/PGM/Page/cZeroPages", STAMUNIT_OCCURENCES, "The number of zero backed pages.");
1594	STAM_REG(pVM, &pPGM->ChunkR3Map.c, STAMTYPE_U32, "/PGM/ChunkR3Map/c", STAMUNIT_OCCURENCES, "Number of mapped chunks.");
1595	STAM_REG(pVM, &pPGM->ChunkR3Map.cMax, STAMTYPE_U32, "/PGM/ChunkR3Map/cMax", STAMUNIT_OCCURENCES, "Maximum number of mapped chunks.");
1596
1597	/* Common - stats */
1598	#ifdef PGMPOOL_WITH_GCPHYS_TRACKING
1599	STAM_REG(pVM, &pPGM->StatTrackVirgin, STAMTYPE_COUNTER, "/PGM/Track/Virgin", STAMUNIT_OCCURENCES, "The number of first time shadowings");
1600	STAM_REG(pVM, &pPGM->StatTrackAliased, STAMTYPE_COUNTER, "/PGM/Track/Aliased", STAMUNIT_OCCURENCES, "The number of times switching to cRef2, i.e. the page is being shadowed by two PTs.");
1601	STAM_REG(pVM, &pPGM->StatTrackAliasedMany, STAMTYPE_COUNTER, "/PGM/Track/AliasedMany", STAMUNIT_OCCURENCES, "The number of times we're tracking using cRef2.");
1602	STAM_REG(pVM, &pPGM->StatTrackAliasedLots, STAMTYPE_COUNTER, "/PGM/Track/AliasedLots", STAMUNIT_OCCURENCES, "The number of times we're hitting pages which has overflowed cRef2");
1603	STAM_REG(pVM, &pPGM->StatTrackOverflows, STAMTYPE_COUNTER, "/PGM/Track/Overflows", STAMUNIT_OCCURENCES, "The number of times the extent list grows to long.");
1604	STAM_REG(pVM, &pPGM->StatTrackDeref, STAMTYPE_PROFILE, "/PGM/Track/Deref", STAMUNIT_OCCURENCES, "Profiling of SyncPageWorkerTrackDeref (expensive).");
1605	#endif
1606	for (i = 0; i < RT_ELEMENTS(pPGM->StatSyncPtPD); i++)
1607	STAMR3RegisterF(pVM, &pPGM->StatSyncPtPD[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
1608	"The number of SyncPT per PD n.", "/PGM/PDSyncPT/%04X", i);
1609	for (i = 0; i < RT_ELEMENTS(pPGM->StatSyncPagePD); i++)
1610	STAMR3RegisterF(pVM, &pPGM->StatSyncPagePD[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
1611	"The number of SyncPage per PD n.", "/PGM/PDSyncPage/%04X", i);
1612
1613	/* R3 only: */
1614	STAM_REG(pVM, &pPGM->StatR3DetectedConflicts, STAMTYPE_COUNTER, "/PGM/R3/DetectedConflicts", STAMUNIT_OCCURENCES, "The number of times PGMR3CheckMappingConflicts() detected a conflict.");
1615	STAM_REG(pVM, &pPGM->StatR3ResolveConflict, STAMTYPE_PROFILE, "/PGM/R3/ResolveConflict", STAMUNIT_TICKS_PER_CALL, "pgmR3SyncPTResolveConflict() profiling (includes the entire relocation).");
1616	STAM_REG(pVM, &pPGM->StatR3GuestPDWrite, STAMTYPE_COUNTER, "/PGM/R3/PDWrite", STAMUNIT_OCCURENCES, "The total number of times pgmHCGuestPDWriteHandler() was called.");
1617	STAM_REG(pVM, &pPGM->StatR3GuestPDWriteConflict, STAMTYPE_COUNTER, "/PGM/R3/PDWriteConflict", STAMUNIT_OCCURENCES, "The number of times pgmHCGuestPDWriteHandler() detected a conflict.");
1618	STAM_REG(pVM, &pPGM->StatR3DynRamTotal, STAMTYPE_COUNTER, "/PGM/DynAlloc/TotalAlloc", STAMUNIT_MEGABYTES, "Allocated MBs of guest ram.");
1619	STAM_REG(pVM, &pPGM->StatR3DynRamGrow, STAMTYPE_COUNTER, "/PGM/DynAlloc/Grow", STAMUNIT_OCCURENCES, "Nr of pgmr3PhysGrowRange calls.");
1620
1621	/* R0 only: */
1622	STAM_REG(pVM, &pPGM->StatR0DynMapMigrateInvlPg, STAMTYPE_COUNTER, "/PGM/R0/DynMapMigrateInvlPg", STAMUNIT_OCCURENCES, "invlpg count in PGMDynMapMigrateAutoSet.");
1623	STAM_REG(pVM, &pPGM->StatR0DynMapGCPageInl, STAMTYPE_PROFILE, "/PGM/R0/DynMapPageGCPageInl", STAMUNIT_TICKS_PER_CALL, "Calls to pgmR0DynMapGCPageInlined.");
1624	STAM_REG(pVM, &pPGM->StatR0DynMapGCPageInlHits, STAMTYPE_COUNTER, "/PGM/R0/DynMapPageGCPageInl/Hits", STAMUNIT_OCCURENCES, "Hash table lookup hits.");
1625	STAM_REG(pVM, &pPGM->StatR0DynMapGCPageInlMisses, STAMTYPE_COUNTER, "/PGM/R0/DynMapPageGCPageInl/Misses", STAMUNIT_OCCURENCES, "Misses that falls back to code common with PGMDynMapHCPage.");
1626	STAM_REG(pVM, &pPGM->StatR0DynMapGCPageInlRamHits, STAMTYPE_COUNTER, "/PGM/R0/DynMapPageGCPageInl/RamHits", STAMUNIT_OCCURENCES, "1st ram range hits.");
1627	STAM_REG(pVM, &pPGM->StatR0DynMapGCPageInlRamMisses, STAMTYPE_COUNTER, "/PGM/R0/DynMapPageGCPageInl/RamMisses", STAMUNIT_OCCURENCES, "1st ram range misses, takes slow path.");
1628	STAM_REG(pVM, &pPGM->StatR0DynMapHCPageInl, STAMTYPE_PROFILE, "/PGM/R0/DynMapPageHCPageInl", STAMUNIT_TICKS_PER_CALL, "Calls to pgmR0DynMapHCPageInlined.");
1629	STAM_REG(pVM, &pPGM->StatR0DynMapHCPageInlHits, STAMTYPE_COUNTER, "/PGM/R0/DynMapPageHCPageInl/Hits", STAMUNIT_OCCURENCES, "Hash table lookup hits.");
1630	STAM_REG(pVM, &pPGM->StatR0DynMapHCPageInlMisses, STAMTYPE_COUNTER, "/PGM/R0/DynMapPageHCPageInl/Misses", STAMUNIT_OCCURENCES, "Misses that falls back to code common with PGMDynMapHCPage.");
1631	STAM_REG(pVM, &pPGM->StatR0DynMapPage, STAMTYPE_COUNTER, "/PGM/R0/DynMapPage", STAMUNIT_OCCURENCES, "Calls to pgmR0DynMapPage");
1632	STAM_REG(pVM, &pPGM->StatR0DynMapSetOptimize, STAMTYPE_COUNTER, "/PGM/R0/DynMapPage/SetOptimize", STAMUNIT_OCCURENCES, "Calls to pgmDynMapOptimizeAutoSet.");
1633	STAM_REG(pVM, &pPGM->StatR0DynMapSetSearchFlushes, STAMTYPE_COUNTER, "/PGM/R0/DynMapPage/SetSearchFlushes",STAMUNIT_OCCURENCES, "Set search restorting to subset flushes.");
1634	STAM_REG(pVM, &pPGM->StatR0DynMapSetSearchHits, STAMTYPE_COUNTER, "/PGM/R0/DynMapPage/SetSearchHits", STAMUNIT_OCCURENCES, "Set search hits.");
1635	STAM_REG(pVM, &pPGM->StatR0DynMapSetSearchMisses, STAMTYPE_COUNTER, "/PGM/R0/DynMapPage/SetSearchMisses", STAMUNIT_OCCURENCES, "Set search misses.");
1636	STAM_REG(pVM, &pPGM->StatR0DynMapHCPage, STAMTYPE_PROFILE, "/PGM/R0/DynMapPage/HCPage", STAMUNIT_TICKS_PER_CALL, "Calls to PGMDynMapHCPage (ring-0).");
1637	STAM_REG(pVM, &pPGM->StatR0DynMapPageHits0, STAMTYPE_COUNTER, "/PGM/R0/DynMapPage/Hits0", STAMUNIT_OCCURENCES, "Hits at iPage+0");
1638	STAM_REG(pVM, &pPGM->StatR0DynMapPageHits1, STAMTYPE_COUNTER, "/PGM/R0/DynMapPage/Hits1", STAMUNIT_OCCURENCES, "Hits at iPage+1");
1639	STAM_REG(pVM, &pPGM->StatR0DynMapPageHits2, STAMTYPE_COUNTER, "/PGM/R0/DynMapPage/Hits2", STAMUNIT_OCCURENCES, "Hits at iPage+2");
1640	STAM_REG(pVM, &pPGM->StatR0DynMapPageInvlPg, STAMTYPE_COUNTER, "/PGM/R0/DynMapPage/InvlPg", STAMUNIT_OCCURENCES, "invlpg count in pgmR0DynMapPageSlow.");
1641	STAM_REG(pVM, &pPGM->StatR0DynMapPageSlow, STAMTYPE_COUNTER, "/PGM/R0/DynMapPage/Slow", STAMUNIT_OCCURENCES, "Calls to pgmR0DynMapPageSlow - subtract this from pgmR0DynMapPage to get 1st level hits.");
1642	STAM_REG(pVM, &pPGM->StatR0DynMapPageSlowLoopHits, STAMTYPE_COUNTER, "/PGM/R0/DynMapPage/SlowLoopHits" , STAMUNIT_OCCURENCES, "Hits in the loop path.");
1643	STAM_REG(pVM, &pPGM->StatR0DynMapPageSlowLoopMisses, STAMTYPE_COUNTER, "/PGM/R0/DynMapPage/SlowLoopMisses", STAMUNIT_OCCURENCES, "Misses in the loop path. NonLoopMisses = Slow - SlowLoopHit - SlowLoopMisses");
1644	//STAM_REG(pVM, &pPGM->StatR0DynMapPageSlowLostHits, STAMTYPE_COUNTER, "/PGM/R0/DynMapPage/SlowLostHits", STAMUNIT_OCCURENCES, "Lost hits.");
1645	STAM_REG(pVM, &pPGM->StatR0DynMapSubsets, STAMTYPE_COUNTER, "/PGM/R0/Subsets", STAMUNIT_OCCURENCES, "Times PGMDynMapPushAutoSubset was called.");
1646	STAM_REG(pVM, &pPGM->StatR0DynMapPopFlushes, STAMTYPE_COUNTER, "/PGM/R0/SubsetPopFlushes", STAMUNIT_OCCURENCES, "Times PGMDynMapPopAutoSubset flushes the subset.");
1647	STAM_REG(pVM, &pPGM->aStatR0DynMapSetSize[0], STAMTYPE_COUNTER, "/PGM/R0/SetSize000..09", STAMUNIT_OCCURENCES, "00-09% filled");
1648	STAM_REG(pVM, &pPGM->aStatR0DynMapSetSize[1], STAMTYPE_COUNTER, "/PGM/R0/SetSize010..19", STAMUNIT_OCCURENCES, "10-19% filled");
1649	STAM_REG(pVM, &pPGM->aStatR0DynMapSetSize[2], STAMTYPE_COUNTER, "/PGM/R0/SetSize020..29", STAMUNIT_OCCURENCES, "20-29% filled");
1650	STAM_REG(pVM, &pPGM->aStatR0DynMapSetSize[3], STAMTYPE_COUNTER, "/PGM/R0/SetSize030..39", STAMUNIT_OCCURENCES, "30-39% filled");
1651	STAM_REG(pVM, &pPGM->aStatR0DynMapSetSize[4], STAMTYPE_COUNTER, "/PGM/R0/SetSize040..49", STAMUNIT_OCCURENCES, "40-49% filled");
1652	STAM_REG(pVM, &pPGM->aStatR0DynMapSetSize[5], STAMTYPE_COUNTER, "/PGM/R0/SetSize050..59", STAMUNIT_OCCURENCES, "50-59% filled");
1653	STAM_REG(pVM, &pPGM->aStatR0DynMapSetSize[6], STAMTYPE_COUNTER, "/PGM/R0/SetSize060..69", STAMUNIT_OCCURENCES, "60-69% filled");
1654	STAM_REG(pVM, &pPGM->aStatR0DynMapSetSize[7], STAMTYPE_COUNTER, "/PGM/R0/SetSize070..79", STAMUNIT_OCCURENCES, "70-79% filled");
1655	STAM_REG(pVM, &pPGM->aStatR0DynMapSetSize[8], STAMTYPE_COUNTER, "/PGM/R0/SetSize080..89", STAMUNIT_OCCURENCES, "80-89% filled");
1656	STAM_REG(pVM, &pPGM->aStatR0DynMapSetSize[9], STAMTYPE_COUNTER, "/PGM/R0/SetSize090..99", STAMUNIT_OCCURENCES, "90-99% filled");
1657	STAM_REG(pVM, &pPGM->aStatR0DynMapSetSize[10], STAMTYPE_COUNTER, "/PGM/R0/SetSize100", STAMUNIT_OCCURENCES, "100% filled");
1658
1659	/* GC only: */
1660	STAM_REG(pVM, &pPGM->StatRCDynMapCacheHits, STAMTYPE_COUNTER, "/PGM/RC/DynMapCache/Hits" , STAMUNIT_OCCURENCES, "Number of dynamic page mapping cache hits.");
1661	STAM_REG(pVM, &pPGM->StatRCDynMapCacheMisses, STAMTYPE_COUNTER, "/PGM/RC/DynMapCache/Misses" , STAMUNIT_OCCURENCES, "Number of dynamic page mapping cache misses.");
1662	STAM_REG(pVM, &pPGM->StatRCInvlPgConflict, STAMTYPE_COUNTER, "/PGM/RC/InvlPgConflict", STAMUNIT_OCCURENCES, "Number of times PGMInvalidatePage() detected a mapping conflict.");
1663	STAM_REG(pVM, &pPGM->StatRCInvlPgSyncMonCR3, STAMTYPE_COUNTER, "/PGM/RC/InvlPgSyncMonitorCR3", STAMUNIT_OCCURENCES, "Number of times PGMInvalidatePage() ran into PGM_SYNC_MONITOR_CR3.");
1664
1665	/* RZ only: */
1666	STAM_REG(pVM, &pPGM->StatRZTrap0e, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMTrap0eHandler() body.");
1667	STAM_REG(pVM, &pPGM->StatRZTrap0eTimeCheckPageFault, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time/CheckPageFault", STAMUNIT_TICKS_PER_CALL, "Profiling of checking for dirty/access emulation faults.");
1668	STAM_REG(pVM, &pPGM->StatRZTrap0eTimeSyncPT, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time/SyncPT", STAMUNIT_TICKS_PER_CALL, "Profiling of lazy page table syncing.");
1669	STAM_REG(pVM, &pPGM->StatRZTrap0eTimeMapping, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time/Mapping", STAMUNIT_TICKS_PER_CALL, "Profiling of checking virtual mappings.");
1670	STAM_REG(pVM, &pPGM->StatRZTrap0eTimeOutOfSync, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time/OutOfSync", STAMUNIT_TICKS_PER_CALL, "Profiling of out of sync page handling.");
1671	STAM_REG(pVM, &pPGM->StatRZTrap0eTimeHandlers, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time/Handlers", STAMUNIT_TICKS_PER_CALL, "Profiling of checking handlers.");
1672	STAM_REG(pVM, &pPGM->StatRZTrap0eTime2CSAM, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time2/CSAM", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is CSAM.");
1673	STAM_REG(pVM, &pPGM->StatRZTrap0eTime2DirtyAndAccessed, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time2/DirtyAndAccessedBits", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is dirty and/or accessed bit emulation.");
1674	STAM_REG(pVM, &pPGM->StatRZTrap0eTime2GuestTrap, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time2/GuestTrap", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is a guest trap.");
1675	STAM_REG(pVM, &pPGM->StatRZTrap0eTime2HndPhys, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time2/HandlerPhysical", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is a physical handler.");
1676	STAM_REG(pVM, &pPGM->StatRZTrap0eTime2HndVirt, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time2/HandlerVirtual", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is a virtual handler.");
1677	STAM_REG(pVM, &pPGM->StatRZTrap0eTime2HndUnhandled, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time2/HandlerUnhandled", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is access outside the monitored areas of a monitored page.");
1678	STAM_REG(pVM, &pPGM->StatRZTrap0eTime2Misc, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time2/Misc", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is not known.");
1679	STAM_REG(pVM, &pPGM->StatRZTrap0eTime2OutOfSync, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time2/OutOfSync", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is an out-of-sync page.");
1680	STAM_REG(pVM, &pPGM->StatRZTrap0eTime2OutOfSyncHndPhys, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time2/OutOfSyncHndPhys", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is an out-of-sync physical handler page.");
1681	STAM_REG(pVM, &pPGM->StatRZTrap0eTime2OutOfSyncHndVirt, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time2/OutOfSyncHndVirt", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is an out-of-sync virtual handler page.");
1682	STAM_REG(pVM, &pPGM->StatRZTrap0eTime2OutOfSyncHndObs, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time2/OutOfSyncObsHnd", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is an obsolete handler page.");
1683	STAM_REG(pVM, &pPGM->StatRZTrap0eTime2SyncPT, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time2/SyncPT", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is lazy syncing of a PT.");
1684	STAM_REG(pVM, &pPGM->StatRZTrap0eConflicts, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Conflicts", STAMUNIT_OCCURENCES, "The number of times #PF was caused by an undetected conflict.");
1685	STAM_REG(pVM, &pPGM->StatRZTrap0eHandlersMapping, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Handlers/Mapping", STAMUNIT_OCCURENCES, "Number of traps due to access handlers in mappings.");
1686	STAM_REG(pVM, &pPGM->StatRZTrap0eHandlersOutOfSync, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Handlers/OutOfSync", STAMUNIT_OCCURENCES, "Number of traps due to out-of-sync handled pages.");
1687	STAM_REG(pVM, &pPGM->StatRZTrap0eHandlersPhysical, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Handlers/Physical", STAMUNIT_OCCURENCES, "Number of traps due to physical access handlers.");
1688	STAM_REG(pVM, &pPGM->StatRZTrap0eHandlersVirtual, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Handlers/Virtual", STAMUNIT_OCCURENCES, "Number of traps due to virtual access handlers.");
1689	STAM_REG(pVM, &pPGM->StatRZTrap0eHandlersVirtualByPhys, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Handlers/VirtualByPhys", STAMUNIT_OCCURENCES, "Number of traps due to virtual access handlers by physical address.");
1690	STAM_REG(pVM, &pPGM->StatRZTrap0eHandlersVirtualUnmarked,STAMTYPE_COUNTER,"/PGM/RZ/Trap0e/Handlers/VirtualUnmarked",STAMUNIT_OCCURENCES, "Number of traps due to virtual access handlers by virtual address (without proper physical flags).");
1691	STAM_REG(pVM, &pPGM->StatRZTrap0eHandlersUnhandled, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Handlers/Unhandled", STAMUNIT_OCCURENCES, "Number of traps due to access outside range of monitored page(s).");
1692	STAM_REG(pVM, &pPGM->StatRZTrap0eHandlersInvalid, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Handlers/Invalid", STAMUNIT_OCCURENCES, "Number of traps due to access to invalid physical memory.");
1693	STAM_REG(pVM, &pPGM->StatRZTrap0eUSNotPresentRead, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Err/User/NPRead", STAMUNIT_OCCURENCES, "Number of user mode not present read page faults.");
1694	STAM_REG(pVM, &pPGM->StatRZTrap0eUSNotPresentWrite, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Err/User/NPWrite", STAMUNIT_OCCURENCES, "Number of user mode not present write page faults.");
1695	STAM_REG(pVM, &pPGM->StatRZTrap0eUSWrite, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Err/User/Write", STAMUNIT_OCCURENCES, "Number of user mode write page faults.");
1696	STAM_REG(pVM, &pPGM->StatRZTrap0eUSReserved, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Err/User/Reserved", STAMUNIT_OCCURENCES, "Number of user mode reserved bit page faults.");
1697	STAM_REG(pVM, &pPGM->StatRZTrap0eUSNXE, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Err/User/NXE", STAMUNIT_OCCURENCES, "Number of user mode NXE page faults.");
1698	STAM_REG(pVM, &pPGM->StatRZTrap0eUSRead, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Err/User/Read", STAMUNIT_OCCURENCES, "Number of user mode read page faults.");
1699	STAM_REG(pVM, &pPGM->StatRZTrap0eSVNotPresentRead, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Err/Supervisor/NPRead", STAMUNIT_OCCURENCES, "Number of supervisor mode not present read page faults.");
1700	STAM_REG(pVM, &pPGM->StatRZTrap0eSVNotPresentWrite, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Err/Supervisor/NPWrite", STAMUNIT_OCCURENCES, "Number of supervisor mode not present write page faults.");
1701	STAM_REG(pVM, &pPGM->StatRZTrap0eSVWrite, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Err/Supervisor/Write", STAMUNIT_OCCURENCES, "Number of supervisor mode write page faults.");
1702	STAM_REG(pVM, &pPGM->StatRZTrap0eSVReserved, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Err/Supervisor/Reserved", STAMUNIT_OCCURENCES, "Number of supervisor mode reserved bit page faults.");
1703	STAM_REG(pVM, &pPGM->StatRZTrap0eSNXE, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Err/Supervisor/NXE", STAMUNIT_OCCURENCES, "Number of supervisor mode NXE page faults.");
1704	STAM_REG(pVM, &pPGM->StatRZTrap0eGuestPF, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/GuestPF", STAMUNIT_OCCURENCES, "Number of real guest page faults.");
1705	STAM_REG(pVM, &pPGM->StatRZTrap0eGuestPFUnh, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/GuestPF/Unhandled", STAMUNIT_OCCURENCES, "Number of real guest page faults from the 'unhandled' case.");
1706	STAM_REG(pVM, &pPGM->StatRZTrap0eGuestPFMapping, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/GuestPF/InMapping", STAMUNIT_OCCURENCES, "Number of real guest page faults in a mapping.");
1707	STAM_REG(pVM, &pPGM->StatRZTrap0eWPEmulInRZ, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/WP/InRZ", STAMUNIT_OCCURENCES, "Number of guest page faults due to X86_CR0_WP emulation.");
1708	STAM_REG(pVM, &pPGM->StatRZTrap0eWPEmulToR3, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/WP/ToR3", STAMUNIT_OCCURENCES, "Number of guest page faults due to X86_CR0_WP emulation (forward to R3 for emulation).");
1709	for (i = 0; i < RT_ELEMENTS(pPGM->StatRZTrap0ePD); i++)
1710	STAMR3RegisterF(pVM, &pPGM->StatRZTrap0ePD[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
1711	"The number of traps in page directory n.", "/PGM/RZ/Trap0e/PD/%04X", i);
1712	STAM_REG(pVM, &pPGM->StatRZGuestCR3WriteHandled, STAMTYPE_COUNTER, "/PGM/RZ/CR3WriteHandled", STAMUNIT_OCCURENCES, "The number of times the Guest CR3 change was successfully handled.");
1713	STAM_REG(pVM, &pPGM->StatRZGuestCR3WriteUnhandled, STAMTYPE_COUNTER, "/PGM/RZ/CR3WriteUnhandled", STAMUNIT_OCCURENCES, "The number of times the Guest CR3 change was passed back to the recompiler.");
1714	STAM_REG(pVM, &pPGM->StatRZGuestCR3WriteConflict, STAMTYPE_COUNTER, "/PGM/RZ/CR3WriteConflict", STAMUNIT_OCCURENCES, "The number of times the Guest CR3 monitoring detected a conflict.");
1715	STAM_REG(pVM, &pPGM->StatRZGuestROMWriteHandled, STAMTYPE_COUNTER, "/PGM/RZ/ROMWriteHandled", STAMUNIT_OCCURENCES, "The number of times the Guest ROM change was successfully handled.");
1716	STAM_REG(pVM, &pPGM->StatRZGuestROMWriteUnhandled, STAMTYPE_COUNTER, "/PGM/RZ/ROMWriteUnhandled", STAMUNIT_OCCURENCES, "The number of times the Guest ROM change was passed back to the recompiler.");
1717
1718	/* HC only: */
1719
1720	/* RZ & R3: */
1721	STAM_REG(pVM, &pPGM->StatRZSyncCR3, STAMTYPE_PROFILE, "/PGM/RZ/SyncCR3", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMSyncCR3() body.");
1722	STAM_REG(pVM, &pPGM->StatRZSyncCR3Handlers, STAMTYPE_PROFILE, "/PGM/RZ/SyncCR3/Handlers", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMSyncCR3() update handler section.");
1723	STAM_REG(pVM, &pPGM->StatRZSyncCR3HandlerVirtualUpdate, STAMTYPE_PROFILE, "/PGM/RZ/SyncCR3/Handlers/VirtualUpdate", STAMUNIT_TICKS_PER_CALL, "Profiling of the virtual handler updates.");
1724	STAM_REG(pVM, &pPGM->StatRZSyncCR3HandlerVirtualReset, STAMTYPE_PROFILE, "/PGM/RZ/SyncCR3/Handlers/VirtualReset", STAMUNIT_TICKS_PER_CALL, "Profiling of the virtual handler resets.");
1725	STAM_REG(pVM, &pPGM->StatRZSyncCR3Global, STAMTYPE_COUNTER, "/PGM/RZ/SyncCR3/Global", STAMUNIT_OCCURENCES, "The number of global CR3 syncs.");
1726	STAM_REG(pVM, &pPGM->StatRZSyncCR3NotGlobal, STAMTYPE_COUNTER, "/PGM/RZ/SyncCR3/NotGlobal", STAMUNIT_OCCURENCES, "The number of non-global CR3 syncs.");
1727	STAM_REG(pVM, &pPGM->StatRZSyncCR3DstCacheHit, STAMTYPE_COUNTER, "/PGM/RZ/SyncCR3/DstChacheHit", STAMUNIT_OCCURENCES, "The number of times we got some kind of a cache hit.");
1728	STAM_REG(pVM, &pPGM->StatRZSyncCR3DstFreed, STAMTYPE_COUNTER, "/PGM/RZ/SyncCR3/DstFreed", STAMUNIT_OCCURENCES, "The number of times we've had to free a shadow entry.");
1729	STAM_REG(pVM, &pPGM->StatRZSyncCR3DstFreedSrcNP, STAMTYPE_COUNTER, "/PGM/RZ/SyncCR3/DstFreedSrcNP", STAMUNIT_OCCURENCES, "The number of times we've had to free a shadow entry for which the source entry was not present.");
1730	STAM_REG(pVM, &pPGM->StatRZSyncCR3DstNotPresent, STAMTYPE_COUNTER, "/PGM/RZ/SyncCR3/DstNotPresent", STAMUNIT_OCCURENCES, "The number of times we've encountered a not present shadow entry for a present guest entry.");
1731	STAM_REG(pVM, &pPGM->StatRZSyncCR3DstSkippedGlobalPD, STAMTYPE_COUNTER, "/PGM/RZ/SyncCR3/DstSkippedGlobalPD", STAMUNIT_OCCURENCES, "The number of times a global page directory wasn't flushed.");
1732	STAM_REG(pVM, &pPGM->StatRZSyncCR3DstSkippedGlobalPT, STAMTYPE_COUNTER, "/PGM/RZ/SyncCR3/DstSkippedGlobalPT", STAMUNIT_OCCURENCES, "The number of times a page table with only global entries wasn't flushed.");
1733	STAM_REG(pVM, &pPGM->StatRZSyncPT, STAMTYPE_PROFILE, "/PGM/RZ/SyncPT", STAMUNIT_TICKS_PER_CALL, "Profiling of the pfnSyncPT() body.");
1734	STAM_REG(pVM, &pPGM->StatRZSyncPTFailed, STAMTYPE_COUNTER, "/PGM/RZ/SyncPT/Failed", STAMUNIT_OCCURENCES, "The number of times pfnSyncPT() failed.");
1735	STAM_REG(pVM, &pPGM->StatRZSyncPT4K, STAMTYPE_COUNTER, "/PGM/RZ/SyncPT/4K", STAMUNIT_OCCURENCES, "Nr of 4K PT syncs");
1736	STAM_REG(pVM, &pPGM->StatRZSyncPT4M, STAMTYPE_COUNTER, "/PGM/RZ/SyncPT/4M", STAMUNIT_OCCURENCES, "Nr of 4M PT syncs");
1737	STAM_REG(pVM, &pPGM->StatRZSyncPagePDNAs, STAMTYPE_COUNTER, "/PGM/RZ/SyncPagePDNAs", STAMUNIT_OCCURENCES, "The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit.");
1738	STAM_REG(pVM, &pPGM->StatRZSyncPagePDOutOfSync, STAMTYPE_COUNTER, "/PGM/RZ/SyncPagePDOutOfSync", STAMUNIT_OCCURENCES, "The number of time we've encountered an out-of-sync PD in SyncPage.");
1739	STAM_REG(pVM, &pPGM->StatRZAccessedPage, STAMTYPE_COUNTER, "/PGM/RZ/AccessedPage", STAMUNIT_OCCURENCES, "The number of pages marked not present for accessed bit emulation.");
1740	STAM_REG(pVM, &pPGM->StatRZDirtyBitTracking, STAMTYPE_PROFILE, "/PGM/RZ/DirtyPage", STAMUNIT_TICKS_PER_CALL, "Profiling the dirty bit tracking in CheckPageFault().");
1741	STAM_REG(pVM, &pPGM->StatRZDirtyPage, STAMTYPE_COUNTER, "/PGM/RZ/DirtyPage/Mark", STAMUNIT_OCCURENCES, "The number of pages marked read-only for dirty bit tracking.");
1742	STAM_REG(pVM, &pPGM->StatRZDirtyPageBig, STAMTYPE_COUNTER, "/PGM/RZ/DirtyPage/MarkBig", STAMUNIT_OCCURENCES, "The number of 4MB pages marked read-only for dirty bit tracking.");
1743	STAM_REG(pVM, &pPGM->StatRZDirtyPageSkipped, STAMTYPE_COUNTER, "/PGM/RZ/DirtyPage/Skipped", STAMUNIT_OCCURENCES, "The number of pages already dirty or readonly.");
1744	STAM_REG(pVM, &pPGM->StatRZDirtyPageTrap, STAMTYPE_COUNTER, "/PGM/RZ/DirtyPage/Trap", STAMUNIT_OCCURENCES, "The number of traps generated for dirty bit tracking.");
1745	STAM_REG(pVM, &pPGM->StatRZDirtiedPage, STAMTYPE_COUNTER, "/PGM/RZ/DirtyPage/SetDirty", STAMUNIT_OCCURENCES, "The number of pages marked dirty because of write accesses.");
1746	STAM_REG(pVM, &pPGM->StatRZDirtyTrackRealPF, STAMTYPE_COUNTER, "/PGM/RZ/DirtyPage/RealPF", STAMUNIT_OCCURENCES, "The number of real pages faults during dirty bit tracking.");
1747	STAM_REG(pVM, &pPGM->StatRZPageAlreadyDirty, STAMTYPE_COUNTER, "/PGM/RZ/DirtyPage/AlreadySet", STAMUNIT_OCCURENCES, "The number of pages already marked dirty because of write accesses.");
1748	STAM_REG(pVM, &pPGM->StatRZInvalidatePage, STAMTYPE_PROFILE, "/PGM/RZ/InvalidatePage", STAMUNIT_TICKS_PER_CALL, "PGMInvalidatePage() profiling.");
1749	STAM_REG(pVM, &pPGM->StatRZInvalidatePage4KBPages, STAMTYPE_COUNTER, "/PGM/RZ/InvalidatePage/4KBPages", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was called for a 4KB page.");
1750	STAM_REG(pVM, &pPGM->StatRZInvalidatePage4MBPages, STAMTYPE_COUNTER, "/PGM/RZ/InvalidatePage/4MBPages", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was called for a 4MB page.");
1751	STAM_REG(pVM, &pPGM->StatRZInvalidatePage4MBPagesSkip, STAMTYPE_COUNTER, "/PGM/RZ/InvalidatePage/4MBPagesSkip",STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() skipped a 4MB page.");
1752	STAM_REG(pVM, &pPGM->StatRZInvalidatePagePDMappings, STAMTYPE_COUNTER, "/PGM/RZ/InvalidatePage/PDMappings", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict).");
1753	STAM_REG(pVM, &pPGM->StatRZInvalidatePagePDNAs, STAMTYPE_COUNTER, "/PGM/RZ/InvalidatePage/PDNAs", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was called for a not accessed page directory.");
1754	STAM_REG(pVM, &pPGM->StatRZInvalidatePagePDNPs, STAMTYPE_COUNTER, "/PGM/RZ/InvalidatePage/PDNPs", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was called for a not present page directory.");
1755	STAM_REG(pVM, &pPGM->StatRZInvalidatePagePDOutOfSync, STAMTYPE_COUNTER, "/PGM/RZ/InvalidatePage/PDOutOfSync", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was called for an out of sync page directory.");
1756	STAM_REG(pVM, &pPGM->StatRZInvalidatePageSkipped, STAMTYPE_COUNTER, "/PGM/RZ/InvalidatePage/Skipped", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3.");
1757	STAM_REG(pVM, &pPGM->StatRZVirtHandlerSearchByPhys, STAMTYPE_PROFILE, "/PGM/RZ/VirtHandlerSearchByPhys", STAMUNIT_TICKS_PER_CALL, "Profiling of pgmHandlerVirtualFindByPhysAddr.");
1758	STAM_REG(pVM, &pPGM->StatRZPhysHandlerReset, STAMTYPE_COUNTER, "/PGM/RZ/PhysHandlerReset", STAMUNIT_OCCURENCES, "The number of times PGMHandlerPhysicalReset is called.");
1759	STAM_REG(pVM, &pPGM->StatRZPageOutOfSyncSupervisor, STAMTYPE_COUNTER, "/PGM/RZ/OutOfSync/SuperVisor", STAMUNIT_OCCURENCES, "Number of traps due to pages out of sync and times VerifyAccessSyncPage calls SyncPage.");
1760	STAM_REG(pVM, &pPGM->StatRZPageOutOfSyncUser, STAMTYPE_COUNTER, "/PGM/RZ/OutOfSync/User", STAMUNIT_OCCURENCES, "Number of traps due to pages out of sync and times VerifyAccessSyncPage calls SyncPage.");
1761	STAM_REG(pVM, &pPGM->StatRZPrefetch, STAMTYPE_PROFILE, "/PGM/RZ/Prefetch", STAMUNIT_TICKS_PER_CALL, "PGMPrefetchPage profiling.");
1762	STAM_REG(pVM, &pPGM->StatRZChunkR3MapTlbHits, STAMTYPE_COUNTER, "/PGM/ChunkR3Map/TlbHitsRZ", STAMUNIT_OCCURENCES, "TLB hits.");
1763	STAM_REG(pVM, &pPGM->StatRZChunkR3MapTlbMisses, STAMTYPE_COUNTER, "/PGM/ChunkR3Map/TlbMissesRZ", STAMUNIT_OCCURENCES, "TLB misses.");
1764	STAM_REG(pVM, &pPGM->StatRZPageMapTlbHits, STAMTYPE_COUNTER, "/PGM/RZ/Page/MapTlbHits", STAMUNIT_OCCURENCES, "TLB hits.");
1765	STAM_REG(pVM, &pPGM->StatRZPageMapTlbMisses, STAMTYPE_COUNTER, "/PGM/RZ/Page/MapTlbMisses", STAMUNIT_OCCURENCES, "TLB misses.");
1766	STAM_REG(pVM, &pPGM->StatRZPageReplaceShared, STAMTYPE_COUNTER, "/PGM/RZ/Page/ReplacedShared", STAMUNIT_OCCURENCES, "Times a shared page was replaced.");
1767	STAM_REG(pVM, &pPGM->StatRZPageReplaceZero, STAMTYPE_COUNTER, "/PGM/RZ/Page/ReplacedZero", STAMUNIT_OCCURENCES, "Times the zero page was replaced.");
1768	/// @todo STAM_REG(pVM, &pPGM->StatRZPageHandyAllocs, STAMTYPE_COUNTER, "/PGM/RZ/Page/HandyAllocs", STAMUNIT_OCCURENCES, "Number of times we've allocated more handy pages.");
1769	STAM_REG(pVM, &pPGM->StatRZFlushTLB, STAMTYPE_PROFILE, "/PGM/RZ/FlushTLB", STAMUNIT_OCCURENCES, "Profiling of the PGMFlushTLB() body.");
1770	STAM_REG(pVM, &pPGM->StatRZFlushTLBNewCR3, STAMTYPE_COUNTER, "/PGM/RZ/FlushTLB/NewCR3", STAMUNIT_OCCURENCES, "The number of times PGMFlushTLB was called with a new CR3, non-global. (switch)");
1771	STAM_REG(pVM, &pPGM->StatRZFlushTLBNewCR3Global, STAMTYPE_COUNTER, "/PGM/RZ/FlushTLB/NewCR3Global", STAMUNIT_OCCURENCES, "The number of times PGMFlushTLB was called with a new CR3, global. (switch)");
1772	STAM_REG(pVM, &pPGM->StatRZFlushTLBSameCR3, STAMTYPE_COUNTER, "/PGM/RZ/FlushTLB/SameCR3", STAMUNIT_OCCURENCES, "The number of times PGMFlushTLB was called with the same CR3, non-global. (flush)");
1773	STAM_REG(pVM, &pPGM->StatRZFlushTLBSameCR3Global, STAMTYPE_COUNTER, "/PGM/RZ/FlushTLB/SameCR3Global", STAMUNIT_OCCURENCES, "The number of times PGMFlushTLB was called with the same CR3, global. (flush)");
1774	STAM_REG(pVM, &pPGM->StatRZGstModifyPage, STAMTYPE_PROFILE, "/PGM/RZ/GstModifyPage", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMGstModifyPage() body.");
1775
1776	STAM_REG(pVM, &pPGM->StatR3SyncCR3, STAMTYPE_PROFILE, "/PGM/R3/SyncCR3", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMSyncCR3() body.");
1777	STAM_REG(pVM, &pPGM->StatR3SyncCR3Handlers, STAMTYPE_PROFILE, "/PGM/R3/SyncCR3/Handlers", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMSyncCR3() update handler section.");
1778	STAM_REG(pVM, &pPGM->StatR3SyncCR3HandlerVirtualUpdate, STAMTYPE_PROFILE, "/PGM/R3/SyncCR3/Handlers/VirtualUpdate", STAMUNIT_TICKS_PER_CALL, "Profiling of the virtual handler updates.");
1779	STAM_REG(pVM, &pPGM->StatR3SyncCR3HandlerVirtualReset, STAMTYPE_PROFILE, "/PGM/R3/SyncCR3/Handlers/VirtualReset", STAMUNIT_TICKS_PER_CALL, "Profiling of the virtual handler resets.");
1780	STAM_REG(pVM, &pPGM->StatR3SyncCR3Global, STAMTYPE_COUNTER, "/PGM/R3/SyncCR3/Global", STAMUNIT_OCCURENCES, "The number of global CR3 syncs.");
1781	STAM_REG(pVM, &pPGM->StatR3SyncCR3NotGlobal, STAMTYPE_COUNTER, "/PGM/R3/SyncCR3/NotGlobal", STAMUNIT_OCCURENCES, "The number of non-global CR3 syncs.");
1782	STAM_REG(pVM, &pPGM->StatR3SyncCR3DstCacheHit, STAMTYPE_COUNTER, "/PGM/R3/SyncCR3/DstChacheHit", STAMUNIT_OCCURENCES, "The number of times we got some kind of a cache hit.");
1783	STAM_REG(pVM, &pPGM->StatR3SyncCR3DstFreed, STAMTYPE_COUNTER, "/PGM/R3/SyncCR3/DstFreed", STAMUNIT_OCCURENCES, "The number of times we've had to free a shadow entry.");
1784	STAM_REG(pVM, &pPGM->StatR3SyncCR3DstFreedSrcNP, STAMTYPE_COUNTER, "/PGM/R3/SyncCR3/DstFreedSrcNP", STAMUNIT_OCCURENCES, "The number of times we've had to free a shadow entry for which the source entry was not present.");
1785	STAM_REG(pVM, &pPGM->StatR3SyncCR3DstNotPresent, STAMTYPE_COUNTER, "/PGM/R3/SyncCR3/DstNotPresent", STAMUNIT_OCCURENCES, "The number of times we've encountered a not present shadow entry for a present guest entry.");
1786	STAM_REG(pVM, &pPGM->StatR3SyncCR3DstSkippedGlobalPD, STAMTYPE_COUNTER, "/PGM/R3/SyncCR3/DstSkippedGlobalPD", STAMUNIT_OCCURENCES, "The number of times a global page directory wasn't flushed.");
1787	STAM_REG(pVM, &pPGM->StatR3SyncCR3DstSkippedGlobalPT, STAMTYPE_COUNTER, "/PGM/R3/SyncCR3/DstSkippedGlobalPT", STAMUNIT_OCCURENCES, "The number of times a page table with only global entries wasn't flushed.");
1788	STAM_REG(pVM, &pPGM->StatR3SyncPT, STAMTYPE_PROFILE, "/PGM/R3/SyncPT", STAMUNIT_TICKS_PER_CALL, "Profiling of the pfnSyncPT() body.");
1789	STAM_REG(pVM, &pPGM->StatR3SyncPTFailed, STAMTYPE_COUNTER, "/PGM/R3/SyncPT/Failed", STAMUNIT_OCCURENCES, "The number of times pfnSyncPT() failed.");
1790	STAM_REG(pVM, &pPGM->StatR3SyncPT4K, STAMTYPE_COUNTER, "/PGM/R3/SyncPT/4K", STAMUNIT_OCCURENCES, "Nr of 4K PT syncs");
1791	STAM_REG(pVM, &pPGM->StatR3SyncPT4M, STAMTYPE_COUNTER, "/PGM/R3/SyncPT/4M", STAMUNIT_OCCURENCES, "Nr of 4M PT syncs");
1792	STAM_REG(pVM, &pPGM->StatR3SyncPagePDNAs, STAMTYPE_COUNTER, "/PGM/R3/SyncPagePDNAs", STAMUNIT_OCCURENCES, "The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit.");
1793	STAM_REG(pVM, &pPGM->StatR3SyncPagePDOutOfSync, STAMTYPE_COUNTER, "/PGM/R3/SyncPagePDOutOfSync", STAMUNIT_OCCURENCES, "The number of time we've encountered an out-of-sync PD in SyncPage.");
1794	STAM_REG(pVM, &pPGM->StatR3AccessedPage, STAMTYPE_COUNTER, "/PGM/R3/AccessedPage", STAMUNIT_OCCURENCES, "The number of pages marked not present for accessed bit emulation.");
1795	STAM_REG(pVM, &pPGM->StatR3DirtyBitTracking, STAMTYPE_PROFILE, "/PGM/R3/DirtyPage", STAMUNIT_TICKS_PER_CALL, "Profiling the dirty bit tracking in CheckPageFault().");
1796	STAM_REG(pVM, &pPGM->StatR3DirtyPage, STAMTYPE_COUNTER, "/PGM/R3/DirtyPage/Mark", STAMUNIT_OCCURENCES, "The number of pages marked read-only for dirty bit tracking.");
1797	STAM_REG(pVM, &pPGM->StatR3DirtyPageBig, STAMTYPE_COUNTER, "/PGM/R3/DirtyPage/MarkBig", STAMUNIT_OCCURENCES, "The number of 4MB pages marked read-only for dirty bit tracking.");
1798	STAM_REG(pVM, &pPGM->StatR3DirtyPageSkipped, STAMTYPE_COUNTER, "/PGM/R3/DirtyPage/Skipped", STAMUNIT_OCCURENCES, "The number of pages already dirty or readonly.");
1799	STAM_REG(pVM, &pPGM->StatR3DirtyPageTrap, STAMTYPE_COUNTER, "/PGM/R3/DirtyPage/Trap", STAMUNIT_OCCURENCES, "The number of traps generated for dirty bit tracking.");
1800	STAM_REG(pVM, &pPGM->StatR3DirtiedPage, STAMTYPE_COUNTER, "/PGM/R3/DirtyPage/SetDirty", STAMUNIT_OCCURENCES, "The number of pages marked dirty because of write accesses.");
1801	STAM_REG(pVM, &pPGM->StatR3DirtyTrackRealPF, STAMTYPE_COUNTER, "/PGM/R3/DirtyPage/RealPF", STAMUNIT_OCCURENCES, "The number of real pages faults during dirty bit tracking.");
1802	STAM_REG(pVM, &pPGM->StatR3PageAlreadyDirty, STAMTYPE_COUNTER, "/PGM/R3/DirtyPage/AlreadySet", STAMUNIT_OCCURENCES, "The number of pages already marked dirty because of write accesses.");
1803	STAM_REG(pVM, &pPGM->StatR3InvalidatePage, STAMTYPE_PROFILE, "/PGM/R3/InvalidatePage", STAMUNIT_TICKS_PER_CALL, "PGMInvalidatePage() profiling.");
1804	STAM_REG(pVM, &pPGM->StatR3InvalidatePage4KBPages, STAMTYPE_COUNTER, "/PGM/R3/InvalidatePage/4KBPages", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was called for a 4KB page.");
1805	STAM_REG(pVM, &pPGM->StatR3InvalidatePage4MBPages, STAMTYPE_COUNTER, "/PGM/R3/InvalidatePage/4MBPages", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was called for a 4MB page.");
1806	STAM_REG(pVM, &pPGM->StatR3InvalidatePage4MBPagesSkip, STAMTYPE_COUNTER, "/PGM/R3/InvalidatePage/4MBPagesSkip",STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() skipped a 4MB page.");
1807	STAM_REG(pVM, &pPGM->StatR3InvalidatePagePDMappings, STAMTYPE_COUNTER, "/PGM/R3/InvalidatePage/PDMappings", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict).");
1808	STAM_REG(pVM, &pPGM->StatR3InvalidatePagePDNAs, STAMTYPE_COUNTER, "/PGM/R3/InvalidatePage/PDNAs", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was called for a not accessed page directory.");
1809	STAM_REG(pVM, &pPGM->StatR3InvalidatePagePDNPs, STAMTYPE_COUNTER, "/PGM/R3/InvalidatePage/PDNPs", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was called for a not present page directory.");
1810	STAM_REG(pVM, &pPGM->StatR3InvalidatePagePDOutOfSync, STAMTYPE_COUNTER, "/PGM/R3/InvalidatePage/PDOutOfSync", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was called for an out of sync page directory.");
1811	STAM_REG(pVM, &pPGM->StatR3InvalidatePageSkipped, STAMTYPE_COUNTER, "/PGM/R3/InvalidatePage/Skipped", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3.");
1812	STAM_REG(pVM, &pPGM->StatR3VirtHandlerSearchByPhys, STAMTYPE_PROFILE, "/PGM/R3/VirtHandlerSearchByPhys", STAMUNIT_TICKS_PER_CALL, "Profiling of pgmHandlerVirtualFindByPhysAddr.");
1813	STAM_REG(pVM, &pPGM->StatR3PhysHandlerReset, STAMTYPE_COUNTER, "/PGM/R3/PhysHandlerReset", STAMUNIT_OCCURENCES, "The number of times PGMHandlerPhysicalReset is called.");
1814	STAM_REG(pVM, &pPGM->StatR3PageOutOfSyncSupervisor, STAMTYPE_COUNTER, "/PGM/R3/OutOfSync/SuperVisor", STAMUNIT_OCCURENCES, "Number of traps due to pages out of sync and times VerifyAccessSyncPage calls SyncPage.");
1815	STAM_REG(pVM, &pPGM->StatR3PageOutOfSyncUser, STAMTYPE_COUNTER, "/PGM/R3/OutOfSync/User", STAMUNIT_OCCURENCES, "Number of traps due to pages out of sync and times VerifyAccessSyncPage calls SyncPage.");
1816	STAM_REG(pVM, &pPGM->StatR3Prefetch, STAMTYPE_PROFILE, "/PGM/R3/Prefetch", STAMUNIT_TICKS_PER_CALL, "PGMPrefetchPage profiling.");
1817	STAM_REG(pVM, &pPGM->StatR3ChunkR3MapTlbHits, STAMTYPE_COUNTER, "/PGM/ChunkR3Map/TlbHitsR3", STAMUNIT_OCCURENCES, "TLB hits.");
1818	STAM_REG(pVM, &pPGM->StatR3ChunkR3MapTlbMisses, STAMTYPE_COUNTER, "/PGM/ChunkR3Map/TlbMissesR3", STAMUNIT_OCCURENCES, "TLB misses.");
1819	STAM_REG(pVM, &pPGM->StatR3PageMapTlbHits, STAMTYPE_COUNTER, "/PGM/R3/Page/MapTlbHits", STAMUNIT_OCCURENCES, "TLB hits.");
1820	STAM_REG(pVM, &pPGM->StatR3PageMapTlbMisses, STAMTYPE_COUNTER, "/PGM/R3/Page/MapTlbMisses", STAMUNIT_OCCURENCES, "TLB misses.");
1821	STAM_REG(pVM, &pPGM->StatR3PageReplaceShared, STAMTYPE_COUNTER, "/PGM/R3/Page/ReplacedShared", STAMUNIT_OCCURENCES, "Times a shared page was replaced.");
1822	STAM_REG(pVM, &pPGM->StatR3PageReplaceZero, STAMTYPE_COUNTER, "/PGM/R3/Page/ReplacedZero", STAMUNIT_OCCURENCES, "Times the zero page was replaced.");
1823	/// @todo STAM_REG(pVM, &pPGM->StatR3PageHandyAllocs, STAMTYPE_COUNTER, "/PGM/R3/Page/HandyAllocs", STAMUNIT_OCCURENCES, "Number of times we've allocated more handy pages.");
1824	STAM_REG(pVM, &pPGM->StatR3FlushTLB, STAMTYPE_PROFILE, "/PGM/R3/FlushTLB", STAMUNIT_OCCURENCES, "Profiling of the PGMFlushTLB() body.");
1825	STAM_REG(pVM, &pPGM->StatR3FlushTLBNewCR3, STAMTYPE_COUNTER, "/PGM/R3/FlushTLB/NewCR3", STAMUNIT_OCCURENCES, "The number of times PGMFlushTLB was called with a new CR3, non-global. (switch)");
1826	STAM_REG(pVM, &pPGM->StatR3FlushTLBNewCR3Global, STAMTYPE_COUNTER, "/PGM/R3/FlushTLB/NewCR3Global", STAMUNIT_OCCURENCES, "The number of times PGMFlushTLB was called with a new CR3, global. (switch)");
1827	STAM_REG(pVM, &pPGM->StatR3FlushTLBSameCR3, STAMTYPE_COUNTER, "/PGM/R3/FlushTLB/SameCR3", STAMUNIT_OCCURENCES, "The number of times PGMFlushTLB was called with the same CR3, non-global. (flush)");
1828	STAM_REG(pVM, &pPGM->StatR3FlushTLBSameCR3Global, STAMTYPE_COUNTER, "/PGM/R3/FlushTLB/SameCR3Global", STAMUNIT_OCCURENCES, "The number of times PGMFlushTLB was called with the same CR3, global. (flush)");
1829	STAM_REG(pVM, &pPGM->StatR3GstModifyPage, STAMTYPE_PROFILE, "/PGM/R3/GstModifyPage", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMGstModifyPage() body.");
1830
1831	}
1832	#endif /* VBOX_WITH_STATISTICS */
1833
1834
1835	/**
1836	* Init the PGM bits that rely on VMMR0 and MM to be fully initialized.
1837	*
1838	* The dynamic mapping area will also be allocated and initialized at this
1839	* time. We could allocate it during PGMR3Init of course, but the mapping
1840	* wouldn't be allocated at that time preventing us from setting up the
1841	* page table entries with the dummy page.
1842	*
1843	* @returns VBox status code.
1844	* @param pVM VM handle.
1845	*/
1846	VMMR3DECL(int) PGMR3InitDynMap(PVM pVM)
1847	{
1848	RTGCPTR GCPtr;
1849	int rc;
1850
1851	#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
1852	/*
1853	* Reserve space for mapping the paging pages into guest context.
1854	*/
1855	rc = MMR3HyperReserve(pVM, PAGE_SIZE * (2 + RT_ELEMENTS(pVM->pgm.s.apShwPaePDsR3) + 1 + 2 + 2), "Paging", &GCPtr);
1856	AssertRCReturn(rc, rc);
1857	pVM->pgm.s.pShw32BitPdRC = GCPtr;
1858	MMR3HyperReserve(pVM, PAGE_SIZE, "fence", NULL);
1859	#endif
1860
1861	/*
1862	* Reserve space for the dynamic mappings.
1863	*/
1864	rc = MMR3HyperReserve(pVM, MM_HYPER_DYNAMIC_SIZE, "Dynamic mapping", &GCPtr);
1865	if (RT_SUCCESS(rc))
1866	pVM->pgm.s.pbDynPageMapBaseGC = GCPtr;
1867
1868	if ( RT_SUCCESS(rc)
1869	&& (pVM->pgm.s.pbDynPageMapBaseGC >> X86_PD_PAE_SHIFT) != ((pVM->pgm.s.pbDynPageMapBaseGC + MM_HYPER_DYNAMIC_SIZE - 1) >> X86_PD_PAE_SHIFT))
1870	{
1871	rc = MMR3HyperReserve(pVM, MM_HYPER_DYNAMIC_SIZE, "Dynamic mapping not crossing", &GCPtr);
1872	if (RT_SUCCESS(rc))
1873	pVM->pgm.s.pbDynPageMapBaseGC = GCPtr;
1874	}
1875	if (RT_SUCCESS(rc))
1876	{
1877	AssertRelease((pVM->pgm.s.pbDynPageMapBaseGC >> X86_PD_PAE_SHIFT) == ((pVM->pgm.s.pbDynPageMapBaseGC + MM_HYPER_DYNAMIC_SIZE - 1) >> X86_PD_PAE_SHIFT));
1878	MMR3HyperReserve(pVM, PAGE_SIZE, "fence", NULL);
1879	}
1880	return rc;
1881	}
1882
1883
1884	/**
1885	* Ring-3 init finalizing.
1886	*
1887	* @returns VBox status code.
1888	* @param pVM The VM handle.
1889	*/
1890	VMMR3DECL(int) PGMR3InitFinalize(PVM pVM)
1891	{
1892	int rc;
1893
1894	#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
1895	/*
1896	* Map the paging pages into the guest context.
1897	*/
1898	RTGCPTR GCPtr = pVM->pgm.s.pShw32BitPdRC;
1899	AssertReleaseReturn(GCPtr, VERR_INTERNAL_ERROR);
1900
1901	rc = PGMMap(pVM, GCPtr, pVM->pgm.s.HCPhysShw32BitPD, PAGE_SIZE, 0);
1902	AssertRCReturn(rc, rc);
1903	pVM->pgm.s.pShw32BitPdRC = GCPtr;
1904	GCPtr += PAGE_SIZE;
1905	GCPtr += PAGE_SIZE; /* reserved page */
1906
1907	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.apShwPaePDsR3); i++)
1908	{
1909	rc = PGMMap(pVM, GCPtr, pVM->pgm.s.aHCPhysPaePDs[i], PAGE_SIZE, 0);
1910	AssertRCReturn(rc, rc);
1911	pVM->pgm.s.apShwPaePDsRC[i] = GCPtr;
1912	GCPtr += PAGE_SIZE;
1913	}
1914	/* A bit of paranoia is justified. */
1915	AssertRelease(pVM->pgm.s.apShwPaePDsRC[0] + PAGE_SIZE == pVM->pgm.s.apShwPaePDsRC[1]);
1916	AssertRelease(pVM->pgm.s.apShwPaePDsRC[1] + PAGE_SIZE == pVM->pgm.s.apShwPaePDsRC[2]);
1917	AssertRelease(pVM->pgm.s.apShwPaePDsRC[2] + PAGE_SIZE == pVM->pgm.s.apShwPaePDsRC[3]);
1918	GCPtr += PAGE_SIZE; /* reserved page */
1919
1920	rc = PGMMap(pVM, GCPtr, pVM->pgm.s.HCPhysShwPaePdpt, PAGE_SIZE, 0);
1921	AssertRCReturn(rc, rc);
1922	pVM->pgm.s.pShwPaePdptRC = GCPtr;
1923	GCPtr += PAGE_SIZE;
1924	GCPtr += PAGE_SIZE; /* reserved page */
1925	#endif
1926
1927	/*
1928	* Reserve space for the dynamic mappings.
1929	* Initialize the dynamic mapping pages with dummy pages to simply the cache.
1930	*/
1931	/* get the pointer to the page table entries. */
1932	PPGMMAPPING pMapping = pgmGetMapping(pVM, pVM->pgm.s.pbDynPageMapBaseGC);
1933	AssertRelease(pMapping);
1934	const uintptr_t off = pVM->pgm.s.pbDynPageMapBaseGC - pMapping->GCPtr;
1935	const unsigned iPT = off >> X86_PD_SHIFT;
1936	const unsigned iPG = (off >> X86_PT_SHIFT) & X86_PT_MASK;
1937	pVM->pgm.s.paDynPageMap32BitPTEsGC = pMapping->aPTs[iPT].pPTRC + iPG * sizeof(pMapping->aPTs[0].pPTR3->a[0]);
1938	pVM->pgm.s.paDynPageMapPaePTEsGC = pMapping->aPTs[iPT].paPaePTsRC + iPG * sizeof(pMapping->aPTs[0].paPaePTsR3->a[0]);
1939
1940	/* init cache */
1941	RTHCPHYS HCPhysDummy = MMR3PageDummyHCPhys(pVM);
1942	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.aHCPhysDynPageMapCache); i++)
1943	pVM->pgm.s.aHCPhysDynPageMapCache[i] = HCPhysDummy;
1944
1945	for (unsigned i = 0; i < MM_HYPER_DYNAMIC_SIZE; i += PAGE_SIZE)
1946	{
1947	rc = PGMMap(pVM, pVM->pgm.s.pbDynPageMapBaseGC + i, HCPhysDummy, PAGE_SIZE, 0);
1948	AssertRCReturn(rc, rc);
1949	}
1950
1951	/*
1952	* Note that AMD uses all the 8 reserved bits for the address (so 40 bits in total);
1953	* Intel only goes up to 36 bits, so we stick to 36 as well.
1954	*/
1955	/** @todo How to test for the 40 bits support? Long mode seems to be the test criterium. */
1956	uint32_t u32Dummy, u32Features;
1957	CPUMGetGuestCpuId(pVM, 1, &u32Dummy, &u32Dummy, &u32Dummy, &u32Features);
1958
1959	if (u32Features & X86_CPUID_FEATURE_EDX_PSE36)
1960	pVM->pgm.s.GCPhys4MBPSEMask = RT_BIT_64(36) - 1;
1961	else
1962	pVM->pgm.s.GCPhys4MBPSEMask = RT_BIT_64(32) - 1;
1963
1964	LogRel(("PGMR3InitFinalize: 4 MB PSE mask %RGp\n", pVM->pgm.s.GCPhys4MBPSEMask));
1965	return rc;
1966	}
1967
1968
1969	/**
1970	* Applies relocations to data and code managed by this component.
1971	*
1972	* This function will be called at init and whenever the VMM need to relocate it
1973	* self inside the GC.
1974	*
1975	* @param pVM The VM.
1976	* @param offDelta Relocation delta relative to old location.
1977	*/
1978	VMMR3DECL(void) PGMR3Relocate(PVM pVM, RTGCINTPTR offDelta)
1979	{
1980	LogFlow(("PGMR3Relocate\n"));
1981
1982	/*
1983	* Paging stuff.
1984	*/
1985	pVM->pgm.s.GCPtrCR3Mapping += offDelta;
1986	/** @todo move this into shadow and guest specific relocation functions. */
1987	#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
1988	AssertMsg(pVM->pgm.s.pShwNestedRootR3, ("Init order, no relocation before paging is initialized!\n"));
1989	#else
1990	AssertMsg(pVM->pgm.s.pShw32BitPdR3, ("Init order, no relocation before paging is initialized!\n"));
1991	pVM->pgm.s.pShw32BitPdRC += offDelta;
1992	#endif
1993	pVM->pgm.s.pGst32BitPdRC += offDelta;
1994	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.apGstPaePDsRC); i++)
1995	{
1996	#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
1997	AssertCompile(RT_ELEMENTS(pVM->pgm.s.apShwPaePDsRC) == RT_ELEMENTS(pVM->pgm.s.apGstPaePDsRC));
1998	pVM->pgm.s.apShwPaePDsRC[i] += offDelta;
1999	#endif
2000	pVM->pgm.s.apGstPaePDsRC[i] += offDelta;
2001	}
2002	pVM->pgm.s.pGstPaePdptRC += offDelta;
2003	#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
2004	pVM->pgm.s.pShwPaePdptRC += offDelta;
2005	#endif
2006
2007	#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
2008	pVM->pgm.s.pShwPageCR3RC += offDelta;
2009	#endif
2010
2011	pgmR3ModeDataInit(pVM, true /* resolve GC/R0 symbols */);
2012	pgmR3ModeDataSwitch(pVM, pVM->pgm.s.enmShadowMode, pVM->pgm.s.enmGuestMode);
2013
2014	PGM_SHW_PFN(Relocate, pVM)(pVM, offDelta);
2015	PGM_GST_PFN(Relocate, pVM)(pVM, offDelta);
2016	PGM_BTH_PFN(Relocate, pVM)(pVM, offDelta);
2017
2018	/*
2019	* Trees.
2020	*/
2021	pVM->pgm.s.pTreesRC = MMHyperR3ToRC(pVM, pVM->pgm.s.pTreesR3);
2022
2023	/*
2024	* Ram ranges.
2025	*/
2026	if (pVM->pgm.s.pRamRangesR3)
2027	{
2028	pVM->pgm.s.pRamRangesRC = MMHyperR3ToRC(pVM, pVM->pgm.s.pRamRangesR3);
2029	for (PPGMRAMRANGE pCur = pVM->pgm.s.pRamRangesR3; pCur->pNextR3; pCur = pCur->pNextR3)
2030	pCur->pNextRC = MMHyperR3ToRC(pVM, pCur->pNextR3);
2031	}
2032
2033	/*
2034	* Update the two page directories with all page table mappings.
2035	* (One or more of them have changed, that's why we're here.)
2036	*/
2037	pVM->pgm.s.pMappingsRC = MMHyperR3ToRC(pVM, pVM->pgm.s.pMappingsR3);
2038	for (PPGMMAPPING pCur = pVM->pgm.s.pMappingsR3; pCur->pNextR3; pCur = pCur->pNextR3)
2039	pCur->pNextRC = MMHyperR3ToRC(pVM, pCur->pNextR3);
2040
2041	/* Relocate GC addresses of Page Tables. */
2042	for (PPGMMAPPING pCur = pVM->pgm.s.pMappingsR3; pCur; pCur = pCur->pNextR3)
2043	{
2044	for (RTHCUINT i = 0; i < pCur->cPTs; i++)
2045	{
2046	pCur->aPTs[i].pPTRC = MMHyperR3ToRC(pVM, pCur->aPTs[i].pPTR3);
2047	pCur->aPTs[i].paPaePTsRC = MMHyperR3ToRC(pVM, pCur->aPTs[i].paPaePTsR3);
2048	}
2049	}
2050
2051	/*
2052	* Dynamic page mapping area.
2053	*/
2054	pVM->pgm.s.paDynPageMap32BitPTEsGC += offDelta;
2055	pVM->pgm.s.paDynPageMapPaePTEsGC += offDelta;
2056	pVM->pgm.s.pbDynPageMapBaseGC += offDelta;
2057
2058	/*
2059	* The Zero page.
2060	*/
2061	pVM->pgm.s.pvZeroPgR0 = MMHyperR3ToR0(pVM, pVM->pgm.s.pvZeroPgR3);
2062	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
2063	AssertRelease(pVM->pgm.s.pvZeroPgR0 != NIL_RTR0PTR \|\| !VMMIsHwVirtExtForced(pVM));
2064	#else
2065	AssertRelease(pVM->pgm.s.pvZeroPgR0 != NIL_RTR0PTR);
2066	#endif
2067
2068	/*
2069	* Physical and virtual handlers.
2070	*/
2071	RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysHandlers, true, pgmR3RelocatePhysHandler, &offDelta);
2072	RTAvlroGCPtrDoWithAll(&pVM->pgm.s.pTreesR3->VirtHandlers, true, pgmR3RelocateVirtHandler, &offDelta);
2073	RTAvlroGCPtrDoWithAll(&pVM->pgm.s.pTreesR3->HyperVirtHandlers, true, pgmR3RelocateHyperVirtHandler, &offDelta);
2074
2075	/*
2076	* The page pool.
2077	*/
2078	pgmR3PoolRelocate(pVM);
2079	}
2080
2081
2082	/**
2083	* Callback function for relocating a physical access handler.
2084	*
2085	* @returns 0 (continue enum)
2086	* @param pNode Pointer to a PGMPHYSHANDLER node.
2087	* @param pvUser Pointer to the offDelta. This is a pointer to the delta since we're
2088	* not certain the delta will fit in a void pointer for all possible configs.
2089	*/
2090	static DECLCALLBACK(int) pgmR3RelocatePhysHandler(PAVLROGCPHYSNODECORE pNode, void *pvUser)
2091	{
2092	PPGMPHYSHANDLER pHandler = (PPGMPHYSHANDLER)pNode;
2093	RTGCINTPTR offDelta = *(PRTGCINTPTR)pvUser;
2094	if (pHandler->pfnHandlerRC)
2095	pHandler->pfnHandlerRC += offDelta;
2096	if (pHandler->pvUserRC >= 0x10000)
2097	pHandler->pvUserRC += offDelta;
2098	return 0;
2099	}
2100
2101
2102	/**
2103	* Callback function for relocating a virtual access handler.
2104	*
2105	* @returns 0 (continue enum)
2106	* @param pNode Pointer to a PGMVIRTHANDLER node.
2107	* @param pvUser Pointer to the offDelta. This is a pointer to the delta since we're
2108	* not certain the delta will fit in a void pointer for all possible configs.
2109	*/
2110	static DECLCALLBACK(int) pgmR3RelocateVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser)
2111	{
2112	PPGMVIRTHANDLER pHandler = (PPGMVIRTHANDLER)pNode;
2113	RTGCINTPTR offDelta = *(PRTGCINTPTR)pvUser;
2114	Assert( pHandler->enmType == PGMVIRTHANDLERTYPE_ALL
2115	\|\| pHandler->enmType == PGMVIRTHANDLERTYPE_WRITE);
2116	Assert(pHandler->pfnHandlerRC);
2117	pHandler->pfnHandlerRC += offDelta;
2118	return 0;
2119	}
2120
2121
2122	/**
2123	* Callback function for relocating a virtual access handler for the hypervisor mapping.
2124	*
2125	* @returns 0 (continue enum)
2126	* @param pNode Pointer to a PGMVIRTHANDLER node.
2127	* @param pvUser Pointer to the offDelta. This is a pointer to the delta since we're
2128	* not certain the delta will fit in a void pointer for all possible configs.
2129	*/
2130	static DECLCALLBACK(int) pgmR3RelocateHyperVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser)
2131	{
2132	PPGMVIRTHANDLER pHandler = (PPGMVIRTHANDLER)pNode;
2133	RTGCINTPTR offDelta = *(PRTGCINTPTR)pvUser;
2134	Assert(pHandler->enmType == PGMVIRTHANDLERTYPE_HYPERVISOR);
2135	Assert(pHandler->pfnHandlerRC);
2136	pHandler->pfnHandlerRC += offDelta;
2137	return 0;
2138	}
2139
2140
2141	/**
2142	* The VM is being reset.
2143	*
2144	* For the PGM component this means that any PD write monitors
2145	* needs to be removed.
2146	*
2147	* @param pVM VM handle.
2148	*/
2149	VMMR3DECL(void) PGMR3Reset(PVM pVM)
2150	{
2151	LogFlow(("PGMR3Reset:\n"));
2152	VM_ASSERT_EMT(pVM);
2153
2154	pgmLock(pVM);
2155
2156	/*
2157	* Unfix any fixed mappings and disable CR3 monitoring.
2158	*/
2159	pVM->pgm.s.fMappingsFixed = false;
2160	pVM->pgm.s.GCPtrMappingFixed = 0;
2161	pVM->pgm.s.cbMappingFixed = 0;
2162
2163	/* Exit the guest paging mode before the pgm pool gets reset.
2164	* Important to clean up the amd64 case.
2165	*/
2166	int rc = PGM_GST_PFN(Exit, pVM)(pVM);
2167	AssertRC(rc);
2168	#ifdef DEBUG
2169	DBGFR3InfoLog(pVM, "mappings", NULL);
2170	DBGFR3InfoLog(pVM, "handlers", "all nostat");
2171	#endif
2172
2173	/*
2174	* Reset the shadow page pool.
2175	*/
2176	pgmR3PoolReset(pVM);
2177
2178	/*
2179	* Re-init other members.
2180	*/
2181	pVM->pgm.s.fA20Enabled = true;
2182
2183	/*
2184	* Clear the FFs PGM owns.
2185	*/
2186	VM_FF_CLEAR(pVM, VM_FF_PGM_SYNC_CR3);
2187	VM_FF_CLEAR(pVM, VM_FF_PGM_SYNC_CR3_NON_GLOBAL);
2188
2189	/*
2190	* Reset (zero) RAM pages.
2191	*/
2192	rc = pgmR3PhysRamReset(pVM);
2193	if (RT_SUCCESS(rc))
2194	{
2195	#ifdef VBOX_WITH_NEW_PHYS_CODE
2196	/*
2197	* Reset (zero) shadow ROM pages.
2198	*/
2199	rc = pgmR3PhysRomReset(pVM);
2200	#endif
2201	if (RT_SUCCESS(rc))
2202	{
2203	/*
2204	* Switch mode back to real mode.
2205	*/
2206	rc = PGMR3ChangeMode(pVM, PGMMODE_REAL);
2207	STAM_REL_COUNTER_RESET(&pVM->pgm.s.cGuestModeChanges);
2208	}
2209	}
2210
2211	pgmUnlock(pVM);
2212	//return rc;
2213	AssertReleaseRC(rc);
2214	}
2215
2216
2217	#ifdef VBOX_STRICT
2218	/**
2219	* VM state change callback for clearing fNoMorePhysWrites after
2220	* a snapshot has been created.
2221	*/
2222	static DECLCALLBACK(void) pgmR3ResetNoMorePhysWritesFlag(PVM pVM, VMSTATE enmState, VMSTATE enmOldState, void *pvUser)
2223	{
2224	if (enmState == VMSTATE_RUNNING)
2225	pVM->pgm.s.fNoMorePhysWrites = false;
2226	}
2227	#endif
2228
2229
2230	/**
2231	* Terminates the PGM.
2232	*
2233	* @returns VBox status code.
2234	* @param pVM Pointer to VM structure.
2235	*/
2236	VMMR3DECL(int) PGMR3Term(PVM pVM)
2237	{
2238	return PDMR3CritSectDelete(&pVM->pgm.s.CritSect);
2239	}
2240
2241
2242	/**
2243	* Terminates the per-VCPU PGM.
2244	*
2245	* Termination means cleaning up and freeing all resources,
2246	* the VM it self is at this point powered off or suspended.
2247	*
2248	* @returns VBox status code.
2249	* @param pVM The VM to operate on.
2250	*/
2251	VMMR3DECL(int) PGMR3TermCPU(PVM pVM)
2252	{
2253	return 0;
2254	}
2255
2256
2257	/**
2258	* Execute state save operation.
2259	*
2260	* @returns VBox status code.
2261	* @param pVM VM Handle.
2262	* @param pSSM SSM operation handle.
2263	*/
2264	static DECLCALLBACK(int) pgmR3Save(PVM pVM, PSSMHANDLE pSSM)
2265	{
2266	PPGM pPGM = &pVM->pgm.s;
2267
2268	/* No more writes to physical memory after this point! */
2269	pVM->pgm.s.fNoMorePhysWrites = true;
2270
2271	/*
2272	* Save basic data (required / unaffected by relocation).
2273	*/
2274	#if 1
2275	SSMR3PutBool(pSSM, pPGM->fMappingsFixed);
2276	#else
2277	SSMR3PutUInt(pSSM, pPGM->fMappingsFixed);
2278	#endif
2279	SSMR3PutGCPtr(pSSM, pPGM->GCPtrMappingFixed);
2280	SSMR3PutU32(pSSM, pPGM->cbMappingFixed);
2281	SSMR3PutUInt(pSSM, pPGM->cbRamSize);
2282	SSMR3PutGCPhys(pSSM, pPGM->GCPhysA20Mask);
2283	SSMR3PutUInt(pSSM, pPGM->fA20Enabled);
2284	SSMR3PutUInt(pSSM, pPGM->fSyncFlags);
2285	SSMR3PutUInt(pSSM, pPGM->enmGuestMode);
2286	SSMR3PutU32(pSSM, ~0); /* Separator. */
2287
2288	/*
2289	* The guest mappings.
2290	*/
2291	uint32_t i = 0;
2292	for (PPGMMAPPING pMapping = pPGM->pMappingsR3; pMapping; pMapping = pMapping->pNextR3, i++)
2293	{
2294	SSMR3PutU32(pSSM, i);
2295	SSMR3PutStrZ(pSSM, pMapping->pszDesc); /* This is the best unique id we have... */
2296	SSMR3PutGCPtr(pSSM, pMapping->GCPtr);
2297	SSMR3PutGCUIntPtr(pSSM, pMapping->cPTs);
2298	/* flags are done by the mapping owners! */
2299	}
2300	SSMR3PutU32(pSSM, ~0); /* terminator. */
2301
2302	/*
2303	* Ram range flags and bits.
2304	*/
2305	i = 0;
2306	for (PPGMRAMRANGE pRam = pPGM->pRamRangesR3; pRam; pRam = pRam->pNextR3, i++)
2307	{
2308	/** @todo MMIO ranges may move (PCI reconfig), we currently assume they don't. */
2309
2310	SSMR3PutU32(pSSM, i);
2311	SSMR3PutGCPhys(pSSM, pRam->GCPhys);
2312	SSMR3PutGCPhys(pSSM, pRam->GCPhysLast);
2313	SSMR3PutGCPhys(pSSM, pRam->cb);
2314	SSMR3PutU8(pSSM, !!pRam->pvR3); /* boolean indicating memory or not. */
2315
2316	/* Flags. */
2317	const unsigned cPages = pRam->cb >> PAGE_SHIFT;
2318	for (unsigned iPage = 0; iPage < cPages; iPage++)
2319	SSMR3PutU16(pSSM, (uint16_t)(pRam->aPages[iPage].HCPhys & ~X86_PTE_PAE_PG_MASK)); /** @todo PAGE FLAGS */
2320
2321	/* any memory associated with the range. */
2322	if (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)
2323	{
2324	for (unsigned iChunk = 0; iChunk < (pRam->cb >> PGM_DYNAMIC_CHUNK_SHIFT); iChunk++)
2325	{
2326	if (pRam->paChunkR3Ptrs[iChunk])
2327	{
2328	SSMR3PutU8(pSSM, 1); /* chunk present */
2329	SSMR3PutMem(pSSM, (void *)pRam->paChunkR3Ptrs[iChunk], PGM_DYNAMIC_CHUNK_SIZE);
2330	}
2331	else
2332	SSMR3PutU8(pSSM, 0); /* no chunk present */
2333	}
2334	}
2335	else if (pRam->pvR3)
2336	{
2337	int rc = SSMR3PutMem(pSSM, pRam->pvR3, pRam->cb);
2338	if (RT_FAILURE(rc))
2339	{
2340	Log(("pgmR3Save: SSMR3PutMem(, %p, %#x) -> %Rrc\n", pRam->pvR3, pRam->cb, rc));
2341	return rc;
2342	}
2343	}
2344	}
2345	return SSMR3PutU32(pSSM, ~0); /* terminator. */
2346	}
2347
2348
2349	/**
2350	* Execute state load operation.
2351	*
2352	* @returns VBox status code.
2353	* @param pVM VM Handle.
2354	* @param pSSM SSM operation handle.
2355	* @param u32Version Data layout version.
2356	*/
2357	static DECLCALLBACK(int) pgmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version)
2358	{
2359	/*
2360	* Validate version.
2361	*/
2362	if (u32Version != PGM_SAVED_STATE_VERSION)
2363	{
2364	AssertMsgFailed(("pgmR3Load: Invalid version u32Version=%d (current %d)!\n", u32Version, PGM_SAVED_STATE_VERSION));
2365	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
2366	}
2367
2368	/*
2369	* Call the reset function to make sure all the memory is cleared.
2370	*/
2371	PGMR3Reset(pVM);
2372
2373	/*
2374	* Load basic data (required / unaffected by relocation).
2375	*/
2376	PPGM pPGM = &pVM->pgm.s;
2377	#if 1
2378	SSMR3GetBool(pSSM, &pPGM->fMappingsFixed);
2379	#else
2380	uint32_t u;
2381	SSMR3GetU32(pSSM, &u);
2382	pPGM->fMappingsFixed = u;
2383	#endif
2384	SSMR3GetGCPtr(pSSM, &pPGM->GCPtrMappingFixed);
2385	SSMR3GetU32(pSSM, &pPGM->cbMappingFixed);
2386
2387	RTUINT cbRamSize;
2388	int rc = SSMR3GetU32(pSSM, &cbRamSize);
2389	if (RT_FAILURE(rc))
2390	return rc;
2391	if (cbRamSize != pPGM->cbRamSize)
2392	return VERR_SSM_LOAD_MEMORY_SIZE_MISMATCH;
2393	SSMR3GetGCPhys(pSSM, &pPGM->GCPhysA20Mask);
2394	SSMR3GetUInt(pSSM, &pPGM->fA20Enabled);
2395	SSMR3GetUInt(pSSM, &pPGM->fSyncFlags);
2396	RTUINT uGuestMode;
2397	SSMR3GetUInt(pSSM, &uGuestMode);
2398	pPGM->enmGuestMode = (PGMMODE)uGuestMode;
2399
2400	/* check separator. */
2401	uint32_t u32Sep;
2402	SSMR3GetU32(pSSM, &u32Sep);
2403	if (RT_FAILURE(rc))
2404	return rc;
2405	if (u32Sep != (uint32_t)~0)
2406	{
2407	AssertMsgFailed(("u32Sep=%#x (first)\n", u32Sep));
2408	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2409	}
2410
2411	/*
2412	* The guest mappings.
2413	*/
2414	uint32_t i = 0;
2415	for (;; i++)
2416	{
2417	/* Check the seqence number / separator. */
2418	rc = SSMR3GetU32(pSSM, &u32Sep);
2419	if (RT_FAILURE(rc))
2420	return rc;
2421	if (u32Sep == ~0U)
2422	break;
2423	if (u32Sep != i)
2424	{
2425	AssertMsgFailed(("u32Sep=%#x (last)\n", u32Sep));
2426	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2427	}
2428
2429	/* get the mapping details. */
2430	char szDesc[256];
2431	szDesc[0] = '\0';
2432	rc = SSMR3GetStrZ(pSSM, szDesc, sizeof(szDesc));
2433	if (RT_FAILURE(rc))
2434	return rc;
2435	RTGCPTR GCPtr;
2436	SSMR3GetGCPtr(pSSM, &GCPtr);
2437	RTGCPTR cPTs;
2438	rc = SSMR3GetGCUIntPtr(pSSM, &cPTs);
2439	if (RT_FAILURE(rc))
2440	return rc;
2441
2442	/* find matching range. */
2443	PPGMMAPPING pMapping;
2444	for (pMapping = pPGM->pMappingsR3; pMapping; pMapping = pMapping->pNextR3)
2445	if ( pMapping->cPTs == cPTs
2446	&& !strcmp(pMapping->pszDesc, szDesc))
2447	break;
2448	if (!pMapping)
2449	{
2450	LogRel(("Couldn't find mapping: cPTs=%#x szDesc=%s (GCPtr=%RGv)\n",
2451	cPTs, szDesc, GCPtr));
2452	AssertFailed();
2453	return VERR_SSM_LOAD_CONFIG_MISMATCH;
2454	}
2455
2456	/* relocate it. */
2457	if (pMapping->GCPtr != GCPtr)
2458	{
2459	AssertMsg((GCPtr >> X86_PD_SHIFT << X86_PD_SHIFT) == GCPtr, ("GCPtr=%RGv\n", GCPtr));
2460	pgmR3MapRelocate(pVM, pMapping, pMapping->GCPtr, GCPtr);
2461	}
2462	else
2463	Log(("pgmR3Load: '%s' needed no relocation (%RGv)\n", szDesc, GCPtr));
2464	}
2465
2466	/*
2467	* Ram range flags and bits.
2468	*/
2469	i = 0;
2470	for (PPGMRAMRANGE pRam = pPGM->pRamRangesR3; pRam; pRam = pRam->pNextR3, i++)
2471	{
2472	/** @todo MMIO ranges may move (PCI reconfig), we currently assume they don't. */
2473	/* Check the seqence number / separator. */
2474	rc = SSMR3GetU32(pSSM, &u32Sep);
2475	if (RT_FAILURE(rc))
2476	return rc;
2477	if (u32Sep == ~0U)
2478	break;
2479	if (u32Sep != i)
2480	{
2481	AssertMsgFailed(("u32Sep=%#x (last)\n", u32Sep));
2482	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2483	}
2484
2485	/* Get the range details. */
2486	RTGCPHYS GCPhys;
2487	SSMR3GetGCPhys(pSSM, &GCPhys);
2488	RTGCPHYS GCPhysLast;
2489	SSMR3GetGCPhys(pSSM, &GCPhysLast);
2490	RTGCPHYS cb;
2491	SSMR3GetGCPhys(pSSM, &cb);
2492	uint8_t fHaveBits;
2493	rc = SSMR3GetU8(pSSM, &fHaveBits);
2494	if (RT_FAILURE(rc))
2495	return rc;
2496	if (fHaveBits & ~1)
2497	{
2498	AssertMsgFailed(("u32Sep=%#x (last)\n", u32Sep));
2499	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2500	}
2501
2502	/* Match it up with the current range. */
2503	if ( GCPhys != pRam->GCPhys
2504	\|\| GCPhysLast != pRam->GCPhysLast
2505	\|\| cb != pRam->cb
2506	\|\| fHaveBits != !!pRam->pvR3)
2507	{
2508	LogRel(("Ram range: %RGp-%RGp %RGp bytes %s\n"
2509	"State : %RGp-%RGp %RGp bytes %s\n",
2510	pRam->GCPhys, pRam->GCPhysLast, pRam->cb, pRam->pvR3 ? "bits" : "nobits",
2511	GCPhys, GCPhysLast, cb, fHaveBits ? "bits" : "nobits"));
2512	/*
2513	* If we're loading a state for debugging purpose, don't make a fuss if
2514	* the MMIO[2] and ROM stuff isn't 100% right, just skip the mismatches.
2515	*/
2516	if ( SSMR3HandleGetAfter(pSSM) != SSMAFTER_DEBUG_IT
2517	\|\| GCPhys < 8 * _1M)
2518	AssertFailedReturn(VERR_SSM_LOAD_CONFIG_MISMATCH);
2519
2520	RTGCPHYS cPages = ((GCPhysLast - GCPhys) + 1) >> PAGE_SHIFT;
2521	while (cPages-- > 0)
2522	{
2523	uint16_t u16Ignore;
2524	SSMR3GetU16(pSSM, &u16Ignore);
2525	}
2526	continue;
2527	}
2528
2529	/* Flags. */
2530	const unsigned cPages = pRam->cb >> PAGE_SHIFT;
2531	for (unsigned iPage = 0; iPage < cPages; iPage++)
2532	{
2533	uint16_t u16 = 0;
2534	SSMR3GetU16(pSSM, &u16);
2535	u16 &= PAGE_OFFSET_MASK & ~( RT_BIT(4) \| RT_BIT(5) \| RT_BIT(6)
2536	\| RT_BIT(7) \| RT_BIT(8) \| RT_BIT(9) \| RT_BIT(10) );
2537	// &= MM_RAM_FLAGS_DYNAMIC_ALLOC \| MM_RAM_FLAGS_RESERVED \| MM_RAM_FLAGS_ROM \| MM_RAM_FLAGS_MMIO \| MM_RAM_FLAGS_MMIO2
2538	pRam->aPages[iPage].HCPhys = PGM_PAGE_GET_HCPHYS(&pRam->aPages[iPage]) \| (RTHCPHYS)u16; /** @todo PAGE FLAGS */
2539	}
2540
2541	/* any memory associated with the range. */
2542	if (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)
2543	{
2544	for (unsigned iChunk = 0; iChunk < (pRam->cb >> PGM_DYNAMIC_CHUNK_SHIFT); iChunk++)
2545	{
2546	uint8_t fValidChunk;
2547
2548	rc = SSMR3GetU8(pSSM, &fValidChunk);
2549	if (RT_FAILURE(rc))
2550	return rc;
2551	if (fValidChunk > 1)
2552	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2553
2554	if (fValidChunk)
2555	{
2556	if (!pRam->paChunkR3Ptrs[iChunk])
2557	{
2558	rc = pgmr3PhysGrowRange(pVM, pRam->GCPhys + iChunk * PGM_DYNAMIC_CHUNK_SIZE);
2559	if (RT_FAILURE(rc))
2560	return rc;
2561	}
2562	Assert(pRam->paChunkR3Ptrs[iChunk]);
2563
2564	SSMR3GetMem(pSSM, (void *)pRam->paChunkR3Ptrs[iChunk], PGM_DYNAMIC_CHUNK_SIZE);
2565	}
2566	/* else nothing to do */
2567	}
2568	}
2569	else if (pRam->pvR3)
2570	{
2571	int rc = SSMR3GetMem(pSSM, pRam->pvR3, pRam->cb);
2572	if (RT_FAILURE(rc))
2573	{
2574	Log(("pgmR3Save: SSMR3GetMem(, %p, %#x) -> %Rrc\n", pRam->pvR3, pRam->cb, rc));
2575	return rc;
2576	}
2577	}
2578	}
2579
2580	/*
2581	* We require a full resync now.
2582	*/
2583	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3_NON_GLOBAL);
2584	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
2585	pPGM->fSyncFlags \|= PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL;
2586	pPGM->fPhysCacheFlushPending = true;
2587	pgmR3HandlerPhysicalUpdateAll(pVM);
2588
2589	/*
2590	* Change the paging mode.
2591	*/
2592	rc = PGMR3ChangeMode(pVM, pPGM->enmGuestMode);
2593
2594	/* Restore pVM->pgm.s.GCPhysCR3. */
2595	Assert(pVM->pgm.s.GCPhysCR3 == NIL_RTGCPHYS);
2596	RTGCPHYS GCPhysCR3 = CPUMGetGuestCR3(pVM);
2597	if ( pVM->pgm.s.enmGuestMode == PGMMODE_PAE
2598	\|\| pVM->pgm.s.enmGuestMode == PGMMODE_PAE_NX
2599	\|\| pVM->pgm.s.enmGuestMode == PGMMODE_AMD64
2600	\|\| pVM->pgm.s.enmGuestMode == PGMMODE_AMD64_NX)
2601	GCPhysCR3 = (GCPhysCR3 & X86_CR3_PAE_PAGE_MASK);
2602	else
2603	GCPhysCR3 = (GCPhysCR3 & X86_CR3_PAGE_MASK);
2604	pVM->pgm.s.GCPhysCR3 = GCPhysCR3;
2605
2606	return rc;
2607	}
2608
2609
2610	/**
2611	* Show paging mode.
2612	*
2613	* @param pVM VM Handle.
2614	* @param pHlp The info helpers.
2615	* @param pszArgs "all" (default), "guest", "shadow" or "host".
2616	*/
2617	static DECLCALLBACK(void) pgmR3InfoMode(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2618	{
2619	/* digest argument. */
2620	bool fGuest, fShadow, fHost;
2621	if (pszArgs)
2622	pszArgs = RTStrStripL(pszArgs);
2623	if (!pszArgs \|\| !*pszArgs \|\| strstr(pszArgs, "all"))
2624	fShadow = fHost = fGuest = true;
2625	else
2626	{
2627	fShadow = fHost = fGuest = false;
2628	if (strstr(pszArgs, "guest"))
2629	fGuest = true;
2630	if (strstr(pszArgs, "shadow"))
2631	fShadow = true;
2632	if (strstr(pszArgs, "host"))
2633	fHost = true;
2634	}
2635
2636	/* print info. */
2637	if (fGuest)
2638	pHlp->pfnPrintf(pHlp, "Guest paging mode: %s, changed %RU64 times, A20 %s\n",
2639	PGMGetModeName(pVM->pgm.s.enmGuestMode), pVM->pgm.s.cGuestModeChanges.c,
2640	pVM->pgm.s.fA20Enabled ? "enabled" : "disabled");
2641	if (fShadow)
2642	pHlp->pfnPrintf(pHlp, "Shadow paging mode: %s\n", PGMGetModeName(pVM->pgm.s.enmShadowMode));
2643	if (fHost)
2644	{
2645	const char *psz;
2646	switch (pVM->pgm.s.enmHostMode)
2647	{
2648	case SUPPAGINGMODE_INVALID: psz = "invalid"; break;
2649	case SUPPAGINGMODE_32_BIT: psz = "32-bit"; break;
2650	case SUPPAGINGMODE_32_BIT_GLOBAL: psz = "32-bit+G"; break;
2651	case SUPPAGINGMODE_PAE: psz = "PAE"; break;
2652	case SUPPAGINGMODE_PAE_GLOBAL: psz = "PAE+G"; break;
2653	case SUPPAGINGMODE_PAE_NX: psz = "PAE+NX"; break;
2654	case SUPPAGINGMODE_PAE_GLOBAL_NX: psz = "PAE+G+NX"; break;
2655	case SUPPAGINGMODE_AMD64: psz = "AMD64"; break;
2656	case SUPPAGINGMODE_AMD64_GLOBAL: psz = "AMD64+G"; break;
2657	case SUPPAGINGMODE_AMD64_NX: psz = "AMD64+NX"; break;
2658	case SUPPAGINGMODE_AMD64_GLOBAL_NX: psz = "AMD64+G+NX"; break;
2659	default: psz = "unknown"; break;
2660	}
2661	pHlp->pfnPrintf(pHlp, "Host paging mode: %s\n", psz);
2662	}
2663	}
2664
2665
2666	/**
2667	* Dump registered MMIO ranges to the log.
2668	*
2669	* @param pVM VM Handle.
2670	* @param pHlp The info helpers.
2671	* @param pszArgs Arguments, ignored.
2672	*/
2673	static DECLCALLBACK(void) pgmR3PhysInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2674	{
2675	NOREF(pszArgs);
2676	pHlp->pfnPrintf(pHlp,
2677	"RAM ranges (pVM=%p)\n"
2678	"%.s %.s\n",
2679	pVM,
2680	sizeof(RTGCPHYS) * 4 + 1, "GC Phys Range ",
2681	sizeof(RTHCPTR) * 2, "pvHC ");
2682
2683	for (PPGMRAMRANGE pCur = pVM->pgm.s.pRamRangesR3; pCur; pCur = pCur->pNextR3)
2684	pHlp->pfnPrintf(pHlp,
2685	"%RGp-%RGp %RHv %s\n",
2686	pCur->GCPhys,
2687	pCur->GCPhysLast,
2688	pCur->pvR3,
2689	pCur->pszDesc);
2690	}
2691
2692	/**
2693	* Dump the page directory to the log.
2694	*
2695	* @param pVM VM Handle.
2696	* @param pHlp The info helpers.
2697	* @param pszArgs Arguments, ignored.
2698	*/
2699	static DECLCALLBACK(void) pgmR3InfoCr3(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2700	{
2701	/** @todo fix this! Convert the PGMR3DumpHierarchyHC functions to do guest stuff. */
2702	/* Big pages supported? */
2703	const bool fPSE = !!(CPUMGetGuestCR4(pVM) & X86_CR4_PSE);
2704
2705	/* Global pages supported? */
2706	const bool fPGE = !!(CPUMGetGuestCR4(pVM) & X86_CR4_PGE);
2707
2708	NOREF(pszArgs);
2709
2710	/*
2711	* Get page directory addresses.
2712	*/
2713	PX86PD pPDSrc = pVM->pgm.s.pGst32BitPdR3;
2714	Assert(pPDSrc);
2715	Assert(PGMPhysGCPhys2R3PtrAssert(pVM, (RTGCPHYS)(CPUMGetGuestCR3(pVM) & X86_CR3_PAGE_MASK), sizeof(*pPDSrc)) == pPDSrc);
2716
2717	/*
2718	* Iterate the page directory.
2719	*/
2720	for (unsigned iPD = 0; iPD < RT_ELEMENTS(pPDSrc->a); iPD++)
2721	{
2722	X86PDE PdeSrc = pPDSrc->a[iPD];
2723	if (PdeSrc.n.u1Present)
2724	{
2725	if (PdeSrc.b.u1Size && fPSE)
2726	pHlp->pfnPrintf(pHlp,
2727	"%04X - %RGp P=%d U=%d RW=%d G=%d - BIG\n",
2728	iPD,
2729	pgmGstGet4MBPhysPage(&pVM->pgm.s, PdeSrc),
2730	PdeSrc.b.u1Present, PdeSrc.b.u1User, PdeSrc.b.u1Write, PdeSrc.b.u1Global && fPGE);
2731	else
2732	pHlp->pfnPrintf(pHlp,
2733	"%04X - %RGp P=%d U=%d RW=%d [G=%d]\n",
2734	iPD,
2735	(RTGCPHYS)(PdeSrc.u & X86_PDE_PG_MASK),
2736	PdeSrc.n.u1Present, PdeSrc.n.u1User, PdeSrc.n.u1Write, PdeSrc.b.u1Global && fPGE);
2737	}
2738	}
2739	}
2740
2741
2742	/**
2743	* Serivce a VMMCALLHOST_PGM_LOCK call.
2744	*
2745	* @returns VBox status code.
2746	* @param pVM The VM handle.
2747	*/
2748	VMMR3DECL(int) PGMR3LockCall(PVM pVM)
2749	{
2750	int rc = PDMR3CritSectEnterEx(&pVM->pgm.s.CritSect, true /* fHostCall */);
2751	AssertRC(rc);
2752	return rc;
2753	}
2754
2755
2756	/**
2757	* Converts a PGMMODE value to a PGM_TYPE_* \#define.
2758	*
2759	* @returns PGM_TYPE_*.
2760	* @param pgmMode The mode value to convert.
2761	*/
2762	DECLINLINE(unsigned) pgmModeToType(PGMMODE pgmMode)
2763	{
2764	switch (pgmMode)
2765	{
2766	case PGMMODE_REAL: return PGM_TYPE_REAL;
2767	case PGMMODE_PROTECTED: return PGM_TYPE_PROT;
2768	case PGMMODE_32_BIT: return PGM_TYPE_32BIT;
2769	case PGMMODE_PAE:
2770	case PGMMODE_PAE_NX: return PGM_TYPE_PAE;
2771	case PGMMODE_AMD64:
2772	case PGMMODE_AMD64_NX: return PGM_TYPE_AMD64;
2773	case PGMMODE_NESTED: return PGM_TYPE_NESTED;
2774	case PGMMODE_EPT: return PGM_TYPE_EPT;
2775	default:
2776	AssertFatalMsgFailed(("pgmMode=%d\n", pgmMode));
2777	}
2778	}
2779
2780
2781	/**
2782	* Gets the index into the paging mode data array of a SHW+GST mode.
2783	*
2784	* @returns PGM::paPagingData index.
2785	* @param uShwType The shadow paging mode type.
2786	* @param uGstType The guest paging mode type.
2787	*/
2788	DECLINLINE(unsigned) pgmModeDataIndex(unsigned uShwType, unsigned uGstType)
2789	{
2790	Assert(uShwType >= PGM_TYPE_32BIT && uShwType <= PGM_TYPE_MAX);
2791	Assert(uGstType >= PGM_TYPE_REAL && uGstType <= PGM_TYPE_AMD64);
2792	return (uShwType - PGM_TYPE_32BIT) * (PGM_TYPE_AMD64 - PGM_TYPE_REAL + 1)
2793	+ (uGstType - PGM_TYPE_REAL);
2794	}
2795
2796
2797	/**
2798	* Gets the index into the paging mode data array of a SHW+GST mode.
2799	*
2800	* @returns PGM::paPagingData index.
2801	* @param enmShw The shadow paging mode.
2802	* @param enmGst The guest paging mode.
2803	*/
2804	DECLINLINE(unsigned) pgmModeDataIndexByMode(PGMMODE enmShw, PGMMODE enmGst)
2805	{
2806	Assert(enmShw >= PGMMODE_32_BIT && enmShw <= PGMMODE_MAX);
2807	Assert(enmGst > PGMMODE_INVALID && enmGst < PGMMODE_MAX);
2808	return pgmModeDataIndex(pgmModeToType(enmShw), pgmModeToType(enmGst));
2809	}
2810
2811
2812	/**
2813	* Calculates the max data index.
2814	* @returns The number of entries in the paging data array.
2815	*/
2816	DECLINLINE(unsigned) pgmModeDataMaxIndex(void)
2817	{
2818	return pgmModeDataIndex(PGM_TYPE_MAX, PGM_TYPE_AMD64) + 1;
2819	}
2820
2821
2822	/**
2823	* Initializes the paging mode data kept in PGM::paModeData.
2824	*
2825	* @param pVM The VM handle.
2826	* @param fResolveGCAndR0 Indicate whether or not GC and Ring-0 symbols can be resolved now.
2827	* This is used early in the init process to avoid trouble with PDM
2828	* not being initialized yet.
2829	*/
2830	static int pgmR3ModeDataInit(PVM pVM, bool fResolveGCAndR0)
2831	{
2832	PPGMMODEDATA pModeData;
2833	int rc;
2834
2835	/*
2836	* Allocate the array on the first call.
2837	*/
2838	if (!pVM->pgm.s.paModeData)
2839	{
2840	pVM->pgm.s.paModeData = (PPGMMODEDATA)MMR3HeapAllocZ(pVM, MM_TAG_PGM, sizeof(PGMMODEDATA) * pgmModeDataMaxIndex());
2841	AssertReturn(pVM->pgm.s.paModeData, VERR_NO_MEMORY);
2842	}
2843
2844	/*
2845	* Initialize the array entries.
2846	*/
2847	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_32BIT, PGM_TYPE_REAL)];
2848	pModeData->uShwType = PGM_TYPE_32BIT;
2849	pModeData->uGstType = PGM_TYPE_REAL;
2850	rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2851	rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2852	rc = PGM_BTH_NAME_32BIT_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2853
2854	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_32BIT, PGMMODE_PROTECTED)];
2855	pModeData->uShwType = PGM_TYPE_32BIT;
2856	pModeData->uGstType = PGM_TYPE_PROT;
2857	rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2858	rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2859	rc = PGM_BTH_NAME_32BIT_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2860
2861	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_32BIT, PGM_TYPE_32BIT)];
2862	pModeData->uShwType = PGM_TYPE_32BIT;
2863	pModeData->uGstType = PGM_TYPE_32BIT;
2864	rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2865	rc = PGM_GST_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2866	rc = PGM_BTH_NAME_32BIT_32BIT(InitData)(pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2867
2868	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_REAL)];
2869	pModeData->uShwType = PGM_TYPE_PAE;
2870	pModeData->uGstType = PGM_TYPE_REAL;
2871	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2872	rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2873	rc = PGM_BTH_NAME_PAE_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2874
2875	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_PROT)];
2876	pModeData->uShwType = PGM_TYPE_PAE;
2877	pModeData->uGstType = PGM_TYPE_PROT;
2878	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2879	rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2880	rc = PGM_BTH_NAME_PAE_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2881
2882	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_32BIT)];
2883	pModeData->uShwType = PGM_TYPE_PAE;
2884	pModeData->uGstType = PGM_TYPE_32BIT;
2885	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2886	rc = PGM_GST_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2887	rc = PGM_BTH_NAME_PAE_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2888
2889	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_PAE)];
2890	pModeData->uShwType = PGM_TYPE_PAE;
2891	pModeData->uGstType = PGM_TYPE_PAE;
2892	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2893	rc = PGM_GST_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2894	rc = PGM_BTH_NAME_PAE_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2895
2896	#ifdef VBOX_WITH_64_BITS_GUESTS
2897	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_AMD64, PGM_TYPE_AMD64)];
2898	pModeData->uShwType = PGM_TYPE_AMD64;
2899	pModeData->uGstType = PGM_TYPE_AMD64;
2900	rc = PGM_SHW_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2901	rc = PGM_GST_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2902	rc = PGM_BTH_NAME_AMD64_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2903	#endif
2904
2905	/* The nested paging mode. */
2906	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_REAL)];
2907	pModeData->uShwType = PGM_TYPE_NESTED;
2908	pModeData->uGstType = PGM_TYPE_REAL;
2909	rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2910	rc = PGM_BTH_NAME_NESTED_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2911
2912	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGMMODE_PROTECTED)];
2913	pModeData->uShwType = PGM_TYPE_NESTED;
2914	pModeData->uGstType = PGM_TYPE_PROT;
2915	rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2916	rc = PGM_BTH_NAME_NESTED_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2917
2918	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_32BIT)];
2919	pModeData->uShwType = PGM_TYPE_NESTED;
2920	pModeData->uGstType = PGM_TYPE_32BIT;
2921	rc = PGM_GST_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2922	rc = PGM_BTH_NAME_NESTED_32BIT(InitData)(pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2923
2924	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_PAE)];
2925	pModeData->uShwType = PGM_TYPE_NESTED;
2926	pModeData->uGstType = PGM_TYPE_PAE;
2927	rc = PGM_GST_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2928	rc = PGM_BTH_NAME_NESTED_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2929
2930	#ifdef VBOX_WITH_64_BITS_GUESTS
2931	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_AMD64)];
2932	pModeData->uShwType = PGM_TYPE_NESTED;
2933	pModeData->uGstType = PGM_TYPE_AMD64;
2934	rc = PGM_GST_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2935	rc = PGM_BTH_NAME_NESTED_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2936	#endif
2937
2938	/* The shadow part of the nested callback mode depends on the host paging mode (AMD-V only). */
2939	switch (pVM->pgm.s.enmHostMode)
2940	{
2941	#if HC_ARCH_BITS == 32
2942	case SUPPAGINGMODE_32_BIT:
2943	case SUPPAGINGMODE_32_BIT_GLOBAL:
2944	for (unsigned i = PGM_TYPE_REAL; i <= PGM_TYPE_PAE; i++)
2945	{
2946	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, i)];
2947	rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2948	}
2949	# ifdef VBOX_WITH_64_BITS_GUESTS
2950	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_AMD64)];
2951	rc = PGM_SHW_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2952	# endif
2953	break;
2954
2955	case SUPPAGINGMODE_PAE:
2956	case SUPPAGINGMODE_PAE_NX:
2957	case SUPPAGINGMODE_PAE_GLOBAL:
2958	case SUPPAGINGMODE_PAE_GLOBAL_NX:
2959	for (unsigned i = PGM_TYPE_REAL; i <= PGM_TYPE_PAE; i++)
2960	{
2961	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, i)];
2962	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2963	}
2964	# ifdef VBOX_WITH_64_BITS_GUESTS
2965	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_AMD64)];
2966	rc = PGM_SHW_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2967	# endif
2968	break;
2969	#endif /* HC_ARCH_BITS == 32 */
2970
2971	#if HC_ARCH_BITS == 64 \|\| defined(RT_OS_DARWIN)
2972	case SUPPAGINGMODE_AMD64:
2973	case SUPPAGINGMODE_AMD64_GLOBAL:
2974	case SUPPAGINGMODE_AMD64_NX:
2975	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
2976	# ifdef VBOX_WITH_64_BITS_GUESTS
2977	for (unsigned i = PGM_TYPE_REAL; i <= PGM_TYPE_AMD64; i++)
2978	# else
2979	for (unsigned i = PGM_TYPE_REAL; i <= PGM_TYPE_PAE; i++)
2980	# endif
2981	{
2982	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, i)];
2983	rc = PGM_SHW_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2984	}
2985	break;
2986	#endif /* HC_ARCH_BITS == 64 \|\| RT_OS_DARWIN */
2987
2988	default:
2989	AssertFailed();
2990	break;
2991	}
2992
2993	/* Extended paging (EPT) / Intel VT-x */
2994	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_REAL)];
2995	pModeData->uShwType = PGM_TYPE_EPT;
2996	pModeData->uGstType = PGM_TYPE_REAL;
2997	rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2998	rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2999	rc = PGM_BTH_NAME_EPT_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3000
3001	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_PROT)];
3002	pModeData->uShwType = PGM_TYPE_EPT;
3003	pModeData->uGstType = PGM_TYPE_PROT;
3004	rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3005	rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3006	rc = PGM_BTH_NAME_EPT_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3007
3008	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_32BIT)];
3009	pModeData->uShwType = PGM_TYPE_EPT;
3010	pModeData->uGstType = PGM_TYPE_32BIT;
3011	rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3012	rc = PGM_GST_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3013	rc = PGM_BTH_NAME_EPT_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3014
3015	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_PAE)];
3016	pModeData->uShwType = PGM_TYPE_EPT;
3017	pModeData->uGstType = PGM_TYPE_PAE;
3018	rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3019	rc = PGM_GST_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3020	rc = PGM_BTH_NAME_EPT_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3021
3022	#ifdef VBOX_WITH_64_BITS_GUESTS
3023	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_AMD64)];
3024	pModeData->uShwType = PGM_TYPE_EPT;
3025	pModeData->uGstType = PGM_TYPE_AMD64;
3026	rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3027	rc = PGM_GST_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3028	rc = PGM_BTH_NAME_EPT_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3029	#endif
3030	return VINF_SUCCESS;
3031	}
3032
3033
3034	/**
3035	* Switch to different (or relocated in the relocate case) mode data.
3036	*
3037	* @param pVM The VM handle.
3038	* @param enmShw The the shadow paging mode.
3039	* @param enmGst The the guest paging mode.
3040	*/
3041	static void pgmR3ModeDataSwitch(PVM pVM, PGMMODE enmShw, PGMMODE enmGst)
3042	{
3043	PPGMMODEDATA pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndexByMode(enmShw, enmGst)];
3044
3045	Assert(pModeData->uGstType == pgmModeToType(enmGst));
3046	Assert(pModeData->uShwType == pgmModeToType(enmShw));
3047
3048	/* shadow */
3049	pVM->pgm.s.pfnR3ShwRelocate = pModeData->pfnR3ShwRelocate;
3050	pVM->pgm.s.pfnR3ShwExit = pModeData->pfnR3ShwExit;
3051	pVM->pgm.s.pfnR3ShwGetPage = pModeData->pfnR3ShwGetPage;
3052	Assert(pVM->pgm.s.pfnR3ShwGetPage);
3053	pVM->pgm.s.pfnR3ShwModifyPage = pModeData->pfnR3ShwModifyPage;
3054
3055	pVM->pgm.s.pfnRCShwGetPage = pModeData->pfnRCShwGetPage;
3056	pVM->pgm.s.pfnRCShwModifyPage = pModeData->pfnRCShwModifyPage;
3057
3058	pVM->pgm.s.pfnR0ShwGetPage = pModeData->pfnR0ShwGetPage;
3059	pVM->pgm.s.pfnR0ShwModifyPage = pModeData->pfnR0ShwModifyPage;
3060
3061
3062	/* guest */
3063	pVM->pgm.s.pfnR3GstRelocate = pModeData->pfnR3GstRelocate;
3064	pVM->pgm.s.pfnR3GstExit = pModeData->pfnR3GstExit;
3065	pVM->pgm.s.pfnR3GstGetPage = pModeData->pfnR3GstGetPage;
3066	Assert(pVM->pgm.s.pfnR3GstGetPage);
3067	pVM->pgm.s.pfnR3GstModifyPage = pModeData->pfnR3GstModifyPage;
3068	pVM->pgm.s.pfnR3GstGetPDE = pModeData->pfnR3GstGetPDE;
3069	#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
3070	pVM->pgm.s.pfnR3GstMonitorCR3 = pModeData->pfnR3GstMonitorCR3;
3071	pVM->pgm.s.pfnR3GstUnmonitorCR3 = pModeData->pfnR3GstUnmonitorCR3;
3072	#endif
3073	#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
3074	pVM->pgm.s.pfnR3GstWriteHandlerCR3 = pModeData->pfnR3GstWriteHandlerCR3;
3075	pVM->pgm.s.pszR3GstWriteHandlerCR3 = pModeData->pszR3GstWriteHandlerCR3;
3076	pVM->pgm.s.pfnR3GstPAEWriteHandlerCR3 = pModeData->pfnR3GstPAEWriteHandlerCR3;
3077	pVM->pgm.s.pszR3GstPAEWriteHandlerCR3 = pModeData->pszR3GstPAEWriteHandlerCR3;
3078	#endif
3079	pVM->pgm.s.pfnRCGstGetPage = pModeData->pfnRCGstGetPage;
3080	pVM->pgm.s.pfnRCGstModifyPage = pModeData->pfnRCGstModifyPage;
3081	pVM->pgm.s.pfnRCGstGetPDE = pModeData->pfnRCGstGetPDE;
3082	#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
3083	pVM->pgm.s.pfnRCGstMonitorCR3 = pModeData->pfnRCGstMonitorCR3;
3084	pVM->pgm.s.pfnRCGstUnmonitorCR3 = pModeData->pfnRCGstUnmonitorCR3;
3085	#endif
3086	#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
3087	pVM->pgm.s.pfnRCGstWriteHandlerCR3 = pModeData->pfnRCGstWriteHandlerCR3;
3088	pVM->pgm.s.pfnRCGstPAEWriteHandlerCR3 = pModeData->pfnRCGstPAEWriteHandlerCR3;
3089	#endif
3090	pVM->pgm.s.pfnR0GstGetPage = pModeData->pfnR0GstGetPage;
3091	pVM->pgm.s.pfnR0GstModifyPage = pModeData->pfnR0GstModifyPage;
3092	pVM->pgm.s.pfnR0GstGetPDE = pModeData->pfnR0GstGetPDE;
3093	#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
3094	pVM->pgm.s.pfnR0GstMonitorCR3 = pModeData->pfnR0GstMonitorCR3;
3095	pVM->pgm.s.pfnR0GstUnmonitorCR3 = pModeData->pfnR0GstUnmonitorCR3;
3096	#endif
3097	#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
3098	pVM->pgm.s.pfnR0GstWriteHandlerCR3 = pModeData->pfnR0GstWriteHandlerCR3;
3099	pVM->pgm.s.pfnR0GstPAEWriteHandlerCR3 = pModeData->pfnR0GstPAEWriteHandlerCR3;
3100	#endif
3101
3102	/* both */
3103	pVM->pgm.s.pfnR3BthRelocate = pModeData->pfnR3BthRelocate;
3104	pVM->pgm.s.pfnR3BthInvalidatePage = pModeData->pfnR3BthInvalidatePage;
3105	pVM->pgm.s.pfnR3BthSyncCR3 = pModeData->pfnR3BthSyncCR3;
3106	Assert(pVM->pgm.s.pfnR3BthSyncCR3);
3107	pVM->pgm.s.pfnR3BthSyncPage = pModeData->pfnR3BthSyncPage;
3108	pVM->pgm.s.pfnR3BthPrefetchPage = pModeData->pfnR3BthPrefetchPage;
3109	pVM->pgm.s.pfnR3BthVerifyAccessSyncPage = pModeData->pfnR3BthVerifyAccessSyncPage;
3110	#ifdef VBOX_STRICT
3111	pVM->pgm.s.pfnR3BthAssertCR3 = pModeData->pfnR3BthAssertCR3;
3112	#endif
3113	pVM->pgm.s.pfnR3BthMapCR3 = pModeData->pfnR3BthMapCR3;
3114	pVM->pgm.s.pfnR3BthUnmapCR3 = pModeData->pfnR3BthUnmapCR3;
3115
3116	pVM->pgm.s.pfnRCBthTrap0eHandler = pModeData->pfnRCBthTrap0eHandler;
3117	pVM->pgm.s.pfnRCBthInvalidatePage = pModeData->pfnRCBthInvalidatePage;
3118	pVM->pgm.s.pfnRCBthSyncCR3 = pModeData->pfnRCBthSyncCR3;
3119	pVM->pgm.s.pfnRCBthSyncPage = pModeData->pfnRCBthSyncPage;
3120	pVM->pgm.s.pfnRCBthPrefetchPage = pModeData->pfnRCBthPrefetchPage;
3121	pVM->pgm.s.pfnRCBthVerifyAccessSyncPage = pModeData->pfnRCBthVerifyAccessSyncPage;
3122	#ifdef VBOX_STRICT
3123	pVM->pgm.s.pfnRCBthAssertCR3 = pModeData->pfnRCBthAssertCR3;
3124	#endif
3125	pVM->pgm.s.pfnRCBthMapCR3 = pModeData->pfnRCBthMapCR3;
3126	pVM->pgm.s.pfnRCBthUnmapCR3 = pModeData->pfnRCBthUnmapCR3;
3127
3128	pVM->pgm.s.pfnR0BthTrap0eHandler = pModeData->pfnR0BthTrap0eHandler;
3129	pVM->pgm.s.pfnR0BthInvalidatePage = pModeData->pfnR0BthInvalidatePage;
3130	pVM->pgm.s.pfnR0BthSyncCR3 = pModeData->pfnR0BthSyncCR3;
3131	pVM->pgm.s.pfnR0BthSyncPage = pModeData->pfnR0BthSyncPage;
3132	pVM->pgm.s.pfnR0BthPrefetchPage = pModeData->pfnR0BthPrefetchPage;
3133	pVM->pgm.s.pfnR0BthVerifyAccessSyncPage = pModeData->pfnR0BthVerifyAccessSyncPage;
3134	#ifdef VBOX_STRICT
3135	pVM->pgm.s.pfnR0BthAssertCR3 = pModeData->pfnR0BthAssertCR3;
3136	#endif
3137	pVM->pgm.s.pfnR0BthMapCR3 = pModeData->pfnR0BthMapCR3;
3138	pVM->pgm.s.pfnR0BthUnmapCR3 = pModeData->pfnR0BthUnmapCR3;
3139	}
3140
3141
3142	/**
3143	* Calculates the shadow paging mode.
3144	*
3145	* @returns The shadow paging mode.
3146	* @param pVM VM handle.
3147	* @param enmGuestMode The guest mode.
3148	* @param enmHostMode The host mode.
3149	* @param enmShadowMode The current shadow mode.
3150	* @param penmSwitcher Where to store the switcher to use.
3151	* VMMSWITCHER_INVALID means no change.
3152	*/
3153	static PGMMODE pgmR3CalcShadowMode(PVM pVM, PGMMODE enmGuestMode, SUPPAGINGMODE enmHostMode, PGMMODE enmShadowMode, VMMSWITCHER *penmSwitcher)
3154	{
3155	VMMSWITCHER enmSwitcher = VMMSWITCHER_INVALID;
3156	switch (enmGuestMode)
3157	{
3158	/*
3159	* When switching to real or protected mode we don't change
3160	* anything since it's likely that we'll switch back pretty soon.
3161	*
3162	* During pgmR3InitPaging we'll end up here with PGMMODE_INVALID
3163	* and is supposed to determine which shadow paging and switcher to
3164	* use during init.
3165	*/
3166	case PGMMODE_REAL:
3167	case PGMMODE_PROTECTED:
3168	if ( enmShadowMode != PGMMODE_INVALID
3169	&& !HWACCMIsEnabled(pVM) /* always switch in hwaccm mode! */)
3170	break; /* (no change) */
3171
3172	switch (enmHostMode)
3173	{
3174	case SUPPAGINGMODE_32_BIT:
3175	case SUPPAGINGMODE_32_BIT_GLOBAL:
3176	enmShadowMode = PGMMODE_32_BIT;
3177	enmSwitcher = VMMSWITCHER_32_TO_32;
3178	break;
3179
3180	case SUPPAGINGMODE_PAE:
3181	case SUPPAGINGMODE_PAE_NX:
3182	case SUPPAGINGMODE_PAE_GLOBAL:
3183	case SUPPAGINGMODE_PAE_GLOBAL_NX:
3184	enmShadowMode = PGMMODE_PAE;
3185	enmSwitcher = VMMSWITCHER_PAE_TO_PAE;
3186	#ifdef DEBUG_bird
3187	if (RTEnvExist("VBOX_32BIT"))
3188	{
3189	enmShadowMode = PGMMODE_32_BIT;
3190	enmSwitcher = VMMSWITCHER_PAE_TO_32;
3191	}
3192	#endif
3193	break;
3194
3195	case SUPPAGINGMODE_AMD64:
3196	case SUPPAGINGMODE_AMD64_GLOBAL:
3197	case SUPPAGINGMODE_AMD64_NX:
3198	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
3199	enmShadowMode = PGMMODE_PAE;
3200	enmSwitcher = VMMSWITCHER_AMD64_TO_PAE;
3201	#ifdef DEBUG_bird
3202	if (RTEnvExist("VBOX_32BIT"))
3203	{
3204	enmShadowMode = PGMMODE_32_BIT;
3205	enmSwitcher = VMMSWITCHER_AMD64_TO_32;
3206	}
3207	#endif
3208	break;
3209
3210	default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
3211	}
3212	break;
3213
3214	case PGMMODE_32_BIT:
3215	switch (enmHostMode)
3216	{
3217	case SUPPAGINGMODE_32_BIT:
3218	case SUPPAGINGMODE_32_BIT_GLOBAL:
3219	enmShadowMode = PGMMODE_32_BIT;
3220	enmSwitcher = VMMSWITCHER_32_TO_32;
3221	break;
3222
3223	case SUPPAGINGMODE_PAE:
3224	case SUPPAGINGMODE_PAE_NX:
3225	case SUPPAGINGMODE_PAE_GLOBAL:
3226	case SUPPAGINGMODE_PAE_GLOBAL_NX:
3227	enmShadowMode = PGMMODE_PAE;
3228	enmSwitcher = VMMSWITCHER_PAE_TO_PAE;
3229	#ifdef DEBUG_bird
3230	if (RTEnvExist("VBOX_32BIT"))
3231	{
3232	enmShadowMode = PGMMODE_32_BIT;
3233	enmSwitcher = VMMSWITCHER_PAE_TO_32;
3234	}
3235	#endif
3236	break;
3237
3238	case SUPPAGINGMODE_AMD64:
3239	case SUPPAGINGMODE_AMD64_GLOBAL:
3240	case SUPPAGINGMODE_AMD64_NX:
3241	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
3242	enmShadowMode = PGMMODE_PAE;
3243	enmSwitcher = VMMSWITCHER_AMD64_TO_PAE;
3244	#ifdef DEBUG_bird
3245	if (RTEnvExist("VBOX_32BIT"))
3246	{
3247	enmShadowMode = PGMMODE_32_BIT;
3248	enmSwitcher = VMMSWITCHER_AMD64_TO_32;
3249	}
3250	#endif
3251	break;
3252
3253	default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
3254	}
3255	break;
3256
3257	case PGMMODE_PAE:
3258	case PGMMODE_PAE_NX: /** @todo This might require more switchers and guest+both modes. */
3259	switch (enmHostMode)
3260	{
3261	case SUPPAGINGMODE_32_BIT:
3262	case SUPPAGINGMODE_32_BIT_GLOBAL:
3263	enmShadowMode = PGMMODE_PAE;
3264	enmSwitcher = VMMSWITCHER_32_TO_PAE;
3265	break;
3266
3267	case SUPPAGINGMODE_PAE:
3268	case SUPPAGINGMODE_PAE_NX:
3269	case SUPPAGINGMODE_PAE_GLOBAL:
3270	case SUPPAGINGMODE_PAE_GLOBAL_NX:
3271	enmShadowMode = PGMMODE_PAE;
3272	enmSwitcher = VMMSWITCHER_PAE_TO_PAE;
3273	break;
3274
3275	case SUPPAGINGMODE_AMD64:
3276	case SUPPAGINGMODE_AMD64_GLOBAL:
3277	case SUPPAGINGMODE_AMD64_NX:
3278	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
3279	enmShadowMode = PGMMODE_PAE;
3280	enmSwitcher = VMMSWITCHER_AMD64_TO_PAE;
3281	break;
3282
3283	default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
3284	}
3285	break;
3286
3287	case PGMMODE_AMD64:
3288	case PGMMODE_AMD64_NX:
3289	switch (enmHostMode)
3290	{
3291	case SUPPAGINGMODE_32_BIT:
3292	case SUPPAGINGMODE_32_BIT_GLOBAL:
3293	enmShadowMode = PGMMODE_AMD64;
3294	enmSwitcher = VMMSWITCHER_32_TO_AMD64;
3295	break;
3296
3297	case SUPPAGINGMODE_PAE:
3298	case SUPPAGINGMODE_PAE_NX:
3299	case SUPPAGINGMODE_PAE_GLOBAL:
3300	case SUPPAGINGMODE_PAE_GLOBAL_NX:
3301	enmShadowMode = PGMMODE_AMD64;
3302	enmSwitcher = VMMSWITCHER_PAE_TO_AMD64;
3303	break;
3304
3305	case SUPPAGINGMODE_AMD64:
3306	case SUPPAGINGMODE_AMD64_GLOBAL:
3307	case SUPPAGINGMODE_AMD64_NX:
3308	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
3309	enmShadowMode = PGMMODE_AMD64;
3310	enmSwitcher = VMMSWITCHER_AMD64_TO_AMD64;
3311	break;
3312
3313	default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
3314	}
3315	break;
3316
3317
3318	default:
3319	AssertReleaseMsgFailed(("enmGuestMode=%d\n", enmGuestMode));
3320	return PGMMODE_INVALID;
3321	}
3322	/* Override the shadow mode is nested paging is active. */
3323	if (HWACCMIsNestedPagingActive(pVM))
3324	enmShadowMode = HWACCMGetShwPagingMode(pVM);
3325
3326	*penmSwitcher = enmSwitcher;
3327	return enmShadowMode;
3328	}
3329
3330
3331	/**
3332	* Performs the actual mode change.
3333	* This is called by PGMChangeMode and pgmR3InitPaging().
3334	*
3335	* @returns VBox status code.
3336	* @param pVM VM handle.
3337	* @param enmGuestMode The new guest mode. This is assumed to be different from
3338	* the current mode.
3339	*/
3340	VMMR3DECL(int) PGMR3ChangeMode(PVM pVM, PGMMODE enmGuestMode)
3341	{
3342	Log(("PGMR3ChangeMode: Guest mode: %s -> %s\n", PGMGetModeName(pVM->pgm.s.enmGuestMode), PGMGetModeName(enmGuestMode)));
3343	STAM_REL_COUNTER_INC(&pVM->pgm.s.cGuestModeChanges);
3344
3345	/*
3346	* Calc the shadow mode and switcher.
3347	*/
3348	VMMSWITCHER enmSwitcher;
3349	PGMMODE enmShadowMode = pgmR3CalcShadowMode(pVM, enmGuestMode, pVM->pgm.s.enmHostMode, pVM->pgm.s.enmShadowMode, &enmSwitcher);
3350	if (enmSwitcher != VMMSWITCHER_INVALID)
3351	{
3352	/*
3353	* Select new switcher.
3354	*/
3355	int rc = VMMR3SelectSwitcher(pVM, enmSwitcher);
3356	if (RT_FAILURE(rc))
3357	{
3358	AssertReleaseMsgFailed(("VMMR3SelectSwitcher(%d) -> %Rrc\n", enmSwitcher, rc));
3359	return rc;
3360	}
3361	}
3362
3363	/*
3364	* Exit old mode(s).
3365	*/
3366	/* shadow */
3367	if (enmShadowMode != pVM->pgm.s.enmShadowMode)
3368	{
3369	LogFlow(("PGMR3ChangeMode: Shadow mode: %s -> %s\n", PGMGetModeName(pVM->pgm.s.enmShadowMode), PGMGetModeName(enmShadowMode)));
3370	if (PGM_SHW_PFN(Exit, pVM))
3371	{
3372	int rc = PGM_SHW_PFN(Exit, pVM)(pVM);
3373	if (RT_FAILURE(rc))
3374	{
3375	AssertMsgFailed(("Exit failed for shadow mode %d: %Rrc\n", pVM->pgm.s.enmShadowMode, rc));
3376	return rc;
3377	}
3378	}
3379
3380	}
3381	else
3382	LogFlow(("PGMR3ChangeMode: Shadow mode remains: %s\n", PGMGetModeName(pVM->pgm.s.enmShadowMode)));
3383
3384	/* guest */
3385	if (PGM_GST_PFN(Exit, pVM))
3386	{
3387	int rc = PGM_GST_PFN(Exit, pVM)(pVM);
3388	if (RT_FAILURE(rc))
3389	{
3390	AssertMsgFailed(("Exit failed for guest mode %d: %Rrc\n", pVM->pgm.s.enmGuestMode, rc));
3391	return rc;
3392	}
3393	}
3394
3395	/*
3396	* Load new paging mode data.
3397	*/
3398	pgmR3ModeDataSwitch(pVM, enmShadowMode, enmGuestMode);
3399
3400	/*
3401	* Enter new shadow mode (if changed).
3402	*/
3403	if (enmShadowMode != pVM->pgm.s.enmShadowMode)
3404	{
3405	int rc;
3406	pVM->pgm.s.enmShadowMode = enmShadowMode;
3407	switch (enmShadowMode)
3408	{
3409	case PGMMODE_32_BIT:
3410	rc = PGM_SHW_NAME_32BIT(Enter)(pVM);
3411	break;
3412	case PGMMODE_PAE:
3413	case PGMMODE_PAE_NX:
3414	rc = PGM_SHW_NAME_PAE(Enter)(pVM);
3415	break;
3416	case PGMMODE_AMD64:
3417	case PGMMODE_AMD64_NX:
3418	rc = PGM_SHW_NAME_AMD64(Enter)(pVM);
3419	break;
3420	case PGMMODE_NESTED:
3421	rc = PGM_SHW_NAME_NESTED(Enter)(pVM);
3422	break;
3423	case PGMMODE_EPT:
3424	rc = PGM_SHW_NAME_EPT(Enter)(pVM);
3425	break;
3426	case PGMMODE_REAL:
3427	case PGMMODE_PROTECTED:
3428	default:
3429	AssertReleaseMsgFailed(("enmShadowMode=%d\n", enmShadowMode));
3430	return VERR_INTERNAL_ERROR;
3431	}
3432	if (RT_FAILURE(rc))
3433	{
3434	AssertReleaseMsgFailed(("Entering enmShadowMode=%d failed: %Rrc\n", enmShadowMode, rc));
3435	pVM->pgm.s.enmShadowMode = PGMMODE_INVALID;
3436	return rc;
3437	}
3438	}
3439
3440	#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
3441	/** @todo This is a bug!
3442	*
3443	* We must flush the PGM pool cache if the guest mode changes; we don't always
3444	* switch shadow paging mode (e.g. protected->32-bit) and shouldn't reuse
3445	* the shadow page tables.
3446	*
3447	* That only applies when switching between paging and non-paging modes.
3448	*/
3449	/** @todo A20 setting */
3450	if ( pVM->pgm.s.CTX_SUFF(pPool)
3451	&& !HWACCMIsNestedPagingActive(pVM)
3452	&& PGMMODE_WITH_PAGING(pVM->pgm.s.enmGuestMode) != PGMMODE_WITH_PAGING(enmGuestMode))
3453	{
3454	Log(("PGMR3ChangeMode: changing guest paging mode -> flush pgm pool cache!\n"));
3455	pgmPoolFlushAll(pVM);
3456	}
3457	#endif
3458
3459	/*
3460	* Enter the new guest and shadow+guest modes.
3461	*/
3462	int rc = -1;
3463	int rc2 = -1;
3464	RTGCPHYS GCPhysCR3 = NIL_RTGCPHYS;
3465	pVM->pgm.s.enmGuestMode = enmGuestMode;
3466	switch (enmGuestMode)
3467	{
3468	case PGMMODE_REAL:
3469	rc = PGM_GST_NAME_REAL(Enter)(pVM, NIL_RTGCPHYS);
3470	switch (pVM->pgm.s.enmShadowMode)
3471	{
3472	case PGMMODE_32_BIT:
3473	rc2 = PGM_BTH_NAME_32BIT_REAL(Enter)(pVM, NIL_RTGCPHYS);
3474	break;
3475	case PGMMODE_PAE:
3476	case PGMMODE_PAE_NX:
3477	rc2 = PGM_BTH_NAME_PAE_REAL(Enter)(pVM, NIL_RTGCPHYS);
3478	break;
3479	case PGMMODE_NESTED:
3480	rc2 = PGM_BTH_NAME_NESTED_REAL(Enter)(pVM, NIL_RTGCPHYS);
3481	break;
3482	case PGMMODE_EPT:
3483	rc2 = PGM_BTH_NAME_EPT_REAL(Enter)(pVM, NIL_RTGCPHYS);
3484	break;
3485	case PGMMODE_AMD64:
3486	case PGMMODE_AMD64_NX:
3487	AssertMsgFailed(("Should use PAE shadow mode!\n"));
3488	default: AssertFailed(); break;
3489	}
3490	break;
3491
3492	case PGMMODE_PROTECTED:
3493	rc = PGM_GST_NAME_PROT(Enter)(pVM, NIL_RTGCPHYS);
3494	switch (pVM->pgm.s.enmShadowMode)
3495	{
3496	case PGMMODE_32_BIT:
3497	rc2 = PGM_BTH_NAME_32BIT_PROT(Enter)(pVM, NIL_RTGCPHYS);
3498	break;
3499	case PGMMODE_PAE:
3500	case PGMMODE_PAE_NX:
3501	rc2 = PGM_BTH_NAME_PAE_PROT(Enter)(pVM, NIL_RTGCPHYS);
3502	break;
3503	case PGMMODE_NESTED:
3504	rc2 = PGM_BTH_NAME_NESTED_PROT(Enter)(pVM, NIL_RTGCPHYS);
3505	break;
3506	case PGMMODE_EPT:
3507	rc2 = PGM_BTH_NAME_EPT_PROT(Enter)(pVM, NIL_RTGCPHYS);
3508	break;
3509	case PGMMODE_AMD64:
3510	case PGMMODE_AMD64_NX:
3511	AssertMsgFailed(("Should use PAE shadow mode!\n"));
3512	default: AssertFailed(); break;
3513	}
3514	break;
3515
3516	case PGMMODE_32_BIT:
3517	GCPhysCR3 = CPUMGetGuestCR3(pVM) & X86_CR3_PAGE_MASK;
3518	rc = PGM_GST_NAME_32BIT(Enter)(pVM, GCPhysCR3);
3519	switch (pVM->pgm.s.enmShadowMode)
3520	{
3521	case PGMMODE_32_BIT:
3522	rc2 = PGM_BTH_NAME_32BIT_32BIT(Enter)(pVM, GCPhysCR3);
3523	break;
3524	case PGMMODE_PAE:
3525	case PGMMODE_PAE_NX:
3526	rc2 = PGM_BTH_NAME_PAE_32BIT(Enter)(pVM, GCPhysCR3);
3527	break;
3528	case PGMMODE_NESTED:
3529	rc2 = PGM_BTH_NAME_NESTED_32BIT(Enter)(pVM, GCPhysCR3);
3530	break;
3531	case PGMMODE_EPT:
3532	rc2 = PGM_BTH_NAME_EPT_32BIT(Enter)(pVM, GCPhysCR3);
3533	break;
3534	case PGMMODE_AMD64:
3535	case PGMMODE_AMD64_NX:
3536	AssertMsgFailed(("Should use PAE shadow mode!\n"));
3537	default: AssertFailed(); break;
3538	}
3539	break;
3540
3541	case PGMMODE_PAE_NX:
3542	case PGMMODE_PAE:
3543	{
3544	uint32_t u32Dummy, u32Features;
3545
3546	CPUMGetGuestCpuId(pVM, 1, &u32Dummy, &u32Dummy, &u32Dummy, &u32Features);
3547	if (!(u32Features & X86_CPUID_FEATURE_EDX_PAE))
3548	{
3549	/* Pause first, then inform Main. */
3550	rc = VMR3SuspendNoSave(pVM);
3551	AssertRC(rc);
3552
3553	VMSetRuntimeError(pVM, true, "PAEmode",
3554	N_("The guest is trying to switch to the PAE mode which is currently disabled by default in VirtualBox. PAE support can be enabled using the VM settings (General/Advanced)"));
3555	/* we must return VINF_SUCCESS here otherwise the recompiler will assert */
3556	return VINF_SUCCESS;
3557	}
3558	GCPhysCR3 = CPUMGetGuestCR3(pVM) & X86_CR3_PAE_PAGE_MASK;
3559	rc = PGM_GST_NAME_PAE(Enter)(pVM, GCPhysCR3);
3560	switch (pVM->pgm.s.enmShadowMode)
3561	{
3562	case PGMMODE_PAE:
3563	case PGMMODE_PAE_NX:
3564	rc2 = PGM_BTH_NAME_PAE_PAE(Enter)(pVM, GCPhysCR3);
3565	break;
3566	case PGMMODE_NESTED:
3567	rc2 = PGM_BTH_NAME_NESTED_PAE(Enter)(pVM, GCPhysCR3);
3568	break;
3569	case PGMMODE_EPT:
3570	rc2 = PGM_BTH_NAME_EPT_PAE(Enter)(pVM, GCPhysCR3);
3571	break;
3572	case PGMMODE_32_BIT:
3573	case PGMMODE_AMD64:
3574	case PGMMODE_AMD64_NX:
3575	AssertMsgFailed(("Should use PAE shadow mode!\n"));
3576	default: AssertFailed(); break;
3577	}
3578	break;
3579	}
3580
3581	#ifdef VBOX_WITH_64_BITS_GUESTS
3582	case PGMMODE_AMD64_NX:
3583	case PGMMODE_AMD64:
3584	GCPhysCR3 = CPUMGetGuestCR3(pVM) & UINT64_C(0xfffffffffffff000); /** @todo define this mask! */
3585	rc = PGM_GST_NAME_AMD64(Enter)(pVM, GCPhysCR3);
3586	switch (pVM->pgm.s.enmShadowMode)
3587	{
3588	case PGMMODE_AMD64:
3589	case PGMMODE_AMD64_NX:
3590	rc2 = PGM_BTH_NAME_AMD64_AMD64(Enter)(pVM, GCPhysCR3);
3591	break;
3592	case PGMMODE_NESTED:
3593	rc2 = PGM_BTH_NAME_NESTED_AMD64(Enter)(pVM, GCPhysCR3);
3594	break;
3595	case PGMMODE_EPT:
3596	rc2 = PGM_BTH_NAME_EPT_AMD64(Enter)(pVM, GCPhysCR3);
3597	break;
3598	case PGMMODE_32_BIT:
3599	case PGMMODE_PAE:
3600	case PGMMODE_PAE_NX:
3601	AssertMsgFailed(("Should use AMD64 shadow mode!\n"));
3602	default: AssertFailed(); break;
3603	}
3604	break;
3605	#endif
3606
3607	default:
3608	AssertReleaseMsgFailed(("enmGuestMode=%d\n", enmGuestMode));
3609	rc = VERR_NOT_IMPLEMENTED;
3610	break;
3611	}
3612
3613	/* status codes. */
3614	AssertRC(rc);
3615	AssertRC(rc2);
3616	if (RT_SUCCESS(rc))
3617	{
3618	rc = rc2;
3619	if (RT_SUCCESS(rc)) /* no informational status codes. */
3620	rc = VINF_SUCCESS;
3621	}
3622
3623	/*
3624	* Notify SELM so it can update the TSSes with correct CR3s.
3625	*/
3626	SELMR3PagingModeChanged(pVM);
3627
3628	/* Notify HWACCM as well. */
3629	HWACCMR3PagingModeChanged(pVM, pVM->pgm.s.enmShadowMode, pVM->pgm.s.enmGuestMode);
3630	return rc;
3631	}
3632
3633
3634	/**
3635	* Dumps a PAE shadow page table.
3636	*
3637	* @returns VBox status code (VINF_SUCCESS).
3638	* @param pVM The VM handle.
3639	* @param pPT Pointer to the page table.
3640	* @param u64Address The virtual address of the page table starts.
3641	* @param fLongMode Set if this a long mode table; clear if it's a legacy mode table.
3642	* @param cMaxDepth The maxium depth.
3643	* @param pHlp Pointer to the output functions.
3644	*/
3645	static int pgmR3DumpHierarchyHCPaePT(PVM pVM, PX86PTPAE pPT, uint64_t u64Address, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
3646	{
3647	for (unsigned i = 0; i < RT_ELEMENTS(pPT->a); i++)
3648	{
3649	X86PTEPAE Pte = pPT->a[i];
3650	if (Pte.n.u1Present)
3651	{
3652	pHlp->pfnPrintf(pHlp,
3653	fLongMode /P R S A D G WT CD AT NX 4M a p ? /
3654	? "%016llx 3 \| P %c %c %c %c %c %s %s %s %s 4K %c%c%c %016llx\n"
3655	: "%08llx 2 \| P %c %c %c %c %c %s %s %s %s 4K %c%c%c %016llx\n",
3656	u64Address + ((uint64_t)i << X86_PT_PAE_SHIFT),
3657	Pte.n.u1Write ? 'W' : 'R',
3658	Pte.n.u1User ? 'U' : 'S',
3659	Pte.n.u1Accessed ? 'A' : '-',
3660	Pte.n.u1Dirty ? 'D' : '-',
3661	Pte.n.u1Global ? 'G' : '-',
3662	Pte.n.u1WriteThru ? "WT" : "--",
3663	Pte.n.u1CacheDisable? "CD" : "--",
3664	Pte.n.u1PAT ? "AT" : "--",
3665	Pte.n.u1NoExecute ? "NX" : "--",
3666	Pte.u & PGM_PTFLAGS_TRACK_DIRTY ? 'd' : '-',
3667	Pte.u & RT_BIT(10) ? '1' : '0',
3668	Pte.u & PGM_PTFLAGS_CSAM_VALIDATED? 'v' : '-',
3669	Pte.u & X86_PTE_PAE_PG_MASK);
3670	}
3671	}
3672	return VINF_SUCCESS;
3673	}
3674
3675
3676	/**
3677	* Dumps a PAE shadow page directory table.
3678	*
3679	* @returns VBox status code (VINF_SUCCESS).
3680	* @param pVM The VM handle.
3681	* @param HCPhys The physical address of the page directory table.
3682	* @param u64Address The virtual address of the page table starts.
3683	* @param cr4 The CR4, PSE is currently used.
3684	* @param fLongMode Set if this a long mode table; clear if it's a legacy mode table.
3685	* @param cMaxDepth The maxium depth.
3686	* @param pHlp Pointer to the output functions.
3687	*/
3688	static int pgmR3DumpHierarchyHCPaePD(PVM pVM, RTHCPHYS HCPhys, uint64_t u64Address, uint32_t cr4, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
3689	{
3690	PX86PDPAE pPD = (PX86PDPAE)MMPagePhys2Page(pVM, HCPhys);
3691	if (!pPD)
3692	{
3693	pHlp->pfnPrintf(pHlp, "%0*llx error! Page directory at HCPhys=%RHp was not found in the page pool!\n",
3694	fLongMode ? 16 : 8, u64Address, HCPhys);
3695	return VERR_INVALID_PARAMETER;
3696	}
3697	const bool fBigPagesSupported = fLongMode \|\| !!(cr4 & X86_CR4_PSE);
3698
3699	int rc = VINF_SUCCESS;
3700	for (unsigned i = 0; i < RT_ELEMENTS(pPD->a); i++)
3701	{
3702	X86PDEPAE Pde = pPD->a[i];
3703	if (Pde.n.u1Present)
3704	{
3705	if (fBigPagesSupported && Pde.b.u1Size)
3706	pHlp->pfnPrintf(pHlp,
3707	fLongMode /P R S A D G WT CD AT NX 4M a p ? /
3708	? "%016llx 2 \| P %c %c %c %c %c %s %s %s %s 4M %c%c%c %016llx\n"
3709	: "%08llx 1 \| P %c %c %c %c %c %s %s %s %s 4M %c%c%c %016llx\n",
3710	u64Address + ((uint64_t)i << X86_PD_PAE_SHIFT),
3711	Pde.b.u1Write ? 'W' : 'R',
3712	Pde.b.u1User ? 'U' : 'S',
3713	Pde.b.u1Accessed ? 'A' : '-',
3714	Pde.b.u1Dirty ? 'D' : '-',
3715	Pde.b.u1Global ? 'G' : '-',
3716	Pde.b.u1WriteThru ? "WT" : "--",
3717	Pde.b.u1CacheDisable? "CD" : "--",
3718	Pde.b.u1PAT ? "AT" : "--",
3719	Pde.b.u1NoExecute ? "NX" : "--",
3720	Pde.u & RT_BIT_64(9) ? '1' : '0',
3721	Pde.u & PGM_PDFLAGS_MAPPING ? 'm' : '-',
3722	Pde.u & PGM_PDFLAGS_TRACK_DIRTY ? 'd' : '-',
3723	Pde.u & X86_PDE_PAE_PG_MASK);
3724	else
3725	{
3726	pHlp->pfnPrintf(pHlp,
3727	fLongMode /P R S A D G WT CD AT NX 4M a p ? /
3728	? "%016llx 2 \| P %c %c %c %c %c %s %s .. %s 4K %c%c%c %016llx\n"
3729	: "%08llx 1 \| P %c %c %c %c %c %s %s .. %s 4K %c%c%c %016llx\n",
3730	u64Address + ((uint64_t)i << X86_PD_PAE_SHIFT),
3731	Pde.n.u1Write ? 'W' : 'R',
3732	Pde.n.u1User ? 'U' : 'S',
3733	Pde.n.u1Accessed ? 'A' : '-',
3734	Pde.n.u1Reserved0 ? '?' : '.', /* ignored */
3735	Pde.n.u1Reserved1 ? '?' : '.', /* ignored */
3736	Pde.n.u1WriteThru ? "WT" : "--",
3737	Pde.n.u1CacheDisable? "CD" : "--",
3738	Pde.n.u1NoExecute ? "NX" : "--",
3739	Pde.u & RT_BIT_64(9) ? '1' : '0',
3740	Pde.u & PGM_PDFLAGS_MAPPING ? 'm' : '-',
3741	Pde.u & PGM_PDFLAGS_TRACK_DIRTY ? 'd' : '-',
3742	Pde.u & X86_PDE_PAE_PG_MASK);
3743	if (cMaxDepth >= 1)
3744	{
3745	/** @todo what about using the page pool for mapping PTs? */
3746	uint64_t u64AddressPT = u64Address + ((uint64_t)i << X86_PD_PAE_SHIFT);
3747	RTHCPHYS HCPhysPT = Pde.u & X86_PDE_PAE_PG_MASK;
3748	PX86PTPAE pPT = NULL;
3749	if (!(Pde.u & PGM_PDFLAGS_MAPPING))
3750	pPT = (PX86PTPAE)MMPagePhys2Page(pVM, HCPhysPT);
3751	else
3752	{
3753	for (PPGMMAPPING pMap = pVM->pgm.s.pMappingsR3; pMap; pMap = pMap->pNextR3)
3754	{
3755	uint64_t off = u64AddressPT - pMap->GCPtr;
3756	if (off < pMap->cb)
3757	{
3758	const int iPDE = (uint32_t)(off >> X86_PD_SHIFT);
3759	const int iSub = (int)((off >> X86_PD_PAE_SHIFT) & 1); /* MSC is a pain sometimes */
3760	if ((iSub ? pMap->aPTs[iPDE].HCPhysPaePT1 : pMap->aPTs[iPDE].HCPhysPaePT0) != HCPhysPT)
3761	pHlp->pfnPrintf(pHlp, "%0*llx error! Mapping error! PT %d has HCPhysPT=%RHp not %RHp is in the PD.\n",
3762	fLongMode ? 16 : 8, u64AddressPT, iPDE,
3763	iSub ? pMap->aPTs[iPDE].HCPhysPaePT1 : pMap->aPTs[iPDE].HCPhysPaePT0, HCPhysPT);
3764	pPT = &pMap->aPTs[iPDE].paPaePTsR3[iSub];
3765	}
3766	}
3767	}
3768	int rc2 = VERR_INVALID_PARAMETER;
3769	if (pPT)
3770	rc2 = pgmR3DumpHierarchyHCPaePT(pVM, pPT, u64AddressPT, fLongMode, cMaxDepth - 1, pHlp);
3771	else
3772	pHlp->pfnPrintf(pHlp, "%0*llx error! Page table at HCPhys=%RHp was not found in the page pool!\n",
3773	fLongMode ? 16 : 8, u64AddressPT, HCPhysPT);
3774	if (rc2 < rc && RT_SUCCESS(rc))
3775	rc = rc2;
3776	}
3777	}
3778	}
3779	}
3780	return rc;
3781	}
3782
3783
3784	/**
3785	* Dumps a PAE shadow page directory pointer table.
3786	*
3787	* @returns VBox status code (VINF_SUCCESS).
3788	* @param pVM The VM handle.
3789	* @param HCPhys The physical address of the page directory pointer table.
3790	* @param u64Address The virtual address of the page table starts.
3791	* @param cr4 The CR4, PSE is currently used.
3792	* @param fLongMode Set if this a long mode table; clear if it's a legacy mode table.
3793	* @param cMaxDepth The maxium depth.
3794	* @param pHlp Pointer to the output functions.
3795	*/
3796	static int pgmR3DumpHierarchyHCPaePDPT(PVM pVM, RTHCPHYS HCPhys, uint64_t u64Address, uint32_t cr4, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
3797	{
3798	PX86PDPT pPDPT = (PX86PDPT)MMPagePhys2Page(pVM, HCPhys);
3799	if (!pPDPT)
3800	{
3801	pHlp->pfnPrintf(pHlp, "%0*llx error! Page directory pointer table at HCPhys=%RHp was not found in the page pool!\n",
3802	fLongMode ? 16 : 8, u64Address, HCPhys);
3803	return VERR_INVALID_PARAMETER;
3804	}
3805
3806	int rc = VINF_SUCCESS;
3807	const unsigned c = fLongMode ? RT_ELEMENTS(pPDPT->a) : X86_PG_PAE_PDPE_ENTRIES;
3808	for (unsigned i = 0; i < c; i++)
3809	{
3810	X86PDPE Pdpe = pPDPT->a[i];
3811	if (Pdpe.n.u1Present)
3812	{
3813	if (fLongMode)
3814	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a p ? /
3815	"%016llx 1 \| P %c %c %c %c %c %s %s %s %s .. %c%c%c %016llx\n",
3816	u64Address + ((uint64_t)i << X86_PDPT_SHIFT),
3817	Pdpe.lm.u1Write ? 'W' : 'R',
3818	Pdpe.lm.u1User ? 'U' : 'S',
3819	Pdpe.lm.u1Accessed ? 'A' : '-',
3820	Pdpe.lm.u3Reserved & 1? '?' : '.', /* ignored */
3821	Pdpe.lm.u3Reserved & 4? '!' : '.', /* mbz */
3822	Pdpe.lm.u1WriteThru ? "WT" : "--",
3823	Pdpe.lm.u1CacheDisable? "CD" : "--",
3824	Pdpe.lm.u3Reserved & 2? "!" : "..",/* mbz */
3825	Pdpe.lm.u1NoExecute ? "NX" : "--",
3826	Pdpe.u & RT_BIT(9) ? '1' : '0',
3827	Pdpe.u & PGM_PLXFLAGS_PERMANENT ? 'p' : '-',
3828	Pdpe.u & RT_BIT(11) ? '1' : '0',
3829	Pdpe.u & X86_PDPE_PG_MASK);
3830	else
3831	pHlp->pfnPrintf(pHlp, /P G WT CD AT NX 4M a p ? /
3832	"%08x 0 \| P %c %s %s %s %s .. %c%c%c %016llx\n",
3833	i << X86_PDPT_SHIFT,
3834	Pdpe.n.u4Reserved & 1? '!' : '.', /* mbz */
3835	Pdpe.n.u4Reserved & 4? '!' : '.', /* mbz */
3836	Pdpe.n.u1WriteThru ? "WT" : "--",
3837	Pdpe.n.u1CacheDisable? "CD" : "--",
3838	Pdpe.n.u4Reserved & 2? "!" : "..",/* mbz */
3839	Pdpe.u & RT_BIT(9) ? '1' : '0',
3840	Pdpe.u & PGM_PLXFLAGS_PERMANENT ? 'p' : '-',
3841	Pdpe.u & RT_BIT(11) ? '1' : '0',
3842	Pdpe.u & X86_PDPE_PG_MASK);
3843	if (cMaxDepth >= 1)
3844	{
3845	int rc2 = pgmR3DumpHierarchyHCPaePD(pVM, Pdpe.u & X86_PDPE_PG_MASK, u64Address + ((uint64_t)i << X86_PDPT_SHIFT),
3846	cr4, fLongMode, cMaxDepth - 1, pHlp);
3847	if (rc2 < rc && RT_SUCCESS(rc))
3848	rc = rc2;
3849	}
3850	}
3851	}
3852	return rc;
3853	}
3854
3855
3856	/**
3857	* Dumps a 32-bit shadow page table.
3858	*
3859	* @returns VBox status code (VINF_SUCCESS).
3860	* @param pVM The VM handle.
3861	* @param HCPhys The physical address of the table.
3862	* @param cr4 The CR4, PSE is currently used.
3863	* @param cMaxDepth The maxium depth.
3864	* @param pHlp Pointer to the output functions.
3865	*/
3866	static int pgmR3DumpHierarchyHcPaePML4(PVM pVM, RTHCPHYS HCPhys, uint32_t cr4, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
3867	{
3868	PX86PML4 pPML4 = (PX86PML4)MMPagePhys2Page(pVM, HCPhys);
3869	if (!pPML4)
3870	{
3871	pHlp->pfnPrintf(pHlp, "Page map level 4 at HCPhys=%RHp was not found in the page pool!\n", HCPhys);
3872	return VERR_INVALID_PARAMETER;
3873	}
3874
3875	int rc = VINF_SUCCESS;
3876	for (unsigned i = 0; i < RT_ELEMENTS(pPML4->a); i++)
3877	{
3878	X86PML4E Pml4e = pPML4->a[i];
3879	if (Pml4e.n.u1Present)
3880	{
3881	uint64_t u64Address = ((uint64_t)i << X86_PML4_SHIFT) \| (((uint64_t)i >> (X86_PML4_SHIFT - X86_PDPT_SHIFT - 1)) * 0xffff000000000000ULL);
3882	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a p ? /
3883	"%016llx 0 \| P %c %c %c %c %c %s %s %s %s .. %c%c%c %016llx\n",
3884	u64Address,
3885	Pml4e.n.u1Write ? 'W' : 'R',
3886	Pml4e.n.u1User ? 'U' : 'S',
3887	Pml4e.n.u1Accessed ? 'A' : '-',
3888	Pml4e.n.u3Reserved & 1? '?' : '.', /* ignored */
3889	Pml4e.n.u3Reserved & 4? '!' : '.', /* mbz */
3890	Pml4e.n.u1WriteThru ? "WT" : "--",
3891	Pml4e.n.u1CacheDisable? "CD" : "--",
3892	Pml4e.n.u3Reserved & 2? "!" : "..",/* mbz */
3893	Pml4e.n.u1NoExecute ? "NX" : "--",
3894	Pml4e.u & RT_BIT(9) ? '1' : '0',
3895	Pml4e.u & PGM_PLXFLAGS_PERMANENT ? 'p' : '-',
3896	Pml4e.u & RT_BIT(11) ? '1' : '0',
3897	Pml4e.u & X86_PML4E_PG_MASK);
3898
3899	if (cMaxDepth >= 1)
3900	{
3901	int rc2 = pgmR3DumpHierarchyHCPaePDPT(pVM, Pml4e.u & X86_PML4E_PG_MASK, u64Address, cr4, true, cMaxDepth - 1, pHlp);
3902	if (rc2 < rc && RT_SUCCESS(rc))
3903	rc = rc2;
3904	}
3905	}
3906	}
3907	return rc;
3908	}
3909
3910
3911	/**
3912	* Dumps a 32-bit shadow page table.
3913	*
3914	* @returns VBox status code (VINF_SUCCESS).
3915	* @param pVM The VM handle.
3916	* @param pPT Pointer to the page table.
3917	* @param u32Address The virtual address this table starts at.
3918	* @param pHlp Pointer to the output functions.
3919	*/
3920	int pgmR3DumpHierarchyHC32BitPT(PVM pVM, PX86PT pPT, uint32_t u32Address, PCDBGFINFOHLP pHlp)
3921	{
3922	for (unsigned i = 0; i < RT_ELEMENTS(pPT->a); i++)
3923	{
3924	X86PTE Pte = pPT->a[i];
3925	if (Pte.n.u1Present)
3926	{
3927	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a m d /
3928	"%08x 1 \| P %c %c %c %c %c %s %s %s .. 4K %c%c%c %08x\n",
3929	u32Address + (i << X86_PT_SHIFT),
3930	Pte.n.u1Write ? 'W' : 'R',
3931	Pte.n.u1User ? 'U' : 'S',
3932	Pte.n.u1Accessed ? 'A' : '-',
3933	Pte.n.u1Dirty ? 'D' : '-',
3934	Pte.n.u1Global ? 'G' : '-',
3935	Pte.n.u1WriteThru ? "WT" : "--",
3936	Pte.n.u1CacheDisable? "CD" : "--",
3937	Pte.n.u1PAT ? "AT" : "--",
3938	Pte.u & PGM_PTFLAGS_TRACK_DIRTY ? 'd' : '-',
3939	Pte.u & RT_BIT(10) ? '1' : '0',
3940	Pte.u & PGM_PTFLAGS_CSAM_VALIDATED ? 'v' : '-',
3941	Pte.u & X86_PDE_PG_MASK);
3942	}
3943	}
3944	return VINF_SUCCESS;
3945	}
3946
3947
3948	/**
3949	* Dumps a 32-bit shadow page directory and page tables.
3950	*
3951	* @returns VBox status code (VINF_SUCCESS).
3952	* @param pVM The VM handle.
3953	* @param cr3 The root of the hierarchy.
3954	* @param cr4 The CR4, PSE is currently used.
3955	* @param cMaxDepth How deep into the hierarchy the dumper should go.
3956	* @param pHlp Pointer to the output functions.
3957	*/
3958	int pgmR3DumpHierarchyHC32BitPD(PVM pVM, uint32_t cr3, uint32_t cr4, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
3959	{
3960	PX86PD pPD = (PX86PD)MMPagePhys2Page(pVM, cr3 & X86_CR3_PAGE_MASK);
3961	if (!pPD)
3962	{
3963	pHlp->pfnPrintf(pHlp, "Page directory at %#x was not found in the page pool!\n", cr3 & X86_CR3_PAGE_MASK);
3964	return VERR_INVALID_PARAMETER;
3965	}
3966
3967	int rc = VINF_SUCCESS;
3968	for (unsigned i = 0; i < RT_ELEMENTS(pPD->a); i++)
3969	{
3970	X86PDE Pde = pPD->a[i];
3971	if (Pde.n.u1Present)
3972	{
3973	const uint32_t u32Address = i << X86_PD_SHIFT;
3974	if ((cr4 & X86_CR4_PSE) && Pde.b.u1Size)
3975	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a m d /
3976	"%08x 0 \| P %c %c %c %c %c %s %s %s .. 4M %c%c%c %08x\n",
3977	u32Address,
3978	Pde.b.u1Write ? 'W' : 'R',
3979	Pde.b.u1User ? 'U' : 'S',
3980	Pde.b.u1Accessed ? 'A' : '-',
3981	Pde.b.u1Dirty ? 'D' : '-',
3982	Pde.b.u1Global ? 'G' : '-',
3983	Pde.b.u1WriteThru ? "WT" : "--",
3984	Pde.b.u1CacheDisable? "CD" : "--",
3985	Pde.b.u1PAT ? "AT" : "--",
3986	Pde.u & RT_BIT_64(9) ? '1' : '0',
3987	Pde.u & PGM_PDFLAGS_MAPPING ? 'm' : '-',
3988	Pde.u & PGM_PDFLAGS_TRACK_DIRTY ? 'd' : '-',
3989	Pde.u & X86_PDE4M_PG_MASK);
3990	else
3991	{
3992	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a m d /
3993	"%08x 0 \| P %c %c %c %c %c %s %s .. .. 4K %c%c%c %08x\n",
3994	u32Address,
3995	Pde.n.u1Write ? 'W' : 'R',
3996	Pde.n.u1User ? 'U' : 'S',
3997	Pde.n.u1Accessed ? 'A' : '-',
3998	Pde.n.u1Reserved0 ? '?' : '.', /* ignored */
3999	Pde.n.u1Reserved1 ? '?' : '.', /* ignored */
4000	Pde.n.u1WriteThru ? "WT" : "--",
4001	Pde.n.u1CacheDisable? "CD" : "--",
4002	Pde.u & RT_BIT_64(9) ? '1' : '0',
4003	Pde.u & PGM_PDFLAGS_MAPPING ? 'm' : '-',
4004	Pde.u & PGM_PDFLAGS_TRACK_DIRTY ? 'd' : '-',
4005	Pde.u & X86_PDE_PG_MASK);
4006	if (cMaxDepth >= 1)
4007	{
4008	/** @todo what about using the page pool for mapping PTs? */
4009	RTHCPHYS HCPhys = Pde.u & X86_PDE_PG_MASK;
4010	PX86PT pPT = NULL;
4011	if (!(Pde.u & PGM_PDFLAGS_MAPPING))
4012	pPT = (PX86PT)MMPagePhys2Page(pVM, HCPhys);
4013	else
4014	{
4015	for (PPGMMAPPING pMap = pVM->pgm.s.pMappingsR3; pMap; pMap = pMap->pNextR3)
4016	if (u32Address - pMap->GCPtr < pMap->cb)
4017	{
4018	int iPDE = (u32Address - pMap->GCPtr) >> X86_PD_SHIFT;
4019	if (pMap->aPTs[iPDE].HCPhysPT != HCPhys)
4020	pHlp->pfnPrintf(pHlp, "%08x error! Mapping error! PT %d has HCPhysPT=%RHp not %RHp is in the PD.\n",
4021	u32Address, iPDE, pMap->aPTs[iPDE].HCPhysPT, HCPhys);
4022	pPT = pMap->aPTs[iPDE].pPTR3;
4023	}
4024	}
4025	int rc2 = VERR_INVALID_PARAMETER;
4026	if (pPT)
4027	rc2 = pgmR3DumpHierarchyHC32BitPT(pVM, pPT, u32Address, pHlp);
4028	else
4029	pHlp->pfnPrintf(pHlp, "%08x error! Page table at %#x was not found in the page pool!\n", u32Address, HCPhys);
4030	if (rc2 < rc && RT_SUCCESS(rc))
4031	rc = rc2;
4032	}
4033	}
4034	}
4035	}
4036
4037	return rc;
4038	}
4039
4040
4041	/**
4042	* Dumps a 32-bit shadow page table.
4043	*
4044	* @returns VBox status code (VINF_SUCCESS).
4045	* @param pVM The VM handle.
4046	* @param pPT Pointer to the page table.
4047	* @param u32Address The virtual address this table starts at.
4048	* @param PhysSearch Address to search for.
4049	*/
4050	int pgmR3DumpHierarchyGC32BitPT(PVM pVM, PX86PT pPT, uint32_t u32Address, RTGCPHYS PhysSearch)
4051	{
4052	for (unsigned i = 0; i < RT_ELEMENTS(pPT->a); i++)
4053	{
4054	X86PTE Pte = pPT->a[i];
4055	if (Pte.n.u1Present)
4056	{
4057	Log(( /P R S A D G WT CD AT NX 4M a m d /
4058	"%08x 1 \| P %c %c %c %c %c %s %s %s .. 4K %c%c%c %08x\n",
4059	u32Address + (i << X86_PT_SHIFT),
4060	Pte.n.u1Write ? 'W' : 'R',
4061	Pte.n.u1User ? 'U' : 'S',
4062	Pte.n.u1Accessed ? 'A' : '-',
4063	Pte.n.u1Dirty ? 'D' : '-',
4064	Pte.n.u1Global ? 'G' : '-',
4065	Pte.n.u1WriteThru ? "WT" : "--",
4066	Pte.n.u1CacheDisable? "CD" : "--",
4067	Pte.n.u1PAT ? "AT" : "--",
4068	Pte.u & PGM_PTFLAGS_TRACK_DIRTY ? 'd' : '-',
4069	Pte.u & RT_BIT(10) ? '1' : '0',
4070	Pte.u & PGM_PTFLAGS_CSAM_VALIDATED ? 'v' : '-',
4071	Pte.u & X86_PDE_PG_MASK));
4072
4073	if ((Pte.u & X86_PDE_PG_MASK) == PhysSearch)
4074	{
4075	uint64_t fPageShw = 0;
4076	RTHCPHYS pPhysHC = 0;
4077
4078	PGMShwGetPage(pVM, (RTGCPTR)(u32Address + (i << X86_PT_SHIFT)), &fPageShw, &pPhysHC);
4079	Log(("Found %RGp at %RGv -> flags=%llx\n", PhysSearch, (RTGCPTR)(u32Address + (i << X86_PT_SHIFT)), fPageShw));
4080	}
4081	}
4082	}
4083	return VINF_SUCCESS;
4084	}
4085
4086
4087	/**
4088	* Dumps a 32-bit guest page directory and page tables.
4089	*
4090	* @returns VBox status code (VINF_SUCCESS).
4091	* @param pVM The VM handle.
4092	* @param cr3 The root of the hierarchy.
4093	* @param cr4 The CR4, PSE is currently used.
4094	* @param PhysSearch Address to search for.
4095	*/
4096	VMMR3DECL(int) PGMR3DumpHierarchyGC(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCPHYS PhysSearch)
4097	{
4098	bool fLongMode = false;
4099	const unsigned cch = fLongMode ? 16 : 8; NOREF(cch);
4100	PX86PD pPD = 0;
4101
4102	int rc = PGM_GCPHYS_2_PTR(pVM, cr3 & X86_CR3_PAGE_MASK, &pPD);
4103	if (RT_FAILURE(rc) \|\| !pPD)
4104	{
4105	Log(("Page directory at %#x was not found in the page pool!\n", cr3 & X86_CR3_PAGE_MASK));
4106	return VERR_INVALID_PARAMETER;
4107	}
4108
4109	Log(("cr3=%08x cr4=%08x%s\n"
4110	"%-*s P - Present\n"
4111	"%-*s \| R/W - Read (0) / Write (1)\n"
4112	"%-*s \| \| U/S - User (1) / Supervisor (0)\n"
4113	"%-*s \| \| \| A - Accessed\n"
4114	"%-*s \| \| \| \| D - Dirty\n"
4115	"%-*s \| \| \| \| \| G - Global\n"
4116	"%-*s \| \| \| \| \| \| WT - Write thru\n"
4117	"%-*s \| \| \| \| \| \| \| CD - Cache disable\n"
4118	"%-*s \| \| \| \| \| \| \| \| AT - Attribute table (PAT)\n"
4119	"%-*s \| \| \| \| \| \| \| \| \| NX - No execute (K8)\n"
4120	"%-*s \| \| \| \| \| \| \| \| \| \| 4K/4M/2M - Page size.\n"
4121	"%-*s \| \| \| \| \| \| \| \| \| \| \| AVL - a=allocated; m=mapping; d=track dirty;\n"
4122	"%-*s \| \| \| \| \| \| \| \| \| \| \| \| p=permanent; v=validated;\n"
4123	"%-*s Level \| \| \| \| \| \| \| \| \| \| \| \| Page\n"
4124	/* xxxx n **** P R S A D G WT CD AT NX 4M AVL xxxxxxxxxxxxx
4125	- W U - - - -- -- -- -- -- 010 */
4126	, cr3, cr4, fLongMode ? " Long Mode" : "",
4127	cch, "", cch, "", cch, "", cch, "", cch, "", cch, "", cch, "",
4128	cch, "", cch, "", cch, "", cch, "", cch, "", cch, "", cch, "Address"));
4129
4130	for (unsigned i = 0; i < RT_ELEMENTS(pPD->a); i++)
4131	{
4132	X86PDE Pde = pPD->a[i];
4133	if (Pde.n.u1Present)
4134	{
4135	const uint32_t u32Address = i << X86_PD_SHIFT;
4136
4137	if ((cr4 & X86_CR4_PSE) && Pde.b.u1Size)
4138	Log(( /P R S A D G WT CD AT NX 4M a m d /
4139	"%08x 0 \| P %c %c %c %c %c %s %s %s .. 4M %c%c%c %08x\n",
4140	u32Address,
4141	Pde.b.u1Write ? 'W' : 'R',
4142	Pde.b.u1User ? 'U' : 'S',
4143	Pde.b.u1Accessed ? 'A' : '-',
4144	Pde.b.u1Dirty ? 'D' : '-',
4145	Pde.b.u1Global ? 'G' : '-',
4146	Pde.b.u1WriteThru ? "WT" : "--",
4147	Pde.b.u1CacheDisable? "CD" : "--",
4148	Pde.b.u1PAT ? "AT" : "--",
4149	Pde.u & RT_BIT(9) ? '1' : '0',
4150	Pde.u & RT_BIT(10) ? '1' : '0',
4151	Pde.u & RT_BIT(11) ? '1' : '0',
4152	pgmGstGet4MBPhysPage(&pVM->pgm.s, Pde)));
4153	/** @todo PhysSearch */
4154	else
4155	{
4156	Log(( /P R S A D G WT CD AT NX 4M a m d /
4157	"%08x 0 \| P %c %c %c %c %c %s %s .. .. 4K %c%c%c %08x\n",
4158	u32Address,
4159	Pde.n.u1Write ? 'W' : 'R',
4160	Pde.n.u1User ? 'U' : 'S',
4161	Pde.n.u1Accessed ? 'A' : '-',
4162	Pde.n.u1Reserved0 ? '?' : '.', /* ignored */
4163	Pde.n.u1Reserved1 ? '?' : '.', /* ignored */
4164	Pde.n.u1WriteThru ? "WT" : "--",
4165	Pde.n.u1CacheDisable? "CD" : "--",
4166	Pde.u & RT_BIT(9) ? '1' : '0',
4167	Pde.u & RT_BIT(10) ? '1' : '0',
4168	Pde.u & RT_BIT(11) ? '1' : '0',
4169	Pde.u & X86_PDE_PG_MASK));
4170	////if (cMaxDepth >= 1)
4171	{
4172	/** @todo what about using the page pool for mapping PTs? */
4173	RTGCPHYS GCPhys = Pde.u & X86_PDE_PG_MASK;
4174	PX86PT pPT = NULL;
4175
4176	rc = PGM_GCPHYS_2_PTR(pVM, GCPhys, &pPT);
4177
4178	int rc2 = VERR_INVALID_PARAMETER;
4179	if (pPT)
4180	rc2 = pgmR3DumpHierarchyGC32BitPT(pVM, pPT, u32Address, PhysSearch);
4181	else
4182	Log(("%08x error! Page table at %#x was not found in the page pool!\n", u32Address, GCPhys));
4183	if (rc2 < rc && RT_SUCCESS(rc))
4184	rc = rc2;
4185	}
4186	}
4187	}
4188	}
4189
4190	return rc;
4191	}
4192
4193
4194	/**
4195	* Dumps a page table hierarchy use only physical addresses and cr4/lm flags.
4196	*
4197	* @returns VBox status code (VINF_SUCCESS).
4198	* @param pVM The VM handle.
4199	* @param cr3 The root of the hierarchy.
4200	* @param cr4 The cr4, only PAE and PSE is currently used.
4201	* @param fLongMode Set if long mode, false if not long mode.
4202	* @param cMaxDepth Number of levels to dump.
4203	* @param pHlp Pointer to the output functions.
4204	*/
4205	VMMR3DECL(int) PGMR3DumpHierarchyHC(PVM pVM, uint64_t cr3, uint64_t cr4, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
4206	{
4207	if (!pHlp)
4208	pHlp = DBGFR3InfoLogHlp();
4209	if (!cMaxDepth)
4210	return VINF_SUCCESS;
4211	const unsigned cch = fLongMode ? 16 : 8;
4212	pHlp->pfnPrintf(pHlp,
4213	"cr3=%08x cr4=%08x%s\n"
4214	"%-*s P - Present\n"
4215	"%-*s \| R/W - Read (0) / Write (1)\n"
4216	"%-*s \| \| U/S - User (1) / Supervisor (0)\n"
4217	"%-*s \| \| \| A - Accessed\n"
4218	"%-*s \| \| \| \| D - Dirty\n"
4219	"%-*s \| \| \| \| \| G - Global\n"
4220	"%-*s \| \| \| \| \| \| WT - Write thru\n"
4221	"%-*s \| \| \| \| \| \| \| CD - Cache disable\n"
4222	"%-*s \| \| \| \| \| \| \| \| AT - Attribute table (PAT)\n"
4223	"%-*s \| \| \| \| \| \| \| \| \| NX - No execute (K8)\n"
4224	"%-*s \| \| \| \| \| \| \| \| \| \| 4K/4M/2M - Page size.\n"
4225	"%-*s \| \| \| \| \| \| \| \| \| \| \| AVL - a=allocated; m=mapping; d=track dirty;\n"
4226	"%-*s \| \| \| \| \| \| \| \| \| \| \| \| p=permanent; v=validated;\n"
4227	"%-*s Level \| \| \| \| \| \| \| \| \| \| \| \| Page\n"
4228	/* xxxx n **** P R S A D G WT CD AT NX 4M AVL xxxxxxxxxxxxx
4229	- W U - - - -- -- -- -- -- 010 */
4230	, cr3, cr4, fLongMode ? " Long Mode" : "",
4231	cch, "", cch, "", cch, "", cch, "", cch, "", cch, "", cch, "",
4232	cch, "", cch, "", cch, "", cch, "", cch, "", cch, "", cch, "Address");
4233	if (cr4 & X86_CR4_PAE)
4234	{
4235	if (fLongMode)
4236	return pgmR3DumpHierarchyHcPaePML4(pVM, cr3 & X86_CR3_PAGE_MASK, cr4, cMaxDepth, pHlp);
4237	return pgmR3DumpHierarchyHCPaePDPT(pVM, cr3 & X86_CR3_PAE_PAGE_MASK, 0, cr4, false, cMaxDepth, pHlp);
4238	}
4239	return pgmR3DumpHierarchyHC32BitPD(pVM, cr3 & X86_CR3_PAGE_MASK, cr4, cMaxDepth, pHlp);
4240	}
4241
4242	#ifdef VBOX_WITH_DEBUGGER
4243
4244	/**
4245	* The '.pgmram' command.
4246	*
4247	* @returns VBox status.
4248	* @param pCmd Pointer to the command descriptor (as registered).
4249	* @param pCmdHlp Pointer to command helper functions.
4250	* @param pVM Pointer to the current VM (if any).
4251	* @param paArgs Pointer to (readonly) array of arguments.
4252	* @param cArgs Number of arguments in the array.
4253	*/
4254	static DECLCALLBACK(int) pgmR3CmdRam(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4255	{
4256	/*
4257	* Validate input.
4258	*/
4259	if (!pVM)
4260	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4261	if (!pVM->pgm.s.pRamRangesRC)
4262	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Sorry, no Ram is registered.\n");
4263
4264	/*
4265	* Dump the ranges.
4266	*/
4267	int rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL, "From - To (incl) pvHC\n");
4268	PPGMRAMRANGE pRam;
4269	for (pRam = pVM->pgm.s.pRamRangesR3; pRam; pRam = pRam->pNextR3)
4270	{
4271	rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL,
4272	"%RGp - %RGp %p\n",
4273	pRam->GCPhys, pRam->GCPhysLast, pRam->pvR3);
4274	if (RT_FAILURE(rc))
4275	return rc;
4276	}
4277
4278	return VINF_SUCCESS;
4279	}
4280
4281
4282	/**
4283	* The '.pgmmap' command.
4284	*
4285	* @returns VBox status.
4286	* @param pCmd Pointer to the command descriptor (as registered).
4287	* @param pCmdHlp Pointer to command helper functions.
4288	* @param pVM Pointer to the current VM (if any).
4289	* @param paArgs Pointer to (readonly) array of arguments.
4290	* @param cArgs Number of arguments in the array.
4291	*/
4292	static DECLCALLBACK(int) pgmR3CmdMap(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4293	{
4294	/*
4295	* Validate input.
4296	*/
4297	if (!pVM)
4298	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4299	if (!pVM->pgm.s.pMappingsR3)
4300	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Sorry, no mappings are registered.\n");
4301
4302	/*
4303	* Print message about the fixedness of the mappings.
4304	*/
4305	int rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL, pVM->pgm.s.fMappingsFixed ? "The mappings are FIXED.\n" : "The mappings are FLOATING.\n");
4306	if (RT_FAILURE(rc))
4307	return rc;
4308
4309	/*
4310	* Dump the ranges.
4311	*/
4312	PPGMMAPPING pCur;
4313	for (pCur = pVM->pgm.s.pMappingsR3; pCur; pCur = pCur->pNextR3)
4314	{
4315	rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL,
4316	"%08x - %08x %s\n",
4317	pCur->GCPtr, pCur->GCPtrLast, pCur->pszDesc);
4318	if (RT_FAILURE(rc))
4319	return rc;
4320	}
4321
4322	return VINF_SUCCESS;
4323	}
4324
4325
4326	/**
4327	* The '.pgmsync' command.
4328	*
4329	* @returns VBox status.
4330	* @param pCmd Pointer to the command descriptor (as registered).
4331	* @param pCmdHlp Pointer to command helper functions.
4332	* @param pVM Pointer to the current VM (if any).
4333	* @param paArgs Pointer to (readonly) array of arguments.
4334	* @param cArgs Number of arguments in the array.
4335	*/
4336	static DECLCALLBACK(int) pgmR3CmdSync(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4337	{
4338	/*
4339	* Validate input.
4340	*/
4341	if (!pVM)
4342	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4343
4344	/*
4345	* Force page directory sync.
4346	*/
4347	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
4348
4349	int rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Forcing page directory sync.\n");
4350	if (RT_FAILURE(rc))
4351	return rc;
4352
4353	return VINF_SUCCESS;
4354	}
4355
4356
4357	#ifdef VBOX_STRICT
4358	/**
4359	* The '.pgmassertcr3' command.
4360	*
4361	* @returns VBox status.
4362	* @param pCmd Pointer to the command descriptor (as registered).
4363	* @param pCmdHlp Pointer to command helper functions.
4364	* @param pVM Pointer to the current VM (if any).
4365	* @param paArgs Pointer to (readonly) array of arguments.
4366	* @param cArgs Number of arguments in the array.
4367	*/
4368	static DECLCALLBACK(int) pgmR3CmdAssertCR3(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4369	{
4370	/*
4371	* Validate input.
4372	*/
4373	if (!pVM)
4374	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4375
4376	int rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Checking shadow CR3 page tables for consistency.\n");
4377	if (RT_FAILURE(rc))
4378	return rc;
4379
4380	PGMAssertCR3(pVM, CPUMGetGuestCR3(pVM), CPUMGetGuestCR4(pVM));
4381
4382	return VINF_SUCCESS;
4383	}
4384	#endif /* VBOX_STRICT */
4385
4386
4387	/**
4388	* The '.pgmsyncalways' command.
4389	*
4390	* @returns VBox status.
4391	* @param pCmd Pointer to the command descriptor (as registered).
4392	* @param pCmdHlp Pointer to command helper functions.
4393	* @param pVM Pointer to the current VM (if any).
4394	* @param paArgs Pointer to (readonly) array of arguments.
4395	* @param cArgs Number of arguments in the array.
4396	*/
4397	static DECLCALLBACK(int) pgmR3CmdSyncAlways(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4398	{
4399	/*
4400	* Validate input.
4401	*/
4402	if (!pVM)
4403	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4404
4405	/*
4406	* Force page directory sync.
4407	*/
4408	if (pVM->pgm.s.fSyncFlags & PGM_SYNC_ALWAYS)
4409	{
4410	ASMAtomicAndU32(&pVM->pgm.s.fSyncFlags, ~PGM_SYNC_ALWAYS);
4411	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Disabled permanent forced page directory syncing.\n");
4412	}
4413	else
4414	{
4415	ASMAtomicOrU32(&pVM->pgm.s.fSyncFlags, PGM_SYNC_ALWAYS);
4416	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
4417	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Enabled permanent forced page directory syncing.\n");
4418	}
4419	}
4420
4421	#endif /* VBOX_WITH_DEBUGGER */
4422
4423	/**
4424	* pvUser argument of the pgmR3CheckIntegrity*Node callbacks.
4425	*/
4426	typedef struct PGMCHECKINTARGS
4427	{
4428	bool fLeftToRight; /*< true: left-to-right; false: right-to-left. /
4429	PPGMPHYSHANDLER pPrevPhys;
4430	PPGMVIRTHANDLER pPrevVirt;
4431	PPGMPHYS2VIRTHANDLER pPrevPhys2Virt;
4432	PVM pVM;
4433	} PGMCHECKINTARGS, *PPGMCHECKINTARGS;
4434
4435	/**
4436	* Validate a node in the physical handler tree.
4437	*
4438	* @returns 0 on if ok, other wise 1.
4439	* @param pNode The handler node.
4440	* @param pvUser pVM.
4441	*/
4442	static DECLCALLBACK(int) pgmR3CheckIntegrityPhysHandlerNode(PAVLROGCPHYSNODECORE pNode, void *pvUser)
4443	{
4444	PPGMCHECKINTARGS pArgs = (PPGMCHECKINTARGS)pvUser;
4445	PPGMPHYSHANDLER pCur = (PPGMPHYSHANDLER)pNode;
4446	AssertReleaseReturn(!((uintptr_t)pCur & 7), 1);
4447	AssertReleaseMsg(pCur->Core.Key <= pCur->Core.KeyLast,("pCur=%p %RGp-%RGp %s\n", pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
4448	AssertReleaseMsg( !pArgs->pPrevPhys
4449	\|\| (pArgs->fLeftToRight ? pArgs->pPrevPhys->Core.KeyLast < pCur->Core.Key : pArgs->pPrevPhys->Core.KeyLast > pCur->Core.Key),
4450	("pPrevPhys=%p %RGp-%RGp %s\n"
4451	" pCur=%p %RGp-%RGp %s\n",
4452	pArgs->pPrevPhys, pArgs->pPrevPhys->Core.Key, pArgs->pPrevPhys->Core.KeyLast, pArgs->pPrevPhys->pszDesc,
4453	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
4454	pArgs->pPrevPhys = pCur;
4455	return 0;
4456	}
4457
4458
4459	/**
4460	* Validate a node in the virtual handler tree.
4461	*
4462	* @returns 0 on if ok, other wise 1.
4463	* @param pNode The handler node.
4464	* @param pvUser pVM.
4465	*/
4466	static DECLCALLBACK(int) pgmR3CheckIntegrityVirtHandlerNode(PAVLROGCPTRNODECORE pNode, void *pvUser)
4467	{
4468	PPGMCHECKINTARGS pArgs = (PPGMCHECKINTARGS)pvUser;
4469	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)pNode;
4470	AssertReleaseReturn(!((uintptr_t)pCur & 7), 1);
4471	AssertReleaseMsg(pCur->Core.Key <= pCur->Core.KeyLast,("pCur=%p %RGv-%RGv %s\n", pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
4472	AssertReleaseMsg( !pArgs->pPrevVirt
4473	\|\| (pArgs->fLeftToRight ? pArgs->pPrevVirt->Core.KeyLast < pCur->Core.Key : pArgs->pPrevVirt->Core.KeyLast > pCur->Core.Key),
4474	("pPrevVirt=%p %RGv-%RGv %s\n"
4475	" pCur=%p %RGv-%RGv %s\n",
4476	pArgs->pPrevVirt, pArgs->pPrevVirt->Core.Key, pArgs->pPrevVirt->Core.KeyLast, pArgs->pPrevVirt->pszDesc,
4477	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
4478	for (unsigned iPage = 0; iPage < pCur->cPages; iPage++)
4479	{
4480	AssertReleaseMsg(pCur->aPhysToVirt[iPage].offVirtHandler == -RT_OFFSETOF(PGMVIRTHANDLER, aPhysToVirt[iPage]),
4481	("pCur=%p %RGv-%RGv %s\n"
4482	"iPage=%d offVirtHandle=%#x expected %#x\n",
4483	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc,
4484	iPage, pCur->aPhysToVirt[iPage].offVirtHandler, -RT_OFFSETOF(PGMVIRTHANDLER, aPhysToVirt[iPage])));
4485	}
4486	pArgs->pPrevVirt = pCur;
4487	return 0;
4488	}
4489
4490
4491	/**
4492	* Validate a node in the virtual handler tree.
4493	*
4494	* @returns 0 on if ok, other wise 1.
4495	* @param pNode The handler node.
4496	* @param pvUser pVM.
4497	*/
4498	static DECLCALLBACK(int) pgmR3CheckIntegrityPhysToVirtHandlerNode(PAVLROGCPHYSNODECORE pNode, void *pvUser)
4499	{
4500	PPGMCHECKINTARGS pArgs = (PPGMCHECKINTARGS)pvUser;
4501	PPGMPHYS2VIRTHANDLER pCur = (PPGMPHYS2VIRTHANDLER)pNode;
4502	AssertReleaseMsgReturn(!((uintptr_t)pCur & 3), ("\n"), 1);
4503	AssertReleaseMsgReturn(!(pCur->offVirtHandler & 3), ("\n"), 1);
4504	AssertReleaseMsg(pCur->Core.Key <= pCur->Core.KeyLast,("pCur=%p %RGp-%RGp\n", pCur, pCur->Core.Key, pCur->Core.KeyLast));
4505	AssertReleaseMsg( !pArgs->pPrevPhys2Virt
4506	\|\| (pArgs->fLeftToRight ? pArgs->pPrevPhys2Virt->Core.KeyLast < pCur->Core.Key : pArgs->pPrevPhys2Virt->Core.KeyLast > pCur->Core.Key),
4507	("pPrevPhys2Virt=%p %RGp-%RGp\n"
4508	" pCur=%p %RGp-%RGp\n",
4509	pArgs->pPrevPhys2Virt, pArgs->pPrevPhys2Virt->Core.Key, pArgs->pPrevPhys2Virt->Core.KeyLast,
4510	pCur, pCur->Core.Key, pCur->Core.KeyLast));
4511	AssertReleaseMsg( !pArgs->pPrevPhys2Virt
4512	\|\| (pArgs->fLeftToRight ? pArgs->pPrevPhys2Virt->Core.KeyLast < pCur->Core.Key : pArgs->pPrevPhys2Virt->Core.KeyLast > pCur->Core.Key),
4513	("pPrevPhys2Virt=%p %RGp-%RGp\n"
4514	" pCur=%p %RGp-%RGp\n",
4515	pArgs->pPrevPhys2Virt, pArgs->pPrevPhys2Virt->Core.Key, pArgs->pPrevPhys2Virt->Core.KeyLast,
4516	pCur, pCur->Core.Key, pCur->Core.KeyLast));
4517	AssertReleaseMsg((pCur->offNextAlias & (PGMPHYS2VIRTHANDLER_IN_TREE \| PGMPHYS2VIRTHANDLER_IS_HEAD)) == (PGMPHYS2VIRTHANDLER_IN_TREE \| PGMPHYS2VIRTHANDLER_IS_HEAD),
4518	("pCur=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4519	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias));
4520	if (pCur->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK)
4521	{
4522	PPGMPHYS2VIRTHANDLER pCur2 = pCur;
4523	for (;;)
4524	{
4525	pCur2 = (PPGMPHYS2VIRTHANDLER)((intptr_t)pCur + (pCur->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK));
4526	AssertReleaseMsg(pCur2 != pCur,
4527	(" pCur=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4528	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias));
4529	AssertReleaseMsg((pCur2->offNextAlias & (PGMPHYS2VIRTHANDLER_IN_TREE \| PGMPHYS2VIRTHANDLER_IS_HEAD)) == PGMPHYS2VIRTHANDLER_IN_TREE,
4530	(" pCur=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
4531	"pCur2=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4532	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias,
4533	pCur2, pCur2->Core.Key, pCur2->Core.KeyLast, pCur2->offVirtHandler, pCur2->offNextAlias));
4534	AssertReleaseMsg((pCur2->Core.Key ^ pCur->Core.Key) < PAGE_SIZE,
4535	(" pCur=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
4536	"pCur2=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4537	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias,
4538	pCur2, pCur2->Core.Key, pCur2->Core.KeyLast, pCur2->offVirtHandler, pCur2->offNextAlias));
4539	AssertReleaseMsg((pCur2->Core.KeyLast ^ pCur->Core.KeyLast) < PAGE_SIZE,
4540	(" pCur=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
4541	"pCur2=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4542	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias,
4543	pCur2, pCur2->Core.Key, pCur2->Core.KeyLast, pCur2->offVirtHandler, pCur2->offNextAlias));
4544	if (!(pCur2->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK))
4545	break;
4546	}
4547	}
4548
4549	pArgs->pPrevPhys2Virt = pCur;
4550	return 0;
4551	}
4552
4553
4554	/**
4555	* Perform an integrity check on the PGM component.
4556	*
4557	* @returns VINF_SUCCESS if everything is fine.
4558	* @returns VBox error status after asserting on integrity breach.
4559	* @param pVM The VM handle.
4560	*/
4561	VMMR3DECL(int) PGMR3CheckIntegrity(PVM pVM)
4562	{
4563	AssertReleaseReturn(pVM->pgm.s.offVM, VERR_INTERNAL_ERROR);
4564
4565	/*
4566	* Check the trees.
4567	*/
4568	int cErrors = 0;
4569	const static PGMCHECKINTARGS s_LeftToRight = { true, NULL, NULL, NULL, pVM };
4570	const static PGMCHECKINTARGS s_RightToLeft = { false, NULL, NULL, NULL, pVM };
4571	PGMCHECKINTARGS Args = s_LeftToRight;
4572	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysHandlers, true, pgmR3CheckIntegrityPhysHandlerNode, &Args);
4573	Args = s_RightToLeft;
4574	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysHandlers, false, pgmR3CheckIntegrityPhysHandlerNode, &Args);
4575	Args = s_LeftToRight;
4576	cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesR3->VirtHandlers, true, pgmR3CheckIntegrityVirtHandlerNode, &Args);
4577	Args = s_RightToLeft;
4578	cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesR3->VirtHandlers, false, pgmR3CheckIntegrityVirtHandlerNode, &Args);
4579	Args = s_LeftToRight;
4580	cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesR3->HyperVirtHandlers, true, pgmR3CheckIntegrityVirtHandlerNode, &Args);
4581	Args = s_RightToLeft;
4582	cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesR3->HyperVirtHandlers, false, pgmR3CheckIntegrityVirtHandlerNode, &Args);
4583	Args = s_LeftToRight;
4584	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysToVirtHandlers, true, pgmR3CheckIntegrityPhysToVirtHandlerNode, &Args);
4585	Args = s_RightToLeft;
4586	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysToVirtHandlers, false, pgmR3CheckIntegrityPhysToVirtHandlerNode, &Args);
4587
4588	return !cErrors ? VINF_SUCCESS : VERR_INTERNAL_ERROR;
4589	}
4590
4591

Note: See TracBrowser for help on using the repository browser.

source: vbox/trunk/src/VBox/VMM/PGM.cpp@ 17049

Download in other formats: