PGM.cpp@ 18291

Last change on this file since 18291 was 18291, checked in by vboxsync, 16 years ago
PGM: Map PGMRAMRANGES above 4GB outside HMA (see defect). Changed PGMR3MapPT to take a flag indicating whether PGMR3UnmapPT will be used; this way we can select a more optimal allocation function for the ram ranges. PGMMapResolveConflicts: Walk the list correctly after reloc. pgmMapClearShadowPDEs: Don't clear PGM_PLXFLAGS_MAPPING when we shouldn't (odd PAE cases).
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1	/* $Id: PGM.cpp 18291 2009-03-26 05:11:07Z vboxsync $ */
2	/** @file
3	* PGM - Page Manager and Monitor. (Mixing stuff here, not good?)
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22
23	/** @page pg_pgm PGM - The Page Manager and Monitor
24	*
25	* @see grp_pgm,
26	* @ref pg_pgm_pool,
27	* @ref pg_pgm_phys.
28	*
29	*
30	* @section sec_pgm_modes Paging Modes
31	*
32	* There are three memory contexts: Host Context (HC), Guest Context (GC)
33	* and intermediate context. When talking about paging HC can also be refered to
34	* as "host paging", and GC refered to as "shadow paging".
35	*
36	* We define three basic paging modes: 32-bit, PAE and AMD64. The host paging mode
37	* is defined by the host operating system. The mode used in the shadow paging mode
38	* depends on the host paging mode and what the mode the guest is currently in. The
39	* following relation between the two is defined:
40	*
41	* @verbatim
42	Host > 32-bit \| PAE \| AMD64 \|
43	Guest \| \| \| \|
44	==v================================
45	32-bit 32-bit PAE PAE
46	-------\|--------\|--------\|--------\|
47	PAE PAE PAE PAE
48	-------\|--------\|--------\|--------\|
49	AMD64 AMD64 AMD64 AMD64
50	-------\|--------\|--------\|--------\| @endverbatim
51	*
52	* All configuration except those in the diagonal (upper left) are expected to
53	* require special effort from the switcher (i.e. a bit slower).
54	*
55	*
56	*
57	*
58	* @section sec_pgm_shw The Shadow Memory Context
59	*
60	*
61	* [..]
62	*
63	* Because of guest context mappings requires PDPT and PML4 entries to allow
64	* writing on AMD64, the two upper levels will have fixed flags whatever the
65	* guest is thinking of using there. So, when shadowing the PD level we will
66	* calculate the effective flags of PD and all the higher levels. In legacy
67	* PAE mode this only applies to the PWT and PCD bits (the rest are
68	* ignored/reserved/MBZ). We will ignore those bits for the present.
69	*
70	*
71	*
72	* @section sec_pgm_int The Intermediate Memory Context
73	*
74	* The world switch goes thru an intermediate memory context which purpose it is
75	* to provide different mappings of the switcher code. All guest mappings are also
76	* present in this context.
77	*
78	* The switcher code is mapped at the same location as on the host, at an
79	* identity mapped location (physical equals virtual address), and at the
80	* hypervisor location. The identity mapped location is for when the world
81	* switches that involves disabling paging.
82	*
83	* PGM maintain page tables for 32-bit, PAE and AMD64 paging modes. This
84	* simplifies switching guest CPU mode and consistency at the cost of more
85	* code to do the work. All memory use for those page tables is located below
86	* 4GB (this includes page tables for guest context mappings).
87	*
88	*
89	* @subsection subsec_pgm_int_gc Guest Context Mappings
90	*
91	* During assignment and relocation of a guest context mapping the intermediate
92	* memory context is used to verify the new location.
93	*
94	* Guest context mappings are currently restricted to below 4GB, for reasons
95	* of simplicity. This may change when we implement AMD64 support.
96	*
97	*
98	*
99	*
100	* @section sec_pgm_misc Misc
101	*
102	* @subsection subsec_pgm_misc_diff Differences Between Legacy PAE and Long Mode PAE
103	*
104	* The differences between legacy PAE and long mode PAE are:
105	* -# PDPE bits 1, 2, 5 and 6 are defined differently. In leagcy mode they are
106	* all marked down as must-be-zero, while in long mode 1, 2 and 5 have the
107	* usual meanings while 6 is ignored (AMD). This means that upon switching to
108	* legacy PAE mode we'll have to clear these bits and when going to long mode
109	* they must be set. This applies to both intermediate and shadow contexts,
110	* however we don't need to do it for the intermediate one since we're
111	* executing with CR0.WP at that time.
112	* -# CR3 allows a 32-byte aligned address in legacy mode, while in long mode
113	* a page aligned one is required.
114	*
115	*
116	* @section sec_pgm_handlers Access Handlers
117	*
118	* Placeholder.
119	*
120	*
121	* @subsection sec_pgm_handlers_virt Virtual Access Handlers
122	*
123	* Placeholder.
124	*
125	*
126	* @subsection sec_pgm_handlers_virt Virtual Access Handlers
127	*
128	* We currently implement three types of virtual access handlers: ALL, WRITE
129	* and HYPERVISOR (WRITE). See PGMVIRTHANDLERTYPE for some more details.
130	*
131	* The HYPERVISOR access handlers is kept in a separate tree since it doesn't apply
132	* to physical pages (PGMTREES::HyperVirtHandlers) and only needs to be consulted in
133	* a special \#PF case. The ALL and WRITE are in the PGMTREES::VirtHandlers tree, the
134	* rest of this section is going to be about these handlers.
135	*
136	* We'll go thru the life cycle of a handler and try make sense of it all, don't know
137	* how successfull this is gonna be...
138	*
139	* 1. A handler is registered thru the PGMR3HandlerVirtualRegister and
140	* PGMHandlerVirtualRegisterEx APIs. We check for conflicting virtual handlers
141	* and create a new node that is inserted into the AVL tree (range key). Then
142	* a full PGM resync is flagged (clear pool, sync cr3, update virtual bit of PGMPAGE).
143	*
144	* 2. The following PGMSyncCR3/SyncCR3 operation will first make invoke HandlerVirtualUpdate.
145	*
146	* 2a. HandlerVirtualUpdate will will lookup all the pages covered by virtual handlers
147	* via the current guest CR3 and update the physical page -> virtual handler
148	* translation. Needless to say, this doesn't exactly scale very well. If any changes
149	* are detected, it will flag a virtual bit update just like we did on registration.
150	* PGMPHYS pages with changes will have their virtual handler state reset to NONE.
151	*
152	* 2b. The virtual bit update process will iterate all the pages covered by all the
153	* virtual handlers and update the PGMPAGE virtual handler state to the max of all
154	* virtual handlers on that page.
155	*
156	* 2c. Back in SyncCR3 we will now flush the entire shadow page cache to make sure
157	* we don't miss any alias mappings of the monitored pages.
158	*
159	* 2d. SyncCR3 will then proceed with syncing the CR3 table.
160	*
161	* 3. \#PF(np,read) on a page in the range. This will cause it to be synced
162	* read-only and resumed if it's a WRITE handler. If it's an ALL handler we
163	* will call the handlers like in the next step. If the physical mapping has
164	* changed we will - some time in the future - perform a handler callback
165	* (optional) and update the physical -> virtual handler cache.
166	*
167	* 4. \#PF(,write) on a page in the range. This will cause the handler to
168	* be invoked.
169	*
170	* 5. The guest invalidates the page and changes the physical backing or
171	* unmaps it. This should cause the invalidation callback to be invoked
172	* (it might not yet be 100% perfect). Exactly what happens next... is
173	* this where we mess up and end up out of sync for a while?
174	*
175	* 6. The handler is deregistered by the client via PGMHandlerVirtualDeregister.
176	* We will then set all PGMPAGEs in the physical -> virtual handler cache for
177	* this handler to NONE and trigger a full PGM resync (basically the same
178	* as int step 1). Which means 2 is executed again.
179	*
180	*
181	* @subsubsection sub_sec_pgm_handler_virt_todo TODOs
182	*
183	* There is a bunch of things that needs to be done to make the virtual handlers
184	* work 100% correctly and work more efficiently.
185	*
186	* The first bit hasn't been implemented yet because it's going to slow the
187	* whole mess down even more, and besides it seems to be working reliably for
188	* our current uses. OTOH, some of the optimizations might end up more or less
189	* implementing the missing bits, so we'll see.
190	*
191	* On the optimization side, the first thing to do is to try avoid unnecessary
192	* cache flushing. Then try team up with the shadowing code to track changes
193	* in mappings by means of access to them (shadow in), updates to shadows pages,
194	* invlpg, and shadow PT discarding (perhaps).
195	*
196	* Some idea that have popped up for optimization for current and new features:
197	* - bitmap indicating where there are virtual handlers installed.
198	* (4KB => 220 pages, page 212 => covers 32-bit address space 1:1!)
199	* - Further optimize this by min/max (needs min/max avl getters).
200	* - Shadow page table entry bit (if any left)?
201	*
202	*/
203
204
205	/** @page pg_pgm_phys PGM Physical Guest Memory Management
206	*
207	*
208	* Objectives:
209	* - Guest RAM over-commitment using memory ballooning,
210	* zero pages and general page sharing.
211	* - Moving or mirroring a VM onto a different physical machine.
212	*
213	*
214	* @subsection subsec_pgmPhys_Definitions Definitions
215	*
216	* Allocation chunk - A RTR0MemObjAllocPhysNC object and the tracking
217	* machinery assoicated with it.
218	*
219	*
220	*
221	*
222	* @subsection subsec_pgmPhys_AllocPage Allocating a page.
223	*
224	* Initially we map all guest memory to the (per VM) zero page, which
225	* means that none of the read functions will cause pages to be allocated.
226	*
227	* Exception, access bit in page tables that have been shared. This must
228	* be handled, but we must also make sure PGMGst*Modify doesn't make
229	* unnecessary modifications.
230	*
231	* Allocation points:
232	* - PGMPhysSimpleWriteGCPhys and PGMPhysWrite.
233	* - Replacing a zero page mapping at \#PF.
234	* - Replacing a shared page mapping at \#PF.
235	* - ROM registration (currently MMR3RomRegister).
236	* - VM restore (pgmR3Load).
237	*
238	* For the first three it would make sense to keep a few pages handy
239	* until we've reached the max memory commitment for the VM.
240	*
241	* For the ROM registration, we know exactly how many pages we need
242	* and will request these from ring-0. For restore, we will save
243	* the number of non-zero pages in the saved state and allocate
244	* them up front. This would allow the ring-0 component to refuse
245	* the request if the isn't sufficient memory available for VM use.
246	*
247	* Btw. for both ROM and restore allocations we won't be requiring
248	* zeroed pages as they are going to be filled instantly.
249	*
250	*
251	* @subsection subsec_pgmPhys_FreePage Freeing a page
252	*
253	* There are a few points where a page can be freed:
254	* - After being replaced by the zero page.
255	* - After being replaced by a shared page.
256	* - After being ballooned by the guest additions.
257	* - At reset.
258	* - At restore.
259	*
260	* When freeing one or more pages they will be returned to the ring-0
261	* component and replaced by the zero page.
262	*
263	* The reasoning for clearing out all the pages on reset is that it will
264	* return us to the exact same state as on power on, and may thereby help
265	* us reduce the memory load on the system. Further it might have a
266	* (temporary) positive influence on memory fragmentation (@see subsec_pgmPhys_Fragmentation).
267	*
268	* On restore, as mention under the allocation topic, pages should be
269	* freed / allocated depending on how many is actually required by the
270	* new VM state. The simplest approach is to do like on reset, and free
271	* all non-ROM pages and then allocate what we need.
272	*
273	* A measure to prevent some fragmentation, would be to let each allocation
274	* chunk have some affinity towards the VM having allocated the most pages
275	* from it. Also, try make sure to allocate from allocation chunks that
276	* are almost full. Admittedly, both these measures might work counter to
277	* our intentions and its probably not worth putting a lot of effort,
278	* cpu time or memory into this.
279	*
280	*
281	* @subsection subsec_pgmPhys_SharePage Sharing a page
282	*
283	* The basic idea is that there there will be a idle priority kernel
284	* thread walking the non-shared VM pages hashing them and looking for
285	* pages with the same checksum. If such pages are found, it will compare
286	* them byte-by-byte to see if they actually are identical. If found to be
287	* identical it will allocate a shared page, copy the content, check that
288	* the page didn't change while doing this, and finally request both the
289	* VMs to use the shared page instead. If the page is all zeros (special
290	* checksum and byte-by-byte check) it will request the VM that owns it
291	* to replace it with the zero page.
292	*
293	* To make this efficient, we will have to make sure not to try share a page
294	* that will change its contents soon. This part requires the most work.
295	* A simple idea would be to request the VM to write monitor the page for
296	* a while to make sure it isn't modified any time soon. Also, it may
297	* make sense to skip pages that are being write monitored since this
298	* information is readily available to the thread if it works on the
299	* per-VM guest memory structures (presently called PGMRAMRANGE).
300	*
301	*
302	* @subsection subsec_pgmPhys_Fragmentation Fragmentation Concerns and Counter Measures
303	*
304	* The pages are organized in allocation chunks in ring-0, this is a necessity
305	* if we wish to have an OS agnostic approach to this whole thing. (On Linux we
306	* could easily work on a page-by-page basis if we liked. Whether this is possible
307	* or efficient on NT I don't quite know.) Fragmentation within these chunks may
308	* become a problem as part of the idea here is that we wish to return memory to
309	* the host system.
310	*
311	* For instance, starting two VMs at the same time, they will both allocate the
312	* guest memory on-demand and if permitted their page allocations will be
313	* intermixed. Shut down one of the two VMs and it will be difficult to return
314	* any memory to the host system because the page allocation for the two VMs are
315	* mixed up in the same allocation chunks.
316	*
317	* To further complicate matters, when pages are freed because they have been
318	* ballooned or become shared/zero the whole idea is that the page is supposed
319	* to be reused by another VM or returned to the host system. This will cause
320	* allocation chunks to contain pages belonging to different VMs and prevent
321	* returning memory to the host when one of those VM shuts down.
322	*
323	* The only way to really deal with this problem is to move pages. This can
324	* either be done at VM shutdown and or by the idle priority worker thread
325	* that will be responsible for finding sharable/zero pages. The mechanisms
326	* involved for coercing a VM to move a page (or to do it for it) will be
327	* the same as when telling it to share/zero a page.
328	*
329	*
330	* @subsection subsec_pgmPhys_Tracking Tracking Structures And Their Cost
331	*
332	* There's a difficult balance between keeping the per-page tracking structures
333	* (global and guest page) easy to use and keeping them from eating too much
334	* memory. We have limited virtual memory resources available when operating in
335	* 32-bit kernel space (on 64-bit there'll it's quite a different story). The
336	* tracking structures will be attemted designed such that we can deal with up
337	* to 32GB of memory on a 32-bit system and essentially unlimited on 64-bit ones.
338	*
339	*
340	* @subsubsection subsubsec_pgmPhys_Tracking_Kernel Kernel Space
341	*
342	* @see pg_GMM
343	*
344	* @subsubsection subsubsec_pgmPhys_Tracking_PerVM Per-VM
345	*
346	* Fixed info is the physical address of the page (HCPhys) and the page id
347	* (described above). Theoretically we'll need 48(-12) bits for the HCPhys part.
348	* Today we've restricting ourselves to 40(-12) bits because this is the current
349	* restrictions of all AMD64 implementations (I think Barcelona will up this
350	* to 48(-12) bits, not that it really matters) and I needed the bits for
351	* tracking mappings of a page. 48-12 = 36. That leaves 28 bits, which means a
352	* decent range for the page id: 2^(28+12) = 1024TB.
353	*
354	* In additions to these, we'll have to keep maintaining the page flags as we
355	* currently do. Although it wouldn't harm to optimize these quite a bit, like
356	* for instance the ROM shouldn't depend on having a write handler installed
357	* in order for it to become read-only. A RO/RW bit should be considered so
358	* that the page syncing code doesn't have to mess about checking multiple
359	* flag combinations (ROM \|\| RW handler \|\| write monitored) in order to
360	* figure out how to setup a shadow PTE. But this of course, is second
361	* priority at present. Current this requires 12 bits, but could probably
362	* be optimized to ~8.
363	*
364	* Then there's the 24 bits used to track which shadow page tables are
365	* currently mapping a page for the purpose of speeding up physical
366	* access handlers, and thereby the page pool cache. More bit for this
367	* purpose wouldn't hurt IIRC.
368	*
369	* Then there is a new bit in which we need to record what kind of page
370	* this is, shared, zero, normal or write-monitored-normal. This'll
371	* require 2 bits. One bit might be needed for indicating whether a
372	* write monitored page has been written to. And yet another one or
373	* two for tracking migration status. 3-4 bits total then.
374	*
375	* Whatever is left will can be used to record the sharabilitiy of a
376	* page. The page checksum will not be stored in the per-VM table as
377	* the idle thread will not be permitted to do modifications to it.
378	* It will instead have to keep its own working set of potentially
379	* shareable pages and their check sums and stuff.
380	*
381	* For the present we'll keep the current packing of the
382	* PGMRAMRANGE::aHCPhys to keep the changes simple, only of course,
383	* we'll have to change it to a struct with a total of 128-bits at
384	* our disposal.
385	*
386	* The initial layout will be like this:
387	* @verbatim
388	RTHCPHYS HCPhys; The current stuff.
389	63:40 Current shadow PT tracking stuff.
390	39:12 The physical page frame number.
391	11:0 The current flags.
392	uint32_t u28PageId : 28; The page id.
393	uint32_t u2State : 2; The page state { zero, shared, normal, write monitored }.
394	uint32_t fWrittenTo : 1; Whether a write monitored page was written to.
395	uint32_t u1Reserved : 1; Reserved for later.
396	uint32_t u32Reserved; Reserved for later, mostly sharing stats.
397	@endverbatim
398	*
399	* The final layout will be something like this:
400	* @verbatim
401	RTHCPHYS HCPhys; The current stuff.
402	63:48 High page id (12+).
403	47:12 The physical page frame number.
404	11:0 Low page id.
405	uint32_t fReadOnly : 1; Whether it's readonly page (rom or monitored in some way).
406	uint32_t u3Type : 3; The page type {RESERVED, MMIO, MMIO2, ROM, shadowed ROM, RAM}.
407	uint32_t u2PhysMon : 2; Physical access handler type {none, read, write, all}.
408	uint32_t u2VirtMon : 2; Virtual access handler type {none, read, write, all}..
409	uint32_t u2State : 2; The page state { zero, shared, normal, write monitored }.
410	uint32_t fWrittenTo : 1; Whether a write monitored page was written to.
411	uint32_t u20Reserved : 20; Reserved for later, mostly sharing stats.
412	uint32_t u32Tracking; The shadow PT tracking stuff, roughly.
413	@endverbatim
414	*
415	* Cost wise, this means we'll double the cost for guest memory. There isn't anyway
416	* around that I'm afraid. It means that the cost of dealing out 32GB of memory
417	* to one or more VMs is: (32GB >> PAGE_SHIFT) * 16 bytes, or 128MBs. Or another
418	* example, the VM heap cost when assigning 1GB to a VM will be: 4MB.
419	*
420	* A couple of cost examples for the total cost per-VM + kernel.
421	* 32-bit Windows and 32-bit linux:
422	* 1GB guest ram, 256K pages: 4MB + 2MB(+) = 6MB
423	* 4GB guest ram, 1M pages: 16MB + 8MB(+) = 24MB
424	* 32GB guest ram, 8M pages: 128MB + 64MB(+) = 192MB
425	* 64-bit Windows and 64-bit linux:
426	* 1GB guest ram, 256K pages: 4MB + 3MB(+) = 7MB
427	* 4GB guest ram, 1M pages: 16MB + 12MB(+) = 28MB
428	* 32GB guest ram, 8M pages: 128MB + 96MB(+) = 224MB
429	*
430	* UPDATE - 2007-09-27:
431	* Will need a ballooned flag/state too because we cannot
432	* trust the guest 100% and reporting the same page as ballooned more
433	* than once will put the GMM off balance.
434	*
435	*
436	* @subsection subsec_pgmPhys_Serializing Serializing Access
437	*
438	* Initially, we'll try a simple scheme:
439	*
440	* - The per-VM RAM tracking structures (PGMRAMRANGE) is only modified
441	* by the EMT thread of that VM while in the pgm critsect.
442	* - Other threads in the VM process that needs to make reliable use of
443	* the per-VM RAM tracking structures will enter the critsect.
444	* - No process external thread or kernel thread will ever try enter
445	* the pgm critical section, as that just won't work.
446	* - The idle thread (and similar threads) doesn't not need 100% reliable
447	* data when performing it tasks as the EMT thread will be the one to
448	* do the actual changes later anyway. So, as long as it only accesses
449	* the main ram range, it can do so by somehow preventing the VM from
450	* being destroyed while it works on it...
451	*
452	* - The over-commitment management, including the allocating/freeing
453	* chunks, is serialized by a ring-0 mutex lock (a fast one since the
454	* more mundane mutex implementation is broken on Linux).
455	* - A separeate mutex is protecting the set of allocation chunks so
456	* that pages can be shared or/and freed up while some other VM is
457	* allocating more chunks. This mutex can be take from under the other
458	* one, but not the otherway around.
459	*
460	*
461	* @subsection subsec_pgmPhys_Request VM Request interface
462	*
463	* When in ring-0 it will become necessary to send requests to a VM so it can
464	* for instance move a page while defragmenting during VM destroy. The idle
465	* thread will make use of this interface to request VMs to setup shared
466	* pages and to perform write monitoring of pages.
467	*
468	* I would propose an interface similar to the current VMReq interface, similar
469	* in that it doesn't require locking and that the one sending the request may
470	* wait for completion if it wishes to. This shouldn't be very difficult to
471	* realize.
472	*
473	* The requests themselves are also pretty simple. They are basically:
474	* -# Check that some precondition is still true.
475	* -# Do the update.
476	* -# Update all shadow page tables involved with the page.
477	*
478	* The 3rd step is identical to what we're already doing when updating a
479	* physical handler, see pgmHandlerPhysicalSetRamFlagsAndFlushShadowPTs.
480	*
481	*
482	*
483	* @section sec_pgmPhys_MappingCaches Mapping Caches
484	*
485	* In order to be able to map in and out memory and to be able to support
486	* guest with more RAM than we've got virtual address space, we'll employing
487	* a mapping cache. There is already a tiny one for GC (see PGMGCDynMapGCPageEx)
488	* and we'll create a similar one for ring-0 unless we decide to setup a dedicate
489	* memory context for the HWACCM execution.
490	*
491	*
492	* @subsection subsec_pgmPhys_MappingCaches_R3 Ring-3
493	*
494	* We've considered implementing the ring-3 mapping cache page based but found
495	* that this was bother some when one had to take into account TLBs+SMP and
496	* portability (missing the necessary APIs on several platforms). There were
497	* also some performance concerns with this approach which hadn't quite been
498	* worked out.
499	*
500	* Instead, we'll be mapping allocation chunks into the VM process. This simplifies
501	* matters greatly quite a bit since we don't need to invent any new ring-0 stuff,
502	* only some minor RTR0MEMOBJ mapping stuff. The main concern here is that mapping
503	* compared to the previous idea is that mapping or unmapping a 1MB chunk is more
504	* costly than a single page, although how much more costly is uncertain. We'll
505	* try address this by using a very big cache, preferably bigger than the actual
506	* VM RAM size if possible. The current VM RAM sizes should give some idea for
507	* 32-bit boxes, while on 64-bit we can probably get away with employing an
508	* unlimited cache.
509	*
510	* The cache have to parts, as already indicated, the ring-3 side and the
511	* ring-0 side.
512	*
513	* The ring-0 will be tied to the page allocator since it will operate on the
514	* memory objects it contains. It will therefore require the first ring-0 mutex
515	* discussed in @ref subsec_pgmPhys_Serializing. We
516	* some double house keeping wrt to who has mapped what I think, since both
517	* VMMR0.r0 and RTR0MemObj will keep track of mapping relataions
518	*
519	* The ring-3 part will be protected by the pgm critsect. For simplicity, we'll
520	* require anyone that desires to do changes to the mapping cache to do that
521	* from within this critsect. Alternatively, we could employ a separate critsect
522	* for serializing changes to the mapping cache as this would reduce potential
523	* contention with other threads accessing mappings unrelated to the changes
524	* that are in process. We can see about this later, contention will show
525	* up in the statistics anyway, so it'll be simple to tell.
526	*
527	* The organization of the ring-3 part will be very much like how the allocation
528	* chunks are organized in ring-0, that is in an AVL tree by chunk id. To avoid
529	* having to walk the tree all the time, we'll have a couple of lookaside entries
530	* like in we do for I/O ports and MMIO in IOM.
531	*
532	* The simplified flow of a PGMPhysRead/Write function:
533	* -# Enter the PGM critsect.
534	* -# Lookup GCPhys in the ram ranges and get the Page ID.
535	* -# Calc the Allocation Chunk ID from the Page ID.
536	* -# Check the lookaside entries and then the AVL tree for the Chunk ID.
537	* If not found in cache:
538	* -# Call ring-0 and request it to be mapped and supply
539	* a chunk to be unmapped if the cache is maxed out already.
540	* -# Insert the new mapping into the AVL tree (id + R3 address).
541	* -# Update the relevant lookaside entry and return the mapping address.
542	* -# Do the read/write according to monitoring flags and everything.
543	* -# Leave the critsect.
544	*
545	*
546	* @section sec_pgmPhys_Fallback Fallback
547	*
548	* Current all the "second tier" hosts will not support the RTR0MemObjAllocPhysNC
549	* API and thus require a fallback.
550	*
551	* So, when RTR0MemObjAllocPhysNC returns VERR_NOT_SUPPORTED the page allocator
552	* will return to the ring-3 caller (and later ring-0) and asking it to seed
553	* the page allocator with some fresh pages (VERR_GMM_SEED_ME). Ring-3 will
554	* then perform an SUPPageAlloc(cbChunk >> PAGE_SHIFT) call and make a
555	* "SeededAllocPages" call to ring-0.
556	*
557	* The first time ring-0 sees the VERR_NOT_SUPPORTED failure it will disable
558	* all page sharing (zero page detection will continue). It will also force
559	* all allocations to come from the VM which seeded the page. Both these
560	* measures are taken to make sure that there will never be any need for
561	* mapping anything into ring-3 - everything will be mapped already.
562	*
563	* Whether we'll continue to use the current MM locked memory management
564	* for this I don't quite know (I'd prefer not to and just ditch that all
565	* togther), we'll see what's simplest to do.
566	*
567	*
568	*
569	* @section sec_pgmPhys_Changes Changes
570	*
571	* Breakdown of the changes involved?
572	*/
573
574	/*******************************************************************************
575	* Header Files *
576	*******************************************************************************/
577	#define LOG_GROUP LOG_GROUP_PGM
578	#include <VBox/dbgf.h>
579	#include <VBox/pgm.h>
580	#include <VBox/cpum.h>
581	#include <VBox/iom.h>
582	#include <VBox/sup.h>
583	#include <VBox/mm.h>
584	#include <VBox/em.h>
585	#include <VBox/stam.h>
586	#include <VBox/rem.h>
587	#include <VBox/dbgf.h>
588	#include <VBox/rem.h>
589	#include <VBox/selm.h>
590	#include <VBox/ssm.h>
591	#include "PGMInternal.h"
592	#include <VBox/vm.h>
593	#include <VBox/dbg.h>
594	#include <VBox/hwaccm.h>
595
596	#include <iprt/assert.h>
597	#include <iprt/alloc.h>
598	#include <iprt/asm.h>
599	#include <iprt/thread.h>
600	#include <iprt/string.h>
601	#ifdef DEBUG_bird
602	# include <iprt/env.h>
603	#endif
604	#include <VBox/param.h>
605	#include <VBox/err.h>
606
607
608	/*******************************************************************************
609	* Defined Constants And Macros *
610	*******************************************************************************/
611	/** Saved state data unit version. */
612	#ifdef VBOX_WITH_NEW_PHYS_CODE
613	# define PGM_SAVED_STATE_VERSION 7
614	#else
615	# define PGM_SAVED_STATE_VERSION 6
616	#endif
617	/** Saved state data unit version. */
618	#define PGM_SAVED_STATE_VERSION_OLD_PHYS_CODE 6
619
620
621	/*******************************************************************************
622	* Internal Functions *
623	*******************************************************************************/
624	static int pgmR3InitPaging(PVM pVM);
625	static DECLCALLBACK(void) pgmR3PhysInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
626	static DECLCALLBACK(void) pgmR3InfoMode(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
627	static DECLCALLBACK(void) pgmR3InfoCr3(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
628	static DECLCALLBACK(int) pgmR3RelocatePhysHandler(PAVLROGCPHYSNODECORE pNode, void *pvUser);
629	static DECLCALLBACK(int) pgmR3RelocateVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser);
630	static DECLCALLBACK(int) pgmR3RelocateHyperVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser);
631	#ifdef VBOX_STRICT
632	static DECLCALLBACK(void) pgmR3ResetNoMorePhysWritesFlag(PVM pVM, VMSTATE enmState, VMSTATE enmOldState, void *pvUser);
633	#endif
634	static DECLCALLBACK(int) pgmR3Save(PVM pVM, PSSMHANDLE pSSM);
635	static DECLCALLBACK(int) pgmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version);
636	static int pgmR3ModeDataInit(PVM pVM, bool fResolveGCAndR0);
637	static void pgmR3ModeDataSwitch(PVM pVM, PGMMODE enmShw, PGMMODE enmGst);
638	static PGMMODE pgmR3CalcShadowMode(PVM pVM, PGMMODE enmGuestMode, SUPPAGINGMODE enmHostMode, PGMMODE enmShadowMode, VMMSWITCHER *penmSwitcher);
639
640	#ifdef VBOX_WITH_STATISTICS
641	static void pgmR3InitStats(PVM pVM);
642	#endif
643
644	#ifdef VBOX_WITH_DEBUGGER
645	/** @todo all but the two last commands must be converted to 'info'. */
646	static DECLCALLBACK(int) pgmR3CmdRam(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
647	static DECLCALLBACK(int) pgmR3CmdMap(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
648	static DECLCALLBACK(int) pgmR3CmdSync(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
649	static DECLCALLBACK(int) pgmR3CmdSyncAlways(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
650	# ifdef VBOX_STRICT
651	static DECLCALLBACK(int) pgmR3CmdAssertCR3(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
652	# endif
653	#endif
654
655
656	/*******************************************************************************
657	* Global Variables *
658	*******************************************************************************/
659	#ifdef VBOX_WITH_DEBUGGER
660	/** Command descriptors. */
661	static const DBGCCMD g_aCmds[] =
662	{
663	/* pszCmd, cArgsMin, cArgsMax, paArgDesc, cArgDescs, pResultDesc, fFlags, pfnHandler pszSyntax, ....pszDescription */
664	{ "pgmram", 0, 0, NULL, 0, NULL, 0, pgmR3CmdRam, "", "Display the ram ranges." },
665	{ "pgmmap", 0, 0, NULL, 0, NULL, 0, pgmR3CmdMap, "", "Display the mapping ranges." },
666	{ "pgmsync", 0, 0, NULL, 0, NULL, 0, pgmR3CmdSync, "", "Sync the CR3 page." },
667	#ifdef VBOX_STRICT
668	{ "pgmassertcr3", 0, 0, NULL, 0, NULL, 0, pgmR3CmdAssertCR3, "", "Check the shadow CR3 mapping." },
669	#endif
670	{ "pgmsyncalways", 0, 0, NULL, 0, NULL, 0, pgmR3CmdSyncAlways, "", "Toggle permanent CR3 syncing." },
671	};
672	#endif
673
674
675
676
677	/*
678	* Shadow - 32-bit mode
679	*/
680	#define PGM_SHW_TYPE PGM_TYPE_32BIT
681	#define PGM_SHW_NAME(name) PGM_SHW_NAME_32BIT(name)
682	#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_32BIT_STR(name)
683	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_32BIT_STR(name)
684	#include "PGMShw.h"
685
686	/* Guest - real mode */
687	#define PGM_GST_TYPE PGM_TYPE_REAL
688	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
689	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_REAL_STR(name)
690	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
691	#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_REAL(name)
692	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_32BIT_REAL_STR(name)
693	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_32BIT_REAL_STR(name)
694	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_PHYS
695	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_32BIT_PD_PHYS
696	#include "PGMBth.h"
697	#include "PGMGstDefs.h"
698	#include "PGMGst.h"
699	#undef BTH_PGMPOOLKIND_PT_FOR_PT
700	#undef BTH_PGMPOOLKIND_ROOT
701	#undef PGM_BTH_NAME
702	#undef PGM_BTH_NAME_RC_STR
703	#undef PGM_BTH_NAME_R0_STR
704	#undef PGM_GST_TYPE
705	#undef PGM_GST_NAME
706	#undef PGM_GST_NAME_RC_STR
707	#undef PGM_GST_NAME_R0_STR
708
709	/* Guest - protected mode */
710	#define PGM_GST_TYPE PGM_TYPE_PROT
711	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
712	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PROT_STR(name)
713	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
714	#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_PROT(name)
715	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_32BIT_PROT_STR(name)
716	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_32BIT_PROT_STR(name)
717	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_PHYS
718	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_32BIT_PD_PHYS
719	#include "PGMBth.h"
720	#include "PGMGstDefs.h"
721	#include "PGMGst.h"
722	#undef BTH_PGMPOOLKIND_PT_FOR_PT
723	#undef BTH_PGMPOOLKIND_ROOT
724	#undef PGM_BTH_NAME
725	#undef PGM_BTH_NAME_RC_STR
726	#undef PGM_BTH_NAME_R0_STR
727	#undef PGM_GST_TYPE
728	#undef PGM_GST_NAME
729	#undef PGM_GST_NAME_RC_STR
730	#undef PGM_GST_NAME_R0_STR
731
732	/* Guest - 32-bit mode */
733	#define PGM_GST_TYPE PGM_TYPE_32BIT
734	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
735	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_32BIT_STR(name)
736	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
737	#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_32BIT(name)
738	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_32BIT_32BIT_STR(name)
739	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_32BIT_32BIT_STR(name)
740	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT
741	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB
742	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_32BIT_PD
743	#include "PGMBth.h"
744	#include "PGMGstDefs.h"
745	#include "PGMGst.h"
746	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
747	#undef BTH_PGMPOOLKIND_PT_FOR_PT
748	#undef BTH_PGMPOOLKIND_ROOT
749	#undef PGM_BTH_NAME
750	#undef PGM_BTH_NAME_RC_STR
751	#undef PGM_BTH_NAME_R0_STR
752	#undef PGM_GST_TYPE
753	#undef PGM_GST_NAME
754	#undef PGM_GST_NAME_RC_STR
755	#undef PGM_GST_NAME_R0_STR
756
757	#undef PGM_SHW_TYPE
758	#undef PGM_SHW_NAME
759	#undef PGM_SHW_NAME_RC_STR
760	#undef PGM_SHW_NAME_R0_STR
761
762
763	/*
764	* Shadow - PAE mode
765	*/
766	#define PGM_SHW_TYPE PGM_TYPE_PAE
767	#define PGM_SHW_NAME(name) PGM_SHW_NAME_PAE(name)
768	#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_PAE_STR(name)
769	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_PAE_STR(name)
770	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_REAL(name)
771	#include "PGMShw.h"
772
773	/* Guest - real mode */
774	#define PGM_GST_TYPE PGM_TYPE_REAL
775	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
776	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_REAL_STR(name)
777	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
778	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_REAL(name)
779	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_PAE_REAL_STR(name)
780	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_REAL_STR(name)
781	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
782	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT_PHYS
783	#include "PGMGstDefs.h"
784	#include "PGMBth.h"
785	#undef BTH_PGMPOOLKIND_PT_FOR_PT
786	#undef BTH_PGMPOOLKIND_ROOT
787	#undef PGM_BTH_NAME
788	#undef PGM_BTH_NAME_RC_STR
789	#undef PGM_BTH_NAME_R0_STR
790	#undef PGM_GST_TYPE
791	#undef PGM_GST_NAME
792	#undef PGM_GST_NAME_RC_STR
793	#undef PGM_GST_NAME_R0_STR
794
795	/* Guest - protected mode */
796	#define PGM_GST_TYPE PGM_TYPE_PROT
797	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
798	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PROT_STR(name)
799	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
800	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_PROT(name)
801	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_PAE_PROT_STR(name)
802	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_PROT_STR(name)
803	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
804	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT_PHYS
805	#include "PGMGstDefs.h"
806	#include "PGMBth.h"
807	#undef BTH_PGMPOOLKIND_PT_FOR_PT
808	#undef BTH_PGMPOOLKIND_ROOT
809	#undef PGM_BTH_NAME
810	#undef PGM_BTH_NAME_RC_STR
811	#undef PGM_BTH_NAME_R0_STR
812	#undef PGM_GST_TYPE
813	#undef PGM_GST_NAME
814	#undef PGM_GST_NAME_RC_STR
815	#undef PGM_GST_NAME_R0_STR
816
817	/* Guest - 32-bit mode */
818	#define PGM_GST_TYPE PGM_TYPE_32BIT
819	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
820	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_32BIT_STR(name)
821	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
822	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_32BIT(name)
823	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_PAE_32BIT_STR(name)
824	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_32BIT_STR(name)
825	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_32BIT_PT
826	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB
827	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT_FOR_32BIT
828	#include "PGMGstDefs.h"
829	#include "PGMBth.h"
830	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
831	#undef BTH_PGMPOOLKIND_PT_FOR_PT
832	#undef BTH_PGMPOOLKIND_ROOT
833	#undef PGM_BTH_NAME
834	#undef PGM_BTH_NAME_RC_STR
835	#undef PGM_BTH_NAME_R0_STR
836	#undef PGM_GST_TYPE
837	#undef PGM_GST_NAME
838	#undef PGM_GST_NAME_RC_STR
839	#undef PGM_GST_NAME_R0_STR
840
841	/* Guest - PAE mode */
842	#define PGM_GST_TYPE PGM_TYPE_PAE
843	#define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
844	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PAE_STR(name)
845	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PAE_STR(name)
846	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_PAE(name)
847	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_PAE_PAE_STR(name)
848	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_PAE_STR(name)
849	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
850	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
851	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT
852	#include "PGMBth.h"
853	#include "PGMGstDefs.h"
854	#include "PGMGst.h"
855	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
856	#undef BTH_PGMPOOLKIND_PT_FOR_PT
857	#undef BTH_PGMPOOLKIND_ROOT
858	#undef PGM_BTH_NAME
859	#undef PGM_BTH_NAME_RC_STR
860	#undef PGM_BTH_NAME_R0_STR
861	#undef PGM_GST_TYPE
862	#undef PGM_GST_NAME
863	#undef PGM_GST_NAME_RC_STR
864	#undef PGM_GST_NAME_R0_STR
865
866	#undef PGM_SHW_TYPE
867	#undef PGM_SHW_NAME
868	#undef PGM_SHW_NAME_RC_STR
869	#undef PGM_SHW_NAME_R0_STR
870
871
872	/*
873	* Shadow - AMD64 mode
874	*/
875	#define PGM_SHW_TYPE PGM_TYPE_AMD64
876	#define PGM_SHW_NAME(name) PGM_SHW_NAME_AMD64(name)
877	#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_AMD64_STR(name)
878	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_AMD64_STR(name)
879	#include "PGMShw.h"
880
881	#ifdef VBOX_WITH_64_BITS_GUESTS
882	/* Guest - AMD64 mode */
883	# define PGM_GST_TYPE PGM_TYPE_AMD64
884	# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
885	# define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_AMD64_STR(name)
886	# define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_AMD64_STR(name)
887	# define PGM_BTH_NAME(name) PGM_BTH_NAME_AMD64_AMD64(name)
888	# define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_AMD64_AMD64_STR(name)
889	# define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_AMD64_AMD64_STR(name)
890	# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
891	# define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
892	# define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_64BIT_PML4
893	# include "PGMBth.h"
894	# include "PGMGstDefs.h"
895	# include "PGMGst.h"
896	# undef BTH_PGMPOOLKIND_PT_FOR_BIG
897	# undef BTH_PGMPOOLKIND_PT_FOR_PT
898	# undef BTH_PGMPOOLKIND_ROOT
899	# undef PGM_BTH_NAME
900	# undef PGM_BTH_NAME_RC_STR
901	# undef PGM_BTH_NAME_R0_STR
902	# undef PGM_GST_TYPE
903	# undef PGM_GST_NAME
904	# undef PGM_GST_NAME_RC_STR
905	# undef PGM_GST_NAME_R0_STR
906	#endif /* VBOX_WITH_64_BITS_GUESTS */
907
908	#undef PGM_SHW_TYPE
909	#undef PGM_SHW_NAME
910	#undef PGM_SHW_NAME_RC_STR
911	#undef PGM_SHW_NAME_R0_STR
912
913
914	/*
915	* Shadow - Nested paging mode
916	*/
917	#define PGM_SHW_TYPE PGM_TYPE_NESTED
918	#define PGM_SHW_NAME(name) PGM_SHW_NAME_NESTED(name)
919	#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_NESTED_STR(name)
920	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_NESTED_STR(name)
921	#include "PGMShw.h"
922
923	/* Guest - real mode */
924	#define PGM_GST_TYPE PGM_TYPE_REAL
925	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
926	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_REAL_STR(name)
927	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
928	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_REAL(name)
929	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_REAL_STR(name)
930	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_REAL_STR(name)
931	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
932	#include "PGMGstDefs.h"
933	#include "PGMBth.h"
934	#undef BTH_PGMPOOLKIND_PT_FOR_PT
935	#undef PGM_BTH_NAME
936	#undef PGM_BTH_NAME_RC_STR
937	#undef PGM_BTH_NAME_R0_STR
938	#undef PGM_GST_TYPE
939	#undef PGM_GST_NAME
940	#undef PGM_GST_NAME_RC_STR
941	#undef PGM_GST_NAME_R0_STR
942
943	/* Guest - protected mode */
944	#define PGM_GST_TYPE PGM_TYPE_PROT
945	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
946	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PROT_STR(name)
947	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
948	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_PROT(name)
949	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_PROT_STR(name)
950	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_PROT_STR(name)
951	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
952	#include "PGMGstDefs.h"
953	#include "PGMBth.h"
954	#undef BTH_PGMPOOLKIND_PT_FOR_PT
955	#undef PGM_BTH_NAME
956	#undef PGM_BTH_NAME_RC_STR
957	#undef PGM_BTH_NAME_R0_STR
958	#undef PGM_GST_TYPE
959	#undef PGM_GST_NAME
960	#undef PGM_GST_NAME_RC_STR
961	#undef PGM_GST_NAME_R0_STR
962
963	/* Guest - 32-bit mode */
964	#define PGM_GST_TYPE PGM_TYPE_32BIT
965	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
966	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_32BIT_STR(name)
967	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
968	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_32BIT(name)
969	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_32BIT_STR(name)
970	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_32BIT_STR(name)
971	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_32BIT_PT
972	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB
973	#include "PGMGstDefs.h"
974	#include "PGMBth.h"
975	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
976	#undef BTH_PGMPOOLKIND_PT_FOR_PT
977	#undef PGM_BTH_NAME
978	#undef PGM_BTH_NAME_RC_STR
979	#undef PGM_BTH_NAME_R0_STR
980	#undef PGM_GST_TYPE
981	#undef PGM_GST_NAME
982	#undef PGM_GST_NAME_RC_STR
983	#undef PGM_GST_NAME_R0_STR
984
985	/* Guest - PAE mode */
986	#define PGM_GST_TYPE PGM_TYPE_PAE
987	#define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
988	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PAE_STR(name)
989	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PAE_STR(name)
990	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_PAE(name)
991	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_PAE_STR(name)
992	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_PAE_STR(name)
993	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
994	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
995	#include "PGMGstDefs.h"
996	#include "PGMBth.h"
997	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
998	#undef BTH_PGMPOOLKIND_PT_FOR_PT
999	#undef PGM_BTH_NAME
1000	#undef PGM_BTH_NAME_RC_STR
1001	#undef PGM_BTH_NAME_R0_STR
1002	#undef PGM_GST_TYPE
1003	#undef PGM_GST_NAME
1004	#undef PGM_GST_NAME_RC_STR
1005	#undef PGM_GST_NAME_R0_STR
1006
1007	#ifdef VBOX_WITH_64_BITS_GUESTS
1008	/* Guest - AMD64 mode */
1009	# define PGM_GST_TYPE PGM_TYPE_AMD64
1010	# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
1011	# define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_AMD64_STR(name)
1012	# define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_AMD64_STR(name)
1013	# define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_AMD64(name)
1014	# define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_AMD64_STR(name)
1015	# define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_AMD64_STR(name)
1016	# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
1017	# define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
1018	# include "PGMGstDefs.h"
1019	# include "PGMBth.h"
1020	# undef BTH_PGMPOOLKIND_PT_FOR_BIG
1021	# undef BTH_PGMPOOLKIND_PT_FOR_PT
1022	# undef PGM_BTH_NAME
1023	# undef PGM_BTH_NAME_RC_STR
1024	# undef PGM_BTH_NAME_R0_STR
1025	# undef PGM_GST_TYPE
1026	# undef PGM_GST_NAME
1027	# undef PGM_GST_NAME_RC_STR
1028	# undef PGM_GST_NAME_R0_STR
1029	#endif /* VBOX_WITH_64_BITS_GUESTS */
1030
1031	#undef PGM_SHW_TYPE
1032	#undef PGM_SHW_NAME
1033	#undef PGM_SHW_NAME_RC_STR
1034	#undef PGM_SHW_NAME_R0_STR
1035
1036
1037	/*
1038	* Shadow - EPT
1039	*/
1040	#define PGM_SHW_TYPE PGM_TYPE_EPT
1041	#define PGM_SHW_NAME(name) PGM_SHW_NAME_EPT(name)
1042	#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_EPT_STR(name)
1043	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_EPT_STR(name)
1044	#include "PGMShw.h"
1045
1046	/* Guest - real mode */
1047	#define PGM_GST_TYPE PGM_TYPE_REAL
1048	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
1049	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_REAL_STR(name)
1050	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
1051	#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_REAL(name)
1052	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_REAL_STR(name)
1053	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_REAL_STR(name)
1054	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
1055	#include "PGMGstDefs.h"
1056	#include "PGMBth.h"
1057	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1058	#undef PGM_BTH_NAME
1059	#undef PGM_BTH_NAME_RC_STR
1060	#undef PGM_BTH_NAME_R0_STR
1061	#undef PGM_GST_TYPE
1062	#undef PGM_GST_NAME
1063	#undef PGM_GST_NAME_RC_STR
1064	#undef PGM_GST_NAME_R0_STR
1065
1066	/* Guest - protected mode */
1067	#define PGM_GST_TYPE PGM_TYPE_PROT
1068	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
1069	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PROT_STR(name)
1070	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
1071	#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_PROT(name)
1072	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_PROT_STR(name)
1073	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_PROT_STR(name)
1074	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
1075	#include "PGMGstDefs.h"
1076	#include "PGMBth.h"
1077	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1078	#undef PGM_BTH_NAME
1079	#undef PGM_BTH_NAME_RC_STR
1080	#undef PGM_BTH_NAME_R0_STR
1081	#undef PGM_GST_TYPE
1082	#undef PGM_GST_NAME
1083	#undef PGM_GST_NAME_RC_STR
1084	#undef PGM_GST_NAME_R0_STR
1085
1086	/* Guest - 32-bit mode */
1087	#define PGM_GST_TYPE PGM_TYPE_32BIT
1088	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
1089	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_32BIT_STR(name)
1090	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
1091	#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_32BIT(name)
1092	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_32BIT_STR(name)
1093	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_32BIT_STR(name)
1094	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_32BIT_PT
1095	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB
1096	#include "PGMGstDefs.h"
1097	#include "PGMBth.h"
1098	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
1099	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1100	#undef PGM_BTH_NAME
1101	#undef PGM_BTH_NAME_RC_STR
1102	#undef PGM_BTH_NAME_R0_STR
1103	#undef PGM_GST_TYPE
1104	#undef PGM_GST_NAME
1105	#undef PGM_GST_NAME_RC_STR
1106	#undef PGM_GST_NAME_R0_STR
1107
1108	/* Guest - PAE mode */
1109	#define PGM_GST_TYPE PGM_TYPE_PAE
1110	#define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
1111	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PAE_STR(name)
1112	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PAE_STR(name)
1113	#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_PAE(name)
1114	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_PAE_STR(name)
1115	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_PAE_STR(name)
1116	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
1117	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
1118	#include "PGMGstDefs.h"
1119	#include "PGMBth.h"
1120	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
1121	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1122	#undef PGM_BTH_NAME
1123	#undef PGM_BTH_NAME_RC_STR
1124	#undef PGM_BTH_NAME_R0_STR
1125	#undef PGM_GST_TYPE
1126	#undef PGM_GST_NAME
1127	#undef PGM_GST_NAME_RC_STR
1128	#undef PGM_GST_NAME_R0_STR
1129
1130	#ifdef VBOX_WITH_64_BITS_GUESTS
1131	/* Guest - AMD64 mode */
1132	# define PGM_GST_TYPE PGM_TYPE_AMD64
1133	# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
1134	# define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_AMD64_STR(name)
1135	# define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_AMD64_STR(name)
1136	# define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_AMD64(name)
1137	# define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_AMD64_STR(name)
1138	# define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_AMD64_STR(name)
1139	# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
1140	# define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
1141	# include "PGMGstDefs.h"
1142	# include "PGMBth.h"
1143	# undef BTH_PGMPOOLKIND_PT_FOR_BIG
1144	# undef BTH_PGMPOOLKIND_PT_FOR_PT
1145	# undef PGM_BTH_NAME
1146	# undef PGM_BTH_NAME_RC_STR
1147	# undef PGM_BTH_NAME_R0_STR
1148	# undef PGM_GST_TYPE
1149	# undef PGM_GST_NAME
1150	# undef PGM_GST_NAME_RC_STR
1151	# undef PGM_GST_NAME_R0_STR
1152	#endif /* VBOX_WITH_64_BITS_GUESTS */
1153
1154	#undef PGM_SHW_TYPE
1155	#undef PGM_SHW_NAME
1156	#undef PGM_SHW_NAME_RC_STR
1157	#undef PGM_SHW_NAME_R0_STR
1158
1159
1160
1161	/**
1162	* Initiates the paging of VM.
1163	*
1164	* @returns VBox status code.
1165	* @param pVM Pointer to VM structure.
1166	*/
1167	VMMR3DECL(int) PGMR3Init(PVM pVM)
1168	{
1169	LogFlow(("PGMR3Init:\n"));
1170	PCFGMNODE pCfgPGM = CFGMR3GetChild(CFGMR3GetRoot(pVM), "/PGM");
1171	int rc;
1172
1173	/*
1174	* Assert alignment and sizes.
1175	*/
1176	AssertRelease(sizeof(pVM->pgm.s) <= sizeof(pVM->pgm.padding));
1177
1178	/*
1179	* Init the structure.
1180	*/
1181	pVM->pgm.s.offVM = RT_OFFSETOF(VM, pgm.s);
1182	pVM->pgm.s.offVCpu = RT_OFFSETOF(VMCPU, pgm.s);
1183	pVM->pgm.s.enmShadowMode = PGMMODE_INVALID;
1184	pVM->pgm.s.enmGuestMode = PGMMODE_INVALID;
1185	pVM->pgm.s.enmHostMode = SUPPAGINGMODE_INVALID;
1186	pVM->pgm.s.GCPhysCR3 = NIL_RTGCPHYS;
1187	pVM->pgm.s.GCPtrPrevRamRangeMapping = MM_HYPER_AREA_ADDRESS;
1188	pVM->pgm.s.fA20Enabled = true;
1189	pVM->pgm.s.GCPhys4MBPSEMask = RT_BIT_64(32) - 1; /* default; checked later */
1190	pVM->pgm.s.pGstPaePdptR3 = NULL;
1191	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
1192	pVM->pgm.s.pGstPaePdptR0 = NIL_RTR0PTR;
1193	#endif
1194	pVM->pgm.s.pGstPaePdptRC = NIL_RTRCPTR;
1195	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.apGstPaePDsR3); i++)
1196	{
1197	pVM->pgm.s.apGstPaePDsR3[i] = NULL;
1198	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
1199	pVM->pgm.s.apGstPaePDsR0[i] = NIL_RTR0PTR;
1200	#endif
1201	pVM->pgm.s.apGstPaePDsRC[i] = NIL_RTRCPTR;
1202	pVM->pgm.s.aGCPhysGstPaePDs[i] = NIL_RTGCPHYS;
1203	pVM->pgm.s.aGCPhysGstPaePDsMonitored[i] = NIL_RTGCPHYS;
1204	}
1205
1206	rc = CFGMR3QueryBoolDef(pCfgPGM, "RamPreAlloc", &pVM->pgm.s.fRamPreAlloc, false);
1207	AssertLogRelRCReturn(rc, rc);
1208
1209	#if HC_ARCH_BITS == 64 \|\| 1 /** @todo 4GB/32-bit: remove \|\| 1 later and adjust the limit. */
1210	rc = CFGMR3QueryU32Def(pCfgPGM, "MaxRing3Chunks", &pVM->pgm.s.ChunkR3Map.cMax, UINT32_MAX);
1211	#else
1212	rc = CFGMR3QueryU32Def(pCfgPGM, "MaxRing3Chunks", &pVM->pgm.s.ChunkR3Map.cMax, _1G / GMM_CHUNK_SIZE);
1213	#endif
1214	AssertLogRelRCReturn(rc, rc);
1215	for (uint32_t i = 0; i < RT_ELEMENTS(pVM->pgm.s.ChunkR3Map.Tlb.aEntries); i++)
1216	pVM->pgm.s.ChunkR3Map.Tlb.aEntries[i].idChunk = NIL_GMM_CHUNKID;
1217
1218	/*
1219	* Get the configured RAM size - to estimate saved state size.
1220	*/
1221	uint64_t cbRam;
1222	rc = CFGMR3QueryU64(CFGMR3GetRoot(pVM), "RamSize", &cbRam);
1223	if (rc == VERR_CFGM_VALUE_NOT_FOUND)
1224	cbRam = pVM->pgm.s.cbRamSize = 0;
1225	else if (RT_SUCCESS(rc))
1226	{
1227	if (cbRam < PAGE_SIZE)
1228	cbRam = 0;
1229	cbRam = RT_ALIGN_64(cbRam, PAGE_SIZE);
1230	pVM->pgm.s.cbRamSize = (RTUINT)cbRam; /* pointless legacy, remove after enabling the new phys code. */
1231	}
1232	else
1233	{
1234	AssertMsgFailed(("Configuration error: Failed to query integer \"RamSize\", rc=%Rrc.\n", rc));
1235	return rc;
1236	}
1237
1238	/*
1239	* Register callbacks, string formatters and the saved state data unit.
1240	*/
1241	#ifdef VBOX_STRICT
1242	VMR3AtStateRegister(pVM, pgmR3ResetNoMorePhysWritesFlag, NULL);
1243	#endif
1244	PGMRegisterStringFormatTypes();
1245
1246	rc = SSMR3RegisterInternal(pVM, "pgm", 1, PGM_SAVED_STATE_VERSION, (size_t)cbRam + sizeof(PGM),
1247	NULL, pgmR3Save, NULL,
1248	NULL, pgmR3Load, NULL);
1249	if (RT_FAILURE(rc))
1250	return rc;
1251
1252	/*
1253	* Initialize the PGM critical section and flush the phys TLBs
1254	*/
1255	rc = PDMR3CritSectInit(pVM, &pVM->pgm.s.CritSect, "PGM");
1256	AssertRCReturn(rc, rc);
1257
1258	PGMR3PhysChunkInvalidateTLB(pVM);
1259	PGMPhysInvalidatePageR3MapTLB(pVM);
1260	PGMPhysInvalidatePageR0MapTLB(pVM);
1261	PGMPhysInvalidatePageGCMapTLB(pVM);
1262
1263	#ifdef VBOX_WITH_NEW_PHYS_CODE
1264	/*
1265	* For the time being we sport a full set of handy pages in addition to the base
1266	* memory to simplify things.
1267	*/
1268	rc = MMR3ReserveHandyPages(pVM, RT_ELEMENTS(pVM->pgm.s.aHandyPages));
1269	AssertRCReturn(rc, rc);
1270	#endif
1271
1272	/*
1273	* Trees
1274	*/
1275	rc = MMHyperAlloc(pVM, sizeof(PGMTREES), 0, MM_TAG_PGM, (void **)&pVM->pgm.s.pTreesR3);
1276	if (RT_SUCCESS(rc))
1277	{
1278	pVM->pgm.s.pTreesR0 = MMHyperR3ToR0(pVM, pVM->pgm.s.pTreesR3);
1279	pVM->pgm.s.pTreesRC = MMHyperR3ToRC(pVM, pVM->pgm.s.pTreesR3);
1280
1281	/*
1282	* Alocate the zero page.
1283	*/
1284	rc = MMHyperAlloc(pVM, PAGE_SIZE, PAGE_SIZE, MM_TAG_PGM, &pVM->pgm.s.pvZeroPgR3);
1285	}
1286	if (RT_SUCCESS(rc))
1287	{
1288	pVM->pgm.s.pvZeroPgGC = MMHyperR3ToRC(pVM, pVM->pgm.s.pvZeroPgR3);
1289	pVM->pgm.s.pvZeroPgR0 = MMHyperR3ToR0(pVM, pVM->pgm.s.pvZeroPgR3);
1290	pVM->pgm.s.HCPhysZeroPg = MMR3HyperHCVirt2HCPhys(pVM, pVM->pgm.s.pvZeroPgR3);
1291	AssertRelease(pVM->pgm.s.HCPhysZeroPg != NIL_RTHCPHYS);
1292
1293	/*
1294	* Init the paging.
1295	*/
1296	rc = pgmR3InitPaging(pVM);
1297	}
1298	if (RT_SUCCESS(rc))
1299	{
1300	/*
1301	* Init the page pool.
1302	*/
1303	rc = pgmR3PoolInit(pVM);
1304	}
1305	if (RT_SUCCESS(rc))
1306	rc = PGMR3ChangeMode(pVM, PGMMODE_REAL);
1307
1308	if (RT_SUCCESS(rc))
1309	{
1310	/*
1311	* Info & statistics
1312	*/
1313	DBGFR3InfoRegisterInternal(pVM, "mode",
1314	"Shows the current paging mode. "
1315	"Recognizes 'all', 'guest', 'shadow' and 'host' as arguments, defaulting to 'all' if nothing's given.",
1316	pgmR3InfoMode);
1317	DBGFR3InfoRegisterInternal(pVM, "pgmcr3",
1318	"Dumps all the entries in the top level paging table. No arguments.",
1319	pgmR3InfoCr3);
1320	DBGFR3InfoRegisterInternal(pVM, "phys",
1321	"Dumps all the physical address ranges. No arguments.",
1322	pgmR3PhysInfo);
1323	DBGFR3InfoRegisterInternal(pVM, "handlers",
1324	"Dumps physical, virtual and hyper virtual handlers. "
1325	"Pass 'phys', 'virt', 'hyper' as argument if only one kind is wanted."
1326	"Add 'nost' if the statistics are unwanted, use together with 'all' or explicit selection.",
1327	pgmR3InfoHandlers);
1328	DBGFR3InfoRegisterInternal(pVM, "mappings",
1329	"Dumps guest mappings.",
1330	pgmR3MapInfo);
1331
1332	STAM_REL_REG(pVM, &pVM->pgm.s.cGuestModeChanges, STAMTYPE_COUNTER, "/PGM/cGuestModeChanges", STAMUNIT_OCCURENCES, "Number of guest mode changes.");
1333	STAM_REL_REG(pVM, &pVM->pgm.s.cRelocations, STAMTYPE_COUNTER, "/PGM/cRelocations", STAMUNIT_OCCURENCES, "Number of hypervisor relocations.");
1334	#ifdef VBOX_WITH_STATISTICS
1335	pgmR3InitStats(pVM);
1336	#endif
1337	#ifdef VBOX_WITH_DEBUGGER
1338	/*
1339	* Debugger commands.
1340	*/
1341	static bool s_fRegisteredCmds = false;
1342	if (!s_fRegisteredCmds)
1343	{
1344	int rc = DBGCRegisterCommands(&g_aCmds[0], RT_ELEMENTS(g_aCmds));
1345	if (RT_SUCCESS(rc))
1346	s_fRegisteredCmds = true;
1347	}
1348	#endif
1349	return VINF_SUCCESS;
1350	}
1351
1352	/* Almost no cleanup necessary, MM frees all memory. */
1353	PDMR3CritSectDelete(&pVM->pgm.s.CritSect);
1354
1355	return rc;
1356	}
1357
1358
1359	/**
1360	* Initializes the per-VCPU PGM.
1361	*
1362	* @returns VBox status code.
1363	* @param pVM The VM to operate on.
1364	*/
1365	VMMR3DECL(int) PGMR3InitCPU(PVM pVM)
1366	{
1367	LogFlow(("PGMR3InitCPU\n"));
1368	return VINF_SUCCESS;
1369	}
1370
1371
1372	/**
1373	* Init paging.
1374	*
1375	* Since we need to check what mode the host is operating in before we can choose
1376	* the right paging functions for the host we have to delay this until R0 has
1377	* been initialized.
1378	*
1379	* @returns VBox status code.
1380	* @param pVM VM handle.
1381	*/
1382	static int pgmR3InitPaging(PVM pVM)
1383	{
1384	/*
1385	* Force a recalculation of modes and switcher so everyone gets notified.
1386	*/
1387	pVM->pgm.s.enmShadowMode = PGMMODE_INVALID;
1388	pVM->pgm.s.enmGuestMode = PGMMODE_INVALID;
1389	pVM->pgm.s.enmHostMode = SUPPAGINGMODE_INVALID;
1390
1391	/*
1392	* Allocate static mapping space for whatever the cr3 register
1393	* points to and in the case of PAE mode to the 4 PDs.
1394	*/
1395	int rc = MMR3HyperReserve(pVM, PAGE_SIZE * 5, "CR3 mapping", &pVM->pgm.s.GCPtrCR3Mapping);
1396	if (RT_FAILURE(rc))
1397	{
1398	AssertMsgFailed(("Failed to reserve two pages for cr mapping in HMA, rc=%Rrc\n", rc));
1399	return rc;
1400	}
1401	MMR3HyperReserve(pVM, PAGE_SIZE, "fence", NULL);
1402
1403	/*
1404	* Allocate pages for the three possible intermediate contexts
1405	* (AMD64, PAE and plain 32-Bit). We maintain all three contexts
1406	* for the sake of simplicity. The AMD64 uses the PAE for the
1407	* lower levels, making the total number of pages 11 (3 + 7 + 1).
1408	*
1409	* We assume that two page tables will be enought for the core code
1410	* mappings (HC virtual and identity).
1411	*/
1412	pVM->pgm.s.pInterPD = (PX86PD)MMR3PageAllocLow(pVM);
1413	pVM->pgm.s.apInterPTs[0] = (PX86PT)MMR3PageAllocLow(pVM);
1414	pVM->pgm.s.apInterPTs[1] = (PX86PT)MMR3PageAllocLow(pVM);
1415	pVM->pgm.s.apInterPaePTs[0] = (PX86PTPAE)MMR3PageAlloc(pVM);
1416	pVM->pgm.s.apInterPaePTs[1] = (PX86PTPAE)MMR3PageAlloc(pVM);
1417	pVM->pgm.s.apInterPaePDs[0] = (PX86PDPAE)MMR3PageAlloc(pVM);
1418	pVM->pgm.s.apInterPaePDs[1] = (PX86PDPAE)MMR3PageAlloc(pVM);
1419	pVM->pgm.s.apInterPaePDs[2] = (PX86PDPAE)MMR3PageAlloc(pVM);
1420	pVM->pgm.s.apInterPaePDs[3] = (PX86PDPAE)MMR3PageAlloc(pVM);
1421	pVM->pgm.s.pInterPaePDPT = (PX86PDPT)MMR3PageAllocLow(pVM);
1422	pVM->pgm.s.pInterPaePDPT64 = (PX86PDPT)MMR3PageAllocLow(pVM);
1423	pVM->pgm.s.pInterPaePML4 = (PX86PML4)MMR3PageAllocLow(pVM);
1424	if ( !pVM->pgm.s.pInterPD
1425	\|\| !pVM->pgm.s.apInterPTs[0]
1426	\|\| !pVM->pgm.s.apInterPTs[1]
1427	\|\| !pVM->pgm.s.apInterPaePTs[0]
1428	\|\| !pVM->pgm.s.apInterPaePTs[1]
1429	\|\| !pVM->pgm.s.apInterPaePDs[0]
1430	\|\| !pVM->pgm.s.apInterPaePDs[1]
1431	\|\| !pVM->pgm.s.apInterPaePDs[2]
1432	\|\| !pVM->pgm.s.apInterPaePDs[3]
1433	\|\| !pVM->pgm.s.pInterPaePDPT
1434	\|\| !pVM->pgm.s.pInterPaePDPT64
1435	\|\| !pVM->pgm.s.pInterPaePML4)
1436	{
1437	AssertMsgFailed(("Failed to allocate pages for the intermediate context!\n"));
1438	return VERR_NO_PAGE_MEMORY;
1439	}
1440
1441	pVM->pgm.s.HCPhysInterPD = MMPage2Phys(pVM, pVM->pgm.s.pInterPD);
1442	AssertRelease(pVM->pgm.s.HCPhysInterPD != NIL_RTHCPHYS && !(pVM->pgm.s.HCPhysInterPD & PAGE_OFFSET_MASK));
1443	pVM->pgm.s.HCPhysInterPaePDPT = MMPage2Phys(pVM, pVM->pgm.s.pInterPaePDPT);
1444	AssertRelease(pVM->pgm.s.HCPhysInterPaePDPT != NIL_RTHCPHYS && !(pVM->pgm.s.HCPhysInterPaePDPT & PAGE_OFFSET_MASK));
1445	pVM->pgm.s.HCPhysInterPaePML4 = MMPage2Phys(pVM, pVM->pgm.s.pInterPaePML4);
1446	AssertRelease(pVM->pgm.s.HCPhysInterPaePML4 != NIL_RTHCPHYS && !(pVM->pgm.s.HCPhysInterPaePML4 & PAGE_OFFSET_MASK) && pVM->pgm.s.HCPhysInterPaePML4 < 0xffffffff);
1447
1448	/*
1449	* Initialize the pages, setting up the PML4 and PDPT for repetitive 4GB action.
1450	*/
1451	ASMMemZeroPage(pVM->pgm.s.pInterPD);
1452	ASMMemZeroPage(pVM->pgm.s.apInterPTs[0]);
1453	ASMMemZeroPage(pVM->pgm.s.apInterPTs[1]);
1454
1455	ASMMemZeroPage(pVM->pgm.s.apInterPaePTs[0]);
1456	ASMMemZeroPage(pVM->pgm.s.apInterPaePTs[1]);
1457
1458	ASMMemZeroPage(pVM->pgm.s.pInterPaePDPT);
1459	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.apInterPaePDs); i++)
1460	{
1461	ASMMemZeroPage(pVM->pgm.s.apInterPaePDs[i]);
1462	pVM->pgm.s.pInterPaePDPT->a[i].u = X86_PDPE_P \| PGM_PLXFLAGS_PERMANENT
1463	\| MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[i]);
1464	}
1465
1466	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.pInterPaePDPT64->a); i++)
1467	{
1468	const unsigned iPD = i % RT_ELEMENTS(pVM->pgm.s.apInterPaePDs);
1469	pVM->pgm.s.pInterPaePDPT64->a[i].u = X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_A \| PGM_PLXFLAGS_PERMANENT
1470	\| MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[iPD]);
1471	}
1472
1473	RTHCPHYS HCPhysInterPaePDPT64 = MMPage2Phys(pVM, pVM->pgm.s.pInterPaePDPT64);
1474	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.pInterPaePML4->a); i++)
1475	pVM->pgm.s.pInterPaePML4->a[i].u = X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_A \| PGM_PLXFLAGS_PERMANENT
1476	\| HCPhysInterPaePDPT64;
1477
1478	/*
1479	* Initialize paging workers and mode from current host mode
1480	* and the guest running in real mode.
1481	*/
1482	pVM->pgm.s.enmHostMode = SUPGetPagingMode();
1483	switch (pVM->pgm.s.enmHostMode)
1484	{
1485	case SUPPAGINGMODE_32_BIT:
1486	case SUPPAGINGMODE_32_BIT_GLOBAL:
1487	case SUPPAGINGMODE_PAE:
1488	case SUPPAGINGMODE_PAE_GLOBAL:
1489	case SUPPAGINGMODE_PAE_NX:
1490	case SUPPAGINGMODE_PAE_GLOBAL_NX:
1491	break;
1492
1493	case SUPPAGINGMODE_AMD64:
1494	case SUPPAGINGMODE_AMD64_GLOBAL:
1495	case SUPPAGINGMODE_AMD64_NX:
1496	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
1497	#ifndef VBOX_WITH_HYBRID_32BIT_KERNEL
1498	if (ARCH_BITS != 64)
1499	{
1500	AssertMsgFailed(("Host mode %d (64-bit) is not supported by non-64bit builds\n", pVM->pgm.s.enmHostMode));
1501	LogRel(("Host mode %d (64-bit) is not supported by non-64bit builds\n", pVM->pgm.s.enmHostMode));
1502	return VERR_PGM_UNSUPPORTED_HOST_PAGING_MODE;
1503	}
1504	#endif
1505	break;
1506	default:
1507	AssertMsgFailed(("Host mode %d is not supported\n", pVM->pgm.s.enmHostMode));
1508	return VERR_PGM_UNSUPPORTED_HOST_PAGING_MODE;
1509	}
1510	rc = pgmR3ModeDataInit(pVM, false /* don't resolve GC and R0 syms yet */);
1511	if (RT_SUCCESS(rc))
1512	{
1513	LogFlow(("pgmR3InitPaging: returns successfully\n"));
1514	#if HC_ARCH_BITS == 64
1515	LogRel(("Debug: HCPhysInterPD=%RHp HCPhysInterPaePDPT=%RHp HCPhysInterPaePML4=%RHp\n",
1516	pVM->pgm.s.HCPhysInterPD, pVM->pgm.s.HCPhysInterPaePDPT, pVM->pgm.s.HCPhysInterPaePML4));
1517	LogRel(("Debug: apInterPTs={%RHp,%RHp} apInterPaePTs={%RHp,%RHp} apInterPaePDs={%RHp,%RHp,%RHp,%RHp} pInterPaePDPT64=%RHp\n",
1518	MMPage2Phys(pVM, pVM->pgm.s.apInterPTs[0]), MMPage2Phys(pVM, pVM->pgm.s.apInterPTs[1]),
1519	MMPage2Phys(pVM, pVM->pgm.s.apInterPaePTs[0]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePTs[1]),
1520	MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[0]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[1]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[2]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[3]),
1521	MMPage2Phys(pVM, pVM->pgm.s.pInterPaePDPT64)));
1522	#endif
1523
1524	return VINF_SUCCESS;
1525	}
1526
1527	LogFlow(("pgmR3InitPaging: returns %Rrc\n", rc));
1528	return rc;
1529	}
1530
1531
1532	#ifdef VBOX_WITH_STATISTICS
1533	/**
1534	* Init statistics
1535	*/
1536	static void pgmR3InitStats(PVM pVM)
1537	{
1538	PPGM pPGM = &pVM->pgm.s;
1539	unsigned i;
1540
1541	/*
1542	* Note! The layout of this function matches the member layout exactly!
1543	*/
1544
1545	/* Common - misc variables */
1546	STAM_REG(pVM, &pPGM->cAllPages, STAMTYPE_U32, "/PGM/Page/cAllPages", STAMUNIT_OCCURENCES, "The total number of pages.");
1547	STAM_REG(pVM, &pPGM->cPrivatePages, STAMTYPE_U32, "/PGM/Page/cPrivatePages", STAMUNIT_OCCURENCES, "The number of private pages.");
1548	STAM_REG(pVM, &pPGM->cSharedPages, STAMTYPE_U32, "/PGM/Page/cSharedPages", STAMUNIT_OCCURENCES, "The number of shared pages.");
1549	STAM_REG(pVM, &pPGM->cZeroPages, STAMTYPE_U32, "/PGM/Page/cZeroPages", STAMUNIT_OCCURENCES, "The number of zero backed pages.");
1550	STAM_REG(pVM, &pPGM->cHandyPages, STAMTYPE_U32, "/PGM/Page/cHandyPages", STAMUNIT_OCCURENCES, "The number of handy pages (not included in cAllPages).");
1551	STAM_REG(pVM, &pPGM->ChunkR3Map.c, STAMTYPE_U32, "/PGM/ChunkR3Map/c", STAMUNIT_OCCURENCES, "Number of mapped chunks.");
1552	STAM_REG(pVM, &pPGM->ChunkR3Map.cMax, STAMTYPE_U32, "/PGM/ChunkR3Map/cMax", STAMUNIT_OCCURENCES, "Maximum number of mapped chunks.");
1553
1554	/* Common - stats */
1555	#ifdef PGMPOOL_WITH_GCPHYS_TRACKING
1556	STAM_REG(pVM, &pPGM->StatTrackVirgin, STAMTYPE_COUNTER, "/PGM/Track/Virgin", STAMUNIT_OCCURENCES, "The number of first time shadowings");
1557	STAM_REG(pVM, &pPGM->StatTrackAliased, STAMTYPE_COUNTER, "/PGM/Track/Aliased", STAMUNIT_OCCURENCES, "The number of times switching to cRef2, i.e. the page is being shadowed by two PTs.");
1558	STAM_REG(pVM, &pPGM->StatTrackAliasedMany, STAMTYPE_COUNTER, "/PGM/Track/AliasedMany", STAMUNIT_OCCURENCES, "The number of times we're tracking using cRef2.");
1559	STAM_REG(pVM, &pPGM->StatTrackAliasedLots, STAMTYPE_COUNTER, "/PGM/Track/AliasedLots", STAMUNIT_OCCURENCES, "The number of times we're hitting pages which has overflowed cRef2");
1560	STAM_REG(pVM, &pPGM->StatTrackOverflows, STAMTYPE_COUNTER, "/PGM/Track/Overflows", STAMUNIT_OCCURENCES, "The number of times the extent list grows to long.");
1561	STAM_REG(pVM, &pPGM->StatTrackDeref, STAMTYPE_PROFILE, "/PGM/Track/Deref", STAMUNIT_OCCURENCES, "Profiling of SyncPageWorkerTrackDeref (expensive).");
1562	#endif
1563	for (i = 0; i < RT_ELEMENTS(pPGM->StatSyncPtPD); i++)
1564	STAMR3RegisterF(pVM, &pPGM->StatSyncPtPD[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
1565	"The number of SyncPT per PD n.", "/PGM/PDSyncPT/%04X", i);
1566	for (i = 0; i < RT_ELEMENTS(pPGM->StatSyncPagePD); i++)
1567	STAMR3RegisterF(pVM, &pPGM->StatSyncPagePD[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
1568	"The number of SyncPage per PD n.", "/PGM/PDSyncPage/%04X", i);
1569
1570	/* R3 only: */
1571	STAM_REG(pVM, &pPGM->StatR3DetectedConflicts, STAMTYPE_COUNTER, "/PGM/R3/DetectedConflicts", STAMUNIT_OCCURENCES, "The number of times PGMR3CheckMappingConflicts() detected a conflict.");
1572	STAM_REG(pVM, &pPGM->StatR3ResolveConflict, STAMTYPE_PROFILE, "/PGM/R3/ResolveConflict", STAMUNIT_TICKS_PER_CALL, "pgmR3SyncPTResolveConflict() profiling (includes the entire relocation).");
1573	STAM_REG(pVM, &pPGM->StatR3GuestPDWrite, STAMTYPE_COUNTER, "/PGM/R3/PDWrite", STAMUNIT_OCCURENCES, "The total number of times pgmHCGuestPDWriteHandler() was called.");
1574	STAM_REG(pVM, &pPGM->StatR3GuestPDWriteConflict, STAMTYPE_COUNTER, "/PGM/R3/PDWriteConflict", STAMUNIT_OCCURENCES, "The number of times pgmHCGuestPDWriteHandler() detected a conflict.");
1575	#ifndef VBOX_WITH_NEW_PHYS_CODE
1576	STAM_REG(pVM, &pPGM->StatR3DynRamTotal, STAMTYPE_COUNTER, "/PGM/DynAlloc/TotalAlloc", STAMUNIT_MEGABYTES, "Allocated MBs of guest ram.");
1577	STAM_REG(pVM, &pPGM->StatR3DynRamGrow, STAMTYPE_COUNTER, "/PGM/DynAlloc/Grow", STAMUNIT_OCCURENCES, "Nr of pgmr3PhysGrowRange calls.");
1578	#endif
1579
1580	/* R0 only: */
1581	STAM_REG(pVM, &pPGM->StatR0DynMapMigrateInvlPg, STAMTYPE_COUNTER, "/PGM/R0/DynMapMigrateInvlPg", STAMUNIT_OCCURENCES, "invlpg count in PGMDynMapMigrateAutoSet.");
1582	STAM_REG(pVM, &pPGM->StatR0DynMapGCPageInl, STAMTYPE_PROFILE, "/PGM/R0/DynMapPageGCPageInl", STAMUNIT_TICKS_PER_CALL, "Calls to pgmR0DynMapGCPageInlined.");
1583	STAM_REG(pVM, &pPGM->StatR0DynMapGCPageInlHits, STAMTYPE_COUNTER, "/PGM/R0/DynMapPageGCPageInl/Hits", STAMUNIT_OCCURENCES, "Hash table lookup hits.");
1584	STAM_REG(pVM, &pPGM->StatR0DynMapGCPageInlMisses, STAMTYPE_COUNTER, "/PGM/R0/DynMapPageGCPageInl/Misses", STAMUNIT_OCCURENCES, "Misses that falls back to code common with PGMDynMapHCPage.");
1585	STAM_REG(pVM, &pPGM->StatR0DynMapGCPageInlRamHits, STAMTYPE_COUNTER, "/PGM/R0/DynMapPageGCPageInl/RamHits", STAMUNIT_OCCURENCES, "1st ram range hits.");
1586	STAM_REG(pVM, &pPGM->StatR0DynMapGCPageInlRamMisses, STAMTYPE_COUNTER, "/PGM/R0/DynMapPageGCPageInl/RamMisses", STAMUNIT_OCCURENCES, "1st ram range misses, takes slow path.");
1587	STAM_REG(pVM, &pPGM->StatR0DynMapHCPageInl, STAMTYPE_PROFILE, "/PGM/R0/DynMapPageHCPageInl", STAMUNIT_TICKS_PER_CALL, "Calls to pgmR0DynMapHCPageInlined.");
1588	STAM_REG(pVM, &pPGM->StatR0DynMapHCPageInlHits, STAMTYPE_COUNTER, "/PGM/R0/DynMapPageHCPageInl/Hits", STAMUNIT_OCCURENCES, "Hash table lookup hits.");
1589	STAM_REG(pVM, &pPGM->StatR0DynMapHCPageInlMisses, STAMTYPE_COUNTER, "/PGM/R0/DynMapPageHCPageInl/Misses", STAMUNIT_OCCURENCES, "Misses that falls back to code common with PGMDynMapHCPage.");
1590	STAM_REG(pVM, &pPGM->StatR0DynMapPage, STAMTYPE_COUNTER, "/PGM/R0/DynMapPage", STAMUNIT_OCCURENCES, "Calls to pgmR0DynMapPage");
1591	STAM_REG(pVM, &pPGM->StatR0DynMapSetOptimize, STAMTYPE_COUNTER, "/PGM/R0/DynMapPage/SetOptimize", STAMUNIT_OCCURENCES, "Calls to pgmDynMapOptimizeAutoSet.");
1592	STAM_REG(pVM, &pPGM->StatR0DynMapSetSearchFlushes, STAMTYPE_COUNTER, "/PGM/R0/DynMapPage/SetSearchFlushes",STAMUNIT_OCCURENCES, "Set search restorting to subset flushes.");
1593	STAM_REG(pVM, &pPGM->StatR0DynMapSetSearchHits, STAMTYPE_COUNTER, "/PGM/R0/DynMapPage/SetSearchHits", STAMUNIT_OCCURENCES, "Set search hits.");
1594	STAM_REG(pVM, &pPGM->StatR0DynMapSetSearchMisses, STAMTYPE_COUNTER, "/PGM/R0/DynMapPage/SetSearchMisses", STAMUNIT_OCCURENCES, "Set search misses.");
1595	STAM_REG(pVM, &pPGM->StatR0DynMapHCPage, STAMTYPE_PROFILE, "/PGM/R0/DynMapPage/HCPage", STAMUNIT_TICKS_PER_CALL, "Calls to PGMDynMapHCPage (ring-0).");
1596	STAM_REG(pVM, &pPGM->StatR0DynMapPageHits0, STAMTYPE_COUNTER, "/PGM/R0/DynMapPage/Hits0", STAMUNIT_OCCURENCES, "Hits at iPage+0");
1597	STAM_REG(pVM, &pPGM->StatR0DynMapPageHits1, STAMTYPE_COUNTER, "/PGM/R0/DynMapPage/Hits1", STAMUNIT_OCCURENCES, "Hits at iPage+1");
1598	STAM_REG(pVM, &pPGM->StatR0DynMapPageHits2, STAMTYPE_COUNTER, "/PGM/R0/DynMapPage/Hits2", STAMUNIT_OCCURENCES, "Hits at iPage+2");
1599	STAM_REG(pVM, &pPGM->StatR0DynMapPageInvlPg, STAMTYPE_COUNTER, "/PGM/R0/DynMapPage/InvlPg", STAMUNIT_OCCURENCES, "invlpg count in pgmR0DynMapPageSlow.");
1600	STAM_REG(pVM, &pPGM->StatR0DynMapPageSlow, STAMTYPE_COUNTER, "/PGM/R0/DynMapPage/Slow", STAMUNIT_OCCURENCES, "Calls to pgmR0DynMapPageSlow - subtract this from pgmR0DynMapPage to get 1st level hits.");
1601	STAM_REG(pVM, &pPGM->StatR0DynMapPageSlowLoopHits, STAMTYPE_COUNTER, "/PGM/R0/DynMapPage/SlowLoopHits" , STAMUNIT_OCCURENCES, "Hits in the loop path.");
1602	STAM_REG(pVM, &pPGM->StatR0DynMapPageSlowLoopMisses, STAMTYPE_COUNTER, "/PGM/R0/DynMapPage/SlowLoopMisses", STAMUNIT_OCCURENCES, "Misses in the loop path. NonLoopMisses = Slow - SlowLoopHit - SlowLoopMisses");
1603	//STAM_REG(pVM, &pPGM->StatR0DynMapPageSlowLostHits, STAMTYPE_COUNTER, "/PGM/R0/DynMapPage/SlowLostHits", STAMUNIT_OCCURENCES, "Lost hits.");
1604	STAM_REG(pVM, &pPGM->StatR0DynMapSubsets, STAMTYPE_COUNTER, "/PGM/R0/Subsets", STAMUNIT_OCCURENCES, "Times PGMDynMapPushAutoSubset was called.");
1605	STAM_REG(pVM, &pPGM->StatR0DynMapPopFlushes, STAMTYPE_COUNTER, "/PGM/R0/SubsetPopFlushes", STAMUNIT_OCCURENCES, "Times PGMDynMapPopAutoSubset flushes the subset.");
1606	STAM_REG(pVM, &pPGM->aStatR0DynMapSetSize[0], STAMTYPE_COUNTER, "/PGM/R0/SetSize000..09", STAMUNIT_OCCURENCES, "00-09% filled");
1607	STAM_REG(pVM, &pPGM->aStatR0DynMapSetSize[1], STAMTYPE_COUNTER, "/PGM/R0/SetSize010..19", STAMUNIT_OCCURENCES, "10-19% filled");
1608	STAM_REG(pVM, &pPGM->aStatR0DynMapSetSize[2], STAMTYPE_COUNTER, "/PGM/R0/SetSize020..29", STAMUNIT_OCCURENCES, "20-29% filled");
1609	STAM_REG(pVM, &pPGM->aStatR0DynMapSetSize[3], STAMTYPE_COUNTER, "/PGM/R0/SetSize030..39", STAMUNIT_OCCURENCES, "30-39% filled");
1610	STAM_REG(pVM, &pPGM->aStatR0DynMapSetSize[4], STAMTYPE_COUNTER, "/PGM/R0/SetSize040..49", STAMUNIT_OCCURENCES, "40-49% filled");
1611	STAM_REG(pVM, &pPGM->aStatR0DynMapSetSize[5], STAMTYPE_COUNTER, "/PGM/R0/SetSize050..59", STAMUNIT_OCCURENCES, "50-59% filled");
1612	STAM_REG(pVM, &pPGM->aStatR0DynMapSetSize[6], STAMTYPE_COUNTER, "/PGM/R0/SetSize060..69", STAMUNIT_OCCURENCES, "60-69% filled");
1613	STAM_REG(pVM, &pPGM->aStatR0DynMapSetSize[7], STAMTYPE_COUNTER, "/PGM/R0/SetSize070..79", STAMUNIT_OCCURENCES, "70-79% filled");
1614	STAM_REG(pVM, &pPGM->aStatR0DynMapSetSize[8], STAMTYPE_COUNTER, "/PGM/R0/SetSize080..89", STAMUNIT_OCCURENCES, "80-89% filled");
1615	STAM_REG(pVM, &pPGM->aStatR0DynMapSetSize[9], STAMTYPE_COUNTER, "/PGM/R0/SetSize090..99", STAMUNIT_OCCURENCES, "90-99% filled");
1616	STAM_REG(pVM, &pPGM->aStatR0DynMapSetSize[10], STAMTYPE_COUNTER, "/PGM/R0/SetSize100", STAMUNIT_OCCURENCES, "100% filled");
1617
1618	/* GC only: */
1619	STAM_REG(pVM, &pPGM->StatRCDynMapCacheHits, STAMTYPE_COUNTER, "/PGM/RC/DynMapCache/Hits" , STAMUNIT_OCCURENCES, "Number of dynamic page mapping cache hits.");
1620	STAM_REG(pVM, &pPGM->StatRCDynMapCacheMisses, STAMTYPE_COUNTER, "/PGM/RC/DynMapCache/Misses" , STAMUNIT_OCCURENCES, "Number of dynamic page mapping cache misses.");
1621	STAM_REG(pVM, &pPGM->StatRCInvlPgConflict, STAMTYPE_COUNTER, "/PGM/RC/InvlPgConflict", STAMUNIT_OCCURENCES, "Number of times PGMInvalidatePage() detected a mapping conflict.");
1622	STAM_REG(pVM, &pPGM->StatRCInvlPgSyncMonCR3, STAMTYPE_COUNTER, "/PGM/RC/InvlPgSyncMonitorCR3", STAMUNIT_OCCURENCES, "Number of times PGMInvalidatePage() ran into PGM_SYNC_MONITOR_CR3.");
1623
1624	/* RZ only: */
1625	STAM_REG(pVM, &pPGM->StatRZTrap0e, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMTrap0eHandler() body.");
1626	STAM_REG(pVM, &pPGM->StatRZTrap0eTimeCheckPageFault, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time/CheckPageFault", STAMUNIT_TICKS_PER_CALL, "Profiling of checking for dirty/access emulation faults.");
1627	STAM_REG(pVM, &pPGM->StatRZTrap0eTimeSyncPT, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time/SyncPT", STAMUNIT_TICKS_PER_CALL, "Profiling of lazy page table syncing.");
1628	STAM_REG(pVM, &pPGM->StatRZTrap0eTimeMapping, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time/Mapping", STAMUNIT_TICKS_PER_CALL, "Profiling of checking virtual mappings.");
1629	STAM_REG(pVM, &pPGM->StatRZTrap0eTimeOutOfSync, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time/OutOfSync", STAMUNIT_TICKS_PER_CALL, "Profiling of out of sync page handling.");
1630	STAM_REG(pVM, &pPGM->StatRZTrap0eTimeHandlers, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time/Handlers", STAMUNIT_TICKS_PER_CALL, "Profiling of checking handlers.");
1631	STAM_REG(pVM, &pPGM->StatRZTrap0eTime2CSAM, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time2/CSAM", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is CSAM.");
1632	STAM_REG(pVM, &pPGM->StatRZTrap0eTime2DirtyAndAccessed, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time2/DirtyAndAccessedBits", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is dirty and/or accessed bit emulation.");
1633	STAM_REG(pVM, &pPGM->StatRZTrap0eTime2GuestTrap, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time2/GuestTrap", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is a guest trap.");
1634	STAM_REG(pVM, &pPGM->StatRZTrap0eTime2HndPhys, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time2/HandlerPhysical", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is a physical handler.");
1635	STAM_REG(pVM, &pPGM->StatRZTrap0eTime2HndVirt, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time2/HandlerVirtual", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is a virtual handler.");
1636	STAM_REG(pVM, &pPGM->StatRZTrap0eTime2HndUnhandled, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time2/HandlerUnhandled", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is access outside the monitored areas of a monitored page.");
1637	STAM_REG(pVM, &pPGM->StatRZTrap0eTime2Misc, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time2/Misc", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is not known.");
1638	STAM_REG(pVM, &pPGM->StatRZTrap0eTime2OutOfSync, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time2/OutOfSync", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is an out-of-sync page.");
1639	STAM_REG(pVM, &pPGM->StatRZTrap0eTime2OutOfSyncHndPhys, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time2/OutOfSyncHndPhys", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is an out-of-sync physical handler page.");
1640	STAM_REG(pVM, &pPGM->StatRZTrap0eTime2OutOfSyncHndVirt, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time2/OutOfSyncHndVirt", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is an out-of-sync virtual handler page.");
1641	STAM_REG(pVM, &pPGM->StatRZTrap0eTime2OutOfSyncHndObs, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time2/OutOfSyncObsHnd", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is an obsolete handler page.");
1642	STAM_REG(pVM, &pPGM->StatRZTrap0eTime2SyncPT, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time2/SyncPT", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is lazy syncing of a PT.");
1643	STAM_REG(pVM, &pPGM->StatRZTrap0eConflicts, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Conflicts", STAMUNIT_OCCURENCES, "The number of times #PF was caused by an undetected conflict.");
1644	STAM_REG(pVM, &pPGM->StatRZTrap0eHandlersMapping, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Handlers/Mapping", STAMUNIT_OCCURENCES, "Number of traps due to access handlers in mappings.");
1645	STAM_REG(pVM, &pPGM->StatRZTrap0eHandlersOutOfSync, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Handlers/OutOfSync", STAMUNIT_OCCURENCES, "Number of traps due to out-of-sync handled pages.");
1646	STAM_REG(pVM, &pPGM->StatRZTrap0eHandlersPhysical, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Handlers/Physical", STAMUNIT_OCCURENCES, "Number of traps due to physical access handlers.");
1647	STAM_REG(pVM, &pPGM->StatRZTrap0eHandlersVirtual, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Handlers/Virtual", STAMUNIT_OCCURENCES, "Number of traps due to virtual access handlers.");
1648	STAM_REG(pVM, &pPGM->StatRZTrap0eHandlersVirtualByPhys, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Handlers/VirtualByPhys", STAMUNIT_OCCURENCES, "Number of traps due to virtual access handlers by physical address.");
1649	STAM_REG(pVM, &pPGM->StatRZTrap0eHandlersVirtualUnmarked,STAMTYPE_COUNTER,"/PGM/RZ/Trap0e/Handlers/VirtualUnmarked",STAMUNIT_OCCURENCES, "Number of traps due to virtual access handlers by virtual address (without proper physical flags).");
1650	STAM_REG(pVM, &pPGM->StatRZTrap0eHandlersUnhandled, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Handlers/Unhandled", STAMUNIT_OCCURENCES, "Number of traps due to access outside range of monitored page(s).");
1651	STAM_REG(pVM, &pPGM->StatRZTrap0eHandlersInvalid, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Handlers/Invalid", STAMUNIT_OCCURENCES, "Number of traps due to access to invalid physical memory.");
1652	STAM_REG(pVM, &pPGM->StatRZTrap0eUSNotPresentRead, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Err/User/NPRead", STAMUNIT_OCCURENCES, "Number of user mode not present read page faults.");
1653	STAM_REG(pVM, &pPGM->StatRZTrap0eUSNotPresentWrite, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Err/User/NPWrite", STAMUNIT_OCCURENCES, "Number of user mode not present write page faults.");
1654	STAM_REG(pVM, &pPGM->StatRZTrap0eUSWrite, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Err/User/Write", STAMUNIT_OCCURENCES, "Number of user mode write page faults.");
1655	STAM_REG(pVM, &pPGM->StatRZTrap0eUSReserved, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Err/User/Reserved", STAMUNIT_OCCURENCES, "Number of user mode reserved bit page faults.");
1656	STAM_REG(pVM, &pPGM->StatRZTrap0eUSNXE, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Err/User/NXE", STAMUNIT_OCCURENCES, "Number of user mode NXE page faults.");
1657	STAM_REG(pVM, &pPGM->StatRZTrap0eUSRead, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Err/User/Read", STAMUNIT_OCCURENCES, "Number of user mode read page faults.");
1658	STAM_REG(pVM, &pPGM->StatRZTrap0eSVNotPresentRead, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Err/Supervisor/NPRead", STAMUNIT_OCCURENCES, "Number of supervisor mode not present read page faults.");
1659	STAM_REG(pVM, &pPGM->StatRZTrap0eSVNotPresentWrite, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Err/Supervisor/NPWrite", STAMUNIT_OCCURENCES, "Number of supervisor mode not present write page faults.");
1660	STAM_REG(pVM, &pPGM->StatRZTrap0eSVWrite, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Err/Supervisor/Write", STAMUNIT_OCCURENCES, "Number of supervisor mode write page faults.");
1661	STAM_REG(pVM, &pPGM->StatRZTrap0eSVReserved, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Err/Supervisor/Reserved", STAMUNIT_OCCURENCES, "Number of supervisor mode reserved bit page faults.");
1662	STAM_REG(pVM, &pPGM->StatRZTrap0eSNXE, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Err/Supervisor/NXE", STAMUNIT_OCCURENCES, "Number of supervisor mode NXE page faults.");
1663	STAM_REG(pVM, &pPGM->StatRZTrap0eGuestPF, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/GuestPF", STAMUNIT_OCCURENCES, "Number of real guest page faults.");
1664	STAM_REG(pVM, &pPGM->StatRZTrap0eGuestPFUnh, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/GuestPF/Unhandled", STAMUNIT_OCCURENCES, "Number of real guest page faults from the 'unhandled' case.");
1665	STAM_REG(pVM, &pPGM->StatRZTrap0eGuestPFMapping, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/GuestPF/InMapping", STAMUNIT_OCCURENCES, "Number of real guest page faults in a mapping.");
1666	STAM_REG(pVM, &pPGM->StatRZTrap0eWPEmulInRZ, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/WP/InRZ", STAMUNIT_OCCURENCES, "Number of guest page faults due to X86_CR0_WP emulation.");
1667	STAM_REG(pVM, &pPGM->StatRZTrap0eWPEmulToR3, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/WP/ToR3", STAMUNIT_OCCURENCES, "Number of guest page faults due to X86_CR0_WP emulation (forward to R3 for emulation).");
1668	for (i = 0; i < RT_ELEMENTS(pPGM->StatRZTrap0ePD); i++)
1669	STAMR3RegisterF(pVM, &pPGM->StatRZTrap0ePD[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
1670	"The number of traps in page directory n.", "/PGM/RZ/Trap0e/PD/%04X", i);
1671	STAM_REG(pVM, &pPGM->StatRZGuestCR3WriteHandled, STAMTYPE_COUNTER, "/PGM/RZ/CR3WriteHandled", STAMUNIT_OCCURENCES, "The number of times the Guest CR3 change was successfully handled.");
1672	STAM_REG(pVM, &pPGM->StatRZGuestCR3WriteUnhandled, STAMTYPE_COUNTER, "/PGM/RZ/CR3WriteUnhandled", STAMUNIT_OCCURENCES, "The number of times the Guest CR3 change was passed back to the recompiler.");
1673	STAM_REG(pVM, &pPGM->StatRZGuestCR3WriteConflict, STAMTYPE_COUNTER, "/PGM/RZ/CR3WriteConflict", STAMUNIT_OCCURENCES, "The number of times the Guest CR3 monitoring detected a conflict.");
1674	STAM_REG(pVM, &pPGM->StatRZGuestROMWriteHandled, STAMTYPE_COUNTER, "/PGM/RZ/ROMWriteHandled", STAMUNIT_OCCURENCES, "The number of times the Guest ROM change was successfully handled.");
1675	STAM_REG(pVM, &pPGM->StatRZGuestROMWriteUnhandled, STAMTYPE_COUNTER, "/PGM/RZ/ROMWriteUnhandled", STAMUNIT_OCCURENCES, "The number of times the Guest ROM change was passed back to the recompiler.");
1676
1677	/* HC only: */
1678
1679	/* RZ & R3: */
1680	STAM_REG(pVM, &pPGM->StatRZSyncCR3, STAMTYPE_PROFILE, "/PGM/RZ/SyncCR3", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMSyncCR3() body.");
1681	STAM_REG(pVM, &pPGM->StatRZSyncCR3Handlers, STAMTYPE_PROFILE, "/PGM/RZ/SyncCR3/Handlers", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMSyncCR3() update handler section.");
1682	STAM_REG(pVM, &pPGM->StatRZSyncCR3HandlerVirtualUpdate, STAMTYPE_PROFILE, "/PGM/RZ/SyncCR3/Handlers/VirtualUpdate", STAMUNIT_TICKS_PER_CALL, "Profiling of the virtual handler updates.");
1683	STAM_REG(pVM, &pPGM->StatRZSyncCR3HandlerVirtualReset, STAMTYPE_PROFILE, "/PGM/RZ/SyncCR3/Handlers/VirtualReset", STAMUNIT_TICKS_PER_CALL, "Profiling of the virtual handler resets.");
1684	STAM_REG(pVM, &pPGM->StatRZSyncCR3Global, STAMTYPE_COUNTER, "/PGM/RZ/SyncCR3/Global", STAMUNIT_OCCURENCES, "The number of global CR3 syncs.");
1685	STAM_REG(pVM, &pPGM->StatRZSyncCR3NotGlobal, STAMTYPE_COUNTER, "/PGM/RZ/SyncCR3/NotGlobal", STAMUNIT_OCCURENCES, "The number of non-global CR3 syncs.");
1686	STAM_REG(pVM, &pPGM->StatRZSyncCR3DstCacheHit, STAMTYPE_COUNTER, "/PGM/RZ/SyncCR3/DstChacheHit", STAMUNIT_OCCURENCES, "The number of times we got some kind of a cache hit.");
1687	STAM_REG(pVM, &pPGM->StatRZSyncCR3DstFreed, STAMTYPE_COUNTER, "/PGM/RZ/SyncCR3/DstFreed", STAMUNIT_OCCURENCES, "The number of times we've had to free a shadow entry.");
1688	STAM_REG(pVM, &pPGM->StatRZSyncCR3DstFreedSrcNP, STAMTYPE_COUNTER, "/PGM/RZ/SyncCR3/DstFreedSrcNP", STAMUNIT_OCCURENCES, "The number of times we've had to free a shadow entry for which the source entry was not present.");
1689	STAM_REG(pVM, &pPGM->StatRZSyncCR3DstNotPresent, STAMTYPE_COUNTER, "/PGM/RZ/SyncCR3/DstNotPresent", STAMUNIT_OCCURENCES, "The number of times we've encountered a not present shadow entry for a present guest entry.");
1690	STAM_REG(pVM, &pPGM->StatRZSyncCR3DstSkippedGlobalPD, STAMTYPE_COUNTER, "/PGM/RZ/SyncCR3/DstSkippedGlobalPD", STAMUNIT_OCCURENCES, "The number of times a global page directory wasn't flushed.");
1691	STAM_REG(pVM, &pPGM->StatRZSyncCR3DstSkippedGlobalPT, STAMTYPE_COUNTER, "/PGM/RZ/SyncCR3/DstSkippedGlobalPT", STAMUNIT_OCCURENCES, "The number of times a page table with only global entries wasn't flushed.");
1692	STAM_REG(pVM, &pPGM->StatRZSyncPT, STAMTYPE_PROFILE, "/PGM/RZ/SyncPT", STAMUNIT_TICKS_PER_CALL, "Profiling of the pfnSyncPT() body.");
1693	STAM_REG(pVM, &pPGM->StatRZSyncPTFailed, STAMTYPE_COUNTER, "/PGM/RZ/SyncPT/Failed", STAMUNIT_OCCURENCES, "The number of times pfnSyncPT() failed.");
1694	STAM_REG(pVM, &pPGM->StatRZSyncPT4K, STAMTYPE_COUNTER, "/PGM/RZ/SyncPT/4K", STAMUNIT_OCCURENCES, "Nr of 4K PT syncs");
1695	STAM_REG(pVM, &pPGM->StatRZSyncPT4M, STAMTYPE_COUNTER, "/PGM/RZ/SyncPT/4M", STAMUNIT_OCCURENCES, "Nr of 4M PT syncs");
1696	STAM_REG(pVM, &pPGM->StatRZSyncPagePDNAs, STAMTYPE_COUNTER, "/PGM/RZ/SyncPagePDNAs", STAMUNIT_OCCURENCES, "The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit.");
1697	STAM_REG(pVM, &pPGM->StatRZSyncPagePDOutOfSync, STAMTYPE_COUNTER, "/PGM/RZ/SyncPagePDOutOfSync", STAMUNIT_OCCURENCES, "The number of time we've encountered an out-of-sync PD in SyncPage.");
1698	STAM_REG(pVM, &pPGM->StatRZAccessedPage, STAMTYPE_COUNTER, "/PGM/RZ/AccessedPage", STAMUNIT_OCCURENCES, "The number of pages marked not present for accessed bit emulation.");
1699	STAM_REG(pVM, &pPGM->StatRZDirtyBitTracking, STAMTYPE_PROFILE, "/PGM/RZ/DirtyPage", STAMUNIT_TICKS_PER_CALL, "Profiling the dirty bit tracking in CheckPageFault().");
1700	STAM_REG(pVM, &pPGM->StatRZDirtyPage, STAMTYPE_COUNTER, "/PGM/RZ/DirtyPage/Mark", STAMUNIT_OCCURENCES, "The number of pages marked read-only for dirty bit tracking.");
1701	STAM_REG(pVM, &pPGM->StatRZDirtyPageBig, STAMTYPE_COUNTER, "/PGM/RZ/DirtyPage/MarkBig", STAMUNIT_OCCURENCES, "The number of 4MB pages marked read-only for dirty bit tracking.");
1702	STAM_REG(pVM, &pPGM->StatRZDirtyPageSkipped, STAMTYPE_COUNTER, "/PGM/RZ/DirtyPage/Skipped", STAMUNIT_OCCURENCES, "The number of pages already dirty or readonly.");
1703	STAM_REG(pVM, &pPGM->StatRZDirtyPageTrap, STAMTYPE_COUNTER, "/PGM/RZ/DirtyPage/Trap", STAMUNIT_OCCURENCES, "The number of traps generated for dirty bit tracking.");
1704	STAM_REG(pVM, &pPGM->StatRZDirtiedPage, STAMTYPE_COUNTER, "/PGM/RZ/DirtyPage/SetDirty", STAMUNIT_OCCURENCES, "The number of pages marked dirty because of write accesses.");
1705	STAM_REG(pVM, &pPGM->StatRZDirtyTrackRealPF, STAMTYPE_COUNTER, "/PGM/RZ/DirtyPage/RealPF", STAMUNIT_OCCURENCES, "The number of real pages faults during dirty bit tracking.");
1706	STAM_REG(pVM, &pPGM->StatRZPageAlreadyDirty, STAMTYPE_COUNTER, "/PGM/RZ/DirtyPage/AlreadySet", STAMUNIT_OCCURENCES, "The number of pages already marked dirty because of write accesses.");
1707	STAM_REG(pVM, &pPGM->StatRZInvalidatePage, STAMTYPE_PROFILE, "/PGM/RZ/InvalidatePage", STAMUNIT_TICKS_PER_CALL, "PGMInvalidatePage() profiling.");
1708	STAM_REG(pVM, &pPGM->StatRZInvalidatePage4KBPages, STAMTYPE_COUNTER, "/PGM/RZ/InvalidatePage/4KBPages", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was called for a 4KB page.");
1709	STAM_REG(pVM, &pPGM->StatRZInvalidatePage4MBPages, STAMTYPE_COUNTER, "/PGM/RZ/InvalidatePage/4MBPages", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was called for a 4MB page.");
1710	STAM_REG(pVM, &pPGM->StatRZInvalidatePage4MBPagesSkip, STAMTYPE_COUNTER, "/PGM/RZ/InvalidatePage/4MBPagesSkip",STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() skipped a 4MB page.");
1711	STAM_REG(pVM, &pPGM->StatRZInvalidatePagePDMappings, STAMTYPE_COUNTER, "/PGM/RZ/InvalidatePage/PDMappings", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict).");
1712	STAM_REG(pVM, &pPGM->StatRZInvalidatePagePDNAs, STAMTYPE_COUNTER, "/PGM/RZ/InvalidatePage/PDNAs", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was called for a not accessed page directory.");
1713	STAM_REG(pVM, &pPGM->StatRZInvalidatePagePDNPs, STAMTYPE_COUNTER, "/PGM/RZ/InvalidatePage/PDNPs", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was called for a not present page directory.");
1714	STAM_REG(pVM, &pPGM->StatRZInvalidatePagePDOutOfSync, STAMTYPE_COUNTER, "/PGM/RZ/InvalidatePage/PDOutOfSync", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was called for an out of sync page directory.");
1715	STAM_REG(pVM, &pPGM->StatRZInvalidatePageSkipped, STAMTYPE_COUNTER, "/PGM/RZ/InvalidatePage/Skipped", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3.");
1716	STAM_REG(pVM, &pPGM->StatRZVirtHandlerSearchByPhys, STAMTYPE_PROFILE, "/PGM/RZ/VirtHandlerSearchByPhys", STAMUNIT_TICKS_PER_CALL, "Profiling of pgmHandlerVirtualFindByPhysAddr.");
1717	STAM_REG(pVM, &pPGM->StatRZPhysHandlerReset, STAMTYPE_COUNTER, "/PGM/RZ/PhysHandlerReset", STAMUNIT_OCCURENCES, "The number of times PGMHandlerPhysicalReset is called.");
1718	STAM_REG(pVM, &pPGM->StatRZPageOutOfSyncSupervisor, STAMTYPE_COUNTER, "/PGM/RZ/OutOfSync/SuperVisor", STAMUNIT_OCCURENCES, "Number of traps due to pages out of sync and times VerifyAccessSyncPage calls SyncPage.");
1719	STAM_REG(pVM, &pPGM->StatRZPageOutOfSyncUser, STAMTYPE_COUNTER, "/PGM/RZ/OutOfSync/User", STAMUNIT_OCCURENCES, "Number of traps due to pages out of sync and times VerifyAccessSyncPage calls SyncPage.");
1720	STAM_REG(pVM, &pPGM->StatRZPrefetch, STAMTYPE_PROFILE, "/PGM/RZ/Prefetch", STAMUNIT_TICKS_PER_CALL, "PGMPrefetchPage profiling.");
1721	STAM_REG(pVM, &pPGM->StatRZChunkR3MapTlbHits, STAMTYPE_COUNTER, "/PGM/ChunkR3Map/TlbHitsRZ", STAMUNIT_OCCURENCES, "TLB hits.");
1722	STAM_REG(pVM, &pPGM->StatRZChunkR3MapTlbMisses, STAMTYPE_COUNTER, "/PGM/ChunkR3Map/TlbMissesRZ", STAMUNIT_OCCURENCES, "TLB misses.");
1723	STAM_REG(pVM, &pPGM->StatRZPageMapTlbHits, STAMTYPE_COUNTER, "/PGM/RZ/Page/MapTlbHits", STAMUNIT_OCCURENCES, "TLB hits.");
1724	STAM_REG(pVM, &pPGM->StatRZPageMapTlbMisses, STAMTYPE_COUNTER, "/PGM/RZ/Page/MapTlbMisses", STAMUNIT_OCCURENCES, "TLB misses.");
1725	STAM_REG(pVM, &pPGM->StatRZPageReplaceShared, STAMTYPE_COUNTER, "/PGM/RZ/Page/ReplacedShared", STAMUNIT_OCCURENCES, "Times a shared page was replaced.");
1726	STAM_REG(pVM, &pPGM->StatRZPageReplaceZero, STAMTYPE_COUNTER, "/PGM/RZ/Page/ReplacedZero", STAMUNIT_OCCURENCES, "Times the zero page was replaced.");
1727	/// @todo STAM_REG(pVM, &pPGM->StatRZPageHandyAllocs, STAMTYPE_COUNTER, "/PGM/RZ/Page/HandyAllocs", STAMUNIT_OCCURENCES, "Number of times we've allocated more handy pages.");
1728	STAM_REG(pVM, &pPGM->StatRZFlushTLB, STAMTYPE_PROFILE, "/PGM/RZ/FlushTLB", STAMUNIT_OCCURENCES, "Profiling of the PGMFlushTLB() body.");
1729	STAM_REG(pVM, &pPGM->StatRZFlushTLBNewCR3, STAMTYPE_COUNTER, "/PGM/RZ/FlushTLB/NewCR3", STAMUNIT_OCCURENCES, "The number of times PGMFlushTLB was called with a new CR3, non-global. (switch)");
1730	STAM_REG(pVM, &pPGM->StatRZFlushTLBNewCR3Global, STAMTYPE_COUNTER, "/PGM/RZ/FlushTLB/NewCR3Global", STAMUNIT_OCCURENCES, "The number of times PGMFlushTLB was called with a new CR3, global. (switch)");
1731	STAM_REG(pVM, &pPGM->StatRZFlushTLBSameCR3, STAMTYPE_COUNTER, "/PGM/RZ/FlushTLB/SameCR3", STAMUNIT_OCCURENCES, "The number of times PGMFlushTLB was called with the same CR3, non-global. (flush)");
1732	STAM_REG(pVM, &pPGM->StatRZFlushTLBSameCR3Global, STAMTYPE_COUNTER, "/PGM/RZ/FlushTLB/SameCR3Global", STAMUNIT_OCCURENCES, "The number of times PGMFlushTLB was called with the same CR3, global. (flush)");
1733	STAM_REG(pVM, &pPGM->StatRZGstModifyPage, STAMTYPE_PROFILE, "/PGM/RZ/GstModifyPage", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMGstModifyPage() body.");
1734
1735	STAM_REG(pVM, &pPGM->StatR3SyncCR3, STAMTYPE_PROFILE, "/PGM/R3/SyncCR3", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMSyncCR3() body.");
1736	STAM_REG(pVM, &pPGM->StatR3SyncCR3Handlers, STAMTYPE_PROFILE, "/PGM/R3/SyncCR3/Handlers", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMSyncCR3() update handler section.");
1737	STAM_REG(pVM, &pPGM->StatR3SyncCR3HandlerVirtualUpdate, STAMTYPE_PROFILE, "/PGM/R3/SyncCR3/Handlers/VirtualUpdate", STAMUNIT_TICKS_PER_CALL, "Profiling of the virtual handler updates.");
1738	STAM_REG(pVM, &pPGM->StatR3SyncCR3HandlerVirtualReset, STAMTYPE_PROFILE, "/PGM/R3/SyncCR3/Handlers/VirtualReset", STAMUNIT_TICKS_PER_CALL, "Profiling of the virtual handler resets.");
1739	STAM_REG(pVM, &pPGM->StatR3SyncCR3Global, STAMTYPE_COUNTER, "/PGM/R3/SyncCR3/Global", STAMUNIT_OCCURENCES, "The number of global CR3 syncs.");
1740	STAM_REG(pVM, &pPGM->StatR3SyncCR3NotGlobal, STAMTYPE_COUNTER, "/PGM/R3/SyncCR3/NotGlobal", STAMUNIT_OCCURENCES, "The number of non-global CR3 syncs.");
1741	STAM_REG(pVM, &pPGM->StatR3SyncCR3DstCacheHit, STAMTYPE_COUNTER, "/PGM/R3/SyncCR3/DstChacheHit", STAMUNIT_OCCURENCES, "The number of times we got some kind of a cache hit.");
1742	STAM_REG(pVM, &pPGM->StatR3SyncCR3DstFreed, STAMTYPE_COUNTER, "/PGM/R3/SyncCR3/DstFreed", STAMUNIT_OCCURENCES, "The number of times we've had to free a shadow entry.");
1743	STAM_REG(pVM, &pPGM->StatR3SyncCR3DstFreedSrcNP, STAMTYPE_COUNTER, "/PGM/R3/SyncCR3/DstFreedSrcNP", STAMUNIT_OCCURENCES, "The number of times we've had to free a shadow entry for which the source entry was not present.");
1744	STAM_REG(pVM, &pPGM->StatR3SyncCR3DstNotPresent, STAMTYPE_COUNTER, "/PGM/R3/SyncCR3/DstNotPresent", STAMUNIT_OCCURENCES, "The number of times we've encountered a not present shadow entry for a present guest entry.");
1745	STAM_REG(pVM, &pPGM->StatR3SyncCR3DstSkippedGlobalPD, STAMTYPE_COUNTER, "/PGM/R3/SyncCR3/DstSkippedGlobalPD", STAMUNIT_OCCURENCES, "The number of times a global page directory wasn't flushed.");
1746	STAM_REG(pVM, &pPGM->StatR3SyncCR3DstSkippedGlobalPT, STAMTYPE_COUNTER, "/PGM/R3/SyncCR3/DstSkippedGlobalPT", STAMUNIT_OCCURENCES, "The number of times a page table with only global entries wasn't flushed.");
1747	STAM_REG(pVM, &pPGM->StatR3SyncPT, STAMTYPE_PROFILE, "/PGM/R3/SyncPT", STAMUNIT_TICKS_PER_CALL, "Profiling of the pfnSyncPT() body.");
1748	STAM_REG(pVM, &pPGM->StatR3SyncPTFailed, STAMTYPE_COUNTER, "/PGM/R3/SyncPT/Failed", STAMUNIT_OCCURENCES, "The number of times pfnSyncPT() failed.");
1749	STAM_REG(pVM, &pPGM->StatR3SyncPT4K, STAMTYPE_COUNTER, "/PGM/R3/SyncPT/4K", STAMUNIT_OCCURENCES, "Nr of 4K PT syncs");
1750	STAM_REG(pVM, &pPGM->StatR3SyncPT4M, STAMTYPE_COUNTER, "/PGM/R3/SyncPT/4M", STAMUNIT_OCCURENCES, "Nr of 4M PT syncs");
1751	STAM_REG(pVM, &pPGM->StatR3SyncPagePDNAs, STAMTYPE_COUNTER, "/PGM/R3/SyncPagePDNAs", STAMUNIT_OCCURENCES, "The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit.");
1752	STAM_REG(pVM, &pPGM->StatR3SyncPagePDOutOfSync, STAMTYPE_COUNTER, "/PGM/R3/SyncPagePDOutOfSync", STAMUNIT_OCCURENCES, "The number of time we've encountered an out-of-sync PD in SyncPage.");
1753	STAM_REG(pVM, &pPGM->StatR3AccessedPage, STAMTYPE_COUNTER, "/PGM/R3/AccessedPage", STAMUNIT_OCCURENCES, "The number of pages marked not present for accessed bit emulation.");
1754	STAM_REG(pVM, &pPGM->StatR3DirtyBitTracking, STAMTYPE_PROFILE, "/PGM/R3/DirtyPage", STAMUNIT_TICKS_PER_CALL, "Profiling the dirty bit tracking in CheckPageFault().");
1755	STAM_REG(pVM, &pPGM->StatR3DirtyPage, STAMTYPE_COUNTER, "/PGM/R3/DirtyPage/Mark", STAMUNIT_OCCURENCES, "The number of pages marked read-only for dirty bit tracking.");
1756	STAM_REG(pVM, &pPGM->StatR3DirtyPageBig, STAMTYPE_COUNTER, "/PGM/R3/DirtyPage/MarkBig", STAMUNIT_OCCURENCES, "The number of 4MB pages marked read-only for dirty bit tracking.");
1757	STAM_REG(pVM, &pPGM->StatR3DirtyPageSkipped, STAMTYPE_COUNTER, "/PGM/R3/DirtyPage/Skipped", STAMUNIT_OCCURENCES, "The number of pages already dirty or readonly.");
1758	STAM_REG(pVM, &pPGM->StatR3DirtyPageTrap, STAMTYPE_COUNTER, "/PGM/R3/DirtyPage/Trap", STAMUNIT_OCCURENCES, "The number of traps generated for dirty bit tracking.");
1759	STAM_REG(pVM, &pPGM->StatR3DirtiedPage, STAMTYPE_COUNTER, "/PGM/R3/DirtyPage/SetDirty", STAMUNIT_OCCURENCES, "The number of pages marked dirty because of write accesses.");
1760	STAM_REG(pVM, &pPGM->StatR3DirtyTrackRealPF, STAMTYPE_COUNTER, "/PGM/R3/DirtyPage/RealPF", STAMUNIT_OCCURENCES, "The number of real pages faults during dirty bit tracking.");
1761	STAM_REG(pVM, &pPGM->StatR3PageAlreadyDirty, STAMTYPE_COUNTER, "/PGM/R3/DirtyPage/AlreadySet", STAMUNIT_OCCURENCES, "The number of pages already marked dirty because of write accesses.");
1762	STAM_REG(pVM, &pPGM->StatR3InvalidatePage, STAMTYPE_PROFILE, "/PGM/R3/InvalidatePage", STAMUNIT_TICKS_PER_CALL, "PGMInvalidatePage() profiling.");
1763	STAM_REG(pVM, &pPGM->StatR3InvalidatePage4KBPages, STAMTYPE_COUNTER, "/PGM/R3/InvalidatePage/4KBPages", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was called for a 4KB page.");
1764	STAM_REG(pVM, &pPGM->StatR3InvalidatePage4MBPages, STAMTYPE_COUNTER, "/PGM/R3/InvalidatePage/4MBPages", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was called for a 4MB page.");
1765	STAM_REG(pVM, &pPGM->StatR3InvalidatePage4MBPagesSkip, STAMTYPE_COUNTER, "/PGM/R3/InvalidatePage/4MBPagesSkip",STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() skipped a 4MB page.");
1766	STAM_REG(pVM, &pPGM->StatR3InvalidatePagePDMappings, STAMTYPE_COUNTER, "/PGM/R3/InvalidatePage/PDMappings", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict).");
1767	STAM_REG(pVM, &pPGM->StatR3InvalidatePagePDNAs, STAMTYPE_COUNTER, "/PGM/R3/InvalidatePage/PDNAs", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was called for a not accessed page directory.");
1768	STAM_REG(pVM, &pPGM->StatR3InvalidatePagePDNPs, STAMTYPE_COUNTER, "/PGM/R3/InvalidatePage/PDNPs", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was called for a not present page directory.");
1769	STAM_REG(pVM, &pPGM->StatR3InvalidatePagePDOutOfSync, STAMTYPE_COUNTER, "/PGM/R3/InvalidatePage/PDOutOfSync", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was called for an out of sync page directory.");
1770	STAM_REG(pVM, &pPGM->StatR3InvalidatePageSkipped, STAMTYPE_COUNTER, "/PGM/R3/InvalidatePage/Skipped", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3.");
1771	STAM_REG(pVM, &pPGM->StatR3VirtHandlerSearchByPhys, STAMTYPE_PROFILE, "/PGM/R3/VirtHandlerSearchByPhys", STAMUNIT_TICKS_PER_CALL, "Profiling of pgmHandlerVirtualFindByPhysAddr.");
1772	STAM_REG(pVM, &pPGM->StatR3PhysHandlerReset, STAMTYPE_COUNTER, "/PGM/R3/PhysHandlerReset", STAMUNIT_OCCURENCES, "The number of times PGMHandlerPhysicalReset is called.");
1773	STAM_REG(pVM, &pPGM->StatR3PageOutOfSyncSupervisor, STAMTYPE_COUNTER, "/PGM/R3/OutOfSync/SuperVisor", STAMUNIT_OCCURENCES, "Number of traps due to pages out of sync and times VerifyAccessSyncPage calls SyncPage.");
1774	STAM_REG(pVM, &pPGM->StatR3PageOutOfSyncUser, STAMTYPE_COUNTER, "/PGM/R3/OutOfSync/User", STAMUNIT_OCCURENCES, "Number of traps due to pages out of sync and times VerifyAccessSyncPage calls SyncPage.");
1775	STAM_REG(pVM, &pPGM->StatR3Prefetch, STAMTYPE_PROFILE, "/PGM/R3/Prefetch", STAMUNIT_TICKS_PER_CALL, "PGMPrefetchPage profiling.");
1776	STAM_REG(pVM, &pPGM->StatR3ChunkR3MapTlbHits, STAMTYPE_COUNTER, "/PGM/ChunkR3Map/TlbHitsR3", STAMUNIT_OCCURENCES, "TLB hits.");
1777	STAM_REG(pVM, &pPGM->StatR3ChunkR3MapTlbMisses, STAMTYPE_COUNTER, "/PGM/ChunkR3Map/TlbMissesR3", STAMUNIT_OCCURENCES, "TLB misses.");
1778	STAM_REG(pVM, &pPGM->StatR3PageMapTlbHits, STAMTYPE_COUNTER, "/PGM/R3/Page/MapTlbHits", STAMUNIT_OCCURENCES, "TLB hits.");
1779	STAM_REG(pVM, &pPGM->StatR3PageMapTlbMisses, STAMTYPE_COUNTER, "/PGM/R3/Page/MapTlbMisses", STAMUNIT_OCCURENCES, "TLB misses.");
1780	STAM_REG(pVM, &pPGM->StatR3PageReplaceShared, STAMTYPE_COUNTER, "/PGM/R3/Page/ReplacedShared", STAMUNIT_OCCURENCES, "Times a shared page was replaced.");
1781	STAM_REG(pVM, &pPGM->StatR3PageReplaceZero, STAMTYPE_COUNTER, "/PGM/R3/Page/ReplacedZero", STAMUNIT_OCCURENCES, "Times the zero page was replaced.");
1782	/// @todo STAM_REG(pVM, &pPGM->StatR3PageHandyAllocs, STAMTYPE_COUNTER, "/PGM/R3/Page/HandyAllocs", STAMUNIT_OCCURENCES, "Number of times we've allocated more handy pages.");
1783	STAM_REG(pVM, &pPGM->StatR3FlushTLB, STAMTYPE_PROFILE, "/PGM/R3/FlushTLB", STAMUNIT_OCCURENCES, "Profiling of the PGMFlushTLB() body.");
1784	STAM_REG(pVM, &pPGM->StatR3FlushTLBNewCR3, STAMTYPE_COUNTER, "/PGM/R3/FlushTLB/NewCR3", STAMUNIT_OCCURENCES, "The number of times PGMFlushTLB was called with a new CR3, non-global. (switch)");
1785	STAM_REG(pVM, &pPGM->StatR3FlushTLBNewCR3Global, STAMTYPE_COUNTER, "/PGM/R3/FlushTLB/NewCR3Global", STAMUNIT_OCCURENCES, "The number of times PGMFlushTLB was called with a new CR3, global. (switch)");
1786	STAM_REG(pVM, &pPGM->StatR3FlushTLBSameCR3, STAMTYPE_COUNTER, "/PGM/R3/FlushTLB/SameCR3", STAMUNIT_OCCURENCES, "The number of times PGMFlushTLB was called with the same CR3, non-global. (flush)");
1787	STAM_REG(pVM, &pPGM->StatR3FlushTLBSameCR3Global, STAMTYPE_COUNTER, "/PGM/R3/FlushTLB/SameCR3Global", STAMUNIT_OCCURENCES, "The number of times PGMFlushTLB was called with the same CR3, global. (flush)");
1788	STAM_REG(pVM, &pPGM->StatR3GstModifyPage, STAMTYPE_PROFILE, "/PGM/R3/GstModifyPage", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMGstModifyPage() body.");
1789
1790	}
1791	#endif /* VBOX_WITH_STATISTICS */
1792
1793
1794	/**
1795	* Init the PGM bits that rely on VMMR0 and MM to be fully initialized.
1796	*
1797	* The dynamic mapping area will also be allocated and initialized at this
1798	* time. We could allocate it during PGMR3Init of course, but the mapping
1799	* wouldn't be allocated at that time preventing us from setting up the
1800	* page table entries with the dummy page.
1801	*
1802	* @returns VBox status code.
1803	* @param pVM VM handle.
1804	*/
1805	VMMR3DECL(int) PGMR3InitDynMap(PVM pVM)
1806	{
1807	RTGCPTR GCPtr;
1808	int rc;
1809
1810	/*
1811	* Reserve space for the dynamic mappings.
1812	*/
1813	rc = MMR3HyperReserve(pVM, MM_HYPER_DYNAMIC_SIZE, "Dynamic mapping", &GCPtr);
1814	if (RT_SUCCESS(rc))
1815	pVM->pgm.s.pbDynPageMapBaseGC = GCPtr;
1816
1817	if ( RT_SUCCESS(rc)
1818	&& (pVM->pgm.s.pbDynPageMapBaseGC >> X86_PD_PAE_SHIFT) != ((pVM->pgm.s.pbDynPageMapBaseGC + MM_HYPER_DYNAMIC_SIZE - 1) >> X86_PD_PAE_SHIFT))
1819	{
1820	rc = MMR3HyperReserve(pVM, MM_HYPER_DYNAMIC_SIZE, "Dynamic mapping not crossing", &GCPtr);
1821	if (RT_SUCCESS(rc))
1822	pVM->pgm.s.pbDynPageMapBaseGC = GCPtr;
1823	}
1824	if (RT_SUCCESS(rc))
1825	{
1826	AssertRelease((pVM->pgm.s.pbDynPageMapBaseGC >> X86_PD_PAE_SHIFT) == ((pVM->pgm.s.pbDynPageMapBaseGC + MM_HYPER_DYNAMIC_SIZE - 1) >> X86_PD_PAE_SHIFT));
1827	MMR3HyperReserve(pVM, PAGE_SIZE, "fence", NULL);
1828	}
1829	return rc;
1830	}
1831
1832
1833	/**
1834	* Ring-3 init finalizing.
1835	*
1836	* @returns VBox status code.
1837	* @param pVM The VM handle.
1838	*/
1839	VMMR3DECL(int) PGMR3InitFinalize(PVM pVM)
1840	{
1841	int rc;
1842
1843	/*
1844	* Reserve space for the dynamic mappings.
1845	* Initialize the dynamic mapping pages with dummy pages to simply the cache.
1846	*/
1847	/* get the pointer to the page table entries. */
1848	PPGMMAPPING pMapping = pgmGetMapping(pVM, pVM->pgm.s.pbDynPageMapBaseGC);
1849	AssertRelease(pMapping);
1850	const uintptr_t off = pVM->pgm.s.pbDynPageMapBaseGC - pMapping->GCPtr;
1851	const unsigned iPT = off >> X86_PD_SHIFT;
1852	const unsigned iPG = (off >> X86_PT_SHIFT) & X86_PT_MASK;
1853	pVM->pgm.s.paDynPageMap32BitPTEsGC = pMapping->aPTs[iPT].pPTRC + iPG * sizeof(pMapping->aPTs[0].pPTR3->a[0]);
1854	pVM->pgm.s.paDynPageMapPaePTEsGC = pMapping->aPTs[iPT].paPaePTsRC + iPG * sizeof(pMapping->aPTs[0].paPaePTsR3->a[0]);
1855
1856	/* init cache */
1857	RTHCPHYS HCPhysDummy = MMR3PageDummyHCPhys(pVM);
1858	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.aHCPhysDynPageMapCache); i++)
1859	pVM->pgm.s.aHCPhysDynPageMapCache[i] = HCPhysDummy;
1860
1861	for (unsigned i = 0; i < MM_HYPER_DYNAMIC_SIZE; i += PAGE_SIZE)
1862	{
1863	rc = PGMMap(pVM, pVM->pgm.s.pbDynPageMapBaseGC + i, HCPhysDummy, PAGE_SIZE, 0);
1864	AssertRCReturn(rc, rc);
1865	}
1866
1867	/*
1868	* Note that AMD uses all the 8 reserved bits for the address (so 40 bits in total);
1869	* Intel only goes up to 36 bits, so we stick to 36 as well.
1870	*/
1871	/** @todo How to test for the 40 bits support? Long mode seems to be the test criterium. */
1872	uint32_t u32Dummy, u32Features;
1873	CPUMGetGuestCpuId(pVM, 1, &u32Dummy, &u32Dummy, &u32Dummy, &u32Features);
1874
1875	if (u32Features & X86_CPUID_FEATURE_EDX_PSE36)
1876	pVM->pgm.s.GCPhys4MBPSEMask = RT_BIT_64(36) - 1;
1877	else
1878	pVM->pgm.s.GCPhys4MBPSEMask = RT_BIT_64(32) - 1;
1879
1880	LogRel(("PGMR3InitFinalize: 4 MB PSE mask %RGp\n", pVM->pgm.s.GCPhys4MBPSEMask));
1881	return rc;
1882	}
1883
1884
1885	/**
1886	* Applies relocations to data and code managed by this component.
1887	*
1888	* This function will be called at init and whenever the VMM need to relocate it
1889	* self inside the GC.
1890	*
1891	* @param pVM The VM.
1892	* @param offDelta Relocation delta relative to old location.
1893	*/
1894	VMMR3DECL(void) PGMR3Relocate(PVM pVM, RTGCINTPTR offDelta)
1895	{
1896	LogFlow(("PGMR3Relocate %RGv to %RGv\n", pVM->pgm.s.GCPtrCR3Mapping, pVM->pgm.s.GCPtrCR3Mapping + offDelta));
1897
1898	/*
1899	* Paging stuff.
1900	*/
1901	pVM->pgm.s.GCPtrCR3Mapping += offDelta;
1902	/** @todo move this into shadow and guest specific relocation functions. */
1903	pVM->pgm.s.pGst32BitPdRC += offDelta;
1904	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.apGstPaePDsRC); i++)
1905	{
1906	pVM->pgm.s.apGstPaePDsRC[i] += offDelta;
1907	}
1908	pVM->pgm.s.pGstPaePdptRC += offDelta;
1909
1910	pVM->pgm.s.pShwPageCR3RC += offDelta;
1911
1912	pgmR3ModeDataInit(pVM, true /* resolve GC/R0 symbols */);
1913	pgmR3ModeDataSwitch(pVM, pVM->pgm.s.enmShadowMode, pVM->pgm.s.enmGuestMode);
1914
1915	PGM_SHW_PFN(Relocate, pVM)(pVM, offDelta);
1916	PGM_GST_PFN(Relocate, pVM)(pVM, offDelta);
1917	PGM_BTH_PFN(Relocate, pVM)(pVM, offDelta);
1918
1919	/*
1920	* Trees.
1921	*/
1922	pVM->pgm.s.pTreesRC = MMHyperR3ToRC(pVM, pVM->pgm.s.pTreesR3);
1923
1924	/*
1925	* Ram ranges.
1926	*/
1927	if (pVM->pgm.s.pRamRangesR3)
1928	{
1929	/* Update the pSelfRC pointers and relink them. */
1930	for (PPGMRAMRANGE pCur = pVM->pgm.s.pRamRangesR3; pCur; pCur = pCur->pNextR3)
1931	if (!(pCur->fFlags & PGM_RAM_RANGE_FLAGS_FLOATING))
1932	pCur->pSelfRC = MMHyperCCToRC(pVM, pCur);
1933	pgmR3PhysRelinkRamRanges(pVM);
1934	}
1935
1936	/*
1937	* Update the two page directories with all page table mappings.
1938	* (One or more of them have changed, that's why we're here.)
1939	*/
1940	pVM->pgm.s.pMappingsRC = MMHyperR3ToRC(pVM, pVM->pgm.s.pMappingsR3);
1941	for (PPGMMAPPING pCur = pVM->pgm.s.pMappingsR3; pCur->pNextR3; pCur = pCur->pNextR3)
1942	pCur->pNextRC = MMHyperR3ToRC(pVM, pCur->pNextR3);
1943
1944	/* Relocate GC addresses of Page Tables. */
1945	for (PPGMMAPPING pCur = pVM->pgm.s.pMappingsR3; pCur; pCur = pCur->pNextR3)
1946	{
1947	for (RTHCUINT i = 0; i < pCur->cPTs; i++)
1948	{
1949	pCur->aPTs[i].pPTRC = MMHyperR3ToRC(pVM, pCur->aPTs[i].pPTR3);
1950	pCur->aPTs[i].paPaePTsRC = MMHyperR3ToRC(pVM, pCur->aPTs[i].paPaePTsR3);
1951	}
1952	}
1953
1954	/*
1955	* Dynamic page mapping area.
1956	*/
1957	pVM->pgm.s.paDynPageMap32BitPTEsGC += offDelta;
1958	pVM->pgm.s.paDynPageMapPaePTEsGC += offDelta;
1959	pVM->pgm.s.pbDynPageMapBaseGC += offDelta;
1960
1961	/*
1962	* The Zero page.
1963	*/
1964	pVM->pgm.s.pvZeroPgR0 = MMHyperR3ToR0(pVM, pVM->pgm.s.pvZeroPgR3);
1965	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1966	AssertRelease(pVM->pgm.s.pvZeroPgR0 != NIL_RTR0PTR \|\| !VMMIsHwVirtExtForced(pVM));
1967	#else
1968	AssertRelease(pVM->pgm.s.pvZeroPgR0 != NIL_RTR0PTR);
1969	#endif
1970
1971	/*
1972	* Physical and virtual handlers.
1973	*/
1974	RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysHandlers, true, pgmR3RelocatePhysHandler, &offDelta);
1975	RTAvlroGCPtrDoWithAll(&pVM->pgm.s.pTreesR3->VirtHandlers, true, pgmR3RelocateVirtHandler, &offDelta);
1976	RTAvlroGCPtrDoWithAll(&pVM->pgm.s.pTreesR3->HyperVirtHandlers, true, pgmR3RelocateHyperVirtHandler, &offDelta);
1977
1978	/*
1979	* The page pool.
1980	*/
1981	pgmR3PoolRelocate(pVM);
1982	}
1983
1984
1985	/**
1986	* Callback function for relocating a physical access handler.
1987	*
1988	* @returns 0 (continue enum)
1989	* @param pNode Pointer to a PGMPHYSHANDLER node.
1990	* @param pvUser Pointer to the offDelta. This is a pointer to the delta since we're
1991	* not certain the delta will fit in a void pointer for all possible configs.
1992	*/
1993	static DECLCALLBACK(int) pgmR3RelocatePhysHandler(PAVLROGCPHYSNODECORE pNode, void *pvUser)
1994	{
1995	PPGMPHYSHANDLER pHandler = (PPGMPHYSHANDLER)pNode;
1996	RTGCINTPTR offDelta = *(PRTGCINTPTR)pvUser;
1997	if (pHandler->pfnHandlerRC)
1998	pHandler->pfnHandlerRC += offDelta;
1999	if (pHandler->pvUserRC >= 0x10000)
2000	pHandler->pvUserRC += offDelta;
2001	return 0;
2002	}
2003
2004
2005	/**
2006	* Callback function for relocating a virtual access handler.
2007	*
2008	* @returns 0 (continue enum)
2009	* @param pNode Pointer to a PGMVIRTHANDLER node.
2010	* @param pvUser Pointer to the offDelta. This is a pointer to the delta since we're
2011	* not certain the delta will fit in a void pointer for all possible configs.
2012	*/
2013	static DECLCALLBACK(int) pgmR3RelocateVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser)
2014	{
2015	PPGMVIRTHANDLER pHandler = (PPGMVIRTHANDLER)pNode;
2016	RTGCINTPTR offDelta = *(PRTGCINTPTR)pvUser;
2017	Assert( pHandler->enmType == PGMVIRTHANDLERTYPE_ALL
2018	\|\| pHandler->enmType == PGMVIRTHANDLERTYPE_WRITE);
2019	Assert(pHandler->pfnHandlerRC);
2020	pHandler->pfnHandlerRC += offDelta;
2021	return 0;
2022	}
2023
2024
2025	/**
2026	* Callback function for relocating a virtual access handler for the hypervisor mapping.
2027	*
2028	* @returns 0 (continue enum)
2029	* @param pNode Pointer to a PGMVIRTHANDLER node.
2030	* @param pvUser Pointer to the offDelta. This is a pointer to the delta since we're
2031	* not certain the delta will fit in a void pointer for all possible configs.
2032	*/
2033	static DECLCALLBACK(int) pgmR3RelocateHyperVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser)
2034	{
2035	PPGMVIRTHANDLER pHandler = (PPGMVIRTHANDLER)pNode;
2036	RTGCINTPTR offDelta = *(PRTGCINTPTR)pvUser;
2037	Assert(pHandler->enmType == PGMVIRTHANDLERTYPE_HYPERVISOR);
2038	Assert(pHandler->pfnHandlerRC);
2039	pHandler->pfnHandlerRC += offDelta;
2040	return 0;
2041	}
2042
2043
2044	/**
2045	* The VM is being reset.
2046	*
2047	* For the PGM component this means that any PD write monitors
2048	* needs to be removed.
2049	*
2050	* @param pVM VM handle.
2051	*/
2052	VMMR3DECL(void) PGMR3Reset(PVM pVM)
2053	{
2054	LogFlow(("PGMR3Reset:\n"));
2055	VM_ASSERT_EMT(pVM);
2056
2057	pgmLock(pVM);
2058
2059	/*
2060	* Unfix any fixed mappings and disable CR3 monitoring.
2061	*/
2062	pVM->pgm.s.fMappingsFixed = false;
2063	pVM->pgm.s.GCPtrMappingFixed = 0;
2064	pVM->pgm.s.cbMappingFixed = 0;
2065
2066	/* Exit the guest paging mode before the pgm pool gets reset.
2067	* Important to clean up the amd64 case.
2068	*/
2069	int rc = PGM_GST_PFN(Exit, pVM)(pVM);
2070	AssertRC(rc);
2071	#ifdef DEBUG
2072	DBGFR3InfoLog(pVM, "mappings", NULL);
2073	DBGFR3InfoLog(pVM, "handlers", "all nostat");
2074	#endif
2075
2076	/*
2077	* Reset the shadow page pool.
2078	*/
2079	pgmR3PoolReset(pVM);
2080
2081	/*
2082	* Re-init other members.
2083	*/
2084	pVM->pgm.s.fA20Enabled = true;
2085
2086	/*
2087	* Clear the FFs PGM owns.
2088	*/
2089	VM_FF_CLEAR(pVM, VM_FF_PGM_SYNC_CR3);
2090	VM_FF_CLEAR(pVM, VM_FF_PGM_SYNC_CR3_NON_GLOBAL);
2091
2092	/*
2093	* Reset (zero) RAM pages.
2094	*/
2095	rc = pgmR3PhysRamReset(pVM);
2096	if (RT_SUCCESS(rc))
2097	{
2098	#ifdef VBOX_WITH_NEW_PHYS_CODE
2099	/*
2100	* Reset (zero) shadow ROM pages.
2101	*/
2102	rc = pgmR3PhysRomReset(pVM);
2103	#endif
2104	if (RT_SUCCESS(rc))
2105	{
2106	/*
2107	* Switch mode back to real mode.
2108	*/
2109	rc = PGMR3ChangeMode(pVM, PGMMODE_REAL);
2110	STAM_REL_COUNTER_RESET(&pVM->pgm.s.cGuestModeChanges);
2111	}
2112	}
2113
2114	pgmUnlock(pVM);
2115	//return rc;
2116	AssertReleaseRC(rc);
2117	}
2118
2119
2120	#ifdef VBOX_STRICT
2121	/**
2122	* VM state change callback for clearing fNoMorePhysWrites after
2123	* a snapshot has been created.
2124	*/
2125	static DECLCALLBACK(void) pgmR3ResetNoMorePhysWritesFlag(PVM pVM, VMSTATE enmState, VMSTATE enmOldState, void *pvUser)
2126	{
2127	if (enmState == VMSTATE_RUNNING)
2128	pVM->pgm.s.fNoMorePhysWrites = false;
2129	}
2130	#endif
2131
2132
2133	/**
2134	* Terminates the PGM.
2135	*
2136	* @returns VBox status code.
2137	* @param pVM Pointer to VM structure.
2138	*/
2139	VMMR3DECL(int) PGMR3Term(PVM pVM)
2140	{
2141	PGMDeregisterStringFormatTypes();
2142	return PDMR3CritSectDelete(&pVM->pgm.s.CritSect);
2143	}
2144
2145
2146	/**
2147	* Terminates the per-VCPU PGM.
2148	*
2149	* Termination means cleaning up and freeing all resources,
2150	* the VM it self is at this point powered off or suspended.
2151	*
2152	* @returns VBox status code.
2153	* @param pVM The VM to operate on.
2154	*/
2155	VMMR3DECL(int) PGMR3TermCPU(PVM pVM)
2156	{
2157	return 0;
2158	}
2159
2160	#ifdef VBOX_WITH_NEW_PHYS_CODE
2161
2162	/**
2163	* Find the ROM tracking structure for the given page.
2164	*
2165	* @returns Pointer to the ROM page structure. NULL if the caller didn't check
2166	* that it's a ROM page.
2167	* @param pVM The VM handle.
2168	* @param GCPhys The address of the ROM page.
2169	*/
2170	static PPGMROMPAGE pgmR3GetRomPage(PVM pVM, RTGCPHYS GCPhys)
2171	{
2172	for (PPGMROMRANGE pRomRange = pVM->pgm.s.CTX_SUFF(pRomRanges);
2173	pRomRange;
2174	pRomRange = pRomRange->CTX_SUFF(pNext))
2175	{
2176	RTGCPHYS off = GCPhys - pRomRange->GCPhys;
2177	if (GCPhys - pRomRange->GCPhys < pRomRange->cb)
2178	return &pRomRange->aPages[off >> PAGE_SHIFT];
2179	}
2180	return NULL;
2181	}
2182
2183
2184	/**
2185	* Save zero indicator + bits for the specified page.
2186	*
2187	* @returns VBox status code, errors are logged/asserted before returning.
2188	* @param pVM The VM handle.
2189	* @param pSSH The saved state handle.
2190	* @param pPage The page to save.
2191	* @param GCPhys The address of the page.
2192	* @param pRam The ram range (for error logging).
2193	*/
2194	static int pgmR3SavePage(PVM pVM, PSSMHANDLE pSSM, PPGMPAGE pPage, RTGCPHYS GCPhys, PPGMRAMRANGE pRam)
2195	{
2196	int rc;
2197	if (PGM_PAGE_IS_ZERO(pPage))
2198	rc = SSMR3PutU8(pSSM, 0);
2199	else
2200	{
2201	void const *pvPage;
2202	rc = pgmPhysGCPhys2CCPtrInternalReadOnly(pVM, pPage, GCPhys, &pvPage);
2203	AssertLogRelMsgRCReturn(rc, ("pPage=%R[pgmpage] GCPhys=%#x %s\n", pPage, GCPhys, pRam->pszDesc), rc);
2204
2205	SSMR3PutU8(pSSM, 1);
2206	rc = SSMR3PutMem(pSSM, pvPage, PAGE_SIZE);
2207	}
2208	return rc;
2209	}
2210
2211
2212	/**
2213	* Save a shadowed ROM page.
2214	*
2215	* Format: Type, protection, and two pages with zero indicators.
2216	*
2217	* @returns VBox status code, errors are logged/asserted before returning.
2218	* @param pVM The VM handle.
2219	* @param pSSH The saved state handle.
2220	* @param pPage The page to save.
2221	* @param GCPhys The address of the page.
2222	* @param pRam The ram range (for error logging).
2223	*/
2224	static int pgmR3SaveShadowedRomPage(PVM pVM, PSSMHANDLE pSSM, PPGMPAGE pPage, RTGCPHYS GCPhys, PPGMRAMRANGE pRam)
2225	{
2226	/* Need to save both pages and the current state. */
2227	PPGMROMPAGE pRomPage = pgmR3GetRomPage(pVM, GCPhys);
2228	AssertLogRelMsgReturn(pRomPage, ("GCPhys=%RGp %s\n", GCPhys, pRam->pszDesc), VERR_INTERNAL_ERROR);
2229
2230	SSMR3PutU8(pSSM, PGMPAGETYPE_ROM_SHADOW);
2231	SSMR3PutU8(pSSM, pRomPage->enmProt);
2232
2233	int rc = pgmR3SavePage(pVM, pSSM, pPage, GCPhys, pRam);
2234	if (RT_SUCCESS(rc))
2235	{
2236	PPGMPAGE pPagePassive = PGMROMPROT_IS_ROM(pRomPage->enmProt) ? &pRomPage->Shadow : &pRomPage->Virgin;
2237	rc = pgmR3SavePage(pVM, pSSM, pPagePassive, GCPhys, pRam);
2238	}
2239	return rc;
2240	}
2241
2242	/** PGM fields to save/load. */
2243	static SSMFIELD s_aPGMFields[] =
2244	{
2245	SSMFIELD_ENTRY( PGM, fMappingsFixed),
2246	SSMFIELD_ENTRY_GCPTR( PGM, GCPtrMappingFixed),
2247	SSMFIELD_ENTRY( PGM, cbMappingFixed),
2248	SSMFIELD_ENTRY( PGM, fA20Enabled),
2249	SSMFIELD_ENTRY_GCPHYS( PGM, GCPhysA20Mask),
2250	SSMFIELD_ENTRY( PGM, enmGuestMode),
2251	SSMFIELD_ENTRY_TERM()
2252	};
2253	#endif /* VBOX_WITH_NEW_PHYS_CODE */
2254
2255
2256	/**
2257	* Execute state save operation.
2258	*
2259	* @returns VBox status code.
2260	* @param pVM VM Handle.
2261	* @param pSSM SSM operation handle.
2262	*/
2263	static DECLCALLBACK(int) pgmR3Save(PVM pVM, PSSMHANDLE pSSM)
2264	{
2265	int rc;
2266	PPGM pPGM = &pVM->pgm.s;
2267
2268	/*
2269	* Lock PGM and set the no-more-writes indicator.
2270	*/
2271	#ifdef VBOX_WITH_NEW_PHYS_CODE
2272	pgmLock(pVM);
2273	#endif
2274	pVM->pgm.s.fNoMorePhysWrites = true;
2275
2276	/*
2277	* Save basic data (required / unaffected by relocation).
2278	*/
2279	#ifdef VBOX_WITH_NEW_PHYS_CODE
2280	SSMR3PutStruct(pSSM, pPGM, &s_aPGMFields[0]);
2281	#else
2282	SSMR3PutBool( pSSM, pPGM->fMappingsFixed);
2283	SSMR3PutGCPtr( pSSM, pPGM->GCPtrMappingFixed);
2284	SSMR3PutU32( pSSM, pPGM->cbMappingFixed);
2285	SSMR3PutUInt( pSSM, pPGM->cbRamSize);
2286	SSMR3PutGCPhys(pSSM, pPGM->GCPhysA20Mask);
2287	SSMR3PutUInt( pSSM, pPGM->fA20Enabled);
2288	SSMR3PutUInt( pSSM, pPGM->fSyncFlags);
2289	SSMR3PutUInt( pSSM, pPGM->enmGuestMode);
2290	SSMR3PutU32( pSSM, ~0); /* Separator. */
2291	#endif
2292
2293	/*
2294	* The guest mappings.
2295	*/
2296	uint32_t i = 0;
2297	for (PPGMMAPPING pMapping = pPGM->pMappingsR3; pMapping; pMapping = pMapping->pNextR3, i++)
2298	{
2299	SSMR3PutU32( pSSM, i);
2300	SSMR3PutStrZ( pSSM, pMapping->pszDesc); /* This is the best unique id we have... */
2301	SSMR3PutGCPtr( pSSM, pMapping->GCPtr);
2302	SSMR3PutGCUIntPtr(pSSM, pMapping->cPTs);
2303	}
2304	rc = SSMR3PutU32(pSSM, ~0); /* terminator. */
2305
2306	/*
2307	* Ram ranges and the memory they describe.
2308	*/
2309	i = 0;
2310	for (PPGMRAMRANGE pRam = pPGM->pRamRangesR3; pRam; pRam = pRam->pNextR3, i++)
2311	{
2312	/*
2313	* Save the ram range details.
2314	*/
2315	SSMR3PutU32(pSSM, i);
2316	SSMR3PutGCPhys(pSSM, pRam->GCPhys);
2317	SSMR3PutGCPhys(pSSM, pRam->GCPhysLast);
2318	SSMR3PutGCPhys(pSSM, pRam->cb);
2319	SSMR3PutU8(pSSM, !!pRam->pvR3); /* Boolean indicating memory or not. */
2320	#ifdef VBOX_WITH_NEW_PHYS_CODE
2321	SSMR3PutStrZ(pSSM, pRam->pszDesc); /* This is the best unique id we have... */
2322
2323	/*
2324	* Iterate the pages, only two special case.
2325	*/
2326	uint32_t const cPages = pRam->cb >> PAGE_SHIFT;
2327	for (uint32_t iPage = 0; iPage < cPages; iPage++)
2328	{
2329	RTGCPHYS GCPhysPage = pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT);
2330	PPGMPAGE pPage = &pRam->aPages[iPage];
2331	uint8_t uType = PGM_PAGE_GET_TYPE(pPage);
2332
2333	if (uType == PGMPAGETYPE_ROM_SHADOW)
2334	rc = pgmR3SaveShadowedRomPage(pVM, pSSM, pPage, GCPhysPage, pRam);
2335	else if (uType == PGMPAGETYPE_MMIO2_ALIAS_MMIO)
2336	{
2337	/* MMIO2 alias -> MMIO; the device will just have to deal with this. */
2338	SSMR3PutU8(pSSM, PGMPAGETYPE_MMIO);
2339	rc = SSMR3PutU8(pSSM, 0 /* ZERO */);
2340	}
2341	else
2342	{
2343	SSMR3PutU8(pSSM, uType);
2344	rc = pgmR3SavePage(pVM, pSSM, pPage, GCPhysPage, pRam);
2345	}
2346	if (RT_FAILURE(rc))
2347	break;
2348	}
2349	if (RT_FAILURE(rc))
2350	break;
2351
2352	#else /* !VBOX_WITH_NEW_PHYS_CODE */
2353	/* Flags. */
2354	const unsigned cPages = pRam->cb >> PAGE_SHIFT;
2355	for (unsigned iPage = 0; iPage < cPages; iPage++)
2356	SSMR3PutU16(pSSM, (uint16_t)(pRam->aPages[iPage].HCPhys & ~X86_PTE_PAE_PG_MASK)); /** @todo PAGE FLAGS */
2357
2358	/* Any memory associated with the range. */
2359	if (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)
2360	{
2361	for (unsigned iChunk = 0; iChunk < (pRam->cb >> PGM_DYNAMIC_CHUNK_SHIFT); iChunk++)
2362	{
2363	if (pRam->paChunkR3Ptrs[iChunk])
2364	{
2365	SSMR3PutU8(pSSM, 1); /* chunk present */
2366	SSMR3PutMem(pSSM, (void *)pRam->paChunkR3Ptrs[iChunk], PGM_DYNAMIC_CHUNK_SIZE);
2367	}
2368	else
2369	SSMR3PutU8(pSSM, 0); /* no chunk present */
2370	}
2371	}
2372	else if (pRam->pvR3)
2373	{
2374	rc = SSMR3PutMem(pSSM, pRam->pvR3, pRam->cb);
2375	if (RT_FAILURE(rc))
2376	{
2377	Log(("pgmR3Save: SSMR3PutMem(, %p, %#x) -> %Rrc\n", pRam->pvR3, pRam->cb, rc));
2378	return rc;
2379	}
2380	}
2381	#endif /* !VBOX_WITH_NEW_PHYS_CODE */
2382	}
2383
2384	#ifdef VBOX_WITH_NEW_PHYS_CODE
2385	pgmUnlock(pVM);
2386	#endif
2387	return SSMR3PutU32(pSSM, ~0); /* terminator. */
2388	}
2389
2390
2391	#ifdef VBOX_WITH_NEW_PHYS_CODE
2392
2393	/**
2394	* Load an ignored page.
2395	*
2396	* @returns VBox status code.
2397	* @param pSSM The saved state handle.
2398	*/
2399	static int pgmR3LoadPageToDevNull(PSSMHANDLE pSSM)
2400	{
2401	uint8_t abPage[PAGE_SIZE];
2402	return SSMR3GetMem(pSSM, &abPage[0], sizeof(abPage));
2403	}
2404
2405
2406	/**
2407	* Loads a page without any bits in the saved state, i.e. making sure it's
2408	* really zero.
2409	*
2410	* @returns VBox status code.
2411	* @param pVM The VM handle.
2412	* @param uType The page type or PGMPAGETYPE_INVALID (old saved
2413	* state).
2414	* @param pPage The guest page tracking structure.
2415	* @param GCPhys The page address.
2416	* @param pRam The ram range (logging).
2417	*/
2418	static int pgmR3LoadPageZero(PVM pVM, uint8_t uType, PPGMPAGE pPage, RTGCPHYS GCPhys, PPGMRAMRANGE pRam)
2419	{
2420	if ( PGM_PAGE_GET_TYPE(pPage) != uType
2421	&& uType != PGMPAGETYPE_INVALID)
2422	return VERR_SSM_UNEXPECTED_DATA;
2423
2424	/* I think this should be sufficient. */
2425	if (!PGM_PAGE_IS_ZERO(pPage))
2426	return VERR_SSM_UNEXPECTED_DATA;
2427
2428	NOREF(pVM);
2429	NOREF(GCPhys);
2430	NOREF(pRam);
2431	return VINF_SUCCESS;
2432	}
2433
2434
2435	/**
2436	* Loads a page from the saved state.
2437	*
2438	* @returns VBox status code.
2439	* @param pVM The VM handle.
2440	* @param pSSM The SSM handle.
2441	* @param uType The page type or PGMPAGETYEP_INVALID (old saved
2442	* state).
2443	* @param pPage The guest page tracking structure.
2444	* @param GCPhys The page address.
2445	* @param pRam The ram range (logging).
2446	*/
2447	static int pgmR3LoadPageBits(PVM pVM, PSSMHANDLE pSSM, uint8_t uType, PPGMPAGE pPage, RTGCPHYS GCPhys, PPGMRAMRANGE pRam)
2448	{
2449	int rc;
2450
2451	/*
2452	* Match up the type, dealing with MMIO2 aliases (dropped).
2453	*/
2454	AssertLogRelMsgReturn( PGM_PAGE_GET_TYPE(pPage) == uType
2455	\|\| uType == PGMPAGETYPE_INVALID,
2456	("pPage=%R[pgmpage] GCPhys=%#x %s\n", pPage, GCPhys, pRam->pszDesc),
2457	VERR_SSM_UNEXPECTED_DATA);
2458
2459	/*
2460	* Load the page.
2461	*/
2462	void *pvPage;
2463	rc = pgmPhysGCPhys2CCPtrInternal(pVM, pPage, GCPhys, &pvPage);
2464	if (RT_SUCCESS(rc))
2465	rc = SSMR3GetMem(pSSM, pvPage, PAGE_SIZE);
2466
2467	return rc;
2468	}
2469
2470
2471	/**
2472	* Loads a page (counter part to pgmR3SavePage).
2473	*
2474	* @returns VBox status code, fully bitched errors.
2475	* @param pVM The VM handle.
2476	* @param pSSM The SSM handle.
2477	* @param uType The page type.
2478	* @param pPage The page.
2479	* @param GCPhys The page address.
2480	* @param pRam The RAM range (for error messages).
2481	*/
2482	static int pgmR3LoadPage(PVM pVM, PSSMHANDLE pSSM, uint8_t uType, PPGMPAGE pPage, RTGCPHYS GCPhys, PPGMRAMRANGE pRam)
2483	{
2484	uint8_t uState;
2485	int rc = SSMR3GetU8(pSSM, &uState);
2486	AssertLogRelMsgRCReturn(rc, ("pPage=%R[pgmpage] GCPhys=%#x %s rc=%Rrc\n", pPage, GCPhys, pRam->pszDesc, rc), rc);
2487	if (uState == 0 /* zero */)
2488	rc = pgmR3LoadPageZero(pVM, uType, pPage, GCPhys, pRam);
2489	else if (uState == 1)
2490	rc = pgmR3LoadPageBits(pVM, pSSM, uType, pPage, GCPhys, pRam);
2491	else
2492	rc = VERR_INTERNAL_ERROR;
2493	AssertLogRelMsgRCReturn(rc, ("pPage=%R[pgmpage] uState=%d uType=%d GCPhys=%RGp %s rc=%Rrc\n",
2494	pPage, uState, uType, GCPhys, pRam->pszDesc, rc),
2495	rc);
2496	return VINF_SUCCESS;
2497	}
2498
2499
2500	/**
2501	* Loads a shadowed ROM page.
2502	*
2503	* @returns VBox status code, errors are fully bitched.
2504	* @param pVM The VM handle.
2505	* @param pSSM The saved state handle.
2506	* @param pPage The page.
2507	* @param GCPhys The page address.
2508	* @param pRam The RAM range (for error messages).
2509	*/
2510	static int pgmR3LoadShadowedRomPage(PVM pVM, PSSMHANDLE pSSM, PPGMPAGE pPage, RTGCPHYS GCPhys, PPGMRAMRANGE pRam)
2511	{
2512	/*
2513	* Load and set the protection first, then load the two pages, the first
2514	* one is the active the other is the passive.
2515	*/
2516	PPGMROMPAGE pRomPage = pgmR3GetRomPage(pVM, GCPhys);
2517	AssertLogRelMsgReturn(pRomPage, ("GCPhys=%RGp %s\n", GCPhys, pRam->pszDesc), VERR_INTERNAL_ERROR);
2518
2519	uint8_t uProt;
2520	int rc = SSMR3GetU8(pSSM, &uProt);
2521	AssertLogRelMsgRCReturn(rc, ("pPage=%R[pgmpage] GCPhys=%#x %s\n", pPage, GCPhys, pRam->pszDesc), rc);
2522	PGMROMPROT enmProt = (PGMROMPROT)uProt;
2523	AssertLogRelMsgReturn( enmProt >= PGMROMPROT_INVALID
2524	&& enmProt < PGMROMPROT_END,
2525	("enmProt=%d pPage=%R[pgmpage] GCPhys=%#x %s\n", enmProt, pPage, GCPhys, pRam->pszDesc),
2526	VERR_SSM_UNEXPECTED_DATA);
2527
2528	if (pRomPage->enmProt != enmProt)
2529	{
2530	rc = PGMR3PhysRomProtect(pVM, GCPhys, PAGE_SIZE, enmProt);
2531	AssertLogRelRCReturn(rc, rc);
2532	AssertLogRelReturn(pRomPage->enmProt == enmProt, VERR_INTERNAL_ERROR);
2533	}
2534
2535	PPGMPAGE pPageActive = PGMROMPROT_IS_ROM(enmProt) ? &pRomPage->Virgin : &pRomPage->Shadow;
2536	PPGMPAGE pPagePassive = PGMROMPROT_IS_ROM(enmProt) ? &pRomPage->Shadow : &pRomPage->Virgin;
2537	uint8_t u8ActiveType = PGMROMPROT_IS_ROM(enmProt) ? PGMPAGETYPE_ROM : PGMPAGETYPE_ROM_SHADOW;
2538	uint8_t u8PassiveType= PGMROMPROT_IS_ROM(enmProt) ? PGMPAGETYPE_ROM_SHADOW : PGMPAGETYPE_ROM;
2539
2540	rc = pgmR3LoadPage(pVM, pSSM, u8ActiveType, pPage, GCPhys, pRam);
2541	if (RT_SUCCESS(rc))
2542	{
2543	pPageActive = pPage;
2544	rc = pgmR3LoadPage(pVM, pSSM, u8PassiveType, pPagePassive, GCPhys, pRam);
2545	}
2546	return rc;
2547	}
2548
2549	#endif /* VBOX_WITH_NEW_PHYS_CODE */
2550
2551	/**
2552	* Worker for pgmR3Load.
2553	*
2554	* @returns VBox status code.
2555	*
2556	* @param pVM The VM handle.
2557	* @param pSSM The SSM handle.
2558	* @param u32Version The saved state version.
2559	*/
2560	static int pgmR3LoadLocked(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version)
2561	{
2562	int rc;
2563	PPGM pPGM = &pVM->pgm.s;
2564	uint32_t u32Sep;
2565
2566	/*
2567	* Load basic data (required / unaffected by relocation).
2568	*/
2569	#ifdef VBOX_WITH_NEW_PHYS_CODE
2570	if (u32Version >= PGM_SAVED_STATE_VERSION)
2571	{
2572	rc = SSMR3GetStruct(pSSM, pPGM, &s_aPGMFields[0]);
2573	AssertLogRelRCReturn(rc, rc);
2574	}
2575	else
2576	#endif
2577	{
2578	SSMR3GetBool(pSSM, &pPGM->fMappingsFixed);
2579	SSMR3GetGCPtr(pSSM, &pPGM->GCPtrMappingFixed);
2580	SSMR3GetU32(pSSM, &pPGM->cbMappingFixed);
2581
2582	RTUINT cbRamSize;
2583	rc = SSMR3GetU32(pSSM, &cbRamSize);
2584	if (RT_FAILURE(rc))
2585	return rc;
2586	AssertLogRelMsgReturn(cbRamSize == pPGM->cbRamSize, ("%#x != %#x\n", cbRamSize, pPGM->cbRamSize),
2587	VERR_SSM_LOAD_MEMORY_SIZE_MISMATCH);
2588	SSMR3GetGCPhys(pSSM, &pPGM->GCPhysA20Mask);
2589
2590	uint32_t u32 = 0;
2591	SSMR3GetUInt(pSSM, &u32);
2592	pPGM->fA20Enabled = !!u32;
2593	SSMR3GetUInt(pSSM, &pPGM->fSyncFlags);
2594	RTUINT uGuestMode;
2595	SSMR3GetUInt(pSSM, &uGuestMode);
2596	pPGM->enmGuestMode = (PGMMODE)uGuestMode;
2597
2598	/* check separator. */
2599	SSMR3GetU32(pSSM, &u32Sep);
2600	if (RT_FAILURE(rc))
2601	return rc;
2602	if (u32Sep != (uint32_t)~0)
2603	{
2604	AssertMsgFailed(("u32Sep=%#x (first)\n", u32Sep));
2605	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2606	}
2607	}
2608
2609	/*
2610	* The guest mappings.
2611	*/
2612	uint32_t i = 0;
2613	for (;; i++)
2614	{
2615	/* Check the seqence number / separator. */
2616	rc = SSMR3GetU32(pSSM, &u32Sep);
2617	if (RT_FAILURE(rc))
2618	return rc;
2619	if (u32Sep == ~0U)
2620	break;
2621	if (u32Sep != i)
2622	{
2623	AssertMsgFailed(("u32Sep=%#x (last)\n", u32Sep));
2624	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2625	}
2626
2627	/* get the mapping details. */
2628	char szDesc[256];
2629	szDesc[0] = '\0';
2630	rc = SSMR3GetStrZ(pSSM, szDesc, sizeof(szDesc));
2631	if (RT_FAILURE(rc))
2632	return rc;
2633	RTGCPTR GCPtr;
2634	SSMR3GetGCPtr(pSSM, &GCPtr);
2635	RTGCPTR cPTs;
2636	rc = SSMR3GetGCUIntPtr(pSSM, &cPTs);
2637	if (RT_FAILURE(rc))
2638	return rc;
2639
2640	/* find matching range. */
2641	PPGMMAPPING pMapping;
2642	for (pMapping = pPGM->pMappingsR3; pMapping; pMapping = pMapping->pNextR3)
2643	if ( pMapping->cPTs == cPTs
2644	&& !strcmp(pMapping->pszDesc, szDesc))
2645	break;
2646	AssertLogRelMsgReturn(pMapping, ("Couldn't find mapping: cPTs=%#x szDesc=%s (GCPtr=%RGv)\n",
2647	cPTs, szDesc, GCPtr),
2648	VERR_SSM_LOAD_CONFIG_MISMATCH);
2649
2650	/* relocate it. */
2651	if (pMapping->GCPtr != GCPtr)
2652	{
2653	AssertMsg((GCPtr >> X86_PD_SHIFT << X86_PD_SHIFT) == GCPtr, ("GCPtr=%RGv\n", GCPtr));
2654	pgmR3MapRelocate(pVM, pMapping, pMapping->GCPtr, GCPtr);
2655	}
2656	else
2657	Log(("pgmR3Load: '%s' needed no relocation (%RGv)\n", szDesc, GCPtr));
2658	}
2659
2660	/*
2661	* Ram range flags and bits.
2662	*/
2663	i = 0;
2664	for (PPGMRAMRANGE pRam = pPGM->pRamRangesR3; pRam; pRam = pRam->pNextR3, i++)
2665	{
2666	/** @todo MMIO ranges may move (PCI reconfig), we currently assume they don't. */
2667
2668	/* Check the seqence number / separator. */
2669	rc = SSMR3GetU32(pSSM, &u32Sep);
2670	if (RT_FAILURE(rc))
2671	return rc;
2672	if (u32Sep == ~0U)
2673	break;
2674	if (u32Sep != i)
2675	{
2676	AssertMsgFailed(("u32Sep=%#x (last)\n", u32Sep));
2677	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2678	}
2679
2680	/* Get the range details. */
2681	RTGCPHYS GCPhys;
2682	SSMR3GetGCPhys(pSSM, &GCPhys);
2683	RTGCPHYS GCPhysLast;
2684	SSMR3GetGCPhys(pSSM, &GCPhysLast);
2685	RTGCPHYS cb;
2686	SSMR3GetGCPhys(pSSM, &cb);
2687	uint8_t fHaveBits;
2688	rc = SSMR3GetU8(pSSM, &fHaveBits);
2689	if (RT_FAILURE(rc))
2690	return rc;
2691	if (fHaveBits & ~1)
2692	{
2693	AssertMsgFailed(("u32Sep=%#x (last)\n", u32Sep));
2694	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2695	}
2696	char szDesc[256];
2697	szDesc[0] = '\0';
2698	#ifdef VBOX_WITH_NEW_PHYS_CODE
2699	if (u32Version >= PGM_SAVED_STATE_VERSION)
2700	{
2701	rc = SSMR3GetStrZ(pSSM, szDesc, sizeof(szDesc));
2702	if (RT_FAILURE(rc))
2703	return rc;
2704	}
2705	#endif
2706
2707	/*
2708	* Match it up with the current range.
2709	*
2710	* Note there is a hack for dealing with the high BIOS mapping
2711	* in the old saved state format, this means we might not have
2712	* a 1:1 match on success.
2713	*/
2714	if ( ( GCPhys != pRam->GCPhys
2715	\|\| GCPhysLast != pRam->GCPhysLast
2716	\|\| cb != pRam->cb
2717	#ifdef VBOX_WITH_NEW_PHYS_CODE
2718	\|\| (szDesc[0] && strcmp(szDesc, pRam->pszDesc))
2719	#else
2720	\|\| fHaveBits != !!pRam->pvR3
2721	#endif
2722	)
2723	#ifdef VBOX_WITH_NEW_PHYS_CODE
2724	/* Hack for PDMDevHlpPhysReserve(pDevIns, 0xfff80000, 0x80000, "High ROM Region"); */
2725	&& ( u32Version != PGM_SAVED_STATE_VERSION_OLD_PHYS_CODE
2726	\|\| GCPhys != UINT32_C(0xfff80000)
2727	\|\| GCPhysLast != UINT32_C(0xffffffff)
2728	\|\| pRam->GCPhysLast != GCPhysLast
2729	\|\| pRam->GCPhys < GCPhys
2730	\|\| !fHaveBits)
2731	#endif
2732	)
2733	{
2734	LogRel(("Ram range: %RGp-%RGp %RGp bytes %s %s\n"
2735	"State : %RGp-%RGp %RGp bytes %s %s\n",
2736	pRam->GCPhys, pRam->GCPhysLast, pRam->cb, pRam->pvR3 ? "bits" : "nobits", pRam->pszDesc,
2737	GCPhys, GCPhysLast, cb, fHaveBits ? "bits" : "nobits", szDesc));
2738	/*
2739	* If we're loading a state for debugging purpose, don't make a fuss if
2740	* the MMIO and ROM stuff isn't 100% right, just skip the mismatches.
2741	*/
2742	if ( SSMR3HandleGetAfter(pSSM) != SSMAFTER_DEBUG_IT
2743	\|\| GCPhys < 8 * _1M)
2744	AssertFailedReturn(VERR_SSM_LOAD_CONFIG_MISMATCH);
2745
2746	#ifdef VBOX_WITH_NEW_PHYS_CODE
2747	if (u32Version > PGM_SAVED_STATE_VERSION_OLD_PHYS_CODE)
2748	AssertMsgFailed(("debug skipping not implemented, sorry\n"));
2749	else
2750	#else
2751	{
2752	RTGCPHYS cPages = ((GCPhysLast - GCPhys) + 1) >> PAGE_SHIFT;
2753	while (cPages-- > 0)
2754	{
2755	uint16_t u16Ignore;
2756	SSMR3GetU16(pSSM, &u16Ignore);
2757	}
2758	}
2759	#endif
2760	continue;
2761	}
2762
2763	uint32_t cPages = (GCPhysLast - GCPhys + 1) >> PAGE_SHIFT;
2764
2765	#ifdef VBOX_WITH_NEW_PHYS_CODE
2766	if (u32Version >= PGM_SAVED_STATE_VERSION)
2767	{
2768	/*
2769	* Load the pages one by one.
2770	*/
2771	for (uint32_t iPage = 0; iPage < cPages; iPage++)
2772	{
2773	RTGCPHYS const GCPhysPage = ((RTGCPHYS)iPage << PAGE_SHIFT) + pRam->GCPhys;
2774	PPGMPAGE pPage = &pRam->aPages[iPage];
2775	uint8_t uType;
2776	rc = SSMR3GetU8(pSSM, &uType);
2777	AssertLogRelMsgRCReturn(rc, ("pPage=%R[pgmpage] iPage=%#x GCPhysPage=%#x %s\n", pPage, iPage, GCPhysPage, pRam->pszDesc), rc);
2778	if (uType == PGMPAGETYPE_ROM_SHADOW)
2779	rc = pgmR3LoadShadowedRomPage(pVM, pSSM, pPage, GCPhysPage, pRam);
2780	else
2781	rc = pgmR3LoadPage(pVM, pSSM, uType, pPage, GCPhysPage, pRam);
2782	AssertLogRelMsgRCReturn(rc, ("rc=%Rrc iPage=%#x GCPhysPage=%#x %s\n", rc, iPage, GCPhysPage, pRam->pszDesc), rc);
2783	}
2784	}
2785	else
2786	{
2787	/*
2788	* Old format.
2789	*/
2790	AssertLogRelReturn(!pVM->pgm.s.fRamPreAlloc, VERR_NOT_SUPPORTED); /* can't be detected. */
2791
2792	/* Of the page flags, pick up MMIO2 and ROM/RESERVED for the !fHaveBits case.
2793	The rest is generally irrelevant and wrong since the stuff have to match registrations. */
2794	uint32_t fFlags = 0;
2795	for (uint32_t iPage = 0; iPage < cPages; iPage++)
2796	{
2797	uint16_t u16Flags;
2798	rc = SSMR3GetU16(pSSM, &u16Flags);
2799	AssertLogRelMsgRCReturn(rc, ("rc=%Rrc iPage=%#x GCPhys=%#x %s\n", rc, iPage, pRam->GCPhys, pRam->pszDesc), rc);
2800	fFlags \|= u16Flags;
2801	}
2802
2803	/* Load the bits */
2804	if ( !fHaveBits
2805	&& GCPhysLast < UINT32_C(0xe0000000))
2806	{
2807	/*
2808	* Dynamic chunks.
2809	*/
2810	const uint32_t cPagesInChunk = (110241024) >> PAGE_SHIFT;
2811	AssertLogRelMsgReturn(cPages % cPagesInChunk == 0,
2812	("cPages=%#x cPagesInChunk=%#x\n", cPages, cPagesInChunk, pRam->GCPhys, pRam->pszDesc),
2813	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2814
2815	for (uint32_t iPage = 0; iPage < cPages; /* incremented by inner loop */ )
2816	{
2817	uint8_t fPresent;
2818	rc = SSMR3GetU8(pSSM, &fPresent);
2819	AssertLogRelMsgRCReturn(rc, ("rc=%Rrc iPage=%#x GCPhys=%#x %s\n", rc, iPage, pRam->GCPhys, pRam->pszDesc), rc);
2820	AssertLogRelMsgReturn(fPresent == (uint8_t)true \|\| fPresent == (uint8_t)false,
2821	("fPresent=%#x iPage=%#x GCPhys=%#x %s\n", fPresent, iPage, pRam->GCPhys, pRam->pszDesc),
2822	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2823
2824	for (uint32_t iChunkPage = 0; iChunkPage < cPagesInChunk; iChunkPage++, iPage++)
2825	{
2826	RTGCPHYS const GCPhysPage = ((RTGCPHYS)iPage << PAGE_SHIFT) + pRam->GCPhys;
2827	PPGMPAGE pPage = &pRam->aPages[iPage];
2828	if (fPresent)
2829	{
2830	if (PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_MMIO)
2831	rc = pgmR3LoadPageToDevNull(pSSM);
2832	else
2833	rc = pgmR3LoadPageBits(pVM, pSSM, PGMPAGETYPE_INVALID, pPage, GCPhysPage, pRam);
2834	}
2835	else
2836	rc = pgmR3LoadPageZero(pVM, PGMPAGETYPE_INVALID, pPage, GCPhysPage, pRam);
2837	AssertLogRelMsgRCReturn(rc, ("rc=%Rrc iPage=%#x GCPhysPage=%#x %s\n", rc, iPage, GCPhysPage, pRam->pszDesc), rc);
2838	}
2839	}
2840	}
2841	else if (pRam->pvR3)
2842	{
2843	/*
2844	* MMIO2.
2845	*/
2846	AssertLogRelMsgReturn((fFlags & 0x0f) == RT_BIT(3) /MM_RAM_FLAGS_MMIO2/,
2847	("fFlags=%#x GCPhys=%#x %s\n", fFlags, pRam->GCPhys, pRam->pszDesc),
2848	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2849	AssertLogRelMsgReturn(pRam->pvR3,
2850	("GCPhys=%#x %s\n", pRam->GCPhys, pRam->pszDesc),
2851	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2852
2853	rc = SSMR3GetMem(pSSM, pRam->pvR3, pRam->cb);
2854	AssertLogRelMsgRCReturn(rc, ("GCPhys=%#x %s\n", pRam->GCPhys, pRam->pszDesc), rc);
2855	}
2856	else if (GCPhysLast < UINT32_C(0xfff80000))
2857	{
2858	/*
2859	* PCI MMIO, no pages saved.
2860	*/
2861	}
2862	else
2863	{
2864	/*
2865	* Load the 0xfff80000..0xffffffff BIOS range.
2866	* It starts with X reserved pages that we have to skip over since
2867	* the RAMRANGE create by the new code won't include those.
2868	*/
2869	AssertLogRelMsgReturn( !(fFlags & RT_BIT(3) /MM_RAM_FLAGS_MMIO2/)
2870	&& (fFlags & RT_BIT(0) /MM_RAM_FLAGS_RESERVED/),
2871	("fFlags=%#x GCPhys=%#x %s\n", fFlags, pRam->GCPhys, pRam->pszDesc),
2872	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2873	AssertLogRelMsgReturn(GCPhys == UINT32_C(0xfff80000),
2874	("GCPhys=%RGp pRamRange{GCPhys=%#x %s}\n", GCPhys, pRam->GCPhys, pRam->pszDesc),
2875	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2876
2877	/* Skip wasted reserved pages before the ROM. */
2878	while (GCPhys < pRam->GCPhys)
2879	{
2880	rc = pgmR3LoadPageToDevNull(pSSM);
2881	GCPhys += PAGE_SIZE;
2882	}
2883
2884	/* Load the bios pages. */
2885	cPages = pRam->cb >> PAGE_SHIFT;
2886	for (uint32_t iPage = 0; iPage < cPages; iPage++)
2887	{
2888	RTGCPHYS const GCPhysPage = ((RTGCPHYS)iPage << PAGE_SHIFT) + pRam->GCPhys;
2889	PPGMPAGE pPage = &pRam->aPages[iPage];
2890
2891	AssertLogRelMsgReturn(PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_ROM,
2892	("GCPhys=%RGp pPage=%R[pgmpage]\n", GCPhys, GCPhys),
2893	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2894	rc = pgmR3LoadPageBits(pVM, pSSM, PGMPAGETYPE_ROM, pPage, GCPhysPage, pRam);
2895	AssertLogRelMsgRCReturn(rc, ("rc=%Rrc iPage=%#x GCPhys=%#x %s\n", rc, iPage, pRam->GCPhys, pRam->pszDesc), rc);
2896	}
2897	}
2898	}
2899
2900	#else /* !VBOX_WITH_NEW_PHYS_CODE */
2901	/* Flags. */
2902	for (uint32_t iPage = 0; iPage < cPages; iPage++)
2903	{
2904	uint16_t u16 = 0;
2905	SSMR3GetU16(pSSM, &u16);
2906	u16 &= PAGE_OFFSET_MASK & ~( RT_BIT(4) \| RT_BIT(5) \| RT_BIT(6)
2907	\| RT_BIT(7) \| RT_BIT(8) \| RT_BIT(9) \| RT_BIT(10) );
2908	// &= MM_RAM_FLAGS_DYNAMIC_ALLOC \| MM_RAM_FLAGS_RESERVED \| MM_RAM_FLAGS_ROM \| MM_RAM_FLAGS_MMIO \| MM_RAM_FLAGS_MMIO2
2909	pRam->aPages[iPage].HCPhys = PGM_PAGE_GET_HCPHYS(&pRam->aPages[iPage]) \| (RTHCPHYS)u16; /** @todo PAGE FLAGS */
2910	}
2911
2912	/* any memory associated with the range. */
2913	if (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)
2914	{
2915	for (unsigned iChunk = 0; iChunk < (pRam->cb >> PGM_DYNAMIC_CHUNK_SHIFT); iChunk++)
2916	{
2917	uint8_t fValidChunk;
2918
2919	rc = SSMR3GetU8(pSSM, &fValidChunk);
2920	if (RT_FAILURE(rc))
2921	return rc;
2922	if (fValidChunk > 1)
2923	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2924
2925	if (fValidChunk)
2926	{
2927	if (!pRam->paChunkR3Ptrs[iChunk])
2928	{
2929	rc = pgmr3PhysGrowRange(pVM, pRam->GCPhys + iChunk * PGM_DYNAMIC_CHUNK_SIZE);
2930	if (RT_FAILURE(rc))
2931	return rc;
2932	}
2933	Assert(pRam->paChunkR3Ptrs[iChunk]);
2934
2935	SSMR3GetMem(pSSM, (void *)pRam->paChunkR3Ptrs[iChunk], PGM_DYNAMIC_CHUNK_SIZE);
2936	}
2937	/* else nothing to do */
2938	}
2939	}
2940	else if (pRam->pvR3)
2941	{
2942	rc = SSMR3GetMem(pSSM, pRam->pvR3, pRam->cb);
2943	if (RT_FAILURE(rc))
2944	{
2945	Log(("pgmR3Save: SSMR3GetMem(, %p, %#x) -> %Rrc\n", pRam->pvR3, pRam->cb, rc));
2946	return rc;
2947	}
2948	}
2949	#endif /* !VBOX_WITH_NEW_PHYS_CODE */
2950	}
2951
2952	return rc;
2953	}
2954
2955
2956	/**
2957	* Execute state load operation.
2958	*
2959	* @returns VBox status code.
2960	* @param pVM VM Handle.
2961	* @param pSSM SSM operation handle.
2962	* @param u32Version Data layout version.
2963	*/
2964	static DECLCALLBACK(int) pgmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version)
2965	{
2966	int rc;
2967	PPGM pPGM = &pVM->pgm.s;
2968
2969	/*
2970	* Validate version.
2971	*/
2972	if ( u32Version != PGM_SAVED_STATE_VERSION
2973	#ifdef VBOX_WITH_NEW_PHYS_CODE
2974	&& u32Version != PGM_SAVED_STATE_VERSION_OLD_PHYS_CODE
2975	#endif
2976	)
2977	{
2978	AssertMsgFailed(("pgmR3Load: Invalid version u32Version=%d (current %d)!\n", u32Version, PGM_SAVED_STATE_VERSION));
2979	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
2980	}
2981
2982	/*
2983	* Call the reset function to make sure all the memory is cleared.
2984	*/
2985	PGMR3Reset(pVM);
2986
2987	/*
2988	* Do the loading while owning the lock because a bunch of the functions
2989	* we're using requires this.
2990	*/
2991	pgmLock(pVM);
2992	rc = pgmR3LoadLocked(pVM, pSSM, u32Version);
2993	pgmUnlock(pVM);
2994	if (RT_SUCCESS(rc))
2995	{
2996	/*
2997	* We require a full resync now.
2998	*/
2999	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3_NON_GLOBAL);
3000	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
3001	pPGM->fSyncFlags \|= PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL;
3002	pPGM->fPhysCacheFlushPending = true;
3003	pgmR3HandlerPhysicalUpdateAll(pVM);
3004
3005	/*
3006	* Change the paging mode.
3007	*/
3008	rc = PGMR3ChangeMode(pVM, pPGM->enmGuestMode);
3009
3010	/* Restore pVM->pgm.s.GCPhysCR3. */
3011	Assert(pVM->pgm.s.GCPhysCR3 == NIL_RTGCPHYS);
3012	RTGCPHYS GCPhysCR3 = CPUMGetGuestCR3(pVM);
3013	if ( pVM->pgm.s.enmGuestMode == PGMMODE_PAE
3014	\|\| pVM->pgm.s.enmGuestMode == PGMMODE_PAE_NX
3015	\|\| pVM->pgm.s.enmGuestMode == PGMMODE_AMD64
3016	\|\| pVM->pgm.s.enmGuestMode == PGMMODE_AMD64_NX)
3017	GCPhysCR3 = (GCPhysCR3 & X86_CR3_PAE_PAGE_MASK);
3018	else
3019	GCPhysCR3 = (GCPhysCR3 & X86_CR3_PAGE_MASK);
3020	pVM->pgm.s.GCPhysCR3 = GCPhysCR3;
3021	}
3022
3023	return rc;
3024	}
3025
3026
3027	/**
3028	* Show paging mode.
3029	*
3030	* @param pVM VM Handle.
3031	* @param pHlp The info helpers.
3032	* @param pszArgs "all" (default), "guest", "shadow" or "host".
3033	*/
3034	static DECLCALLBACK(void) pgmR3InfoMode(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3035	{
3036	/* digest argument. */
3037	bool fGuest, fShadow, fHost;
3038	if (pszArgs)
3039	pszArgs = RTStrStripL(pszArgs);
3040	if (!pszArgs \|\| !*pszArgs \|\| strstr(pszArgs, "all"))
3041	fShadow = fHost = fGuest = true;
3042	else
3043	{
3044	fShadow = fHost = fGuest = false;
3045	if (strstr(pszArgs, "guest"))
3046	fGuest = true;
3047	if (strstr(pszArgs, "shadow"))
3048	fShadow = true;
3049	if (strstr(pszArgs, "host"))
3050	fHost = true;
3051	}
3052
3053	/* print info. */
3054	if (fGuest)
3055	pHlp->pfnPrintf(pHlp, "Guest paging mode: %s, changed %RU64 times, A20 %s\n",
3056	PGMGetModeName(pVM->pgm.s.enmGuestMode), pVM->pgm.s.cGuestModeChanges.c,
3057	pVM->pgm.s.fA20Enabled ? "enabled" : "disabled");
3058	if (fShadow)
3059	pHlp->pfnPrintf(pHlp, "Shadow paging mode: %s\n", PGMGetModeName(pVM->pgm.s.enmShadowMode));
3060	if (fHost)
3061	{
3062	const char *psz;
3063	switch (pVM->pgm.s.enmHostMode)
3064	{
3065	case SUPPAGINGMODE_INVALID: psz = "invalid"; break;
3066	case SUPPAGINGMODE_32_BIT: psz = "32-bit"; break;
3067	case SUPPAGINGMODE_32_BIT_GLOBAL: psz = "32-bit+G"; break;
3068	case SUPPAGINGMODE_PAE: psz = "PAE"; break;
3069	case SUPPAGINGMODE_PAE_GLOBAL: psz = "PAE+G"; break;
3070	case SUPPAGINGMODE_PAE_NX: psz = "PAE+NX"; break;
3071	case SUPPAGINGMODE_PAE_GLOBAL_NX: psz = "PAE+G+NX"; break;
3072	case SUPPAGINGMODE_AMD64: psz = "AMD64"; break;
3073	case SUPPAGINGMODE_AMD64_GLOBAL: psz = "AMD64+G"; break;
3074	case SUPPAGINGMODE_AMD64_NX: psz = "AMD64+NX"; break;
3075	case SUPPAGINGMODE_AMD64_GLOBAL_NX: psz = "AMD64+G+NX"; break;
3076	default: psz = "unknown"; break;
3077	}
3078	pHlp->pfnPrintf(pHlp, "Host paging mode: %s\n", psz);
3079	}
3080	}
3081
3082
3083	/**
3084	* Dump registered MMIO ranges to the log.
3085	*
3086	* @param pVM VM Handle.
3087	* @param pHlp The info helpers.
3088	* @param pszArgs Arguments, ignored.
3089	*/
3090	static DECLCALLBACK(void) pgmR3PhysInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3091	{
3092	NOREF(pszArgs);
3093	pHlp->pfnPrintf(pHlp,
3094	"RAM ranges (pVM=%p)\n"
3095	"%.s %.s\n",
3096	pVM,
3097	sizeof(RTGCPHYS) * 4 + 1, "GC Phys Range ",
3098	sizeof(RTHCPTR) * 2, "pvHC ");
3099
3100	for (PPGMRAMRANGE pCur = pVM->pgm.s.pRamRangesR3; pCur; pCur = pCur->pNextR3)
3101	pHlp->pfnPrintf(pHlp,
3102	"%RGp-%RGp %RHv %s\n",
3103	pCur->GCPhys,
3104	pCur->GCPhysLast,
3105	pCur->pvR3,
3106	pCur->pszDesc);
3107	}
3108
3109	/**
3110	* Dump the page directory to the log.
3111	*
3112	* @param pVM VM Handle.
3113	* @param pHlp The info helpers.
3114	* @param pszArgs Arguments, ignored.
3115	*/
3116	static DECLCALLBACK(void) pgmR3InfoCr3(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3117	{
3118	/** @todo fix this! Convert the PGMR3DumpHierarchyHC functions to do guest stuff. */
3119	/* Big pages supported? */
3120	const bool fPSE = !!(CPUMGetGuestCR4(pVM) & X86_CR4_PSE);
3121
3122	/* Global pages supported? */
3123	const bool fPGE = !!(CPUMGetGuestCR4(pVM) & X86_CR4_PGE);
3124
3125	NOREF(pszArgs);
3126
3127	/*
3128	* Get page directory addresses.
3129	*/
3130	PX86PD pPDSrc = pgmGstGet32bitPDPtr(&pVM->pgm.s);
3131	Assert(pPDSrc);
3132	Assert(PGMPhysGCPhys2R3PtrAssert(pVM, (RTGCPHYS)(CPUMGetGuestCR3(pVM) & X86_CR3_PAGE_MASK), sizeof(*pPDSrc)) == pPDSrc);
3133
3134	/*
3135	* Iterate the page directory.
3136	*/
3137	for (unsigned iPD = 0; iPD < RT_ELEMENTS(pPDSrc->a); iPD++)
3138	{
3139	X86PDE PdeSrc = pPDSrc->a[iPD];
3140	if (PdeSrc.n.u1Present)
3141	{
3142	if (PdeSrc.b.u1Size && fPSE)
3143	pHlp->pfnPrintf(pHlp,
3144	"%04X - %RGp P=%d U=%d RW=%d G=%d - BIG\n",
3145	iPD,
3146	pgmGstGet4MBPhysPage(&pVM->pgm.s, PdeSrc),
3147	PdeSrc.b.u1Present, PdeSrc.b.u1User, PdeSrc.b.u1Write, PdeSrc.b.u1Global && fPGE);
3148	else
3149	pHlp->pfnPrintf(pHlp,
3150	"%04X - %RGp P=%d U=%d RW=%d [G=%d]\n",
3151	iPD,
3152	(RTGCPHYS)(PdeSrc.u & X86_PDE_PG_MASK),
3153	PdeSrc.n.u1Present, PdeSrc.n.u1User, PdeSrc.n.u1Write, PdeSrc.b.u1Global && fPGE);
3154	}
3155	}
3156	}
3157
3158
3159	/**
3160	* Serivce a VMMCALLHOST_PGM_LOCK call.
3161	*
3162	* @returns VBox status code.
3163	* @param pVM The VM handle.
3164	*/
3165	VMMR3DECL(int) PGMR3LockCall(PVM pVM)
3166	{
3167	int rc = PDMR3CritSectEnterEx(&pVM->pgm.s.CritSect, true /* fHostCall */);
3168	AssertRC(rc);
3169	return rc;
3170	}
3171
3172
3173	/**
3174	* Converts a PGMMODE value to a PGM_TYPE_* \#define.
3175	*
3176	* @returns PGM_TYPE_*.
3177	* @param pgmMode The mode value to convert.
3178	*/
3179	DECLINLINE(unsigned) pgmModeToType(PGMMODE pgmMode)
3180	{
3181	switch (pgmMode)
3182	{
3183	case PGMMODE_REAL: return PGM_TYPE_REAL;
3184	case PGMMODE_PROTECTED: return PGM_TYPE_PROT;
3185	case PGMMODE_32_BIT: return PGM_TYPE_32BIT;
3186	case PGMMODE_PAE:
3187	case PGMMODE_PAE_NX: return PGM_TYPE_PAE;
3188	case PGMMODE_AMD64:
3189	case PGMMODE_AMD64_NX: return PGM_TYPE_AMD64;
3190	case PGMMODE_NESTED: return PGM_TYPE_NESTED;
3191	case PGMMODE_EPT: return PGM_TYPE_EPT;
3192	default:
3193	AssertFatalMsgFailed(("pgmMode=%d\n", pgmMode));
3194	}
3195	}
3196
3197
3198	/**
3199	* Gets the index into the paging mode data array of a SHW+GST mode.
3200	*
3201	* @returns PGM::paPagingData index.
3202	* @param uShwType The shadow paging mode type.
3203	* @param uGstType The guest paging mode type.
3204	*/
3205	DECLINLINE(unsigned) pgmModeDataIndex(unsigned uShwType, unsigned uGstType)
3206	{
3207	Assert(uShwType >= PGM_TYPE_32BIT && uShwType <= PGM_TYPE_MAX);
3208	Assert(uGstType >= PGM_TYPE_REAL && uGstType <= PGM_TYPE_AMD64);
3209	return (uShwType - PGM_TYPE_32BIT) * (PGM_TYPE_AMD64 - PGM_TYPE_REAL + 1)
3210	+ (uGstType - PGM_TYPE_REAL);
3211	}
3212
3213
3214	/**
3215	* Gets the index into the paging mode data array of a SHW+GST mode.
3216	*
3217	* @returns PGM::paPagingData index.
3218	* @param enmShw The shadow paging mode.
3219	* @param enmGst The guest paging mode.
3220	*/
3221	DECLINLINE(unsigned) pgmModeDataIndexByMode(PGMMODE enmShw, PGMMODE enmGst)
3222	{
3223	Assert(enmShw >= PGMMODE_32_BIT && enmShw <= PGMMODE_MAX);
3224	Assert(enmGst > PGMMODE_INVALID && enmGst < PGMMODE_MAX);
3225	return pgmModeDataIndex(pgmModeToType(enmShw), pgmModeToType(enmGst));
3226	}
3227
3228
3229	/**
3230	* Calculates the max data index.
3231	* @returns The number of entries in the paging data array.
3232	*/
3233	DECLINLINE(unsigned) pgmModeDataMaxIndex(void)
3234	{
3235	return pgmModeDataIndex(PGM_TYPE_MAX, PGM_TYPE_AMD64) + 1;
3236	}
3237
3238
3239	/**
3240	* Initializes the paging mode data kept in PGM::paModeData.
3241	*
3242	* @param pVM The VM handle.
3243	* @param fResolveGCAndR0 Indicate whether or not GC and Ring-0 symbols can be resolved now.
3244	* This is used early in the init process to avoid trouble with PDM
3245	* not being initialized yet.
3246	*/
3247	static int pgmR3ModeDataInit(PVM pVM, bool fResolveGCAndR0)
3248	{
3249	PPGMMODEDATA pModeData;
3250	int rc;
3251
3252	/*
3253	* Allocate the array on the first call.
3254	*/
3255	if (!pVM->pgm.s.paModeData)
3256	{
3257	pVM->pgm.s.paModeData = (PPGMMODEDATA)MMR3HeapAllocZ(pVM, MM_TAG_PGM, sizeof(PGMMODEDATA) * pgmModeDataMaxIndex());
3258	AssertReturn(pVM->pgm.s.paModeData, VERR_NO_MEMORY);
3259	}
3260
3261	/*
3262	* Initialize the array entries.
3263	*/
3264	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_32BIT, PGM_TYPE_REAL)];
3265	pModeData->uShwType = PGM_TYPE_32BIT;
3266	pModeData->uGstType = PGM_TYPE_REAL;
3267	rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3268	rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3269	rc = PGM_BTH_NAME_32BIT_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3270
3271	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_32BIT, PGMMODE_PROTECTED)];
3272	pModeData->uShwType = PGM_TYPE_32BIT;
3273	pModeData->uGstType = PGM_TYPE_PROT;
3274	rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3275	rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3276	rc = PGM_BTH_NAME_32BIT_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3277
3278	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_32BIT, PGM_TYPE_32BIT)];
3279	pModeData->uShwType = PGM_TYPE_32BIT;
3280	pModeData->uGstType = PGM_TYPE_32BIT;
3281	rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3282	rc = PGM_GST_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3283	rc = PGM_BTH_NAME_32BIT_32BIT(InitData)(pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3284
3285	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_REAL)];
3286	pModeData->uShwType = PGM_TYPE_PAE;
3287	pModeData->uGstType = PGM_TYPE_REAL;
3288	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3289	rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3290	rc = PGM_BTH_NAME_PAE_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3291
3292	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_PROT)];
3293	pModeData->uShwType = PGM_TYPE_PAE;
3294	pModeData->uGstType = PGM_TYPE_PROT;
3295	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3296	rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3297	rc = PGM_BTH_NAME_PAE_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3298
3299	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_32BIT)];
3300	pModeData->uShwType = PGM_TYPE_PAE;
3301	pModeData->uGstType = PGM_TYPE_32BIT;
3302	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3303	rc = PGM_GST_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3304	rc = PGM_BTH_NAME_PAE_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3305
3306	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_PAE)];
3307	pModeData->uShwType = PGM_TYPE_PAE;
3308	pModeData->uGstType = PGM_TYPE_PAE;
3309	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3310	rc = PGM_GST_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3311	rc = PGM_BTH_NAME_PAE_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3312
3313	#ifdef VBOX_WITH_64_BITS_GUESTS
3314	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_AMD64, PGM_TYPE_AMD64)];
3315	pModeData->uShwType = PGM_TYPE_AMD64;
3316	pModeData->uGstType = PGM_TYPE_AMD64;
3317	rc = PGM_SHW_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3318	rc = PGM_GST_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3319	rc = PGM_BTH_NAME_AMD64_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3320	#endif
3321
3322	/* The nested paging mode. */
3323	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_REAL)];
3324	pModeData->uShwType = PGM_TYPE_NESTED;
3325	pModeData->uGstType = PGM_TYPE_REAL;
3326	rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3327	rc = PGM_BTH_NAME_NESTED_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3328
3329	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGMMODE_PROTECTED)];
3330	pModeData->uShwType = PGM_TYPE_NESTED;
3331	pModeData->uGstType = PGM_TYPE_PROT;
3332	rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3333	rc = PGM_BTH_NAME_NESTED_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3334
3335	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_32BIT)];
3336	pModeData->uShwType = PGM_TYPE_NESTED;
3337	pModeData->uGstType = PGM_TYPE_32BIT;
3338	rc = PGM_GST_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3339	rc = PGM_BTH_NAME_NESTED_32BIT(InitData)(pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3340
3341	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_PAE)];
3342	pModeData->uShwType = PGM_TYPE_NESTED;
3343	pModeData->uGstType = PGM_TYPE_PAE;
3344	rc = PGM_GST_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3345	rc = PGM_BTH_NAME_NESTED_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3346
3347	#ifdef VBOX_WITH_64_BITS_GUESTS
3348	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_AMD64)];
3349	pModeData->uShwType = PGM_TYPE_NESTED;
3350	pModeData->uGstType = PGM_TYPE_AMD64;
3351	rc = PGM_GST_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3352	rc = PGM_BTH_NAME_NESTED_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3353	#endif
3354
3355	/* The shadow part of the nested callback mode depends on the host paging mode (AMD-V only). */
3356	switch (pVM->pgm.s.enmHostMode)
3357	{
3358	#if HC_ARCH_BITS == 32
3359	case SUPPAGINGMODE_32_BIT:
3360	case SUPPAGINGMODE_32_BIT_GLOBAL:
3361	for (unsigned i = PGM_TYPE_REAL; i <= PGM_TYPE_PAE; i++)
3362	{
3363	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, i)];
3364	rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3365	}
3366	# ifdef VBOX_WITH_64_BITS_GUESTS
3367	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_AMD64)];
3368	rc = PGM_SHW_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3369	# endif
3370	break;
3371
3372	case SUPPAGINGMODE_PAE:
3373	case SUPPAGINGMODE_PAE_NX:
3374	case SUPPAGINGMODE_PAE_GLOBAL:
3375	case SUPPAGINGMODE_PAE_GLOBAL_NX:
3376	for (unsigned i = PGM_TYPE_REAL; i <= PGM_TYPE_PAE; i++)
3377	{
3378	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, i)];
3379	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3380	}
3381	# ifdef VBOX_WITH_64_BITS_GUESTS
3382	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_AMD64)];
3383	rc = PGM_SHW_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3384	# endif
3385	break;
3386	#endif /* HC_ARCH_BITS == 32 */
3387
3388	#if HC_ARCH_BITS == 64 \|\| defined(RT_OS_DARWIN)
3389	case SUPPAGINGMODE_AMD64:
3390	case SUPPAGINGMODE_AMD64_GLOBAL:
3391	case SUPPAGINGMODE_AMD64_NX:
3392	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
3393	# ifdef VBOX_WITH_64_BITS_GUESTS
3394	for (unsigned i = PGM_TYPE_REAL; i <= PGM_TYPE_AMD64; i++)
3395	# else
3396	for (unsigned i = PGM_TYPE_REAL; i <= PGM_TYPE_PAE; i++)
3397	# endif
3398	{
3399	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, i)];
3400	rc = PGM_SHW_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3401	}
3402	break;
3403	#endif /* HC_ARCH_BITS == 64 \|\| RT_OS_DARWIN */
3404
3405	default:
3406	AssertFailed();
3407	break;
3408	}
3409
3410	/* Extended paging (EPT) / Intel VT-x */
3411	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_REAL)];
3412	pModeData->uShwType = PGM_TYPE_EPT;
3413	pModeData->uGstType = PGM_TYPE_REAL;
3414	rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3415	rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3416	rc = PGM_BTH_NAME_EPT_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3417
3418	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_PROT)];
3419	pModeData->uShwType = PGM_TYPE_EPT;
3420	pModeData->uGstType = PGM_TYPE_PROT;
3421	rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3422	rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3423	rc = PGM_BTH_NAME_EPT_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3424
3425	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_32BIT)];
3426	pModeData->uShwType = PGM_TYPE_EPT;
3427	pModeData->uGstType = PGM_TYPE_32BIT;
3428	rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3429	rc = PGM_GST_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3430	rc = PGM_BTH_NAME_EPT_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3431
3432	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_PAE)];
3433	pModeData->uShwType = PGM_TYPE_EPT;
3434	pModeData->uGstType = PGM_TYPE_PAE;
3435	rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3436	rc = PGM_GST_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3437	rc = PGM_BTH_NAME_EPT_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3438
3439	#ifdef VBOX_WITH_64_BITS_GUESTS
3440	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_AMD64)];
3441	pModeData->uShwType = PGM_TYPE_EPT;
3442	pModeData->uGstType = PGM_TYPE_AMD64;
3443	rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3444	rc = PGM_GST_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3445	rc = PGM_BTH_NAME_EPT_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3446	#endif
3447	return VINF_SUCCESS;
3448	}
3449
3450
3451	/**
3452	* Switch to different (or relocated in the relocate case) mode data.
3453	*
3454	* @param pVM The VM handle.
3455	* @param enmShw The the shadow paging mode.
3456	* @param enmGst The the guest paging mode.
3457	*/
3458	static void pgmR3ModeDataSwitch(PVM pVM, PGMMODE enmShw, PGMMODE enmGst)
3459	{
3460	PPGMMODEDATA pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndexByMode(enmShw, enmGst)];
3461
3462	Assert(pModeData->uGstType == pgmModeToType(enmGst));
3463	Assert(pModeData->uShwType == pgmModeToType(enmShw));
3464
3465	/* shadow */
3466	pVM->pgm.s.pfnR3ShwRelocate = pModeData->pfnR3ShwRelocate;
3467	pVM->pgm.s.pfnR3ShwExit = pModeData->pfnR3ShwExit;
3468	pVM->pgm.s.pfnR3ShwGetPage = pModeData->pfnR3ShwGetPage;
3469	Assert(pVM->pgm.s.pfnR3ShwGetPage);
3470	pVM->pgm.s.pfnR3ShwModifyPage = pModeData->pfnR3ShwModifyPage;
3471
3472	pVM->pgm.s.pfnRCShwGetPage = pModeData->pfnRCShwGetPage;
3473	pVM->pgm.s.pfnRCShwModifyPage = pModeData->pfnRCShwModifyPage;
3474
3475	pVM->pgm.s.pfnR0ShwGetPage = pModeData->pfnR0ShwGetPage;
3476	pVM->pgm.s.pfnR0ShwModifyPage = pModeData->pfnR0ShwModifyPage;
3477
3478
3479	/* guest */
3480	pVM->pgm.s.pfnR3GstRelocate = pModeData->pfnR3GstRelocate;
3481	pVM->pgm.s.pfnR3GstExit = pModeData->pfnR3GstExit;
3482	pVM->pgm.s.pfnR3GstGetPage = pModeData->pfnR3GstGetPage;
3483	Assert(pVM->pgm.s.pfnR3GstGetPage);
3484	pVM->pgm.s.pfnR3GstModifyPage = pModeData->pfnR3GstModifyPage;
3485	pVM->pgm.s.pfnR3GstGetPDE = pModeData->pfnR3GstGetPDE;
3486	pVM->pgm.s.pfnRCGstGetPage = pModeData->pfnRCGstGetPage;
3487	pVM->pgm.s.pfnRCGstModifyPage = pModeData->pfnRCGstModifyPage;
3488	pVM->pgm.s.pfnRCGstGetPDE = pModeData->pfnRCGstGetPDE;
3489	pVM->pgm.s.pfnR0GstGetPage = pModeData->pfnR0GstGetPage;
3490	pVM->pgm.s.pfnR0GstModifyPage = pModeData->pfnR0GstModifyPage;
3491	pVM->pgm.s.pfnR0GstGetPDE = pModeData->pfnR0GstGetPDE;
3492
3493	/* both */
3494	pVM->pgm.s.pfnR3BthRelocate = pModeData->pfnR3BthRelocate;
3495	pVM->pgm.s.pfnR3BthInvalidatePage = pModeData->pfnR3BthInvalidatePage;
3496	pVM->pgm.s.pfnR3BthSyncCR3 = pModeData->pfnR3BthSyncCR3;
3497	Assert(pVM->pgm.s.pfnR3BthSyncCR3);
3498	pVM->pgm.s.pfnR3BthSyncPage = pModeData->pfnR3BthSyncPage;
3499	pVM->pgm.s.pfnR3BthPrefetchPage = pModeData->pfnR3BthPrefetchPage;
3500	pVM->pgm.s.pfnR3BthVerifyAccessSyncPage = pModeData->pfnR3BthVerifyAccessSyncPage;
3501	#ifdef VBOX_STRICT
3502	pVM->pgm.s.pfnR3BthAssertCR3 = pModeData->pfnR3BthAssertCR3;
3503	#endif
3504	pVM->pgm.s.pfnR3BthMapCR3 = pModeData->pfnR3BthMapCR3;
3505	pVM->pgm.s.pfnR3BthUnmapCR3 = pModeData->pfnR3BthUnmapCR3;
3506
3507	pVM->pgm.s.pfnRCBthTrap0eHandler = pModeData->pfnRCBthTrap0eHandler;
3508	pVM->pgm.s.pfnRCBthInvalidatePage = pModeData->pfnRCBthInvalidatePage;
3509	pVM->pgm.s.pfnRCBthSyncCR3 = pModeData->pfnRCBthSyncCR3;
3510	pVM->pgm.s.pfnRCBthSyncPage = pModeData->pfnRCBthSyncPage;
3511	pVM->pgm.s.pfnRCBthPrefetchPage = pModeData->pfnRCBthPrefetchPage;
3512	pVM->pgm.s.pfnRCBthVerifyAccessSyncPage = pModeData->pfnRCBthVerifyAccessSyncPage;
3513	#ifdef VBOX_STRICT
3514	pVM->pgm.s.pfnRCBthAssertCR3 = pModeData->pfnRCBthAssertCR3;
3515	#endif
3516	pVM->pgm.s.pfnRCBthMapCR3 = pModeData->pfnRCBthMapCR3;
3517	pVM->pgm.s.pfnRCBthUnmapCR3 = pModeData->pfnRCBthUnmapCR3;
3518
3519	pVM->pgm.s.pfnR0BthTrap0eHandler = pModeData->pfnR0BthTrap0eHandler;
3520	pVM->pgm.s.pfnR0BthInvalidatePage = pModeData->pfnR0BthInvalidatePage;
3521	pVM->pgm.s.pfnR0BthSyncCR3 = pModeData->pfnR0BthSyncCR3;
3522	pVM->pgm.s.pfnR0BthSyncPage = pModeData->pfnR0BthSyncPage;
3523	pVM->pgm.s.pfnR0BthPrefetchPage = pModeData->pfnR0BthPrefetchPage;
3524	pVM->pgm.s.pfnR0BthVerifyAccessSyncPage = pModeData->pfnR0BthVerifyAccessSyncPage;
3525	#ifdef VBOX_STRICT
3526	pVM->pgm.s.pfnR0BthAssertCR3 = pModeData->pfnR0BthAssertCR3;
3527	#endif
3528	pVM->pgm.s.pfnR0BthMapCR3 = pModeData->pfnR0BthMapCR3;
3529	pVM->pgm.s.pfnR0BthUnmapCR3 = pModeData->pfnR0BthUnmapCR3;
3530	}
3531
3532
3533	/**
3534	* Calculates the shadow paging mode.
3535	*
3536	* @returns The shadow paging mode.
3537	* @param pVM VM handle.
3538	* @param enmGuestMode The guest mode.
3539	* @param enmHostMode The host mode.
3540	* @param enmShadowMode The current shadow mode.
3541	* @param penmSwitcher Where to store the switcher to use.
3542	* VMMSWITCHER_INVALID means no change.
3543	*/
3544	static PGMMODE pgmR3CalcShadowMode(PVM pVM, PGMMODE enmGuestMode, SUPPAGINGMODE enmHostMode, PGMMODE enmShadowMode, VMMSWITCHER *penmSwitcher)
3545	{
3546	VMMSWITCHER enmSwitcher = VMMSWITCHER_INVALID;
3547	switch (enmGuestMode)
3548	{
3549	/*
3550	* When switching to real or protected mode we don't change
3551	* anything since it's likely that we'll switch back pretty soon.
3552	*
3553	* During pgmR3InitPaging we'll end up here with PGMMODE_INVALID
3554	* and is supposed to determine which shadow paging and switcher to
3555	* use during init.
3556	*/
3557	case PGMMODE_REAL:
3558	case PGMMODE_PROTECTED:
3559	if ( enmShadowMode != PGMMODE_INVALID
3560	&& !HWACCMIsEnabled(pVM) /* always switch in hwaccm mode! */)
3561	break; /* (no change) */
3562
3563	switch (enmHostMode)
3564	{
3565	case SUPPAGINGMODE_32_BIT:
3566	case SUPPAGINGMODE_32_BIT_GLOBAL:
3567	enmShadowMode = PGMMODE_32_BIT;
3568	enmSwitcher = VMMSWITCHER_32_TO_32;
3569	break;
3570
3571	case SUPPAGINGMODE_PAE:
3572	case SUPPAGINGMODE_PAE_NX:
3573	case SUPPAGINGMODE_PAE_GLOBAL:
3574	case SUPPAGINGMODE_PAE_GLOBAL_NX:
3575	enmShadowMode = PGMMODE_PAE;
3576	enmSwitcher = VMMSWITCHER_PAE_TO_PAE;
3577	#ifdef DEBUG_bird
3578	if (RTEnvExist("VBOX_32BIT"))
3579	{
3580	enmShadowMode = PGMMODE_32_BIT;
3581	enmSwitcher = VMMSWITCHER_PAE_TO_32;
3582	}
3583	#endif
3584	break;
3585
3586	case SUPPAGINGMODE_AMD64:
3587	case SUPPAGINGMODE_AMD64_GLOBAL:
3588	case SUPPAGINGMODE_AMD64_NX:
3589	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
3590	enmShadowMode = PGMMODE_PAE;
3591	enmSwitcher = VMMSWITCHER_AMD64_TO_PAE;
3592	#ifdef DEBUG_bird
3593	if (RTEnvExist("VBOX_32BIT"))
3594	{
3595	enmShadowMode = PGMMODE_32_BIT;
3596	enmSwitcher = VMMSWITCHER_AMD64_TO_32;
3597	}
3598	#endif
3599	break;
3600
3601	default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
3602	}
3603	break;
3604
3605	case PGMMODE_32_BIT:
3606	switch (enmHostMode)
3607	{
3608	case SUPPAGINGMODE_32_BIT:
3609	case SUPPAGINGMODE_32_BIT_GLOBAL:
3610	enmShadowMode = PGMMODE_32_BIT;
3611	enmSwitcher = VMMSWITCHER_32_TO_32;
3612	break;
3613
3614	case SUPPAGINGMODE_PAE:
3615	case SUPPAGINGMODE_PAE_NX:
3616	case SUPPAGINGMODE_PAE_GLOBAL:
3617	case SUPPAGINGMODE_PAE_GLOBAL_NX:
3618	enmShadowMode = PGMMODE_PAE;
3619	enmSwitcher = VMMSWITCHER_PAE_TO_PAE;
3620	#ifdef DEBUG_bird
3621	if (RTEnvExist("VBOX_32BIT"))
3622	{
3623	enmShadowMode = PGMMODE_32_BIT;
3624	enmSwitcher = VMMSWITCHER_PAE_TO_32;
3625	}
3626	#endif
3627	break;
3628
3629	case SUPPAGINGMODE_AMD64:
3630	case SUPPAGINGMODE_AMD64_GLOBAL:
3631	case SUPPAGINGMODE_AMD64_NX:
3632	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
3633	enmShadowMode = PGMMODE_PAE;
3634	enmSwitcher = VMMSWITCHER_AMD64_TO_PAE;
3635	#ifdef DEBUG_bird
3636	if (RTEnvExist("VBOX_32BIT"))
3637	{
3638	enmShadowMode = PGMMODE_32_BIT;
3639	enmSwitcher = VMMSWITCHER_AMD64_TO_32;
3640	}
3641	#endif
3642	break;
3643
3644	default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
3645	}
3646	break;
3647
3648	case PGMMODE_PAE:
3649	case PGMMODE_PAE_NX: /** @todo This might require more switchers and guest+both modes. */
3650	switch (enmHostMode)
3651	{
3652	case SUPPAGINGMODE_32_BIT:
3653	case SUPPAGINGMODE_32_BIT_GLOBAL:
3654	enmShadowMode = PGMMODE_PAE;
3655	enmSwitcher = VMMSWITCHER_32_TO_PAE;
3656	break;
3657
3658	case SUPPAGINGMODE_PAE:
3659	case SUPPAGINGMODE_PAE_NX:
3660	case SUPPAGINGMODE_PAE_GLOBAL:
3661	case SUPPAGINGMODE_PAE_GLOBAL_NX:
3662	enmShadowMode = PGMMODE_PAE;
3663	enmSwitcher = VMMSWITCHER_PAE_TO_PAE;
3664	break;
3665
3666	case SUPPAGINGMODE_AMD64:
3667	case SUPPAGINGMODE_AMD64_GLOBAL:
3668	case SUPPAGINGMODE_AMD64_NX:
3669	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
3670	enmShadowMode = PGMMODE_PAE;
3671	enmSwitcher = VMMSWITCHER_AMD64_TO_PAE;
3672	break;
3673
3674	default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
3675	}
3676	break;
3677
3678	case PGMMODE_AMD64:
3679	case PGMMODE_AMD64_NX:
3680	switch (enmHostMode)
3681	{
3682	case SUPPAGINGMODE_32_BIT:
3683	case SUPPAGINGMODE_32_BIT_GLOBAL:
3684	enmShadowMode = PGMMODE_AMD64;
3685	enmSwitcher = VMMSWITCHER_32_TO_AMD64;
3686	break;
3687
3688	case SUPPAGINGMODE_PAE:
3689	case SUPPAGINGMODE_PAE_NX:
3690	case SUPPAGINGMODE_PAE_GLOBAL:
3691	case SUPPAGINGMODE_PAE_GLOBAL_NX:
3692	enmShadowMode = PGMMODE_AMD64;
3693	enmSwitcher = VMMSWITCHER_PAE_TO_AMD64;
3694	break;
3695
3696	case SUPPAGINGMODE_AMD64:
3697	case SUPPAGINGMODE_AMD64_GLOBAL:
3698	case SUPPAGINGMODE_AMD64_NX:
3699	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
3700	enmShadowMode = PGMMODE_AMD64;
3701	enmSwitcher = VMMSWITCHER_AMD64_TO_AMD64;
3702	break;
3703
3704	default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
3705	}
3706	break;
3707
3708
3709	default:
3710	AssertReleaseMsgFailed(("enmGuestMode=%d\n", enmGuestMode));
3711	return PGMMODE_INVALID;
3712	}
3713	/* Override the shadow mode is nested paging is active. */
3714	if (HWACCMIsNestedPagingActive(pVM))
3715	enmShadowMode = HWACCMGetShwPagingMode(pVM);
3716
3717	*penmSwitcher = enmSwitcher;
3718	return enmShadowMode;
3719	}
3720
3721
3722	/**
3723	* Performs the actual mode change.
3724	* This is called by PGMChangeMode and pgmR3InitPaging().
3725	*
3726	* @returns VBox status code.
3727	* @param pVM VM handle.
3728	* @param enmGuestMode The new guest mode. This is assumed to be different from
3729	* the current mode.
3730	*/
3731	VMMR3DECL(int) PGMR3ChangeMode(PVM pVM, PGMMODE enmGuestMode)
3732	{
3733	Log(("PGMR3ChangeMode: Guest mode: %s -> %s\n", PGMGetModeName(pVM->pgm.s.enmGuestMode), PGMGetModeName(enmGuestMode)));
3734	STAM_REL_COUNTER_INC(&pVM->pgm.s.cGuestModeChanges);
3735
3736	/*
3737	* Calc the shadow mode and switcher.
3738	*/
3739	VMMSWITCHER enmSwitcher;
3740	PGMMODE enmShadowMode = pgmR3CalcShadowMode(pVM, enmGuestMode, pVM->pgm.s.enmHostMode, pVM->pgm.s.enmShadowMode, &enmSwitcher);
3741	if (enmSwitcher != VMMSWITCHER_INVALID)
3742	{
3743	/*
3744	* Select new switcher.
3745	*/
3746	int rc = VMMR3SelectSwitcher(pVM, enmSwitcher);
3747	if (RT_FAILURE(rc))
3748	{
3749	AssertReleaseMsgFailed(("VMMR3SelectSwitcher(%d) -> %Rrc\n", enmSwitcher, rc));
3750	return rc;
3751	}
3752	}
3753
3754	/*
3755	* Exit old mode(s).
3756	*/
3757	/* shadow */
3758	if (enmShadowMode != pVM->pgm.s.enmShadowMode)
3759	{
3760	LogFlow(("PGMR3ChangeMode: Shadow mode: %s -> %s\n", PGMGetModeName(pVM->pgm.s.enmShadowMode), PGMGetModeName(enmShadowMode)));
3761	if (PGM_SHW_PFN(Exit, pVM))
3762	{
3763	int rc = PGM_SHW_PFN(Exit, pVM)(pVM);
3764	if (RT_FAILURE(rc))
3765	{
3766	AssertMsgFailed(("Exit failed for shadow mode %d: %Rrc\n", pVM->pgm.s.enmShadowMode, rc));
3767	return rc;
3768	}
3769	}
3770
3771	}
3772	else
3773	LogFlow(("PGMR3ChangeMode: Shadow mode remains: %s\n", PGMGetModeName(pVM->pgm.s.enmShadowMode)));
3774
3775	/* guest */
3776	if (PGM_GST_PFN(Exit, pVM))
3777	{
3778	int rc = PGM_GST_PFN(Exit, pVM)(pVM);
3779	if (RT_FAILURE(rc))
3780	{
3781	AssertMsgFailed(("Exit failed for guest mode %d: %Rrc\n", pVM->pgm.s.enmGuestMode, rc));
3782	return rc;
3783	}
3784	}
3785
3786	/*
3787	* Load new paging mode data.
3788	*/
3789	pgmR3ModeDataSwitch(pVM, enmShadowMode, enmGuestMode);
3790
3791	/*
3792	* Enter new shadow mode (if changed).
3793	*/
3794	if (enmShadowMode != pVM->pgm.s.enmShadowMode)
3795	{
3796	int rc;
3797	pVM->pgm.s.enmShadowMode = enmShadowMode;
3798	switch (enmShadowMode)
3799	{
3800	case PGMMODE_32_BIT:
3801	rc = PGM_SHW_NAME_32BIT(Enter)(pVM);
3802	break;
3803	case PGMMODE_PAE:
3804	case PGMMODE_PAE_NX:
3805	rc = PGM_SHW_NAME_PAE(Enter)(pVM);
3806	break;
3807	case PGMMODE_AMD64:
3808	case PGMMODE_AMD64_NX:
3809	rc = PGM_SHW_NAME_AMD64(Enter)(pVM);
3810	break;
3811	case PGMMODE_NESTED:
3812	rc = PGM_SHW_NAME_NESTED(Enter)(pVM);
3813	break;
3814	case PGMMODE_EPT:
3815	rc = PGM_SHW_NAME_EPT(Enter)(pVM);
3816	break;
3817	case PGMMODE_REAL:
3818	case PGMMODE_PROTECTED:
3819	default:
3820	AssertReleaseMsgFailed(("enmShadowMode=%d\n", enmShadowMode));
3821	return VERR_INTERNAL_ERROR;
3822	}
3823	if (RT_FAILURE(rc))
3824	{
3825	AssertReleaseMsgFailed(("Entering enmShadowMode=%d failed: %Rrc\n", enmShadowMode, rc));
3826	pVM->pgm.s.enmShadowMode = PGMMODE_INVALID;
3827	return rc;
3828	}
3829	}
3830
3831	/*
3832	* Always flag the necessary updates
3833	*/
3834	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
3835
3836	/*
3837	* Enter the new guest and shadow+guest modes.
3838	*/
3839	int rc = -1;
3840	int rc2 = -1;
3841	RTGCPHYS GCPhysCR3 = NIL_RTGCPHYS;
3842	pVM->pgm.s.enmGuestMode = enmGuestMode;
3843	switch (enmGuestMode)
3844	{
3845	case PGMMODE_REAL:
3846	rc = PGM_GST_NAME_REAL(Enter)(pVM, NIL_RTGCPHYS);
3847	switch (pVM->pgm.s.enmShadowMode)
3848	{
3849	case PGMMODE_32_BIT:
3850	rc2 = PGM_BTH_NAME_32BIT_REAL(Enter)(pVM, NIL_RTGCPHYS);
3851	break;
3852	case PGMMODE_PAE:
3853	case PGMMODE_PAE_NX:
3854	rc2 = PGM_BTH_NAME_PAE_REAL(Enter)(pVM, NIL_RTGCPHYS);
3855	break;
3856	case PGMMODE_NESTED:
3857	rc2 = PGM_BTH_NAME_NESTED_REAL(Enter)(pVM, NIL_RTGCPHYS);
3858	break;
3859	case PGMMODE_EPT:
3860	rc2 = PGM_BTH_NAME_EPT_REAL(Enter)(pVM, NIL_RTGCPHYS);
3861	break;
3862	case PGMMODE_AMD64:
3863	case PGMMODE_AMD64_NX:
3864	AssertMsgFailed(("Should use PAE shadow mode!\n"));
3865	default: AssertFailed(); break;
3866	}
3867	break;
3868
3869	case PGMMODE_PROTECTED:
3870	rc = PGM_GST_NAME_PROT(Enter)(pVM, NIL_RTGCPHYS);
3871	switch (pVM->pgm.s.enmShadowMode)
3872	{
3873	case PGMMODE_32_BIT:
3874	rc2 = PGM_BTH_NAME_32BIT_PROT(Enter)(pVM, NIL_RTGCPHYS);
3875	break;
3876	case PGMMODE_PAE:
3877	case PGMMODE_PAE_NX:
3878	rc2 = PGM_BTH_NAME_PAE_PROT(Enter)(pVM, NIL_RTGCPHYS);
3879	break;
3880	case PGMMODE_NESTED:
3881	rc2 = PGM_BTH_NAME_NESTED_PROT(Enter)(pVM, NIL_RTGCPHYS);
3882	break;
3883	case PGMMODE_EPT:
3884	rc2 = PGM_BTH_NAME_EPT_PROT(Enter)(pVM, NIL_RTGCPHYS);
3885	break;
3886	case PGMMODE_AMD64:
3887	case PGMMODE_AMD64_NX:
3888	AssertMsgFailed(("Should use PAE shadow mode!\n"));
3889	default: AssertFailed(); break;
3890	}
3891	break;
3892
3893	case PGMMODE_32_BIT:
3894	GCPhysCR3 = CPUMGetGuestCR3(pVM) & X86_CR3_PAGE_MASK;
3895	rc = PGM_GST_NAME_32BIT(Enter)(pVM, GCPhysCR3);
3896	switch (pVM->pgm.s.enmShadowMode)
3897	{
3898	case PGMMODE_32_BIT:
3899	rc2 = PGM_BTH_NAME_32BIT_32BIT(Enter)(pVM, GCPhysCR3);
3900	break;
3901	case PGMMODE_PAE:
3902	case PGMMODE_PAE_NX:
3903	rc2 = PGM_BTH_NAME_PAE_32BIT(Enter)(pVM, GCPhysCR3);
3904	break;
3905	case PGMMODE_NESTED:
3906	rc2 = PGM_BTH_NAME_NESTED_32BIT(Enter)(pVM, GCPhysCR3);
3907	break;
3908	case PGMMODE_EPT:
3909	rc2 = PGM_BTH_NAME_EPT_32BIT(Enter)(pVM, GCPhysCR3);
3910	break;
3911	case PGMMODE_AMD64:
3912	case PGMMODE_AMD64_NX:
3913	AssertMsgFailed(("Should use PAE shadow mode!\n"));
3914	default: AssertFailed(); break;
3915	}
3916	break;
3917
3918	case PGMMODE_PAE_NX:
3919	case PGMMODE_PAE:
3920	{
3921	uint32_t u32Dummy, u32Features;
3922
3923	CPUMGetGuestCpuId(pVM, 1, &u32Dummy, &u32Dummy, &u32Dummy, &u32Features);
3924	if (!(u32Features & X86_CPUID_FEATURE_EDX_PAE))
3925	{
3926	/* Pause first, then inform Main. */
3927	rc = VMR3SuspendNoSave(pVM);
3928	AssertRC(rc);
3929
3930	VMSetRuntimeError(pVM, true, "PAEmode",
3931	N_("The guest is trying to switch to the PAE mode which is currently disabled by default in VirtualBox. PAE support can be enabled using the VM settings (General/Advanced)"));
3932	/* we must return VINF_SUCCESS here otherwise the recompiler will assert */
3933	return VINF_SUCCESS;
3934	}
3935	GCPhysCR3 = CPUMGetGuestCR3(pVM) & X86_CR3_PAE_PAGE_MASK;
3936	rc = PGM_GST_NAME_PAE(Enter)(pVM, GCPhysCR3);
3937	switch (pVM->pgm.s.enmShadowMode)
3938	{
3939	case PGMMODE_PAE:
3940	case PGMMODE_PAE_NX:
3941	rc2 = PGM_BTH_NAME_PAE_PAE(Enter)(pVM, GCPhysCR3);
3942	break;
3943	case PGMMODE_NESTED:
3944	rc2 = PGM_BTH_NAME_NESTED_PAE(Enter)(pVM, GCPhysCR3);
3945	break;
3946	case PGMMODE_EPT:
3947	rc2 = PGM_BTH_NAME_EPT_PAE(Enter)(pVM, GCPhysCR3);
3948	break;
3949	case PGMMODE_32_BIT:
3950	case PGMMODE_AMD64:
3951	case PGMMODE_AMD64_NX:
3952	AssertMsgFailed(("Should use PAE shadow mode!\n"));
3953	default: AssertFailed(); break;
3954	}
3955	break;
3956	}
3957
3958	#ifdef VBOX_WITH_64_BITS_GUESTS
3959	case PGMMODE_AMD64_NX:
3960	case PGMMODE_AMD64:
3961	GCPhysCR3 = CPUMGetGuestCR3(pVM) & UINT64_C(0xfffffffffffff000); /** @todo define this mask! */
3962	rc = PGM_GST_NAME_AMD64(Enter)(pVM, GCPhysCR3);
3963	switch (pVM->pgm.s.enmShadowMode)
3964	{
3965	case PGMMODE_AMD64:
3966	case PGMMODE_AMD64_NX:
3967	rc2 = PGM_BTH_NAME_AMD64_AMD64(Enter)(pVM, GCPhysCR3);
3968	break;
3969	case PGMMODE_NESTED:
3970	rc2 = PGM_BTH_NAME_NESTED_AMD64(Enter)(pVM, GCPhysCR3);
3971	break;
3972	case PGMMODE_EPT:
3973	rc2 = PGM_BTH_NAME_EPT_AMD64(Enter)(pVM, GCPhysCR3);
3974	break;
3975	case PGMMODE_32_BIT:
3976	case PGMMODE_PAE:
3977	case PGMMODE_PAE_NX:
3978	AssertMsgFailed(("Should use AMD64 shadow mode!\n"));
3979	default: AssertFailed(); break;
3980	}
3981	break;
3982	#endif
3983
3984	default:
3985	AssertReleaseMsgFailed(("enmGuestMode=%d\n", enmGuestMode));
3986	rc = VERR_NOT_IMPLEMENTED;
3987	break;
3988	}
3989
3990	/* status codes. */
3991	AssertRC(rc);
3992	AssertRC(rc2);
3993	if (RT_SUCCESS(rc))
3994	{
3995	rc = rc2;
3996	if (RT_SUCCESS(rc)) /* no informational status codes. */
3997	rc = VINF_SUCCESS;
3998	}
3999
4000	/* Notify HWACCM as well. */
4001	HWACCMR3PagingModeChanged(pVM, pVM->pgm.s.enmShadowMode, pVM->pgm.s.enmGuestMode);
4002	return rc;
4003	}
4004
4005
4006	/**
4007	* Dumps a PAE shadow page table.
4008	*
4009	* @returns VBox status code (VINF_SUCCESS).
4010	* @param pVM The VM handle.
4011	* @param pPT Pointer to the page table.
4012	* @param u64Address The virtual address of the page table starts.
4013	* @param fLongMode Set if this a long mode table; clear if it's a legacy mode table.
4014	* @param cMaxDepth The maxium depth.
4015	* @param pHlp Pointer to the output functions.
4016	*/
4017	static int pgmR3DumpHierarchyHCPaePT(PVM pVM, PX86PTPAE pPT, uint64_t u64Address, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
4018	{
4019	for (unsigned i = 0; i < RT_ELEMENTS(pPT->a); i++)
4020	{
4021	X86PTEPAE Pte = pPT->a[i];
4022	if (Pte.n.u1Present)
4023	{
4024	pHlp->pfnPrintf(pHlp,
4025	fLongMode /P R S A D G WT CD AT NX 4M a p ? /
4026	? "%016llx 3 \| P %c %c %c %c %c %s %s %s %s 4K %c%c%c %016llx\n"
4027	: "%08llx 2 \| P %c %c %c %c %c %s %s %s %s 4K %c%c%c %016llx\n",
4028	u64Address + ((uint64_t)i << X86_PT_PAE_SHIFT),
4029	Pte.n.u1Write ? 'W' : 'R',
4030	Pte.n.u1User ? 'U' : 'S',
4031	Pte.n.u1Accessed ? 'A' : '-',
4032	Pte.n.u1Dirty ? 'D' : '-',
4033	Pte.n.u1Global ? 'G' : '-',
4034	Pte.n.u1WriteThru ? "WT" : "--",
4035	Pte.n.u1CacheDisable? "CD" : "--",
4036	Pte.n.u1PAT ? "AT" : "--",
4037	Pte.n.u1NoExecute ? "NX" : "--",
4038	Pte.u & PGM_PTFLAGS_TRACK_DIRTY ? 'd' : '-',
4039	Pte.u & RT_BIT(10) ? '1' : '0',
4040	Pte.u & PGM_PTFLAGS_CSAM_VALIDATED? 'v' : '-',
4041	Pte.u & X86_PTE_PAE_PG_MASK);
4042	}
4043	}
4044	return VINF_SUCCESS;
4045	}
4046
4047
4048	/**
4049	* Dumps a PAE shadow page directory table.
4050	*
4051	* @returns VBox status code (VINF_SUCCESS).
4052	* @param pVM The VM handle.
4053	* @param HCPhys The physical address of the page directory table.
4054	* @param u64Address The virtual address of the page table starts.
4055	* @param cr4 The CR4, PSE is currently used.
4056	* @param fLongMode Set if this a long mode table; clear if it's a legacy mode table.
4057	* @param cMaxDepth The maxium depth.
4058	* @param pHlp Pointer to the output functions.
4059	*/
4060	static int pgmR3DumpHierarchyHCPaePD(PVM pVM, RTHCPHYS HCPhys, uint64_t u64Address, uint32_t cr4, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
4061	{
4062	PX86PDPAE pPD = (PX86PDPAE)MMPagePhys2Page(pVM, HCPhys);
4063	if (!pPD)
4064	{
4065	pHlp->pfnPrintf(pHlp, "%0*llx error! Page directory at HCPhys=%RHp was not found in the page pool!\n",
4066	fLongMode ? 16 : 8, u64Address, HCPhys);
4067	return VERR_INVALID_PARAMETER;
4068	}
4069	const bool fBigPagesSupported = fLongMode \|\| !!(cr4 & X86_CR4_PSE);
4070
4071	int rc = VINF_SUCCESS;
4072	for (unsigned i = 0; i < RT_ELEMENTS(pPD->a); i++)
4073	{
4074	X86PDEPAE Pde = pPD->a[i];
4075	if (Pde.n.u1Present)
4076	{
4077	if (fBigPagesSupported && Pde.b.u1Size)
4078	pHlp->pfnPrintf(pHlp,
4079	fLongMode /P R S A D G WT CD AT NX 4M a p ? /
4080	? "%016llx 2 \| P %c %c %c %c %c %s %s %s %s 4M %c%c%c %016llx\n"
4081	: "%08llx 1 \| P %c %c %c %c %c %s %s %s %s 4M %c%c%c %016llx\n",
4082	u64Address + ((uint64_t)i << X86_PD_PAE_SHIFT),
4083	Pde.b.u1Write ? 'W' : 'R',
4084	Pde.b.u1User ? 'U' : 'S',
4085	Pde.b.u1Accessed ? 'A' : '-',
4086	Pde.b.u1Dirty ? 'D' : '-',
4087	Pde.b.u1Global ? 'G' : '-',
4088	Pde.b.u1WriteThru ? "WT" : "--",
4089	Pde.b.u1CacheDisable? "CD" : "--",
4090	Pde.b.u1PAT ? "AT" : "--",
4091	Pde.b.u1NoExecute ? "NX" : "--",
4092	Pde.u & RT_BIT_64(9) ? '1' : '0',
4093	Pde.u & PGM_PDFLAGS_MAPPING ? 'm' : '-',
4094	Pde.u & PGM_PDFLAGS_TRACK_DIRTY ? 'd' : '-',
4095	Pde.u & X86_PDE_PAE_PG_MASK);
4096	else
4097	{
4098	pHlp->pfnPrintf(pHlp,
4099	fLongMode /P R S A D G WT CD AT NX 4M a p ? /
4100	? "%016llx 2 \| P %c %c %c %c %c %s %s .. %s 4K %c%c%c %016llx\n"
4101	: "%08llx 1 \| P %c %c %c %c %c %s %s .. %s 4K %c%c%c %016llx\n",
4102	u64Address + ((uint64_t)i << X86_PD_PAE_SHIFT),
4103	Pde.n.u1Write ? 'W' : 'R',
4104	Pde.n.u1User ? 'U' : 'S',
4105	Pde.n.u1Accessed ? 'A' : '-',
4106	Pde.n.u1Reserved0 ? '?' : '.', /* ignored */
4107	Pde.n.u1Reserved1 ? '?' : '.', /* ignored */
4108	Pde.n.u1WriteThru ? "WT" : "--",
4109	Pde.n.u1CacheDisable? "CD" : "--",
4110	Pde.n.u1NoExecute ? "NX" : "--",
4111	Pde.u & RT_BIT_64(9) ? '1' : '0',
4112	Pde.u & PGM_PDFLAGS_MAPPING ? 'm' : '-',
4113	Pde.u & PGM_PDFLAGS_TRACK_DIRTY ? 'd' : '-',
4114	Pde.u & X86_PDE_PAE_PG_MASK);
4115	if (cMaxDepth >= 1)
4116	{
4117	/** @todo what about using the page pool for mapping PTs? */
4118	uint64_t u64AddressPT = u64Address + ((uint64_t)i << X86_PD_PAE_SHIFT);
4119	RTHCPHYS HCPhysPT = Pde.u & X86_PDE_PAE_PG_MASK;
4120	PX86PTPAE pPT = NULL;
4121	if (!(Pde.u & PGM_PDFLAGS_MAPPING))
4122	pPT = (PX86PTPAE)MMPagePhys2Page(pVM, HCPhysPT);
4123	else
4124	{
4125	for (PPGMMAPPING pMap = pVM->pgm.s.pMappingsR3; pMap; pMap = pMap->pNextR3)
4126	{
4127	uint64_t off = u64AddressPT - pMap->GCPtr;
4128	if (off < pMap->cb)
4129	{
4130	const int iPDE = (uint32_t)(off >> X86_PD_SHIFT);
4131	const int iSub = (int)((off >> X86_PD_PAE_SHIFT) & 1); /* MSC is a pain sometimes */
4132	if ((iSub ? pMap->aPTs[iPDE].HCPhysPaePT1 : pMap->aPTs[iPDE].HCPhysPaePT0) != HCPhysPT)
4133	pHlp->pfnPrintf(pHlp, "%0*llx error! Mapping error! PT %d has HCPhysPT=%RHp not %RHp is in the PD.\n",
4134	fLongMode ? 16 : 8, u64AddressPT, iPDE,
4135	iSub ? pMap->aPTs[iPDE].HCPhysPaePT1 : pMap->aPTs[iPDE].HCPhysPaePT0, HCPhysPT);
4136	pPT = &pMap->aPTs[iPDE].paPaePTsR3[iSub];
4137	}
4138	}
4139	}
4140	int rc2 = VERR_INVALID_PARAMETER;
4141	if (pPT)
4142	rc2 = pgmR3DumpHierarchyHCPaePT(pVM, pPT, u64AddressPT, fLongMode, cMaxDepth - 1, pHlp);
4143	else
4144	pHlp->pfnPrintf(pHlp, "%0*llx error! Page table at HCPhys=%RHp was not found in the page pool!\n",
4145	fLongMode ? 16 : 8, u64AddressPT, HCPhysPT);
4146	if (rc2 < rc && RT_SUCCESS(rc))
4147	rc = rc2;
4148	}
4149	}
4150	}
4151	}
4152	return rc;
4153	}
4154
4155
4156	/**
4157	* Dumps a PAE shadow page directory pointer table.
4158	*
4159	* @returns VBox status code (VINF_SUCCESS).
4160	* @param pVM The VM handle.
4161	* @param HCPhys The physical address of the page directory pointer table.
4162	* @param u64Address The virtual address of the page table starts.
4163	* @param cr4 The CR4, PSE is currently used.
4164	* @param fLongMode Set if this a long mode table; clear if it's a legacy mode table.
4165	* @param cMaxDepth The maxium depth.
4166	* @param pHlp Pointer to the output functions.
4167	*/
4168	static int pgmR3DumpHierarchyHCPaePDPT(PVM pVM, RTHCPHYS HCPhys, uint64_t u64Address, uint32_t cr4, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
4169	{
4170	PX86PDPT pPDPT = (PX86PDPT)MMPagePhys2Page(pVM, HCPhys);
4171	if (!pPDPT)
4172	{
4173	pHlp->pfnPrintf(pHlp, "%0*llx error! Page directory pointer table at HCPhys=%RHp was not found in the page pool!\n",
4174	fLongMode ? 16 : 8, u64Address, HCPhys);
4175	return VERR_INVALID_PARAMETER;
4176	}
4177
4178	int rc = VINF_SUCCESS;
4179	const unsigned c = fLongMode ? RT_ELEMENTS(pPDPT->a) : X86_PG_PAE_PDPE_ENTRIES;
4180	for (unsigned i = 0; i < c; i++)
4181	{
4182	X86PDPE Pdpe = pPDPT->a[i];
4183	if (Pdpe.n.u1Present)
4184	{
4185	if (fLongMode)
4186	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a p ? /
4187	"%016llx 1 \| P %c %c %c %c %c %s %s %s %s .. %c%c%c %016llx\n",
4188	u64Address + ((uint64_t)i << X86_PDPT_SHIFT),
4189	Pdpe.lm.u1Write ? 'W' : 'R',
4190	Pdpe.lm.u1User ? 'U' : 'S',
4191	Pdpe.lm.u1Accessed ? 'A' : '-',
4192	Pdpe.lm.u3Reserved & 1? '?' : '.', /* ignored */
4193	Pdpe.lm.u3Reserved & 4? '!' : '.', /* mbz */
4194	Pdpe.lm.u1WriteThru ? "WT" : "--",
4195	Pdpe.lm.u1CacheDisable? "CD" : "--",
4196	Pdpe.lm.u3Reserved & 2? "!" : "..",/* mbz */
4197	Pdpe.lm.u1NoExecute ? "NX" : "--",
4198	Pdpe.u & RT_BIT(9) ? '1' : '0',
4199	Pdpe.u & PGM_PLXFLAGS_PERMANENT ? 'p' : '-',
4200	Pdpe.u & RT_BIT(11) ? '1' : '0',
4201	Pdpe.u & X86_PDPE_PG_MASK);
4202	else
4203	pHlp->pfnPrintf(pHlp, /P G WT CD AT NX 4M a p ? /
4204	"%08x 0 \| P %c %s %s %s %s .. %c%c%c %016llx\n",
4205	i << X86_PDPT_SHIFT,
4206	Pdpe.n.u4Reserved & 1? '!' : '.', /* mbz */
4207	Pdpe.n.u4Reserved & 4? '!' : '.', /* mbz */
4208	Pdpe.n.u1WriteThru ? "WT" : "--",
4209	Pdpe.n.u1CacheDisable? "CD" : "--",
4210	Pdpe.n.u4Reserved & 2? "!" : "..",/* mbz */
4211	Pdpe.u & RT_BIT(9) ? '1' : '0',
4212	Pdpe.u & PGM_PLXFLAGS_PERMANENT ? 'p' : '-',
4213	Pdpe.u & RT_BIT(11) ? '1' : '0',
4214	Pdpe.u & X86_PDPE_PG_MASK);
4215	if (cMaxDepth >= 1)
4216	{
4217	int rc2 = pgmR3DumpHierarchyHCPaePD(pVM, Pdpe.u & X86_PDPE_PG_MASK, u64Address + ((uint64_t)i << X86_PDPT_SHIFT),
4218	cr4, fLongMode, cMaxDepth - 1, pHlp);
4219	if (rc2 < rc && RT_SUCCESS(rc))
4220	rc = rc2;
4221	}
4222	}
4223	}
4224	return rc;
4225	}
4226
4227
4228	/**
4229	* Dumps a 32-bit shadow page table.
4230	*
4231	* @returns VBox status code (VINF_SUCCESS).
4232	* @param pVM The VM handle.
4233	* @param HCPhys The physical address of the table.
4234	* @param cr4 The CR4, PSE is currently used.
4235	* @param cMaxDepth The maxium depth.
4236	* @param pHlp Pointer to the output functions.
4237	*/
4238	static int pgmR3DumpHierarchyHcPaePML4(PVM pVM, RTHCPHYS HCPhys, uint32_t cr4, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
4239	{
4240	PX86PML4 pPML4 = (PX86PML4)MMPagePhys2Page(pVM, HCPhys);
4241	if (!pPML4)
4242	{
4243	pHlp->pfnPrintf(pHlp, "Page map level 4 at HCPhys=%RHp was not found in the page pool!\n", HCPhys);
4244	return VERR_INVALID_PARAMETER;
4245	}
4246
4247	int rc = VINF_SUCCESS;
4248	for (unsigned i = 0; i < RT_ELEMENTS(pPML4->a); i++)
4249	{
4250	X86PML4E Pml4e = pPML4->a[i];
4251	if (Pml4e.n.u1Present)
4252	{
4253	uint64_t u64Address = ((uint64_t)i << X86_PML4_SHIFT) \| (((uint64_t)i >> (X86_PML4_SHIFT - X86_PDPT_SHIFT - 1)) * 0xffff000000000000ULL);
4254	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a p ? /
4255	"%016llx 0 \| P %c %c %c %c %c %s %s %s %s .. %c%c%c %016llx\n",
4256	u64Address,
4257	Pml4e.n.u1Write ? 'W' : 'R',
4258	Pml4e.n.u1User ? 'U' : 'S',
4259	Pml4e.n.u1Accessed ? 'A' : '-',
4260	Pml4e.n.u3Reserved & 1? '?' : '.', /* ignored */
4261	Pml4e.n.u3Reserved & 4? '!' : '.', /* mbz */
4262	Pml4e.n.u1WriteThru ? "WT" : "--",
4263	Pml4e.n.u1CacheDisable? "CD" : "--",
4264	Pml4e.n.u3Reserved & 2? "!" : "..",/* mbz */
4265	Pml4e.n.u1NoExecute ? "NX" : "--",
4266	Pml4e.u & RT_BIT(9) ? '1' : '0',
4267	Pml4e.u & PGM_PLXFLAGS_PERMANENT ? 'p' : '-',
4268	Pml4e.u & RT_BIT(11) ? '1' : '0',
4269	Pml4e.u & X86_PML4E_PG_MASK);
4270
4271	if (cMaxDepth >= 1)
4272	{
4273	int rc2 = pgmR3DumpHierarchyHCPaePDPT(pVM, Pml4e.u & X86_PML4E_PG_MASK, u64Address, cr4, true, cMaxDepth - 1, pHlp);
4274	if (rc2 < rc && RT_SUCCESS(rc))
4275	rc = rc2;
4276	}
4277	}
4278	}
4279	return rc;
4280	}
4281
4282
4283	/**
4284	* Dumps a 32-bit shadow page table.
4285	*
4286	* @returns VBox status code (VINF_SUCCESS).
4287	* @param pVM The VM handle.
4288	* @param pPT Pointer to the page table.
4289	* @param u32Address The virtual address this table starts at.
4290	* @param pHlp Pointer to the output functions.
4291	*/
4292	int pgmR3DumpHierarchyHC32BitPT(PVM pVM, PX86PT pPT, uint32_t u32Address, PCDBGFINFOHLP pHlp)
4293	{
4294	for (unsigned i = 0; i < RT_ELEMENTS(pPT->a); i++)
4295	{
4296	X86PTE Pte = pPT->a[i];
4297	if (Pte.n.u1Present)
4298	{
4299	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a m d /
4300	"%08x 1 \| P %c %c %c %c %c %s %s %s .. 4K %c%c%c %08x\n",
4301	u32Address + (i << X86_PT_SHIFT),
4302	Pte.n.u1Write ? 'W' : 'R',
4303	Pte.n.u1User ? 'U' : 'S',
4304	Pte.n.u1Accessed ? 'A' : '-',
4305	Pte.n.u1Dirty ? 'D' : '-',
4306	Pte.n.u1Global ? 'G' : '-',
4307	Pte.n.u1WriteThru ? "WT" : "--",
4308	Pte.n.u1CacheDisable? "CD" : "--",
4309	Pte.n.u1PAT ? "AT" : "--",
4310	Pte.u & PGM_PTFLAGS_TRACK_DIRTY ? 'd' : '-',
4311	Pte.u & RT_BIT(10) ? '1' : '0',
4312	Pte.u & PGM_PTFLAGS_CSAM_VALIDATED ? 'v' : '-',
4313	Pte.u & X86_PDE_PG_MASK);
4314	}
4315	}
4316	return VINF_SUCCESS;
4317	}
4318
4319
4320	/**
4321	* Dumps a 32-bit shadow page directory and page tables.
4322	*
4323	* @returns VBox status code (VINF_SUCCESS).
4324	* @param pVM The VM handle.
4325	* @param cr3 The root of the hierarchy.
4326	* @param cr4 The CR4, PSE is currently used.
4327	* @param cMaxDepth How deep into the hierarchy the dumper should go.
4328	* @param pHlp Pointer to the output functions.
4329	*/
4330	int pgmR3DumpHierarchyHC32BitPD(PVM pVM, uint32_t cr3, uint32_t cr4, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
4331	{
4332	PX86PD pPD = (PX86PD)MMPagePhys2Page(pVM, cr3 & X86_CR3_PAGE_MASK);
4333	if (!pPD)
4334	{
4335	pHlp->pfnPrintf(pHlp, "Page directory at %#x was not found in the page pool!\n", cr3 & X86_CR3_PAGE_MASK);
4336	return VERR_INVALID_PARAMETER;
4337	}
4338
4339	int rc = VINF_SUCCESS;
4340	for (unsigned i = 0; i < RT_ELEMENTS(pPD->a); i++)
4341	{
4342	X86PDE Pde = pPD->a[i];
4343	if (Pde.n.u1Present)
4344	{
4345	const uint32_t u32Address = i << X86_PD_SHIFT;
4346	if ((cr4 & X86_CR4_PSE) && Pde.b.u1Size)
4347	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a m d /
4348	"%08x 0 \| P %c %c %c %c %c %s %s %s .. 4M %c%c%c %08x\n",
4349	u32Address,
4350	Pde.b.u1Write ? 'W' : 'R',
4351	Pde.b.u1User ? 'U' : 'S',
4352	Pde.b.u1Accessed ? 'A' : '-',
4353	Pde.b.u1Dirty ? 'D' : '-',
4354	Pde.b.u1Global ? 'G' : '-',
4355	Pde.b.u1WriteThru ? "WT" : "--",
4356	Pde.b.u1CacheDisable? "CD" : "--",
4357	Pde.b.u1PAT ? "AT" : "--",
4358	Pde.u & RT_BIT_64(9) ? '1' : '0',
4359	Pde.u & PGM_PDFLAGS_MAPPING ? 'm' : '-',
4360	Pde.u & PGM_PDFLAGS_TRACK_DIRTY ? 'd' : '-',
4361	Pde.u & X86_PDE4M_PG_MASK);
4362	else
4363	{
4364	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a m d /
4365	"%08x 0 \| P %c %c %c %c %c %s %s .. .. 4K %c%c%c %08x\n",
4366	u32Address,
4367	Pde.n.u1Write ? 'W' : 'R',
4368	Pde.n.u1User ? 'U' : 'S',
4369	Pde.n.u1Accessed ? 'A' : '-',
4370	Pde.n.u1Reserved0 ? '?' : '.', /* ignored */
4371	Pde.n.u1Reserved1 ? '?' : '.', /* ignored */
4372	Pde.n.u1WriteThru ? "WT" : "--",
4373	Pde.n.u1CacheDisable? "CD" : "--",
4374	Pde.u & RT_BIT_64(9) ? '1' : '0',
4375	Pde.u & PGM_PDFLAGS_MAPPING ? 'm' : '-',
4376	Pde.u & PGM_PDFLAGS_TRACK_DIRTY ? 'd' : '-',
4377	Pde.u & X86_PDE_PG_MASK);
4378	if (cMaxDepth >= 1)
4379	{
4380	/** @todo what about using the page pool for mapping PTs? */
4381	RTHCPHYS HCPhys = Pde.u & X86_PDE_PG_MASK;
4382	PX86PT pPT = NULL;
4383	if (!(Pde.u & PGM_PDFLAGS_MAPPING))
4384	pPT = (PX86PT)MMPagePhys2Page(pVM, HCPhys);
4385	else
4386	{
4387	for (PPGMMAPPING pMap = pVM->pgm.s.pMappingsR3; pMap; pMap = pMap->pNextR3)
4388	if (u32Address - pMap->GCPtr < pMap->cb)
4389	{
4390	int iPDE = (u32Address - pMap->GCPtr) >> X86_PD_SHIFT;
4391	if (pMap->aPTs[iPDE].HCPhysPT != HCPhys)
4392	pHlp->pfnPrintf(pHlp, "%08x error! Mapping error! PT %d has HCPhysPT=%RHp not %RHp is in the PD.\n",
4393	u32Address, iPDE, pMap->aPTs[iPDE].HCPhysPT, HCPhys);
4394	pPT = pMap->aPTs[iPDE].pPTR3;
4395	}
4396	}
4397	int rc2 = VERR_INVALID_PARAMETER;
4398	if (pPT)
4399	rc2 = pgmR3DumpHierarchyHC32BitPT(pVM, pPT, u32Address, pHlp);
4400	else
4401	pHlp->pfnPrintf(pHlp, "%08x error! Page table at %#x was not found in the page pool!\n", u32Address, HCPhys);
4402	if (rc2 < rc && RT_SUCCESS(rc))
4403	rc = rc2;
4404	}
4405	}
4406	}
4407	}
4408
4409	return rc;
4410	}
4411
4412
4413	/**
4414	* Dumps a 32-bit shadow page table.
4415	*
4416	* @returns VBox status code (VINF_SUCCESS).
4417	* @param pVM The VM handle.
4418	* @param pPT Pointer to the page table.
4419	* @param u32Address The virtual address this table starts at.
4420	* @param PhysSearch Address to search for.
4421	*/
4422	int pgmR3DumpHierarchyGC32BitPT(PVM pVM, PX86PT pPT, uint32_t u32Address, RTGCPHYS PhysSearch)
4423	{
4424	for (unsigned i = 0; i < RT_ELEMENTS(pPT->a); i++)
4425	{
4426	X86PTE Pte = pPT->a[i];
4427	if (Pte.n.u1Present)
4428	{
4429	Log(( /P R S A D G WT CD AT NX 4M a m d /
4430	"%08x 1 \| P %c %c %c %c %c %s %s %s .. 4K %c%c%c %08x\n",
4431	u32Address + (i << X86_PT_SHIFT),
4432	Pte.n.u1Write ? 'W' : 'R',
4433	Pte.n.u1User ? 'U' : 'S',
4434	Pte.n.u1Accessed ? 'A' : '-',
4435	Pte.n.u1Dirty ? 'D' : '-',
4436	Pte.n.u1Global ? 'G' : '-',
4437	Pte.n.u1WriteThru ? "WT" : "--",
4438	Pte.n.u1CacheDisable? "CD" : "--",
4439	Pte.n.u1PAT ? "AT" : "--",
4440	Pte.u & PGM_PTFLAGS_TRACK_DIRTY ? 'd' : '-',
4441	Pte.u & RT_BIT(10) ? '1' : '0',
4442	Pte.u & PGM_PTFLAGS_CSAM_VALIDATED ? 'v' : '-',
4443	Pte.u & X86_PDE_PG_MASK));
4444
4445	if ((Pte.u & X86_PDE_PG_MASK) == PhysSearch)
4446	{
4447	uint64_t fPageShw = 0;
4448	RTHCPHYS pPhysHC = 0;
4449
4450	PGMShwGetPage(pVM, (RTGCPTR)(u32Address + (i << X86_PT_SHIFT)), &fPageShw, &pPhysHC);
4451	Log(("Found %RGp at %RGv -> flags=%llx\n", PhysSearch, (RTGCPTR)(u32Address + (i << X86_PT_SHIFT)), fPageShw));
4452	}
4453	}
4454	}
4455	return VINF_SUCCESS;
4456	}
4457
4458
4459	/**
4460	* Dumps a 32-bit guest page directory and page tables.
4461	*
4462	* @returns VBox status code (VINF_SUCCESS).
4463	* @param pVM The VM handle.
4464	* @param cr3 The root of the hierarchy.
4465	* @param cr4 The CR4, PSE is currently used.
4466	* @param PhysSearch Address to search for.
4467	*/
4468	VMMR3DECL(int) PGMR3DumpHierarchyGC(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCPHYS PhysSearch)
4469	{
4470	bool fLongMode = false;
4471	const unsigned cch = fLongMode ? 16 : 8; NOREF(cch);
4472	PX86PD pPD = 0;
4473
4474	int rc = PGM_GCPHYS_2_PTR(pVM, cr3 & X86_CR3_PAGE_MASK, &pPD);
4475	if (RT_FAILURE(rc) \|\| !pPD)
4476	{
4477	Log(("Page directory at %#x was not found in the page pool!\n", cr3 & X86_CR3_PAGE_MASK));
4478	return VERR_INVALID_PARAMETER;
4479	}
4480
4481	Log(("cr3=%08x cr4=%08x%s\n"
4482	"%-*s P - Present\n"
4483	"%-*s \| R/W - Read (0) / Write (1)\n"
4484	"%-*s \| \| U/S - User (1) / Supervisor (0)\n"
4485	"%-*s \| \| \| A - Accessed\n"
4486	"%-*s \| \| \| \| D - Dirty\n"
4487	"%-*s \| \| \| \| \| G - Global\n"
4488	"%-*s \| \| \| \| \| \| WT - Write thru\n"
4489	"%-*s \| \| \| \| \| \| \| CD - Cache disable\n"
4490	"%-*s \| \| \| \| \| \| \| \| AT - Attribute table (PAT)\n"
4491	"%-*s \| \| \| \| \| \| \| \| \| NX - No execute (K8)\n"
4492	"%-*s \| \| \| \| \| \| \| \| \| \| 4K/4M/2M - Page size.\n"
4493	"%-*s \| \| \| \| \| \| \| \| \| \| \| AVL - a=allocated; m=mapping; d=track dirty;\n"
4494	"%-*s \| \| \| \| \| \| \| \| \| \| \| \| p=permanent; v=validated;\n"
4495	"%-*s Level \| \| \| \| \| \| \| \| \| \| \| \| Page\n"
4496	/* xxxx n **** P R S A D G WT CD AT NX 4M AVL xxxxxxxxxxxxx
4497	- W U - - - -- -- -- -- -- 010 */
4498	, cr3, cr4, fLongMode ? " Long Mode" : "",
4499	cch, "", cch, "", cch, "", cch, "", cch, "", cch, "", cch, "",
4500	cch, "", cch, "", cch, "", cch, "", cch, "", cch, "", cch, "Address"));
4501
4502	for (unsigned i = 0; i < RT_ELEMENTS(pPD->a); i++)
4503	{
4504	X86PDE Pde = pPD->a[i];
4505	if (Pde.n.u1Present)
4506	{
4507	const uint32_t u32Address = i << X86_PD_SHIFT;
4508
4509	if ((cr4 & X86_CR4_PSE) && Pde.b.u1Size)
4510	Log(( /P R S A D G WT CD AT NX 4M a m d /
4511	"%08x 0 \| P %c %c %c %c %c %s %s %s .. 4M %c%c%c %08x\n",
4512	u32Address,
4513	Pde.b.u1Write ? 'W' : 'R',
4514	Pde.b.u1User ? 'U' : 'S',
4515	Pde.b.u1Accessed ? 'A' : '-',
4516	Pde.b.u1Dirty ? 'D' : '-',
4517	Pde.b.u1Global ? 'G' : '-',
4518	Pde.b.u1WriteThru ? "WT" : "--",
4519	Pde.b.u1CacheDisable? "CD" : "--",
4520	Pde.b.u1PAT ? "AT" : "--",
4521	Pde.u & RT_BIT(9) ? '1' : '0',
4522	Pde.u & RT_BIT(10) ? '1' : '0',
4523	Pde.u & RT_BIT(11) ? '1' : '0',
4524	pgmGstGet4MBPhysPage(&pVM->pgm.s, Pde)));
4525	/** @todo PhysSearch */
4526	else
4527	{
4528	Log(( /P R S A D G WT CD AT NX 4M a m d /
4529	"%08x 0 \| P %c %c %c %c %c %s %s .. .. 4K %c%c%c %08x\n",
4530	u32Address,
4531	Pde.n.u1Write ? 'W' : 'R',
4532	Pde.n.u1User ? 'U' : 'S',
4533	Pde.n.u1Accessed ? 'A' : '-',
4534	Pde.n.u1Reserved0 ? '?' : '.', /* ignored */
4535	Pde.n.u1Reserved1 ? '?' : '.', /* ignored */
4536	Pde.n.u1WriteThru ? "WT" : "--",
4537	Pde.n.u1CacheDisable? "CD" : "--",
4538	Pde.u & RT_BIT(9) ? '1' : '0',
4539	Pde.u & RT_BIT(10) ? '1' : '0',
4540	Pde.u & RT_BIT(11) ? '1' : '0',
4541	Pde.u & X86_PDE_PG_MASK));
4542	////if (cMaxDepth >= 1)
4543	{
4544	/** @todo what about using the page pool for mapping PTs? */
4545	RTGCPHYS GCPhys = Pde.u & X86_PDE_PG_MASK;
4546	PX86PT pPT = NULL;
4547
4548	rc = PGM_GCPHYS_2_PTR(pVM, GCPhys, &pPT);
4549
4550	int rc2 = VERR_INVALID_PARAMETER;
4551	if (pPT)
4552	rc2 = pgmR3DumpHierarchyGC32BitPT(pVM, pPT, u32Address, PhysSearch);
4553	else
4554	Log(("%08x error! Page table at %#x was not found in the page pool!\n", u32Address, GCPhys));
4555	if (rc2 < rc && RT_SUCCESS(rc))
4556	rc = rc2;
4557	}
4558	}
4559	}
4560	}
4561
4562	return rc;
4563	}
4564
4565
4566	/**
4567	* Dumps a page table hierarchy use only physical addresses and cr4/lm flags.
4568	*
4569	* @returns VBox status code (VINF_SUCCESS).
4570	* @param pVM The VM handle.
4571	* @param cr3 The root of the hierarchy.
4572	* @param cr4 The cr4, only PAE and PSE is currently used.
4573	* @param fLongMode Set if long mode, false if not long mode.
4574	* @param cMaxDepth Number of levels to dump.
4575	* @param pHlp Pointer to the output functions.
4576	*/
4577	VMMR3DECL(int) PGMR3DumpHierarchyHC(PVM pVM, uint64_t cr3, uint64_t cr4, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
4578	{
4579	if (!pHlp)
4580	pHlp = DBGFR3InfoLogHlp();
4581	if (!cMaxDepth)
4582	return VINF_SUCCESS;
4583	const unsigned cch = fLongMode ? 16 : 8;
4584	pHlp->pfnPrintf(pHlp,
4585	"cr3=%08x cr4=%08x%s\n"
4586	"%-*s P - Present\n"
4587	"%-*s \| R/W - Read (0) / Write (1)\n"
4588	"%-*s \| \| U/S - User (1) / Supervisor (0)\n"
4589	"%-*s \| \| \| A - Accessed\n"
4590	"%-*s \| \| \| \| D - Dirty\n"
4591	"%-*s \| \| \| \| \| G - Global\n"
4592	"%-*s \| \| \| \| \| \| WT - Write thru\n"
4593	"%-*s \| \| \| \| \| \| \| CD - Cache disable\n"
4594	"%-*s \| \| \| \| \| \| \| \| AT - Attribute table (PAT)\n"
4595	"%-*s \| \| \| \| \| \| \| \| \| NX - No execute (K8)\n"
4596	"%-*s \| \| \| \| \| \| \| \| \| \| 4K/4M/2M - Page size.\n"
4597	"%-*s \| \| \| \| \| \| \| \| \| \| \| AVL - a=allocated; m=mapping; d=track dirty;\n"
4598	"%-*s \| \| \| \| \| \| \| \| \| \| \| \| p=permanent; v=validated;\n"
4599	"%-*s Level \| \| \| \| \| \| \| \| \| \| \| \| Page\n"
4600	/* xxxx n **** P R S A D G WT CD AT NX 4M AVL xxxxxxxxxxxxx
4601	- W U - - - -- -- -- -- -- 010 */
4602	, cr3, cr4, fLongMode ? " Long Mode" : "",
4603	cch, "", cch, "", cch, "", cch, "", cch, "", cch, "", cch, "",
4604	cch, "", cch, "", cch, "", cch, "", cch, "", cch, "", cch, "Address");
4605	if (cr4 & X86_CR4_PAE)
4606	{
4607	if (fLongMode)
4608	return pgmR3DumpHierarchyHcPaePML4(pVM, cr3 & X86_CR3_PAGE_MASK, cr4, cMaxDepth, pHlp);
4609	return pgmR3DumpHierarchyHCPaePDPT(pVM, cr3 & X86_CR3_PAE_PAGE_MASK, 0, cr4, false, cMaxDepth, pHlp);
4610	}
4611	return pgmR3DumpHierarchyHC32BitPD(pVM, cr3 & X86_CR3_PAGE_MASK, cr4, cMaxDepth, pHlp);
4612	}
4613
4614	#ifdef VBOX_WITH_DEBUGGER
4615
4616	/**
4617	* The '.pgmram' command.
4618	*
4619	* @returns VBox status.
4620	* @param pCmd Pointer to the command descriptor (as registered).
4621	* @param pCmdHlp Pointer to command helper functions.
4622	* @param pVM Pointer to the current VM (if any).
4623	* @param paArgs Pointer to (readonly) array of arguments.
4624	* @param cArgs Number of arguments in the array.
4625	*/
4626	static DECLCALLBACK(int) pgmR3CmdRam(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4627	{
4628	/*
4629	* Validate input.
4630	*/
4631	if (!pVM)
4632	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4633	if (!pVM->pgm.s.pRamRangesRC)
4634	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Sorry, no Ram is registered.\n");
4635
4636	/*
4637	* Dump the ranges.
4638	*/
4639	int rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL, "From - To (incl) pvHC\n");
4640	PPGMRAMRANGE pRam;
4641	for (pRam = pVM->pgm.s.pRamRangesR3; pRam; pRam = pRam->pNextR3)
4642	{
4643	rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL,
4644	"%RGp - %RGp %p\n",
4645	pRam->GCPhys, pRam->GCPhysLast, pRam->pvR3);
4646	if (RT_FAILURE(rc))
4647	return rc;
4648	}
4649
4650	return VINF_SUCCESS;
4651	}
4652
4653
4654	/**
4655	* The '.pgmmap' command.
4656	*
4657	* @returns VBox status.
4658	* @param pCmd Pointer to the command descriptor (as registered).
4659	* @param pCmdHlp Pointer to command helper functions.
4660	* @param pVM Pointer to the current VM (if any).
4661	* @param paArgs Pointer to (readonly) array of arguments.
4662	* @param cArgs Number of arguments in the array.
4663	*/
4664	static DECLCALLBACK(int) pgmR3CmdMap(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4665	{
4666	/*
4667	* Validate input.
4668	*/
4669	if (!pVM)
4670	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4671	if (!pVM->pgm.s.pMappingsR3)
4672	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Sorry, no mappings are registered.\n");
4673
4674	/*
4675	* Print message about the fixedness of the mappings.
4676	*/
4677	int rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL, pVM->pgm.s.fMappingsFixed ? "The mappings are FIXED.\n" : "The mappings are FLOATING.\n");
4678	if (RT_FAILURE(rc))
4679	return rc;
4680
4681	/*
4682	* Dump the ranges.
4683	*/
4684	PPGMMAPPING pCur;
4685	for (pCur = pVM->pgm.s.pMappingsR3; pCur; pCur = pCur->pNextR3)
4686	{
4687	rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL,
4688	"%08x - %08x %s\n",
4689	pCur->GCPtr, pCur->GCPtrLast, pCur->pszDesc);
4690	if (RT_FAILURE(rc))
4691	return rc;
4692	}
4693
4694	return VINF_SUCCESS;
4695	}
4696
4697
4698	/**
4699	* The '.pgmsync' command.
4700	*
4701	* @returns VBox status.
4702	* @param pCmd Pointer to the command descriptor (as registered).
4703	* @param pCmdHlp Pointer to command helper functions.
4704	* @param pVM Pointer to the current VM (if any).
4705	* @param paArgs Pointer to (readonly) array of arguments.
4706	* @param cArgs Number of arguments in the array.
4707	*/
4708	static DECLCALLBACK(int) pgmR3CmdSync(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4709	{
4710	/*
4711	* Validate input.
4712	*/
4713	if (!pVM)
4714	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4715
4716	/*
4717	* Force page directory sync.
4718	*/
4719	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
4720
4721	int rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Forcing page directory sync.\n");
4722	if (RT_FAILURE(rc))
4723	return rc;
4724
4725	return VINF_SUCCESS;
4726	}
4727
4728
4729	#ifdef VBOX_STRICT
4730	/**
4731	* The '.pgmassertcr3' command.
4732	*
4733	* @returns VBox status.
4734	* @param pCmd Pointer to the command descriptor (as registered).
4735	* @param pCmdHlp Pointer to command helper functions.
4736	* @param pVM Pointer to the current VM (if any).
4737	* @param paArgs Pointer to (readonly) array of arguments.
4738	* @param cArgs Number of arguments in the array.
4739	*/
4740	static DECLCALLBACK(int) pgmR3CmdAssertCR3(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4741	{
4742	/*
4743	* Validate input.
4744	*/
4745	if (!pVM)
4746	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4747
4748	int rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Checking shadow CR3 page tables for consistency.\n");
4749	if (RT_FAILURE(rc))
4750	return rc;
4751
4752	PGMAssertCR3(pVM, CPUMGetGuestCR3(pVM), CPUMGetGuestCR4(pVM));
4753
4754	return VINF_SUCCESS;
4755	}
4756	#endif /* VBOX_STRICT */
4757
4758
4759	/**
4760	* The '.pgmsyncalways' command.
4761	*
4762	* @returns VBox status.
4763	* @param pCmd Pointer to the command descriptor (as registered).
4764	* @param pCmdHlp Pointer to command helper functions.
4765	* @param pVM Pointer to the current VM (if any).
4766	* @param paArgs Pointer to (readonly) array of arguments.
4767	* @param cArgs Number of arguments in the array.
4768	*/
4769	static DECLCALLBACK(int) pgmR3CmdSyncAlways(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4770	{
4771	/*
4772	* Validate input.
4773	*/
4774	if (!pVM)
4775	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4776
4777	/*
4778	* Force page directory sync.
4779	*/
4780	if (pVM->pgm.s.fSyncFlags & PGM_SYNC_ALWAYS)
4781	{
4782	ASMAtomicAndU32(&pVM->pgm.s.fSyncFlags, ~PGM_SYNC_ALWAYS);
4783	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Disabled permanent forced page directory syncing.\n");
4784	}
4785	else
4786	{
4787	ASMAtomicOrU32(&pVM->pgm.s.fSyncFlags, PGM_SYNC_ALWAYS);
4788	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
4789	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Enabled permanent forced page directory syncing.\n");
4790	}
4791	}
4792
4793	#endif /* VBOX_WITH_DEBUGGER */
4794
4795	/**
4796	* pvUser argument of the pgmR3CheckIntegrity*Node callbacks.
4797	*/
4798	typedef struct PGMCHECKINTARGS
4799	{
4800	bool fLeftToRight; /*< true: left-to-right; false: right-to-left. /
4801	PPGMPHYSHANDLER pPrevPhys;
4802	PPGMVIRTHANDLER pPrevVirt;
4803	PPGMPHYS2VIRTHANDLER pPrevPhys2Virt;
4804	PVM pVM;
4805	} PGMCHECKINTARGS, *PPGMCHECKINTARGS;
4806
4807	/**
4808	* Validate a node in the physical handler tree.
4809	*
4810	* @returns 0 on if ok, other wise 1.
4811	* @param pNode The handler node.
4812	* @param pvUser pVM.
4813	*/
4814	static DECLCALLBACK(int) pgmR3CheckIntegrityPhysHandlerNode(PAVLROGCPHYSNODECORE pNode, void *pvUser)
4815	{
4816	PPGMCHECKINTARGS pArgs = (PPGMCHECKINTARGS)pvUser;
4817	PPGMPHYSHANDLER pCur = (PPGMPHYSHANDLER)pNode;
4818	AssertReleaseReturn(!((uintptr_t)pCur & 7), 1);
4819	AssertReleaseMsg(pCur->Core.Key <= pCur->Core.KeyLast,("pCur=%p %RGp-%RGp %s\n", pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
4820	AssertReleaseMsg( !pArgs->pPrevPhys
4821	\|\| (pArgs->fLeftToRight ? pArgs->pPrevPhys->Core.KeyLast < pCur->Core.Key : pArgs->pPrevPhys->Core.KeyLast > pCur->Core.Key),
4822	("pPrevPhys=%p %RGp-%RGp %s\n"
4823	" pCur=%p %RGp-%RGp %s\n",
4824	pArgs->pPrevPhys, pArgs->pPrevPhys->Core.Key, pArgs->pPrevPhys->Core.KeyLast, pArgs->pPrevPhys->pszDesc,
4825	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
4826	pArgs->pPrevPhys = pCur;
4827	return 0;
4828	}
4829
4830
4831	/**
4832	* Validate a node in the virtual handler tree.
4833	*
4834	* @returns 0 on if ok, other wise 1.
4835	* @param pNode The handler node.
4836	* @param pvUser pVM.
4837	*/
4838	static DECLCALLBACK(int) pgmR3CheckIntegrityVirtHandlerNode(PAVLROGCPTRNODECORE pNode, void *pvUser)
4839	{
4840	PPGMCHECKINTARGS pArgs = (PPGMCHECKINTARGS)pvUser;
4841	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)pNode;
4842	AssertReleaseReturn(!((uintptr_t)pCur & 7), 1);
4843	AssertReleaseMsg(pCur->Core.Key <= pCur->Core.KeyLast,("pCur=%p %RGv-%RGv %s\n", pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
4844	AssertReleaseMsg( !pArgs->pPrevVirt
4845	\|\| (pArgs->fLeftToRight ? pArgs->pPrevVirt->Core.KeyLast < pCur->Core.Key : pArgs->pPrevVirt->Core.KeyLast > pCur->Core.Key),
4846	("pPrevVirt=%p %RGv-%RGv %s\n"
4847	" pCur=%p %RGv-%RGv %s\n",
4848	pArgs->pPrevVirt, pArgs->pPrevVirt->Core.Key, pArgs->pPrevVirt->Core.KeyLast, pArgs->pPrevVirt->pszDesc,
4849	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
4850	for (unsigned iPage = 0; iPage < pCur->cPages; iPage++)
4851	{
4852	AssertReleaseMsg(pCur->aPhysToVirt[iPage].offVirtHandler == -RT_OFFSETOF(PGMVIRTHANDLER, aPhysToVirt[iPage]),
4853	("pCur=%p %RGv-%RGv %s\n"
4854	"iPage=%d offVirtHandle=%#x expected %#x\n",
4855	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc,
4856	iPage, pCur->aPhysToVirt[iPage].offVirtHandler, -RT_OFFSETOF(PGMVIRTHANDLER, aPhysToVirt[iPage])));
4857	}
4858	pArgs->pPrevVirt = pCur;
4859	return 0;
4860	}
4861
4862
4863	/**
4864	* Validate a node in the virtual handler tree.
4865	*
4866	* @returns 0 on if ok, other wise 1.
4867	* @param pNode The handler node.
4868	* @param pvUser pVM.
4869	*/
4870	static DECLCALLBACK(int) pgmR3CheckIntegrityPhysToVirtHandlerNode(PAVLROGCPHYSNODECORE pNode, void *pvUser)
4871	{
4872	PPGMCHECKINTARGS pArgs = (PPGMCHECKINTARGS)pvUser;
4873	PPGMPHYS2VIRTHANDLER pCur = (PPGMPHYS2VIRTHANDLER)pNode;
4874	AssertReleaseMsgReturn(!((uintptr_t)pCur & 3), ("\n"), 1);
4875	AssertReleaseMsgReturn(!(pCur->offVirtHandler & 3), ("\n"), 1);
4876	AssertReleaseMsg(pCur->Core.Key <= pCur->Core.KeyLast,("pCur=%p %RGp-%RGp\n", pCur, pCur->Core.Key, pCur->Core.KeyLast));
4877	AssertReleaseMsg( !pArgs->pPrevPhys2Virt
4878	\|\| (pArgs->fLeftToRight ? pArgs->pPrevPhys2Virt->Core.KeyLast < pCur->Core.Key : pArgs->pPrevPhys2Virt->Core.KeyLast > pCur->Core.Key),
4879	("pPrevPhys2Virt=%p %RGp-%RGp\n"
4880	" pCur=%p %RGp-%RGp\n",
4881	pArgs->pPrevPhys2Virt, pArgs->pPrevPhys2Virt->Core.Key, pArgs->pPrevPhys2Virt->Core.KeyLast,
4882	pCur, pCur->Core.Key, pCur->Core.KeyLast));
4883	AssertReleaseMsg( !pArgs->pPrevPhys2Virt
4884	\|\| (pArgs->fLeftToRight ? pArgs->pPrevPhys2Virt->Core.KeyLast < pCur->Core.Key : pArgs->pPrevPhys2Virt->Core.KeyLast > pCur->Core.Key),
4885	("pPrevPhys2Virt=%p %RGp-%RGp\n"
4886	" pCur=%p %RGp-%RGp\n",
4887	pArgs->pPrevPhys2Virt, pArgs->pPrevPhys2Virt->Core.Key, pArgs->pPrevPhys2Virt->Core.KeyLast,
4888	pCur, pCur->Core.Key, pCur->Core.KeyLast));
4889	AssertReleaseMsg((pCur->offNextAlias & (PGMPHYS2VIRTHANDLER_IN_TREE \| PGMPHYS2VIRTHANDLER_IS_HEAD)) == (PGMPHYS2VIRTHANDLER_IN_TREE \| PGMPHYS2VIRTHANDLER_IS_HEAD),
4890	("pCur=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4891	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias));
4892	if (pCur->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK)
4893	{
4894	PPGMPHYS2VIRTHANDLER pCur2 = pCur;
4895	for (;;)
4896	{
4897	pCur2 = (PPGMPHYS2VIRTHANDLER)((intptr_t)pCur + (pCur->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK));
4898	AssertReleaseMsg(pCur2 != pCur,
4899	(" pCur=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4900	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias));
4901	AssertReleaseMsg((pCur2->offNextAlias & (PGMPHYS2VIRTHANDLER_IN_TREE \| PGMPHYS2VIRTHANDLER_IS_HEAD)) == PGMPHYS2VIRTHANDLER_IN_TREE,
4902	(" pCur=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
4903	"pCur2=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4904	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias,
4905	pCur2, pCur2->Core.Key, pCur2->Core.KeyLast, pCur2->offVirtHandler, pCur2->offNextAlias));
4906	AssertReleaseMsg((pCur2->Core.Key ^ pCur->Core.Key) < PAGE_SIZE,
4907	(" pCur=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
4908	"pCur2=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4909	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias,
4910	pCur2, pCur2->Core.Key, pCur2->Core.KeyLast, pCur2->offVirtHandler, pCur2->offNextAlias));
4911	AssertReleaseMsg((pCur2->Core.KeyLast ^ pCur->Core.KeyLast) < PAGE_SIZE,
4912	(" pCur=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
4913	"pCur2=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4914	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias,
4915	pCur2, pCur2->Core.Key, pCur2->Core.KeyLast, pCur2->offVirtHandler, pCur2->offNextAlias));
4916	if (!(pCur2->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK))
4917	break;
4918	}
4919	}
4920
4921	pArgs->pPrevPhys2Virt = pCur;
4922	return 0;
4923	}
4924
4925
4926	/**
4927	* Perform an integrity check on the PGM component.
4928	*
4929	* @returns VINF_SUCCESS if everything is fine.
4930	* @returns VBox error status after asserting on integrity breach.
4931	* @param pVM The VM handle.
4932	*/
4933	VMMR3DECL(int) PGMR3CheckIntegrity(PVM pVM)
4934	{
4935	AssertReleaseReturn(pVM->pgm.s.offVM, VERR_INTERNAL_ERROR);
4936
4937	/*
4938	* Check the trees.
4939	*/
4940	int cErrors = 0;
4941	const static PGMCHECKINTARGS s_LeftToRight = { true, NULL, NULL, NULL, pVM };
4942	const static PGMCHECKINTARGS s_RightToLeft = { false, NULL, NULL, NULL, pVM };
4943	PGMCHECKINTARGS Args = s_LeftToRight;
4944	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysHandlers, true, pgmR3CheckIntegrityPhysHandlerNode, &Args);
4945	Args = s_RightToLeft;
4946	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysHandlers, false, pgmR3CheckIntegrityPhysHandlerNode, &Args);
4947	Args = s_LeftToRight;
4948	cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesR3->VirtHandlers, true, pgmR3CheckIntegrityVirtHandlerNode, &Args);
4949	Args = s_RightToLeft;
4950	cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesR3->VirtHandlers, false, pgmR3CheckIntegrityVirtHandlerNode, &Args);
4951	Args = s_LeftToRight;
4952	cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesR3->HyperVirtHandlers, true, pgmR3CheckIntegrityVirtHandlerNode, &Args);
4953	Args = s_RightToLeft;
4954	cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesR3->HyperVirtHandlers, false, pgmR3CheckIntegrityVirtHandlerNode, &Args);
4955	Args = s_LeftToRight;
4956	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysToVirtHandlers, true, pgmR3CheckIntegrityPhysToVirtHandlerNode, &Args);
4957	Args = s_RightToLeft;
4958	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysToVirtHandlers, false, pgmR3CheckIntegrityPhysToVirtHandlerNode, &Args);
4959
4960	return !cErrors ? VINF_SUCCESS : VERR_INTERNAL_ERROR;
4961	}
4962
4963

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source: vbox/trunk/src/VBox/VMM/PGM.cpp@ 18291

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