PGM.cpp@ 22288

Last change on this file since 22288 was 22137, checked in by vboxsync, 15 years ago
PGM: Relocate pSelfRC of the MMIO2 ram ranges since unmapped ones will otherwise not be updated. Fixes #4195.
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1	/* $Id: PGM.cpp 22137 2009-08-10 14:05:44Z vboxsync $ */
2	/** @file
3	* PGM - Page Manager and Monitor. (Mixing stuff here, not good?)
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22
23	/** @page pg_pgm PGM - The Page Manager and Monitor
24	*
25	* @see grp_pgm,
26	* @ref pg_pgm_pool,
27	* @ref pg_pgm_phys.
28	*
29	*
30	* @section sec_pgm_modes Paging Modes
31	*
32	* There are three memory contexts: Host Context (HC), Guest Context (GC)
33	* and intermediate context. When talking about paging HC can also be refered to
34	* as "host paging", and GC refered to as "shadow paging".
35	*
36	* We define three basic paging modes: 32-bit, PAE and AMD64. The host paging mode
37	* is defined by the host operating system. The mode used in the shadow paging mode
38	* depends on the host paging mode and what the mode the guest is currently in. The
39	* following relation between the two is defined:
40	*
41	* @verbatim
42	Host > 32-bit \| PAE \| AMD64 \|
43	Guest \| \| \| \|
44	==v================================
45	32-bit 32-bit PAE PAE
46	-------\|--------\|--------\|--------\|
47	PAE PAE PAE PAE
48	-------\|--------\|--------\|--------\|
49	AMD64 AMD64 AMD64 AMD64
50	-------\|--------\|--------\|--------\| @endverbatim
51	*
52	* All configuration except those in the diagonal (upper left) are expected to
53	* require special effort from the switcher (i.e. a bit slower).
54	*
55	*
56	*
57	*
58	* @section sec_pgm_shw The Shadow Memory Context
59	*
60	*
61	* [..]
62	*
63	* Because of guest context mappings requires PDPT and PML4 entries to allow
64	* writing on AMD64, the two upper levels will have fixed flags whatever the
65	* guest is thinking of using there. So, when shadowing the PD level we will
66	* calculate the effective flags of PD and all the higher levels. In legacy
67	* PAE mode this only applies to the PWT and PCD bits (the rest are
68	* ignored/reserved/MBZ). We will ignore those bits for the present.
69	*
70	*
71	*
72	* @section sec_pgm_int The Intermediate Memory Context
73	*
74	* The world switch goes thru an intermediate memory context which purpose it is
75	* to provide different mappings of the switcher code. All guest mappings are also
76	* present in this context.
77	*
78	* The switcher code is mapped at the same location as on the host, at an
79	* identity mapped location (physical equals virtual address), and at the
80	* hypervisor location. The identity mapped location is for when the world
81	* switches that involves disabling paging.
82	*
83	* PGM maintain page tables for 32-bit, PAE and AMD64 paging modes. This
84	* simplifies switching guest CPU mode and consistency at the cost of more
85	* code to do the work. All memory use for those page tables is located below
86	* 4GB (this includes page tables for guest context mappings).
87	*
88	*
89	* @subsection subsec_pgm_int_gc Guest Context Mappings
90	*
91	* During assignment and relocation of a guest context mapping the intermediate
92	* memory context is used to verify the new location.
93	*
94	* Guest context mappings are currently restricted to below 4GB, for reasons
95	* of simplicity. This may change when we implement AMD64 support.
96	*
97	*
98	*
99	*
100	* @section sec_pgm_misc Misc
101	*
102	* @subsection subsec_pgm_misc_diff Differences Between Legacy PAE and Long Mode PAE
103	*
104	* The differences between legacy PAE and long mode PAE are:
105	* -# PDPE bits 1, 2, 5 and 6 are defined differently. In leagcy mode they are
106	* all marked down as must-be-zero, while in long mode 1, 2 and 5 have the
107	* usual meanings while 6 is ignored (AMD). This means that upon switching to
108	* legacy PAE mode we'll have to clear these bits and when going to long mode
109	* they must be set. This applies to both intermediate and shadow contexts,
110	* however we don't need to do it for the intermediate one since we're
111	* executing with CR0.WP at that time.
112	* -# CR3 allows a 32-byte aligned address in legacy mode, while in long mode
113	* a page aligned one is required.
114	*
115	*
116	* @section sec_pgm_handlers Access Handlers
117	*
118	* Placeholder.
119	*
120	*
121	* @subsection sec_pgm_handlers_virt Virtual Access Handlers
122	*
123	* Placeholder.
124	*
125	*
126	* @subsection sec_pgm_handlers_virt Virtual Access Handlers
127	*
128	* We currently implement three types of virtual access handlers: ALL, WRITE
129	* and HYPERVISOR (WRITE). See PGMVIRTHANDLERTYPE for some more details.
130	*
131	* The HYPERVISOR access handlers is kept in a separate tree since it doesn't apply
132	* to physical pages (PGMTREES::HyperVirtHandlers) and only needs to be consulted in
133	* a special \#PF case. The ALL and WRITE are in the PGMTREES::VirtHandlers tree, the
134	* rest of this section is going to be about these handlers.
135	*
136	* We'll go thru the life cycle of a handler and try make sense of it all, don't know
137	* how successfull this is gonna be...
138	*
139	* 1. A handler is registered thru the PGMR3HandlerVirtualRegister and
140	* PGMHandlerVirtualRegisterEx APIs. We check for conflicting virtual handlers
141	* and create a new node that is inserted into the AVL tree (range key). Then
142	* a full PGM resync is flagged (clear pool, sync cr3, update virtual bit of PGMPAGE).
143	*
144	* 2. The following PGMSyncCR3/SyncCR3 operation will first make invoke HandlerVirtualUpdate.
145	*
146	* 2a. HandlerVirtualUpdate will will lookup all the pages covered by virtual handlers
147	* via the current guest CR3 and update the physical page -> virtual handler
148	* translation. Needless to say, this doesn't exactly scale very well. If any changes
149	* are detected, it will flag a virtual bit update just like we did on registration.
150	* PGMPHYS pages with changes will have their virtual handler state reset to NONE.
151	*
152	* 2b. The virtual bit update process will iterate all the pages covered by all the
153	* virtual handlers and update the PGMPAGE virtual handler state to the max of all
154	* virtual handlers on that page.
155	*
156	* 2c. Back in SyncCR3 we will now flush the entire shadow page cache to make sure
157	* we don't miss any alias mappings of the monitored pages.
158	*
159	* 2d. SyncCR3 will then proceed with syncing the CR3 table.
160	*
161	* 3. \#PF(np,read) on a page in the range. This will cause it to be synced
162	* read-only and resumed if it's a WRITE handler. If it's an ALL handler we
163	* will call the handlers like in the next step. If the physical mapping has
164	* changed we will - some time in the future - perform a handler callback
165	* (optional) and update the physical -> virtual handler cache.
166	*
167	* 4. \#PF(,write) on a page in the range. This will cause the handler to
168	* be invoked.
169	*
170	* 5. The guest invalidates the page and changes the physical backing or
171	* unmaps it. This should cause the invalidation callback to be invoked
172	* (it might not yet be 100% perfect). Exactly what happens next... is
173	* this where we mess up and end up out of sync for a while?
174	*
175	* 6. The handler is deregistered by the client via PGMHandlerVirtualDeregister.
176	* We will then set all PGMPAGEs in the physical -> virtual handler cache for
177	* this handler to NONE and trigger a full PGM resync (basically the same
178	* as int step 1). Which means 2 is executed again.
179	*
180	*
181	* @subsubsection sub_sec_pgm_handler_virt_todo TODOs
182	*
183	* There is a bunch of things that needs to be done to make the virtual handlers
184	* work 100% correctly and work more efficiently.
185	*
186	* The first bit hasn't been implemented yet because it's going to slow the
187	* whole mess down even more, and besides it seems to be working reliably for
188	* our current uses. OTOH, some of the optimizations might end up more or less
189	* implementing the missing bits, so we'll see.
190	*
191	* On the optimization side, the first thing to do is to try avoid unnecessary
192	* cache flushing. Then try team up with the shadowing code to track changes
193	* in mappings by means of access to them (shadow in), updates to shadows pages,
194	* invlpg, and shadow PT discarding (perhaps).
195	*
196	* Some idea that have popped up for optimization for current and new features:
197	* - bitmap indicating where there are virtual handlers installed.
198	* (4KB => 220 pages, page 212 => covers 32-bit address space 1:1!)
199	* - Further optimize this by min/max (needs min/max avl getters).
200	* - Shadow page table entry bit (if any left)?
201	*
202	*/
203
204
205	/** @page pg_pgm_phys PGM Physical Guest Memory Management
206	*
207	*
208	* Objectives:
209	* - Guest RAM over-commitment using memory ballooning,
210	* zero pages and general page sharing.
211	* - Moving or mirroring a VM onto a different physical machine.
212	*
213	*
214	* @subsection subsec_pgmPhys_Definitions Definitions
215	*
216	* Allocation chunk - A RTR0MemObjAllocPhysNC object and the tracking
217	* machinery assoicated with it.
218	*
219	*
220	*
221	*
222	* @subsection subsec_pgmPhys_AllocPage Allocating a page.
223	*
224	* Initially we map all guest memory to the (per VM) zero page, which
225	* means that none of the read functions will cause pages to be allocated.
226	*
227	* Exception, access bit in page tables that have been shared. This must
228	* be handled, but we must also make sure PGMGst*Modify doesn't make
229	* unnecessary modifications.
230	*
231	* Allocation points:
232	* - PGMPhysSimpleWriteGCPhys and PGMPhysWrite.
233	* - Replacing a zero page mapping at \#PF.
234	* - Replacing a shared page mapping at \#PF.
235	* - ROM registration (currently MMR3RomRegister).
236	* - VM restore (pgmR3Load).
237	*
238	* For the first three it would make sense to keep a few pages handy
239	* until we've reached the max memory commitment for the VM.
240	*
241	* For the ROM registration, we know exactly how many pages we need
242	* and will request these from ring-0. For restore, we will save
243	* the number of non-zero pages in the saved state and allocate
244	* them up front. This would allow the ring-0 component to refuse
245	* the request if the isn't sufficient memory available for VM use.
246	*
247	* Btw. for both ROM and restore allocations we won't be requiring
248	* zeroed pages as they are going to be filled instantly.
249	*
250	*
251	* @subsection subsec_pgmPhys_FreePage Freeing a page
252	*
253	* There are a few points where a page can be freed:
254	* - After being replaced by the zero page.
255	* - After being replaced by a shared page.
256	* - After being ballooned by the guest additions.
257	* - At reset.
258	* - At restore.
259	*
260	* When freeing one or more pages they will be returned to the ring-0
261	* component and replaced by the zero page.
262	*
263	* The reasoning for clearing out all the pages on reset is that it will
264	* return us to the exact same state as on power on, and may thereby help
265	* us reduce the memory load on the system. Further it might have a
266	* (temporary) positive influence on memory fragmentation (@see subsec_pgmPhys_Fragmentation).
267	*
268	* On restore, as mention under the allocation topic, pages should be
269	* freed / allocated depending on how many is actually required by the
270	* new VM state. The simplest approach is to do like on reset, and free
271	* all non-ROM pages and then allocate what we need.
272	*
273	* A measure to prevent some fragmentation, would be to let each allocation
274	* chunk have some affinity towards the VM having allocated the most pages
275	* from it. Also, try make sure to allocate from allocation chunks that
276	* are almost full. Admittedly, both these measures might work counter to
277	* our intentions and its probably not worth putting a lot of effort,
278	* cpu time or memory into this.
279	*
280	*
281	* @subsection subsec_pgmPhys_SharePage Sharing a page
282	*
283	* The basic idea is that there there will be a idle priority kernel
284	* thread walking the non-shared VM pages hashing them and looking for
285	* pages with the same checksum. If such pages are found, it will compare
286	* them byte-by-byte to see if they actually are identical. If found to be
287	* identical it will allocate a shared page, copy the content, check that
288	* the page didn't change while doing this, and finally request both the
289	* VMs to use the shared page instead. If the page is all zeros (special
290	* checksum and byte-by-byte check) it will request the VM that owns it
291	* to replace it with the zero page.
292	*
293	* To make this efficient, we will have to make sure not to try share a page
294	* that will change its contents soon. This part requires the most work.
295	* A simple idea would be to request the VM to write monitor the page for
296	* a while to make sure it isn't modified any time soon. Also, it may
297	* make sense to skip pages that are being write monitored since this
298	* information is readily available to the thread if it works on the
299	* per-VM guest memory structures (presently called PGMRAMRANGE).
300	*
301	*
302	* @subsection subsec_pgmPhys_Fragmentation Fragmentation Concerns and Counter Measures
303	*
304	* The pages are organized in allocation chunks in ring-0, this is a necessity
305	* if we wish to have an OS agnostic approach to this whole thing. (On Linux we
306	* could easily work on a page-by-page basis if we liked. Whether this is possible
307	* or efficient on NT I don't quite know.) Fragmentation within these chunks may
308	* become a problem as part of the idea here is that we wish to return memory to
309	* the host system.
310	*
311	* For instance, starting two VMs at the same time, they will both allocate the
312	* guest memory on-demand and if permitted their page allocations will be
313	* intermixed. Shut down one of the two VMs and it will be difficult to return
314	* any memory to the host system because the page allocation for the two VMs are
315	* mixed up in the same allocation chunks.
316	*
317	* To further complicate matters, when pages are freed because they have been
318	* ballooned or become shared/zero the whole idea is that the page is supposed
319	* to be reused by another VM or returned to the host system. This will cause
320	* allocation chunks to contain pages belonging to different VMs and prevent
321	* returning memory to the host when one of those VM shuts down.
322	*
323	* The only way to really deal with this problem is to move pages. This can
324	* either be done at VM shutdown and or by the idle priority worker thread
325	* that will be responsible for finding sharable/zero pages. The mechanisms
326	* involved for coercing a VM to move a page (or to do it for it) will be
327	* the same as when telling it to share/zero a page.
328	*
329	*
330	* @subsection subsec_pgmPhys_Tracking Tracking Structures And Their Cost
331	*
332	* There's a difficult balance between keeping the per-page tracking structures
333	* (global and guest page) easy to use and keeping them from eating too much
334	* memory. We have limited virtual memory resources available when operating in
335	* 32-bit kernel space (on 64-bit there'll it's quite a different story). The
336	* tracking structures will be attemted designed such that we can deal with up
337	* to 32GB of memory on a 32-bit system and essentially unlimited on 64-bit ones.
338	*
339	*
340	* @subsubsection subsubsec_pgmPhys_Tracking_Kernel Kernel Space
341	*
342	* @see pg_GMM
343	*
344	* @subsubsection subsubsec_pgmPhys_Tracking_PerVM Per-VM
345	*
346	* Fixed info is the physical address of the page (HCPhys) and the page id
347	* (described above). Theoretically we'll need 48(-12) bits for the HCPhys part.
348	* Today we've restricting ourselves to 40(-12) bits because this is the current
349	* restrictions of all AMD64 implementations (I think Barcelona will up this
350	* to 48(-12) bits, not that it really matters) and I needed the bits for
351	* tracking mappings of a page. 48-12 = 36. That leaves 28 bits, which means a
352	* decent range for the page id: 2^(28+12) = 1024TB.
353	*
354	* In additions to these, we'll have to keep maintaining the page flags as we
355	* currently do. Although it wouldn't harm to optimize these quite a bit, like
356	* for instance the ROM shouldn't depend on having a write handler installed
357	* in order for it to become read-only. A RO/RW bit should be considered so
358	* that the page syncing code doesn't have to mess about checking multiple
359	* flag combinations (ROM \|\| RW handler \|\| write monitored) in order to
360	* figure out how to setup a shadow PTE. But this of course, is second
361	* priority at present. Current this requires 12 bits, but could probably
362	* be optimized to ~8.
363	*
364	* Then there's the 24 bits used to track which shadow page tables are
365	* currently mapping a page for the purpose of speeding up physical
366	* access handlers, and thereby the page pool cache. More bit for this
367	* purpose wouldn't hurt IIRC.
368	*
369	* Then there is a new bit in which we need to record what kind of page
370	* this is, shared, zero, normal or write-monitored-normal. This'll
371	* require 2 bits. One bit might be needed for indicating whether a
372	* write monitored page has been written to. And yet another one or
373	* two for tracking migration status. 3-4 bits total then.
374	*
375	* Whatever is left will can be used to record the sharabilitiy of a
376	* page. The page checksum will not be stored in the per-VM table as
377	* the idle thread will not be permitted to do modifications to it.
378	* It will instead have to keep its own working set of potentially
379	* shareable pages and their check sums and stuff.
380	*
381	* For the present we'll keep the current packing of the
382	* PGMRAMRANGE::aHCPhys to keep the changes simple, only of course,
383	* we'll have to change it to a struct with a total of 128-bits at
384	* our disposal.
385	*
386	* The initial layout will be like this:
387	* @verbatim
388	RTHCPHYS HCPhys; The current stuff.
389	63:40 Current shadow PT tracking stuff.
390	39:12 The physical page frame number.
391	11:0 The current flags.
392	uint32_t u28PageId : 28; The page id.
393	uint32_t u2State : 2; The page state { zero, shared, normal, write monitored }.
394	uint32_t fWrittenTo : 1; Whether a write monitored page was written to.
395	uint32_t u1Reserved : 1; Reserved for later.
396	uint32_t u32Reserved; Reserved for later, mostly sharing stats.
397	@endverbatim
398	*
399	* The final layout will be something like this:
400	* @verbatim
401	RTHCPHYS HCPhys; The current stuff.
402	63:48 High page id (12+).
403	47:12 The physical page frame number.
404	11:0 Low page id.
405	uint32_t fReadOnly : 1; Whether it's readonly page (rom or monitored in some way).
406	uint32_t u3Type : 3; The page type {RESERVED, MMIO, MMIO2, ROM, shadowed ROM, RAM}.
407	uint32_t u2PhysMon : 2; Physical access handler type {none, read, write, all}.
408	uint32_t u2VirtMon : 2; Virtual access handler type {none, read, write, all}..
409	uint32_t u2State : 2; The page state { zero, shared, normal, write monitored }.
410	uint32_t fWrittenTo : 1; Whether a write monitored page was written to.
411	uint32_t u20Reserved : 20; Reserved for later, mostly sharing stats.
412	uint32_t u32Tracking; The shadow PT tracking stuff, roughly.
413	@endverbatim
414	*
415	* Cost wise, this means we'll double the cost for guest memory. There isn't anyway
416	* around that I'm afraid. It means that the cost of dealing out 32GB of memory
417	* to one or more VMs is: (32GB >> PAGE_SHIFT) * 16 bytes, or 128MBs. Or another
418	* example, the VM heap cost when assigning 1GB to a VM will be: 4MB.
419	*
420	* A couple of cost examples for the total cost per-VM + kernel.
421	* 32-bit Windows and 32-bit linux:
422	* 1GB guest ram, 256K pages: 4MB + 2MB(+) = 6MB
423	* 4GB guest ram, 1M pages: 16MB + 8MB(+) = 24MB
424	* 32GB guest ram, 8M pages: 128MB + 64MB(+) = 192MB
425	* 64-bit Windows and 64-bit linux:
426	* 1GB guest ram, 256K pages: 4MB + 3MB(+) = 7MB
427	* 4GB guest ram, 1M pages: 16MB + 12MB(+) = 28MB
428	* 32GB guest ram, 8M pages: 128MB + 96MB(+) = 224MB
429	*
430	* UPDATE - 2007-09-27:
431	* Will need a ballooned flag/state too because we cannot
432	* trust the guest 100% and reporting the same page as ballooned more
433	* than once will put the GMM off balance.
434	*
435	*
436	* @subsection subsec_pgmPhys_Serializing Serializing Access
437	*
438	* Initially, we'll try a simple scheme:
439	*
440	* - The per-VM RAM tracking structures (PGMRAMRANGE) is only modified
441	* by the EMT thread of that VM while in the pgm critsect.
442	* - Other threads in the VM process that needs to make reliable use of
443	* the per-VM RAM tracking structures will enter the critsect.
444	* - No process external thread or kernel thread will ever try enter
445	* the pgm critical section, as that just won't work.
446	* - The idle thread (and similar threads) doesn't not need 100% reliable
447	* data when performing it tasks as the EMT thread will be the one to
448	* do the actual changes later anyway. So, as long as it only accesses
449	* the main ram range, it can do so by somehow preventing the VM from
450	* being destroyed while it works on it...
451	*
452	* - The over-commitment management, including the allocating/freeing
453	* chunks, is serialized by a ring-0 mutex lock (a fast one since the
454	* more mundane mutex implementation is broken on Linux).
455	* - A separeate mutex is protecting the set of allocation chunks so
456	* that pages can be shared or/and freed up while some other VM is
457	* allocating more chunks. This mutex can be take from under the other
458	* one, but not the otherway around.
459	*
460	*
461	* @subsection subsec_pgmPhys_Request VM Request interface
462	*
463	* When in ring-0 it will become necessary to send requests to a VM so it can
464	* for instance move a page while defragmenting during VM destroy. The idle
465	* thread will make use of this interface to request VMs to setup shared
466	* pages and to perform write monitoring of pages.
467	*
468	* I would propose an interface similar to the current VMReq interface, similar
469	* in that it doesn't require locking and that the one sending the request may
470	* wait for completion if it wishes to. This shouldn't be very difficult to
471	* realize.
472	*
473	* The requests themselves are also pretty simple. They are basically:
474	* -# Check that some precondition is still true.
475	* -# Do the update.
476	* -# Update all shadow page tables involved with the page.
477	*
478	* The 3rd step is identical to what we're already doing when updating a
479	* physical handler, see pgmHandlerPhysicalSetRamFlagsAndFlushShadowPTs.
480	*
481	*
482	*
483	* @section sec_pgmPhys_MappingCaches Mapping Caches
484	*
485	* In order to be able to map in and out memory and to be able to support
486	* guest with more RAM than we've got virtual address space, we'll employing
487	* a mapping cache. There is already a tiny one for GC (see PGMGCDynMapGCPageEx)
488	* and we'll create a similar one for ring-0 unless we decide to setup a dedicate
489	* memory context for the HWACCM execution.
490	*
491	*
492	* @subsection subsec_pgmPhys_MappingCaches_R3 Ring-3
493	*
494	* We've considered implementing the ring-3 mapping cache page based but found
495	* that this was bother some when one had to take into account TLBs+SMP and
496	* portability (missing the necessary APIs on several platforms). There were
497	* also some performance concerns with this approach which hadn't quite been
498	* worked out.
499	*
500	* Instead, we'll be mapping allocation chunks into the VM process. This simplifies
501	* matters greatly quite a bit since we don't need to invent any new ring-0 stuff,
502	* only some minor RTR0MEMOBJ mapping stuff. The main concern here is that mapping
503	* compared to the previous idea is that mapping or unmapping a 1MB chunk is more
504	* costly than a single page, although how much more costly is uncertain. We'll
505	* try address this by using a very big cache, preferably bigger than the actual
506	* VM RAM size if possible. The current VM RAM sizes should give some idea for
507	* 32-bit boxes, while on 64-bit we can probably get away with employing an
508	* unlimited cache.
509	*
510	* The cache have to parts, as already indicated, the ring-3 side and the
511	* ring-0 side.
512	*
513	* The ring-0 will be tied to the page allocator since it will operate on the
514	* memory objects it contains. It will therefore require the first ring-0 mutex
515	* discussed in @ref subsec_pgmPhys_Serializing. We
516	* some double house keeping wrt to who has mapped what I think, since both
517	* VMMR0.r0 and RTR0MemObj will keep track of mapping relataions
518	*
519	* The ring-3 part will be protected by the pgm critsect. For simplicity, we'll
520	* require anyone that desires to do changes to the mapping cache to do that
521	* from within this critsect. Alternatively, we could employ a separate critsect
522	* for serializing changes to the mapping cache as this would reduce potential
523	* contention with other threads accessing mappings unrelated to the changes
524	* that are in process. We can see about this later, contention will show
525	* up in the statistics anyway, so it'll be simple to tell.
526	*
527	* The organization of the ring-3 part will be very much like how the allocation
528	* chunks are organized in ring-0, that is in an AVL tree by chunk id. To avoid
529	* having to walk the tree all the time, we'll have a couple of lookaside entries
530	* like in we do for I/O ports and MMIO in IOM.
531	*
532	* The simplified flow of a PGMPhysRead/Write function:
533	* -# Enter the PGM critsect.
534	* -# Lookup GCPhys in the ram ranges and get the Page ID.
535	* -# Calc the Allocation Chunk ID from the Page ID.
536	* -# Check the lookaside entries and then the AVL tree for the Chunk ID.
537	* If not found in cache:
538	* -# Call ring-0 and request it to be mapped and supply
539	* a chunk to be unmapped if the cache is maxed out already.
540	* -# Insert the new mapping into the AVL tree (id + R3 address).
541	* -# Update the relevant lookaside entry and return the mapping address.
542	* -# Do the read/write according to monitoring flags and everything.
543	* -# Leave the critsect.
544	*
545	*
546	* @section sec_pgmPhys_Fallback Fallback
547	*
548	* Current all the "second tier" hosts will not support the RTR0MemObjAllocPhysNC
549	* API and thus require a fallback.
550	*
551	* So, when RTR0MemObjAllocPhysNC returns VERR_NOT_SUPPORTED the page allocator
552	* will return to the ring-3 caller (and later ring-0) and asking it to seed
553	* the page allocator with some fresh pages (VERR_GMM_SEED_ME). Ring-3 will
554	* then perform an SUPR3PageAlloc(cbChunk >> PAGE_SHIFT) call and make a
555	* "SeededAllocPages" call to ring-0.
556	*
557	* The first time ring-0 sees the VERR_NOT_SUPPORTED failure it will disable
558	* all page sharing (zero page detection will continue). It will also force
559	* all allocations to come from the VM which seeded the page. Both these
560	* measures are taken to make sure that there will never be any need for
561	* mapping anything into ring-3 - everything will be mapped already.
562	*
563	* Whether we'll continue to use the current MM locked memory management
564	* for this I don't quite know (I'd prefer not to and just ditch that all
565	* togther), we'll see what's simplest to do.
566	*
567	*
568	*
569	* @section sec_pgmPhys_Changes Changes
570	*
571	* Breakdown of the changes involved?
572	*/
573
574	/*******************************************************************************
575	* Header Files *
576	*******************************************************************************/
577	#define LOG_GROUP LOG_GROUP_PGM
578	#include <VBox/dbgf.h>
579	#include <VBox/pgm.h>
580	#include <VBox/cpum.h>
581	#include <VBox/iom.h>
582	#include <VBox/sup.h>
583	#include <VBox/mm.h>
584	#include <VBox/em.h>
585	#include <VBox/stam.h>
586	#include <VBox/rem.h>
587	#include <VBox/dbgf.h>
588	#include <VBox/rem.h>
589	#include <VBox/selm.h>
590	#include <VBox/ssm.h>
591	#include <VBox/hwaccm.h>
592	#include "PGMInternal.h"
593	#include <VBox/vm.h>
594
595	#include <VBox/dbg.h>
596	#include <VBox/param.h>
597	#include <VBox/err.h>
598
599	#include <iprt/asm.h>
600	#include <iprt/assert.h>
601	#include <iprt/env.h>
602	#include <iprt/mem.h>
603	#include <iprt/file.h>
604	#include <iprt/string.h>
605	#include <iprt/thread.h>
606
607
608	/*******************************************************************************
609	* Defined Constants And Macros *
610	*******************************************************************************/
611	/** Saved state data unit version for 2.5.x and later. */
612	#define PGM_SAVED_STATE_VERSION 9
613	/** Saved state data unit version for 2.2.2 and later. */
614	#define PGM_SAVED_STATE_VERSION_2_2_2 8
615	/** Saved state data unit version for 2.2.0. */
616	#define PGM_SAVED_STATE_VERSION_RR_DESC 7
617	/** Saved state data unit version. */
618	#define PGM_SAVED_STATE_VERSION_OLD_PHYS_CODE 6
619
620
621	/*******************************************************************************
622	* Internal Functions *
623	*******************************************************************************/
624	static int pgmR3InitPaging(PVM pVM);
625	static void pgmR3InitStats(PVM pVM);
626	static DECLCALLBACK(void) pgmR3PhysInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
627	static DECLCALLBACK(void) pgmR3InfoMode(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
628	static DECLCALLBACK(void) pgmR3InfoCr3(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
629	static DECLCALLBACK(int) pgmR3RelocatePhysHandler(PAVLROGCPHYSNODECORE pNode, void *pvUser);
630	static DECLCALLBACK(int) pgmR3RelocateVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser);
631	static DECLCALLBACK(int) pgmR3RelocateHyperVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser);
632	#ifdef VBOX_STRICT
633	static DECLCALLBACK(void) pgmR3ResetNoMorePhysWritesFlag(PVM pVM, VMSTATE enmState, VMSTATE enmOldState, void *pvUser);
634	#endif
635	static DECLCALLBACK(int) pgmR3Save(PVM pVM, PSSMHANDLE pSSM);
636	static DECLCALLBACK(int) pgmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version);
637	static int pgmR3ModeDataInit(PVM pVM, bool fResolveGCAndR0);
638	static void pgmR3ModeDataSwitch(PVM pVM, PVMCPU pVCpu, PGMMODE enmShw, PGMMODE enmGst);
639	static PGMMODE pgmR3CalcShadowMode(PVM pVM, PGMMODE enmGuestMode, SUPPAGINGMODE enmHostMode, PGMMODE enmShadowMode, VMMSWITCHER *penmSwitcher);
640
641	#ifdef VBOX_WITH_DEBUGGER
642	/** @todo Convert the first two commands to 'info' items. */
643	static DECLCALLBACK(int) pgmR3CmdRam(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
644	static DECLCALLBACK(int) pgmR3CmdMap(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
645	static DECLCALLBACK(int) pgmR3CmdError(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
646	static DECLCALLBACK(int) pgmR3CmdSync(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
647	static DECLCALLBACK(int) pgmR3CmdSyncAlways(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
648	# ifdef VBOX_STRICT
649	static DECLCALLBACK(int) pgmR3CmdAssertCR3(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
650	# endif
651	static DECLCALLBACK(int) pgmR3CmdPhysToFile(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
652	#endif
653
654
655	/*******************************************************************************
656	* Global Variables *
657	*******************************************************************************/
658	#ifdef VBOX_WITH_DEBUGGER
659	/** Argument descriptors for '.pgmerror' and '.pgmerroroff'. */
660	static const DBGCVARDESC g_aPgmErrorArgs[] =
661	{
662	/* cTimesMin, cTimesMax, enmCategory, fFlags, pszName, pszDescription */
663	{ 0, 1, DBGCVAR_CAT_STRING, 0, "where", "Error injection location." },
664	};
665
666	static const DBGCVARDESC g_aPgmPhysToFileArgs[] =
667	{
668	/* cTimesMin, cTimesMax, enmCategory, fFlags, pszName, pszDescription */
669	{ 1, 1, DBGCVAR_CAT_STRING, 0, "file", "The file name." },
670	{ 0, 1, DBGCVAR_CAT_STRING, 0, "nozero", "If present, zero pages are skipped." },
671	};
672
673	/** Command descriptors. */
674	static const DBGCCMD g_aCmds[] =
675	{
676	/* pszCmd, cArgsMin, cArgsMax, paArgDesc, cArgDescs, pResultDesc, fFlags, pfnHandler pszSyntax, ....pszDescription */
677	{ "pgmram", 0, 0, NULL, 0, NULL, 0, pgmR3CmdRam, "", "Display the ram ranges." },
678	{ "pgmmap", 0, 0, NULL, 0, NULL, 0, pgmR3CmdMap, "", "Display the mapping ranges." },
679	{ "pgmsync", 0, 0, NULL, 0, NULL, 0, pgmR3CmdSync, "", "Sync the CR3 page." },
680	{ "pgmerror", 0, 1, &g_aPgmErrorArgs[0], 1, NULL, 0, pgmR3CmdError, "", "Enables inject runtime of errors into parts of PGM." },
681	{ "pgmerroroff", 0, 1, &g_aPgmErrorArgs[0], 1, NULL, 0, pgmR3CmdError, "", "Disables inject runtime errors into parts of PGM." },
682	#ifdef VBOX_STRICT
683	{ "pgmassertcr3", 0, 0, NULL, 0, NULL, 0, pgmR3CmdAssertCR3, "", "Check the shadow CR3 mapping." },
684	#endif
685	{ "pgmsyncalways", 0, 0, NULL, 0, NULL, 0, pgmR3CmdSyncAlways, "", "Toggle permanent CR3 syncing." },
686	{ "pgmphystofile", 1, 2, &g_aPgmPhysToFileArgs[0], 2, NULL, 0, pgmR3CmdPhysToFile, "", "Save the physical memory to file." },
687	};
688	#endif
689
690
691
692
693	/*
694	* Shadow - 32-bit mode
695	*/
696	#define PGM_SHW_TYPE PGM_TYPE_32BIT
697	#define PGM_SHW_NAME(name) PGM_SHW_NAME_32BIT(name)
698	#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_32BIT_STR(name)
699	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_32BIT_STR(name)
700	#include "PGMShw.h"
701
702	/* Guest - real mode */
703	#define PGM_GST_TYPE PGM_TYPE_REAL
704	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
705	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_REAL_STR(name)
706	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
707	#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_REAL(name)
708	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_32BIT_REAL_STR(name)
709	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_32BIT_REAL_STR(name)
710	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_PHYS
711	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_32BIT_PD_PHYS
712	#include "PGMBth.h"
713	#include "PGMGstDefs.h"
714	#include "PGMGst.h"
715	#undef BTH_PGMPOOLKIND_PT_FOR_PT
716	#undef BTH_PGMPOOLKIND_ROOT
717	#undef PGM_BTH_NAME
718	#undef PGM_BTH_NAME_RC_STR
719	#undef PGM_BTH_NAME_R0_STR
720	#undef PGM_GST_TYPE
721	#undef PGM_GST_NAME
722	#undef PGM_GST_NAME_RC_STR
723	#undef PGM_GST_NAME_R0_STR
724
725	/* Guest - protected mode */
726	#define PGM_GST_TYPE PGM_TYPE_PROT
727	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
728	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PROT_STR(name)
729	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
730	#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_PROT(name)
731	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_32BIT_PROT_STR(name)
732	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_32BIT_PROT_STR(name)
733	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_PHYS
734	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_32BIT_PD_PHYS
735	#include "PGMBth.h"
736	#include "PGMGstDefs.h"
737	#include "PGMGst.h"
738	#undef BTH_PGMPOOLKIND_PT_FOR_PT
739	#undef BTH_PGMPOOLKIND_ROOT
740	#undef PGM_BTH_NAME
741	#undef PGM_BTH_NAME_RC_STR
742	#undef PGM_BTH_NAME_R0_STR
743	#undef PGM_GST_TYPE
744	#undef PGM_GST_NAME
745	#undef PGM_GST_NAME_RC_STR
746	#undef PGM_GST_NAME_R0_STR
747
748	/* Guest - 32-bit mode */
749	#define PGM_GST_TYPE PGM_TYPE_32BIT
750	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
751	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_32BIT_STR(name)
752	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
753	#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_32BIT(name)
754	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_32BIT_32BIT_STR(name)
755	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_32BIT_32BIT_STR(name)
756	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT
757	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB
758	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_32BIT_PD
759	#include "PGMBth.h"
760	#include "PGMGstDefs.h"
761	#include "PGMGst.h"
762	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
763	#undef BTH_PGMPOOLKIND_PT_FOR_PT
764	#undef BTH_PGMPOOLKIND_ROOT
765	#undef PGM_BTH_NAME
766	#undef PGM_BTH_NAME_RC_STR
767	#undef PGM_BTH_NAME_R0_STR
768	#undef PGM_GST_TYPE
769	#undef PGM_GST_NAME
770	#undef PGM_GST_NAME_RC_STR
771	#undef PGM_GST_NAME_R0_STR
772
773	#undef PGM_SHW_TYPE
774	#undef PGM_SHW_NAME
775	#undef PGM_SHW_NAME_RC_STR
776	#undef PGM_SHW_NAME_R0_STR
777
778
779	/*
780	* Shadow - PAE mode
781	*/
782	#define PGM_SHW_TYPE PGM_TYPE_PAE
783	#define PGM_SHW_NAME(name) PGM_SHW_NAME_PAE(name)
784	#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_PAE_STR(name)
785	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_PAE_STR(name)
786	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_REAL(name)
787	#include "PGMShw.h"
788
789	/* Guest - real mode */
790	#define PGM_GST_TYPE PGM_TYPE_REAL
791	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
792	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_REAL_STR(name)
793	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
794	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_REAL(name)
795	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_PAE_REAL_STR(name)
796	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_REAL_STR(name)
797	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
798	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT_PHYS
799	#include "PGMGstDefs.h"
800	#include "PGMBth.h"
801	#undef BTH_PGMPOOLKIND_PT_FOR_PT
802	#undef BTH_PGMPOOLKIND_ROOT
803	#undef PGM_BTH_NAME
804	#undef PGM_BTH_NAME_RC_STR
805	#undef PGM_BTH_NAME_R0_STR
806	#undef PGM_GST_TYPE
807	#undef PGM_GST_NAME
808	#undef PGM_GST_NAME_RC_STR
809	#undef PGM_GST_NAME_R0_STR
810
811	/* Guest - protected mode */
812	#define PGM_GST_TYPE PGM_TYPE_PROT
813	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
814	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PROT_STR(name)
815	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
816	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_PROT(name)
817	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_PAE_PROT_STR(name)
818	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_PROT_STR(name)
819	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
820	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT_PHYS
821	#include "PGMGstDefs.h"
822	#include "PGMBth.h"
823	#undef BTH_PGMPOOLKIND_PT_FOR_PT
824	#undef BTH_PGMPOOLKIND_ROOT
825	#undef PGM_BTH_NAME
826	#undef PGM_BTH_NAME_RC_STR
827	#undef PGM_BTH_NAME_R0_STR
828	#undef PGM_GST_TYPE
829	#undef PGM_GST_NAME
830	#undef PGM_GST_NAME_RC_STR
831	#undef PGM_GST_NAME_R0_STR
832
833	/* Guest - 32-bit mode */
834	#define PGM_GST_TYPE PGM_TYPE_32BIT
835	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
836	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_32BIT_STR(name)
837	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
838	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_32BIT(name)
839	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_PAE_32BIT_STR(name)
840	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_32BIT_STR(name)
841	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_32BIT_PT
842	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB
843	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT_FOR_32BIT
844	#include "PGMGstDefs.h"
845	#include "PGMBth.h"
846	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
847	#undef BTH_PGMPOOLKIND_PT_FOR_PT
848	#undef BTH_PGMPOOLKIND_ROOT
849	#undef PGM_BTH_NAME
850	#undef PGM_BTH_NAME_RC_STR
851	#undef PGM_BTH_NAME_R0_STR
852	#undef PGM_GST_TYPE
853	#undef PGM_GST_NAME
854	#undef PGM_GST_NAME_RC_STR
855	#undef PGM_GST_NAME_R0_STR
856
857	/* Guest - PAE mode */
858	#define PGM_GST_TYPE PGM_TYPE_PAE
859	#define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
860	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PAE_STR(name)
861	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PAE_STR(name)
862	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_PAE(name)
863	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_PAE_PAE_STR(name)
864	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_PAE_STR(name)
865	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
866	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
867	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT
868	#include "PGMBth.h"
869	#include "PGMGstDefs.h"
870	#include "PGMGst.h"
871	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
872	#undef BTH_PGMPOOLKIND_PT_FOR_PT
873	#undef BTH_PGMPOOLKIND_ROOT
874	#undef PGM_BTH_NAME
875	#undef PGM_BTH_NAME_RC_STR
876	#undef PGM_BTH_NAME_R0_STR
877	#undef PGM_GST_TYPE
878	#undef PGM_GST_NAME
879	#undef PGM_GST_NAME_RC_STR
880	#undef PGM_GST_NAME_R0_STR
881
882	#undef PGM_SHW_TYPE
883	#undef PGM_SHW_NAME
884	#undef PGM_SHW_NAME_RC_STR
885	#undef PGM_SHW_NAME_R0_STR
886
887
888	/*
889	* Shadow - AMD64 mode
890	*/
891	#define PGM_SHW_TYPE PGM_TYPE_AMD64
892	#define PGM_SHW_NAME(name) PGM_SHW_NAME_AMD64(name)
893	#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_AMD64_STR(name)
894	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_AMD64_STR(name)
895	#include "PGMShw.h"
896
897	#ifdef VBOX_WITH_64_BITS_GUESTS
898	/* Guest - AMD64 mode */
899	# define PGM_GST_TYPE PGM_TYPE_AMD64
900	# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
901	# define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_AMD64_STR(name)
902	# define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_AMD64_STR(name)
903	# define PGM_BTH_NAME(name) PGM_BTH_NAME_AMD64_AMD64(name)
904	# define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_AMD64_AMD64_STR(name)
905	# define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_AMD64_AMD64_STR(name)
906	# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
907	# define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
908	# define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_64BIT_PML4
909	# include "PGMBth.h"
910	# include "PGMGstDefs.h"
911	# include "PGMGst.h"
912	# undef BTH_PGMPOOLKIND_PT_FOR_BIG
913	# undef BTH_PGMPOOLKIND_PT_FOR_PT
914	# undef BTH_PGMPOOLKIND_ROOT
915	# undef PGM_BTH_NAME
916	# undef PGM_BTH_NAME_RC_STR
917	# undef PGM_BTH_NAME_R0_STR
918	# undef PGM_GST_TYPE
919	# undef PGM_GST_NAME
920	# undef PGM_GST_NAME_RC_STR
921	# undef PGM_GST_NAME_R0_STR
922	#endif /* VBOX_WITH_64_BITS_GUESTS */
923
924	#undef PGM_SHW_TYPE
925	#undef PGM_SHW_NAME
926	#undef PGM_SHW_NAME_RC_STR
927	#undef PGM_SHW_NAME_R0_STR
928
929
930	/*
931	* Shadow - Nested paging mode
932	*/
933	#define PGM_SHW_TYPE PGM_TYPE_NESTED
934	#define PGM_SHW_NAME(name) PGM_SHW_NAME_NESTED(name)
935	#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_NESTED_STR(name)
936	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_NESTED_STR(name)
937	#include "PGMShw.h"
938
939	/* Guest - real mode */
940	#define PGM_GST_TYPE PGM_TYPE_REAL
941	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
942	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_REAL_STR(name)
943	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
944	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_REAL(name)
945	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_REAL_STR(name)
946	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_REAL_STR(name)
947	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
948	#include "PGMGstDefs.h"
949	#include "PGMBth.h"
950	#undef BTH_PGMPOOLKIND_PT_FOR_PT
951	#undef PGM_BTH_NAME
952	#undef PGM_BTH_NAME_RC_STR
953	#undef PGM_BTH_NAME_R0_STR
954	#undef PGM_GST_TYPE
955	#undef PGM_GST_NAME
956	#undef PGM_GST_NAME_RC_STR
957	#undef PGM_GST_NAME_R0_STR
958
959	/* Guest - protected mode */
960	#define PGM_GST_TYPE PGM_TYPE_PROT
961	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
962	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PROT_STR(name)
963	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
964	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_PROT(name)
965	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_PROT_STR(name)
966	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_PROT_STR(name)
967	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
968	#include "PGMGstDefs.h"
969	#include "PGMBth.h"
970	#undef BTH_PGMPOOLKIND_PT_FOR_PT
971	#undef PGM_BTH_NAME
972	#undef PGM_BTH_NAME_RC_STR
973	#undef PGM_BTH_NAME_R0_STR
974	#undef PGM_GST_TYPE
975	#undef PGM_GST_NAME
976	#undef PGM_GST_NAME_RC_STR
977	#undef PGM_GST_NAME_R0_STR
978
979	/* Guest - 32-bit mode */
980	#define PGM_GST_TYPE PGM_TYPE_32BIT
981	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
982	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_32BIT_STR(name)
983	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
984	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_32BIT(name)
985	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_32BIT_STR(name)
986	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_32BIT_STR(name)
987	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_32BIT_PT
988	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB
989	#include "PGMGstDefs.h"
990	#include "PGMBth.h"
991	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
992	#undef BTH_PGMPOOLKIND_PT_FOR_PT
993	#undef PGM_BTH_NAME
994	#undef PGM_BTH_NAME_RC_STR
995	#undef PGM_BTH_NAME_R0_STR
996	#undef PGM_GST_TYPE
997	#undef PGM_GST_NAME
998	#undef PGM_GST_NAME_RC_STR
999	#undef PGM_GST_NAME_R0_STR
1000
1001	/* Guest - PAE mode */
1002	#define PGM_GST_TYPE PGM_TYPE_PAE
1003	#define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
1004	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PAE_STR(name)
1005	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PAE_STR(name)
1006	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_PAE(name)
1007	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_PAE_STR(name)
1008	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_PAE_STR(name)
1009	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
1010	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
1011	#include "PGMGstDefs.h"
1012	#include "PGMBth.h"
1013	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
1014	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1015	#undef PGM_BTH_NAME
1016	#undef PGM_BTH_NAME_RC_STR
1017	#undef PGM_BTH_NAME_R0_STR
1018	#undef PGM_GST_TYPE
1019	#undef PGM_GST_NAME
1020	#undef PGM_GST_NAME_RC_STR
1021	#undef PGM_GST_NAME_R0_STR
1022
1023	#ifdef VBOX_WITH_64_BITS_GUESTS
1024	/* Guest - AMD64 mode */
1025	# define PGM_GST_TYPE PGM_TYPE_AMD64
1026	# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
1027	# define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_AMD64_STR(name)
1028	# define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_AMD64_STR(name)
1029	# define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_AMD64(name)
1030	# define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_AMD64_STR(name)
1031	# define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_AMD64_STR(name)
1032	# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
1033	# define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
1034	# include "PGMGstDefs.h"
1035	# include "PGMBth.h"
1036	# undef BTH_PGMPOOLKIND_PT_FOR_BIG
1037	# undef BTH_PGMPOOLKIND_PT_FOR_PT
1038	# undef PGM_BTH_NAME
1039	# undef PGM_BTH_NAME_RC_STR
1040	# undef PGM_BTH_NAME_R0_STR
1041	# undef PGM_GST_TYPE
1042	# undef PGM_GST_NAME
1043	# undef PGM_GST_NAME_RC_STR
1044	# undef PGM_GST_NAME_R0_STR
1045	#endif /* VBOX_WITH_64_BITS_GUESTS */
1046
1047	#undef PGM_SHW_TYPE
1048	#undef PGM_SHW_NAME
1049	#undef PGM_SHW_NAME_RC_STR
1050	#undef PGM_SHW_NAME_R0_STR
1051
1052
1053	/*
1054	* Shadow - EPT
1055	*/
1056	#define PGM_SHW_TYPE PGM_TYPE_EPT
1057	#define PGM_SHW_NAME(name) PGM_SHW_NAME_EPT(name)
1058	#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_EPT_STR(name)
1059	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_EPT_STR(name)
1060	#include "PGMShw.h"
1061
1062	/* Guest - real mode */
1063	#define PGM_GST_TYPE PGM_TYPE_REAL
1064	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
1065	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_REAL_STR(name)
1066	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
1067	#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_REAL(name)
1068	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_REAL_STR(name)
1069	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_REAL_STR(name)
1070	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
1071	#include "PGMGstDefs.h"
1072	#include "PGMBth.h"
1073	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1074	#undef PGM_BTH_NAME
1075	#undef PGM_BTH_NAME_RC_STR
1076	#undef PGM_BTH_NAME_R0_STR
1077	#undef PGM_GST_TYPE
1078	#undef PGM_GST_NAME
1079	#undef PGM_GST_NAME_RC_STR
1080	#undef PGM_GST_NAME_R0_STR
1081
1082	/* Guest - protected mode */
1083	#define PGM_GST_TYPE PGM_TYPE_PROT
1084	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
1085	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PROT_STR(name)
1086	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
1087	#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_PROT(name)
1088	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_PROT_STR(name)
1089	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_PROT_STR(name)
1090	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
1091	#include "PGMGstDefs.h"
1092	#include "PGMBth.h"
1093	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1094	#undef PGM_BTH_NAME
1095	#undef PGM_BTH_NAME_RC_STR
1096	#undef PGM_BTH_NAME_R0_STR
1097	#undef PGM_GST_TYPE
1098	#undef PGM_GST_NAME
1099	#undef PGM_GST_NAME_RC_STR
1100	#undef PGM_GST_NAME_R0_STR
1101
1102	/* Guest - 32-bit mode */
1103	#define PGM_GST_TYPE PGM_TYPE_32BIT
1104	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
1105	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_32BIT_STR(name)
1106	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
1107	#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_32BIT(name)
1108	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_32BIT_STR(name)
1109	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_32BIT_STR(name)
1110	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_32BIT_PT
1111	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB
1112	#include "PGMGstDefs.h"
1113	#include "PGMBth.h"
1114	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
1115	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1116	#undef PGM_BTH_NAME
1117	#undef PGM_BTH_NAME_RC_STR
1118	#undef PGM_BTH_NAME_R0_STR
1119	#undef PGM_GST_TYPE
1120	#undef PGM_GST_NAME
1121	#undef PGM_GST_NAME_RC_STR
1122	#undef PGM_GST_NAME_R0_STR
1123
1124	/* Guest - PAE mode */
1125	#define PGM_GST_TYPE PGM_TYPE_PAE
1126	#define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
1127	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PAE_STR(name)
1128	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PAE_STR(name)
1129	#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_PAE(name)
1130	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_PAE_STR(name)
1131	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_PAE_STR(name)
1132	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
1133	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
1134	#include "PGMGstDefs.h"
1135	#include "PGMBth.h"
1136	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
1137	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1138	#undef PGM_BTH_NAME
1139	#undef PGM_BTH_NAME_RC_STR
1140	#undef PGM_BTH_NAME_R0_STR
1141	#undef PGM_GST_TYPE
1142	#undef PGM_GST_NAME
1143	#undef PGM_GST_NAME_RC_STR
1144	#undef PGM_GST_NAME_R0_STR
1145
1146	#ifdef VBOX_WITH_64_BITS_GUESTS
1147	/* Guest - AMD64 mode */
1148	# define PGM_GST_TYPE PGM_TYPE_AMD64
1149	# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
1150	# define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_AMD64_STR(name)
1151	# define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_AMD64_STR(name)
1152	# define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_AMD64(name)
1153	# define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_AMD64_STR(name)
1154	# define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_AMD64_STR(name)
1155	# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
1156	# define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
1157	# include "PGMGstDefs.h"
1158	# include "PGMBth.h"
1159	# undef BTH_PGMPOOLKIND_PT_FOR_BIG
1160	# undef BTH_PGMPOOLKIND_PT_FOR_PT
1161	# undef PGM_BTH_NAME
1162	# undef PGM_BTH_NAME_RC_STR
1163	# undef PGM_BTH_NAME_R0_STR
1164	# undef PGM_GST_TYPE
1165	# undef PGM_GST_NAME
1166	# undef PGM_GST_NAME_RC_STR
1167	# undef PGM_GST_NAME_R0_STR
1168	#endif /* VBOX_WITH_64_BITS_GUESTS */
1169
1170	#undef PGM_SHW_TYPE
1171	#undef PGM_SHW_NAME
1172	#undef PGM_SHW_NAME_RC_STR
1173	#undef PGM_SHW_NAME_R0_STR
1174
1175
1176
1177	/**
1178	* Initiates the paging of VM.
1179	*
1180	* @returns VBox status code.
1181	* @param pVM Pointer to VM structure.
1182	*/
1183	VMMR3DECL(int) PGMR3Init(PVM pVM)
1184	{
1185	LogFlow(("PGMR3Init:\n"));
1186	PCFGMNODE pCfgPGM = CFGMR3GetChild(CFGMR3GetRoot(pVM), "/PGM");
1187	int rc;
1188
1189	/*
1190	* Assert alignment and sizes.
1191	*/
1192	AssertCompile(sizeof(pVM->pgm.s) <= sizeof(pVM->pgm.padding));
1193	AssertCompileMemberAlignment(PGM, CritSect, sizeof(uintptr_t));
1194
1195	/*
1196	* Init the structure.
1197	*/
1198	pVM->pgm.s.offVM = RT_OFFSETOF(VM, pgm.s);
1199	pVM->pgm.s.offVCpuPGM = RT_OFFSETOF(VMCPU, pgm.s);
1200
1201	/* Init the per-CPU part. */
1202	for (unsigned i=0;i<pVM->cCPUs;i++)
1203	{
1204	PVMCPU pVCpu = &pVM->aCpus[i];
1205	PPGMCPU pPGM = &pVCpu->pgm.s;
1206
1207	pPGM->offVM = (uintptr_t)&pVCpu->pgm.s - (uintptr_t)pVM;
1208	pPGM->offVCpu = RT_OFFSETOF(VMCPU, pgm.s);
1209	pPGM->offPGM = (uintptr_t)&pVCpu->pgm.s - (uintptr_t)&pVM->pgm.s;
1210
1211	pPGM->enmShadowMode = PGMMODE_INVALID;
1212	pPGM->enmGuestMode = PGMMODE_INVALID;
1213
1214	pPGM->GCPhysCR3 = NIL_RTGCPHYS;
1215
1216	pPGM->pGstPaePdptR3 = NULL;
1217	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
1218	pPGM->pGstPaePdptR0 = NIL_RTR0PTR;
1219	#endif
1220	pPGM->pGstPaePdptRC = NIL_RTRCPTR;
1221	for (unsigned i = 0; i < RT_ELEMENTS(pVCpu->pgm.s.apGstPaePDsR3); i++)
1222	{
1223	pPGM->apGstPaePDsR3[i] = NULL;
1224	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
1225	pPGM->apGstPaePDsR0[i] = NIL_RTR0PTR;
1226	#endif
1227	pPGM->apGstPaePDsRC[i] = NIL_RTRCPTR;
1228	pPGM->aGCPhysGstPaePDs[i] = NIL_RTGCPHYS;
1229	pPGM->aGCPhysGstPaePDsMonitored[i] = NIL_RTGCPHYS;
1230	}
1231
1232	pPGM->fA20Enabled = true;
1233	}
1234
1235	pVM->pgm.s.enmHostMode = SUPPAGINGMODE_INVALID;
1236	pVM->pgm.s.GCPhys4MBPSEMask = RT_BIT_64(32) - 1; /* default; checked later */
1237	pVM->pgm.s.GCPtrPrevRamRangeMapping = MM_HYPER_AREA_ADDRESS;
1238
1239	rc = CFGMR3QueryBoolDef(CFGMR3GetRoot(pVM), "RamPreAlloc", &pVM->pgm.s.fRamPreAlloc,
1240	#ifdef VBOX_WITH_PREALLOC_RAM_BY_DEFAULT
1241	true
1242	#else
1243	false
1244	#endif
1245	);
1246	AssertLogRelRCReturn(rc, rc);
1247
1248	#if HC_ARCH_BITS == 64 \|\| 1 /** @todo 4GB/32-bit: remove \|\| 1 later and adjust the limit. */
1249	rc = CFGMR3QueryU32Def(pCfgPGM, "MaxRing3Chunks", &pVM->pgm.s.ChunkR3Map.cMax, UINT32_MAX);
1250	#else
1251	rc = CFGMR3QueryU32Def(pCfgPGM, "MaxRing3Chunks", &pVM->pgm.s.ChunkR3Map.cMax, _1G / GMM_CHUNK_SIZE);
1252	#endif
1253	AssertLogRelRCReturn(rc, rc);
1254	for (uint32_t i = 0; i < RT_ELEMENTS(pVM->pgm.s.ChunkR3Map.Tlb.aEntries); i++)
1255	pVM->pgm.s.ChunkR3Map.Tlb.aEntries[i].idChunk = NIL_GMM_CHUNKID;
1256
1257	/*
1258	* Get the configured RAM size - to estimate saved state size.
1259	*/
1260	uint64_t cbRam;
1261	rc = CFGMR3QueryU64(CFGMR3GetRoot(pVM), "RamSize", &cbRam);
1262	if (rc == VERR_CFGM_VALUE_NOT_FOUND)
1263	cbRam = 0;
1264	else if (RT_SUCCESS(rc))
1265	{
1266	if (cbRam < PAGE_SIZE)
1267	cbRam = 0;
1268	cbRam = RT_ALIGN_64(cbRam, PAGE_SIZE);
1269	}
1270	else
1271	{
1272	AssertMsgFailed(("Configuration error: Failed to query integer \"RamSize\", rc=%Rrc.\n", rc));
1273	return rc;
1274	}
1275
1276	/*
1277	* Register callbacks, string formatters and the saved state data unit.
1278	*/
1279	#ifdef VBOX_STRICT
1280	VMR3AtStateRegister(pVM, pgmR3ResetNoMorePhysWritesFlag, NULL);
1281	#endif
1282	PGMRegisterStringFormatTypes();
1283
1284	rc = SSMR3RegisterInternal(pVM, "pgm", 1, PGM_SAVED_STATE_VERSION, (size_t)cbRam + sizeof(PGM),
1285	NULL, pgmR3Save, NULL,
1286	NULL, pgmR3Load, NULL);
1287	if (RT_FAILURE(rc))
1288	return rc;
1289
1290	/*
1291	* Initialize the PGM critical section and flush the phys TLBs
1292	*/
1293	rc = PDMR3CritSectInit(pVM, &pVM->pgm.s.CritSect, "PGM");
1294	AssertRCReturn(rc, rc);
1295
1296	PGMR3PhysChunkInvalidateTLB(pVM);
1297	PGMPhysInvalidatePageR3MapTLB(pVM);
1298	PGMPhysInvalidatePageR0MapTLB(pVM);
1299	PGMPhysInvalidatePageGCMapTLB(pVM);
1300
1301	/*
1302	* For the time being we sport a full set of handy pages in addition to the base
1303	* memory to simplify things.
1304	*/
1305	rc = MMR3ReserveHandyPages(pVM, RT_ELEMENTS(pVM->pgm.s.aHandyPages)); /** @todo this should be changed to PGM_HANDY_PAGES_MIN but this needs proper testing... */
1306	AssertRCReturn(rc, rc);
1307
1308	/*
1309	* Trees
1310	*/
1311	rc = MMHyperAlloc(pVM, sizeof(PGMTREES), 0, MM_TAG_PGM, (void **)&pVM->pgm.s.pTreesR3);
1312	if (RT_SUCCESS(rc))
1313	{
1314	pVM->pgm.s.pTreesR0 = MMHyperR3ToR0(pVM, pVM->pgm.s.pTreesR3);
1315	pVM->pgm.s.pTreesRC = MMHyperR3ToRC(pVM, pVM->pgm.s.pTreesR3);
1316
1317	/*
1318	* Alocate the zero page.
1319	*/
1320	rc = MMHyperAlloc(pVM, PAGE_SIZE, PAGE_SIZE, MM_TAG_PGM, &pVM->pgm.s.pvZeroPgR3);
1321	}
1322	if (RT_SUCCESS(rc))
1323	{
1324	pVM->pgm.s.pvZeroPgRC = MMHyperR3ToRC(pVM, pVM->pgm.s.pvZeroPgR3);
1325	pVM->pgm.s.pvZeroPgR0 = MMHyperR3ToR0(pVM, pVM->pgm.s.pvZeroPgR3);
1326	pVM->pgm.s.HCPhysZeroPg = MMR3HyperHCVirt2HCPhys(pVM, pVM->pgm.s.pvZeroPgR3);
1327	AssertRelease(pVM->pgm.s.HCPhysZeroPg != NIL_RTHCPHYS);
1328
1329	/*
1330	* Init the paging.
1331	*/
1332	rc = pgmR3InitPaging(pVM);
1333	}
1334	if (RT_SUCCESS(rc))
1335	{
1336	/*
1337	* Init the page pool.
1338	*/
1339	rc = pgmR3PoolInit(pVM);
1340	}
1341	if (RT_SUCCESS(rc))
1342	{
1343	for (unsigned i=0;i<pVM->cCPUs;i++)
1344	{
1345	PVMCPU pVCpu = &pVM->aCpus[i];
1346
1347	rc = PGMR3ChangeMode(pVM, pVCpu, PGMMODE_REAL);
1348	if (RT_FAILURE(rc))
1349	break;
1350	}
1351	}
1352
1353	if (RT_SUCCESS(rc))
1354	{
1355	/*
1356	* Info & statistics
1357	*/
1358	DBGFR3InfoRegisterInternal(pVM, "mode",
1359	"Shows the current paging mode. "
1360	"Recognizes 'all', 'guest', 'shadow' and 'host' as arguments, defaulting to 'all' if nothing's given.",
1361	pgmR3InfoMode);
1362	DBGFR3InfoRegisterInternal(pVM, "pgmcr3",
1363	"Dumps all the entries in the top level paging table. No arguments.",
1364	pgmR3InfoCr3);
1365	DBGFR3InfoRegisterInternal(pVM, "phys",
1366	"Dumps all the physical address ranges. No arguments.",
1367	pgmR3PhysInfo);
1368	DBGFR3InfoRegisterInternal(pVM, "handlers",
1369	"Dumps physical, virtual and hyper virtual handlers. "
1370	"Pass 'phys', 'virt', 'hyper' as argument if only one kind is wanted."
1371	"Add 'nost' if the statistics are unwanted, use together with 'all' or explicit selection.",
1372	pgmR3InfoHandlers);
1373	DBGFR3InfoRegisterInternal(pVM, "mappings",
1374	"Dumps guest mappings.",
1375	pgmR3MapInfo);
1376
1377	pgmR3InitStats(pVM);
1378
1379	#ifdef VBOX_WITH_DEBUGGER
1380	/*
1381	* Debugger commands.
1382	*/
1383	static bool s_fRegisteredCmds = false;
1384	if (!s_fRegisteredCmds)
1385	{
1386	int rc = DBGCRegisterCommands(&g_aCmds[0], RT_ELEMENTS(g_aCmds));
1387	if (RT_SUCCESS(rc))
1388	s_fRegisteredCmds = true;
1389	}
1390	#endif
1391	return VINF_SUCCESS;
1392	}
1393
1394	/* Almost no cleanup necessary, MM frees all memory. */
1395	PDMR3CritSectDelete(&pVM->pgm.s.CritSect);
1396
1397	return rc;
1398	}
1399
1400
1401	/**
1402	* Initializes the per-VCPU PGM.
1403	*
1404	* @returns VBox status code.
1405	* @param pVM The VM to operate on.
1406	*/
1407	VMMR3DECL(int) PGMR3InitCPU(PVM pVM)
1408	{
1409	LogFlow(("PGMR3InitCPU\n"));
1410	return VINF_SUCCESS;
1411	}
1412
1413
1414	/**
1415	* Init paging.
1416	*
1417	* Since we need to check what mode the host is operating in before we can choose
1418	* the right paging functions for the host we have to delay this until R0 has
1419	* been initialized.
1420	*
1421	* @returns VBox status code.
1422	* @param pVM VM handle.
1423	*/
1424	static int pgmR3InitPaging(PVM pVM)
1425	{
1426	/*
1427	* Force a recalculation of modes and switcher so everyone gets notified.
1428	*/
1429	for (unsigned i=0;i<pVM->cCPUs;i++)
1430	{
1431	PVMCPU pVCpu = &pVM->aCpus[i];
1432
1433	pVCpu->pgm.s.enmShadowMode = PGMMODE_INVALID;
1434	pVCpu->pgm.s.enmGuestMode = PGMMODE_INVALID;
1435	}
1436
1437	pVM->pgm.s.enmHostMode = SUPPAGINGMODE_INVALID;
1438
1439	/*
1440	* Allocate static mapping space for whatever the cr3 register
1441	* points to and in the case of PAE mode to the 4 PDs.
1442	*/
1443	int rc = MMR3HyperReserve(pVM, PAGE_SIZE * 5, "CR3 mapping", &pVM->pgm.s.GCPtrCR3Mapping);
1444	if (RT_FAILURE(rc))
1445	{
1446	AssertMsgFailed(("Failed to reserve two pages for cr mapping in HMA, rc=%Rrc\n", rc));
1447	return rc;
1448	}
1449	MMR3HyperReserve(pVM, PAGE_SIZE, "fence", NULL);
1450
1451	/*
1452	* Allocate pages for the three possible intermediate contexts
1453	* (AMD64, PAE and plain 32-Bit). We maintain all three contexts
1454	* for the sake of simplicity. The AMD64 uses the PAE for the
1455	* lower levels, making the total number of pages 11 (3 + 7 + 1).
1456	*
1457	* We assume that two page tables will be enought for the core code
1458	* mappings (HC virtual and identity).
1459	*/
1460	pVM->pgm.s.pInterPD = (PX86PD)MMR3PageAllocLow(pVM); AssertReturn(pVM->pgm.s.pInterPD, VERR_NO_PAGE_MEMORY);
1461	pVM->pgm.s.apInterPTs[0] = (PX86PT)MMR3PageAllocLow(pVM); AssertReturn(pVM->pgm.s.apInterPTs[0], VERR_NO_PAGE_MEMORY);
1462	pVM->pgm.s.apInterPTs[1] = (PX86PT)MMR3PageAllocLow(pVM); AssertReturn(pVM->pgm.s.apInterPTs[1], VERR_NO_PAGE_MEMORY);
1463	pVM->pgm.s.apInterPaePTs[0] = (PX86PTPAE)MMR3PageAlloc(pVM); AssertReturn(pVM->pgm.s.apInterPaePTs[0], VERR_NO_PAGE_MEMORY);
1464	pVM->pgm.s.apInterPaePTs[1] = (PX86PTPAE)MMR3PageAlloc(pVM); AssertReturn(pVM->pgm.s.apInterPaePTs[1], VERR_NO_PAGE_MEMORY);
1465	pVM->pgm.s.apInterPaePDs[0] = (PX86PDPAE)MMR3PageAlloc(pVM); AssertReturn(pVM->pgm.s.apInterPaePDs[0], VERR_NO_PAGE_MEMORY);
1466	pVM->pgm.s.apInterPaePDs[1] = (PX86PDPAE)MMR3PageAlloc(pVM); AssertReturn(pVM->pgm.s.apInterPaePDs[1], VERR_NO_PAGE_MEMORY);
1467	pVM->pgm.s.apInterPaePDs[2] = (PX86PDPAE)MMR3PageAlloc(pVM); AssertReturn(pVM->pgm.s.apInterPaePDs[2], VERR_NO_PAGE_MEMORY);
1468	pVM->pgm.s.apInterPaePDs[3] = (PX86PDPAE)MMR3PageAlloc(pVM); AssertReturn(pVM->pgm.s.apInterPaePDs[3], VERR_NO_PAGE_MEMORY);
1469	pVM->pgm.s.pInterPaePDPT = (PX86PDPT)MMR3PageAllocLow(pVM); AssertReturn(pVM->pgm.s.pInterPaePDPT, VERR_NO_PAGE_MEMORY);
1470	pVM->pgm.s.pInterPaePDPT64 = (PX86PDPT)MMR3PageAllocLow(pVM); AssertReturn(pVM->pgm.s.pInterPaePDPT64, VERR_NO_PAGE_MEMORY);
1471	pVM->pgm.s.pInterPaePML4 = (PX86PML4)MMR3PageAllocLow(pVM); AssertReturn(pVM->pgm.s.pInterPaePML4, VERR_NO_PAGE_MEMORY);
1472
1473	pVM->pgm.s.HCPhysInterPD = MMPage2Phys(pVM, pVM->pgm.s.pInterPD);
1474	AssertRelease(pVM->pgm.s.HCPhysInterPD != NIL_RTHCPHYS && !(pVM->pgm.s.HCPhysInterPD & PAGE_OFFSET_MASK));
1475	pVM->pgm.s.HCPhysInterPaePDPT = MMPage2Phys(pVM, pVM->pgm.s.pInterPaePDPT);
1476	AssertRelease(pVM->pgm.s.HCPhysInterPaePDPT != NIL_RTHCPHYS && !(pVM->pgm.s.HCPhysInterPaePDPT & PAGE_OFFSET_MASK));
1477	pVM->pgm.s.HCPhysInterPaePML4 = MMPage2Phys(pVM, pVM->pgm.s.pInterPaePML4);
1478	AssertRelease(pVM->pgm.s.HCPhysInterPaePML4 != NIL_RTHCPHYS && !(pVM->pgm.s.HCPhysInterPaePML4 & PAGE_OFFSET_MASK) && pVM->pgm.s.HCPhysInterPaePML4 < 0xffffffff);
1479
1480	/*
1481	* Initialize the pages, setting up the PML4 and PDPT for repetitive 4GB action.
1482	*/
1483	ASMMemZeroPage(pVM->pgm.s.pInterPD);
1484	ASMMemZeroPage(pVM->pgm.s.apInterPTs[0]);
1485	ASMMemZeroPage(pVM->pgm.s.apInterPTs[1]);
1486
1487	ASMMemZeroPage(pVM->pgm.s.apInterPaePTs[0]);
1488	ASMMemZeroPage(pVM->pgm.s.apInterPaePTs[1]);
1489
1490	ASMMemZeroPage(pVM->pgm.s.pInterPaePDPT);
1491	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.apInterPaePDs); i++)
1492	{
1493	ASMMemZeroPage(pVM->pgm.s.apInterPaePDs[i]);
1494	pVM->pgm.s.pInterPaePDPT->a[i].u = X86_PDPE_P \| PGM_PLXFLAGS_PERMANENT
1495	\| MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[i]);
1496	}
1497
1498	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.pInterPaePDPT64->a); i++)
1499	{
1500	const unsigned iPD = i % RT_ELEMENTS(pVM->pgm.s.apInterPaePDs);
1501	pVM->pgm.s.pInterPaePDPT64->a[i].u = X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_A \| PGM_PLXFLAGS_PERMANENT
1502	\| MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[iPD]);
1503	}
1504
1505	RTHCPHYS HCPhysInterPaePDPT64 = MMPage2Phys(pVM, pVM->pgm.s.pInterPaePDPT64);
1506	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.pInterPaePML4->a); i++)
1507	pVM->pgm.s.pInterPaePML4->a[i].u = X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_A \| PGM_PLXFLAGS_PERMANENT
1508	\| HCPhysInterPaePDPT64;
1509
1510	/*
1511	* Initialize paging workers and mode from current host mode
1512	* and the guest running in real mode.
1513	*/
1514	pVM->pgm.s.enmHostMode = SUPR3GetPagingMode();
1515	switch (pVM->pgm.s.enmHostMode)
1516	{
1517	case SUPPAGINGMODE_32_BIT:
1518	case SUPPAGINGMODE_32_BIT_GLOBAL:
1519	case SUPPAGINGMODE_PAE:
1520	case SUPPAGINGMODE_PAE_GLOBAL:
1521	case SUPPAGINGMODE_PAE_NX:
1522	case SUPPAGINGMODE_PAE_GLOBAL_NX:
1523	break;
1524
1525	case SUPPAGINGMODE_AMD64:
1526	case SUPPAGINGMODE_AMD64_GLOBAL:
1527	case SUPPAGINGMODE_AMD64_NX:
1528	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
1529	#ifndef VBOX_WITH_HYBRID_32BIT_KERNEL
1530	if (ARCH_BITS != 64)
1531	{
1532	AssertMsgFailed(("Host mode %d (64-bit) is not supported by non-64bit builds\n", pVM->pgm.s.enmHostMode));
1533	LogRel(("Host mode %d (64-bit) is not supported by non-64bit builds\n", pVM->pgm.s.enmHostMode));
1534	return VERR_PGM_UNSUPPORTED_HOST_PAGING_MODE;
1535	}
1536	#endif
1537	break;
1538	default:
1539	AssertMsgFailed(("Host mode %d is not supported\n", pVM->pgm.s.enmHostMode));
1540	return VERR_PGM_UNSUPPORTED_HOST_PAGING_MODE;
1541	}
1542	rc = pgmR3ModeDataInit(pVM, false /* don't resolve GC and R0 syms yet */);
1543	if (RT_SUCCESS(rc))
1544	{
1545	LogFlow(("pgmR3InitPaging: returns successfully\n"));
1546	#if HC_ARCH_BITS == 64
1547	LogRel(("Debug: HCPhysInterPD=%RHp HCPhysInterPaePDPT=%RHp HCPhysInterPaePML4=%RHp\n",
1548	pVM->pgm.s.HCPhysInterPD, pVM->pgm.s.HCPhysInterPaePDPT, pVM->pgm.s.HCPhysInterPaePML4));
1549	LogRel(("Debug: apInterPTs={%RHp,%RHp} apInterPaePTs={%RHp,%RHp} apInterPaePDs={%RHp,%RHp,%RHp,%RHp} pInterPaePDPT64=%RHp\n",
1550	MMPage2Phys(pVM, pVM->pgm.s.apInterPTs[0]), MMPage2Phys(pVM, pVM->pgm.s.apInterPTs[1]),
1551	MMPage2Phys(pVM, pVM->pgm.s.apInterPaePTs[0]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePTs[1]),
1552	MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[0]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[1]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[2]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[3]),
1553	MMPage2Phys(pVM, pVM->pgm.s.pInterPaePDPT64)));
1554	#endif
1555
1556	return VINF_SUCCESS;
1557	}
1558
1559	LogFlow(("pgmR3InitPaging: returns %Rrc\n", rc));
1560	return rc;
1561	}
1562
1563
1564	/**
1565	* Init statistics
1566	*/
1567	static void pgmR3InitStats(PVM pVM)
1568	{
1569	PPGM pPGM = &pVM->pgm.s;
1570	int rc;
1571
1572	/* Common - misc variables */
1573	STAM_REL_REG(pVM, &pPGM->cAllPages, STAMTYPE_U32, "/PGM/Page/cAllPages", STAMUNIT_OCCURENCES, "The total number of pages.");
1574	STAM_REL_REG(pVM, &pPGM->cPrivatePages, STAMTYPE_U32, "/PGM/Page/cPrivatePages", STAMUNIT_OCCURENCES, "The number of private pages.");
1575	STAM_REL_REG(pVM, &pPGM->cSharedPages, STAMTYPE_U32, "/PGM/Page/cSharedPages", STAMUNIT_OCCURENCES, "The number of shared pages.");
1576	STAM_REL_REG(pVM, &pPGM->cZeroPages, STAMTYPE_U32, "/PGM/Page/cZeroPages", STAMUNIT_OCCURENCES, "The number of zero backed pages.");
1577	STAM_REL_REG(pVM, &pPGM->cHandyPages, STAMTYPE_U32, "/PGM/Page/cHandyPages", STAMUNIT_OCCURENCES, "The number of handy pages (not included in cAllPages).");
1578	STAM_REL_REG(pVM, &pPGM->cRelocations, STAMTYPE_COUNTER, "/PGM/cRelocations", STAMUNIT_OCCURENCES, "Number of hypervisor relocations.");
1579	STAM_REL_REG(pVM, &pPGM->ChunkR3Map.c, STAMTYPE_U32, "/PGM/ChunkR3Map/c", STAMUNIT_OCCURENCES, "Number of mapped chunks.");
1580	STAM_REL_REG(pVM, &pPGM->ChunkR3Map.cMax, STAMTYPE_U32, "/PGM/ChunkR3Map/cMax", STAMUNIT_OCCURENCES, "Maximum number of mapped chunks.");
1581
1582	#ifdef VBOX_WITH_STATISTICS
1583
1584	# define PGM_REG_COUNTER(a, b, c) \
1585	rc = STAMR3RegisterF(pVM, a, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, c, b); \
1586	AssertRC(rc);
1587
1588	# define PGM_REG_COUNTER_BYTES(a, b, c) \
1589	rc = STAMR3RegisterF(pVM, a, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_BYTES, c, b); \
1590	AssertRC(rc);
1591
1592	# define PGM_REG_PROFILE(a, b, c) \
1593	rc = STAMR3RegisterF(pVM, a, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, c, b); \
1594	AssertRC(rc);
1595
1596	PGM_REG_COUNTER(&pPGM->StatR3DetectedConflicts, "/PGM/R3/DetectedConflicts", "The number of times PGMR3CheckMappingConflicts() detected a conflict.");
1597	PGM_REG_PROFILE(&pPGM->StatR3ResolveConflict, "/PGM/R3/ResolveConflict", "pgmR3SyncPTResolveConflict() profiling (includes the entire relocation).");
1598	PGM_REG_COUNTER(&pPGM->StatR3PhysRead, "/PGM/R3/Phys/Read", "The number of times PGMPhysRead was called.");
1599	PGM_REG_COUNTER_BYTES(&pPGM->StatR3PhysReadBytes, "/PGM/R3/Phys/Read/Bytes", "The number of bytes read by PGMPhysRead.");
1600	PGM_REG_COUNTER(&pPGM->StatR3PhysWrite, "/PGM/R3/Phys/Write", "The number of times PGMPhysWrite was called.");
1601	PGM_REG_COUNTER_BYTES(&pPGM->StatR3PhysWriteBytes, "/PGM/R3/Phys/Write/Bytes", "The number of bytes written by PGMPhysWrite.");
1602	PGM_REG_COUNTER(&pPGM->StatR3PhysSimpleRead, "/PGM/R3/Phys/Simple/Read", "The number of times PGMPhysSimpleReadGCPtr was called.");
1603	PGM_REG_COUNTER_BYTES(&pPGM->StatR3PhysSimpleReadBytes, "/PGM/R3/Phys/Simple/Read/Bytes", "The number of bytes read by PGMPhysSimpleReadGCPtr.");
1604	PGM_REG_COUNTER(&pPGM->StatR3PhysSimpleWrite, "/PGM/R3/Phys/Simple/Write", "The number of times PGMPhysSimpleWriteGCPtr was called.");
1605	PGM_REG_COUNTER_BYTES(&pPGM->StatR3PhysSimpleWriteBytes, "/PGM/R3/Phys/Simple/Write/Bytes", "The number of bytes written by PGMPhysSimpleWriteGCPtr.");
1606
1607	PGM_REG_COUNTER(&pPGM->StatRZChunkR3MapTlbHits, "/PGM/ChunkR3Map/TlbHitsRZ", "TLB hits.");
1608	PGM_REG_COUNTER(&pPGM->StatRZChunkR3MapTlbMisses, "/PGM/ChunkR3Map/TlbMissesRZ", "TLB misses.");
1609	PGM_REG_COUNTER(&pPGM->StatRZPageMapTlbHits, "/PGM/RZ/Page/MapTlbHits", "TLB hits.");
1610	PGM_REG_COUNTER(&pPGM->StatRZPageMapTlbMisses, "/PGM/RZ/Page/MapTlbMisses", "TLB misses.");
1611	PGM_REG_COUNTER(&pPGM->StatR3ChunkR3MapTlbHits, "/PGM/ChunkR3Map/TlbHitsR3", "TLB hits.");
1612	PGM_REG_COUNTER(&pPGM->StatR3ChunkR3MapTlbMisses, "/PGM/ChunkR3Map/TlbMissesR3", "TLB misses.");
1613	PGM_REG_COUNTER(&pPGM->StatR3PageMapTlbHits, "/PGM/R3/Page/MapTlbHits", "TLB hits.");
1614	PGM_REG_COUNTER(&pPGM->StatR3PageMapTlbMisses, "/PGM/R3/Page/MapTlbMisses", "TLB misses.");
1615
1616	PGM_REG_PROFILE(&pPGM->StatRZSyncCR3HandlerVirtualUpdate, "/PGM/RZ/SyncCR3/Handlers/VirtualUpdate", "Profiling of the virtual handler updates.");
1617	PGM_REG_PROFILE(&pPGM->StatRZSyncCR3HandlerVirtualReset, "/PGM/RZ/SyncCR3/Handlers/VirtualReset", "Profiling of the virtual handler resets.");
1618	PGM_REG_PROFILE(&pPGM->StatR3SyncCR3HandlerVirtualUpdate, "/PGM/R3/SyncCR3/Handlers/VirtualUpdate", "Profiling of the virtual handler updates.");
1619	PGM_REG_PROFILE(&pPGM->StatR3SyncCR3HandlerVirtualReset, "/PGM/R3/SyncCR3/Handlers/VirtualReset", "Profiling of the virtual handler resets.");
1620
1621	PGM_REG_COUNTER(&pPGM->StatRZPhysHandlerReset, "/PGM/RZ/PhysHandlerReset", "The number of times PGMHandlerPhysicalReset is called.");
1622	PGM_REG_COUNTER(&pPGM->StatR3PhysHandlerReset, "/PGM/R3/PhysHandlerReset", "The number of times PGMHandlerPhysicalReset is called.");
1623	PGM_REG_PROFILE(&pPGM->StatRZVirtHandlerSearchByPhys, "/PGM/RZ/VirtHandlerSearchByPhys", "Profiling of pgmHandlerVirtualFindByPhysAddr.");
1624	PGM_REG_PROFILE(&pPGM->StatR3VirtHandlerSearchByPhys, "/PGM/R3/VirtHandlerSearchByPhys", "Profiling of pgmHandlerVirtualFindByPhysAddr.");
1625
1626	PGM_REG_COUNTER(&pPGM->StatRZPageReplaceShared, "/PGM/RZ/Page/ReplacedShared", "Times a shared page was replaced.");
1627	PGM_REG_COUNTER(&pPGM->StatRZPageReplaceZero, "/PGM/RZ/Page/ReplacedZero", "Times the zero page was replaced.");
1628	/// @todo PGM_REG_COUNTER(&pPGM->StatRZPageHandyAllocs, "/PGM/RZ/Page/HandyAllocs", "Number of times we've allocated more handy pages.");
1629	PGM_REG_COUNTER(&pPGM->StatR3PageReplaceShared, "/PGM/R3/Page/ReplacedShared", "Times a shared page was replaced.");
1630	PGM_REG_COUNTER(&pPGM->StatR3PageReplaceZero, "/PGM/R3/Page/ReplacedZero", "Times the zero page was replaced.");
1631	/// @todo PGM_REG_COUNTER(&pPGM->StatR3PageHandyAllocs, "/PGM/R3/Page/HandyAllocs", "Number of times we've allocated more handy pages.");
1632
1633	PGM_REG_COUNTER(&pPGM->StatRZPhysRead, "/PGM/RZ/Phys/Read", "The number of times PGMPhysRead was called.");
1634	PGM_REG_COUNTER_BYTES(&pPGM->StatRZPhysReadBytes, "/PGM/RZ/Phys/Read/Bytes", "The number of bytes read by PGMPhysRead.");
1635	PGM_REG_COUNTER(&pPGM->StatRZPhysWrite, "/PGM/RZ/Phys/Write", "The number of times PGMPhysWrite was called.");
1636	PGM_REG_COUNTER_BYTES(&pPGM->StatRZPhysWriteBytes, "/PGM/RZ/Phys/Write/Bytes", "The number of bytes written by PGMPhysWrite.");
1637	PGM_REG_COUNTER(&pPGM->StatRZPhysSimpleRead, "/PGM/RZ/Phys/Simple/Read", "The number of times PGMPhysSimpleReadGCPtr was called.");
1638	PGM_REG_COUNTER_BYTES(&pPGM->StatRZPhysSimpleReadBytes, "/PGM/RZ/Phys/Simple/Read/Bytes", "The number of bytes read by PGMPhysSimpleReadGCPtr.");
1639	PGM_REG_COUNTER(&pPGM->StatRZPhysSimpleWrite, "/PGM/RZ/Phys/Simple/Write", "The number of times PGMPhysSimpleWriteGCPtr was called.");
1640	PGM_REG_COUNTER_BYTES(&pPGM->StatRZPhysSimpleWriteBytes, "/PGM/RZ/Phys/Simple/Write/Bytes", "The number of bytes written by PGMPhysSimpleWriteGCPtr.");
1641
1642	/* GC only: */
1643	PGM_REG_COUNTER(&pPGM->StatRCDynMapCacheHits, "/PGM/RC/DynMapCache/Hits" , "Number of dynamic page mapping cache hits.");
1644	PGM_REG_COUNTER(&pPGM->StatRCDynMapCacheMisses, "/PGM/RC/DynMapCache/Misses" , "Number of dynamic page mapping cache misses.");
1645	PGM_REG_COUNTER(&pPGM->StatRCInvlPgConflict, "/PGM/RC/InvlPgConflict", "Number of times PGMInvalidatePage() detected a mapping conflict.");
1646	PGM_REG_COUNTER(&pPGM->StatRCInvlPgSyncMonCR3, "/PGM/RC/InvlPgSyncMonitorCR3", "Number of times PGMInvalidatePage() ran into PGM_SYNC_MONITOR_CR3.");
1647
1648	PGM_REG_COUNTER(&pPGM->StatRCPhysRead, "/PGM/RC/Phys/Read", "The number of times PGMPhysRead was called.");
1649	PGM_REG_COUNTER_BYTES(&pPGM->StatRCPhysReadBytes, "/PGM/RC/Phys/Read/Bytes", "The number of bytes read by PGMPhysRead.");
1650	PGM_REG_COUNTER(&pPGM->StatRCPhysWrite, "/PGM/RC/Phys/Write", "The number of times PGMPhysWrite was called.");
1651	PGM_REG_COUNTER_BYTES(&pPGM->StatRCPhysWriteBytes, "/PGM/RC/Phys/Write/Bytes", "The number of bytes written by PGMPhysWrite.");
1652	PGM_REG_COUNTER(&pPGM->StatRCPhysSimpleRead, "/PGM/RC/Phys/Simple/Read", "The number of times PGMPhysSimpleReadGCPtr was called.");
1653	PGM_REG_COUNTER_BYTES(&pPGM->StatRCPhysSimpleReadBytes, "/PGM/RC/Phys/Simple/Read/Bytes", "The number of bytes read by PGMPhysSimpleReadGCPtr.");
1654	PGM_REG_COUNTER(&pPGM->StatRCPhysSimpleWrite, "/PGM/RC/Phys/Simple/Write", "The number of times PGMPhysSimpleWriteGCPtr was called.");
1655	PGM_REG_COUNTER_BYTES(&pPGM->StatRCPhysSimpleWriteBytes, "/PGM/RC/Phys/Simple/Write/Bytes", "The number of bytes written by PGMPhysSimpleWriteGCPtr.");
1656
1657	# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
1658	PGM_REG_COUNTER(&pPGM->StatTrackVirgin, "/PGM/Track/Virgin", "The number of first time shadowings");
1659	PGM_REG_COUNTER(&pPGM->StatTrackAliased, "/PGM/Track/Aliased", "The number of times switching to cRef2, i.e. the page is being shadowed by two PTs.");
1660	PGM_REG_COUNTER(&pPGM->StatTrackAliasedMany, "/PGM/Track/AliasedMany", "The number of times we're tracking using cRef2.");
1661	PGM_REG_COUNTER(&pPGM->StatTrackAliasedLots, "/PGM/Track/AliasedLots", "The number of times we're hitting pages which has overflowed cRef2");
1662	PGM_REG_COUNTER(&pPGM->StatTrackOverflows, "/PGM/Track/Overflows", "The number of times the extent list grows too long.");
1663	PGM_REG_PROFILE(&pPGM->StatTrackDeref, "/PGM/Track/Deref", "Profiling of SyncPageWorkerTrackDeref (expensive).");
1664	# endif
1665
1666	# undef PGM_REG_COUNTER
1667	# undef PGM_REG_PROFILE
1668	#endif
1669
1670	/*
1671	* Note! The layout below matches the member layout exactly!
1672	*/
1673
1674	/*
1675	* Common - stats
1676	*/
1677	for (unsigned i=0;i<pVM->cCPUs;i++)
1678	{
1679	PVMCPU pVCpu = &pVM->aCpus[i];
1680	PPGMCPU pPGM = &pVCpu->pgm.s;
1681
1682	#define PGM_REG_COUNTER(a, b, c) \
1683	rc = STAMR3RegisterF(pVM, a, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, c, b, i); \
1684	AssertRC(rc);
1685	#define PGM_REG_PROFILE(a, b, c) \
1686	rc = STAMR3RegisterF(pVM, a, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, c, b, i); \
1687	AssertRC(rc);
1688
1689	PGM_REG_COUNTER(&pPGM->cGuestModeChanges, "/PGM/CPU%d/cGuestModeChanges", "Number of guest mode changes.");
1690
1691	#ifdef VBOX_WITH_STATISTICS
1692	for (unsigned j = 0; j < RT_ELEMENTS(pPGM->StatSyncPtPD); j++)
1693	STAMR3RegisterF(pVM, &pPGM->StatSyncPtPD[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
1694	"The number of SyncPT per PD n.", "/PGM/CPU%d/PDSyncPT/%04X", i, j);
1695	for (unsigned j = 0; j < RT_ELEMENTS(pPGM->StatSyncPagePD); j++)
1696	STAMR3RegisterF(pVM, &pPGM->StatSyncPagePD[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
1697	"The number of SyncPage per PD n.", "/PGM/CPU%d/PDSyncPage/%04X", i, j);
1698
1699	/* R0 only: */
1700	PGM_REG_COUNTER(&pPGM->StatR0DynMapMigrateInvlPg, "/PGM/CPU%d/R0/DynMapMigrateInvlPg", "invlpg count in PGMDynMapMigrateAutoSet.");
1701	PGM_REG_PROFILE(&pPGM->StatR0DynMapGCPageInl, "/PGM/CPU%d/R0/DynMapPageGCPageInl", "Calls to pgmR0DynMapGCPageInlined.");
1702	PGM_REG_COUNTER(&pPGM->StatR0DynMapGCPageInlHits, "/PGM/CPU%d/R0/DynMapPageGCPageInl/Hits", "Hash table lookup hits.");
1703	PGM_REG_COUNTER(&pPGM->StatR0DynMapGCPageInlMisses, "/PGM/CPU%d/R0/DynMapPageGCPageInl/Misses", "Misses that falls back to code common with PGMDynMapHCPage.");
1704	PGM_REG_COUNTER(&pPGM->StatR0DynMapGCPageInlRamHits, "/PGM/CPU%d/R0/DynMapPageGCPageInl/RamHits", "1st ram range hits.");
1705	PGM_REG_COUNTER(&pPGM->StatR0DynMapGCPageInlRamMisses, "/PGM/CPU%d/R0/DynMapPageGCPageInl/RamMisses", "1st ram range misses, takes slow path.");
1706	PGM_REG_PROFILE(&pPGM->StatR0DynMapHCPageInl, "/PGM/CPU%d/R0/DynMapPageHCPageInl", "Calls to pgmR0DynMapHCPageInlined.");
1707	PGM_REG_COUNTER(&pPGM->StatR0DynMapHCPageInlHits, "/PGM/CPU%d/R0/DynMapPageHCPageInl/Hits", "Hash table lookup hits.");
1708	PGM_REG_COUNTER(&pPGM->StatR0DynMapHCPageInlMisses, "/PGM/CPU%d/R0/DynMapPageHCPageInl/Misses", "Misses that falls back to code common with PGMDynMapHCPage.");
1709	PGM_REG_COUNTER(&pPGM->StatR0DynMapPage, "/PGM/CPU%d/R0/DynMapPage", "Calls to pgmR0DynMapPage");
1710	PGM_REG_COUNTER(&pPGM->StatR0DynMapSetOptimize, "/PGM/CPU%d/R0/DynMapPage/SetOptimize", "Calls to pgmDynMapOptimizeAutoSet.");
1711	PGM_REG_COUNTER(&pPGM->StatR0DynMapSetSearchFlushes, "/PGM/CPU%d/R0/DynMapPage/SetSearchFlushes","Set search restorting to subset flushes.");
1712	PGM_REG_COUNTER(&pPGM->StatR0DynMapSetSearchHits, "/PGM/CPU%d/R0/DynMapPage/SetSearchHits", "Set search hits.");
1713	PGM_REG_COUNTER(&pPGM->StatR0DynMapSetSearchMisses, "/PGM/CPU%d/R0/DynMapPage/SetSearchMisses", "Set search misses.");
1714	PGM_REG_PROFILE(&pPGM->StatR0DynMapHCPage, "/PGM/CPU%d/R0/DynMapPage/HCPage", "Calls to PGMDynMapHCPage (ring-0).");
1715	PGM_REG_COUNTER(&pPGM->StatR0DynMapPageHits0, "/PGM/CPU%d/R0/DynMapPage/Hits0", "Hits at iPage+0");
1716	PGM_REG_COUNTER(&pPGM->StatR0DynMapPageHits1, "/PGM/CPU%d/R0/DynMapPage/Hits1", "Hits at iPage+1");
1717	PGM_REG_COUNTER(&pPGM->StatR0DynMapPageHits2, "/PGM/CPU%d/R0/DynMapPage/Hits2", "Hits at iPage+2");
1718	PGM_REG_COUNTER(&pPGM->StatR0DynMapPageInvlPg, "/PGM/CPU%d/R0/DynMapPage/InvlPg", "invlpg count in pgmR0DynMapPageSlow.");
1719	PGM_REG_COUNTER(&pPGM->StatR0DynMapPageSlow, "/PGM/CPU%d/R0/DynMapPage/Slow", "Calls to pgmR0DynMapPageSlow - subtract this from pgmR0DynMapPage to get 1st level hits.");
1720	PGM_REG_COUNTER(&pPGM->StatR0DynMapPageSlowLoopHits, "/PGM/CPU%d/R0/DynMapPage/SlowLoopHits" , "Hits in the loop path.");
1721	PGM_REG_COUNTER(&pPGM->StatR0DynMapPageSlowLoopMisses, "/PGM/CPU%d/R0/DynMapPage/SlowLoopMisses", "Misses in the loop path. NonLoopMisses = Slow - SlowLoopHit - SlowLoopMisses");
1722	//PGM_REG_COUNTER(&pPGM->StatR0DynMapPageSlowLostHits, "/PGM/CPU%d/R0/DynMapPage/SlowLostHits", "Lost hits.");
1723	PGM_REG_COUNTER(&pPGM->StatR0DynMapSubsets, "/PGM/CPU%d/R0/Subsets", "Times PGMDynMapPushAutoSubset was called.");
1724	PGM_REG_COUNTER(&pPGM->StatR0DynMapPopFlushes, "/PGM/CPU%d/R0/SubsetPopFlushes", "Times PGMDynMapPopAutoSubset flushes the subset.");
1725	PGM_REG_COUNTER(&pPGM->aStatR0DynMapSetSize[0], "/PGM/CPU%d/R0/SetSize000..09", "00-09% filled");
1726	PGM_REG_COUNTER(&pPGM->aStatR0DynMapSetSize[1], "/PGM/CPU%d/R0/SetSize010..19", "10-19% filled");
1727	PGM_REG_COUNTER(&pPGM->aStatR0DynMapSetSize[2], "/PGM/CPU%d/R0/SetSize020..29", "20-29% filled");
1728	PGM_REG_COUNTER(&pPGM->aStatR0DynMapSetSize[3], "/PGM/CPU%d/R0/SetSize030..39", "30-39% filled");
1729	PGM_REG_COUNTER(&pPGM->aStatR0DynMapSetSize[4], "/PGM/CPU%d/R0/SetSize040..49", "40-49% filled");
1730	PGM_REG_COUNTER(&pPGM->aStatR0DynMapSetSize[5], "/PGM/CPU%d/R0/SetSize050..59", "50-59% filled");
1731	PGM_REG_COUNTER(&pPGM->aStatR0DynMapSetSize[6], "/PGM/CPU%d/R0/SetSize060..69", "60-69% filled");
1732	PGM_REG_COUNTER(&pPGM->aStatR0DynMapSetSize[7], "/PGM/CPU%d/R0/SetSize070..79", "70-79% filled");
1733	PGM_REG_COUNTER(&pPGM->aStatR0DynMapSetSize[8], "/PGM/CPU%d/R0/SetSize080..89", "80-89% filled");
1734	PGM_REG_COUNTER(&pPGM->aStatR0DynMapSetSize[9], "/PGM/CPU%d/R0/SetSize090..99", "90-99% filled");
1735	PGM_REG_COUNTER(&pPGM->aStatR0DynMapSetSize[10], "/PGM/CPU%d/R0/SetSize100", "100% filled");
1736
1737	/* RZ only: */
1738	PGM_REG_PROFILE(&pPGM->StatRZTrap0e, "/PGM/CPU%d/RZ/Trap0e", "Profiling of the PGMTrap0eHandler() body.");
1739	PGM_REG_PROFILE(&pPGM->StatRZTrap0eTimeCheckPageFault, "/PGM/CPU%d/RZ/Trap0e/Time/CheckPageFault", "Profiling of checking for dirty/access emulation faults.");
1740	PGM_REG_PROFILE(&pPGM->StatRZTrap0eTimeSyncPT, "/PGM/CPU%d/RZ/Trap0e/Time/SyncPT", "Profiling of lazy page table syncing.");
1741	PGM_REG_PROFILE(&pPGM->StatRZTrap0eTimeMapping, "/PGM/CPU%d/RZ/Trap0e/Time/Mapping", "Profiling of checking virtual mappings.");
1742	PGM_REG_PROFILE(&pPGM->StatRZTrap0eTimeOutOfSync, "/PGM/CPU%d/RZ/Trap0e/Time/OutOfSync", "Profiling of out of sync page handling.");
1743	PGM_REG_PROFILE(&pPGM->StatRZTrap0eTimeHandlers, "/PGM/CPU%d/RZ/Trap0e/Time/Handlers", "Profiling of checking handlers.");
1744	PGM_REG_PROFILE(&pPGM->StatRZTrap0eTime2CSAM, "/PGM/CPU%d/RZ/Trap0e/Time2/CSAM", "Profiling of the Trap0eHandler body when the cause is CSAM.");
1745	PGM_REG_PROFILE(&pPGM->StatRZTrap0eTime2DirtyAndAccessed, "/PGM/CPU%d/RZ/Trap0e/Time2/DirtyAndAccessedBits", "Profiling of the Trap0eHandler body when the cause is dirty and/or accessed bit emulation.");
1746	PGM_REG_PROFILE(&pPGM->StatRZTrap0eTime2GuestTrap, "/PGM/CPU%d/RZ/Trap0e/Time2/GuestTrap", "Profiling of the Trap0eHandler body when the cause is a guest trap.");
1747	PGM_REG_PROFILE(&pPGM->StatRZTrap0eTime2HndPhys, "/PGM/CPU%d/RZ/Trap0e/Time2/HandlerPhysical", "Profiling of the Trap0eHandler body when the cause is a physical handler.");
1748	PGM_REG_PROFILE(&pPGM->StatRZTrap0eTime2HndVirt, "/PGM/CPU%d/RZ/Trap0e/Time2/HandlerVirtual", "Profiling of the Trap0eHandler body when the cause is a virtual handler.");
1749	PGM_REG_PROFILE(&pPGM->StatRZTrap0eTime2HndUnhandled, "/PGM/CPU%d/RZ/Trap0e/Time2/HandlerUnhandled", "Profiling of the Trap0eHandler body when the cause is access outside the monitored areas of a monitored page.");
1750	PGM_REG_PROFILE(&pPGM->StatRZTrap0eTime2Misc, "/PGM/CPU%d/RZ/Trap0e/Time2/Misc", "Profiling of the Trap0eHandler body when the cause is not known.");
1751	PGM_REG_PROFILE(&pPGM->StatRZTrap0eTime2OutOfSync, "/PGM/CPU%d/RZ/Trap0e/Time2/OutOfSync", "Profiling of the Trap0eHandler body when the cause is an out-of-sync page.");
1752	PGM_REG_PROFILE(&pPGM->StatRZTrap0eTime2OutOfSyncHndPhys, "/PGM/CPU%d/RZ/Trap0e/Time2/OutOfSyncHndPhys", "Profiling of the Trap0eHandler body when the cause is an out-of-sync physical handler page.");
1753	PGM_REG_PROFILE(&pPGM->StatRZTrap0eTime2OutOfSyncHndVirt, "/PGM/CPU%d/RZ/Trap0e/Time2/OutOfSyncHndVirt", "Profiling of the Trap0eHandler body when the cause is an out-of-sync virtual handler page.");
1754	PGM_REG_PROFILE(&pPGM->StatRZTrap0eTime2OutOfSyncHndObs, "/PGM/CPU%d/RZ/Trap0e/Time2/OutOfSyncObsHnd", "Profiling of the Trap0eHandler body when the cause is an obsolete handler page.");
1755	PGM_REG_PROFILE(&pPGM->StatRZTrap0eTime2SyncPT, "/PGM/CPU%d/RZ/Trap0e/Time2/SyncPT", "Profiling of the Trap0eHandler body when the cause is lazy syncing of a PT.");
1756	PGM_REG_COUNTER(&pPGM->StatRZTrap0eConflicts, "/PGM/CPU%d/RZ/Trap0e/Conflicts", "The number of times #PF was caused by an undetected conflict.");
1757	PGM_REG_COUNTER(&pPGM->StatRZTrap0eHandlersMapping, "/PGM/CPU%d/RZ/Trap0e/Handlers/Mapping", "Number of traps due to access handlers in mappings.");
1758	PGM_REG_COUNTER(&pPGM->StatRZTrap0eHandlersOutOfSync, "/PGM/CPU%d/RZ/Trap0e/Handlers/OutOfSync", "Number of traps due to out-of-sync handled pages.");
1759	PGM_REG_COUNTER(&pPGM->StatRZTrap0eHandlersPhysical, "/PGM/CPU%d/RZ/Trap0e/Handlers/Physical", "Number of traps due to physical access handlers.");
1760	PGM_REG_COUNTER(&pPGM->StatRZTrap0eHandlersVirtual, "/PGM/CPU%d/RZ/Trap0e/Handlers/Virtual", "Number of traps due to virtual access handlers.");
1761	PGM_REG_COUNTER(&pPGM->StatRZTrap0eHandlersVirtualByPhys, "/PGM/CPU%d/RZ/Trap0e/Handlers/VirtualByPhys", "Number of traps due to virtual access handlers by physical address.");
1762	PGM_REG_COUNTER(&pPGM->StatRZTrap0eHandlersVirtualUnmarked,"/PGM/CPU%d/RZ/Trap0e/Handlers/VirtualUnmarked","Number of traps due to virtual access handlers by virtual address (without proper physical flags).");
1763	PGM_REG_COUNTER(&pPGM->StatRZTrap0eHandlersUnhandled, "/PGM/CPU%d/RZ/Trap0e/Handlers/Unhandled", "Number of traps due to access outside range of monitored page(s).");
1764	PGM_REG_COUNTER(&pPGM->StatRZTrap0eHandlersInvalid, "/PGM/CPU%d/RZ/Trap0e/Handlers/Invalid", "Number of traps due to access to invalid physical memory.");
1765	PGM_REG_COUNTER(&pPGM->StatRZTrap0eUSNotPresentRead, "/PGM/CPU%d/RZ/Trap0e/Err/User/NPRead", "Number of user mode not present read page faults.");
1766	PGM_REG_COUNTER(&pPGM->StatRZTrap0eUSNotPresentWrite, "/PGM/CPU%d/RZ/Trap0e/Err/User/NPWrite", "Number of user mode not present write page faults.");
1767	PGM_REG_COUNTER(&pPGM->StatRZTrap0eUSWrite, "/PGM/CPU%d/RZ/Trap0e/Err/User/Write", "Number of user mode write page faults.");
1768	PGM_REG_COUNTER(&pPGM->StatRZTrap0eUSReserved, "/PGM/CPU%d/RZ/Trap0e/Err/User/Reserved", "Number of user mode reserved bit page faults.");
1769	PGM_REG_COUNTER(&pPGM->StatRZTrap0eUSNXE, "/PGM/CPU%d/RZ/Trap0e/Err/User/NXE", "Number of user mode NXE page faults.");
1770	PGM_REG_COUNTER(&pPGM->StatRZTrap0eUSRead, "/PGM/CPU%d/RZ/Trap0e/Err/User/Read", "Number of user mode read page faults.");
1771	PGM_REG_COUNTER(&pPGM->StatRZTrap0eSVNotPresentRead, "/PGM/CPU%d/RZ/Trap0e/Err/Supervisor/NPRead", "Number of supervisor mode not present read page faults.");
1772	PGM_REG_COUNTER(&pPGM->StatRZTrap0eSVNotPresentWrite, "/PGM/CPU%d/RZ/Trap0e/Err/Supervisor/NPWrite", "Number of supervisor mode not present write page faults.");
1773	PGM_REG_COUNTER(&pPGM->StatRZTrap0eSVWrite, "/PGM/CPU%d/RZ/Trap0e/Err/Supervisor/Write", "Number of supervisor mode write page faults.");
1774	PGM_REG_COUNTER(&pPGM->StatRZTrap0eSVReserved, "/PGM/CPU%d/RZ/Trap0e/Err/Supervisor/Reserved", "Number of supervisor mode reserved bit page faults.");
1775	PGM_REG_COUNTER(&pPGM->StatRZTrap0eSNXE, "/PGM/CPU%d/RZ/Trap0e/Err/Supervisor/NXE", "Number of supervisor mode NXE page faults.");
1776	PGM_REG_COUNTER(&pPGM->StatRZTrap0eGuestPF, "/PGM/CPU%d/RZ/Trap0e/GuestPF", "Number of real guest page faults.");
1777	PGM_REG_COUNTER(&pPGM->StatRZTrap0eGuestPFUnh, "/PGM/CPU%d/RZ/Trap0e/GuestPF/Unhandled", "Number of real guest page faults from the 'unhandled' case.");
1778	PGM_REG_COUNTER(&pPGM->StatRZTrap0eGuestPFMapping, "/PGM/CPU%d/RZ/Trap0e/GuestPF/InMapping", "Number of real guest page faults in a mapping.");
1779	PGM_REG_COUNTER(&pPGM->StatRZTrap0eWPEmulInRZ, "/PGM/CPU%d/RZ/Trap0e/WP/InRZ", "Number of guest page faults due to X86_CR0_WP emulation.");
1780	PGM_REG_COUNTER(&pPGM->StatRZTrap0eWPEmulToR3, "/PGM/CPU%d/RZ/Trap0e/WP/ToR3", "Number of guest page faults due to X86_CR0_WP emulation (forward to R3 for emulation).");
1781	for (unsigned j = 0; j < RT_ELEMENTS(pPGM->StatRZTrap0ePD); j++)
1782	STAMR3RegisterF(pVM, &pPGM->StatRZTrap0ePD[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
1783	"The number of traps in page directory n.", "/PGM/CPU%d/RZ/Trap0e/PD/%04X", i, j);
1784
1785	PGM_REG_COUNTER(&pPGM->StatRZGuestCR3WriteHandled, "/PGM/CPU%d/RZ/CR3WriteHandled", "The number of times the Guest CR3 change was successfully handled.");
1786	PGM_REG_COUNTER(&pPGM->StatRZGuestCR3WriteUnhandled, "/PGM/CPU%d/RZ/CR3WriteUnhandled", "The number of times the Guest CR3 change was passed back to the recompiler.");
1787	PGM_REG_COUNTER(&pPGM->StatRZGuestCR3WriteConflict, "/PGM/CPU%d/RZ/CR3WriteConflict", "The number of times the Guest CR3 monitoring detected a conflict.");
1788	PGM_REG_COUNTER(&pPGM->StatRZGuestROMWriteHandled, "/PGM/CPU%d/RZ/ROMWriteHandled", "The number of times the Guest ROM change was successfully handled.");
1789	PGM_REG_COUNTER(&pPGM->StatRZGuestROMWriteUnhandled, "/PGM/CPU%d/RZ/ROMWriteUnhandled", "The number of times the Guest ROM change was passed back to the recompiler.");
1790
1791	/* HC only: */
1792
1793	/* RZ & R3: */
1794	PGM_REG_PROFILE(&pPGM->StatRZSyncCR3, "/PGM/CPU%d/RZ/SyncCR3", "Profiling of the PGMSyncCR3() body.");
1795	PGM_REG_PROFILE(&pPGM->StatRZSyncCR3Handlers, "/PGM/CPU%d/RZ/SyncCR3/Handlers", "Profiling of the PGMSyncCR3() update handler section.");
1796	PGM_REG_COUNTER(&pPGM->StatRZSyncCR3Global, "/PGM/CPU%d/RZ/SyncCR3/Global", "The number of global CR3 syncs.");
1797	PGM_REG_COUNTER(&pPGM->StatRZSyncCR3NotGlobal, "/PGM/CPU%d/RZ/SyncCR3/NotGlobal", "The number of non-global CR3 syncs.");
1798	PGM_REG_COUNTER(&pPGM->StatRZSyncCR3DstCacheHit, "/PGM/CPU%d/RZ/SyncCR3/DstChacheHit", "The number of times we got some kind of a cache hit.");
1799	PGM_REG_COUNTER(&pPGM->StatRZSyncCR3DstFreed, "/PGM/CPU%d/RZ/SyncCR3/DstFreed", "The number of times we've had to free a shadow entry.");
1800	PGM_REG_COUNTER(&pPGM->StatRZSyncCR3DstFreedSrcNP, "/PGM/CPU%d/RZ/SyncCR3/DstFreedSrcNP", "The number of times we've had to free a shadow entry for which the source entry was not present.");
1801	PGM_REG_COUNTER(&pPGM->StatRZSyncCR3DstNotPresent, "/PGM/CPU%d/RZ/SyncCR3/DstNotPresent", "The number of times we've encountered a not present shadow entry for a present guest entry.");
1802	PGM_REG_COUNTER(&pPGM->StatRZSyncCR3DstSkippedGlobalPD, "/PGM/CPU%d/RZ/SyncCR3/DstSkippedGlobalPD", "The number of times a global page directory wasn't flushed.");
1803	PGM_REG_COUNTER(&pPGM->StatRZSyncCR3DstSkippedGlobalPT, "/PGM/CPU%d/RZ/SyncCR3/DstSkippedGlobalPT", "The number of times a page table with only global entries wasn't flushed.");
1804	PGM_REG_PROFILE(&pPGM->StatRZSyncPT, "/PGM/CPU%d/RZ/SyncPT", "Profiling of the pfnSyncPT() body.");
1805	PGM_REG_COUNTER(&pPGM->StatRZSyncPTFailed, "/PGM/CPU%d/RZ/SyncPT/Failed", "The number of times pfnSyncPT() failed.");
1806	PGM_REG_COUNTER(&pPGM->StatRZSyncPT4K, "/PGM/CPU%d/RZ/SyncPT/4K", "Nr of 4K PT syncs");
1807	PGM_REG_COUNTER(&pPGM->StatRZSyncPT4M, "/PGM/CPU%d/RZ/SyncPT/4M", "Nr of 4M PT syncs");
1808	PGM_REG_COUNTER(&pPGM->StatRZSyncPagePDNAs, "/PGM/CPU%d/RZ/SyncPagePDNAs", "The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit.");
1809	PGM_REG_COUNTER(&pPGM->StatRZSyncPagePDOutOfSync, "/PGM/CPU%d/RZ/SyncPagePDOutOfSync", "The number of time we've encountered an out-of-sync PD in SyncPage.");
1810	PGM_REG_COUNTER(&pPGM->StatRZAccessedPage, "/PGM/CPU%d/RZ/AccessedPage", "The number of pages marked not present for accessed bit emulation.");
1811	PGM_REG_PROFILE(&pPGM->StatRZDirtyBitTracking, "/PGM/CPU%d/RZ/DirtyPage", "Profiling the dirty bit tracking in CheckPageFault().");
1812	PGM_REG_COUNTER(&pPGM->StatRZDirtyPage, "/PGM/CPU%d/RZ/DirtyPage/Mark", "The number of pages marked read-only for dirty bit tracking.");
1813	PGM_REG_COUNTER(&pPGM->StatRZDirtyPageBig, "/PGM/CPU%d/RZ/DirtyPage/MarkBig", "The number of 4MB pages marked read-only for dirty bit tracking.");
1814	PGM_REG_COUNTER(&pPGM->StatRZDirtyPageSkipped, "/PGM/CPU%d/RZ/DirtyPage/Skipped", "The number of pages already dirty or readonly.");
1815	PGM_REG_COUNTER(&pPGM->StatRZDirtyPageTrap, "/PGM/CPU%d/RZ/DirtyPage/Trap", "The number of traps generated for dirty bit tracking.");
1816	PGM_REG_COUNTER(&pPGM->StatRZDirtyPageStale, "/PGM/CPU%d/RZ/DirtyPage/Stale", "The number of traps generated for dirty bit tracking (stale tlb entries).");
1817	PGM_REG_COUNTER(&pPGM->StatRZDirtiedPage, "/PGM/CPU%d/RZ/DirtyPage/SetDirty", "The number of pages marked dirty because of write accesses.");
1818	PGM_REG_COUNTER(&pPGM->StatRZDirtyTrackRealPF, "/PGM/CPU%d/RZ/DirtyPage/RealPF", "The number of real pages faults during dirty bit tracking.");
1819	PGM_REG_COUNTER(&pPGM->StatRZPageAlreadyDirty, "/PGM/CPU%d/RZ/DirtyPage/AlreadySet", "The number of pages already marked dirty because of write accesses.");
1820	PGM_REG_PROFILE(&pPGM->StatRZInvalidatePage, "/PGM/CPU%d/RZ/InvalidatePage", "PGMInvalidatePage() profiling.");
1821	PGM_REG_COUNTER(&pPGM->StatRZInvalidatePage4KBPages, "/PGM/CPU%d/RZ/InvalidatePage/4KBPages", "The number of times PGMInvalidatePage() was called for a 4KB page.");
1822	PGM_REG_COUNTER(&pPGM->StatRZInvalidatePage4MBPages, "/PGM/CPU%d/RZ/InvalidatePage/4MBPages", "The number of times PGMInvalidatePage() was called for a 4MB page.");
1823	PGM_REG_COUNTER(&pPGM->StatRZInvalidatePage4MBPagesSkip, "/PGM/CPU%d/RZ/InvalidatePage/4MBPagesSkip","The number of times PGMInvalidatePage() skipped a 4MB page.");
1824	PGM_REG_COUNTER(&pPGM->StatRZInvalidatePagePDMappings, "/PGM/CPU%d/RZ/InvalidatePage/PDMappings", "The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict).");
1825	PGM_REG_COUNTER(&pPGM->StatRZInvalidatePagePDNAs, "/PGM/CPU%d/RZ/InvalidatePage/PDNAs", "The number of times PGMInvalidatePage() was called for a not accessed page directory.");
1826	PGM_REG_COUNTER(&pPGM->StatRZInvalidatePagePDNPs, "/PGM/CPU%d/RZ/InvalidatePage/PDNPs", "The number of times PGMInvalidatePage() was called for a not present page directory.");
1827	PGM_REG_COUNTER(&pPGM->StatRZInvalidatePagePDOutOfSync, "/PGM/CPU%d/RZ/InvalidatePage/PDOutOfSync", "The number of times PGMInvalidatePage() was called for an out of sync page directory.");
1828	PGM_REG_COUNTER(&pPGM->StatRZInvalidatePageSkipped, "/PGM/CPU%d/RZ/InvalidatePage/Skipped", "The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3.");
1829	PGM_REG_COUNTER(&pPGM->StatRZPageOutOfSyncSupervisor, "/PGM/CPU%d/RZ/OutOfSync/SuperVisor", "Number of traps due to pages out of sync and times VerifyAccessSyncPage calls SyncPage.");
1830	PGM_REG_COUNTER(&pPGM->StatRZPageOutOfSyncUser, "/PGM/CPU%d/RZ/OutOfSync/User", "Number of traps due to pages out of sync and times VerifyAccessSyncPage calls SyncPage.");
1831	PGM_REG_PROFILE(&pPGM->StatRZPrefetch, "/PGM/CPU%d/RZ/Prefetch", "PGMPrefetchPage profiling.");
1832	PGM_REG_PROFILE(&pPGM->StatRZFlushTLB, "/PGM/CPU%d/RZ/FlushTLB", "Profiling of the PGMFlushTLB() body.");
1833	PGM_REG_COUNTER(&pPGM->StatRZFlushTLBNewCR3, "/PGM/CPU%d/RZ/FlushTLB/NewCR3", "The number of times PGMFlushTLB was called with a new CR3, non-global. (switch)");
1834	PGM_REG_COUNTER(&pPGM->StatRZFlushTLBNewCR3Global, "/PGM/CPU%d/RZ/FlushTLB/NewCR3Global", "The number of times PGMFlushTLB was called with a new CR3, global. (switch)");
1835	PGM_REG_COUNTER(&pPGM->StatRZFlushTLBSameCR3, "/PGM/CPU%d/RZ/FlushTLB/SameCR3", "The number of times PGMFlushTLB was called with the same CR3, non-global. (flush)");
1836	PGM_REG_COUNTER(&pPGM->StatRZFlushTLBSameCR3Global, "/PGM/CPU%d/RZ/FlushTLB/SameCR3Global", "The number of times PGMFlushTLB was called with the same CR3, global. (flush)");
1837	PGM_REG_PROFILE(&pPGM->StatRZGstModifyPage, "/PGM/CPU%d/RZ/GstModifyPage", "Profiling of the PGMGstModifyPage() body.");
1838
1839	PGM_REG_PROFILE(&pPGM->StatR3SyncCR3, "/PGM/CPU%d/R3/SyncCR3", "Profiling of the PGMSyncCR3() body.");
1840	PGM_REG_PROFILE(&pPGM->StatR3SyncCR3Handlers, "/PGM/CPU%d/R3/SyncCR3/Handlers", "Profiling of the PGMSyncCR3() update handler section.");
1841	PGM_REG_COUNTER(&pPGM->StatR3SyncCR3Global, "/PGM/CPU%d/R3/SyncCR3/Global", "The number of global CR3 syncs.");
1842	PGM_REG_COUNTER(&pPGM->StatR3SyncCR3NotGlobal, "/PGM/CPU%d/R3/SyncCR3/NotGlobal", "The number of non-global CR3 syncs.");
1843	PGM_REG_COUNTER(&pPGM->StatR3SyncCR3DstCacheHit, "/PGM/CPU%d/R3/SyncCR3/DstChacheHit", "The number of times we got some kind of a cache hit.");
1844	PGM_REG_COUNTER(&pPGM->StatR3SyncCR3DstFreed, "/PGM/CPU%d/R3/SyncCR3/DstFreed", "The number of times we've had to free a shadow entry.");
1845	PGM_REG_COUNTER(&pPGM->StatR3SyncCR3DstFreedSrcNP, "/PGM/CPU%d/R3/SyncCR3/DstFreedSrcNP", "The number of times we've had to free a shadow entry for which the source entry was not present.");
1846	PGM_REG_COUNTER(&pPGM->StatR3SyncCR3DstNotPresent, "/PGM/CPU%d/R3/SyncCR3/DstNotPresent", "The number of times we've encountered a not present shadow entry for a present guest entry.");
1847	PGM_REG_COUNTER(&pPGM->StatR3SyncCR3DstSkippedGlobalPD, "/PGM/CPU%d/R3/SyncCR3/DstSkippedGlobalPD", "The number of times a global page directory wasn't flushed.");
1848	PGM_REG_COUNTER(&pPGM->StatR3SyncCR3DstSkippedGlobalPT, "/PGM/CPU%d/R3/SyncCR3/DstSkippedGlobalPT", "The number of times a page table with only global entries wasn't flushed.");
1849	PGM_REG_PROFILE(&pPGM->StatR3SyncPT, "/PGM/CPU%d/R3/SyncPT", "Profiling of the pfnSyncPT() body.");
1850	PGM_REG_COUNTER(&pPGM->StatR3SyncPTFailed, "/PGM/CPU%d/R3/SyncPT/Failed", "The number of times pfnSyncPT() failed.");
1851	PGM_REG_COUNTER(&pPGM->StatR3SyncPT4K, "/PGM/CPU%d/R3/SyncPT/4K", "Nr of 4K PT syncs");
1852	PGM_REG_COUNTER(&pPGM->StatR3SyncPT4M, "/PGM/CPU%d/R3/SyncPT/4M", "Nr of 4M PT syncs");
1853	PGM_REG_COUNTER(&pPGM->StatR3SyncPagePDNAs, "/PGM/CPU%d/R3/SyncPagePDNAs", "The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit.");
1854	PGM_REG_COUNTER(&pPGM->StatR3SyncPagePDOutOfSync, "/PGM/CPU%d/R3/SyncPagePDOutOfSync", "The number of time we've encountered an out-of-sync PD in SyncPage.");
1855	PGM_REG_COUNTER(&pPGM->StatR3AccessedPage, "/PGM/CPU%d/R3/AccessedPage", "The number of pages marked not present for accessed bit emulation.");
1856	PGM_REG_PROFILE(&pPGM->StatR3DirtyBitTracking, "/PGM/CPU%d/R3/DirtyPage", "Profiling the dirty bit tracking in CheckPageFault().");
1857	PGM_REG_COUNTER(&pPGM->StatR3DirtyPage, "/PGM/CPU%d/R3/DirtyPage/Mark", "The number of pages marked read-only for dirty bit tracking.");
1858	PGM_REG_COUNTER(&pPGM->StatR3DirtyPageBig, "/PGM/CPU%d/R3/DirtyPage/MarkBig", "The number of 4MB pages marked read-only for dirty bit tracking.");
1859	PGM_REG_COUNTER(&pPGM->StatR3DirtyPageSkipped, "/PGM/CPU%d/R3/DirtyPage/Skipped", "The number of pages already dirty or readonly.");
1860	PGM_REG_COUNTER(&pPGM->StatR3DirtyPageTrap, "/PGM/CPU%d/R3/DirtyPage/Trap", "The number of traps generated for dirty bit tracking.");
1861	PGM_REG_COUNTER(&pPGM->StatR3DirtiedPage, "/PGM/CPU%d/R3/DirtyPage/SetDirty", "The number of pages marked dirty because of write accesses.");
1862	PGM_REG_COUNTER(&pPGM->StatR3DirtyTrackRealPF, "/PGM/CPU%d/R3/DirtyPage/RealPF", "The number of real pages faults during dirty bit tracking.");
1863	PGM_REG_COUNTER(&pPGM->StatR3PageAlreadyDirty, "/PGM/CPU%d/R3/DirtyPage/AlreadySet", "The number of pages already marked dirty because of write accesses.");
1864	PGM_REG_PROFILE(&pPGM->StatR3InvalidatePage, "/PGM/CPU%d/R3/InvalidatePage", "PGMInvalidatePage() profiling.");
1865	PGM_REG_COUNTER(&pPGM->StatR3InvalidatePage4KBPages, "/PGM/CPU%d/R3/InvalidatePage/4KBPages", "The number of times PGMInvalidatePage() was called for a 4KB page.");
1866	PGM_REG_COUNTER(&pPGM->StatR3InvalidatePage4MBPages, "/PGM/CPU%d/R3/InvalidatePage/4MBPages", "The number of times PGMInvalidatePage() was called for a 4MB page.");
1867	PGM_REG_COUNTER(&pPGM->StatR3InvalidatePage4MBPagesSkip, "/PGM/CPU%d/R3/InvalidatePage/4MBPagesSkip","The number of times PGMInvalidatePage() skipped a 4MB page.");
1868	PGM_REG_COUNTER(&pPGM->StatR3InvalidatePagePDMappings, "/PGM/CPU%d/R3/InvalidatePage/PDMappings", "The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict).");
1869	PGM_REG_COUNTER(&pPGM->StatR3InvalidatePagePDNAs, "/PGM/CPU%d/R3/InvalidatePage/PDNAs", "The number of times PGMInvalidatePage() was called for a not accessed page directory.");
1870	PGM_REG_COUNTER(&pPGM->StatR3InvalidatePagePDNPs, "/PGM/CPU%d/R3/InvalidatePage/PDNPs", "The number of times PGMInvalidatePage() was called for a not present page directory.");
1871	PGM_REG_COUNTER(&pPGM->StatR3InvalidatePagePDOutOfSync, "/PGM/CPU%d/R3/InvalidatePage/PDOutOfSync", "The number of times PGMInvalidatePage() was called for an out of sync page directory.");
1872	PGM_REG_COUNTER(&pPGM->StatR3InvalidatePageSkipped, "/PGM/CPU%d/R3/InvalidatePage/Skipped", "The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3.");
1873	PGM_REG_COUNTER(&pPGM->StatR3PageOutOfSyncSupervisor, "/PGM/CPU%d/R3/OutOfSync/SuperVisor", "Number of traps due to pages out of sync and times VerifyAccessSyncPage calls SyncPage.");
1874	PGM_REG_COUNTER(&pPGM->StatR3PageOutOfSyncUser, "/PGM/CPU%d/R3/OutOfSync/User", "Number of traps due to pages out of sync and times VerifyAccessSyncPage calls SyncPage.");
1875	PGM_REG_PROFILE(&pPGM->StatR3Prefetch, "/PGM/CPU%d/R3/Prefetch", "PGMPrefetchPage profiling.");
1876	PGM_REG_PROFILE(&pPGM->StatR3FlushTLB, "/PGM/CPU%d/R3/FlushTLB", "Profiling of the PGMFlushTLB() body.");
1877	PGM_REG_COUNTER(&pPGM->StatR3FlushTLBNewCR3, "/PGM/CPU%d/R3/FlushTLB/NewCR3", "The number of times PGMFlushTLB was called with a new CR3, non-global. (switch)");
1878	PGM_REG_COUNTER(&pPGM->StatR3FlushTLBNewCR3Global, "/PGM/CPU%d/R3/FlushTLB/NewCR3Global", "The number of times PGMFlushTLB was called with a new CR3, global. (switch)");
1879	PGM_REG_COUNTER(&pPGM->StatR3FlushTLBSameCR3, "/PGM/CPU%d/R3/FlushTLB/SameCR3", "The number of times PGMFlushTLB was called with the same CR3, non-global. (flush)");
1880	PGM_REG_COUNTER(&pPGM->StatR3FlushTLBSameCR3Global, "/PGM/CPU%d/R3/FlushTLB/SameCR3Global", "The number of times PGMFlushTLB was called with the same CR3, global. (flush)");
1881	PGM_REG_PROFILE(&pPGM->StatR3GstModifyPage, "/PGM/CPU%d/R3/GstModifyPage", "Profiling of the PGMGstModifyPage() body.");
1882	#endif /* VBOX_WITH_STATISTICS */
1883
1884	#undef PGM_REG_PROFILE
1885	#undef PGM_REG_COUNTER
1886
1887	}
1888	}
1889
1890
1891	/**
1892	* Init the PGM bits that rely on VMMR0 and MM to be fully initialized.
1893	*
1894	* The dynamic mapping area will also be allocated and initialized at this
1895	* time. We could allocate it during PGMR3Init of course, but the mapping
1896	* wouldn't be allocated at that time preventing us from setting up the
1897	* page table entries with the dummy page.
1898	*
1899	* @returns VBox status code.
1900	* @param pVM VM handle.
1901	*/
1902	VMMR3DECL(int) PGMR3InitDynMap(PVM pVM)
1903	{
1904	RTGCPTR GCPtr;
1905	int rc;
1906
1907	/*
1908	* Reserve space for the dynamic mappings.
1909	*/
1910	rc = MMR3HyperReserve(pVM, MM_HYPER_DYNAMIC_SIZE, "Dynamic mapping", &GCPtr);
1911	if (RT_SUCCESS(rc))
1912	pVM->pgm.s.pbDynPageMapBaseGC = GCPtr;
1913
1914	if ( RT_SUCCESS(rc)
1915	&& (pVM->pgm.s.pbDynPageMapBaseGC >> X86_PD_PAE_SHIFT) != ((pVM->pgm.s.pbDynPageMapBaseGC + MM_HYPER_DYNAMIC_SIZE - 1) >> X86_PD_PAE_SHIFT))
1916	{
1917	rc = MMR3HyperReserve(pVM, MM_HYPER_DYNAMIC_SIZE, "Dynamic mapping not crossing", &GCPtr);
1918	if (RT_SUCCESS(rc))
1919	pVM->pgm.s.pbDynPageMapBaseGC = GCPtr;
1920	}
1921	if (RT_SUCCESS(rc))
1922	{
1923	AssertRelease((pVM->pgm.s.pbDynPageMapBaseGC >> X86_PD_PAE_SHIFT) == ((pVM->pgm.s.pbDynPageMapBaseGC + MM_HYPER_DYNAMIC_SIZE - 1) >> X86_PD_PAE_SHIFT));
1924	MMR3HyperReserve(pVM, PAGE_SIZE, "fence", NULL);
1925	}
1926	return rc;
1927	}
1928
1929
1930	/**
1931	* Ring-3 init finalizing.
1932	*
1933	* @returns VBox status code.
1934	* @param pVM The VM handle.
1935	*/
1936	VMMR3DECL(int) PGMR3InitFinalize(PVM pVM)
1937	{
1938	int rc;
1939
1940	/*
1941	* Reserve space for the dynamic mappings.
1942	* Initialize the dynamic mapping pages with dummy pages to simply the cache.
1943	*/
1944	/* get the pointer to the page table entries. */
1945	PPGMMAPPING pMapping = pgmGetMapping(pVM, pVM->pgm.s.pbDynPageMapBaseGC);
1946	AssertRelease(pMapping);
1947	const uintptr_t off = pVM->pgm.s.pbDynPageMapBaseGC - pMapping->GCPtr;
1948	const unsigned iPT = off >> X86_PD_SHIFT;
1949	const unsigned iPG = (off >> X86_PT_SHIFT) & X86_PT_MASK;
1950	pVM->pgm.s.paDynPageMap32BitPTEsGC = pMapping->aPTs[iPT].pPTRC + iPG * sizeof(pMapping->aPTs[0].pPTR3->a[0]);
1951	pVM->pgm.s.paDynPageMapPaePTEsGC = pMapping->aPTs[iPT].paPaePTsRC + iPG * sizeof(pMapping->aPTs[0].paPaePTsR3->a[0]);
1952
1953	/* init cache */
1954	RTHCPHYS HCPhysDummy = MMR3PageDummyHCPhys(pVM);
1955	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.aHCPhysDynPageMapCache); i++)
1956	pVM->pgm.s.aHCPhysDynPageMapCache[i] = HCPhysDummy;
1957
1958	for (unsigned i = 0; i < MM_HYPER_DYNAMIC_SIZE; i += PAGE_SIZE)
1959	{
1960	rc = PGMMap(pVM, pVM->pgm.s.pbDynPageMapBaseGC + i, HCPhysDummy, PAGE_SIZE, 0);
1961	AssertRCReturn(rc, rc);
1962	}
1963
1964	/*
1965	* Note that AMD uses all the 8 reserved bits for the address (so 40 bits in total);
1966	* Intel only goes up to 36 bits, so we stick to 36 as well.
1967	*/
1968	/** @todo How to test for the 40 bits support? Long mode seems to be the test criterium. */
1969	uint32_t u32Dummy, u32Features;
1970	CPUMGetGuestCpuId(VMMGetCpu(pVM), 1, &u32Dummy, &u32Dummy, &u32Dummy, &u32Features);
1971
1972	if (u32Features & X86_CPUID_FEATURE_EDX_PSE36)
1973	pVM->pgm.s.GCPhys4MBPSEMask = RT_BIT_64(36) - 1;
1974	else
1975	pVM->pgm.s.GCPhys4MBPSEMask = RT_BIT_64(32) - 1;
1976
1977	/*
1978	* Allocate memory if we're supposed to do that.
1979	*/
1980	if (pVM->pgm.s.fRamPreAlloc)
1981	rc = pgmR3PhysRamPreAllocate(pVM);
1982
1983	LogRel(("PGMR3InitFinalize: 4 MB PSE mask %RGp\n", pVM->pgm.s.GCPhys4MBPSEMask));
1984	return rc;
1985	}
1986
1987
1988	/**
1989	* Applies relocations to data and code managed by this component.
1990	*
1991	* This function will be called at init and whenever the VMM need to relocate it
1992	* self inside the GC.
1993	*
1994	* @param pVM The VM.
1995	* @param offDelta Relocation delta relative to old location.
1996	*/
1997	VMMR3DECL(void) PGMR3Relocate(PVM pVM, RTGCINTPTR offDelta)
1998	{
1999	LogFlow(("PGMR3Relocate %RGv to %RGv\n", pVM->pgm.s.GCPtrCR3Mapping, pVM->pgm.s.GCPtrCR3Mapping + offDelta));
2000
2001	/*
2002	* Paging stuff.
2003	*/
2004	pVM->pgm.s.GCPtrCR3Mapping += offDelta;
2005
2006	pgmR3ModeDataInit(pVM, true /* resolve GC/R0 symbols */);
2007
2008	/* Shadow, guest and both mode switch & relocation for each VCPU. */
2009	for (unsigned i=0;i<pVM->cCPUs;i++)
2010	{
2011	PVMCPU pVCpu = &pVM->aCpus[i];
2012
2013	pgmR3ModeDataSwitch(pVM, pVCpu, pVCpu->pgm.s.enmShadowMode, pVCpu->pgm.s.enmGuestMode);
2014
2015	PGM_SHW_PFN(Relocate, pVCpu)(pVCpu, offDelta);
2016	PGM_GST_PFN(Relocate, pVCpu)(pVCpu, offDelta);
2017	PGM_BTH_PFN(Relocate, pVCpu)(pVCpu, offDelta);
2018	}
2019
2020	/*
2021	* Trees.
2022	*/
2023	pVM->pgm.s.pTreesRC = MMHyperR3ToRC(pVM, pVM->pgm.s.pTreesR3);
2024
2025	/*
2026	* Ram ranges.
2027	*/
2028	if (pVM->pgm.s.pRamRangesR3)
2029	{
2030	/* Update the pSelfRC pointers and relink them. */
2031	for (PPGMRAMRANGE pCur = pVM->pgm.s.pRamRangesR3; pCur; pCur = pCur->pNextR3)
2032	if (!(pCur->fFlags & PGM_RAM_RANGE_FLAGS_FLOATING))
2033	pCur->pSelfRC = MMHyperCCToRC(pVM, pCur);
2034	pgmR3PhysRelinkRamRanges(pVM);
2035	}
2036
2037	/*
2038	* Update the pSelfRC pointer of the MMIO2 ram ranges since they might not
2039	* be mapped and thus not included in the above exercise.
2040	*/
2041	for (PPGMMMIO2RANGE pCur = pVM->pgm.s.pMmio2RangesR3; pCur; pCur = pCur->pNextR3)
2042	if (!(pCur->RamRange.fFlags & PGM_RAM_RANGE_FLAGS_FLOATING))
2043	pCur->RamRange.pSelfRC = MMHyperCCToRC(pVM, &pCur->RamRange);
2044
2045	/*
2046	* Update the two page directories with all page table mappings.
2047	* (One or more of them have changed, that's why we're here.)
2048	*/
2049	pVM->pgm.s.pMappingsRC = MMHyperR3ToRC(pVM, pVM->pgm.s.pMappingsR3);
2050	for (PPGMMAPPING pCur = pVM->pgm.s.pMappingsR3; pCur->pNextR3; pCur = pCur->pNextR3)
2051	pCur->pNextRC = MMHyperR3ToRC(pVM, pCur->pNextR3);
2052
2053	/* Relocate GC addresses of Page Tables. */
2054	for (PPGMMAPPING pCur = pVM->pgm.s.pMappingsR3; pCur; pCur = pCur->pNextR3)
2055	{
2056	for (RTHCUINT i = 0; i < pCur->cPTs; i++)
2057	{
2058	pCur->aPTs[i].pPTRC = MMHyperR3ToRC(pVM, pCur->aPTs[i].pPTR3);
2059	pCur->aPTs[i].paPaePTsRC = MMHyperR3ToRC(pVM, pCur->aPTs[i].paPaePTsR3);
2060	}
2061	}
2062
2063	/*
2064	* Dynamic page mapping area.
2065	*/
2066	pVM->pgm.s.paDynPageMap32BitPTEsGC += offDelta;
2067	pVM->pgm.s.paDynPageMapPaePTEsGC += offDelta;
2068	pVM->pgm.s.pbDynPageMapBaseGC += offDelta;
2069
2070	/*
2071	* The Zero page.
2072	*/
2073	pVM->pgm.s.pvZeroPgR0 = MMHyperR3ToR0(pVM, pVM->pgm.s.pvZeroPgR3);
2074	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
2075	AssertRelease(pVM->pgm.s.pvZeroPgR0 != NIL_RTR0PTR \|\| !VMMIsHwVirtExtForced(pVM));
2076	#else
2077	AssertRelease(pVM->pgm.s.pvZeroPgR0 != NIL_RTR0PTR);
2078	#endif
2079
2080	/*
2081	* Physical and virtual handlers.
2082	*/
2083	RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysHandlers, true, pgmR3RelocatePhysHandler, &offDelta);
2084	RTAvlroGCPtrDoWithAll(&pVM->pgm.s.pTreesR3->VirtHandlers, true, pgmR3RelocateVirtHandler, &offDelta);
2085	RTAvlroGCPtrDoWithAll(&pVM->pgm.s.pTreesR3->HyperVirtHandlers, true, pgmR3RelocateHyperVirtHandler, &offDelta);
2086
2087	/*
2088	* The page pool.
2089	*/
2090	pgmR3PoolRelocate(pVM);
2091	}
2092
2093
2094	/**
2095	* Callback function for relocating a physical access handler.
2096	*
2097	* @returns 0 (continue enum)
2098	* @param pNode Pointer to a PGMPHYSHANDLER node.
2099	* @param pvUser Pointer to the offDelta. This is a pointer to the delta since we're
2100	* not certain the delta will fit in a void pointer for all possible configs.
2101	*/
2102	static DECLCALLBACK(int) pgmR3RelocatePhysHandler(PAVLROGCPHYSNODECORE pNode, void *pvUser)
2103	{
2104	PPGMPHYSHANDLER pHandler = (PPGMPHYSHANDLER)pNode;
2105	RTGCINTPTR offDelta = *(PRTGCINTPTR)pvUser;
2106	if (pHandler->pfnHandlerRC)
2107	pHandler->pfnHandlerRC += offDelta;
2108	if (pHandler->pvUserRC >= 0x10000)
2109	pHandler->pvUserRC += offDelta;
2110	return 0;
2111	}
2112
2113
2114	/**
2115	* Callback function for relocating a virtual access handler.
2116	*
2117	* @returns 0 (continue enum)
2118	* @param pNode Pointer to a PGMVIRTHANDLER node.
2119	* @param pvUser Pointer to the offDelta. This is a pointer to the delta since we're
2120	* not certain the delta will fit in a void pointer for all possible configs.
2121	*/
2122	static DECLCALLBACK(int) pgmR3RelocateVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser)
2123	{
2124	PPGMVIRTHANDLER pHandler = (PPGMVIRTHANDLER)pNode;
2125	RTGCINTPTR offDelta = *(PRTGCINTPTR)pvUser;
2126	Assert( pHandler->enmType == PGMVIRTHANDLERTYPE_ALL
2127	\|\| pHandler->enmType == PGMVIRTHANDLERTYPE_WRITE);
2128	Assert(pHandler->pfnHandlerRC);
2129	pHandler->pfnHandlerRC += offDelta;
2130	return 0;
2131	}
2132
2133
2134	/**
2135	* Callback function for relocating a virtual access handler for the hypervisor mapping.
2136	*
2137	* @returns 0 (continue enum)
2138	* @param pNode Pointer to a PGMVIRTHANDLER node.
2139	* @param pvUser Pointer to the offDelta. This is a pointer to the delta since we're
2140	* not certain the delta will fit in a void pointer for all possible configs.
2141	*/
2142	static DECLCALLBACK(int) pgmR3RelocateHyperVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser)
2143	{
2144	PPGMVIRTHANDLER pHandler = (PPGMVIRTHANDLER)pNode;
2145	RTGCINTPTR offDelta = *(PRTGCINTPTR)pvUser;
2146	Assert(pHandler->enmType == PGMVIRTHANDLERTYPE_HYPERVISOR);
2147	Assert(pHandler->pfnHandlerRC);
2148	pHandler->pfnHandlerRC += offDelta;
2149	return 0;
2150	}
2151
2152
2153	/**
2154	* The VM is being reset.
2155	*
2156	* For the PGM component this means that any PD write monitors
2157	* needs to be removed.
2158	*
2159	* @param pVM VM handle.
2160	*/
2161	VMMR3DECL(void) PGMR3Reset(PVM pVM)
2162	{
2163	int rc;
2164
2165	LogFlow(("PGMR3Reset:\n"));
2166	VM_ASSERT_EMT(pVM);
2167
2168	pgmLock(pVM);
2169
2170	/*
2171	* Unfix any fixed mappings and disable CR3 monitoring.
2172	*/
2173	pVM->pgm.s.fMappingsFixed = false;
2174	pVM->pgm.s.GCPtrMappingFixed = 0;
2175	pVM->pgm.s.cbMappingFixed = 0;
2176
2177	/* Exit the guest paging mode before the pgm pool gets reset.
2178	* Important to clean up the amd64 case.
2179	*/
2180	for (unsigned i=0;i<pVM->cCPUs;i++)
2181	{
2182	PVMCPU pVCpu = &pVM->aCpus[i];
2183
2184	rc = PGM_GST_PFN(Exit, pVCpu)(pVCpu);
2185	AssertRC(rc);
2186	}
2187
2188	#ifdef DEBUG
2189	DBGFR3InfoLog(pVM, "mappings", NULL);
2190	DBGFR3InfoLog(pVM, "handlers", "all nostat");
2191	#endif
2192
2193	/*
2194	* Switch mode back to real mode. (before resetting the pgm pool!)
2195	*/
2196	for (unsigned i=0;i<pVM->cCPUs;i++)
2197	{
2198	PVMCPU pVCpu = &pVM->aCpus[i];
2199
2200	rc = PGMR3ChangeMode(pVM, pVCpu, PGMMODE_REAL);
2201	AssertRC(rc);
2202
2203	STAM_REL_COUNTER_RESET(&pVCpu->pgm.s.cGuestModeChanges);
2204	}
2205
2206	/*
2207	* Reset the shadow page pool.
2208	*/
2209	pgmR3PoolReset(pVM);
2210
2211	for (unsigned i=0;i<pVM->cCPUs;i++)
2212	{
2213	PVMCPU pVCpu = &pVM->aCpus[i];
2214
2215	/*
2216	* Re-init other members.
2217	*/
2218	pVCpu->pgm.s.fA20Enabled = true;
2219
2220	/*
2221	* Clear the FFs PGM owns.
2222	*/
2223	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
2224	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL);
2225	}
2226
2227	/*
2228	* Reset (zero) RAM pages.
2229	*/
2230	rc = pgmR3PhysRamReset(pVM);
2231	if (RT_SUCCESS(rc))
2232	{
2233	/*
2234	* Reset (zero) shadow ROM pages.
2235	*/
2236	rc = pgmR3PhysRomReset(pVM);
2237	}
2238
2239	pgmUnlock(pVM);
2240	//return rc;
2241	AssertReleaseRC(rc);
2242	}
2243
2244
2245	#ifdef VBOX_STRICT
2246	/**
2247	* VM state change callback for clearing fNoMorePhysWrites after
2248	* a snapshot has been created.
2249	*/
2250	static DECLCALLBACK(void) pgmR3ResetNoMorePhysWritesFlag(PVM pVM, VMSTATE enmState, VMSTATE enmOldState, void *pvUser)
2251	{
2252	if (enmState == VMSTATE_RUNNING)
2253	pVM->pgm.s.fNoMorePhysWrites = false;
2254	}
2255	#endif
2256
2257
2258	/**
2259	* Terminates the PGM.
2260	*
2261	* @returns VBox status code.
2262	* @param pVM Pointer to VM structure.
2263	*/
2264	VMMR3DECL(int) PGMR3Term(PVM pVM)
2265	{
2266	PGMDeregisterStringFormatTypes();
2267	return PDMR3CritSectDelete(&pVM->pgm.s.CritSect);
2268	}
2269
2270
2271	/**
2272	* Terminates the per-VCPU PGM.
2273	*
2274	* Termination means cleaning up and freeing all resources,
2275	* the VM it self is at this point powered off or suspended.
2276	*
2277	* @returns VBox status code.
2278	* @param pVM The VM to operate on.
2279	*/
2280	VMMR3DECL(int) PGMR3TermCPU(PVM pVM)
2281	{
2282	return 0;
2283	}
2284
2285
2286	/**
2287	* Find the ROM tracking structure for the given page.
2288	*
2289	* @returns Pointer to the ROM page structure. NULL if the caller didn't check
2290	* that it's a ROM page.
2291	* @param pVM The VM handle.
2292	* @param GCPhys The address of the ROM page.
2293	*/
2294	static PPGMROMPAGE pgmR3GetRomPage(PVM pVM, RTGCPHYS GCPhys)
2295	{
2296	for (PPGMROMRANGE pRomRange = pVM->pgm.s.CTX_SUFF(pRomRanges);
2297	pRomRange;
2298	pRomRange = pRomRange->CTX_SUFF(pNext))
2299	{
2300	RTGCPHYS off = GCPhys - pRomRange->GCPhys;
2301	if (GCPhys - pRomRange->GCPhys < pRomRange->cb)
2302	return &pRomRange->aPages[off >> PAGE_SHIFT];
2303	}
2304	return NULL;
2305	}
2306
2307
2308	/**
2309	* Save zero indicator + bits for the specified page.
2310	*
2311	* @returns VBox status code, errors are logged/asserted before returning.
2312	* @param pVM The VM handle.
2313	* @param pSSH The saved state handle.
2314	* @param pPage The page to save.
2315	* @param GCPhys The address of the page.
2316	* @param pRam The ram range (for error logging).
2317	*/
2318	static int pgmR3SavePage(PVM pVM, PSSMHANDLE pSSM, PPGMPAGE pPage, RTGCPHYS GCPhys, PPGMRAMRANGE pRam)
2319	{
2320	int rc;
2321	if (PGM_PAGE_IS_ZERO(pPage))
2322	rc = SSMR3PutU8(pSSM, 0);
2323	else
2324	{
2325	void const *pvPage;
2326	rc = pgmPhysGCPhys2CCPtrInternalReadOnly(pVM, pPage, GCPhys, &pvPage);
2327	AssertLogRelMsgRCReturn(rc, ("pPage=%R[pgmpage] GCPhys=%#x %s\n", pPage, GCPhys, pRam->pszDesc), rc);
2328
2329	SSMR3PutU8(pSSM, 1);
2330	rc = SSMR3PutMem(pSSM, pvPage, PAGE_SIZE);
2331	}
2332	return rc;
2333	}
2334
2335
2336	/**
2337	* Save a shadowed ROM page.
2338	*
2339	* Format: Type, protection, and two pages with zero indicators.
2340	*
2341	* @returns VBox status code, errors are logged/asserted before returning.
2342	* @param pVM The VM handle.
2343	* @param pSSH The saved state handle.
2344	* @param pPage The page to save.
2345	* @param GCPhys The address of the page.
2346	* @param pRam The ram range (for error logging).
2347	*/
2348	static int pgmR3SaveShadowedRomPage(PVM pVM, PSSMHANDLE pSSM, PPGMPAGE pPage, RTGCPHYS GCPhys, PPGMRAMRANGE pRam)
2349	{
2350	/* Need to save both pages and the current state. */
2351	PPGMROMPAGE pRomPage = pgmR3GetRomPage(pVM, GCPhys);
2352	AssertLogRelMsgReturn(pRomPage, ("GCPhys=%RGp %s\n", GCPhys, pRam->pszDesc), VERR_INTERNAL_ERROR);
2353
2354	SSMR3PutU8(pSSM, PGMPAGETYPE_ROM_SHADOW);
2355	SSMR3PutU8(pSSM, pRomPage->enmProt);
2356
2357	int rc = pgmR3SavePage(pVM, pSSM, pPage, GCPhys, pRam);
2358	if (RT_SUCCESS(rc))
2359	{
2360	PPGMPAGE pPagePassive = PGMROMPROT_IS_ROM(pRomPage->enmProt) ? &pRomPage->Shadow : &pRomPage->Virgin;
2361	rc = pgmR3SavePage(pVM, pSSM, pPagePassive, GCPhys, pRam);
2362	}
2363	return rc;
2364	}
2365
2366	/** PGM fields to save/load. */
2367	static const SSMFIELD s_aPGMFields[] =
2368	{
2369	SSMFIELD_ENTRY( PGM, fMappingsFixed),
2370	SSMFIELD_ENTRY_GCPTR( PGM, GCPtrMappingFixed),
2371	SSMFIELD_ENTRY( PGM, cbMappingFixed),
2372	SSMFIELD_ENTRY_TERM()
2373	};
2374
2375	static const SSMFIELD s_aPGMCpuFields[] =
2376	{
2377	SSMFIELD_ENTRY( PGMCPU, fA20Enabled),
2378	SSMFIELD_ENTRY_GCPHYS( PGMCPU, GCPhysA20Mask),
2379	SSMFIELD_ENTRY( PGMCPU, enmGuestMode),
2380	SSMFIELD_ENTRY_TERM()
2381	};
2382
2383	/* For loading old saved states. (pre-smp) */
2384	typedef struct
2385	{
2386	/** If set no conflict checks are required. (boolean) */
2387	bool fMappingsFixed;
2388	/** Size of fixed mapping */
2389	uint32_t cbMappingFixed;
2390	/** Base address (GC) of fixed mapping */
2391	RTGCPTR GCPtrMappingFixed;
2392	/** A20 gate mask.
2393	* Our current approach to A20 emulation is to let REM do it and don't bother
2394	* anywhere else. The interesting Guests will be operating with it enabled anyway.
2395	* But whould need arrise, we'll subject physical addresses to this mask. */
2396	RTGCPHYS GCPhysA20Mask;
2397	/** A20 gate state - boolean! */
2398	bool fA20Enabled;
2399	/** The guest paging mode. */
2400	PGMMODE enmGuestMode;
2401	} PGMOLD;
2402
2403	static const SSMFIELD s_aPGMFields_Old[] =
2404	{
2405	SSMFIELD_ENTRY( PGMOLD, fMappingsFixed),
2406	SSMFIELD_ENTRY_GCPTR( PGMOLD, GCPtrMappingFixed),
2407	SSMFIELD_ENTRY( PGMOLD, cbMappingFixed),
2408	SSMFIELD_ENTRY( PGMOLD, fA20Enabled),
2409	SSMFIELD_ENTRY_GCPHYS( PGMOLD, GCPhysA20Mask),
2410	SSMFIELD_ENTRY( PGMOLD, enmGuestMode),
2411	SSMFIELD_ENTRY_TERM()
2412	};
2413
2414
2415	/**
2416	* Execute state save operation.
2417	*
2418	* @returns VBox status code.
2419	* @param pVM VM Handle.
2420	* @param pSSM SSM operation handle.
2421	*/
2422	static DECLCALLBACK(int) pgmR3Save(PVM pVM, PSSMHANDLE pSSM)
2423	{
2424	int rc;
2425	unsigned i;
2426	PPGM pPGM = &pVM->pgm.s;
2427
2428	/*
2429	* Lock PGM and set the no-more-writes indicator.
2430	*/
2431	pgmLock(pVM);
2432	pVM->pgm.s.fNoMorePhysWrites = true;
2433
2434	/*
2435	* Save basic data (required / unaffected by relocation).
2436	*/
2437	SSMR3PutStruct(pSSM, pPGM, &s_aPGMFields[0]);
2438
2439	for (i=0;i<pVM->cCPUs;i++)
2440	{
2441	PVMCPU pVCpu = &pVM->aCpus[i];
2442
2443	SSMR3PutStruct(pSSM, &pVCpu->pgm.s, &s_aPGMCpuFields[0]);
2444	}
2445
2446	/*
2447	* The guest mappings.
2448	*/
2449	i = 0;
2450	for (PPGMMAPPING pMapping = pPGM->pMappingsR3; pMapping; pMapping = pMapping->pNextR3, i++)
2451	{
2452	SSMR3PutU32( pSSM, i);
2453	SSMR3PutStrZ( pSSM, pMapping->pszDesc); /* This is the best unique id we have... */
2454	SSMR3PutGCPtr( pSSM, pMapping->GCPtr);
2455	SSMR3PutGCUIntPtr(pSSM, pMapping->cPTs);
2456	}
2457	rc = SSMR3PutU32(pSSM, ~0); /* terminator. */
2458
2459	/*
2460	* Ram ranges and the memory they describe.
2461	*/
2462	i = 0;
2463	for (PPGMRAMRANGE pRam = pPGM->pRamRangesR3; pRam; pRam = pRam->pNextR3, i++)
2464	{
2465	/*
2466	* Save the ram range details.
2467	*/
2468	SSMR3PutU32(pSSM, i);
2469	SSMR3PutGCPhys(pSSM, pRam->GCPhys);
2470	SSMR3PutGCPhys(pSSM, pRam->GCPhysLast);
2471	SSMR3PutGCPhys(pSSM, pRam->cb);
2472	SSMR3PutU8(pSSM, !!pRam->pvR3); /* Boolean indicating memory or not. */
2473	SSMR3PutStrZ(pSSM, pRam->pszDesc); /* This is the best unique id we have... */
2474
2475	/*
2476	* Iterate the pages, only two special case.
2477	*/
2478	uint32_t const cPages = pRam->cb >> PAGE_SHIFT;
2479	for (uint32_t iPage = 0; iPage < cPages; iPage++)
2480	{
2481	RTGCPHYS GCPhysPage = pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT);
2482	PPGMPAGE pPage = &pRam->aPages[iPage];
2483	uint8_t uType = PGM_PAGE_GET_TYPE(pPage);
2484
2485	if (uType == PGMPAGETYPE_ROM_SHADOW)
2486	rc = pgmR3SaveShadowedRomPage(pVM, pSSM, pPage, GCPhysPage, pRam);
2487	else if (uType == PGMPAGETYPE_MMIO2_ALIAS_MMIO)
2488	{
2489	/* MMIO2 alias -> MMIO; the device will just have to deal with this. */
2490	SSMR3PutU8(pSSM, PGMPAGETYPE_MMIO);
2491	rc = SSMR3PutU8(pSSM, 0 /* ZERO */);
2492	}
2493	else
2494	{
2495	SSMR3PutU8(pSSM, uType);
2496	rc = pgmR3SavePage(pVM, pSSM, pPage, GCPhysPage, pRam);
2497	}
2498	if (RT_FAILURE(rc))
2499	break;
2500	}
2501	if (RT_FAILURE(rc))
2502	break;
2503	}
2504
2505	pgmUnlock(pVM);
2506	return SSMR3PutU32(pSSM, ~0); /* terminator. */
2507	}
2508
2509
2510	/**
2511	* Load an ignored page.
2512	*
2513	* @returns VBox status code.
2514	* @param pSSM The saved state handle.
2515	*/
2516	static int pgmR3LoadPageToDevNull(PSSMHANDLE pSSM)
2517	{
2518	uint8_t abPage[PAGE_SIZE];
2519	return SSMR3GetMem(pSSM, &abPage[0], sizeof(abPage));
2520	}
2521
2522
2523	/**
2524	* Loads a page without any bits in the saved state, i.e. making sure it's
2525	* really zero.
2526	*
2527	* @returns VBox status code.
2528	* @param pVM The VM handle.
2529	* @param uType The page type or PGMPAGETYPE_INVALID (old saved
2530	* state).
2531	* @param pPage The guest page tracking structure.
2532	* @param GCPhys The page address.
2533	* @param pRam The ram range (logging).
2534	*/
2535	static int pgmR3LoadPageZero(PVM pVM, uint8_t uType, PPGMPAGE pPage, RTGCPHYS GCPhys, PPGMRAMRANGE pRam)
2536	{
2537	if ( PGM_PAGE_GET_TYPE(pPage) != uType
2538	&& uType != PGMPAGETYPE_INVALID)
2539	return VERR_SSM_UNEXPECTED_DATA;
2540
2541	/* I think this should be sufficient. */
2542	if (!PGM_PAGE_IS_ZERO(pPage))
2543	return VERR_SSM_UNEXPECTED_DATA;
2544
2545	NOREF(pVM);
2546	NOREF(GCPhys);
2547	NOREF(pRam);
2548	return VINF_SUCCESS;
2549	}
2550
2551
2552	/**
2553	* Loads a page from the saved state.
2554	*
2555	* @returns VBox status code.
2556	* @param pVM The VM handle.
2557	* @param pSSM The SSM handle.
2558	* @param uType The page type or PGMPAGETYEP_INVALID (old saved
2559	* state).
2560	* @param pPage The guest page tracking structure.
2561	* @param GCPhys The page address.
2562	* @param pRam The ram range (logging).
2563	*/
2564	static int pgmR3LoadPageBits(PVM pVM, PSSMHANDLE pSSM, uint8_t uType, PPGMPAGE pPage, RTGCPHYS GCPhys, PPGMRAMRANGE pRam)
2565	{
2566	int rc;
2567
2568	/*
2569	* Match up the type, dealing with MMIO2 aliases (dropped).
2570	*/
2571	AssertLogRelMsgReturn( PGM_PAGE_GET_TYPE(pPage) == uType
2572	\|\| uType == PGMPAGETYPE_INVALID,
2573	("pPage=%R[pgmpage] GCPhys=%#x %s\n", pPage, GCPhys, pRam->pszDesc),
2574	VERR_SSM_UNEXPECTED_DATA);
2575
2576	/*
2577	* Load the page.
2578	*/
2579	void *pvPage;
2580	rc = pgmPhysGCPhys2CCPtrInternal(pVM, pPage, GCPhys, &pvPage);
2581	if (RT_SUCCESS(rc))
2582	rc = SSMR3GetMem(pSSM, pvPage, PAGE_SIZE);
2583
2584	return rc;
2585	}
2586
2587
2588	/**
2589	* Loads a page (counter part to pgmR3SavePage).
2590	*
2591	* @returns VBox status code, fully bitched errors.
2592	* @param pVM The VM handle.
2593	* @param pSSM The SSM handle.
2594	* @param uType The page type.
2595	* @param pPage The page.
2596	* @param GCPhys The page address.
2597	* @param pRam The RAM range (for error messages).
2598	*/
2599	static int pgmR3LoadPage(PVM pVM, PSSMHANDLE pSSM, uint8_t uType, PPGMPAGE pPage, RTGCPHYS GCPhys, PPGMRAMRANGE pRam)
2600	{
2601	uint8_t uState;
2602	int rc = SSMR3GetU8(pSSM, &uState);
2603	AssertLogRelMsgRCReturn(rc, ("pPage=%R[pgmpage] GCPhys=%#x %s rc=%Rrc\n", pPage, GCPhys, pRam->pszDesc, rc), rc);
2604	if (uState == 0 /* zero */)
2605	rc = pgmR3LoadPageZero(pVM, uType, pPage, GCPhys, pRam);
2606	else if (uState == 1)
2607	rc = pgmR3LoadPageBits(pVM, pSSM, uType, pPage, GCPhys, pRam);
2608	else
2609	rc = VERR_INTERNAL_ERROR;
2610	AssertLogRelMsgRCReturn(rc, ("pPage=%R[pgmpage] uState=%d uType=%d GCPhys=%RGp %s rc=%Rrc\n",
2611	pPage, uState, uType, GCPhys, pRam->pszDesc, rc),
2612	rc);
2613	return VINF_SUCCESS;
2614	}
2615
2616
2617	/**
2618	* Loads a shadowed ROM page.
2619	*
2620	* @returns VBox status code, errors are fully bitched.
2621	* @param pVM The VM handle.
2622	* @param pSSM The saved state handle.
2623	* @param pPage The page.
2624	* @param GCPhys The page address.
2625	* @param pRam The RAM range (for error messages).
2626	*/
2627	static int pgmR3LoadShadowedRomPage(PVM pVM, PSSMHANDLE pSSM, PPGMPAGE pPage, RTGCPHYS GCPhys, PPGMRAMRANGE pRam)
2628	{
2629	/*
2630	* Load and set the protection first, then load the two pages, the first
2631	* one is the active the other is the passive.
2632	*/
2633	PPGMROMPAGE pRomPage = pgmR3GetRomPage(pVM, GCPhys);
2634	AssertLogRelMsgReturn(pRomPage, ("GCPhys=%RGp %s\n", GCPhys, pRam->pszDesc), VERR_INTERNAL_ERROR);
2635
2636	uint8_t uProt;
2637	int rc = SSMR3GetU8(pSSM, &uProt);
2638	AssertLogRelMsgRCReturn(rc, ("pPage=%R[pgmpage] GCPhys=%#x %s\n", pPage, GCPhys, pRam->pszDesc), rc);
2639	PGMROMPROT enmProt = (PGMROMPROT)uProt;
2640	AssertLogRelMsgReturn( enmProt >= PGMROMPROT_INVALID
2641	&& enmProt < PGMROMPROT_END,
2642	("enmProt=%d pPage=%R[pgmpage] GCPhys=%#x %s\n", enmProt, pPage, GCPhys, pRam->pszDesc),
2643	VERR_SSM_UNEXPECTED_DATA);
2644
2645	if (pRomPage->enmProt != enmProt)
2646	{
2647	rc = PGMR3PhysRomProtect(pVM, GCPhys, PAGE_SIZE, enmProt);
2648	AssertLogRelRCReturn(rc, rc);
2649	AssertLogRelReturn(pRomPage->enmProt == enmProt, VERR_INTERNAL_ERROR);
2650	}
2651
2652	PPGMPAGE pPageActive = PGMROMPROT_IS_ROM(enmProt) ? &pRomPage->Virgin : &pRomPage->Shadow;
2653	PPGMPAGE pPagePassive = PGMROMPROT_IS_ROM(enmProt) ? &pRomPage->Shadow : &pRomPage->Virgin;
2654	uint8_t u8ActiveType = PGMROMPROT_IS_ROM(enmProt) ? PGMPAGETYPE_ROM : PGMPAGETYPE_ROM_SHADOW;
2655	uint8_t u8PassiveType= PGMROMPROT_IS_ROM(enmProt) ? PGMPAGETYPE_ROM_SHADOW : PGMPAGETYPE_ROM;
2656
2657	rc = pgmR3LoadPage(pVM, pSSM, u8ActiveType, pPage, GCPhys, pRam);
2658	if (RT_SUCCESS(rc))
2659	{
2660	pPageActive = pPage;
2661	rc = pgmR3LoadPage(pVM, pSSM, u8PassiveType, pPagePassive, GCPhys, pRam);
2662	}
2663	return rc;
2664	}
2665
2666
2667	/**
2668	* Worker for pgmR3Load.
2669	*
2670	* @returns VBox status code.
2671	*
2672	* @param pVM The VM handle.
2673	* @param pSSM The SSM handle.
2674	* @param u32Version The saved state version.
2675	*/
2676	static int pgmR3LoadLocked(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version)
2677	{
2678	PPGM pPGM = &pVM->pgm.s;
2679	int rc;
2680	uint32_t u32Sep;
2681
2682	/*
2683	* Load basic data (required / unaffected by relocation).
2684	*/
2685	if (u32Version >= PGM_SAVED_STATE_VERSION)
2686	{
2687	rc = SSMR3GetStruct(pSSM, pPGM, &s_aPGMFields[0]);
2688	AssertLogRelRCReturn(rc, rc);
2689
2690	for (VMCPUID i = 0; i < pVM->cCPUs; i++)
2691	{
2692	rc = SSMR3GetStruct(pSSM, &pVM->aCpus[i].pgm.s, &s_aPGMCpuFields[0]);
2693	AssertLogRelRCReturn(rc, rc);
2694	}
2695	}
2696	else if (u32Version >= PGM_SAVED_STATE_VERSION_RR_DESC)
2697	{
2698	AssertRelease(pVM->cCPUs == 1);
2699
2700	PGMOLD pgmOld;
2701	rc = SSMR3GetStruct(pSSM, &pgmOld, &s_aPGMFields_Old[0]);
2702	AssertLogRelRCReturn(rc, rc);
2703
2704	pPGM->fMappingsFixed = pgmOld.fMappingsFixed;
2705	pPGM->GCPtrMappingFixed = pgmOld.GCPtrMappingFixed;
2706	pPGM->cbMappingFixed = pgmOld.cbMappingFixed;
2707
2708	pVM->aCpus[0].pgm.s.fA20Enabled = pgmOld.fA20Enabled;
2709	pVM->aCpus[0].pgm.s.GCPhysA20Mask = pgmOld.GCPhysA20Mask;
2710	pVM->aCpus[0].pgm.s.enmGuestMode = pgmOld.enmGuestMode;
2711	}
2712	else
2713	{
2714	AssertRelease(pVM->cCPUs == 1);
2715
2716	SSMR3GetBool(pSSM, &pPGM->fMappingsFixed);
2717	SSMR3GetGCPtr(pSSM, &pPGM->GCPtrMappingFixed);
2718	SSMR3GetU32(pSSM, &pPGM->cbMappingFixed);
2719
2720	uint32_t cbRamSizeIgnored;
2721	rc = SSMR3GetU32(pSSM, &cbRamSizeIgnored);
2722	if (RT_FAILURE(rc))
2723	return rc;
2724	SSMR3GetGCPhys(pSSM, &pVM->aCpus[0].pgm.s.GCPhysA20Mask);
2725
2726	uint32_t u32 = 0;
2727	SSMR3GetUInt(pSSM, &u32);
2728	pVM->aCpus[0].pgm.s.fA20Enabled = !!u32;
2729	SSMR3GetUInt(pSSM, &pVM->aCpus[0].pgm.s.fSyncFlags);
2730	RTUINT uGuestMode;
2731	SSMR3GetUInt(pSSM, &uGuestMode);
2732	pVM->aCpus[0].pgm.s.enmGuestMode = (PGMMODE)uGuestMode;
2733
2734	/* check separator. */
2735	SSMR3GetU32(pSSM, &u32Sep);
2736	if (RT_FAILURE(rc))
2737	return rc;
2738	if (u32Sep != (uint32_t)~0)
2739	{
2740	AssertMsgFailed(("u32Sep=%#x (first)\n", u32Sep));
2741	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2742	}
2743	}
2744
2745	/*
2746	* The guest mappings.
2747	*/
2748	uint32_t i = 0;
2749	for (;; i++)
2750	{
2751	/* Check the seqence number / separator. */
2752	rc = SSMR3GetU32(pSSM, &u32Sep);
2753	if (RT_FAILURE(rc))
2754	return rc;
2755	if (u32Sep == ~0U)
2756	break;
2757	if (u32Sep != i)
2758	{
2759	AssertMsgFailed(("u32Sep=%#x (last)\n", u32Sep));
2760	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2761	}
2762
2763	/* get the mapping details. */
2764	char szDesc[256];
2765	szDesc[0] = '\0';
2766	rc = SSMR3GetStrZ(pSSM, szDesc, sizeof(szDesc));
2767	if (RT_FAILURE(rc))
2768	return rc;
2769	RTGCPTR GCPtr;
2770	SSMR3GetGCPtr(pSSM, &GCPtr);
2771	RTGCPTR cPTs;
2772	rc = SSMR3GetGCUIntPtr(pSSM, &cPTs);
2773	if (RT_FAILURE(rc))
2774	return rc;
2775
2776	/* find matching range. */
2777	PPGMMAPPING pMapping;
2778	for (pMapping = pPGM->pMappingsR3; pMapping; pMapping = pMapping->pNextR3)
2779	if ( pMapping->cPTs == cPTs
2780	&& !strcmp(pMapping->pszDesc, szDesc))
2781	break;
2782	AssertLogRelMsgReturn(pMapping, ("Couldn't find mapping: cPTs=%#x szDesc=%s (GCPtr=%RGv)\n",
2783	cPTs, szDesc, GCPtr),
2784	VERR_SSM_LOAD_CONFIG_MISMATCH);
2785
2786	/* relocate it. */
2787	if (pMapping->GCPtr != GCPtr)
2788	{
2789	AssertMsg((GCPtr >> X86_PD_SHIFT << X86_PD_SHIFT) == GCPtr, ("GCPtr=%RGv\n", GCPtr));
2790	pgmR3MapRelocate(pVM, pMapping, pMapping->GCPtr, GCPtr);
2791	}
2792	else
2793	Log(("pgmR3Load: '%s' needed no relocation (%RGv)\n", szDesc, GCPtr));
2794	}
2795
2796	/*
2797	* Ram range flags and bits.
2798	*/
2799	i = 0;
2800	for (PPGMRAMRANGE pRam = pPGM->pRamRangesR3; ; pRam = pRam->pNextR3, i++)
2801	{
2802	/* Check the seqence number / separator. */
2803	rc = SSMR3GetU32(pSSM, &u32Sep);
2804	if (RT_FAILURE(rc))
2805	return rc;
2806	if (u32Sep == ~0U)
2807	break;
2808	if (u32Sep != i)
2809	{
2810	AssertMsgFailed(("u32Sep=%#x (last)\n", u32Sep));
2811	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2812	}
2813	AssertLogRelReturn(pRam, VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2814
2815	/* Get the range details. */
2816	RTGCPHYS GCPhys;
2817	SSMR3GetGCPhys(pSSM, &GCPhys);
2818	RTGCPHYS GCPhysLast;
2819	SSMR3GetGCPhys(pSSM, &GCPhysLast);
2820	RTGCPHYS cb;
2821	SSMR3GetGCPhys(pSSM, &cb);
2822	uint8_t fHaveBits;
2823	rc = SSMR3GetU8(pSSM, &fHaveBits);
2824	if (RT_FAILURE(rc))
2825	return rc;
2826	if (fHaveBits & ~1)
2827	{
2828	AssertMsgFailed(("u32Sep=%#x (last)\n", u32Sep));
2829	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2830	}
2831	size_t cchDesc = 0;
2832	char szDesc[256];
2833	szDesc[0] = '\0';
2834	if (u32Version >= PGM_SAVED_STATE_VERSION_RR_DESC)
2835	{
2836	rc = SSMR3GetStrZ(pSSM, szDesc, sizeof(szDesc));
2837	if (RT_FAILURE(rc))
2838	return rc;
2839	/* Since we've modified the description strings in r45878, only compare
2840	them if the saved state is more recent. */
2841	if (u32Version != PGM_SAVED_STATE_VERSION_RR_DESC)
2842	cchDesc = strlen(szDesc);
2843	}
2844
2845	/*
2846	* Match it up with the current range.
2847	*
2848	* Note there is a hack for dealing with the high BIOS mapping
2849	* in the old saved state format, this means we might not have
2850	* a 1:1 match on success.
2851	*/
2852	if ( ( GCPhys != pRam->GCPhys
2853	\|\| GCPhysLast != pRam->GCPhysLast
2854	\|\| cb != pRam->cb
2855	\|\| ( cchDesc
2856	&& strcmp(szDesc, pRam->pszDesc)) )
2857	/* Hack for PDMDevHlpPhysReserve(pDevIns, 0xfff80000, 0x80000, "High ROM Region"); */
2858	&& ( u32Version != PGM_SAVED_STATE_VERSION_OLD_PHYS_CODE
2859	\|\| GCPhys != UINT32_C(0xfff80000)
2860	\|\| GCPhysLast != UINT32_C(0xffffffff)
2861	\|\| pRam->GCPhysLast != GCPhysLast
2862	\|\| pRam->GCPhys < GCPhys
2863	\|\| !fHaveBits)
2864	)
2865	{
2866	LogRel(("Ram range: %RGp-%RGp %RGp bytes %s %s\n"
2867	"State : %RGp-%RGp %RGp bytes %s %s\n",
2868	pRam->GCPhys, pRam->GCPhysLast, pRam->cb, pRam->pvR3 ? "bits" : "nobits", pRam->pszDesc,
2869	GCPhys, GCPhysLast, cb, fHaveBits ? "bits" : "nobits", szDesc));
2870	/*
2871	* If we're loading a state for debugging purpose, don't make a fuss if
2872	* the MMIO and ROM stuff isn't 100% right, just skip the mismatches.
2873	*/
2874	if ( SSMR3HandleGetAfter(pSSM) != SSMAFTER_DEBUG_IT
2875	\|\| GCPhys < 8 * _1M)
2876	AssertFailedReturn(VERR_SSM_LOAD_CONFIG_MISMATCH);
2877
2878	AssertMsgFailed(("debug skipping not implemented, sorry\n"));
2879	continue;
2880	}
2881
2882	uint32_t cPages = (GCPhysLast - GCPhys + 1) >> PAGE_SHIFT;
2883	if (u32Version >= PGM_SAVED_STATE_VERSION_RR_DESC)
2884	{
2885	/*
2886	* Load the pages one by one.
2887	*/
2888	for (uint32_t iPage = 0; iPage < cPages; iPage++)
2889	{
2890	RTGCPHYS const GCPhysPage = ((RTGCPHYS)iPage << PAGE_SHIFT) + pRam->GCPhys;
2891	PPGMPAGE pPage = &pRam->aPages[iPage];
2892	uint8_t uType;
2893	rc = SSMR3GetU8(pSSM, &uType);
2894	AssertLogRelMsgRCReturn(rc, ("pPage=%R[pgmpage] iPage=%#x GCPhysPage=%#x %s\n", pPage, iPage, GCPhysPage, pRam->pszDesc), rc);
2895	if (uType == PGMPAGETYPE_ROM_SHADOW)
2896	rc = pgmR3LoadShadowedRomPage(pVM, pSSM, pPage, GCPhysPage, pRam);
2897	else
2898	rc = pgmR3LoadPage(pVM, pSSM, uType, pPage, GCPhysPage, pRam);
2899	AssertLogRelMsgRCReturn(rc, ("rc=%Rrc iPage=%#x GCPhysPage=%#x %s\n", rc, iPage, GCPhysPage, pRam->pszDesc), rc);
2900	}
2901	}
2902	else
2903	{
2904	/*
2905	* Old format.
2906	*/
2907	AssertLogRelReturn(!pVM->pgm.s.fRamPreAlloc, VERR_NOT_SUPPORTED); /* can't be detected. */
2908
2909	/* Of the page flags, pick up MMIO2 and ROM/RESERVED for the !fHaveBits case.
2910	The rest is generally irrelevant and wrong since the stuff have to match registrations. */
2911	uint32_t fFlags = 0;
2912	for (uint32_t iPage = 0; iPage < cPages; iPage++)
2913	{
2914	uint16_t u16Flags;
2915	rc = SSMR3GetU16(pSSM, &u16Flags);
2916	AssertLogRelMsgRCReturn(rc, ("rc=%Rrc iPage=%#x GCPhys=%#x %s\n", rc, iPage, pRam->GCPhys, pRam->pszDesc), rc);
2917	fFlags \|= u16Flags;
2918	}
2919
2920	/* Load the bits */
2921	if ( !fHaveBits
2922	&& GCPhysLast < UINT32_C(0xe0000000))
2923	{
2924	/*
2925	* Dynamic chunks.
2926	*/
2927	const uint32_t cPagesInChunk = (110241024) >> PAGE_SHIFT;
2928	AssertLogRelMsgReturn(cPages % cPagesInChunk == 0,
2929	("cPages=%#x cPagesInChunk=%#x\n", cPages, cPagesInChunk, pRam->GCPhys, pRam->pszDesc),
2930	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2931
2932	for (uint32_t iPage = 0; iPage < cPages; /* incremented by inner loop */ )
2933	{
2934	uint8_t fPresent;
2935	rc = SSMR3GetU8(pSSM, &fPresent);
2936	AssertLogRelMsgRCReturn(rc, ("rc=%Rrc iPage=%#x GCPhys=%#x %s\n", rc, iPage, pRam->GCPhys, pRam->pszDesc), rc);
2937	AssertLogRelMsgReturn(fPresent == (uint8_t)true \|\| fPresent == (uint8_t)false,
2938	("fPresent=%#x iPage=%#x GCPhys=%#x %s\n", fPresent, iPage, pRam->GCPhys, pRam->pszDesc),
2939	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2940
2941	for (uint32_t iChunkPage = 0; iChunkPage < cPagesInChunk; iChunkPage++, iPage++)
2942	{
2943	RTGCPHYS const GCPhysPage = ((RTGCPHYS)iPage << PAGE_SHIFT) + pRam->GCPhys;
2944	PPGMPAGE pPage = &pRam->aPages[iPage];
2945	if (fPresent)
2946	{
2947	if (PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_MMIO)
2948	rc = pgmR3LoadPageToDevNull(pSSM);
2949	else
2950	rc = pgmR3LoadPageBits(pVM, pSSM, PGMPAGETYPE_INVALID, pPage, GCPhysPage, pRam);
2951	}
2952	else
2953	rc = pgmR3LoadPageZero(pVM, PGMPAGETYPE_INVALID, pPage, GCPhysPage, pRam);
2954	AssertLogRelMsgRCReturn(rc, ("rc=%Rrc iPage=%#x GCPhysPage=%#x %s\n", rc, iPage, GCPhysPage, pRam->pszDesc), rc);
2955	}
2956	}
2957	}
2958	else if (pRam->pvR3)
2959	{
2960	/*
2961	* MMIO2.
2962	*/
2963	AssertLogRelMsgReturn((fFlags & 0x0f) == RT_BIT(3) /MM_RAM_FLAGS_MMIO2/,
2964	("fFlags=%#x GCPhys=%#x %s\n", fFlags, pRam->GCPhys, pRam->pszDesc),
2965	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2966	AssertLogRelMsgReturn(pRam->pvR3,
2967	("GCPhys=%#x %s\n", pRam->GCPhys, pRam->pszDesc),
2968	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2969
2970	rc = SSMR3GetMem(pSSM, pRam->pvR3, pRam->cb);
2971	AssertLogRelMsgRCReturn(rc, ("GCPhys=%#x %s\n", pRam->GCPhys, pRam->pszDesc), rc);
2972	}
2973	else if (GCPhysLast < UINT32_C(0xfff80000))
2974	{
2975	/*
2976	* PCI MMIO, no pages saved.
2977	*/
2978	}
2979	else
2980	{
2981	/*
2982	* Load the 0xfff80000..0xffffffff BIOS range.
2983	* It starts with X reserved pages that we have to skip over since
2984	* the RAMRANGE create by the new code won't include those.
2985	*/
2986	AssertLogRelMsgReturn( !(fFlags & RT_BIT(3) /MM_RAM_FLAGS_MMIO2/)
2987	&& (fFlags & RT_BIT(0) /MM_RAM_FLAGS_RESERVED/),
2988	("fFlags=%#x GCPhys=%#x %s\n", fFlags, pRam->GCPhys, pRam->pszDesc),
2989	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2990	AssertLogRelMsgReturn(GCPhys == UINT32_C(0xfff80000),
2991	("GCPhys=%RGp pRamRange{GCPhys=%#x %s}\n", GCPhys, pRam->GCPhys, pRam->pszDesc),
2992	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2993
2994	/* Skip wasted reserved pages before the ROM. */
2995	while (GCPhys < pRam->GCPhys)
2996	{
2997	rc = pgmR3LoadPageToDevNull(pSSM);
2998	GCPhys += PAGE_SIZE;
2999	}
3000
3001	/* Load the bios pages. */
3002	cPages = pRam->cb >> PAGE_SHIFT;
3003	for (uint32_t iPage = 0; iPage < cPages; iPage++)
3004	{
3005	RTGCPHYS const GCPhysPage = ((RTGCPHYS)iPage << PAGE_SHIFT) + pRam->GCPhys;
3006	PPGMPAGE pPage = &pRam->aPages[iPage];
3007
3008	AssertLogRelMsgReturn(PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_ROM,
3009	("GCPhys=%RGp pPage=%R[pgmpage]\n", GCPhys, GCPhys),
3010	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
3011	rc = pgmR3LoadPageBits(pVM, pSSM, PGMPAGETYPE_ROM, pPage, GCPhysPage, pRam);
3012	AssertLogRelMsgRCReturn(rc, ("rc=%Rrc iPage=%#x GCPhys=%#x %s\n", rc, iPage, pRam->GCPhys, pRam->pszDesc), rc);
3013	}
3014	}
3015	}
3016	}
3017
3018	return rc;
3019	}
3020
3021
3022	/**
3023	* Execute state load operation.
3024	*
3025	* @returns VBox status code.
3026	* @param pVM VM Handle.
3027	* @param pSSM SSM operation handle.
3028	* @param u32Version Data layout version.
3029	*/
3030	static DECLCALLBACK(int) pgmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version)
3031	{
3032	int rc;
3033	PPGM pPGM = &pVM->pgm.s;
3034
3035	/*
3036	* Validate version.
3037	*/
3038	if ( u32Version != PGM_SAVED_STATE_VERSION
3039	&& u32Version != PGM_SAVED_STATE_VERSION_2_2_2
3040	&& u32Version != PGM_SAVED_STATE_VERSION_RR_DESC
3041	&& u32Version != PGM_SAVED_STATE_VERSION_OLD_PHYS_CODE)
3042	{
3043	AssertMsgFailed(("pgmR3Load: Invalid version u32Version=%d (current %d)!\n", u32Version, PGM_SAVED_STATE_VERSION));
3044	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
3045	}
3046
3047	/*
3048	* Call the reset function to make sure all the memory is cleared.
3049	*/
3050	PGMR3Reset(pVM);
3051
3052	/*
3053	* Do the loading while owning the lock because a bunch of the functions
3054	* we're using requires this.
3055	*/
3056	pgmLock(pVM);
3057	rc = pgmR3LoadLocked(pVM, pSSM, u32Version);
3058	pgmUnlock(pVM);
3059	if (RT_SUCCESS(rc))
3060	{
3061	/*
3062	* We require a full resync now.
3063	*/
3064	for (unsigned i=0;i<pVM->cCPUs;i++)
3065	{
3066	PVMCPU pVCpu = &pVM->aCpus[i];
3067	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL);
3068	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
3069
3070	pVCpu->pgm.s.fSyncFlags \|= PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL;
3071	}
3072
3073	pgmR3HandlerPhysicalUpdateAll(pVM);
3074
3075	for (unsigned i=0;i<pVM->cCPUs;i++)
3076	{
3077	PVMCPU pVCpu = &pVM->aCpus[i];
3078
3079	/*
3080	* Change the paging mode.
3081	*/
3082	rc = PGMR3ChangeMode(pVM, pVCpu, pVCpu->pgm.s.enmGuestMode);
3083
3084	/* Restore pVM->pgm.s.GCPhysCR3. */
3085	Assert(pVCpu->pgm.s.GCPhysCR3 == NIL_RTGCPHYS);
3086	RTGCPHYS GCPhysCR3 = CPUMGetGuestCR3(pVCpu);
3087	if ( pVCpu->pgm.s.enmGuestMode == PGMMODE_PAE
3088	\|\| pVCpu->pgm.s.enmGuestMode == PGMMODE_PAE_NX
3089	\|\| pVCpu->pgm.s.enmGuestMode == PGMMODE_AMD64
3090	\|\| pVCpu->pgm.s.enmGuestMode == PGMMODE_AMD64_NX)
3091	GCPhysCR3 = (GCPhysCR3 & X86_CR3_PAE_PAGE_MASK);
3092	else
3093	GCPhysCR3 = (GCPhysCR3 & X86_CR3_PAGE_MASK);
3094	pVCpu->pgm.s.GCPhysCR3 = GCPhysCR3;
3095	}
3096	}
3097
3098	return rc;
3099	}
3100
3101
3102	/**
3103	* Show paging mode.
3104	*
3105	* @param pVM VM Handle.
3106	* @param pHlp The info helpers.
3107	* @param pszArgs "all" (default), "guest", "shadow" or "host".
3108	*/
3109	static DECLCALLBACK(void) pgmR3InfoMode(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3110	{
3111	/* digest argument. */
3112	bool fGuest, fShadow, fHost;
3113	if (pszArgs)
3114	pszArgs = RTStrStripL(pszArgs);
3115	if (!pszArgs \|\| !*pszArgs \|\| strstr(pszArgs, "all"))
3116	fShadow = fHost = fGuest = true;
3117	else
3118	{
3119	fShadow = fHost = fGuest = false;
3120	if (strstr(pszArgs, "guest"))
3121	fGuest = true;
3122	if (strstr(pszArgs, "shadow"))
3123	fShadow = true;
3124	if (strstr(pszArgs, "host"))
3125	fHost = true;
3126	}
3127
3128	/** @todo SMP support! */
3129	/* print info. */
3130	if (fGuest)
3131	pHlp->pfnPrintf(pHlp, "Guest paging mode: %s, changed %RU64 times, A20 %s\n",
3132	PGMGetModeName(pVM->aCpus[0].pgm.s.enmGuestMode), pVM->aCpus[0].pgm.s.cGuestModeChanges.c,
3133	pVM->aCpus[0].pgm.s.fA20Enabled ? "enabled" : "disabled");
3134	if (fShadow)
3135	pHlp->pfnPrintf(pHlp, "Shadow paging mode: %s\n", PGMGetModeName(pVM->aCpus[0].pgm.s.enmShadowMode));
3136	if (fHost)
3137	{
3138	const char *psz;
3139	switch (pVM->pgm.s.enmHostMode)
3140	{
3141	case SUPPAGINGMODE_INVALID: psz = "invalid"; break;
3142	case SUPPAGINGMODE_32_BIT: psz = "32-bit"; break;
3143	case SUPPAGINGMODE_32_BIT_GLOBAL: psz = "32-bit+G"; break;
3144	case SUPPAGINGMODE_PAE: psz = "PAE"; break;
3145	case SUPPAGINGMODE_PAE_GLOBAL: psz = "PAE+G"; break;
3146	case SUPPAGINGMODE_PAE_NX: psz = "PAE+NX"; break;
3147	case SUPPAGINGMODE_PAE_GLOBAL_NX: psz = "PAE+G+NX"; break;
3148	case SUPPAGINGMODE_AMD64: psz = "AMD64"; break;
3149	case SUPPAGINGMODE_AMD64_GLOBAL: psz = "AMD64+G"; break;
3150	case SUPPAGINGMODE_AMD64_NX: psz = "AMD64+NX"; break;
3151	case SUPPAGINGMODE_AMD64_GLOBAL_NX: psz = "AMD64+G+NX"; break;
3152	default: psz = "unknown"; break;
3153	}
3154	pHlp->pfnPrintf(pHlp, "Host paging mode: %s\n", psz);
3155	}
3156	}
3157
3158
3159	/**
3160	* Dump registered MMIO ranges to the log.
3161	*
3162	* @param pVM VM Handle.
3163	* @param pHlp The info helpers.
3164	* @param pszArgs Arguments, ignored.
3165	*/
3166	static DECLCALLBACK(void) pgmR3PhysInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3167	{
3168	NOREF(pszArgs);
3169	pHlp->pfnPrintf(pHlp,
3170	"RAM ranges (pVM=%p)\n"
3171	"%.s %.s\n",
3172	pVM,
3173	sizeof(RTGCPHYS) * 4 + 1, "GC Phys Range ",
3174	sizeof(RTHCPTR) * 2, "pvHC ");
3175
3176	for (PPGMRAMRANGE pCur = pVM->pgm.s.pRamRangesR3; pCur; pCur = pCur->pNextR3)
3177	pHlp->pfnPrintf(pHlp,
3178	"%RGp-%RGp %RHv %s\n",
3179	pCur->GCPhys,
3180	pCur->GCPhysLast,
3181	pCur->pvR3,
3182	pCur->pszDesc);
3183	}
3184
3185	/**
3186	* Dump the page directory to the log.
3187	*
3188	* @param pVM VM Handle.
3189	* @param pHlp The info helpers.
3190	* @param pszArgs Arguments, ignored.
3191	*/
3192	static DECLCALLBACK(void) pgmR3InfoCr3(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3193	{
3194	/** @todo SMP support!! */
3195	PVMCPU pVCpu = &pVM->aCpus[0];
3196
3197	/** @todo fix this! Convert the PGMR3DumpHierarchyHC functions to do guest stuff. */
3198	/* Big pages supported? */
3199	const bool fPSE = !!(CPUMGetGuestCR4(pVCpu) & X86_CR4_PSE);
3200
3201	/* Global pages supported? */
3202	const bool fPGE = !!(CPUMGetGuestCR4(pVCpu) & X86_CR4_PGE);
3203
3204	NOREF(pszArgs);
3205
3206	/*
3207	* Get page directory addresses.
3208	*/
3209	PX86PD pPDSrc = pgmGstGet32bitPDPtr(&pVCpu->pgm.s);
3210	Assert(pPDSrc);
3211	Assert(PGMPhysGCPhys2R3PtrAssert(pVM, (RTGCPHYS)(CPUMGetGuestCR3(pVCpu) & X86_CR3_PAGE_MASK), sizeof(*pPDSrc)) == pPDSrc);
3212
3213	/*
3214	* Iterate the page directory.
3215	*/
3216	for (unsigned iPD = 0; iPD < RT_ELEMENTS(pPDSrc->a); iPD++)
3217	{
3218	X86PDE PdeSrc = pPDSrc->a[iPD];
3219	if (PdeSrc.n.u1Present)
3220	{
3221	if (PdeSrc.b.u1Size && fPSE)
3222	pHlp->pfnPrintf(pHlp,
3223	"%04X - %RGp P=%d U=%d RW=%d G=%d - BIG\n",
3224	iPD,
3225	pgmGstGet4MBPhysPage(&pVM->pgm.s, PdeSrc),
3226	PdeSrc.b.u1Present, PdeSrc.b.u1User, PdeSrc.b.u1Write, PdeSrc.b.u1Global && fPGE);
3227	else
3228	pHlp->pfnPrintf(pHlp,
3229	"%04X - %RGp P=%d U=%d RW=%d [G=%d]\n",
3230	iPD,
3231	(RTGCPHYS)(PdeSrc.u & X86_PDE_PG_MASK),
3232	PdeSrc.n.u1Present, PdeSrc.n.u1User, PdeSrc.n.u1Write, PdeSrc.b.u1Global && fPGE);
3233	}
3234	}
3235	}
3236
3237
3238	/**
3239	* Service a VMMCALLRING3_PGM_LOCK call.
3240	*
3241	* @returns VBox status code.
3242	* @param pVM The VM handle.
3243	*/
3244	VMMR3DECL(int) PGMR3LockCall(PVM pVM)
3245	{
3246	int rc = PDMR3CritSectEnterEx(&pVM->pgm.s.CritSect, true /* fHostCall */);
3247	AssertRC(rc);
3248	return rc;
3249	}
3250
3251
3252	/**
3253	* Converts a PGMMODE value to a PGM_TYPE_* \#define.
3254	*
3255	* @returns PGM_TYPE_*.
3256	* @param pgmMode The mode value to convert.
3257	*/
3258	DECLINLINE(unsigned) pgmModeToType(PGMMODE pgmMode)
3259	{
3260	switch (pgmMode)
3261	{
3262	case PGMMODE_REAL: return PGM_TYPE_REAL;
3263	case PGMMODE_PROTECTED: return PGM_TYPE_PROT;
3264	case PGMMODE_32_BIT: return PGM_TYPE_32BIT;
3265	case PGMMODE_PAE:
3266	case PGMMODE_PAE_NX: return PGM_TYPE_PAE;
3267	case PGMMODE_AMD64:
3268	case PGMMODE_AMD64_NX: return PGM_TYPE_AMD64;
3269	case PGMMODE_NESTED: return PGM_TYPE_NESTED;
3270	case PGMMODE_EPT: return PGM_TYPE_EPT;
3271	default:
3272	AssertFatalMsgFailed(("pgmMode=%d\n", pgmMode));
3273	}
3274	}
3275
3276
3277	/**
3278	* Gets the index into the paging mode data array of a SHW+GST mode.
3279	*
3280	* @returns PGM::paPagingData index.
3281	* @param uShwType The shadow paging mode type.
3282	* @param uGstType The guest paging mode type.
3283	*/
3284	DECLINLINE(unsigned) pgmModeDataIndex(unsigned uShwType, unsigned uGstType)
3285	{
3286	Assert(uShwType >= PGM_TYPE_32BIT && uShwType <= PGM_TYPE_MAX);
3287	Assert(uGstType >= PGM_TYPE_REAL && uGstType <= PGM_TYPE_AMD64);
3288	return (uShwType - PGM_TYPE_32BIT) * (PGM_TYPE_AMD64 - PGM_TYPE_REAL + 1)
3289	+ (uGstType - PGM_TYPE_REAL);
3290	}
3291
3292
3293	/**
3294	* Gets the index into the paging mode data array of a SHW+GST mode.
3295	*
3296	* @returns PGM::paPagingData index.
3297	* @param enmShw The shadow paging mode.
3298	* @param enmGst The guest paging mode.
3299	*/
3300	DECLINLINE(unsigned) pgmModeDataIndexByMode(PGMMODE enmShw, PGMMODE enmGst)
3301	{
3302	Assert(enmShw >= PGMMODE_32_BIT && enmShw <= PGMMODE_MAX);
3303	Assert(enmGst > PGMMODE_INVALID && enmGst < PGMMODE_MAX);
3304	return pgmModeDataIndex(pgmModeToType(enmShw), pgmModeToType(enmGst));
3305	}
3306
3307
3308	/**
3309	* Calculates the max data index.
3310	* @returns The number of entries in the paging data array.
3311	*/
3312	DECLINLINE(unsigned) pgmModeDataMaxIndex(void)
3313	{
3314	return pgmModeDataIndex(PGM_TYPE_MAX, PGM_TYPE_AMD64) + 1;
3315	}
3316
3317
3318	/**
3319	* Initializes the paging mode data kept in PGM::paModeData.
3320	*
3321	* @param pVM The VM handle.
3322	* @param fResolveGCAndR0 Indicate whether or not GC and Ring-0 symbols can be resolved now.
3323	* This is used early in the init process to avoid trouble with PDM
3324	* not being initialized yet.
3325	*/
3326	static int pgmR3ModeDataInit(PVM pVM, bool fResolveGCAndR0)
3327	{
3328	PPGMMODEDATA pModeData;
3329	int rc;
3330
3331	/*
3332	* Allocate the array on the first call.
3333	*/
3334	if (!pVM->pgm.s.paModeData)
3335	{
3336	pVM->pgm.s.paModeData = (PPGMMODEDATA)MMR3HeapAllocZ(pVM, MM_TAG_PGM, sizeof(PGMMODEDATA) * pgmModeDataMaxIndex());
3337	AssertReturn(pVM->pgm.s.paModeData, VERR_NO_MEMORY);
3338	}
3339
3340	/*
3341	* Initialize the array entries.
3342	*/
3343	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_32BIT, PGM_TYPE_REAL)];
3344	pModeData->uShwType = PGM_TYPE_32BIT;
3345	pModeData->uGstType = PGM_TYPE_REAL;
3346	rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3347	rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3348	rc = PGM_BTH_NAME_32BIT_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3349
3350	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_32BIT, PGMMODE_PROTECTED)];
3351	pModeData->uShwType = PGM_TYPE_32BIT;
3352	pModeData->uGstType = PGM_TYPE_PROT;
3353	rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3354	rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3355	rc = PGM_BTH_NAME_32BIT_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3356
3357	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_32BIT, PGM_TYPE_32BIT)];
3358	pModeData->uShwType = PGM_TYPE_32BIT;
3359	pModeData->uGstType = PGM_TYPE_32BIT;
3360	rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3361	rc = PGM_GST_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3362	rc = PGM_BTH_NAME_32BIT_32BIT(InitData)(pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3363
3364	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_REAL)];
3365	pModeData->uShwType = PGM_TYPE_PAE;
3366	pModeData->uGstType = PGM_TYPE_REAL;
3367	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3368	rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3369	rc = PGM_BTH_NAME_PAE_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3370
3371	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_PROT)];
3372	pModeData->uShwType = PGM_TYPE_PAE;
3373	pModeData->uGstType = PGM_TYPE_PROT;
3374	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3375	rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3376	rc = PGM_BTH_NAME_PAE_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3377
3378	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_32BIT)];
3379	pModeData->uShwType = PGM_TYPE_PAE;
3380	pModeData->uGstType = PGM_TYPE_32BIT;
3381	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3382	rc = PGM_GST_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3383	rc = PGM_BTH_NAME_PAE_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3384
3385	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_PAE)];
3386	pModeData->uShwType = PGM_TYPE_PAE;
3387	pModeData->uGstType = PGM_TYPE_PAE;
3388	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3389	rc = PGM_GST_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3390	rc = PGM_BTH_NAME_PAE_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3391
3392	#ifdef VBOX_WITH_64_BITS_GUESTS
3393	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_AMD64, PGM_TYPE_AMD64)];
3394	pModeData->uShwType = PGM_TYPE_AMD64;
3395	pModeData->uGstType = PGM_TYPE_AMD64;
3396	rc = PGM_SHW_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3397	rc = PGM_GST_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3398	rc = PGM_BTH_NAME_AMD64_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3399	#endif
3400
3401	/* The nested paging mode. */
3402	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_REAL)];
3403	pModeData->uShwType = PGM_TYPE_NESTED;
3404	pModeData->uGstType = PGM_TYPE_REAL;
3405	rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3406	rc = PGM_BTH_NAME_NESTED_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3407
3408	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGMMODE_PROTECTED)];
3409	pModeData->uShwType = PGM_TYPE_NESTED;
3410	pModeData->uGstType = PGM_TYPE_PROT;
3411	rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3412	rc = PGM_BTH_NAME_NESTED_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3413
3414	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_32BIT)];
3415	pModeData->uShwType = PGM_TYPE_NESTED;
3416	pModeData->uGstType = PGM_TYPE_32BIT;
3417	rc = PGM_GST_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3418	rc = PGM_BTH_NAME_NESTED_32BIT(InitData)(pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3419
3420	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_PAE)];
3421	pModeData->uShwType = PGM_TYPE_NESTED;
3422	pModeData->uGstType = PGM_TYPE_PAE;
3423	rc = PGM_GST_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3424	rc = PGM_BTH_NAME_NESTED_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3425
3426	#ifdef VBOX_WITH_64_BITS_GUESTS
3427	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_AMD64)];
3428	pModeData->uShwType = PGM_TYPE_NESTED;
3429	pModeData->uGstType = PGM_TYPE_AMD64;
3430	rc = PGM_GST_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3431	rc = PGM_BTH_NAME_NESTED_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3432	#endif
3433
3434	/* The shadow part of the nested callback mode depends on the host paging mode (AMD-V only). */
3435	switch (pVM->pgm.s.enmHostMode)
3436	{
3437	#if HC_ARCH_BITS == 32
3438	case SUPPAGINGMODE_32_BIT:
3439	case SUPPAGINGMODE_32_BIT_GLOBAL:
3440	for (unsigned i = PGM_TYPE_REAL; i <= PGM_TYPE_PAE; i++)
3441	{
3442	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, i)];
3443	rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3444	}
3445	# ifdef VBOX_WITH_64_BITS_GUESTS
3446	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_AMD64)];
3447	rc = PGM_SHW_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3448	# endif
3449	break;
3450
3451	case SUPPAGINGMODE_PAE:
3452	case SUPPAGINGMODE_PAE_NX:
3453	case SUPPAGINGMODE_PAE_GLOBAL:
3454	case SUPPAGINGMODE_PAE_GLOBAL_NX:
3455	for (unsigned i = PGM_TYPE_REAL; i <= PGM_TYPE_PAE; i++)
3456	{
3457	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, i)];
3458	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3459	}
3460	# ifdef VBOX_WITH_64_BITS_GUESTS
3461	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_AMD64)];
3462	rc = PGM_SHW_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3463	# endif
3464	break;
3465	#endif /* HC_ARCH_BITS == 32 */
3466
3467	#if HC_ARCH_BITS == 64 \|\| defined(RT_OS_DARWIN)
3468	case SUPPAGINGMODE_AMD64:
3469	case SUPPAGINGMODE_AMD64_GLOBAL:
3470	case SUPPAGINGMODE_AMD64_NX:
3471	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
3472	# ifdef VBOX_WITH_64_BITS_GUESTS
3473	for (unsigned i = PGM_TYPE_REAL; i <= PGM_TYPE_AMD64; i++)
3474	# else
3475	for (unsigned i = PGM_TYPE_REAL; i <= PGM_TYPE_PAE; i++)
3476	# endif
3477	{
3478	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, i)];
3479	rc = PGM_SHW_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3480	}
3481	break;
3482	#endif /* HC_ARCH_BITS == 64 \|\| RT_OS_DARWIN */
3483
3484	default:
3485	AssertFailed();
3486	break;
3487	}
3488
3489	/* Extended paging (EPT) / Intel VT-x */
3490	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_REAL)];
3491	pModeData->uShwType = PGM_TYPE_EPT;
3492	pModeData->uGstType = PGM_TYPE_REAL;
3493	rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3494	rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3495	rc = PGM_BTH_NAME_EPT_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3496
3497	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_PROT)];
3498	pModeData->uShwType = PGM_TYPE_EPT;
3499	pModeData->uGstType = PGM_TYPE_PROT;
3500	rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3501	rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3502	rc = PGM_BTH_NAME_EPT_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3503
3504	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_32BIT)];
3505	pModeData->uShwType = PGM_TYPE_EPT;
3506	pModeData->uGstType = PGM_TYPE_32BIT;
3507	rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3508	rc = PGM_GST_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3509	rc = PGM_BTH_NAME_EPT_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3510
3511	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_PAE)];
3512	pModeData->uShwType = PGM_TYPE_EPT;
3513	pModeData->uGstType = PGM_TYPE_PAE;
3514	rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3515	rc = PGM_GST_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3516	rc = PGM_BTH_NAME_EPT_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3517
3518	#ifdef VBOX_WITH_64_BITS_GUESTS
3519	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_AMD64)];
3520	pModeData->uShwType = PGM_TYPE_EPT;
3521	pModeData->uGstType = PGM_TYPE_AMD64;
3522	rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3523	rc = PGM_GST_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3524	rc = PGM_BTH_NAME_EPT_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3525	#endif
3526	return VINF_SUCCESS;
3527	}
3528
3529
3530	/**
3531	* Switch to different (or relocated in the relocate case) mode data.
3532	*
3533	* @param pVM The VM handle.
3534	* @param pVCpu The VMCPU to operate on.
3535	* @param enmShw The the shadow paging mode.
3536	* @param enmGst The the guest paging mode.
3537	*/
3538	static void pgmR3ModeDataSwitch(PVM pVM, PVMCPU pVCpu, PGMMODE enmShw, PGMMODE enmGst)
3539	{
3540	PPGMMODEDATA pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndexByMode(enmShw, enmGst)];
3541
3542	Assert(pModeData->uGstType == pgmModeToType(enmGst));
3543	Assert(pModeData->uShwType == pgmModeToType(enmShw));
3544
3545	/* shadow */
3546	pVCpu->pgm.s.pfnR3ShwRelocate = pModeData->pfnR3ShwRelocate;
3547	pVCpu->pgm.s.pfnR3ShwExit = pModeData->pfnR3ShwExit;
3548	pVCpu->pgm.s.pfnR3ShwGetPage = pModeData->pfnR3ShwGetPage;
3549	Assert(pVCpu->pgm.s.pfnR3ShwGetPage);
3550	pVCpu->pgm.s.pfnR3ShwModifyPage = pModeData->pfnR3ShwModifyPage;
3551
3552	pVCpu->pgm.s.pfnRCShwGetPage = pModeData->pfnRCShwGetPage;
3553	pVCpu->pgm.s.pfnRCShwModifyPage = pModeData->pfnRCShwModifyPage;
3554
3555	pVCpu->pgm.s.pfnR0ShwGetPage = pModeData->pfnR0ShwGetPage;
3556	pVCpu->pgm.s.pfnR0ShwModifyPage = pModeData->pfnR0ShwModifyPage;
3557
3558
3559	/* guest */
3560	pVCpu->pgm.s.pfnR3GstRelocate = pModeData->pfnR3GstRelocate;
3561	pVCpu->pgm.s.pfnR3GstExit = pModeData->pfnR3GstExit;
3562	pVCpu->pgm.s.pfnR3GstGetPage = pModeData->pfnR3GstGetPage;
3563	Assert(pVCpu->pgm.s.pfnR3GstGetPage);
3564	pVCpu->pgm.s.pfnR3GstModifyPage = pModeData->pfnR3GstModifyPage;
3565	pVCpu->pgm.s.pfnR3GstGetPDE = pModeData->pfnR3GstGetPDE;
3566	pVCpu->pgm.s.pfnRCGstGetPage = pModeData->pfnRCGstGetPage;
3567	pVCpu->pgm.s.pfnRCGstModifyPage = pModeData->pfnRCGstModifyPage;
3568	pVCpu->pgm.s.pfnRCGstGetPDE = pModeData->pfnRCGstGetPDE;
3569	pVCpu->pgm.s.pfnR0GstGetPage = pModeData->pfnR0GstGetPage;
3570	pVCpu->pgm.s.pfnR0GstModifyPage = pModeData->pfnR0GstModifyPage;
3571	pVCpu->pgm.s.pfnR0GstGetPDE = pModeData->pfnR0GstGetPDE;
3572
3573	/* both */
3574	pVCpu->pgm.s.pfnR3BthRelocate = pModeData->pfnR3BthRelocate;
3575	pVCpu->pgm.s.pfnR3BthInvalidatePage = pModeData->pfnR3BthInvalidatePage;
3576	pVCpu->pgm.s.pfnR3BthSyncCR3 = pModeData->pfnR3BthSyncCR3;
3577	Assert(pVCpu->pgm.s.pfnR3BthSyncCR3);
3578	pVCpu->pgm.s.pfnR3BthSyncPage = pModeData->pfnR3BthSyncPage;
3579	pVCpu->pgm.s.pfnR3BthPrefetchPage = pModeData->pfnR3BthPrefetchPage;
3580	pVCpu->pgm.s.pfnR3BthVerifyAccessSyncPage = pModeData->pfnR3BthVerifyAccessSyncPage;
3581	#ifdef VBOX_STRICT
3582	pVCpu->pgm.s.pfnR3BthAssertCR3 = pModeData->pfnR3BthAssertCR3;
3583	#endif
3584	pVCpu->pgm.s.pfnR3BthMapCR3 = pModeData->pfnR3BthMapCR3;
3585	pVCpu->pgm.s.pfnR3BthUnmapCR3 = pModeData->pfnR3BthUnmapCR3;
3586
3587	pVCpu->pgm.s.pfnRCBthTrap0eHandler = pModeData->pfnRCBthTrap0eHandler;
3588	pVCpu->pgm.s.pfnRCBthInvalidatePage = pModeData->pfnRCBthInvalidatePage;
3589	pVCpu->pgm.s.pfnRCBthSyncCR3 = pModeData->pfnRCBthSyncCR3;
3590	pVCpu->pgm.s.pfnRCBthSyncPage = pModeData->pfnRCBthSyncPage;
3591	pVCpu->pgm.s.pfnRCBthPrefetchPage = pModeData->pfnRCBthPrefetchPage;
3592	pVCpu->pgm.s.pfnRCBthVerifyAccessSyncPage = pModeData->pfnRCBthVerifyAccessSyncPage;
3593	#ifdef VBOX_STRICT
3594	pVCpu->pgm.s.pfnRCBthAssertCR3 = pModeData->pfnRCBthAssertCR3;
3595	#endif
3596	pVCpu->pgm.s.pfnRCBthMapCR3 = pModeData->pfnRCBthMapCR3;
3597	pVCpu->pgm.s.pfnRCBthUnmapCR3 = pModeData->pfnRCBthUnmapCR3;
3598
3599	pVCpu->pgm.s.pfnR0BthTrap0eHandler = pModeData->pfnR0BthTrap0eHandler;
3600	pVCpu->pgm.s.pfnR0BthInvalidatePage = pModeData->pfnR0BthInvalidatePage;
3601	pVCpu->pgm.s.pfnR0BthSyncCR3 = pModeData->pfnR0BthSyncCR3;
3602	pVCpu->pgm.s.pfnR0BthSyncPage = pModeData->pfnR0BthSyncPage;
3603	pVCpu->pgm.s.pfnR0BthPrefetchPage = pModeData->pfnR0BthPrefetchPage;
3604	pVCpu->pgm.s.pfnR0BthVerifyAccessSyncPage = pModeData->pfnR0BthVerifyAccessSyncPage;
3605	#ifdef VBOX_STRICT
3606	pVCpu->pgm.s.pfnR0BthAssertCR3 = pModeData->pfnR0BthAssertCR3;
3607	#endif
3608	pVCpu->pgm.s.pfnR0BthMapCR3 = pModeData->pfnR0BthMapCR3;
3609	pVCpu->pgm.s.pfnR0BthUnmapCR3 = pModeData->pfnR0BthUnmapCR3;
3610	}
3611
3612
3613	/**
3614	* Calculates the shadow paging mode.
3615	*
3616	* @returns The shadow paging mode.
3617	* @param pVM VM handle.
3618	* @param enmGuestMode The guest mode.
3619	* @param enmHostMode The host mode.
3620	* @param enmShadowMode The current shadow mode.
3621	* @param penmSwitcher Where to store the switcher to use.
3622	* VMMSWITCHER_INVALID means no change.
3623	*/
3624	static PGMMODE pgmR3CalcShadowMode(PVM pVM, PGMMODE enmGuestMode, SUPPAGINGMODE enmHostMode, PGMMODE enmShadowMode, VMMSWITCHER *penmSwitcher)
3625	{
3626	VMMSWITCHER enmSwitcher = VMMSWITCHER_INVALID;
3627	switch (enmGuestMode)
3628	{
3629	/*
3630	* When switching to real or protected mode we don't change
3631	* anything since it's likely that we'll switch back pretty soon.
3632	*
3633	* During pgmR3InitPaging we'll end up here with PGMMODE_INVALID
3634	* and is supposed to determine which shadow paging and switcher to
3635	* use during init.
3636	*/
3637	case PGMMODE_REAL:
3638	case PGMMODE_PROTECTED:
3639	if ( enmShadowMode != PGMMODE_INVALID
3640	&& !HWACCMIsEnabled(pVM) /* always switch in hwaccm mode! */)
3641	break; /* (no change) */
3642
3643	switch (enmHostMode)
3644	{
3645	case SUPPAGINGMODE_32_BIT:
3646	case SUPPAGINGMODE_32_BIT_GLOBAL:
3647	enmShadowMode = PGMMODE_32_BIT;
3648	enmSwitcher = VMMSWITCHER_32_TO_32;
3649	break;
3650
3651	case SUPPAGINGMODE_PAE:
3652	case SUPPAGINGMODE_PAE_NX:
3653	case SUPPAGINGMODE_PAE_GLOBAL:
3654	case SUPPAGINGMODE_PAE_GLOBAL_NX:
3655	enmShadowMode = PGMMODE_PAE;
3656	enmSwitcher = VMMSWITCHER_PAE_TO_PAE;
3657	#ifdef DEBUG_bird
3658	if (RTEnvExist("VBOX_32BIT"))
3659	{
3660	enmShadowMode = PGMMODE_32_BIT;
3661	enmSwitcher = VMMSWITCHER_PAE_TO_32;
3662	}
3663	#endif
3664	break;
3665
3666	case SUPPAGINGMODE_AMD64:
3667	case SUPPAGINGMODE_AMD64_GLOBAL:
3668	case SUPPAGINGMODE_AMD64_NX:
3669	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
3670	enmShadowMode = PGMMODE_PAE;
3671	enmSwitcher = VMMSWITCHER_AMD64_TO_PAE;
3672	#ifdef DEBUG_bird
3673	if (RTEnvExist("VBOX_32BIT"))
3674	{
3675	enmShadowMode = PGMMODE_32_BIT;
3676	enmSwitcher = VMMSWITCHER_AMD64_TO_32;
3677	}
3678	#endif
3679	break;
3680
3681	default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
3682	}
3683	break;
3684
3685	case PGMMODE_32_BIT:
3686	switch (enmHostMode)
3687	{
3688	case SUPPAGINGMODE_32_BIT:
3689	case SUPPAGINGMODE_32_BIT_GLOBAL:
3690	enmShadowMode = PGMMODE_32_BIT;
3691	enmSwitcher = VMMSWITCHER_32_TO_32;
3692	break;
3693
3694	case SUPPAGINGMODE_PAE:
3695	case SUPPAGINGMODE_PAE_NX:
3696	case SUPPAGINGMODE_PAE_GLOBAL:
3697	case SUPPAGINGMODE_PAE_GLOBAL_NX:
3698	enmShadowMode = PGMMODE_PAE;
3699	enmSwitcher = VMMSWITCHER_PAE_TO_PAE;
3700	#ifdef DEBUG_bird
3701	if (RTEnvExist("VBOX_32BIT"))
3702	{
3703	enmShadowMode = PGMMODE_32_BIT;
3704	enmSwitcher = VMMSWITCHER_PAE_TO_32;
3705	}
3706	#endif
3707	break;
3708
3709	case SUPPAGINGMODE_AMD64:
3710	case SUPPAGINGMODE_AMD64_GLOBAL:
3711	case SUPPAGINGMODE_AMD64_NX:
3712	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
3713	enmShadowMode = PGMMODE_PAE;
3714	enmSwitcher = VMMSWITCHER_AMD64_TO_PAE;
3715	#ifdef DEBUG_bird
3716	if (RTEnvExist("VBOX_32BIT"))
3717	{
3718	enmShadowMode = PGMMODE_32_BIT;
3719	enmSwitcher = VMMSWITCHER_AMD64_TO_32;
3720	}
3721	#endif
3722	break;
3723
3724	default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
3725	}
3726	break;
3727
3728	case PGMMODE_PAE:
3729	case PGMMODE_PAE_NX: /** @todo This might require more switchers and guest+both modes. */
3730	switch (enmHostMode)
3731	{
3732	case SUPPAGINGMODE_32_BIT:
3733	case SUPPAGINGMODE_32_BIT_GLOBAL:
3734	enmShadowMode = PGMMODE_PAE;
3735	enmSwitcher = VMMSWITCHER_32_TO_PAE;
3736	break;
3737
3738	case SUPPAGINGMODE_PAE:
3739	case SUPPAGINGMODE_PAE_NX:
3740	case SUPPAGINGMODE_PAE_GLOBAL:
3741	case SUPPAGINGMODE_PAE_GLOBAL_NX:
3742	enmShadowMode = PGMMODE_PAE;
3743	enmSwitcher = VMMSWITCHER_PAE_TO_PAE;
3744	break;
3745
3746	case SUPPAGINGMODE_AMD64:
3747	case SUPPAGINGMODE_AMD64_GLOBAL:
3748	case SUPPAGINGMODE_AMD64_NX:
3749	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
3750	enmShadowMode = PGMMODE_PAE;
3751	enmSwitcher = VMMSWITCHER_AMD64_TO_PAE;
3752	break;
3753
3754	default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
3755	}
3756	break;
3757
3758	case PGMMODE_AMD64:
3759	case PGMMODE_AMD64_NX:
3760	switch (enmHostMode)
3761	{
3762	case SUPPAGINGMODE_32_BIT:
3763	case SUPPAGINGMODE_32_BIT_GLOBAL:
3764	enmShadowMode = PGMMODE_AMD64;
3765	enmSwitcher = VMMSWITCHER_32_TO_AMD64;
3766	break;
3767
3768	case SUPPAGINGMODE_PAE:
3769	case SUPPAGINGMODE_PAE_NX:
3770	case SUPPAGINGMODE_PAE_GLOBAL:
3771	case SUPPAGINGMODE_PAE_GLOBAL_NX:
3772	enmShadowMode = PGMMODE_AMD64;
3773	enmSwitcher = VMMSWITCHER_PAE_TO_AMD64;
3774	break;
3775
3776	case SUPPAGINGMODE_AMD64:
3777	case SUPPAGINGMODE_AMD64_GLOBAL:
3778	case SUPPAGINGMODE_AMD64_NX:
3779	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
3780	enmShadowMode = PGMMODE_AMD64;
3781	enmSwitcher = VMMSWITCHER_AMD64_TO_AMD64;
3782	break;
3783
3784	default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
3785	}
3786	break;
3787
3788
3789	default:
3790	AssertReleaseMsgFailed(("enmGuestMode=%d\n", enmGuestMode));
3791	return PGMMODE_INVALID;
3792	}
3793	/* Override the shadow mode is nested paging is active. */
3794	if (HWACCMIsNestedPagingActive(pVM))
3795	enmShadowMode = HWACCMGetShwPagingMode(pVM);
3796
3797	*penmSwitcher = enmSwitcher;
3798	return enmShadowMode;
3799	}
3800
3801
3802	/**
3803	* Performs the actual mode change.
3804	* This is called by PGMChangeMode and pgmR3InitPaging().
3805	*
3806	* @returns VBox status code. May suspend or power off the VM on error, but this
3807	* will trigger using FFs and not status codes.
3808	*
3809	* @param pVM VM handle.
3810	* @param pVCpu The VMCPU to operate on.
3811	* @param enmGuestMode The new guest mode. This is assumed to be different from
3812	* the current mode.
3813	*/
3814	VMMR3DECL(int) PGMR3ChangeMode(PVM pVM, PVMCPU pVCpu, PGMMODE enmGuestMode)
3815	{
3816	Log(("PGMR3ChangeMode: Guest mode: %s -> %s\n", PGMGetModeName(pVCpu->pgm.s.enmGuestMode), PGMGetModeName(enmGuestMode)));
3817	STAM_REL_COUNTER_INC(&pVCpu->pgm.s.cGuestModeChanges);
3818
3819	/*
3820	* Calc the shadow mode and switcher.
3821	*/
3822	VMMSWITCHER enmSwitcher;
3823	PGMMODE enmShadowMode = pgmR3CalcShadowMode(pVM, enmGuestMode, pVM->pgm.s.enmHostMode, pVCpu->pgm.s.enmShadowMode, &enmSwitcher);
3824	if (enmSwitcher != VMMSWITCHER_INVALID)
3825	{
3826	/*
3827	* Select new switcher.
3828	*/
3829	int rc = VMMR3SelectSwitcher(pVM, enmSwitcher);
3830	if (RT_FAILURE(rc))
3831	{
3832	AssertReleaseMsgFailed(("VMMR3SelectSwitcher(%d) -> %Rrc\n", enmSwitcher, rc));
3833	return rc;
3834	}
3835	}
3836
3837	/*
3838	* Exit old mode(s).
3839	*/
3840	/* shadow */
3841	if (enmShadowMode != pVCpu->pgm.s.enmShadowMode)
3842	{
3843	LogFlow(("PGMR3ChangeMode: Shadow mode: %s -> %s\n", PGMGetModeName(pVCpu->pgm.s.enmShadowMode), PGMGetModeName(enmShadowMode)));
3844	if (PGM_SHW_PFN(Exit, pVCpu))
3845	{
3846	int rc = PGM_SHW_PFN(Exit, pVCpu)(pVCpu);
3847	if (RT_FAILURE(rc))
3848	{
3849	AssertMsgFailed(("Exit failed for shadow mode %d: %Rrc\n", pVCpu->pgm.s.enmShadowMode, rc));
3850	return rc;
3851	}
3852	}
3853
3854	}
3855	else
3856	LogFlow(("PGMR3ChangeMode: Shadow mode remains: %s\n", PGMGetModeName(pVCpu->pgm.s.enmShadowMode)));
3857
3858	/* guest */
3859	if (PGM_GST_PFN(Exit, pVCpu))
3860	{
3861	int rc = PGM_GST_PFN(Exit, pVCpu)(pVCpu);
3862	if (RT_FAILURE(rc))
3863	{
3864	AssertMsgFailed(("Exit failed for guest mode %d: %Rrc\n", pVCpu->pgm.s.enmGuestMode, rc));
3865	return rc;
3866	}
3867	}
3868
3869	/*
3870	* Load new paging mode data.
3871	*/
3872	pgmR3ModeDataSwitch(pVM, pVCpu, enmShadowMode, enmGuestMode);
3873
3874	/*
3875	* Enter new shadow mode (if changed).
3876	*/
3877	if (enmShadowMode != pVCpu->pgm.s.enmShadowMode)
3878	{
3879	int rc;
3880	pVCpu->pgm.s.enmShadowMode = enmShadowMode;
3881	switch (enmShadowMode)
3882	{
3883	case PGMMODE_32_BIT:
3884	rc = PGM_SHW_NAME_32BIT(Enter)(pVCpu);
3885	break;
3886	case PGMMODE_PAE:
3887	case PGMMODE_PAE_NX:
3888	rc = PGM_SHW_NAME_PAE(Enter)(pVCpu);
3889	break;
3890	case PGMMODE_AMD64:
3891	case PGMMODE_AMD64_NX:
3892	rc = PGM_SHW_NAME_AMD64(Enter)(pVCpu);
3893	break;
3894	case PGMMODE_NESTED:
3895	rc = PGM_SHW_NAME_NESTED(Enter)(pVCpu);
3896	break;
3897	case PGMMODE_EPT:
3898	rc = PGM_SHW_NAME_EPT(Enter)(pVCpu);
3899	break;
3900	case PGMMODE_REAL:
3901	case PGMMODE_PROTECTED:
3902	default:
3903	AssertReleaseMsgFailed(("enmShadowMode=%d\n", enmShadowMode));
3904	return VERR_INTERNAL_ERROR;
3905	}
3906	if (RT_FAILURE(rc))
3907	{
3908	AssertReleaseMsgFailed(("Entering enmShadowMode=%d failed: %Rrc\n", enmShadowMode, rc));
3909	pVCpu->pgm.s.enmShadowMode = PGMMODE_INVALID;
3910	return rc;
3911	}
3912	}
3913
3914	/*
3915	* Always flag the necessary updates
3916	*/
3917	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
3918
3919	/*
3920	* Enter the new guest and shadow+guest modes.
3921	*/
3922	int rc = -1;
3923	int rc2 = -1;
3924	RTGCPHYS GCPhysCR3 = NIL_RTGCPHYS;
3925	pVCpu->pgm.s.enmGuestMode = enmGuestMode;
3926	switch (enmGuestMode)
3927	{
3928	case PGMMODE_REAL:
3929	rc = PGM_GST_NAME_REAL(Enter)(pVCpu, NIL_RTGCPHYS);
3930	switch (pVCpu->pgm.s.enmShadowMode)
3931	{
3932	case PGMMODE_32_BIT:
3933	rc2 = PGM_BTH_NAME_32BIT_REAL(Enter)(pVCpu, NIL_RTGCPHYS);
3934	break;
3935	case PGMMODE_PAE:
3936	case PGMMODE_PAE_NX:
3937	rc2 = PGM_BTH_NAME_PAE_REAL(Enter)(pVCpu, NIL_RTGCPHYS);
3938	break;
3939	case PGMMODE_NESTED:
3940	rc2 = PGM_BTH_NAME_NESTED_REAL(Enter)(pVCpu, NIL_RTGCPHYS);
3941	break;
3942	case PGMMODE_EPT:
3943	rc2 = PGM_BTH_NAME_EPT_REAL(Enter)(pVCpu, NIL_RTGCPHYS);
3944	break;
3945	case PGMMODE_AMD64:
3946	case PGMMODE_AMD64_NX:
3947	AssertMsgFailed(("Should use PAE shadow mode!\n"));
3948	default: AssertFailed(); break;
3949	}
3950	break;
3951
3952	case PGMMODE_PROTECTED:
3953	rc = PGM_GST_NAME_PROT(Enter)(pVCpu, NIL_RTGCPHYS);
3954	switch (pVCpu->pgm.s.enmShadowMode)
3955	{
3956	case PGMMODE_32_BIT:
3957	rc2 = PGM_BTH_NAME_32BIT_PROT(Enter)(pVCpu, NIL_RTGCPHYS);
3958	break;
3959	case PGMMODE_PAE:
3960	case PGMMODE_PAE_NX:
3961	rc2 = PGM_BTH_NAME_PAE_PROT(Enter)(pVCpu, NIL_RTGCPHYS);
3962	break;
3963	case PGMMODE_NESTED:
3964	rc2 = PGM_BTH_NAME_NESTED_PROT(Enter)(pVCpu, NIL_RTGCPHYS);
3965	break;
3966	case PGMMODE_EPT:
3967	rc2 = PGM_BTH_NAME_EPT_PROT(Enter)(pVCpu, NIL_RTGCPHYS);
3968	break;
3969	case PGMMODE_AMD64:
3970	case PGMMODE_AMD64_NX:
3971	AssertMsgFailed(("Should use PAE shadow mode!\n"));
3972	default: AssertFailed(); break;
3973	}
3974	break;
3975
3976	case PGMMODE_32_BIT:
3977	GCPhysCR3 = CPUMGetGuestCR3(pVCpu) & X86_CR3_PAGE_MASK;
3978	rc = PGM_GST_NAME_32BIT(Enter)(pVCpu, GCPhysCR3);
3979	switch (pVCpu->pgm.s.enmShadowMode)
3980	{
3981	case PGMMODE_32_BIT:
3982	rc2 = PGM_BTH_NAME_32BIT_32BIT(Enter)(pVCpu, GCPhysCR3);
3983	break;
3984	case PGMMODE_PAE:
3985	case PGMMODE_PAE_NX:
3986	rc2 = PGM_BTH_NAME_PAE_32BIT(Enter)(pVCpu, GCPhysCR3);
3987	break;
3988	case PGMMODE_NESTED:
3989	rc2 = PGM_BTH_NAME_NESTED_32BIT(Enter)(pVCpu, GCPhysCR3);
3990	break;
3991	case PGMMODE_EPT:
3992	rc2 = PGM_BTH_NAME_EPT_32BIT(Enter)(pVCpu, GCPhysCR3);
3993	break;
3994	case PGMMODE_AMD64:
3995	case PGMMODE_AMD64_NX:
3996	AssertMsgFailed(("Should use PAE shadow mode!\n"));
3997	default: AssertFailed(); break;
3998	}
3999	break;
4000
4001	case PGMMODE_PAE_NX:
4002	case PGMMODE_PAE:
4003	{
4004	uint32_t u32Dummy, u32Features;
4005
4006	CPUMGetGuestCpuId(pVCpu, 1, &u32Dummy, &u32Dummy, &u32Dummy, &u32Features);
4007	if (!(u32Features & X86_CPUID_FEATURE_EDX_PAE))
4008	return VMSetRuntimeError(pVM, VMSETRTERR_FLAGS_FATAL, "PAEmode",
4009	N_("The guest is trying to switch to the PAE mode which is currently disabled by default in VirtualBox. PAE support can be enabled using the VM settings (General/Advanced)"));
4010
4011	GCPhysCR3 = CPUMGetGuestCR3(pVCpu) & X86_CR3_PAE_PAGE_MASK;
4012	rc = PGM_GST_NAME_PAE(Enter)(pVCpu, GCPhysCR3);
4013	switch (pVCpu->pgm.s.enmShadowMode)
4014	{
4015	case PGMMODE_PAE:
4016	case PGMMODE_PAE_NX:
4017	rc2 = PGM_BTH_NAME_PAE_PAE(Enter)(pVCpu, GCPhysCR3);
4018	break;
4019	case PGMMODE_NESTED:
4020	rc2 = PGM_BTH_NAME_NESTED_PAE(Enter)(pVCpu, GCPhysCR3);
4021	break;
4022	case PGMMODE_EPT:
4023	rc2 = PGM_BTH_NAME_EPT_PAE(Enter)(pVCpu, GCPhysCR3);
4024	break;
4025	case PGMMODE_32_BIT:
4026	case PGMMODE_AMD64:
4027	case PGMMODE_AMD64_NX:
4028	AssertMsgFailed(("Should use PAE shadow mode!\n"));
4029	default: AssertFailed(); break;
4030	}
4031	break;
4032	}
4033
4034	#ifdef VBOX_WITH_64_BITS_GUESTS
4035	case PGMMODE_AMD64_NX:
4036	case PGMMODE_AMD64:
4037	GCPhysCR3 = CPUMGetGuestCR3(pVCpu) & UINT64_C(0xfffffffffffff000); /** @todo define this mask! */
4038	rc = PGM_GST_NAME_AMD64(Enter)(pVCpu, GCPhysCR3);
4039	switch (pVCpu->pgm.s.enmShadowMode)
4040	{
4041	case PGMMODE_AMD64:
4042	case PGMMODE_AMD64_NX:
4043	rc2 = PGM_BTH_NAME_AMD64_AMD64(Enter)(pVCpu, GCPhysCR3);
4044	break;
4045	case PGMMODE_NESTED:
4046	rc2 = PGM_BTH_NAME_NESTED_AMD64(Enter)(pVCpu, GCPhysCR3);
4047	break;
4048	case PGMMODE_EPT:
4049	rc2 = PGM_BTH_NAME_EPT_AMD64(Enter)(pVCpu, GCPhysCR3);
4050	break;
4051	case PGMMODE_32_BIT:
4052	case PGMMODE_PAE:
4053	case PGMMODE_PAE_NX:
4054	AssertMsgFailed(("Should use AMD64 shadow mode!\n"));
4055	default: AssertFailed(); break;
4056	}
4057	break;
4058	#endif
4059
4060	default:
4061	AssertReleaseMsgFailed(("enmGuestMode=%d\n", enmGuestMode));
4062	rc = VERR_NOT_IMPLEMENTED;
4063	break;
4064	}
4065
4066	/* status codes. */
4067	AssertRC(rc);
4068	AssertRC(rc2);
4069	if (RT_SUCCESS(rc))
4070	{
4071	rc = rc2;
4072	if (RT_SUCCESS(rc)) /* no informational status codes. */
4073	rc = VINF_SUCCESS;
4074	}
4075
4076	/* Notify HWACCM as well. */
4077	HWACCMR3PagingModeChanged(pVM, pVCpu, pVCpu->pgm.s.enmShadowMode, pVCpu->pgm.s.enmGuestMode);
4078	return rc;
4079	}
4080
4081	/**
4082	* Release the pgm lock if owned by the current VCPU
4083	*
4084	* @param pVM The VM to operate on.
4085	*/
4086	VMMR3DECL(void) PGMR3ReleaseOwnedLocks(PVM pVM)
4087	{
4088	while (PDMCritSectIsOwner(&pVM->pgm.s.CritSect))
4089	PDMCritSectLeave(&pVM->pgm.s.CritSect);
4090	}
4091
4092	/**
4093	* Called by pgmPoolFlushAllInt prior to flushing the pool.
4094	*
4095	* @returns VBox status code, fully asserted.
4096	* @param pVM The VM handle.
4097	* @param pVCpu The VMCPU to operate on.
4098	*/
4099	int pgmR3ExitShadowModeBeforePoolFlush(PVM pVM, PVMCPU pVCpu)
4100	{
4101	/* Unmap the old CR3 value before flushing everything. */
4102	int rc = PGM_BTH_PFN(UnmapCR3, pVCpu)(pVCpu);
4103	AssertRC(rc);
4104
4105	/* Exit the current shadow paging mode as well; nested paging and EPT use a root CR3 which will get flushed here. */
4106	rc = PGM_SHW_PFN(Exit, pVCpu)(pVCpu);
4107	AssertRC(rc);
4108	Assert(pVCpu->pgm.s.pShwPageCR3R3 == NULL);
4109	return rc;
4110	}
4111
4112
4113	/**
4114	* Called by pgmPoolFlushAllInt after flushing the pool.
4115	*
4116	* @returns VBox status code, fully asserted.
4117	* @param pVM The VM handle.
4118	* @param pVCpu The VMCPU to operate on.
4119	*/
4120	int pgmR3ReEnterShadowModeAfterPoolFlush(PVM pVM, PVMCPU pVCpu)
4121	{
4122	pVCpu->pgm.s.enmShadowMode = PGMMODE_INVALID;
4123	int rc = PGMR3ChangeMode(pVM, pVCpu, PGMGetGuestMode(pVCpu));
4124	Assert(VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
4125	AssertRCReturn(rc, rc);
4126	AssertRCSuccessReturn(rc, VERR_IPE_UNEXPECTED_INFO_STATUS);
4127
4128	Assert(pVCpu->pgm.s.pShwPageCR3R3 != NULL);
4129	AssertMsg( pVCpu->pgm.s.enmShadowMode >= PGMMODE_NESTED
4130	\|\| CPUMGetHyperCR3(pVCpu) == PGMGetHyperCR3(pVCpu),
4131	("%RHp != %RHp %s\n", (RTHCPHYS)CPUMGetHyperCR3(pVCpu), PGMGetHyperCR3(pVCpu), PGMGetModeName(pVCpu->pgm.s.enmShadowMode)));
4132	return rc;
4133	}
4134
4135
4136	/**
4137	* Dumps a PAE shadow page table.
4138	*
4139	* @returns VBox status code (VINF_SUCCESS).
4140	* @param pVM The VM handle.
4141	* @param pPT Pointer to the page table.
4142	* @param u64Address The virtual address of the page table starts.
4143	* @param fLongMode Set if this a long mode table; clear if it's a legacy mode table.
4144	* @param cMaxDepth The maxium depth.
4145	* @param pHlp Pointer to the output functions.
4146	*/
4147	static int pgmR3DumpHierarchyHCPaePT(PVM pVM, PX86PTPAE pPT, uint64_t u64Address, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
4148	{
4149	for (unsigned i = 0; i < RT_ELEMENTS(pPT->a); i++)
4150	{
4151	X86PTEPAE Pte = pPT->a[i];
4152	if (Pte.n.u1Present)
4153	{
4154	pHlp->pfnPrintf(pHlp,
4155	fLongMode /P R S A D G WT CD AT NX 4M a p ? /
4156	? "%016llx 3 \| P %c %c %c %c %c %s %s %s %s 4K %c%c%c %016llx\n"
4157	: "%08llx 2 \| P %c %c %c %c %c %s %s %s %s 4K %c%c%c %016llx\n",
4158	u64Address + ((uint64_t)i << X86_PT_PAE_SHIFT),
4159	Pte.n.u1Write ? 'W' : 'R',
4160	Pte.n.u1User ? 'U' : 'S',
4161	Pte.n.u1Accessed ? 'A' : '-',
4162	Pte.n.u1Dirty ? 'D' : '-',
4163	Pte.n.u1Global ? 'G' : '-',
4164	Pte.n.u1WriteThru ? "WT" : "--",
4165	Pte.n.u1CacheDisable? "CD" : "--",
4166	Pte.n.u1PAT ? "AT" : "--",
4167	Pte.n.u1NoExecute ? "NX" : "--",
4168	Pte.u & PGM_PTFLAGS_TRACK_DIRTY ? 'd' : '-',
4169	Pte.u & RT_BIT(10) ? '1' : '0',
4170	Pte.u & PGM_PTFLAGS_CSAM_VALIDATED? 'v' : '-',
4171	Pte.u & X86_PTE_PAE_PG_MASK);
4172	}
4173	}
4174	return VINF_SUCCESS;
4175	}
4176
4177
4178	/**
4179	* Dumps a PAE shadow page directory table.
4180	*
4181	* @returns VBox status code (VINF_SUCCESS).
4182	* @param pVM The VM handle.
4183	* @param HCPhys The physical address of the page directory table.
4184	* @param u64Address The virtual address of the page table starts.
4185	* @param cr4 The CR4, PSE is currently used.
4186	* @param fLongMode Set if this a long mode table; clear if it's a legacy mode table.
4187	* @param cMaxDepth The maxium depth.
4188	* @param pHlp Pointer to the output functions.
4189	*/
4190	static int pgmR3DumpHierarchyHCPaePD(PVM pVM, RTHCPHYS HCPhys, uint64_t u64Address, uint32_t cr4, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
4191	{
4192	PX86PDPAE pPD = (PX86PDPAE)MMPagePhys2Page(pVM, HCPhys);
4193	if (!pPD)
4194	{
4195	pHlp->pfnPrintf(pHlp, "%0*llx error! Page directory at HCPhys=%RHp was not found in the page pool!\n",
4196	fLongMode ? 16 : 8, u64Address, HCPhys);
4197	return VERR_INVALID_PARAMETER;
4198	}
4199	const bool fBigPagesSupported = fLongMode \|\| !!(cr4 & X86_CR4_PSE);
4200
4201	int rc = VINF_SUCCESS;
4202	for (unsigned i = 0; i < RT_ELEMENTS(pPD->a); i++)
4203	{
4204	X86PDEPAE Pde = pPD->a[i];
4205	if (Pde.n.u1Present)
4206	{
4207	if (fBigPagesSupported && Pde.b.u1Size)
4208	pHlp->pfnPrintf(pHlp,
4209	fLongMode /P R S A D G WT CD AT NX 4M a p ? /
4210	? "%016llx 2 \| P %c %c %c %c %c %s %s %s %s 4M %c%c%c %016llx\n"
4211	: "%08llx 1 \| P %c %c %c %c %c %s %s %s %s 4M %c%c%c %016llx\n",
4212	u64Address + ((uint64_t)i << X86_PD_PAE_SHIFT),
4213	Pde.b.u1Write ? 'W' : 'R',
4214	Pde.b.u1User ? 'U' : 'S',
4215	Pde.b.u1Accessed ? 'A' : '-',
4216	Pde.b.u1Dirty ? 'D' : '-',
4217	Pde.b.u1Global ? 'G' : '-',
4218	Pde.b.u1WriteThru ? "WT" : "--",
4219	Pde.b.u1CacheDisable? "CD" : "--",
4220	Pde.b.u1PAT ? "AT" : "--",
4221	Pde.b.u1NoExecute ? "NX" : "--",
4222	Pde.u & RT_BIT_64(9) ? '1' : '0',
4223	Pde.u & PGM_PDFLAGS_MAPPING ? 'm' : '-',
4224	Pde.u & PGM_PDFLAGS_TRACK_DIRTY ? 'd' : '-',
4225	Pde.u & X86_PDE_PAE_PG_MASK);
4226	else
4227	{
4228	pHlp->pfnPrintf(pHlp,
4229	fLongMode /P R S A D G WT CD AT NX 4M a p ? /
4230	? "%016llx 2 \| P %c %c %c %c %c %s %s .. %s 4K %c%c%c %016llx\n"
4231	: "%08llx 1 \| P %c %c %c %c %c %s %s .. %s 4K %c%c%c %016llx\n",
4232	u64Address + ((uint64_t)i << X86_PD_PAE_SHIFT),
4233	Pde.n.u1Write ? 'W' : 'R',
4234	Pde.n.u1User ? 'U' : 'S',
4235	Pde.n.u1Accessed ? 'A' : '-',
4236	Pde.n.u1Reserved0 ? '?' : '.', /* ignored */
4237	Pde.n.u1Reserved1 ? '?' : '.', /* ignored */
4238	Pde.n.u1WriteThru ? "WT" : "--",
4239	Pde.n.u1CacheDisable? "CD" : "--",
4240	Pde.n.u1NoExecute ? "NX" : "--",
4241	Pde.u & RT_BIT_64(9) ? '1' : '0',
4242	Pde.u & PGM_PDFLAGS_MAPPING ? 'm' : '-',
4243	Pde.u & PGM_PDFLAGS_TRACK_DIRTY ? 'd' : '-',
4244	Pde.u & X86_PDE_PAE_PG_MASK);
4245	if (cMaxDepth >= 1)
4246	{
4247	/** @todo what about using the page pool for mapping PTs? */
4248	uint64_t u64AddressPT = u64Address + ((uint64_t)i << X86_PD_PAE_SHIFT);
4249	RTHCPHYS HCPhysPT = Pde.u & X86_PDE_PAE_PG_MASK;
4250	PX86PTPAE pPT = NULL;
4251	if (!(Pde.u & PGM_PDFLAGS_MAPPING))
4252	pPT = (PX86PTPAE)MMPagePhys2Page(pVM, HCPhysPT);
4253	else
4254	{
4255	for (PPGMMAPPING pMap = pVM->pgm.s.pMappingsR3; pMap; pMap = pMap->pNextR3)
4256	{
4257	uint64_t off = u64AddressPT - pMap->GCPtr;
4258	if (off < pMap->cb)
4259	{
4260	const int iPDE = (uint32_t)(off >> X86_PD_SHIFT);
4261	const int iSub = (int)((off >> X86_PD_PAE_SHIFT) & 1); /* MSC is a pain sometimes */
4262	if ((iSub ? pMap->aPTs[iPDE].HCPhysPaePT1 : pMap->aPTs[iPDE].HCPhysPaePT0) != HCPhysPT)
4263	pHlp->pfnPrintf(pHlp, "%0*llx error! Mapping error! PT %d has HCPhysPT=%RHp not %RHp is in the PD.\n",
4264	fLongMode ? 16 : 8, u64AddressPT, iPDE,
4265	iSub ? pMap->aPTs[iPDE].HCPhysPaePT1 : pMap->aPTs[iPDE].HCPhysPaePT0, HCPhysPT);
4266	pPT = &pMap->aPTs[iPDE].paPaePTsR3[iSub];
4267	}
4268	}
4269	}
4270	int rc2 = VERR_INVALID_PARAMETER;
4271	if (pPT)
4272	rc2 = pgmR3DumpHierarchyHCPaePT(pVM, pPT, u64AddressPT, fLongMode, cMaxDepth - 1, pHlp);
4273	else
4274	pHlp->pfnPrintf(pHlp, "%0*llx error! Page table at HCPhys=%RHp was not found in the page pool!\n",
4275	fLongMode ? 16 : 8, u64AddressPT, HCPhysPT);
4276	if (rc2 < rc && RT_SUCCESS(rc))
4277	rc = rc2;
4278	}
4279	}
4280	}
4281	}
4282	return rc;
4283	}
4284
4285
4286	/**
4287	* Dumps a PAE shadow page directory pointer table.
4288	*
4289	* @returns VBox status code (VINF_SUCCESS).
4290	* @param pVM The VM handle.
4291	* @param HCPhys The physical address of the page directory pointer table.
4292	* @param u64Address The virtual address of the page table starts.
4293	* @param cr4 The CR4, PSE is currently used.
4294	* @param fLongMode Set if this a long mode table; clear if it's a legacy mode table.
4295	* @param cMaxDepth The maxium depth.
4296	* @param pHlp Pointer to the output functions.
4297	*/
4298	static int pgmR3DumpHierarchyHCPaePDPT(PVM pVM, RTHCPHYS HCPhys, uint64_t u64Address, uint32_t cr4, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
4299	{
4300	PX86PDPT pPDPT = (PX86PDPT)MMPagePhys2Page(pVM, HCPhys);
4301	if (!pPDPT)
4302	{
4303	pHlp->pfnPrintf(pHlp, "%0*llx error! Page directory pointer table at HCPhys=%RHp was not found in the page pool!\n",
4304	fLongMode ? 16 : 8, u64Address, HCPhys);
4305	return VERR_INVALID_PARAMETER;
4306	}
4307
4308	int rc = VINF_SUCCESS;
4309	const unsigned c = fLongMode ? RT_ELEMENTS(pPDPT->a) : X86_PG_PAE_PDPE_ENTRIES;
4310	for (unsigned i = 0; i < c; i++)
4311	{
4312	X86PDPE Pdpe = pPDPT->a[i];
4313	if (Pdpe.n.u1Present)
4314	{
4315	if (fLongMode)
4316	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a p ? /
4317	"%016llx 1 \| P %c %c %c %c %c %s %s %s %s .. %c%c%c %016llx\n",
4318	u64Address + ((uint64_t)i << X86_PDPT_SHIFT),
4319	Pdpe.lm.u1Write ? 'W' : 'R',
4320	Pdpe.lm.u1User ? 'U' : 'S',
4321	Pdpe.lm.u1Accessed ? 'A' : '-',
4322	Pdpe.lm.u3Reserved & 1? '?' : '.', /* ignored */
4323	Pdpe.lm.u3Reserved & 4? '!' : '.', /* mbz */
4324	Pdpe.lm.u1WriteThru ? "WT" : "--",
4325	Pdpe.lm.u1CacheDisable? "CD" : "--",
4326	Pdpe.lm.u3Reserved & 2? "!" : "..",/* mbz */
4327	Pdpe.lm.u1NoExecute ? "NX" : "--",
4328	Pdpe.u & RT_BIT(9) ? '1' : '0',
4329	Pdpe.u & PGM_PLXFLAGS_PERMANENT ? 'p' : '-',
4330	Pdpe.u & RT_BIT(11) ? '1' : '0',
4331	Pdpe.u & X86_PDPE_PG_MASK);
4332	else
4333	pHlp->pfnPrintf(pHlp, /P G WT CD AT NX 4M a p ? /
4334	"%08x 0 \| P %c %s %s %s %s .. %c%c%c %016llx\n",
4335	i << X86_PDPT_SHIFT,
4336	Pdpe.n.u4Reserved & 1? '!' : '.', /* mbz */
4337	Pdpe.n.u4Reserved & 4? '!' : '.', /* mbz */
4338	Pdpe.n.u1WriteThru ? "WT" : "--",
4339	Pdpe.n.u1CacheDisable? "CD" : "--",
4340	Pdpe.n.u4Reserved & 2? "!" : "..",/* mbz */
4341	Pdpe.u & RT_BIT(9) ? '1' : '0',
4342	Pdpe.u & PGM_PLXFLAGS_PERMANENT ? 'p' : '-',
4343	Pdpe.u & RT_BIT(11) ? '1' : '0',
4344	Pdpe.u & X86_PDPE_PG_MASK);
4345	if (cMaxDepth >= 1)
4346	{
4347	int rc2 = pgmR3DumpHierarchyHCPaePD(pVM, Pdpe.u & X86_PDPE_PG_MASK, u64Address + ((uint64_t)i << X86_PDPT_SHIFT),
4348	cr4, fLongMode, cMaxDepth - 1, pHlp);
4349	if (rc2 < rc && RT_SUCCESS(rc))
4350	rc = rc2;
4351	}
4352	}
4353	}
4354	return rc;
4355	}
4356
4357
4358	/**
4359	* Dumps a 32-bit shadow page table.
4360	*
4361	* @returns VBox status code (VINF_SUCCESS).
4362	* @param pVM The VM handle.
4363	* @param HCPhys The physical address of the table.
4364	* @param cr4 The CR4, PSE is currently used.
4365	* @param cMaxDepth The maxium depth.
4366	* @param pHlp Pointer to the output functions.
4367	*/
4368	static int pgmR3DumpHierarchyHcPaePML4(PVM pVM, RTHCPHYS HCPhys, uint32_t cr4, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
4369	{
4370	PX86PML4 pPML4 = (PX86PML4)MMPagePhys2Page(pVM, HCPhys);
4371	if (!pPML4)
4372	{
4373	pHlp->pfnPrintf(pHlp, "Page map level 4 at HCPhys=%RHp was not found in the page pool!\n", HCPhys);
4374	return VERR_INVALID_PARAMETER;
4375	}
4376
4377	int rc = VINF_SUCCESS;
4378	for (unsigned i = 0; i < RT_ELEMENTS(pPML4->a); i++)
4379	{
4380	X86PML4E Pml4e = pPML4->a[i];
4381	if (Pml4e.n.u1Present)
4382	{
4383	uint64_t u64Address = ((uint64_t)i << X86_PML4_SHIFT) \| (((uint64_t)i >> (X86_PML4_SHIFT - X86_PDPT_SHIFT - 1)) * 0xffff000000000000ULL);
4384	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a p ? /
4385	"%016llx 0 \| P %c %c %c %c %c %s %s %s %s .. %c%c%c %016llx\n",
4386	u64Address,
4387	Pml4e.n.u1Write ? 'W' : 'R',
4388	Pml4e.n.u1User ? 'U' : 'S',
4389	Pml4e.n.u1Accessed ? 'A' : '-',
4390	Pml4e.n.u3Reserved & 1? '?' : '.', /* ignored */
4391	Pml4e.n.u3Reserved & 4? '!' : '.', /* mbz */
4392	Pml4e.n.u1WriteThru ? "WT" : "--",
4393	Pml4e.n.u1CacheDisable? "CD" : "--",
4394	Pml4e.n.u3Reserved & 2? "!" : "..",/* mbz */
4395	Pml4e.n.u1NoExecute ? "NX" : "--",
4396	Pml4e.u & RT_BIT(9) ? '1' : '0',
4397	Pml4e.u & PGM_PLXFLAGS_PERMANENT ? 'p' : '-',
4398	Pml4e.u & RT_BIT(11) ? '1' : '0',
4399	Pml4e.u & X86_PML4E_PG_MASK);
4400
4401	if (cMaxDepth >= 1)
4402	{
4403	int rc2 = pgmR3DumpHierarchyHCPaePDPT(pVM, Pml4e.u & X86_PML4E_PG_MASK, u64Address, cr4, true, cMaxDepth - 1, pHlp);
4404	if (rc2 < rc && RT_SUCCESS(rc))
4405	rc = rc2;
4406	}
4407	}
4408	}
4409	return rc;
4410	}
4411
4412
4413	/**
4414	* Dumps a 32-bit shadow page table.
4415	*
4416	* @returns VBox status code (VINF_SUCCESS).
4417	* @param pVM The VM handle.
4418	* @param pPT Pointer to the page table.
4419	* @param u32Address The virtual address this table starts at.
4420	* @param pHlp Pointer to the output functions.
4421	*/
4422	int pgmR3DumpHierarchyHC32BitPT(PVM pVM, PX86PT pPT, uint32_t u32Address, PCDBGFINFOHLP pHlp)
4423	{
4424	for (unsigned i = 0; i < RT_ELEMENTS(pPT->a); i++)
4425	{
4426	X86PTE Pte = pPT->a[i];
4427	if (Pte.n.u1Present)
4428	{
4429	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a m d /
4430	"%08x 1 \| P %c %c %c %c %c %s %s %s .. 4K %c%c%c %08x\n",
4431	u32Address + (i << X86_PT_SHIFT),
4432	Pte.n.u1Write ? 'W' : 'R',
4433	Pte.n.u1User ? 'U' : 'S',
4434	Pte.n.u1Accessed ? 'A' : '-',
4435	Pte.n.u1Dirty ? 'D' : '-',
4436	Pte.n.u1Global ? 'G' : '-',
4437	Pte.n.u1WriteThru ? "WT" : "--",
4438	Pte.n.u1CacheDisable? "CD" : "--",
4439	Pte.n.u1PAT ? "AT" : "--",
4440	Pte.u & PGM_PTFLAGS_TRACK_DIRTY ? 'd' : '-',
4441	Pte.u & RT_BIT(10) ? '1' : '0',
4442	Pte.u & PGM_PTFLAGS_CSAM_VALIDATED ? 'v' : '-',
4443	Pte.u & X86_PDE_PG_MASK);
4444	}
4445	}
4446	return VINF_SUCCESS;
4447	}
4448
4449
4450	/**
4451	* Dumps a 32-bit shadow page directory and page tables.
4452	*
4453	* @returns VBox status code (VINF_SUCCESS).
4454	* @param pVM The VM handle.
4455	* @param cr3 The root of the hierarchy.
4456	* @param cr4 The CR4, PSE is currently used.
4457	* @param cMaxDepth How deep into the hierarchy the dumper should go.
4458	* @param pHlp Pointer to the output functions.
4459	*/
4460	int pgmR3DumpHierarchyHC32BitPD(PVM pVM, uint32_t cr3, uint32_t cr4, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
4461	{
4462	PX86PD pPD = (PX86PD)MMPagePhys2Page(pVM, cr3 & X86_CR3_PAGE_MASK);
4463	if (!pPD)
4464	{
4465	pHlp->pfnPrintf(pHlp, "Page directory at %#x was not found in the page pool!\n", cr3 & X86_CR3_PAGE_MASK);
4466	return VERR_INVALID_PARAMETER;
4467	}
4468
4469	int rc = VINF_SUCCESS;
4470	for (unsigned i = 0; i < RT_ELEMENTS(pPD->a); i++)
4471	{
4472	X86PDE Pde = pPD->a[i];
4473	if (Pde.n.u1Present)
4474	{
4475	const uint32_t u32Address = i << X86_PD_SHIFT;
4476	if ((cr4 & X86_CR4_PSE) && Pde.b.u1Size)
4477	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a m d /
4478	"%08x 0 \| P %c %c %c %c %c %s %s %s .. 4M %c%c%c %08x\n",
4479	u32Address,
4480	Pde.b.u1Write ? 'W' : 'R',
4481	Pde.b.u1User ? 'U' : 'S',
4482	Pde.b.u1Accessed ? 'A' : '-',
4483	Pde.b.u1Dirty ? 'D' : '-',
4484	Pde.b.u1Global ? 'G' : '-',
4485	Pde.b.u1WriteThru ? "WT" : "--",
4486	Pde.b.u1CacheDisable? "CD" : "--",
4487	Pde.b.u1PAT ? "AT" : "--",
4488	Pde.u & RT_BIT_64(9) ? '1' : '0',
4489	Pde.u & PGM_PDFLAGS_MAPPING ? 'm' : '-',
4490	Pde.u & PGM_PDFLAGS_TRACK_DIRTY ? 'd' : '-',
4491	Pde.u & X86_PDE4M_PG_MASK);
4492	else
4493	{
4494	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a m d /
4495	"%08x 0 \| P %c %c %c %c %c %s %s .. .. 4K %c%c%c %08x\n",
4496	u32Address,
4497	Pde.n.u1Write ? 'W' : 'R',
4498	Pde.n.u1User ? 'U' : 'S',
4499	Pde.n.u1Accessed ? 'A' : '-',
4500	Pde.n.u1Reserved0 ? '?' : '.', /* ignored */
4501	Pde.n.u1Reserved1 ? '?' : '.', /* ignored */
4502	Pde.n.u1WriteThru ? "WT" : "--",
4503	Pde.n.u1CacheDisable? "CD" : "--",
4504	Pde.u & RT_BIT_64(9) ? '1' : '0',
4505	Pde.u & PGM_PDFLAGS_MAPPING ? 'm' : '-',
4506	Pde.u & PGM_PDFLAGS_TRACK_DIRTY ? 'd' : '-',
4507	Pde.u & X86_PDE_PG_MASK);
4508	if (cMaxDepth >= 1)
4509	{
4510	/** @todo what about using the page pool for mapping PTs? */
4511	RTHCPHYS HCPhys = Pde.u & X86_PDE_PG_MASK;
4512	PX86PT pPT = NULL;
4513	if (!(Pde.u & PGM_PDFLAGS_MAPPING))
4514	pPT = (PX86PT)MMPagePhys2Page(pVM, HCPhys);
4515	else
4516	{
4517	for (PPGMMAPPING pMap = pVM->pgm.s.pMappingsR3; pMap; pMap = pMap->pNextR3)
4518	if (u32Address - pMap->GCPtr < pMap->cb)
4519	{
4520	int iPDE = (u32Address - pMap->GCPtr) >> X86_PD_SHIFT;
4521	if (pMap->aPTs[iPDE].HCPhysPT != HCPhys)
4522	pHlp->pfnPrintf(pHlp, "%08x error! Mapping error! PT %d has HCPhysPT=%RHp not %RHp is in the PD.\n",
4523	u32Address, iPDE, pMap->aPTs[iPDE].HCPhysPT, HCPhys);
4524	pPT = pMap->aPTs[iPDE].pPTR3;
4525	}
4526	}
4527	int rc2 = VERR_INVALID_PARAMETER;
4528	if (pPT)
4529	rc2 = pgmR3DumpHierarchyHC32BitPT(pVM, pPT, u32Address, pHlp);
4530	else
4531	pHlp->pfnPrintf(pHlp, "%08x error! Page table at %#x was not found in the page pool!\n", u32Address, HCPhys);
4532	if (rc2 < rc && RT_SUCCESS(rc))
4533	rc = rc2;
4534	}
4535	}
4536	}
4537	}
4538
4539	return rc;
4540	}
4541
4542
4543	/**
4544	* Dumps a 32-bit shadow page table.
4545	*
4546	* @returns VBox status code (VINF_SUCCESS).
4547	* @param pVM The VM handle.
4548	* @param pPT Pointer to the page table.
4549	* @param u32Address The virtual address this table starts at.
4550	* @param PhysSearch Address to search for.
4551	*/
4552	int pgmR3DumpHierarchyGC32BitPT(PVM pVM, PX86PT pPT, uint32_t u32Address, RTGCPHYS PhysSearch)
4553	{
4554	for (unsigned i = 0; i < RT_ELEMENTS(pPT->a); i++)
4555	{
4556	X86PTE Pte = pPT->a[i];
4557	if (Pte.n.u1Present)
4558	{
4559	Log(( /P R S A D G WT CD AT NX 4M a m d /
4560	"%08x 1 \| P %c %c %c %c %c %s %s %s .. 4K %c%c%c %08x\n",
4561	u32Address + (i << X86_PT_SHIFT),
4562	Pte.n.u1Write ? 'W' : 'R',
4563	Pte.n.u1User ? 'U' : 'S',
4564	Pte.n.u1Accessed ? 'A' : '-',
4565	Pte.n.u1Dirty ? 'D' : '-',
4566	Pte.n.u1Global ? 'G' : '-',
4567	Pte.n.u1WriteThru ? "WT" : "--",
4568	Pte.n.u1CacheDisable? "CD" : "--",
4569	Pte.n.u1PAT ? "AT" : "--",
4570	Pte.u & PGM_PTFLAGS_TRACK_DIRTY ? 'd' : '-',
4571	Pte.u & RT_BIT(10) ? '1' : '0',
4572	Pte.u & PGM_PTFLAGS_CSAM_VALIDATED ? 'v' : '-',
4573	Pte.u & X86_PDE_PG_MASK));
4574
4575	if ((Pte.u & X86_PDE_PG_MASK) == PhysSearch)
4576	{
4577	uint64_t fPageShw = 0;
4578	RTHCPHYS pPhysHC = 0;
4579
4580	/** @todo SMP support!! */
4581	PGMShwGetPage(&pVM->aCpus[0], (RTGCPTR)(u32Address + (i << X86_PT_SHIFT)), &fPageShw, &pPhysHC);
4582	Log(("Found %RGp at %RGv -> flags=%llx\n", PhysSearch, (RTGCPTR)(u32Address + (i << X86_PT_SHIFT)), fPageShw));
4583	}
4584	}
4585	}
4586	return VINF_SUCCESS;
4587	}
4588
4589
4590	/**
4591	* Dumps a 32-bit guest page directory and page tables.
4592	*
4593	* @returns VBox status code (VINF_SUCCESS).
4594	* @param pVM The VM handle.
4595	* @param cr3 The root of the hierarchy.
4596	* @param cr4 The CR4, PSE is currently used.
4597	* @param PhysSearch Address to search for.
4598	*/
4599	VMMR3DECL(int) PGMR3DumpHierarchyGC(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCPHYS PhysSearch)
4600	{
4601	bool fLongMode = false;
4602	const unsigned cch = fLongMode ? 16 : 8; NOREF(cch);
4603	PX86PD pPD = 0;
4604
4605	int rc = PGM_GCPHYS_2_PTR(pVM, cr3 & X86_CR3_PAGE_MASK, &pPD);
4606	if (RT_FAILURE(rc) \|\| !pPD)
4607	{
4608	Log(("Page directory at %#x was not found in the page pool!\n", cr3 & X86_CR3_PAGE_MASK));
4609	return VERR_INVALID_PARAMETER;
4610	}
4611
4612	Log(("cr3=%08x cr4=%08x%s\n"
4613	"%-*s P - Present\n"
4614	"%-*s \| R/W - Read (0) / Write (1)\n"
4615	"%-*s \| \| U/S - User (1) / Supervisor (0)\n"
4616	"%-*s \| \| \| A - Accessed\n"
4617	"%-*s \| \| \| \| D - Dirty\n"
4618	"%-*s \| \| \| \| \| G - Global\n"
4619	"%-*s \| \| \| \| \| \| WT - Write thru\n"
4620	"%-*s \| \| \| \| \| \| \| CD - Cache disable\n"
4621	"%-*s \| \| \| \| \| \| \| \| AT - Attribute table (PAT)\n"
4622	"%-*s \| \| \| \| \| \| \| \| \| NX - No execute (K8)\n"
4623	"%-*s \| \| \| \| \| \| \| \| \| \| 4K/4M/2M - Page size.\n"
4624	"%-*s \| \| \| \| \| \| \| \| \| \| \| AVL - a=allocated; m=mapping; d=track dirty;\n"
4625	"%-*s \| \| \| \| \| \| \| \| \| \| \| \| p=permanent; v=validated;\n"
4626	"%-*s Level \| \| \| \| \| \| \| \| \| \| \| \| Page\n"
4627	/* xxxx n **** P R S A D G WT CD AT NX 4M AVL xxxxxxxxxxxxx
4628	- W U - - - -- -- -- -- -- 010 */
4629	, cr3, cr4, fLongMode ? " Long Mode" : "",
4630	cch, "", cch, "", cch, "", cch, "", cch, "", cch, "", cch, "",
4631	cch, "", cch, "", cch, "", cch, "", cch, "", cch, "", cch, "Address"));
4632
4633	for (unsigned i = 0; i < RT_ELEMENTS(pPD->a); i++)
4634	{
4635	X86PDE Pde = pPD->a[i];
4636	if (Pde.n.u1Present)
4637	{
4638	const uint32_t u32Address = i << X86_PD_SHIFT;
4639
4640	if ((cr4 & X86_CR4_PSE) && Pde.b.u1Size)
4641	Log(( /P R S A D G WT CD AT NX 4M a m d /
4642	"%08x 0 \| P %c %c %c %c %c %s %s %s .. 4M %c%c%c %08x\n",
4643	u32Address,
4644	Pde.b.u1Write ? 'W' : 'R',
4645	Pde.b.u1User ? 'U' : 'S',
4646	Pde.b.u1Accessed ? 'A' : '-',
4647	Pde.b.u1Dirty ? 'D' : '-',
4648	Pde.b.u1Global ? 'G' : '-',
4649	Pde.b.u1WriteThru ? "WT" : "--",
4650	Pde.b.u1CacheDisable? "CD" : "--",
4651	Pde.b.u1PAT ? "AT" : "--",
4652	Pde.u & RT_BIT(9) ? '1' : '0',
4653	Pde.u & RT_BIT(10) ? '1' : '0',
4654	Pde.u & RT_BIT(11) ? '1' : '0',
4655	pgmGstGet4MBPhysPage(&pVM->pgm.s, Pde)));
4656	/** @todo PhysSearch */
4657	else
4658	{
4659	Log(( /P R S A D G WT CD AT NX 4M a m d /
4660	"%08x 0 \| P %c %c %c %c %c %s %s .. .. 4K %c%c%c %08x\n",
4661	u32Address,
4662	Pde.n.u1Write ? 'W' : 'R',
4663	Pde.n.u1User ? 'U' : 'S',
4664	Pde.n.u1Accessed ? 'A' : '-',
4665	Pde.n.u1Reserved0 ? '?' : '.', /* ignored */
4666	Pde.n.u1Reserved1 ? '?' : '.', /* ignored */
4667	Pde.n.u1WriteThru ? "WT" : "--",
4668	Pde.n.u1CacheDisable? "CD" : "--",
4669	Pde.u & RT_BIT(9) ? '1' : '0',
4670	Pde.u & RT_BIT(10) ? '1' : '0',
4671	Pde.u & RT_BIT(11) ? '1' : '0',
4672	Pde.u & X86_PDE_PG_MASK));
4673	////if (cMaxDepth >= 1)
4674	{
4675	/** @todo what about using the page pool for mapping PTs? */
4676	RTGCPHYS GCPhys = Pde.u & X86_PDE_PG_MASK;
4677	PX86PT pPT = NULL;
4678
4679	rc = PGM_GCPHYS_2_PTR(pVM, GCPhys, &pPT);
4680
4681	int rc2 = VERR_INVALID_PARAMETER;
4682	if (pPT)
4683	rc2 = pgmR3DumpHierarchyGC32BitPT(pVM, pPT, u32Address, PhysSearch);
4684	else
4685	Log(("%08x error! Page table at %#x was not found in the page pool!\n", u32Address, GCPhys));
4686	if (rc2 < rc && RT_SUCCESS(rc))
4687	rc = rc2;
4688	}
4689	}
4690	}
4691	}
4692
4693	return rc;
4694	}
4695
4696
4697	/**
4698	* Dumps a page table hierarchy use only physical addresses and cr4/lm flags.
4699	*
4700	* @returns VBox status code (VINF_SUCCESS).
4701	* @param pVM The VM handle.
4702	* @param cr3 The root of the hierarchy.
4703	* @param cr4 The cr4, only PAE and PSE is currently used.
4704	* @param fLongMode Set if long mode, false if not long mode.
4705	* @param cMaxDepth Number of levels to dump.
4706	* @param pHlp Pointer to the output functions.
4707	*/
4708	VMMR3DECL(int) PGMR3DumpHierarchyHC(PVM pVM, uint64_t cr3, uint64_t cr4, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
4709	{
4710	if (!pHlp)
4711	pHlp = DBGFR3InfoLogHlp();
4712	if (!cMaxDepth)
4713	return VINF_SUCCESS;
4714	const unsigned cch = fLongMode ? 16 : 8;
4715	pHlp->pfnPrintf(pHlp,
4716	"cr3=%08x cr4=%08x%s\n"
4717	"%-*s P - Present\n"
4718	"%-*s \| R/W - Read (0) / Write (1)\n"
4719	"%-*s \| \| U/S - User (1) / Supervisor (0)\n"
4720	"%-*s \| \| \| A - Accessed\n"
4721	"%-*s \| \| \| \| D - Dirty\n"
4722	"%-*s \| \| \| \| \| G - Global\n"
4723	"%-*s \| \| \| \| \| \| WT - Write thru\n"
4724	"%-*s \| \| \| \| \| \| \| CD - Cache disable\n"
4725	"%-*s \| \| \| \| \| \| \| \| AT - Attribute table (PAT)\n"
4726	"%-*s \| \| \| \| \| \| \| \| \| NX - No execute (K8)\n"
4727	"%-*s \| \| \| \| \| \| \| \| \| \| 4K/4M/2M - Page size.\n"
4728	"%-*s \| \| \| \| \| \| \| \| \| \| \| AVL - a=allocated; m=mapping; d=track dirty;\n"
4729	"%-*s \| \| \| \| \| \| \| \| \| \| \| \| p=permanent; v=validated;\n"
4730	"%-*s Level \| \| \| \| \| \| \| \| \| \| \| \| Page\n"
4731	/* xxxx n **** P R S A D G WT CD AT NX 4M AVL xxxxxxxxxxxxx
4732	- W U - - - -- -- -- -- -- 010 */
4733	, cr3, cr4, fLongMode ? " Long Mode" : "",
4734	cch, "", cch, "", cch, "", cch, "", cch, "", cch, "", cch, "",
4735	cch, "", cch, "", cch, "", cch, "", cch, "", cch, "", cch, "Address");
4736	if (cr4 & X86_CR4_PAE)
4737	{
4738	if (fLongMode)
4739	return pgmR3DumpHierarchyHcPaePML4(pVM, cr3 & X86_CR3_PAGE_MASK, cr4, cMaxDepth, pHlp);
4740	return pgmR3DumpHierarchyHCPaePDPT(pVM, cr3 & X86_CR3_PAE_PAGE_MASK, 0, cr4, false, cMaxDepth, pHlp);
4741	}
4742	return pgmR3DumpHierarchyHC32BitPD(pVM, cr3 & X86_CR3_PAGE_MASK, cr4, cMaxDepth, pHlp);
4743	}
4744
4745	#ifdef VBOX_WITH_DEBUGGER
4746
4747	/**
4748	* The '.pgmram' command.
4749	*
4750	* @returns VBox status.
4751	* @param pCmd Pointer to the command descriptor (as registered).
4752	* @param pCmdHlp Pointer to command helper functions.
4753	* @param pVM Pointer to the current VM (if any).
4754	* @param paArgs Pointer to (readonly) array of arguments.
4755	* @param cArgs Number of arguments in the array.
4756	*/
4757	static DECLCALLBACK(int) pgmR3CmdRam(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4758	{
4759	/*
4760	* Validate input.
4761	*/
4762	if (!pVM)
4763	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4764	if (!pVM->pgm.s.pRamRangesRC)
4765	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Sorry, no Ram is registered.\n");
4766
4767	/*
4768	* Dump the ranges.
4769	*/
4770	int rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL, "From - To (incl) pvHC\n");
4771	PPGMRAMRANGE pRam;
4772	for (pRam = pVM->pgm.s.pRamRangesR3; pRam; pRam = pRam->pNextR3)
4773	{
4774	rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL,
4775	"%RGp - %RGp %p\n",
4776	pRam->GCPhys, pRam->GCPhysLast, pRam->pvR3);
4777	if (RT_FAILURE(rc))
4778	return rc;
4779	}
4780
4781	return VINF_SUCCESS;
4782	}
4783
4784
4785	/**
4786	* The '.pgmmap' command.
4787	*
4788	* @returns VBox status.
4789	* @param pCmd Pointer to the command descriptor (as registered).
4790	* @param pCmdHlp Pointer to command helper functions.
4791	* @param pVM Pointer to the current VM (if any).
4792	* @param paArgs Pointer to (readonly) array of arguments.
4793	* @param cArgs Number of arguments in the array.
4794	*/
4795	static DECLCALLBACK(int) pgmR3CmdMap(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4796	{
4797	/*
4798	* Validate input.
4799	*/
4800	if (!pVM)
4801	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4802	if (!pVM->pgm.s.pMappingsR3)
4803	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Sorry, no mappings are registered.\n");
4804
4805	/*
4806	* Print message about the fixedness of the mappings.
4807	*/
4808	int rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL, pVM->pgm.s.fMappingsFixed ? "The mappings are FIXED.\n" : "The mappings are FLOATING.\n");
4809	if (RT_FAILURE(rc))
4810	return rc;
4811
4812	/*
4813	* Dump the ranges.
4814	*/
4815	PPGMMAPPING pCur;
4816	for (pCur = pVM->pgm.s.pMappingsR3; pCur; pCur = pCur->pNextR3)
4817	{
4818	rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL,
4819	"%08x - %08x %s\n",
4820	pCur->GCPtr, pCur->GCPtrLast, pCur->pszDesc);
4821	if (RT_FAILURE(rc))
4822	return rc;
4823	}
4824
4825	return VINF_SUCCESS;
4826	}
4827
4828
4829	/**
4830	* The '.pgmerror' and '.pgmerroroff' commands.
4831	*
4832	* @returns VBox status.
4833	* @param pCmd Pointer to the command descriptor (as registered).
4834	* @param pCmdHlp Pointer to command helper functions.
4835	* @param pVM Pointer to the current VM (if any).
4836	* @param paArgs Pointer to (readonly) array of arguments.
4837	* @param cArgs Number of arguments in the array.
4838	*/
4839	static DECLCALLBACK(int) pgmR3CmdError(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4840	{
4841	/*
4842	* Validate input.
4843	*/
4844	if (!pVM)
4845	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4846	AssertReturn(cArgs == 0 \|\| (cArgs == 1 && paArgs[0].enmType == DBGCVAR_TYPE_STRING),
4847	pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: Hit bug in the parser.\n"));
4848
4849	if (!cArgs)
4850	{
4851	/*
4852	* Print the list of error injection locations with status.
4853	*/
4854	pCmdHlp->pfnPrintf(pCmdHlp, NULL, "PGM error inject locations:\n");
4855	pCmdHlp->pfnPrintf(pCmdHlp, NULL, " handy - %RTbool\n", pVM->pgm.s.fErrInjHandyPages);
4856	}
4857	else
4858	{
4859
4860	/*
4861	* String switch on where to inject the error.
4862	*/
4863	bool const fNewState = !strcmp(pCmd->pszCmd, "pgmerror");
4864	const char *pszWhere = paArgs[0].u.pszString;
4865	if (!strcmp(pszWhere, "handy"))
4866	ASMAtomicWriteBool(&pVM->pgm.s.fErrInjHandyPages, fNewState);
4867	else
4868	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: Invalid 'where' value: %s.\n", pszWhere);
4869	pCmdHlp->pfnPrintf(pCmdHlp, NULL, "done\n");
4870	}
4871	return VINF_SUCCESS;
4872	}
4873
4874
4875	/**
4876	* The '.pgmsync' command.
4877	*
4878	* @returns VBox status.
4879	* @param pCmd Pointer to the command descriptor (as registered).
4880	* @param pCmdHlp Pointer to command helper functions.
4881	* @param pVM Pointer to the current VM (if any).
4882	* @param paArgs Pointer to (readonly) array of arguments.
4883	* @param cArgs Number of arguments in the array.
4884	*/
4885	static DECLCALLBACK(int) pgmR3CmdSync(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4886	{
4887	/** @todo SMP support */
4888	PVMCPU pVCpu = &pVM->aCpus[0];
4889
4890	/*
4891	* Validate input.
4892	*/
4893	if (!pVM)
4894	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4895
4896	/*
4897	* Force page directory sync.
4898	*/
4899	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
4900
4901	int rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Forcing page directory sync.\n");
4902	if (RT_FAILURE(rc))
4903	return rc;
4904
4905	return VINF_SUCCESS;
4906	}
4907
4908
4909	#ifdef VBOX_STRICT
4910	/**
4911	* The '.pgmassertcr3' command.
4912	*
4913	* @returns VBox status.
4914	* @param pCmd Pointer to the command descriptor (as registered).
4915	* @param pCmdHlp Pointer to command helper functions.
4916	* @param pVM Pointer to the current VM (if any).
4917	* @param paArgs Pointer to (readonly) array of arguments.
4918	* @param cArgs Number of arguments in the array.
4919	*/
4920	static DECLCALLBACK(int) pgmR3CmdAssertCR3(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4921	{
4922	/** @todo SMP support!! */
4923	PVMCPU pVCpu = &pVM->aCpus[0];
4924
4925	/*
4926	* Validate input.
4927	*/
4928	if (!pVM)
4929	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4930
4931	int rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Checking shadow CR3 page tables for consistency.\n");
4932	if (RT_FAILURE(rc))
4933	return rc;
4934
4935	PGMAssertCR3(pVM, pVCpu, CPUMGetGuestCR3(pVCpu), CPUMGetGuestCR4(pVCpu));
4936
4937	return VINF_SUCCESS;
4938	}
4939	#endif /* VBOX_STRICT */
4940
4941
4942	/**
4943	* The '.pgmsyncalways' command.
4944	*
4945	* @returns VBox status.
4946	* @param pCmd Pointer to the command descriptor (as registered).
4947	* @param pCmdHlp Pointer to command helper functions.
4948	* @param pVM Pointer to the current VM (if any).
4949	* @param paArgs Pointer to (readonly) array of arguments.
4950	* @param cArgs Number of arguments in the array.
4951	*/
4952	static DECLCALLBACK(int) pgmR3CmdSyncAlways(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4953	{
4954	/** @todo SMP support!! */
4955	PVMCPU pVCpu = &pVM->aCpus[0];
4956
4957	/*
4958	* Validate input.
4959	*/
4960	if (!pVM)
4961	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4962
4963	/*
4964	* Force page directory sync.
4965	*/
4966	if (pVCpu->pgm.s.fSyncFlags & PGM_SYNC_ALWAYS)
4967	{
4968	ASMAtomicAndU32(&pVCpu->pgm.s.fSyncFlags, ~PGM_SYNC_ALWAYS);
4969	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Disabled permanent forced page directory syncing.\n");
4970	}
4971	else
4972	{
4973	ASMAtomicOrU32(&pVCpu->pgm.s.fSyncFlags, PGM_SYNC_ALWAYS);
4974	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
4975	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Enabled permanent forced page directory syncing.\n");
4976	}
4977	}
4978
4979
4980	/**
4981	* The '.pgmsyncalways' command.
4982	*
4983	* @returns VBox status.
4984	* @param pCmd Pointer to the command descriptor (as registered).
4985	* @param pCmdHlp Pointer to command helper functions.
4986	* @param pVM Pointer to the current VM (if any).
4987	* @param paArgs Pointer to (readonly) array of arguments.
4988	* @param cArgs Number of arguments in the array.
4989	*/
4990	static DECLCALLBACK(int) pgmR3CmdPhysToFile(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4991	{
4992	/*
4993	* Validate input.
4994	*/
4995	if (!pVM)
4996	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4997	if ( cArgs < 1
4998	\|\| cArgs > 2
4999	\|\| paArgs[0].enmType != DBGCVAR_TYPE_STRING
5000	\|\| ( cArgs > 1
5001	&& paArgs[1].enmType != DBGCVAR_TYPE_STRING))
5002	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: parser error, invalid arguments.\n");
5003	if ( cArgs >= 2
5004	&& strcmp(paArgs[1].u.pszString, "nozero"))
5005	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: Invalid 2nd argument '%s', must be 'nozero'.\n", paArgs[1].u.pszString);
5006	bool fIncZeroPgs = cArgs < 2;
5007
5008	/*
5009	* Open the output file and get the ram parameters.
5010	*/
5011	RTFILE hFile;
5012	int rc = RTFileOpen(&hFile, paArgs[0].u.pszString, RTFILE_O_WRITE \| RTFILE_O_CREATE_REPLACE \| RTFILE_O_DENY_WRITE);
5013	if (RT_FAILURE(rc))
5014	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: RTFileOpen(,'%s',) -> %Rrc.\n", paArgs[0].u.pszString, rc);
5015
5016	uint32_t cbRamHole = 0;
5017	CFGMR3QueryU32Def(CFGMR3GetRoot(pVM), "RamHoleSize", &cbRamHole, MM_RAM_HOLE_SIZE_DEFAULT);
5018	uint64_t cbRam = 0;
5019	CFGMR3QueryU64Def(CFGMR3GetRoot(pVM), "RamSize", &cbRam, 0);
5020	RTGCPHYS GCPhysEnd = cbRam + cbRamHole;
5021
5022	/*
5023	* Dump the physical memory, page by page.
5024	*/
5025	RTGCPHYS GCPhys = 0;
5026	char abZeroPg[PAGE_SIZE];
5027	RT_ZERO(abZeroPg);
5028
5029	pgmLock(pVM);
5030	for (PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesR3;
5031	pRam && pRam->GCPhys < GCPhysEnd && RT_SUCCESS(rc);
5032	pRam = pRam->pNextR3)
5033	{
5034	/* fill the gap */
5035	if (pRam->GCPhys > GCPhys && fIncZeroPgs)
5036	{
5037	while (pRam->GCPhys > GCPhys && RT_SUCCESS(rc))
5038	{
5039	rc = RTFileWrite(hFile, abZeroPg, PAGE_SIZE, NULL);
5040	GCPhys += PAGE_SIZE;
5041	}
5042	}
5043
5044	PCPGMPAGE pPage = &pRam->aPages[0];
5045	while (GCPhys < pRam->GCPhysLast && RT_SUCCESS(rc))
5046	{
5047	if (PGM_PAGE_IS_ZERO(pPage))
5048	{
5049	if (fIncZeroPgs)
5050	{
5051	rc = RTFileWrite(hFile, abZeroPg, PAGE_SIZE, NULL);
5052	if (RT_FAILURE(rc))
5053	pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: RTFileWrite -> %Rrc at GCPhys=%RGp.\n", rc, GCPhys);
5054	}
5055	}
5056	else
5057	{
5058	switch (PGM_PAGE_GET_TYPE(pPage))
5059	{
5060	case PGMPAGETYPE_RAM:
5061	case PGMPAGETYPE_ROM_SHADOW: /* trouble?? */
5062	case PGMPAGETYPE_ROM:
5063	case PGMPAGETYPE_MMIO2:
5064	{
5065	void const *pvPage;
5066	PGMPAGEMAPLOCK Lock;
5067	rc = PGMPhysGCPhys2CCPtrReadOnly(pVM, GCPhys, &pvPage, &Lock);
5068	if (RT_SUCCESS(rc))
5069	{
5070	rc = RTFileWrite(hFile, pvPage, PAGE_SIZE, NULL);
5071	PGMPhysReleasePageMappingLock(pVM, &Lock);
5072	if (RT_FAILURE(rc))
5073	pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: RTFileWrite -> %Rrc at GCPhys=%RGp.\n", rc, GCPhys);
5074	}
5075	else
5076	pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: PGMPhysGCPhys2CCPtrReadOnly -> %Rrc at GCPhys=%RGp.\n", rc, GCPhys);
5077	break;
5078	}
5079
5080	default:
5081	AssertFailed();
5082	case PGMPAGETYPE_MMIO2_ALIAS_MMIO:
5083	case PGMPAGETYPE_MMIO:
5084	if (fIncZeroPgs)
5085	{
5086	rc = RTFileWrite(hFile, abZeroPg, PAGE_SIZE, NULL);
5087	if (RT_FAILURE(rc))
5088	pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: RTFileWrite -> %Rrc at GCPhys=%RGp.\n", rc, GCPhys);
5089	}
5090	break;
5091	}
5092	}
5093
5094
5095	/* advance */
5096	GCPhys += PAGE_SIZE;
5097	pPage++;
5098	}
5099	}
5100	pgmUnlock(pVM);
5101
5102	RTFileClose(hFile);
5103	if (RT_SUCCESS(rc))
5104	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Successfully saved physical memory to '%s'.\n", paArgs[0].u.pszString);
5105	return VINF_SUCCESS;
5106	}
5107
5108	#endif /* VBOX_WITH_DEBUGGER */
5109
5110	/**
5111	* pvUser argument of the pgmR3CheckIntegrity*Node callbacks.
5112	*/
5113	typedef struct PGMCHECKINTARGS
5114	{
5115	bool fLeftToRight; /*< true: left-to-right; false: right-to-left. /
5116	PPGMPHYSHANDLER pPrevPhys;
5117	PPGMVIRTHANDLER pPrevVirt;
5118	PPGMPHYS2VIRTHANDLER pPrevPhys2Virt;
5119	PVM pVM;
5120	} PGMCHECKINTARGS, *PPGMCHECKINTARGS;
5121
5122	/**
5123	* Validate a node in the physical handler tree.
5124	*
5125	* @returns 0 on if ok, other wise 1.
5126	* @param pNode The handler node.
5127	* @param pvUser pVM.
5128	*/
5129	static DECLCALLBACK(int) pgmR3CheckIntegrityPhysHandlerNode(PAVLROGCPHYSNODECORE pNode, void *pvUser)
5130	{
5131	PPGMCHECKINTARGS pArgs = (PPGMCHECKINTARGS)pvUser;
5132	PPGMPHYSHANDLER pCur = (PPGMPHYSHANDLER)pNode;
5133	AssertReleaseReturn(!((uintptr_t)pCur & 7), 1);
5134	AssertReleaseMsg(pCur->Core.Key <= pCur->Core.KeyLast,("pCur=%p %RGp-%RGp %s\n", pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
5135	AssertReleaseMsg( !pArgs->pPrevPhys
5136	\|\| (pArgs->fLeftToRight ? pArgs->pPrevPhys->Core.KeyLast < pCur->Core.Key : pArgs->pPrevPhys->Core.KeyLast > pCur->Core.Key),
5137	("pPrevPhys=%p %RGp-%RGp %s\n"
5138	" pCur=%p %RGp-%RGp %s\n",
5139	pArgs->pPrevPhys, pArgs->pPrevPhys->Core.Key, pArgs->pPrevPhys->Core.KeyLast, pArgs->pPrevPhys->pszDesc,
5140	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
5141	pArgs->pPrevPhys = pCur;
5142	return 0;
5143	}
5144
5145
5146	/**
5147	* Validate a node in the virtual handler tree.
5148	*
5149	* @returns 0 on if ok, other wise 1.
5150	* @param pNode The handler node.
5151	* @param pvUser pVM.
5152	*/
5153	static DECLCALLBACK(int) pgmR3CheckIntegrityVirtHandlerNode(PAVLROGCPTRNODECORE pNode, void *pvUser)
5154	{
5155	PPGMCHECKINTARGS pArgs = (PPGMCHECKINTARGS)pvUser;
5156	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)pNode;
5157	AssertReleaseReturn(!((uintptr_t)pCur & 7), 1);
5158	AssertReleaseMsg(pCur->Core.Key <= pCur->Core.KeyLast,("pCur=%p %RGv-%RGv %s\n", pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
5159	AssertReleaseMsg( !pArgs->pPrevVirt
5160	\|\| (pArgs->fLeftToRight ? pArgs->pPrevVirt->Core.KeyLast < pCur->Core.Key : pArgs->pPrevVirt->Core.KeyLast > pCur->Core.Key),
5161	("pPrevVirt=%p %RGv-%RGv %s\n"
5162	" pCur=%p %RGv-%RGv %s\n",
5163	pArgs->pPrevVirt, pArgs->pPrevVirt->Core.Key, pArgs->pPrevVirt->Core.KeyLast, pArgs->pPrevVirt->pszDesc,
5164	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
5165	for (unsigned iPage = 0; iPage < pCur->cPages; iPage++)
5166	{
5167	AssertReleaseMsg(pCur->aPhysToVirt[iPage].offVirtHandler == -RT_OFFSETOF(PGMVIRTHANDLER, aPhysToVirt[iPage]),
5168	("pCur=%p %RGv-%RGv %s\n"
5169	"iPage=%d offVirtHandle=%#x expected %#x\n",
5170	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc,
5171	iPage, pCur->aPhysToVirt[iPage].offVirtHandler, -RT_OFFSETOF(PGMVIRTHANDLER, aPhysToVirt[iPage])));
5172	}
5173	pArgs->pPrevVirt = pCur;
5174	return 0;
5175	}
5176
5177
5178	/**
5179	* Validate a node in the virtual handler tree.
5180	*
5181	* @returns 0 on if ok, other wise 1.
5182	* @param pNode The handler node.
5183	* @param pvUser pVM.
5184	*/
5185	static DECLCALLBACK(int) pgmR3CheckIntegrityPhysToVirtHandlerNode(PAVLROGCPHYSNODECORE pNode, void *pvUser)
5186	{
5187	PPGMCHECKINTARGS pArgs = (PPGMCHECKINTARGS)pvUser;
5188	PPGMPHYS2VIRTHANDLER pCur = (PPGMPHYS2VIRTHANDLER)pNode;
5189	AssertReleaseMsgReturn(!((uintptr_t)pCur & 3), ("\n"), 1);
5190	AssertReleaseMsgReturn(!(pCur->offVirtHandler & 3), ("\n"), 1);
5191	AssertReleaseMsg(pCur->Core.Key <= pCur->Core.KeyLast,("pCur=%p %RGp-%RGp\n", pCur, pCur->Core.Key, pCur->Core.KeyLast));
5192	AssertReleaseMsg( !pArgs->pPrevPhys2Virt
5193	\|\| (pArgs->fLeftToRight ? pArgs->pPrevPhys2Virt->Core.KeyLast < pCur->Core.Key : pArgs->pPrevPhys2Virt->Core.KeyLast > pCur->Core.Key),
5194	("pPrevPhys2Virt=%p %RGp-%RGp\n"
5195	" pCur=%p %RGp-%RGp\n",
5196	pArgs->pPrevPhys2Virt, pArgs->pPrevPhys2Virt->Core.Key, pArgs->pPrevPhys2Virt->Core.KeyLast,
5197	pCur, pCur->Core.Key, pCur->Core.KeyLast));
5198	AssertReleaseMsg( !pArgs->pPrevPhys2Virt
5199	\|\| (pArgs->fLeftToRight ? pArgs->pPrevPhys2Virt->Core.KeyLast < pCur->Core.Key : pArgs->pPrevPhys2Virt->Core.KeyLast > pCur->Core.Key),
5200	("pPrevPhys2Virt=%p %RGp-%RGp\n"
5201	" pCur=%p %RGp-%RGp\n",
5202	pArgs->pPrevPhys2Virt, pArgs->pPrevPhys2Virt->Core.Key, pArgs->pPrevPhys2Virt->Core.KeyLast,
5203	pCur, pCur->Core.Key, pCur->Core.KeyLast));
5204	AssertReleaseMsg((pCur->offNextAlias & (PGMPHYS2VIRTHANDLER_IN_TREE \| PGMPHYS2VIRTHANDLER_IS_HEAD)) == (PGMPHYS2VIRTHANDLER_IN_TREE \| PGMPHYS2VIRTHANDLER_IS_HEAD),
5205	("pCur=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
5206	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias));
5207	if (pCur->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK)
5208	{
5209	PPGMPHYS2VIRTHANDLER pCur2 = pCur;
5210	for (;;)
5211	{
5212	pCur2 = (PPGMPHYS2VIRTHANDLER)((intptr_t)pCur + (pCur->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK));
5213	AssertReleaseMsg(pCur2 != pCur,
5214	(" pCur=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
5215	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias));
5216	AssertReleaseMsg((pCur2->offNextAlias & (PGMPHYS2VIRTHANDLER_IN_TREE \| PGMPHYS2VIRTHANDLER_IS_HEAD)) == PGMPHYS2VIRTHANDLER_IN_TREE,
5217	(" pCur=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
5218	"pCur2=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
5219	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias,
5220	pCur2, pCur2->Core.Key, pCur2->Core.KeyLast, pCur2->offVirtHandler, pCur2->offNextAlias));
5221	AssertReleaseMsg((pCur2->Core.Key ^ pCur->Core.Key) < PAGE_SIZE,
5222	(" pCur=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
5223	"pCur2=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
5224	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias,
5225	pCur2, pCur2->Core.Key, pCur2->Core.KeyLast, pCur2->offVirtHandler, pCur2->offNextAlias));
5226	AssertReleaseMsg((pCur2->Core.KeyLast ^ pCur->Core.KeyLast) < PAGE_SIZE,
5227	(" pCur=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
5228	"pCur2=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
5229	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias,
5230	pCur2, pCur2->Core.Key, pCur2->Core.KeyLast, pCur2->offVirtHandler, pCur2->offNextAlias));
5231	if (!(pCur2->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK))
5232	break;
5233	}
5234	}
5235
5236	pArgs->pPrevPhys2Virt = pCur;
5237	return 0;
5238	}
5239
5240
5241	/**
5242	* Perform an integrity check on the PGM component.
5243	*
5244	* @returns VINF_SUCCESS if everything is fine.
5245	* @returns VBox error status after asserting on integrity breach.
5246	* @param pVM The VM handle.
5247	*/
5248	VMMR3DECL(int) PGMR3CheckIntegrity(PVM pVM)
5249	{
5250	AssertReleaseReturn(pVM->pgm.s.offVM, VERR_INTERNAL_ERROR);
5251
5252	/*
5253	* Check the trees.
5254	*/
5255	int cErrors = 0;
5256	const static PGMCHECKINTARGS s_LeftToRight = { true, NULL, NULL, NULL, pVM };
5257	const static PGMCHECKINTARGS s_RightToLeft = { false, NULL, NULL, NULL, pVM };
5258	PGMCHECKINTARGS Args = s_LeftToRight;
5259	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysHandlers, true, pgmR3CheckIntegrityPhysHandlerNode, &Args);
5260	Args = s_RightToLeft;
5261	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysHandlers, false, pgmR3CheckIntegrityPhysHandlerNode, &Args);
5262	Args = s_LeftToRight;
5263	cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesR3->VirtHandlers, true, pgmR3CheckIntegrityVirtHandlerNode, &Args);
5264	Args = s_RightToLeft;
5265	cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesR3->VirtHandlers, false, pgmR3CheckIntegrityVirtHandlerNode, &Args);
5266	Args = s_LeftToRight;
5267	cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesR3->HyperVirtHandlers, true, pgmR3CheckIntegrityVirtHandlerNode, &Args);
5268	Args = s_RightToLeft;
5269	cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesR3->HyperVirtHandlers, false, pgmR3CheckIntegrityVirtHandlerNode, &Args);
5270	Args = s_LeftToRight;
5271	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysToVirtHandlers, true, pgmR3CheckIntegrityPhysToVirtHandlerNode, &Args);
5272	Args = s_RightToLeft;
5273	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysToVirtHandlers, false, pgmR3CheckIntegrityPhysToVirtHandlerNode, &Args);
5274
5275	return !cErrors ? VINF_SUCCESS : VERR_INTERNAL_ERROR;
5276	}
5277
5278

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source: vbox/trunk/src/VBox/VMM/PGM.cpp@ 22288

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