PGM.cpp@ 31844

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1	/* $Id: PGM.cpp 31807 2010-08-20 09:15:56Z vboxsync $ */
2	/** @file
3	* PGM - Page Manager and Monitor. (Mixing stuff here, not good?)
4	*/
5
6	/*
7	* Copyright (C) 2006-2010 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/** @page pg_pgm PGM - The Page Manager and Monitor
20	*
21	* @see grp_pgm,
22	* @ref pg_pgm_pool,
23	* @ref pg_pgm_phys.
24	*
25	*
26	* @section sec_pgm_modes Paging Modes
27	*
28	* There are three memory contexts: Host Context (HC), Guest Context (GC)
29	* and intermediate context. When talking about paging HC can also be refered to
30	* as "host paging", and GC refered to as "shadow paging".
31	*
32	* We define three basic paging modes: 32-bit, PAE and AMD64. The host paging mode
33	* is defined by the host operating system. The mode used in the shadow paging mode
34	* depends on the host paging mode and what the mode the guest is currently in. The
35	* following relation between the two is defined:
36	*
37	* @verbatim
38	Host > 32-bit \| PAE \| AMD64 \|
39	Guest \| \| \| \|
40	==v================================
41	32-bit 32-bit PAE PAE
42	-------\|--------\|--------\|--------\|
43	PAE PAE PAE PAE
44	-------\|--------\|--------\|--------\|
45	AMD64 AMD64 AMD64 AMD64
46	-------\|--------\|--------\|--------\| @endverbatim
47	*
48	* All configuration except those in the diagonal (upper left) are expected to
49	* require special effort from the switcher (i.e. a bit slower).
50	*
51	*
52	*
53	*
54	* @section sec_pgm_shw The Shadow Memory Context
55	*
56	*
57	* [..]
58	*
59	* Because of guest context mappings requires PDPT and PML4 entries to allow
60	* writing on AMD64, the two upper levels will have fixed flags whatever the
61	* guest is thinking of using there. So, when shadowing the PD level we will
62	* calculate the effective flags of PD and all the higher levels. In legacy
63	* PAE mode this only applies to the PWT and PCD bits (the rest are
64	* ignored/reserved/MBZ). We will ignore those bits for the present.
65	*
66	*
67	*
68	* @section sec_pgm_int The Intermediate Memory Context
69	*
70	* The world switch goes thru an intermediate memory context which purpose it is
71	* to provide different mappings of the switcher code. All guest mappings are also
72	* present in this context.
73	*
74	* The switcher code is mapped at the same location as on the host, at an
75	* identity mapped location (physical equals virtual address), and at the
76	* hypervisor location. The identity mapped location is for when the world
77	* switches that involves disabling paging.
78	*
79	* PGM maintain page tables for 32-bit, PAE and AMD64 paging modes. This
80	* simplifies switching guest CPU mode and consistency at the cost of more
81	* code to do the work. All memory use for those page tables is located below
82	* 4GB (this includes page tables for guest context mappings).
83	*
84	*
85	* @subsection subsec_pgm_int_gc Guest Context Mappings
86	*
87	* During assignment and relocation of a guest context mapping the intermediate
88	* memory context is used to verify the new location.
89	*
90	* Guest context mappings are currently restricted to below 4GB, for reasons
91	* of simplicity. This may change when we implement AMD64 support.
92	*
93	*
94	*
95	*
96	* @section sec_pgm_misc Misc
97	*
98	* @subsection subsec_pgm_misc_diff Differences Between Legacy PAE and Long Mode PAE
99	*
100	* The differences between legacy PAE and long mode PAE are:
101	* -# PDPE bits 1, 2, 5 and 6 are defined differently. In leagcy mode they are
102	* all marked down as must-be-zero, while in long mode 1, 2 and 5 have the
103	* usual meanings while 6 is ignored (AMD). This means that upon switching to
104	* legacy PAE mode we'll have to clear these bits and when going to long mode
105	* they must be set. This applies to both intermediate and shadow contexts,
106	* however we don't need to do it for the intermediate one since we're
107	* executing with CR0.WP at that time.
108	* -# CR3 allows a 32-byte aligned address in legacy mode, while in long mode
109	* a page aligned one is required.
110	*
111	*
112	* @section sec_pgm_handlers Access Handlers
113	*
114	* Placeholder.
115	*
116	*
117	* @subsection sec_pgm_handlers_virt Virtual Access Handlers
118	*
119	* Placeholder.
120	*
121	*
122	* @subsection sec_pgm_handlers_virt Virtual Access Handlers
123	*
124	* We currently implement three types of virtual access handlers: ALL, WRITE
125	* and HYPERVISOR (WRITE). See PGMVIRTHANDLERTYPE for some more details.
126	*
127	* The HYPERVISOR access handlers is kept in a separate tree since it doesn't apply
128	* to physical pages (PGMTREES::HyperVirtHandlers) and only needs to be consulted in
129	* a special \#PF case. The ALL and WRITE are in the PGMTREES::VirtHandlers tree, the
130	* rest of this section is going to be about these handlers.
131	*
132	* We'll go thru the life cycle of a handler and try make sense of it all, don't know
133	* how successfull this is gonna be...
134	*
135	* 1. A handler is registered thru the PGMR3HandlerVirtualRegister and
136	* PGMHandlerVirtualRegisterEx APIs. We check for conflicting virtual handlers
137	* and create a new node that is inserted into the AVL tree (range key). Then
138	* a full PGM resync is flagged (clear pool, sync cr3, update virtual bit of PGMPAGE).
139	*
140	* 2. The following PGMSyncCR3/SyncCR3 operation will first make invoke HandlerVirtualUpdate.
141	*
142	* 2a. HandlerVirtualUpdate will will lookup all the pages covered by virtual handlers
143	* via the current guest CR3 and update the physical page -> virtual handler
144	* translation. Needless to say, this doesn't exactly scale very well. If any changes
145	* are detected, it will flag a virtual bit update just like we did on registration.
146	* PGMPHYS pages with changes will have their virtual handler state reset to NONE.
147	*
148	* 2b. The virtual bit update process will iterate all the pages covered by all the
149	* virtual handlers and update the PGMPAGE virtual handler state to the max of all
150	* virtual handlers on that page.
151	*
152	* 2c. Back in SyncCR3 we will now flush the entire shadow page cache to make sure
153	* we don't miss any alias mappings of the monitored pages.
154	*
155	* 2d. SyncCR3 will then proceed with syncing the CR3 table.
156	*
157	* 3. \#PF(np,read) on a page in the range. This will cause it to be synced
158	* read-only and resumed if it's a WRITE handler. If it's an ALL handler we
159	* will call the handlers like in the next step. If the physical mapping has
160	* changed we will - some time in the future - perform a handler callback
161	* (optional) and update the physical -> virtual handler cache.
162	*
163	* 4. \#PF(,write) on a page in the range. This will cause the handler to
164	* be invoked.
165	*
166	* 5. The guest invalidates the page and changes the physical backing or
167	* unmaps it. This should cause the invalidation callback to be invoked
168	* (it might not yet be 100% perfect). Exactly what happens next... is
169	* this where we mess up and end up out of sync for a while?
170	*
171	* 6. The handler is deregistered by the client via PGMHandlerVirtualDeregister.
172	* We will then set all PGMPAGEs in the physical -> virtual handler cache for
173	* this handler to NONE and trigger a full PGM resync (basically the same
174	* as int step 1). Which means 2 is executed again.
175	*
176	*
177	* @subsubsection sub_sec_pgm_handler_virt_todo TODOs
178	*
179	* There is a bunch of things that needs to be done to make the virtual handlers
180	* work 100% correctly and work more efficiently.
181	*
182	* The first bit hasn't been implemented yet because it's going to slow the
183	* whole mess down even more, and besides it seems to be working reliably for
184	* our current uses. OTOH, some of the optimizations might end up more or less
185	* implementing the missing bits, so we'll see.
186	*
187	* On the optimization side, the first thing to do is to try avoid unnecessary
188	* cache flushing. Then try team up with the shadowing code to track changes
189	* in mappings by means of access to them (shadow in), updates to shadows pages,
190	* invlpg, and shadow PT discarding (perhaps).
191	*
192	* Some idea that have popped up for optimization for current and new features:
193	* - bitmap indicating where there are virtual handlers installed.
194	* (4KB => 220 pages, page 212 => covers 32-bit address space 1:1!)
195	* - Further optimize this by min/max (needs min/max avl getters).
196	* - Shadow page table entry bit (if any left)?
197	*
198	*/
199
200
201	/** @page pg_pgm_phys PGM Physical Guest Memory Management
202	*
203	*
204	* Objectives:
205	* - Guest RAM over-commitment using memory ballooning,
206	* zero pages and general page sharing.
207	* - Moving or mirroring a VM onto a different physical machine.
208	*
209	*
210	* @subsection subsec_pgmPhys_Definitions Definitions
211	*
212	* Allocation chunk - A RTR0MemObjAllocPhysNC object and the tracking
213	* machinery assoicated with it.
214	*
215	*
216	*
217	*
218	* @subsection subsec_pgmPhys_AllocPage Allocating a page.
219	*
220	* Initially we map all guest memory to the (per VM) zero page, which
221	* means that none of the read functions will cause pages to be allocated.
222	*
223	* Exception, access bit in page tables that have been shared. This must
224	* be handled, but we must also make sure PGMGst*Modify doesn't make
225	* unnecessary modifications.
226	*
227	* Allocation points:
228	* - PGMPhysSimpleWriteGCPhys and PGMPhysWrite.
229	* - Replacing a zero page mapping at \#PF.
230	* - Replacing a shared page mapping at \#PF.
231	* - ROM registration (currently MMR3RomRegister).
232	* - VM restore (pgmR3Load).
233	*
234	* For the first three it would make sense to keep a few pages handy
235	* until we've reached the max memory commitment for the VM.
236	*
237	* For the ROM registration, we know exactly how many pages we need
238	* and will request these from ring-0. For restore, we will save
239	* the number of non-zero pages in the saved state and allocate
240	* them up front. This would allow the ring-0 component to refuse
241	* the request if the isn't sufficient memory available for VM use.
242	*
243	* Btw. for both ROM and restore allocations we won't be requiring
244	* zeroed pages as they are going to be filled instantly.
245	*
246	*
247	* @subsection subsec_pgmPhys_FreePage Freeing a page
248	*
249	* There are a few points where a page can be freed:
250	* - After being replaced by the zero page.
251	* - After being replaced by a shared page.
252	* - After being ballooned by the guest additions.
253	* - At reset.
254	* - At restore.
255	*
256	* When freeing one or more pages they will be returned to the ring-0
257	* component and replaced by the zero page.
258	*
259	* The reasoning for clearing out all the pages on reset is that it will
260	* return us to the exact same state as on power on, and may thereby help
261	* us reduce the memory load on the system. Further it might have a
262	* (temporary) positive influence on memory fragmentation (@see subsec_pgmPhys_Fragmentation).
263	*
264	* On restore, as mention under the allocation topic, pages should be
265	* freed / allocated depending on how many is actually required by the
266	* new VM state. The simplest approach is to do like on reset, and free
267	* all non-ROM pages and then allocate what we need.
268	*
269	* A measure to prevent some fragmentation, would be to let each allocation
270	* chunk have some affinity towards the VM having allocated the most pages
271	* from it. Also, try make sure to allocate from allocation chunks that
272	* are almost full. Admittedly, both these measures might work counter to
273	* our intentions and its probably not worth putting a lot of effort,
274	* cpu time or memory into this.
275	*
276	*
277	* @subsection subsec_pgmPhys_SharePage Sharing a page
278	*
279	* The basic idea is that there there will be a idle priority kernel
280	* thread walking the non-shared VM pages hashing them and looking for
281	* pages with the same checksum. If such pages are found, it will compare
282	* them byte-by-byte to see if they actually are identical. If found to be
283	* identical it will allocate a shared page, copy the content, check that
284	* the page didn't change while doing this, and finally request both the
285	* VMs to use the shared page instead. If the page is all zeros (special
286	* checksum and byte-by-byte check) it will request the VM that owns it
287	* to replace it with the zero page.
288	*
289	* To make this efficient, we will have to make sure not to try share a page
290	* that will change its contents soon. This part requires the most work.
291	* A simple idea would be to request the VM to write monitor the page for
292	* a while to make sure it isn't modified any time soon. Also, it may
293	* make sense to skip pages that are being write monitored since this
294	* information is readily available to the thread if it works on the
295	* per-VM guest memory structures (presently called PGMRAMRANGE).
296	*
297	*
298	* @subsection subsec_pgmPhys_Fragmentation Fragmentation Concerns and Counter Measures
299	*
300	* The pages are organized in allocation chunks in ring-0, this is a necessity
301	* if we wish to have an OS agnostic approach to this whole thing. (On Linux we
302	* could easily work on a page-by-page basis if we liked. Whether this is possible
303	* or efficient on NT I don't quite know.) Fragmentation within these chunks may
304	* become a problem as part of the idea here is that we wish to return memory to
305	* the host system.
306	*
307	* For instance, starting two VMs at the same time, they will both allocate the
308	* guest memory on-demand and if permitted their page allocations will be
309	* intermixed. Shut down one of the two VMs and it will be difficult to return
310	* any memory to the host system because the page allocation for the two VMs are
311	* mixed up in the same allocation chunks.
312	*
313	* To further complicate matters, when pages are freed because they have been
314	* ballooned or become shared/zero the whole idea is that the page is supposed
315	* to be reused by another VM or returned to the host system. This will cause
316	* allocation chunks to contain pages belonging to different VMs and prevent
317	* returning memory to the host when one of those VM shuts down.
318	*
319	* The only way to really deal with this problem is to move pages. This can
320	* either be done at VM shutdown and or by the idle priority worker thread
321	* that will be responsible for finding sharable/zero pages. The mechanisms
322	* involved for coercing a VM to move a page (or to do it for it) will be
323	* the same as when telling it to share/zero a page.
324	*
325	*
326	* @subsection subsec_pgmPhys_Tracking Tracking Structures And Their Cost
327	*
328	* There's a difficult balance between keeping the per-page tracking structures
329	* (global and guest page) easy to use and keeping them from eating too much
330	* memory. We have limited virtual memory resources available when operating in
331	* 32-bit kernel space (on 64-bit there'll it's quite a different story). The
332	* tracking structures will be attemted designed such that we can deal with up
333	* to 32GB of memory on a 32-bit system and essentially unlimited on 64-bit ones.
334	*
335	*
336	* @subsubsection subsubsec_pgmPhys_Tracking_Kernel Kernel Space
337	*
338	* @see pg_GMM
339	*
340	* @subsubsection subsubsec_pgmPhys_Tracking_PerVM Per-VM
341	*
342	* Fixed info is the physical address of the page (HCPhys) and the page id
343	* (described above). Theoretically we'll need 48(-12) bits for the HCPhys part.
344	* Today we've restricting ourselves to 40(-12) bits because this is the current
345	* restrictions of all AMD64 implementations (I think Barcelona will up this
346	* to 48(-12) bits, not that it really matters) and I needed the bits for
347	* tracking mappings of a page. 48-12 = 36. That leaves 28 bits, which means a
348	* decent range for the page id: 2^(28+12) = 1024TB.
349	*
350	* In additions to these, we'll have to keep maintaining the page flags as we
351	* currently do. Although it wouldn't harm to optimize these quite a bit, like
352	* for instance the ROM shouldn't depend on having a write handler installed
353	* in order for it to become read-only. A RO/RW bit should be considered so
354	* that the page syncing code doesn't have to mess about checking multiple
355	* flag combinations (ROM \|\| RW handler \|\| write monitored) in order to
356	* figure out how to setup a shadow PTE. But this of course, is second
357	* priority at present. Current this requires 12 bits, but could probably
358	* be optimized to ~8.
359	*
360	* Then there's the 24 bits used to track which shadow page tables are
361	* currently mapping a page for the purpose of speeding up physical
362	* access handlers, and thereby the page pool cache. More bit for this
363	* purpose wouldn't hurt IIRC.
364	*
365	* Then there is a new bit in which we need to record what kind of page
366	* this is, shared, zero, normal or write-monitored-normal. This'll
367	* require 2 bits. One bit might be needed for indicating whether a
368	* write monitored page has been written to. And yet another one or
369	* two for tracking migration status. 3-4 bits total then.
370	*
371	* Whatever is left will can be used to record the sharabilitiy of a
372	* page. The page checksum will not be stored in the per-VM table as
373	* the idle thread will not be permitted to do modifications to it.
374	* It will instead have to keep its own working set of potentially
375	* shareable pages and their check sums and stuff.
376	*
377	* For the present we'll keep the current packing of the
378	* PGMRAMRANGE::aHCPhys to keep the changes simple, only of course,
379	* we'll have to change it to a struct with a total of 128-bits at
380	* our disposal.
381	*
382	* The initial layout will be like this:
383	* @verbatim
384	RTHCPHYS HCPhys; The current stuff.
385	63:40 Current shadow PT tracking stuff.
386	39:12 The physical page frame number.
387	11:0 The current flags.
388	uint32_t u28PageId : 28; The page id.
389	uint32_t u2State : 2; The page state { zero, shared, normal, write monitored }.
390	uint32_t fWrittenTo : 1; Whether a write monitored page was written to.
391	uint32_t u1Reserved : 1; Reserved for later.
392	uint32_t u32Reserved; Reserved for later, mostly sharing stats.
393	@endverbatim
394	*
395	* The final layout will be something like this:
396	* @verbatim
397	RTHCPHYS HCPhys; The current stuff.
398	63:48 High page id (12+).
399	47:12 The physical page frame number.
400	11:0 Low page id.
401	uint32_t fReadOnly : 1; Whether it's readonly page (rom or monitored in some way).
402	uint32_t u3Type : 3; The page type {RESERVED, MMIO, MMIO2, ROM, shadowed ROM, RAM}.
403	uint32_t u2PhysMon : 2; Physical access handler type {none, read, write, all}.
404	uint32_t u2VirtMon : 2; Virtual access handler type {none, read, write, all}..
405	uint32_t u2State : 2; The page state { zero, shared, normal, write monitored }.
406	uint32_t fWrittenTo : 1; Whether a write monitored page was written to.
407	uint32_t u20Reserved : 20; Reserved for later, mostly sharing stats.
408	uint32_t u32Tracking; The shadow PT tracking stuff, roughly.
409	@endverbatim
410	*
411	* Cost wise, this means we'll double the cost for guest memory. There isn't anyway
412	* around that I'm afraid. It means that the cost of dealing out 32GB of memory
413	* to one or more VMs is: (32GB >> PAGE_SHIFT) * 16 bytes, or 128MBs. Or another
414	* example, the VM heap cost when assigning 1GB to a VM will be: 4MB.
415	*
416	* A couple of cost examples for the total cost per-VM + kernel.
417	* 32-bit Windows and 32-bit linux:
418	* 1GB guest ram, 256K pages: 4MB + 2MB(+) = 6MB
419	* 4GB guest ram, 1M pages: 16MB + 8MB(+) = 24MB
420	* 32GB guest ram, 8M pages: 128MB + 64MB(+) = 192MB
421	* 64-bit Windows and 64-bit linux:
422	* 1GB guest ram, 256K pages: 4MB + 3MB(+) = 7MB
423	* 4GB guest ram, 1M pages: 16MB + 12MB(+) = 28MB
424	* 32GB guest ram, 8M pages: 128MB + 96MB(+) = 224MB
425	*
426	* UPDATE - 2007-09-27:
427	* Will need a ballooned flag/state too because we cannot
428	* trust the guest 100% and reporting the same page as ballooned more
429	* than once will put the GMM off balance.
430	*
431	*
432	* @subsection subsec_pgmPhys_Serializing Serializing Access
433	*
434	* Initially, we'll try a simple scheme:
435	*
436	* - The per-VM RAM tracking structures (PGMRAMRANGE) is only modified
437	* by the EMT thread of that VM while in the pgm critsect.
438	* - Other threads in the VM process that needs to make reliable use of
439	* the per-VM RAM tracking structures will enter the critsect.
440	* - No process external thread or kernel thread will ever try enter
441	* the pgm critical section, as that just won't work.
442	* - The idle thread (and similar threads) doesn't not need 100% reliable
443	* data when performing it tasks as the EMT thread will be the one to
444	* do the actual changes later anyway. So, as long as it only accesses
445	* the main ram range, it can do so by somehow preventing the VM from
446	* being destroyed while it works on it...
447	*
448	* - The over-commitment management, including the allocating/freeing
449	* chunks, is serialized by a ring-0 mutex lock (a fast one since the
450	* more mundane mutex implementation is broken on Linux).
451	* - A separeate mutex is protecting the set of allocation chunks so
452	* that pages can be shared or/and freed up while some other VM is
453	* allocating more chunks. This mutex can be take from under the other
454	* one, but not the otherway around.
455	*
456	*
457	* @subsection subsec_pgmPhys_Request VM Request interface
458	*
459	* When in ring-0 it will become necessary to send requests to a VM so it can
460	* for instance move a page while defragmenting during VM destroy. The idle
461	* thread will make use of this interface to request VMs to setup shared
462	* pages and to perform write monitoring of pages.
463	*
464	* I would propose an interface similar to the current VMReq interface, similar
465	* in that it doesn't require locking and that the one sending the request may
466	* wait for completion if it wishes to. This shouldn't be very difficult to
467	* realize.
468	*
469	* The requests themselves are also pretty simple. They are basically:
470	* -# Check that some precondition is still true.
471	* -# Do the update.
472	* -# Update all shadow page tables involved with the page.
473	*
474	* The 3rd step is identical to what we're already doing when updating a
475	* physical handler, see pgmHandlerPhysicalSetRamFlagsAndFlushShadowPTs.
476	*
477	*
478	*
479	* @section sec_pgmPhys_MappingCaches Mapping Caches
480	*
481	* In order to be able to map in and out memory and to be able to support
482	* guest with more RAM than we've got virtual address space, we'll employing
483	* a mapping cache. Normally ring-0 and ring-3 can share the same cache,
484	* however on 32-bit darwin the ring-0 code is running in a different memory
485	* context and therefore needs a separate cache. In raw-mode context we also
486	* need a separate cache. The 32-bit darwin mapping cache and the one for
487	* raw-mode context share a lot of code, see PGMRZDYNMAP.
488	*
489	*
490	* @subsection subsec_pgmPhys_MappingCaches_R3 Ring-3
491	*
492	* We've considered implementing the ring-3 mapping cache page based but found
493	* that this was bother some when one had to take into account TLBs+SMP and
494	* portability (missing the necessary APIs on several platforms). There were
495	* also some performance concerns with this approach which hadn't quite been
496	* worked out.
497	*
498	* Instead, we'll be mapping allocation chunks into the VM process. This simplifies
499	* matters greatly quite a bit since we don't need to invent any new ring-0 stuff,
500	* only some minor RTR0MEMOBJ mapping stuff. The main concern here is that mapping
501	* compared to the previous idea is that mapping or unmapping a 1MB chunk is more
502	* costly than a single page, although how much more costly is uncertain. We'll
503	* try address this by using a very big cache, preferably bigger than the actual
504	* VM RAM size if possible. The current VM RAM sizes should give some idea for
505	* 32-bit boxes, while on 64-bit we can probably get away with employing an
506	* unlimited cache.
507	*
508	* The cache have to parts, as already indicated, the ring-3 side and the
509	* ring-0 side.
510	*
511	* The ring-0 will be tied to the page allocator since it will operate on the
512	* memory objects it contains. It will therefore require the first ring-0 mutex
513	* discussed in @ref subsec_pgmPhys_Serializing. We
514	* some double house keeping wrt to who has mapped what I think, since both
515	* VMMR0.r0 and RTR0MemObj will keep track of mapping relataions
516	*
517	* The ring-3 part will be protected by the pgm critsect. For simplicity, we'll
518	* require anyone that desires to do changes to the mapping cache to do that
519	* from within this critsect. Alternatively, we could employ a separate critsect
520	* for serializing changes to the mapping cache as this would reduce potential
521	* contention with other threads accessing mappings unrelated to the changes
522	* that are in process. We can see about this later, contention will show
523	* up in the statistics anyway, so it'll be simple to tell.
524	*
525	* The organization of the ring-3 part will be very much like how the allocation
526	* chunks are organized in ring-0, that is in an AVL tree by chunk id. To avoid
527	* having to walk the tree all the time, we'll have a couple of lookaside entries
528	* like in we do for I/O ports and MMIO in IOM.
529	*
530	* The simplified flow of a PGMPhysRead/Write function:
531	* -# Enter the PGM critsect.
532	* -# Lookup GCPhys in the ram ranges and get the Page ID.
533	* -# Calc the Allocation Chunk ID from the Page ID.
534	* -# Check the lookaside entries and then the AVL tree for the Chunk ID.
535	* If not found in cache:
536	* -# Call ring-0 and request it to be mapped and supply
537	* a chunk to be unmapped if the cache is maxed out already.
538	* -# Insert the new mapping into the AVL tree (id + R3 address).
539	* -# Update the relevant lookaside entry and return the mapping address.
540	* -# Do the read/write according to monitoring flags and everything.
541	* -# Leave the critsect.
542	*
543	*
544	* @section sec_pgmPhys_Fallback Fallback
545	*
546	* Current all the "second tier" hosts will not support the RTR0MemObjAllocPhysNC
547	* API and thus require a fallback.
548	*
549	* So, when RTR0MemObjAllocPhysNC returns VERR_NOT_SUPPORTED the page allocator
550	* will return to the ring-3 caller (and later ring-0) and asking it to seed
551	* the page allocator with some fresh pages (VERR_GMM_SEED_ME). Ring-3 will
552	* then perform an SUPR3PageAlloc(cbChunk >> PAGE_SHIFT) call and make a
553	* "SeededAllocPages" call to ring-0.
554	*
555	* The first time ring-0 sees the VERR_NOT_SUPPORTED failure it will disable
556	* all page sharing (zero page detection will continue). It will also force
557	* all allocations to come from the VM which seeded the page. Both these
558	* measures are taken to make sure that there will never be any need for
559	* mapping anything into ring-3 - everything will be mapped already.
560	*
561	* Whether we'll continue to use the current MM locked memory management
562	* for this I don't quite know (I'd prefer not to and just ditch that all
563	* togther), we'll see what's simplest to do.
564	*
565	*
566	*
567	* @section sec_pgmPhys_Changes Changes
568	*
569	* Breakdown of the changes involved?
570	*/
571
572	/*******************************************************************************
573	* Header Files *
574	*******************************************************************************/
575	#define LOG_GROUP LOG_GROUP_PGM
576	#include <VBox/dbgf.h>
577	#include <VBox/pgm.h>
578	#include <VBox/cpum.h>
579	#include <VBox/iom.h>
580	#include <VBox/sup.h>
581	#include <VBox/mm.h>
582	#include <VBox/em.h>
583	#include <VBox/stam.h>
584	#include <VBox/rem.h>
585	#include <VBox/selm.h>
586	#include <VBox/ssm.h>
587	#include <VBox/hwaccm.h>
588	#include "PGMInternal.h"
589	#include <VBox/vm.h>
590	#include "PGMInline.h"
591
592	#include <VBox/dbg.h>
593	#include <VBox/param.h>
594	#include <VBox/err.h>
595
596	#include <iprt/asm.h>
597	#include <iprt/asm-amd64-x86.h>
598	#include <iprt/assert.h>
599	#include <iprt/env.h>
600	#include <iprt/mem.h>
601	#include <iprt/file.h>
602	#include <iprt/string.h>
603	#include <iprt/thread.h>
604
605
606	/*******************************************************************************
607	* Internal Functions *
608	*******************************************************************************/
609	static int pgmR3InitPaging(PVM pVM);
610	static int pgmR3InitStats(PVM pVM);
611	static DECLCALLBACK(void) pgmR3PhysInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
612	static DECLCALLBACK(void) pgmR3InfoMode(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
613	static DECLCALLBACK(void) pgmR3InfoCr3(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
614	static DECLCALLBACK(int) pgmR3RelocatePhysHandler(PAVLROGCPHYSNODECORE pNode, void *pvUser);
615	static DECLCALLBACK(int) pgmR3RelocateVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser);
616	static DECLCALLBACK(int) pgmR3RelocateHyperVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser);
617	#ifdef VBOX_STRICT
618	static DECLCALLBACK(void) pgmR3ResetNoMorePhysWritesFlag(PVM pVM, VMSTATE enmState, VMSTATE enmOldState, void *pvUser);
619	#endif
620	static int pgmR3ModeDataInit(PVM pVM, bool fResolveGCAndR0);
621	static void pgmR3ModeDataSwitch(PVM pVM, PVMCPU pVCpu, PGMMODE enmShw, PGMMODE enmGst);
622	static PGMMODE pgmR3CalcShadowMode(PVM pVM, PGMMODE enmGuestMode, SUPPAGINGMODE enmHostMode, PGMMODE enmShadowMode, VMMSWITCHER *penmSwitcher);
623
624	#ifdef VBOX_WITH_DEBUGGER
625	/** @todo Convert the first two commands to 'info' items. */
626	static DECLCALLBACK(int) pgmR3CmdRam(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
627	static DECLCALLBACK(int) pgmR3CmdError(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
628	static DECLCALLBACK(int) pgmR3CmdSync(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
629	static DECLCALLBACK(int) pgmR3CmdSyncAlways(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
630	# ifdef VBOX_STRICT
631	static DECLCALLBACK(int) pgmR3CmdAssertCR3(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
632	# endif
633	static DECLCALLBACK(int) pgmR3CmdPhysToFile(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
634	#endif
635
636
637	/*******************************************************************************
638	* Global Variables *
639	*******************************************************************************/
640	#ifdef VBOX_WITH_DEBUGGER
641	/** Argument descriptors for '.pgmerror' and '.pgmerroroff'. */
642	static const DBGCVARDESC g_aPgmErrorArgs[] =
643	{
644	/* cTimesMin, cTimesMax, enmCategory, fFlags, pszName, pszDescription */
645	{ 0, 1, DBGCVAR_CAT_STRING, 0, "where", "Error injection location." },
646	};
647
648	static const DBGCVARDESC g_aPgmPhysToFileArgs[] =
649	{
650	/* cTimesMin, cTimesMax, enmCategory, fFlags, pszName, pszDescription */
651	{ 1, 1, DBGCVAR_CAT_STRING, 0, "file", "The file name." },
652	{ 0, 1, DBGCVAR_CAT_STRING, 0, "nozero", "If present, zero pages are skipped." },
653	};
654
655	# ifdef DEBUG_sandervl
656	static const DBGCVARDESC g_aPgmCountPhysWritesArgs[] =
657	{
658	/* cTimesMin, cTimesMax, enmCategory, fFlags, pszName, pszDescription */
659	{ 1, 1, DBGCVAR_CAT_STRING, 0, "enabled", "on/off." },
660	{ 1, 1, DBGCVAR_CAT_NUMBER_NO_RANGE, 0, "interval", "Interval in ms." },
661	};
662	# endif
663
664	/** Command descriptors. */
665	static const DBGCCMD g_aCmds[] =
666	{
667	/* pszCmd, cArgsMin, cArgsMax, paArgDesc, cArgDescs, pResultDesc, fFlags, pfnHandler pszSyntax, ....pszDescription */
668	{ "pgmram", 0, 0, NULL, 0, NULL, 0, pgmR3CmdRam, "", "Display the ram ranges." },
669	{ "pgmsync", 0, 0, NULL, 0, NULL, 0, pgmR3CmdSync, "", "Sync the CR3 page." },
670	{ "pgmerror", 0, 1, &g_aPgmErrorArgs[0], 1, NULL, 0, pgmR3CmdError, "", "Enables inject runtime of errors into parts of PGM." },
671	{ "pgmerroroff", 0, 1, &g_aPgmErrorArgs[0], 1, NULL, 0, pgmR3CmdError, "", "Disables inject runtime errors into parts of PGM." },
672	# ifdef VBOX_STRICT
673	{ "pgmassertcr3", 0, 0, NULL, 0, NULL, 0, pgmR3CmdAssertCR3, "", "Check the shadow CR3 mapping." },
674	# if HC_ARCH_BITS == 64
675	{ "pgmcheckduppages", 0, 0, NULL, 0, NULL, 0, pgmR3CmdCheckDuplicatePages, "", "Check for duplicate pages in all running VMs." },
676	{ "pgmsharedmodules", 0, 0, NULL, 0, NULL, 0, pgmR3CmdShowSharedModules, "", "Print shared modules info." },
677	# endif
678	# endif
679	{ "pgmsyncalways", 0, 0, NULL, 0, NULL, 0, pgmR3CmdSyncAlways, "", "Toggle permanent CR3 syncing." },
680	{ "pgmphystofile", 1, 2, &g_aPgmPhysToFileArgs[0], 2, NULL, 0, pgmR3CmdPhysToFile, "", "Save the physical memory to file." },
681	};
682	#endif
683
684
685
686
687	/*
688	* Shadow - 32-bit mode
689	*/
690	#define PGM_SHW_TYPE PGM_TYPE_32BIT
691	#define PGM_SHW_NAME(name) PGM_SHW_NAME_32BIT(name)
692	#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_32BIT_STR(name)
693	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_32BIT_STR(name)
694	#include "PGMShw.h"
695
696	/* Guest - real mode */
697	#define PGM_GST_TYPE PGM_TYPE_REAL
698	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
699	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_REAL_STR(name)
700	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
701	#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_REAL(name)
702	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_32BIT_REAL_STR(name)
703	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_32BIT_REAL_STR(name)
704	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_PHYS
705	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_32BIT_PD_PHYS
706	#include "PGMBth.h"
707	#include "PGMGstDefs.h"
708	#include "PGMGst.h"
709	#undef BTH_PGMPOOLKIND_PT_FOR_PT
710	#undef BTH_PGMPOOLKIND_ROOT
711	#undef PGM_BTH_NAME
712	#undef PGM_BTH_NAME_RC_STR
713	#undef PGM_BTH_NAME_R0_STR
714	#undef PGM_GST_TYPE
715	#undef PGM_GST_NAME
716	#undef PGM_GST_NAME_RC_STR
717	#undef PGM_GST_NAME_R0_STR
718
719	/* Guest - protected mode */
720	#define PGM_GST_TYPE PGM_TYPE_PROT
721	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
722	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PROT_STR(name)
723	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
724	#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_PROT(name)
725	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_32BIT_PROT_STR(name)
726	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_32BIT_PROT_STR(name)
727	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_PHYS
728	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_32BIT_PD_PHYS
729	#include "PGMBth.h"
730	#include "PGMGstDefs.h"
731	#include "PGMGst.h"
732	#undef BTH_PGMPOOLKIND_PT_FOR_PT
733	#undef BTH_PGMPOOLKIND_ROOT
734	#undef PGM_BTH_NAME
735	#undef PGM_BTH_NAME_RC_STR
736	#undef PGM_BTH_NAME_R0_STR
737	#undef PGM_GST_TYPE
738	#undef PGM_GST_NAME
739	#undef PGM_GST_NAME_RC_STR
740	#undef PGM_GST_NAME_R0_STR
741
742	/* Guest - 32-bit mode */
743	#define PGM_GST_TYPE PGM_TYPE_32BIT
744	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
745	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_32BIT_STR(name)
746	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
747	#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_32BIT(name)
748	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_32BIT_32BIT_STR(name)
749	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_32BIT_32BIT_STR(name)
750	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT
751	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB
752	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_32BIT_PD
753	#include "PGMBth.h"
754	#include "PGMGstDefs.h"
755	#include "PGMGst.h"
756	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
757	#undef BTH_PGMPOOLKIND_PT_FOR_PT
758	#undef BTH_PGMPOOLKIND_ROOT
759	#undef PGM_BTH_NAME
760	#undef PGM_BTH_NAME_RC_STR
761	#undef PGM_BTH_NAME_R0_STR
762	#undef PGM_GST_TYPE
763	#undef PGM_GST_NAME
764	#undef PGM_GST_NAME_RC_STR
765	#undef PGM_GST_NAME_R0_STR
766
767	#undef PGM_SHW_TYPE
768	#undef PGM_SHW_NAME
769	#undef PGM_SHW_NAME_RC_STR
770	#undef PGM_SHW_NAME_R0_STR
771
772
773	/*
774	* Shadow - PAE mode
775	*/
776	#define PGM_SHW_TYPE PGM_TYPE_PAE
777	#define PGM_SHW_NAME(name) PGM_SHW_NAME_PAE(name)
778	#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_PAE_STR(name)
779	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_PAE_STR(name)
780	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_REAL(name)
781	#include "PGMShw.h"
782
783	/* Guest - real mode */
784	#define PGM_GST_TYPE PGM_TYPE_REAL
785	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
786	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_REAL_STR(name)
787	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
788	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_REAL(name)
789	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_PAE_REAL_STR(name)
790	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_REAL_STR(name)
791	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
792	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT_PHYS
793	#include "PGMGstDefs.h"
794	#include "PGMBth.h"
795	#undef BTH_PGMPOOLKIND_PT_FOR_PT
796	#undef BTH_PGMPOOLKIND_ROOT
797	#undef PGM_BTH_NAME
798	#undef PGM_BTH_NAME_RC_STR
799	#undef PGM_BTH_NAME_R0_STR
800	#undef PGM_GST_TYPE
801	#undef PGM_GST_NAME
802	#undef PGM_GST_NAME_RC_STR
803	#undef PGM_GST_NAME_R0_STR
804
805	/* Guest - protected mode */
806	#define PGM_GST_TYPE PGM_TYPE_PROT
807	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
808	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PROT_STR(name)
809	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
810	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_PROT(name)
811	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_PAE_PROT_STR(name)
812	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_PROT_STR(name)
813	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
814	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT_PHYS
815	#include "PGMGstDefs.h"
816	#include "PGMBth.h"
817	#undef BTH_PGMPOOLKIND_PT_FOR_PT
818	#undef BTH_PGMPOOLKIND_ROOT
819	#undef PGM_BTH_NAME
820	#undef PGM_BTH_NAME_RC_STR
821	#undef PGM_BTH_NAME_R0_STR
822	#undef PGM_GST_TYPE
823	#undef PGM_GST_NAME
824	#undef PGM_GST_NAME_RC_STR
825	#undef PGM_GST_NAME_R0_STR
826
827	/* Guest - 32-bit mode */
828	#define PGM_GST_TYPE PGM_TYPE_32BIT
829	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
830	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_32BIT_STR(name)
831	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
832	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_32BIT(name)
833	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_PAE_32BIT_STR(name)
834	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_32BIT_STR(name)
835	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_32BIT_PT
836	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB
837	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT_FOR_32BIT
838	#include "PGMGstDefs.h"
839	#include "PGMBth.h"
840	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
841	#undef BTH_PGMPOOLKIND_PT_FOR_PT
842	#undef BTH_PGMPOOLKIND_ROOT
843	#undef PGM_BTH_NAME
844	#undef PGM_BTH_NAME_RC_STR
845	#undef PGM_BTH_NAME_R0_STR
846	#undef PGM_GST_TYPE
847	#undef PGM_GST_NAME
848	#undef PGM_GST_NAME_RC_STR
849	#undef PGM_GST_NAME_R0_STR
850
851	/* Guest - PAE mode */
852	#define PGM_GST_TYPE PGM_TYPE_PAE
853	#define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
854	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PAE_STR(name)
855	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PAE_STR(name)
856	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_PAE(name)
857	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_PAE_PAE_STR(name)
858	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_PAE_STR(name)
859	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
860	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
861	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT
862	#include "PGMBth.h"
863	#include "PGMGstDefs.h"
864	#include "PGMGst.h"
865	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
866	#undef BTH_PGMPOOLKIND_PT_FOR_PT
867	#undef BTH_PGMPOOLKIND_ROOT
868	#undef PGM_BTH_NAME
869	#undef PGM_BTH_NAME_RC_STR
870	#undef PGM_BTH_NAME_R0_STR
871	#undef PGM_GST_TYPE
872	#undef PGM_GST_NAME
873	#undef PGM_GST_NAME_RC_STR
874	#undef PGM_GST_NAME_R0_STR
875
876	#undef PGM_SHW_TYPE
877	#undef PGM_SHW_NAME
878	#undef PGM_SHW_NAME_RC_STR
879	#undef PGM_SHW_NAME_R0_STR
880
881
882	/*
883	* Shadow - AMD64 mode
884	*/
885	#define PGM_SHW_TYPE PGM_TYPE_AMD64
886	#define PGM_SHW_NAME(name) PGM_SHW_NAME_AMD64(name)
887	#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_AMD64_STR(name)
888	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_AMD64_STR(name)
889	#include "PGMShw.h"
890
891	#ifdef VBOX_WITH_64_BITS_GUESTS
892	/* Guest - AMD64 mode */
893	# define PGM_GST_TYPE PGM_TYPE_AMD64
894	# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
895	# define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_AMD64_STR(name)
896	# define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_AMD64_STR(name)
897	# define PGM_BTH_NAME(name) PGM_BTH_NAME_AMD64_AMD64(name)
898	# define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_AMD64_AMD64_STR(name)
899	# define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_AMD64_AMD64_STR(name)
900	# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
901	# define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
902	# define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_64BIT_PML4
903	# include "PGMBth.h"
904	# include "PGMGstDefs.h"
905	# include "PGMGst.h"
906	# undef BTH_PGMPOOLKIND_PT_FOR_BIG
907	# undef BTH_PGMPOOLKIND_PT_FOR_PT
908	# undef BTH_PGMPOOLKIND_ROOT
909	# undef PGM_BTH_NAME
910	# undef PGM_BTH_NAME_RC_STR
911	# undef PGM_BTH_NAME_R0_STR
912	# undef PGM_GST_TYPE
913	# undef PGM_GST_NAME
914	# undef PGM_GST_NAME_RC_STR
915	# undef PGM_GST_NAME_R0_STR
916	#endif /* VBOX_WITH_64_BITS_GUESTS */
917
918	#undef PGM_SHW_TYPE
919	#undef PGM_SHW_NAME
920	#undef PGM_SHW_NAME_RC_STR
921	#undef PGM_SHW_NAME_R0_STR
922
923
924	/*
925	* Shadow - Nested paging mode
926	*/
927	#define PGM_SHW_TYPE PGM_TYPE_NESTED
928	#define PGM_SHW_NAME(name) PGM_SHW_NAME_NESTED(name)
929	#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_NESTED_STR(name)
930	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_NESTED_STR(name)
931	#include "PGMShw.h"
932
933	/* Guest - real mode */
934	#define PGM_GST_TYPE PGM_TYPE_REAL
935	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
936	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_REAL_STR(name)
937	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
938	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_REAL(name)
939	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_REAL_STR(name)
940	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_REAL_STR(name)
941	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
942	#include "PGMGstDefs.h"
943	#include "PGMBth.h"
944	#undef BTH_PGMPOOLKIND_PT_FOR_PT
945	#undef PGM_BTH_NAME
946	#undef PGM_BTH_NAME_RC_STR
947	#undef PGM_BTH_NAME_R0_STR
948	#undef PGM_GST_TYPE
949	#undef PGM_GST_NAME
950	#undef PGM_GST_NAME_RC_STR
951	#undef PGM_GST_NAME_R0_STR
952
953	/* Guest - protected mode */
954	#define PGM_GST_TYPE PGM_TYPE_PROT
955	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
956	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PROT_STR(name)
957	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
958	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_PROT(name)
959	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_PROT_STR(name)
960	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_PROT_STR(name)
961	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
962	#include "PGMGstDefs.h"
963	#include "PGMBth.h"
964	#undef BTH_PGMPOOLKIND_PT_FOR_PT
965	#undef PGM_BTH_NAME
966	#undef PGM_BTH_NAME_RC_STR
967	#undef PGM_BTH_NAME_R0_STR
968	#undef PGM_GST_TYPE
969	#undef PGM_GST_NAME
970	#undef PGM_GST_NAME_RC_STR
971	#undef PGM_GST_NAME_R0_STR
972
973	/* Guest - 32-bit mode */
974	#define PGM_GST_TYPE PGM_TYPE_32BIT
975	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
976	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_32BIT_STR(name)
977	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
978	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_32BIT(name)
979	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_32BIT_STR(name)
980	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_32BIT_STR(name)
981	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_32BIT_PT
982	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB
983	#include "PGMGstDefs.h"
984	#include "PGMBth.h"
985	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
986	#undef BTH_PGMPOOLKIND_PT_FOR_PT
987	#undef PGM_BTH_NAME
988	#undef PGM_BTH_NAME_RC_STR
989	#undef PGM_BTH_NAME_R0_STR
990	#undef PGM_GST_TYPE
991	#undef PGM_GST_NAME
992	#undef PGM_GST_NAME_RC_STR
993	#undef PGM_GST_NAME_R0_STR
994
995	/* Guest - PAE mode */
996	#define PGM_GST_TYPE PGM_TYPE_PAE
997	#define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
998	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PAE_STR(name)
999	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PAE_STR(name)
1000	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_PAE(name)
1001	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_PAE_STR(name)
1002	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_PAE_STR(name)
1003	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
1004	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
1005	#include "PGMGstDefs.h"
1006	#include "PGMBth.h"
1007	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
1008	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1009	#undef PGM_BTH_NAME
1010	#undef PGM_BTH_NAME_RC_STR
1011	#undef PGM_BTH_NAME_R0_STR
1012	#undef PGM_GST_TYPE
1013	#undef PGM_GST_NAME
1014	#undef PGM_GST_NAME_RC_STR
1015	#undef PGM_GST_NAME_R0_STR
1016
1017	#ifdef VBOX_WITH_64_BITS_GUESTS
1018	/* Guest - AMD64 mode */
1019	# define PGM_GST_TYPE PGM_TYPE_AMD64
1020	# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
1021	# define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_AMD64_STR(name)
1022	# define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_AMD64_STR(name)
1023	# define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_AMD64(name)
1024	# define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_AMD64_STR(name)
1025	# define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_AMD64_STR(name)
1026	# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
1027	# define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
1028	# include "PGMGstDefs.h"
1029	# include "PGMBth.h"
1030	# undef BTH_PGMPOOLKIND_PT_FOR_BIG
1031	# undef BTH_PGMPOOLKIND_PT_FOR_PT
1032	# undef PGM_BTH_NAME
1033	# undef PGM_BTH_NAME_RC_STR
1034	# undef PGM_BTH_NAME_R0_STR
1035	# undef PGM_GST_TYPE
1036	# undef PGM_GST_NAME
1037	# undef PGM_GST_NAME_RC_STR
1038	# undef PGM_GST_NAME_R0_STR
1039	#endif /* VBOX_WITH_64_BITS_GUESTS */
1040
1041	#undef PGM_SHW_TYPE
1042	#undef PGM_SHW_NAME
1043	#undef PGM_SHW_NAME_RC_STR
1044	#undef PGM_SHW_NAME_R0_STR
1045
1046
1047	/*
1048	* Shadow - EPT
1049	*/
1050	#define PGM_SHW_TYPE PGM_TYPE_EPT
1051	#define PGM_SHW_NAME(name) PGM_SHW_NAME_EPT(name)
1052	#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_EPT_STR(name)
1053	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_EPT_STR(name)
1054	#include "PGMShw.h"
1055
1056	/* Guest - real mode */
1057	#define PGM_GST_TYPE PGM_TYPE_REAL
1058	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
1059	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_REAL_STR(name)
1060	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
1061	#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_REAL(name)
1062	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_REAL_STR(name)
1063	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_REAL_STR(name)
1064	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
1065	#include "PGMGstDefs.h"
1066	#include "PGMBth.h"
1067	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1068	#undef PGM_BTH_NAME
1069	#undef PGM_BTH_NAME_RC_STR
1070	#undef PGM_BTH_NAME_R0_STR
1071	#undef PGM_GST_TYPE
1072	#undef PGM_GST_NAME
1073	#undef PGM_GST_NAME_RC_STR
1074	#undef PGM_GST_NAME_R0_STR
1075
1076	/* Guest - protected mode */
1077	#define PGM_GST_TYPE PGM_TYPE_PROT
1078	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
1079	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PROT_STR(name)
1080	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
1081	#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_PROT(name)
1082	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_PROT_STR(name)
1083	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_PROT_STR(name)
1084	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
1085	#include "PGMGstDefs.h"
1086	#include "PGMBth.h"
1087	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1088	#undef PGM_BTH_NAME
1089	#undef PGM_BTH_NAME_RC_STR
1090	#undef PGM_BTH_NAME_R0_STR
1091	#undef PGM_GST_TYPE
1092	#undef PGM_GST_NAME
1093	#undef PGM_GST_NAME_RC_STR
1094	#undef PGM_GST_NAME_R0_STR
1095
1096	/* Guest - 32-bit mode */
1097	#define PGM_GST_TYPE PGM_TYPE_32BIT
1098	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
1099	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_32BIT_STR(name)
1100	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
1101	#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_32BIT(name)
1102	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_32BIT_STR(name)
1103	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_32BIT_STR(name)
1104	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_32BIT_PT
1105	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB
1106	#include "PGMGstDefs.h"
1107	#include "PGMBth.h"
1108	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
1109	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1110	#undef PGM_BTH_NAME
1111	#undef PGM_BTH_NAME_RC_STR
1112	#undef PGM_BTH_NAME_R0_STR
1113	#undef PGM_GST_TYPE
1114	#undef PGM_GST_NAME
1115	#undef PGM_GST_NAME_RC_STR
1116	#undef PGM_GST_NAME_R0_STR
1117
1118	/* Guest - PAE mode */
1119	#define PGM_GST_TYPE PGM_TYPE_PAE
1120	#define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
1121	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PAE_STR(name)
1122	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PAE_STR(name)
1123	#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_PAE(name)
1124	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_PAE_STR(name)
1125	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_PAE_STR(name)
1126	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
1127	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
1128	#include "PGMGstDefs.h"
1129	#include "PGMBth.h"
1130	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
1131	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1132	#undef PGM_BTH_NAME
1133	#undef PGM_BTH_NAME_RC_STR
1134	#undef PGM_BTH_NAME_R0_STR
1135	#undef PGM_GST_TYPE
1136	#undef PGM_GST_NAME
1137	#undef PGM_GST_NAME_RC_STR
1138	#undef PGM_GST_NAME_R0_STR
1139
1140	#ifdef VBOX_WITH_64_BITS_GUESTS
1141	/* Guest - AMD64 mode */
1142	# define PGM_GST_TYPE PGM_TYPE_AMD64
1143	# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
1144	# define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_AMD64_STR(name)
1145	# define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_AMD64_STR(name)
1146	# define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_AMD64(name)
1147	# define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_AMD64_STR(name)
1148	# define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_AMD64_STR(name)
1149	# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
1150	# define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
1151	# include "PGMGstDefs.h"
1152	# include "PGMBth.h"
1153	# undef BTH_PGMPOOLKIND_PT_FOR_BIG
1154	# undef BTH_PGMPOOLKIND_PT_FOR_PT
1155	# undef PGM_BTH_NAME
1156	# undef PGM_BTH_NAME_RC_STR
1157	# undef PGM_BTH_NAME_R0_STR
1158	# undef PGM_GST_TYPE
1159	# undef PGM_GST_NAME
1160	# undef PGM_GST_NAME_RC_STR
1161	# undef PGM_GST_NAME_R0_STR
1162	#endif /* VBOX_WITH_64_BITS_GUESTS */
1163
1164	#undef PGM_SHW_TYPE
1165	#undef PGM_SHW_NAME
1166	#undef PGM_SHW_NAME_RC_STR
1167	#undef PGM_SHW_NAME_R0_STR
1168
1169
1170
1171	/**
1172	* Initiates the paging of VM.
1173	*
1174	* @returns VBox status code.
1175	* @param pVM Pointer to VM structure.
1176	*/
1177	VMMR3DECL(int) PGMR3Init(PVM pVM)
1178	{
1179	LogFlow(("PGMR3Init:\n"));
1180	PCFGMNODE pCfgPGM = CFGMR3GetChild(CFGMR3GetRoot(pVM), "/PGM");
1181	int rc;
1182
1183	/*
1184	* Assert alignment and sizes.
1185	*/
1186	AssertCompile(sizeof(pVM->pgm.s) <= sizeof(pVM->pgm.padding));
1187	AssertCompile(sizeof(pVM->aCpus[0].pgm.s) <= sizeof(pVM->aCpus[0].pgm.padding));
1188	AssertCompileMemberAlignment(PGM, CritSect, sizeof(uintptr_t));
1189
1190	/*
1191	* Init the structure.
1192	*/
1193	#ifdef PGM_WITHOUT_MAPPINGS
1194	pVM->pgm.s.fMappingsDisabled = true;
1195	#endif
1196	pVM->pgm.s.offVM = RT_OFFSETOF(VM, pgm.s);
1197	pVM->pgm.s.offVCpuPGM = RT_OFFSETOF(VMCPU, pgm.s);
1198
1199	/* Init the per-CPU part. */
1200	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1201	{
1202	PVMCPU pVCpu = &pVM->aCpus[idCpu];
1203	PPGMCPU pPGM = &pVCpu->pgm.s;
1204
1205	pPGM->offVM = (uintptr_t)&pVCpu->pgm.s - (uintptr_t)pVM;
1206	pPGM->offVCpu = RT_OFFSETOF(VMCPU, pgm.s);
1207	pPGM->offPGM = (uintptr_t)&pVCpu->pgm.s - (uintptr_t)&pVM->pgm.s;
1208
1209	pPGM->enmShadowMode = PGMMODE_INVALID;
1210	pPGM->enmGuestMode = PGMMODE_INVALID;
1211
1212	pPGM->GCPhysCR3 = NIL_RTGCPHYS;
1213
1214	pPGM->pGst32BitPdR3 = NULL;
1215	pPGM->pGstPaePdptR3 = NULL;
1216	pPGM->pGstAmd64Pml4R3 = NULL;
1217	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
1218	pPGM->pGst32BitPdR0 = NIL_RTR0PTR;
1219	pPGM->pGstPaePdptR0 = NIL_RTR0PTR;
1220	pPGM->pGstAmd64Pml4R0 = NIL_RTR0PTR;
1221	#endif
1222	pPGM->pGst32BitPdRC = NIL_RTRCPTR;
1223	pPGM->pGstPaePdptRC = NIL_RTRCPTR;
1224	for (unsigned i = 0; i < RT_ELEMENTS(pVCpu->pgm.s.apGstPaePDsR3); i++)
1225	{
1226	pPGM->apGstPaePDsR3[i] = NULL;
1227	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
1228	pPGM->apGstPaePDsR0[i] = NIL_RTR0PTR;
1229	#endif
1230	pPGM->apGstPaePDsRC[i] = NIL_RTRCPTR;
1231	pPGM->aGCPhysGstPaePDs[i] = NIL_RTGCPHYS;
1232	pPGM->aGCPhysGstPaePDsMonitored[i] = NIL_RTGCPHYS;
1233	}
1234
1235	pPGM->fA20Enabled = true;
1236	}
1237
1238	pVM->pgm.s.enmHostMode = SUPPAGINGMODE_INVALID;
1239	pVM->pgm.s.GCPhys4MBPSEMask = RT_BIT_64(32) - 1; /* default; checked later */
1240	pVM->pgm.s.GCPtrPrevRamRangeMapping = MM_HYPER_AREA_ADDRESS;
1241
1242	rc = CFGMR3QueryBoolDef(CFGMR3GetRoot(pVM), "RamPreAlloc", &pVM->pgm.s.fRamPreAlloc,
1243	#ifdef VBOX_WITH_PREALLOC_RAM_BY_DEFAULT
1244	true
1245	#else
1246	false
1247	#endif
1248	);
1249	AssertLogRelRCReturn(rc, rc);
1250
1251	#ifdef PGM_WITH_LARGE_ADDRESS_SPACE_ON_32_BIT_HOST
1252	rc = CFGMR3QueryU32Def(pCfgPGM, "MaxRing3Chunks", &pVM->pgm.s.ChunkR3Map.cMax, _1G / GMM_CHUNK_SIZE);
1253	#else
1254	rc = CFGMR3QueryU32Def(pCfgPGM, "MaxRing3Chunks", &pVM->pgm.s.ChunkR3Map.cMax, UINT32_MAX);
1255	#endif
1256	AssertLogRelRCReturn(rc, rc);
1257	for (uint32_t i = 0; i < RT_ELEMENTS(pVM->pgm.s.ChunkR3Map.Tlb.aEntries); i++)
1258	pVM->pgm.s.ChunkR3Map.Tlb.aEntries[i].idChunk = NIL_GMM_CHUNKID;
1259
1260	/*
1261	* Get the configured RAM size - to estimate saved state size.
1262	*/
1263	uint64_t cbRam;
1264	rc = CFGMR3QueryU64(CFGMR3GetRoot(pVM), "RamSize", &cbRam);
1265	if (rc == VERR_CFGM_VALUE_NOT_FOUND)
1266	cbRam = 0;
1267	else if (RT_SUCCESS(rc))
1268	{
1269	if (cbRam < PAGE_SIZE)
1270	cbRam = 0;
1271	cbRam = RT_ALIGN_64(cbRam, PAGE_SIZE);
1272	}
1273	else
1274	{
1275	AssertMsgFailed(("Configuration error: Failed to query integer \"RamSize\", rc=%Rrc.\n", rc));
1276	return rc;
1277	}
1278
1279	#ifdef VBOX_WITH_STATISTICS
1280	/*
1281	* Allocate memory for the statistics before someone tries to use them.
1282	*/
1283	size_t cbTotalStats = RT_ALIGN_Z(sizeof(PGMSTATS), 64) + RT_ALIGN_Z(sizeof(PGMCPUSTATS), 64) * pVM->cCpus;
1284	void *pv;
1285	rc = MMHyperAlloc(pVM, RT_ALIGN_Z(cbTotalStats, PAGE_SIZE), PAGE_SIZE, MM_TAG_PGM, &pv);
1286	AssertRCReturn(rc, rc);
1287
1288	pVM->pgm.s.pStatsR3 = (PGMSTATS *)pv;
1289	pVM->pgm.s.pStatsR0 = MMHyperCCToR0(pVM, pv);
1290	pVM->pgm.s.pStatsRC = MMHyperCCToRC(pVM, pv);
1291	pv = (uint8_t *)pv + RT_ALIGN_Z(sizeof(PGMSTATS), 64);
1292
1293	for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
1294	{
1295	pVM->aCpus[iCpu].pgm.s.pStatsR3 = (PGMCPUSTATS *)pv;
1296	pVM->aCpus[iCpu].pgm.s.pStatsR0 = MMHyperCCToR0(pVM, pv);
1297	pVM->aCpus[iCpu].pgm.s.pStatsRC = MMHyperCCToRC(pVM, pv);
1298
1299	pv = (uint8_t *)pv + RT_ALIGN_Z(sizeof(PGMCPUSTATS), 64);
1300	}
1301	#endif /* VBOX_WITH_STATISTICS */
1302
1303	/*
1304	* Register callbacks, string formatters and the saved state data unit.
1305	*/
1306	#ifdef VBOX_STRICT
1307	VMR3AtStateRegister(pVM, pgmR3ResetNoMorePhysWritesFlag, NULL);
1308	#endif
1309	PGMRegisterStringFormatTypes();
1310
1311	rc = pgmR3InitSavedState(pVM, cbRam);
1312	if (RT_FAILURE(rc))
1313	return rc;
1314
1315	/*
1316	* Initialize the PGM critical section and flush the phys TLBs
1317	*/
1318	rc = PDMR3CritSectInit(pVM, &pVM->pgm.s.CritSect, RT_SRC_POS, "PGM");
1319	AssertRCReturn(rc, rc);
1320
1321	PGMR3PhysChunkInvalidateTLB(pVM);
1322	PGMPhysInvalidatePageMapTLB(pVM);
1323
1324	/*
1325	* For the time being we sport a full set of handy pages in addition to the base
1326	* memory to simplify things.
1327	*/
1328	rc = MMR3ReserveHandyPages(pVM, RT_ELEMENTS(pVM->pgm.s.aHandyPages)); /** @todo this should be changed to PGM_HANDY_PAGES_MIN but this needs proper testing... */
1329	AssertRCReturn(rc, rc);
1330
1331	/*
1332	* Trees
1333	*/
1334	rc = MMHyperAlloc(pVM, sizeof(PGMTREES), 0, MM_TAG_PGM, (void **)&pVM->pgm.s.pTreesR3);
1335	if (RT_SUCCESS(rc))
1336	{
1337	pVM->pgm.s.pTreesR0 = MMHyperR3ToR0(pVM, pVM->pgm.s.pTreesR3);
1338	pVM->pgm.s.pTreesRC = MMHyperR3ToRC(pVM, pVM->pgm.s.pTreesR3);
1339
1340	/*
1341	* Allocate the zero page.
1342	*/
1343	rc = MMHyperAlloc(pVM, PAGE_SIZE, PAGE_SIZE, MM_TAG_PGM, &pVM->pgm.s.pvZeroPgR3);
1344	}
1345	if (RT_SUCCESS(rc))
1346	{
1347	pVM->pgm.s.pvZeroPgRC = MMHyperR3ToRC(pVM, pVM->pgm.s.pvZeroPgR3);
1348	pVM->pgm.s.pvZeroPgR0 = MMHyperR3ToR0(pVM, pVM->pgm.s.pvZeroPgR3);
1349	pVM->pgm.s.HCPhysZeroPg = MMR3HyperHCVirt2HCPhys(pVM, pVM->pgm.s.pvZeroPgR3);
1350	AssertRelease(pVM->pgm.s.HCPhysZeroPg != NIL_RTHCPHYS);
1351
1352	/*
1353	* Allocate the invalid MMIO page.
1354	* (The invalid bits in HCPhysInvMmioPg are set later on init complete.)
1355	*/
1356	rc = MMHyperAlloc(pVM, PAGE_SIZE, PAGE_SIZE, MM_TAG_PGM, &pVM->pgm.s.pvMmioPgR3);
1357	}
1358	if (RT_SUCCESS(rc))
1359	{
1360	ASMMemFill32(pVM->pgm.s.pvMmioPgR3, PAGE_SIZE, 0xfeedface);
1361	pVM->pgm.s.HCPhysMmioPg = MMR3HyperHCVirt2HCPhys(pVM, pVM->pgm.s.pvMmioPgR3);
1362	AssertRelease(pVM->pgm.s.HCPhysMmioPg != NIL_RTHCPHYS);
1363	pVM->pgm.s.HCPhysInvMmioPg = pVM->pgm.s.HCPhysMmioPg;
1364
1365	/*
1366	* Init the paging.
1367	*/
1368	rc = pgmR3InitPaging(pVM);
1369	}
1370	if (RT_SUCCESS(rc))
1371	{
1372	/*
1373	* Init the page pool.
1374	*/
1375	rc = pgmR3PoolInit(pVM);
1376	}
1377	if (RT_SUCCESS(rc))
1378	{
1379	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1380	{
1381	PVMCPU pVCpu = &pVM->aCpus[i];
1382	rc = PGMR3ChangeMode(pVM, pVCpu, PGMMODE_REAL);
1383	if (RT_FAILURE(rc))
1384	break;
1385	}
1386	}
1387
1388	if (RT_SUCCESS(rc))
1389	{
1390	/*
1391	* Info & statistics
1392	*/
1393	DBGFR3InfoRegisterInternal(pVM, "mode",
1394	"Shows the current paging mode. "
1395	"Recognizes 'all', 'guest', 'shadow' and 'host' as arguments, defaulting to 'all' if nothing's given.",
1396	pgmR3InfoMode);
1397	DBGFR3InfoRegisterInternal(pVM, "pgmcr3",
1398	"Dumps all the entries in the top level paging table. No arguments.",
1399	pgmR3InfoCr3);
1400	DBGFR3InfoRegisterInternal(pVM, "phys",
1401	"Dumps all the physical address ranges. No arguments.",
1402	pgmR3PhysInfo);
1403	DBGFR3InfoRegisterInternal(pVM, "handlers",
1404	"Dumps physical, virtual and hyper virtual handlers. "
1405	"Pass 'phys', 'virt', 'hyper' as argument if only one kind is wanted."
1406	"Add 'nost' if the statistics are unwanted, use together with 'all' or explicit selection.",
1407	pgmR3InfoHandlers);
1408	DBGFR3InfoRegisterInternal(pVM, "mappings",
1409	"Dumps guest mappings.",
1410	pgmR3MapInfo);
1411
1412	pgmR3InitStats(pVM);
1413
1414	#ifdef VBOX_WITH_DEBUGGER
1415	/*
1416	* Debugger commands.
1417	*/
1418	static bool s_fRegisteredCmds = false;
1419	if (!s_fRegisteredCmds)
1420	{
1421	int rc2 = DBGCRegisterCommands(&g_aCmds[0], RT_ELEMENTS(g_aCmds));
1422	if (RT_SUCCESS(rc2))
1423	s_fRegisteredCmds = true;
1424	}
1425	#endif
1426	return VINF_SUCCESS;
1427	}
1428
1429	/* Almost no cleanup necessary, MM frees all memory. */
1430	PDMR3CritSectDelete(&pVM->pgm.s.CritSect);
1431
1432	return rc;
1433	}
1434
1435
1436	/**
1437	* Initializes the per-VCPU PGM.
1438	*
1439	* @returns VBox status code.
1440	* @param pVM The VM to operate on.
1441	*/
1442	VMMR3DECL(int) PGMR3InitCPU(PVM pVM)
1443	{
1444	LogFlow(("PGMR3InitCPU\n"));
1445	return VINF_SUCCESS;
1446	}
1447
1448
1449	/**
1450	* Init paging.
1451	*
1452	* Since we need to check what mode the host is operating in before we can choose
1453	* the right paging functions for the host we have to delay this until R0 has
1454	* been initialized.
1455	*
1456	* @returns VBox status code.
1457	* @param pVM VM handle.
1458	*/
1459	static int pgmR3InitPaging(PVM pVM)
1460	{
1461	/*
1462	* Force a recalculation of modes and switcher so everyone gets notified.
1463	*/
1464	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1465	{
1466	PVMCPU pVCpu = &pVM->aCpus[i];
1467
1468	pVCpu->pgm.s.enmShadowMode = PGMMODE_INVALID;
1469	pVCpu->pgm.s.enmGuestMode = PGMMODE_INVALID;
1470	}
1471
1472	pVM->pgm.s.enmHostMode = SUPPAGINGMODE_INVALID;
1473
1474	/*
1475	* Allocate static mapping space for whatever the cr3 register
1476	* points to and in the case of PAE mode to the 4 PDs.
1477	*/
1478	int rc = MMR3HyperReserve(pVM, PAGE_SIZE * 5, "CR3 mapping", &pVM->pgm.s.GCPtrCR3Mapping);
1479	if (RT_FAILURE(rc))
1480	{
1481	AssertMsgFailed(("Failed to reserve two pages for cr mapping in HMA, rc=%Rrc\n", rc));
1482	return rc;
1483	}
1484	MMR3HyperReserve(pVM, PAGE_SIZE, "fence", NULL);
1485
1486	/*
1487	* Allocate pages for the three possible intermediate contexts
1488	* (AMD64, PAE and plain 32-Bit). We maintain all three contexts
1489	* for the sake of simplicity. The AMD64 uses the PAE for the
1490	* lower levels, making the total number of pages 11 (3 + 7 + 1).
1491	*
1492	* We assume that two page tables will be enought for the core code
1493	* mappings (HC virtual and identity).
1494	*/
1495	pVM->pgm.s.pInterPD = (PX86PD)MMR3PageAllocLow(pVM); AssertReturn(pVM->pgm.s.pInterPD, VERR_NO_PAGE_MEMORY);
1496	pVM->pgm.s.apInterPTs[0] = (PX86PT)MMR3PageAllocLow(pVM); AssertReturn(pVM->pgm.s.apInterPTs[0], VERR_NO_PAGE_MEMORY);
1497	pVM->pgm.s.apInterPTs[1] = (PX86PT)MMR3PageAllocLow(pVM); AssertReturn(pVM->pgm.s.apInterPTs[1], VERR_NO_PAGE_MEMORY);
1498	pVM->pgm.s.apInterPaePTs[0] = (PX86PTPAE)MMR3PageAlloc(pVM); AssertReturn(pVM->pgm.s.apInterPaePTs[0], VERR_NO_PAGE_MEMORY);
1499	pVM->pgm.s.apInterPaePTs[1] = (PX86PTPAE)MMR3PageAlloc(pVM); AssertReturn(pVM->pgm.s.apInterPaePTs[1], VERR_NO_PAGE_MEMORY);
1500	pVM->pgm.s.apInterPaePDs[0] = (PX86PDPAE)MMR3PageAlloc(pVM); AssertReturn(pVM->pgm.s.apInterPaePDs[0], VERR_NO_PAGE_MEMORY);
1501	pVM->pgm.s.apInterPaePDs[1] = (PX86PDPAE)MMR3PageAlloc(pVM); AssertReturn(pVM->pgm.s.apInterPaePDs[1], VERR_NO_PAGE_MEMORY);
1502	pVM->pgm.s.apInterPaePDs[2] = (PX86PDPAE)MMR3PageAlloc(pVM); AssertReturn(pVM->pgm.s.apInterPaePDs[2], VERR_NO_PAGE_MEMORY);
1503	pVM->pgm.s.apInterPaePDs[3] = (PX86PDPAE)MMR3PageAlloc(pVM); AssertReturn(pVM->pgm.s.apInterPaePDs[3], VERR_NO_PAGE_MEMORY);
1504	pVM->pgm.s.pInterPaePDPT = (PX86PDPT)MMR3PageAllocLow(pVM); AssertReturn(pVM->pgm.s.pInterPaePDPT, VERR_NO_PAGE_MEMORY);
1505	pVM->pgm.s.pInterPaePDPT64 = (PX86PDPT)MMR3PageAllocLow(pVM); AssertReturn(pVM->pgm.s.pInterPaePDPT64, VERR_NO_PAGE_MEMORY);
1506	pVM->pgm.s.pInterPaePML4 = (PX86PML4)MMR3PageAllocLow(pVM); AssertReturn(pVM->pgm.s.pInterPaePML4, VERR_NO_PAGE_MEMORY);
1507
1508	pVM->pgm.s.HCPhysInterPD = MMPage2Phys(pVM, pVM->pgm.s.pInterPD);
1509	AssertRelease(pVM->pgm.s.HCPhysInterPD != NIL_RTHCPHYS && !(pVM->pgm.s.HCPhysInterPD & PAGE_OFFSET_MASK));
1510	pVM->pgm.s.HCPhysInterPaePDPT = MMPage2Phys(pVM, pVM->pgm.s.pInterPaePDPT);
1511	AssertRelease(pVM->pgm.s.HCPhysInterPaePDPT != NIL_RTHCPHYS && !(pVM->pgm.s.HCPhysInterPaePDPT & PAGE_OFFSET_MASK));
1512	pVM->pgm.s.HCPhysInterPaePML4 = MMPage2Phys(pVM, pVM->pgm.s.pInterPaePML4);
1513	AssertRelease(pVM->pgm.s.HCPhysInterPaePML4 != NIL_RTHCPHYS && !(pVM->pgm.s.HCPhysInterPaePML4 & PAGE_OFFSET_MASK) && pVM->pgm.s.HCPhysInterPaePML4 < 0xffffffff);
1514
1515	/*
1516	* Initialize the pages, setting up the PML4 and PDPT for repetitive 4GB action.
1517	*/
1518	ASMMemZeroPage(pVM->pgm.s.pInterPD);
1519	ASMMemZeroPage(pVM->pgm.s.apInterPTs[0]);
1520	ASMMemZeroPage(pVM->pgm.s.apInterPTs[1]);
1521
1522	ASMMemZeroPage(pVM->pgm.s.apInterPaePTs[0]);
1523	ASMMemZeroPage(pVM->pgm.s.apInterPaePTs[1]);
1524
1525	ASMMemZeroPage(pVM->pgm.s.pInterPaePDPT);
1526	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.apInterPaePDs); i++)
1527	{
1528	ASMMemZeroPage(pVM->pgm.s.apInterPaePDs[i]);
1529	pVM->pgm.s.pInterPaePDPT->a[i].u = X86_PDPE_P \| PGM_PLXFLAGS_PERMANENT
1530	\| MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[i]);
1531	}
1532
1533	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.pInterPaePDPT64->a); i++)
1534	{
1535	const unsigned iPD = i % RT_ELEMENTS(pVM->pgm.s.apInterPaePDs);
1536	pVM->pgm.s.pInterPaePDPT64->a[i].u = X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_A \| PGM_PLXFLAGS_PERMANENT
1537	\| MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[iPD]);
1538	}
1539
1540	RTHCPHYS HCPhysInterPaePDPT64 = MMPage2Phys(pVM, pVM->pgm.s.pInterPaePDPT64);
1541	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.pInterPaePML4->a); i++)
1542	pVM->pgm.s.pInterPaePML4->a[i].u = X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_A \| PGM_PLXFLAGS_PERMANENT
1543	\| HCPhysInterPaePDPT64;
1544
1545	/*
1546	* Initialize paging workers and mode from current host mode
1547	* and the guest running in real mode.
1548	*/
1549	pVM->pgm.s.enmHostMode = SUPR3GetPagingMode();
1550	switch (pVM->pgm.s.enmHostMode)
1551	{
1552	case SUPPAGINGMODE_32_BIT:
1553	case SUPPAGINGMODE_32_BIT_GLOBAL:
1554	case SUPPAGINGMODE_PAE:
1555	case SUPPAGINGMODE_PAE_GLOBAL:
1556	case SUPPAGINGMODE_PAE_NX:
1557	case SUPPAGINGMODE_PAE_GLOBAL_NX:
1558	break;
1559
1560	case SUPPAGINGMODE_AMD64:
1561	case SUPPAGINGMODE_AMD64_GLOBAL:
1562	case SUPPAGINGMODE_AMD64_NX:
1563	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
1564	#ifndef VBOX_WITH_HYBRID_32BIT_KERNEL
1565	if (ARCH_BITS != 64)
1566	{
1567	AssertMsgFailed(("Host mode %d (64-bit) is not supported by non-64bit builds\n", pVM->pgm.s.enmHostMode));
1568	LogRel(("Host mode %d (64-bit) is not supported by non-64bit builds\n", pVM->pgm.s.enmHostMode));
1569	return VERR_PGM_UNSUPPORTED_HOST_PAGING_MODE;
1570	}
1571	#endif
1572	break;
1573	default:
1574	AssertMsgFailed(("Host mode %d is not supported\n", pVM->pgm.s.enmHostMode));
1575	return VERR_PGM_UNSUPPORTED_HOST_PAGING_MODE;
1576	}
1577	rc = pgmR3ModeDataInit(pVM, false /* don't resolve GC and R0 syms yet */);
1578	if (RT_SUCCESS(rc))
1579	{
1580	LogFlow(("pgmR3InitPaging: returns successfully\n"));
1581	#if HC_ARCH_BITS == 64
1582	LogRel(("Debug: HCPhysInterPD=%RHp HCPhysInterPaePDPT=%RHp HCPhysInterPaePML4=%RHp\n",
1583	pVM->pgm.s.HCPhysInterPD, pVM->pgm.s.HCPhysInterPaePDPT, pVM->pgm.s.HCPhysInterPaePML4));
1584	LogRel(("Debug: apInterPTs={%RHp,%RHp} apInterPaePTs={%RHp,%RHp} apInterPaePDs={%RHp,%RHp,%RHp,%RHp} pInterPaePDPT64=%RHp\n",
1585	MMPage2Phys(pVM, pVM->pgm.s.apInterPTs[0]), MMPage2Phys(pVM, pVM->pgm.s.apInterPTs[1]),
1586	MMPage2Phys(pVM, pVM->pgm.s.apInterPaePTs[0]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePTs[1]),
1587	MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[0]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[1]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[2]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[3]),
1588	MMPage2Phys(pVM, pVM->pgm.s.pInterPaePDPT64)));
1589	#endif
1590	return VINF_SUCCESS;
1591	}
1592
1593	LogFlow(("pgmR3InitPaging: returns %Rrc\n", rc));
1594	return rc;
1595	}
1596
1597
1598	/**
1599	* Init statistics
1600	* @returns VBox status code.
1601	*/
1602	static int pgmR3InitStats(PVM pVM)
1603	{
1604	PPGM pPGM = &pVM->pgm.s;
1605	int rc;
1606
1607	/*
1608	* Release statistics.
1609	*/
1610	/* Common - misc variables */
1611	STAM_REL_REG(pVM, &pPGM->cAllPages, STAMTYPE_U32, "/PGM/Page/cAllPages", STAMUNIT_COUNT, "The total number of pages.");
1612	STAM_REL_REG(pVM, &pPGM->cPrivatePages, STAMTYPE_U32, "/PGM/Page/cPrivatePages", STAMUNIT_COUNT, "The number of private pages.");
1613	STAM_REL_REG(pVM, &pPGM->cSharedPages, STAMTYPE_U32, "/PGM/Page/cSharedPages", STAMUNIT_COUNT, "The number of shared pages.");
1614	STAM_REL_REG(pVM, &pPGM->cReusedSharedPages, STAMTYPE_U32, "/PGM/Page/cReusedSharedPages", STAMUNIT_COUNT, "The number of reused shared pages.");
1615	STAM_REL_REG(pVM, &pPGM->cZeroPages, STAMTYPE_U32, "/PGM/Page/cZeroPages", STAMUNIT_COUNT, "The number of zero backed pages.");
1616	STAM_REL_REG(pVM, &pPGM->cPureMmioPages, STAMTYPE_U32, "/PGM/Page/cPureMmioPages", STAMUNIT_COUNT, "The number of pure MMIO pages.");
1617	STAM_REL_REG(pVM, &pPGM->cMonitoredPages, STAMTYPE_U32, "/PGM/Page/cMonitoredPages", STAMUNIT_COUNT, "The number of write monitored pages.");
1618	STAM_REL_REG(pVM, &pPGM->cWrittenToPages, STAMTYPE_U32, "/PGM/Page/cWrittenToPages", STAMUNIT_COUNT, "The number of previously write monitored pages that have been written to.");
1619	STAM_REL_REG(pVM, &pPGM->cWriteLockedPages, STAMTYPE_U32, "/PGM/Page/cWriteLockedPages", STAMUNIT_COUNT, "The number of write(/read) locked pages.");
1620	STAM_REL_REG(pVM, &pPGM->cReadLockedPages, STAMTYPE_U32, "/PGM/Page/cReadLockedPages", STAMUNIT_COUNT, "The number of read (only) locked pages.");
1621	STAM_REL_REG(pVM, &pPGM->cBalloonedPages, STAMTYPE_U32, "/PGM/Page/cBalloonedPages", STAMUNIT_COUNT, "The number of ballooned pages.");
1622	STAM_REL_REG(pVM, &pPGM->cHandyPages, STAMTYPE_U32, "/PGM/Page/cHandyPages", STAMUNIT_COUNT, "The number of handy pages (not included in cAllPages).");
1623	STAM_REL_REG(pVM, &pPGM->cRelocations, STAMTYPE_COUNTER, "/PGM/cRelocations", STAMUNIT_OCCURENCES,"Number of hypervisor relocations.");
1624	STAM_REL_REG(pVM, &pPGM->ChunkR3Map.c, STAMTYPE_U32, "/PGM/ChunkR3Map/c", STAMUNIT_COUNT, "Number of mapped chunks.");
1625	STAM_REL_REG(pVM, &pPGM->ChunkR3Map.cMax, STAMTYPE_U32, "/PGM/ChunkR3Map/cMax", STAMUNIT_COUNT, "Maximum number of mapped chunks.");
1626	STAM_REL_REG(pVM, &pPGM->cMappedChunks, STAMTYPE_U32, "/PGM/ChunkR3Map/Mapped", STAMUNIT_COUNT, "Number of times we mapped a chunk.");
1627	STAM_REL_REG(pVM, &pPGM->cUnmappedChunks, STAMTYPE_U32, "/PGM/ChunkR3Map/Unmapped", STAMUNIT_COUNT, "Number of times we unmapped a chunk.");
1628
1629	STAM_REL_REG(pVM, &pPGM->StatLargePageAlloc, STAMTYPE_COUNTER, "/PGM/LargePage/Alloc", STAMUNIT_OCCURENCES, "The number of large pages we've used.");
1630	STAM_REL_REG(pVM, &pPGM->StatLargePageReused, STAMTYPE_COUNTER, "/PGM/LargePage/Reused", STAMUNIT_OCCURENCES, "The number of times we've reused a large page.");
1631	STAM_REL_REG(pVM, &pPGM->StatLargePageRefused, STAMTYPE_COUNTER, "/PGM/LargePage/Refused", STAMUNIT_OCCURENCES, "The number of times we couldn't use a large page.");
1632	STAM_REL_REG(pVM, &pPGM->StatLargePageRecheck, STAMTYPE_COUNTER, "/PGM/LargePage/Recheck", STAMUNIT_OCCURENCES, "The number of times we've rechecked a disabled large page.");
1633
1634	/* Live save */
1635	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.fActive, STAMTYPE_U8, "/PGM/LiveSave/fActive", STAMUNIT_COUNT, "Active or not.");
1636	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.cIgnoredPages, STAMTYPE_U32, "/PGM/LiveSave/cIgnoredPages", STAMUNIT_COUNT, "The number of ignored pages in the RAM ranges (i.e. MMIO, MMIO2 and ROM).");
1637	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.cDirtyPagesLong, STAMTYPE_U32, "/PGM/LiveSave/cDirtyPagesLong", STAMUNIT_COUNT, "Longer term dirty page average.");
1638	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.cDirtyPagesShort, STAMTYPE_U32, "/PGM/LiveSave/cDirtyPagesShort", STAMUNIT_COUNT, "Short term dirty page average.");
1639	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.cPagesPerSecond, STAMTYPE_U32, "/PGM/LiveSave/cPagesPerSecond", STAMUNIT_COUNT, "Pages per second.");
1640	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.cSavedPages, STAMTYPE_U64, "/PGM/LiveSave/cSavedPages", STAMUNIT_COUNT, "The total number of saved pages.");
1641	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Ram.cReadyPages, STAMTYPE_U32, "/PGM/LiveSave/Ram/cReadPages", STAMUNIT_COUNT, "RAM: Ready pages.");
1642	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Ram.cDirtyPages, STAMTYPE_U32, "/PGM/LiveSave/Ram/cDirtyPages", STAMUNIT_COUNT, "RAM: Dirty pages.");
1643	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Ram.cZeroPages, STAMTYPE_U32, "/PGM/LiveSave/Ram/cZeroPages", STAMUNIT_COUNT, "RAM: Ready zero pages.");
1644	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Ram.cMonitoredPages, STAMTYPE_U32, "/PGM/LiveSave/Ram/cMonitoredPages", STAMUNIT_COUNT, "RAM: Write monitored pages.");
1645	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Rom.cReadyPages, STAMTYPE_U32, "/PGM/LiveSave/Rom/cReadPages", STAMUNIT_COUNT, "ROM: Ready pages.");
1646	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Rom.cDirtyPages, STAMTYPE_U32, "/PGM/LiveSave/Rom/cDirtyPages", STAMUNIT_COUNT, "ROM: Dirty pages.");
1647	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Rom.cZeroPages, STAMTYPE_U32, "/PGM/LiveSave/Rom/cZeroPages", STAMUNIT_COUNT, "ROM: Ready zero pages.");
1648	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Rom.cMonitoredPages, STAMTYPE_U32, "/PGM/LiveSave/Rom/cMonitoredPages", STAMUNIT_COUNT, "ROM: Write monitored pages.");
1649	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Mmio2.cReadyPages, STAMTYPE_U32, "/PGM/LiveSave/Mmio2/cReadPages", STAMUNIT_COUNT, "MMIO2: Ready pages.");
1650	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Mmio2.cDirtyPages, STAMTYPE_U32, "/PGM/LiveSave/Mmio2/cDirtyPages", STAMUNIT_COUNT, "MMIO2: Dirty pages.");
1651	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Mmio2.cZeroPages, STAMTYPE_U32, "/PGM/LiveSave/Mmio2/cZeroPages", STAMUNIT_COUNT, "MMIO2: Ready zero pages.");
1652	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Mmio2.cMonitoredPages,STAMTYPE_U32, "/PGM/LiveSave/Mmio2/cMonitoredPages",STAMUNIT_COUNT, "MMIO2: Write monitored pages.");
1653
1654	#ifdef VBOX_WITH_STATISTICS
1655
1656	# define PGM_REG_COUNTER(a, b, c) \
1657	rc = STAMR3RegisterF(pVM, a, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, c, b); \
1658	AssertRC(rc);
1659
1660	# define PGM_REG_COUNTER_BYTES(a, b, c) \
1661	rc = STAMR3RegisterF(pVM, a, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_BYTES, c, b); \
1662	AssertRC(rc);
1663
1664	# define PGM_REG_PROFILE(a, b, c) \
1665	rc = STAMR3RegisterF(pVM, a, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, c, b); \
1666	AssertRC(rc);
1667
1668	PGMSTATS *pStats = pVM->pgm.s.pStatsR3;
1669
1670	PGM_REG_PROFILE(&pStats->StatAllocLargePage, "/PGM/LargePage/Prof/Alloc", "Time spent by the host OS for large page allocation.");
1671	PGM_REG_PROFILE(&pStats->StatClearLargePage, "/PGM/LargePage/Prof/Clear", "Time spent clearing the newly allocated large pages.");
1672	PGM_REG_PROFILE(&pStats->StatR3IsValidLargePage, "/PGM/LargePage/Prof/R3/IsValid", "pgmPhysIsValidLargePage profiling - R3.");
1673	PGM_REG_PROFILE(&pStats->StatRZIsValidLargePage, "/PGM/LargePage/Prof/RZ/IsValid", "pgmPhysIsValidLargePage profiling - RZ.");
1674
1675	PGM_REG_COUNTER(&pStats->StatR3DetectedConflicts, "/PGM/R3/DetectedConflicts", "The number of times PGMR3CheckMappingConflicts() detected a conflict.");
1676	PGM_REG_PROFILE(&pStats->StatR3ResolveConflict, "/PGM/R3/ResolveConflict", "pgmR3SyncPTResolveConflict() profiling (includes the entire relocation).");
1677	PGM_REG_COUNTER(&pStats->StatR3PhysRead, "/PGM/R3/Phys/Read", "The number of times PGMPhysRead was called.");
1678	PGM_REG_COUNTER_BYTES(&pStats->StatR3PhysReadBytes, "/PGM/R3/Phys/Read/Bytes", "The number of bytes read by PGMPhysRead.");
1679	PGM_REG_COUNTER(&pStats->StatR3PhysWrite, "/PGM/R3/Phys/Write", "The number of times PGMPhysWrite was called.");
1680	PGM_REG_COUNTER_BYTES(&pStats->StatR3PhysWriteBytes, "/PGM/R3/Phys/Write/Bytes", "The number of bytes written by PGMPhysWrite.");
1681	PGM_REG_COUNTER(&pStats->StatR3PhysSimpleRead, "/PGM/R3/Phys/Simple/Read", "The number of times PGMPhysSimpleReadGCPtr was called.");
1682	PGM_REG_COUNTER_BYTES(&pStats->StatR3PhysSimpleReadBytes, "/PGM/R3/Phys/Simple/Read/Bytes", "The number of bytes read by PGMPhysSimpleReadGCPtr.");
1683	PGM_REG_COUNTER(&pStats->StatR3PhysSimpleWrite, "/PGM/R3/Phys/Simple/Write", "The number of times PGMPhysSimpleWriteGCPtr was called.");
1684	PGM_REG_COUNTER_BYTES(&pStats->StatR3PhysSimpleWriteBytes, "/PGM/R3/Phys/Simple/Write/Bytes", "The number of bytes written by PGMPhysSimpleWriteGCPtr.");
1685
1686	PGM_REG_COUNTER(&pStats->StatRZChunkR3MapTlbHits, "/PGM/ChunkR3Map/TlbHitsRZ", "TLB hits.");
1687	PGM_REG_COUNTER(&pStats->StatRZChunkR3MapTlbMisses, "/PGM/ChunkR3Map/TlbMissesRZ", "TLB misses.");
1688	PGM_REG_PROFILE(&pStats->StatChunkAging, "/PGM/ChunkR3Map/Map/Aging", "Chunk aging profiling.");
1689	PGM_REG_PROFILE(&pStats->StatChunkFindCandidate, "/PGM/ChunkR3Map/Map/Find", "Chunk unmap find profiling.");
1690	PGM_REG_PROFILE(&pStats->StatChunkUnmap, "/PGM/ChunkR3Map/Map/Unmap", "Chunk unmap of address space profiling.");
1691	PGM_REG_PROFILE(&pStats->StatChunkMap, "/PGM/ChunkR3Map/Map/Map", "Chunk map of address space profiling.");
1692
1693	PGM_REG_COUNTER(&pStats->StatRZPageMapTlbHits, "/PGM/RZ/Page/MapTlbHits", "TLB hits.");
1694	PGM_REG_COUNTER(&pStats->StatRZPageMapTlbMisses, "/PGM/RZ/Page/MapTlbMisses", "TLB misses.");
1695	PGM_REG_COUNTER(&pStats->StatR3ChunkR3MapTlbHits, "/PGM/ChunkR3Map/TlbHitsR3", "TLB hits.");
1696	PGM_REG_COUNTER(&pStats->StatR3ChunkR3MapTlbMisses, "/PGM/ChunkR3Map/TlbMissesR3", "TLB misses.");
1697	PGM_REG_COUNTER(&pStats->StatR3PageMapTlbHits, "/PGM/R3/Page/MapTlbHits", "TLB hits.");
1698	PGM_REG_COUNTER(&pStats->StatR3PageMapTlbMisses, "/PGM/R3/Page/MapTlbMisses", "TLB misses.");
1699	PGM_REG_COUNTER(&pStats->StatPageMapTlbFlushes, "/PGM/R3/Page/MapTlbFlushes", "TLB flushes (all contexts).");
1700	PGM_REG_COUNTER(&pStats->StatPageMapTlbFlushEntry, "/PGM/R3/Page/MapTlbFlushEntry", "TLB entry flushes (all contexts).");
1701
1702	PGM_REG_PROFILE(&pStats->StatRZSyncCR3HandlerVirtualUpdate, "/PGM/RZ/SyncCR3/Handlers/VirtualUpdate", "Profiling of the virtual handler updates.");
1703	PGM_REG_PROFILE(&pStats->StatRZSyncCR3HandlerVirtualReset, "/PGM/RZ/SyncCR3/Handlers/VirtualReset", "Profiling of the virtual handler resets.");
1704	PGM_REG_PROFILE(&pStats->StatR3SyncCR3HandlerVirtualUpdate, "/PGM/R3/SyncCR3/Handlers/VirtualUpdate", "Profiling of the virtual handler updates.");
1705	PGM_REG_PROFILE(&pStats->StatR3SyncCR3HandlerVirtualReset, "/PGM/R3/SyncCR3/Handlers/VirtualReset", "Profiling of the virtual handler resets.");
1706
1707	PGM_REG_COUNTER(&pStats->StatRZPhysHandlerReset, "/PGM/RZ/PhysHandlerReset", "The number of times PGMHandlerPhysicalReset is called.");
1708	PGM_REG_COUNTER(&pStats->StatR3PhysHandlerReset, "/PGM/R3/PhysHandlerReset", "The number of times PGMHandlerPhysicalReset is called.");
1709	PGM_REG_COUNTER(&pStats->StatRZPhysHandlerLookupHits, "/PGM/RZ/PhysHandlerLookupHits", "The number of cache hits when looking up physical handlers.");
1710	PGM_REG_COUNTER(&pStats->StatR3PhysHandlerLookupHits, "/PGM/R3/PhysHandlerLookupHits", "The number of cache hits when looking up physical handlers.");
1711	PGM_REG_COUNTER(&pStats->StatRZPhysHandlerLookupMisses, "/PGM/RZ/PhysHandlerLookupMisses", "The number of cache misses when looking up physical handlers.");
1712	PGM_REG_COUNTER(&pStats->StatR3PhysHandlerLookupMisses, "/PGM/R3/PhysHandlerLookupMisses", "The number of cache misses when looking up physical handlers.");
1713	PGM_REG_PROFILE(&pStats->StatRZVirtHandlerSearchByPhys, "/PGM/RZ/VirtHandlerSearchByPhys", "Profiling of pgmHandlerVirtualFindByPhysAddr.");
1714	PGM_REG_PROFILE(&pStats->StatR3VirtHandlerSearchByPhys, "/PGM/R3/VirtHandlerSearchByPhys", "Profiling of pgmHandlerVirtualFindByPhysAddr.");
1715
1716	PGM_REG_COUNTER(&pStats->StatRZPageReplaceShared, "/PGM/RZ/Page/ReplacedShared", "Times a shared page was replaced.");
1717	PGM_REG_COUNTER(&pStats->StatRZPageReplaceZero, "/PGM/RZ/Page/ReplacedZero", "Times the zero page was replaced.");
1718	/// @todo PGM_REG_COUNTER(&pStats->StatRZPageHandyAllocs, "/PGM/RZ/Page/HandyAllocs", "Number of times we've allocated more handy pages.");
1719	PGM_REG_COUNTER(&pStats->StatR3PageReplaceShared, "/PGM/R3/Page/ReplacedShared", "Times a shared page was replaced.");
1720	PGM_REG_COUNTER(&pStats->StatR3PageReplaceZero, "/PGM/R3/Page/ReplacedZero", "Times the zero page was replaced.");
1721	/// @todo PGM_REG_COUNTER(&pStats->StatR3PageHandyAllocs, "/PGM/R3/Page/HandyAllocs", "Number of times we've allocated more handy pages.");
1722
1723	PGM_REG_COUNTER(&pStats->StatRZPhysRead, "/PGM/RZ/Phys/Read", "The number of times PGMPhysRead was called.");
1724	PGM_REG_COUNTER_BYTES(&pStats->StatRZPhysReadBytes, "/PGM/RZ/Phys/Read/Bytes", "The number of bytes read by PGMPhysRead.");
1725	PGM_REG_COUNTER(&pStats->StatRZPhysWrite, "/PGM/RZ/Phys/Write", "The number of times PGMPhysWrite was called.");
1726	PGM_REG_COUNTER_BYTES(&pStats->StatRZPhysWriteBytes, "/PGM/RZ/Phys/Write/Bytes", "The number of bytes written by PGMPhysWrite.");
1727	PGM_REG_COUNTER(&pStats->StatRZPhysSimpleRead, "/PGM/RZ/Phys/Simple/Read", "The number of times PGMPhysSimpleReadGCPtr was called.");
1728	PGM_REG_COUNTER_BYTES(&pStats->StatRZPhysSimpleReadBytes, "/PGM/RZ/Phys/Simple/Read/Bytes", "The number of bytes read by PGMPhysSimpleReadGCPtr.");
1729	PGM_REG_COUNTER(&pStats->StatRZPhysSimpleWrite, "/PGM/RZ/Phys/Simple/Write", "The number of times PGMPhysSimpleWriteGCPtr was called.");
1730	PGM_REG_COUNTER_BYTES(&pStats->StatRZPhysSimpleWriteBytes, "/PGM/RZ/Phys/Simple/Write/Bytes", "The number of bytes written by PGMPhysSimpleWriteGCPtr.");
1731
1732	/* GC only: */
1733	PGM_REG_COUNTER(&pStats->StatRCInvlPgConflict, "/PGM/RC/InvlPgConflict", "Number of times PGMInvalidatePage() detected a mapping conflict.");
1734	PGM_REG_COUNTER(&pStats->StatRCInvlPgSyncMonCR3, "/PGM/RC/InvlPgSyncMonitorCR3", "Number of times PGMInvalidatePage() ran into PGM_SYNC_MONITOR_CR3.");
1735
1736	PGM_REG_COUNTER(&pStats->StatRCPhysRead, "/PGM/RC/Phys/Read", "The number of times PGMPhysRead was called.");
1737	PGM_REG_COUNTER_BYTES(&pStats->StatRCPhysReadBytes, "/PGM/RC/Phys/Read/Bytes", "The number of bytes read by PGMPhysRead.");
1738	PGM_REG_COUNTER(&pStats->StatRCPhysWrite, "/PGM/RC/Phys/Write", "The number of times PGMPhysWrite was called.");
1739	PGM_REG_COUNTER_BYTES(&pStats->StatRCPhysWriteBytes, "/PGM/RC/Phys/Write/Bytes", "The number of bytes written by PGMPhysWrite.");
1740	PGM_REG_COUNTER(&pStats->StatRCPhysSimpleRead, "/PGM/RC/Phys/Simple/Read", "The number of times PGMPhysSimpleReadGCPtr was called.");
1741	PGM_REG_COUNTER_BYTES(&pStats->StatRCPhysSimpleReadBytes, "/PGM/RC/Phys/Simple/Read/Bytes", "The number of bytes read by PGMPhysSimpleReadGCPtr.");
1742	PGM_REG_COUNTER(&pStats->StatRCPhysSimpleWrite, "/PGM/RC/Phys/Simple/Write", "The number of times PGMPhysSimpleWriteGCPtr was called.");
1743	PGM_REG_COUNTER_BYTES(&pStats->StatRCPhysSimpleWriteBytes, "/PGM/RC/Phys/Simple/Write/Bytes", "The number of bytes written by PGMPhysSimpleWriteGCPtr.");
1744
1745	PGM_REG_COUNTER(&pStats->StatTrackVirgin, "/PGM/Track/Virgin", "The number of first time shadowings");
1746	PGM_REG_COUNTER(&pStats->StatTrackAliased, "/PGM/Track/Aliased", "The number of times switching to cRef2, i.e. the page is being shadowed by two PTs.");
1747	PGM_REG_COUNTER(&pStats->StatTrackAliasedMany, "/PGM/Track/AliasedMany", "The number of times we're tracking using cRef2.");
1748	PGM_REG_COUNTER(&pStats->StatTrackAliasedLots, "/PGM/Track/AliasedLots", "The number of times we're hitting pages which has overflowed cRef2");
1749	PGM_REG_COUNTER(&pStats->StatTrackOverflows, "/PGM/Track/Overflows", "The number of times the extent list grows too long.");
1750	PGM_REG_COUNTER(&pStats->StatTrackNoExtentsLeft, "/PGM/Track/NoExtentLeft", "The number of times the extent list was exhausted.");
1751	PGM_REG_PROFILE(&pStats->StatTrackDeref, "/PGM/Track/Deref", "Profiling of SyncPageWorkerTrackDeref (expensive).");
1752
1753	# undef PGM_REG_COUNTER
1754	# undef PGM_REG_PROFILE
1755	#endif
1756
1757	/*
1758	* Note! The layout below matches the member layout exactly!
1759	*/
1760
1761	/*
1762	* Common - stats
1763	*/
1764	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1765	{
1766	PPGMCPU pPgmCpu = &pVM->aCpus[idCpu].pgm.s;
1767
1768	#define PGM_REG_COUNTER(a, b, c) \
1769	rc = STAMR3RegisterF(pVM, a, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, c, b, idCpu); \
1770	AssertRC(rc);
1771	#define PGM_REG_PROFILE(a, b, c) \
1772	rc = STAMR3RegisterF(pVM, a, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, c, b, idCpu); \
1773	AssertRC(rc);
1774
1775	PGM_REG_COUNTER(&pPgmCpu->cGuestModeChanges, "/PGM/CPU%u/cGuestModeChanges", "Number of guest mode changes.");
1776
1777	#ifdef VBOX_WITH_STATISTICS
1778	PGMCPUSTATS *pCpuStats = pVM->aCpus[idCpu].pgm.s.pStatsR3;
1779
1780	# if 0 /* rarely useful; leave for debugging. */
1781	for (unsigned j = 0; j < RT_ELEMENTS(pPgmCpu->StatSyncPtPD); j++)
1782	STAMR3RegisterF(pVM, &pCpuStats->StatSyncPtPD[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
1783	"The number of SyncPT per PD n.", "/PGM/CPU%u/PDSyncPT/%04X", i, j);
1784	for (unsigned j = 0; j < RT_ELEMENTS(pCpuStats->StatSyncPagePD); j++)
1785	STAMR3RegisterF(pVM, &pCpuStats->StatSyncPagePD[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
1786	"The number of SyncPage per PD n.", "/PGM/CPU%u/PDSyncPage/%04X", i, j);
1787	# endif
1788	/* R0 only: */
1789	PGM_REG_PROFILE(&pCpuStats->StatR0NpMiscfg, "/PGM/CPU%u/R0/NpMiscfg", "PGMR0Trap0eHandlerNPMisconfig() profiling.");
1790	PGM_REG_COUNTER(&pCpuStats->StatR0NpMiscfgSyncPage, "/PGM/CPU%u/R0/NpMiscfgSyncPage", "SyncPage calls from PGMR0Trap0eHandlerNPMisconfig().");
1791
1792	/* RZ only: */
1793	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0e, "/PGM/CPU%u/RZ/Trap0e", "Profiling of the PGMTrap0eHandler() body.");
1794	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2Ballooned, "/PGM/CPU%u/RZ/Trap0e/Time2/Ballooned", "Profiling of the Trap0eHandler body when the cause is read access to a ballooned page.");
1795	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2CSAM, "/PGM/CPU%u/RZ/Trap0e/Time2/CSAM", "Profiling of the Trap0eHandler body when the cause is CSAM.");
1796	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2DirtyAndAccessed, "/PGM/CPU%u/RZ/Trap0e/Time2/DirtyAndAccessedBits", "Profiling of the Trap0eHandler body when the cause is dirty and/or accessed bit emulation.");
1797	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2GuestTrap, "/PGM/CPU%u/RZ/Trap0e/Time2/GuestTrap", "Profiling of the Trap0eHandler body when the cause is a guest trap.");
1798	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2HndPhys, "/PGM/CPU%u/RZ/Trap0e/Time2/HandlerPhysical", "Profiling of the Trap0eHandler body when the cause is a physical handler.");
1799	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2HndVirt, "/PGM/CPU%u/RZ/Trap0e/Time2/HandlerVirtual", "Profiling of the Trap0eHandler body when the cause is a virtual handler.");
1800	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2HndUnhandled, "/PGM/CPU%u/RZ/Trap0e/Time2/HandlerUnhandled", "Profiling of the Trap0eHandler body when the cause is access outside the monitored areas of a monitored page.");
1801	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2InvalidPhys, "/PGM/CPU%u/RZ/Trap0e/Time2/InvalidPhys", "Profiling of the Trap0eHandler body when the cause is access to an invalid physical guest address.");
1802	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2MakeWritable, "/PGM/CPU%u/RZ/Trap0e/Time2/MakeWritable", "Profiling of the Trap0eHandler body when the cause is that a page needed to be made writeable.");
1803	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2Mapping, "/PGM/CPU%u/RZ/Trap0e/Time2/Mapping", "Profiling of the Trap0eHandler body when the cause is releated to the guest mappings.");
1804	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2Misc, "/PGM/CPU%u/RZ/Trap0e/Time2/Misc", "Profiling of the Trap0eHandler body when the cause is not known.");
1805	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2OutOfSync, "/PGM/CPU%u/RZ/Trap0e/Time2/OutOfSync", "Profiling of the Trap0eHandler body when the cause is an out-of-sync page.");
1806	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2OutOfSyncHndPhys, "/PGM/CPU%u/RZ/Trap0e/Time2/OutOfSyncHndPhys", "Profiling of the Trap0eHandler body when the cause is an out-of-sync physical handler page.");
1807	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2OutOfSyncHndVirt, "/PGM/CPU%u/RZ/Trap0e/Time2/OutOfSyncHndVirt", "Profiling of the Trap0eHandler body when the cause is an out-of-sync virtual handler page.");
1808	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2OutOfSyncHndObs, "/PGM/CPU%u/RZ/Trap0e/Time2/OutOfSyncObsHnd", "Profiling of the Trap0eHandler body when the cause is an obsolete handler page.");
1809	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2SyncPT, "/PGM/CPU%u/RZ/Trap0e/Time2/SyncPT", "Profiling of the Trap0eHandler body when the cause is lazy syncing of a PT.");
1810	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2WPEmulation, "/PGM/CPU%u/RZ/Trap0e/Time2/WPEmulation", "Profiling of the Trap0eHandler body when the cause is CR0.WP emulation.");
1811	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eConflicts, "/PGM/CPU%u/RZ/Trap0e/Conflicts", "The number of times #PF was caused by an undetected conflict.");
1812	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eHandlersMapping, "/PGM/CPU%u/RZ/Trap0e/Handlers/Mapping", "Number of traps due to access handlers in mappings.");
1813	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eHandlersOutOfSync, "/PGM/CPU%u/RZ/Trap0e/Handlers/OutOfSync", "Number of traps due to out-of-sync handled pages.");
1814	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eHandlersPhysAll, "/PGM/CPU%u/RZ/Trap0e/Handlers/PhysAll", "Number of traps due to physical all-access handlers.");
1815	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eHandlersPhysAllOpt, "/PGM/CPU%u/RZ/Trap0e/Handlers/PhysAllOpt", "Number of the physical all-access handler traps using the optimization.");
1816	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eHandlersPhysWrite, "/PGM/CPU%u/RZ/Trap0e/Handlers/PhysWrite", "Number of traps due to physical write-access handlers.");
1817	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eHandlersVirtual, "/PGM/CPU%u/RZ/Trap0e/Handlers/Virtual", "Number of traps due to virtual access handlers.");
1818	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eHandlersVirtualByPhys, "/PGM/CPU%u/RZ/Trap0e/Handlers/VirtualByPhys", "Number of traps due to virtual access handlers by physical address.");
1819	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eHandlersVirtualUnmarked,"/PGM/CPU%u/RZ/Trap0e/Handlers/VirtualUnmarked","Number of traps due to virtual access handlers by virtual address (without proper physical flags).");
1820	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eHandlersUnhandled, "/PGM/CPU%u/RZ/Trap0e/Handlers/Unhandled", "Number of traps due to access outside range of monitored page(s).");
1821	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eHandlersInvalid, "/PGM/CPU%u/RZ/Trap0e/Handlers/Invalid", "Number of traps due to access to invalid physical memory.");
1822	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eUSNotPresentRead, "/PGM/CPU%u/RZ/Trap0e/Err/User/NPRead", "Number of user mode not present read page faults.");
1823	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eUSNotPresentWrite, "/PGM/CPU%u/RZ/Trap0e/Err/User/NPWrite", "Number of user mode not present write page faults.");
1824	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eUSWrite, "/PGM/CPU%u/RZ/Trap0e/Err/User/Write", "Number of user mode write page faults.");
1825	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eUSReserved, "/PGM/CPU%u/RZ/Trap0e/Err/User/Reserved", "Number of user mode reserved bit page faults.");
1826	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eUSNXE, "/PGM/CPU%u/RZ/Trap0e/Err/User/NXE", "Number of user mode NXE page faults.");
1827	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eUSRead, "/PGM/CPU%u/RZ/Trap0e/Err/User/Read", "Number of user mode read page faults.");
1828	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eSVNotPresentRead, "/PGM/CPU%u/RZ/Trap0e/Err/Supervisor/NPRead", "Number of supervisor mode not present read page faults.");
1829	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eSVNotPresentWrite, "/PGM/CPU%u/RZ/Trap0e/Err/Supervisor/NPWrite", "Number of supervisor mode not present write page faults.");
1830	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eSVWrite, "/PGM/CPU%u/RZ/Trap0e/Err/Supervisor/Write", "Number of supervisor mode write page faults.");
1831	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eSVReserved, "/PGM/CPU%u/RZ/Trap0e/Err/Supervisor/Reserved", "Number of supervisor mode reserved bit page faults.");
1832	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eSNXE, "/PGM/CPU%u/RZ/Trap0e/Err/Supervisor/NXE", "Number of supervisor mode NXE page faults.");
1833	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eGuestPF, "/PGM/CPU%u/RZ/Trap0e/GuestPF", "Number of real guest page faults.");
1834	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eGuestPFMapping, "/PGM/CPU%u/RZ/Trap0e/GuestPF/InMapping", "Number of real guest page faults in a mapping.");
1835	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eWPEmulInRZ, "/PGM/CPU%u/RZ/Trap0e/WP/InRZ", "Number of guest page faults due to X86_CR0_WP emulation.");
1836	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eWPEmulToR3, "/PGM/CPU%u/RZ/Trap0e/WP/ToR3", "Number of guest page faults due to X86_CR0_WP emulation (forward to R3 for emulation).");
1837	#if 0 /* rarely useful; leave for debugging. */
1838	for (unsigned j = 0; j < RT_ELEMENTS(pCpuStats->StatRZTrap0ePD); j++)
1839	STAMR3RegisterF(pVM, &pCpuStats->StatRZTrap0ePD[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
1840	"The number of traps in page directory n.", "/PGM/CPU%u/RZ/Trap0e/PD/%04X", i, j);
1841	#endif
1842	PGM_REG_COUNTER(&pCpuStats->StatRZGuestCR3WriteHandled, "/PGM/CPU%u/RZ/CR3WriteHandled", "The number of times the Guest CR3 change was successfully handled.");
1843	PGM_REG_COUNTER(&pCpuStats->StatRZGuestCR3WriteUnhandled, "/PGM/CPU%u/RZ/CR3WriteUnhandled", "The number of times the Guest CR3 change was passed back to the recompiler.");
1844	PGM_REG_COUNTER(&pCpuStats->StatRZGuestCR3WriteConflict, "/PGM/CPU%u/RZ/CR3WriteConflict", "The number of times the Guest CR3 monitoring detected a conflict.");
1845	PGM_REG_COUNTER(&pCpuStats->StatRZGuestROMWriteHandled, "/PGM/CPU%u/RZ/ROMWriteHandled", "The number of times the Guest ROM change was successfully handled.");
1846	PGM_REG_COUNTER(&pCpuStats->StatRZGuestROMWriteUnhandled, "/PGM/CPU%u/RZ/ROMWriteUnhandled", "The number of times the Guest ROM change was passed back to the recompiler.");
1847
1848	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapMigrateInvlPg, "/PGM/CPU%u/RZ/DynMap/MigrateInvlPg", "invlpg count in PGMR0DynMapMigrateAutoSet.");
1849	PGM_REG_PROFILE(&pCpuStats->StatRZDynMapGCPageInl, "/PGM/CPU%u/RZ/DynMap/PageGCPageInl", "Calls to pgmR0DynMapGCPageInlined.");
1850	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapGCPageInlHits, "/PGM/CPU%u/RZ/DynMap/PageGCPageInl/Hits", "Hash table lookup hits.");
1851	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapGCPageInlMisses, "/PGM/CPU%u/RZ/DynMap/PageGCPageInl/Misses", "Misses that falls back to the code common.");
1852	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapGCPageInlRamHits, "/PGM/CPU%u/RZ/DynMap/PageGCPageInl/RamHits", "1st ram range hits.");
1853	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapGCPageInlRamMisses, "/PGM/CPU%u/RZ/DynMap/PageGCPageInl/RamMisses", "1st ram range misses, takes slow path.");
1854	PGM_REG_PROFILE(&pCpuStats->StatRZDynMapHCPageInl, "/PGM/CPU%u/RZ/DynMap/PageHCPageInl", "Calls to pgmRZDynMapHCPageInlined.");
1855	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapHCPageInlHits, "/PGM/CPU%u/RZ/DynMap/PageHCPageInl/Hits", "Hash table lookup hits.");
1856	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapHCPageInlMisses, "/PGM/CPU%u/RZ/DynMap/PageHCPageInl/Misses", "Misses that falls back to the code common.");
1857	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapPage, "/PGM/CPU%u/RZ/DynMap/Page", "Calls to pgmR0DynMapPage");
1858	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapSetOptimize, "/PGM/CPU%u/RZ/DynMap/Page/SetOptimize", "Calls to pgmRZDynMapOptimizeAutoSet.");
1859	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapSetSearchFlushes, "/PGM/CPU%u/RZ/DynMap/Page/SetSearchFlushes", "Set search restorting to subset flushes.");
1860	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapSetSearchHits, "/PGM/CPU%u/RZ/DynMap/Page/SetSearchHits", "Set search hits.");
1861	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapSetSearchMisses, "/PGM/CPU%u/RZ/DynMap/Page/SetSearchMisses", "Set search misses.");
1862	PGM_REG_PROFILE(&pCpuStats->StatRZDynMapHCPage, "/PGM/CPU%u/RZ/DynMap/Page/HCPage", "Calls to pgmRZDynMapHCPageCommon (ring-0).");
1863	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapPageHits0, "/PGM/CPU%u/RZ/DynMap/Page/Hits0", "Hits at iPage+0");
1864	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapPageHits1, "/PGM/CPU%u/RZ/DynMap/Page/Hits1", "Hits at iPage+1");
1865	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapPageHits2, "/PGM/CPU%u/RZ/DynMap/Page/Hits2", "Hits at iPage+2");
1866	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapPageInvlPg, "/PGM/CPU%u/RZ/DynMap/Page/InvlPg", "invlpg count in pgmR0DynMapPageSlow.");
1867	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapPageSlow, "/PGM/CPU%u/RZ/DynMap/Page/Slow", "Calls to pgmR0DynMapPageSlow - subtract this from pgmR0DynMapPage to get 1st level hits.");
1868	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapPageSlowLoopHits, "/PGM/CPU%u/RZ/DynMap/Page/SlowLoopHits" , "Hits in the loop path.");
1869	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapPageSlowLoopMisses, "/PGM/CPU%u/RZ/DynMap/Page/SlowLoopMisses", "Misses in the loop path. NonLoopMisses = Slow - SlowLoopHit - SlowLoopMisses");
1870	//PGM_REG_COUNTER(&pCpuStats->StatRZDynMapPageSlowLostHits, "/PGM/CPU%u/R0/DynMap/Page/SlowLostHits", "Lost hits.");
1871	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapSubsets, "/PGM/CPU%u/RZ/DynMap/Subsets", "Times PGMRZDynMapPushAutoSubset was called.");
1872	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapPopFlushes, "/PGM/CPU%u/RZ/DynMap/SubsetPopFlushes", "Times PGMRZDynMapPopAutoSubset flushes the subset.");
1873	PGM_REG_COUNTER(&pCpuStats->aStatRZDynMapSetFilledPct[0], "/PGM/CPU%u/RZ/DynMap/SetFilledPct000..09", "00-09% filled (RC: min(set-size, dynmap-size))");
1874	PGM_REG_COUNTER(&pCpuStats->aStatRZDynMapSetFilledPct[1], "/PGM/CPU%u/RZ/DynMap/SetFilledPct010..19", "10-19% filled (RC: min(set-size, dynmap-size))");
1875	PGM_REG_COUNTER(&pCpuStats->aStatRZDynMapSetFilledPct[2], "/PGM/CPU%u/RZ/DynMap/SetFilledPct020..29", "20-29% filled (RC: min(set-size, dynmap-size))");
1876	PGM_REG_COUNTER(&pCpuStats->aStatRZDynMapSetFilledPct[3], "/PGM/CPU%u/RZ/DynMap/SetFilledPct030..39", "30-39% filled (RC: min(set-size, dynmap-size))");
1877	PGM_REG_COUNTER(&pCpuStats->aStatRZDynMapSetFilledPct[4], "/PGM/CPU%u/RZ/DynMap/SetFilledPct040..49", "40-49% filled (RC: min(set-size, dynmap-size))");
1878	PGM_REG_COUNTER(&pCpuStats->aStatRZDynMapSetFilledPct[5], "/PGM/CPU%u/RZ/DynMap/SetFilledPct050..59", "50-59% filled (RC: min(set-size, dynmap-size))");
1879	PGM_REG_COUNTER(&pCpuStats->aStatRZDynMapSetFilledPct[6], "/PGM/CPU%u/RZ/DynMap/SetFilledPct060..69", "60-69% filled (RC: min(set-size, dynmap-size))");
1880	PGM_REG_COUNTER(&pCpuStats->aStatRZDynMapSetFilledPct[7], "/PGM/CPU%u/RZ/DynMap/SetFilledPct070..79", "70-79% filled (RC: min(set-size, dynmap-size))");
1881	PGM_REG_COUNTER(&pCpuStats->aStatRZDynMapSetFilledPct[8], "/PGM/CPU%u/RZ/DynMap/SetFilledPct080..89", "80-89% filled (RC: min(set-size, dynmap-size))");
1882	PGM_REG_COUNTER(&pCpuStats->aStatRZDynMapSetFilledPct[9], "/PGM/CPU%u/RZ/DynMap/SetFilledPct090..99", "90-99% filled (RC: min(set-size, dynmap-size))");
1883	PGM_REG_COUNTER(&pCpuStats->aStatRZDynMapSetFilledPct[10], "/PGM/CPU%u/RZ/DynMap/SetFilledPct100", "100% filled (RC: min(set-size, dynmap-size))");
1884
1885	/* HC only: */
1886
1887	/* RZ & R3: */
1888	PGM_REG_PROFILE(&pCpuStats->StatRZSyncCR3, "/PGM/CPU%u/RZ/SyncCR3", "Profiling of the PGMSyncCR3() body.");
1889	PGM_REG_PROFILE(&pCpuStats->StatRZSyncCR3Handlers, "/PGM/CPU%u/RZ/SyncCR3/Handlers", "Profiling of the PGMSyncCR3() update handler section.");
1890	PGM_REG_COUNTER(&pCpuStats->StatRZSyncCR3Global, "/PGM/CPU%u/RZ/SyncCR3/Global", "The number of global CR3 syncs.");
1891	PGM_REG_COUNTER(&pCpuStats->StatRZSyncCR3NotGlobal, "/PGM/CPU%u/RZ/SyncCR3/NotGlobal", "The number of non-global CR3 syncs.");
1892	PGM_REG_COUNTER(&pCpuStats->StatRZSyncCR3DstCacheHit, "/PGM/CPU%u/RZ/SyncCR3/DstChacheHit", "The number of times we got some kind of a cache hit.");
1893	PGM_REG_COUNTER(&pCpuStats->StatRZSyncCR3DstFreed, "/PGM/CPU%u/RZ/SyncCR3/DstFreed", "The number of times we've had to free a shadow entry.");
1894	PGM_REG_COUNTER(&pCpuStats->StatRZSyncCR3DstFreedSrcNP, "/PGM/CPU%u/RZ/SyncCR3/DstFreedSrcNP", "The number of times we've had to free a shadow entry for which the source entry was not present.");
1895	PGM_REG_COUNTER(&pCpuStats->StatRZSyncCR3DstNotPresent, "/PGM/CPU%u/RZ/SyncCR3/DstNotPresent", "The number of times we've encountered a not present shadow entry for a present guest entry.");
1896	PGM_REG_COUNTER(&pCpuStats->StatRZSyncCR3DstSkippedGlobalPD, "/PGM/CPU%u/RZ/SyncCR3/DstSkippedGlobalPD", "The number of times a global page directory wasn't flushed.");
1897	PGM_REG_COUNTER(&pCpuStats->StatRZSyncCR3DstSkippedGlobalPT, "/PGM/CPU%u/RZ/SyncCR3/DstSkippedGlobalPT", "The number of times a page table with only global entries wasn't flushed.");
1898	PGM_REG_PROFILE(&pCpuStats->StatRZSyncPT, "/PGM/CPU%u/RZ/SyncPT", "Profiling of the pfnSyncPT() body.");
1899	PGM_REG_COUNTER(&pCpuStats->StatRZSyncPTFailed, "/PGM/CPU%u/RZ/SyncPT/Failed", "The number of times pfnSyncPT() failed.");
1900	PGM_REG_COUNTER(&pCpuStats->StatRZSyncPT4K, "/PGM/CPU%u/RZ/SyncPT/4K", "Nr of 4K PT syncs");
1901	PGM_REG_COUNTER(&pCpuStats->StatRZSyncPT4M, "/PGM/CPU%u/RZ/SyncPT/4M", "Nr of 4M PT syncs");
1902	PGM_REG_COUNTER(&pCpuStats->StatRZSyncPagePDNAs, "/PGM/CPU%u/RZ/SyncPagePDNAs", "The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit.");
1903	PGM_REG_COUNTER(&pCpuStats->StatRZSyncPagePDOutOfSync, "/PGM/CPU%u/RZ/SyncPagePDOutOfSync", "The number of time we've encountered an out-of-sync PD in SyncPage.");
1904	PGM_REG_COUNTER(&pCpuStats->StatRZAccessedPage, "/PGM/CPU%u/RZ/AccessedPage", "The number of pages marked not present for accessed bit emulation.");
1905	PGM_REG_PROFILE(&pCpuStats->StatRZDirtyBitTracking, "/PGM/CPU%u/RZ/DirtyPage", "Profiling the dirty bit tracking in CheckPageFault().");
1906	PGM_REG_COUNTER(&pCpuStats->StatRZDirtyPage, "/PGM/CPU%u/RZ/DirtyPage/Mark", "The number of pages marked read-only for dirty bit tracking.");
1907	PGM_REG_COUNTER(&pCpuStats->StatRZDirtyPageBig, "/PGM/CPU%u/RZ/DirtyPage/MarkBig", "The number of 4MB pages marked read-only for dirty bit tracking.");
1908	PGM_REG_COUNTER(&pCpuStats->StatRZDirtyPageSkipped, "/PGM/CPU%u/RZ/DirtyPage/Skipped", "The number of pages already dirty or readonly.");
1909	PGM_REG_COUNTER(&pCpuStats->StatRZDirtyPageTrap, "/PGM/CPU%u/RZ/DirtyPage/Trap", "The number of traps generated for dirty bit tracking.");
1910	PGM_REG_COUNTER(&pCpuStats->StatRZDirtyPageStale, "/PGM/CPU%u/RZ/DirtyPage/Stale", "The number of traps generated for dirty bit tracking (stale tlb entries).");
1911	PGM_REG_COUNTER(&pCpuStats->StatRZDirtiedPage, "/PGM/CPU%u/RZ/DirtyPage/SetDirty", "The number of pages marked dirty because of write accesses.");
1912	PGM_REG_COUNTER(&pCpuStats->StatRZDirtyTrackRealPF, "/PGM/CPU%u/RZ/DirtyPage/RealPF", "The number of real pages faults during dirty bit tracking.");
1913	PGM_REG_COUNTER(&pCpuStats->StatRZPageAlreadyDirty, "/PGM/CPU%u/RZ/DirtyPage/AlreadySet", "The number of pages already marked dirty because of write accesses.");
1914	PGM_REG_PROFILE(&pCpuStats->StatRZInvalidatePage, "/PGM/CPU%u/RZ/InvalidatePage", "PGMInvalidatePage() profiling.");
1915	PGM_REG_COUNTER(&pCpuStats->StatRZInvalidatePage4KBPages, "/PGM/CPU%u/RZ/InvalidatePage/4KBPages", "The number of times PGMInvalidatePage() was called for a 4KB page.");
1916	PGM_REG_COUNTER(&pCpuStats->StatRZInvalidatePage4MBPages, "/PGM/CPU%u/RZ/InvalidatePage/4MBPages", "The number of times PGMInvalidatePage() was called for a 4MB page.");
1917	PGM_REG_COUNTER(&pCpuStats->StatRZInvalidatePage4MBPagesSkip, "/PGM/CPU%u/RZ/InvalidatePage/4MBPagesSkip","The number of times PGMInvalidatePage() skipped a 4MB page.");
1918	PGM_REG_COUNTER(&pCpuStats->StatRZInvalidatePagePDMappings, "/PGM/CPU%u/RZ/InvalidatePage/PDMappings", "The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict).");
1919	PGM_REG_COUNTER(&pCpuStats->StatRZInvalidatePagePDNAs, "/PGM/CPU%u/RZ/InvalidatePage/PDNAs", "The number of times PGMInvalidatePage() was called for a not accessed page directory.");
1920	PGM_REG_COUNTER(&pCpuStats->StatRZInvalidatePagePDNPs, "/PGM/CPU%u/RZ/InvalidatePage/PDNPs", "The number of times PGMInvalidatePage() was called for a not present page directory.");
1921	PGM_REG_COUNTER(&pCpuStats->StatRZInvalidatePagePDOutOfSync, "/PGM/CPU%u/RZ/InvalidatePage/PDOutOfSync", "The number of times PGMInvalidatePage() was called for an out of sync page directory.");
1922	PGM_REG_COUNTER(&pCpuStats->StatRZInvalidatePageSkipped, "/PGM/CPU%u/RZ/InvalidatePage/Skipped", "The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3.");
1923	PGM_REG_COUNTER(&pCpuStats->StatRZPageOutOfSyncSupervisor, "/PGM/CPU%u/RZ/OutOfSync/SuperVisor", "Number of traps due to pages out of sync (P) and times VerifyAccessSyncPage calls SyncPage.");
1924	PGM_REG_COUNTER(&pCpuStats->StatRZPageOutOfSyncUser, "/PGM/CPU%u/RZ/OutOfSync/User", "Number of traps due to pages out of sync (P) and times VerifyAccessSyncPage calls SyncPage.");
1925	PGM_REG_COUNTER(&pCpuStats->StatRZPageOutOfSyncSupervisorWrite,"/PGM/CPU%u/RZ/OutOfSync/SuperVisorWrite", "Number of traps due to pages out of sync (RW) and times VerifyAccessSyncPage calls SyncPage.");
1926	PGM_REG_COUNTER(&pCpuStats->StatRZPageOutOfSyncUserWrite, "/PGM/CPU%u/RZ/OutOfSync/UserWrite", "Number of traps due to pages out of sync (RW) and times VerifyAccessSyncPage calls SyncPage.");
1927	PGM_REG_COUNTER(&pCpuStats->StatRZPageOutOfSyncBallloon, "/PGM/CPU%u/RZ/OutOfSync/Balloon", "The number of times a ballooned page was accessed (read).");
1928	PGM_REG_PROFILE(&pCpuStats->StatRZPrefetch, "/PGM/CPU%u/RZ/Prefetch", "PGMPrefetchPage profiling.");
1929	PGM_REG_PROFILE(&pCpuStats->StatRZFlushTLB, "/PGM/CPU%u/RZ/FlushTLB", "Profiling of the PGMFlushTLB() body.");
1930	PGM_REG_COUNTER(&pCpuStats->StatRZFlushTLBNewCR3, "/PGM/CPU%u/RZ/FlushTLB/NewCR3", "The number of times PGMFlushTLB was called with a new CR3, non-global. (switch)");
1931	PGM_REG_COUNTER(&pCpuStats->StatRZFlushTLBNewCR3Global, "/PGM/CPU%u/RZ/FlushTLB/NewCR3Global", "The number of times PGMFlushTLB was called with a new CR3, global. (switch)");
1932	PGM_REG_COUNTER(&pCpuStats->StatRZFlushTLBSameCR3, "/PGM/CPU%u/RZ/FlushTLB/SameCR3", "The number of times PGMFlushTLB was called with the same CR3, non-global. (flush)");
1933	PGM_REG_COUNTER(&pCpuStats->StatRZFlushTLBSameCR3Global, "/PGM/CPU%u/RZ/FlushTLB/SameCR3Global", "The number of times PGMFlushTLB was called with the same CR3, global. (flush)");
1934	PGM_REG_PROFILE(&pCpuStats->StatRZGstModifyPage, "/PGM/CPU%u/RZ/GstModifyPage", "Profiling of the PGMGstModifyPage() body.");
1935
1936	PGM_REG_PROFILE(&pCpuStats->StatR3SyncCR3, "/PGM/CPU%u/R3/SyncCR3", "Profiling of the PGMSyncCR3() body.");
1937	PGM_REG_PROFILE(&pCpuStats->StatR3SyncCR3Handlers, "/PGM/CPU%u/R3/SyncCR3/Handlers", "Profiling of the PGMSyncCR3() update handler section.");
1938	PGM_REG_COUNTER(&pCpuStats->StatR3SyncCR3Global, "/PGM/CPU%u/R3/SyncCR3/Global", "The number of global CR3 syncs.");
1939	PGM_REG_COUNTER(&pCpuStats->StatR3SyncCR3NotGlobal, "/PGM/CPU%u/R3/SyncCR3/NotGlobal", "The number of non-global CR3 syncs.");
1940	PGM_REG_COUNTER(&pCpuStats->StatR3SyncCR3DstCacheHit, "/PGM/CPU%u/R3/SyncCR3/DstChacheHit", "The number of times we got some kind of a cache hit.");
1941	PGM_REG_COUNTER(&pCpuStats->StatR3SyncCR3DstFreed, "/PGM/CPU%u/R3/SyncCR3/DstFreed", "The number of times we've had to free a shadow entry.");
1942	PGM_REG_COUNTER(&pCpuStats->StatR3SyncCR3DstFreedSrcNP, "/PGM/CPU%u/R3/SyncCR3/DstFreedSrcNP", "The number of times we've had to free a shadow entry for which the source entry was not present.");
1943	PGM_REG_COUNTER(&pCpuStats->StatR3SyncCR3DstNotPresent, "/PGM/CPU%u/R3/SyncCR3/DstNotPresent", "The number of times we've encountered a not present shadow entry for a present guest entry.");
1944	PGM_REG_COUNTER(&pCpuStats->StatR3SyncCR3DstSkippedGlobalPD, "/PGM/CPU%u/R3/SyncCR3/DstSkippedGlobalPD", "The number of times a global page directory wasn't flushed.");
1945	PGM_REG_COUNTER(&pCpuStats->StatR3SyncCR3DstSkippedGlobalPT, "/PGM/CPU%u/R3/SyncCR3/DstSkippedGlobalPT", "The number of times a page table with only global entries wasn't flushed.");
1946	PGM_REG_PROFILE(&pCpuStats->StatR3SyncPT, "/PGM/CPU%u/R3/SyncPT", "Profiling of the pfnSyncPT() body.");
1947	PGM_REG_COUNTER(&pCpuStats->StatR3SyncPTFailed, "/PGM/CPU%u/R3/SyncPT/Failed", "The number of times pfnSyncPT() failed.");
1948	PGM_REG_COUNTER(&pCpuStats->StatR3SyncPT4K, "/PGM/CPU%u/R3/SyncPT/4K", "Nr of 4K PT syncs");
1949	PGM_REG_COUNTER(&pCpuStats->StatR3SyncPT4M, "/PGM/CPU%u/R3/SyncPT/4M", "Nr of 4M PT syncs");
1950	PGM_REG_COUNTER(&pCpuStats->StatR3SyncPagePDNAs, "/PGM/CPU%u/R3/SyncPagePDNAs", "The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit.");
1951	PGM_REG_COUNTER(&pCpuStats->StatR3SyncPagePDOutOfSync, "/PGM/CPU%u/R3/SyncPagePDOutOfSync", "The number of time we've encountered an out-of-sync PD in SyncPage.");
1952	PGM_REG_COUNTER(&pCpuStats->StatR3AccessedPage, "/PGM/CPU%u/R3/AccessedPage", "The number of pages marked not present for accessed bit emulation.");
1953	PGM_REG_PROFILE(&pCpuStats->StatR3DirtyBitTracking, "/PGM/CPU%u/R3/DirtyPage", "Profiling the dirty bit tracking in CheckPageFault().");
1954	PGM_REG_COUNTER(&pCpuStats->StatR3DirtyPage, "/PGM/CPU%u/R3/DirtyPage/Mark", "The number of pages marked read-only for dirty bit tracking.");
1955	PGM_REG_COUNTER(&pCpuStats->StatR3DirtyPageBig, "/PGM/CPU%u/R3/DirtyPage/MarkBig", "The number of 4MB pages marked read-only for dirty bit tracking.");
1956	PGM_REG_COUNTER(&pCpuStats->StatR3DirtyPageSkipped, "/PGM/CPU%u/R3/DirtyPage/Skipped", "The number of pages already dirty or readonly.");
1957	PGM_REG_COUNTER(&pCpuStats->StatR3DirtyPageTrap, "/PGM/CPU%u/R3/DirtyPage/Trap", "The number of traps generated for dirty bit tracking.");
1958	PGM_REG_COUNTER(&pCpuStats->StatR3DirtiedPage, "/PGM/CPU%u/R3/DirtyPage/SetDirty", "The number of pages marked dirty because of write accesses.");
1959	PGM_REG_COUNTER(&pCpuStats->StatR3DirtyTrackRealPF, "/PGM/CPU%u/R3/DirtyPage/RealPF", "The number of real pages faults during dirty bit tracking.");
1960	PGM_REG_COUNTER(&pCpuStats->StatR3PageAlreadyDirty, "/PGM/CPU%u/R3/DirtyPage/AlreadySet", "The number of pages already marked dirty because of write accesses.");
1961	PGM_REG_PROFILE(&pCpuStats->StatR3InvalidatePage, "/PGM/CPU%u/R3/InvalidatePage", "PGMInvalidatePage() profiling.");
1962	PGM_REG_COUNTER(&pCpuStats->StatR3InvalidatePage4KBPages, "/PGM/CPU%u/R3/InvalidatePage/4KBPages", "The number of times PGMInvalidatePage() was called for a 4KB page.");
1963	PGM_REG_COUNTER(&pCpuStats->StatR3InvalidatePage4MBPages, "/PGM/CPU%u/R3/InvalidatePage/4MBPages", "The number of times PGMInvalidatePage() was called for a 4MB page.");
1964	PGM_REG_COUNTER(&pCpuStats->StatR3InvalidatePage4MBPagesSkip, "/PGM/CPU%u/R3/InvalidatePage/4MBPagesSkip","The number of times PGMInvalidatePage() skipped a 4MB page.");
1965	PGM_REG_COUNTER(&pCpuStats->StatR3InvalidatePagePDMappings, "/PGM/CPU%u/R3/InvalidatePage/PDMappings", "The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict).");
1966	PGM_REG_COUNTER(&pCpuStats->StatR3InvalidatePagePDNAs, "/PGM/CPU%u/R3/InvalidatePage/PDNAs", "The number of times PGMInvalidatePage() was called for a not accessed page directory.");
1967	PGM_REG_COUNTER(&pCpuStats->StatR3InvalidatePagePDNPs, "/PGM/CPU%u/R3/InvalidatePage/PDNPs", "The number of times PGMInvalidatePage() was called for a not present page directory.");
1968	PGM_REG_COUNTER(&pCpuStats->StatR3InvalidatePagePDOutOfSync, "/PGM/CPU%u/R3/InvalidatePage/PDOutOfSync", "The number of times PGMInvalidatePage() was called for an out of sync page directory.");
1969	PGM_REG_COUNTER(&pCpuStats->StatR3InvalidatePageSkipped, "/PGM/CPU%u/R3/InvalidatePage/Skipped", "The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3.");
1970	PGM_REG_COUNTER(&pCpuStats->StatR3PageOutOfSyncSupervisor, "/PGM/CPU%u/R3/OutOfSync/SuperVisor", "Number of traps due to pages out of sync and times VerifyAccessSyncPage calls SyncPage.");
1971	PGM_REG_COUNTER(&pCpuStats->StatR3PageOutOfSyncUser, "/PGM/CPU%u/R3/OutOfSync/User", "Number of traps due to pages out of sync and times VerifyAccessSyncPage calls SyncPage.");
1972	PGM_REG_COUNTER(&pCpuStats->StatR3PageOutOfSyncBallloon, "/PGM/CPU%u/R3/OutOfSync/Balloon", "The number of times a ballooned page was accessed (read).");
1973	PGM_REG_PROFILE(&pCpuStats->StatR3Prefetch, "/PGM/CPU%u/R3/Prefetch", "PGMPrefetchPage profiling.");
1974	PGM_REG_PROFILE(&pCpuStats->StatR3FlushTLB, "/PGM/CPU%u/R3/FlushTLB", "Profiling of the PGMFlushTLB() body.");
1975	PGM_REG_COUNTER(&pCpuStats->StatR3FlushTLBNewCR3, "/PGM/CPU%u/R3/FlushTLB/NewCR3", "The number of times PGMFlushTLB was called with a new CR3, non-global. (switch)");
1976	PGM_REG_COUNTER(&pCpuStats->StatR3FlushTLBNewCR3Global, "/PGM/CPU%u/R3/FlushTLB/NewCR3Global", "The number of times PGMFlushTLB was called with a new CR3, global. (switch)");
1977	PGM_REG_COUNTER(&pCpuStats->StatR3FlushTLBSameCR3, "/PGM/CPU%u/R3/FlushTLB/SameCR3", "The number of times PGMFlushTLB was called with the same CR3, non-global. (flush)");
1978	PGM_REG_COUNTER(&pCpuStats->StatR3FlushTLBSameCR3Global, "/PGM/CPU%u/R3/FlushTLB/SameCR3Global", "The number of times PGMFlushTLB was called with the same CR3, global. (flush)");
1979	PGM_REG_PROFILE(&pCpuStats->StatR3GstModifyPage, "/PGM/CPU%u/R3/GstModifyPage", "Profiling of the PGMGstModifyPage() body.");
1980	#endif /* VBOX_WITH_STATISTICS */
1981
1982	#undef PGM_REG_PROFILE
1983	#undef PGM_REG_COUNTER
1984
1985	}
1986
1987	return VINF_SUCCESS;
1988	}
1989
1990
1991	/**
1992	* Init the PGM bits that rely on VMMR0 and MM to be fully initialized.
1993	*
1994	* The dynamic mapping area will also be allocated and initialized at this
1995	* time. We could allocate it during PGMR3Init of course, but the mapping
1996	* wouldn't be allocated at that time preventing us from setting up the
1997	* page table entries with the dummy page.
1998	*
1999	* @returns VBox status code.
2000	* @param pVM VM handle.
2001	*/
2002	VMMR3DECL(int) PGMR3InitDynMap(PVM pVM)
2003	{
2004	RTGCPTR GCPtr;
2005	int rc;
2006
2007	/*
2008	* Reserve space for the dynamic mappings.
2009	*/
2010	rc = MMR3HyperReserve(pVM, MM_HYPER_DYNAMIC_SIZE, "Dynamic mapping", &GCPtr);
2011	if (RT_SUCCESS(rc))
2012	pVM->pgm.s.pbDynPageMapBaseGC = GCPtr;
2013
2014	if ( RT_SUCCESS(rc)
2015	&& (pVM->pgm.s.pbDynPageMapBaseGC >> X86_PD_PAE_SHIFT) != ((pVM->pgm.s.pbDynPageMapBaseGC + MM_HYPER_DYNAMIC_SIZE - 1) >> X86_PD_PAE_SHIFT))
2016	{
2017	rc = MMR3HyperReserve(pVM, MM_HYPER_DYNAMIC_SIZE, "Dynamic mapping not crossing", &GCPtr);
2018	if (RT_SUCCESS(rc))
2019	pVM->pgm.s.pbDynPageMapBaseGC = GCPtr;
2020	}
2021	if (RT_SUCCESS(rc))
2022	{
2023	AssertRelease((pVM->pgm.s.pbDynPageMapBaseGC >> X86_PD_PAE_SHIFT) == ((pVM->pgm.s.pbDynPageMapBaseGC + MM_HYPER_DYNAMIC_SIZE - 1) >> X86_PD_PAE_SHIFT));
2024	MMR3HyperReserve(pVM, PAGE_SIZE, "fence", NULL);
2025	}
2026	return rc;
2027	}
2028
2029
2030	/**
2031	* Ring-3 init finalizing.
2032	*
2033	* @returns VBox status code.
2034	* @param pVM The VM handle.
2035	*/
2036	VMMR3DECL(int) PGMR3InitFinalize(PVM pVM)
2037	{
2038	int rc;
2039
2040	/*
2041	* Reserve space for the dynamic mappings.
2042	* Initialize the dynamic mapping pages with dummy pages to simply the cache.
2043	*/
2044	/* get the pointer to the page table entries. */
2045	PPGMMAPPING pMapping = pgmGetMapping(pVM, pVM->pgm.s.pbDynPageMapBaseGC);
2046	AssertRelease(pMapping);
2047	const uintptr_t off = pVM->pgm.s.pbDynPageMapBaseGC - pMapping->GCPtr;
2048	const unsigned iPT = off >> X86_PD_SHIFT;
2049	const unsigned iPG = (off >> X86_PT_SHIFT) & X86_PT_MASK;
2050	pVM->pgm.s.paDynPageMap32BitPTEsGC = pMapping->aPTs[iPT].pPTRC + iPG * sizeof(pMapping->aPTs[0].pPTR3->a[0]);
2051	pVM->pgm.s.paDynPageMapPaePTEsGC = pMapping->aPTs[iPT].paPaePTsRC + iPG * sizeof(pMapping->aPTs[0].paPaePTsR3->a[0]);
2052
2053	/* init cache area */
2054	RTHCPHYS HCPhysDummy = MMR3PageDummyHCPhys(pVM);
2055	for (uint32_t offDynMap = 0; offDynMap < MM_HYPER_DYNAMIC_SIZE; offDynMap += PAGE_SIZE)
2056	{
2057	rc = PGMMap(pVM, pVM->pgm.s.pbDynPageMapBaseGC + offDynMap, HCPhysDummy, PAGE_SIZE, 0);
2058	AssertRCReturn(rc, rc);
2059	}
2060
2061	/*
2062	* Determin the max physical address width (MAXPHYADDR) and apply it to
2063	* all the mask members and stuff.
2064	*/
2065	uint32_t cMaxPhysAddrWidth;
2066	uint32_t uMaxExtLeaf = ASMCpuId_EAX(0x80000000);
2067	if ( uMaxExtLeaf >= 0x80000008
2068	&& uMaxExtLeaf <= 0x80000fff)
2069	{
2070	cMaxPhysAddrWidth = ASMCpuId_EAX(0x80000008) & 0xff;
2071	LogRel(("PGM: The CPU physical address width is %u bits\n", cMaxPhysAddrWidth));
2072	cMaxPhysAddrWidth = RT_MIN(52, cMaxPhysAddrWidth);
2073	pVM->pgm.s.fLessThan52PhysicalAddressBits = cMaxPhysAddrWidth < 52;
2074	for (uint32_t iBit = cMaxPhysAddrWidth; iBit < 52; iBit++)
2075	pVM->pgm.s.HCPhysInvMmioPg \|= RT_BIT_64(iBit);
2076	}
2077	else
2078	{
2079	LogRel(("PGM: ASSUMING CPU physical address width of 48 bits (uMaxExtLeaf=%#x)\n", uMaxExtLeaf));
2080	cMaxPhysAddrWidth = 48;
2081	pVM->pgm.s.fLessThan52PhysicalAddressBits = true;
2082	pVM->pgm.s.HCPhysInvMmioPg \|= UINT64_C(0x000f0000000000);
2083	}
2084
2085	pVM->pgm.s.GCPhysInvAddrMask = 0;
2086	for (uint32_t iBit = cMaxPhysAddrWidth; iBit < 64; iBit++)
2087	pVM->pgm.s.GCPhysInvAddrMask \|= RT_BIT_64(iBit);
2088
2089	/*
2090	* Initialize the invalid paging entry masks, assuming NX is disabled.
2091	*/
2092	uint64_t fMbzPageFrameMask = pVM->pgm.s.GCPhysInvAddrMask & UINT64_C(0x000ffffffffff000);
2093	for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
2094	{
2095	PVMCPU pVCpu = &pVM->aCpus[iCpu];
2096
2097	/** @todo The manuals are not entirely clear whether the physical
2098	* address width is relevant. See table 5-9 in the intel
2099	* manual vs the PDE4M descriptions. Write testcase (NP). */
2100	pVCpu->pgm.s.fGst32BitMbzBigPdeMask = ((uint32_t)(fMbzPageFrameMask >> (32 - 13)) & X86_PDE4M_PG_HIGH_MASK)
2101	\| X86_PDE4M_MBZ_MASK;
2102
2103	pVCpu->pgm.s.fGstPaeMbzPteMask = fMbzPageFrameMask \| X86_PTE_PAE_MBZ_MASK_NO_NX;
2104	pVCpu->pgm.s.fGstPaeMbzPdeMask = fMbzPageFrameMask \| X86_PDE_PAE_MBZ_MASK_NO_NX;
2105	pVCpu->pgm.s.fGstPaeMbzBigPdeMask = fMbzPageFrameMask \| X86_PDE2M_PAE_MBZ_MASK_NO_NX;
2106	pVCpu->pgm.s.fGstPaeMbzPdpeMask = fMbzPageFrameMask \| X86_PDPE_PAE_MBZ_MASK;
2107
2108	pVCpu->pgm.s.fGstAmd64MbzPteMask = fMbzPageFrameMask \| X86_PTE_LM_MBZ_MASK_NO_NX;
2109	pVCpu->pgm.s.fGstAmd64MbzPdeMask = fMbzPageFrameMask \| X86_PDE_LM_MBZ_MASK_NX;
2110	pVCpu->pgm.s.fGstAmd64MbzBigPdeMask = fMbzPageFrameMask \| X86_PDE2M_LM_MBZ_MASK_NX;
2111	pVCpu->pgm.s.fGstAmd64MbzPdpeMask = fMbzPageFrameMask \| X86_PDPE_LM_MBZ_MASK_NO_NX;
2112	pVCpu->pgm.s.fGstAmd64MbzBigPdpeMask = fMbzPageFrameMask \| X86_PDPE1G_LM_MBZ_MASK_NO_NX;
2113	pVCpu->pgm.s.fGstAmd64MbzPml4eMask = fMbzPageFrameMask \| X86_PML4E_MBZ_MASK_NO_NX;
2114	}
2115
2116	/*
2117	* Note that AMD uses all the 8 reserved bits for the address (so 40 bits in total);
2118	* Intel only goes up to 36 bits, so we stick to 36 as well.
2119	* Update: More recent intel manuals specifies 40 bits just like AMD.
2120	*/
2121	uint32_t u32Dummy, u32Features;
2122	CPUMGetGuestCpuId(VMMGetCpu(pVM), 1, &u32Dummy, &u32Dummy, &u32Dummy, &u32Features);
2123	if (u32Features & X86_CPUID_FEATURE_EDX_PSE36)
2124	pVM->pgm.s.GCPhys4MBPSEMask = RT_BIT_64(RT_MAX(36, cMaxPhysAddrWidth)) - 1;
2125	else
2126	pVM->pgm.s.GCPhys4MBPSEMask = RT_BIT_64(32) - 1;
2127
2128	/*
2129	* Allocate memory if we're supposed to do that.
2130	*/
2131	if (pVM->pgm.s.fRamPreAlloc)
2132	rc = pgmR3PhysRamPreAllocate(pVM);
2133
2134	LogRel(("PGMR3InitFinalize: 4 MB PSE mask %RGp\n", pVM->pgm.s.GCPhys4MBPSEMask));
2135	return rc;
2136	}
2137
2138
2139	/**
2140	* Applies relocations to data and code managed by this component.
2141	*
2142	* This function will be called at init and whenever the VMM need to relocate it
2143	* self inside the GC.
2144	*
2145	* @param pVM The VM.
2146	* @param offDelta Relocation delta relative to old location.
2147	*/
2148	VMMR3DECL(void) PGMR3Relocate(PVM pVM, RTGCINTPTR offDelta)
2149	{
2150	LogFlow(("PGMR3Relocate %RGv to %RGv\n", pVM->pgm.s.GCPtrCR3Mapping, pVM->pgm.s.GCPtrCR3Mapping + offDelta));
2151
2152	/*
2153	* Paging stuff.
2154	*/
2155	pVM->pgm.s.GCPtrCR3Mapping += offDelta;
2156
2157	pgmR3ModeDataInit(pVM, true /* resolve GC/R0 symbols */);
2158
2159	/* Shadow, guest and both mode switch & relocation for each VCPU. */
2160	for (VMCPUID i = 0; i < pVM->cCpus; i++)
2161	{
2162	PVMCPU pVCpu = &pVM->aCpus[i];
2163
2164	pgmR3ModeDataSwitch(pVM, pVCpu, pVCpu->pgm.s.enmShadowMode, pVCpu->pgm.s.enmGuestMode);
2165
2166	PGM_SHW_PFN(Relocate, pVCpu)(pVCpu, offDelta);
2167	PGM_GST_PFN(Relocate, pVCpu)(pVCpu, offDelta);
2168	PGM_BTH_PFN(Relocate, pVCpu)(pVCpu, offDelta);
2169	}
2170
2171	/*
2172	* Trees.
2173	*/
2174	pVM->pgm.s.pTreesRC = MMHyperR3ToRC(pVM, pVM->pgm.s.pTreesR3);
2175
2176	/*
2177	* Ram ranges.
2178	*/
2179	if (pVM->pgm.s.pRamRangesR3)
2180	{
2181	/* Update the pSelfRC pointers and relink them. */
2182	for (PPGMRAMRANGE pCur = pVM->pgm.s.pRamRangesR3; pCur; pCur = pCur->pNextR3)
2183	if (!(pCur->fFlags & PGM_RAM_RANGE_FLAGS_FLOATING))
2184	pCur->pSelfRC = MMHyperCCToRC(pVM, pCur);
2185	pgmR3PhysRelinkRamRanges(pVM);
2186	}
2187
2188	/*
2189	* Update the pSelfRC pointer of the MMIO2 ram ranges since they might not
2190	* be mapped and thus not included in the above exercise.
2191	*/
2192	for (PPGMMMIO2RANGE pCur = pVM->pgm.s.pMmio2RangesR3; pCur; pCur = pCur->pNextR3)
2193	if (!(pCur->RamRange.fFlags & PGM_RAM_RANGE_FLAGS_FLOATING))
2194	pCur->RamRange.pSelfRC = MMHyperCCToRC(pVM, &pCur->RamRange);
2195
2196	/*
2197	* Update the two page directories with all page table mappings.
2198	* (One or more of them have changed, that's why we're here.)
2199	*/
2200	pVM->pgm.s.pMappingsRC = MMHyperR3ToRC(pVM, pVM->pgm.s.pMappingsR3);
2201	for (PPGMMAPPING pCur = pVM->pgm.s.pMappingsR3; pCur->pNextR3; pCur = pCur->pNextR3)
2202	pCur->pNextRC = MMHyperR3ToRC(pVM, pCur->pNextR3);
2203
2204	/* Relocate GC addresses of Page Tables. */
2205	for (PPGMMAPPING pCur = pVM->pgm.s.pMappingsR3; pCur; pCur = pCur->pNextR3)
2206	{
2207	for (RTHCUINT i = 0; i < pCur->cPTs; i++)
2208	{
2209	pCur->aPTs[i].pPTRC = MMHyperR3ToRC(pVM, pCur->aPTs[i].pPTR3);
2210	pCur->aPTs[i].paPaePTsRC = MMHyperR3ToRC(pVM, pCur->aPTs[i].paPaePTsR3);
2211	}
2212	}
2213
2214	/*
2215	* Dynamic page mapping area.
2216	*/
2217	pVM->pgm.s.paDynPageMap32BitPTEsGC += offDelta;
2218	pVM->pgm.s.paDynPageMapPaePTEsGC += offDelta;
2219	pVM->pgm.s.pbDynPageMapBaseGC += offDelta;
2220
2221	if (pVM->pgm.s.pRCDynMap)
2222	{
2223	pVM->pgm.s.pRCDynMap += offDelta;
2224	PPGMRCDYNMAP pDynMap = (PPGMRCDYNMAP)MMHyperRCToCC(pVM, pVM->pgm.s.pRCDynMap);
2225
2226	pDynMap->paPages += offDelta;
2227	PPGMRCDYNMAPENTRY paPages = (PPGMRCDYNMAPENTRY)MMHyperRCToCC(pVM, pDynMap->paPages);
2228
2229	for (uint32_t iPage = 0; iPage < pDynMap->cPages; iPage++)
2230	{
2231	paPages[iPage].pvPage += offDelta;
2232	paPages[iPage].uPte.pv += offDelta;
2233	}
2234	}
2235
2236	/*
2237	* The Zero page.
2238	*/
2239	pVM->pgm.s.pvZeroPgR0 = MMHyperR3ToR0(pVM, pVM->pgm.s.pvZeroPgR3);
2240	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
2241	AssertRelease(pVM->pgm.s.pvZeroPgR0 != NIL_RTR0PTR \|\| !VMMIsHwVirtExtForced(pVM));
2242	#else
2243	AssertRelease(pVM->pgm.s.pvZeroPgR0 != NIL_RTR0PTR);
2244	#endif
2245
2246	/*
2247	* Physical and virtual handlers.
2248	*/
2249	RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysHandlers, true, pgmR3RelocatePhysHandler, &offDelta);
2250	pVM->pgm.s.pLastPhysHandlerRC = NIL_RTRCPTR;
2251	RTAvlroGCPtrDoWithAll(&pVM->pgm.s.pTreesR3->VirtHandlers, true, pgmR3RelocateVirtHandler, &offDelta);
2252	RTAvlroGCPtrDoWithAll(&pVM->pgm.s.pTreesR3->HyperVirtHandlers, true, pgmR3RelocateHyperVirtHandler, &offDelta);
2253
2254	/*
2255	* The page pool.
2256	*/
2257	pgmR3PoolRelocate(pVM);
2258
2259	#ifdef VBOX_WITH_STATISTICS
2260	/*
2261	* Statistics.
2262	*/
2263	pVM->pgm.s.pStatsRC = MMHyperCCToRC(pVM, pVM->pgm.s.pStatsR3);
2264	for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
2265	pVM->aCpus[iCpu].pgm.s.pStatsRC = MMHyperCCToRC(pVM, pVM->aCpus[iCpu].pgm.s.pStatsR3);
2266	#endif
2267	}
2268
2269
2270	/**
2271	* Callback function for relocating a physical access handler.
2272	*
2273	* @returns 0 (continue enum)
2274	* @param pNode Pointer to a PGMPHYSHANDLER node.
2275	* @param pvUser Pointer to the offDelta. This is a pointer to the delta since we're
2276	* not certain the delta will fit in a void pointer for all possible configs.
2277	*/
2278	static DECLCALLBACK(int) pgmR3RelocatePhysHandler(PAVLROGCPHYSNODECORE pNode, void *pvUser)
2279	{
2280	PPGMPHYSHANDLER pHandler = (PPGMPHYSHANDLER)pNode;
2281	RTGCINTPTR offDelta = *(PRTGCINTPTR)pvUser;
2282	if (pHandler->pfnHandlerRC)
2283	pHandler->pfnHandlerRC += offDelta;
2284	if (pHandler->pvUserRC >= 0x10000)
2285	pHandler->pvUserRC += offDelta;
2286	return 0;
2287	}
2288
2289
2290	/**
2291	* Callback function for relocating a virtual access handler.
2292	*
2293	* @returns 0 (continue enum)
2294	* @param pNode Pointer to a PGMVIRTHANDLER node.
2295	* @param pvUser Pointer to the offDelta. This is a pointer to the delta since we're
2296	* not certain the delta will fit in a void pointer for all possible configs.
2297	*/
2298	static DECLCALLBACK(int) pgmR3RelocateVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser)
2299	{
2300	PPGMVIRTHANDLER pHandler = (PPGMVIRTHANDLER)pNode;
2301	RTGCINTPTR offDelta = *(PRTGCINTPTR)pvUser;
2302	Assert( pHandler->enmType == PGMVIRTHANDLERTYPE_ALL
2303	\|\| pHandler->enmType == PGMVIRTHANDLERTYPE_WRITE);
2304	Assert(pHandler->pfnHandlerRC);
2305	pHandler->pfnHandlerRC += offDelta;
2306	return 0;
2307	}
2308
2309
2310	/**
2311	* Callback function for relocating a virtual access handler for the hypervisor mapping.
2312	*
2313	* @returns 0 (continue enum)
2314	* @param pNode Pointer to a PGMVIRTHANDLER node.
2315	* @param pvUser Pointer to the offDelta. This is a pointer to the delta since we're
2316	* not certain the delta will fit in a void pointer for all possible configs.
2317	*/
2318	static DECLCALLBACK(int) pgmR3RelocateHyperVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser)
2319	{
2320	PPGMVIRTHANDLER pHandler = (PPGMVIRTHANDLER)pNode;
2321	RTGCINTPTR offDelta = *(PRTGCINTPTR)pvUser;
2322	Assert(pHandler->enmType == PGMVIRTHANDLERTYPE_HYPERVISOR);
2323	Assert(pHandler->pfnHandlerRC);
2324	pHandler->pfnHandlerRC += offDelta;
2325	return 0;
2326	}
2327
2328
2329	/**
2330	* Resets a virtual CPU when unplugged.
2331	*
2332	* @param pVM The VM handle.
2333	* @param pVCpu The virtual CPU handle.
2334	*/
2335	VMMR3DECL(void) PGMR3ResetUnpluggedCpu(PVM pVM, PVMCPU pVCpu)
2336	{
2337	int rc = PGM_GST_PFN(Exit, pVCpu)(pVCpu);
2338	AssertRC(rc);
2339
2340	rc = PGMR3ChangeMode(pVM, pVCpu, PGMMODE_REAL);
2341	AssertRC(rc);
2342
2343	STAM_REL_COUNTER_RESET(&pVCpu->pgm.s.cGuestModeChanges);
2344
2345	pgmR3PoolResetUnpluggedCpu(pVM, pVCpu);
2346
2347	/*
2348	* Re-init other members.
2349	*/
2350	pVCpu->pgm.s.fA20Enabled = true;
2351
2352	/*
2353	* Clear the FFs PGM owns.
2354	*/
2355	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
2356	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL);
2357	}
2358
2359
2360	/**
2361	* The VM is being reset.
2362	*
2363	* For the PGM component this means that any PD write monitors
2364	* needs to be removed.
2365	*
2366	* @param pVM VM handle.
2367	*/
2368	VMMR3DECL(void) PGMR3Reset(PVM pVM)
2369	{
2370	int rc;
2371
2372	LogFlow(("PGMR3Reset:\n"));
2373	VM_ASSERT_EMT(pVM);
2374
2375	pgmLock(pVM);
2376
2377	/*
2378	* Unfix any fixed mappings and disable CR3 monitoring.
2379	*/
2380	pVM->pgm.s.fMappingsFixed = false;
2381	pVM->pgm.s.fMappingsFixedRestored = false;
2382	pVM->pgm.s.GCPtrMappingFixed = NIL_RTGCPTR;
2383	pVM->pgm.s.cbMappingFixed = 0;
2384
2385	/*
2386	* Exit the guest paging mode before the pgm pool gets reset.
2387	* Important to clean up the amd64 case.
2388	*/
2389	for (VMCPUID i = 0; i < pVM->cCpus; i++)
2390	{
2391	PVMCPU pVCpu = &pVM->aCpus[i];
2392	rc = PGM_GST_PFN(Exit, pVCpu)(pVCpu);
2393	AssertRC(rc);
2394	}
2395
2396	#ifdef DEBUG
2397	DBGFR3InfoLog(pVM, "mappings", NULL);
2398	DBGFR3InfoLog(pVM, "handlers", "all nostat");
2399	#endif
2400
2401	/*
2402	* Switch mode back to real mode. (before resetting the pgm pool!)
2403	*/
2404	for (VMCPUID i = 0; i < pVM->cCpus; i++)
2405	{
2406	PVMCPU pVCpu = &pVM->aCpus[i];
2407
2408	rc = PGMR3ChangeMode(pVM, pVCpu, PGMMODE_REAL);
2409	AssertRC(rc);
2410
2411	STAM_REL_COUNTER_RESET(&pVCpu->pgm.s.cGuestModeChanges);
2412	}
2413
2414	/*
2415	* Reset the shadow page pool.
2416	*/
2417	pgmR3PoolReset(pVM);
2418
2419	/*
2420	* Re-init various other members and clear the FFs that PGM owns.
2421	*/
2422	for (VMCPUID i = 0; i < pVM->cCpus; i++)
2423	{
2424	PVMCPU pVCpu = &pVM->aCpus[i];
2425
2426	pVCpu->pgm.s.fA20Enabled = true;
2427	pVCpu->pgm.s.fGst32BitPageSizeExtension = false;
2428	PGMNotifyNxeChanged(pVCpu, false);
2429
2430	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
2431	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL);
2432	}
2433
2434	/*
2435	* Reset (zero) RAM and shadow ROM pages.
2436	*/
2437	rc = pgmR3PhysRamReset(pVM);
2438	if (RT_SUCCESS(rc))
2439	rc = pgmR3PhysRomReset(pVM);
2440
2441
2442	pgmUnlock(pVM);
2443	AssertReleaseRC(rc);
2444	}
2445
2446
2447	#ifdef VBOX_STRICT
2448	/**
2449	* VM state change callback for clearing fNoMorePhysWrites after
2450	* a snapshot has been created.
2451	*/
2452	static DECLCALLBACK(void) pgmR3ResetNoMorePhysWritesFlag(PVM pVM, VMSTATE enmState, VMSTATE enmOldState, void *pvUser)
2453	{
2454	if ( enmState == VMSTATE_RUNNING
2455	\|\| enmState == VMSTATE_RESUMING)
2456	pVM->pgm.s.fNoMorePhysWrites = false;
2457	}
2458	#endif
2459
2460
2461	/**
2462	* Terminates the PGM.
2463	*
2464	* @returns VBox status code.
2465	* @param pVM Pointer to VM structure.
2466	*/
2467	VMMR3DECL(int) PGMR3Term(PVM pVM)
2468	{
2469	/* Must free shared pages here. */
2470	pgmLock(pVM);
2471	pgmR3PhysRamTerm(pVM);
2472	pgmR3PhysRomTerm(pVM);
2473	pgmUnlock(pVM);
2474
2475	PGMDeregisterStringFormatTypes();
2476	return PDMR3CritSectDelete(&pVM->pgm.s.CritSect);
2477	}
2478
2479
2480	/**
2481	* Terminates the per-VCPU PGM.
2482	*
2483	* Termination means cleaning up and freeing all resources,
2484	* the VM it self is at this point powered off or suspended.
2485	*
2486	* @returns VBox status code.
2487	* @param pVM The VM to operate on.
2488	*/
2489	VMMR3DECL(int) PGMR3TermCPU(PVM pVM)
2490	{
2491	return 0;
2492	}
2493
2494
2495	/**
2496	* Show paging mode.
2497	*
2498	* @param pVM VM Handle.
2499	* @param pHlp The info helpers.
2500	* @param pszArgs "all" (default), "guest", "shadow" or "host".
2501	*/
2502	static DECLCALLBACK(void) pgmR3InfoMode(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2503	{
2504	/* digest argument. */
2505	bool fGuest, fShadow, fHost;
2506	if (pszArgs)
2507	pszArgs = RTStrStripL(pszArgs);
2508	if (!pszArgs \|\| !*pszArgs \|\| strstr(pszArgs, "all"))
2509	fShadow = fHost = fGuest = true;
2510	else
2511	{
2512	fShadow = fHost = fGuest = false;
2513	if (strstr(pszArgs, "guest"))
2514	fGuest = true;
2515	if (strstr(pszArgs, "shadow"))
2516	fShadow = true;
2517	if (strstr(pszArgs, "host"))
2518	fHost = true;
2519	}
2520
2521	/** @todo SMP support! */
2522	/* print info. */
2523	if (fGuest)
2524	pHlp->pfnPrintf(pHlp, "Guest paging mode: %s, changed %RU64 times, A20 %s\n",
2525	PGMGetModeName(pVM->aCpus[0].pgm.s.enmGuestMode), pVM->aCpus[0].pgm.s.cGuestModeChanges.c,
2526	pVM->aCpus[0].pgm.s.fA20Enabled ? "enabled" : "disabled");
2527	if (fShadow)
2528	pHlp->pfnPrintf(pHlp, "Shadow paging mode: %s\n", PGMGetModeName(pVM->aCpus[0].pgm.s.enmShadowMode));
2529	if (fHost)
2530	{
2531	const char *psz;
2532	switch (pVM->pgm.s.enmHostMode)
2533	{
2534	case SUPPAGINGMODE_INVALID: psz = "invalid"; break;
2535	case SUPPAGINGMODE_32_BIT: psz = "32-bit"; break;
2536	case SUPPAGINGMODE_32_BIT_GLOBAL: psz = "32-bit+G"; break;
2537	case SUPPAGINGMODE_PAE: psz = "PAE"; break;
2538	case SUPPAGINGMODE_PAE_GLOBAL: psz = "PAE+G"; break;
2539	case SUPPAGINGMODE_PAE_NX: psz = "PAE+NX"; break;
2540	case SUPPAGINGMODE_PAE_GLOBAL_NX: psz = "PAE+G+NX"; break;
2541	case SUPPAGINGMODE_AMD64: psz = "AMD64"; break;
2542	case SUPPAGINGMODE_AMD64_GLOBAL: psz = "AMD64+G"; break;
2543	case SUPPAGINGMODE_AMD64_NX: psz = "AMD64+NX"; break;
2544	case SUPPAGINGMODE_AMD64_GLOBAL_NX: psz = "AMD64+G+NX"; break;
2545	default: psz = "unknown"; break;
2546	}
2547	pHlp->pfnPrintf(pHlp, "Host paging mode: %s\n", psz);
2548	}
2549	}
2550
2551
2552	/**
2553	* Dump registered MMIO ranges to the log.
2554	*
2555	* @param pVM VM Handle.
2556	* @param pHlp The info helpers.
2557	* @param pszArgs Arguments, ignored.
2558	*/
2559	static DECLCALLBACK(void) pgmR3PhysInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2560	{
2561	NOREF(pszArgs);
2562	pHlp->pfnPrintf(pHlp,
2563	"RAM ranges (pVM=%p)\n"
2564	"%.s %.s\n",
2565	pVM,
2566	sizeof(RTGCPHYS) * 4 + 1, "GC Phys Range ",
2567	sizeof(RTHCPTR) * 2, "pvHC ");
2568
2569	for (PPGMRAMRANGE pCur = pVM->pgm.s.pRamRangesR3; pCur; pCur = pCur->pNextR3)
2570	pHlp->pfnPrintf(pHlp,
2571	"%RGp-%RGp %RHv %s\n",
2572	pCur->GCPhys,
2573	pCur->GCPhysLast,
2574	pCur->pvR3,
2575	pCur->pszDesc);
2576	}
2577
2578	/**
2579	* Dump the page directory to the log.
2580	*
2581	* @param pVM VM Handle.
2582	* @param pHlp The info helpers.
2583	* @param pszArgs Arguments, ignored.
2584	*/
2585	static DECLCALLBACK(void) pgmR3InfoCr3(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2586	{
2587	/** @todo SMP support!! */
2588	PVMCPU pVCpu = &pVM->aCpus[0];
2589
2590	/** @todo fix this! Convert the PGMR3DumpHierarchyHC functions to do guest stuff. */
2591	/* Big pages supported? */
2592	const bool fPSE = !!(CPUMGetGuestCR4(pVCpu) & X86_CR4_PSE);
2593
2594	/* Global pages supported? */
2595	const bool fPGE = !!(CPUMGetGuestCR4(pVCpu) & X86_CR4_PGE);
2596
2597	NOREF(pszArgs);
2598
2599	/*
2600	* Get page directory addresses.
2601	*/
2602	PX86PD pPDSrc = pgmGstGet32bitPDPtr(pVCpu);
2603	Assert(pPDSrc);
2604	Assert(PGMPhysGCPhys2R3PtrAssert(pVM, (RTGCPHYS)(CPUMGetGuestCR3(pVCpu) & X86_CR3_PAGE_MASK), sizeof(*pPDSrc)) == pPDSrc);
2605
2606	/*
2607	* Iterate the page directory.
2608	*/
2609	for (unsigned iPD = 0; iPD < RT_ELEMENTS(pPDSrc->a); iPD++)
2610	{
2611	X86PDE PdeSrc = pPDSrc->a[iPD];
2612	if (PdeSrc.n.u1Present)
2613	{
2614	if (PdeSrc.b.u1Size && fPSE)
2615	pHlp->pfnPrintf(pHlp,
2616	"%04X - %RGp P=%d U=%d RW=%d G=%d - BIG\n",
2617	iPD,
2618	pgmGstGet4MBPhysPage(&pVM->pgm.s, PdeSrc),
2619	PdeSrc.b.u1Present, PdeSrc.b.u1User, PdeSrc.b.u1Write, PdeSrc.b.u1Global && fPGE);
2620	else
2621	pHlp->pfnPrintf(pHlp,
2622	"%04X - %RGp P=%d U=%d RW=%d [G=%d]\n",
2623	iPD,
2624	(RTGCPHYS)(PdeSrc.u & X86_PDE_PG_MASK),
2625	PdeSrc.n.u1Present, PdeSrc.n.u1User, PdeSrc.n.u1Write, PdeSrc.b.u1Global && fPGE);
2626	}
2627	}
2628	}
2629
2630
2631	/**
2632	* Service a VMMCALLRING3_PGM_LOCK call.
2633	*
2634	* @returns VBox status code.
2635	* @param pVM The VM handle.
2636	*/
2637	VMMR3DECL(int) PGMR3LockCall(PVM pVM)
2638	{
2639	int rc = PDMR3CritSectEnterEx(&pVM->pgm.s.CritSect, true /* fHostCall */);
2640	AssertRC(rc);
2641	return rc;
2642	}
2643
2644
2645	/**
2646	* Converts a PGMMODE value to a PGM_TYPE_* \#define.
2647	*
2648	* @returns PGM_TYPE_*.
2649	* @param pgmMode The mode value to convert.
2650	*/
2651	DECLINLINE(unsigned) pgmModeToType(PGMMODE pgmMode)
2652	{
2653	switch (pgmMode)
2654	{
2655	case PGMMODE_REAL: return PGM_TYPE_REAL;
2656	case PGMMODE_PROTECTED: return PGM_TYPE_PROT;
2657	case PGMMODE_32_BIT: return PGM_TYPE_32BIT;
2658	case PGMMODE_PAE:
2659	case PGMMODE_PAE_NX: return PGM_TYPE_PAE;
2660	case PGMMODE_AMD64:
2661	case PGMMODE_AMD64_NX: return PGM_TYPE_AMD64;
2662	case PGMMODE_NESTED: return PGM_TYPE_NESTED;
2663	case PGMMODE_EPT: return PGM_TYPE_EPT;
2664	default:
2665	AssertFatalMsgFailed(("pgmMode=%d\n", pgmMode));
2666	}
2667	}
2668
2669
2670	/**
2671	* Gets the index into the paging mode data array of a SHW+GST mode.
2672	*
2673	* @returns PGM::paPagingData index.
2674	* @param uShwType The shadow paging mode type.
2675	* @param uGstType The guest paging mode type.
2676	*/
2677	DECLINLINE(unsigned) pgmModeDataIndex(unsigned uShwType, unsigned uGstType)
2678	{
2679	Assert(uShwType >= PGM_TYPE_32BIT && uShwType <= PGM_TYPE_MAX);
2680	Assert(uGstType >= PGM_TYPE_REAL && uGstType <= PGM_TYPE_AMD64);
2681	return (uShwType - PGM_TYPE_32BIT) * (PGM_TYPE_AMD64 - PGM_TYPE_REAL + 1)
2682	+ (uGstType - PGM_TYPE_REAL);
2683	}
2684
2685
2686	/**
2687	* Gets the index into the paging mode data array of a SHW+GST mode.
2688	*
2689	* @returns PGM::paPagingData index.
2690	* @param enmShw The shadow paging mode.
2691	* @param enmGst The guest paging mode.
2692	*/
2693	DECLINLINE(unsigned) pgmModeDataIndexByMode(PGMMODE enmShw, PGMMODE enmGst)
2694	{
2695	Assert(enmShw >= PGMMODE_32_BIT && enmShw <= PGMMODE_MAX);
2696	Assert(enmGst > PGMMODE_INVALID && enmGst < PGMMODE_MAX);
2697	return pgmModeDataIndex(pgmModeToType(enmShw), pgmModeToType(enmGst));
2698	}
2699
2700
2701	/**
2702	* Calculates the max data index.
2703	* @returns The number of entries in the paging data array.
2704	*/
2705	DECLINLINE(unsigned) pgmModeDataMaxIndex(void)
2706	{
2707	return pgmModeDataIndex(PGM_TYPE_MAX, PGM_TYPE_AMD64) + 1;
2708	}
2709
2710
2711	/**
2712	* Initializes the paging mode data kept in PGM::paModeData.
2713	*
2714	* @param pVM The VM handle.
2715	* @param fResolveGCAndR0 Indicate whether or not GC and Ring-0 symbols can be resolved now.
2716	* This is used early in the init process to avoid trouble with PDM
2717	* not being initialized yet.
2718	*/
2719	static int pgmR3ModeDataInit(PVM pVM, bool fResolveGCAndR0)
2720	{
2721	PPGMMODEDATA pModeData;
2722	int rc;
2723
2724	/*
2725	* Allocate the array on the first call.
2726	*/
2727	if (!pVM->pgm.s.paModeData)
2728	{
2729	pVM->pgm.s.paModeData = (PPGMMODEDATA)MMR3HeapAllocZ(pVM, MM_TAG_PGM, sizeof(PGMMODEDATA) * pgmModeDataMaxIndex());
2730	AssertReturn(pVM->pgm.s.paModeData, VERR_NO_MEMORY);
2731	}
2732
2733	/*
2734	* Initialize the array entries.
2735	*/
2736	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_32BIT, PGM_TYPE_REAL)];
2737	pModeData->uShwType = PGM_TYPE_32BIT;
2738	pModeData->uGstType = PGM_TYPE_REAL;
2739	rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2740	rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2741	rc = PGM_BTH_NAME_32BIT_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2742
2743	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_32BIT, PGMMODE_PROTECTED)];
2744	pModeData->uShwType = PGM_TYPE_32BIT;
2745	pModeData->uGstType = PGM_TYPE_PROT;
2746	rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2747	rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2748	rc = PGM_BTH_NAME_32BIT_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2749
2750	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_32BIT, PGM_TYPE_32BIT)];
2751	pModeData->uShwType = PGM_TYPE_32BIT;
2752	pModeData->uGstType = PGM_TYPE_32BIT;
2753	rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2754	rc = PGM_GST_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2755	rc = PGM_BTH_NAME_32BIT_32BIT(InitData)(pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2756
2757	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_REAL)];
2758	pModeData->uShwType = PGM_TYPE_PAE;
2759	pModeData->uGstType = PGM_TYPE_REAL;
2760	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2761	rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2762	rc = PGM_BTH_NAME_PAE_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2763
2764	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_PROT)];
2765	pModeData->uShwType = PGM_TYPE_PAE;
2766	pModeData->uGstType = PGM_TYPE_PROT;
2767	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2768	rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2769	rc = PGM_BTH_NAME_PAE_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2770
2771	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_32BIT)];
2772	pModeData->uShwType = PGM_TYPE_PAE;
2773	pModeData->uGstType = PGM_TYPE_32BIT;
2774	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2775	rc = PGM_GST_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2776	rc = PGM_BTH_NAME_PAE_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2777
2778	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_PAE)];
2779	pModeData->uShwType = PGM_TYPE_PAE;
2780	pModeData->uGstType = PGM_TYPE_PAE;
2781	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2782	rc = PGM_GST_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2783	rc = PGM_BTH_NAME_PAE_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2784
2785	#ifdef VBOX_WITH_64_BITS_GUESTS
2786	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_AMD64, PGM_TYPE_AMD64)];
2787	pModeData->uShwType = PGM_TYPE_AMD64;
2788	pModeData->uGstType = PGM_TYPE_AMD64;
2789	rc = PGM_SHW_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2790	rc = PGM_GST_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2791	rc = PGM_BTH_NAME_AMD64_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2792	#endif
2793
2794	/* The nested paging mode. */
2795	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_REAL)];
2796	pModeData->uShwType = PGM_TYPE_NESTED;
2797	pModeData->uGstType = PGM_TYPE_REAL;
2798	rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2799	rc = PGM_BTH_NAME_NESTED_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2800
2801	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGMMODE_PROTECTED)];
2802	pModeData->uShwType = PGM_TYPE_NESTED;
2803	pModeData->uGstType = PGM_TYPE_PROT;
2804	rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2805	rc = PGM_BTH_NAME_NESTED_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2806
2807	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_32BIT)];
2808	pModeData->uShwType = PGM_TYPE_NESTED;
2809	pModeData->uGstType = PGM_TYPE_32BIT;
2810	rc = PGM_GST_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2811	rc = PGM_BTH_NAME_NESTED_32BIT(InitData)(pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2812
2813	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_PAE)];
2814	pModeData->uShwType = PGM_TYPE_NESTED;
2815	pModeData->uGstType = PGM_TYPE_PAE;
2816	rc = PGM_GST_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2817	rc = PGM_BTH_NAME_NESTED_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2818
2819	#ifdef VBOX_WITH_64_BITS_GUESTS
2820	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_AMD64)];
2821	pModeData->uShwType = PGM_TYPE_NESTED;
2822	pModeData->uGstType = PGM_TYPE_AMD64;
2823	rc = PGM_GST_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2824	rc = PGM_BTH_NAME_NESTED_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2825	#endif
2826
2827	/* The shadow part of the nested callback mode depends on the host paging mode (AMD-V only). */
2828	switch (pVM->pgm.s.enmHostMode)
2829	{
2830	#if HC_ARCH_BITS == 32
2831	case SUPPAGINGMODE_32_BIT:
2832	case SUPPAGINGMODE_32_BIT_GLOBAL:
2833	for (unsigned i = PGM_TYPE_REAL; i <= PGM_TYPE_PAE; i++)
2834	{
2835	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, i)];
2836	rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2837	}
2838	# ifdef VBOX_WITH_64_BITS_GUESTS
2839	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_AMD64)];
2840	rc = PGM_SHW_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2841	# endif
2842	break;
2843
2844	case SUPPAGINGMODE_PAE:
2845	case SUPPAGINGMODE_PAE_NX:
2846	case SUPPAGINGMODE_PAE_GLOBAL:
2847	case SUPPAGINGMODE_PAE_GLOBAL_NX:
2848	for (unsigned i = PGM_TYPE_REAL; i <= PGM_TYPE_PAE; i++)
2849	{
2850	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, i)];
2851	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2852	}
2853	# ifdef VBOX_WITH_64_BITS_GUESTS
2854	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_AMD64)];
2855	rc = PGM_SHW_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2856	# endif
2857	break;
2858	#endif /* HC_ARCH_BITS == 32 */
2859
2860	#if HC_ARCH_BITS == 64 \|\| defined(RT_OS_DARWIN)
2861	case SUPPAGINGMODE_AMD64:
2862	case SUPPAGINGMODE_AMD64_GLOBAL:
2863	case SUPPAGINGMODE_AMD64_NX:
2864	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
2865	# ifdef VBOX_WITH_64_BITS_GUESTS
2866	for (unsigned i = PGM_TYPE_REAL; i <= PGM_TYPE_AMD64; i++)
2867	# else
2868	for (unsigned i = PGM_TYPE_REAL; i <= PGM_TYPE_PAE; i++)
2869	# endif
2870	{
2871	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, i)];
2872	rc = PGM_SHW_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2873	}
2874	break;
2875	#endif /* HC_ARCH_BITS == 64 \|\| RT_OS_DARWIN */
2876
2877	default:
2878	AssertFailed();
2879	break;
2880	}
2881
2882	/* Extended paging (EPT) / Intel VT-x */
2883	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_REAL)];
2884	pModeData->uShwType = PGM_TYPE_EPT;
2885	pModeData->uGstType = PGM_TYPE_REAL;
2886	rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2887	rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2888	rc = PGM_BTH_NAME_EPT_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2889
2890	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_PROT)];
2891	pModeData->uShwType = PGM_TYPE_EPT;
2892	pModeData->uGstType = PGM_TYPE_PROT;
2893	rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2894	rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2895	rc = PGM_BTH_NAME_EPT_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2896
2897	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_32BIT)];
2898	pModeData->uShwType = PGM_TYPE_EPT;
2899	pModeData->uGstType = PGM_TYPE_32BIT;
2900	rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2901	rc = PGM_GST_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2902	rc = PGM_BTH_NAME_EPT_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2903
2904	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_PAE)];
2905	pModeData->uShwType = PGM_TYPE_EPT;
2906	pModeData->uGstType = PGM_TYPE_PAE;
2907	rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2908	rc = PGM_GST_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2909	rc = PGM_BTH_NAME_EPT_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2910
2911	#ifdef VBOX_WITH_64_BITS_GUESTS
2912	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_AMD64)];
2913	pModeData->uShwType = PGM_TYPE_EPT;
2914	pModeData->uGstType = PGM_TYPE_AMD64;
2915	rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2916	rc = PGM_GST_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2917	rc = PGM_BTH_NAME_EPT_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2918	#endif
2919	return VINF_SUCCESS;
2920	}
2921
2922
2923	/**
2924	* Switch to different (or relocated in the relocate case) mode data.
2925	*
2926	* @param pVM The VM handle.
2927	* @param pVCpu The VMCPU to operate on.
2928	* @param enmShw The the shadow paging mode.
2929	* @param enmGst The the guest paging mode.
2930	*/
2931	static void pgmR3ModeDataSwitch(PVM pVM, PVMCPU pVCpu, PGMMODE enmShw, PGMMODE enmGst)
2932	{
2933	PPGMMODEDATA pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndexByMode(enmShw, enmGst)];
2934
2935	Assert(pModeData->uGstType == pgmModeToType(enmGst));
2936	Assert(pModeData->uShwType == pgmModeToType(enmShw));
2937
2938	/* shadow */
2939	pVCpu->pgm.s.pfnR3ShwRelocate = pModeData->pfnR3ShwRelocate;
2940	pVCpu->pgm.s.pfnR3ShwExit = pModeData->pfnR3ShwExit;
2941	pVCpu->pgm.s.pfnR3ShwGetPage = pModeData->pfnR3ShwGetPage;
2942	Assert(pVCpu->pgm.s.pfnR3ShwGetPage);
2943	pVCpu->pgm.s.pfnR3ShwModifyPage = pModeData->pfnR3ShwModifyPage;
2944
2945	pVCpu->pgm.s.pfnRCShwGetPage = pModeData->pfnRCShwGetPage;
2946	pVCpu->pgm.s.pfnRCShwModifyPage = pModeData->pfnRCShwModifyPage;
2947
2948	pVCpu->pgm.s.pfnR0ShwGetPage = pModeData->pfnR0ShwGetPage;
2949	pVCpu->pgm.s.pfnR0ShwModifyPage = pModeData->pfnR0ShwModifyPage;
2950
2951
2952	/* guest */
2953	pVCpu->pgm.s.pfnR3GstRelocate = pModeData->pfnR3GstRelocate;
2954	pVCpu->pgm.s.pfnR3GstExit = pModeData->pfnR3GstExit;
2955	pVCpu->pgm.s.pfnR3GstGetPage = pModeData->pfnR3GstGetPage;
2956	Assert(pVCpu->pgm.s.pfnR3GstGetPage);
2957	pVCpu->pgm.s.pfnR3GstModifyPage = pModeData->pfnR3GstModifyPage;
2958	pVCpu->pgm.s.pfnR3GstGetPDE = pModeData->pfnR3GstGetPDE;
2959	pVCpu->pgm.s.pfnRCGstGetPage = pModeData->pfnRCGstGetPage;
2960	pVCpu->pgm.s.pfnRCGstModifyPage = pModeData->pfnRCGstModifyPage;
2961	pVCpu->pgm.s.pfnRCGstGetPDE = pModeData->pfnRCGstGetPDE;
2962	pVCpu->pgm.s.pfnR0GstGetPage = pModeData->pfnR0GstGetPage;
2963	pVCpu->pgm.s.pfnR0GstModifyPage = pModeData->pfnR0GstModifyPage;
2964	pVCpu->pgm.s.pfnR0GstGetPDE = pModeData->pfnR0GstGetPDE;
2965
2966	/* both */
2967	pVCpu->pgm.s.pfnR3BthRelocate = pModeData->pfnR3BthRelocate;
2968	pVCpu->pgm.s.pfnR3BthInvalidatePage = pModeData->pfnR3BthInvalidatePage;
2969	pVCpu->pgm.s.pfnR3BthSyncCR3 = pModeData->pfnR3BthSyncCR3;
2970	Assert(pVCpu->pgm.s.pfnR3BthSyncCR3);
2971	pVCpu->pgm.s.pfnR3BthPrefetchPage = pModeData->pfnR3BthPrefetchPage;
2972	pVCpu->pgm.s.pfnR3BthVerifyAccessSyncPage = pModeData->pfnR3BthVerifyAccessSyncPage;
2973	#ifdef VBOX_STRICT
2974	pVCpu->pgm.s.pfnR3BthAssertCR3 = pModeData->pfnR3BthAssertCR3;
2975	#endif
2976	pVCpu->pgm.s.pfnR3BthMapCR3 = pModeData->pfnR3BthMapCR3;
2977	pVCpu->pgm.s.pfnR3BthUnmapCR3 = pModeData->pfnR3BthUnmapCR3;
2978
2979	pVCpu->pgm.s.pfnRCBthTrap0eHandler = pModeData->pfnRCBthTrap0eHandler;
2980	pVCpu->pgm.s.pfnRCBthInvalidatePage = pModeData->pfnRCBthInvalidatePage;
2981	pVCpu->pgm.s.pfnRCBthSyncCR3 = pModeData->pfnRCBthSyncCR3;
2982	pVCpu->pgm.s.pfnRCBthPrefetchPage = pModeData->pfnRCBthPrefetchPage;
2983	pVCpu->pgm.s.pfnRCBthVerifyAccessSyncPage = pModeData->pfnRCBthVerifyAccessSyncPage;
2984	#ifdef VBOX_STRICT
2985	pVCpu->pgm.s.pfnRCBthAssertCR3 = pModeData->pfnRCBthAssertCR3;
2986	#endif
2987	pVCpu->pgm.s.pfnRCBthMapCR3 = pModeData->pfnRCBthMapCR3;
2988	pVCpu->pgm.s.pfnRCBthUnmapCR3 = pModeData->pfnRCBthUnmapCR3;
2989
2990	pVCpu->pgm.s.pfnR0BthTrap0eHandler = pModeData->pfnR0BthTrap0eHandler;
2991	pVCpu->pgm.s.pfnR0BthInvalidatePage = pModeData->pfnR0BthInvalidatePage;
2992	pVCpu->pgm.s.pfnR0BthSyncCR3 = pModeData->pfnR0BthSyncCR3;
2993	pVCpu->pgm.s.pfnR0BthPrefetchPage = pModeData->pfnR0BthPrefetchPage;
2994	pVCpu->pgm.s.pfnR0BthVerifyAccessSyncPage = pModeData->pfnR0BthVerifyAccessSyncPage;
2995	#ifdef VBOX_STRICT
2996	pVCpu->pgm.s.pfnR0BthAssertCR3 = pModeData->pfnR0BthAssertCR3;
2997	#endif
2998	pVCpu->pgm.s.pfnR0BthMapCR3 = pModeData->pfnR0BthMapCR3;
2999	pVCpu->pgm.s.pfnR0BthUnmapCR3 = pModeData->pfnR0BthUnmapCR3;
3000	}
3001
3002
3003	/**
3004	* Calculates the shadow paging mode.
3005	*
3006	* @returns The shadow paging mode.
3007	* @param pVM VM handle.
3008	* @param enmGuestMode The guest mode.
3009	* @param enmHostMode The host mode.
3010	* @param enmShadowMode The current shadow mode.
3011	* @param penmSwitcher Where to store the switcher to use.
3012	* VMMSWITCHER_INVALID means no change.
3013	*/
3014	static PGMMODE pgmR3CalcShadowMode(PVM pVM, PGMMODE enmGuestMode, SUPPAGINGMODE enmHostMode, PGMMODE enmShadowMode, VMMSWITCHER *penmSwitcher)
3015	{
3016	VMMSWITCHER enmSwitcher = VMMSWITCHER_INVALID;
3017	switch (enmGuestMode)
3018	{
3019	/*
3020	* When switching to real or protected mode we don't change
3021	* anything since it's likely that we'll switch back pretty soon.
3022	*
3023	* During pgmR3InitPaging we'll end up here with PGMMODE_INVALID
3024	* and is supposed to determine which shadow paging and switcher to
3025	* use during init.
3026	*/
3027	case PGMMODE_REAL:
3028	case PGMMODE_PROTECTED:
3029	if ( enmShadowMode != PGMMODE_INVALID
3030	&& !HWACCMIsEnabled(pVM) /* always switch in hwaccm mode! */)
3031	break; /* (no change) */
3032
3033	switch (enmHostMode)
3034	{
3035	case SUPPAGINGMODE_32_BIT:
3036	case SUPPAGINGMODE_32_BIT_GLOBAL:
3037	enmShadowMode = PGMMODE_32_BIT;
3038	enmSwitcher = VMMSWITCHER_32_TO_32;
3039	break;
3040
3041	case SUPPAGINGMODE_PAE:
3042	case SUPPAGINGMODE_PAE_NX:
3043	case SUPPAGINGMODE_PAE_GLOBAL:
3044	case SUPPAGINGMODE_PAE_GLOBAL_NX:
3045	enmShadowMode = PGMMODE_PAE;
3046	enmSwitcher = VMMSWITCHER_PAE_TO_PAE;
3047	#ifdef DEBUG_bird
3048	if (RTEnvExist("VBOX_32BIT"))
3049	{
3050	enmShadowMode = PGMMODE_32_BIT;
3051	enmSwitcher = VMMSWITCHER_PAE_TO_32;
3052	}
3053	#endif
3054	break;
3055
3056	case SUPPAGINGMODE_AMD64:
3057	case SUPPAGINGMODE_AMD64_GLOBAL:
3058	case SUPPAGINGMODE_AMD64_NX:
3059	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
3060	enmShadowMode = PGMMODE_PAE;
3061	enmSwitcher = VMMSWITCHER_AMD64_TO_PAE;
3062	#ifdef DEBUG_bird
3063	if (RTEnvExist("VBOX_32BIT"))
3064	{
3065	enmShadowMode = PGMMODE_32_BIT;
3066	enmSwitcher = VMMSWITCHER_AMD64_TO_32;
3067	}
3068	#endif
3069	break;
3070
3071	default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
3072	}
3073	break;
3074
3075	case PGMMODE_32_BIT:
3076	switch (enmHostMode)
3077	{
3078	case SUPPAGINGMODE_32_BIT:
3079	case SUPPAGINGMODE_32_BIT_GLOBAL:
3080	enmShadowMode = PGMMODE_32_BIT;
3081	enmSwitcher = VMMSWITCHER_32_TO_32;
3082	break;
3083
3084	case SUPPAGINGMODE_PAE:
3085	case SUPPAGINGMODE_PAE_NX:
3086	case SUPPAGINGMODE_PAE_GLOBAL:
3087	case SUPPAGINGMODE_PAE_GLOBAL_NX:
3088	enmShadowMode = PGMMODE_PAE;
3089	enmSwitcher = VMMSWITCHER_PAE_TO_PAE;
3090	#ifdef DEBUG_bird
3091	if (RTEnvExist("VBOX_32BIT"))
3092	{
3093	enmShadowMode = PGMMODE_32_BIT;
3094	enmSwitcher = VMMSWITCHER_PAE_TO_32;
3095	}
3096	#endif
3097	break;
3098
3099	case SUPPAGINGMODE_AMD64:
3100	case SUPPAGINGMODE_AMD64_GLOBAL:
3101	case SUPPAGINGMODE_AMD64_NX:
3102	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
3103	enmShadowMode = PGMMODE_PAE;
3104	enmSwitcher = VMMSWITCHER_AMD64_TO_PAE;
3105	#ifdef DEBUG_bird
3106	if (RTEnvExist("VBOX_32BIT"))
3107	{
3108	enmShadowMode = PGMMODE_32_BIT;
3109	enmSwitcher = VMMSWITCHER_AMD64_TO_32;
3110	}
3111	#endif
3112	break;
3113
3114	default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
3115	}
3116	break;
3117
3118	case PGMMODE_PAE:
3119	case PGMMODE_PAE_NX: /** @todo This might require more switchers and guest+both modes. */
3120	switch (enmHostMode)
3121	{
3122	case SUPPAGINGMODE_32_BIT:
3123	case SUPPAGINGMODE_32_BIT_GLOBAL:
3124	enmShadowMode = PGMMODE_PAE;
3125	enmSwitcher = VMMSWITCHER_32_TO_PAE;
3126	break;
3127
3128	case SUPPAGINGMODE_PAE:
3129	case SUPPAGINGMODE_PAE_NX:
3130	case SUPPAGINGMODE_PAE_GLOBAL:
3131	case SUPPAGINGMODE_PAE_GLOBAL_NX:
3132	enmShadowMode = PGMMODE_PAE;
3133	enmSwitcher = VMMSWITCHER_PAE_TO_PAE;
3134	break;
3135
3136	case SUPPAGINGMODE_AMD64:
3137	case SUPPAGINGMODE_AMD64_GLOBAL:
3138	case SUPPAGINGMODE_AMD64_NX:
3139	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
3140	enmShadowMode = PGMMODE_PAE;
3141	enmSwitcher = VMMSWITCHER_AMD64_TO_PAE;
3142	break;
3143
3144	default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
3145	}
3146	break;
3147
3148	case PGMMODE_AMD64:
3149	case PGMMODE_AMD64_NX:
3150	switch (enmHostMode)
3151	{
3152	case SUPPAGINGMODE_32_BIT:
3153	case SUPPAGINGMODE_32_BIT_GLOBAL:
3154	enmShadowMode = PGMMODE_AMD64;
3155	enmSwitcher = VMMSWITCHER_32_TO_AMD64;
3156	break;
3157
3158	case SUPPAGINGMODE_PAE:
3159	case SUPPAGINGMODE_PAE_NX:
3160	case SUPPAGINGMODE_PAE_GLOBAL:
3161	case SUPPAGINGMODE_PAE_GLOBAL_NX:
3162	enmShadowMode = PGMMODE_AMD64;
3163	enmSwitcher = VMMSWITCHER_PAE_TO_AMD64;
3164	break;
3165
3166	case SUPPAGINGMODE_AMD64:
3167	case SUPPAGINGMODE_AMD64_GLOBAL:
3168	case SUPPAGINGMODE_AMD64_NX:
3169	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
3170	enmShadowMode = PGMMODE_AMD64;
3171	enmSwitcher = VMMSWITCHER_AMD64_TO_AMD64;
3172	break;
3173
3174	default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
3175	}
3176	break;
3177
3178
3179	default:
3180	AssertReleaseMsgFailed(("enmGuestMode=%d\n", enmGuestMode));
3181	*penmSwitcher = VMMSWITCHER_INVALID;
3182	return PGMMODE_INVALID;
3183	}
3184	/* Override the shadow mode is nested paging is active. */
3185	pVM->pgm.s.fNestedPaging = HWACCMIsNestedPagingActive(pVM);
3186	if (pVM->pgm.s.fNestedPaging)
3187	enmShadowMode = HWACCMGetShwPagingMode(pVM);
3188
3189	*penmSwitcher = enmSwitcher;
3190	return enmShadowMode;
3191	}
3192
3193
3194	/**
3195	* Performs the actual mode change.
3196	* This is called by PGMChangeMode and pgmR3InitPaging().
3197	*
3198	* @returns VBox status code. May suspend or power off the VM on error, but this
3199	* will trigger using FFs and not status codes.
3200	*
3201	* @param pVM VM handle.
3202	* @param pVCpu The VMCPU to operate on.
3203	* @param enmGuestMode The new guest mode. This is assumed to be different from
3204	* the current mode.
3205	*/
3206	VMMR3DECL(int) PGMR3ChangeMode(PVM pVM, PVMCPU pVCpu, PGMMODE enmGuestMode)
3207	{
3208	bool fIsOldGuestPagingMode64Bits = (pVCpu->pgm.s.enmGuestMode >= PGMMODE_AMD64);
3209	bool fIsNewGuestPagingMode64Bits = (enmGuestMode >= PGMMODE_AMD64);
3210
3211	Log(("PGMR3ChangeMode: Guest mode: %s -> %s\n", PGMGetModeName(pVCpu->pgm.s.enmGuestMode), PGMGetModeName(enmGuestMode)));
3212	STAM_REL_COUNTER_INC(&pVCpu->pgm.s.cGuestModeChanges);
3213
3214	/*
3215	* Calc the shadow mode and switcher.
3216	*/
3217	VMMSWITCHER enmSwitcher;
3218	PGMMODE enmShadowMode = pgmR3CalcShadowMode(pVM, enmGuestMode, pVM->pgm.s.enmHostMode, pVCpu->pgm.s.enmShadowMode, &enmSwitcher);
3219
3220	#ifdef VBOX_WITH_RAW_MODE
3221	if (enmSwitcher != VMMSWITCHER_INVALID)
3222	{
3223	/*
3224	* Select new switcher.
3225	*/
3226	int rc = VMMR3SelectSwitcher(pVM, enmSwitcher);
3227	if (RT_FAILURE(rc))
3228	{
3229	AssertReleaseMsgFailed(("VMMR3SelectSwitcher(%d) -> %Rrc\n", enmSwitcher, rc));
3230	return rc;
3231	}
3232	}
3233	#endif
3234
3235	/*
3236	* Exit old mode(s).
3237	*/
3238	#if HC_ARCH_BITS == 32
3239	/* The nested shadow paging mode for AMD-V does change when running 64 bits guests on 32 bits hosts; typically PAE <-> AMD64 */
3240	const bool fForceShwEnterExit = ( fIsOldGuestPagingMode64Bits != fIsNewGuestPagingMode64Bits
3241	&& enmShadowMode == PGMMODE_NESTED);
3242	#else
3243	const bool fForceShwEnterExit = false;
3244	#endif
3245	/* shadow */
3246	if ( enmShadowMode != pVCpu->pgm.s.enmShadowMode
3247	\|\| fForceShwEnterExit)
3248	{
3249	LogFlow(("PGMR3ChangeMode: Shadow mode: %s -> %s\n", PGMGetModeName(pVCpu->pgm.s.enmShadowMode), PGMGetModeName(enmShadowMode)));
3250	if (PGM_SHW_PFN(Exit, pVCpu))
3251	{
3252	int rc = PGM_SHW_PFN(Exit, pVCpu)(pVCpu);
3253	if (RT_FAILURE(rc))
3254	{
3255	AssertMsgFailed(("Exit failed for shadow mode %d: %Rrc\n", pVCpu->pgm.s.enmShadowMode, rc));
3256	return rc;
3257	}
3258	}
3259
3260	}
3261	else
3262	LogFlow(("PGMR3ChangeMode: Shadow mode remains: %s\n", PGMGetModeName(pVCpu->pgm.s.enmShadowMode)));
3263
3264	/* guest */
3265	if (PGM_GST_PFN(Exit, pVCpu))
3266	{
3267	int rc = PGM_GST_PFN(Exit, pVCpu)(pVCpu);
3268	if (RT_FAILURE(rc))
3269	{
3270	AssertMsgFailed(("Exit failed for guest mode %d: %Rrc\n", pVCpu->pgm.s.enmGuestMode, rc));
3271	return rc;
3272	}
3273	}
3274
3275	/*
3276	* Load new paging mode data.
3277	*/
3278	pgmR3ModeDataSwitch(pVM, pVCpu, enmShadowMode, enmGuestMode);
3279
3280	/*
3281	* Enter new shadow mode (if changed).
3282	*/
3283	if ( enmShadowMode != pVCpu->pgm.s.enmShadowMode
3284	\|\| fForceShwEnterExit)
3285	{
3286	int rc;
3287	pVCpu->pgm.s.enmShadowMode = enmShadowMode;
3288	switch (enmShadowMode)
3289	{
3290	case PGMMODE_32_BIT:
3291	rc = PGM_SHW_NAME_32BIT(Enter)(pVCpu, false);
3292	break;
3293	case PGMMODE_PAE:
3294	case PGMMODE_PAE_NX:
3295	rc = PGM_SHW_NAME_PAE(Enter)(pVCpu, false);
3296	break;
3297	case PGMMODE_AMD64:
3298	case PGMMODE_AMD64_NX:
3299	rc = PGM_SHW_NAME_AMD64(Enter)(pVCpu, fIsNewGuestPagingMode64Bits);
3300	break;
3301	case PGMMODE_NESTED:
3302	rc = PGM_SHW_NAME_NESTED(Enter)(pVCpu, fIsNewGuestPagingMode64Bits);
3303	break;
3304	case PGMMODE_EPT:
3305	rc = PGM_SHW_NAME_EPT(Enter)(pVCpu, fIsNewGuestPagingMode64Bits);
3306	break;
3307	case PGMMODE_REAL:
3308	case PGMMODE_PROTECTED:
3309	default:
3310	AssertReleaseMsgFailed(("enmShadowMode=%d\n", enmShadowMode));
3311	return VERR_INTERNAL_ERROR;
3312	}
3313	if (RT_FAILURE(rc))
3314	{
3315	AssertReleaseMsgFailed(("Entering enmShadowMode=%d failed: %Rrc\n", enmShadowMode, rc));
3316	pVCpu->pgm.s.enmShadowMode = PGMMODE_INVALID;
3317	return rc;
3318	}
3319	}
3320
3321	/*
3322	* Always flag the necessary updates
3323	*/
3324	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
3325
3326	/*
3327	* Enter the new guest and shadow+guest modes.
3328	*/
3329	int rc = -1;
3330	int rc2 = -1;
3331	RTGCPHYS GCPhysCR3 = NIL_RTGCPHYS;
3332	pVCpu->pgm.s.enmGuestMode = enmGuestMode;
3333	switch (enmGuestMode)
3334	{
3335	case PGMMODE_REAL:
3336	rc = PGM_GST_NAME_REAL(Enter)(pVCpu, NIL_RTGCPHYS);
3337	switch (pVCpu->pgm.s.enmShadowMode)
3338	{
3339	case PGMMODE_32_BIT:
3340	rc2 = PGM_BTH_NAME_32BIT_REAL(Enter)(pVCpu, NIL_RTGCPHYS);
3341	break;
3342	case PGMMODE_PAE:
3343	case PGMMODE_PAE_NX:
3344	rc2 = PGM_BTH_NAME_PAE_REAL(Enter)(pVCpu, NIL_RTGCPHYS);
3345	break;
3346	case PGMMODE_NESTED:
3347	rc2 = PGM_BTH_NAME_NESTED_REAL(Enter)(pVCpu, NIL_RTGCPHYS);
3348	break;
3349	case PGMMODE_EPT:
3350	rc2 = PGM_BTH_NAME_EPT_REAL(Enter)(pVCpu, NIL_RTGCPHYS);
3351	break;
3352	case PGMMODE_AMD64:
3353	case PGMMODE_AMD64_NX:
3354	AssertMsgFailed(("Should use PAE shadow mode!\n"));
3355	default: AssertFailed(); break;
3356	}
3357	break;
3358
3359	case PGMMODE_PROTECTED:
3360	rc = PGM_GST_NAME_PROT(Enter)(pVCpu, NIL_RTGCPHYS);
3361	switch (pVCpu->pgm.s.enmShadowMode)
3362	{
3363	case PGMMODE_32_BIT:
3364	rc2 = PGM_BTH_NAME_32BIT_PROT(Enter)(pVCpu, NIL_RTGCPHYS);
3365	break;
3366	case PGMMODE_PAE:
3367	case PGMMODE_PAE_NX:
3368	rc2 = PGM_BTH_NAME_PAE_PROT(Enter)(pVCpu, NIL_RTGCPHYS);
3369	break;
3370	case PGMMODE_NESTED:
3371	rc2 = PGM_BTH_NAME_NESTED_PROT(Enter)(pVCpu, NIL_RTGCPHYS);
3372	break;
3373	case PGMMODE_EPT:
3374	rc2 = PGM_BTH_NAME_EPT_PROT(Enter)(pVCpu, NIL_RTGCPHYS);
3375	break;
3376	case PGMMODE_AMD64:
3377	case PGMMODE_AMD64_NX:
3378	AssertMsgFailed(("Should use PAE shadow mode!\n"));
3379	default: AssertFailed(); break;
3380	}
3381	break;
3382
3383	case PGMMODE_32_BIT:
3384	GCPhysCR3 = CPUMGetGuestCR3(pVCpu) & X86_CR3_PAGE_MASK;
3385	rc = PGM_GST_NAME_32BIT(Enter)(pVCpu, GCPhysCR3);
3386	switch (pVCpu->pgm.s.enmShadowMode)
3387	{
3388	case PGMMODE_32_BIT:
3389	rc2 = PGM_BTH_NAME_32BIT_32BIT(Enter)(pVCpu, GCPhysCR3);
3390	break;
3391	case PGMMODE_PAE:
3392	case PGMMODE_PAE_NX:
3393	rc2 = PGM_BTH_NAME_PAE_32BIT(Enter)(pVCpu, GCPhysCR3);
3394	break;
3395	case PGMMODE_NESTED:
3396	rc2 = PGM_BTH_NAME_NESTED_32BIT(Enter)(pVCpu, GCPhysCR3);
3397	break;
3398	case PGMMODE_EPT:
3399	rc2 = PGM_BTH_NAME_EPT_32BIT(Enter)(pVCpu, GCPhysCR3);
3400	break;
3401	case PGMMODE_AMD64:
3402	case PGMMODE_AMD64_NX:
3403	AssertMsgFailed(("Should use PAE shadow mode!\n"));
3404	default: AssertFailed(); break;
3405	}
3406	break;
3407
3408	case PGMMODE_PAE_NX:
3409	case PGMMODE_PAE:
3410	{
3411	uint32_t u32Dummy, u32Features;
3412
3413	CPUMGetGuestCpuId(pVCpu, 1, &u32Dummy, &u32Dummy, &u32Dummy, &u32Features);
3414	if (!(u32Features & X86_CPUID_FEATURE_EDX_PAE))
3415	return VMSetRuntimeError(pVM, VMSETRTERR_FLAGS_FATAL, "PAEmode",
3416	N_("The guest is trying to switch to the PAE mode which is currently disabled by default in VirtualBox. PAE support can be enabled using the VM settings (General/Advanced)"));
3417
3418	GCPhysCR3 = CPUMGetGuestCR3(pVCpu) & X86_CR3_PAE_PAGE_MASK;
3419	rc = PGM_GST_NAME_PAE(Enter)(pVCpu, GCPhysCR3);
3420	switch (pVCpu->pgm.s.enmShadowMode)
3421	{
3422	case PGMMODE_PAE:
3423	case PGMMODE_PAE_NX:
3424	rc2 = PGM_BTH_NAME_PAE_PAE(Enter)(pVCpu, GCPhysCR3);
3425	break;
3426	case PGMMODE_NESTED:
3427	rc2 = PGM_BTH_NAME_NESTED_PAE(Enter)(pVCpu, GCPhysCR3);
3428	break;
3429	case PGMMODE_EPT:
3430	rc2 = PGM_BTH_NAME_EPT_PAE(Enter)(pVCpu, GCPhysCR3);
3431	break;
3432	case PGMMODE_32_BIT:
3433	case PGMMODE_AMD64:
3434	case PGMMODE_AMD64_NX:
3435	AssertMsgFailed(("Should use PAE shadow mode!\n"));
3436	default: AssertFailed(); break;
3437	}
3438	break;
3439	}
3440
3441	#ifdef VBOX_WITH_64_BITS_GUESTS
3442	case PGMMODE_AMD64_NX:
3443	case PGMMODE_AMD64:
3444	GCPhysCR3 = CPUMGetGuestCR3(pVCpu) & UINT64_C(0xfffffffffffff000); /** @todo define this mask! */
3445	rc = PGM_GST_NAME_AMD64(Enter)(pVCpu, GCPhysCR3);
3446	switch (pVCpu->pgm.s.enmShadowMode)
3447	{
3448	case PGMMODE_AMD64:
3449	case PGMMODE_AMD64_NX:
3450	rc2 = PGM_BTH_NAME_AMD64_AMD64(Enter)(pVCpu, GCPhysCR3);
3451	break;
3452	case PGMMODE_NESTED:
3453	rc2 = PGM_BTH_NAME_NESTED_AMD64(Enter)(pVCpu, GCPhysCR3);
3454	break;
3455	case PGMMODE_EPT:
3456	rc2 = PGM_BTH_NAME_EPT_AMD64(Enter)(pVCpu, GCPhysCR3);
3457	break;
3458	case PGMMODE_32_BIT:
3459	case PGMMODE_PAE:
3460	case PGMMODE_PAE_NX:
3461	AssertMsgFailed(("Should use AMD64 shadow mode!\n"));
3462	default: AssertFailed(); break;
3463	}
3464	break;
3465	#endif
3466
3467	default:
3468	AssertReleaseMsgFailed(("enmGuestMode=%d\n", enmGuestMode));
3469	rc = VERR_NOT_IMPLEMENTED;
3470	break;
3471	}
3472
3473	/* status codes. */
3474	AssertRC(rc);
3475	AssertRC(rc2);
3476	if (RT_SUCCESS(rc))
3477	{
3478	rc = rc2;
3479	if (RT_SUCCESS(rc)) /* no informational status codes. */
3480	rc = VINF_SUCCESS;
3481	}
3482
3483	/* Notify HWACCM as well. */
3484	HWACCMR3PagingModeChanged(pVM, pVCpu, pVCpu->pgm.s.enmShadowMode, pVCpu->pgm.s.enmGuestMode);
3485	return rc;
3486	}
3487
3488
3489	/**
3490	* Called by pgmPoolFlushAllInt prior to flushing the pool.
3491	*
3492	* @returns VBox status code, fully asserted.
3493	* @param pVM The VM handle.
3494	* @param pVCpu The VMCPU to operate on.
3495	*/
3496	int pgmR3ExitShadowModeBeforePoolFlush(PVM pVM, PVMCPU pVCpu)
3497	{
3498	/* Unmap the old CR3 value before flushing everything. */
3499	int rc = PGM_BTH_PFN(UnmapCR3, pVCpu)(pVCpu);
3500	AssertRC(rc);
3501
3502	/* Exit the current shadow paging mode as well; nested paging and EPT use a root CR3 which will get flushed here. */
3503	rc = PGM_SHW_PFN(Exit, pVCpu)(pVCpu);
3504	AssertRC(rc);
3505	Assert(pVCpu->pgm.s.pShwPageCR3R3 == NULL);
3506	return rc;
3507	}
3508
3509
3510	/**
3511	* Called by pgmPoolFlushAllInt after flushing the pool.
3512	*
3513	* @returns VBox status code, fully asserted.
3514	* @param pVM The VM handle.
3515	* @param pVCpu The VMCPU to operate on.
3516	*/
3517	int pgmR3ReEnterShadowModeAfterPoolFlush(PVM pVM, PVMCPU pVCpu)
3518	{
3519	pVCpu->pgm.s.enmShadowMode = PGMMODE_INVALID;
3520	int rc = PGMR3ChangeMode(pVM, pVCpu, PGMGetGuestMode(pVCpu));
3521	Assert(VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
3522	AssertRCReturn(rc, rc);
3523	AssertRCSuccessReturn(rc, VERR_IPE_UNEXPECTED_INFO_STATUS);
3524
3525	Assert(pVCpu->pgm.s.pShwPageCR3R3 != NULL);
3526	AssertMsg( pVCpu->pgm.s.enmShadowMode >= PGMMODE_NESTED
3527	\|\| CPUMGetHyperCR3(pVCpu) == PGMGetHyperCR3(pVCpu),
3528	("%RHp != %RHp %s\n", (RTHCPHYS)CPUMGetHyperCR3(pVCpu), PGMGetHyperCR3(pVCpu), PGMGetModeName(pVCpu->pgm.s.enmShadowMode)));
3529	return rc;
3530	}
3531
3532
3533	/**
3534	* Dumps a PAE shadow page table.
3535	*
3536	* @returns VBox status code (VINF_SUCCESS).
3537	* @param pVM The VM handle.
3538	* @param pPT Pointer to the page table.
3539	* @param u64Address The virtual address of the page table starts.
3540	* @param fLongMode Set if this a long mode table; clear if it's a legacy mode table.
3541	* @param cMaxDepth The maxium depth.
3542	* @param pHlp Pointer to the output functions.
3543	*/
3544	static int pgmR3DumpHierarchyHCPaePT(PVM pVM, PCPGMSHWPTPAE pPT, uint64_t u64Address, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
3545	{
3546	for (unsigned i = 0; i < RT_ELEMENTS(pPT->a); i++)
3547	if (PGMSHWPTEPAE_IS_P(pPT->a[i]))
3548	{
3549	X86PTEPAE Pte;
3550	Pte.u = PGMSHWPTEPAE_GET_U(pPT->a[i]);
3551	pHlp->pfnPrintf(pHlp,
3552	fLongMode /P R S A D G WT CD AT NX 4M a p ? /
3553	? "%016llx 3 \| P %c %c %c %c %c %s %s %s %s 4K %c%c%c %016llx\n"
3554	: "%08llx 2 \| P %c %c %c %c %c %s %s %s %s 4K %c%c%c %016llx\n",
3555	u64Address + ((uint64_t)i << X86_PT_PAE_SHIFT),
3556	Pte.n.u1Write ? 'W' : 'R',
3557	Pte.n.u1User ? 'U' : 'S',
3558	Pte.n.u1Accessed ? 'A' : '-',
3559	Pte.n.u1Dirty ? 'D' : '-',
3560	Pte.n.u1Global ? 'G' : '-',
3561	Pte.n.u1WriteThru ? "WT" : "--",
3562	Pte.n.u1CacheDisable? "CD" : "--",
3563	Pte.n.u1PAT ? "AT" : "--",
3564	Pte.n.u1NoExecute ? "NX" : "--",
3565	Pte.u & PGM_PTFLAGS_TRACK_DIRTY ? 'd' : '-',
3566	Pte.u & RT_BIT(10) ? '1' : '0',
3567	Pte.u & PGM_PTFLAGS_CSAM_VALIDATED? 'v' : '-',
3568	Pte.u & X86_PTE_PAE_PG_MASK);
3569	}
3570	return VINF_SUCCESS;
3571	}
3572
3573
3574	/**
3575	* Dumps a PAE shadow page directory table.
3576	*
3577	* @returns VBox status code (VINF_SUCCESS).
3578	* @param pVM The VM handle.
3579	* @param HCPhys The physical address of the page directory table.
3580	* @param u64Address The virtual address of the page table starts.
3581	* @param cr4 The CR4, PSE is currently used.
3582	* @param fLongMode Set if this a long mode table; clear if it's a legacy mode table.
3583	* @param cMaxDepth The maxium depth.
3584	* @param pHlp Pointer to the output functions.
3585	*/
3586	static int pgmR3DumpHierarchyHCPaePD(PVM pVM, RTHCPHYS HCPhys, uint64_t u64Address, uint32_t cr4, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
3587	{
3588	PX86PDPAE pPD = (PX86PDPAE)MMPagePhys2Page(pVM, HCPhys);
3589	if (!pPD)
3590	{
3591	pHlp->pfnPrintf(pHlp, "%0*llx error! Page directory at HCPhys=%RHp was not found in the page pool!\n",
3592	fLongMode ? 16 : 8, u64Address, HCPhys);
3593	return VERR_INVALID_PARAMETER;
3594	}
3595	const bool fBigPagesSupported = fLongMode \|\| !!(cr4 & X86_CR4_PSE);
3596
3597	int rc = VINF_SUCCESS;
3598	for (unsigned i = 0; i < RT_ELEMENTS(pPD->a); i++)
3599	{
3600	X86PDEPAE Pde = pPD->a[i];
3601	if (Pde.n.u1Present)
3602	{
3603	if (fBigPagesSupported && Pde.b.u1Size)
3604	pHlp->pfnPrintf(pHlp,
3605	fLongMode /P R S A D G WT CD AT NX 4M a p ? /
3606	? "%016llx 2 \| P %c %c %c %c %c %s %s %s %s 4M %c%c%c %016llx\n"
3607	: "%08llx 1 \| P %c %c %c %c %c %s %s %s %s 4M %c%c%c %016llx\n",
3608	u64Address + ((uint64_t)i << X86_PD_PAE_SHIFT),
3609	Pde.b.u1Write ? 'W' : 'R',
3610	Pde.b.u1User ? 'U' : 'S',
3611	Pde.b.u1Accessed ? 'A' : '-',
3612	Pde.b.u1Dirty ? 'D' : '-',
3613	Pde.b.u1Global ? 'G' : '-',
3614	Pde.b.u1WriteThru ? "WT" : "--",
3615	Pde.b.u1CacheDisable? "CD" : "--",
3616	Pde.b.u1PAT ? "AT" : "--",
3617	Pde.b.u1NoExecute ? "NX" : "--",
3618	Pde.u & RT_BIT_64(9) ? '1' : '0',
3619	Pde.u & PGM_PDFLAGS_MAPPING ? 'm' : '-',
3620	Pde.u & PGM_PDFLAGS_TRACK_DIRTY ? 'd' : '-',
3621	Pde.u & X86_PDE_PAE_PG_MASK);
3622	else
3623	{
3624	pHlp->pfnPrintf(pHlp,
3625	fLongMode /P R S A D G WT CD AT NX 4M a p ? /
3626	? "%016llx 2 \| P %c %c %c %c %c %s %s .. %s 4K %c%c%c %016llx\n"
3627	: "%08llx 1 \| P %c %c %c %c %c %s %s .. %s 4K %c%c%c %016llx\n",
3628	u64Address + ((uint64_t)i << X86_PD_PAE_SHIFT),
3629	Pde.n.u1Write ? 'W' : 'R',
3630	Pde.n.u1User ? 'U' : 'S',
3631	Pde.n.u1Accessed ? 'A' : '-',
3632	Pde.n.u1Reserved0 ? '?' : '.', /* ignored */
3633	Pde.n.u1Reserved1 ? '?' : '.', /* ignored */
3634	Pde.n.u1WriteThru ? "WT" : "--",
3635	Pde.n.u1CacheDisable? "CD" : "--",
3636	Pde.n.u1NoExecute ? "NX" : "--",
3637	Pde.u & RT_BIT_64(9) ? '1' : '0',
3638	Pde.u & PGM_PDFLAGS_MAPPING ? 'm' : '-',
3639	Pde.u & PGM_PDFLAGS_TRACK_DIRTY ? 'd' : '-',
3640	Pde.u & X86_PDE_PAE_PG_MASK);
3641	if (cMaxDepth >= 1)
3642	{
3643	/** @todo what about using the page pool for mapping PTs? */
3644	uint64_t u64AddressPT = u64Address + ((uint64_t)i << X86_PD_PAE_SHIFT);
3645	RTHCPHYS HCPhysPT = Pde.u & X86_PDE_PAE_PG_MASK;
3646	PPGMSHWPTPAE pPT = NULL;
3647	if (!(Pde.u & PGM_PDFLAGS_MAPPING))
3648	pPT = (PPGMSHWPTPAE)MMPagePhys2Page(pVM, HCPhysPT);
3649	else
3650	{
3651	for (PPGMMAPPING pMap = pVM->pgm.s.pMappingsR3; pMap; pMap = pMap->pNextR3)
3652	{
3653	uint64_t off = u64AddressPT - pMap->GCPtr;
3654	if (off < pMap->cb)
3655	{
3656	const int iPDE = (uint32_t)(off >> X86_PD_SHIFT);
3657	const int iSub = (int)((off >> X86_PD_PAE_SHIFT) & 1); /* MSC is a pain sometimes */
3658	if ((iSub ? pMap->aPTs[iPDE].HCPhysPaePT1 : pMap->aPTs[iPDE].HCPhysPaePT0) != HCPhysPT)
3659	pHlp->pfnPrintf(pHlp, "%0*llx error! Mapping error! PT %d has HCPhysPT=%RHp not %RHp is in the PD.\n",
3660	fLongMode ? 16 : 8, u64AddressPT, iPDE,
3661	iSub ? pMap->aPTs[iPDE].HCPhysPaePT1 : pMap->aPTs[iPDE].HCPhysPaePT0, HCPhysPT);
3662	pPT = &pMap->aPTs[iPDE].paPaePTsR3[iSub];
3663	}
3664	}
3665	}
3666	int rc2 = VERR_INVALID_PARAMETER;
3667	if (pPT)
3668	rc2 = pgmR3DumpHierarchyHCPaePT(pVM, pPT, u64AddressPT, fLongMode, cMaxDepth - 1, pHlp);
3669	else
3670	pHlp->pfnPrintf(pHlp, "%0*llx error! Page table at HCPhys=%RHp was not found in the page pool!\n",
3671	fLongMode ? 16 : 8, u64AddressPT, HCPhysPT);
3672	if (rc2 < rc && RT_SUCCESS(rc))
3673	rc = rc2;
3674	}
3675	}
3676	}
3677	}
3678	return rc;
3679	}
3680
3681
3682	/**
3683	* Dumps a PAE shadow page directory pointer table.
3684	*
3685	* @returns VBox status code (VINF_SUCCESS).
3686	* @param pVM The VM handle.
3687	* @param HCPhys The physical address of the page directory pointer table.
3688	* @param u64Address The virtual address of the page table starts.
3689	* @param cr4 The CR4, PSE is currently used.
3690	* @param fLongMode Set if this a long mode table; clear if it's a legacy mode table.
3691	* @param cMaxDepth The maxium depth.
3692	* @param pHlp Pointer to the output functions.
3693	*/
3694	static int pgmR3DumpHierarchyHCPaePDPT(PVM pVM, RTHCPHYS HCPhys, uint64_t u64Address, uint32_t cr4, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
3695	{
3696	PX86PDPT pPDPT = (PX86PDPT)MMPagePhys2Page(pVM, HCPhys);
3697	if (!pPDPT)
3698	{
3699	pHlp->pfnPrintf(pHlp, "%0*llx error! Page directory pointer table at HCPhys=%RHp was not found in the page pool!\n",
3700	fLongMode ? 16 : 8, u64Address, HCPhys);
3701	return VERR_INVALID_PARAMETER;
3702	}
3703
3704	int rc = VINF_SUCCESS;
3705	const unsigned c = fLongMode ? RT_ELEMENTS(pPDPT->a) : X86_PG_PAE_PDPE_ENTRIES;
3706	for (unsigned i = 0; i < c; i++)
3707	{
3708	X86PDPE Pdpe = pPDPT->a[i];
3709	if (Pdpe.n.u1Present)
3710	{
3711	if (fLongMode)
3712	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a p ? /
3713	"%016llx 1 \| P %c %c %c %c %c %s %s %s %s .. %c%c%c %016llx\n",
3714	u64Address + ((uint64_t)i << X86_PDPT_SHIFT),
3715	Pdpe.lm.u1Write ? 'W' : 'R',
3716	Pdpe.lm.u1User ? 'U' : 'S',
3717	Pdpe.lm.u1Accessed ? 'A' : '-',
3718	Pdpe.lm.u3Reserved & 1? '?' : '.', /* ignored */
3719	Pdpe.lm.u3Reserved & 4? '!' : '.', /* mbz */
3720	Pdpe.lm.u1WriteThru ? "WT" : "--",
3721	Pdpe.lm.u1CacheDisable? "CD" : "--",
3722	Pdpe.lm.u3Reserved & 2? "!" : "..",/* mbz */
3723	Pdpe.lm.u1NoExecute ? "NX" : "--",
3724	Pdpe.u & RT_BIT(9) ? '1' : '0',
3725	Pdpe.u & PGM_PLXFLAGS_PERMANENT ? 'p' : '-',
3726	Pdpe.u & RT_BIT(11) ? '1' : '0',
3727	Pdpe.u & X86_PDPE_PG_MASK);
3728	else
3729	pHlp->pfnPrintf(pHlp, /P G WT CD AT NX 4M a p ? /
3730	"%08x 0 \| P %c %s %s %s %s .. %c%c%c %016llx\n",
3731	i << X86_PDPT_SHIFT,
3732	Pdpe.n.u4Reserved & 1? '!' : '.', /* mbz */
3733	Pdpe.n.u4Reserved & 4? '!' : '.', /* mbz */
3734	Pdpe.n.u1WriteThru ? "WT" : "--",
3735	Pdpe.n.u1CacheDisable? "CD" : "--",
3736	Pdpe.n.u4Reserved & 2? "!" : "..",/* mbz */
3737	Pdpe.u & RT_BIT(9) ? '1' : '0',
3738	Pdpe.u & PGM_PLXFLAGS_PERMANENT ? 'p' : '-',
3739	Pdpe.u & RT_BIT(11) ? '1' : '0',
3740	Pdpe.u & X86_PDPE_PG_MASK);
3741	if (cMaxDepth >= 1)
3742	{
3743	int rc2 = pgmR3DumpHierarchyHCPaePD(pVM, Pdpe.u & X86_PDPE_PG_MASK, u64Address + ((uint64_t)i << X86_PDPT_SHIFT),
3744	cr4, fLongMode, cMaxDepth - 1, pHlp);
3745	if (rc2 < rc && RT_SUCCESS(rc))
3746	rc = rc2;
3747	}
3748	}
3749	}
3750	return rc;
3751	}
3752
3753
3754	/**
3755	* Dumps a 32-bit shadow page table.
3756	*
3757	* @returns VBox status code (VINF_SUCCESS).
3758	* @param pVM The VM handle.
3759	* @param HCPhys The physical address of the table.
3760	* @param cr4 The CR4, PSE is currently used.
3761	* @param cMaxDepth The maxium depth.
3762	* @param pHlp Pointer to the output functions.
3763	*/
3764	static int pgmR3DumpHierarchyHcPaePML4(PVM pVM, RTHCPHYS HCPhys, uint32_t cr4, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
3765	{
3766	PX86PML4 pPML4 = (PX86PML4)MMPagePhys2Page(pVM, HCPhys);
3767	if (!pPML4)
3768	{
3769	pHlp->pfnPrintf(pHlp, "Page map level 4 at HCPhys=%RHp was not found in the page pool!\n", HCPhys);
3770	return VERR_INVALID_PARAMETER;
3771	}
3772
3773	int rc = VINF_SUCCESS;
3774	for (unsigned i = 0; i < RT_ELEMENTS(pPML4->a); i++)
3775	{
3776	X86PML4E Pml4e = pPML4->a[i];
3777	if (Pml4e.n.u1Present)
3778	{
3779	uint64_t u64Address = ((uint64_t)i << X86_PML4_SHIFT) \| (((uint64_t)i >> (X86_PML4_SHIFT - X86_PDPT_SHIFT - 1)) * 0xffff000000000000ULL);
3780	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a p ? /
3781	"%016llx 0 \| P %c %c %c %c %c %s %s %s %s .. %c%c%c %016llx\n",
3782	u64Address,
3783	Pml4e.n.u1Write ? 'W' : 'R',
3784	Pml4e.n.u1User ? 'U' : 'S',
3785	Pml4e.n.u1Accessed ? 'A' : '-',
3786	Pml4e.n.u3Reserved & 1? '?' : '.', /* ignored */
3787	Pml4e.n.u3Reserved & 4? '!' : '.', /* mbz */
3788	Pml4e.n.u1WriteThru ? "WT" : "--",
3789	Pml4e.n.u1CacheDisable? "CD" : "--",
3790	Pml4e.n.u3Reserved & 2? "!" : "..",/* mbz */
3791	Pml4e.n.u1NoExecute ? "NX" : "--",
3792	Pml4e.u & RT_BIT(9) ? '1' : '0',
3793	Pml4e.u & PGM_PLXFLAGS_PERMANENT ? 'p' : '-',
3794	Pml4e.u & RT_BIT(11) ? '1' : '0',
3795	Pml4e.u & X86_PML4E_PG_MASK);
3796
3797	if (cMaxDepth >= 1)
3798	{
3799	int rc2 = pgmR3DumpHierarchyHCPaePDPT(pVM, Pml4e.u & X86_PML4E_PG_MASK, u64Address, cr4, true, cMaxDepth - 1, pHlp);
3800	if (rc2 < rc && RT_SUCCESS(rc))
3801	rc = rc2;
3802	}
3803	}
3804	}
3805	return rc;
3806	}
3807
3808
3809	/**
3810	* Dumps a 32-bit shadow page table.
3811	*
3812	* @returns VBox status code (VINF_SUCCESS).
3813	* @param pVM The VM handle.
3814	* @param pPT Pointer to the page table.
3815	* @param u32Address The virtual address this table starts at.
3816	* @param pHlp Pointer to the output functions.
3817	*/
3818	int pgmR3DumpHierarchyHC32BitPT(PVM pVM, PX86PT pPT, uint32_t u32Address, PCDBGFINFOHLP pHlp)
3819	{
3820	for (unsigned i = 0; i < RT_ELEMENTS(pPT->a); i++)
3821	{
3822	X86PTE Pte = pPT->a[i];
3823	if (Pte.n.u1Present)
3824	{
3825	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a m d /
3826	"%08x 1 \| P %c %c %c %c %c %s %s %s .. 4K %c%c%c %08x\n",
3827	u32Address + (i << X86_PT_SHIFT),
3828	Pte.n.u1Write ? 'W' : 'R',
3829	Pte.n.u1User ? 'U' : 'S',
3830	Pte.n.u1Accessed ? 'A' : '-',
3831	Pte.n.u1Dirty ? 'D' : '-',
3832	Pte.n.u1Global ? 'G' : '-',
3833	Pte.n.u1WriteThru ? "WT" : "--",
3834	Pte.n.u1CacheDisable? "CD" : "--",
3835	Pte.n.u1PAT ? "AT" : "--",
3836	Pte.u & PGM_PTFLAGS_TRACK_DIRTY ? 'd' : '-',
3837	Pte.u & RT_BIT(10) ? '1' : '0',
3838	Pte.u & PGM_PTFLAGS_CSAM_VALIDATED ? 'v' : '-',
3839	Pte.u & X86_PDE_PG_MASK);
3840	}
3841	}
3842	return VINF_SUCCESS;
3843	}
3844
3845
3846	/**
3847	* Dumps a 32-bit shadow page directory and page tables.
3848	*
3849	* @returns VBox status code (VINF_SUCCESS).
3850	* @param pVM The VM handle.
3851	* @param cr3 The root of the hierarchy.
3852	* @param cr4 The CR4, PSE is currently used.
3853	* @param cMaxDepth How deep into the hierarchy the dumper should go.
3854	* @param pHlp Pointer to the output functions.
3855	*/
3856	int pgmR3DumpHierarchyHC32BitPD(PVM pVM, uint32_t cr3, uint32_t cr4, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
3857	{
3858	PX86PD pPD = (PX86PD)MMPagePhys2Page(pVM, cr3 & X86_CR3_PAGE_MASK);
3859	if (!pPD)
3860	{
3861	pHlp->pfnPrintf(pHlp, "Page directory at %#x was not found in the page pool!\n", cr3 & X86_CR3_PAGE_MASK);
3862	return VERR_INVALID_PARAMETER;
3863	}
3864
3865	int rc = VINF_SUCCESS;
3866	for (unsigned i = 0; i < RT_ELEMENTS(pPD->a); i++)
3867	{
3868	X86PDE Pde = pPD->a[i];
3869	if (Pde.n.u1Present)
3870	{
3871	const uint32_t u32Address = i << X86_PD_SHIFT;
3872	if ((cr4 & X86_CR4_PSE) && Pde.b.u1Size)
3873	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a m d /
3874	"%08x 0 \| P %c %c %c %c %c %s %s %s .. 4M %c%c%c %08x\n",
3875	u32Address,
3876	Pde.b.u1Write ? 'W' : 'R',
3877	Pde.b.u1User ? 'U' : 'S',
3878	Pde.b.u1Accessed ? 'A' : '-',
3879	Pde.b.u1Dirty ? 'D' : '-',
3880	Pde.b.u1Global ? 'G' : '-',
3881	Pde.b.u1WriteThru ? "WT" : "--",
3882	Pde.b.u1CacheDisable? "CD" : "--",
3883	Pde.b.u1PAT ? "AT" : "--",
3884	Pde.u & RT_BIT_64(9) ? '1' : '0',
3885	Pde.u & PGM_PDFLAGS_MAPPING ? 'm' : '-',
3886	Pde.u & PGM_PDFLAGS_TRACK_DIRTY ? 'd' : '-',
3887	Pde.u & X86_PDE4M_PG_MASK);
3888	else
3889	{
3890	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a m d /
3891	"%08x 0 \| P %c %c %c %c %c %s %s .. .. 4K %c%c%c %08x\n",
3892	u32Address,
3893	Pde.n.u1Write ? 'W' : 'R',
3894	Pde.n.u1User ? 'U' : 'S',
3895	Pde.n.u1Accessed ? 'A' : '-',
3896	Pde.n.u1Reserved0 ? '?' : '.', /* ignored */
3897	Pde.n.u1Reserved1 ? '?' : '.', /* ignored */
3898	Pde.n.u1WriteThru ? "WT" : "--",
3899	Pde.n.u1CacheDisable? "CD" : "--",
3900	Pde.u & RT_BIT_64(9) ? '1' : '0',
3901	Pde.u & PGM_PDFLAGS_MAPPING ? 'm' : '-',
3902	Pde.u & PGM_PDFLAGS_TRACK_DIRTY ? 'd' : '-',
3903	Pde.u & X86_PDE_PG_MASK);
3904	if (cMaxDepth >= 1)
3905	{
3906	/** @todo what about using the page pool for mapping PTs? */
3907	RTHCPHYS HCPhys = Pde.u & X86_PDE_PG_MASK;
3908	PX86PT pPT = NULL;
3909	if (!(Pde.u & PGM_PDFLAGS_MAPPING))
3910	pPT = (PX86PT)MMPagePhys2Page(pVM, HCPhys);
3911	else
3912	{
3913	for (PPGMMAPPING pMap = pVM->pgm.s.pMappingsR3; pMap; pMap = pMap->pNextR3)
3914	if (u32Address - pMap->GCPtr < pMap->cb)
3915	{
3916	int iPDE = (u32Address - pMap->GCPtr) >> X86_PD_SHIFT;
3917	if (pMap->aPTs[iPDE].HCPhysPT != HCPhys)
3918	pHlp->pfnPrintf(pHlp, "%08x error! Mapping error! PT %d has HCPhysPT=%RHp not %RHp is in the PD.\n",
3919	u32Address, iPDE, pMap->aPTs[iPDE].HCPhysPT, HCPhys);
3920	pPT = pMap->aPTs[iPDE].pPTR3;
3921	}
3922	}
3923	int rc2 = VERR_INVALID_PARAMETER;
3924	if (pPT)
3925	rc2 = pgmR3DumpHierarchyHC32BitPT(pVM, pPT, u32Address, pHlp);
3926	else
3927	pHlp->pfnPrintf(pHlp, "%08x error! Page table at %#x was not found in the page pool!\n", u32Address, HCPhys);
3928	if (rc2 < rc && RT_SUCCESS(rc))
3929	rc = rc2;
3930	}
3931	}
3932	}
3933	}
3934
3935	return rc;
3936	}
3937
3938
3939	/**
3940	* Dumps a 32-bit shadow page table.
3941	*
3942	* @returns VBox status code (VINF_SUCCESS).
3943	* @param pVM The VM handle.
3944	* @param pPT Pointer to the page table.
3945	* @param u32Address The virtual address this table starts at.
3946	* @param PhysSearch Address to search for.
3947	*/
3948	int pgmR3DumpHierarchyGC32BitPT(PVM pVM, PX86PT pPT, uint32_t u32Address, RTGCPHYS PhysSearch)
3949	{
3950	for (unsigned i = 0; i < RT_ELEMENTS(pPT->a); i++)
3951	{
3952	X86PTE Pte = pPT->a[i];
3953	if (Pte.n.u1Present)
3954	{
3955	Log(( /P R S A D G WT CD AT NX 4M a m d /
3956	"%08x 1 \| P %c %c %c %c %c %s %s %s .. 4K %c%c%c %08x\n",
3957	u32Address + (i << X86_PT_SHIFT),
3958	Pte.n.u1Write ? 'W' : 'R',
3959	Pte.n.u1User ? 'U' : 'S',
3960	Pte.n.u1Accessed ? 'A' : '-',
3961	Pte.n.u1Dirty ? 'D' : '-',
3962	Pte.n.u1Global ? 'G' : '-',
3963	Pte.n.u1WriteThru ? "WT" : "--",
3964	Pte.n.u1CacheDisable? "CD" : "--",
3965	Pte.n.u1PAT ? "AT" : "--",
3966	Pte.u & PGM_PTFLAGS_TRACK_DIRTY ? 'd' : '-',
3967	Pte.u & RT_BIT(10) ? '1' : '0',
3968	Pte.u & PGM_PTFLAGS_CSAM_VALIDATED ? 'v' : '-',
3969	Pte.u & X86_PDE_PG_MASK));
3970
3971	if ((Pte.u & X86_PDE_PG_MASK) == PhysSearch)
3972	{
3973	uint64_t fPageShw = 0;
3974	RTHCPHYS pPhysHC = 0;
3975
3976	/** @todo SMP support!! */
3977	PGMShwGetPage(&pVM->aCpus[0], (RTGCPTR)(u32Address + (i << X86_PT_SHIFT)), &fPageShw, &pPhysHC);
3978	Log(("Found %RGp at %RGv -> flags=%llx\n", PhysSearch, (RTGCPTR)(u32Address + (i << X86_PT_SHIFT)), fPageShw));
3979	}
3980	}
3981	}
3982	return VINF_SUCCESS;
3983	}
3984
3985
3986	/**
3987	* Dumps a 32-bit guest page directory and page tables.
3988	*
3989	* @returns VBox status code (VINF_SUCCESS).
3990	* @param pVM The VM handle.
3991	* @param cr3 The root of the hierarchy.
3992	* @param cr4 The CR4, PSE is currently used.
3993	* @param PhysSearch Address to search for.
3994	*/
3995	VMMR3DECL(int) PGMR3DumpHierarchyGC(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCPHYS PhysSearch)
3996	{
3997	bool fLongMode = false;
3998	const unsigned cch = fLongMode ? 16 : 8; NOREF(cch);
3999	PX86PD pPD = 0;
4000	PGMPAGEMAPLOCK LockCr3;
4001
4002	int rc = PGMPhysGCPhys2CCPtrReadOnly(pVM, cr3 & X86_CR3_PAGE_MASK, (const void **)&pPD, &LockCr3);
4003	if ( RT_FAILURE(rc)
4004	\|\| !pPD)
4005	{
4006	Log(("Page directory at %#x was not found in the page pool!\n", cr3 & X86_CR3_PAGE_MASK));
4007	return VERR_INVALID_PARAMETER;
4008	}
4009
4010	Log(("cr3=%08x cr4=%08x%s\n"
4011	"%-*s P - Present\n"
4012	"%-*s \| R/W - Read (0) / Write (1)\n"
4013	"%-*s \| \| U/S - User (1) / Supervisor (0)\n"
4014	"%-*s \| \| \| A - Accessed\n"
4015	"%-*s \| \| \| \| D - Dirty\n"
4016	"%-*s \| \| \| \| \| G - Global\n"
4017	"%-*s \| \| \| \| \| \| WT - Write thru\n"
4018	"%-*s \| \| \| \| \| \| \| CD - Cache disable\n"
4019	"%-*s \| \| \| \| \| \| \| \| AT - Attribute table (PAT)\n"
4020	"%-*s \| \| \| \| \| \| \| \| \| NX - No execute (K8)\n"
4021	"%-*s \| \| \| \| \| \| \| \| \| \| 4K/4M/2M - Page size.\n"
4022	"%-*s \| \| \| \| \| \| \| \| \| \| \| AVL - a=allocated; m=mapping; d=track dirty;\n"
4023	"%-*s \| \| \| \| \| \| \| \| \| \| \| \| p=permanent; v=validated;\n"
4024	"%-*s Level \| \| \| \| \| \| \| \| \| \| \| \| Page\n"
4025	/* xxxx n **** P R S A D G WT CD AT NX 4M AVL xxxxxxxxxxxxx
4026	- W U - - - -- -- -- -- -- 010 */
4027	, cr3, cr4, fLongMode ? " Long Mode" : "",
4028	cch, "", cch, "", cch, "", cch, "", cch, "", cch, "", cch, "",
4029	cch, "", cch, "", cch, "", cch, "", cch, "", cch, "", cch, "Address"));
4030
4031	for (unsigned i = 0; i < RT_ELEMENTS(pPD->a); i++)
4032	{
4033	X86PDE Pde = pPD->a[i];
4034	if (Pde.n.u1Present)
4035	{
4036	const uint32_t u32Address = i << X86_PD_SHIFT;
4037
4038	if ((cr4 & X86_CR4_PSE) && Pde.b.u1Size)
4039	Log(( /P R S A D G WT CD AT NX 4M a m d /
4040	"%08x 0 \| P %c %c %c %c %c %s %s %s .. 4M %c%c%c %08x\n",
4041	u32Address,
4042	Pde.b.u1Write ? 'W' : 'R',
4043	Pde.b.u1User ? 'U' : 'S',
4044	Pde.b.u1Accessed ? 'A' : '-',
4045	Pde.b.u1Dirty ? 'D' : '-',
4046	Pde.b.u1Global ? 'G' : '-',
4047	Pde.b.u1WriteThru ? "WT" : "--",
4048	Pde.b.u1CacheDisable? "CD" : "--",
4049	Pde.b.u1PAT ? "AT" : "--",
4050	Pde.u & RT_BIT(9) ? '1' : '0',
4051	Pde.u & RT_BIT(10) ? '1' : '0',
4052	Pde.u & RT_BIT(11) ? '1' : '0',
4053	pgmGstGet4MBPhysPage(&pVM->pgm.s, Pde)));
4054	/** @todo PhysSearch */
4055	else
4056	{
4057	Log(( /P R S A D G WT CD AT NX 4M a m d /
4058	"%08x 0 \| P %c %c %c %c %c %s %s .. .. 4K %c%c%c %08x\n",
4059	u32Address,
4060	Pde.n.u1Write ? 'W' : 'R',
4061	Pde.n.u1User ? 'U' : 'S',
4062	Pde.n.u1Accessed ? 'A' : '-',
4063	Pde.n.u1Reserved0 ? '?' : '.', /* ignored */
4064	Pde.n.u1Reserved1 ? '?' : '.', /* ignored */
4065	Pde.n.u1WriteThru ? "WT" : "--",
4066	Pde.n.u1CacheDisable? "CD" : "--",
4067	Pde.u & RT_BIT(9) ? '1' : '0',
4068	Pde.u & RT_BIT(10) ? '1' : '0',
4069	Pde.u & RT_BIT(11) ? '1' : '0',
4070	Pde.u & X86_PDE_PG_MASK));
4071	////if (cMaxDepth >= 1)
4072	{
4073	/** @todo what about using the page pool for mapping PTs? */
4074	RTGCPHYS GCPhys = Pde.u & X86_PDE_PG_MASK;
4075	PX86PT pPT = NULL;
4076	PGMPAGEMAPLOCK LockPT;
4077
4078	rc = PGMPhysGCPhys2CCPtrReadOnly(pVM, GCPhys, (const void **)&pPT, &LockPT);
4079
4080	int rc2 = VERR_INVALID_PARAMETER;
4081	if (pPT)
4082	rc2 = pgmR3DumpHierarchyGC32BitPT(pVM, pPT, u32Address, PhysSearch);
4083	else
4084	Log(("%08x error! Page table at %#x was not found in the page pool!\n", u32Address, GCPhys));
4085
4086	if (rc == VINF_SUCCESS)
4087	PGMPhysReleasePageMappingLock(pVM, &LockPT);
4088
4089	if (rc2 < rc && RT_SUCCESS(rc))
4090	rc = rc2;
4091	}
4092	}
4093	}
4094	}
4095	PGMPhysReleasePageMappingLock(pVM, &LockCr3);
4096	return rc;
4097	}
4098
4099
4100	/**
4101	* Dumps a page table hierarchy use only physical addresses and cr4/lm flags.
4102	*
4103	* @returns VBox status code (VINF_SUCCESS).
4104	* @param pVM The VM handle.
4105	* @param cr3 The root of the hierarchy.
4106	* @param cr4 The cr4, only PAE and PSE is currently used.
4107	* @param fLongMode Set if long mode, false if not long mode.
4108	* @param cMaxDepth Number of levels to dump.
4109	* @param pHlp Pointer to the output functions.
4110	*/
4111	VMMR3DECL(int) PGMR3DumpHierarchyHC(PVM pVM, uint64_t cr3, uint64_t cr4, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
4112	{
4113	if (!pHlp)
4114	pHlp = DBGFR3InfoLogHlp();
4115	if (!cMaxDepth)
4116	return VINF_SUCCESS;
4117	const unsigned cch = fLongMode ? 16 : 8;
4118	pHlp->pfnPrintf(pHlp,
4119	"cr3=%08x cr4=%08x%s\n"
4120	"%-*s P - Present\n"
4121	"%-*s \| R/W - Read (0) / Write (1)\n"
4122	"%-*s \| \| U/S - User (1) / Supervisor (0)\n"
4123	"%-*s \| \| \| A - Accessed\n"
4124	"%-*s \| \| \| \| D - Dirty\n"
4125	"%-*s \| \| \| \| \| G - Global\n"
4126	"%-*s \| \| \| \| \| \| WT - Write thru\n"
4127	"%-*s \| \| \| \| \| \| \| CD - Cache disable\n"
4128	"%-*s \| \| \| \| \| \| \| \| AT - Attribute table (PAT)\n"
4129	"%-*s \| \| \| \| \| \| \| \| \| NX - No execute (K8)\n"
4130	"%-*s \| \| \| \| \| \| \| \| \| \| 4K/4M/2M - Page size.\n"
4131	"%-*s \| \| \| \| \| \| \| \| \| \| \| AVL - a=allocated; m=mapping; d=track dirty;\n"
4132	"%-*s \| \| \| \| \| \| \| \| \| \| \| \| p=permanent; v=validated;\n"
4133	"%-*s Level \| \| \| \| \| \| \| \| \| \| \| \| Page\n"
4134	/* xxxx n **** P R S A D G WT CD AT NX 4M AVL xxxxxxxxxxxxx
4135	- W U - - - -- -- -- -- -- 010 */
4136	, cr3, cr4, fLongMode ? " Long Mode" : "",
4137	cch, "", cch, "", cch, "", cch, "", cch, "", cch, "", cch, "",
4138	cch, "", cch, "", cch, "", cch, "", cch, "", cch, "", cch, "Address");
4139	if (cr4 & X86_CR4_PAE)
4140	{
4141	if (fLongMode)
4142	return pgmR3DumpHierarchyHcPaePML4(pVM, cr3 & X86_CR3_PAGE_MASK, cr4, cMaxDepth, pHlp);
4143	return pgmR3DumpHierarchyHCPaePDPT(pVM, cr3 & X86_CR3_PAE_PAGE_MASK, 0, cr4, false, cMaxDepth, pHlp);
4144	}
4145	return pgmR3DumpHierarchyHC32BitPD(pVM, cr3 & X86_CR3_PAGE_MASK, cr4, cMaxDepth, pHlp);
4146	}
4147
4148	#ifdef VBOX_WITH_DEBUGGER
4149
4150	/**
4151	* The '.pgmram' command.
4152	*
4153	* @returns VBox status.
4154	* @param pCmd Pointer to the command descriptor (as registered).
4155	* @param pCmdHlp Pointer to command helper functions.
4156	* @param pVM Pointer to the current VM (if any).
4157	* @param paArgs Pointer to (readonly) array of arguments.
4158	* @param cArgs Number of arguments in the array.
4159	*/
4160	static DECLCALLBACK(int) pgmR3CmdRam(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4161	{
4162	/*
4163	* Validate input.
4164	*/
4165	if (!pVM)
4166	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4167	if (!pVM->pgm.s.pRamRangesRC)
4168	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Sorry, no Ram is registered.\n");
4169
4170	/*
4171	* Dump the ranges.
4172	*/
4173	int rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL, "From - To (incl) pvHC\n");
4174	PPGMRAMRANGE pRam;
4175	for (pRam = pVM->pgm.s.pRamRangesR3; pRam; pRam = pRam->pNextR3)
4176	{
4177	rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL,
4178	"%RGp - %RGp %p\n",
4179	pRam->GCPhys, pRam->GCPhysLast, pRam->pvR3);
4180	if (RT_FAILURE(rc))
4181	return rc;
4182	}
4183
4184	return VINF_SUCCESS;
4185	}
4186
4187
4188	/**
4189	* The '.pgmerror' and '.pgmerroroff' commands.
4190	*
4191	* @returns VBox status.
4192	* @param pCmd Pointer to the command descriptor (as registered).
4193	* @param pCmdHlp Pointer to command helper functions.
4194	* @param pVM Pointer to the current VM (if any).
4195	* @param paArgs Pointer to (readonly) array of arguments.
4196	* @param cArgs Number of arguments in the array.
4197	*/
4198	static DECLCALLBACK(int) pgmR3CmdError(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4199	{
4200	/*
4201	* Validate input.
4202	*/
4203	if (!pVM)
4204	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4205	AssertReturn(cArgs == 0 \|\| (cArgs == 1 && paArgs[0].enmType == DBGCVAR_TYPE_STRING),
4206	pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: Hit bug in the parser.\n"));
4207
4208	if (!cArgs)
4209	{
4210	/*
4211	* Print the list of error injection locations with status.
4212	*/
4213	pCmdHlp->pfnPrintf(pCmdHlp, NULL, "PGM error inject locations:\n");
4214	pCmdHlp->pfnPrintf(pCmdHlp, NULL, " handy - %RTbool\n", pVM->pgm.s.fErrInjHandyPages);
4215	}
4216	else
4217	{
4218
4219	/*
4220	* String switch on where to inject the error.
4221	*/
4222	bool const fNewState = !strcmp(pCmd->pszCmd, "pgmerror");
4223	const char *pszWhere = paArgs[0].u.pszString;
4224	if (!strcmp(pszWhere, "handy"))
4225	ASMAtomicWriteBool(&pVM->pgm.s.fErrInjHandyPages, fNewState);
4226	else
4227	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: Invalid 'where' value: %s.\n", pszWhere);
4228	pCmdHlp->pfnPrintf(pCmdHlp, NULL, "done\n");
4229	}
4230	return VINF_SUCCESS;
4231	}
4232
4233
4234	/**
4235	* The '.pgmsync' command.
4236	*
4237	* @returns VBox status.
4238	* @param pCmd Pointer to the command descriptor (as registered).
4239	* @param pCmdHlp Pointer to command helper functions.
4240	* @param pVM Pointer to the current VM (if any).
4241	* @param paArgs Pointer to (readonly) array of arguments.
4242	* @param cArgs Number of arguments in the array.
4243	*/
4244	static DECLCALLBACK(int) pgmR3CmdSync(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4245	{
4246	/** @todo SMP support */
4247	PVMCPU pVCpu = &pVM->aCpus[0];
4248
4249	/*
4250	* Validate input.
4251	*/
4252	if (!pVM)
4253	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4254
4255	/*
4256	* Force page directory sync.
4257	*/
4258	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
4259
4260	int rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Forcing page directory sync.\n");
4261	if (RT_FAILURE(rc))
4262	return rc;
4263
4264	return VINF_SUCCESS;
4265	}
4266
4267
4268	#ifdef VBOX_STRICT
4269	/**
4270	* The '.pgmassertcr3' command.
4271	*
4272	* @returns VBox status.
4273	* @param pCmd Pointer to the command descriptor (as registered).
4274	* @param pCmdHlp Pointer to command helper functions.
4275	* @param pVM Pointer to the current VM (if any).
4276	* @param paArgs Pointer to (readonly) array of arguments.
4277	* @param cArgs Number of arguments in the array.
4278	*/
4279	static DECLCALLBACK(int) pgmR3CmdAssertCR3(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4280	{
4281	/** @todo SMP support!! */
4282	PVMCPU pVCpu = &pVM->aCpus[0];
4283
4284	/*
4285	* Validate input.
4286	*/
4287	if (!pVM)
4288	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4289
4290	int rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Checking shadow CR3 page tables for consistency.\n");
4291	if (RT_FAILURE(rc))
4292	return rc;
4293
4294	PGMAssertCR3(pVM, pVCpu, CPUMGetGuestCR3(pVCpu), CPUMGetGuestCR4(pVCpu));
4295
4296	return VINF_SUCCESS;
4297	}
4298	#endif /* VBOX_STRICT */
4299
4300
4301	/**
4302	* The '.pgmsyncalways' command.
4303	*
4304	* @returns VBox status.
4305	* @param pCmd Pointer to the command descriptor (as registered).
4306	* @param pCmdHlp Pointer to command helper functions.
4307	* @param pVM Pointer to the current VM (if any).
4308	* @param paArgs Pointer to (readonly) array of arguments.
4309	* @param cArgs Number of arguments in the array.
4310	*/
4311	static DECLCALLBACK(int) pgmR3CmdSyncAlways(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4312	{
4313	/** @todo SMP support!! */
4314	PVMCPU pVCpu = &pVM->aCpus[0];
4315
4316	/*
4317	* Validate input.
4318	*/
4319	if (!pVM)
4320	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4321
4322	/*
4323	* Force page directory sync.
4324	*/
4325	if (pVCpu->pgm.s.fSyncFlags & PGM_SYNC_ALWAYS)
4326	{
4327	ASMAtomicAndU32(&pVCpu->pgm.s.fSyncFlags, ~PGM_SYNC_ALWAYS);
4328	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Disabled permanent forced page directory syncing.\n");
4329	}
4330	else
4331	{
4332	ASMAtomicOrU32(&pVCpu->pgm.s.fSyncFlags, PGM_SYNC_ALWAYS);
4333	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
4334	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Enabled permanent forced page directory syncing.\n");
4335	}
4336	}
4337
4338
4339	/**
4340	* The '.pgmphystofile' command.
4341	*
4342	* @returns VBox status.
4343	* @param pCmd Pointer to the command descriptor (as registered).
4344	* @param pCmdHlp Pointer to command helper functions.
4345	* @param pVM Pointer to the current VM (if any).
4346	* @param paArgs Pointer to (readonly) array of arguments.
4347	* @param cArgs Number of arguments in the array.
4348	*/
4349	static DECLCALLBACK(int) pgmR3CmdPhysToFile(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4350	{
4351	/*
4352	* Validate input.
4353	*/
4354	if (!pVM)
4355	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4356	if ( cArgs < 1
4357	\|\| cArgs > 2
4358	\|\| paArgs[0].enmType != DBGCVAR_TYPE_STRING
4359	\|\| ( cArgs > 1
4360	&& paArgs[1].enmType != DBGCVAR_TYPE_STRING))
4361	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: parser error, invalid arguments.\n");
4362	if ( cArgs >= 2
4363	&& strcmp(paArgs[1].u.pszString, "nozero"))
4364	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: Invalid 2nd argument '%s', must be 'nozero'.\n", paArgs[1].u.pszString);
4365	bool fIncZeroPgs = cArgs < 2;
4366
4367	/*
4368	* Open the output file and get the ram parameters.
4369	*/
4370	RTFILE hFile;
4371	int rc = RTFileOpen(&hFile, paArgs[0].u.pszString, RTFILE_O_WRITE \| RTFILE_O_CREATE_REPLACE \| RTFILE_O_DENY_WRITE);
4372	if (RT_FAILURE(rc))
4373	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: RTFileOpen(,'%s',) -> %Rrc.\n", paArgs[0].u.pszString, rc);
4374
4375	uint32_t cbRamHole = 0;
4376	CFGMR3QueryU32Def(CFGMR3GetRoot(pVM), "RamHoleSize", &cbRamHole, MM_RAM_HOLE_SIZE_DEFAULT);
4377	uint64_t cbRam = 0;
4378	CFGMR3QueryU64Def(CFGMR3GetRoot(pVM), "RamSize", &cbRam, 0);
4379	RTGCPHYS GCPhysEnd = cbRam + cbRamHole;
4380
4381	/*
4382	* Dump the physical memory, page by page.
4383	*/
4384	RTGCPHYS GCPhys = 0;
4385	char abZeroPg[PAGE_SIZE];
4386	RT_ZERO(abZeroPg);
4387
4388	pgmLock(pVM);
4389	for (PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesR3;
4390	pRam && pRam->GCPhys < GCPhysEnd && RT_SUCCESS(rc);
4391	pRam = pRam->pNextR3)
4392	{
4393	/* fill the gap */
4394	if (pRam->GCPhys > GCPhys && fIncZeroPgs)
4395	{
4396	while (pRam->GCPhys > GCPhys && RT_SUCCESS(rc))
4397	{
4398	rc = RTFileWrite(hFile, abZeroPg, PAGE_SIZE, NULL);
4399	GCPhys += PAGE_SIZE;
4400	}
4401	}
4402
4403	PCPGMPAGE pPage = &pRam->aPages[0];
4404	while (GCPhys < pRam->GCPhysLast && RT_SUCCESS(rc))
4405	{
4406	if ( PGM_PAGE_IS_ZERO(pPage)
4407	\|\| PGM_PAGE_IS_BALLOONED(pPage))
4408	{
4409	if (fIncZeroPgs)
4410	{
4411	rc = RTFileWrite(hFile, abZeroPg, PAGE_SIZE, NULL);
4412	if (RT_FAILURE(rc))
4413	pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: RTFileWrite -> %Rrc at GCPhys=%RGp.\n", rc, GCPhys);
4414	}
4415	}
4416	else
4417	{
4418	switch (PGM_PAGE_GET_TYPE(pPage))
4419	{
4420	case PGMPAGETYPE_RAM:
4421	case PGMPAGETYPE_ROM_SHADOW: /* trouble?? */
4422	case PGMPAGETYPE_ROM:
4423	case PGMPAGETYPE_MMIO2:
4424	{
4425	void const *pvPage;
4426	PGMPAGEMAPLOCK Lock;
4427	rc = PGMPhysGCPhys2CCPtrReadOnly(pVM, GCPhys, &pvPage, &Lock);
4428	if (RT_SUCCESS(rc))
4429	{
4430	rc = RTFileWrite(hFile, pvPage, PAGE_SIZE, NULL);
4431	PGMPhysReleasePageMappingLock(pVM, &Lock);
4432	if (RT_FAILURE(rc))
4433	pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: RTFileWrite -> %Rrc at GCPhys=%RGp.\n", rc, GCPhys);
4434	}
4435	else
4436	pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: PGMPhysGCPhys2CCPtrReadOnly -> %Rrc at GCPhys=%RGp.\n", rc, GCPhys);
4437	break;
4438	}
4439
4440	default:
4441	AssertFailed();
4442	case PGMPAGETYPE_MMIO2_ALIAS_MMIO:
4443	case PGMPAGETYPE_MMIO:
4444	if (fIncZeroPgs)
4445	{
4446	rc = RTFileWrite(hFile, abZeroPg, PAGE_SIZE, NULL);
4447	if (RT_FAILURE(rc))
4448	pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: RTFileWrite -> %Rrc at GCPhys=%RGp.\n", rc, GCPhys);
4449	}
4450	break;
4451	}
4452	}
4453
4454
4455	/* advance */
4456	GCPhys += PAGE_SIZE;
4457	pPage++;
4458	}
4459	}
4460	pgmUnlock(pVM);
4461
4462	RTFileClose(hFile);
4463	if (RT_SUCCESS(rc))
4464	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Successfully saved physical memory to '%s'.\n", paArgs[0].u.pszString);
4465	return VINF_SUCCESS;
4466	}
4467
4468	#endif /* VBOX_WITH_DEBUGGER */
4469
4470	/**
4471	* pvUser argument of the pgmR3CheckIntegrity*Node callbacks.
4472	*/
4473	typedef struct PGMCHECKINTARGS
4474	{
4475	bool fLeftToRight; /*< true: left-to-right; false: right-to-left. /
4476	PPGMPHYSHANDLER pPrevPhys;
4477	PPGMVIRTHANDLER pPrevVirt;
4478	PPGMPHYS2VIRTHANDLER pPrevPhys2Virt;
4479	PVM pVM;
4480	} PGMCHECKINTARGS, *PPGMCHECKINTARGS;
4481
4482	/**
4483	* Validate a node in the physical handler tree.
4484	*
4485	* @returns 0 on if ok, other wise 1.
4486	* @param pNode The handler node.
4487	* @param pvUser pVM.
4488	*/
4489	static DECLCALLBACK(int) pgmR3CheckIntegrityPhysHandlerNode(PAVLROGCPHYSNODECORE pNode, void *pvUser)
4490	{
4491	PPGMCHECKINTARGS pArgs = (PPGMCHECKINTARGS)pvUser;
4492	PPGMPHYSHANDLER pCur = (PPGMPHYSHANDLER)pNode;
4493	AssertReleaseReturn(!((uintptr_t)pCur & 7), 1);
4494	AssertReleaseMsg(pCur->Core.Key <= pCur->Core.KeyLast,("pCur=%p %RGp-%RGp %s\n", pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
4495	AssertReleaseMsg( !pArgs->pPrevPhys
4496	\|\| (pArgs->fLeftToRight ? pArgs->pPrevPhys->Core.KeyLast < pCur->Core.Key : pArgs->pPrevPhys->Core.KeyLast > pCur->Core.Key),
4497	("pPrevPhys=%p %RGp-%RGp %s\n"
4498	" pCur=%p %RGp-%RGp %s\n",
4499	pArgs->pPrevPhys, pArgs->pPrevPhys->Core.Key, pArgs->pPrevPhys->Core.KeyLast, pArgs->pPrevPhys->pszDesc,
4500	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
4501	pArgs->pPrevPhys = pCur;
4502	return 0;
4503	}
4504
4505
4506	/**
4507	* Validate a node in the virtual handler tree.
4508	*
4509	* @returns 0 on if ok, other wise 1.
4510	* @param pNode The handler node.
4511	* @param pvUser pVM.
4512	*/
4513	static DECLCALLBACK(int) pgmR3CheckIntegrityVirtHandlerNode(PAVLROGCPTRNODECORE pNode, void *pvUser)
4514	{
4515	PPGMCHECKINTARGS pArgs = (PPGMCHECKINTARGS)pvUser;
4516	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)pNode;
4517	AssertReleaseReturn(!((uintptr_t)pCur & 7), 1);
4518	AssertReleaseMsg(pCur->Core.Key <= pCur->Core.KeyLast,("pCur=%p %RGv-%RGv %s\n", pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
4519	AssertReleaseMsg( !pArgs->pPrevVirt
4520	\|\| (pArgs->fLeftToRight ? pArgs->pPrevVirt->Core.KeyLast < pCur->Core.Key : pArgs->pPrevVirt->Core.KeyLast > pCur->Core.Key),
4521	("pPrevVirt=%p %RGv-%RGv %s\n"
4522	" pCur=%p %RGv-%RGv %s\n",
4523	pArgs->pPrevVirt, pArgs->pPrevVirt->Core.Key, pArgs->pPrevVirt->Core.KeyLast, pArgs->pPrevVirt->pszDesc,
4524	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
4525	for (unsigned iPage = 0; iPage < pCur->cPages; iPage++)
4526	{
4527	AssertReleaseMsg(pCur->aPhysToVirt[iPage].offVirtHandler == -RT_OFFSETOF(PGMVIRTHANDLER, aPhysToVirt[iPage]),
4528	("pCur=%p %RGv-%RGv %s\n"
4529	"iPage=%d offVirtHandle=%#x expected %#x\n",
4530	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc,
4531	iPage, pCur->aPhysToVirt[iPage].offVirtHandler, -RT_OFFSETOF(PGMVIRTHANDLER, aPhysToVirt[iPage])));
4532	}
4533	pArgs->pPrevVirt = pCur;
4534	return 0;
4535	}
4536
4537
4538	/**
4539	* Validate a node in the virtual handler tree.
4540	*
4541	* @returns 0 on if ok, other wise 1.
4542	* @param pNode The handler node.
4543	* @param pvUser pVM.
4544	*/
4545	static DECLCALLBACK(int) pgmR3CheckIntegrityPhysToVirtHandlerNode(PAVLROGCPHYSNODECORE pNode, void *pvUser)
4546	{
4547	PPGMCHECKINTARGS pArgs = (PPGMCHECKINTARGS)pvUser;
4548	PPGMPHYS2VIRTHANDLER pCur = (PPGMPHYS2VIRTHANDLER)pNode;
4549	AssertReleaseMsgReturn(!((uintptr_t)pCur & 3), ("\n"), 1);
4550	AssertReleaseMsgReturn(!(pCur->offVirtHandler & 3), ("\n"), 1);
4551	AssertReleaseMsg(pCur->Core.Key <= pCur->Core.KeyLast,("pCur=%p %RGp-%RGp\n", pCur, pCur->Core.Key, pCur->Core.KeyLast));
4552	AssertReleaseMsg( !pArgs->pPrevPhys2Virt
4553	\|\| (pArgs->fLeftToRight ? pArgs->pPrevPhys2Virt->Core.KeyLast < pCur->Core.Key : pArgs->pPrevPhys2Virt->Core.KeyLast > pCur->Core.Key),
4554	("pPrevPhys2Virt=%p %RGp-%RGp\n"
4555	" pCur=%p %RGp-%RGp\n",
4556	pArgs->pPrevPhys2Virt, pArgs->pPrevPhys2Virt->Core.Key, pArgs->pPrevPhys2Virt->Core.KeyLast,
4557	pCur, pCur->Core.Key, pCur->Core.KeyLast));
4558	AssertReleaseMsg( !pArgs->pPrevPhys2Virt
4559	\|\| (pArgs->fLeftToRight ? pArgs->pPrevPhys2Virt->Core.KeyLast < pCur->Core.Key : pArgs->pPrevPhys2Virt->Core.KeyLast > pCur->Core.Key),
4560	("pPrevPhys2Virt=%p %RGp-%RGp\n"
4561	" pCur=%p %RGp-%RGp\n",
4562	pArgs->pPrevPhys2Virt, pArgs->pPrevPhys2Virt->Core.Key, pArgs->pPrevPhys2Virt->Core.KeyLast,
4563	pCur, pCur->Core.Key, pCur->Core.KeyLast));
4564	AssertReleaseMsg((pCur->offNextAlias & (PGMPHYS2VIRTHANDLER_IN_TREE \| PGMPHYS2VIRTHANDLER_IS_HEAD)) == (PGMPHYS2VIRTHANDLER_IN_TREE \| PGMPHYS2VIRTHANDLER_IS_HEAD),
4565	("pCur=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4566	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias));
4567	if (pCur->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK)
4568	{
4569	PPGMPHYS2VIRTHANDLER pCur2 = pCur;
4570	for (;;)
4571	{
4572	pCur2 = (PPGMPHYS2VIRTHANDLER)((intptr_t)pCur + (pCur->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK));
4573	AssertReleaseMsg(pCur2 != pCur,
4574	(" pCur=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4575	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias));
4576	AssertReleaseMsg((pCur2->offNextAlias & (PGMPHYS2VIRTHANDLER_IN_TREE \| PGMPHYS2VIRTHANDLER_IS_HEAD)) == PGMPHYS2VIRTHANDLER_IN_TREE,
4577	(" pCur=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
4578	"pCur2=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4579	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias,
4580	pCur2, pCur2->Core.Key, pCur2->Core.KeyLast, pCur2->offVirtHandler, pCur2->offNextAlias));
4581	AssertReleaseMsg((pCur2->Core.Key ^ pCur->Core.Key) < PAGE_SIZE,
4582	(" pCur=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
4583	"pCur2=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4584	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias,
4585	pCur2, pCur2->Core.Key, pCur2->Core.KeyLast, pCur2->offVirtHandler, pCur2->offNextAlias));
4586	AssertReleaseMsg((pCur2->Core.KeyLast ^ pCur->Core.KeyLast) < PAGE_SIZE,
4587	(" pCur=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
4588	"pCur2=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4589	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias,
4590	pCur2, pCur2->Core.Key, pCur2->Core.KeyLast, pCur2->offVirtHandler, pCur2->offNextAlias));
4591	if (!(pCur2->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK))
4592	break;
4593	}
4594	}
4595
4596	pArgs->pPrevPhys2Virt = pCur;
4597	return 0;
4598	}
4599
4600
4601	/**
4602	* Perform an integrity check on the PGM component.
4603	*
4604	* @returns VINF_SUCCESS if everything is fine.
4605	* @returns VBox error status after asserting on integrity breach.
4606	* @param pVM The VM handle.
4607	*/
4608	VMMR3DECL(int) PGMR3CheckIntegrity(PVM pVM)
4609	{
4610	AssertReleaseReturn(pVM->pgm.s.offVM, VERR_INTERNAL_ERROR);
4611
4612	/*
4613	* Check the trees.
4614	*/
4615	int cErrors = 0;
4616	const static PGMCHECKINTARGS s_LeftToRight = { true, NULL, NULL, NULL, pVM };
4617	const static PGMCHECKINTARGS s_RightToLeft = { false, NULL, NULL, NULL, pVM };
4618	PGMCHECKINTARGS Args = s_LeftToRight;
4619	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysHandlers, true, pgmR3CheckIntegrityPhysHandlerNode, &Args);
4620	Args = s_RightToLeft;
4621	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysHandlers, false, pgmR3CheckIntegrityPhysHandlerNode, &Args);
4622	Args = s_LeftToRight;
4623	cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesR3->VirtHandlers, true, pgmR3CheckIntegrityVirtHandlerNode, &Args);
4624	Args = s_RightToLeft;
4625	cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesR3->VirtHandlers, false, pgmR3CheckIntegrityVirtHandlerNode, &Args);
4626	Args = s_LeftToRight;
4627	cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesR3->HyperVirtHandlers, true, pgmR3CheckIntegrityVirtHandlerNode, &Args);
4628	Args = s_RightToLeft;
4629	cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesR3->HyperVirtHandlers, false, pgmR3CheckIntegrityVirtHandlerNode, &Args);
4630	Args = s_LeftToRight;
4631	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysToVirtHandlers, true, pgmR3CheckIntegrityPhysToVirtHandlerNode, &Args);
4632	Args = s_RightToLeft;
4633	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysToVirtHandlers, false, pgmR3CheckIntegrityPhysToVirtHandlerNode, &Args);
4634
4635	return !cErrors ? VINF_SUCCESS : VERR_INTERNAL_ERROR;
4636	}
4637

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source: vbox/trunk/src/VBox/VMM/PGM.cpp@ 31844

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