PGM.cpp@ 4729

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1	/* $Id: PGM.cpp 4714 2007-09-11 16:30:42Z vboxsync $ */
2	/** @file
3	* PGM - Page Manager and Monitor. (Mixing stuff here, not good?)
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 innotek GmbH
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License as published by the Free Software Foundation,
13	* in version 2 as it comes in the "COPYING" file of the VirtualBox OSE
14	* distribution. VirtualBox OSE is distributed in the hope that it will
15	* be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/** @page pg_pgm PGM - The Page Manager and Monitor
20	*
21	*
22	*
23	* @section sec_pgm_modes Paging Modes
24	*
25	* There are three memory contexts: Host Context (HC), Guest Context (GC)
26	* and intermediate context. When talking about paging HC can also be refered to
27	* as "host paging", and GC refered to as "shadow paging".
28	*
29	* We define three basic paging modes: 32-bit, PAE and AMD64. The host paging mode
30	* is defined by the host operating system. The mode used in the shadow paging mode
31	* depends on the host paging mode and what the mode the guest is currently in. The
32	* following relation between the two is defined:
33	*
34	* @verbatim
35	Host > 32-bit \| PAE \| AMD64 \|
36	Guest \| \| \| \|
37	==v================================
38	32-bit 32-bit PAE PAE
39	-------\|--------\|--------\|--------\|
40	PAE PAE PAE PAE
41	-------\|--------\|--------\|--------\|
42	AMD64 AMD64 AMD64 AMD64
43	-------\|--------\|--------\|--------\| @endverbatim
44	*
45	* All configuration except those in the diagonal (upper left) are expected to
46	* require special effort from the switcher (i.e. a bit slower).
47	*
48	*
49	*
50	*
51	* @section sec_pgm_shw The Shadow Memory Context
52	*
53	*
54	* [..]
55	*
56	* Because of guest context mappings requires PDPTR and PML4 entries to allow
57	* writing on AMD64, the two upper levels will have fixed flags whatever the
58	* guest is thinking of using there. So, when shadowing the PD level we will
59	* calculate the effective flags of PD and all the higher levels. In legacy
60	* PAE mode this only applies to the PWT and PCD bits (the rest are
61	* ignored/reserved/MBZ). We will ignore those bits for the present.
62	*
63	*
64	*
65	* @section sec_pgm_int The Intermediate Memory Context
66	*
67	* The world switch goes thru an intermediate memory context which purpose it is
68	* to provide different mappings of the switcher code. All guest mappings are also
69	* present in this context.
70	*
71	* The switcher code is mapped at the same location as on the host, at an
72	* identity mapped location (physical equals virtual address), and at the
73	* hypervisor location.
74	*
75	* PGM maintain page tables for 32-bit, PAE and AMD64 paging modes. This
76	* simplifies switching guest CPU mode and consistency at the cost of more
77	* code to do the work. All memory use for those page tables is located below
78	* 4GB (this includes page tables for guest context mappings).
79	*
80	*
81	* @subsection subsec_pgm_int_gc Guest Context Mappings
82	*
83	* During assignment and relocation of a guest context mapping the intermediate
84	* memory context is used to verify the new location.
85	*
86	* Guest context mappings are currently restricted to below 4GB, for reasons
87	* of simplicity. This may change when we implement AMD64 support.
88	*
89	*
90	*
91	*
92	* @section sec_pgm_misc Misc
93	*
94	* @subsection subsec_pgm_misc_diff Differences Between Legacy PAE and Long Mode PAE
95	*
96	* The differences between legacy PAE and long mode PAE are:
97	* -# PDPE bits 1, 2, 5 and 6 are defined differently. In leagcy mode they are
98	* all marked down as must-be-zero, while in long mode 1, 2 and 5 have the
99	* usual meanings while 6 is ignored (AMD). This means that upon switching to
100	* legacy PAE mode we'll have to clear these bits and when going to long mode
101	* they must be set. This applies to both intermediate and shadow contexts,
102	* however we don't need to do it for the intermediate one since we're
103	* executing with CR0.WP at that time.
104	* -# CR3 allows a 32-byte aligned address in legacy mode, while in long mode
105	* a page aligned one is required.
106	*/
107
108
109	/** @page pg_pgmPhys PGMPhys - Physical Guest Memory Management.
110	*
111	*
112	* Objectives:
113	* - Guest RAM over-commitment using memory ballooning,
114	* zero pages and general page sharing.
115	* - Moving or mirroring a VM onto a different physical machine.
116	*
117	*
118	* @subsection subsec_pgmPhys_Definitions Definitions
119	*
120	* Allocation chunk - A RTR0MemObjAllocPhysNC object and the tracking
121	* machinery assoicated with it.
122	*
123	*
124	*
125	*
126	* @subsection subsec_pgmPhys_AllocPage Allocating a page.
127	*
128	* Initially we map all guest memory to the (per VM) zero page, which
129	* means that none of the read functions will cause pages to be allocated.
130	*
131	* Exception, access bit in page tables that have been shared. This must
132	* be handled, but we must also make sure PGMGst*Modify doesn't make
133	* unnecessary modifications.
134	*
135	* Allocation points:
136	* - PGMPhysWriteGCPhys and PGMPhysWrite.
137	* - Replacing a zero page mapping at \#PF.
138	* - Replacing a shared page mapping at \#PF.
139	* - ROM registration (currently MMR3RomRegister).
140	* - VM restore (pgmR3Load).
141	*
142	* For the first three it would make sense to keep a few pages handy
143	* until we've reached the max memory commitment for the VM.
144	*
145	* For the ROM registration, we know exactly how many pages we need
146	* and will request these from ring-0. For restore, we will save
147	* the number of non-zero pages in the saved state and allocate
148	* them up front. This would allow the ring-0 component to refuse
149	* the request if the isn't sufficient memory available for VM use.
150	*
151	* Btw. for both ROM and restore allocations we won't be requiring
152	* zeroed pages as they are going to be filled instantly.
153	*
154	*
155	* @subsection subsec_pgmPhys_FreePage Freeing a page
156	*
157	* There are a few points where a page can be freed:
158	* - After being replaced by the zero page.
159	* - After being replaced by a shared page.
160	* - After being ballooned by the guest additions.
161	* - At reset.
162	* - At restore.
163	*
164	* When freeing one or more pages they will be returned to the ring-0
165	* component and replaced by the zero page.
166	*
167	* The reasoning for clearing out all the pages on reset is that it will
168	* return us to the exact same state as on power on, and may thereby help
169	* us reduce the memory load on the system. Further it might have a
170	* (temporary) positive influence on memory fragmentation (@see subsec_pgmPhys_Fragmentation).
171	*
172	* On restore, as mention under the allocation topic, pages should be
173	* freed / allocated depending on how many is actually required by the
174	* new VM state. The simplest approach is to do like on reset, and free
175	* all non-ROM pages and then allocate what we need.
176	*
177	* A measure to prevent some fragmentation, would be to let each allocation
178	* chunk have some affinity towards the VM having allocated the most pages
179	* from it. Also, try make sure to allocate from allocation chunks that
180	* are almost full. Admittedly, both these measures might work counter to
181	* our intentions and its probably not worth putting a lot of effort,
182	* cpu time or memory into this.
183	*
184	*
185	* @subsection subsec_pgmPhys_SharePage Sharing a page
186	*
187	* The basic idea is that there there will be a idle priority kernel
188	* thread walking the non-shared VM pages hashing them and looking for
189	* pages with the same checksum. If such pages are found, it will compare
190	* them byte-by-byte to see if they actually are identical. If found to be
191	* identical it will allocate a shared page, copy the content, check that
192	* the page didn't change while doing this, and finally request both the
193	* VMs to use the shared page instead. If the page is all zeros (special
194	* checksum and byte-by-byte check) it will request the VM that owns it
195	* to replace it with the zero page.
196	*
197	* To make this efficient, we will have to make sure not to try share a page
198	* that will change its contents soon. This part requires the most work.
199	* A simple idea would be to request the VM to write monitor the page for
200	* a while to make sure it isn't modified any time soon. Also, it may
201	* make sense to skip pages that are being write monitored since this
202	* information is readily available to the thread if it works on the
203	* per-VM guest memory structures (presently called PGMRAMRANGE).
204	*
205	*
206	* @subsection subsec_pgmPhys_Fragmentation Fragmentation Concerns and Counter Measures
207	*
208	* The pages are organized in allocation chunks in ring-0, this is a necessity
209	* if we wish to have an OS agnostic approach to this whole thing. (On Linux we
210	* could easily work on a page-by-page basis if we liked. Whether this is possible
211	* or efficient on NT I don't quite know.) Fragmentation within these chunks may
212	* become a problem as part of the idea here is that we wish to return memory to
213	* the host system.
214	*
215	* For instance, starting two VMs at the same time, they will both allocate the
216	* guest memory on-demand and if permitted their page allocations will be
217	* intermixed. Shut down one of the two VMs and it will be difficult to return
218	* any memory to the host system because the page allocation for the two VMs are
219	* mixed up in the same allocation chunks.
220	*
221	* To further complicate matters, when pages are freed because they have been
222	* ballooned or become shared/zero the whole idea is that the page is supposed
223	* to be reused by another VM or returned to the host system. This will cause
224	* allocation chunks to contain pages belonging to different VMs and prevent
225	* returning memory to the host when one of those VM shuts down.
226	*
227	* The only way to really deal with this problem is to move pages. This can
228	* either be done at VM shutdown and or by the idle priority worker thread
229	* that will be responsible for finding sharable/zero pages. The mechanisms
230	* involved for coercing a VM to move a page (or to do it for it) will be
231	* the same as when telling it to share/zero a page.
232	*
233	*
234	* @subsection subsec_pgmPhys_Tracking Tracking Structures And Their Cost
235	*
236	* There's a difficult balance between keeping the per-page tracking structures
237	* (global and guest page) easy to use and keeping them from eating too much
238	* memory. We have limited virtual memory resources available when operating in
239	* 32-bit kernel space (on 64-bit there'll it's quite a different story). The
240	* tracking structures will be attemted designed such that we can deal with up
241	* to 32GB of memory on a 32-bit system and essentially unlimited on 64-bit ones.
242	*
243	*
244	* @subsubsection subsubsec_pgmPhys_Tracking_Kernel Kernel Space
245	*
246	* The allocation chunks are of fixed sized, the size defined at build time.
247	* Each chunk is given an unquie ID. Each page can be addressed by
248	* (idChunk << CHUNK_SHIFT) \| iPage, where CHUNK_SHIFT is log2(cbChunk / PAGE_SIZE).
249	* Meaning that each page have an unique ID, a sort of virtual page frame number
250	* if you like, so that a page can be referenced to in an efficient manner.
251	* No surprise, the allocation chunks are organized in an AVL tree with
252	* their IDs being the key.
253	*
254	* The physical address of each page in an allocation chunk is maintained by
255	* the RTR0MEMOBJ and obtained using RTR0MemObjGetPagePhysAddr. There is no
256	* need to duplicate this information unnecessarily.
257	*
258	* We wish to maintain a reference to the VM owning the page. For the purposes
259	* of defragmenting allocation chunks, it would make sense to keep track of
260	* which page within the VM that it's being used as, although this will
261	* obviously make the handy pages a wee more work to realize. For shared
262	* pages we need a reference count so we know when to free the page. But tracking
263	* which VMs using shared pages will be too complicated and expensive, so we'll
264	* just forget about it. And finally, free pages needs to be chained somehow,
265	* so we can do allocations in an efficient manner.
266	*
267	* Putting shared pages in dedicated allocation chunks will simplify matters
268	* quite a bit. It will more or less eliminate the problem with defragmenting
269	* shared pages, but arranging it so that we will never encounter shared pages
270	* and normal pages in the same allocation chunks. And it will I think permit
271	* us to get away with a 32-bit field for each page.
272	*
273	* We'll chain the free pages using this field to indicate the index of the
274	* next page. (I'm undecided whether this chain should be on a per-chunk
275	* level or not, it depends a bit on whether it's desirable to keep chunks
276	* with free pages in a priority list by free page count (ascending) in order
277	* to maximize the number of full chunks.) In any case, there'll be two free
278	* lists, one for shared pages and one for normal pages.
279	*
280	* Shared pages that have been allocated will use the 32-bit field for keeping
281	* the reference counter.
282	*
283	* Normal pages that have been allocated will use the first 24 bits for guest
284	* page frame number (i.e. shift by PAGE_SHIFT and you'll have the physical
285	* address, all 24-bit set means unknown or out of range). The top 8 bits will
286	* be used as VM handle index - we assign each VM a unique handle [0..255] for
287	* this purpose. This implies a max of 256 VMs and 64GB of base RAM per VM.
288	* Neither limits should cause any trouble for the time being.
289	*
290	* The per page cost in kernel space is 32-bit plus whatever RTR0MEMOBJ
291	* entails. In addition there is the chunk cost of approximately
292	* (sizeof(RT0MEMOBJ) + sizof(CHUNK)) / 2^CHUNK_SHIFT bytes per page.
293	*
294	* On Windows the per page RTR0MEMOBJ cost is 32-bit on 32-bit windows
295	* and 64-bit on 64-bit windows (a PFN_NUMBER in the MDL). So, 64-bit per page.
296	* The cost on Linux is identical, but here it's because of sizeof(struct page *).
297	*
298	*
299	* @subsubsection subsubsec_pgmPhys_Tracking_PerVM Per-VM
300	*
301	* Fixed info is the physical address of the page (HCPhys) and the page id
302	* (described above). Theoretically we'll need 48(-12) bits for the HCPhys part.
303	* Today we've restricting ourselves to 40(-12) bits because this is the current
304	* restrictions of all AMD64 implementations (I think Barcelona will up this
305	* to 48(-12) bits, not that it really matters) and I needed the bits for
306	* tracking mappings of a page. 48-12 = 36. That leaves 28 bits, which means a
307	* decent range for the page id: 2^(28+12) = 1024TB.
308	*
309	* In additions to these, we'll have to keep maintaining the page flags as we
310	* currently do. Although it wouldn't harm to optimize these quite a bit, like
311	* for instance the ROM shouldn't depend on having a write handler installed
312	* in order for it to become read-only. A RO/RW bit should be considered so
313	* that the page syncing code doesn't have to mess about checking multiple
314	* flag combinations (ROM \|\| RW handler \|\| write monitored) in order to
315	* figure out how to setup a shadow PTE. But this of course, is second
316	* priority at present. Current this requires 12 bits, but could probably
317	* be optimized to ~8.
318	*
319	* Then there's the 24 bits used to track which shadow page tables are
320	* currently mapping a page for the purpose of speeding up physical
321	* access handlers, and thereby the page pool cache. More bit for this
322	* purpose wouldn't hurt IIRC.
323	*
324	* Then there is a new bit in which we need to record what kind of page
325	* this is, shared, zero, normal or write-monitored-normal. This'll
326	* require 2 bits. One bit might be needed for indicating whether a
327	* write monitored page has been written to. And yet another one or
328	* two for tracking migration status. 3-4 bits total then.
329	*
330	* Whatever is left will can be used to record the sharabilitiy of a
331	* page. The page checksum will not be stored in the per-VM table as
332	* the idle thread will not be permitted to do modifications to it.
333	* It will instead have to keep its own working set of potentially
334	* shareable pages and their check sums and stuff.
335	*
336	* For the present we'll keep the current packing of the
337	* PGMRAMRANGE::aHCPhys to keep the changes simple, only of course,
338	* we'll have to change it to a struct with a total of 128-bits at
339	* our disposal.
340	*
341	* The initial layout will be like this:
342	* @verbatim
343	RTHCPHYS HCPhys; The current stuff.
344	63:40 Current shadow PT tracking stuff.
345	39:12 The physical page frame number.
346	11:0 The current flags.
347	uint32_t u28PageId : 28; The page id.
348	uint32_t u2State : 2; The page state { zero, shared, normal, write monitored }.
349	uint32_t fWrittenTo : 1; Whether a write monitored page was written to.
350	uint32_t u1Reserved : 1; Reserved for later.
351	uint32_t u32Reserved; Reserved for later, mostly sharing stats.
352	@endverbatim
353	*
354	* The final layout will be something like this:
355	* @verbatim
356	RTHCPHYS HCPhys; The current stuff.
357	63:48 High page id (12+).
358	47:12 The physical page frame number.
359	11:0 Low page id.
360	uint32_t fReadOnly : 1; Whether it's readonly page (rom or monitored in some way).
361	uint32_t u3Type : 3; The page type {RESERVED, MMIO, MMIO2, ROM, shadowed ROM, RAM}.
362	uint32_t u2PhysMon : 2; Physical access handler type {none, read, write, all}.
363	uint32_t u2VirtMon : 2; Virtual access handler type {none, read, write, all}..
364	uint32_t u2State : 2; The page state { zero, shared, normal, write monitored }.
365	uint32_t fWrittenTo : 1; Whether a write monitored page was written to.
366	uint32_t u20Reserved : 20; Reserved for later, mostly sharing stats.
367	uint32_t u32Tracking; The shadow PT tracking stuff, roughly.
368	@endverbatim
369	*
370	* Cost wise, this means we'll double the cost for guest memory. There isn't anyway
371	* around that I'm afraid. It means that the cost of dealing out 32GB of memory
372	* to one or more VMs is: (32GB >> PAGE_SHIFT) * 16 bytes, or 128MBs. Or another
373	* example, the VM heap cost when assigning 1GB to a VM will be: 4MB.
374	*
375	* A couple of cost examples for the total cost per-VM + kernel.
376	* 32-bit Windows and 32-bit linux:
377	* 1GB guest ram, 256K pages: 4MB + 2MB(+) = 6MB
378	* 4GB guest ram, 1M pages: 16MB + 8MB(+) = 24MB
379	* 32GB guest ram, 8M pages: 128MB + 64MB(+) = 192MB
380	* 64-bit Windows and 64-bit linux:
381	* 1GB guest ram, 256K pages: 4MB + 3MB(+) = 7MB
382	* 4GB guest ram, 1M pages: 16MB + 12MB(+) = 28MB
383	* 32GB guest ram, 8M pages: 128MB + 96MB(+) = 224MB
384	*
385	*
386	* @subsection subsec_pgmPhys_Serializing Serializing Access
387	*
388	* Initially, we'll try a simple scheme:
389	*
390	* - The per-VM RAM tracking structures (PGMRAMRANGE) is only modified
391	* by the EMT thread of that VM while in the pgm critsect.
392	* - Other threads in the VM process that needs to make reliable use of
393	* the per-VM RAM tracking structures will enter the critsect.
394	* - No process external thread or kernel thread will ever try enter
395	* the pgm critical section, as that just won't work.
396	* - The idle thread (and similar threads) doesn't not need 100% reliable
397	* data when performing it tasks as the EMT thread will be the one to
398	* do the actual changes later anyway. So, as long as it only accesses
399	* the main ram range, it can do so by somehow preventing the VM from
400	* being destroyed while it works on it...
401	*
402	* - The over-commitment management, including the allocating/freeing
403	* chunks, is serialized by a ring-0 mutex lock (a fast one since the
404	* more mundane mutex implementation is broken on Linux).
405	* - A separeate mutex is protecting the set of allocation chunks so
406	* that pages can be shared or/and freed up while some other VM is
407	* allocating more chunks. This mutex can be take from under the other
408	* one, but not the otherway around.
409	*
410	*
411	* @subsection subsec_pgmPhys_Request VM Request interface
412	*
413	* When in ring-0 it will become necessary to send requests to a VM so it can
414	* for instance move a page while defragmenting during VM destroy. The idle
415	* thread will make use of this interface to request VMs to setup shared
416	* pages and to perform write monitoring of pages.
417	*
418	* I would propose an interface similar to the current VMReq interface, similar
419	* in that it doesn't require locking and that the one sending the request may
420	* wait for completion if it wishes to. This shouldn't be very difficult to
421	* realize.
422	*
423	* The requests themselves are also pretty simple. They are basically:
424	* -# Check that some precondition is still true.
425	* -# Do the update.
426	* -# Update all shadow page tables involved with the page.
427	*
428	* The 3rd step is identical to what we're already doing when updating a
429	* physical handler, see pgmHandlerPhysicalSetRamFlagsAndFlushShadowPTs.
430	*
431	*
432	*
433	* @section sec_pgmPhys_MappingCaches Mapping Caches
434	*
435	* In order to be able to map in and out memory and to be able to support
436	* guest with more RAM than we've got virtual address space, we'll employing
437	* a mapping cache. There is already a tiny one for GC (see PGMGCDynMapGCPageEx)
438	* and we'll create a similar one for ring-0 unless we decide to setup a dedicate
439	* memory context for the HWACCM execution.
440	*
441	*
442	* @subsection subsec_pgmPhys_MappingCaches_R3 Ring-3
443	*
444	* We've considered implementing the ring-3 mapping cache page based but found
445	* that this was bother some when one had to take into account TLBs+SMP and
446	* portability (missing the necessary APIs on several platforms). There were
447	* also some performance concerns with this approach which hadn't quite been
448	* worked out.
449	*
450	* Instead, we'll be mapping allocation chunks into the VM process. This simplifies
451	* matters greatly quite a bit since we don't need to invent any new ring-0 stuff,
452	* only some minor RTR0MEMOBJ mapping stuff. The main concern here is that mapping
453	* compared to the previous idea is that mapping or unmapping a 1MB chunk is more
454	* costly than a single page, although how much more costly is uncertain. We'll
455	* try address this by using a very big cache, preferably bigger than the actual
456	* VM RAM size if possible. The current VM RAM sizes should give some idea for
457	* 32-bit boxes, while on 64-bit we can probably get away with employing an
458	* unlimited cache.
459	*
460	* The cache have to parts, as already indicated, the ring-3 side and the
461	* ring-0 side.
462	*
463	* The ring-0 will be tied to the page allocator since it will operate on the
464	* memory objects it contains. It will therefore require the first ring-0 mutex
465	* discussed in @ref subsec_pgmPhys_Serializing. We
466	* some double house keeping wrt to who has mapped what I think, since both
467	* VMMR0.r0 and RTR0MemObj will keep track of mapping relataions
468	*
469	* The ring-3 part will be protected by the pgm critsect. For simplicity, we'll
470	* require anyone that desires to do changes to the mapping cache to do that
471	* from within this critsect. Alternatively, we could employ a separate critsect
472	* for serializing changes to the mapping cache as this would reduce potential
473	* contention with other threads accessing mappings unrelated to the changes
474	* that are in process. We can see about this later, contention will show
475	* up in the statistics anyway, so it'll be simple to tell.
476	*
477	* The organization of the ring-3 part will be very much like how the allocation
478	* chunks are organized in ring-0, that is in an AVL tree by chunk id. To avoid
479	* having to walk the tree all the time, we'll have a couple of lookaside entries
480	* like in we do for I/O ports and MMIO in IOM.
481	*
482	* The simplified flow of a PGMPhysRead/Write function:
483	* -# Enter the PGM critsect.
484	* -# Lookup GCPhys in the ram ranges and get the Page ID.
485	* -# Calc the Allocation Chunk ID from the Page ID.
486	* -# Check the lookaside entries and then the AVL tree for the Chunk ID.
487	* If not found in cache:
488	* -# Call ring-0 and request it to be mapped and supply
489	* a chunk to be unmapped if the cache is maxed out already.
490	* -# Insert the new mapping into the AVL tree (id + R3 address).
491	* -# Update the relevant lookaside entry and return the mapping address.
492	* -# Do the read/write according to monitoring flags and everything.
493	* -# Leave the critsect.
494	*
495	*
496	* @section sec_pgmPhys_Fallback Fallback
497	*
498	* Current all the "second tier" hosts will not support the RTR0MemObjAllocPhysNC
499	* API and thus require a fallback.
500	*
501	* So, when RTR0MemObjAllocPhysNC returns VERR_NOT_SUPPORTED the page allocator
502	* will return to the ring-3 caller (and later ring-0) and asking it to seed
503	* the page allocator with some fresh pages (VERR_GVM_SEED_ME). Ring-3 will
504	* then perform an SUPPageAlloc(cbChunk >> PAGE_SHIFT) call and make a
505	* "SeededAllocPages" call to ring-0.
506	*
507	* The first time ring-0 sees the VERR_NOT_SUPPORTED failure it will disable
508	* all page sharing (zero page detection will continue). It will also force
509	* all allocations to come from the VM which seeded the page. Both these
510	* measures are taken to make sure that there will never be any need for
511	* mapping anything into ring-3 - everything will be mapped already.
512	*
513	* Whether we'll continue to use the current MM locked memory management
514	* for this I don't quite know (I'd prefer not to and just ditch that all
515	* togther), we'll see what's simplest to do.
516	*
517	*
518	*
519	* @section sec_pgmPhys_Changes Changes
520	*
521	* Breakdown of the changes involved?
522	*/
523
524
525	/** Saved state data unit version. */
526	#define PGM_SAVED_STATE_VERSION 5
527
528	/*******************************************************************************
529	* Header Files *
530	*******************************************************************************/
531	#define LOG_GROUP LOG_GROUP_PGM
532	#include <VBox/dbgf.h>
533	#include <VBox/pgm.h>
534	#include <VBox/cpum.h>
535	#include <VBox/iom.h>
536	#include <VBox/sup.h>
537	#include <VBox/mm.h>
538	#include <VBox/em.h>
539	#include <VBox/stam.h>
540	#include <VBox/rem.h>
541	#include <VBox/dbgf.h>
542	#include <VBox/rem.h>
543	#include <VBox/selm.h>
544	#include <VBox/ssm.h>
545	#include "PGMInternal.h"
546	#include <VBox/vm.h>
547	#include <VBox/dbg.h>
548	#include <VBox/hwaccm.h>
549
550	#include <iprt/assert.h>
551	#include <iprt/alloc.h>
552	#include <iprt/asm.h>
553	#include <iprt/thread.h>
554	#include <iprt/string.h>
555	#include <VBox/param.h>
556	#include <VBox/err.h>
557
558
559
560	/*******************************************************************************
561	* Internal Functions *
562	*******************************************************************************/
563	static int pgmR3InitPaging(PVM pVM);
564	static DECLCALLBACK(void) pgmR3PhysInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
565	static DECLCALLBACK(void) pgmR3InfoMode(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
566	static DECLCALLBACK(void) pgmR3InfoCr3(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
567	static DECLCALLBACK(int) pgmR3RelocatePhysHandler(PAVLROGCPHYSNODECORE pNode, void *pvUser);
568	static DECLCALLBACK(int) pgmR3RelocateVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser);
569	#ifdef VBOX_STRICT
570	static DECLCALLBACK(void) pgmR3ResetNoMorePhysWritesFlag(PVM pVM, VMSTATE enmState, VMSTATE enmOldState, void *pvUser);
571	#endif
572	static DECLCALLBACK(int) pgmR3Save(PVM pVM, PSSMHANDLE pSSM);
573	static DECLCALLBACK(int) pgmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version);
574	static int pgmR3ModeDataInit(PVM pVM, bool fResolveGCAndR0);
575	static void pgmR3ModeDataSwitch(PVM pVM, PGMMODE enmShw, PGMMODE enmGst);
576	static PGMMODE pgmR3CalcShadowMode(PGMMODE enmGuestMode, SUPPAGINGMODE enmHostMode, PGMMODE enmShadowMode, VMMSWITCHER *penmSwitcher);
577
578	#ifdef VBOX_WITH_STATISTICS
579	static void pgmR3InitStats(PVM pVM);
580	#endif
581
582	#ifdef VBOX_WITH_DEBUGGER
583	/** @todo all but the two last commands must be converted to 'info'. */
584	static DECLCALLBACK(int) pgmR3CmdRam(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
585	static DECLCALLBACK(int) pgmR3CmdMap(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
586	static DECLCALLBACK(int) pgmR3CmdSync(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
587	static DECLCALLBACK(int) pgmR3CmdSyncAlways(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
588	#endif
589
590
591	/*******************************************************************************
592	* Global Variables *
593	*******************************************************************************/
594	#ifdef VBOX_WITH_DEBUGGER
595	/** Command descriptors. */
596	static const DBGCCMD g_aCmds[] =
597	{
598	/* pszCmd, cArgsMin, cArgsMax, paArgDesc, cArgDescs, pResultDesc, fFlags, pfnHandler pszSyntax, ....pszDescription */
599	{ "pgmram", 0, 0, NULL, 0, NULL, 0, pgmR3CmdRam, "", "Display the ram ranges." },
600	{ "pgmmap", 0, 0, NULL, 0, NULL, 0, pgmR3CmdMap, "", "Display the mapping ranges." },
601	{ "pgmsync", 0, 0, NULL, 0, NULL, 0, pgmR3CmdSync, "", "Sync the CR3 page." },
602	{ "pgmsyncalways", 0, 0, NULL, 0, NULL, 0, pgmR3CmdSyncAlways, "", "Toggle permanent CR3 syncing." },
603	};
604	#endif
605
606
607
608
609	#if 1/// @todo ndef RT_ARCH_AMD64
610	/*
611	* Shadow - 32-bit mode
612	*/
613	#define PGM_SHW_TYPE PGM_TYPE_32BIT
614	#define PGM_SHW_NAME(name) PGM_SHW_NAME_32BIT(name)
615	#define PGM_SHW_NAME_GC_STR(name) PGM_SHW_NAME_GC_32BIT_STR(name)
616	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_32BIT_STR(name)
617	#include "PGMShw.h"
618
619	/* Guest - real mode */
620	#define PGM_GST_TYPE PGM_TYPE_REAL
621	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
622	#define PGM_GST_NAME_GC_STR(name) PGM_GST_NAME_GC_REAL_STR(name)
623	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
624	#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_REAL(name)
625	#define PGM_BTH_NAME_GC_STR(name) PGM_BTH_NAME_GC_32BIT_REAL_STR(name)
626	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_32BIT_REAL_STR(name)
627	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_PHYS
628	#include "PGMGst.h"
629	#include "PGMBth.h"
630	#undef BTH_PGMPOOLKIND_PT_FOR_PT
631	#undef PGM_BTH_NAME
632	#undef PGM_BTH_NAME_GC_STR
633	#undef PGM_BTH_NAME_R0_STR
634	#undef PGM_GST_TYPE
635	#undef PGM_GST_NAME
636	#undef PGM_GST_NAME_GC_STR
637	#undef PGM_GST_NAME_R0_STR
638
639	/* Guest - protected mode */
640	#define PGM_GST_TYPE PGM_TYPE_PROT
641	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
642	#define PGM_GST_NAME_GC_STR(name) PGM_GST_NAME_GC_PROT_STR(name)
643	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
644	#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_PROT(name)
645	#define PGM_BTH_NAME_GC_STR(name) PGM_BTH_NAME_GC_32BIT_PROT_STR(name)
646	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_32BIT_PROT_STR(name)
647	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_PHYS
648	#include "PGMGst.h"
649	#include "PGMBth.h"
650	#undef BTH_PGMPOOLKIND_PT_FOR_PT
651	#undef PGM_BTH_NAME
652	#undef PGM_BTH_NAME_GC_STR
653	#undef PGM_BTH_NAME_R0_STR
654	#undef PGM_GST_TYPE
655	#undef PGM_GST_NAME
656	#undef PGM_GST_NAME_GC_STR
657	#undef PGM_GST_NAME_R0_STR
658
659	/* Guest - 32-bit mode */
660	#define PGM_GST_TYPE PGM_TYPE_32BIT
661	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
662	#define PGM_GST_NAME_GC_STR(name) PGM_GST_NAME_GC_32BIT_STR(name)
663	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
664	#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_32BIT(name)
665	#define PGM_BTH_NAME_GC_STR(name) PGM_BTH_NAME_GC_32BIT_32BIT_STR(name)
666	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_32BIT_32BIT_STR(name)
667	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT
668	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB
669	#include "PGMGst.h"
670	#include "PGMBth.h"
671	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
672	#undef BTH_PGMPOOLKIND_PT_FOR_PT
673	#undef PGM_BTH_NAME
674	#undef PGM_BTH_NAME_GC_STR
675	#undef PGM_BTH_NAME_R0_STR
676	#undef PGM_GST_TYPE
677	#undef PGM_GST_NAME
678	#undef PGM_GST_NAME_GC_STR
679	#undef PGM_GST_NAME_R0_STR
680
681	#undef PGM_SHW_TYPE
682	#undef PGM_SHW_NAME
683	#undef PGM_SHW_NAME_GC_STR
684	#undef PGM_SHW_NAME_R0_STR
685	#endif /* !RT_ARCH_AMD64 */
686
687
688	/*
689	* Shadow - PAE mode
690	*/
691	#define PGM_SHW_TYPE PGM_TYPE_PAE
692	#define PGM_SHW_NAME(name) PGM_SHW_NAME_PAE(name)
693	#define PGM_SHW_NAME_GC_STR(name) PGM_SHW_NAME_GC_PAE_STR(name)
694	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_PAE_STR(name)
695	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_REAL(name)
696	#include "PGMShw.h"
697
698	/* Guest - real mode */
699	#define PGM_GST_TYPE PGM_TYPE_REAL
700	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
701	#define PGM_GST_NAME_GC_STR(name) PGM_GST_NAME_GC_REAL_STR(name)
702	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
703	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_REAL(name)
704	#define PGM_BTH_NAME_GC_STR(name) PGM_BTH_NAME_GC_PAE_REAL_STR(name)
705	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_REAL_STR(name)
706	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
707	#include "PGMBth.h"
708	#undef BTH_PGMPOOLKIND_PT_FOR_PT
709	#undef PGM_BTH_NAME
710	#undef PGM_BTH_NAME_GC_STR
711	#undef PGM_BTH_NAME_R0_STR
712	#undef PGM_GST_TYPE
713	#undef PGM_GST_NAME
714	#undef PGM_GST_NAME_GC_STR
715	#undef PGM_GST_NAME_R0_STR
716
717	/* Guest - protected mode */
718	#define PGM_GST_TYPE PGM_TYPE_PROT
719	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
720	#define PGM_GST_NAME_GC_STR(name) PGM_GST_NAME_GC_PROT_STR(name)
721	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
722	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_PROT(name)
723	#define PGM_BTH_NAME_GC_STR(name) PGM_BTH_NAME_GC_PAE_PROT_STR(name)
724	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_PROT_STR(name)
725	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
726	#include "PGMBth.h"
727	#undef BTH_PGMPOOLKIND_PT_FOR_PT
728	#undef PGM_BTH_NAME
729	#undef PGM_BTH_NAME_GC_STR
730	#undef PGM_BTH_NAME_R0_STR
731	#undef PGM_GST_TYPE
732	#undef PGM_GST_NAME
733	#undef PGM_GST_NAME_GC_STR
734	#undef PGM_GST_NAME_R0_STR
735
736	/* Guest - 32-bit mode */
737	#define PGM_GST_TYPE PGM_TYPE_32BIT
738	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
739	#define PGM_GST_NAME_GC_STR(name) PGM_GST_NAME_GC_32BIT_STR(name)
740	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
741	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_32BIT(name)
742	#define PGM_BTH_NAME_GC_STR(name) PGM_BTH_NAME_GC_PAE_32BIT_STR(name)
743	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_32BIT_STR(name)
744	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_32BIT_PT
745	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB
746	#include "PGMBth.h"
747	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
748	#undef BTH_PGMPOOLKIND_PT_FOR_PT
749	#undef PGM_BTH_NAME
750	#undef PGM_BTH_NAME_GC_STR
751	#undef PGM_BTH_NAME_R0_STR
752	#undef PGM_GST_TYPE
753	#undef PGM_GST_NAME
754	#undef PGM_GST_NAME_GC_STR
755	#undef PGM_GST_NAME_R0_STR
756
757	/* Guest - PAE mode */
758	#define PGM_GST_TYPE PGM_TYPE_PAE
759	#define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
760	#define PGM_GST_NAME_GC_STR(name) PGM_GST_NAME_GC_PAE_STR(name)
761	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PAE_STR(name)
762	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_PAE(name)
763	#define PGM_BTH_NAME_GC_STR(name) PGM_BTH_NAME_GC_PAE_PAE_STR(name)
764	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_PAE_STR(name)
765	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
766	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
767	#include "PGMGst.h"
768	#include "PGMBth.h"
769	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
770	#undef BTH_PGMPOOLKIND_PT_FOR_PT
771	#undef PGM_BTH_NAME
772	#undef PGM_BTH_NAME_GC_STR
773	#undef PGM_BTH_NAME_R0_STR
774	#undef PGM_GST_TYPE
775	#undef PGM_GST_NAME
776	#undef PGM_GST_NAME_GC_STR
777	#undef PGM_GST_NAME_R0_STR
778
779	#undef PGM_SHW_TYPE
780	#undef PGM_SHW_NAME
781	#undef PGM_SHW_NAME_GC_STR
782	#undef PGM_SHW_NAME_R0_STR
783
784
785	/*
786	* Shadow - AMD64 mode
787	*/
788	#define PGM_SHW_TYPE PGM_TYPE_AMD64
789	#define PGM_SHW_NAME(name) PGM_SHW_NAME_AMD64(name)
790	#define PGM_SHW_NAME_GC_STR(name) PGM_SHW_NAME_GC_AMD64_STR(name)
791	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_AMD64_STR(name)
792	#include "PGMShw.h"
793
794	/* Guest - real mode */
795	#define PGM_GST_TYPE PGM_TYPE_REAL
796	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
797	#define PGM_GST_NAME_GC_STR(name) PGM_GST_NAME_GC_REAL_STR(name)
798	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
799	#define PGM_BTH_NAME(name) PGM_BTH_NAME_AMD64_REAL(name)
800	#define PGM_BTH_NAME_GC_STR(name) PGM_BTH_NAME_GC_AMD64_REAL_STR(name)
801	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_AMD64_REAL_STR(name)
802	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
803	#include "PGMBth.h"
804	#undef BTH_PGMPOOLKIND_PT_FOR_PT
805	#undef PGM_BTH_NAME
806	#undef PGM_BTH_NAME_GC_STR
807	#undef PGM_BTH_NAME_R0_STR
808	#undef PGM_GST_TYPE
809	#undef PGM_GST_NAME
810	#undef PGM_GST_NAME_GC_STR
811	#undef PGM_GST_NAME_R0_STR
812
813	/* Guest - protected mode */
814	#define PGM_GST_TYPE PGM_TYPE_PROT
815	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
816	#define PGM_GST_NAME_GC_STR(name) PGM_GST_NAME_GC_PROT_STR(name)
817	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
818	#define PGM_BTH_NAME(name) PGM_BTH_NAME_AMD64_PROT(name)
819	#define PGM_BTH_NAME_GC_STR(name) PGM_BTH_NAME_GC_AMD64_PROT_STR(name)
820	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_AMD64_PROT_STR(name)
821	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
822	#include "PGMBth.h"
823	#undef BTH_PGMPOOLKIND_PT_FOR_PT
824	#undef PGM_BTH_NAME
825	#undef PGM_BTH_NAME_GC_STR
826	#undef PGM_BTH_NAME_R0_STR
827	#undef PGM_GST_TYPE
828	#undef PGM_GST_NAME
829	#undef PGM_GST_NAME_GC_STR
830	#undef PGM_GST_NAME_R0_STR
831
832	/* Guest - AMD64 mode */
833	#define PGM_GST_TYPE PGM_TYPE_AMD64
834	#define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
835	#define PGM_GST_NAME_GC_STR(name) PGM_GST_NAME_GC_AMD64_STR(name)
836	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_AMD64_STR(name)
837	#define PGM_BTH_NAME(name) PGM_BTH_NAME_AMD64_AMD64(name)
838	#define PGM_BTH_NAME_GC_STR(name) PGM_BTH_NAME_GC_AMD64_AMD64_STR(name)
839	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_AMD64_AMD64_STR(name)
840	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
841	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
842	#include "PGMGst.h"
843	#include "PGMBth.h"
844	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
845	#undef BTH_PGMPOOLKIND_PT_FOR_PT
846	#undef PGM_BTH_NAME
847	#undef PGM_BTH_NAME_GC_STR
848	#undef PGM_BTH_NAME_R0_STR
849	#undef PGM_GST_TYPE
850	#undef PGM_GST_NAME
851	#undef PGM_GST_NAME_GC_STR
852	#undef PGM_GST_NAME_R0_STR
853
854	#undef PGM_SHW_TYPE
855	#undef PGM_SHW_NAME
856	#undef PGM_SHW_NAME_GC_STR
857	#undef PGM_SHW_NAME_R0_STR
858
859
860	/**
861	* Initiates the paging of VM.
862	*
863	* @returns VBox status code.
864	* @param pVM Pointer to VM structure.
865	*/
866	PGMR3DECL(int) PGMR3Init(PVM pVM)
867	{
868	LogFlow(("PGMR3Init:\n"));
869
870	/*
871	* Assert alignment and sizes.
872	*/
873	AssertRelease(sizeof(pVM->pgm.s) <= sizeof(pVM->pgm.padding));
874
875	/*
876	* Init the structure.
877	*/
878	pVM->pgm.s.offVM = RT_OFFSETOF(VM, pgm.s);
879	pVM->pgm.s.enmShadowMode = PGMMODE_INVALID;
880	pVM->pgm.s.enmGuestMode = PGMMODE_INVALID;
881	pVM->pgm.s.enmHostMode = SUPPAGINGMODE_INVALID;
882	pVM->pgm.s.GCPhysCR3 = NIL_RTGCPHYS;
883	pVM->pgm.s.GCPhysGstCR3Monitored = NIL_RTGCPHYS;
884	pVM->pgm.s.fA20Enabled = true;
885	pVM->pgm.s.pGstPaePDPTRHC = NULL;
886	pVM->pgm.s.pGstPaePDPTRGC = 0;
887	for (unsigned i = 0; i < ELEMENTS(pVM->pgm.s.apGstPaePDsHC); i++)
888	{
889	pVM->pgm.s.apGstPaePDsHC[i] = NULL;
890	pVM->pgm.s.apGstPaePDsGC[i] = 0;
891	pVM->pgm.s.aGCPhysGstPaePDs[i] = NIL_RTGCPHYS;
892	}
893
894	#ifdef VBOX_STRICT
895	VMR3AtStateRegister(pVM, pgmR3ResetNoMorePhysWritesFlag, NULL);
896	#endif
897
898	/*
899	* Get the configured RAM size - to estimate saved state size.
900	*/
901	uint64_t cbRam;
902	int rc = CFGMR3QueryU64(CFGMR3GetRoot(pVM), "RamSize", &cbRam);
903	if (rc == VERR_CFGM_VALUE_NOT_FOUND)
904	cbRam = pVM->pgm.s.cbRamSize = 0;
905	else if (VBOX_SUCCESS(rc))
906	{
907	if (cbRam < PAGE_SIZE)
908	cbRam = 0;
909	cbRam = RT_ALIGN_64(cbRam, PAGE_SIZE);
910	pVM->pgm.s.cbRamSize = (RTUINT)cbRam;
911	}
912	else
913	{
914	AssertMsgFailed(("Configuration error: Failed to query integer \"RamSize\", rc=%Vrc.\n", rc));
915	return rc;
916	}
917
918	/*
919	* Register saved state data unit.
920	*/
921	rc = SSMR3RegisterInternal(pVM, "pgm", 1, PGM_SAVED_STATE_VERSION, (size_t)cbRam + sizeof(PGM),
922	NULL, pgmR3Save, NULL,
923	NULL, pgmR3Load, NULL);
924	if (VBOX_FAILURE(rc))
925	return rc;
926
927	/*
928	* Initialize the PGM critical section and flush the phys TLBs
929	*/
930	rc = PDMR3CritSectInit(pVM, &pVM->pgm.s.CritSect, "PGM");
931	AssertRCReturn(rc, rc);
932
933	PGMR3PhysChunkInvalidateTLB(pVM);
934	PGMPhysInvalidatePageR3MapTLB(pVM);
935	PGMPhysInvalidatePageR0MapTLB(pVM);
936	PGMPhysInvalidatePageGCMapTLB(pVM);
937
938	/*
939	* Trees
940	*/
941	rc = MMHyperAlloc(pVM, sizeof(PGMTREES), 0, MM_TAG_PGM, (void **)&pVM->pgm.s.pTreesHC);
942	if (VBOX_SUCCESS(rc))
943	{
944	pVM->pgm.s.pTreesGC = MMHyperHC2GC(pVM, pVM->pgm.s.pTreesHC);
945
946	/*
947	* Alocate the zero page.
948	*/
949	rc = MMHyperAlloc(pVM, PAGE_SIZE, PAGE_SIZE, MM_TAG_PGM, &pVM->pgm.s.pvZeroPgR3);
950	}
951	if (VBOX_SUCCESS(rc))
952	{
953	pVM->pgm.s.pvZeroPgGC = MMHyperR3ToGC(pVM, pVM->pgm.s.pvZeroPgR3);
954	pVM->pgm.s.pvZeroPgR0 = MMHyperR3ToR0(pVM, pVM->pgm.s.pvZeroPgR3);
955	AssertRelease(pVM->pgm.s.pvZeroPgR0 != NIL_RTHCPHYS);
956	pVM->pgm.s.HCPhysZeroPg = MMR3HyperHCVirt2HCPhys(pVM, pVM->pgm.s.pvZeroPgR3);
957	AssertRelease(pVM->pgm.s.HCPhysZeroPg != NIL_RTHCPHYS);
958
959	/*
960	* Init the paging.
961	*/
962	rc = pgmR3InitPaging(pVM);
963	}
964	if (VBOX_SUCCESS(rc))
965	{
966	/*
967	* Init the page pool.
968	*/
969	rc = pgmR3PoolInit(pVM);
970	}
971	if (VBOX_SUCCESS(rc))
972	{
973	/*
974	* Info & statistics
975	*/
976	DBGFR3InfoRegisterInternal(pVM, "mode",
977	"Shows the current paging mode. "
978	"Recognizes 'all', 'guest', 'shadow' and 'host' as arguments, defaulting to 'all' if nothing's given.",
979	pgmR3InfoMode);
980	DBGFR3InfoRegisterInternal(pVM, "pgmcr3",
981	"Dumps all the entries in the top level paging table. No arguments.",
982	pgmR3InfoCr3);
983	DBGFR3InfoRegisterInternal(pVM, "phys",
984	"Dumps all the physical address ranges. No arguments.",
985	pgmR3PhysInfo);
986	DBGFR3InfoRegisterInternal(pVM, "handlers",
987	"Dumps physical and virtual handlers. "
988	"Pass 'phys' or 'virt' as argument if only one kind is wanted.",
989	pgmR3InfoHandlers);
990
991	STAM_REL_REG(pVM, &pVM->pgm.s.cGuestModeChanges, STAMTYPE_COUNTER, "/PGM/cGuestModeChanges", STAMUNIT_OCCURENCES, "Number of guest mode changes.");
992	#ifdef VBOX_WITH_STATISTICS
993	pgmR3InitStats(pVM);
994	#endif
995	#ifdef VBOX_WITH_DEBUGGER
996	/*
997	* Debugger commands.
998	*/
999	static bool fRegisteredCmds = false;
1000	if (!fRegisteredCmds)
1001	{
1002	int rc = DBGCRegisterCommands(&g_aCmds[0], ELEMENTS(g_aCmds));
1003	if (VBOX_SUCCESS(rc))
1004	fRegisteredCmds = true;
1005	}
1006	#endif
1007	return VINF_SUCCESS;
1008	}
1009
1010	/* Almost no cleanup necessary, MM frees all memory. */
1011	PDMR3CritSectDelete(&pVM->pgm.s.CritSect);
1012
1013	return rc;
1014	}
1015
1016
1017	/**
1018	* Init paging.
1019	*
1020	* Since we need to check what mode the host is operating in before we can choose
1021	* the right paging functions for the host we have to delay this until R0 has
1022	* been initialized.
1023	*
1024	* @returns VBox status code.
1025	* @param pVM VM handle.
1026	*/
1027	static int pgmR3InitPaging(PVM pVM)
1028	{
1029	/*
1030	* Force a recalculation of modes and switcher so everyone gets notified.
1031	*/
1032	pVM->pgm.s.enmShadowMode = PGMMODE_INVALID;
1033	pVM->pgm.s.enmGuestMode = PGMMODE_INVALID;
1034	pVM->pgm.s.enmHostMode = SUPPAGINGMODE_INVALID;
1035
1036	/*
1037	* Allocate static mapping space for whatever the cr3 register
1038	* points to and in the case of PAE mode to the 4 PDs.
1039	*/
1040	int rc = MMR3HyperReserve(pVM, PAGE_SIZE * 5, "CR3 mapping", &pVM->pgm.s.GCPtrCR3Mapping);
1041	if (VBOX_FAILURE(rc))
1042	{
1043	AssertMsgFailed(("Failed to reserve two pages for cr mapping in HMA, rc=%Vrc\n", rc));
1044	return rc;
1045	}
1046	MMR3HyperReserve(pVM, PAGE_SIZE, "fence", NULL);
1047
1048	/*
1049	* Allocate pages for the three possible intermediate contexts
1050	* (AMD64, PAE and plain 32-Bit). We maintain all three contexts
1051	* for the sake of simplicity. The AMD64 uses the PAE for the
1052	* lower levels, making the total number of pages 11 (3 + 7 + 1).
1053	*
1054	* We assume that two page tables will be enought for the core code
1055	* mappings (HC virtual and identity).
1056	*/
1057	pVM->pgm.s.pInterPD = (PX86PD)MMR3PageAllocLow(pVM);
1058	pVM->pgm.s.apInterPTs[0] = (PX86PT)MMR3PageAllocLow(pVM);
1059	pVM->pgm.s.apInterPTs[1] = (PX86PT)MMR3PageAllocLow(pVM);
1060	pVM->pgm.s.apInterPaePTs[0] = (PX86PTPAE)MMR3PageAlloc(pVM);
1061	pVM->pgm.s.apInterPaePTs[1] = (PX86PTPAE)MMR3PageAlloc(pVM);
1062	pVM->pgm.s.apInterPaePDs[0] = (PX86PDPAE)MMR3PageAlloc(pVM);
1063	pVM->pgm.s.apInterPaePDs[1] = (PX86PDPAE)MMR3PageAlloc(pVM);
1064	pVM->pgm.s.apInterPaePDs[2] = (PX86PDPAE)MMR3PageAlloc(pVM);
1065	pVM->pgm.s.apInterPaePDs[3] = (PX86PDPAE)MMR3PageAlloc(pVM);
1066	pVM->pgm.s.pInterPaePDPTR = (PX86PDPTR)MMR3PageAllocLow(pVM);
1067	pVM->pgm.s.pInterPaePDPTR64 = (PX86PDPTR)MMR3PageAllocLow(pVM);
1068	pVM->pgm.s.pInterPaePML4 = (PX86PML4)MMR3PageAllocLow(pVM);
1069	if ( !pVM->pgm.s.pInterPD
1070	\|\| !pVM->pgm.s.apInterPTs[0]
1071	\|\| !pVM->pgm.s.apInterPTs[1]
1072	\|\| !pVM->pgm.s.apInterPaePTs[0]
1073	\|\| !pVM->pgm.s.apInterPaePTs[1]
1074	\|\| !pVM->pgm.s.apInterPaePDs[0]
1075	\|\| !pVM->pgm.s.apInterPaePDs[1]
1076	\|\| !pVM->pgm.s.apInterPaePDs[2]
1077	\|\| !pVM->pgm.s.apInterPaePDs[3]
1078	\|\| !pVM->pgm.s.pInterPaePDPTR
1079	\|\| !pVM->pgm.s.pInterPaePDPTR64
1080	\|\| !pVM->pgm.s.pInterPaePML4)
1081	{
1082	AssertMsgFailed(("Failed to allocate pages for the intermediate context!\n"));
1083	return VERR_NO_PAGE_MEMORY;
1084	}
1085
1086	pVM->pgm.s.HCPhysInterPD = MMPage2Phys(pVM, pVM->pgm.s.pInterPD);
1087	AssertRelease(pVM->pgm.s.HCPhysInterPD != NIL_RTHCPHYS && !(pVM->pgm.s.HCPhysInterPD & PAGE_OFFSET_MASK));
1088	pVM->pgm.s.HCPhysInterPaePDPTR = MMPage2Phys(pVM, pVM->pgm.s.pInterPaePDPTR);
1089	AssertRelease(pVM->pgm.s.HCPhysInterPaePDPTR != NIL_RTHCPHYS && !(pVM->pgm.s.HCPhysInterPaePDPTR & PAGE_OFFSET_MASK));
1090	pVM->pgm.s.HCPhysInterPaePML4 = MMPage2Phys(pVM, pVM->pgm.s.pInterPaePML4);
1091	AssertRelease(pVM->pgm.s.HCPhysInterPaePML4 != NIL_RTHCPHYS && !(pVM->pgm.s.HCPhysInterPaePML4 & PAGE_OFFSET_MASK));
1092
1093	/*
1094	* Initialize the pages, setting up the PML4 and PDPTR for repetitive 4GB action.
1095	*/
1096	ASMMemZeroPage(pVM->pgm.s.pInterPD);
1097	ASMMemZeroPage(pVM->pgm.s.apInterPTs[0]);
1098	ASMMemZeroPage(pVM->pgm.s.apInterPTs[1]);
1099
1100	ASMMemZeroPage(pVM->pgm.s.apInterPaePTs[0]);
1101	ASMMemZeroPage(pVM->pgm.s.apInterPaePTs[1]);
1102
1103	ASMMemZeroPage(pVM->pgm.s.pInterPaePDPTR);
1104	for (unsigned i = 0; i < ELEMENTS(pVM->pgm.s.apInterPaePDs); i++)
1105	{
1106	ASMMemZeroPage(pVM->pgm.s.apInterPaePDs[i]);
1107	pVM->pgm.s.pInterPaePDPTR->a[i].u = X86_PDPE_P \| PGM_PLXFLAGS_PERMANENT
1108	\| MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[i]);
1109	}
1110
1111	for (unsigned i = 0; i < ELEMENTS(pVM->pgm.s.pInterPaePDPTR64->a); i++)
1112	{
1113	const unsigned iPD = i % ELEMENTS(pVM->pgm.s.apInterPaePDs);
1114	pVM->pgm.s.pInterPaePDPTR64->a[i].u = X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_A \| PGM_PLXFLAGS_PERMANENT
1115	\| MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[iPD]);
1116	}
1117
1118	RTHCPHYS HCPhysInterPaePDPTR64 = MMPage2Phys(pVM, pVM->pgm.s.pInterPaePDPTR64);
1119	for (unsigned i = 0; i < ELEMENTS(pVM->pgm.s.pInterPaePML4->a); i++)
1120	pVM->pgm.s.pInterPaePML4->a[i].u = X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_A \| PGM_PLXFLAGS_PERMANENT
1121	\| HCPhysInterPaePDPTR64;
1122
1123	/*
1124	* Allocate pages for the three possible guest contexts (AMD64, PAE and plain 32-Bit).
1125	* We allocate pages for all three posibilities to in order to simplify mappings and
1126	* avoid resource failure during mode switches. So, we need to cover all levels of the
1127	* of the first 4GB down to PD level.
1128	* As with the intermediate context, AMD64 uses the PAE PDPTR and PDs.
1129	*/
1130	pVM->pgm.s.pHC32BitPD = (PX86PD)MMR3PageAllocLow(pVM);
1131	pVM->pgm.s.apHCPaePDs[0] = (PX86PDPAE)MMR3PageAlloc(pVM);
1132	pVM->pgm.s.apHCPaePDs[1] = (PX86PDPAE)MMR3PageAlloc(pVM);
1133	AssertRelease((uintptr_t)pVM->pgm.s.apHCPaePDs[0] + PAGE_SIZE == (uintptr_t)pVM->pgm.s.apHCPaePDs[1]);
1134	pVM->pgm.s.apHCPaePDs[2] = (PX86PDPAE)MMR3PageAlloc(pVM);
1135	AssertRelease((uintptr_t)pVM->pgm.s.apHCPaePDs[1] + PAGE_SIZE == (uintptr_t)pVM->pgm.s.apHCPaePDs[2]);
1136	pVM->pgm.s.apHCPaePDs[3] = (PX86PDPAE)MMR3PageAlloc(pVM);
1137	AssertRelease((uintptr_t)pVM->pgm.s.apHCPaePDs[2] + PAGE_SIZE == (uintptr_t)pVM->pgm.s.apHCPaePDs[3]);
1138	pVM->pgm.s.pHCPaePDPTR = (PX86PDPTR)MMR3PageAllocLow(pVM);
1139	pVM->pgm.s.pHCPaePML4 = (PX86PML4)MMR3PageAllocLow(pVM);
1140	if ( !pVM->pgm.s.pHC32BitPD
1141	\|\| !pVM->pgm.s.apHCPaePDs[0]
1142	\|\| !pVM->pgm.s.apHCPaePDs[1]
1143	\|\| !pVM->pgm.s.apHCPaePDs[2]
1144	\|\| !pVM->pgm.s.apHCPaePDs[3]
1145	\|\| !pVM->pgm.s.pHCPaePDPTR
1146	\|\| !pVM->pgm.s.pHCPaePML4)
1147	{
1148	AssertMsgFailed(("Failed to allocate pages for the intermediate context!\n"));
1149	return VERR_NO_PAGE_MEMORY;
1150	}
1151
1152	/* get physical addresses. */
1153	pVM->pgm.s.HCPhys32BitPD = MMPage2Phys(pVM, pVM->pgm.s.pHC32BitPD);
1154	Assert(MMPagePhys2Page(pVM, pVM->pgm.s.HCPhys32BitPD) == pVM->pgm.s.pHC32BitPD);
1155	pVM->pgm.s.aHCPhysPaePDs[0] = MMPage2Phys(pVM, pVM->pgm.s.apHCPaePDs[0]);
1156	pVM->pgm.s.aHCPhysPaePDs[1] = MMPage2Phys(pVM, pVM->pgm.s.apHCPaePDs[1]);
1157	pVM->pgm.s.aHCPhysPaePDs[2] = MMPage2Phys(pVM, pVM->pgm.s.apHCPaePDs[2]);
1158	pVM->pgm.s.aHCPhysPaePDs[3] = MMPage2Phys(pVM, pVM->pgm.s.apHCPaePDs[3]);
1159	pVM->pgm.s.HCPhysPaePDPTR = MMPage2Phys(pVM, pVM->pgm.s.pHCPaePDPTR);
1160	pVM->pgm.s.HCPhysPaePML4 = MMPage2Phys(pVM, pVM->pgm.s.pHCPaePML4);
1161
1162	/*
1163	* Initialize the pages, setting up the PML4 and PDPTR for action below 4GB.
1164	*/
1165	ASMMemZero32(pVM->pgm.s.pHC32BitPD, PAGE_SIZE);
1166
1167	ASMMemZero32(pVM->pgm.s.pHCPaePDPTR, PAGE_SIZE);
1168	for (unsigned i = 0; i < ELEMENTS(pVM->pgm.s.apHCPaePDs); i++)
1169	{
1170	ASMMemZero32(pVM->pgm.s.apHCPaePDs[i], PAGE_SIZE);
1171	pVM->pgm.s.pHCPaePDPTR->a[i].u = X86_PDPE_P \| PGM_PLXFLAGS_PERMANENT \| pVM->pgm.s.aHCPhysPaePDs[i];
1172	/* The flags will be corrected when entering and leaving long mode. */
1173	}
1174
1175	ASMMemZero32(pVM->pgm.s.pHCPaePML4, PAGE_SIZE);
1176	pVM->pgm.s.pHCPaePML4->a[0].u = X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_A
1177	\| PGM_PLXFLAGS_PERMANENT \| pVM->pgm.s.HCPhysPaePDPTR;
1178
1179	CPUMSetHyperCR3(pVM, (uint32_t)pVM->pgm.s.HCPhys32BitPD);
1180
1181	/*
1182	* Initialize paging workers and mode from current host mode
1183	* and the guest running in real mode.
1184	*/
1185	pVM->pgm.s.enmHostMode = SUPGetPagingMode();
1186	switch (pVM->pgm.s.enmHostMode)
1187	{
1188	case SUPPAGINGMODE_32_BIT:
1189	case SUPPAGINGMODE_32_BIT_GLOBAL:
1190	case SUPPAGINGMODE_PAE:
1191	case SUPPAGINGMODE_PAE_GLOBAL:
1192	case SUPPAGINGMODE_PAE_NX:
1193	case SUPPAGINGMODE_PAE_GLOBAL_NX:
1194	break;
1195
1196	case SUPPAGINGMODE_AMD64:
1197	case SUPPAGINGMODE_AMD64_GLOBAL:
1198	case SUPPAGINGMODE_AMD64_NX:
1199	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
1200	#ifndef VBOX_WITH_HYBIRD_32BIT_KERNEL
1201	if (ARCH_BITS != 64)
1202	{
1203	AssertMsgFailed(("Host mode %d (64-bit) is not supported by non-64bit builds\n", pVM->pgm.s.enmHostMode));
1204	LogRel(("Host mode %d (64-bit) is not supported by non-64bit builds\n", pVM->pgm.s.enmHostMode));
1205	return VERR_PGM_UNSUPPORTED_HOST_PAGING_MODE;
1206	}
1207	#endif
1208	break;
1209	default:
1210	AssertMsgFailed(("Host mode %d is not supported\n", pVM->pgm.s.enmHostMode));
1211	return VERR_PGM_UNSUPPORTED_HOST_PAGING_MODE;
1212	}
1213	rc = pgmR3ModeDataInit(pVM, false /* don't resolve GC and R0 syms yet */);
1214	if (VBOX_SUCCESS(rc))
1215	rc = pgmR3ChangeMode(pVM, PGMMODE_REAL);
1216	if (VBOX_SUCCESS(rc))
1217	{
1218	LogFlow(("pgmR3InitPaging: returns successfully\n"));
1219	#if HC_ARCH_BITS == 64
1220	LogRel(("Debug: HCPhys32BitPD=%VHp aHCPhysPaePDs={%VHp,%VHp,%VHp,%VHp} HCPhysPaePDPTR=%VHp HCPhysPaePML4=%VHp\n",
1221	pVM->pgm.s.HCPhys32BitPD, pVM->pgm.s.aHCPhysPaePDs[0], pVM->pgm.s.aHCPhysPaePDs[1], pVM->pgm.s.aHCPhysPaePDs[2], pVM->pgm.s.aHCPhysPaePDs[3],
1222	pVM->pgm.s.HCPhysPaePDPTR, pVM->pgm.s.HCPhysPaePML4));
1223	LogRel(("Debug: HCPhysInterPD=%VHp HCPhysInterPaePDPTR=%VHp HCPhysInterPaePML4=%VHp\n",
1224	pVM->pgm.s.HCPhysInterPD, pVM->pgm.s.HCPhysInterPaePDPTR, pVM->pgm.s.HCPhysInterPaePML4));
1225	LogRel(("Debug: apInterPTs={%VHp,%VHp} apInterPaePTs={%VHp,%VHp} apInterPaePDs={%VHp,%VHp,%VHp,%VHp} pInterPaePDPTR64=%VHp\n",
1226	MMPage2Phys(pVM, pVM->pgm.s.apInterPTs[0]), MMPage2Phys(pVM, pVM->pgm.s.apInterPTs[1]),
1227	MMPage2Phys(pVM, pVM->pgm.s.apInterPaePTs[0]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePTs[1]),
1228	MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[0]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[1]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[2]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[3]),
1229	MMPage2Phys(pVM, pVM->pgm.s.pInterPaePDPTR64)));
1230	#endif
1231
1232	return VINF_SUCCESS;
1233	}
1234
1235	LogFlow(("pgmR3InitPaging: returns %Vrc\n", rc));
1236	return rc;
1237	}
1238
1239
1240	#ifdef VBOX_WITH_STATISTICS
1241	/**
1242	* Init statistics
1243	*/
1244	static void pgmR3InitStats(PVM pVM)
1245	{
1246	PPGM pPGM = &pVM->pgm.s;
1247	STAM_REG(pVM, &pPGM->StatGCInvalidatePage, STAMTYPE_PROFILE, "/PGM/GC/InvalidatePage", STAMUNIT_TICKS_PER_CALL, "PGMGCInvalidatePage() profiling.");
1248	STAM_REG(pVM, &pPGM->StatGCInvalidatePage4KBPages, STAMTYPE_COUNTER, "/PGM/GC/InvalidatePage/4KBPages", STAMUNIT_OCCURENCES, "The number of times PGMGCInvalidatePage() was called for a 4KB page.");
1249	STAM_REG(pVM, &pPGM->StatGCInvalidatePage4MBPages, STAMTYPE_COUNTER, "/PGM/GC/InvalidatePage/4MBPages", STAMUNIT_OCCURENCES, "The number of times PGMGCInvalidatePage() was called for a 4MB page.");
1250	STAM_REG(pVM, &pPGM->StatGCInvalidatePage4MBPagesSkip, STAMTYPE_COUNTER, "/PGM/GC/InvalidatePage/4MBPagesSkip",STAMUNIT_OCCURENCES, "The number of times PGMGCInvalidatePage() skipped a 4MB page.");
1251	STAM_REG(pVM, &pPGM->StatGCInvalidatePagePDMappings, STAMTYPE_COUNTER, "/PGM/GC/InvalidatePage/PDMappings", STAMUNIT_OCCURENCES, "The number of times PGMGCInvalidatePage() was called for a page directory containing mappings (no conflict).");
1252	STAM_REG(pVM, &pPGM->StatGCInvalidatePagePDNAs, STAMTYPE_COUNTER, "/PGM/GC/InvalidatePage/PDNAs", STAMUNIT_OCCURENCES, "The number of times PGMGCInvalidatePage() was called for a not accessed page directory.");
1253	STAM_REG(pVM, &pPGM->StatGCInvalidatePagePDNPs, STAMTYPE_COUNTER, "/PGM/GC/InvalidatePage/PDNPs", STAMUNIT_OCCURENCES, "The number of times PGMGCInvalidatePage() was called for a not present page directory.");
1254	STAM_REG(pVM, &pPGM->StatGCInvalidatePagePDOutOfSync, STAMTYPE_COUNTER, "/PGM/GC/InvalidatePage/PDOutOfSync", STAMUNIT_OCCURENCES, "The number of times PGMGCInvalidatePage() was called for an out of sync page directory.");
1255	STAM_REG(pVM, &pPGM->StatGCInvalidatePageSkipped, STAMTYPE_COUNTER, "/PGM/GC/InvalidatePage/Skipped", STAMUNIT_OCCURENCES, "The number of times PGMGCInvalidatePage() was skipped due to not present shw or pending pending SyncCR3.");
1256	STAM_REG(pVM, &pPGM->StatGCSyncPT, STAMTYPE_PROFILE, "/PGM/GC/SyncPT", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMGCSyncPT() body.");
1257	STAM_REG(pVM, &pPGM->StatGCAccessedPage, STAMTYPE_COUNTER, "/PGM/GC/AccessedPage", STAMUNIT_OCCURENCES, "The number of pages marked not present for accessed bit emulation.");
1258	STAM_REG(pVM, &pPGM->StatGCDirtyPage, STAMTYPE_COUNTER, "/PGM/GC/DirtyPage/Mark", STAMUNIT_OCCURENCES, "The number of pages marked read-only for dirty bit tracking.");
1259	STAM_REG(pVM, &pPGM->StatGCDirtyPageBig, STAMTYPE_COUNTER, "/PGM/GC/DirtyPage/MarkBig", STAMUNIT_OCCURENCES, "The number of 4MB pages marked read-only for dirty bit tracking.");
1260	STAM_REG(pVM, &pPGM->StatGCDirtyPageTrap, STAMTYPE_COUNTER, "/PGM/GC/DirtyPage/Trap", STAMUNIT_OCCURENCES, "The number of traps generated for dirty bit tracking.");
1261	STAM_REG(pVM, &pPGM->StatGCDirtyPageSkipped, STAMTYPE_COUNTER, "/PGM/GC/DirtyPage/Skipped", STAMUNIT_OCCURENCES, "The number of pages already dirty or readonly.");
1262	STAM_REG(pVM, &pPGM->StatGCDirtiedPage, STAMTYPE_COUNTER, "/PGM/GC/DirtyPage/SetDirty", STAMUNIT_OCCURENCES, "The number of pages marked dirty because of write accesses.");
1263	STAM_REG(pVM, &pPGM->StatGCDirtyTrackRealPF, STAMTYPE_COUNTER, "/PGM/GC/DirtyPage/RealPF", STAMUNIT_OCCURENCES, "The number of real pages faults during dirty bit tracking.");
1264	STAM_REG(pVM, &pPGM->StatGCPageAlreadyDirty, STAMTYPE_COUNTER, "/PGM/GC/DirtyPage/AlreadySet", STAMUNIT_OCCURENCES, "The number of pages already marked dirty because of write accesses.");
1265	STAM_REG(pVM, &pPGM->StatGCDirtyBitTracking, STAMTYPE_PROFILE, "/PGM/GC/DirtyPage", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMTrackDirtyBit() body.");
1266	STAM_REG(pVM, &pPGM->StatGCSyncPTAlloc, STAMTYPE_COUNTER, "/PGM/GC/SyncPT/Alloc", STAMUNIT_OCCURENCES, "The number of times PGMGCSyncPT() needed to allocate page tables.");
1267	STAM_REG(pVM, &pPGM->StatGCSyncPTConflict, STAMTYPE_COUNTER, "/PGM/GC/SyncPT/Conflicts", STAMUNIT_OCCURENCES, "The number of times PGMGCSyncPT() detected conflicts.");
1268	STAM_REG(pVM, &pPGM->StatGCSyncPTFailed, STAMTYPE_COUNTER, "/PGM/GC/SyncPT/Failed", STAMUNIT_OCCURENCES, "The number of times PGMGCSyncPT() failed.");
1269
1270	STAM_REG(pVM, &pPGM->StatGCTrap0e, STAMTYPE_PROFILE, "/PGM/GC/Trap0e", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMGCTrap0eHandler() body.");
1271	STAM_REG(pVM, &pPGM->StatCheckPageFault, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time/CheckPageFault", STAMUNIT_TICKS_PER_CALL, "Profiling of checking for dirty/access emulation faults.");
1272	STAM_REG(pVM, &pPGM->StatLazySyncPT, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time/SyncPT", STAMUNIT_TICKS_PER_CALL, "Profiling of lazy page table syncing.");
1273	STAM_REG(pVM, &pPGM->StatMapping, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time/Mapping", STAMUNIT_TICKS_PER_CALL, "Profiling of checking virtual mappings.");
1274	STAM_REG(pVM, &pPGM->StatOutOfSync, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time/OutOfSync", STAMUNIT_TICKS_PER_CALL, "Profiling of out of sync page handling.");
1275	STAM_REG(pVM, &pPGM->StatHandlers, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time/Handlers", STAMUNIT_TICKS_PER_CALL, "Profiling of checking handlers.");
1276	STAM_REG(pVM, &pPGM->StatEIPHandlers, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time/EIPHandlers", STAMUNIT_TICKS_PER_CALL, "Profiling of checking eip handlers.");
1277	STAM_REG(pVM, &pPGM->StatTrap0eCSAM, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time2/CSAM", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is CSAM.");
1278	STAM_REG(pVM, &pPGM->StatTrap0eDirtyAndAccessedBits, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time2/DirtyAndAccessedBits", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is dirty and/or accessed bit emulation.");
1279	STAM_REG(pVM, &pPGM->StatTrap0eGuestTrap, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time2/GuestTrap", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is a guest trap.");
1280	STAM_REG(pVM, &pPGM->StatTrap0eHndPhys, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time2/HandlerPhysical", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is a physical handler.");
1281	STAM_REG(pVM, &pPGM->StatTrap0eHndVirt, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time2/HandlerVirtual",STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is a virtual handler.");
1282	STAM_REG(pVM, &pPGM->StatTrap0eHndUnhandled, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time2/HandlerUnhandled", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is access outside the monitored areas of a monitored page.");
1283	STAM_REG(pVM, &pPGM->StatTrap0eMisc, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time2/Misc", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is not known.");
1284	STAM_REG(pVM, &pPGM->StatTrap0eOutOfSync, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time2/OutOfSync", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is an out-of-sync page.");
1285	STAM_REG(pVM, &pPGM->StatTrap0eOutOfSyncHndPhys, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time2/OutOfSyncHndPhys", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is an out-of-sync physical handler page.");
1286	STAM_REG(pVM, &pPGM->StatTrap0eOutOfSyncHndVirt, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time2/OutOfSyncHndVirt", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is an out-of-sync virtual handler page.");
1287	STAM_REG(pVM, &pPGM->StatTrap0eOutOfSyncObsHnd, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time2/OutOfSyncObsHnd", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is an obsolete handler page.");
1288	STAM_REG(pVM, &pPGM->StatTrap0eSyncPT, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time2/SyncPT", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is lazy syncing of a PT.");
1289
1290	STAM_REG(pVM, &pPGM->StatTrap0eMapHandler, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/Handlers/Mapping", STAMUNIT_OCCURENCES, "Number of traps due to access handlers in mappings.");
1291	STAM_REG(pVM, &pPGM->StatHandlersOutOfSync, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/Handlers/OutOfSync", STAMUNIT_OCCURENCES, "Number of traps due to out-of-sync handled pages.");
1292	STAM_REG(pVM, &pPGM->StatHandlersPhysical, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/Handlers/Physical", STAMUNIT_OCCURENCES, "Number of traps due to physical access handlers.");
1293	STAM_REG(pVM, &pPGM->StatHandlersVirtual, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/Handlers/Virtual", STAMUNIT_OCCURENCES, "Number of traps due to virtual access handlers.");
1294	STAM_REG(pVM, &pPGM->StatHandlersVirtualByPhys, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/Handlers/VirtualByPhys", STAMUNIT_OCCURENCES, "Number of traps due to virtual access handlers by physical address.");
1295	STAM_REG(pVM, &pPGM->StatHandlersVirtualUnmarked, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/Handlers/VirtualUnmarked", STAMUNIT_OCCURENCES,"Number of traps due to virtual access handlers by virtual address (without proper physical flags).");
1296	STAM_REG(pVM, &pPGM->StatHandlersUnhandled, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/Handlers/Unhandled", STAMUNIT_OCCURENCES, "Number of traps due to access outside range of monitored page(s).");
1297
1298	STAM_REG(pVM, &pPGM->StatGCTrap0eConflicts, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/Conflicts", STAMUNIT_OCCURENCES, "The number of times #PF was caused by an undetected conflict.");
1299	STAM_REG(pVM, &pPGM->StatGCTrap0eUSNotPresentRead, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/User/NPRead", STAMUNIT_OCCURENCES, "Number of user mode not present read page faults.");
1300	STAM_REG(pVM, &pPGM->StatGCTrap0eUSNotPresentWrite, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/User/NPWrite", STAMUNIT_OCCURENCES, "Number of user mode not present write page faults.");
1301	STAM_REG(pVM, &pPGM->StatGCTrap0eUSWrite, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/User/Write", STAMUNIT_OCCURENCES, "Number of user mode write page faults.");
1302	STAM_REG(pVM, &pPGM->StatGCTrap0eUSReserved, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/User/Reserved", STAMUNIT_OCCURENCES, "Number of user mode reserved bit page faults.");
1303	STAM_REG(pVM, &pPGM->StatGCTrap0eUSRead, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/User/Read", STAMUNIT_OCCURENCES, "Number of user mode read page faults.");
1304
1305	STAM_REG(pVM, &pPGM->StatGCTrap0eSVNotPresentRead, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/Supervisor/NPRead", STAMUNIT_OCCURENCES, "Number of supervisor mode not present read page faults.");
1306	STAM_REG(pVM, &pPGM->StatGCTrap0eSVNotPresentWrite, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/Supervisor/NPWrite", STAMUNIT_OCCURENCES, "Number of supervisor mode not present write page faults.");
1307	STAM_REG(pVM, &pPGM->StatGCTrap0eSVWrite, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/Supervisor/Write", STAMUNIT_OCCURENCES, "Number of supervisor mode write page faults.");
1308	STAM_REG(pVM, &pPGM->StatGCTrap0eSVReserved, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/Supervisor/Reserved", STAMUNIT_OCCURENCES, "Number of supervisor mode reserved bit page faults.");
1309	STAM_REG(pVM, &pPGM->StatGCTrap0eUnhandled, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/GuestPF/Unhandled", STAMUNIT_OCCURENCES, "Number of guest real page faults.");
1310	STAM_REG(pVM, &pPGM->StatGCTrap0eMap, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/GuestPF/Map", STAMUNIT_OCCURENCES, "Number of guest page faults due to map accesses.");
1311
1312
1313	STAM_REG(pVM, &pPGM->StatGCGuestCR3WriteHandled, STAMTYPE_COUNTER, "/PGM/GC/CR3WriteInt", STAMUNIT_OCCURENCES, "The number of times the Guest CR3 change was successfully handled.");
1314	STAM_REG(pVM, &pPGM->StatGCGuestCR3WriteUnhandled, STAMTYPE_COUNTER, "/PGM/GC/CR3WriteEmu", STAMUNIT_OCCURENCES, "The number of times the Guest CR3 change was passed back to the recompiler.");
1315	STAM_REG(pVM, &pPGM->StatGCGuestCR3WriteConflict, STAMTYPE_COUNTER, "/PGM/GC/CR3WriteConflict", STAMUNIT_OCCURENCES, "The number of times the Guest CR3 monitoring detected a conflict.");
1316
1317	STAM_REG(pVM, &pPGM->StatGCPageOutOfSyncSupervisor, STAMTYPE_COUNTER, "/PGM/GC/OutOfSync/SuperVisor", STAMUNIT_OCCURENCES, "Number of traps due to pages out of sync.");
1318	STAM_REG(pVM, &pPGM->StatGCPageOutOfSyncUser, STAMTYPE_COUNTER, "/PGM/GC/OutOfSync/User", STAMUNIT_OCCURENCES, "Number of traps due to pages out of sync.");
1319
1320	STAM_REG(pVM, &pPGM->StatGCGuestROMWriteHandled, STAMTYPE_COUNTER, "/PGM/GC/ROMWriteInt", STAMUNIT_OCCURENCES, "The number of times the Guest ROM change was successfully handled.");
1321	STAM_REG(pVM, &pPGM->StatGCGuestROMWriteUnhandled, STAMTYPE_COUNTER, "/PGM/GC/ROMWriteEmu", STAMUNIT_OCCURENCES, "The number of times the Guest ROM change was passed back to the recompiler.");
1322
1323	STAM_REG(pVM, &pPGM->StatDynMapCacheHits, STAMTYPE_COUNTER, "/PGM/GC/DynMapCache/Hits" , STAMUNIT_OCCURENCES, "Number of dynamic page mapping cache hits.");
1324	STAM_REG(pVM, &pPGM->StatDynMapCacheMisses, STAMTYPE_COUNTER, "/PGM/GC/DynMapCache/Misses" , STAMUNIT_OCCURENCES, "Number of dynamic page mapping cache misses.");
1325
1326	STAM_REG(pVM, &pPGM->StatHCDetectedConflicts, STAMTYPE_COUNTER, "/PGM/HC/DetectedConflicts", STAMUNIT_OCCURENCES, "The number of times PGMR3CheckMappingConflicts() detected a conflict.");
1327	STAM_REG(pVM, &pPGM->StatHCGuestPDWrite, STAMTYPE_COUNTER, "/PGM/HC/PDWrite", STAMUNIT_OCCURENCES, "The total number of times pgmHCGuestPDWriteHandler() was called.");
1328	STAM_REG(pVM, &pPGM->StatHCGuestPDWriteConflict, STAMTYPE_COUNTER, "/PGM/HC/PDWriteConflict", STAMUNIT_OCCURENCES, "The number of times pgmHCGuestPDWriteHandler() detected a conflict.");
1329
1330	STAM_REG(pVM, &pPGM->StatHCInvalidatePage, STAMTYPE_PROFILE, "/PGM/HC/InvalidatePage", STAMUNIT_TICKS_PER_CALL, "PGMHCInvalidatePage() profiling.");
1331	STAM_REG(pVM, &pPGM->StatHCInvalidatePage4KBPages, STAMTYPE_COUNTER, "/PGM/HC/InvalidatePage/4KBPages", STAMUNIT_OCCURENCES, "The number of times PGMHCInvalidatePage() was called for a 4KB page.");
1332	STAM_REG(pVM, &pPGM->StatHCInvalidatePage4MBPages, STAMTYPE_COUNTER, "/PGM/HC/InvalidatePage/4MBPages", STAMUNIT_OCCURENCES, "The number of times PGMHCInvalidatePage() was called for a 4MB page.");
1333	STAM_REG(pVM, &pPGM->StatHCInvalidatePage4MBPagesSkip, STAMTYPE_COUNTER, "/PGM/HC/InvalidatePage/4MBPagesSkip",STAMUNIT_OCCURENCES, "The number of times PGMHCInvalidatePage() skipped a 4MB page.");
1334	STAM_REG(pVM, &pPGM->StatHCInvalidatePagePDMappings, STAMTYPE_COUNTER, "/PGM/HC/InvalidatePage/PDMappings", STAMUNIT_OCCURENCES, "The number of times PGMHCInvalidatePage() was called for a page directory containing mappings (no conflict).");
1335	STAM_REG(pVM, &pPGM->StatHCInvalidatePagePDNAs, STAMTYPE_COUNTER, "/PGM/HC/InvalidatePage/PDNAs", STAMUNIT_OCCURENCES, "The number of times PGMHCInvalidatePage() was called for a not accessed page directory.");
1336	STAM_REG(pVM, &pPGM->StatHCInvalidatePagePDNPs, STAMTYPE_COUNTER, "/PGM/HC/InvalidatePage/PDNPs", STAMUNIT_OCCURENCES, "The number of times PGMHCInvalidatePage() was called for a not present page directory.");
1337	STAM_REG(pVM, &pPGM->StatHCInvalidatePagePDOutOfSync, STAMTYPE_COUNTER, "/PGM/HC/InvalidatePage/PDOutOfSync", STAMUNIT_OCCURENCES, "The number of times PGMGCInvalidatePage() was called for an out of sync page directory.");
1338	STAM_REG(pVM, &pPGM->StatHCInvalidatePageSkipped, STAMTYPE_COUNTER, "/PGM/HC/InvalidatePage/Skipped", STAMUNIT_OCCURENCES, "The number of times PGMHCInvalidatePage() was skipped due to not present shw or pending pending SyncCR3.");
1339	STAM_REG(pVM, &pPGM->StatHCResolveConflict, STAMTYPE_PROFILE, "/PGM/HC/ResolveConflict", STAMUNIT_TICKS_PER_CALL, "pgmR3SyncPTResolveConflict() profiling (includes the entire relocation).");
1340	STAM_REG(pVM, &pPGM->StatHCPrefetch, STAMTYPE_PROFILE, "/PGM/HC/Prefetch", STAMUNIT_TICKS_PER_CALL, "PGMR3PrefetchPage profiling.");
1341
1342	STAM_REG(pVM, &pPGM->StatHCSyncPT, STAMTYPE_PROFILE, "/PGM/HC/SyncPT", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMR3SyncPT() body.");
1343	STAM_REG(pVM, &pPGM->StatHCAccessedPage, STAMTYPE_COUNTER, "/PGM/HC/AccessedPage", STAMUNIT_OCCURENCES, "The number of pages marked not present for accessed bit emulation.");
1344	STAM_REG(pVM, &pPGM->StatHCDirtyPage, STAMTYPE_COUNTER, "/PGM/HC/DirtyPage/Mark", STAMUNIT_OCCURENCES, "The number of pages marked read-only for dirty bit tracking.");
1345	STAM_REG(pVM, &pPGM->StatHCDirtyPageBig, STAMTYPE_COUNTER, "/PGM/HC/DirtyPage/MarkBig", STAMUNIT_OCCURENCES, "The number of 4MB pages marked read-only for dirty bit tracking.");
1346	STAM_REG(pVM, &pPGM->StatHCDirtyPageTrap, STAMTYPE_COUNTER, "/PGM/HC/DirtyPage/Trap", STAMUNIT_OCCURENCES, "The number of traps generated for dirty bit tracking.");
1347	STAM_REG(pVM, &pPGM->StatHCDirtyPageSkipped, STAMTYPE_COUNTER, "/PGM/HC/DirtyPage/Skipped", STAMUNIT_OCCURENCES, "The number of pages already dirty or readonly.");
1348	STAM_REG(pVM, &pPGM->StatHCDirtyBitTracking, STAMTYPE_PROFILE, "/PGM/HC/DirtyPage", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMTrackDirtyBit() body.");
1349
1350	STAM_REG(pVM, &pPGM->StatGCSyncPagePDNAs, STAMTYPE_COUNTER, "/PGM/GC/SyncPagePDNAs", STAMUNIT_OCCURENCES, "The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit.");
1351	STAM_REG(pVM, &pPGM->StatGCSyncPagePDOutOfSync, STAMTYPE_COUNTER, "/PGM/GC/SyncPagePDOutOfSync", STAMUNIT_OCCURENCES, "The number of time we've encountered an out-of-sync PD in SyncPage.");
1352	STAM_REG(pVM, &pPGM->StatHCSyncPagePDNAs, STAMTYPE_COUNTER, "/PGM/HC/SyncPagePDNAs", STAMUNIT_OCCURENCES, "The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit.");
1353	STAM_REG(pVM, &pPGM->StatHCSyncPagePDOutOfSync, STAMTYPE_COUNTER, "/PGM/HC/SyncPagePDOutOfSync", STAMUNIT_OCCURENCES, "The number of time we've encountered an out-of-sync PD in SyncPage.");
1354
1355	STAM_REG(pVM, &pPGM->StatFlushTLB, STAMTYPE_PROFILE, "/PGM/FlushTLB", STAMUNIT_OCCURENCES, "Profiling of the PGMFlushTLB() body.");
1356	STAM_REG(pVM, &pPGM->StatFlushTLBNewCR3, STAMTYPE_COUNTER, "/PGM/FlushTLB/NewCR3", STAMUNIT_OCCURENCES, "The number of times PGMFlushTLB was called with a new CR3, non-global. (switch)");
1357	STAM_REG(pVM, &pPGM->StatFlushTLBNewCR3Global, STAMTYPE_COUNTER, "/PGM/FlushTLB/NewCR3Global", STAMUNIT_OCCURENCES, "The number of times PGMFlushTLB was called with a new CR3, global. (switch)");
1358	STAM_REG(pVM, &pPGM->StatFlushTLBSameCR3, STAMTYPE_COUNTER, "/PGM/FlushTLB/SameCR3", STAMUNIT_OCCURENCES, "The number of times PGMFlushTLB was called with the same CR3, non-global. (flush)");
1359	STAM_REG(pVM, &pPGM->StatFlushTLBSameCR3Global, STAMTYPE_COUNTER, "/PGM/FlushTLB/SameCR3Global", STAMUNIT_OCCURENCES, "The number of times PGMFlushTLB was called with the same CR3, global. (flush)");
1360
1361	STAM_REG(pVM, &pPGM->StatGCSyncCR3, STAMTYPE_PROFILE, "/PGM/GC/SyncCR3", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMSyncCR3() body.");
1362	STAM_REG(pVM, &pPGM->StatGCSyncCR3Handlers, STAMTYPE_PROFILE, "/PGM/GC/SyncCR3/Handlers", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMSyncCR3() update handler section.");
1363	STAM_REG(pVM, &pPGM->StatGCSyncCR3HandlerVirtualUpdate, STAMTYPE_PROFILE, "/PGM/GC/SyncCR3/Handlers/VirtualUpdate",STAMUNIT_TICKS_PER_CALL, "Profiling of the virtual handler updates.");
1364	STAM_REG(pVM, &pPGM->StatGCSyncCR3HandlerVirtualReset, STAMTYPE_PROFILE, "/PGM/GC/SyncCR3/Handlers/VirtualReset", STAMUNIT_TICKS_PER_CALL, "Profiling of the virtual handler resets.");
1365	STAM_REG(pVM, &pPGM->StatGCSyncCR3Global, STAMTYPE_COUNTER, "/PGM/GC/SyncCR3/Global", STAMUNIT_OCCURENCES, "The number of global CR3 syncs.");
1366	STAM_REG(pVM, &pPGM->StatGCSyncCR3NotGlobal, STAMTYPE_COUNTER, "/PGM/GC/SyncCR3/NotGlobal", STAMUNIT_OCCURENCES, "The number of non-global CR3 syncs.");
1367	STAM_REG(pVM, &pPGM->StatGCSyncCR3DstCacheHit, STAMTYPE_COUNTER, "/PGM/GC/SyncCR3/DstChacheHit", STAMUNIT_OCCURENCES, "The number of times we got some kind of a cache hit.");
1368	STAM_REG(pVM, &pPGM->StatGCSyncCR3DstFreed, STAMTYPE_COUNTER, "/PGM/GC/SyncCR3/DstFreed", STAMUNIT_OCCURENCES, "The number of times we've had to free a shadow entry.");
1369	STAM_REG(pVM, &pPGM->StatGCSyncCR3DstFreedSrcNP, STAMTYPE_COUNTER, "/PGM/GC/SyncCR3/DstFreedSrcNP", STAMUNIT_OCCURENCES, "The number of times we've had to free a shadow entry for which the source entry was not present.");
1370	STAM_REG(pVM, &pPGM->StatGCSyncCR3DstNotPresent, STAMTYPE_COUNTER, "/PGM/GC/SyncCR3/DstNotPresent", STAMUNIT_OCCURENCES, "The number of times we've encountered a not present shadow entry for a present guest entry.");
1371	STAM_REG(pVM, &pPGM->StatGCSyncCR3DstSkippedGlobalPD, STAMTYPE_COUNTER, "/PGM/GC/SyncCR3/DstSkippedGlobalPD", STAMUNIT_OCCURENCES, "The number of times a global page directory wasn't flushed.");
1372	STAM_REG(pVM, &pPGM->StatGCSyncCR3DstSkippedGlobalPT, STAMTYPE_COUNTER, "/PGM/GC/SyncCR3/DstSkippedGlobalPT", STAMUNIT_OCCURENCES, "The number of times a page table with only global entries wasn't flushed.");
1373
1374	STAM_REG(pVM, &pPGM->StatHCSyncCR3, STAMTYPE_PROFILE, "/PGM/HC/SyncCR3", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMSyncCR3() body.");
1375	STAM_REG(pVM, &pPGM->StatHCSyncCR3Handlers, STAMTYPE_PROFILE, "/PGM/HC/SyncCR3/Handlers", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMSyncCR3() update handler section.");
1376	STAM_REG(pVM, &pPGM->StatHCSyncCR3HandlerVirtualUpdate, STAMTYPE_PROFILE, "/PGM/HC/SyncCR3/Handlers/VirtualUpdate",STAMUNIT_TICKS_PER_CALL, "Profiling of the virtual handler updates.");
1377	STAM_REG(pVM, &pPGM->StatHCSyncCR3HandlerVirtualReset, STAMTYPE_PROFILE, "/PGM/HC/SyncCR3/Handlers/VirtualReset", STAMUNIT_TICKS_PER_CALL, "Profiling of the virtual handler resets.");
1378	STAM_REG(pVM, &pPGM->StatHCSyncCR3Global, STAMTYPE_COUNTER, "/PGM/HC/SyncCR3/Global", STAMUNIT_OCCURENCES, "The number of global CR3 syncs.");
1379	STAM_REG(pVM, &pPGM->StatHCSyncCR3NotGlobal, STAMTYPE_COUNTER, "/PGM/HC/SyncCR3/NotGlobal", STAMUNIT_OCCURENCES, "The number of non-global CR3 syncs.");
1380	STAM_REG(pVM, &pPGM->StatHCSyncCR3DstCacheHit, STAMTYPE_COUNTER, "/PGM/HC/SyncCR3/DstChacheHit", STAMUNIT_OCCURENCES, "The number of times we got some kind of a cache hit.");
1381	STAM_REG(pVM, &pPGM->StatHCSyncCR3DstFreed, STAMTYPE_COUNTER, "/PGM/HC/SyncCR3/DstFreed", STAMUNIT_OCCURENCES, "The number of times we've had to free a shadow entry.");
1382	STAM_REG(pVM, &pPGM->StatHCSyncCR3DstFreedSrcNP, STAMTYPE_COUNTER, "/PGM/HC/SyncCR3/DstFreedSrcNP", STAMUNIT_OCCURENCES, "The number of times we've had to free a shadow entry for which the source entry was not present.");
1383	STAM_REG(pVM, &pPGM->StatHCSyncCR3DstNotPresent, STAMTYPE_COUNTER, "/PGM/HC/SyncCR3/DstNotPresent", STAMUNIT_OCCURENCES, "The number of times we've encountered a not present shadow entry for a present guest entry.");
1384	STAM_REG(pVM, &pPGM->StatHCSyncCR3DstSkippedGlobalPD, STAMTYPE_COUNTER, "/PGM/HC/SyncCR3/DstSkippedGlobalPD", STAMUNIT_OCCURENCES, "The number of times a global page directory wasn't flushed.");
1385	STAM_REG(pVM, &pPGM->StatHCSyncCR3DstSkippedGlobalPT, STAMTYPE_COUNTER, "/PGM/HC/SyncCR3/DstSkippedGlobalPT", STAMUNIT_OCCURENCES, "The number of times a page table with only global entries wasn't flushed.");
1386
1387	STAM_REG(pVM, &pPGM->StatVirtHandleSearchByPhysGC, STAMTYPE_PROFILE, "/PGM/VirtHandler/SearchByPhys/GC", STAMUNIT_TICKS_PER_CALL, "Profiling of pgmHandlerVirtualFindByPhysAddr in GC.");
1388	STAM_REG(pVM, &pPGM->StatVirtHandleSearchByPhysHC, STAMTYPE_PROFILE, "/PGM/VirtHandler/SearchByPhys/HC", STAMUNIT_TICKS_PER_CALL, "Profiling of pgmHandlerVirtualFindByPhysAddr in HC.");
1389	STAM_REG(pVM, &pPGM->StatHandlePhysicalReset, STAMTYPE_COUNTER, "/PGM/HC/HandlerPhysicalReset", STAMUNIT_OCCURENCES, "The number of times PGMR3HandlerPhysicalReset is called.");
1390
1391	STAM_REG(pVM, &pPGM->StatHCGstModifyPage, STAMTYPE_PROFILE, "/PGM/HC/GstModifyPage", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMGstModifyPage() body.");
1392	STAM_REG(pVM, &pPGM->StatGCGstModifyPage, STAMTYPE_PROFILE, "/PGM/GC/GstModifyPage", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMGstModifyPage() body.");
1393
1394	STAM_REG(pVM, &pPGM->StatSynPT4kGC, STAMTYPE_COUNTER, "/PGM/GC/SyncPT/4k", STAMUNIT_OCCURENCES, "Nr of 4k PT syncs");
1395	STAM_REG(pVM, &pPGM->StatSynPT4kHC, STAMTYPE_COUNTER, "/PGM/HC/SyncPT/4k", STAMUNIT_OCCURENCES, "Nr of 4k PT syncs");
1396	STAM_REG(pVM, &pPGM->StatSynPT4MGC, STAMTYPE_COUNTER, "/PGM/GC/SyncPT/4M", STAMUNIT_OCCURENCES, "Nr of 4M PT syncs");
1397	STAM_REG(pVM, &pPGM->StatSynPT4MHC, STAMTYPE_COUNTER, "/PGM/HC/SyncPT/4M", STAMUNIT_OCCURENCES, "Nr of 4M PT syncs");
1398
1399	STAM_REG(pVM, &pPGM->StatDynRamTotal, STAMTYPE_COUNTER, "/PGM/RAM/TotalAlloc", STAMUNIT_MEGABYTES, "Allocated mbs of guest ram.");
1400	STAM_REG(pVM, &pPGM->StatDynRamGrow, STAMTYPE_COUNTER, "/PGM/RAM/Grow", STAMUNIT_OCCURENCES, "Nr of pgmr3PhysGrowRange calls.");
1401
1402	STAM_REG(pVM, &pPGM->StatPageHCMapTlbHits, STAMTYPE_COUNTER, "/PGM/PageHCMap/TlbHits", STAMUNIT_OCCURENCES, "TLB hits.");
1403	STAM_REG(pVM, &pPGM->StatPageHCMapTlbMisses, STAMTYPE_COUNTER, "/PGM/PageHCMap/TlbMisses", STAMUNIT_OCCURENCES, "TLB misses.");
1404	STAM_REG(pVM, &pPGM->ChunkR3Map.c, STAMTYPE_U32, "/PGM/ChunkR3Map/c", STAMUNIT_OCCURENCES, "Number of mapped chunks.");
1405	STAM_REG(pVM, &pPGM->ChunkR3Map.cMax, STAMTYPE_U32, "/PGM/ChunkR3Map/cMax", STAMUNIT_OCCURENCES, "Maximum number of mapped chunks.");
1406	STAM_REG(pVM, &pPGM->StatChunkR3MapTlbHits, STAMTYPE_COUNTER, "/PGM/ChunkR3Map/TlbHits", STAMUNIT_OCCURENCES, "TLB hits.");
1407	STAM_REG(pVM, &pPGM->StatChunkR3MapTlbMisses, STAMTYPE_COUNTER, "/PGM/ChunkR3Map/TlbMisses", STAMUNIT_OCCURENCES, "TLB misses.");
1408
1409	#ifdef PGMPOOL_WITH_GCPHYS_TRACKING
1410	STAM_REG(pVM, &pPGM->StatTrackVirgin, STAMTYPE_COUNTER, "/PGM/Track/Virgin", STAMUNIT_OCCURENCES, "The number of first time shadowings");
1411	STAM_REG(pVM, &pPGM->StatTrackAliased, STAMTYPE_COUNTER, "/PGM/Track/Aliased", STAMUNIT_OCCURENCES, "The number of times switching to cRef2, i.e. the page is being shadowed by two PTs.");
1412	STAM_REG(pVM, &pPGM->StatTrackAliasedMany, STAMTYPE_COUNTER, "/PGM/Track/AliasedMany", STAMUNIT_OCCURENCES, "The number of times we're tracking using cRef2.");
1413	STAM_REG(pVM, &pPGM->StatTrackAliasedLots, STAMTYPE_COUNTER, "/PGM/Track/AliasedLots", STAMUNIT_OCCURENCES, "The number of times we're hitting pages which has overflowed cRef2");
1414	STAM_REG(pVM, &pPGM->StatTrackOverflows, STAMTYPE_COUNTER, "/PGM/Track/Overflows", STAMUNIT_OCCURENCES, "The number of times the extent list grows to long.");
1415	STAM_REG(pVM, &pPGM->StatTrackDeref, STAMTYPE_PROFILE, "/PGM/Track/Deref", STAMUNIT_OCCURENCES, "Profiling of SyncPageWorkerTrackDeref (expensive).");
1416	#endif
1417
1418	for (unsigned i = 0; i < PAGE_ENTRIES; i++)
1419	{
1420	/** @todo r=bird: We need a STAMR3RegisterF()! */
1421	char szName[32];
1422
1423	RTStrPrintf(szName, sizeof(szName), "/PGM/GC/PD/Trap0e/%04X", i);
1424	int rc = STAMR3Register(pVM, &pPGM->StatGCTrap0ePD[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, szName, STAMUNIT_OCCURENCES, "The number of traps in page directory n.");
1425	AssertRC(rc);
1426
1427	RTStrPrintf(szName, sizeof(szName), "/PGM/GC/PD/SyncPt/%04X", i);
1428	rc = STAMR3Register(pVM, &pPGM->StatGCSyncPtPD[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, szName, STAMUNIT_OCCURENCES, "The number of syncs per PD n.");
1429	AssertRC(rc);
1430
1431	RTStrPrintf(szName, sizeof(szName), "/PGM/GC/PD/SyncPage/%04X", i);
1432	rc = STAMR3Register(pVM, &pPGM->StatGCSyncPagePD[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, szName, STAMUNIT_OCCURENCES, "The number of out of sync pages per page directory n.");
1433	AssertRC(rc);
1434	}
1435	}
1436	#endif /* VBOX_WITH_STATISTICS */
1437
1438	/**
1439	* Init the PGM bits that rely on VMMR0 and MM to be fully initialized.
1440	*
1441	* The dynamic mapping area will also be allocated and initialized at this
1442	* time. We could allocate it during PGMR3Init of course, but the mapping
1443	* wouldn't be allocated at that time preventing us from setting up the
1444	* page table entries with the dummy page.
1445	*
1446	* @returns VBox status code.
1447	* @param pVM VM handle.
1448	*/
1449	PGMR3DECL(int) PGMR3InitDynMap(PVM pVM)
1450	{
1451	/*
1452	* Reserve space for mapping the paging pages into guest context.
1453	*/
1454	int rc = MMR3HyperReserve(pVM, PAGE_SIZE * (2 + ELEMENTS(pVM->pgm.s.apHCPaePDs) + 1 + 2 + 2), "Paging", &pVM->pgm.s.pGC32BitPD);
1455	AssertRCReturn(rc, rc);
1456	MMR3HyperReserve(pVM, PAGE_SIZE, "fence", NULL);
1457
1458	/*
1459	* Reserve space for the dynamic mappings.
1460	*/
1461	/** @todo r=bird: Need to verify that the checks for crossing PTs are correct here. They seems to be assuming 4MB PTs.. */
1462	rc = MMR3HyperReserve(pVM, MM_HYPER_DYNAMIC_SIZE, "Dynamic mapping", &pVM->pgm.s.pbDynPageMapBaseGC);
1463	if ( VBOX_SUCCESS(rc)
1464	&& (pVM->pgm.s.pbDynPageMapBaseGC >> PGDIR_SHIFT) != ((pVM->pgm.s.pbDynPageMapBaseGC + MM_HYPER_DYNAMIC_SIZE - 1) >> PGDIR_SHIFT))
1465	rc = MMR3HyperReserve(pVM, MM_HYPER_DYNAMIC_SIZE, "Dynamic mapping not crossing", &pVM->pgm.s.pbDynPageMapBaseGC);
1466	if (VBOX_SUCCESS(rc))
1467	{
1468	AssertRelease((pVM->pgm.s.pbDynPageMapBaseGC >> PGDIR_SHIFT) == ((pVM->pgm.s.pbDynPageMapBaseGC + MM_HYPER_DYNAMIC_SIZE - 1) >> PGDIR_SHIFT));
1469	MMR3HyperReserve(pVM, PAGE_SIZE, "fence", NULL);
1470	}
1471	return rc;
1472	}
1473
1474
1475	/**
1476	* Ring-3 init finalizing.
1477	*
1478	* @returns VBox status code.
1479	* @param pVM The VM handle.
1480	*/
1481	PGMR3DECL(int) PGMR3InitFinalize(PVM pVM)
1482	{
1483	/*
1484	* Map the paging pages into the guest context.
1485	*/
1486	RTGCPTR GCPtr = pVM->pgm.s.pGC32BitPD;
1487	AssertReleaseReturn(GCPtr, VERR_INTERNAL_ERROR);
1488
1489	int rc = PGMMap(pVM, GCPtr, pVM->pgm.s.HCPhys32BitPD, PAGE_SIZE, 0);
1490	AssertRCReturn(rc, rc);
1491	pVM->pgm.s.pGC32BitPD = GCPtr;
1492	GCPtr += PAGE_SIZE;
1493	GCPtr += PAGE_SIZE; /* reserved page */
1494
1495	for (unsigned i = 0; i < ELEMENTS(pVM->pgm.s.apHCPaePDs); i++)
1496	{
1497	rc = PGMMap(pVM, GCPtr, pVM->pgm.s.aHCPhysPaePDs[i], PAGE_SIZE, 0);
1498	AssertRCReturn(rc, rc);
1499	pVM->pgm.s.apGCPaePDs[i] = GCPtr;
1500	GCPtr += PAGE_SIZE;
1501	}
1502	/* A bit of paranoia is justified. */
1503	AssertRelease((RTGCUINTPTR)pVM->pgm.s.apGCPaePDs[0] + PAGE_SIZE == (RTGCUINTPTR)pVM->pgm.s.apGCPaePDs[1]);
1504	AssertRelease((RTGCUINTPTR)pVM->pgm.s.apGCPaePDs[1] + PAGE_SIZE == (RTGCUINTPTR)pVM->pgm.s.apGCPaePDs[2]);
1505	AssertRelease((RTGCUINTPTR)pVM->pgm.s.apGCPaePDs[2] + PAGE_SIZE == (RTGCUINTPTR)pVM->pgm.s.apGCPaePDs[3]);
1506	GCPtr += PAGE_SIZE; /* reserved page */
1507
1508	rc = PGMMap(pVM, GCPtr, pVM->pgm.s.HCPhysPaePDPTR, PAGE_SIZE, 0);
1509	AssertRCReturn(rc, rc);
1510	pVM->pgm.s.pGCPaePDPTR = GCPtr;
1511	GCPtr += PAGE_SIZE;
1512	GCPtr += PAGE_SIZE; /* reserved page */
1513
1514	rc = PGMMap(pVM, GCPtr, pVM->pgm.s.HCPhysPaePML4, PAGE_SIZE, 0);
1515	AssertRCReturn(rc, rc);
1516	pVM->pgm.s.pGCPaePML4 = GCPtr;
1517	GCPtr += PAGE_SIZE;
1518	GCPtr += PAGE_SIZE; /* reserved page */
1519
1520
1521	/*
1522	* Reserve space for the dynamic mappings.
1523	* Initialize the dynamic mapping pages with dummy pages to simply the cache.
1524	*/
1525	/* get the pointer to the page table entries. */
1526	PPGMMAPPING pMapping = pgmGetMapping(pVM, pVM->pgm.s.pbDynPageMapBaseGC);
1527	AssertRelease(pMapping);
1528	const uintptr_t off = pVM->pgm.s.pbDynPageMapBaseGC - pMapping->GCPtr;
1529	const unsigned iPT = off >> X86_PD_SHIFT;
1530	const unsigned iPG = (off >> X86_PT_SHIFT) & X86_PT_MASK;
1531	pVM->pgm.s.paDynPageMap32BitPTEsGC = pMapping->aPTs[iPT].pPTGC + iPG * sizeof(pMapping->aPTs[0].pPTR3->a[0]);
1532	pVM->pgm.s.paDynPageMapPaePTEsGC = pMapping->aPTs[iPT].paPaePTsGC + iPG * sizeof(pMapping->aPTs[0].paPaePTsR3->a[0]);
1533
1534	/* init cache */
1535	RTHCPHYS HCPhysDummy = MMR3PageDummyHCPhys(pVM);
1536	for (unsigned i = 0; i < ELEMENTS(pVM->pgm.s.aHCPhysDynPageMapCache); i++)
1537	pVM->pgm.s.aHCPhysDynPageMapCache[i] = HCPhysDummy;
1538
1539	for (unsigned i = 0; i < MM_HYPER_DYNAMIC_SIZE; i += PAGE_SIZE)
1540	{
1541	rc = PGMMap(pVM, pVM->pgm.s.pbDynPageMapBaseGC + i, HCPhysDummy, PAGE_SIZE, 0);
1542	AssertRCReturn(rc, rc);
1543	}
1544
1545	return rc;
1546	}
1547
1548
1549	/**
1550	* Applies relocations to data and code managed by this
1551	* component. This function will be called at init and
1552	* whenever the VMM need to relocate it self inside the GC.
1553	*
1554	* @param pVM The VM.
1555	* @param offDelta Relocation delta relative to old location.
1556	*/
1557	PGMR3DECL(void) PGMR3Relocate(PVM pVM, RTGCINTPTR offDelta)
1558	{
1559	LogFlow(("PGMR3Relocate\n"));
1560
1561	/*
1562	* Paging stuff.
1563	*/
1564	pVM->pgm.s.GCPtrCR3Mapping += offDelta;
1565	/** @todo move this into shadow and guest specific relocation functions. */
1566	AssertMsg(pVM->pgm.s.pGC32BitPD, ("Init order, no relocation before paging is initialized!\n"));
1567	pVM->pgm.s.pGC32BitPD += offDelta;
1568	pVM->pgm.s.pGuestPDGC += offDelta;
1569	for (unsigned i = 0; i < ELEMENTS(pVM->pgm.s.apGCPaePDs); i++)
1570	pVM->pgm.s.apGCPaePDs[i] += offDelta;
1571	pVM->pgm.s.pGCPaePDPTR += offDelta;
1572	pVM->pgm.s.pGCPaePML4 += offDelta;
1573
1574	pgmR3ModeDataInit(pVM, true /* resolve GC/R0 symbols */);
1575	pgmR3ModeDataSwitch(pVM, pVM->pgm.s.enmShadowMode, pVM->pgm.s.enmGuestMode);
1576
1577	PGM_SHW_PFN(Relocate, pVM)(pVM, offDelta);
1578	PGM_GST_PFN(Relocate, pVM)(pVM, offDelta);
1579	PGM_BTH_PFN(Relocate, pVM)(pVM, offDelta);
1580
1581	/*
1582	* Trees.
1583	*/
1584	pVM->pgm.s.pTreesGC = MMHyperHC2GC(pVM, pVM->pgm.s.pTreesHC);
1585
1586	/*
1587	* Ram ranges.
1588	*/
1589	if (pVM->pgm.s.pRamRangesHC)
1590	{
1591	pVM->pgm.s.pRamRangesGC = MMHyperHC2GC(pVM, pVM->pgm.s.pRamRangesHC);
1592	for (PPGMRAMRANGE pCur = pVM->pgm.s.pRamRangesHC; pCur->pNextHC; pCur = pCur->pNextHC)
1593	{
1594	pCur->pNextGC = MMHyperHC2GC(pVM, pCur->pNextHC);
1595	if (pCur->pavHCChunkGC)
1596	pCur->pavHCChunkGC = MMHyperHC2GC(pVM, pCur->pavHCChunkHC);
1597	}
1598	}
1599
1600	/*
1601	* Update the two page directories with all page table mappings.
1602	* (One or more of them have changed, that's why we're here.)
1603	*/
1604	pVM->pgm.s.pMappingsGC = MMHyperHC2GC(pVM, pVM->pgm.s.pMappingsR3);
1605	for (PPGMMAPPING pCur = pVM->pgm.s.pMappingsR3; pCur->pNextR3; pCur = pCur->pNextR3)
1606	pCur->pNextGC = MMHyperHC2GC(pVM, pCur->pNextR3);
1607
1608	/* Relocate GC addresses of Page Tables. */
1609	for (PPGMMAPPING pCur = pVM->pgm.s.pMappingsR3; pCur; pCur = pCur->pNextR3)
1610	{
1611	for (RTHCUINT i = 0; i < pCur->cPTs; i++)
1612	{
1613	pCur->aPTs[i].pPTGC = MMHyperR3ToGC(pVM, pCur->aPTs[i].pPTR3);
1614	pCur->aPTs[i].paPaePTsGC = MMHyperR3ToGC(pVM, pCur->aPTs[i].paPaePTsR3);
1615	}
1616	}
1617
1618	/*
1619	* Dynamic page mapping area.
1620	*/
1621	pVM->pgm.s.paDynPageMap32BitPTEsGC += offDelta;
1622	pVM->pgm.s.paDynPageMapPaePTEsGC += offDelta;
1623	pVM->pgm.s.pbDynPageMapBaseGC += offDelta;
1624
1625	/*
1626	* The Zero page.
1627	*/
1628	pVM->pgm.s.pvZeroPgR0 = MMHyperR3ToR0(pVM, pVM->pgm.s.pvZeroPgR3);
1629	AssertRelease(pVM->pgm.s.pvZeroPgR0);
1630
1631	/*
1632	* Physical and virtual handlers.
1633	*/
1634	RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesHC->PhysHandlers, true, pgmR3RelocatePhysHandler, &offDelta);
1635	RTAvlroGCPtrDoWithAll(&pVM->pgm.s.pTreesHC->VirtHandlers, true, pgmR3RelocateVirtHandler, &offDelta);
1636
1637	/*
1638	* The page pool.
1639	*/
1640	pgmR3PoolRelocate(pVM);
1641	}
1642
1643
1644	/**
1645	* Callback function for relocating a physical access handler.
1646	*
1647	* @returns 0 (continue enum)
1648	* @param pNode Pointer to a PGMPHYSHANDLER node.
1649	* @param pvUser Pointer to the offDelta. This is a pointer to the delta since we're
1650	* not certain the delta will fit in a void pointer for all possible configs.
1651	*/
1652	static DECLCALLBACK(int) pgmR3RelocatePhysHandler(PAVLROGCPHYSNODECORE pNode, void *pvUser)
1653	{
1654	PPGMPHYSHANDLER pHandler = (PPGMPHYSHANDLER)pNode;
1655	RTGCINTPTR offDelta = *(PRTGCINTPTR)pvUser;
1656	if (pHandler->pfnHandlerGC)
1657	pHandler->pfnHandlerGC += offDelta;
1658	if ((RTGCUINTPTR)pHandler->pvUserGC >= 0x10000)
1659	pHandler->pvUserGC += offDelta;
1660	return 0;
1661	}
1662
1663
1664	/**
1665	* Callback function for relocating a virtual access handler.
1666	*
1667	* @returns 0 (continue enum)
1668	* @param pNode Pointer to a PGMVIRTHANDLER node.
1669	* @param pvUser Pointer to the offDelta. This is a pointer to the delta since we're
1670	* not certain the delta will fit in a void pointer for all possible configs.
1671	*/
1672	static DECLCALLBACK(int) pgmR3RelocateVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser)
1673	{
1674	PPGMVIRTHANDLER pHandler = (PPGMVIRTHANDLER)pNode;
1675	RTGCINTPTR offDelta = *(PRTGCINTPTR)pvUser;
1676	Assert(pHandler->pfnHandlerGC);
1677	pHandler->pfnHandlerGC += offDelta;
1678	return 0;
1679	}
1680
1681
1682	/**
1683	* The VM is being reset.
1684	*
1685	* For the PGM component this means that any PD write monitors
1686	* needs to be removed.
1687	*
1688	* @param pVM VM handle.
1689	*/
1690	PGMR3DECL(void) PGMR3Reset(PVM pVM)
1691	{
1692	LogFlow(("PGMR3Reset:\n"));
1693	VM_ASSERT_EMT(pVM);
1694
1695	/*
1696	* Unfix any fixed mappings and disable CR3 monitoring.
1697	*/
1698	pVM->pgm.s.fMappingsFixed = false;
1699	pVM->pgm.s.GCPtrMappingFixed = 0;
1700	pVM->pgm.s.cbMappingFixed = 0;
1701
1702	int rc = PGM_GST_PFN(UnmonitorCR3, pVM)(pVM);
1703	AssertRC(rc);
1704	#ifdef DEBUG
1705	PGMR3DumpMappings(pVM);
1706	#endif
1707
1708	/*
1709	* Reset the shadow page pool.
1710	*/
1711	pgmR3PoolReset(pVM);
1712
1713	/*
1714	* Re-init other members.
1715	*/
1716	pVM->pgm.s.fA20Enabled = true;
1717
1718	/*
1719	* Clear the FFs PGM owns.
1720	*/
1721	VM_FF_CLEAR(pVM, VM_FF_PGM_SYNC_CR3);
1722	VM_FF_CLEAR(pVM, VM_FF_PGM_SYNC_CR3_NON_GLOBAL);
1723
1724	/*
1725	* Zero memory.
1726	*/
1727	for (PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesHC; pRam; pRam = pRam->pNextHC)
1728	{
1729	unsigned iPage = pRam->cb >> PAGE_SHIFT;
1730	while (iPage-- > 0)
1731	{
1732	if (pRam->aPages[iPage].HCPhys & (MM_RAM_FLAGS_RESERVED \| MM_RAM_FLAGS_ROM \| MM_RAM_FLAGS_MMIO \| MM_RAM_FLAGS_MMIO2)) /** @todo PAGE FLAGS */
1733	{
1734	/* shadow ram is reloaded elsewhere. */
1735	Log4(("PGMR3Reset: not clearing phys page %RGp due to flags %RHp\n", pRam->GCPhys + (iPage << PAGE_SHIFT), pRam->aPages[iPage].HCPhys & (MM_RAM_FLAGS_RESERVED \| MM_RAM_FLAGS_ROM \| MM_RAM_FLAGS_MMIO))); /** @todo PAGE FLAGS */
1736	continue;
1737	}
1738	if (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)
1739	{
1740	unsigned iChunk = iPage >> (PGM_DYNAMIC_CHUNK_SHIFT - PAGE_SHIFT);
1741	if (pRam->pavHCChunkHC[iChunk])
1742	ASMMemZero32((char *)pRam->pavHCChunkHC[iChunk] + ((iPage << PAGE_SHIFT) & PGM_DYNAMIC_CHUNK_OFFSET_MASK), PAGE_SIZE);
1743	}
1744	else
1745	ASMMemZero32((char *)pRam->pvHC + (iPage << PAGE_SHIFT), PAGE_SIZE);
1746	}
1747	}
1748
1749	/*
1750	* Switch mode back to real mode.
1751	*/
1752	rc = pgmR3ChangeMode(pVM, PGMMODE_REAL);
1753	AssertReleaseRC(rc);
1754	STAM_REL_COUNTER_RESET(&pVM->pgm.s.cGuestModeChanges);
1755	}
1756
1757
1758	/**
1759	* Terminates the PGM.
1760	*
1761	* @returns VBox status code.
1762	* @param pVM Pointer to VM structure.
1763	*/
1764	PGMR3DECL(int) PGMR3Term(PVM pVM)
1765	{
1766	return PDMR3CritSectDelete(&pVM->pgm.s.CritSect);
1767	}
1768
1769
1770	#ifdef VBOX_STRICT
1771	/**
1772	* VM state change callback for clearing fNoMorePhysWrites after
1773	* a snapshot has been created.
1774	*/
1775	static DECLCALLBACK(void) pgmR3ResetNoMorePhysWritesFlag(PVM pVM, VMSTATE enmState, VMSTATE enmOldState, void *pvUser)
1776	{
1777	if (enmState == VMSTATE_RUNNING)
1778	pVM->pgm.s.fNoMorePhysWrites = false;
1779	}
1780	#endif
1781
1782
1783	/**
1784	* Execute state save operation.
1785	*
1786	* @returns VBox status code.
1787	* @param pVM VM Handle.
1788	* @param pSSM SSM operation handle.
1789	*/
1790	static DECLCALLBACK(int) pgmR3Save(PVM pVM, PSSMHANDLE pSSM)
1791	{
1792	PPGM pPGM = &pVM->pgm.s;
1793
1794	/* No more writes to physical memory after this point! */
1795	pVM->pgm.s.fNoMorePhysWrites = true;
1796
1797	/*
1798	* Save basic data (required / unaffected by relocation).
1799	*/
1800	#if 1
1801	SSMR3PutBool(pSSM, pPGM->fMappingsFixed);
1802	#else
1803	SSMR3PutUInt(pSSM, pPGM->fMappingsFixed);
1804	#endif
1805	SSMR3PutGCPtr(pSSM, pPGM->GCPtrMappingFixed);
1806	SSMR3PutU32(pSSM, pPGM->cbMappingFixed);
1807	SSMR3PutUInt(pSSM, pPGM->cbRamSize);
1808	SSMR3PutGCPhys(pSSM, pPGM->GCPhysA20Mask);
1809	SSMR3PutUInt(pSSM, pPGM->fA20Enabled);
1810	SSMR3PutUInt(pSSM, pPGM->fSyncFlags);
1811	SSMR3PutUInt(pSSM, pPGM->enmGuestMode);
1812	SSMR3PutU32(pSSM, ~0); /* Separator. */
1813
1814	/*
1815	* The guest mappings.
1816	*/
1817	uint32_t i = 0;
1818	for (PPGMMAPPING pMapping = pPGM->pMappingsR3; pMapping; pMapping = pMapping->pNextR3, i++)
1819	{
1820	SSMR3PutU32(pSSM, i);
1821	SSMR3PutStrZ(pSSM, pMapping->pszDesc); /* This is the best unique id we have... */
1822	SSMR3PutGCPtr(pSSM, pMapping->GCPtr);
1823	SSMR3PutGCUIntPtr(pSSM, pMapping->cPTs);
1824	/* flags are done by the mapping owners! */
1825	}
1826	SSMR3PutU32(pSSM, ~0); /* terminator. */
1827
1828	/*
1829	* Ram range flags and bits.
1830	*/
1831	i = 0;
1832	for (PPGMRAMRANGE pRam = pPGM->pRamRangesHC; pRam; pRam = pRam->pNextHC, i++)
1833	{
1834	/** @todo MMIO ranges may move (PCI reconfig), we currently assume they don't. */
1835
1836	SSMR3PutU32(pSSM, i);
1837	SSMR3PutGCPhys(pSSM, pRam->GCPhys);
1838	SSMR3PutGCPhys(pSSM, pRam->GCPhysLast);
1839	SSMR3PutGCPhys(pSSM, pRam->cb);
1840	SSMR3PutU8(pSSM, !!pRam->pvHC); /* boolean indicating memory or not. */
1841
1842	/* Flags. */
1843	const unsigned cPages = pRam->cb >> PAGE_SHIFT;
1844	for (unsigned iPage = 0; iPage < cPages; iPage++)
1845	SSMR3PutU16(pSSM, (uint16_t)(pRam->aPages[iPage].HCPhys & ~X86_PTE_PAE_PG_MASK)); /** @todo PAGE FLAGS */
1846
1847	/* any memory associated with the range. */
1848	if (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)
1849	{
1850	for (unsigned iChunk = 0; iChunk < (pRam->cb >> PGM_DYNAMIC_CHUNK_SHIFT); iChunk++)
1851	{
1852	if (pRam->pavHCChunkHC[iChunk])
1853	{
1854	SSMR3PutU8(pSSM, 1); /* chunk present */
1855	SSMR3PutMem(pSSM, pRam->pavHCChunkHC[iChunk], PGM_DYNAMIC_CHUNK_SIZE);
1856	}
1857	else
1858	SSMR3PutU8(pSSM, 0); /* no chunk present */
1859	}
1860	}
1861	else if (pRam->pvHC)
1862	{
1863	int rc = SSMR3PutMem(pSSM, pRam->pvHC, pRam->cb);
1864	if (VBOX_FAILURE(rc))
1865	{
1866	Log(("pgmR3Save: SSMR3PutMem(, %p, %#x) -> %Vrc\n", pRam->pvHC, pRam->cb, rc));
1867	return rc;
1868	}
1869	}
1870	}
1871	return SSMR3PutU32(pSSM, ~0); /* terminator. */
1872	}
1873
1874
1875	/**
1876	* Execute state load operation.
1877	*
1878	* @returns VBox status code.
1879	* @param pVM VM Handle.
1880	* @param pSSM SSM operation handle.
1881	* @param u32Version Data layout version.
1882	*/
1883	static DECLCALLBACK(int) pgmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version)
1884	{
1885	/*
1886	* Validate version.
1887	*/
1888	if (u32Version != PGM_SAVED_STATE_VERSION)
1889	{
1890	Log(("pgmR3Load: Invalid version u32Version=%d (current %d)!\n", u32Version, PGM_SAVED_STATE_VERSION));
1891	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1892	}
1893
1894	/*
1895	* Call the reset function to make sure all the memory is cleared.
1896	*/
1897	PGMR3Reset(pVM);
1898
1899	/*
1900	* Load basic data (required / unaffected by relocation).
1901	*/
1902	PPGM pPGM = &pVM->pgm.s;
1903	#if 1
1904	SSMR3GetBool(pSSM, &pPGM->fMappingsFixed);
1905	#else
1906	uint32_t u;
1907	SSMR3GetU32(pSSM, &u);
1908	pPGM->fMappingsFixed = u;
1909	#endif
1910	SSMR3GetGCPtr(pSSM, &pPGM->GCPtrMappingFixed);
1911	SSMR3GetU32(pSSM, &pPGM->cbMappingFixed);
1912
1913	RTUINT cbRamSize;
1914	int rc = SSMR3GetU32(pSSM, &cbRamSize);
1915	if (VBOX_FAILURE(rc))
1916	return rc;
1917	if (cbRamSize != pPGM->cbRamSize)
1918	return VERR_SSM_LOAD_MEMORY_SIZE_MISMATCH;
1919	SSMR3GetGCPhys(pSSM, &pPGM->GCPhysA20Mask);
1920	SSMR3GetUInt(pSSM, &pPGM->fA20Enabled);
1921	SSMR3GetUInt(pSSM, &pPGM->fSyncFlags);
1922	RTUINT uGuestMode;
1923	SSMR3GetUInt(pSSM, &uGuestMode);
1924	pPGM->enmGuestMode = (PGMMODE)uGuestMode;
1925
1926	/* check separator. */
1927	uint32_t u32Sep;
1928	SSMR3GetU32(pSSM, &u32Sep);
1929	if (VBOX_FAILURE(rc))
1930	return rc;
1931	if (u32Sep != (uint32_t)~0)
1932	{
1933	AssertMsgFailed(("u32Sep=%#x (first)\n", u32Sep));
1934	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1935	}
1936
1937	/*
1938	* The guest mappings.
1939	*/
1940	uint32_t i = 0;
1941	for (;; i++)
1942	{
1943	/* Check the seqence number / separator. */
1944	rc = SSMR3GetU32(pSSM, &u32Sep);
1945	if (VBOX_FAILURE(rc))
1946	return rc;
1947	if (u32Sep == ~0U)
1948	break;
1949	if (u32Sep != i)
1950	{
1951	AssertMsgFailed(("u32Sep=%#x (last)\n", u32Sep));
1952	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1953	}
1954
1955	/* get the mapping details. */
1956	char szDesc[256];
1957	szDesc[0] = '\0';
1958	rc = SSMR3GetStrZ(pSSM, szDesc, sizeof(szDesc));
1959	if (VBOX_FAILURE(rc))
1960	return rc;
1961	RTGCPTR GCPtr;
1962	SSMR3GetGCPtr(pSSM, &GCPtr);
1963	RTGCUINTPTR cPTs;
1964	rc = SSMR3GetU32(pSSM, &cPTs);
1965	if (VBOX_FAILURE(rc))
1966	return rc;
1967
1968	/* find matching range. */
1969	PPGMMAPPING pMapping;
1970	for (pMapping = pPGM->pMappingsR3; pMapping; pMapping = pMapping->pNextR3)
1971	if ( pMapping->cPTs == cPTs
1972	&& !strcmp(pMapping->pszDesc, szDesc))
1973	break;
1974	if (!pMapping)
1975	{
1976	LogRel(("Couldn't find mapping: cPTs=%#x szDesc=%s (GCPtr=%VGv)\n",
1977	cPTs, szDesc, GCPtr));
1978	AssertFailed();
1979	return VERR_SSM_LOAD_CONFIG_MISMATCH;
1980	}
1981
1982	/* relocate it. */
1983	if (pMapping->GCPtr != GCPtr)
1984	{
1985	AssertMsg((GCPtr >> PGDIR_SHIFT << PGDIR_SHIFT) == GCPtr, ("GCPtr=%VGv\n", GCPtr));
1986	#if HC_ARCH_BITS == 64
1987	LogRel(("Mapping: %VGv -> %VGv %s\n", pMapping->GCPtr, GCPtr, pMapping->pszDesc));
1988	#endif
1989	pgmR3MapRelocate(pVM, pMapping, pMapping->GCPtr >> PGDIR_SHIFT, GCPtr >> PGDIR_SHIFT);
1990	}
1991	else
1992	Log(("pgmR3Load: '%s' needed no relocation (%VGv)\n", szDesc, GCPtr));
1993	}
1994
1995	/*
1996	* Ram range flags and bits.
1997	*/
1998	i = 0;
1999	for (PPGMRAMRANGE pRam = pPGM->pRamRangesHC; pRam; pRam = pRam->pNextHC, i++)
2000	{
2001	/** @todo MMIO ranges may move (PCI reconfig), we currently assume they don't. */
2002	/* Check the seqence number / separator. */
2003	rc = SSMR3GetU32(pSSM, &u32Sep);
2004	if (VBOX_FAILURE(rc))
2005	return rc;
2006	if (u32Sep == ~0U)
2007	break;
2008	if (u32Sep != i)
2009	{
2010	AssertMsgFailed(("u32Sep=%#x (last)\n", u32Sep));
2011	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2012	}
2013
2014	/* Get the range details. */
2015	RTGCPHYS GCPhys;
2016	SSMR3GetGCPhys(pSSM, &GCPhys);
2017	RTGCPHYS GCPhysLast;
2018	SSMR3GetGCPhys(pSSM, &GCPhysLast);
2019	RTGCPHYS cb;
2020	SSMR3GetGCPhys(pSSM, &cb);
2021	uint8_t fHaveBits;
2022	rc = SSMR3GetU8(pSSM, &fHaveBits);
2023	if (VBOX_FAILURE(rc))
2024	return rc;
2025	if (fHaveBits & ~1)
2026	{
2027	AssertMsgFailed(("u32Sep=%#x (last)\n", u32Sep));
2028	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2029	}
2030
2031	/* Match it up with the current range. */
2032	if ( GCPhys != pRam->GCPhys
2033	\|\| GCPhysLast != pRam->GCPhysLast
2034	\|\| cb != pRam->cb
2035	\|\| fHaveBits != !!pRam->pvHC)
2036	{
2037	LogRel(("Ram range: %VGp-%VGp %VGp bytes %s\n"
2038	"State : %VGp-%VGp %VGp bytes %s\n",
2039	pRam->GCPhys, pRam->GCPhysLast, pRam->cb, pRam->pvHC ? "bits" : "nobits",
2040	GCPhys, GCPhysLast, cb, fHaveBits ? "bits" : "nobits"));
2041	/*
2042	* If we're loading a state for debugging purpose, don't make a fuss if
2043	* the MMIO[2] and ROM stuff isn't 100% right, just skip the mismatches.
2044	*/
2045	if ( SSMR3HandleGetAfter(pSSM) != SSMAFTER_DEBUG_IT
2046	\|\| GCPhys < 8 * _1M)
2047	AssertFailedReturn(VERR_SSM_LOAD_CONFIG_MISMATCH);
2048
2049	RTGCPHYS cPages = ((GCPhysLast - GCPhys) + 1) >> PAGE_SHIFT;
2050	while (cPages-- > 0)
2051	{
2052	uint16_t u16Ignore;
2053	SSMR3GetU16(pSSM, &u16Ignore);
2054	}
2055	continue;
2056	}
2057
2058	/* Flags. */
2059	const unsigned cPages = pRam->cb >> PAGE_SHIFT;
2060	for (unsigned iPage = 0; iPage < cPages; iPage++)
2061	{
2062	uint16_t u16 = 0;
2063	SSMR3GetU16(pSSM, &u16);
2064	u16 &= PAGE_OFFSET_MASK & ~( MM_RAM_FLAGS_VIRTUAL_HANDLER \| MM_RAM_FLAGS_VIRTUAL_WRITE \| MM_RAM_FLAGS_VIRTUAL_ALL
2065	\| MM_RAM_FLAGS_PHYSICAL_HANDLER \| MM_RAM_FLAGS_PHYSICAL_WRITE \| MM_RAM_FLAGS_PHYSICAL_ALL
2066	\| MM_RAM_FLAGS_PHYSICAL_TEMP_OFF );
2067	pRam->aPages[iPage].HCPhys = PGM_PAGE_GET_HCPHYS(&pRam->aPages[iPage]) \| (RTHCPHYS)u16; /** @todo PAGE FLAGS */
2068	}
2069
2070	/* any memory associated with the range. */
2071	if (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)
2072	{
2073	for (unsigned iChunk = 0; iChunk < (pRam->cb >> PGM_DYNAMIC_CHUNK_SHIFT); iChunk++)
2074	{
2075	uint8_t fValidChunk;
2076
2077	rc = SSMR3GetU8(pSSM, &fValidChunk);
2078	if (VBOX_FAILURE(rc))
2079	return rc;
2080	if (fValidChunk > 1)
2081	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2082
2083	if (fValidChunk)
2084	{
2085	if (!pRam->pavHCChunkHC[iChunk])
2086	{
2087	rc = pgmr3PhysGrowRange(pVM, pRam->GCPhys + iChunk * PGM_DYNAMIC_CHUNK_SIZE);
2088	if (VBOX_FAILURE(rc))
2089	return rc;
2090	}
2091	Assert(pRam->pavHCChunkHC[iChunk]);
2092
2093	SSMR3GetMem(pSSM, pRam->pavHCChunkHC[iChunk], PGM_DYNAMIC_CHUNK_SIZE);
2094	}
2095	/* else nothing to do */
2096	}
2097	}
2098	else if (pRam->pvHC)
2099	{
2100	int rc = SSMR3GetMem(pSSM, pRam->pvHC, pRam->cb);
2101	if (VBOX_FAILURE(rc))
2102	{
2103	Log(("pgmR3Save: SSMR3GetMem(, %p, %#x) -> %Vrc\n", pRam->pvHC, pRam->cb, rc));
2104	return rc;
2105	}
2106	}
2107	}
2108
2109	/*
2110	* We require a full resync now.
2111	*/
2112	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3_NON_GLOBAL);
2113	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
2114	pPGM->fSyncFlags \|= PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL;
2115	pPGM->fPhysCacheFlushPending = true;
2116	pgmR3HandlerPhysicalUpdateAll(pVM);
2117
2118	/*
2119	* Change the paging mode.
2120	*/
2121	return pgmR3ChangeMode(pVM, pPGM->enmGuestMode);
2122	}
2123
2124
2125	/**
2126	* Show paging mode.
2127	*
2128	* @param pVM VM Handle.
2129	* @param pHlp The info helpers.
2130	* @param pszArgs "all" (default), "guest", "shadow" or "host".
2131	*/
2132	static DECLCALLBACK(void) pgmR3InfoMode(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2133	{
2134	/* digest argument. */
2135	bool fGuest, fShadow, fHost;
2136	if (pszArgs)
2137	pszArgs = RTStrStripL(pszArgs);
2138	if (!pszArgs \|\| !*pszArgs \|\| strstr(pszArgs, "all"))
2139	fShadow = fHost = fGuest = true;
2140	else
2141	{
2142	fShadow = fHost = fGuest = false;
2143	if (strstr(pszArgs, "guest"))
2144	fGuest = true;
2145	if (strstr(pszArgs, "shadow"))
2146	fShadow = true;
2147	if (strstr(pszArgs, "host"))
2148	fHost = true;
2149	}
2150
2151	/* print info. */
2152	if (fGuest)
2153	pHlp->pfnPrintf(pHlp, "Guest paging mode: %s, changed %RU64 times, A20 %s\n",
2154	PGMGetModeName(pVM->pgm.s.enmGuestMode), pVM->pgm.s.cGuestModeChanges.c,
2155	pVM->pgm.s.fA20Enabled ? "enabled" : "disabled");
2156	if (fShadow)
2157	pHlp->pfnPrintf(pHlp, "Shadow paging mode: %s\n", PGMGetModeName(pVM->pgm.s.enmShadowMode));
2158	if (fHost)
2159	{
2160	const char *psz;
2161	switch (pVM->pgm.s.enmHostMode)
2162	{
2163	case SUPPAGINGMODE_INVALID: psz = "invalid"; break;
2164	case SUPPAGINGMODE_32_BIT: psz = "32-bit"; break;
2165	case SUPPAGINGMODE_32_BIT_GLOBAL: psz = "32-bit+G"; break;
2166	case SUPPAGINGMODE_PAE: psz = "PAE"; break;
2167	case SUPPAGINGMODE_PAE_GLOBAL: psz = "PAE+G"; break;
2168	case SUPPAGINGMODE_PAE_NX: psz = "PAE+NX"; break;
2169	case SUPPAGINGMODE_PAE_GLOBAL_NX: psz = "PAE+G+NX"; break;
2170	case SUPPAGINGMODE_AMD64: psz = "AMD64"; break;
2171	case SUPPAGINGMODE_AMD64_GLOBAL: psz = "AMD64+G"; break;
2172	case SUPPAGINGMODE_AMD64_NX: psz = "AMD64+NX"; break;
2173	case SUPPAGINGMODE_AMD64_GLOBAL_NX: psz = "AMD64+G+NX"; break;
2174	default: psz = "unknown"; break;
2175	}
2176	pHlp->pfnPrintf(pHlp, "Host paging mode: %s\n", psz);
2177	}
2178	}
2179
2180
2181	/**
2182	* Dump registered MMIO ranges to the log.
2183	*
2184	* @param pVM VM Handle.
2185	* @param pHlp The info helpers.
2186	* @param pszArgs Arguments, ignored.
2187	*/
2188	static DECLCALLBACK(void) pgmR3PhysInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2189	{
2190	NOREF(pszArgs);
2191	pHlp->pfnPrintf(pHlp,
2192	"RAM ranges (pVM=%p)\n"
2193	"%.s %.s\n",
2194	pVM,
2195	sizeof(RTGCPHYS) * 4 + 1, "GC Phys Range ",
2196	sizeof(RTHCPTR) * 2, "pvHC ");
2197
2198	for (PPGMRAMRANGE pCur = pVM->pgm.s.pRamRangesHC; pCur; pCur = pCur->pNextHC)
2199	pHlp->pfnPrintf(pHlp,
2200	"%VGp-%VGp %VHv\n",
2201	pCur->GCPhys,
2202	pCur->GCPhysLast,
2203	pCur->pvHC);
2204	}
2205
2206	/**
2207	* Dump the page directory to the log.
2208	*
2209	* @param pVM VM Handle.
2210	* @param pHlp The info helpers.
2211	* @param pszArgs Arguments, ignored.
2212	*/
2213	static DECLCALLBACK(void) pgmR3InfoCr3(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2214	{
2215	/** @todo fix this! Convert the PGMR3DumpHierarchyHC functions to do guest stuff. */
2216	/* Big pages supported? */
2217	const bool fPSE = !!(CPUMGetGuestCR4(pVM) & X86_CR4_PSE);
2218	/* Global pages supported? */
2219	const bool fPGE = !!(CPUMGetGuestCR4(pVM) & X86_CR4_PGE);
2220
2221	NOREF(pszArgs);
2222
2223	/*
2224	* Get page directory addresses.
2225	*/
2226	PVBOXPD pPDSrc = pVM->pgm.s.pGuestPDHC;
2227	Assert(pPDSrc);
2228	Assert(MMPhysGCPhys2HCVirt(pVM, (RTGCPHYS)(CPUMGetGuestCR3(pVM) & X86_CR3_PAGE_MASK), sizeof(*pPDSrc)) == pPDSrc);
2229
2230	/*
2231	* Iterate the page directory.
2232	*/
2233	for (unsigned iPD = 0; iPD < ELEMENTS(pPDSrc->a); iPD++)
2234	{
2235	VBOXPDE PdeSrc = pPDSrc->a[iPD];
2236	if (PdeSrc.n.u1Present)
2237	{
2238	if (PdeSrc.b.u1Size && fPSE)
2239	{
2240	pHlp->pfnPrintf(pHlp,
2241	"%04X - %VGp P=%d U=%d RW=%d G=%d - BIG\n",
2242	iPD,
2243	PdeSrc.u & X86_PDE_PG_MASK,
2244	PdeSrc.b.u1Present, PdeSrc.b.u1User, PdeSrc.b.u1Write, PdeSrc.b.u1Global && fPGE);
2245	}
2246	else
2247	{
2248	pHlp->pfnPrintf(pHlp,
2249	"%04X - %VGp P=%d U=%d RW=%d [G=%d]\n",
2250	iPD,
2251	PdeSrc.u & X86_PDE4M_PG_MASK,
2252	PdeSrc.n.u1Present, PdeSrc.n.u1User, PdeSrc.n.u1Write, PdeSrc.b.u1Global && fPGE);
2253	}
2254	}
2255	}
2256	}
2257
2258
2259	/**
2260	* Serivce a VMMCALLHOST_PGM_LOCK call.
2261	*
2262	* @returns VBox status code.
2263	* @param pVM The VM handle.
2264	*/
2265	PDMR3DECL(int) PGMR3LockCall(PVM pVM)
2266	{
2267	return pgmLock(pVM);
2268	}
2269
2270
2271	/**
2272	* Converts a PGMMODE value to a PGM_TYPE_* \#define.
2273	*
2274	* @returns PGM_TYPE_*.
2275	* @param pgmMode The mode value to convert.
2276	*/
2277	DECLINLINE(unsigned) pgmModeToType(PGMMODE pgmMode)
2278	{
2279	switch (pgmMode)
2280	{
2281	case PGMMODE_REAL: return PGM_TYPE_REAL;
2282	case PGMMODE_PROTECTED: return PGM_TYPE_PROT;
2283	case PGMMODE_32_BIT: return PGM_TYPE_32BIT;
2284	case PGMMODE_PAE:
2285	case PGMMODE_PAE_NX: return PGM_TYPE_PAE;
2286	case PGMMODE_AMD64:
2287	case PGMMODE_AMD64_NX: return PGM_TYPE_AMD64;
2288	default:
2289	AssertFatalMsgFailed(("pgmMode=%d\n", pgmMode));
2290	}
2291	}
2292
2293
2294	/**
2295	* Gets the index into the paging mode data array of a SHW+GST mode.
2296	*
2297	* @returns PGM::paPagingData index.
2298	* @param uShwType The shadow paging mode type.
2299	* @param uGstType The guest paging mode type.
2300	*/
2301	DECLINLINE(unsigned) pgmModeDataIndex(unsigned uShwType, unsigned uGstType)
2302	{
2303	Assert(uShwType >= PGM_TYPE_32BIT && uShwType <= PGM_TYPE_AMD64);
2304	Assert(uGstType >= PGM_TYPE_REAL && uGstType <= PGM_TYPE_AMD64);
2305	return (uShwType - PGM_TYPE_32BIT) * (PGM_TYPE_AMD64 - PGM_TYPE_32BIT + 1)
2306	+ (uGstType - PGM_TYPE_REAL);
2307	}
2308
2309
2310	/**
2311	* Gets the index into the paging mode data array of a SHW+GST mode.
2312	*
2313	* @returns PGM::paPagingData index.
2314	* @param enmShw The shadow paging mode.
2315	* @param enmGst The guest paging mode.
2316	*/
2317	DECLINLINE(unsigned) pgmModeDataIndexByMode(PGMMODE enmShw, PGMMODE enmGst)
2318	{
2319	Assert(enmShw >= PGMMODE_32_BIT && enmShw <= PGMMODE_MAX);
2320	Assert(enmGst > PGMMODE_INVALID && enmGst < PGMMODE_MAX);
2321	return pgmModeDataIndex(pgmModeToType(enmShw), pgmModeToType(enmGst));
2322	}
2323
2324
2325	/**
2326	* Calculates the max data index.
2327	* @returns The number of entries in the pagaing data array.
2328	*/
2329	DECLINLINE(unsigned) pgmModeDataMaxIndex(void)
2330	{
2331	return pgmModeDataIndex(PGM_TYPE_AMD64, PGM_TYPE_AMD64) + 1;
2332	}
2333
2334
2335	/**
2336	* Initializes the paging mode data kept in PGM::paModeData.
2337	*
2338	* @param pVM The VM handle.
2339	* @param fResolveGCAndR0 Indicate whether or not GC and Ring-0 symbols can be resolved now.
2340	* This is used early in the init process to avoid trouble with PDM
2341	* not being initialized yet.
2342	*/
2343	static int pgmR3ModeDataInit(PVM pVM, bool fResolveGCAndR0)
2344	{
2345	PPGMMODEDATA pModeData;
2346	int rc;
2347
2348	/*
2349	* Allocate the array on the first call.
2350	*/
2351	if (!pVM->pgm.s.paModeData)
2352	{
2353	pVM->pgm.s.paModeData = (PPGMMODEDATA)MMR3HeapAllocZ(pVM, MM_TAG_PGM, sizeof(PGMMODEDATA) * pgmModeDataMaxIndex());
2354	AssertReturn(pVM->pgm.s.paModeData, VERR_NO_MEMORY);
2355	}
2356
2357	/*
2358	* Initialize the array entries.
2359	*/
2360	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_32BIT, PGM_TYPE_REAL)];
2361	pModeData->uShwType = PGM_TYPE_32BIT;
2362	pModeData->uGstType = PGM_TYPE_REAL;
2363	rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2364	rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2365	rc = PGM_BTH_NAME_32BIT_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2366
2367	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_32BIT, PGMMODE_PROTECTED)];
2368	pModeData->uShwType = PGM_TYPE_32BIT;
2369	pModeData->uGstType = PGM_TYPE_PROT;
2370	rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2371	rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2372	rc = PGM_BTH_NAME_32BIT_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2373
2374	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_32BIT, PGM_TYPE_32BIT)];
2375	pModeData->uShwType = PGM_TYPE_32BIT;
2376	pModeData->uGstType = PGM_TYPE_32BIT;
2377	rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2378	rc = PGM_GST_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2379	rc = PGM_BTH_NAME_32BIT_32BIT(InitData)(pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2380
2381	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_REAL)];
2382	pModeData->uShwType = PGM_TYPE_PAE;
2383	pModeData->uGstType = PGM_TYPE_REAL;
2384	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2385	rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2386	rc = PGM_BTH_NAME_PAE_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2387
2388	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_PROT)];
2389	pModeData->uShwType = PGM_TYPE_PAE;
2390	pModeData->uGstType = PGM_TYPE_PROT;
2391	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2392	rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2393	rc = PGM_BTH_NAME_PAE_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2394
2395	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_32BIT)];
2396	pModeData->uShwType = PGM_TYPE_PAE;
2397	pModeData->uGstType = PGM_TYPE_32BIT;
2398	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2399	rc = PGM_GST_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2400	rc = PGM_BTH_NAME_PAE_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2401
2402	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_PAE)];
2403	pModeData->uShwType = PGM_TYPE_PAE;
2404	pModeData->uGstType = PGM_TYPE_PAE;
2405	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2406	rc = PGM_GST_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2407	rc = PGM_BTH_NAME_PAE_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2408
2409	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_AMD64, PGM_TYPE_REAL)];
2410	pModeData->uShwType = PGM_TYPE_AMD64;
2411	pModeData->uGstType = PGM_TYPE_REAL;
2412	rc = PGM_SHW_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2413	rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2414	rc = PGM_BTH_NAME_AMD64_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2415
2416	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_AMD64, PGM_TYPE_PROT)];
2417	pModeData->uShwType = PGM_TYPE_AMD64;
2418	pModeData->uGstType = PGM_TYPE_PROT;
2419	rc = PGM_SHW_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2420	rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2421	rc = PGM_BTH_NAME_AMD64_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2422
2423	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_AMD64, PGM_TYPE_AMD64)];
2424	pModeData->uShwType = PGM_TYPE_AMD64;
2425	pModeData->uGstType = PGM_TYPE_AMD64;
2426	rc = PGM_SHW_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2427	rc = PGM_GST_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2428	rc = PGM_BTH_NAME_AMD64_AMD64(InitData)(pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2429
2430	return VINF_SUCCESS;
2431	}
2432
2433
2434	/**
2435	* Swtich to different (or relocated in the relocate case) mode data.
2436	*
2437	* @param pVM The VM handle.
2438	* @param enmShw The the shadow paging mode.
2439	* @param enmGst The the guest paging mode.
2440	*/
2441	static void pgmR3ModeDataSwitch(PVM pVM, PGMMODE enmShw, PGMMODE enmGst)
2442	{
2443	PPGMMODEDATA pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(enmShw, enmGst)];
2444
2445	Assert(pModeData->uGstType == pgmModeToType(enmGst));
2446	Assert(pModeData->uShwType == pgmModeToType(enmShw));
2447
2448	/* shadow */
2449	pVM->pgm.s.pfnR3ShwRelocate = pModeData->pfnR3ShwRelocate;
2450	pVM->pgm.s.pfnR3ShwExit = pModeData->pfnR3ShwExit;
2451	pVM->pgm.s.pfnR3ShwGetPage = pModeData->pfnR3ShwGetPage;
2452	Assert(pVM->pgm.s.pfnR3ShwGetPage);
2453	pVM->pgm.s.pfnR3ShwModifyPage = pModeData->pfnR3ShwModifyPage;
2454	pVM->pgm.s.pfnR3ShwGetPDEByIndex = pModeData->pfnR3ShwGetPDEByIndex;
2455	pVM->pgm.s.pfnR3ShwSetPDEByIndex = pModeData->pfnR3ShwSetPDEByIndex;
2456	pVM->pgm.s.pfnR3ShwModifyPDEByIndex = pModeData->pfnR3ShwModifyPDEByIndex;
2457
2458	pVM->pgm.s.pfnGCShwGetPage = pModeData->pfnGCShwGetPage;
2459	pVM->pgm.s.pfnGCShwModifyPage = pModeData->pfnGCShwModifyPage;
2460	pVM->pgm.s.pfnGCShwGetPDEByIndex = pModeData->pfnGCShwGetPDEByIndex;
2461	pVM->pgm.s.pfnGCShwSetPDEByIndex = pModeData->pfnGCShwSetPDEByIndex;
2462	pVM->pgm.s.pfnGCShwModifyPDEByIndex = pModeData->pfnGCShwModifyPDEByIndex;
2463
2464	pVM->pgm.s.pfnR0ShwGetPage = pModeData->pfnR0ShwGetPage;
2465	pVM->pgm.s.pfnR0ShwModifyPage = pModeData->pfnR0ShwModifyPage;
2466	pVM->pgm.s.pfnR0ShwGetPDEByIndex = pModeData->pfnR0ShwGetPDEByIndex;
2467	pVM->pgm.s.pfnR0ShwSetPDEByIndex = pModeData->pfnR0ShwSetPDEByIndex;
2468	pVM->pgm.s.pfnR0ShwModifyPDEByIndex = pModeData->pfnR0ShwModifyPDEByIndex;
2469
2470
2471	/* guest */
2472	pVM->pgm.s.pfnR3GstRelocate = pModeData->pfnR3GstRelocate;
2473	pVM->pgm.s.pfnR3GstExit = pModeData->pfnR3GstExit;
2474	pVM->pgm.s.pfnR3GstGetPage = pModeData->pfnR3GstGetPage;
2475	Assert(pVM->pgm.s.pfnR3GstGetPage);
2476	pVM->pgm.s.pfnR3GstModifyPage = pModeData->pfnR3GstModifyPage;
2477	pVM->pgm.s.pfnR3GstGetPDE = pModeData->pfnR3GstGetPDE;
2478	pVM->pgm.s.pfnR3GstMonitorCR3 = pModeData->pfnR3GstMonitorCR3;
2479	pVM->pgm.s.pfnR3GstUnmonitorCR3 = pModeData->pfnR3GstUnmonitorCR3;
2480	pVM->pgm.s.pfnR3GstMapCR3 = pModeData->pfnR3GstMapCR3;
2481	pVM->pgm.s.pfnR3GstUnmapCR3 = pModeData->pfnR3GstUnmapCR3;
2482	pVM->pgm.s.pfnHCGstWriteHandlerCR3 = pModeData->pfnHCGstWriteHandlerCR3;
2483	pVM->pgm.s.pszHCGstWriteHandlerCR3 = pModeData->pszHCGstWriteHandlerCR3;
2484
2485	pVM->pgm.s.pfnGCGstGetPage = pModeData->pfnGCGstGetPage;
2486	pVM->pgm.s.pfnGCGstModifyPage = pModeData->pfnGCGstModifyPage;
2487	pVM->pgm.s.pfnGCGstGetPDE = pModeData->pfnGCGstGetPDE;
2488	pVM->pgm.s.pfnGCGstMonitorCR3 = pModeData->pfnGCGstMonitorCR3;
2489	pVM->pgm.s.pfnGCGstUnmonitorCR3 = pModeData->pfnGCGstUnmonitorCR3;
2490	pVM->pgm.s.pfnGCGstMapCR3 = pModeData->pfnGCGstMapCR3;
2491	pVM->pgm.s.pfnGCGstUnmapCR3 = pModeData->pfnGCGstUnmapCR3;
2492	pVM->pgm.s.pfnGCGstWriteHandlerCR3 = pModeData->pfnGCGstWriteHandlerCR3;
2493
2494	pVM->pgm.s.pfnR0GstGetPage = pModeData->pfnR0GstGetPage;
2495	pVM->pgm.s.pfnR0GstModifyPage = pModeData->pfnR0GstModifyPage;
2496	pVM->pgm.s.pfnR0GstGetPDE = pModeData->pfnR0GstGetPDE;
2497	pVM->pgm.s.pfnR0GstMonitorCR3 = pModeData->pfnR0GstMonitorCR3;
2498	pVM->pgm.s.pfnR0GstUnmonitorCR3 = pModeData->pfnR0GstUnmonitorCR3;
2499	pVM->pgm.s.pfnR0GstMapCR3 = pModeData->pfnR0GstMapCR3;
2500	pVM->pgm.s.pfnR0GstUnmapCR3 = pModeData->pfnR0GstUnmapCR3;
2501	pVM->pgm.s.pfnR0GstWriteHandlerCR3 = pModeData->pfnR0GstWriteHandlerCR3;
2502
2503
2504	/* both */
2505	pVM->pgm.s.pfnR3BthRelocate = pModeData->pfnR3BthRelocate;
2506	pVM->pgm.s.pfnR3BthTrap0eHandler = pModeData->pfnR3BthTrap0eHandler;
2507	pVM->pgm.s.pfnR3BthInvalidatePage = pModeData->pfnR3BthInvalidatePage;
2508	pVM->pgm.s.pfnR3BthSyncCR3 = pModeData->pfnR3BthSyncCR3;
2509	Assert(pVM->pgm.s.pfnR3BthSyncCR3);
2510	pVM->pgm.s.pfnR3BthSyncPage = pModeData->pfnR3BthSyncPage;
2511	pVM->pgm.s.pfnR3BthPrefetchPage = pModeData->pfnR3BthPrefetchPage;
2512	pVM->pgm.s.pfnR3BthVerifyAccessSyncPage = pModeData->pfnR3BthVerifyAccessSyncPage;
2513	#ifdef VBOX_STRICT
2514	pVM->pgm.s.pfnR3BthAssertCR3 = pModeData->pfnR3BthAssertCR3;
2515	#endif
2516
2517	pVM->pgm.s.pfnGCBthTrap0eHandler = pModeData->pfnGCBthTrap0eHandler;
2518	pVM->pgm.s.pfnGCBthInvalidatePage = pModeData->pfnGCBthInvalidatePage;
2519	pVM->pgm.s.pfnGCBthSyncCR3 = pModeData->pfnGCBthSyncCR3;
2520	pVM->pgm.s.pfnGCBthSyncPage = pModeData->pfnGCBthSyncPage;
2521	pVM->pgm.s.pfnGCBthPrefetchPage = pModeData->pfnGCBthPrefetchPage;
2522	pVM->pgm.s.pfnGCBthVerifyAccessSyncPage = pModeData->pfnGCBthVerifyAccessSyncPage;
2523	#ifdef VBOX_STRICT
2524	pVM->pgm.s.pfnGCBthAssertCR3 = pModeData->pfnGCBthAssertCR3;
2525	#endif
2526
2527	pVM->pgm.s.pfnR0BthTrap0eHandler = pModeData->pfnR0BthTrap0eHandler;
2528	pVM->pgm.s.pfnR0BthInvalidatePage = pModeData->pfnR0BthInvalidatePage;
2529	pVM->pgm.s.pfnR0BthSyncCR3 = pModeData->pfnR0BthSyncCR3;
2530	pVM->pgm.s.pfnR0BthSyncPage = pModeData->pfnR0BthSyncPage;
2531	pVM->pgm.s.pfnR0BthPrefetchPage = pModeData->pfnR0BthPrefetchPage;
2532	pVM->pgm.s.pfnR0BthVerifyAccessSyncPage = pModeData->pfnR0BthVerifyAccessSyncPage;
2533	#ifdef VBOX_STRICT
2534	pVM->pgm.s.pfnR0BthAssertCR3 = pModeData->pfnR0BthAssertCR3;
2535	#endif
2536	}
2537
2538
2539	#ifdef DEBUG_bird
2540	#include <stdlib.h> /* getenv() remove me! */
2541	#endif
2542
2543	/**
2544	* Calculates the shadow paging mode.
2545	*
2546	* @returns The shadow paging mode.
2547	* @param enmGuestMode The guest mode.
2548	* @param enmHostMode The host mode.
2549	* @param enmShadowMode The current shadow mode.
2550	* @param penmSwitcher Where to store the switcher to use.
2551	* VMMSWITCHER_INVALID means no change.
2552	*/
2553	static PGMMODE pgmR3CalcShadowMode(PGMMODE enmGuestMode, SUPPAGINGMODE enmHostMode, PGMMODE enmShadowMode, VMMSWITCHER *penmSwitcher)
2554	{
2555	VMMSWITCHER enmSwitcher = VMMSWITCHER_INVALID;
2556	switch (enmGuestMode)
2557	{
2558	/*
2559	* When switching to real or protected mode we don't change
2560	* anything since it's likely that we'll switch back pretty soon.
2561	*
2562	* During pgmR3InitPaging we'll end up here with PGMMODE_INVALID
2563	* and is supposed to determin which shadow paging and switcher to
2564	* use during init.
2565	*/
2566	case PGMMODE_REAL:
2567	case PGMMODE_PROTECTED:
2568	if (enmShadowMode != PGMMODE_INVALID)
2569	break; /* (no change) */
2570	switch (enmHostMode)
2571	{
2572	case SUPPAGINGMODE_32_BIT:
2573	case SUPPAGINGMODE_32_BIT_GLOBAL:
2574	enmShadowMode = PGMMODE_32_BIT;
2575	enmSwitcher = VMMSWITCHER_32_TO_32;
2576	break;
2577
2578	case SUPPAGINGMODE_PAE:
2579	case SUPPAGINGMODE_PAE_NX:
2580	case SUPPAGINGMODE_PAE_GLOBAL:
2581	case SUPPAGINGMODE_PAE_GLOBAL_NX:
2582	enmShadowMode = PGMMODE_PAE;
2583	enmSwitcher = VMMSWITCHER_PAE_TO_PAE;
2584	#ifdef DEBUG_bird
2585	if (getenv("VBOX_32BIT"))
2586	{
2587	enmShadowMode = PGMMODE_32_BIT;
2588	enmSwitcher = VMMSWITCHER_PAE_TO_32;
2589	}
2590	#endif
2591	break;
2592
2593	case SUPPAGINGMODE_AMD64:
2594	case SUPPAGINGMODE_AMD64_GLOBAL:
2595	case SUPPAGINGMODE_AMD64_NX:
2596	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
2597	enmShadowMode = PGMMODE_PAE;
2598	enmSwitcher = VMMSWITCHER_AMD64_TO_PAE;
2599	break;
2600
2601	default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
2602	}
2603	break;
2604
2605	case PGMMODE_32_BIT:
2606	switch (enmHostMode)
2607	{
2608	case SUPPAGINGMODE_32_BIT:
2609	case SUPPAGINGMODE_32_BIT_GLOBAL:
2610	enmShadowMode = PGMMODE_32_BIT;
2611	enmSwitcher = VMMSWITCHER_32_TO_32;
2612	break;
2613
2614	case SUPPAGINGMODE_PAE:
2615	case SUPPAGINGMODE_PAE_NX:
2616	case SUPPAGINGMODE_PAE_GLOBAL:
2617	case SUPPAGINGMODE_PAE_GLOBAL_NX:
2618	enmShadowMode = PGMMODE_PAE;
2619	enmSwitcher = VMMSWITCHER_PAE_TO_PAE;
2620	#ifdef DEBUG_bird
2621	if (getenv("VBOX_32BIT"))
2622	{
2623	enmShadowMode = PGMMODE_32_BIT;
2624	enmSwitcher = VMMSWITCHER_PAE_TO_32;
2625	}
2626	#endif
2627	break;
2628
2629	case SUPPAGINGMODE_AMD64:
2630	case SUPPAGINGMODE_AMD64_GLOBAL:
2631	case SUPPAGINGMODE_AMD64_NX:
2632	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
2633	enmShadowMode = PGMMODE_PAE;
2634	enmSwitcher = VMMSWITCHER_AMD64_TO_PAE;
2635	break;
2636
2637	default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
2638	}
2639	break;
2640
2641	case PGMMODE_PAE:
2642	case PGMMODE_PAE_NX: /** @todo This might require more switchers and guest+both modes. */
2643	switch (enmHostMode)
2644	{
2645	case SUPPAGINGMODE_32_BIT:
2646	case SUPPAGINGMODE_32_BIT_GLOBAL:
2647	enmShadowMode = PGMMODE_PAE;
2648	enmSwitcher = VMMSWITCHER_32_TO_PAE;
2649	break;
2650
2651	case SUPPAGINGMODE_PAE:
2652	case SUPPAGINGMODE_PAE_NX:
2653	case SUPPAGINGMODE_PAE_GLOBAL:
2654	case SUPPAGINGMODE_PAE_GLOBAL_NX:
2655	enmShadowMode = PGMMODE_PAE;
2656	enmSwitcher = VMMSWITCHER_PAE_TO_PAE;
2657	break;
2658
2659	case SUPPAGINGMODE_AMD64:
2660	case SUPPAGINGMODE_AMD64_GLOBAL:
2661	case SUPPAGINGMODE_AMD64_NX:
2662	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
2663	enmShadowMode = PGMMODE_PAE;
2664	enmSwitcher = VMMSWITCHER_AMD64_TO_PAE;
2665	break;
2666
2667	default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
2668	}
2669	break;
2670
2671	case PGMMODE_AMD64:
2672	case PGMMODE_AMD64_NX:
2673	switch (enmHostMode)
2674	{
2675	case SUPPAGINGMODE_32_BIT:
2676	case SUPPAGINGMODE_32_BIT_GLOBAL:
2677	enmShadowMode = PGMMODE_PAE;
2678	enmSwitcher = VMMSWITCHER_32_TO_AMD64;
2679	break;
2680
2681	case SUPPAGINGMODE_PAE:
2682	case SUPPAGINGMODE_PAE_NX:
2683	case SUPPAGINGMODE_PAE_GLOBAL:
2684	case SUPPAGINGMODE_PAE_GLOBAL_NX:
2685	enmShadowMode = PGMMODE_PAE;
2686	enmSwitcher = VMMSWITCHER_PAE_TO_AMD64;
2687	break;
2688
2689	case SUPPAGINGMODE_AMD64:
2690	case SUPPAGINGMODE_AMD64_GLOBAL:
2691	case SUPPAGINGMODE_AMD64_NX:
2692	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
2693	enmShadowMode = PGMMODE_PAE;
2694	enmSwitcher = VMMSWITCHER_AMD64_TO_AMD64;
2695	break;
2696
2697	default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
2698	}
2699	break;
2700
2701
2702	default:
2703	AssertReleaseMsgFailed(("enmGuestMode=%d\n", enmGuestMode));
2704	return PGMMODE_INVALID;
2705	}
2706
2707	*penmSwitcher = enmSwitcher;
2708	return enmShadowMode;
2709	}
2710
2711
2712	/**
2713	* Performs the actual mode change.
2714	* This is called by PGMChangeMode and pgmR3InitPaging().
2715	*
2716	* @returns VBox status code.
2717	* @param pVM VM handle.
2718	* @param enmGuestMode The new guest mode. This is assumed to be different from
2719	* the current mode.
2720	*/
2721	int pgmR3ChangeMode(PVM pVM, PGMMODE enmGuestMode)
2722	{
2723	LogFlow(("pgmR3ChangeMode: Guest mode: %d -> %d\n", pVM->pgm.s.enmGuestMode, enmGuestMode));
2724	STAM_REL_COUNTER_INC(&pVM->pgm.s.cGuestModeChanges);
2725
2726	/*
2727	* Calc the shadow mode and switcher.
2728	*/
2729	VMMSWITCHER enmSwitcher;
2730	PGMMODE enmShadowMode = pgmR3CalcShadowMode(enmGuestMode, pVM->pgm.s.enmHostMode, pVM->pgm.s.enmShadowMode, &enmSwitcher);
2731	if (enmSwitcher != VMMSWITCHER_INVALID)
2732	{
2733	/*
2734	* Select new switcher.
2735	*/
2736	int rc = VMMR3SelectSwitcher(pVM, enmSwitcher);
2737	if (VBOX_FAILURE(rc))
2738	{
2739	AssertReleaseMsgFailed(("VMMR3SelectSwitcher(%d) -> %Vrc\n", enmSwitcher, rc));
2740	return rc;
2741	}
2742	}
2743
2744	/*
2745	* Exit old mode(s).
2746	*/
2747	/* shadow */
2748	if (enmShadowMode != pVM->pgm.s.enmShadowMode)
2749	{
2750	LogFlow(("pgmR3ChangeMode: Shadow mode: %d -> %d\n", pVM->pgm.s.enmShadowMode, enmShadowMode));
2751	if (PGM_SHW_PFN(Exit, pVM))
2752	{
2753	int rc = PGM_SHW_PFN(Exit, pVM)(pVM);
2754	if (VBOX_FAILURE(rc))
2755	{
2756	AssertMsgFailed(("Exit failed for shadow mode %d: %Vrc\n", pVM->pgm.s.enmShadowMode, rc));
2757	return rc;
2758	}
2759	}
2760
2761	}
2762
2763	/* guest */
2764	if (PGM_GST_PFN(Exit, pVM))
2765	{
2766	int rc = PGM_GST_PFN(Exit, pVM)(pVM);
2767	if (VBOX_FAILURE(rc))
2768	{
2769	AssertMsgFailed(("Exit failed for guest mode %d: %Vrc\n", pVM->pgm.s.enmGuestMode, rc));
2770	return rc;
2771	}
2772	}
2773
2774	/*
2775	* Load new paging mode data.
2776	*/
2777	pgmR3ModeDataSwitch(pVM, enmShadowMode, enmGuestMode);
2778
2779	/*
2780	* Enter new shadow mode (if changed).
2781	*/
2782	if (enmShadowMode != pVM->pgm.s.enmShadowMode)
2783	{
2784	int rc;
2785	pVM->pgm.s.enmShadowMode = enmShadowMode;
2786	switch (enmShadowMode)
2787	{
2788	case PGMMODE_32_BIT:
2789	rc = PGM_SHW_NAME_32BIT(Enter)(pVM);
2790	break;
2791	case PGMMODE_PAE:
2792	case PGMMODE_PAE_NX:
2793	rc = PGM_SHW_NAME_PAE(Enter)(pVM);
2794	break;
2795	case PGMMODE_AMD64:
2796	case PGMMODE_AMD64_NX:
2797	rc = PGM_SHW_NAME_AMD64(Enter)(pVM);
2798	break;
2799	case PGMMODE_REAL:
2800	case PGMMODE_PROTECTED:
2801	default:
2802	AssertReleaseMsgFailed(("enmShadowMode=%d\n", enmShadowMode));
2803	return VERR_INTERNAL_ERROR;
2804	}
2805	if (VBOX_FAILURE(rc))
2806	{
2807	AssertReleaseMsgFailed(("Entering enmShadowMode=%d failed: %Vrc\n", enmShadowMode, rc));
2808	pVM->pgm.s.enmShadowMode = PGMMODE_INVALID;
2809	return rc;
2810	}
2811	}
2812
2813	/*
2814	* Enter the new guest and shadow+guest modes.
2815	*/
2816	int rc = -1;
2817	int rc2 = -1;
2818	RTGCPHYS GCPhysCR3 = NIL_RTGCPHYS;
2819	pVM->pgm.s.enmGuestMode = enmGuestMode;
2820	switch (enmGuestMode)
2821	{
2822	case PGMMODE_REAL:
2823	rc = PGM_GST_NAME_REAL(Enter)(pVM, NIL_RTGCPHYS);
2824	switch (pVM->pgm.s.enmShadowMode)
2825	{
2826	case PGMMODE_32_BIT:
2827	rc2 = PGM_BTH_NAME_32BIT_REAL(Enter)(pVM, NIL_RTGCPHYS);
2828	break;
2829	case PGMMODE_PAE:
2830	case PGMMODE_PAE_NX:
2831	rc2 = PGM_BTH_NAME_PAE_REAL(Enter)(pVM, NIL_RTGCPHYS);
2832	break;
2833	case PGMMODE_AMD64:
2834	case PGMMODE_AMD64_NX:
2835	rc2 = PGM_BTH_NAME_AMD64_REAL(Enter)(pVM, NIL_RTGCPHYS);
2836	break;
2837	default: AssertFailed(); break;
2838	}
2839	break;
2840
2841	case PGMMODE_PROTECTED:
2842	rc = PGM_GST_NAME_PROT(Enter)(pVM, NIL_RTGCPHYS);
2843	switch (pVM->pgm.s.enmShadowMode)
2844	{
2845	case PGMMODE_32_BIT:
2846	rc2 = PGM_BTH_NAME_32BIT_PROT(Enter)(pVM, NIL_RTGCPHYS);
2847	break;
2848	case PGMMODE_PAE:
2849	case PGMMODE_PAE_NX:
2850	rc2 = PGM_BTH_NAME_PAE_PROT(Enter)(pVM, NIL_RTGCPHYS);
2851	break;
2852	case PGMMODE_AMD64:
2853	case PGMMODE_AMD64_NX:
2854	rc2 = PGM_BTH_NAME_AMD64_PROT(Enter)(pVM, NIL_RTGCPHYS);
2855	break;
2856	default: AssertFailed(); break;
2857	}
2858	break;
2859
2860	case PGMMODE_32_BIT:
2861	GCPhysCR3 = CPUMGetGuestCR3(pVM) & X86_CR3_PAGE_MASK;
2862	rc = PGM_GST_NAME_32BIT(Enter)(pVM, GCPhysCR3);
2863	switch (pVM->pgm.s.enmShadowMode)
2864	{
2865	case PGMMODE_32_BIT:
2866	rc2 = PGM_BTH_NAME_32BIT_32BIT(Enter)(pVM, GCPhysCR3);
2867	break;
2868	case PGMMODE_PAE:
2869	case PGMMODE_PAE_NX:
2870	rc2 = PGM_BTH_NAME_PAE_32BIT(Enter)(pVM, GCPhysCR3);
2871	break;
2872	case PGMMODE_AMD64:
2873	case PGMMODE_AMD64_NX:
2874	AssertMsgFailed(("Should use PAE shadow mode!\n"));
2875	default: AssertFailed(); break;
2876	}
2877	break;
2878
2879	//case PGMMODE_PAE_NX:
2880	case PGMMODE_PAE:
2881	GCPhysCR3 = CPUMGetGuestCR3(pVM) & X86_CR3_PAE_PAGE_MASK;
2882	rc = PGM_GST_NAME_PAE(Enter)(pVM, GCPhysCR3);
2883	switch (pVM->pgm.s.enmShadowMode)
2884	{
2885	case PGMMODE_PAE:
2886	case PGMMODE_PAE_NX:
2887	rc2 = PGM_BTH_NAME_PAE_PAE(Enter)(pVM, GCPhysCR3);
2888	break;
2889	case PGMMODE_32_BIT:
2890	case PGMMODE_AMD64:
2891	case PGMMODE_AMD64_NX:
2892	AssertMsgFailed(("Should use PAE shadow mode!\n"));
2893	default: AssertFailed(); break;
2894	}
2895	break;
2896
2897	//case PGMMODE_AMD64_NX:
2898	case PGMMODE_AMD64:
2899	GCPhysCR3 = CPUMGetGuestCR3(pVM) & 0xfffffffffffff000ULL; /** @todo define this mask and make CR3 64-bit in this case! */
2900	rc = PGM_GST_NAME_AMD64(Enter)(pVM, GCPhysCR3);
2901	switch (pVM->pgm.s.enmShadowMode)
2902	{
2903	case PGMMODE_AMD64:
2904	case PGMMODE_AMD64_NX:
2905	rc2 = PGM_BTH_NAME_AMD64_AMD64(Enter)(pVM, GCPhysCR3);
2906	break;
2907	case PGMMODE_32_BIT:
2908	case PGMMODE_PAE:
2909	case PGMMODE_PAE_NX:
2910	AssertMsgFailed(("Should use AMD64 shadow mode!\n"));
2911	default: AssertFailed(); break;
2912	}
2913	break;
2914
2915	default:
2916	AssertReleaseMsgFailed(("enmGuestMode=%d\n", enmGuestMode));
2917	rc = VERR_NOT_IMPLEMENTED;
2918	break;
2919	}
2920
2921	/* status codes. */
2922	AssertRC(rc);
2923	AssertRC(rc2);
2924	if (VBOX_SUCCESS(rc))
2925	{
2926	rc = rc2;
2927	if (VBOX_SUCCESS(rc)) /* no informational status codes. */
2928	rc = VINF_SUCCESS;
2929	}
2930
2931	/*
2932	* Notify SELM so it can update the TSSes with correct CR3s.
2933	*/
2934	SELMR3PagingModeChanged(pVM);
2935
2936	/* Notify HWACCM as well. */
2937	HWACCMR3PagingModeChanged(pVM, pVM->pgm.s.enmShadowMode);
2938	return rc;
2939	}
2940
2941
2942	/**
2943	* Dumps a PAE shadow page table.
2944	*
2945	* @returns VBox status code (VINF_SUCCESS).
2946	* @param pVM The VM handle.
2947	* @param pPT Pointer to the page table.
2948	* @param u64Address The virtual address of the page table starts.
2949	* @param fLongMode Set if this a long mode table; clear if it's a legacy mode table.
2950	* @param cMaxDepth The maxium depth.
2951	* @param pHlp Pointer to the output functions.
2952	*/
2953	static int pgmR3DumpHierarchyHCPaePT(PVM pVM, PX86PTPAE pPT, uint64_t u64Address, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
2954	{
2955	for (unsigned i = 0; i < ELEMENTS(pPT->a); i++)
2956	{
2957	X86PTEPAE Pte = pPT->a[i];
2958	if (Pte.n.u1Present)
2959	{
2960	pHlp->pfnPrintf(pHlp,
2961	fLongMode /P R S A D G WT CD AT NX 4M a p ? /
2962	? "%016llx 3 \| P %c %c %c %c %c %s %s %s %s 4K %c%c%c %016llx\n"
2963	: "%08llx 2 \| P %c %c %c %c %c %s %s %s %s 4K %c%c%c %016llx\n",
2964	u64Address + ((uint64_t)i << X86_PT_PAE_SHIFT),
2965	Pte.n.u1Write ? 'W' : 'R',
2966	Pte.n.u1User ? 'U' : 'S',
2967	Pte.n.u1Accessed ? 'A' : '-',
2968	Pte.n.u1Dirty ? 'D' : '-',
2969	Pte.n.u1Global ? 'G' : '-',
2970	Pte.n.u1WriteThru ? "WT" : "--",
2971	Pte.n.u1CacheDisable? "CD" : "--",
2972	Pte.n.u1PAT ? "AT" : "--",
2973	Pte.n.u1NoExecute ? "NX" : "--",
2974	Pte.u & PGM_PTFLAGS_TRACK_DIRTY ? 'd' : '-',
2975	Pte.u & BIT(10) ? '1' : '0',
2976	Pte.u & PGM_PTFLAGS_CSAM_VALIDATED? 'v' : '-',
2977	Pte.u & X86_PTE_PAE_PG_MASK);
2978	}
2979	}
2980	return VINF_SUCCESS;
2981	}
2982
2983
2984	/**
2985	* Dumps a PAE shadow page directory table.
2986	*
2987	* @returns VBox status code (VINF_SUCCESS).
2988	* @param pVM The VM handle.
2989	* @param HCPhys The physical address of the page directory table.
2990	* @param u64Address The virtual address of the page table starts.
2991	* @param cr4 The CR4, PSE is currently used.
2992	* @param fLongMode Set if this a long mode table; clear if it's a legacy mode table.
2993	* @param cMaxDepth The maxium depth.
2994	* @param pHlp Pointer to the output functions.
2995	*/
2996	static int pgmR3DumpHierarchyHCPaePD(PVM pVM, RTHCPHYS HCPhys, uint64_t u64Address, uint32_t cr4, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
2997	{
2998	PX86PDPAE pPD = (PX86PDPAE)MMPagePhys2Page(pVM, HCPhys);
2999	if (!pPD)
3000	{
3001	pHlp->pfnPrintf(pHlp, "%0*llx error! Page directory at HCPhys=%#VHp was not found in the page pool!\n",
3002	fLongMode ? 16 : 8, u64Address, HCPhys);
3003	return VERR_INVALID_PARAMETER;
3004	}
3005	int rc = VINF_SUCCESS;
3006	for (unsigned i = 0; i < ELEMENTS(pPD->a); i++)
3007	{
3008	X86PDEPAE Pde = pPD->a[i];
3009	if (Pde.n.u1Present)
3010	{
3011	if ((cr4 & X86_CR4_PSE) && Pde.b.u1Size)
3012	pHlp->pfnPrintf(pHlp,
3013	fLongMode /P R S A D G WT CD AT NX 4M a p ? /
3014	? "%016llx 2 \| P %c %c %c %c %c %s %s %s %s 4M %c%c%c %016llx\n"
3015	: "%08llx 1 \| P %c %c %c %c %c %s %s %s %s 4M %c%c%c %016llx\n",
3016	u64Address + ((uint64_t)i << X86_PD_PAE_SHIFT),
3017	Pde.b.u1Write ? 'W' : 'R',
3018	Pde.b.u1User ? 'U' : 'S',
3019	Pde.b.u1Accessed ? 'A' : '-',
3020	Pde.b.u1Dirty ? 'D' : '-',
3021	Pde.b.u1Global ? 'G' : '-',
3022	Pde.b.u1WriteThru ? "WT" : "--",
3023	Pde.b.u1CacheDisable? "CD" : "--",
3024	Pde.b.u1PAT ? "AT" : "--",
3025	Pde.b.u1NoExecute ? "NX" : "--",
3026	Pde.u & BIT64(9) ? '1' : '0',
3027	Pde.u & PGM_PDFLAGS_MAPPING ? 'm' : '-',
3028	Pde.u & PGM_PDFLAGS_TRACK_DIRTY ? 'd' : '-',
3029	Pde.u & X86_PDE_PAE_PG_MASK);
3030	else
3031	{
3032	pHlp->pfnPrintf(pHlp,
3033	fLongMode /P R S A D G WT CD AT NX 4M a p ? /
3034	? "%016llx 2 \| P %c %c %c %c %c %s %s .. %s 4K %c%c%c %016llx\n"
3035	: "%08llx 1 \| P %c %c %c %c %c %s %s .. %s 4K %c%c%c %016llx\n",
3036	u64Address + ((uint64_t)i << X86_PD_PAE_SHIFT),
3037	Pde.n.u1Write ? 'W' : 'R',
3038	Pde.n.u1User ? 'U' : 'S',
3039	Pde.n.u1Accessed ? 'A' : '-',
3040	Pde.n.u1Reserved0 ? '?' : '.', /* ignored */
3041	Pde.n.u1Reserved1 ? '?' : '.', /* ignored */
3042	Pde.n.u1WriteThru ? "WT" : "--",
3043	Pde.n.u1CacheDisable? "CD" : "--",
3044	Pde.n.u1NoExecute ? "NX" : "--",
3045	Pde.u & BIT64(9) ? '1' : '0',
3046	Pde.u & PGM_PDFLAGS_MAPPING ? 'm' : '-',
3047	Pde.u & PGM_PDFLAGS_TRACK_DIRTY ? 'd' : '-',
3048	Pde.u & X86_PDE_PAE_PG_MASK);
3049	if (cMaxDepth >= 1)
3050	{
3051	/** @todo what about using the page pool for mapping PTs? */
3052	uint64_t u64AddressPT = u64Address + ((uint64_t)i << X86_PD_PAE_SHIFT);
3053	RTHCPHYS HCPhysPT = Pde.u & X86_PDE_PAE_PG_MASK;
3054	PX86PTPAE pPT = NULL;
3055	if (!(Pde.u & PGM_PDFLAGS_MAPPING))
3056	pPT = (PX86PTPAE)MMPagePhys2Page(pVM, HCPhysPT);
3057	else
3058	{
3059	for (PPGMMAPPING pMap = pVM->pgm.s.pMappingsR3; pMap; pMap = pMap->pNextR3)
3060	{
3061	uint64_t off = u64AddressPT - pMap->GCPtr;
3062	if (off < pMap->cb)
3063	{
3064	const int iPDE = (uint32_t)(off >> X86_PD_SHIFT);
3065	const int iSub = (int)((off >> X86_PD_PAE_SHIFT) & 1); /* MSC is a pain sometimes */
3066	if ((iSub ? pMap->aPTs[iPDE].HCPhysPaePT1 : pMap->aPTs[iPDE].HCPhysPaePT0) != HCPhysPT)
3067	pHlp->pfnPrintf(pHlp, "%0*llx error! Mapping error! PT %d has HCPhysPT=%VHp not %VHp is in the PD.\n",
3068	fLongMode ? 16 : 8, u64AddressPT, iPDE,
3069	iSub ? pMap->aPTs[iPDE].HCPhysPaePT1 : pMap->aPTs[iPDE].HCPhysPaePT0, HCPhysPT);
3070	pPT = &pMap->aPTs[iPDE].paPaePTsR3[iSub];
3071	}
3072	}
3073	}
3074	int rc2 = VERR_INVALID_PARAMETER;
3075	if (pPT)
3076	rc2 = pgmR3DumpHierarchyHCPaePT(pVM, pPT, u64AddressPT, fLongMode, cMaxDepth - 1, pHlp);
3077	else
3078	pHlp->pfnPrintf(pHlp, "%0*llx error! Page table at HCPhys=%#VHp was not found in the page pool!\n",
3079	fLongMode ? 16 : 8, u64AddressPT, HCPhysPT);
3080	if (rc2 < rc && VBOX_SUCCESS(rc))
3081	rc = rc2;
3082	}
3083	}
3084	}
3085	}
3086	return rc;
3087	}
3088
3089
3090	/**
3091	* Dumps a PAE shadow page directory pointer table.
3092	*
3093	* @returns VBox status code (VINF_SUCCESS).
3094	* @param pVM The VM handle.
3095	* @param HCPhys The physical address of the page directory pointer table.
3096	* @param u64Address The virtual address of the page table starts.
3097	* @param cr4 The CR4, PSE is currently used.
3098	* @param fLongMode Set if this a long mode table; clear if it's a legacy mode table.
3099	* @param cMaxDepth The maxium depth.
3100	* @param pHlp Pointer to the output functions.
3101	*/
3102	static int pgmR3DumpHierarchyHCPaePDPTR(PVM pVM, RTHCPHYS HCPhys, uint64_t u64Address, uint32_t cr4, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
3103	{
3104	PX86PDPTR pPDPTR = (PX86PDPTR)MMPagePhys2Page(pVM, HCPhys);
3105	if (!pPDPTR)
3106	{
3107	pHlp->pfnPrintf(pHlp, "%0*llx error! Page directory pointer table at HCPhys=%#VHp was not found in the page pool!\n",
3108	fLongMode ? 16 : 8, u64Address, HCPhys);
3109	return VERR_INVALID_PARAMETER;
3110	}
3111
3112	int rc = VINF_SUCCESS;
3113	const unsigned c = fLongMode ? ELEMENTS(pPDPTR->a) : 4;
3114	for (unsigned i = 0; i < c; i++)
3115	{
3116	X86PDPE Pdpe = pPDPTR->a[i];
3117	if (Pdpe.n.u1Present)
3118	{
3119	if (fLongMode)
3120	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a p ? /
3121	"%016llx 1 \| P %c %c %c %c %c %s %s %s %s .. %c%c%c %016llx\n",
3122	u64Address + ((uint64_t)i << X86_PDPTR_SHIFT),
3123	Pdpe.n.u1Write ? 'W' : 'R',
3124	Pdpe.n.u1User ? 'U' : 'S',
3125	Pdpe.n.u1Accessed ? 'A' : '-',
3126	Pdpe.n.u3Reserved & 1? '?' : '.', /* ignored */
3127	Pdpe.n.u3Reserved & 4? '!' : '.', /* mbz */
3128	Pdpe.n.u1WriteThru ? "WT" : "--",
3129	Pdpe.n.u1CacheDisable? "CD" : "--",
3130	Pdpe.n.u3Reserved & 2? "!" : "..",/* mbz */
3131	Pdpe.n.u1NoExecute ? "NX" : "--",
3132	Pdpe.u & BIT(9) ? '1' : '0',
3133	Pdpe.u & PGM_PLXFLAGS_PERMANENT ? 'p' : '-',
3134	Pdpe.u & BIT(11) ? '1' : '0',
3135	Pdpe.u & X86_PDPE_PG_MASK);
3136	else
3137	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a p ? /
3138	"%08x 0 \| P %c %c %c %c %c %s %s %s %s .. %c%c%c %016llx\n",
3139	i << X86_PDPTR_SHIFT,
3140	Pdpe.n.u1Write ? '!' : '.', /* mbz */
3141	Pdpe.n.u1User ? '!' : '.', /* mbz */
3142	Pdpe.n.u1Accessed ? '!' : '.', /* mbz */
3143	Pdpe.n.u3Reserved & 1? '!' : '.', /* mbz */
3144	Pdpe.n.u3Reserved & 4? '!' : '.', /* mbz */
3145	Pdpe.n.u1WriteThru ? "WT" : "--",
3146	Pdpe.n.u1CacheDisable? "CD" : "--",
3147	Pdpe.n.u3Reserved & 2? "!" : "..",/* mbz */
3148	Pdpe.n.u1NoExecute ? "NX" : "--",
3149	Pdpe.u & BIT(9) ? '1' : '0',
3150	Pdpe.u & PGM_PLXFLAGS_PERMANENT ? 'p' : '-',
3151	Pdpe.u & BIT(11) ? '1' : '0',
3152	Pdpe.u & X86_PDPE_PG_MASK);
3153	if (cMaxDepth >= 1)
3154	{
3155	int rc2 = pgmR3DumpHierarchyHCPaePD(pVM, Pdpe.u & X86_PDPE_PG_MASK, u64Address + ((uint64_t)i << X86_PDPTR_SHIFT),
3156	cr4, fLongMode, cMaxDepth - 1, pHlp);
3157	if (rc2 < rc && VBOX_SUCCESS(rc))
3158	rc = rc2;
3159	}
3160	}
3161	}
3162	return rc;
3163	}
3164
3165
3166	/**
3167	* Dumps a 32-bit shadow page table.
3168	*
3169	* @returns VBox status code (VINF_SUCCESS).
3170	* @param pVM The VM handle.
3171	* @param HCPhys The physical address of the table.
3172	* @param cr4 The CR4, PSE is currently used.
3173	* @param cMaxDepth The maxium depth.
3174	* @param pHlp Pointer to the output functions.
3175	*/
3176	static int pgmR3DumpHierarchyHcPaePML4(PVM pVM, RTHCPHYS HCPhys, uint32_t cr4, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
3177	{
3178	PX86PML4 pPML4 = (PX86PML4)MMPagePhys2Page(pVM, HCPhys);
3179	if (!pPML4)
3180	{
3181	pHlp->pfnPrintf(pHlp, "Page map level 4 at HCPhys=%#VHp was not found in the page pool!\n", HCPhys);
3182	return VERR_INVALID_PARAMETER;
3183	}
3184
3185	int rc = VINF_SUCCESS;
3186	for (unsigned i = 0; i < ELEMENTS(pPML4->a); i++)
3187	{
3188	X86PML4E Pml4e = pPML4->a[i];
3189	if (Pml4e.n.u1Present)
3190	{
3191	uint64_t u64Address = ((uint64_t)i << X86_PML4_SHIFT) \| (((uint64_t)i >> (X86_PML4_SHIFT - X86_PDPTR_SHIFT - 1)) * 0xffff000000000000ULL);
3192	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a p ? /
3193	"%016llx 0 \| P %c %c %c %c %c %s %s %s %s .. %c%c%c %016llx\n",
3194	u64Address,
3195	Pml4e.n.u1Write ? 'W' : 'R',
3196	Pml4e.n.u1User ? 'U' : 'S',
3197	Pml4e.n.u1Accessed ? 'A' : '-',
3198	Pml4e.n.u3Reserved & 1? '?' : '.', /* ignored */
3199	Pml4e.n.u3Reserved & 4? '!' : '.', /* mbz */
3200	Pml4e.n.u1WriteThru ? "WT" : "--",
3201	Pml4e.n.u1CacheDisable? "CD" : "--",
3202	Pml4e.n.u3Reserved & 2? "!" : "..",/* mbz */
3203	Pml4e.n.u1NoExecute ? "NX" : "--",
3204	Pml4e.u & BIT(9) ? '1' : '0',
3205	Pml4e.u & PGM_PLXFLAGS_PERMANENT ? 'p' : '-',
3206	Pml4e.u & BIT(11) ? '1' : '0',
3207	Pml4e.u & X86_PML4E_PG_MASK);
3208
3209	if (cMaxDepth >= 1)
3210	{
3211	int rc2 = pgmR3DumpHierarchyHCPaePDPTR(pVM, Pml4e.u & X86_PML4E_PG_MASK, u64Address, cr4, true, cMaxDepth - 1, pHlp);
3212	if (rc2 < rc && VBOX_SUCCESS(rc))
3213	rc = rc2;
3214	}
3215	}
3216	}
3217	return rc;
3218	}
3219
3220
3221	/**
3222	* Dumps a 32-bit shadow page table.
3223	*
3224	* @returns VBox status code (VINF_SUCCESS).
3225	* @param pVM The VM handle.
3226	* @param pPT Pointer to the page table.
3227	* @param u32Address The virtual address this table starts at.
3228	* @param pHlp Pointer to the output functions.
3229	*/
3230	int pgmR3DumpHierarchyHC32BitPT(PVM pVM, PX86PT pPT, uint32_t u32Address, PCDBGFINFOHLP pHlp)
3231	{
3232	for (unsigned i = 0; i < ELEMENTS(pPT->a); i++)
3233	{
3234	X86PTE Pte = pPT->a[i];
3235	if (Pte.n.u1Present)
3236	{
3237	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a m d /
3238	"%08x 1 \| P %c %c %c %c %c %s %s %s .. 4K %c%c%c %08x\n",
3239	u32Address + (i << X86_PT_SHIFT),
3240	Pte.n.u1Write ? 'W' : 'R',
3241	Pte.n.u1User ? 'U' : 'S',
3242	Pte.n.u1Accessed ? 'A' : '-',
3243	Pte.n.u1Dirty ? 'D' : '-',
3244	Pte.n.u1Global ? 'G' : '-',
3245	Pte.n.u1WriteThru ? "WT" : "--",
3246	Pte.n.u1CacheDisable? "CD" : "--",
3247	Pte.n.u1PAT ? "AT" : "--",
3248	Pte.u & PGM_PTFLAGS_TRACK_DIRTY ? 'd' : '-',
3249	Pte.u & BIT(10) ? '1' : '0',
3250	Pte.u & PGM_PTFLAGS_CSAM_VALIDATED ? 'v' : '-',
3251	Pte.u & X86_PDE_PG_MASK);
3252	}
3253	}
3254	return VINF_SUCCESS;
3255	}
3256
3257
3258	/**
3259	* Dumps a 32-bit shadow page directory and page tables.
3260	*
3261	* @returns VBox status code (VINF_SUCCESS).
3262	* @param pVM The VM handle.
3263	* @param cr3 The root of the hierarchy.
3264	* @param cr4 The CR4, PSE is currently used.
3265	* @param cMaxDepth How deep into the hierarchy the dumper should go.
3266	* @param pHlp Pointer to the output functions.
3267	*/
3268	int pgmR3DumpHierarchyHC32BitPD(PVM pVM, uint32_t cr3, uint32_t cr4, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
3269	{
3270	PX86PD pPD = (PX86PD)MMPagePhys2Page(pVM, cr3 & X86_CR3_PAGE_MASK);
3271	if (!pPD)
3272	{
3273	pHlp->pfnPrintf(pHlp, "Page directory at %#x was not found in the page pool!\n", cr3 & X86_CR3_PAGE_MASK);
3274	return VERR_INVALID_PARAMETER;
3275	}
3276
3277	int rc = VINF_SUCCESS;
3278	for (unsigned i = 0; i < ELEMENTS(pPD->a); i++)
3279	{
3280	X86PDE Pde = pPD->a[i];
3281	if (Pde.n.u1Present)
3282	{
3283	const uint32_t u32Address = i << X86_PD_SHIFT;
3284	if ((cr4 & X86_CR4_PSE) && Pde.b.u1Size)
3285	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a m d /
3286	"%08x 0 \| P %c %c %c %c %c %s %s %s .. 4M %c%c%c %08x\n",
3287	u32Address,
3288	Pde.b.u1Write ? 'W' : 'R',
3289	Pde.b.u1User ? 'U' : 'S',
3290	Pde.b.u1Accessed ? 'A' : '-',
3291	Pde.b.u1Dirty ? 'D' : '-',
3292	Pde.b.u1Global ? 'G' : '-',
3293	Pde.b.u1WriteThru ? "WT" : "--",
3294	Pde.b.u1CacheDisable? "CD" : "--",
3295	Pde.b.u1PAT ? "AT" : "--",
3296	Pde.u & BIT64(9) ? '1' : '0',
3297	Pde.u & PGM_PDFLAGS_MAPPING ? 'm' : '-',
3298	Pde.u & PGM_PDFLAGS_TRACK_DIRTY ? 'd' : '-',
3299	Pde.u & X86_PDE4M_PG_MASK);
3300	else
3301	{
3302	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a m d /
3303	"%08x 0 \| P %c %c %c %c %c %s %s .. .. 4K %c%c%c %08x\n",
3304	u32Address,
3305	Pde.n.u1Write ? 'W' : 'R',
3306	Pde.n.u1User ? 'U' : 'S',
3307	Pde.n.u1Accessed ? 'A' : '-',
3308	Pde.n.u1Reserved0 ? '?' : '.', /* ignored */
3309	Pde.n.u1Reserved1 ? '?' : '.', /* ignored */
3310	Pde.n.u1WriteThru ? "WT" : "--",
3311	Pde.n.u1CacheDisable? "CD" : "--",
3312	Pde.u & BIT64(9) ? '1' : '0',
3313	Pde.u & PGM_PDFLAGS_MAPPING ? 'm' : '-',
3314	Pde.u & PGM_PDFLAGS_TRACK_DIRTY ? 'd' : '-',
3315	Pde.u & X86_PDE_PG_MASK);
3316	if (cMaxDepth >= 1)
3317	{
3318	/** @todo what about using the page pool for mapping PTs? */
3319	RTHCPHYS HCPhys = Pde.u & X86_PDE_PG_MASK;
3320	PX86PT pPT = NULL;
3321	if (!(Pde.u & PGM_PDFLAGS_MAPPING))
3322	pPT = (PX86PT)MMPagePhys2Page(pVM, HCPhys);
3323	else
3324	{
3325	for (PPGMMAPPING pMap = pVM->pgm.s.pMappingsR3; pMap; pMap = pMap->pNextR3)
3326	if (u32Address - pMap->GCPtr < pMap->cb)
3327	{
3328	int iPDE = (u32Address - pMap->GCPtr) >> X86_PD_SHIFT;
3329	if (pMap->aPTs[iPDE].HCPhysPT != HCPhys)
3330	pHlp->pfnPrintf(pHlp, "%08x error! Mapping error! PT %d has HCPhysPT=%VHp not %VHp is in the PD.\n",
3331	u32Address, iPDE, pMap->aPTs[iPDE].HCPhysPT, HCPhys);
3332	pPT = pMap->aPTs[iPDE].pPTR3;
3333	}
3334	}
3335	int rc2 = VERR_INVALID_PARAMETER;
3336	if (pPT)
3337	rc2 = pgmR3DumpHierarchyHC32BitPT(pVM, pPT, u32Address, pHlp);
3338	else
3339	pHlp->pfnPrintf(pHlp, "%08x error! Page table at %#x was not found in the page pool!\n", u32Address, HCPhys);
3340	if (rc2 < rc && VBOX_SUCCESS(rc))
3341	rc = rc2;
3342	}
3343	}
3344	}
3345	}
3346
3347	return rc;
3348	}
3349
3350
3351	/**
3352	* Dumps a 32-bit shadow page table.
3353	*
3354	* @returns VBox status code (VINF_SUCCESS).
3355	* @param pVM The VM handle.
3356	* @param pPT Pointer to the page table.
3357	* @param u32Address The virtual address this table starts at.
3358	* @param PhysSearch Address to search for.
3359	*/
3360	int pgmR3DumpHierarchyGC32BitPT(PVM pVM, PX86PT pPT, uint32_t u32Address, RTGCPHYS PhysSearch)
3361	{
3362	for (unsigned i = 0; i < ELEMENTS(pPT->a); i++)
3363	{
3364	X86PTE Pte = pPT->a[i];
3365	if (Pte.n.u1Present)
3366	{
3367	Log(( /P R S A D G WT CD AT NX 4M a m d /
3368	"%08x 1 \| P %c %c %c %c %c %s %s %s .. 4K %c%c%c %08x\n",
3369	u32Address + (i << X86_PT_SHIFT),
3370	Pte.n.u1Write ? 'W' : 'R',
3371	Pte.n.u1User ? 'U' : 'S',
3372	Pte.n.u1Accessed ? 'A' : '-',
3373	Pte.n.u1Dirty ? 'D' : '-',
3374	Pte.n.u1Global ? 'G' : '-',
3375	Pte.n.u1WriteThru ? "WT" : "--",
3376	Pte.n.u1CacheDisable? "CD" : "--",
3377	Pte.n.u1PAT ? "AT" : "--",
3378	Pte.u & PGM_PTFLAGS_TRACK_DIRTY ? 'd' : '-',
3379	Pte.u & BIT(10) ? '1' : '0',
3380	Pte.u & PGM_PTFLAGS_CSAM_VALIDATED ? 'v' : '-',
3381	Pte.u & X86_PDE_PG_MASK));
3382
3383	if ((Pte.u & X86_PDE_PG_MASK) == PhysSearch)
3384	{
3385	uint64_t fPageShw = 0;
3386	RTHCPHYS pPhysHC = 0;
3387
3388	PGMShwGetPage(pVM, (RTGCPTR)(u32Address + (i << X86_PT_SHIFT)), &fPageShw, &pPhysHC);
3389	Log(("Found %VGp at %VGv -> flags=%llx\n", PhysSearch, (RTGCPTR)(u32Address + (i << X86_PT_SHIFT)), fPageShw));
3390	}
3391	}
3392	}
3393	return VINF_SUCCESS;
3394	}
3395
3396
3397	/**
3398	* Dumps a 32-bit guest page directory and page tables.
3399	*
3400	* @returns VBox status code (VINF_SUCCESS).
3401	* @param pVM The VM handle.
3402	* @param cr3 The root of the hierarchy.
3403	* @param cr4 The CR4, PSE is currently used.
3404	* @param PhysSearch Address to search for.
3405	*/
3406	PGMR3DECL(int) PGMR3DumpHierarchyGC(PVM pVM, uint32_t cr3, uint32_t cr4, RTGCPHYS PhysSearch)
3407	{
3408	bool fLongMode = false;
3409	const unsigned cch = fLongMode ? 16 : 8; NOREF(cch);
3410	PX86PD pPD = 0;
3411
3412	int rc = PGM_GCPHYS_2_PTR(pVM, cr3 & X86_CR3_PAGE_MASK, &pPD);
3413	if (VBOX_FAILURE(rc) \|\| !pPD)
3414	{
3415	Log(("Page directory at %#x was not found in the page pool!\n", cr3 & X86_CR3_PAGE_MASK));
3416	return VERR_INVALID_PARAMETER;
3417	}
3418
3419	Log(("cr3=%08x cr4=%08x%s\n"
3420	"%-*s P - Present\n"
3421	"%-*s \| R/W - Read (0) / Write (1)\n"
3422	"%-*s \| \| U/S - User (1) / Supervisor (0)\n"
3423	"%-*s \| \| \| A - Accessed\n"
3424	"%-*s \| \| \| \| D - Dirty\n"
3425	"%-*s \| \| \| \| \| G - Global\n"
3426	"%-*s \| \| \| \| \| \| WT - Write thru\n"
3427	"%-*s \| \| \| \| \| \| \| CD - Cache disable\n"
3428	"%-*s \| \| \| \| \| \| \| \| AT - Attribute table (PAT)\n"
3429	"%-*s \| \| \| \| \| \| \| \| \| NX - No execute (K8)\n"
3430	"%-*s \| \| \| \| \| \| \| \| \| \| 4K/4M/2M - Page size.\n"
3431	"%-*s \| \| \| \| \| \| \| \| \| \| \| AVL - a=allocated; m=mapping; d=track dirty;\n"
3432	"%-*s \| \| \| \| \| \| \| \| \| \| \| \| p=permanent; v=validated;\n"
3433	"%-*s Level \| \| \| \| \| \| \| \| \| \| \| \| Page\n"
3434	/* xxxx n **** P R S A D G WT CD AT NX 4M AVL xxxxxxxxxxxxx
3435	- W U - - - -- -- -- -- -- 010 */
3436	, cr3, cr4, fLongMode ? " Long Mode" : "",
3437	cch, "", cch, "", cch, "", cch, "", cch, "", cch, "", cch, "",
3438	cch, "", cch, "", cch, "", cch, "", cch, "", cch, "", cch, "Address"));
3439
3440	for (unsigned i = 0; i < ELEMENTS(pPD->a); i++)
3441	{
3442	X86PDE Pde = pPD->a[i];
3443	if (Pde.n.u1Present)
3444	{
3445	const uint32_t u32Address = i << X86_PD_SHIFT;
3446
3447	if ((cr4 & X86_CR4_PSE) && Pde.b.u1Size)
3448	Log(( /P R S A D G WT CD AT NX 4M a m d /
3449	"%08x 0 \| P %c %c %c %c %c %s %s %s .. 4M %c%c%c %08x\n",
3450	u32Address,
3451	Pde.b.u1Write ? 'W' : 'R',
3452	Pde.b.u1User ? 'U' : 'S',
3453	Pde.b.u1Accessed ? 'A' : '-',
3454	Pde.b.u1Dirty ? 'D' : '-',
3455	Pde.b.u1Global ? 'G' : '-',
3456	Pde.b.u1WriteThru ? "WT" : "--",
3457	Pde.b.u1CacheDisable? "CD" : "--",
3458	Pde.b.u1PAT ? "AT" : "--",
3459	Pde.u & BIT(9) ? '1' : '0',
3460	Pde.u & BIT(10) ? '1' : '0',
3461	Pde.u & BIT(11) ? '1' : '0',
3462	Pde.u & X86_PDE4M_PG_MASK));
3463	/** @todo PhysSearch */
3464	else
3465	{
3466	Log(( /P R S A D G WT CD AT NX 4M a m d /
3467	"%08x 0 \| P %c %c %c %c %c %s %s .. .. 4K %c%c%c %08x\n",
3468	u32Address,
3469	Pde.n.u1Write ? 'W' : 'R',
3470	Pde.n.u1User ? 'U' : 'S',
3471	Pde.n.u1Accessed ? 'A' : '-',
3472	Pde.n.u1Reserved0 ? '?' : '.', /* ignored */
3473	Pde.n.u1Reserved1 ? '?' : '.', /* ignored */
3474	Pde.n.u1WriteThru ? "WT" : "--",
3475	Pde.n.u1CacheDisable? "CD" : "--",
3476	Pde.u & BIT(9) ? '1' : '0',
3477	Pde.u & BIT(10) ? '1' : '0',
3478	Pde.u & BIT(11) ? '1' : '0',
3479	Pde.u & X86_PDE_PG_MASK));
3480	////if (cMaxDepth >= 1)
3481	{
3482	/** @todo what about using the page pool for mapping PTs? */
3483	RTGCPHYS GCPhys = Pde.u & X86_PDE_PG_MASK;
3484	PX86PT pPT = NULL;
3485
3486	rc = PGM_GCPHYS_2_PTR(pVM, GCPhys, &pPT);
3487
3488	int rc2 = VERR_INVALID_PARAMETER;
3489	if (pPT)
3490	rc2 = pgmR3DumpHierarchyGC32BitPT(pVM, pPT, u32Address, PhysSearch);
3491	else
3492	Log(("%08x error! Page table at %#x was not found in the page pool!\n", u32Address, GCPhys));
3493	if (rc2 < rc && VBOX_SUCCESS(rc))
3494	rc = rc2;
3495	}
3496	}
3497	}
3498	}
3499
3500	return rc;
3501	}
3502
3503
3504	/**
3505	* Dumps a page table hierarchy use only physical addresses and cr4/lm flags.
3506	*
3507	* @returns VBox status code (VINF_SUCCESS).
3508	* @param pVM The VM handle.
3509	* @param cr3 The root of the hierarchy.
3510	* @param cr4 The cr4, only PAE and PSE is currently used.
3511	* @param fLongMode Set if long mode, false if not long mode.
3512	* @param cMaxDepth Number of levels to dump.
3513	* @param pHlp Pointer to the output functions.
3514	*/
3515	PGMR3DECL(int) PGMR3DumpHierarchyHC(PVM pVM, uint32_t cr3, uint32_t cr4, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
3516	{
3517	if (!pHlp)
3518	pHlp = DBGFR3InfoLogHlp();
3519	if (!cMaxDepth)
3520	return VINF_SUCCESS;
3521	const unsigned cch = fLongMode ? 16 : 8;
3522	pHlp->pfnPrintf(pHlp,
3523	"cr3=%08x cr4=%08x%s\n"
3524	"%-*s P - Present\n"
3525	"%-*s \| R/W - Read (0) / Write (1)\n"
3526	"%-*s \| \| U/S - User (1) / Supervisor (0)\n"
3527	"%-*s \| \| \| A - Accessed\n"
3528	"%-*s \| \| \| \| D - Dirty\n"
3529	"%-*s \| \| \| \| \| G - Global\n"
3530	"%-*s \| \| \| \| \| \| WT - Write thru\n"
3531	"%-*s \| \| \| \| \| \| \| CD - Cache disable\n"
3532	"%-*s \| \| \| \| \| \| \| \| AT - Attribute table (PAT)\n"
3533	"%-*s \| \| \| \| \| \| \| \| \| NX - No execute (K8)\n"
3534	"%-*s \| \| \| \| \| \| \| \| \| \| 4K/4M/2M - Page size.\n"
3535	"%-*s \| \| \| \| \| \| \| \| \| \| \| AVL - a=allocated; m=mapping; d=track dirty;\n"
3536	"%-*s \| \| \| \| \| \| \| \| \| \| \| \| p=permanent; v=validated;\n"
3537	"%-*s Level \| \| \| \| \| \| \| \| \| \| \| \| Page\n"
3538	/* xxxx n **** P R S A D G WT CD AT NX 4M AVL xxxxxxxxxxxxx
3539	- W U - - - -- -- -- -- -- 010 */
3540	, cr3, cr4, fLongMode ? " Long Mode" : "",
3541	cch, "", cch, "", cch, "", cch, "", cch, "", cch, "", cch, "",
3542	cch, "", cch, "", cch, "", cch, "", cch, "", cch, "", cch, "Address");
3543	if (cr4 & X86_CR4_PAE)
3544	{
3545	if (fLongMode)
3546	return pgmR3DumpHierarchyHcPaePML4(pVM, cr3 & X86_CR3_PAGE_MASK, cr4, cMaxDepth, pHlp);
3547	return pgmR3DumpHierarchyHCPaePDPTR(pVM, cr3 & X86_CR3_PAE_PAGE_MASK, 0, cr4, false, cMaxDepth, pHlp);
3548	}
3549	return pgmR3DumpHierarchyHC32BitPD(pVM, cr3 & X86_CR3_PAGE_MASK, cr4, cMaxDepth, pHlp);
3550	}
3551
3552
3553
3554	#ifdef VBOX_WITH_DEBUGGER
3555	/**
3556	* The '.pgmram' command.
3557	*
3558	* @returns VBox status.
3559	* @param pCmd Pointer to the command descriptor (as registered).
3560	* @param pCmdHlp Pointer to command helper functions.
3561	* @param pVM Pointer to the current VM (if any).
3562	* @param paArgs Pointer to (readonly) array of arguments.
3563	* @param cArgs Number of arguments in the array.
3564	*/
3565	static DECLCALLBACK(int) pgmR3CmdRam(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
3566	{
3567	/*
3568	* Validate input.
3569	*/
3570	if (!pVM)
3571	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires VM to be selected.\n");
3572	if (!pVM->pgm.s.pRamRangesGC)
3573	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Sorry, no Ram is registered.\n");
3574
3575	/*
3576	* Dump the ranges.
3577	*/
3578	int rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL, "From - To (incl) pvHC\n");
3579	PPGMRAMRANGE pRam;
3580	for (pRam = pVM->pgm.s.pRamRangesHC; pRam; pRam = pRam->pNextHC)
3581	{
3582	rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL,
3583	"%VGp - %VGp %p\n",
3584	pRam->GCPhys, pRam->GCPhysLast, pRam->pvHC);
3585	if (VBOX_FAILURE(rc))
3586	return rc;
3587	}
3588
3589	return VINF_SUCCESS;
3590	}
3591
3592
3593	/**
3594	* The '.pgmmap' command.
3595	*
3596	* @returns VBox status.
3597	* @param pCmd Pointer to the command descriptor (as registered).
3598	* @param pCmdHlp Pointer to command helper functions.
3599	* @param pVM Pointer to the current VM (if any).
3600	* @param paArgs Pointer to (readonly) array of arguments.
3601	* @param cArgs Number of arguments in the array.
3602	*/
3603	static DECLCALLBACK(int) pgmR3CmdMap(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
3604	{
3605	/*
3606	* Validate input.
3607	*/
3608	if (!pVM)
3609	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires VM to be selected.\n");
3610	if (!pVM->pgm.s.pMappingsR3)
3611	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Sorry, no mappings are registered.\n");
3612
3613	/*
3614	* Print message about the fixedness of the mappings.
3615	*/
3616	int rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL, pVM->pgm.s.fMappingsFixed ? "The mappings are FIXED.\n" : "The mappings are FLOATING.\n");
3617	if (VBOX_FAILURE(rc))
3618	return rc;
3619
3620	/*
3621	* Dump the ranges.
3622	*/
3623	PPGMMAPPING pCur;
3624	for (pCur = pVM->pgm.s.pMappingsR3; pCur; pCur = pCur->pNextR3)
3625	{
3626	rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL,
3627	"%08x - %08x %s\n",
3628	pCur->GCPtr, pCur->GCPtrLast, pCur->pszDesc);
3629	if (VBOX_FAILURE(rc))
3630	return rc;
3631	}
3632
3633	return VINF_SUCCESS;
3634	}
3635
3636
3637	/**
3638	* The '.pgmsync' command.
3639	*
3640	* @returns VBox status.
3641	* @param pCmd Pointer to the command descriptor (as registered).
3642	* @param pCmdHlp Pointer to command helper functions.
3643	* @param pVM Pointer to the current VM (if any).
3644	* @param paArgs Pointer to (readonly) array of arguments.
3645	* @param cArgs Number of arguments in the array.
3646	*/
3647	static DECLCALLBACK(int) pgmR3CmdSync(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
3648	{
3649	/*
3650	* Validate input.
3651	*/
3652	if (!pVM)
3653	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires VM to be selected.\n");
3654
3655	/*
3656	* Force page directory sync.
3657	*/
3658	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
3659
3660	int rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Forcing page directory sync.\n");
3661	if (VBOX_FAILURE(rc))
3662	return rc;
3663
3664	return VINF_SUCCESS;
3665	}
3666
3667
3668	/**
3669	* The '.pgmsyncalways' command.
3670	*
3671	* @returns VBox status.
3672	* @param pCmd Pointer to the command descriptor (as registered).
3673	* @param pCmdHlp Pointer to command helper functions.
3674	* @param pVM Pointer to the current VM (if any).
3675	* @param paArgs Pointer to (readonly) array of arguments.
3676	* @param cArgs Number of arguments in the array.
3677	*/
3678	static DECLCALLBACK(int) pgmR3CmdSyncAlways(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
3679	{
3680	/*
3681	* Validate input.
3682	*/
3683	if (!pVM)
3684	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires VM to be selected.\n");
3685
3686	/*
3687	* Force page directory sync.
3688	*/
3689	if (pVM->pgm.s.fSyncFlags & PGM_SYNC_ALWAYS)
3690	{
3691	ASMAtomicAndU32(&pVM->pgm.s.fSyncFlags, ~PGM_SYNC_ALWAYS);
3692	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Disabled permanent forced page directory syncing.\n");
3693	}
3694	else
3695	{
3696	ASMAtomicOrU32(&pVM->pgm.s.fSyncFlags, PGM_SYNC_ALWAYS);
3697	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
3698	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Enabled permanent forced page directory syncing.\n");
3699	}
3700	}
3701
3702	#endif
3703
3704	/**
3705	* pvUser argument of the pgmR3CheckIntegrity*Node callbacks.
3706	*/
3707	typedef struct PGMCHECKINTARGS
3708	{
3709	bool fLeftToRight; /*< true: left-to-right; false: right-to-left. /
3710	PPGMPHYSHANDLER pPrevPhys;
3711	PPGMVIRTHANDLER pPrevVirt;
3712	PPGMPHYS2VIRTHANDLER pPrevPhys2Virt;
3713	PVM pVM;
3714	} PGMCHECKINTARGS, *PPGMCHECKINTARGS;
3715
3716	/**
3717	* Validate a node in the physical handler tree.
3718	*
3719	* @returns 0 on if ok, other wise 1.
3720	* @param pNode The handler node.
3721	* @param pvUser pVM.
3722	*/
3723	static DECLCALLBACK(int) pgmR3CheckIntegrityPhysHandlerNode(PAVLROGCPHYSNODECORE pNode, void *pvUser)
3724	{
3725	PPGMCHECKINTARGS pArgs = (PPGMCHECKINTARGS)pvUser;
3726	PPGMPHYSHANDLER pCur = (PPGMPHYSHANDLER)pNode;
3727	AssertReleaseReturn(!((uintptr_t)pCur & 7), 1);
3728	AssertReleaseMsg(pCur->Core.Key <= pCur->Core.KeyLast,("pCur=%p %VGp-%VGp %s\n", pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
3729	AssertReleaseMsg( !pArgs->pPrevPhys
3730	\|\| (pArgs->fLeftToRight ? pArgs->pPrevPhys->Core.KeyLast < pCur->Core.Key : pArgs->pPrevPhys->Core.KeyLast > pCur->Core.Key),
3731	("pPrevPhys=%p %VGp-%VGp %s\n"
3732	" pCur=%p %VGp-%VGp %s\n",
3733	pArgs->pPrevPhys, pArgs->pPrevPhys->Core.Key, pArgs->pPrevPhys->Core.KeyLast, pArgs->pPrevPhys->pszDesc,
3734	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
3735	pArgs->pPrevPhys = pCur;
3736	return 0;
3737	}
3738
3739
3740	/**
3741	* Validate a node in the virtual handler tree.
3742	*
3743	* @returns 0 on if ok, other wise 1.
3744	* @param pNode The handler node.
3745	* @param pvUser pVM.
3746	*/
3747	static DECLCALLBACK(int) pgmR3CheckIntegrityVirtHandlerNode(PAVLROGCPTRNODECORE pNode, void *pvUser)
3748	{
3749	PPGMCHECKINTARGS pArgs = (PPGMCHECKINTARGS)pvUser;
3750	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)pNode;
3751	AssertReleaseReturn(!((uintptr_t)pCur & 7), 1);
3752	AssertReleaseMsg(pCur->Core.Key <= pCur->Core.KeyLast,("pCur=%p %VGv-%VGv %s\n", pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
3753	AssertReleaseMsg( !pArgs->pPrevVirt
3754	\|\| (pArgs->fLeftToRight ? pArgs->pPrevVirt->Core.KeyLast < pCur->Core.Key : pArgs->pPrevVirt->Core.KeyLast > pCur->Core.Key),
3755	("pPrevVirt=%p %VGv-%VGv %s\n"
3756	" pCur=%p %VGv-%VGv %s\n",
3757	pArgs->pPrevVirt, pArgs->pPrevVirt->Core.Key, pArgs->pPrevVirt->Core.KeyLast, pArgs->pPrevVirt->pszDesc,
3758	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
3759	for (unsigned iPage = 0; iPage < pCur->cPages; iPage++)
3760	{
3761	AssertReleaseMsg(pCur->aPhysToVirt[iPage].offVirtHandler == -RT_OFFSETOF(PGMVIRTHANDLER, aPhysToVirt[iPage]),
3762	("pCur=%p %VGv-%VGv %s\n"
3763	"iPage=%d offVirtHandle=%#x expected %#x\n",
3764	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc,
3765	iPage, pCur->aPhysToVirt[iPage].offVirtHandler, -RT_OFFSETOF(PGMVIRTHANDLER, aPhysToVirt[iPage])));
3766	}
3767	pArgs->pPrevVirt = pCur;
3768	return 0;
3769	}
3770
3771
3772	/**
3773	* Validate a node in the virtual handler tree.
3774	*
3775	* @returns 0 on if ok, other wise 1.
3776	* @param pNode The handler node.
3777	* @param pvUser pVM.
3778	*/
3779	static DECLCALLBACK(int) pgmR3CheckIntegrityPhysToVirtHandlerNode(PAVLROGCPHYSNODECORE pNode, void *pvUser)
3780	{
3781	PPGMCHECKINTARGS pArgs = (PPGMCHECKINTARGS)pvUser;
3782	PPGMPHYS2VIRTHANDLER pCur = (PPGMPHYS2VIRTHANDLER)pNode;
3783	AssertReleaseMsgReturn(!((uintptr_t)pCur & 3), ("\n"), 1);
3784	AssertReleaseMsgReturn(!(pCur->offVirtHandler & 3), ("\n"), 1);
3785	AssertReleaseMsg(pCur->Core.Key <= pCur->Core.KeyLast,("pCur=%p %VGp-%VGp\n", pCur, pCur->Core.Key, pCur->Core.KeyLast));
3786	AssertReleaseMsg( !pArgs->pPrevPhys2Virt
3787	\|\| (pArgs->fLeftToRight ? pArgs->pPrevPhys2Virt->Core.KeyLast < pCur->Core.Key : pArgs->pPrevPhys2Virt->Core.KeyLast > pCur->Core.Key),
3788	("pPrevPhys2Virt=%p %VGp-%VGp\n"
3789	" pCur=%p %VGp-%VGp\n",
3790	pArgs->pPrevPhys2Virt, pArgs->pPrevPhys2Virt->Core.Key, pArgs->pPrevPhys2Virt->Core.KeyLast,
3791	pCur, pCur->Core.Key, pCur->Core.KeyLast));
3792	AssertReleaseMsg( !pArgs->pPrevPhys2Virt
3793	\|\| (pArgs->fLeftToRight ? pArgs->pPrevPhys2Virt->Core.KeyLast < pCur->Core.Key : pArgs->pPrevPhys2Virt->Core.KeyLast > pCur->Core.Key),
3794	("pPrevPhys2Virt=%p %VGp-%VGp\n"
3795	" pCur=%p %VGp-%VGp\n",
3796	pArgs->pPrevPhys2Virt, pArgs->pPrevPhys2Virt->Core.Key, pArgs->pPrevPhys2Virt->Core.KeyLast,
3797	pCur, pCur->Core.Key, pCur->Core.KeyLast));
3798	AssertReleaseMsg((pCur->offNextAlias & (PGMPHYS2VIRTHANDLER_IN_TREE \| PGMPHYS2VIRTHANDLER_IS_HEAD)) == (PGMPHYS2VIRTHANDLER_IN_TREE \| PGMPHYS2VIRTHANDLER_IS_HEAD),
3799	("pCur=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
3800	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias));
3801	if (pCur->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK)
3802	{
3803	PPGMPHYS2VIRTHANDLER pCur2 = pCur;
3804	for (;;)
3805	{
3806	pCur2 = (PPGMPHYS2VIRTHANDLER)((intptr_t)pCur + (pCur->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK));
3807	AssertReleaseMsg(pCur2 != pCur,
3808	(" pCur=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
3809	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias));
3810	AssertReleaseMsg((pCur2->offNextAlias & (PGMPHYS2VIRTHANDLER_IN_TREE \| PGMPHYS2VIRTHANDLER_IS_HEAD)) == PGMPHYS2VIRTHANDLER_IN_TREE,
3811	(" pCur=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
3812	"pCur2=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
3813	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias,
3814	pCur2, pCur2->Core.Key, pCur2->Core.KeyLast, pCur2->offVirtHandler, pCur2->offNextAlias));
3815	AssertReleaseMsg((pCur2->Core.Key ^ pCur->Core.Key) < PAGE_SIZE,
3816	(" pCur=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
3817	"pCur2=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
3818	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias,
3819	pCur2, pCur2->Core.Key, pCur2->Core.KeyLast, pCur2->offVirtHandler, pCur2->offNextAlias));
3820	AssertReleaseMsg((pCur2->Core.KeyLast ^ pCur->Core.KeyLast) < PAGE_SIZE,
3821	(" pCur=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
3822	"pCur2=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
3823	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias,
3824	pCur2, pCur2->Core.Key, pCur2->Core.KeyLast, pCur2->offVirtHandler, pCur2->offNextAlias));
3825	if (!(pCur2->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK))
3826	break;
3827	}
3828	}
3829
3830	pArgs->pPrevPhys2Virt = pCur;
3831	return 0;
3832	}
3833
3834
3835	/**
3836	* Perform an integrity check on the PGM component.
3837	*
3838	* @returns VINF_SUCCESS if everything is fine.
3839	* @returns VBox error status after asserting on integrity breach.
3840	* @param pVM The VM handle.
3841	*/
3842	PDMR3DECL(int) PGMR3CheckIntegrity(PVM pVM)
3843	{
3844	AssertReleaseReturn(pVM->pgm.s.offVM, VERR_INTERNAL_ERROR);
3845
3846	/*
3847	* Check the trees.
3848	*/
3849	int cErrors = 0;
3850	PGMCHECKINTARGS Args = { true, NULL, NULL, NULL, pVM };
3851	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesHC->PhysHandlers, true, pgmR3CheckIntegrityPhysHandlerNode, &Args);
3852	Args.fLeftToRight = false;
3853	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesHC->PhysHandlers, false, pgmR3CheckIntegrityPhysHandlerNode, &Args);
3854	Args.fLeftToRight = true;
3855	cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesHC->VirtHandlers, true, pgmR3CheckIntegrityVirtHandlerNode, &Args);
3856	Args.fLeftToRight = false;
3857	cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesHC->VirtHandlers, false, pgmR3CheckIntegrityVirtHandlerNode, &Args);
3858	Args.fLeftToRight = true;
3859	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesHC->PhysToVirtHandlers, true, pgmR3CheckIntegrityPhysToVirtHandlerNode, &Args);
3860	Args.fLeftToRight = false;
3861	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesHC->PhysToVirtHandlers, false, pgmR3CheckIntegrityPhysToVirtHandlerNode, &Args);
3862
3863	return !cErrors ? VINF_SUCCESS : VERR_INTERNAL_ERROR;
3864	}
3865
3866
3867	/**
3868	* Inform PGM if we want all mappings to be put into the shadow page table. (necessary for e.g. VMX)
3869	*
3870	* @returns VBox status code.
3871	* @param pVM VM handle.
3872	* @param fEnable Enable or disable shadow mappings
3873	*/
3874	PGMR3DECL(int) PGMR3ChangeShwPDMappings(PVM pVM, bool fEnable)
3875	{
3876	pVM->pgm.s.fDisableMappings = !fEnable;
3877
3878	size_t cb;
3879	int rc = PGMR3MappingsSize(pVM, &cb);
3880	AssertRCReturn(rc, rc);
3881
3882	/* Pretend the mappings are now fixed; to force a refresh of the reserved PDEs. */
3883	rc = PGMR3MappingsFix(pVM, MM_HYPER_AREA_ADDRESS, cb);
3884	AssertRCReturn(rc, rc);
3885
3886	return VINF_SUCCESS;
3887	}

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source: vbox/trunk/src/VBox/VMM/PGM.cpp@ 4729

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