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1	/* $Id: PGM.cpp 10823 2008-07-23 09:04:56Z vboxsync $ */
2	/** @file
3	* PGM - Page Manager and Monitor. (Mixing stuff here, not good?)
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22
23	/** @page pg_pgm PGM - The Page Manager and Monitor
24	*
25	*
26	*
27	* @section sec_pgm_modes Paging Modes
28	*
29	* There are three memory contexts: Host Context (HC), Guest Context (GC)
30	* and intermediate context. When talking about paging HC can also be refered to
31	* as "host paging", and GC refered to as "shadow paging".
32	*
33	* We define three basic paging modes: 32-bit, PAE and AMD64. The host paging mode
34	* is defined by the host operating system. The mode used in the shadow paging mode
35	* depends on the host paging mode and what the mode the guest is currently in. The
36	* following relation between the two is defined:
37	*
38	* @verbatim
39	Host > 32-bit \| PAE \| AMD64 \|
40	Guest \| \| \| \|
41	==v================================
42	32-bit 32-bit PAE PAE
43	-------\|--------\|--------\|--------\|
44	PAE PAE PAE PAE
45	-------\|--------\|--------\|--------\|
46	AMD64 AMD64 AMD64 AMD64
47	-------\|--------\|--------\|--------\| @endverbatim
48	*
49	* All configuration except those in the diagonal (upper left) are expected to
50	* require special effort from the switcher (i.e. a bit slower).
51	*
52	*
53	*
54	*
55	* @section sec_pgm_shw The Shadow Memory Context
56	*
57	*
58	* [..]
59	*
60	* Because of guest context mappings requires PDPT and PML4 entries to allow
61	* writing on AMD64, the two upper levels will have fixed flags whatever the
62	* guest is thinking of using there. So, when shadowing the PD level we will
63	* calculate the effective flags of PD and all the higher levels. In legacy
64	* PAE mode this only applies to the PWT and PCD bits (the rest are
65	* ignored/reserved/MBZ). We will ignore those bits for the present.
66	*
67	*
68	*
69	* @section sec_pgm_int The Intermediate Memory Context
70	*
71	* The world switch goes thru an intermediate memory context which purpose it is
72	* to provide different mappings of the switcher code. All guest mappings are also
73	* present in this context.
74	*
75	* The switcher code is mapped at the same location as on the host, at an
76	* identity mapped location (physical equals virtual address), and at the
77	* hypervisor location.
78	*
79	* PGM maintain page tables for 32-bit, PAE and AMD64 paging modes. This
80	* simplifies switching guest CPU mode and consistency at the cost of more
81	* code to do the work. All memory use for those page tables is located below
82	* 4GB (this includes page tables for guest context mappings).
83	*
84	*
85	* @subsection subsec_pgm_int_gc Guest Context Mappings
86	*
87	* During assignment and relocation of a guest context mapping the intermediate
88	* memory context is used to verify the new location.
89	*
90	* Guest context mappings are currently restricted to below 4GB, for reasons
91	* of simplicity. This may change when we implement AMD64 support.
92	*
93	*
94	*
95	*
96	* @section sec_pgm_misc Misc
97	*
98	* @subsection subsec_pgm_misc_diff Differences Between Legacy PAE and Long Mode PAE
99	*
100	* The differences between legacy PAE and long mode PAE are:
101	* -# PDPE bits 1, 2, 5 and 6 are defined differently. In leagcy mode they are
102	* all marked down as must-be-zero, while in long mode 1, 2 and 5 have the
103	* usual meanings while 6 is ignored (AMD). This means that upon switching to
104	* legacy PAE mode we'll have to clear these bits and when going to long mode
105	* they must be set. This applies to both intermediate and shadow contexts,
106	* however we don't need to do it for the intermediate one since we're
107	* executing with CR0.WP at that time.
108	* -# CR3 allows a 32-byte aligned address in legacy mode, while in long mode
109	* a page aligned one is required.
110	*
111	*
112	* @section sec_pgm_handlers Access Handlers
113	*
114	* Placeholder.
115	*
116	*
117	* @subsection sec_pgm_handlers_virt Virtual Access Handlers
118	*
119	* Placeholder.
120	*
121	*
122	* @subsection sec_pgm_handlers_virt Virtual Access Handlers
123	*
124	* We currently implement three types of virtual access handlers: ALL, WRITE
125	* and HYPERVISOR (WRITE). See PGMVIRTHANDLERTYPE for some more details.
126	*
127	* The HYPERVISOR access handlers is kept in a separate tree since it doesn't apply
128	* to physical pages (PGMTREES::HyperVirtHandlers) and only needs to be consulted in
129	* a special \#PF case. The ALL and WRITE are in the PGMTREES::VirtHandlers tree, the
130	* rest of this section is going to be about these handlers.
131	*
132	* We'll go thru the life cycle of a handler and try make sense of it all, don't know
133	* how successfull this is gonna be...
134	*
135	* 1. A handler is registered thru the PGMR3HandlerVirtualRegister and
136	* PGMHandlerVirtualRegisterEx APIs. We check for conflicting virtual handlers
137	* and create a new node that is inserted into the AVL tree (range key). Then
138	* a full PGM resync is flagged (clear pool, sync cr3, update virtual bit of PGMPAGE).
139	*
140	* 2. The following PGMSyncCR3/SyncCR3 operation will first make invoke HandlerVirtualUpdate.
141	*
142	* 2a. HandlerVirtualUpdate will will lookup all the pages covered by virtual handlers
143	* via the current guest CR3 and update the physical page -> virtual handler
144	* translation. Needless to say, this doesn't exactly scale very well. If any changes
145	* are detected, it will flag a virtual bit update just like we did on registration.
146	* PGMPHYS pages with changes will have their virtual handler state reset to NONE.
147	*
148	* 2b. The virtual bit update process will iterate all the pages covered by all the
149	* virtual handlers and update the PGMPAGE virtual handler state to the max of all
150	* virtual handlers on that page.
151	*
152	* 2c. Back in SyncCR3 we will now flush the entire shadow page cache to make sure
153	* we don't miss any alias mappings of the monitored pages.
154	*
155	* 2d. SyncCR3 will then proceed with syncing the CR3 table.
156	*
157	* 3. \#PF(np,read) on a page in the range. This will cause it to be synced
158	* read-only and resumed if it's a WRITE handler. If it's an ALL handler we
159	* will call the handlers like in the next step. If the physical mapping has
160	* changed we will - some time in the future - perform a handler callback
161	* (optional) and update the physical -> virtual handler cache.
162	*
163	* 4. \#PF(,write) on a page in the range. This will cause the handler to
164	* be invoked.
165	*
166	* 5. The guest invalidates the page and changes the physical backing or
167	* unmaps it. This should cause the invalidation callback to be invoked
168	* (it might not yet be 100% perfect). Exactly what happens next... is
169	* this where we mess up and end up out of sync for a while?
170	*
171	* 6. The handler is deregistered by the client via PGMHandlerVirtualDeregister.
172	* We will then set all PGMPAGEs in the physical -> virtual handler cache for
173	* this handler to NONE and trigger a full PGM resync (basically the same
174	* as int step 1). Which means 2 is executed again.
175	*
176	*
177	* @subsubsection sub_sec_pgm_handler_virt_todo TODOs
178	*
179	* There is a bunch of things that needs to be done to make the virtual handlers
180	* work 100% correctly and work more efficiently.
181	*
182	* The first bit hasn't been implemented yet because it's going to slow the
183	* whole mess down even more, and besides it seems to be working reliably for
184	* our current uses. OTOH, some of the optimizations might end up more or less
185	* implementing the missing bits, so we'll see.
186	*
187	* On the optimization side, the first thing to do is to try avoid unnecessary
188	* cache flushing. Then try team up with the shadowing code to track changes
189	* in mappings by means of access to them (shadow in), updates to shadows pages,
190	* invlpg, and shadow PT discarding (perhaps).
191	*
192	* Some idea that have popped up for optimization for current and new features:
193	* - bitmap indicating where there are virtual handlers installed.
194	* (4KB => 220 pages, page 212 => covers 32-bit address space 1:1!)
195	* - Further optimize this by min/max (needs min/max avl getters).
196	* - Shadow page table entry bit (if any left)?
197	*
198	*/
199
200
201	/** @page pg_pgmPhys PGMPhys - Physical Guest Memory Management.
202	*
203	*
204	* Objectives:
205	* - Guest RAM over-commitment using memory ballooning,
206	* zero pages and general page sharing.
207	* - Moving or mirroring a VM onto a different physical machine.
208	*
209	*
210	* @subsection subsec_pgmPhys_Definitions Definitions
211	*
212	* Allocation chunk - A RTR0MemObjAllocPhysNC object and the tracking
213	* machinery assoicated with it.
214	*
215	*
216	*
217	*
218	* @subsection subsec_pgmPhys_AllocPage Allocating a page.
219	*
220	* Initially we map all guest memory to the (per VM) zero page, which
221	* means that none of the read functions will cause pages to be allocated.
222	*
223	* Exception, access bit in page tables that have been shared. This must
224	* be handled, but we must also make sure PGMGst*Modify doesn't make
225	* unnecessary modifications.
226	*
227	* Allocation points:
228	* - PGMPhysWriteGCPhys and PGMPhysWrite.
229	* - Replacing a zero page mapping at \#PF.
230	* - Replacing a shared page mapping at \#PF.
231	* - ROM registration (currently MMR3RomRegister).
232	* - VM restore (pgmR3Load).
233	*
234	* For the first three it would make sense to keep a few pages handy
235	* until we've reached the max memory commitment for the VM.
236	*
237	* For the ROM registration, we know exactly how many pages we need
238	* and will request these from ring-0. For restore, we will save
239	* the number of non-zero pages in the saved state and allocate
240	* them up front. This would allow the ring-0 component to refuse
241	* the request if the isn't sufficient memory available for VM use.
242	*
243	* Btw. for both ROM and restore allocations we won't be requiring
244	* zeroed pages as they are going to be filled instantly.
245	*
246	*
247	* @subsection subsec_pgmPhys_FreePage Freeing a page
248	*
249	* There are a few points where a page can be freed:
250	* - After being replaced by the zero page.
251	* - After being replaced by a shared page.
252	* - After being ballooned by the guest additions.
253	* - At reset.
254	* - At restore.
255	*
256	* When freeing one or more pages they will be returned to the ring-0
257	* component and replaced by the zero page.
258	*
259	* The reasoning for clearing out all the pages on reset is that it will
260	* return us to the exact same state as on power on, and may thereby help
261	* us reduce the memory load on the system. Further it might have a
262	* (temporary) positive influence on memory fragmentation (@see subsec_pgmPhys_Fragmentation).
263	*
264	* On restore, as mention under the allocation topic, pages should be
265	* freed / allocated depending on how many is actually required by the
266	* new VM state. The simplest approach is to do like on reset, and free
267	* all non-ROM pages and then allocate what we need.
268	*
269	* A measure to prevent some fragmentation, would be to let each allocation
270	* chunk have some affinity towards the VM having allocated the most pages
271	* from it. Also, try make sure to allocate from allocation chunks that
272	* are almost full. Admittedly, both these measures might work counter to
273	* our intentions and its probably not worth putting a lot of effort,
274	* cpu time or memory into this.
275	*
276	*
277	* @subsection subsec_pgmPhys_SharePage Sharing a page
278	*
279	* The basic idea is that there there will be a idle priority kernel
280	* thread walking the non-shared VM pages hashing them and looking for
281	* pages with the same checksum. If such pages are found, it will compare
282	* them byte-by-byte to see if they actually are identical. If found to be
283	* identical it will allocate a shared page, copy the content, check that
284	* the page didn't change while doing this, and finally request both the
285	* VMs to use the shared page instead. If the page is all zeros (special
286	* checksum and byte-by-byte check) it will request the VM that owns it
287	* to replace it with the zero page.
288	*
289	* To make this efficient, we will have to make sure not to try share a page
290	* that will change its contents soon. This part requires the most work.
291	* A simple idea would be to request the VM to write monitor the page for
292	* a while to make sure it isn't modified any time soon. Also, it may
293	* make sense to skip pages that are being write monitored since this
294	* information is readily available to the thread if it works on the
295	* per-VM guest memory structures (presently called PGMRAMRANGE).
296	*
297	*
298	* @subsection subsec_pgmPhys_Fragmentation Fragmentation Concerns and Counter Measures
299	*
300	* The pages are organized in allocation chunks in ring-0, this is a necessity
301	* if we wish to have an OS agnostic approach to this whole thing. (On Linux we
302	* could easily work on a page-by-page basis if we liked. Whether this is possible
303	* or efficient on NT I don't quite know.) Fragmentation within these chunks may
304	* become a problem as part of the idea here is that we wish to return memory to
305	* the host system.
306	*
307	* For instance, starting two VMs at the same time, they will both allocate the
308	* guest memory on-demand and if permitted their page allocations will be
309	* intermixed. Shut down one of the two VMs and it will be difficult to return
310	* any memory to the host system because the page allocation for the two VMs are
311	* mixed up in the same allocation chunks.
312	*
313	* To further complicate matters, when pages are freed because they have been
314	* ballooned or become shared/zero the whole idea is that the page is supposed
315	* to be reused by another VM or returned to the host system. This will cause
316	* allocation chunks to contain pages belonging to different VMs and prevent
317	* returning memory to the host when one of those VM shuts down.
318	*
319	* The only way to really deal with this problem is to move pages. This can
320	* either be done at VM shutdown and or by the idle priority worker thread
321	* that will be responsible for finding sharable/zero pages. The mechanisms
322	* involved for coercing a VM to move a page (or to do it for it) will be
323	* the same as when telling it to share/zero a page.
324	*
325	*
326	* @subsection subsec_pgmPhys_Tracking Tracking Structures And Their Cost
327	*
328	* There's a difficult balance between keeping the per-page tracking structures
329	* (global and guest page) easy to use and keeping them from eating too much
330	* memory. We have limited virtual memory resources available when operating in
331	* 32-bit kernel space (on 64-bit there'll it's quite a different story). The
332	* tracking structures will be attemted designed such that we can deal with up
333	* to 32GB of memory on a 32-bit system and essentially unlimited on 64-bit ones.
334	*
335	*
336	* @subsubsection subsubsec_pgmPhys_Tracking_Kernel Kernel Space
337	*
338	* @see pg_GMM
339	*
340	* @subsubsection subsubsec_pgmPhys_Tracking_PerVM Per-VM
341	*
342	* Fixed info is the physical address of the page (HCPhys) and the page id
343	* (described above). Theoretically we'll need 48(-12) bits for the HCPhys part.
344	* Today we've restricting ourselves to 40(-12) bits because this is the current
345	* restrictions of all AMD64 implementations (I think Barcelona will up this
346	* to 48(-12) bits, not that it really matters) and I needed the bits for
347	* tracking mappings of a page. 48-12 = 36. That leaves 28 bits, which means a
348	* decent range for the page id: 2^(28+12) = 1024TB.
349	*
350	* In additions to these, we'll have to keep maintaining the page flags as we
351	* currently do. Although it wouldn't harm to optimize these quite a bit, like
352	* for instance the ROM shouldn't depend on having a write handler installed
353	* in order for it to become read-only. A RO/RW bit should be considered so
354	* that the page syncing code doesn't have to mess about checking multiple
355	* flag combinations (ROM \|\| RW handler \|\| write monitored) in order to
356	* figure out how to setup a shadow PTE. But this of course, is second
357	* priority at present. Current this requires 12 bits, but could probably
358	* be optimized to ~8.
359	*
360	* Then there's the 24 bits used to track which shadow page tables are
361	* currently mapping a page for the purpose of speeding up physical
362	* access handlers, and thereby the page pool cache. More bit for this
363	* purpose wouldn't hurt IIRC.
364	*
365	* Then there is a new bit in which we need to record what kind of page
366	* this is, shared, zero, normal or write-monitored-normal. This'll
367	* require 2 bits. One bit might be needed for indicating whether a
368	* write monitored page has been written to. And yet another one or
369	* two for tracking migration status. 3-4 bits total then.
370	*
371	* Whatever is left will can be used to record the sharabilitiy of a
372	* page. The page checksum will not be stored in the per-VM table as
373	* the idle thread will not be permitted to do modifications to it.
374	* It will instead have to keep its own working set of potentially
375	* shareable pages and their check sums and stuff.
376	*
377	* For the present we'll keep the current packing of the
378	* PGMRAMRANGE::aHCPhys to keep the changes simple, only of course,
379	* we'll have to change it to a struct with a total of 128-bits at
380	* our disposal.
381	*
382	* The initial layout will be like this:
383	* @verbatim
384	RTHCPHYS HCPhys; The current stuff.
385	63:40 Current shadow PT tracking stuff.
386	39:12 The physical page frame number.
387	11:0 The current flags.
388	uint32_t u28PageId : 28; The page id.
389	uint32_t u2State : 2; The page state { zero, shared, normal, write monitored }.
390	uint32_t fWrittenTo : 1; Whether a write monitored page was written to.
391	uint32_t u1Reserved : 1; Reserved for later.
392	uint32_t u32Reserved; Reserved for later, mostly sharing stats.
393	@endverbatim
394	*
395	* The final layout will be something like this:
396	* @verbatim
397	RTHCPHYS HCPhys; The current stuff.
398	63:48 High page id (12+).
399	47:12 The physical page frame number.
400	11:0 Low page id.
401	uint32_t fReadOnly : 1; Whether it's readonly page (rom or monitored in some way).
402	uint32_t u3Type : 3; The page type {RESERVED, MMIO, MMIO2, ROM, shadowed ROM, RAM}.
403	uint32_t u2PhysMon : 2; Physical access handler type {none, read, write, all}.
404	uint32_t u2VirtMon : 2; Virtual access handler type {none, read, write, all}..
405	uint32_t u2State : 2; The page state { zero, shared, normal, write monitored }.
406	uint32_t fWrittenTo : 1; Whether a write monitored page was written to.
407	uint32_t u20Reserved : 20; Reserved for later, mostly sharing stats.
408	uint32_t u32Tracking; The shadow PT tracking stuff, roughly.
409	@endverbatim
410	*
411	* Cost wise, this means we'll double the cost for guest memory. There isn't anyway
412	* around that I'm afraid. It means that the cost of dealing out 32GB of memory
413	* to one or more VMs is: (32GB >> PAGE_SHIFT) * 16 bytes, or 128MBs. Or another
414	* example, the VM heap cost when assigning 1GB to a VM will be: 4MB.
415	*
416	* A couple of cost examples for the total cost per-VM + kernel.
417	* 32-bit Windows and 32-bit linux:
418	* 1GB guest ram, 256K pages: 4MB + 2MB(+) = 6MB
419	* 4GB guest ram, 1M pages: 16MB + 8MB(+) = 24MB
420	* 32GB guest ram, 8M pages: 128MB + 64MB(+) = 192MB
421	* 64-bit Windows and 64-bit linux:
422	* 1GB guest ram, 256K pages: 4MB + 3MB(+) = 7MB
423	* 4GB guest ram, 1M pages: 16MB + 12MB(+) = 28MB
424	* 32GB guest ram, 8M pages: 128MB + 96MB(+) = 224MB
425	*
426	* UPDATE - 2007-09-27:
427	* Will need a ballooned flag/state too because we cannot
428	* trust the guest 100% and reporting the same page as ballooned more
429	* than once will put the GMM off balance.
430	*
431	*
432	* @subsection subsec_pgmPhys_Serializing Serializing Access
433	*
434	* Initially, we'll try a simple scheme:
435	*
436	* - The per-VM RAM tracking structures (PGMRAMRANGE) is only modified
437	* by the EMT thread of that VM while in the pgm critsect.
438	* - Other threads in the VM process that needs to make reliable use of
439	* the per-VM RAM tracking structures will enter the critsect.
440	* - No process external thread or kernel thread will ever try enter
441	* the pgm critical section, as that just won't work.
442	* - The idle thread (and similar threads) doesn't not need 100% reliable
443	* data when performing it tasks as the EMT thread will be the one to
444	* do the actual changes later anyway. So, as long as it only accesses
445	* the main ram range, it can do so by somehow preventing the VM from
446	* being destroyed while it works on it...
447	*
448	* - The over-commitment management, including the allocating/freeing
449	* chunks, is serialized by a ring-0 mutex lock (a fast one since the
450	* more mundane mutex implementation is broken on Linux).
451	* - A separeate mutex is protecting the set of allocation chunks so
452	* that pages can be shared or/and freed up while some other VM is
453	* allocating more chunks. This mutex can be take from under the other
454	* one, but not the otherway around.
455	*
456	*
457	* @subsection subsec_pgmPhys_Request VM Request interface
458	*
459	* When in ring-0 it will become necessary to send requests to a VM so it can
460	* for instance move a page while defragmenting during VM destroy. The idle
461	* thread will make use of this interface to request VMs to setup shared
462	* pages and to perform write monitoring of pages.
463	*
464	* I would propose an interface similar to the current VMReq interface, similar
465	* in that it doesn't require locking and that the one sending the request may
466	* wait for completion if it wishes to. This shouldn't be very difficult to
467	* realize.
468	*
469	* The requests themselves are also pretty simple. They are basically:
470	* -# Check that some precondition is still true.
471	* -# Do the update.
472	* -# Update all shadow page tables involved with the page.
473	*
474	* The 3rd step is identical to what we're already doing when updating a
475	* physical handler, see pgmHandlerPhysicalSetRamFlagsAndFlushShadowPTs.
476	*
477	*
478	*
479	* @section sec_pgmPhys_MappingCaches Mapping Caches
480	*
481	* In order to be able to map in and out memory and to be able to support
482	* guest with more RAM than we've got virtual address space, we'll employing
483	* a mapping cache. There is already a tiny one for GC (see PGMGCDynMapGCPageEx)
484	* and we'll create a similar one for ring-0 unless we decide to setup a dedicate
485	* memory context for the HWACCM execution.
486	*
487	*
488	* @subsection subsec_pgmPhys_MappingCaches_R3 Ring-3
489	*
490	* We've considered implementing the ring-3 mapping cache page based but found
491	* that this was bother some when one had to take into account TLBs+SMP and
492	* portability (missing the necessary APIs on several platforms). There were
493	* also some performance concerns with this approach which hadn't quite been
494	* worked out.
495	*
496	* Instead, we'll be mapping allocation chunks into the VM process. This simplifies
497	* matters greatly quite a bit since we don't need to invent any new ring-0 stuff,
498	* only some minor RTR0MEMOBJ mapping stuff. The main concern here is that mapping
499	* compared to the previous idea is that mapping or unmapping a 1MB chunk is more
500	* costly than a single page, although how much more costly is uncertain. We'll
501	* try address this by using a very big cache, preferably bigger than the actual
502	* VM RAM size if possible. The current VM RAM sizes should give some idea for
503	* 32-bit boxes, while on 64-bit we can probably get away with employing an
504	* unlimited cache.
505	*
506	* The cache have to parts, as already indicated, the ring-3 side and the
507	* ring-0 side.
508	*
509	* The ring-0 will be tied to the page allocator since it will operate on the
510	* memory objects it contains. It will therefore require the first ring-0 mutex
511	* discussed in @ref subsec_pgmPhys_Serializing. We
512	* some double house keeping wrt to who has mapped what I think, since both
513	* VMMR0.r0 and RTR0MemObj will keep track of mapping relataions
514	*
515	* The ring-3 part will be protected by the pgm critsect. For simplicity, we'll
516	* require anyone that desires to do changes to the mapping cache to do that
517	* from within this critsect. Alternatively, we could employ a separate critsect
518	* for serializing changes to the mapping cache as this would reduce potential
519	* contention with other threads accessing mappings unrelated to the changes
520	* that are in process. We can see about this later, contention will show
521	* up in the statistics anyway, so it'll be simple to tell.
522	*
523	* The organization of the ring-3 part will be very much like how the allocation
524	* chunks are organized in ring-0, that is in an AVL tree by chunk id. To avoid
525	* having to walk the tree all the time, we'll have a couple of lookaside entries
526	* like in we do for I/O ports and MMIO in IOM.
527	*
528	* The simplified flow of a PGMPhysRead/Write function:
529	* -# Enter the PGM critsect.
530	* -# Lookup GCPhys in the ram ranges and get the Page ID.
531	* -# Calc the Allocation Chunk ID from the Page ID.
532	* -# Check the lookaside entries and then the AVL tree for the Chunk ID.
533	* If not found in cache:
534	* -# Call ring-0 and request it to be mapped and supply
535	* a chunk to be unmapped if the cache is maxed out already.
536	* -# Insert the new mapping into the AVL tree (id + R3 address).
537	* -# Update the relevant lookaside entry and return the mapping address.
538	* -# Do the read/write according to monitoring flags and everything.
539	* -# Leave the critsect.
540	*
541	*
542	* @section sec_pgmPhys_Fallback Fallback
543	*
544	* Current all the "second tier" hosts will not support the RTR0MemObjAllocPhysNC
545	* API and thus require a fallback.
546	*
547	* So, when RTR0MemObjAllocPhysNC returns VERR_NOT_SUPPORTED the page allocator
548	* will return to the ring-3 caller (and later ring-0) and asking it to seed
549	* the page allocator with some fresh pages (VERR_GMM_SEED_ME). Ring-3 will
550	* then perform an SUPPageAlloc(cbChunk >> PAGE_SHIFT) call and make a
551	* "SeededAllocPages" call to ring-0.
552	*
553	* The first time ring-0 sees the VERR_NOT_SUPPORTED failure it will disable
554	* all page sharing (zero page detection will continue). It will also force
555	* all allocations to come from the VM which seeded the page. Both these
556	* measures are taken to make sure that there will never be any need for
557	* mapping anything into ring-3 - everything will be mapped already.
558	*
559	* Whether we'll continue to use the current MM locked memory management
560	* for this I don't quite know (I'd prefer not to and just ditch that all
561	* togther), we'll see what's simplest to do.
562	*
563	*
564	*
565	* @section sec_pgmPhys_Changes Changes
566	*
567	* Breakdown of the changes involved?
568	*/
569
570
571	/** Saved state data unit version. */
572	#define PGM_SAVED_STATE_VERSION 6
573
574	/*******************************************************************************
575	* Header Files *
576	*******************************************************************************/
577	#define LOG_GROUP LOG_GROUP_PGM
578	#include <VBox/dbgf.h>
579	#include <VBox/pgm.h>
580	#include <VBox/cpum.h>
581	#include <VBox/iom.h>
582	#include <VBox/sup.h>
583	#include <VBox/mm.h>
584	#include <VBox/em.h>
585	#include <VBox/stam.h>
586	#include <VBox/rem.h>
587	#include <VBox/dbgf.h>
588	#include <VBox/rem.h>
589	#include <VBox/selm.h>
590	#include <VBox/ssm.h>
591	#include "PGMInternal.h"
592	#include <VBox/vm.h>
593	#include <VBox/dbg.h>
594	#include <VBox/hwaccm.h>
595
596	#include <iprt/assert.h>
597	#include <iprt/alloc.h>
598	#include <iprt/asm.h>
599	#include <iprt/thread.h>
600	#include <iprt/string.h>
601	#include <VBox/param.h>
602	#include <VBox/err.h>
603
604
605
606	/*******************************************************************************
607	* Internal Functions *
608	*******************************************************************************/
609	static int pgmR3InitPaging(PVM pVM);
610	static DECLCALLBACK(void) pgmR3PhysInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
611	static DECLCALLBACK(void) pgmR3InfoMode(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
612	static DECLCALLBACK(void) pgmR3InfoCr3(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
613	static DECLCALLBACK(int) pgmR3RelocatePhysHandler(PAVLROGCPHYSNODECORE pNode, void *pvUser);
614	static DECLCALLBACK(int) pgmR3RelocateVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser);
615	static DECLCALLBACK(int) pgmR3RelocateHyperVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser);
616	#ifdef VBOX_STRICT
617	static DECLCALLBACK(void) pgmR3ResetNoMorePhysWritesFlag(PVM pVM, VMSTATE enmState, VMSTATE enmOldState, void *pvUser);
618	#endif
619	static DECLCALLBACK(int) pgmR3Save(PVM pVM, PSSMHANDLE pSSM);
620	static DECLCALLBACK(int) pgmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version);
621	static int pgmR3ModeDataInit(PVM pVM, bool fResolveGCAndR0);
622	static void pgmR3ModeDataSwitch(PVM pVM, PGMMODE enmShw, PGMMODE enmGst);
623	static PGMMODE pgmR3CalcShadowMode(PVM pVM, PGMMODE enmGuestMode, SUPPAGINGMODE enmHostMode, PGMMODE enmShadowMode, VMMSWITCHER *penmSwitcher);
624
625	#ifdef VBOX_WITH_STATISTICS
626	static void pgmR3InitStats(PVM pVM);
627	#endif
628
629	#ifdef VBOX_WITH_DEBUGGER
630	/** @todo all but the two last commands must be converted to 'info'. */
631	static DECLCALLBACK(int) pgmR3CmdRam(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
632	static DECLCALLBACK(int) pgmR3CmdMap(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
633	static DECLCALLBACK(int) pgmR3CmdSync(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
634	static DECLCALLBACK(int) pgmR3CmdSyncAlways(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
635	static DECLCALLBACK(int) pgmR3CmdAssertCR3(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
636	#endif
637
638
639	/*******************************************************************************
640	* Global Variables *
641	*******************************************************************************/
642	#ifdef VBOX_WITH_DEBUGGER
643	/** Command descriptors. */
644	static const DBGCCMD g_aCmds[] =
645	{
646	/* pszCmd, cArgsMin, cArgsMax, paArgDesc, cArgDescs, pResultDesc, fFlags, pfnHandler pszSyntax, ....pszDescription */
647	{ "pgmram", 0, 0, NULL, 0, NULL, 0, pgmR3CmdRam, "", "Display the ram ranges." },
648	{ "pgmmap", 0, 0, NULL, 0, NULL, 0, pgmR3CmdMap, "", "Display the mapping ranges." },
649	{ "pgmsync", 0, 0, NULL, 0, NULL, 0, pgmR3CmdSync, "", "Sync the CR3 page." },
650	#ifdef VBOX_STRICT
651	{ "pgmassertcr3", 0, 0, NULL, 0, NULL, 0, pgmR3CmdAssertCR3, "", "Check the shadow CR3 mapping." },
652	#endif
653	{ "pgmsyncalways", 0, 0, NULL, 0, NULL, 0, pgmR3CmdSyncAlways, "", "Toggle permanent CR3 syncing." },
654	};
655	#endif
656
657
658
659
660	/*
661	* Shadow - 32-bit mode
662	*/
663	#define PGM_SHW_TYPE PGM_TYPE_32BIT
664	#define PGM_SHW_NAME(name) PGM_SHW_NAME_32BIT(name)
665	#define PGM_SHW_NAME_GC_STR(name) PGM_SHW_NAME_GC_32BIT_STR(name)
666	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_32BIT_STR(name)
667	#include "PGMShw.h"
668
669	/* Guest - real mode */
670	#define PGM_GST_TYPE PGM_TYPE_REAL
671	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
672	#define PGM_GST_NAME_GC_STR(name) PGM_GST_NAME_GC_REAL_STR(name)
673	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
674	#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_REAL(name)
675	#define PGM_BTH_NAME_GC_STR(name) PGM_BTH_NAME_GC_32BIT_REAL_STR(name)
676	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_32BIT_REAL_STR(name)
677	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_PHYS
678	#include "PGMGst.h"
679	#include "PGMBth.h"
680	#undef BTH_PGMPOOLKIND_PT_FOR_PT
681	#undef PGM_BTH_NAME
682	#undef PGM_BTH_NAME_GC_STR
683	#undef PGM_BTH_NAME_R0_STR
684	#undef PGM_GST_TYPE
685	#undef PGM_GST_NAME
686	#undef PGM_GST_NAME_GC_STR
687	#undef PGM_GST_NAME_R0_STR
688
689	/* Guest - protected mode */
690	#define PGM_GST_TYPE PGM_TYPE_PROT
691	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
692	#define PGM_GST_NAME_GC_STR(name) PGM_GST_NAME_GC_PROT_STR(name)
693	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
694	#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_PROT(name)
695	#define PGM_BTH_NAME_GC_STR(name) PGM_BTH_NAME_GC_32BIT_PROT_STR(name)
696	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_32BIT_PROT_STR(name)
697	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_PHYS
698	#include "PGMGst.h"
699	#include "PGMBth.h"
700	#undef BTH_PGMPOOLKIND_PT_FOR_PT
701	#undef PGM_BTH_NAME
702	#undef PGM_BTH_NAME_GC_STR
703	#undef PGM_BTH_NAME_R0_STR
704	#undef PGM_GST_TYPE
705	#undef PGM_GST_NAME
706	#undef PGM_GST_NAME_GC_STR
707	#undef PGM_GST_NAME_R0_STR
708
709	/* Guest - 32-bit mode */
710	#define PGM_GST_TYPE PGM_TYPE_32BIT
711	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
712	#define PGM_GST_NAME_GC_STR(name) PGM_GST_NAME_GC_32BIT_STR(name)
713	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
714	#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_32BIT(name)
715	#define PGM_BTH_NAME_GC_STR(name) PGM_BTH_NAME_GC_32BIT_32BIT_STR(name)
716	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_32BIT_32BIT_STR(name)
717	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT
718	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB
719	#include "PGMGst.h"
720	#include "PGMBth.h"
721	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
722	#undef BTH_PGMPOOLKIND_PT_FOR_PT
723	#undef PGM_BTH_NAME
724	#undef PGM_BTH_NAME_GC_STR
725	#undef PGM_BTH_NAME_R0_STR
726	#undef PGM_GST_TYPE
727	#undef PGM_GST_NAME
728	#undef PGM_GST_NAME_GC_STR
729	#undef PGM_GST_NAME_R0_STR
730
731	#undef PGM_SHW_TYPE
732	#undef PGM_SHW_NAME
733	#undef PGM_SHW_NAME_GC_STR
734	#undef PGM_SHW_NAME_R0_STR
735
736
737	/*
738	* Shadow - PAE mode
739	*/
740	#define PGM_SHW_TYPE PGM_TYPE_PAE
741	#define PGM_SHW_NAME(name) PGM_SHW_NAME_PAE(name)
742	#define PGM_SHW_NAME_GC_STR(name) PGM_SHW_NAME_GC_PAE_STR(name)
743	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_PAE_STR(name)
744	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_REAL(name)
745	#include "PGMShw.h"
746
747	/* Guest - real mode */
748	#define PGM_GST_TYPE PGM_TYPE_REAL
749	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
750	#define PGM_GST_NAME_GC_STR(name) PGM_GST_NAME_GC_REAL_STR(name)
751	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
752	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_REAL(name)
753	#define PGM_BTH_NAME_GC_STR(name) PGM_BTH_NAME_GC_PAE_REAL_STR(name)
754	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_REAL_STR(name)
755	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
756	#include "PGMBth.h"
757	#undef BTH_PGMPOOLKIND_PT_FOR_PT
758	#undef PGM_BTH_NAME
759	#undef PGM_BTH_NAME_GC_STR
760	#undef PGM_BTH_NAME_R0_STR
761	#undef PGM_GST_TYPE
762	#undef PGM_GST_NAME
763	#undef PGM_GST_NAME_GC_STR
764	#undef PGM_GST_NAME_R0_STR
765
766	/* Guest - protected mode */
767	#define PGM_GST_TYPE PGM_TYPE_PROT
768	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
769	#define PGM_GST_NAME_GC_STR(name) PGM_GST_NAME_GC_PROT_STR(name)
770	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
771	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_PROT(name)
772	#define PGM_BTH_NAME_GC_STR(name) PGM_BTH_NAME_GC_PAE_PROT_STR(name)
773	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_PROT_STR(name)
774	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
775	#include "PGMBth.h"
776	#undef BTH_PGMPOOLKIND_PT_FOR_PT
777	#undef PGM_BTH_NAME
778	#undef PGM_BTH_NAME_GC_STR
779	#undef PGM_BTH_NAME_R0_STR
780	#undef PGM_GST_TYPE
781	#undef PGM_GST_NAME
782	#undef PGM_GST_NAME_GC_STR
783	#undef PGM_GST_NAME_R0_STR
784
785	/* Guest - 32-bit mode */
786	#define PGM_GST_TYPE PGM_TYPE_32BIT
787	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
788	#define PGM_GST_NAME_GC_STR(name) PGM_GST_NAME_GC_32BIT_STR(name)
789	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
790	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_32BIT(name)
791	#define PGM_BTH_NAME_GC_STR(name) PGM_BTH_NAME_GC_PAE_32BIT_STR(name)
792	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_32BIT_STR(name)
793	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_32BIT_PT
794	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB
795	#include "PGMBth.h"
796	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
797	#undef BTH_PGMPOOLKIND_PT_FOR_PT
798	#undef PGM_BTH_NAME
799	#undef PGM_BTH_NAME_GC_STR
800	#undef PGM_BTH_NAME_R0_STR
801	#undef PGM_GST_TYPE
802	#undef PGM_GST_NAME
803	#undef PGM_GST_NAME_GC_STR
804	#undef PGM_GST_NAME_R0_STR
805
806	/* Guest - PAE mode */
807	#define PGM_GST_TYPE PGM_TYPE_PAE
808	#define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
809	#define PGM_GST_NAME_GC_STR(name) PGM_GST_NAME_GC_PAE_STR(name)
810	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PAE_STR(name)
811	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_PAE(name)
812	#define PGM_BTH_NAME_GC_STR(name) PGM_BTH_NAME_GC_PAE_PAE_STR(name)
813	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_PAE_STR(name)
814	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
815	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
816	#include "PGMGst.h"
817	#include "PGMBth.h"
818	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
819	#undef BTH_PGMPOOLKIND_PT_FOR_PT
820	#undef PGM_BTH_NAME
821	#undef PGM_BTH_NAME_GC_STR
822	#undef PGM_BTH_NAME_R0_STR
823	#undef PGM_GST_TYPE
824	#undef PGM_GST_NAME
825	#undef PGM_GST_NAME_GC_STR
826	#undef PGM_GST_NAME_R0_STR
827
828	#undef PGM_SHW_TYPE
829	#undef PGM_SHW_NAME
830	#undef PGM_SHW_NAME_GC_STR
831	#undef PGM_SHW_NAME_R0_STR
832
833
834	/*
835	* Shadow - AMD64 mode
836	*/
837	#define PGM_SHW_TYPE PGM_TYPE_AMD64
838	#define PGM_SHW_NAME(name) PGM_SHW_NAME_AMD64(name)
839	#define PGM_SHW_NAME_GC_STR(name) PGM_SHW_NAME_GC_AMD64_STR(name)
840	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_AMD64_STR(name)
841	#include "PGMShw.h"
842
843	/* Guest - AMD64 mode */
844	#define PGM_GST_TYPE PGM_TYPE_AMD64
845	#define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
846	#define PGM_GST_NAME_GC_STR(name) PGM_GST_NAME_GC_AMD64_STR(name)
847	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_AMD64_STR(name)
848	#define PGM_BTH_NAME(name) PGM_BTH_NAME_AMD64_AMD64(name)
849	#define PGM_BTH_NAME_GC_STR(name) PGM_BTH_NAME_GC_AMD64_AMD64_STR(name)
850	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_AMD64_AMD64_STR(name)
851	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
852	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
853	#include "PGMGst.h"
854	#include "PGMBth.h"
855	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
856	#undef BTH_PGMPOOLKIND_PT_FOR_PT
857	#undef PGM_BTH_NAME
858	#undef PGM_BTH_NAME_GC_STR
859	#undef PGM_BTH_NAME_R0_STR
860	#undef PGM_GST_TYPE
861	#undef PGM_GST_NAME
862	#undef PGM_GST_NAME_GC_STR
863	#undef PGM_GST_NAME_R0_STR
864
865	#undef PGM_SHW_TYPE
866	#undef PGM_SHW_NAME
867	#undef PGM_SHW_NAME_GC_STR
868	#undef PGM_SHW_NAME_R0_STR
869
870	/*
871	* Shadow - Nested paging mode
872	*/
873	#define PGM_SHW_TYPE PGM_TYPE_NESTED
874	#define PGM_SHW_NAME(name) PGM_SHW_NAME_NESTED(name)
875	#define PGM_SHW_NAME_GC_STR(name) PGM_SHW_NAME_GC_NESTED_STR(name)
876	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_NESTED_STR(name)
877	#include "PGMShw.h"
878
879	/* Guest - real mode */
880	#define PGM_GST_TYPE PGM_TYPE_REAL
881	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
882	#define PGM_GST_NAME_GC_STR(name) PGM_GST_NAME_GC_REAL_STR(name)
883	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
884	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_REAL(name)
885	#define PGM_BTH_NAME_GC_STR(name) PGM_BTH_NAME_GC_NESTED_REAL_STR(name)
886	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_REAL_STR(name)
887	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
888	#include "PGMBth.h"
889	#undef BTH_PGMPOOLKIND_PT_FOR_PT
890	#undef PGM_BTH_NAME
891	#undef PGM_BTH_NAME_GC_STR
892	#undef PGM_BTH_NAME_R0_STR
893	#undef PGM_GST_TYPE
894	#undef PGM_GST_NAME
895	#undef PGM_GST_NAME_GC_STR
896	#undef PGM_GST_NAME_R0_STR
897
898	/* Guest - protected mode */
899	#define PGM_GST_TYPE PGM_TYPE_PROT
900	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
901	#define PGM_GST_NAME_GC_STR(name) PGM_GST_NAME_GC_PROT_STR(name)
902	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
903	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_PROT(name)
904	#define PGM_BTH_NAME_GC_STR(name) PGM_BTH_NAME_GC_NESTED_PROT_STR(name)
905	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_PROT_STR(name)
906	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
907	#include "PGMBth.h"
908	#undef BTH_PGMPOOLKIND_PT_FOR_PT
909	#undef PGM_BTH_NAME
910	#undef PGM_BTH_NAME_GC_STR
911	#undef PGM_BTH_NAME_R0_STR
912	#undef PGM_GST_TYPE
913	#undef PGM_GST_NAME
914	#undef PGM_GST_NAME_GC_STR
915	#undef PGM_GST_NAME_R0_STR
916
917	/* Guest - 32-bit mode */
918	#define PGM_GST_TYPE PGM_TYPE_32BIT
919	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
920	#define PGM_GST_NAME_GC_STR(name) PGM_GST_NAME_GC_32BIT_STR(name)
921	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
922	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_32BIT(name)
923	#define PGM_BTH_NAME_GC_STR(name) PGM_BTH_NAME_GC_NESTED_32BIT_STR(name)
924	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_32BIT_STR(name)
925	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_32BIT_PT
926	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB
927	#include "PGMBth.h"
928	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
929	#undef BTH_PGMPOOLKIND_PT_FOR_PT
930	#undef PGM_BTH_NAME
931	#undef PGM_BTH_NAME_GC_STR
932	#undef PGM_BTH_NAME_R0_STR
933	#undef PGM_GST_TYPE
934	#undef PGM_GST_NAME
935	#undef PGM_GST_NAME_GC_STR
936	#undef PGM_GST_NAME_R0_STR
937
938	/* Guest - PAE mode */
939	#define PGM_GST_TYPE PGM_TYPE_PAE
940	#define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
941	#define PGM_GST_NAME_GC_STR(name) PGM_GST_NAME_GC_PAE_STR(name)
942	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PAE_STR(name)
943	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_PAE(name)
944	#define PGM_BTH_NAME_GC_STR(name) PGM_BTH_NAME_GC_NESTED_PAE_STR(name)
945	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_PAE_STR(name)
946	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
947	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
948	#include "PGMBth.h"
949	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
950	#undef BTH_PGMPOOLKIND_PT_FOR_PT
951	#undef PGM_BTH_NAME
952	#undef PGM_BTH_NAME_GC_STR
953	#undef PGM_BTH_NAME_R0_STR
954	#undef PGM_GST_TYPE
955	#undef PGM_GST_NAME
956	#undef PGM_GST_NAME_GC_STR
957	#undef PGM_GST_NAME_R0_STR
958
959	/* Guest - AMD64 mode */
960	#define PGM_GST_TYPE PGM_TYPE_AMD64
961	#define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
962	#define PGM_GST_NAME_GC_STR(name) PGM_GST_NAME_GC_AMD64_STR(name)
963	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_AMD64_STR(name)
964	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_AMD64(name)
965	#define PGM_BTH_NAME_GC_STR(name) PGM_BTH_NAME_GC_NESTED_AMD64_STR(name)
966	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_AMD64_STR(name)
967	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
968	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
969	#include "PGMBth.h"
970	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
971	#undef BTH_PGMPOOLKIND_PT_FOR_PT
972	#undef PGM_BTH_NAME
973	#undef PGM_BTH_NAME_GC_STR
974	#undef PGM_BTH_NAME_R0_STR
975	#undef PGM_GST_TYPE
976	#undef PGM_GST_NAME
977	#undef PGM_GST_NAME_GC_STR
978	#undef PGM_GST_NAME_R0_STR
979
980	#undef PGM_SHW_TYPE
981	#undef PGM_SHW_NAME
982	#undef PGM_SHW_NAME_GC_STR
983	#undef PGM_SHW_NAME_R0_STR
984
985
986	#ifdef PGM_WITH_EPT
987	/*
988	* Shadow - EPT
989	*/
990	#define PGM_SHW_TYPE PGM_TYPE_EPT
991	#define PGM_SHW_NAME(name) PGM_SHW_NAME_EPT(name)
992	#define PGM_SHW_NAME_GC_STR(name) PGM_SHW_NAME_GC_EPT_STR(name)
993	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_EPT_STR(name)
994	#include "PGMShw.h"
995
996	/* Guest - real mode */
997	#define PGM_GST_TYPE PGM_TYPE_REAL
998	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
999	#define PGM_GST_NAME_GC_STR(name) PGM_GST_NAME_GC_REAL_STR(name)
1000	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
1001	#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_REAL(name)
1002	#define PGM_BTH_NAME_GC_STR(name) PGM_BTH_NAME_GC_EPT_REAL_STR(name)
1003	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_REAL_STR(name)
1004	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
1005	#include "PGMBth.h"
1006	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1007	#undef PGM_BTH_NAME
1008	#undef PGM_BTH_NAME_GC_STR
1009	#undef PGM_BTH_NAME_R0_STR
1010	#undef PGM_GST_TYPE
1011	#undef PGM_GST_NAME
1012	#undef PGM_GST_NAME_GC_STR
1013	#undef PGM_GST_NAME_R0_STR
1014
1015	/* Guest - protected mode */
1016	#define PGM_GST_TYPE PGM_TYPE_PROT
1017	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
1018	#define PGM_GST_NAME_GC_STR(name) PGM_GST_NAME_GC_PROT_STR(name)
1019	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
1020	#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_PROT(name)
1021	#define PGM_BTH_NAME_GC_STR(name) PGM_BTH_NAME_GC_EPT_PROT_STR(name)
1022	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_PROT_STR(name)
1023	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
1024	#include "PGMBth.h"
1025	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1026	#undef PGM_BTH_NAME
1027	#undef PGM_BTH_NAME_GC_STR
1028	#undef PGM_BTH_NAME_R0_STR
1029	#undef PGM_GST_TYPE
1030	#undef PGM_GST_NAME
1031	#undef PGM_GST_NAME_GC_STR
1032	#undef PGM_GST_NAME_R0_STR
1033
1034	/* Guest - 32-bit mode */
1035	#define PGM_GST_TYPE PGM_TYPE_32BIT
1036	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
1037	#define PGM_GST_NAME_GC_STR(name) PGM_GST_NAME_GC_32BIT_STR(name)
1038	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
1039	#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_32BIT(name)
1040	#define PGM_BTH_NAME_GC_STR(name) PGM_BTH_NAME_GC_EPT_32BIT_STR(name)
1041	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_32BIT_STR(name)
1042	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_32BIT_PT
1043	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB
1044	#include "PGMBth.h"
1045	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
1046	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1047	#undef PGM_BTH_NAME
1048	#undef PGM_BTH_NAME_GC_STR
1049	#undef PGM_BTH_NAME_R0_STR
1050	#undef PGM_GST_TYPE
1051	#undef PGM_GST_NAME
1052	#undef PGM_GST_NAME_GC_STR
1053	#undef PGM_GST_NAME_R0_STR
1054
1055	/* Guest - PAE mode */
1056	#define PGM_GST_TYPE PGM_TYPE_PAE
1057	#define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
1058	#define PGM_GST_NAME_GC_STR(name) PGM_GST_NAME_GC_PAE_STR(name)
1059	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PAE_STR(name)
1060	#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_PAE(name)
1061	#define PGM_BTH_NAME_GC_STR(name) PGM_BTH_NAME_GC_EPT_PAE_STR(name)
1062	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_PAE_STR(name)
1063	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
1064	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
1065	#include "PGMBth.h"
1066	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
1067	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1068	#undef PGM_BTH_NAME
1069	#undef PGM_BTH_NAME_GC_STR
1070	#undef PGM_BTH_NAME_R0_STR
1071	#undef PGM_GST_TYPE
1072	#undef PGM_GST_NAME
1073	#undef PGM_GST_NAME_GC_STR
1074	#undef PGM_GST_NAME_R0_STR
1075
1076	/* Guest - AMD64 mode */
1077	#define PGM_GST_TYPE PGM_TYPE_AMD64
1078	#define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
1079	#define PGM_GST_NAME_GC_STR(name) PGM_GST_NAME_GC_AMD64_STR(name)
1080	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_AMD64_STR(name)
1081	#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_AMD64(name)
1082	#define PGM_BTH_NAME_GC_STR(name) PGM_BTH_NAME_GC_EPT_AMD64_STR(name)
1083	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_AMD64_STR(name)
1084	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
1085	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
1086	#include "PGMBth.h"
1087	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
1088	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1089	#undef PGM_BTH_NAME
1090	#undef PGM_BTH_NAME_GC_STR
1091	#undef PGM_BTH_NAME_R0_STR
1092	#undef PGM_GST_TYPE
1093	#undef PGM_GST_NAME
1094	#undef PGM_GST_NAME_GC_STR
1095	#undef PGM_GST_NAME_R0_STR
1096
1097	#undef PGM_SHW_TYPE
1098	#undef PGM_SHW_NAME
1099	#undef PGM_SHW_NAME_GC_STR
1100	#undef PGM_SHW_NAME_R0_STR
1101	#endif /* PGM_WITH_EPT */
1102
1103	/**
1104	* Initiates the paging of VM.
1105	*
1106	* @returns VBox status code.
1107	* @param pVM Pointer to VM structure.
1108	*/
1109	PGMR3DECL(int) PGMR3Init(PVM pVM)
1110	{
1111	LogFlow(("PGMR3Init:\n"));
1112
1113	/*
1114	* Assert alignment and sizes.
1115	*/
1116	AssertRelease(sizeof(pVM->pgm.s) <= sizeof(pVM->pgm.padding));
1117
1118	/*
1119	* Init the structure.
1120	*/
1121	pVM->pgm.s.offVM = RT_OFFSETOF(VM, pgm.s);
1122	pVM->pgm.s.enmShadowMode = PGMMODE_INVALID;
1123	pVM->pgm.s.enmGuestMode = PGMMODE_INVALID;
1124	pVM->pgm.s.enmHostMode = SUPPAGINGMODE_INVALID;
1125	pVM->pgm.s.GCPhysCR3 = NIL_RTGCPHYS;
1126	pVM->pgm.s.GCPhysGstCR3Monitored = NIL_RTGCPHYS;
1127	pVM->pgm.s.fA20Enabled = true;
1128	pVM->pgm.s.pGstPaePDPTHC = NULL;
1129	pVM->pgm.s.pGstPaePDPTGC = 0;
1130	for (unsigned i = 0; i < ELEMENTS(pVM->pgm.s.apGstPaePDsHC); i++)
1131	{
1132	pVM->pgm.s.apGstPaePDsHC[i] = NULL;
1133	pVM->pgm.s.apGstPaePDsGC[i] = 0;
1134	pVM->pgm.s.aGCPhysGstPaePDs[i] = NIL_RTGCPHYS;
1135	pVM->pgm.s.aGCPhysGstPaePDsMonitored[i] = NIL_RTGCPHYS;
1136	}
1137
1138	#ifdef VBOX_STRICT
1139	VMR3AtStateRegister(pVM, pgmR3ResetNoMorePhysWritesFlag, NULL);
1140	#endif
1141
1142	/*
1143	* Get the configured RAM size - to estimate saved state size.
1144	*/
1145	uint64_t cbRam;
1146	int rc = CFGMR3QueryU64(CFGMR3GetRoot(pVM), "RamSize", &cbRam);
1147	if (rc == VERR_CFGM_VALUE_NOT_FOUND)
1148	cbRam = pVM->pgm.s.cbRamSize = 0;
1149	else if (VBOX_SUCCESS(rc))
1150	{
1151	if (cbRam < PAGE_SIZE)
1152	cbRam = 0;
1153	cbRam = RT_ALIGN_64(cbRam, PAGE_SIZE);
1154	pVM->pgm.s.cbRamSize = (RTUINT)cbRam;
1155	}
1156	else
1157	{
1158	AssertMsgFailed(("Configuration error: Failed to query integer \"RamSize\", rc=%Vrc.\n", rc));
1159	return rc;
1160	}
1161
1162	/*
1163	* Register saved state data unit.
1164	*/
1165	rc = SSMR3RegisterInternal(pVM, "pgm", 1, PGM_SAVED_STATE_VERSION, (size_t)cbRam + sizeof(PGM),
1166	NULL, pgmR3Save, NULL,
1167	NULL, pgmR3Load, NULL);
1168	if (VBOX_FAILURE(rc))
1169	return rc;
1170
1171	/*
1172	* Initialize the PGM critical section and flush the phys TLBs
1173	*/
1174	rc = PDMR3CritSectInit(pVM, &pVM->pgm.s.CritSect, "PGM");
1175	AssertRCReturn(rc, rc);
1176
1177	PGMR3PhysChunkInvalidateTLB(pVM);
1178	PGMPhysInvalidatePageR3MapTLB(pVM);
1179	PGMPhysInvalidatePageR0MapTLB(pVM);
1180	PGMPhysInvalidatePageGCMapTLB(pVM);
1181
1182	/*
1183	* Trees
1184	*/
1185	rc = MMHyperAlloc(pVM, sizeof(PGMTREES), 0, MM_TAG_PGM, (void **)&pVM->pgm.s.pTreesHC);
1186	if (VBOX_SUCCESS(rc))
1187	{
1188	pVM->pgm.s.pTreesGC = MMHyperHC2GC(pVM, pVM->pgm.s.pTreesHC);
1189
1190	/*
1191	* Alocate the zero page.
1192	*/
1193	rc = MMHyperAlloc(pVM, PAGE_SIZE, PAGE_SIZE, MM_TAG_PGM, &pVM->pgm.s.pvZeroPgR3);
1194	}
1195	if (VBOX_SUCCESS(rc))
1196	{
1197	pVM->pgm.s.pvZeroPgGC = MMHyperR3ToGC(pVM, pVM->pgm.s.pvZeroPgR3);
1198	pVM->pgm.s.pvZeroPgR0 = MMHyperR3ToR0(pVM, pVM->pgm.s.pvZeroPgR3);
1199	AssertRelease(pVM->pgm.s.pvZeroPgR0 != NIL_RTHCPHYS);
1200	pVM->pgm.s.HCPhysZeroPg = MMR3HyperHCVirt2HCPhys(pVM, pVM->pgm.s.pvZeroPgR3);
1201	AssertRelease(pVM->pgm.s.HCPhysZeroPg != NIL_RTHCPHYS);
1202
1203	/*
1204	* Init the paging.
1205	*/
1206	rc = pgmR3InitPaging(pVM);
1207	}
1208	if (VBOX_SUCCESS(rc))
1209	{
1210	/*
1211	* Init the page pool.
1212	*/
1213	rc = pgmR3PoolInit(pVM);
1214	}
1215	if (VBOX_SUCCESS(rc))
1216	{
1217	/*
1218	* Info & statistics
1219	*/
1220	DBGFR3InfoRegisterInternal(pVM, "mode",
1221	"Shows the current paging mode. "
1222	"Recognizes 'all', 'guest', 'shadow' and 'host' as arguments, defaulting to 'all' if nothing's given.",
1223	pgmR3InfoMode);
1224	DBGFR3InfoRegisterInternal(pVM, "pgmcr3",
1225	"Dumps all the entries in the top level paging table. No arguments.",
1226	pgmR3InfoCr3);
1227	DBGFR3InfoRegisterInternal(pVM, "phys",
1228	"Dumps all the physical address ranges. No arguments.",
1229	pgmR3PhysInfo);
1230	DBGFR3InfoRegisterInternal(pVM, "handlers",
1231	"Dumps physical, virtual and hyper virtual handlers. "
1232	"Pass 'phys', 'virt', 'hyper' as argument if only one kind is wanted."
1233	"Add 'nost' if the statistics are unwanted, use together with 'all' or explicit selection.",
1234	pgmR3InfoHandlers);
1235	DBGFR3InfoRegisterInternal(pVM, "mappings",
1236	"Dumps guest mappings.",
1237	pgmR3MapInfo);
1238
1239	STAM_REL_REG(pVM, &pVM->pgm.s.cGuestModeChanges, STAMTYPE_COUNTER, "/PGM/cGuestModeChanges", STAMUNIT_OCCURENCES, "Number of guest mode changes.");
1240	#ifdef VBOX_WITH_STATISTICS
1241	pgmR3InitStats(pVM);
1242	#endif
1243	#ifdef VBOX_WITH_DEBUGGER
1244	/*
1245	* Debugger commands.
1246	*/
1247	static bool fRegisteredCmds = false;
1248	if (!fRegisteredCmds)
1249	{
1250	int rc = DBGCRegisterCommands(&g_aCmds[0], ELEMENTS(g_aCmds));
1251	if (VBOX_SUCCESS(rc))
1252	fRegisteredCmds = true;
1253	}
1254	#endif
1255	return VINF_SUCCESS;
1256	}
1257
1258	/* Almost no cleanup necessary, MM frees all memory. */
1259	PDMR3CritSectDelete(&pVM->pgm.s.CritSect);
1260
1261	return rc;
1262	}
1263
1264
1265	/**
1266	* Init paging.
1267	*
1268	* Since we need to check what mode the host is operating in before we can choose
1269	* the right paging functions for the host we have to delay this until R0 has
1270	* been initialized.
1271	*
1272	* @returns VBox status code.
1273	* @param pVM VM handle.
1274	*/
1275	static int pgmR3InitPaging(PVM pVM)
1276	{
1277	/*
1278	* Force a recalculation of modes and switcher so everyone gets notified.
1279	*/
1280	pVM->pgm.s.enmShadowMode = PGMMODE_INVALID;
1281	pVM->pgm.s.enmGuestMode = PGMMODE_INVALID;
1282	pVM->pgm.s.enmHostMode = SUPPAGINGMODE_INVALID;
1283
1284	/*
1285	* Allocate static mapping space for whatever the cr3 register
1286	* points to and in the case of PAE mode to the 4 PDs.
1287	*/
1288	int rc = MMR3HyperReserve(pVM, PAGE_SIZE * 5, "CR3 mapping", &pVM->pgm.s.GCPtrCR3Mapping);
1289	if (VBOX_FAILURE(rc))
1290	{
1291	AssertMsgFailed(("Failed to reserve two pages for cr mapping in HMA, rc=%Vrc\n", rc));
1292	return rc;
1293	}
1294	MMR3HyperReserve(pVM, PAGE_SIZE, "fence", NULL);
1295
1296	/*
1297	* Allocate pages for the three possible intermediate contexts
1298	* (AMD64, PAE and plain 32-Bit). We maintain all three contexts
1299	* for the sake of simplicity. The AMD64 uses the PAE for the
1300	* lower levels, making the total number of pages 11 (3 + 7 + 1).
1301	*
1302	* We assume that two page tables will be enought for the core code
1303	* mappings (HC virtual and identity).
1304	*/
1305	pVM->pgm.s.pInterPD = (PX86PD)MMR3PageAllocLow(pVM);
1306	pVM->pgm.s.apInterPTs[0] = (PX86PT)MMR3PageAllocLow(pVM);
1307	pVM->pgm.s.apInterPTs[1] = (PX86PT)MMR3PageAllocLow(pVM);
1308	pVM->pgm.s.apInterPaePTs[0] = (PX86PTPAE)MMR3PageAlloc(pVM);
1309	pVM->pgm.s.apInterPaePTs[1] = (PX86PTPAE)MMR3PageAlloc(pVM);
1310	pVM->pgm.s.apInterPaePDs[0] = (PX86PDPAE)MMR3PageAlloc(pVM);
1311	pVM->pgm.s.apInterPaePDs[1] = (PX86PDPAE)MMR3PageAlloc(pVM);
1312	pVM->pgm.s.apInterPaePDs[2] = (PX86PDPAE)MMR3PageAlloc(pVM);
1313	pVM->pgm.s.apInterPaePDs[3] = (PX86PDPAE)MMR3PageAlloc(pVM);
1314	pVM->pgm.s.pInterPaePDPT = (PX86PDPT)MMR3PageAllocLow(pVM);
1315	pVM->pgm.s.pInterPaePDPT64 = (PX86PDPT)MMR3PageAllocLow(pVM);
1316	pVM->pgm.s.pInterPaePML4 = (PX86PML4)MMR3PageAllocLow(pVM);
1317	if ( !pVM->pgm.s.pInterPD
1318	\|\| !pVM->pgm.s.apInterPTs[0]
1319	\|\| !pVM->pgm.s.apInterPTs[1]
1320	\|\| !pVM->pgm.s.apInterPaePTs[0]
1321	\|\| !pVM->pgm.s.apInterPaePTs[1]
1322	\|\| !pVM->pgm.s.apInterPaePDs[0]
1323	\|\| !pVM->pgm.s.apInterPaePDs[1]
1324	\|\| !pVM->pgm.s.apInterPaePDs[2]
1325	\|\| !pVM->pgm.s.apInterPaePDs[3]
1326	\|\| !pVM->pgm.s.pInterPaePDPT
1327	\|\| !pVM->pgm.s.pInterPaePDPT64
1328	\|\| !pVM->pgm.s.pInterPaePML4)
1329	{
1330	AssertMsgFailed(("Failed to allocate pages for the intermediate context!\n"));
1331	return VERR_NO_PAGE_MEMORY;
1332	}
1333
1334	pVM->pgm.s.HCPhysInterPD = MMPage2Phys(pVM, pVM->pgm.s.pInterPD);
1335	AssertRelease(pVM->pgm.s.HCPhysInterPD != NIL_RTHCPHYS && !(pVM->pgm.s.HCPhysInterPD & PAGE_OFFSET_MASK));
1336	pVM->pgm.s.HCPhysInterPaePDPT = MMPage2Phys(pVM, pVM->pgm.s.pInterPaePDPT);
1337	AssertRelease(pVM->pgm.s.HCPhysInterPaePDPT != NIL_RTHCPHYS && !(pVM->pgm.s.HCPhysInterPaePDPT & PAGE_OFFSET_MASK));
1338	pVM->pgm.s.HCPhysInterPaePML4 = MMPage2Phys(pVM, pVM->pgm.s.pInterPaePML4);
1339	AssertRelease(pVM->pgm.s.HCPhysInterPaePML4 != NIL_RTHCPHYS && !(pVM->pgm.s.HCPhysInterPaePML4 & PAGE_OFFSET_MASK));
1340
1341	/*
1342	* Initialize the pages, setting up the PML4 and PDPT for repetitive 4GB action.
1343	*/
1344	ASMMemZeroPage(pVM->pgm.s.pInterPD);
1345	ASMMemZeroPage(pVM->pgm.s.apInterPTs[0]);
1346	ASMMemZeroPage(pVM->pgm.s.apInterPTs[1]);
1347
1348	ASMMemZeroPage(pVM->pgm.s.apInterPaePTs[0]);
1349	ASMMemZeroPage(pVM->pgm.s.apInterPaePTs[1]);
1350
1351	ASMMemZeroPage(pVM->pgm.s.pInterPaePDPT);
1352	for (unsigned i = 0; i < ELEMENTS(pVM->pgm.s.apInterPaePDs); i++)
1353	{
1354	ASMMemZeroPage(pVM->pgm.s.apInterPaePDs[i]);
1355	pVM->pgm.s.pInterPaePDPT->a[i].u = X86_PDPE_P \| PGM_PLXFLAGS_PERMANENT
1356	\| MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[i]);
1357	}
1358
1359	for (unsigned i = 0; i < ELEMENTS(pVM->pgm.s.pInterPaePDPT64->a); i++)
1360	{
1361	const unsigned iPD = i % ELEMENTS(pVM->pgm.s.apInterPaePDs);
1362	pVM->pgm.s.pInterPaePDPT64->a[i].u = X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_A \| PGM_PLXFLAGS_PERMANENT
1363	\| MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[iPD]);
1364	}
1365
1366	RTHCPHYS HCPhysInterPaePDPT64 = MMPage2Phys(pVM, pVM->pgm.s.pInterPaePDPT64);
1367	for (unsigned i = 0; i < ELEMENTS(pVM->pgm.s.pInterPaePML4->a); i++)
1368	pVM->pgm.s.pInterPaePML4->a[i].u = X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_A \| PGM_PLXFLAGS_PERMANENT
1369	\| HCPhysInterPaePDPT64;
1370
1371	/*
1372	* Allocate pages for the three possible guest contexts (AMD64, PAE and plain 32-Bit).
1373	* We allocate pages for all three posibilities to in order to simplify mappings and
1374	* avoid resource failure during mode switches. So, we need to cover all levels of the
1375	* of the first 4GB down to PD level.
1376	* As with the intermediate context, AMD64 uses the PAE PDPT and PDs.
1377	*/
1378	pVM->pgm.s.pHC32BitPD = (PX86PD)MMR3PageAllocLow(pVM);
1379	pVM->pgm.s.apHCPaePDs[0] = (PX86PDPAE)MMR3PageAlloc(pVM);
1380	pVM->pgm.s.apHCPaePDs[1] = (PX86PDPAE)MMR3PageAlloc(pVM);
1381	AssertRelease((uintptr_t)pVM->pgm.s.apHCPaePDs[0] + PAGE_SIZE == (uintptr_t)pVM->pgm.s.apHCPaePDs[1]);
1382	pVM->pgm.s.apHCPaePDs[2] = (PX86PDPAE)MMR3PageAlloc(pVM);
1383	AssertRelease((uintptr_t)pVM->pgm.s.apHCPaePDs[1] + PAGE_SIZE == (uintptr_t)pVM->pgm.s.apHCPaePDs[2]);
1384	pVM->pgm.s.apHCPaePDs[3] = (PX86PDPAE)MMR3PageAlloc(pVM);
1385	AssertRelease((uintptr_t)pVM->pgm.s.apHCPaePDs[2] + PAGE_SIZE == (uintptr_t)pVM->pgm.s.apHCPaePDs[3]);
1386	pVM->pgm.s.pHCPaePDPT = (PX86PDPT)MMR3PageAllocLow(pVM);
1387	pVM->pgm.s.pHCNestedRoot = MMR3PageAllocLow(pVM);
1388
1389	if ( !pVM->pgm.s.pHC32BitPD
1390	\|\| !pVM->pgm.s.apHCPaePDs[0]
1391	\|\| !pVM->pgm.s.apHCPaePDs[1]
1392	\|\| !pVM->pgm.s.apHCPaePDs[2]
1393	\|\| !pVM->pgm.s.apHCPaePDs[3]
1394	\|\| !pVM->pgm.s.pHCPaePDPT
1395	\|\| !pVM->pgm.s.pHCNestedRoot)
1396	{
1397	AssertMsgFailed(("Failed to allocate pages for the intermediate context!\n"));
1398	return VERR_NO_PAGE_MEMORY;
1399	}
1400
1401	/* get physical addresses. */
1402	pVM->pgm.s.HCPhys32BitPD = MMPage2Phys(pVM, pVM->pgm.s.pHC32BitPD);
1403	Assert(MMPagePhys2Page(pVM, pVM->pgm.s.HCPhys32BitPD) == pVM->pgm.s.pHC32BitPD);
1404	pVM->pgm.s.aHCPhysPaePDs[0] = MMPage2Phys(pVM, pVM->pgm.s.apHCPaePDs[0]);
1405	pVM->pgm.s.aHCPhysPaePDs[1] = MMPage2Phys(pVM, pVM->pgm.s.apHCPaePDs[1]);
1406	pVM->pgm.s.aHCPhysPaePDs[2] = MMPage2Phys(pVM, pVM->pgm.s.apHCPaePDs[2]);
1407	pVM->pgm.s.aHCPhysPaePDs[3] = MMPage2Phys(pVM, pVM->pgm.s.apHCPaePDs[3]);
1408	pVM->pgm.s.HCPhysPaePDPT = MMPage2Phys(pVM, pVM->pgm.s.pHCPaePDPT);
1409	pVM->pgm.s.HCPhysNestedRoot = MMPage2Phys(pVM, pVM->pgm.s.pHCNestedRoot);
1410
1411	/*
1412	* Initialize the pages, setting up the PML4 and PDPT for action below 4GB.
1413	*/
1414	ASMMemZero32(pVM->pgm.s.pHC32BitPD, PAGE_SIZE);
1415	ASMMemZero32(pVM->pgm.s.pHCPaePDPT, PAGE_SIZE);
1416	ASMMemZero32(pVM->pgm.s.pHCNestedRoot, PAGE_SIZE);
1417	for (unsigned i = 0; i < ELEMENTS(pVM->pgm.s.apHCPaePDs); i++)
1418	{
1419	ASMMemZero32(pVM->pgm.s.apHCPaePDs[i], PAGE_SIZE);
1420	pVM->pgm.s.pHCPaePDPT->a[i].u = X86_PDPE_P \| PGM_PLXFLAGS_PERMANENT \| pVM->pgm.s.aHCPhysPaePDs[i];
1421	/* The flags will be corrected when entering and leaving long mode. */
1422	}
1423
1424	CPUMSetHyperCR3(pVM, (uint32_t)pVM->pgm.s.HCPhys32BitPD);
1425
1426	/*
1427	* Initialize paging workers and mode from current host mode
1428	* and the guest running in real mode.
1429	*/
1430	pVM->pgm.s.enmHostMode = SUPGetPagingMode();
1431	switch (pVM->pgm.s.enmHostMode)
1432	{
1433	case SUPPAGINGMODE_32_BIT:
1434	case SUPPAGINGMODE_32_BIT_GLOBAL:
1435	case SUPPAGINGMODE_PAE:
1436	case SUPPAGINGMODE_PAE_GLOBAL:
1437	case SUPPAGINGMODE_PAE_NX:
1438	case SUPPAGINGMODE_PAE_GLOBAL_NX:
1439	break;
1440
1441	case SUPPAGINGMODE_AMD64:
1442	case SUPPAGINGMODE_AMD64_GLOBAL:
1443	case SUPPAGINGMODE_AMD64_NX:
1444	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
1445	#ifndef VBOX_WITH_HYBIRD_32BIT_KERNEL
1446	if (ARCH_BITS != 64)
1447	{
1448	AssertMsgFailed(("Host mode %d (64-bit) is not supported by non-64bit builds\n", pVM->pgm.s.enmHostMode));
1449	LogRel(("Host mode %d (64-bit) is not supported by non-64bit builds\n", pVM->pgm.s.enmHostMode));
1450	return VERR_PGM_UNSUPPORTED_HOST_PAGING_MODE;
1451	}
1452	#endif
1453	break;
1454	default:
1455	AssertMsgFailed(("Host mode %d is not supported\n", pVM->pgm.s.enmHostMode));
1456	return VERR_PGM_UNSUPPORTED_HOST_PAGING_MODE;
1457	}
1458	rc = pgmR3ModeDataInit(pVM, false /* don't resolve GC and R0 syms yet */);
1459	if (VBOX_SUCCESS(rc))
1460	rc = PGMR3ChangeMode(pVM, PGMMODE_REAL);
1461	if (VBOX_SUCCESS(rc))
1462	{
1463	LogFlow(("pgmR3InitPaging: returns successfully\n"));
1464	#if HC_ARCH_BITS == 64
1465	LogRel(("Debug: HCPhys32BitPD=%VHp aHCPhysPaePDs={%VHp,%VHp,%VHp,%VHp} HCPhysPaePDPT=%VHp HCPhysPaePML4=%VHp\n",
1466	pVM->pgm.s.HCPhys32BitPD, pVM->pgm.s.aHCPhysPaePDs[0], pVM->pgm.s.aHCPhysPaePDs[1], pVM->pgm.s.aHCPhysPaePDs[2], pVM->pgm.s.aHCPhysPaePDs[3],
1467	pVM->pgm.s.HCPhysPaePDPT, pVM->pgm.s.HCPhysPaePML4));
1468	LogRel(("Debug: HCPhysInterPD=%VHp HCPhysInterPaePDPT=%VHp HCPhysInterPaePML4=%VHp\n",
1469	pVM->pgm.s.HCPhysInterPD, pVM->pgm.s.HCPhysInterPaePDPT, pVM->pgm.s.HCPhysInterPaePML4));
1470	LogRel(("Debug: apInterPTs={%VHp,%VHp} apInterPaePTs={%VHp,%VHp} apInterPaePDs={%VHp,%VHp,%VHp,%VHp} pInterPaePDPT64=%VHp\n",
1471	MMPage2Phys(pVM, pVM->pgm.s.apInterPTs[0]), MMPage2Phys(pVM, pVM->pgm.s.apInterPTs[1]),
1472	MMPage2Phys(pVM, pVM->pgm.s.apInterPaePTs[0]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePTs[1]),
1473	MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[0]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[1]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[2]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[3]),
1474	MMPage2Phys(pVM, pVM->pgm.s.pInterPaePDPT64)));
1475	#endif
1476
1477	return VINF_SUCCESS;
1478	}
1479
1480	LogFlow(("pgmR3InitPaging: returns %Vrc\n", rc));
1481	return rc;
1482	}
1483
1484
1485	#ifdef VBOX_WITH_STATISTICS
1486	/**
1487	* Init statistics
1488	*/
1489	static void pgmR3InitStats(PVM pVM)
1490	{
1491	PPGM pPGM = &pVM->pgm.s;
1492	STAM_REG(pVM, &pPGM->StatGCInvalidatePage, STAMTYPE_PROFILE, "/PGM/GC/InvalidatePage", STAMUNIT_TICKS_PER_CALL, "PGMGCInvalidatePage() profiling.");
1493	STAM_REG(pVM, &pPGM->StatGCInvalidatePage4KBPages, STAMTYPE_COUNTER, "/PGM/GC/InvalidatePage/4KBPages", STAMUNIT_OCCURENCES, "The number of times PGMGCInvalidatePage() was called for a 4KB page.");
1494	STAM_REG(pVM, &pPGM->StatGCInvalidatePage4MBPages, STAMTYPE_COUNTER, "/PGM/GC/InvalidatePage/4MBPages", STAMUNIT_OCCURENCES, "The number of times PGMGCInvalidatePage() was called for a 4MB page.");
1495	STAM_REG(pVM, &pPGM->StatGCInvalidatePage4MBPagesSkip, STAMTYPE_COUNTER, "/PGM/GC/InvalidatePage/4MBPagesSkip",STAMUNIT_OCCURENCES, "The number of times PGMGCInvalidatePage() skipped a 4MB page.");
1496	STAM_REG(pVM, &pPGM->StatGCInvalidatePagePDMappings, STAMTYPE_COUNTER, "/PGM/GC/InvalidatePage/PDMappings", STAMUNIT_OCCURENCES, "The number of times PGMGCInvalidatePage() was called for a page directory containing mappings (no conflict).");
1497	STAM_REG(pVM, &pPGM->StatGCInvalidatePagePDNAs, STAMTYPE_COUNTER, "/PGM/GC/InvalidatePage/PDNAs", STAMUNIT_OCCURENCES, "The number of times PGMGCInvalidatePage() was called for a not accessed page directory.");
1498	STAM_REG(pVM, &pPGM->StatGCInvalidatePagePDNPs, STAMTYPE_COUNTER, "/PGM/GC/InvalidatePage/PDNPs", STAMUNIT_OCCURENCES, "The number of times PGMGCInvalidatePage() was called for a not present page directory.");
1499	STAM_REG(pVM, &pPGM->StatGCInvalidatePagePDOutOfSync, STAMTYPE_COUNTER, "/PGM/GC/InvalidatePage/PDOutOfSync", STAMUNIT_OCCURENCES, "The number of times PGMGCInvalidatePage() was called for an out of sync page directory.");
1500	STAM_REG(pVM, &pPGM->StatGCInvalidatePageSkipped, STAMTYPE_COUNTER, "/PGM/GC/InvalidatePage/Skipped", STAMUNIT_OCCURENCES, "The number of times PGMGCInvalidatePage() was skipped due to not present shw or pending pending SyncCR3.");
1501	STAM_REG(pVM, &pPGM->StatGCSyncPT, STAMTYPE_PROFILE, "/PGM/GC/SyncPT", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMGCSyncPT() body.");
1502	STAM_REG(pVM, &pPGM->StatGCAccessedPage, STAMTYPE_COUNTER, "/PGM/GC/AccessedPage", STAMUNIT_OCCURENCES, "The number of pages marked not present for accessed bit emulation.");
1503	STAM_REG(pVM, &pPGM->StatGCDirtyPage, STAMTYPE_COUNTER, "/PGM/GC/DirtyPage/Mark", STAMUNIT_OCCURENCES, "The number of pages marked read-only for dirty bit tracking.");
1504	STAM_REG(pVM, &pPGM->StatGCDirtyPageBig, STAMTYPE_COUNTER, "/PGM/GC/DirtyPage/MarkBig", STAMUNIT_OCCURENCES, "The number of 4MB pages marked read-only for dirty bit tracking.");
1505	STAM_REG(pVM, &pPGM->StatGCDirtyPageTrap, STAMTYPE_COUNTER, "/PGM/GC/DirtyPage/Trap", STAMUNIT_OCCURENCES, "The number of traps generated for dirty bit tracking.");
1506	STAM_REG(pVM, &pPGM->StatGCDirtyPageSkipped, STAMTYPE_COUNTER, "/PGM/GC/DirtyPage/Skipped", STAMUNIT_OCCURENCES, "The number of pages already dirty or readonly.");
1507	STAM_REG(pVM, &pPGM->StatGCDirtiedPage, STAMTYPE_COUNTER, "/PGM/GC/DirtyPage/SetDirty", STAMUNIT_OCCURENCES, "The number of pages marked dirty because of write accesses.");
1508	STAM_REG(pVM, &pPGM->StatGCDirtyTrackRealPF, STAMTYPE_COUNTER, "/PGM/GC/DirtyPage/RealPF", STAMUNIT_OCCURENCES, "The number of real pages faults during dirty bit tracking.");
1509	STAM_REG(pVM, &pPGM->StatGCPageAlreadyDirty, STAMTYPE_COUNTER, "/PGM/GC/DirtyPage/AlreadySet", STAMUNIT_OCCURENCES, "The number of pages already marked dirty because of write accesses.");
1510	STAM_REG(pVM, &pPGM->StatGCDirtyBitTracking, STAMTYPE_PROFILE, "/PGM/GC/DirtyPage", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMTrackDirtyBit() body.");
1511	STAM_REG(pVM, &pPGM->StatGCSyncPTAlloc, STAMTYPE_COUNTER, "/PGM/GC/SyncPT/Alloc", STAMUNIT_OCCURENCES, "The number of times PGMGCSyncPT() needed to allocate page tables.");
1512	STAM_REG(pVM, &pPGM->StatGCSyncPTConflict, STAMTYPE_COUNTER, "/PGM/GC/SyncPT/Conflicts", STAMUNIT_OCCURENCES, "The number of times PGMGCSyncPT() detected conflicts.");
1513	STAM_REG(pVM, &pPGM->StatGCSyncPTFailed, STAMTYPE_COUNTER, "/PGM/GC/SyncPT/Failed", STAMUNIT_OCCURENCES, "The number of times PGMGCSyncPT() failed.");
1514
1515	STAM_REG(pVM, &pPGM->StatGCTrap0e, STAMTYPE_PROFILE, "/PGM/GC/Trap0e", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMGCTrap0eHandler() body.");
1516	STAM_REG(pVM, &pPGM->StatCheckPageFault, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time/CheckPageFault", STAMUNIT_TICKS_PER_CALL, "Profiling of checking for dirty/access emulation faults.");
1517	STAM_REG(pVM, &pPGM->StatLazySyncPT, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time/SyncPT", STAMUNIT_TICKS_PER_CALL, "Profiling of lazy page table syncing.");
1518	STAM_REG(pVM, &pPGM->StatMapping, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time/Mapping", STAMUNIT_TICKS_PER_CALL, "Profiling of checking virtual mappings.");
1519	STAM_REG(pVM, &pPGM->StatOutOfSync, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time/OutOfSync", STAMUNIT_TICKS_PER_CALL, "Profiling of out of sync page handling.");
1520	STAM_REG(pVM, &pPGM->StatHandlers, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time/Handlers", STAMUNIT_TICKS_PER_CALL, "Profiling of checking handlers.");
1521	STAM_REG(pVM, &pPGM->StatEIPHandlers, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time/EIPHandlers", STAMUNIT_TICKS_PER_CALL, "Profiling of checking eip handlers.");
1522	STAM_REG(pVM, &pPGM->StatTrap0eCSAM, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time2/CSAM", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is CSAM.");
1523	STAM_REG(pVM, &pPGM->StatTrap0eDirtyAndAccessedBits, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time2/DirtyAndAccessedBits", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is dirty and/or accessed bit emulation.");
1524	STAM_REG(pVM, &pPGM->StatTrap0eGuestTrap, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time2/GuestTrap", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is a guest trap.");
1525	STAM_REG(pVM, &pPGM->StatTrap0eHndPhys, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time2/HandlerPhysical", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is a physical handler.");
1526	STAM_REG(pVM, &pPGM->StatTrap0eHndVirt, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time2/HandlerVirtual",STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is a virtual handler.");
1527	STAM_REG(pVM, &pPGM->StatTrap0eHndUnhandled, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time2/HandlerUnhandled", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is access outside the monitored areas of a monitored page.");
1528	STAM_REG(pVM, &pPGM->StatTrap0eMisc, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time2/Misc", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is not known.");
1529	STAM_REG(pVM, &pPGM->StatTrap0eOutOfSync, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time2/OutOfSync", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is an out-of-sync page.");
1530	STAM_REG(pVM, &pPGM->StatTrap0eOutOfSyncHndPhys, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time2/OutOfSyncHndPhys", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is an out-of-sync physical handler page.");
1531	STAM_REG(pVM, &pPGM->StatTrap0eOutOfSyncHndVirt, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time2/OutOfSyncHndVirt", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is an out-of-sync virtual handler page.");
1532	STAM_REG(pVM, &pPGM->StatTrap0eOutOfSyncObsHnd, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time2/OutOfSyncObsHnd", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is an obsolete handler page.");
1533	STAM_REG(pVM, &pPGM->StatTrap0eSyncPT, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time2/SyncPT", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is lazy syncing of a PT.");
1534
1535	STAM_REG(pVM, &pPGM->StatTrap0eMapHandler, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/Handlers/Mapping", STAMUNIT_OCCURENCES, "Number of traps due to access handlers in mappings.");
1536	STAM_REG(pVM, &pPGM->StatHandlersOutOfSync, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/Handlers/OutOfSync", STAMUNIT_OCCURENCES, "Number of traps due to out-of-sync handled pages.");
1537	STAM_REG(pVM, &pPGM->StatHandlersPhysical, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/Handlers/Physical", STAMUNIT_OCCURENCES, "Number of traps due to physical access handlers.");
1538	STAM_REG(pVM, &pPGM->StatHandlersVirtual, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/Handlers/Virtual", STAMUNIT_OCCURENCES, "Number of traps due to virtual access handlers.");
1539	STAM_REG(pVM, &pPGM->StatHandlersVirtualByPhys, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/Handlers/VirtualByPhys", STAMUNIT_OCCURENCES, "Number of traps due to virtual access handlers by physical address.");
1540	STAM_REG(pVM, &pPGM->StatHandlersVirtualUnmarked, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/Handlers/VirtualUnmarked", STAMUNIT_OCCURENCES,"Number of traps due to virtual access handlers by virtual address (without proper physical flags).");
1541	STAM_REG(pVM, &pPGM->StatHandlersUnhandled, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/Handlers/Unhandled", STAMUNIT_OCCURENCES, "Number of traps due to access outside range of monitored page(s).");
1542	STAM_REG(pVM, &pPGM->StatHandlersInvalid, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/Handlers/Invalid", STAMUNIT_OCCURENCES, "Number of traps due to access to invalid physical memory.");
1543
1544	STAM_REG(pVM, &pPGM->StatGCTrap0eConflicts, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/Conflicts", STAMUNIT_OCCURENCES, "The number of times #PF was caused by an undetected conflict.");
1545	STAM_REG(pVM, &pPGM->StatGCTrap0eUSNotPresentRead, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/User/NPRead", STAMUNIT_OCCURENCES, "Number of user mode not present read page faults.");
1546	STAM_REG(pVM, &pPGM->StatGCTrap0eUSNotPresentWrite, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/User/NPWrite", STAMUNIT_OCCURENCES, "Number of user mode not present write page faults.");
1547	STAM_REG(pVM, &pPGM->StatGCTrap0eUSWrite, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/User/Write", STAMUNIT_OCCURENCES, "Number of user mode write page faults.");
1548	STAM_REG(pVM, &pPGM->StatGCTrap0eUSReserved, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/User/Reserved", STAMUNIT_OCCURENCES, "Number of user mode reserved bit page faults.");
1549	STAM_REG(pVM, &pPGM->StatGCTrap0eUSNXE, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/User/NXE", STAMUNIT_OCCURENCES, "Number of user mode NXE page faults.");
1550	STAM_REG(pVM, &pPGM->StatGCTrap0eUSRead, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/User/Read", STAMUNIT_OCCURENCES, "Number of user mode read page faults.");
1551
1552	STAM_REG(pVM, &pPGM->StatGCTrap0eSVNotPresentRead, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/Supervisor/NPRead", STAMUNIT_OCCURENCES, "Number of supervisor mode not present read page faults.");
1553	STAM_REG(pVM, &pPGM->StatGCTrap0eSVNotPresentWrite, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/Supervisor/NPWrite", STAMUNIT_OCCURENCES, "Number of supervisor mode not present write page faults.");
1554	STAM_REG(pVM, &pPGM->StatGCTrap0eSVWrite, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/Supervisor/Write", STAMUNIT_OCCURENCES, "Number of supervisor mode write page faults.");
1555	STAM_REG(pVM, &pPGM->StatGCTrap0eSVReserved, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/Supervisor/Reserved", STAMUNIT_OCCURENCES, "Number of supervisor mode reserved bit page faults.");
1556	STAM_REG(pVM, &pPGM->StatGCTrap0eSNXE, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/Supervisor/NXE", STAMUNIT_OCCURENCES, "Number of supervisor mode NXE page faults.");
1557	STAM_REG(pVM, &pPGM->StatGCTrap0eUnhandled, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/GuestPF/Unhandled", STAMUNIT_OCCURENCES, "Number of guest real page faults.");
1558	STAM_REG(pVM, &pPGM->StatGCTrap0eMap, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/GuestPF/Map", STAMUNIT_OCCURENCES, "Number of guest page faults due to map accesses.");
1559
1560	STAM_REG(pVM, &pPGM->StatTrap0eWPEmulGC, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/WP/InGC", STAMUNIT_OCCURENCES, "Number of guest page faults due to X86_CR0_WP emulation.");
1561	STAM_REG(pVM, &pPGM->StatTrap0eWPEmulR3, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/WP/ToR3", STAMUNIT_OCCURENCES, "Number of guest page faults due to X86_CR0_WP emulation (forward to R3 for emulation).");
1562
1563	STAM_REG(pVM, &pPGM->StatGCGuestCR3WriteHandled, STAMTYPE_COUNTER, "/PGM/GC/CR3WriteInt", STAMUNIT_OCCURENCES, "The number of times the Guest CR3 change was successfully handled.");
1564	STAM_REG(pVM, &pPGM->StatGCGuestCR3WriteUnhandled, STAMTYPE_COUNTER, "/PGM/GC/CR3WriteEmu", STAMUNIT_OCCURENCES, "The number of times the Guest CR3 change was passed back to the recompiler.");
1565	STAM_REG(pVM, &pPGM->StatGCGuestCR3WriteConflict, STAMTYPE_COUNTER, "/PGM/GC/CR3WriteConflict", STAMUNIT_OCCURENCES, "The number of times the Guest CR3 monitoring detected a conflict.");
1566
1567	STAM_REG(pVM, &pPGM->StatGCPageOutOfSyncSupervisor, STAMTYPE_COUNTER, "/PGM/GC/OutOfSync/SuperVisor", STAMUNIT_OCCURENCES, "Number of traps due to pages out of sync.");
1568	STAM_REG(pVM, &pPGM->StatGCPageOutOfSyncUser, STAMTYPE_COUNTER, "/PGM/GC/OutOfSync/User", STAMUNIT_OCCURENCES, "Number of traps due to pages out of sync.");
1569
1570	STAM_REG(pVM, &pPGM->StatGCGuestROMWriteHandled, STAMTYPE_COUNTER, "/PGM/GC/ROMWriteInt", STAMUNIT_OCCURENCES, "The number of times the Guest ROM change was successfully handled.");
1571	STAM_REG(pVM, &pPGM->StatGCGuestROMWriteUnhandled, STAMTYPE_COUNTER, "/PGM/GC/ROMWriteEmu", STAMUNIT_OCCURENCES, "The number of times the Guest ROM change was passed back to the recompiler.");
1572
1573	STAM_REG(pVM, &pPGM->StatDynMapCacheHits, STAMTYPE_COUNTER, "/PGM/GC/DynMapCache/Hits" , STAMUNIT_OCCURENCES, "Number of dynamic page mapping cache hits.");
1574	STAM_REG(pVM, &pPGM->StatDynMapCacheMisses, STAMTYPE_COUNTER, "/PGM/GC/DynMapCache/Misses" , STAMUNIT_OCCURENCES, "Number of dynamic page mapping cache misses.");
1575
1576	STAM_REG(pVM, &pPGM->StatHCDetectedConflicts, STAMTYPE_COUNTER, "/PGM/HC/DetectedConflicts", STAMUNIT_OCCURENCES, "The number of times PGMR3CheckMappingConflicts() detected a conflict.");
1577	STAM_REG(pVM, &pPGM->StatHCGuestPDWrite, STAMTYPE_COUNTER, "/PGM/HC/PDWrite", STAMUNIT_OCCURENCES, "The total number of times pgmHCGuestPDWriteHandler() was called.");
1578	STAM_REG(pVM, &pPGM->StatHCGuestPDWriteConflict, STAMTYPE_COUNTER, "/PGM/HC/PDWriteConflict", STAMUNIT_OCCURENCES, "The number of times pgmHCGuestPDWriteHandler() detected a conflict.");
1579
1580	STAM_REG(pVM, &pPGM->StatHCInvalidatePage, STAMTYPE_PROFILE, "/PGM/HC/InvalidatePage", STAMUNIT_TICKS_PER_CALL, "PGMHCInvalidatePage() profiling.");
1581	STAM_REG(pVM, &pPGM->StatHCInvalidatePage4KBPages, STAMTYPE_COUNTER, "/PGM/HC/InvalidatePage/4KBPages", STAMUNIT_OCCURENCES, "The number of times PGMHCInvalidatePage() was called for a 4KB page.");
1582	STAM_REG(pVM, &pPGM->StatHCInvalidatePage4MBPages, STAMTYPE_COUNTER, "/PGM/HC/InvalidatePage/4MBPages", STAMUNIT_OCCURENCES, "The number of times PGMHCInvalidatePage() was called for a 4MB page.");
1583	STAM_REG(pVM, &pPGM->StatHCInvalidatePage4MBPagesSkip, STAMTYPE_COUNTER, "/PGM/HC/InvalidatePage/4MBPagesSkip",STAMUNIT_OCCURENCES, "The number of times PGMHCInvalidatePage() skipped a 4MB page.");
1584	STAM_REG(pVM, &pPGM->StatHCInvalidatePagePDMappings, STAMTYPE_COUNTER, "/PGM/HC/InvalidatePage/PDMappings", STAMUNIT_OCCURENCES, "The number of times PGMHCInvalidatePage() was called for a page directory containing mappings (no conflict).");
1585	STAM_REG(pVM, &pPGM->StatHCInvalidatePagePDNAs, STAMTYPE_COUNTER, "/PGM/HC/InvalidatePage/PDNAs", STAMUNIT_OCCURENCES, "The number of times PGMHCInvalidatePage() was called for a not accessed page directory.");
1586	STAM_REG(pVM, &pPGM->StatHCInvalidatePagePDNPs, STAMTYPE_COUNTER, "/PGM/HC/InvalidatePage/PDNPs", STAMUNIT_OCCURENCES, "The number of times PGMHCInvalidatePage() was called for a not present page directory.");
1587	STAM_REG(pVM, &pPGM->StatHCInvalidatePagePDOutOfSync, STAMTYPE_COUNTER, "/PGM/HC/InvalidatePage/PDOutOfSync", STAMUNIT_OCCURENCES, "The number of times PGMGCInvalidatePage() was called for an out of sync page directory.");
1588	STAM_REG(pVM, &pPGM->StatHCInvalidatePageSkipped, STAMTYPE_COUNTER, "/PGM/HC/InvalidatePage/Skipped", STAMUNIT_OCCURENCES, "The number of times PGMHCInvalidatePage() was skipped due to not present shw or pending pending SyncCR3.");
1589	STAM_REG(pVM, &pPGM->StatHCResolveConflict, STAMTYPE_PROFILE, "/PGM/HC/ResolveConflict", STAMUNIT_TICKS_PER_CALL, "pgmR3SyncPTResolveConflict() profiling (includes the entire relocation).");
1590	STAM_REG(pVM, &pPGM->StatHCPrefetch, STAMTYPE_PROFILE, "/PGM/HC/Prefetch", STAMUNIT_TICKS_PER_CALL, "PGMR3PrefetchPage profiling.");
1591
1592	STAM_REG(pVM, &pPGM->StatHCSyncPT, STAMTYPE_PROFILE, "/PGM/HC/SyncPT", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMR3SyncPT() body.");
1593	STAM_REG(pVM, &pPGM->StatHCAccessedPage, STAMTYPE_COUNTER, "/PGM/HC/AccessedPage", STAMUNIT_OCCURENCES, "The number of pages marked not present for accessed bit emulation.");
1594	STAM_REG(pVM, &pPGM->StatHCDirtyPage, STAMTYPE_COUNTER, "/PGM/HC/DirtyPage/Mark", STAMUNIT_OCCURENCES, "The number of pages marked read-only for dirty bit tracking.");
1595	STAM_REG(pVM, &pPGM->StatHCDirtyPageBig, STAMTYPE_COUNTER, "/PGM/HC/DirtyPage/MarkBig", STAMUNIT_OCCURENCES, "The number of 4MB pages marked read-only for dirty bit tracking.");
1596	STAM_REG(pVM, &pPGM->StatHCDirtyPageTrap, STAMTYPE_COUNTER, "/PGM/HC/DirtyPage/Trap", STAMUNIT_OCCURENCES, "The number of traps generated for dirty bit tracking.");
1597	STAM_REG(pVM, &pPGM->StatHCDirtyPageSkipped, STAMTYPE_COUNTER, "/PGM/HC/DirtyPage/Skipped", STAMUNIT_OCCURENCES, "The number of pages already dirty or readonly.");
1598	STAM_REG(pVM, &pPGM->StatHCDirtyBitTracking, STAMTYPE_PROFILE, "/PGM/HC/DirtyPage", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMTrackDirtyBit() body.");
1599
1600	STAM_REG(pVM, &pPGM->StatGCSyncPagePDNAs, STAMTYPE_COUNTER, "/PGM/GC/SyncPagePDNAs", STAMUNIT_OCCURENCES, "The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit.");
1601	STAM_REG(pVM, &pPGM->StatGCSyncPagePDOutOfSync, STAMTYPE_COUNTER, "/PGM/GC/SyncPagePDOutOfSync", STAMUNIT_OCCURENCES, "The number of time we've encountered an out-of-sync PD in SyncPage.");
1602	STAM_REG(pVM, &pPGM->StatHCSyncPagePDNAs, STAMTYPE_COUNTER, "/PGM/HC/SyncPagePDNAs", STAMUNIT_OCCURENCES, "The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit.");
1603	STAM_REG(pVM, &pPGM->StatHCSyncPagePDOutOfSync, STAMTYPE_COUNTER, "/PGM/HC/SyncPagePDOutOfSync", STAMUNIT_OCCURENCES, "The number of time we've encountered an out-of-sync PD in SyncPage.");
1604
1605	STAM_REG(pVM, &pPGM->StatFlushTLB, STAMTYPE_PROFILE, "/PGM/FlushTLB", STAMUNIT_OCCURENCES, "Profiling of the PGMFlushTLB() body.");
1606	STAM_REG(pVM, &pPGM->StatFlushTLBNewCR3, STAMTYPE_COUNTER, "/PGM/FlushTLB/NewCR3", STAMUNIT_OCCURENCES, "The number of times PGMFlushTLB was called with a new CR3, non-global. (switch)");
1607	STAM_REG(pVM, &pPGM->StatFlushTLBNewCR3Global, STAMTYPE_COUNTER, "/PGM/FlushTLB/NewCR3Global", STAMUNIT_OCCURENCES, "The number of times PGMFlushTLB was called with a new CR3, global. (switch)");
1608	STAM_REG(pVM, &pPGM->StatFlushTLBSameCR3, STAMTYPE_COUNTER, "/PGM/FlushTLB/SameCR3", STAMUNIT_OCCURENCES, "The number of times PGMFlushTLB was called with the same CR3, non-global. (flush)");
1609	STAM_REG(pVM, &pPGM->StatFlushTLBSameCR3Global, STAMTYPE_COUNTER, "/PGM/FlushTLB/SameCR3Global", STAMUNIT_OCCURENCES, "The number of times PGMFlushTLB was called with the same CR3, global. (flush)");
1610
1611	STAM_REG(pVM, &pPGM->StatGCSyncCR3, STAMTYPE_PROFILE, "/PGM/GC/SyncCR3", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMSyncCR3() body.");
1612	STAM_REG(pVM, &pPGM->StatGCSyncCR3Handlers, STAMTYPE_PROFILE, "/PGM/GC/SyncCR3/Handlers", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMSyncCR3() update handler section.");
1613	STAM_REG(pVM, &pPGM->StatGCSyncCR3HandlerVirtualUpdate, STAMTYPE_PROFILE, "/PGM/GC/SyncCR3/Handlers/VirtualUpdate",STAMUNIT_TICKS_PER_CALL, "Profiling of the virtual handler updates.");
1614	STAM_REG(pVM, &pPGM->StatGCSyncCR3HandlerVirtualReset, STAMTYPE_PROFILE, "/PGM/GC/SyncCR3/Handlers/VirtualReset", STAMUNIT_TICKS_PER_CALL, "Profiling of the virtual handler resets.");
1615	STAM_REG(pVM, &pPGM->StatGCSyncCR3Global, STAMTYPE_COUNTER, "/PGM/GC/SyncCR3/Global", STAMUNIT_OCCURENCES, "The number of global CR3 syncs.");
1616	STAM_REG(pVM, &pPGM->StatGCSyncCR3NotGlobal, STAMTYPE_COUNTER, "/PGM/GC/SyncCR3/NotGlobal", STAMUNIT_OCCURENCES, "The number of non-global CR3 syncs.");
1617	STAM_REG(pVM, &pPGM->StatGCSyncCR3DstCacheHit, STAMTYPE_COUNTER, "/PGM/GC/SyncCR3/DstChacheHit", STAMUNIT_OCCURENCES, "The number of times we got some kind of a cache hit.");
1618	STAM_REG(pVM, &pPGM->StatGCSyncCR3DstFreed, STAMTYPE_COUNTER, "/PGM/GC/SyncCR3/DstFreed", STAMUNIT_OCCURENCES, "The number of times we've had to free a shadow entry.");
1619	STAM_REG(pVM, &pPGM->StatGCSyncCR3DstFreedSrcNP, STAMTYPE_COUNTER, "/PGM/GC/SyncCR3/DstFreedSrcNP", STAMUNIT_OCCURENCES, "The number of times we've had to free a shadow entry for which the source entry was not present.");
1620	STAM_REG(pVM, &pPGM->StatGCSyncCR3DstNotPresent, STAMTYPE_COUNTER, "/PGM/GC/SyncCR3/DstNotPresent", STAMUNIT_OCCURENCES, "The number of times we've encountered a not present shadow entry for a present guest entry.");
1621	STAM_REG(pVM, &pPGM->StatGCSyncCR3DstSkippedGlobalPD, STAMTYPE_COUNTER, "/PGM/GC/SyncCR3/DstSkippedGlobalPD", STAMUNIT_OCCURENCES, "The number of times a global page directory wasn't flushed.");
1622	STAM_REG(pVM, &pPGM->StatGCSyncCR3DstSkippedGlobalPT, STAMTYPE_COUNTER, "/PGM/GC/SyncCR3/DstSkippedGlobalPT", STAMUNIT_OCCURENCES, "The number of times a page table with only global entries wasn't flushed.");
1623
1624	STAM_REG(pVM, &pPGM->StatHCSyncCR3, STAMTYPE_PROFILE, "/PGM/HC/SyncCR3", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMSyncCR3() body.");
1625	STAM_REG(pVM, &pPGM->StatHCSyncCR3Handlers, STAMTYPE_PROFILE, "/PGM/HC/SyncCR3/Handlers", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMSyncCR3() update handler section.");
1626	STAM_REG(pVM, &pPGM->StatHCSyncCR3HandlerVirtualUpdate, STAMTYPE_PROFILE, "/PGM/HC/SyncCR3/Handlers/VirtualUpdate",STAMUNIT_TICKS_PER_CALL, "Profiling of the virtual handler updates.");
1627	STAM_REG(pVM, &pPGM->StatHCSyncCR3HandlerVirtualReset, STAMTYPE_PROFILE, "/PGM/HC/SyncCR3/Handlers/VirtualReset", STAMUNIT_TICKS_PER_CALL, "Profiling of the virtual handler resets.");
1628	STAM_REG(pVM, &pPGM->StatHCSyncCR3Global, STAMTYPE_COUNTER, "/PGM/HC/SyncCR3/Global", STAMUNIT_OCCURENCES, "The number of global CR3 syncs.");
1629	STAM_REG(pVM, &pPGM->StatHCSyncCR3NotGlobal, STAMTYPE_COUNTER, "/PGM/HC/SyncCR3/NotGlobal", STAMUNIT_OCCURENCES, "The number of non-global CR3 syncs.");
1630	STAM_REG(pVM, &pPGM->StatHCSyncCR3DstCacheHit, STAMTYPE_COUNTER, "/PGM/HC/SyncCR3/DstChacheHit", STAMUNIT_OCCURENCES, "The number of times we got some kind of a cache hit.");
1631	STAM_REG(pVM, &pPGM->StatHCSyncCR3DstFreed, STAMTYPE_COUNTER, "/PGM/HC/SyncCR3/DstFreed", STAMUNIT_OCCURENCES, "The number of times we've had to free a shadow entry.");
1632	STAM_REG(pVM, &pPGM->StatHCSyncCR3DstFreedSrcNP, STAMTYPE_COUNTER, "/PGM/HC/SyncCR3/DstFreedSrcNP", STAMUNIT_OCCURENCES, "The number of times we've had to free a shadow entry for which the source entry was not present.");
1633	STAM_REG(pVM, &pPGM->StatHCSyncCR3DstNotPresent, STAMTYPE_COUNTER, "/PGM/HC/SyncCR3/DstNotPresent", STAMUNIT_OCCURENCES, "The number of times we've encountered a not present shadow entry for a present guest entry.");
1634	STAM_REG(pVM, &pPGM->StatHCSyncCR3DstSkippedGlobalPD, STAMTYPE_COUNTER, "/PGM/HC/SyncCR3/DstSkippedGlobalPD", STAMUNIT_OCCURENCES, "The number of times a global page directory wasn't flushed.");
1635	STAM_REG(pVM, &pPGM->StatHCSyncCR3DstSkippedGlobalPT, STAMTYPE_COUNTER, "/PGM/HC/SyncCR3/DstSkippedGlobalPT", STAMUNIT_OCCURENCES, "The number of times a page table with only global entries wasn't flushed.");
1636
1637	STAM_REG(pVM, &pPGM->StatVirtHandleSearchByPhysGC, STAMTYPE_PROFILE, "/PGM/VirtHandler/SearchByPhys/GC", STAMUNIT_TICKS_PER_CALL, "Profiling of pgmHandlerVirtualFindByPhysAddr in GC.");
1638	STAM_REG(pVM, &pPGM->StatVirtHandleSearchByPhysHC, STAMTYPE_PROFILE, "/PGM/VirtHandler/SearchByPhys/HC", STAMUNIT_TICKS_PER_CALL, "Profiling of pgmHandlerVirtualFindByPhysAddr in HC.");
1639	STAM_REG(pVM, &pPGM->StatHandlePhysicalReset, STAMTYPE_COUNTER, "/PGM/HC/HandlerPhysicalReset", STAMUNIT_OCCURENCES, "The number of times PGMR3HandlerPhysicalReset is called.");
1640
1641	STAM_REG(pVM, &pPGM->StatHCGstModifyPage, STAMTYPE_PROFILE, "/PGM/HC/GstModifyPage", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMGstModifyPage() body.");
1642	STAM_REG(pVM, &pPGM->StatGCGstModifyPage, STAMTYPE_PROFILE, "/PGM/GC/GstModifyPage", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMGstModifyPage() body.");
1643
1644	STAM_REG(pVM, &pPGM->StatSynPT4kGC, STAMTYPE_COUNTER, "/PGM/GC/SyncPT/4k", STAMUNIT_OCCURENCES, "Nr of 4k PT syncs");
1645	STAM_REG(pVM, &pPGM->StatSynPT4kHC, STAMTYPE_COUNTER, "/PGM/HC/SyncPT/4k", STAMUNIT_OCCURENCES, "Nr of 4k PT syncs");
1646	STAM_REG(pVM, &pPGM->StatSynPT4MGC, STAMTYPE_COUNTER, "/PGM/GC/SyncPT/4M", STAMUNIT_OCCURENCES, "Nr of 4M PT syncs");
1647	STAM_REG(pVM, &pPGM->StatSynPT4MHC, STAMTYPE_COUNTER, "/PGM/HC/SyncPT/4M", STAMUNIT_OCCURENCES, "Nr of 4M PT syncs");
1648
1649	STAM_REG(pVM, &pPGM->StatDynRamTotal, STAMTYPE_COUNTER, "/PGM/RAM/TotalAlloc", STAMUNIT_MEGABYTES, "Allocated mbs of guest ram.");
1650	STAM_REG(pVM, &pPGM->StatDynRamGrow, STAMTYPE_COUNTER, "/PGM/RAM/Grow", STAMUNIT_OCCURENCES, "Nr of pgmr3PhysGrowRange calls.");
1651
1652	STAM_REG(pVM, &pPGM->StatPageHCMapTlbHits, STAMTYPE_COUNTER, "/PGM/PageHCMap/TlbHits", STAMUNIT_OCCURENCES, "TLB hits.");
1653	STAM_REG(pVM, &pPGM->StatPageHCMapTlbMisses, STAMTYPE_COUNTER, "/PGM/PageHCMap/TlbMisses", STAMUNIT_OCCURENCES, "TLB misses.");
1654	STAM_REG(pVM, &pPGM->ChunkR3Map.c, STAMTYPE_U32, "/PGM/ChunkR3Map/c", STAMUNIT_OCCURENCES, "Number of mapped chunks.");
1655	STAM_REG(pVM, &pPGM->ChunkR3Map.cMax, STAMTYPE_U32, "/PGM/ChunkR3Map/cMax", STAMUNIT_OCCURENCES, "Maximum number of mapped chunks.");
1656	STAM_REG(pVM, &pPGM->StatChunkR3MapTlbHits, STAMTYPE_COUNTER, "/PGM/ChunkR3Map/TlbHits", STAMUNIT_OCCURENCES, "TLB hits.");
1657	STAM_REG(pVM, &pPGM->StatChunkR3MapTlbMisses, STAMTYPE_COUNTER, "/PGM/ChunkR3Map/TlbMisses", STAMUNIT_OCCURENCES, "TLB misses.");
1658	STAM_REG(pVM, &pPGM->StatPageReplaceShared, STAMTYPE_COUNTER, "/PGM/Page/ReplacedShared", STAMUNIT_OCCURENCES, "Times a shared page was replaced.");
1659	STAM_REG(pVM, &pPGM->StatPageReplaceZero, STAMTYPE_COUNTER, "/PGM/Page/ReplacedZero", STAMUNIT_OCCURENCES, "Times the zero page was replaced.");
1660	STAM_REG(pVM, &pPGM->StatPageHandyAllocs, STAMTYPE_COUNTER, "/PGM/Page/HandyAllocs", STAMUNIT_OCCURENCES, "Number of times we've allocated more handy pages.");
1661	STAM_REG(pVM, &pPGM->cAllPages, STAMTYPE_U32, "/PGM/Page/cAllPages", STAMUNIT_OCCURENCES, "The total number of pages.");
1662	STAM_REG(pVM, &pPGM->cPrivatePages, STAMTYPE_U32, "/PGM/Page/cPrivatePages", STAMUNIT_OCCURENCES, "The number of private pages.");
1663	STAM_REG(pVM, &pPGM->cSharedPages, STAMTYPE_U32, "/PGM/Page/cSharedPages", STAMUNIT_OCCURENCES, "The number of shared pages.");
1664	STAM_REG(pVM, &pPGM->cZeroPages, STAMTYPE_U32, "/PGM/Page/cZeroPages", STAMUNIT_OCCURENCES, "The number of zero backed pages.");
1665
1666	#ifdef PGMPOOL_WITH_GCPHYS_TRACKING
1667	STAM_REG(pVM, &pPGM->StatTrackVirgin, STAMTYPE_COUNTER, "/PGM/Track/Virgin", STAMUNIT_OCCURENCES, "The number of first time shadowings");
1668	STAM_REG(pVM, &pPGM->StatTrackAliased, STAMTYPE_COUNTER, "/PGM/Track/Aliased", STAMUNIT_OCCURENCES, "The number of times switching to cRef2, i.e. the page is being shadowed by two PTs.");
1669	STAM_REG(pVM, &pPGM->StatTrackAliasedMany, STAMTYPE_COUNTER, "/PGM/Track/AliasedMany", STAMUNIT_OCCURENCES, "The number of times we're tracking using cRef2.");
1670	STAM_REG(pVM, &pPGM->StatTrackAliasedLots, STAMTYPE_COUNTER, "/PGM/Track/AliasedLots", STAMUNIT_OCCURENCES, "The number of times we're hitting pages which has overflowed cRef2");
1671	STAM_REG(pVM, &pPGM->StatTrackOverflows, STAMTYPE_COUNTER, "/PGM/Track/Overflows", STAMUNIT_OCCURENCES, "The number of times the extent list grows to long.");
1672	STAM_REG(pVM, &pPGM->StatTrackDeref, STAMTYPE_PROFILE, "/PGM/Track/Deref", STAMUNIT_OCCURENCES, "Profiling of SyncPageWorkerTrackDeref (expensive).");
1673	#endif
1674
1675	for (unsigned i = 0; i < X86_PG_ENTRIES; i++)
1676	{
1677	/** @todo r=bird: We need a STAMR3RegisterF()! */
1678	char szName[32];
1679
1680	RTStrPrintf(szName, sizeof(szName), "/PGM/GC/PD/Trap0e/%04X", i);
1681	int rc = STAMR3Register(pVM, &pPGM->StatGCTrap0ePD[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, szName, STAMUNIT_OCCURENCES, "The number of traps in page directory n.");
1682	AssertRC(rc);
1683
1684	RTStrPrintf(szName, sizeof(szName), "/PGM/GC/PD/SyncPt/%04X", i);
1685	rc = STAMR3Register(pVM, &pPGM->StatGCSyncPtPD[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, szName, STAMUNIT_OCCURENCES, "The number of syncs per PD n.");
1686	AssertRC(rc);
1687
1688	RTStrPrintf(szName, sizeof(szName), "/PGM/GC/PD/SyncPage/%04X", i);
1689	rc = STAMR3Register(pVM, &pPGM->StatGCSyncPagePD[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, szName, STAMUNIT_OCCURENCES, "The number of out of sync pages per page directory n.");
1690	AssertRC(rc);
1691	}
1692	}
1693	#endif /* VBOX_WITH_STATISTICS */
1694
1695	/**
1696	* Init the PGM bits that rely on VMMR0 and MM to be fully initialized.
1697	*
1698	* The dynamic mapping area will also be allocated and initialized at this
1699	* time. We could allocate it during PGMR3Init of course, but the mapping
1700	* wouldn't be allocated at that time preventing us from setting up the
1701	* page table entries with the dummy page.
1702	*
1703	* @returns VBox status code.
1704	* @param pVM VM handle.
1705	*/
1706	PGMR3DECL(int) PGMR3InitDynMap(PVM pVM)
1707	{
1708	RTGCPTR GCPtr;
1709	/*
1710	* Reserve space for mapping the paging pages into guest context.
1711	*/
1712	int rc = MMR3HyperReserve(pVM, PAGE_SIZE * (2 + ELEMENTS(pVM->pgm.s.apHCPaePDs) + 1 + 2 + 2), "Paging", &GCPtr);
1713	AssertRCReturn(rc, rc);
1714	pVM->pgm.s.pGC32BitPD = GCPtr;
1715	MMR3HyperReserve(pVM, PAGE_SIZE, "fence", NULL);
1716
1717	/*
1718	* Reserve space for the dynamic mappings.
1719	*/
1720	/** @todo r=bird: Need to verify that the checks for crossing PTs are correct here. They seems to be assuming 4MB PTs.. */
1721	rc = MMR3HyperReserve(pVM, MM_HYPER_DYNAMIC_SIZE, "Dynamic mapping", &GCPtr);
1722	if (VBOX_SUCCESS(rc))
1723	pVM->pgm.s.pbDynPageMapBaseGC = GCPtr;
1724
1725	if ( VBOX_SUCCESS(rc)
1726	&& (pVM->pgm.s.pbDynPageMapBaseGC >> X86_PD_SHIFT) != ((pVM->pgm.s.pbDynPageMapBaseGC + MM_HYPER_DYNAMIC_SIZE - 1) >> X86_PD_SHIFT))
1727	{
1728	rc = MMR3HyperReserve(pVM, MM_HYPER_DYNAMIC_SIZE, "Dynamic mapping not crossing", &GCPtr);
1729	if (VBOX_SUCCESS(rc))
1730	pVM->pgm.s.pbDynPageMapBaseGC = GCPtr;
1731	}
1732	if (VBOX_SUCCESS(rc))
1733	{
1734	AssertRelease((pVM->pgm.s.pbDynPageMapBaseGC >> X86_PD_SHIFT) == ((pVM->pgm.s.pbDynPageMapBaseGC + MM_HYPER_DYNAMIC_SIZE - 1) >> X86_PD_SHIFT));
1735	MMR3HyperReserve(pVM, PAGE_SIZE, "fence", NULL);
1736	}
1737	return rc;
1738	}
1739
1740
1741	/**
1742	* Ring-3 init finalizing.
1743	*
1744	* @returns VBox status code.
1745	* @param pVM The VM handle.
1746	*/
1747	PGMR3DECL(int) PGMR3InitFinalize(PVM pVM)
1748	{
1749	/*
1750	* Map the paging pages into the guest context.
1751	*/
1752	RTGCPTR GCPtr = pVM->pgm.s.pGC32BitPD;
1753	AssertReleaseReturn(GCPtr, VERR_INTERNAL_ERROR);
1754
1755	int rc = PGMMap(pVM, GCPtr, pVM->pgm.s.HCPhys32BitPD, PAGE_SIZE, 0);
1756	AssertRCReturn(rc, rc);
1757	pVM->pgm.s.pGC32BitPD = GCPtr;
1758	GCPtr += PAGE_SIZE;
1759	GCPtr += PAGE_SIZE; /* reserved page */
1760
1761	for (unsigned i = 0; i < ELEMENTS(pVM->pgm.s.apHCPaePDs); i++)
1762	{
1763	rc = PGMMap(pVM, GCPtr, pVM->pgm.s.aHCPhysPaePDs[i], PAGE_SIZE, 0);
1764	AssertRCReturn(rc, rc);
1765	pVM->pgm.s.apGCPaePDs[i] = GCPtr;
1766	GCPtr += PAGE_SIZE;
1767	}
1768	/* A bit of paranoia is justified. */
1769	AssertRelease((RTGCUINTPTR)pVM->pgm.s.apGCPaePDs[0] + PAGE_SIZE == (RTGCUINTPTR)pVM->pgm.s.apGCPaePDs[1]);
1770	AssertRelease((RTGCUINTPTR)pVM->pgm.s.apGCPaePDs[1] + PAGE_SIZE == (RTGCUINTPTR)pVM->pgm.s.apGCPaePDs[2]);
1771	AssertRelease((RTGCUINTPTR)pVM->pgm.s.apGCPaePDs[2] + PAGE_SIZE == (RTGCUINTPTR)pVM->pgm.s.apGCPaePDs[3]);
1772	GCPtr += PAGE_SIZE; /* reserved page */
1773
1774	rc = PGMMap(pVM, GCPtr, pVM->pgm.s.HCPhysPaePDPT, PAGE_SIZE, 0);
1775	AssertRCReturn(rc, rc);
1776	pVM->pgm.s.pGCPaePDPT = GCPtr;
1777	GCPtr += PAGE_SIZE;
1778	GCPtr += PAGE_SIZE; /* reserved page */
1779
1780
1781	/*
1782	* Reserve space for the dynamic mappings.
1783	* Initialize the dynamic mapping pages with dummy pages to simply the cache.
1784	*/
1785	/* get the pointer to the page table entries. */
1786	PPGMMAPPING pMapping = pgmGetMapping(pVM, pVM->pgm.s.pbDynPageMapBaseGC);
1787	AssertRelease(pMapping);
1788	const uintptr_t off = pVM->pgm.s.pbDynPageMapBaseGC - pMapping->GCPtr;
1789	const unsigned iPT = off >> X86_PD_SHIFT;
1790	const unsigned iPG = (off >> X86_PT_SHIFT) & X86_PT_MASK;
1791	pVM->pgm.s.paDynPageMap32BitPTEsGC = pMapping->aPTs[iPT].pPTGC + iPG * sizeof(pMapping->aPTs[0].pPTR3->a[0]);
1792	pVM->pgm.s.paDynPageMapPaePTEsGC = pMapping->aPTs[iPT].paPaePTsGC + iPG * sizeof(pMapping->aPTs[0].paPaePTsR3->a[0]);
1793
1794	/* init cache */
1795	RTHCPHYS HCPhysDummy = MMR3PageDummyHCPhys(pVM);
1796	for (unsigned i = 0; i < ELEMENTS(pVM->pgm.s.aHCPhysDynPageMapCache); i++)
1797	pVM->pgm.s.aHCPhysDynPageMapCache[i] = HCPhysDummy;
1798
1799	for (unsigned i = 0; i < MM_HYPER_DYNAMIC_SIZE; i += PAGE_SIZE)
1800	{
1801	rc = PGMMap(pVM, pVM->pgm.s.pbDynPageMapBaseGC + i, HCPhysDummy, PAGE_SIZE, 0);
1802	AssertRCReturn(rc, rc);
1803	}
1804
1805	return rc;
1806	}
1807
1808
1809	/**
1810	* Applies relocations to data and code managed by this
1811	* component. This function will be called at init and
1812	* whenever the VMM need to relocate it self inside the GC.
1813	*
1814	* @param pVM The VM.
1815	* @param offDelta Relocation delta relative to old location.
1816	*/
1817	PGMR3DECL(void) PGMR3Relocate(PVM pVM, RTGCINTPTR offDelta)
1818	{
1819	LogFlow(("PGMR3Relocate\n"));
1820
1821	/*
1822	* Paging stuff.
1823	*/
1824	pVM->pgm.s.GCPtrCR3Mapping += offDelta;
1825	/** @todo move this into shadow and guest specific relocation functions. */
1826	AssertMsg(pVM->pgm.s.pGC32BitPD, ("Init order, no relocation before paging is initialized!\n"));
1827	pVM->pgm.s.pGC32BitPD += offDelta;
1828	pVM->pgm.s.pGuestPDGC += offDelta;
1829	AssertCompile(ELEMENTS(pVM->pgm.s.apGCPaePDs) == ELEMENTS(pVM->pgm.s.apGstPaePDsGC));
1830	for (unsigned i = 0; i < ELEMENTS(pVM->pgm.s.apGCPaePDs); i++)
1831	{
1832	pVM->pgm.s.apGCPaePDs[i] += offDelta;
1833	pVM->pgm.s.apGstPaePDsGC[i] += offDelta;
1834	}
1835	pVM->pgm.s.pGstPaePDPTGC += offDelta;
1836	pVM->pgm.s.pGCPaePDPT += offDelta;
1837
1838	pgmR3ModeDataInit(pVM, true /* resolve GC/R0 symbols */);
1839	pgmR3ModeDataSwitch(pVM, pVM->pgm.s.enmShadowMode, pVM->pgm.s.enmGuestMode);
1840
1841	PGM_SHW_PFN(Relocate, pVM)(pVM, offDelta);
1842	PGM_GST_PFN(Relocate, pVM)(pVM, offDelta);
1843	PGM_BTH_PFN(Relocate, pVM)(pVM, offDelta);
1844
1845	/*
1846	* Trees.
1847	*/
1848	pVM->pgm.s.pTreesGC = MMHyperHC2GC(pVM, pVM->pgm.s.pTreesHC);
1849
1850	/*
1851	* Ram ranges.
1852	*/
1853	if (pVM->pgm.s.pRamRangesR3)
1854	{
1855	pVM->pgm.s.pRamRangesGC = MMHyperHC2GC(pVM, pVM->pgm.s.pRamRangesR3);
1856	for (PPGMRAMRANGE pCur = pVM->pgm.s.pRamRangesR3; pCur->pNextR3; pCur = pCur->pNextR3)
1857	#ifdef VBOX_WITH_NEW_PHYS_CODE
1858	pCur->pNextGC = MMHyperR3ToGC(pVM, pCur->pNextR3);
1859	#else
1860	{
1861	pCur->pNextGC = MMHyperR3ToGC(pVM, pCur->pNextR3);
1862	if (pCur->pavHCChunkGC)
1863	pCur->pavHCChunkGC = MMHyperHC2GC(pVM, pCur->pavHCChunkHC);
1864	}
1865	#endif
1866	}
1867
1868	/*
1869	* Update the two page directories with all page table mappings.
1870	* (One or more of them have changed, that's why we're here.)
1871	*/
1872	pVM->pgm.s.pMappingsGC = MMHyperHC2GC(pVM, pVM->pgm.s.pMappingsR3);
1873	for (PPGMMAPPING pCur = pVM->pgm.s.pMappingsR3; pCur->pNextR3; pCur = pCur->pNextR3)
1874	pCur->pNextGC = MMHyperHC2GC(pVM, pCur->pNextR3);
1875
1876	/* Relocate GC addresses of Page Tables. */
1877	for (PPGMMAPPING pCur = pVM->pgm.s.pMappingsR3; pCur; pCur = pCur->pNextR3)
1878	{
1879	for (RTHCUINT i = 0; i < pCur->cPTs; i++)
1880	{
1881	pCur->aPTs[i].pPTGC = MMHyperR3ToGC(pVM, pCur->aPTs[i].pPTR3);
1882	pCur->aPTs[i].paPaePTsGC = MMHyperR3ToGC(pVM, pCur->aPTs[i].paPaePTsR3);
1883	}
1884	}
1885
1886	/*
1887	* Dynamic page mapping area.
1888	*/
1889	pVM->pgm.s.paDynPageMap32BitPTEsGC += offDelta;
1890	pVM->pgm.s.paDynPageMapPaePTEsGC += offDelta;
1891	pVM->pgm.s.pbDynPageMapBaseGC += offDelta;
1892
1893	/*
1894	* The Zero page.
1895	*/
1896	pVM->pgm.s.pvZeroPgR0 = MMHyperR3ToR0(pVM, pVM->pgm.s.pvZeroPgR3);
1897	AssertRelease(pVM->pgm.s.pvZeroPgR0);
1898
1899	/*
1900	* Physical and virtual handlers.
1901	*/
1902	RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesHC->PhysHandlers, true, pgmR3RelocatePhysHandler, &offDelta);
1903	RTAvlroGCPtrDoWithAll(&pVM->pgm.s.pTreesHC->VirtHandlers, true, pgmR3RelocateVirtHandler, &offDelta);
1904	RTAvlroGCPtrDoWithAll(&pVM->pgm.s.pTreesHC->HyperVirtHandlers, true, pgmR3RelocateHyperVirtHandler, &offDelta);
1905
1906	/*
1907	* The page pool.
1908	*/
1909	pgmR3PoolRelocate(pVM);
1910	}
1911
1912
1913	/**
1914	* Callback function for relocating a physical access handler.
1915	*
1916	* @returns 0 (continue enum)
1917	* @param pNode Pointer to a PGMPHYSHANDLER node.
1918	* @param pvUser Pointer to the offDelta. This is a pointer to the delta since we're
1919	* not certain the delta will fit in a void pointer for all possible configs.
1920	*/
1921	static DECLCALLBACK(int) pgmR3RelocatePhysHandler(PAVLROGCPHYSNODECORE pNode, void *pvUser)
1922	{
1923	PPGMPHYSHANDLER pHandler = (PPGMPHYSHANDLER)pNode;
1924	RTGCINTPTR offDelta = *(PRTGCINTPTR)pvUser;
1925	if (pHandler->pfnHandlerGC)
1926	pHandler->pfnHandlerGC += offDelta;
1927	if ((RTGCUINTPTR)pHandler->pvUserGC >= 0x10000)
1928	pHandler->pvUserGC += offDelta;
1929	return 0;
1930	}
1931
1932
1933	/**
1934	* Callback function for relocating a virtual access handler.
1935	*
1936	* @returns 0 (continue enum)
1937	* @param pNode Pointer to a PGMVIRTHANDLER node.
1938	* @param pvUser Pointer to the offDelta. This is a pointer to the delta since we're
1939	* not certain the delta will fit in a void pointer for all possible configs.
1940	*/
1941	static DECLCALLBACK(int) pgmR3RelocateVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser)
1942	{
1943	PPGMVIRTHANDLER pHandler = (PPGMVIRTHANDLER)pNode;
1944	RTGCINTPTR offDelta = *(PRTGCINTPTR)pvUser;
1945	Assert( pHandler->enmType == PGMVIRTHANDLERTYPE_ALL
1946	\|\| pHandler->enmType == PGMVIRTHANDLERTYPE_WRITE);
1947	Assert(pHandler->pfnHandlerGC);
1948	pHandler->pfnHandlerGC += offDelta;
1949	return 0;
1950	}
1951
1952
1953	/**
1954	* Callback function for relocating a virtual access handler for the hypervisor mapping.
1955	*
1956	* @returns 0 (continue enum)
1957	* @param pNode Pointer to a PGMVIRTHANDLER node.
1958	* @param pvUser Pointer to the offDelta. This is a pointer to the delta since we're
1959	* not certain the delta will fit in a void pointer for all possible configs.
1960	*/
1961	static DECLCALLBACK(int) pgmR3RelocateHyperVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser)
1962	{
1963	PPGMVIRTHANDLER pHandler = (PPGMVIRTHANDLER)pNode;
1964	RTGCINTPTR offDelta = *(PRTGCINTPTR)pvUser;
1965	Assert(pHandler->enmType == PGMVIRTHANDLERTYPE_HYPERVISOR);
1966	Assert(pHandler->pfnHandlerGC);
1967	pHandler->pfnHandlerGC += offDelta;
1968	return 0;
1969	}
1970
1971
1972	/**
1973	* The VM is being reset.
1974	*
1975	* For the PGM component this means that any PD write monitors
1976	* needs to be removed.
1977	*
1978	* @param pVM VM handle.
1979	*/
1980	PGMR3DECL(void) PGMR3Reset(PVM pVM)
1981	{
1982	LogFlow(("PGMR3Reset:\n"));
1983	VM_ASSERT_EMT(pVM);
1984
1985	pgmLock(pVM);
1986
1987	/*
1988	* Unfix any fixed mappings and disable CR3 monitoring.
1989	*/
1990	pVM->pgm.s.fMappingsFixed = false;
1991	pVM->pgm.s.GCPtrMappingFixed = 0;
1992	pVM->pgm.s.cbMappingFixed = 0;
1993
1994	/* Exit the guest paging mode before the pgm pool gets reset.
1995	* Important to clean up the amd64 case.
1996	*/
1997	int rc = PGM_GST_PFN(Exit, pVM)(pVM);
1998	AssertRC(rc);
1999	#ifdef DEBUG
2000	DBGFR3InfoLog(pVM, "mappings", NULL);
2001	DBGFR3InfoLog(pVM, "handlers", "all nostat");
2002	#endif
2003
2004	/*
2005	* Reset the shadow page pool.
2006	*/
2007	pgmR3PoolReset(pVM);
2008
2009	/*
2010	* Re-init other members.
2011	*/
2012	pVM->pgm.s.fA20Enabled = true;
2013
2014	/*
2015	* Clear the FFs PGM owns.
2016	*/
2017	VM_FF_CLEAR(pVM, VM_FF_PGM_SYNC_CR3);
2018	VM_FF_CLEAR(pVM, VM_FF_PGM_SYNC_CR3_NON_GLOBAL);
2019
2020	/*
2021	* Reset (zero) RAM pages.
2022	*/
2023	rc = pgmR3PhysRamReset(pVM);
2024	if (RT_SUCCESS(rc))
2025	{
2026	#ifdef VBOX_WITH_NEW_PHYS_CODE
2027	/*
2028	* Reset (zero) shadow ROM pages.
2029	*/
2030	rc = pgmR3PhysRomReset(pVM);
2031	#endif
2032	if (RT_SUCCESS(rc))
2033	{
2034	/*
2035	* Switch mode back to real mode.
2036	*/
2037	rc = PGMR3ChangeMode(pVM, PGMMODE_REAL);
2038	STAM_REL_COUNTER_RESET(&pVM->pgm.s.cGuestModeChanges);
2039	}
2040	}
2041
2042	pgmUnlock(pVM);
2043	//return rc;
2044	AssertReleaseRC(rc);
2045	}
2046
2047
2048	#ifdef VBOX_STRICT
2049	/**
2050	* VM state change callback for clearing fNoMorePhysWrites after
2051	* a snapshot has been created.
2052	*/
2053	static DECLCALLBACK(void) pgmR3ResetNoMorePhysWritesFlag(PVM pVM, VMSTATE enmState, VMSTATE enmOldState, void *pvUser)
2054	{
2055	if (enmState == VMSTATE_RUNNING)
2056	pVM->pgm.s.fNoMorePhysWrites = false;
2057	}
2058	#endif
2059
2060
2061	/**
2062	* Terminates the PGM.
2063	*
2064	* @returns VBox status code.
2065	* @param pVM Pointer to VM structure.
2066	*/
2067	PGMR3DECL(int) PGMR3Term(PVM pVM)
2068	{
2069	return PDMR3CritSectDelete(&pVM->pgm.s.CritSect);
2070	}
2071
2072
2073	/**
2074	* Execute state save operation.
2075	*
2076	* @returns VBox status code.
2077	* @param pVM VM Handle.
2078	* @param pSSM SSM operation handle.
2079	*/
2080	static DECLCALLBACK(int) pgmR3Save(PVM pVM, PSSMHANDLE pSSM)
2081	{
2082	PPGM pPGM = &pVM->pgm.s;
2083
2084	/* No more writes to physical memory after this point! */
2085	pVM->pgm.s.fNoMorePhysWrites = true;
2086
2087	/*
2088	* Save basic data (required / unaffected by relocation).
2089	*/
2090	#if 1
2091	SSMR3PutBool(pSSM, pPGM->fMappingsFixed);
2092	#else
2093	SSMR3PutUInt(pSSM, pPGM->fMappingsFixed);
2094	#endif
2095	SSMR3PutGCPtr(pSSM, pPGM->GCPtrMappingFixed);
2096	SSMR3PutU32(pSSM, pPGM->cbMappingFixed);
2097	SSMR3PutUInt(pSSM, pPGM->cbRamSize);
2098	SSMR3PutGCPhys(pSSM, pPGM->GCPhysA20Mask);
2099	SSMR3PutUInt(pSSM, pPGM->fA20Enabled);
2100	SSMR3PutUInt(pSSM, pPGM->fSyncFlags);
2101	SSMR3PutUInt(pSSM, pPGM->enmGuestMode);
2102	SSMR3PutU32(pSSM, ~0); /* Separator. */
2103
2104	/*
2105	* The guest mappings.
2106	*/
2107	uint32_t i = 0;
2108	for (PPGMMAPPING pMapping = pPGM->pMappingsR3; pMapping; pMapping = pMapping->pNextR3, i++)
2109	{
2110	SSMR3PutU32(pSSM, i);
2111	SSMR3PutStrZ(pSSM, pMapping->pszDesc); /* This is the best unique id we have... */
2112	SSMR3PutGCPtr(pSSM, pMapping->GCPtr);
2113	SSMR3PutGCUIntPtr(pSSM, pMapping->cPTs);
2114	/* flags are done by the mapping owners! */
2115	}
2116	SSMR3PutU32(pSSM, ~0); /* terminator. */
2117
2118	/*
2119	* Ram range flags and bits.
2120	*/
2121	i = 0;
2122	for (PPGMRAMRANGE pRam = pPGM->pRamRangesR3; pRam; pRam = pRam->pNextR3, i++)
2123	{
2124	/** @todo MMIO ranges may move (PCI reconfig), we currently assume they don't. */
2125
2126	SSMR3PutU32(pSSM, i);
2127	SSMR3PutGCPhys(pSSM, pRam->GCPhys);
2128	SSMR3PutGCPhys(pSSM, pRam->GCPhysLast);
2129	SSMR3PutGCPhys(pSSM, pRam->cb);
2130	SSMR3PutU8(pSSM, !!pRam->pvHC); /* boolean indicating memory or not. */
2131
2132	/* Flags. */
2133	const unsigned cPages = pRam->cb >> PAGE_SHIFT;
2134	for (unsigned iPage = 0; iPage < cPages; iPage++)
2135	SSMR3PutU16(pSSM, (uint16_t)(pRam->aPages[iPage].HCPhys & ~X86_PTE_PAE_PG_MASK)); /** @todo PAGE FLAGS */
2136
2137	/* any memory associated with the range. */
2138	if (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)
2139	{
2140	for (unsigned iChunk = 0; iChunk < (pRam->cb >> PGM_DYNAMIC_CHUNK_SHIFT); iChunk++)
2141	{
2142	if (pRam->pavHCChunkHC[iChunk])
2143	{
2144	SSMR3PutU8(pSSM, 1); /* chunk present */
2145	SSMR3PutMem(pSSM, pRam->pavHCChunkHC[iChunk], PGM_DYNAMIC_CHUNK_SIZE);
2146	}
2147	else
2148	SSMR3PutU8(pSSM, 0); /* no chunk present */
2149	}
2150	}
2151	else if (pRam->pvHC)
2152	{
2153	int rc = SSMR3PutMem(pSSM, pRam->pvHC, pRam->cb);
2154	if (VBOX_FAILURE(rc))
2155	{
2156	Log(("pgmR3Save: SSMR3PutMem(, %p, %#x) -> %Vrc\n", pRam->pvHC, pRam->cb, rc));
2157	return rc;
2158	}
2159	}
2160	}
2161	return SSMR3PutU32(pSSM, ~0); /* terminator. */
2162	}
2163
2164
2165	/**
2166	* Execute state load operation.
2167	*
2168	* @returns VBox status code.
2169	* @param pVM VM Handle.
2170	* @param pSSM SSM operation handle.
2171	* @param u32Version Data layout version.
2172	*/
2173	static DECLCALLBACK(int) pgmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version)
2174	{
2175	/*
2176	* Validate version.
2177	*/
2178	if (u32Version != PGM_SAVED_STATE_VERSION)
2179	{
2180	Log(("pgmR3Load: Invalid version u32Version=%d (current %d)!\n", u32Version, PGM_SAVED_STATE_VERSION));
2181	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
2182	}
2183
2184	/*
2185	* Call the reset function to make sure all the memory is cleared.
2186	*/
2187	PGMR3Reset(pVM);
2188
2189	/*
2190	* Load basic data (required / unaffected by relocation).
2191	*/
2192	PPGM pPGM = &pVM->pgm.s;
2193	#if 1
2194	SSMR3GetBool(pSSM, &pPGM->fMappingsFixed);
2195	#else
2196	uint32_t u;
2197	SSMR3GetU32(pSSM, &u);
2198	pPGM->fMappingsFixed = u;
2199	#endif
2200	SSMR3GetGCPtr(pSSM, &pPGM->GCPtrMappingFixed);
2201	SSMR3GetU32(pSSM, &pPGM->cbMappingFixed);
2202
2203	RTUINT cbRamSize;
2204	int rc = SSMR3GetU32(pSSM, &cbRamSize);
2205	if (VBOX_FAILURE(rc))
2206	return rc;
2207	if (cbRamSize != pPGM->cbRamSize)
2208	return VERR_SSM_LOAD_MEMORY_SIZE_MISMATCH;
2209	SSMR3GetGCPhys(pSSM, &pPGM->GCPhysA20Mask);
2210	SSMR3GetUInt(pSSM, &pPGM->fA20Enabled);
2211	SSMR3GetUInt(pSSM, &pPGM->fSyncFlags);
2212	RTUINT uGuestMode;
2213	SSMR3GetUInt(pSSM, &uGuestMode);
2214	pPGM->enmGuestMode = (PGMMODE)uGuestMode;
2215
2216	/* check separator. */
2217	uint32_t u32Sep;
2218	SSMR3GetU32(pSSM, &u32Sep);
2219	if (VBOX_FAILURE(rc))
2220	return rc;
2221	if (u32Sep != (uint32_t)~0)
2222	{
2223	AssertMsgFailed(("u32Sep=%#x (first)\n", u32Sep));
2224	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2225	}
2226
2227	/*
2228	* The guest mappings.
2229	*/
2230	uint32_t i = 0;
2231	for (;; i++)
2232	{
2233	/* Check the seqence number / separator. */
2234	rc = SSMR3GetU32(pSSM, &u32Sep);
2235	if (VBOX_FAILURE(rc))
2236	return rc;
2237	if (u32Sep == ~0U)
2238	break;
2239	if (u32Sep != i)
2240	{
2241	AssertMsgFailed(("u32Sep=%#x (last)\n", u32Sep));
2242	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2243	}
2244
2245	/* get the mapping details. */
2246	char szDesc[256];
2247	szDesc[0] = '\0';
2248	rc = SSMR3GetStrZ(pSSM, szDesc, sizeof(szDesc));
2249	if (VBOX_FAILURE(rc))
2250	return rc;
2251	RTGCPTR GCPtr;
2252	SSMR3GetGCPtr(pSSM, &GCPtr);
2253	RTGCUINTPTR cPTs;
2254	rc = SSMR3GetGCUIntPtr(pSSM, &cPTs);
2255	if (VBOX_FAILURE(rc))
2256	return rc;
2257
2258	/* find matching range. */
2259	PPGMMAPPING pMapping;
2260	for (pMapping = pPGM->pMappingsR3; pMapping; pMapping = pMapping->pNextR3)
2261	if ( pMapping->cPTs == cPTs
2262	&& !strcmp(pMapping->pszDesc, szDesc))
2263	break;
2264	if (!pMapping)
2265	{
2266	LogRel(("Couldn't find mapping: cPTs=%#x szDesc=%s (GCPtr=%VGv)\n",
2267	cPTs, szDesc, GCPtr));
2268	AssertFailed();
2269	return VERR_SSM_LOAD_CONFIG_MISMATCH;
2270	}
2271
2272	/* relocate it. */
2273	if (pMapping->GCPtr != GCPtr)
2274	{
2275	AssertMsg((GCPtr >> X86_PD_SHIFT << X86_PD_SHIFT) == GCPtr, ("GCPtr=%VGv\n", GCPtr));
2276	#if HC_ARCH_BITS == 64
2277	LogRel(("Mapping: %VGv -> %VGv %s\n", pMapping->GCPtr, GCPtr, pMapping->pszDesc));
2278	#endif
2279	pgmR3MapRelocate(pVM, pMapping, pMapping->GCPtr, GCPtr);
2280	}
2281	else
2282	Log(("pgmR3Load: '%s' needed no relocation (%VGv)\n", szDesc, GCPtr));
2283	}
2284
2285	/*
2286	* Ram range flags and bits.
2287	*/
2288	i = 0;
2289	for (PPGMRAMRANGE pRam = pPGM->pRamRangesR3; pRam; pRam = pRam->pNextR3, i++)
2290	{
2291	/** @todo MMIO ranges may move (PCI reconfig), we currently assume they don't. */
2292	/* Check the seqence number / separator. */
2293	rc = SSMR3GetU32(pSSM, &u32Sep);
2294	if (VBOX_FAILURE(rc))
2295	return rc;
2296	if (u32Sep == ~0U)
2297	break;
2298	if (u32Sep != i)
2299	{
2300	AssertMsgFailed(("u32Sep=%#x (last)\n", u32Sep));
2301	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2302	}
2303
2304	/* Get the range details. */
2305	RTGCPHYS GCPhys;
2306	SSMR3GetGCPhys(pSSM, &GCPhys);
2307	RTGCPHYS GCPhysLast;
2308	SSMR3GetGCPhys(pSSM, &GCPhysLast);
2309	RTGCPHYS cb;
2310	SSMR3GetGCPhys(pSSM, &cb);
2311	uint8_t fHaveBits;
2312	rc = SSMR3GetU8(pSSM, &fHaveBits);
2313	if (VBOX_FAILURE(rc))
2314	return rc;
2315	if (fHaveBits & ~1)
2316	{
2317	AssertMsgFailed(("u32Sep=%#x (last)\n", u32Sep));
2318	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2319	}
2320
2321	/* Match it up with the current range. */
2322	if ( GCPhys != pRam->GCPhys
2323	\|\| GCPhysLast != pRam->GCPhysLast
2324	\|\| cb != pRam->cb
2325	\|\| fHaveBits != !!pRam->pvHC)
2326	{
2327	LogRel(("Ram range: %VGp-%VGp %VGp bytes %s\n"
2328	"State : %VGp-%VGp %VGp bytes %s\n",
2329	pRam->GCPhys, pRam->GCPhysLast, pRam->cb, pRam->pvHC ? "bits" : "nobits",
2330	GCPhys, GCPhysLast, cb, fHaveBits ? "bits" : "nobits"));
2331	/*
2332	* If we're loading a state for debugging purpose, don't make a fuss if
2333	* the MMIO[2] and ROM stuff isn't 100% right, just skip the mismatches.
2334	*/
2335	if ( SSMR3HandleGetAfter(pSSM) != SSMAFTER_DEBUG_IT
2336	\|\| GCPhys < 8 * _1M)
2337	AssertFailedReturn(VERR_SSM_LOAD_CONFIG_MISMATCH);
2338
2339	RTGCPHYS cPages = ((GCPhysLast - GCPhys) + 1) >> PAGE_SHIFT;
2340	while (cPages-- > 0)
2341	{
2342	uint16_t u16Ignore;
2343	SSMR3GetU16(pSSM, &u16Ignore);
2344	}
2345	continue;
2346	}
2347
2348	/* Flags. */
2349	const unsigned cPages = pRam->cb >> PAGE_SHIFT;
2350	for (unsigned iPage = 0; iPage < cPages; iPage++)
2351	{
2352	uint16_t u16 = 0;
2353	SSMR3GetU16(pSSM, &u16);
2354	u16 &= PAGE_OFFSET_MASK & ~( RT_BIT(4) \| RT_BIT(5) \| RT_BIT(6)
2355	\| RT_BIT(7) \| RT_BIT(8) \| RT_BIT(9) \| RT_BIT(10) );
2356	// &= MM_RAM_FLAGS_DYNAMIC_ALLOC \| MM_RAM_FLAGS_RESERVED \| MM_RAM_FLAGS_ROM \| MM_RAM_FLAGS_MMIO \| MM_RAM_FLAGS_MMIO2
2357	pRam->aPages[iPage].HCPhys = PGM_PAGE_GET_HCPHYS(&pRam->aPages[iPage]) \| (RTHCPHYS)u16; /** @todo PAGE FLAGS */
2358	}
2359
2360	/* any memory associated with the range. */
2361	if (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)
2362	{
2363	for (unsigned iChunk = 0; iChunk < (pRam->cb >> PGM_DYNAMIC_CHUNK_SHIFT); iChunk++)
2364	{
2365	uint8_t fValidChunk;
2366
2367	rc = SSMR3GetU8(pSSM, &fValidChunk);
2368	if (VBOX_FAILURE(rc))
2369	return rc;
2370	if (fValidChunk > 1)
2371	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2372
2373	if (fValidChunk)
2374	{
2375	if (!pRam->pavHCChunkHC[iChunk])
2376	{
2377	rc = pgmr3PhysGrowRange(pVM, pRam->GCPhys + iChunk * PGM_DYNAMIC_CHUNK_SIZE);
2378	if (VBOX_FAILURE(rc))
2379	return rc;
2380	}
2381	Assert(pRam->pavHCChunkHC[iChunk]);
2382
2383	SSMR3GetMem(pSSM, pRam->pavHCChunkHC[iChunk], PGM_DYNAMIC_CHUNK_SIZE);
2384	}
2385	/* else nothing to do */
2386	}
2387	}
2388	else if (pRam->pvHC)
2389	{
2390	int rc = SSMR3GetMem(pSSM, pRam->pvHC, pRam->cb);
2391	if (VBOX_FAILURE(rc))
2392	{
2393	Log(("pgmR3Save: SSMR3GetMem(, %p, %#x) -> %Vrc\n", pRam->pvHC, pRam->cb, rc));
2394	return rc;
2395	}
2396	}
2397	}
2398
2399	/*
2400	* We require a full resync now.
2401	*/
2402	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3_NON_GLOBAL);
2403	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
2404	pPGM->fSyncFlags \|= PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL;
2405	pPGM->fPhysCacheFlushPending = true;
2406	pgmR3HandlerPhysicalUpdateAll(pVM);
2407
2408	/*
2409	* Change the paging mode.
2410	*/
2411	rc = PGMR3ChangeMode(pVM, pPGM->enmGuestMode);
2412
2413	/* Restore pVM->pgm.s.GCPhysCR3. */
2414	Assert(pVM->pgm.s.GCPhysCR3 == NIL_RTGCPHYS);
2415	RTGCPHYS GCPhysCR3 = CPUMGetGuestCR3(pVM);
2416	if ( pVM->pgm.s.enmGuestMode == PGMMODE_PAE
2417	\|\| pVM->pgm.s.enmGuestMode == PGMMODE_PAE_NX
2418	\|\| pVM->pgm.s.enmGuestMode == PGMMODE_AMD64
2419	\|\| pVM->pgm.s.enmGuestMode == PGMMODE_AMD64_NX)
2420	GCPhysCR3 = (GCPhysCR3 & X86_CR3_PAE_PAGE_MASK);
2421	else
2422	GCPhysCR3 = (GCPhysCR3 & X86_CR3_PAGE_MASK);
2423	pVM->pgm.s.GCPhysCR3 = GCPhysCR3;
2424
2425	return rc;
2426	}
2427
2428
2429	/**
2430	* Show paging mode.
2431	*
2432	* @param pVM VM Handle.
2433	* @param pHlp The info helpers.
2434	* @param pszArgs "all" (default), "guest", "shadow" or "host".
2435	*/
2436	static DECLCALLBACK(void) pgmR3InfoMode(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2437	{
2438	/* digest argument. */
2439	bool fGuest, fShadow, fHost;
2440	if (pszArgs)
2441	pszArgs = RTStrStripL(pszArgs);
2442	if (!pszArgs \|\| !*pszArgs \|\| strstr(pszArgs, "all"))
2443	fShadow = fHost = fGuest = true;
2444	else
2445	{
2446	fShadow = fHost = fGuest = false;
2447	if (strstr(pszArgs, "guest"))
2448	fGuest = true;
2449	if (strstr(pszArgs, "shadow"))
2450	fShadow = true;
2451	if (strstr(pszArgs, "host"))
2452	fHost = true;
2453	}
2454
2455	/* print info. */
2456	if (fGuest)
2457	pHlp->pfnPrintf(pHlp, "Guest paging mode: %s, changed %RU64 times, A20 %s\n",
2458	PGMGetModeName(pVM->pgm.s.enmGuestMode), pVM->pgm.s.cGuestModeChanges.c,
2459	pVM->pgm.s.fA20Enabled ? "enabled" : "disabled");
2460	if (fShadow)
2461	pHlp->pfnPrintf(pHlp, "Shadow paging mode: %s\n", PGMGetModeName(pVM->pgm.s.enmShadowMode));
2462	if (fHost)
2463	{
2464	const char *psz;
2465	switch (pVM->pgm.s.enmHostMode)
2466	{
2467	case SUPPAGINGMODE_INVALID: psz = "invalid"; break;
2468	case SUPPAGINGMODE_32_BIT: psz = "32-bit"; break;
2469	case SUPPAGINGMODE_32_BIT_GLOBAL: psz = "32-bit+G"; break;
2470	case SUPPAGINGMODE_PAE: psz = "PAE"; break;
2471	case SUPPAGINGMODE_PAE_GLOBAL: psz = "PAE+G"; break;
2472	case SUPPAGINGMODE_PAE_NX: psz = "PAE+NX"; break;
2473	case SUPPAGINGMODE_PAE_GLOBAL_NX: psz = "PAE+G+NX"; break;
2474	case SUPPAGINGMODE_AMD64: psz = "AMD64"; break;
2475	case SUPPAGINGMODE_AMD64_GLOBAL: psz = "AMD64+G"; break;
2476	case SUPPAGINGMODE_AMD64_NX: psz = "AMD64+NX"; break;
2477	case SUPPAGINGMODE_AMD64_GLOBAL_NX: psz = "AMD64+G+NX"; break;
2478	default: psz = "unknown"; break;
2479	}
2480	pHlp->pfnPrintf(pHlp, "Host paging mode: %s\n", psz);
2481	}
2482	}
2483
2484
2485	/**
2486	* Dump registered MMIO ranges to the log.
2487	*
2488	* @param pVM VM Handle.
2489	* @param pHlp The info helpers.
2490	* @param pszArgs Arguments, ignored.
2491	*/
2492	static DECLCALLBACK(void) pgmR3PhysInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2493	{
2494	NOREF(pszArgs);
2495	pHlp->pfnPrintf(pHlp,
2496	"RAM ranges (pVM=%p)\n"
2497	"%.s %.s\n",
2498	pVM,
2499	sizeof(RTGCPHYS) * 4 + 1, "GC Phys Range ",
2500	sizeof(RTHCPTR) * 2, "pvHC ");
2501
2502	for (PPGMRAMRANGE pCur = pVM->pgm.s.pRamRangesR3; pCur; pCur = pCur->pNextR3)
2503	pHlp->pfnPrintf(pHlp,
2504	"%RGp-%RGp %RHv %s\n",
2505	pCur->GCPhys,
2506	pCur->GCPhysLast,
2507	pCur->pvHC,
2508	pCur->pszDesc);
2509	}
2510
2511	/**
2512	* Dump the page directory to the log.
2513	*
2514	* @param pVM VM Handle.
2515	* @param pHlp The info helpers.
2516	* @param pszArgs Arguments, ignored.
2517	*/
2518	static DECLCALLBACK(void) pgmR3InfoCr3(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2519	{
2520	/** @todo fix this! Convert the PGMR3DumpHierarchyHC functions to do guest stuff. */
2521	/* Big pages supported? */
2522	const bool fPSE = !!(CPUMGetGuestCR4(pVM) & X86_CR4_PSE);
2523
2524	/* Global pages supported? */
2525	const bool fPGE = !!(CPUMGetGuestCR4(pVM) & X86_CR4_PGE);
2526
2527	NOREF(pszArgs);
2528
2529	/*
2530	* Get page directory addresses.
2531	*/
2532	PX86PD pPDSrc = pVM->pgm.s.pGuestPDHC;
2533	Assert(pPDSrc);
2534	Assert(MMPhysGCPhys2HCVirt(pVM, (RTGCPHYS)(CPUMGetGuestCR3(pVM) & X86_CR3_PAGE_MASK), sizeof(*pPDSrc)) == pPDSrc);
2535
2536	/*
2537	* Iterate the page directory.
2538	*/
2539	for (unsigned iPD = 0; iPD < ELEMENTS(pPDSrc->a); iPD++)
2540	{
2541	X86PDE PdeSrc = pPDSrc->a[iPD];
2542	if (PdeSrc.n.u1Present)
2543	{
2544	if (PdeSrc.b.u1Size && fPSE)
2545	{
2546	pHlp->pfnPrintf(pHlp,
2547	"%04X - %VGp P=%d U=%d RW=%d G=%d - BIG\n",
2548	iPD,
2549	PdeSrc.u & X86_PDE_PG_MASK,
2550	PdeSrc.b.u1Present, PdeSrc.b.u1User, PdeSrc.b.u1Write, PdeSrc.b.u1Global && fPGE);
2551	}
2552	else
2553	{
2554	pHlp->pfnPrintf(pHlp,
2555	"%04X - %VGp P=%d U=%d RW=%d [G=%d]\n",
2556	iPD,
2557	PdeSrc.u & X86_PDE4M_PG_MASK,
2558	PdeSrc.n.u1Present, PdeSrc.n.u1User, PdeSrc.n.u1Write, PdeSrc.b.u1Global && fPGE);
2559	}
2560	}
2561	}
2562	}
2563
2564
2565	/**
2566	* Serivce a VMMCALLHOST_PGM_LOCK call.
2567	*
2568	* @returns VBox status code.
2569	* @param pVM The VM handle.
2570	*/
2571	PDMR3DECL(int) PGMR3LockCall(PVM pVM)
2572	{
2573	int rc = PDMR3CritSectEnterEx(&pVM->pgm.s.CritSect, true /* fHostCall */);
2574	AssertRC(rc);
2575	return rc;
2576	}
2577
2578
2579	/**
2580	* Converts a PGMMODE value to a PGM_TYPE_* \#define.
2581	*
2582	* @returns PGM_TYPE_*.
2583	* @param pgmMode The mode value to convert.
2584	*/
2585	DECLINLINE(unsigned) pgmModeToType(PGMMODE pgmMode)
2586	{
2587	switch (pgmMode)
2588	{
2589	case PGMMODE_REAL: return PGM_TYPE_REAL;
2590	case PGMMODE_PROTECTED: return PGM_TYPE_PROT;
2591	case PGMMODE_32_BIT: return PGM_TYPE_32BIT;
2592	case PGMMODE_PAE:
2593	case PGMMODE_PAE_NX: return PGM_TYPE_PAE;
2594	case PGMMODE_AMD64:
2595	case PGMMODE_AMD64_NX: return PGM_TYPE_AMD64;
2596	case PGMMODE_NESTED: return PGM_TYPE_NESTED;
2597	case PGMMODE_EPT: return PGM_TYPE_EPT;
2598	default:
2599	AssertFatalMsgFailed(("pgmMode=%d\n", pgmMode));
2600	}
2601	}
2602
2603
2604	/**
2605	* Gets the index into the paging mode data array of a SHW+GST mode.
2606	*
2607	* @returns PGM::paPagingData index.
2608	* @param uShwType The shadow paging mode type.
2609	* @param uGstType The guest paging mode type.
2610	*/
2611	DECLINLINE(unsigned) pgmModeDataIndex(unsigned uShwType, unsigned uGstType)
2612	{
2613	Assert(uShwType >= PGM_TYPE_32BIT && uShwType <= PGM_TYPE_NESTED);
2614	Assert(uGstType >= PGM_TYPE_REAL && uGstType <= PGM_TYPE_AMD64);
2615	return (uShwType - PGM_TYPE_32BIT) * (PGM_TYPE_AMD64 - PGM_TYPE_REAL + 1)
2616	+ (uGstType - PGM_TYPE_REAL);
2617	}
2618
2619
2620	/**
2621	* Gets the index into the paging mode data array of a SHW+GST mode.
2622	*
2623	* @returns PGM::paPagingData index.
2624	* @param enmShw The shadow paging mode.
2625	* @param enmGst The guest paging mode.
2626	*/
2627	DECLINLINE(unsigned) pgmModeDataIndexByMode(PGMMODE enmShw, PGMMODE enmGst)
2628	{
2629	Assert(enmShw >= PGMMODE_32_BIT && enmShw <= PGMMODE_MAX);
2630	Assert(enmGst > PGMMODE_INVALID && enmGst < PGMMODE_MAX);
2631	return pgmModeDataIndex(pgmModeToType(enmShw), pgmModeToType(enmGst));
2632	}
2633
2634
2635	/**
2636	* Calculates the max data index.
2637	* @returns The number of entries in the paging data array.
2638	*/
2639	DECLINLINE(unsigned) pgmModeDataMaxIndex(void)
2640	{
2641	return pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_AMD64) + 1;
2642	}
2643
2644
2645	/**
2646	* Initializes the paging mode data kept in PGM::paModeData.
2647	*
2648	* @param pVM The VM handle.
2649	* @param fResolveGCAndR0 Indicate whether or not GC and Ring-0 symbols can be resolved now.
2650	* This is used early in the init process to avoid trouble with PDM
2651	* not being initialized yet.
2652	*/
2653	static int pgmR3ModeDataInit(PVM pVM, bool fResolveGCAndR0)
2654	{
2655	PPGMMODEDATA pModeData;
2656	int rc;
2657
2658	/*
2659	* Allocate the array on the first call.
2660	*/
2661	if (!pVM->pgm.s.paModeData)
2662	{
2663	pVM->pgm.s.paModeData = (PPGMMODEDATA)MMR3HeapAllocZ(pVM, MM_TAG_PGM, sizeof(PGMMODEDATA) * pgmModeDataMaxIndex());
2664	AssertReturn(pVM->pgm.s.paModeData, VERR_NO_MEMORY);
2665	}
2666
2667	/*
2668	* Initialize the array entries.
2669	*/
2670	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_32BIT, PGM_TYPE_REAL)];
2671	pModeData->uShwType = PGM_TYPE_32BIT;
2672	pModeData->uGstType = PGM_TYPE_REAL;
2673	rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2674	rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2675	rc = PGM_BTH_NAME_32BIT_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2676
2677	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_32BIT, PGMMODE_PROTECTED)];
2678	pModeData->uShwType = PGM_TYPE_32BIT;
2679	pModeData->uGstType = PGM_TYPE_PROT;
2680	rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2681	rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2682	rc = PGM_BTH_NAME_32BIT_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2683
2684	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_32BIT, PGM_TYPE_32BIT)];
2685	pModeData->uShwType = PGM_TYPE_32BIT;
2686	pModeData->uGstType = PGM_TYPE_32BIT;
2687	rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2688	rc = PGM_GST_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2689	rc = PGM_BTH_NAME_32BIT_32BIT(InitData)(pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2690
2691	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_REAL)];
2692	pModeData->uShwType = PGM_TYPE_PAE;
2693	pModeData->uGstType = PGM_TYPE_REAL;
2694	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2695	rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2696	rc = PGM_BTH_NAME_PAE_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2697
2698	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_PROT)];
2699	pModeData->uShwType = PGM_TYPE_PAE;
2700	pModeData->uGstType = PGM_TYPE_PROT;
2701	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2702	rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2703	rc = PGM_BTH_NAME_PAE_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2704
2705	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_32BIT)];
2706	pModeData->uShwType = PGM_TYPE_PAE;
2707	pModeData->uGstType = PGM_TYPE_32BIT;
2708	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2709	rc = PGM_GST_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2710	rc = PGM_BTH_NAME_PAE_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2711
2712	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_PAE)];
2713	pModeData->uShwType = PGM_TYPE_PAE;
2714	pModeData->uGstType = PGM_TYPE_PAE;
2715	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2716	rc = PGM_GST_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2717	rc = PGM_BTH_NAME_PAE_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2718
2719	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_AMD64, PGM_TYPE_AMD64)];
2720	pModeData->uShwType = PGM_TYPE_AMD64;
2721	pModeData->uGstType = PGM_TYPE_AMD64;
2722	rc = PGM_SHW_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2723	rc = PGM_GST_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2724	rc = PGM_BTH_NAME_AMD64_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2725
2726	/* The nested paging mode. */
2727	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_REAL)];
2728	pModeData->uShwType = PGM_TYPE_NESTED;
2729	pModeData->uGstType = PGM_TYPE_REAL;
2730	rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2731	rc = PGM_BTH_NAME_NESTED_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2732
2733	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGMMODE_PROTECTED)];
2734	pModeData->uShwType = PGM_TYPE_NESTED;
2735	pModeData->uGstType = PGM_TYPE_PROT;
2736	rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2737	rc = PGM_BTH_NAME_NESTED_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2738
2739	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_32BIT)];
2740	pModeData->uShwType = PGM_TYPE_NESTED;
2741	pModeData->uGstType = PGM_TYPE_32BIT;
2742	rc = PGM_GST_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2743	rc = PGM_BTH_NAME_NESTED_32BIT(InitData)(pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2744
2745	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_PAE)];
2746	pModeData->uShwType = PGM_TYPE_NESTED;
2747	pModeData->uGstType = PGM_TYPE_PAE;
2748	rc = PGM_GST_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2749	rc = PGM_BTH_NAME_NESTED_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2750
2751	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_AMD64)];
2752	pModeData->uShwType = PGM_TYPE_NESTED;
2753	pModeData->uGstType = PGM_TYPE_AMD64;
2754	rc = PGM_GST_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2755	rc = PGM_BTH_NAME_NESTED_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2756
2757	/* The shadow part of the nested callback mode depends on the host paging mode (AMD-V only). */
2758	switch(pVM->pgm.s.enmHostMode)
2759	{
2760	case SUPPAGINGMODE_32_BIT:
2761	case SUPPAGINGMODE_32_BIT_GLOBAL:
2762	for (unsigned i=PGM_TYPE_REAL;i<=PGM_TYPE_AMD64;i++)
2763	{
2764	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, i)];
2765	rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2766	}
2767	break;
2768
2769	case SUPPAGINGMODE_PAE:
2770	case SUPPAGINGMODE_PAE_NX:
2771	case SUPPAGINGMODE_PAE_GLOBAL:
2772	case SUPPAGINGMODE_PAE_GLOBAL_NX:
2773	for (unsigned i=PGM_TYPE_REAL;i<=PGM_TYPE_AMD64;i++)
2774	{
2775	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, i)];
2776	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2777	}
2778	break;
2779
2780	case SUPPAGINGMODE_AMD64:
2781	case SUPPAGINGMODE_AMD64_GLOBAL:
2782	case SUPPAGINGMODE_AMD64_NX:
2783	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
2784	for (unsigned i=PGM_TYPE_REAL;i<=PGM_TYPE_AMD64;i++)
2785	{
2786	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, i)];
2787	rc = PGM_SHW_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2788	}
2789	break;
2790	default:
2791	AssertFailed();
2792	break;
2793	}
2794
2795	#ifdef PGM_WITH_EPT
2796	/* Extended paging (EPT) / Intel VT-x */
2797	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_REAL)];
2798	pModeData->uShwType = PGM_TYPE_EPT;
2799	pModeData->uGstType = PGM_TYPE_REAL;
2800	rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2801	rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2802	rc = PGM_BTH_NAME_EPT_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2803
2804	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_PROT)];
2805	pModeData->uShwType = PGM_TYPE_EPT;
2806	pModeData->uGstType = PGM_TYPE_PROT;
2807	rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2808	rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2809	rc = PGM_BTH_NAME_EPT_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2810
2811	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_32BIT)];
2812	pModeData->uShwType = PGM_TYPE_EPT;
2813	pModeData->uGstType = PGM_TYPE_32BIT;
2814	rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2815	rc = PGM_GST_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2816	rc = PGM_BTH_NAME_EPT_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2817
2818	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_PAE)];
2819	pModeData->uShwType = PGM_TYPE_EPT;
2820	pModeData->uGstType = PGM_TYPE_PAE;
2821	rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2822	rc = PGM_GST_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2823	rc = PGM_BTH_NAME_EPT_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2824
2825	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_AMD64)];
2826	pModeData->uShwType = PGM_TYPE_EPT;
2827	pModeData->uGstType = PGM_TYPE_AMD64;
2828	rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2829	rc = PGM_GST_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2830	rc = PGM_BTH_NAME_EPT_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2831	#endif /* PGM_WITH_EPT */
2832	return VINF_SUCCESS;
2833	}
2834
2835
2836	/**
2837	* Switch to different (or relocated in the relocate case) mode data.
2838	*
2839	* @param pVM The VM handle.
2840	* @param enmShw The the shadow paging mode.
2841	* @param enmGst The the guest paging mode.
2842	*/
2843	static void pgmR3ModeDataSwitch(PVM pVM, PGMMODE enmShw, PGMMODE enmGst)
2844	{
2845	PPGMMODEDATA pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndexByMode(enmShw, enmGst)];
2846
2847	Assert(pModeData->uGstType == pgmModeToType(enmGst));
2848	Assert(pModeData->uShwType == pgmModeToType(enmShw));
2849
2850	/* shadow */
2851	pVM->pgm.s.pfnR3ShwRelocate = pModeData->pfnR3ShwRelocate;
2852	pVM->pgm.s.pfnR3ShwExit = pModeData->pfnR3ShwExit;
2853	pVM->pgm.s.pfnR3ShwGetPage = pModeData->pfnR3ShwGetPage;
2854	Assert(pVM->pgm.s.pfnR3ShwGetPage);
2855	pVM->pgm.s.pfnR3ShwModifyPage = pModeData->pfnR3ShwModifyPage;
2856
2857	pVM->pgm.s.pfnGCShwGetPage = pModeData->pfnGCShwGetPage;
2858	pVM->pgm.s.pfnGCShwModifyPage = pModeData->pfnGCShwModifyPage;
2859
2860	pVM->pgm.s.pfnR0ShwGetPage = pModeData->pfnR0ShwGetPage;
2861	pVM->pgm.s.pfnR0ShwModifyPage = pModeData->pfnR0ShwModifyPage;
2862
2863
2864	/* guest */
2865	pVM->pgm.s.pfnR3GstRelocate = pModeData->pfnR3GstRelocate;
2866	pVM->pgm.s.pfnR3GstExit = pModeData->pfnR3GstExit;
2867	pVM->pgm.s.pfnR3GstGetPage = pModeData->pfnR3GstGetPage;
2868	Assert(pVM->pgm.s.pfnR3GstGetPage);
2869	pVM->pgm.s.pfnR3GstModifyPage = pModeData->pfnR3GstModifyPage;
2870	pVM->pgm.s.pfnR3GstGetPDE = pModeData->pfnR3GstGetPDE;
2871	pVM->pgm.s.pfnR3GstMonitorCR3 = pModeData->pfnR3GstMonitorCR3;
2872	pVM->pgm.s.pfnR3GstUnmonitorCR3 = pModeData->pfnR3GstUnmonitorCR3;
2873	pVM->pgm.s.pfnR3GstMapCR3 = pModeData->pfnR3GstMapCR3;
2874	pVM->pgm.s.pfnR3GstUnmapCR3 = pModeData->pfnR3GstUnmapCR3;
2875	pVM->pgm.s.pfnR3GstWriteHandlerCR3 = pModeData->pfnR3GstWriteHandlerCR3;
2876	pVM->pgm.s.pszR3GstWriteHandlerCR3 = pModeData->pszR3GstWriteHandlerCR3;
2877	pVM->pgm.s.pfnR3GstPAEWriteHandlerCR3 = pModeData->pfnR3GstPAEWriteHandlerCR3;
2878	pVM->pgm.s.pszR3GstPAEWriteHandlerCR3 = pModeData->pszR3GstPAEWriteHandlerCR3;
2879
2880	pVM->pgm.s.pfnGCGstGetPage = pModeData->pfnGCGstGetPage;
2881	pVM->pgm.s.pfnGCGstModifyPage = pModeData->pfnGCGstModifyPage;
2882	pVM->pgm.s.pfnGCGstGetPDE = pModeData->pfnGCGstGetPDE;
2883	pVM->pgm.s.pfnGCGstMonitorCR3 = pModeData->pfnGCGstMonitorCR3;
2884	pVM->pgm.s.pfnGCGstUnmonitorCR3 = pModeData->pfnGCGstUnmonitorCR3;
2885	pVM->pgm.s.pfnGCGstMapCR3 = pModeData->pfnGCGstMapCR3;
2886	pVM->pgm.s.pfnGCGstUnmapCR3 = pModeData->pfnGCGstUnmapCR3;
2887	pVM->pgm.s.pfnGCGstWriteHandlerCR3 = pModeData->pfnGCGstWriteHandlerCR3;
2888	pVM->pgm.s.pfnGCGstPAEWriteHandlerCR3 = pModeData->pfnGCGstPAEWriteHandlerCR3;
2889
2890	pVM->pgm.s.pfnR0GstGetPage = pModeData->pfnR0GstGetPage;
2891	pVM->pgm.s.pfnR0GstModifyPage = pModeData->pfnR0GstModifyPage;
2892	pVM->pgm.s.pfnR0GstGetPDE = pModeData->pfnR0GstGetPDE;
2893	pVM->pgm.s.pfnR0GstMonitorCR3 = pModeData->pfnR0GstMonitorCR3;
2894	pVM->pgm.s.pfnR0GstUnmonitorCR3 = pModeData->pfnR0GstUnmonitorCR3;
2895	pVM->pgm.s.pfnR0GstMapCR3 = pModeData->pfnR0GstMapCR3;
2896	pVM->pgm.s.pfnR0GstUnmapCR3 = pModeData->pfnR0GstUnmapCR3;
2897	pVM->pgm.s.pfnR0GstWriteHandlerCR3 = pModeData->pfnR0GstWriteHandlerCR3;
2898	pVM->pgm.s.pfnR0GstPAEWriteHandlerCR3 = pModeData->pfnR0GstPAEWriteHandlerCR3;
2899
2900
2901	/* both */
2902	pVM->pgm.s.pfnR3BthRelocate = pModeData->pfnR3BthRelocate;
2903	pVM->pgm.s.pfnR3BthTrap0eHandler = pModeData->pfnR3BthTrap0eHandler;
2904	pVM->pgm.s.pfnR3BthInvalidatePage = pModeData->pfnR3BthInvalidatePage;
2905	pVM->pgm.s.pfnR3BthSyncCR3 = pModeData->pfnR3BthSyncCR3;
2906	Assert(pVM->pgm.s.pfnR3BthSyncCR3);
2907	pVM->pgm.s.pfnR3BthSyncPage = pModeData->pfnR3BthSyncPage;
2908	pVM->pgm.s.pfnR3BthPrefetchPage = pModeData->pfnR3BthPrefetchPage;
2909	pVM->pgm.s.pfnR3BthVerifyAccessSyncPage = pModeData->pfnR3BthVerifyAccessSyncPage;
2910	#ifdef VBOX_STRICT
2911	pVM->pgm.s.pfnR3BthAssertCR3 = pModeData->pfnR3BthAssertCR3;
2912	#endif
2913
2914	pVM->pgm.s.pfnGCBthTrap0eHandler = pModeData->pfnGCBthTrap0eHandler;
2915	pVM->pgm.s.pfnGCBthInvalidatePage = pModeData->pfnGCBthInvalidatePage;
2916	pVM->pgm.s.pfnGCBthSyncCR3 = pModeData->pfnGCBthSyncCR3;
2917	pVM->pgm.s.pfnGCBthSyncPage = pModeData->pfnGCBthSyncPage;
2918	pVM->pgm.s.pfnGCBthPrefetchPage = pModeData->pfnGCBthPrefetchPage;
2919	pVM->pgm.s.pfnGCBthVerifyAccessSyncPage = pModeData->pfnGCBthVerifyAccessSyncPage;
2920	#ifdef VBOX_STRICT
2921	pVM->pgm.s.pfnGCBthAssertCR3 = pModeData->pfnGCBthAssertCR3;
2922	#endif
2923
2924	pVM->pgm.s.pfnR0BthTrap0eHandler = pModeData->pfnR0BthTrap0eHandler;
2925	pVM->pgm.s.pfnR0BthInvalidatePage = pModeData->pfnR0BthInvalidatePage;
2926	pVM->pgm.s.pfnR0BthSyncCR3 = pModeData->pfnR0BthSyncCR3;
2927	pVM->pgm.s.pfnR0BthSyncPage = pModeData->pfnR0BthSyncPage;
2928	pVM->pgm.s.pfnR0BthPrefetchPage = pModeData->pfnR0BthPrefetchPage;
2929	pVM->pgm.s.pfnR0BthVerifyAccessSyncPage = pModeData->pfnR0BthVerifyAccessSyncPage;
2930	#ifdef VBOX_STRICT
2931	pVM->pgm.s.pfnR0BthAssertCR3 = pModeData->pfnR0BthAssertCR3;
2932	#endif
2933	}
2934
2935
2936	#ifdef DEBUG_bird
2937	#include <stdlib.h> /* getenv() remove me! */
2938	#endif
2939
2940	/**
2941	* Calculates the shadow paging mode.
2942	*
2943	* @returns The shadow paging mode.
2944	* @param pVM VM handle.
2945	* @param enmGuestMode The guest mode.
2946	* @param enmHostMode The host mode.
2947	* @param enmShadowMode The current shadow mode.
2948	* @param penmSwitcher Where to store the switcher to use.
2949	* VMMSWITCHER_INVALID means no change.
2950	*/
2951	static PGMMODE pgmR3CalcShadowMode(PVM pVM, PGMMODE enmGuestMode, SUPPAGINGMODE enmHostMode, PGMMODE enmShadowMode, VMMSWITCHER *penmSwitcher)
2952	{
2953	VMMSWITCHER enmSwitcher = VMMSWITCHER_INVALID;
2954	switch (enmGuestMode)
2955	{
2956	/*
2957	* When switching to real or protected mode we don't change
2958	* anything since it's likely that we'll switch back pretty soon.
2959	*
2960	* During pgmR3InitPaging we'll end up here with PGMMODE_INVALID
2961	* and is supposed to determine which shadow paging and switcher to
2962	* use during init.
2963	*/
2964	case PGMMODE_REAL:
2965	case PGMMODE_PROTECTED:
2966	if ( enmShadowMode != PGMMODE_INVALID
2967	&& !HWACCMIsEnabled(pVM) /* always switch in hwaccm mode! */)
2968	break; /* (no change) */
2969
2970	switch (enmHostMode)
2971	{
2972	case SUPPAGINGMODE_32_BIT:
2973	case SUPPAGINGMODE_32_BIT_GLOBAL:
2974	enmShadowMode = PGMMODE_32_BIT;
2975	enmSwitcher = VMMSWITCHER_32_TO_32;
2976	break;
2977
2978	case SUPPAGINGMODE_PAE:
2979	case SUPPAGINGMODE_PAE_NX:
2980	case SUPPAGINGMODE_PAE_GLOBAL:
2981	case SUPPAGINGMODE_PAE_GLOBAL_NX:
2982	enmShadowMode = PGMMODE_PAE;
2983	enmSwitcher = VMMSWITCHER_PAE_TO_PAE;
2984	#ifdef DEBUG_bird
2985	if (getenv("VBOX_32BIT"))
2986	{
2987	enmShadowMode = PGMMODE_32_BIT;
2988	enmSwitcher = VMMSWITCHER_PAE_TO_32;
2989	}
2990	#endif
2991	break;
2992
2993	case SUPPAGINGMODE_AMD64:
2994	case SUPPAGINGMODE_AMD64_GLOBAL:
2995	case SUPPAGINGMODE_AMD64_NX:
2996	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
2997	enmShadowMode = PGMMODE_PAE;
2998	enmSwitcher = VMMSWITCHER_AMD64_TO_PAE;
2999	break;
3000
3001	default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
3002	}
3003	break;
3004
3005	case PGMMODE_32_BIT:
3006	switch (enmHostMode)
3007	{
3008	case SUPPAGINGMODE_32_BIT:
3009	case SUPPAGINGMODE_32_BIT_GLOBAL:
3010	enmShadowMode = PGMMODE_32_BIT;
3011	enmSwitcher = VMMSWITCHER_32_TO_32;
3012	break;
3013
3014	case SUPPAGINGMODE_PAE:
3015	case SUPPAGINGMODE_PAE_NX:
3016	case SUPPAGINGMODE_PAE_GLOBAL:
3017	case SUPPAGINGMODE_PAE_GLOBAL_NX:
3018	enmShadowMode = PGMMODE_PAE;
3019	enmSwitcher = VMMSWITCHER_PAE_TO_PAE;
3020	#ifdef DEBUG_bird
3021	if (getenv("VBOX_32BIT"))
3022	{
3023	enmShadowMode = PGMMODE_32_BIT;
3024	enmSwitcher = VMMSWITCHER_PAE_TO_32;
3025	}
3026	#endif
3027	break;
3028
3029	case SUPPAGINGMODE_AMD64:
3030	case SUPPAGINGMODE_AMD64_GLOBAL:
3031	case SUPPAGINGMODE_AMD64_NX:
3032	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
3033	enmShadowMode = PGMMODE_PAE;
3034	enmSwitcher = VMMSWITCHER_AMD64_TO_PAE;
3035	break;
3036
3037	default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
3038	}
3039	break;
3040
3041	case PGMMODE_PAE:
3042	case PGMMODE_PAE_NX: /** @todo This might require more switchers and guest+both modes. */
3043	switch (enmHostMode)
3044	{
3045	case SUPPAGINGMODE_32_BIT:
3046	case SUPPAGINGMODE_32_BIT_GLOBAL:
3047	enmShadowMode = PGMMODE_PAE;
3048	enmSwitcher = VMMSWITCHER_32_TO_PAE;
3049	break;
3050
3051	case SUPPAGINGMODE_PAE:
3052	case SUPPAGINGMODE_PAE_NX:
3053	case SUPPAGINGMODE_PAE_GLOBAL:
3054	case SUPPAGINGMODE_PAE_GLOBAL_NX:
3055	enmShadowMode = PGMMODE_PAE;
3056	enmSwitcher = VMMSWITCHER_PAE_TO_PAE;
3057	break;
3058
3059	case SUPPAGINGMODE_AMD64:
3060	case SUPPAGINGMODE_AMD64_GLOBAL:
3061	case SUPPAGINGMODE_AMD64_NX:
3062	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
3063	enmShadowMode = PGMMODE_PAE;
3064	enmSwitcher = VMMSWITCHER_AMD64_TO_PAE;
3065	break;
3066
3067	default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
3068	}
3069	break;
3070
3071	case PGMMODE_AMD64:
3072	case PGMMODE_AMD64_NX:
3073	switch (enmHostMode)
3074	{
3075	case SUPPAGINGMODE_32_BIT:
3076	case SUPPAGINGMODE_32_BIT_GLOBAL:
3077	enmShadowMode = PGMMODE_PAE;
3078	enmSwitcher = VMMSWITCHER_32_TO_AMD64;
3079	break;
3080
3081	case SUPPAGINGMODE_PAE:
3082	case SUPPAGINGMODE_PAE_NX:
3083	case SUPPAGINGMODE_PAE_GLOBAL:
3084	case SUPPAGINGMODE_PAE_GLOBAL_NX:
3085	enmShadowMode = PGMMODE_PAE;
3086	enmSwitcher = VMMSWITCHER_PAE_TO_AMD64;
3087	break;
3088
3089	case SUPPAGINGMODE_AMD64:
3090	case SUPPAGINGMODE_AMD64_GLOBAL:
3091	case SUPPAGINGMODE_AMD64_NX:
3092	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
3093	enmShadowMode = PGMMODE_AMD64;
3094	enmSwitcher = VMMSWITCHER_AMD64_TO_AMD64;
3095	break;
3096
3097	default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
3098	}
3099	break;
3100
3101
3102	default:
3103	AssertReleaseMsgFailed(("enmGuestMode=%d\n", enmGuestMode));
3104	return PGMMODE_INVALID;
3105	}
3106	/* Override the shadow mode is nested paging is active. */
3107	if (HWACCMIsNestedPagingActive(pVM))
3108	enmShadowMode = HWACCMGetPagingMode(pVM);
3109
3110	*penmSwitcher = enmSwitcher;
3111	return enmShadowMode;
3112	}
3113
3114	/**
3115	* Performs the actual mode change.
3116	* This is called by PGMChangeMode and pgmR3InitPaging().
3117	*
3118	* @returns VBox status code.
3119	* @param pVM VM handle.
3120	* @param enmGuestMode The new guest mode. This is assumed to be different from
3121	* the current mode.
3122	*/
3123	PGMR3DECL(int) PGMR3ChangeMode(PVM pVM, PGMMODE enmGuestMode)
3124	{
3125	LogFlow(("PGMR3ChangeMode: Guest mode: %s -> %s\n", PGMGetModeName(pVM->pgm.s.enmGuestMode), PGMGetModeName(enmGuestMode)));
3126	STAM_REL_COUNTER_INC(&pVM->pgm.s.cGuestModeChanges);
3127
3128	/*
3129	* Calc the shadow mode and switcher.
3130	*/
3131	VMMSWITCHER enmSwitcher;
3132	PGMMODE enmShadowMode = pgmR3CalcShadowMode(pVM, enmGuestMode, pVM->pgm.s.enmHostMode, pVM->pgm.s.enmShadowMode, &enmSwitcher);
3133	if (enmSwitcher != VMMSWITCHER_INVALID)
3134	{
3135	/*
3136	* Select new switcher.
3137	*/
3138	int rc = VMMR3SelectSwitcher(pVM, enmSwitcher);
3139	if (VBOX_FAILURE(rc))
3140	{
3141	AssertReleaseMsgFailed(("VMMR3SelectSwitcher(%d) -> %Vrc\n", enmSwitcher, rc));
3142	return rc;
3143	}
3144	}
3145
3146	/*
3147	* Exit old mode(s).
3148	*/
3149	/* shadow */
3150	if (enmShadowMode != pVM->pgm.s.enmShadowMode)
3151	{
3152	LogFlow(("PGMR3ChangeMode: Shadow mode: %s -> %s\n", PGMGetModeName(pVM->pgm.s.enmShadowMode), PGMGetModeName(enmShadowMode)));
3153	if (PGM_SHW_PFN(Exit, pVM))
3154	{
3155	int rc = PGM_SHW_PFN(Exit, pVM)(pVM);
3156	if (VBOX_FAILURE(rc))
3157	{
3158	AssertMsgFailed(("Exit failed for shadow mode %d: %Vrc\n", pVM->pgm.s.enmShadowMode, rc));
3159	return rc;
3160	}
3161	}
3162
3163	}
3164
3165	/* guest */
3166	if (PGM_GST_PFN(Exit, pVM))
3167	{
3168	int rc = PGM_GST_PFN(Exit, pVM)(pVM);
3169	if (VBOX_FAILURE(rc))
3170	{
3171	AssertMsgFailed(("Exit failed for guest mode %d: %Vrc\n", pVM->pgm.s.enmGuestMode, rc));
3172	return rc;
3173	}
3174	}
3175
3176	/*
3177	* Load new paging mode data.
3178	*/
3179	pgmR3ModeDataSwitch(pVM, enmShadowMode, enmGuestMode);
3180
3181	/*
3182	* Enter new shadow mode (if changed).
3183	*/
3184	if (enmShadowMode != pVM->pgm.s.enmShadowMode)
3185	{
3186	int rc;
3187	pVM->pgm.s.enmShadowMode = enmShadowMode;
3188	switch (enmShadowMode)
3189	{
3190	case PGMMODE_32_BIT:
3191	rc = PGM_SHW_NAME_32BIT(Enter)(pVM);
3192	break;
3193	case PGMMODE_PAE:
3194	case PGMMODE_PAE_NX:
3195	rc = PGM_SHW_NAME_PAE(Enter)(pVM);
3196	break;
3197	case PGMMODE_AMD64:
3198	case PGMMODE_AMD64_NX:
3199	rc = PGM_SHW_NAME_AMD64(Enter)(pVM);
3200	break;
3201	case PGMMODE_NESTED:
3202	rc = PGM_SHW_NAME_NESTED(Enter)(pVM);
3203	break;
3204	#ifdef PGM_WITH_EPT
3205	case PGMMODE_EPT:
3206	rc = PGM_SHW_NAME_EPT(Enter)(pVM);
3207	break;
3208	#endif
3209	case PGMMODE_REAL:
3210	case PGMMODE_PROTECTED:
3211	default:
3212	AssertReleaseMsgFailed(("enmShadowMode=%d\n", enmShadowMode));
3213	return VERR_INTERNAL_ERROR;
3214	}
3215	if (VBOX_FAILURE(rc))
3216	{
3217	AssertReleaseMsgFailed(("Entering enmShadowMode=%d failed: %Vrc\n", enmShadowMode, rc));
3218	pVM->pgm.s.enmShadowMode = PGMMODE_INVALID;
3219	return rc;
3220	}
3221	}
3222
3223	/*
3224	* Enter the new guest and shadow+guest modes.
3225	*/
3226	int rc = -1;
3227	int rc2 = -1;
3228	RTGCPHYS GCPhysCR3 = NIL_RTGCPHYS;
3229	pVM->pgm.s.enmGuestMode = enmGuestMode;
3230	switch (enmGuestMode)
3231	{
3232	case PGMMODE_REAL:
3233	rc = PGM_GST_NAME_REAL(Enter)(pVM, NIL_RTGCPHYS);
3234	switch (pVM->pgm.s.enmShadowMode)
3235	{
3236	case PGMMODE_32_BIT:
3237	rc2 = PGM_BTH_NAME_32BIT_REAL(Enter)(pVM, NIL_RTGCPHYS);
3238	break;
3239	case PGMMODE_PAE:
3240	case PGMMODE_PAE_NX:
3241	rc2 = PGM_BTH_NAME_PAE_REAL(Enter)(pVM, NIL_RTGCPHYS);
3242	break;
3243	case PGMMODE_NESTED:
3244	rc2 = PGM_BTH_NAME_NESTED_REAL(Enter)(pVM, NIL_RTGCPHYS);
3245	break;
3246	#ifdef PGM_WITH_EPT
3247	case PGMMODE_EPT:
3248	rc2 = PGM_BTH_NAME_EPT_REAL(Enter)(pVM, NIL_RTGCPHYS);
3249	break;
3250	#endif
3251	case PGMMODE_AMD64:
3252	case PGMMODE_AMD64_NX:
3253	AssertMsgFailed(("Should use PAE shadow mode!\n"));
3254	default: AssertFailed(); break;
3255	}
3256	break;
3257
3258	case PGMMODE_PROTECTED:
3259	rc = PGM_GST_NAME_PROT(Enter)(pVM, NIL_RTGCPHYS);
3260	switch (pVM->pgm.s.enmShadowMode)
3261	{
3262	case PGMMODE_32_BIT:
3263	rc2 = PGM_BTH_NAME_32BIT_PROT(Enter)(pVM, NIL_RTGCPHYS);
3264	break;
3265	case PGMMODE_PAE:
3266	case PGMMODE_PAE_NX:
3267	rc2 = PGM_BTH_NAME_PAE_PROT(Enter)(pVM, NIL_RTGCPHYS);
3268	break;
3269	case PGMMODE_NESTED:
3270	rc2 = PGM_BTH_NAME_NESTED_PROT(Enter)(pVM, NIL_RTGCPHYS);
3271	break;
3272	#ifdef PGM_WITH_EPT
3273	case PGMMODE_EPT:
3274	rc2 = PGM_BTH_NAME_EPT_PROT(Enter)(pVM, NIL_RTGCPHYS);
3275	break;
3276	#endif
3277	case PGMMODE_AMD64:
3278	case PGMMODE_AMD64_NX:
3279	AssertMsgFailed(("Should use PAE shadow mode!\n"));
3280	default: AssertFailed(); break;
3281	}
3282	break;
3283
3284	case PGMMODE_32_BIT:
3285	GCPhysCR3 = CPUMGetGuestCR3(pVM) & X86_CR3_PAGE_MASK;
3286	rc = PGM_GST_NAME_32BIT(Enter)(pVM, GCPhysCR3);
3287	switch (pVM->pgm.s.enmShadowMode)
3288	{
3289	case PGMMODE_32_BIT:
3290	rc2 = PGM_BTH_NAME_32BIT_32BIT(Enter)(pVM, GCPhysCR3);
3291	break;
3292	case PGMMODE_PAE:
3293	case PGMMODE_PAE_NX:
3294	rc2 = PGM_BTH_NAME_PAE_32BIT(Enter)(pVM, GCPhysCR3);
3295	break;
3296	case PGMMODE_NESTED:
3297	rc2 = PGM_BTH_NAME_NESTED_32BIT(Enter)(pVM, GCPhysCR3);
3298	break;
3299	#ifdef PGM_WITH_EPT
3300	case PGMMODE_EPT:
3301	rc2 = PGM_BTH_NAME_EPT_32BIT(Enter)(pVM, GCPhysCR3);
3302	break;
3303	#endif
3304	case PGMMODE_AMD64:
3305	case PGMMODE_AMD64_NX:
3306	AssertMsgFailed(("Should use PAE shadow mode!\n"));
3307	default: AssertFailed(); break;
3308	}
3309	break;
3310
3311	case PGMMODE_PAE_NX: /* VT-x/AMD-V only */
3312	Assert(HWACCMIsEnabled(pVM));
3313	/* no break */
3314
3315	case PGMMODE_PAE:
3316	{
3317	uint32_t u32Dummy, u32Features;
3318
3319	CPUMGetGuestCpuId(pVM, 1, &u32Dummy, &u32Dummy, &u32Dummy, &u32Features);
3320	if (!(u32Features & X86_CPUID_FEATURE_EDX_PAE))
3321	{
3322	/* Pause first, then inform Main. */
3323	rc = VMR3SuspendNoSave(pVM);
3324	AssertRC(rc);
3325
3326	VMSetRuntimeError(pVM, true, "PAEmode",
3327	N_("The guest is trying to switch to the PAE mode which is currently disabled by default in VirtualBox. Experimental PAE support can be enabled using the -pae option with VBoxManage."));
3328	/* we must return TRUE here otherwise the recompiler will assert */
3329	return VINF_SUCCESS;
3330	}
3331	GCPhysCR3 = CPUMGetGuestCR3(pVM) & X86_CR3_PAE_PAGE_MASK;
3332	rc = PGM_GST_NAME_PAE(Enter)(pVM, GCPhysCR3);
3333	switch (pVM->pgm.s.enmShadowMode)
3334	{
3335	case PGMMODE_PAE:
3336	case PGMMODE_PAE_NX:
3337	rc2 = PGM_BTH_NAME_PAE_PAE(Enter)(pVM, GCPhysCR3);
3338	break;
3339	case PGMMODE_NESTED:
3340	rc2 = PGM_BTH_NAME_NESTED_PAE(Enter)(pVM, GCPhysCR3);
3341	break;
3342	#ifdef PGM_WITH_EPT
3343	case PGMMODE_EPT:
3344	rc2 = PGM_BTH_NAME_EPT_PAE(Enter)(pVM, GCPhysCR3);
3345	break;
3346	#endif
3347	case PGMMODE_32_BIT:
3348	case PGMMODE_AMD64:
3349	case PGMMODE_AMD64_NX:
3350	AssertMsgFailed(("Should use PAE shadow mode!\n"));
3351	default: AssertFailed(); break;
3352	}
3353	break;
3354	}
3355
3356	case PGMMODE_AMD64_NX:
3357	case PGMMODE_AMD64:
3358	GCPhysCR3 = CPUMGetGuestCR3(pVM) & 0xfffffffffffff000ULL; /** @todo define this mask! */
3359	rc = PGM_GST_NAME_AMD64(Enter)(pVM, GCPhysCR3);
3360	switch (pVM->pgm.s.enmShadowMode)
3361	{
3362	case PGMMODE_AMD64:
3363	case PGMMODE_AMD64_NX:
3364	rc2 = PGM_BTH_NAME_AMD64_AMD64(Enter)(pVM, GCPhysCR3);
3365	break;
3366	case PGMMODE_NESTED:
3367	rc2 = PGM_BTH_NAME_NESTED_AMD64(Enter)(pVM, GCPhysCR3);
3368	break;
3369	#ifdef PGM_WITH_EPT
3370	case PGMMODE_EPT:
3371	rc2 = PGM_BTH_NAME_EPT_AMD64(Enter)(pVM, GCPhysCR3);
3372	break;
3373	#endif
3374	case PGMMODE_32_BIT:
3375	case PGMMODE_PAE:
3376	case PGMMODE_PAE_NX:
3377	AssertMsgFailed(("Should use AMD64 shadow mode!\n"));
3378	default: AssertFailed(); break;
3379	}
3380	break;
3381
3382	default:
3383	AssertReleaseMsgFailed(("enmGuestMode=%d\n", enmGuestMode));
3384	rc = VERR_NOT_IMPLEMENTED;
3385	break;
3386	}
3387
3388	/* status codes. */
3389	AssertRC(rc);
3390	AssertRC(rc2);
3391	if (VBOX_SUCCESS(rc))
3392	{
3393	rc = rc2;
3394	if (VBOX_SUCCESS(rc)) /* no informational status codes. */
3395	rc = VINF_SUCCESS;
3396	}
3397
3398	/*
3399	* Notify SELM so it can update the TSSes with correct CR3s.
3400	*/
3401	SELMR3PagingModeChanged(pVM);
3402
3403	/* Notify HWACCM as well. */
3404	HWACCMR3PagingModeChanged(pVM, pVM->pgm.s.enmShadowMode);
3405	return rc;
3406	}
3407
3408
3409	/**
3410	* Dumps a PAE shadow page table.
3411	*
3412	* @returns VBox status code (VINF_SUCCESS).
3413	* @param pVM The VM handle.
3414	* @param pPT Pointer to the page table.
3415	* @param u64Address The virtual address of the page table starts.
3416	* @param fLongMode Set if this a long mode table; clear if it's a legacy mode table.
3417	* @param cMaxDepth The maxium depth.
3418	* @param pHlp Pointer to the output functions.
3419	*/
3420	static int pgmR3DumpHierarchyHCPaePT(PVM pVM, PX86PTPAE pPT, uint64_t u64Address, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
3421	{
3422	for (unsigned i = 0; i < ELEMENTS(pPT->a); i++)
3423	{
3424	X86PTEPAE Pte = pPT->a[i];
3425	if (Pte.n.u1Present)
3426	{
3427	pHlp->pfnPrintf(pHlp,
3428	fLongMode /P R S A D G WT CD AT NX 4M a p ? /
3429	? "%016llx 3 \| P %c %c %c %c %c %s %s %s %s 4K %c%c%c %016llx\n"
3430	: "%08llx 2 \| P %c %c %c %c %c %s %s %s %s 4K %c%c%c %016llx\n",
3431	u64Address + ((uint64_t)i << X86_PT_PAE_SHIFT),
3432	Pte.n.u1Write ? 'W' : 'R',
3433	Pte.n.u1User ? 'U' : 'S',
3434	Pte.n.u1Accessed ? 'A' : '-',
3435	Pte.n.u1Dirty ? 'D' : '-',
3436	Pte.n.u1Global ? 'G' : '-',
3437	Pte.n.u1WriteThru ? "WT" : "--",
3438	Pte.n.u1CacheDisable? "CD" : "--",
3439	Pte.n.u1PAT ? "AT" : "--",
3440	Pte.n.u1NoExecute ? "NX" : "--",
3441	Pte.u & PGM_PTFLAGS_TRACK_DIRTY ? 'd' : '-',
3442	Pte.u & RT_BIT(10) ? '1' : '0',
3443	Pte.u & PGM_PTFLAGS_CSAM_VALIDATED? 'v' : '-',
3444	Pte.u & X86_PTE_PAE_PG_MASK);
3445	}
3446	}
3447	return VINF_SUCCESS;
3448	}
3449
3450
3451	/**
3452	* Dumps a PAE shadow page directory table.
3453	*
3454	* @returns VBox status code (VINF_SUCCESS).
3455	* @param pVM The VM handle.
3456	* @param HCPhys The physical address of the page directory table.
3457	* @param u64Address The virtual address of the page table starts.
3458	* @param cr4 The CR4, PSE is currently used.
3459	* @param fLongMode Set if this a long mode table; clear if it's a legacy mode table.
3460	* @param cMaxDepth The maxium depth.
3461	* @param pHlp Pointer to the output functions.
3462	*/
3463	static int pgmR3DumpHierarchyHCPaePD(PVM pVM, RTHCPHYS HCPhys, uint64_t u64Address, uint32_t cr4, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
3464	{
3465	PX86PDPAE pPD = (PX86PDPAE)MMPagePhys2Page(pVM, HCPhys);
3466	if (!pPD)
3467	{
3468	pHlp->pfnPrintf(pHlp, "%0*llx error! Page directory at HCPhys=%#VHp was not found in the page pool!\n",
3469	fLongMode ? 16 : 8, u64Address, HCPhys);
3470	return VERR_INVALID_PARAMETER;
3471	}
3472	const bool fBigPagesSupported = fLongMode \|\| !!(cr4 & X86_CR4_PSE);
3473
3474	int rc = VINF_SUCCESS;
3475	for (unsigned i = 0; i < ELEMENTS(pPD->a); i++)
3476	{
3477	X86PDEPAE Pde = pPD->a[i];
3478	if (Pde.n.u1Present)
3479	{
3480	if (fBigPagesSupported && Pde.b.u1Size)
3481	pHlp->pfnPrintf(pHlp,
3482	fLongMode /P R S A D G WT CD AT NX 4M a p ? /
3483	? "%016llx 2 \| P %c %c %c %c %c %s %s %s %s 4M %c%c%c %016llx\n"
3484	: "%08llx 1 \| P %c %c %c %c %c %s %s %s %s 4M %c%c%c %016llx\n",
3485	u64Address + ((uint64_t)i << X86_PD_PAE_SHIFT),
3486	Pde.b.u1Write ? 'W' : 'R',
3487	Pde.b.u1User ? 'U' : 'S',
3488	Pde.b.u1Accessed ? 'A' : '-',
3489	Pde.b.u1Dirty ? 'D' : '-',
3490	Pde.b.u1Global ? 'G' : '-',
3491	Pde.b.u1WriteThru ? "WT" : "--",
3492	Pde.b.u1CacheDisable? "CD" : "--",
3493	Pde.b.u1PAT ? "AT" : "--",
3494	Pde.b.u1NoExecute ? "NX" : "--",
3495	Pde.u & RT_BIT_64(9) ? '1' : '0',
3496	Pde.u & PGM_PDFLAGS_MAPPING ? 'm' : '-',
3497	Pde.u & PGM_PDFLAGS_TRACK_DIRTY ? 'd' : '-',
3498	Pde.u & X86_PDE_PAE_PG_MASK);
3499	else
3500	{
3501	pHlp->pfnPrintf(pHlp,
3502	fLongMode /P R S A D G WT CD AT NX 4M a p ? /
3503	? "%016llx 2 \| P %c %c %c %c %c %s %s .. %s 4K %c%c%c %016llx\n"
3504	: "%08llx 1 \| P %c %c %c %c %c %s %s .. %s 4K %c%c%c %016llx\n",
3505	u64Address + ((uint64_t)i << X86_PD_PAE_SHIFT),
3506	Pde.n.u1Write ? 'W' : 'R',
3507	Pde.n.u1User ? 'U' : 'S',
3508	Pde.n.u1Accessed ? 'A' : '-',
3509	Pde.n.u1Reserved0 ? '?' : '.', /* ignored */
3510	Pde.n.u1Reserved1 ? '?' : '.', /* ignored */
3511	Pde.n.u1WriteThru ? "WT" : "--",
3512	Pde.n.u1CacheDisable? "CD" : "--",
3513	Pde.n.u1NoExecute ? "NX" : "--",
3514	Pde.u & RT_BIT_64(9) ? '1' : '0',
3515	Pde.u & PGM_PDFLAGS_MAPPING ? 'm' : '-',
3516	Pde.u & PGM_PDFLAGS_TRACK_DIRTY ? 'd' : '-',
3517	Pde.u & X86_PDE_PAE_PG_MASK);
3518	if (cMaxDepth >= 1)
3519	{
3520	/** @todo what about using the page pool for mapping PTs? */
3521	uint64_t u64AddressPT = u64Address + ((uint64_t)i << X86_PD_PAE_SHIFT);
3522	RTHCPHYS HCPhysPT = Pde.u & X86_PDE_PAE_PG_MASK;
3523	PX86PTPAE pPT = NULL;
3524	if (!(Pde.u & PGM_PDFLAGS_MAPPING))
3525	pPT = (PX86PTPAE)MMPagePhys2Page(pVM, HCPhysPT);
3526	else
3527	{
3528	for (PPGMMAPPING pMap = pVM->pgm.s.pMappingsR3; pMap; pMap = pMap->pNextR3)
3529	{
3530	uint64_t off = u64AddressPT - pMap->GCPtr;
3531	if (off < pMap->cb)
3532	{
3533	const int iPDE = (uint32_t)(off >> X86_PD_SHIFT);
3534	const int iSub = (int)((off >> X86_PD_PAE_SHIFT) & 1); /* MSC is a pain sometimes */
3535	if ((iSub ? pMap->aPTs[iPDE].HCPhysPaePT1 : pMap->aPTs[iPDE].HCPhysPaePT0) != HCPhysPT)
3536	pHlp->pfnPrintf(pHlp, "%0*llx error! Mapping error! PT %d has HCPhysPT=%VHp not %VHp is in the PD.\n",
3537	fLongMode ? 16 : 8, u64AddressPT, iPDE,
3538	iSub ? pMap->aPTs[iPDE].HCPhysPaePT1 : pMap->aPTs[iPDE].HCPhysPaePT0, HCPhysPT);
3539	pPT = &pMap->aPTs[iPDE].paPaePTsR3[iSub];
3540	}
3541	}
3542	}
3543	int rc2 = VERR_INVALID_PARAMETER;
3544	if (pPT)
3545	rc2 = pgmR3DumpHierarchyHCPaePT(pVM, pPT, u64AddressPT, fLongMode, cMaxDepth - 1, pHlp);
3546	else
3547	pHlp->pfnPrintf(pHlp, "%0*llx error! Page table at HCPhys=%#VHp was not found in the page pool!\n",
3548	fLongMode ? 16 : 8, u64AddressPT, HCPhysPT);
3549	if (rc2 < rc && VBOX_SUCCESS(rc))
3550	rc = rc2;
3551	}
3552	}
3553	}
3554	}
3555	return rc;
3556	}
3557
3558
3559	/**
3560	* Dumps a PAE shadow page directory pointer table.
3561	*
3562	* @returns VBox status code (VINF_SUCCESS).
3563	* @param pVM The VM handle.
3564	* @param HCPhys The physical address of the page directory pointer table.
3565	* @param u64Address The virtual address of the page table starts.
3566	* @param cr4 The CR4, PSE is currently used.
3567	* @param fLongMode Set if this a long mode table; clear if it's a legacy mode table.
3568	* @param cMaxDepth The maxium depth.
3569	* @param pHlp Pointer to the output functions.
3570	*/
3571	static int pgmR3DumpHierarchyHCPaePDPT(PVM pVM, RTHCPHYS HCPhys, uint64_t u64Address, uint32_t cr4, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
3572	{
3573	PX86PDPT pPDPT = (PX86PDPT)MMPagePhys2Page(pVM, HCPhys);
3574	if (!pPDPT)
3575	{
3576	pHlp->pfnPrintf(pHlp, "%0*llx error! Page directory pointer table at HCPhys=%#VHp was not found in the page pool!\n",
3577	fLongMode ? 16 : 8, u64Address, HCPhys);
3578	return VERR_INVALID_PARAMETER;
3579	}
3580
3581	int rc = VINF_SUCCESS;
3582	const unsigned c = fLongMode ? ELEMENTS(pPDPT->a) : X86_PG_PAE_PDPE_ENTRIES;
3583	for (unsigned i = 0; i < c; i++)
3584	{
3585	X86PDPE Pdpe = pPDPT->a[i];
3586	if (Pdpe.n.u1Present)
3587	{
3588	if (fLongMode)
3589	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a p ? /
3590	"%016llx 1 \| P %c %c %c %c %c %s %s %s %s .. %c%c%c %016llx\n",
3591	u64Address + ((uint64_t)i << X86_PDPT_SHIFT),
3592	Pdpe.lm.u1Write ? 'W' : 'R',
3593	Pdpe.lm.u1User ? 'U' : 'S',
3594	Pdpe.lm.u1Accessed ? 'A' : '-',
3595	Pdpe.lm.u3Reserved & 1? '?' : '.', /* ignored */
3596	Pdpe.lm.u3Reserved & 4? '!' : '.', /* mbz */
3597	Pdpe.lm.u1WriteThru ? "WT" : "--",
3598	Pdpe.lm.u1CacheDisable? "CD" : "--",
3599	Pdpe.lm.u3Reserved & 2? "!" : "..",/* mbz */
3600	Pdpe.lm.u1NoExecute ? "NX" : "--",
3601	Pdpe.u & RT_BIT(9) ? '1' : '0',
3602	Pdpe.u & PGM_PLXFLAGS_PERMANENT ? 'p' : '-',
3603	Pdpe.u & RT_BIT(11) ? '1' : '0',
3604	Pdpe.u & X86_PDPE_PG_MASK);
3605	else
3606	pHlp->pfnPrintf(pHlp, /P G WT CD AT NX 4M a p ? /
3607	"%08x 0 \| P %c %s %s %s %s .. %c%c%c %016llx\n",
3608	i << X86_PDPT_SHIFT,
3609	Pdpe.n.u4Reserved & 1? '!' : '.', /* mbz */
3610	Pdpe.n.u4Reserved & 4? '!' : '.', /* mbz */
3611	Pdpe.n.u1WriteThru ? "WT" : "--",
3612	Pdpe.n.u1CacheDisable? "CD" : "--",
3613	Pdpe.n.u4Reserved & 2? "!" : "..",/* mbz */
3614	Pdpe.u & RT_BIT(9) ? '1' : '0',
3615	Pdpe.u & PGM_PLXFLAGS_PERMANENT ? 'p' : '-',
3616	Pdpe.u & RT_BIT(11) ? '1' : '0',
3617	Pdpe.u & X86_PDPE_PG_MASK);
3618	if (cMaxDepth >= 1)
3619	{
3620	int rc2 = pgmR3DumpHierarchyHCPaePD(pVM, Pdpe.u & X86_PDPE_PG_MASK, u64Address + ((uint64_t)i << X86_PDPT_SHIFT),
3621	cr4, fLongMode, cMaxDepth - 1, pHlp);
3622	if (rc2 < rc && VBOX_SUCCESS(rc))
3623	rc = rc2;
3624	}
3625	}
3626	}
3627	return rc;
3628	}
3629
3630
3631	/**
3632	* Dumps a 32-bit shadow page table.
3633	*
3634	* @returns VBox status code (VINF_SUCCESS).
3635	* @param pVM The VM handle.
3636	* @param HCPhys The physical address of the table.
3637	* @param cr4 The CR4, PSE is currently used.
3638	* @param cMaxDepth The maxium depth.
3639	* @param pHlp Pointer to the output functions.
3640	*/
3641	static int pgmR3DumpHierarchyHcPaePML4(PVM pVM, RTHCPHYS HCPhys, uint32_t cr4, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
3642	{
3643	PX86PML4 pPML4 = (PX86PML4)MMPagePhys2Page(pVM, HCPhys);
3644	if (!pPML4)
3645	{
3646	pHlp->pfnPrintf(pHlp, "Page map level 4 at HCPhys=%#VHp was not found in the page pool!\n", HCPhys);
3647	return VERR_INVALID_PARAMETER;
3648	}
3649
3650	int rc = VINF_SUCCESS;
3651	for (unsigned i = 0; i < ELEMENTS(pPML4->a); i++)
3652	{
3653	X86PML4E Pml4e = pPML4->a[i];
3654	if (Pml4e.n.u1Present)
3655	{
3656	uint64_t u64Address = ((uint64_t)i << X86_PML4_SHIFT) \| (((uint64_t)i >> (X86_PML4_SHIFT - X86_PDPT_SHIFT - 1)) * 0xffff000000000000ULL);
3657	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a p ? /
3658	"%016llx 0 \| P %c %c %c %c %c %s %s %s %s .. %c%c%c %016llx\n",
3659	u64Address,
3660	Pml4e.n.u1Write ? 'W' : 'R',
3661	Pml4e.n.u1User ? 'U' : 'S',
3662	Pml4e.n.u1Accessed ? 'A' : '-',
3663	Pml4e.n.u3Reserved & 1? '?' : '.', /* ignored */
3664	Pml4e.n.u3Reserved & 4? '!' : '.', /* mbz */
3665	Pml4e.n.u1WriteThru ? "WT" : "--",
3666	Pml4e.n.u1CacheDisable? "CD" : "--",
3667	Pml4e.n.u3Reserved & 2? "!" : "..",/* mbz */
3668	Pml4e.n.u1NoExecute ? "NX" : "--",
3669	Pml4e.u & RT_BIT(9) ? '1' : '0',
3670	Pml4e.u & PGM_PLXFLAGS_PERMANENT ? 'p' : '-',
3671	Pml4e.u & RT_BIT(11) ? '1' : '0',
3672	Pml4e.u & X86_PML4E_PG_MASK);
3673
3674	if (cMaxDepth >= 1)
3675	{
3676	int rc2 = pgmR3DumpHierarchyHCPaePDPT(pVM, Pml4e.u & X86_PML4E_PG_MASK, u64Address, cr4, true, cMaxDepth - 1, pHlp);
3677	if (rc2 < rc && VBOX_SUCCESS(rc))
3678	rc = rc2;
3679	}
3680	}
3681	}
3682	return rc;
3683	}
3684
3685
3686	/**
3687	* Dumps a 32-bit shadow page table.
3688	*
3689	* @returns VBox status code (VINF_SUCCESS).
3690	* @param pVM The VM handle.
3691	* @param pPT Pointer to the page table.
3692	* @param u32Address The virtual address this table starts at.
3693	* @param pHlp Pointer to the output functions.
3694	*/
3695	int pgmR3DumpHierarchyHC32BitPT(PVM pVM, PX86PT pPT, uint32_t u32Address, PCDBGFINFOHLP pHlp)
3696	{
3697	for (unsigned i = 0; i < ELEMENTS(pPT->a); i++)
3698	{
3699	X86PTE Pte = pPT->a[i];
3700	if (Pte.n.u1Present)
3701	{
3702	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a m d /
3703	"%08x 1 \| P %c %c %c %c %c %s %s %s .. 4K %c%c%c %08x\n",
3704	u32Address + (i << X86_PT_SHIFT),
3705	Pte.n.u1Write ? 'W' : 'R',
3706	Pte.n.u1User ? 'U' : 'S',
3707	Pte.n.u1Accessed ? 'A' : '-',
3708	Pte.n.u1Dirty ? 'D' : '-',
3709	Pte.n.u1Global ? 'G' : '-',
3710	Pte.n.u1WriteThru ? "WT" : "--",
3711	Pte.n.u1CacheDisable? "CD" : "--",
3712	Pte.n.u1PAT ? "AT" : "--",
3713	Pte.u & PGM_PTFLAGS_TRACK_DIRTY ? 'd' : '-',
3714	Pte.u & RT_BIT(10) ? '1' : '0',
3715	Pte.u & PGM_PTFLAGS_CSAM_VALIDATED ? 'v' : '-',
3716	Pte.u & X86_PDE_PG_MASK);
3717	}
3718	}
3719	return VINF_SUCCESS;
3720	}
3721
3722
3723	/**
3724	* Dumps a 32-bit shadow page directory and page tables.
3725	*
3726	* @returns VBox status code (VINF_SUCCESS).
3727	* @param pVM The VM handle.
3728	* @param cr3 The root of the hierarchy.
3729	* @param cr4 The CR4, PSE is currently used.
3730	* @param cMaxDepth How deep into the hierarchy the dumper should go.
3731	* @param pHlp Pointer to the output functions.
3732	*/
3733	int pgmR3DumpHierarchyHC32BitPD(PVM pVM, uint32_t cr3, uint32_t cr4, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
3734	{
3735	PX86PD pPD = (PX86PD)MMPagePhys2Page(pVM, cr3 & X86_CR3_PAGE_MASK);
3736	if (!pPD)
3737	{
3738	pHlp->pfnPrintf(pHlp, "Page directory at %#x was not found in the page pool!\n", cr3 & X86_CR3_PAGE_MASK);
3739	return VERR_INVALID_PARAMETER;
3740	}
3741
3742	int rc = VINF_SUCCESS;
3743	for (unsigned i = 0; i < ELEMENTS(pPD->a); i++)
3744	{
3745	X86PDE Pde = pPD->a[i];
3746	if (Pde.n.u1Present)
3747	{
3748	const uint32_t u32Address = i << X86_PD_SHIFT;
3749	if ((cr4 & X86_CR4_PSE) && Pde.b.u1Size)
3750	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a m d /
3751	"%08x 0 \| P %c %c %c %c %c %s %s %s .. 4M %c%c%c %08x\n",
3752	u32Address,
3753	Pde.b.u1Write ? 'W' : 'R',
3754	Pde.b.u1User ? 'U' : 'S',
3755	Pde.b.u1Accessed ? 'A' : '-',
3756	Pde.b.u1Dirty ? 'D' : '-',
3757	Pde.b.u1Global ? 'G' : '-',
3758	Pde.b.u1WriteThru ? "WT" : "--",
3759	Pde.b.u1CacheDisable? "CD" : "--",
3760	Pde.b.u1PAT ? "AT" : "--",
3761	Pde.u & RT_BIT_64(9) ? '1' : '0',
3762	Pde.u & PGM_PDFLAGS_MAPPING ? 'm' : '-',
3763	Pde.u & PGM_PDFLAGS_TRACK_DIRTY ? 'd' : '-',
3764	Pde.u & X86_PDE4M_PG_MASK);
3765	else
3766	{
3767	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a m d /
3768	"%08x 0 \| P %c %c %c %c %c %s %s .. .. 4K %c%c%c %08x\n",
3769	u32Address,
3770	Pde.n.u1Write ? 'W' : 'R',
3771	Pde.n.u1User ? 'U' : 'S',
3772	Pde.n.u1Accessed ? 'A' : '-',
3773	Pde.n.u1Reserved0 ? '?' : '.', /* ignored */
3774	Pde.n.u1Reserved1 ? '?' : '.', /* ignored */
3775	Pde.n.u1WriteThru ? "WT" : "--",
3776	Pde.n.u1CacheDisable? "CD" : "--",
3777	Pde.u & RT_BIT_64(9) ? '1' : '0',
3778	Pde.u & PGM_PDFLAGS_MAPPING ? 'm' : '-',
3779	Pde.u & PGM_PDFLAGS_TRACK_DIRTY ? 'd' : '-',
3780	Pde.u & X86_PDE_PG_MASK);
3781	if (cMaxDepth >= 1)
3782	{
3783	/** @todo what about using the page pool for mapping PTs? */
3784	RTHCPHYS HCPhys = Pde.u & X86_PDE_PG_MASK;
3785	PX86PT pPT = NULL;
3786	if (!(Pde.u & PGM_PDFLAGS_MAPPING))
3787	pPT = (PX86PT)MMPagePhys2Page(pVM, HCPhys);
3788	else
3789	{
3790	for (PPGMMAPPING pMap = pVM->pgm.s.pMappingsR3; pMap; pMap = pMap->pNextR3)
3791	if (u32Address - pMap->GCPtr < pMap->cb)
3792	{
3793	int iPDE = (u32Address - pMap->GCPtr) >> X86_PD_SHIFT;
3794	if (pMap->aPTs[iPDE].HCPhysPT != HCPhys)
3795	pHlp->pfnPrintf(pHlp, "%08x error! Mapping error! PT %d has HCPhysPT=%VHp not %VHp is in the PD.\n",
3796	u32Address, iPDE, pMap->aPTs[iPDE].HCPhysPT, HCPhys);
3797	pPT = pMap->aPTs[iPDE].pPTR3;
3798	}
3799	}
3800	int rc2 = VERR_INVALID_PARAMETER;
3801	if (pPT)
3802	rc2 = pgmR3DumpHierarchyHC32BitPT(pVM, pPT, u32Address, pHlp);
3803	else
3804	pHlp->pfnPrintf(pHlp, "%08x error! Page table at %#x was not found in the page pool!\n", u32Address, HCPhys);
3805	if (rc2 < rc && VBOX_SUCCESS(rc))
3806	rc = rc2;
3807	}
3808	}
3809	}
3810	}
3811
3812	return rc;
3813	}
3814
3815
3816	/**
3817	* Dumps a 32-bit shadow page table.
3818	*
3819	* @returns VBox status code (VINF_SUCCESS).
3820	* @param pVM The VM handle.
3821	* @param pPT Pointer to the page table.
3822	* @param u32Address The virtual address this table starts at.
3823	* @param PhysSearch Address to search for.
3824	*/
3825	int pgmR3DumpHierarchyGC32BitPT(PVM pVM, PX86PT pPT, uint32_t u32Address, RTGCPHYS PhysSearch)
3826	{
3827	for (unsigned i = 0; i < ELEMENTS(pPT->a); i++)
3828	{
3829	X86PTE Pte = pPT->a[i];
3830	if (Pte.n.u1Present)
3831	{
3832	Log(( /P R S A D G WT CD AT NX 4M a m d /
3833	"%08x 1 \| P %c %c %c %c %c %s %s %s .. 4K %c%c%c %08x\n",
3834	u32Address + (i << X86_PT_SHIFT),
3835	Pte.n.u1Write ? 'W' : 'R',
3836	Pte.n.u1User ? 'U' : 'S',
3837	Pte.n.u1Accessed ? 'A' : '-',
3838	Pte.n.u1Dirty ? 'D' : '-',
3839	Pte.n.u1Global ? 'G' : '-',
3840	Pte.n.u1WriteThru ? "WT" : "--",
3841	Pte.n.u1CacheDisable? "CD" : "--",
3842	Pte.n.u1PAT ? "AT" : "--",
3843	Pte.u & PGM_PTFLAGS_TRACK_DIRTY ? 'd' : '-',
3844	Pte.u & RT_BIT(10) ? '1' : '0',
3845	Pte.u & PGM_PTFLAGS_CSAM_VALIDATED ? 'v' : '-',
3846	Pte.u & X86_PDE_PG_MASK));
3847
3848	if ((Pte.u & X86_PDE_PG_MASK) == PhysSearch)
3849	{
3850	uint64_t fPageShw = 0;
3851	RTHCPHYS pPhysHC = 0;
3852
3853	PGMShwGetPage(pVM, (RTGCPTR)(u32Address + (i << X86_PT_SHIFT)), &fPageShw, &pPhysHC);
3854	Log(("Found %VGp at %VGv -> flags=%llx\n", PhysSearch, (RTGCPTR)(u32Address + (i << X86_PT_SHIFT)), fPageShw));
3855	}
3856	}
3857	}
3858	return VINF_SUCCESS;
3859	}
3860
3861
3862	/**
3863	* Dumps a 32-bit guest page directory and page tables.
3864	*
3865	* @returns VBox status code (VINF_SUCCESS).
3866	* @param pVM The VM handle.
3867	* @param cr3 The root of the hierarchy.
3868	* @param cr4 The CR4, PSE is currently used.
3869	* @param PhysSearch Address to search for.
3870	*/
3871	PGMR3DECL(int) PGMR3DumpHierarchyGC(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCPHYS PhysSearch)
3872	{
3873	bool fLongMode = false;
3874	const unsigned cch = fLongMode ? 16 : 8; NOREF(cch);
3875	PX86PD pPD = 0;
3876
3877	int rc = PGM_GCPHYS_2_PTR(pVM, cr3 & X86_CR3_PAGE_MASK, &pPD);
3878	if (VBOX_FAILURE(rc) \|\| !pPD)
3879	{
3880	Log(("Page directory at %#x was not found in the page pool!\n", cr3 & X86_CR3_PAGE_MASK));
3881	return VERR_INVALID_PARAMETER;
3882	}
3883
3884	Log(("cr3=%08x cr4=%08x%s\n"
3885	"%-*s P - Present\n"
3886	"%-*s \| R/W - Read (0) / Write (1)\n"
3887	"%-*s \| \| U/S - User (1) / Supervisor (0)\n"
3888	"%-*s \| \| \| A - Accessed\n"
3889	"%-*s \| \| \| \| D - Dirty\n"
3890	"%-*s \| \| \| \| \| G - Global\n"
3891	"%-*s \| \| \| \| \| \| WT - Write thru\n"
3892	"%-*s \| \| \| \| \| \| \| CD - Cache disable\n"
3893	"%-*s \| \| \| \| \| \| \| \| AT - Attribute table (PAT)\n"
3894	"%-*s \| \| \| \| \| \| \| \| \| NX - No execute (K8)\n"
3895	"%-*s \| \| \| \| \| \| \| \| \| \| 4K/4M/2M - Page size.\n"
3896	"%-*s \| \| \| \| \| \| \| \| \| \| \| AVL - a=allocated; m=mapping; d=track dirty;\n"
3897	"%-*s \| \| \| \| \| \| \| \| \| \| \| \| p=permanent; v=validated;\n"
3898	"%-*s Level \| \| \| \| \| \| \| \| \| \| \| \| Page\n"
3899	/* xxxx n **** P R S A D G WT CD AT NX 4M AVL xxxxxxxxxxxxx
3900	- W U - - - -- -- -- -- -- 010 */
3901	, cr3, cr4, fLongMode ? " Long Mode" : "",
3902	cch, "", cch, "", cch, "", cch, "", cch, "", cch, "", cch, "",
3903	cch, "", cch, "", cch, "", cch, "", cch, "", cch, "", cch, "Address"));
3904
3905	for (unsigned i = 0; i < ELEMENTS(pPD->a); i++)
3906	{
3907	X86PDE Pde = pPD->a[i];
3908	if (Pde.n.u1Present)
3909	{
3910	const uint32_t u32Address = i << X86_PD_SHIFT;
3911
3912	if ((cr4 & X86_CR4_PSE) && Pde.b.u1Size)
3913	Log(( /P R S A D G WT CD AT NX 4M a m d /
3914	"%08x 0 \| P %c %c %c %c %c %s %s %s .. 4M %c%c%c %08x\n",
3915	u32Address,
3916	Pde.b.u1Write ? 'W' : 'R',
3917	Pde.b.u1User ? 'U' : 'S',
3918	Pde.b.u1Accessed ? 'A' : '-',
3919	Pde.b.u1Dirty ? 'D' : '-',
3920	Pde.b.u1Global ? 'G' : '-',
3921	Pde.b.u1WriteThru ? "WT" : "--",
3922	Pde.b.u1CacheDisable? "CD" : "--",
3923	Pde.b.u1PAT ? "AT" : "--",
3924	Pde.u & RT_BIT(9) ? '1' : '0',
3925	Pde.u & RT_BIT(10) ? '1' : '0',
3926	Pde.u & RT_BIT(11) ? '1' : '0',
3927	Pde.u & X86_PDE4M_PG_MASK));
3928	/** @todo PhysSearch */
3929	else
3930	{
3931	Log(( /P R S A D G WT CD AT NX 4M a m d /
3932	"%08x 0 \| P %c %c %c %c %c %s %s .. .. 4K %c%c%c %08x\n",
3933	u32Address,
3934	Pde.n.u1Write ? 'W' : 'R',
3935	Pde.n.u1User ? 'U' : 'S',
3936	Pde.n.u1Accessed ? 'A' : '-',
3937	Pde.n.u1Reserved0 ? '?' : '.', /* ignored */
3938	Pde.n.u1Reserved1 ? '?' : '.', /* ignored */
3939	Pde.n.u1WriteThru ? "WT" : "--",
3940	Pde.n.u1CacheDisable? "CD" : "--",
3941	Pde.u & RT_BIT(9) ? '1' : '0',
3942	Pde.u & RT_BIT(10) ? '1' : '0',
3943	Pde.u & RT_BIT(11) ? '1' : '0',
3944	Pde.u & X86_PDE_PG_MASK));
3945	////if (cMaxDepth >= 1)
3946	{
3947	/** @todo what about using the page pool for mapping PTs? */
3948	RTGCPHYS GCPhys = Pde.u & X86_PDE_PG_MASK;
3949	PX86PT pPT = NULL;
3950
3951	rc = PGM_GCPHYS_2_PTR(pVM, GCPhys, &pPT);
3952
3953	int rc2 = VERR_INVALID_PARAMETER;
3954	if (pPT)
3955	rc2 = pgmR3DumpHierarchyGC32BitPT(pVM, pPT, u32Address, PhysSearch);
3956	else
3957	Log(("%08x error! Page table at %#x was not found in the page pool!\n", u32Address, GCPhys));
3958	if (rc2 < rc && VBOX_SUCCESS(rc))
3959	rc = rc2;
3960	}
3961	}
3962	}
3963	}
3964
3965	return rc;
3966	}
3967
3968
3969	/**
3970	* Dumps a page table hierarchy use only physical addresses and cr4/lm flags.
3971	*
3972	* @returns VBox status code (VINF_SUCCESS).
3973	* @param pVM The VM handle.
3974	* @param cr3 The root of the hierarchy.
3975	* @param cr4 The cr4, only PAE and PSE is currently used.
3976	* @param fLongMode Set if long mode, false if not long mode.
3977	* @param cMaxDepth Number of levels to dump.
3978	* @param pHlp Pointer to the output functions.
3979	*/
3980	PGMR3DECL(int) PGMR3DumpHierarchyHC(PVM pVM, uint64_t cr3, uint64_t cr4, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
3981	{
3982	if (!pHlp)
3983	pHlp = DBGFR3InfoLogHlp();
3984	if (!cMaxDepth)
3985	return VINF_SUCCESS;
3986	const unsigned cch = fLongMode ? 16 : 8;
3987	pHlp->pfnPrintf(pHlp,
3988	"cr3=%08x cr4=%08x%s\n"
3989	"%-*s P - Present\n"
3990	"%-*s \| R/W - Read (0) / Write (1)\n"
3991	"%-*s \| \| U/S - User (1) / Supervisor (0)\n"
3992	"%-*s \| \| \| A - Accessed\n"
3993	"%-*s \| \| \| \| D - Dirty\n"
3994	"%-*s \| \| \| \| \| G - Global\n"
3995	"%-*s \| \| \| \| \| \| WT - Write thru\n"
3996	"%-*s \| \| \| \| \| \| \| CD - Cache disable\n"
3997	"%-*s \| \| \| \| \| \| \| \| AT - Attribute table (PAT)\n"
3998	"%-*s \| \| \| \| \| \| \| \| \| NX - No execute (K8)\n"
3999	"%-*s \| \| \| \| \| \| \| \| \| \| 4K/4M/2M - Page size.\n"
4000	"%-*s \| \| \| \| \| \| \| \| \| \| \| AVL - a=allocated; m=mapping; d=track dirty;\n"
4001	"%-*s \| \| \| \| \| \| \| \| \| \| \| \| p=permanent; v=validated;\n"
4002	"%-*s Level \| \| \| \| \| \| \| \| \| \| \| \| Page\n"
4003	/* xxxx n **** P R S A D G WT CD AT NX 4M AVL xxxxxxxxxxxxx
4004	- W U - - - -- -- -- -- -- 010 */
4005	, cr3, cr4, fLongMode ? " Long Mode" : "",
4006	cch, "", cch, "", cch, "", cch, "", cch, "", cch, "", cch, "",
4007	cch, "", cch, "", cch, "", cch, "", cch, "", cch, "", cch, "Address");
4008	if (cr4 & X86_CR4_PAE)
4009	{
4010	if (fLongMode)
4011	return pgmR3DumpHierarchyHcPaePML4(pVM, cr3 & X86_CR3_PAGE_MASK, cr4, cMaxDepth, pHlp);
4012	return pgmR3DumpHierarchyHCPaePDPT(pVM, cr3 & X86_CR3_PAE_PAGE_MASK, 0, cr4, false, cMaxDepth, pHlp);
4013	}
4014	return pgmR3DumpHierarchyHC32BitPD(pVM, cr3 & X86_CR3_PAGE_MASK, cr4, cMaxDepth, pHlp);
4015	}
4016
4017
4018
4019	#ifdef VBOX_WITH_DEBUGGER
4020	/**
4021	* The '.pgmram' command.
4022	*
4023	* @returns VBox status.
4024	* @param pCmd Pointer to the command descriptor (as registered).
4025	* @param pCmdHlp Pointer to command helper functions.
4026	* @param pVM Pointer to the current VM (if any).
4027	* @param paArgs Pointer to (readonly) array of arguments.
4028	* @param cArgs Number of arguments in the array.
4029	*/
4030	static DECLCALLBACK(int) pgmR3CmdRam(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4031	{
4032	/*
4033	* Validate input.
4034	*/
4035	if (!pVM)
4036	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4037	if (!pVM->pgm.s.pRamRangesGC)
4038	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Sorry, no Ram is registered.\n");
4039
4040	/*
4041	* Dump the ranges.
4042	*/
4043	int rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL, "From - To (incl) pvHC\n");
4044	PPGMRAMRANGE pRam;
4045	for (pRam = pVM->pgm.s.pRamRangesR3; pRam; pRam = pRam->pNextR3)
4046	{
4047	rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL,
4048	"%VGp - %VGp %p\n",
4049	pRam->GCPhys, pRam->GCPhysLast, pRam->pvHC);
4050	if (VBOX_FAILURE(rc))
4051	return rc;
4052	}
4053
4054	return VINF_SUCCESS;
4055	}
4056
4057
4058	/**
4059	* The '.pgmmap' command.
4060	*
4061	* @returns VBox status.
4062	* @param pCmd Pointer to the command descriptor (as registered).
4063	* @param pCmdHlp Pointer to command helper functions.
4064	* @param pVM Pointer to the current VM (if any).
4065	* @param paArgs Pointer to (readonly) array of arguments.
4066	* @param cArgs Number of arguments in the array.
4067	*/
4068	static DECLCALLBACK(int) pgmR3CmdMap(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4069	{
4070	/*
4071	* Validate input.
4072	*/
4073	if (!pVM)
4074	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4075	if (!pVM->pgm.s.pMappingsR3)
4076	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Sorry, no mappings are registered.\n");
4077
4078	/*
4079	* Print message about the fixedness of the mappings.
4080	*/
4081	int rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL, pVM->pgm.s.fMappingsFixed ? "The mappings are FIXED.\n" : "The mappings are FLOATING.\n");
4082	if (VBOX_FAILURE(rc))
4083	return rc;
4084
4085	/*
4086	* Dump the ranges.
4087	*/
4088	PPGMMAPPING pCur;
4089	for (pCur = pVM->pgm.s.pMappingsR3; pCur; pCur = pCur->pNextR3)
4090	{
4091	rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL,
4092	"%08x - %08x %s\n",
4093	pCur->GCPtr, pCur->GCPtrLast, pCur->pszDesc);
4094	if (VBOX_FAILURE(rc))
4095	return rc;
4096	}
4097
4098	return VINF_SUCCESS;
4099	}
4100
4101
4102	/**
4103	* The '.pgmsync' command.
4104	*
4105	* @returns VBox status.
4106	* @param pCmd Pointer to the command descriptor (as registered).
4107	* @param pCmdHlp Pointer to command helper functions.
4108	* @param pVM Pointer to the current VM (if any).
4109	* @param paArgs Pointer to (readonly) array of arguments.
4110	* @param cArgs Number of arguments in the array.
4111	*/
4112	static DECLCALLBACK(int) pgmR3CmdSync(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4113	{
4114	/*
4115	* Validate input.
4116	*/
4117	if (!pVM)
4118	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4119
4120	/*
4121	* Force page directory sync.
4122	*/
4123	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
4124
4125	int rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Forcing page directory sync.\n");
4126	if (VBOX_FAILURE(rc))
4127	return rc;
4128
4129	return VINF_SUCCESS;
4130	}
4131
4132
4133	#ifdef VBOX_STRICT
4134	/**
4135	* The '.pgmassertcr3' command.
4136	*
4137	* @returns VBox status.
4138	* @param pCmd Pointer to the command descriptor (as registered).
4139	* @param pCmdHlp Pointer to command helper functions.
4140	* @param pVM Pointer to the current VM (if any).
4141	* @param paArgs Pointer to (readonly) array of arguments.
4142	* @param cArgs Number of arguments in the array.
4143	*/
4144	static DECLCALLBACK(int) pgmR3CmdAssertCR3(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4145	{
4146	/*
4147	* Validate input.
4148	*/
4149	if (!pVM)
4150	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4151
4152	int rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Checking shadow CR3 page tables for consistency.\n");
4153	if (VBOX_FAILURE(rc))
4154	return rc;
4155
4156	PGMAssertCR3(pVM, CPUMGetGuestCR3(pVM), CPUMGetGuestCR4(pVM));
4157
4158	return VINF_SUCCESS;
4159	}
4160	#endif
4161
4162	/**
4163	* The '.pgmsyncalways' command.
4164	*
4165	* @returns VBox status.
4166	* @param pCmd Pointer to the command descriptor (as registered).
4167	* @param pCmdHlp Pointer to command helper functions.
4168	* @param pVM Pointer to the current VM (if any).
4169	* @param paArgs Pointer to (readonly) array of arguments.
4170	* @param cArgs Number of arguments in the array.
4171	*/
4172	static DECLCALLBACK(int) pgmR3CmdSyncAlways(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4173	{
4174	/*
4175	* Validate input.
4176	*/
4177	if (!pVM)
4178	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4179
4180	/*
4181	* Force page directory sync.
4182	*/
4183	if (pVM->pgm.s.fSyncFlags & PGM_SYNC_ALWAYS)
4184	{
4185	ASMAtomicAndU32(&pVM->pgm.s.fSyncFlags, ~PGM_SYNC_ALWAYS);
4186	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Disabled permanent forced page directory syncing.\n");
4187	}
4188	else
4189	{
4190	ASMAtomicOrU32(&pVM->pgm.s.fSyncFlags, PGM_SYNC_ALWAYS);
4191	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
4192	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Enabled permanent forced page directory syncing.\n");
4193	}
4194	}
4195
4196	#endif
4197
4198	/**
4199	* pvUser argument of the pgmR3CheckIntegrity*Node callbacks.
4200	*/
4201	typedef struct PGMCHECKINTARGS
4202	{
4203	bool fLeftToRight; /*< true: left-to-right; false: right-to-left. /
4204	PPGMPHYSHANDLER pPrevPhys;
4205	PPGMVIRTHANDLER pPrevVirt;
4206	PPGMPHYS2VIRTHANDLER pPrevPhys2Virt;
4207	PVM pVM;
4208	} PGMCHECKINTARGS, *PPGMCHECKINTARGS;
4209
4210	/**
4211	* Validate a node in the physical handler tree.
4212	*
4213	* @returns 0 on if ok, other wise 1.
4214	* @param pNode The handler node.
4215	* @param pvUser pVM.
4216	*/
4217	static DECLCALLBACK(int) pgmR3CheckIntegrityPhysHandlerNode(PAVLROGCPHYSNODECORE pNode, void *pvUser)
4218	{
4219	PPGMCHECKINTARGS pArgs = (PPGMCHECKINTARGS)pvUser;
4220	PPGMPHYSHANDLER pCur = (PPGMPHYSHANDLER)pNode;
4221	AssertReleaseReturn(!((uintptr_t)pCur & 7), 1);
4222	AssertReleaseMsg(pCur->Core.Key <= pCur->Core.KeyLast,("pCur=%p %VGp-%VGp %s\n", pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
4223	AssertReleaseMsg( !pArgs->pPrevPhys
4224	\|\| (pArgs->fLeftToRight ? pArgs->pPrevPhys->Core.KeyLast < pCur->Core.Key : pArgs->pPrevPhys->Core.KeyLast > pCur->Core.Key),
4225	("pPrevPhys=%p %VGp-%VGp %s\n"
4226	" pCur=%p %VGp-%VGp %s\n",
4227	pArgs->pPrevPhys, pArgs->pPrevPhys->Core.Key, pArgs->pPrevPhys->Core.KeyLast, pArgs->pPrevPhys->pszDesc,
4228	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
4229	pArgs->pPrevPhys = pCur;
4230	return 0;
4231	}
4232
4233
4234	/**
4235	* Validate a node in the virtual handler tree.
4236	*
4237	* @returns 0 on if ok, other wise 1.
4238	* @param pNode The handler node.
4239	* @param pvUser pVM.
4240	*/
4241	static DECLCALLBACK(int) pgmR3CheckIntegrityVirtHandlerNode(PAVLROGCPTRNODECORE pNode, void *pvUser)
4242	{
4243	PPGMCHECKINTARGS pArgs = (PPGMCHECKINTARGS)pvUser;
4244	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)pNode;
4245	AssertReleaseReturn(!((uintptr_t)pCur & 7), 1);
4246	AssertReleaseMsg(pCur->Core.Key <= pCur->Core.KeyLast,("pCur=%p %VGv-%VGv %s\n", pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
4247	AssertReleaseMsg( !pArgs->pPrevVirt
4248	\|\| (pArgs->fLeftToRight ? pArgs->pPrevVirt->Core.KeyLast < pCur->Core.Key : pArgs->pPrevVirt->Core.KeyLast > pCur->Core.Key),
4249	("pPrevVirt=%p %VGv-%VGv %s\n"
4250	" pCur=%p %VGv-%VGv %s\n",
4251	pArgs->pPrevVirt, pArgs->pPrevVirt->Core.Key, pArgs->pPrevVirt->Core.KeyLast, pArgs->pPrevVirt->pszDesc,
4252	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
4253	for (unsigned iPage = 0; iPage < pCur->cPages; iPage++)
4254	{
4255	AssertReleaseMsg(pCur->aPhysToVirt[iPage].offVirtHandler == -RT_OFFSETOF(PGMVIRTHANDLER, aPhysToVirt[iPage]),
4256	("pCur=%p %VGv-%VGv %s\n"
4257	"iPage=%d offVirtHandle=%#x expected %#x\n",
4258	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc,
4259	iPage, pCur->aPhysToVirt[iPage].offVirtHandler, -RT_OFFSETOF(PGMVIRTHANDLER, aPhysToVirt[iPage])));
4260	}
4261	pArgs->pPrevVirt = pCur;
4262	return 0;
4263	}
4264
4265
4266	/**
4267	* Validate a node in the virtual handler tree.
4268	*
4269	* @returns 0 on if ok, other wise 1.
4270	* @param pNode The handler node.
4271	* @param pvUser pVM.
4272	*/
4273	static DECLCALLBACK(int) pgmR3CheckIntegrityPhysToVirtHandlerNode(PAVLROGCPHYSNODECORE pNode, void *pvUser)
4274	{
4275	PPGMCHECKINTARGS pArgs = (PPGMCHECKINTARGS)pvUser;
4276	PPGMPHYS2VIRTHANDLER pCur = (PPGMPHYS2VIRTHANDLER)pNode;
4277	AssertReleaseMsgReturn(!((uintptr_t)pCur & 3), ("\n"), 1);
4278	AssertReleaseMsgReturn(!(pCur->offVirtHandler & 3), ("\n"), 1);
4279	AssertReleaseMsg(pCur->Core.Key <= pCur->Core.KeyLast,("pCur=%p %VGp-%VGp\n", pCur, pCur->Core.Key, pCur->Core.KeyLast));
4280	AssertReleaseMsg( !pArgs->pPrevPhys2Virt
4281	\|\| (pArgs->fLeftToRight ? pArgs->pPrevPhys2Virt->Core.KeyLast < pCur->Core.Key : pArgs->pPrevPhys2Virt->Core.KeyLast > pCur->Core.Key),
4282	("pPrevPhys2Virt=%p %VGp-%VGp\n"
4283	" pCur=%p %VGp-%VGp\n",
4284	pArgs->pPrevPhys2Virt, pArgs->pPrevPhys2Virt->Core.Key, pArgs->pPrevPhys2Virt->Core.KeyLast,
4285	pCur, pCur->Core.Key, pCur->Core.KeyLast));
4286	AssertReleaseMsg( !pArgs->pPrevPhys2Virt
4287	\|\| (pArgs->fLeftToRight ? pArgs->pPrevPhys2Virt->Core.KeyLast < pCur->Core.Key : pArgs->pPrevPhys2Virt->Core.KeyLast > pCur->Core.Key),
4288	("pPrevPhys2Virt=%p %VGp-%VGp\n"
4289	" pCur=%p %VGp-%VGp\n",
4290	pArgs->pPrevPhys2Virt, pArgs->pPrevPhys2Virt->Core.Key, pArgs->pPrevPhys2Virt->Core.KeyLast,
4291	pCur, pCur->Core.Key, pCur->Core.KeyLast));
4292	AssertReleaseMsg((pCur->offNextAlias & (PGMPHYS2VIRTHANDLER_IN_TREE \| PGMPHYS2VIRTHANDLER_IS_HEAD)) == (PGMPHYS2VIRTHANDLER_IN_TREE \| PGMPHYS2VIRTHANDLER_IS_HEAD),
4293	("pCur=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4294	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias));
4295	if (pCur->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK)
4296	{
4297	PPGMPHYS2VIRTHANDLER pCur2 = pCur;
4298	for (;;)
4299	{
4300	pCur2 = (PPGMPHYS2VIRTHANDLER)((intptr_t)pCur + (pCur->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK));
4301	AssertReleaseMsg(pCur2 != pCur,
4302	(" pCur=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4303	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias));
4304	AssertReleaseMsg((pCur2->offNextAlias & (PGMPHYS2VIRTHANDLER_IN_TREE \| PGMPHYS2VIRTHANDLER_IS_HEAD)) == PGMPHYS2VIRTHANDLER_IN_TREE,
4305	(" pCur=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
4306	"pCur2=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4307	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias,
4308	pCur2, pCur2->Core.Key, pCur2->Core.KeyLast, pCur2->offVirtHandler, pCur2->offNextAlias));
4309	AssertReleaseMsg((pCur2->Core.Key ^ pCur->Core.Key) < PAGE_SIZE,
4310	(" pCur=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
4311	"pCur2=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4312	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias,
4313	pCur2, pCur2->Core.Key, pCur2->Core.KeyLast, pCur2->offVirtHandler, pCur2->offNextAlias));
4314	AssertReleaseMsg((pCur2->Core.KeyLast ^ pCur->Core.KeyLast) < PAGE_SIZE,
4315	(" pCur=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
4316	"pCur2=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4317	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias,
4318	pCur2, pCur2->Core.Key, pCur2->Core.KeyLast, pCur2->offVirtHandler, pCur2->offNextAlias));
4319	if (!(pCur2->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK))
4320	break;
4321	}
4322	}
4323
4324	pArgs->pPrevPhys2Virt = pCur;
4325	return 0;
4326	}
4327
4328
4329	/**
4330	* Perform an integrity check on the PGM component.
4331	*
4332	* @returns VINF_SUCCESS if everything is fine.
4333	* @returns VBox error status after asserting on integrity breach.
4334	* @param pVM The VM handle.
4335	*/
4336	PDMR3DECL(int) PGMR3CheckIntegrity(PVM pVM)
4337	{
4338	AssertReleaseReturn(pVM->pgm.s.offVM, VERR_INTERNAL_ERROR);
4339
4340	/*
4341	* Check the trees.
4342	*/
4343	int cErrors = 0;
4344	const static PGMCHECKINTARGS s_LeftToRight = { true, NULL, NULL, NULL, pVM };
4345	const static PGMCHECKINTARGS s_RightToLeft = { false, NULL, NULL, NULL, pVM };
4346	PGMCHECKINTARGS Args = s_LeftToRight;
4347	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesHC->PhysHandlers, true, pgmR3CheckIntegrityPhysHandlerNode, &Args);
4348	Args = s_RightToLeft;
4349	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesHC->PhysHandlers, false, pgmR3CheckIntegrityPhysHandlerNode, &Args);
4350	Args = s_LeftToRight;
4351	cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesHC->VirtHandlers, true, pgmR3CheckIntegrityVirtHandlerNode, &Args);
4352	Args = s_RightToLeft;
4353	cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesHC->VirtHandlers, false, pgmR3CheckIntegrityVirtHandlerNode, &Args);
4354	Args = s_LeftToRight;
4355	cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesHC->HyperVirtHandlers, true, pgmR3CheckIntegrityVirtHandlerNode, &Args);
4356	Args = s_RightToLeft;
4357	cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesHC->HyperVirtHandlers, false, pgmR3CheckIntegrityVirtHandlerNode, &Args);
4358	Args = s_LeftToRight;
4359	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesHC->PhysToVirtHandlers, true, pgmR3CheckIntegrityPhysToVirtHandlerNode, &Args);
4360	Args = s_RightToLeft;
4361	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesHC->PhysToVirtHandlers, false, pgmR3CheckIntegrityPhysToVirtHandlerNode, &Args);
4362
4363	return !cErrors ? VINF_SUCCESS : VERR_INTERNAL_ERROR;
4364	}
4365
4366
4367	/**
4368	* Inform PGM if we want all mappings to be put into the shadow page table. (necessary for e.g. VMX)
4369	*
4370	* @returns VBox status code.
4371	* @param pVM VM handle.
4372	* @param fEnable Enable or disable shadow mappings
4373	*/
4374	PGMR3DECL(int) PGMR3ChangeShwPDMappings(PVM pVM, bool fEnable)
4375	{
4376	pVM->pgm.s.fDisableMappings = !fEnable;
4377
4378	uint32_t cb;
4379	int rc = PGMR3MappingsSize(pVM, &cb);
4380	AssertRCReturn(rc, rc);
4381
4382	/* Pretend the mappings are now fixed; to force a refresh of the reserved PDEs. */
4383	rc = PGMR3MappingsFix(pVM, MM_HYPER_AREA_ADDRESS, cb);
4384	AssertRCReturn(rc, rc);
4385
4386	return VINF_SUCCESS;
4387	}

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source: vbox/trunk/src/VBox/VMM/PGM.cpp@ 11043

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