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1	/* $Id: PGM.cpp 11133 2008-08-05 14:08:55Z vboxsync $ */
2	/** @file
3	* PGM - Page Manager and Monitor. (Mixing stuff here, not good?)
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22
23	/** @page pg_pgm PGM - The Page Manager and Monitor
24	*
25	*
26	*
27	* @section sec_pgm_modes Paging Modes
28	*
29	* There are three memory contexts: Host Context (HC), Guest Context (GC)
30	* and intermediate context. When talking about paging HC can also be refered to
31	* as "host paging", and GC refered to as "shadow paging".
32	*
33	* We define three basic paging modes: 32-bit, PAE and AMD64. The host paging mode
34	* is defined by the host operating system. The mode used in the shadow paging mode
35	* depends on the host paging mode and what the mode the guest is currently in. The
36	* following relation between the two is defined:
37	*
38	* @verbatim
39	Host > 32-bit \| PAE \| AMD64 \|
40	Guest \| \| \| \|
41	==v================================
42	32-bit 32-bit PAE PAE
43	-------\|--------\|--------\|--------\|
44	PAE PAE PAE PAE
45	-------\|--------\|--------\|--------\|
46	AMD64 AMD64 AMD64 AMD64
47	-------\|--------\|--------\|--------\| @endverbatim
48	*
49	* All configuration except those in the diagonal (upper left) are expected to
50	* require special effort from the switcher (i.e. a bit slower).
51	*
52	*
53	*
54	*
55	* @section sec_pgm_shw The Shadow Memory Context
56	*
57	*
58	* [..]
59	*
60	* Because of guest context mappings requires PDPT and PML4 entries to allow
61	* writing on AMD64, the two upper levels will have fixed flags whatever the
62	* guest is thinking of using there. So, when shadowing the PD level we will
63	* calculate the effective flags of PD and all the higher levels. In legacy
64	* PAE mode this only applies to the PWT and PCD bits (the rest are
65	* ignored/reserved/MBZ). We will ignore those bits for the present.
66	*
67	*
68	*
69	* @section sec_pgm_int The Intermediate Memory Context
70	*
71	* The world switch goes thru an intermediate memory context which purpose it is
72	* to provide different mappings of the switcher code. All guest mappings are also
73	* present in this context.
74	*
75	* The switcher code is mapped at the same location as on the host, at an
76	* identity mapped location (physical equals virtual address), and at the
77	* hypervisor location.
78	*
79	* PGM maintain page tables for 32-bit, PAE and AMD64 paging modes. This
80	* simplifies switching guest CPU mode and consistency at the cost of more
81	* code to do the work. All memory use for those page tables is located below
82	* 4GB (this includes page tables for guest context mappings).
83	*
84	*
85	* @subsection subsec_pgm_int_gc Guest Context Mappings
86	*
87	* During assignment and relocation of a guest context mapping the intermediate
88	* memory context is used to verify the new location.
89	*
90	* Guest context mappings are currently restricted to below 4GB, for reasons
91	* of simplicity. This may change when we implement AMD64 support.
92	*
93	*
94	*
95	*
96	* @section sec_pgm_misc Misc
97	*
98	* @subsection subsec_pgm_misc_diff Differences Between Legacy PAE and Long Mode PAE
99	*
100	* The differences between legacy PAE and long mode PAE are:
101	* -# PDPE bits 1, 2, 5 and 6 are defined differently. In leagcy mode they are
102	* all marked down as must-be-zero, while in long mode 1, 2 and 5 have the
103	* usual meanings while 6 is ignored (AMD). This means that upon switching to
104	* legacy PAE mode we'll have to clear these bits and when going to long mode
105	* they must be set. This applies to both intermediate and shadow contexts,
106	* however we don't need to do it for the intermediate one since we're
107	* executing with CR0.WP at that time.
108	* -# CR3 allows a 32-byte aligned address in legacy mode, while in long mode
109	* a page aligned one is required.
110	*
111	*
112	* @section sec_pgm_handlers Access Handlers
113	*
114	* Placeholder.
115	*
116	*
117	* @subsection sec_pgm_handlers_virt Virtual Access Handlers
118	*
119	* Placeholder.
120	*
121	*
122	* @subsection sec_pgm_handlers_virt Virtual Access Handlers
123	*
124	* We currently implement three types of virtual access handlers: ALL, WRITE
125	* and HYPERVISOR (WRITE). See PGMVIRTHANDLERTYPE for some more details.
126	*
127	* The HYPERVISOR access handlers is kept in a separate tree since it doesn't apply
128	* to physical pages (PGMTREES::HyperVirtHandlers) and only needs to be consulted in
129	* a special \#PF case. The ALL and WRITE are in the PGMTREES::VirtHandlers tree, the
130	* rest of this section is going to be about these handlers.
131	*
132	* We'll go thru the life cycle of a handler and try make sense of it all, don't know
133	* how successfull this is gonna be...
134	*
135	* 1. A handler is registered thru the PGMR3HandlerVirtualRegister and
136	* PGMHandlerVirtualRegisterEx APIs. We check for conflicting virtual handlers
137	* and create a new node that is inserted into the AVL tree (range key). Then
138	* a full PGM resync is flagged (clear pool, sync cr3, update virtual bit of PGMPAGE).
139	*
140	* 2. The following PGMSyncCR3/SyncCR3 operation will first make invoke HandlerVirtualUpdate.
141	*
142	* 2a. HandlerVirtualUpdate will will lookup all the pages covered by virtual handlers
143	* via the current guest CR3 and update the physical page -> virtual handler
144	* translation. Needless to say, this doesn't exactly scale very well. If any changes
145	* are detected, it will flag a virtual bit update just like we did on registration.
146	* PGMPHYS pages with changes will have their virtual handler state reset to NONE.
147	*
148	* 2b. The virtual bit update process will iterate all the pages covered by all the
149	* virtual handlers and update the PGMPAGE virtual handler state to the max of all
150	* virtual handlers on that page.
151	*
152	* 2c. Back in SyncCR3 we will now flush the entire shadow page cache to make sure
153	* we don't miss any alias mappings of the monitored pages.
154	*
155	* 2d. SyncCR3 will then proceed with syncing the CR3 table.
156	*
157	* 3. \#PF(np,read) on a page in the range. This will cause it to be synced
158	* read-only and resumed if it's a WRITE handler. If it's an ALL handler we
159	* will call the handlers like in the next step. If the physical mapping has
160	* changed we will - some time in the future - perform a handler callback
161	* (optional) and update the physical -> virtual handler cache.
162	*
163	* 4. \#PF(,write) on a page in the range. This will cause the handler to
164	* be invoked.
165	*
166	* 5. The guest invalidates the page and changes the physical backing or
167	* unmaps it. This should cause the invalidation callback to be invoked
168	* (it might not yet be 100% perfect). Exactly what happens next... is
169	* this where we mess up and end up out of sync for a while?
170	*
171	* 6. The handler is deregistered by the client via PGMHandlerVirtualDeregister.
172	* We will then set all PGMPAGEs in the physical -> virtual handler cache for
173	* this handler to NONE and trigger a full PGM resync (basically the same
174	* as int step 1). Which means 2 is executed again.
175	*
176	*
177	* @subsubsection sub_sec_pgm_handler_virt_todo TODOs
178	*
179	* There is a bunch of things that needs to be done to make the virtual handlers
180	* work 100% correctly and work more efficiently.
181	*
182	* The first bit hasn't been implemented yet because it's going to slow the
183	* whole mess down even more, and besides it seems to be working reliably for
184	* our current uses. OTOH, some of the optimizations might end up more or less
185	* implementing the missing bits, so we'll see.
186	*
187	* On the optimization side, the first thing to do is to try avoid unnecessary
188	* cache flushing. Then try team up with the shadowing code to track changes
189	* in mappings by means of access to them (shadow in), updates to shadows pages,
190	* invlpg, and shadow PT discarding (perhaps).
191	*
192	* Some idea that have popped up for optimization for current and new features:
193	* - bitmap indicating where there are virtual handlers installed.
194	* (4KB => 220 pages, page 212 => covers 32-bit address space 1:1!)
195	* - Further optimize this by min/max (needs min/max avl getters).
196	* - Shadow page table entry bit (if any left)?
197	*
198	*/
199
200
201	/** @page pg_pgmPhys PGMPhys - Physical Guest Memory Management.
202	*
203	*
204	* Objectives:
205	* - Guest RAM over-commitment using memory ballooning,
206	* zero pages and general page sharing.
207	* - Moving or mirroring a VM onto a different physical machine.
208	*
209	*
210	* @subsection subsec_pgmPhys_Definitions Definitions
211	*
212	* Allocation chunk - A RTR0MemObjAllocPhysNC object and the tracking
213	* machinery assoicated with it.
214	*
215	*
216	*
217	*
218	* @subsection subsec_pgmPhys_AllocPage Allocating a page.
219	*
220	* Initially we map all guest memory to the (per VM) zero page, which
221	* means that none of the read functions will cause pages to be allocated.
222	*
223	* Exception, access bit in page tables that have been shared. This must
224	* be handled, but we must also make sure PGMGst*Modify doesn't make
225	* unnecessary modifications.
226	*
227	* Allocation points:
228	* - PGMPhysWriteGCPhys and PGMPhysWrite.
229	* - Replacing a zero page mapping at \#PF.
230	* - Replacing a shared page mapping at \#PF.
231	* - ROM registration (currently MMR3RomRegister).
232	* - VM restore (pgmR3Load).
233	*
234	* For the first three it would make sense to keep a few pages handy
235	* until we've reached the max memory commitment for the VM.
236	*
237	* For the ROM registration, we know exactly how many pages we need
238	* and will request these from ring-0. For restore, we will save
239	* the number of non-zero pages in the saved state and allocate
240	* them up front. This would allow the ring-0 component to refuse
241	* the request if the isn't sufficient memory available for VM use.
242	*
243	* Btw. for both ROM and restore allocations we won't be requiring
244	* zeroed pages as they are going to be filled instantly.
245	*
246	*
247	* @subsection subsec_pgmPhys_FreePage Freeing a page
248	*
249	* There are a few points where a page can be freed:
250	* - After being replaced by the zero page.
251	* - After being replaced by a shared page.
252	* - After being ballooned by the guest additions.
253	* - At reset.
254	* - At restore.
255	*
256	* When freeing one or more pages they will be returned to the ring-0
257	* component and replaced by the zero page.
258	*
259	* The reasoning for clearing out all the pages on reset is that it will
260	* return us to the exact same state as on power on, and may thereby help
261	* us reduce the memory load on the system. Further it might have a
262	* (temporary) positive influence on memory fragmentation (@see subsec_pgmPhys_Fragmentation).
263	*
264	* On restore, as mention under the allocation topic, pages should be
265	* freed / allocated depending on how many is actually required by the
266	* new VM state. The simplest approach is to do like on reset, and free
267	* all non-ROM pages and then allocate what we need.
268	*
269	* A measure to prevent some fragmentation, would be to let each allocation
270	* chunk have some affinity towards the VM having allocated the most pages
271	* from it. Also, try make sure to allocate from allocation chunks that
272	* are almost full. Admittedly, both these measures might work counter to
273	* our intentions and its probably not worth putting a lot of effort,
274	* cpu time or memory into this.
275	*
276	*
277	* @subsection subsec_pgmPhys_SharePage Sharing a page
278	*
279	* The basic idea is that there there will be a idle priority kernel
280	* thread walking the non-shared VM pages hashing them and looking for
281	* pages with the same checksum. If such pages are found, it will compare
282	* them byte-by-byte to see if they actually are identical. If found to be
283	* identical it will allocate a shared page, copy the content, check that
284	* the page didn't change while doing this, and finally request both the
285	* VMs to use the shared page instead. If the page is all zeros (special
286	* checksum and byte-by-byte check) it will request the VM that owns it
287	* to replace it with the zero page.
288	*
289	* To make this efficient, we will have to make sure not to try share a page
290	* that will change its contents soon. This part requires the most work.
291	* A simple idea would be to request the VM to write monitor the page for
292	* a while to make sure it isn't modified any time soon. Also, it may
293	* make sense to skip pages that are being write monitored since this
294	* information is readily available to the thread if it works on the
295	* per-VM guest memory structures (presently called PGMRAMRANGE).
296	*
297	*
298	* @subsection subsec_pgmPhys_Fragmentation Fragmentation Concerns and Counter Measures
299	*
300	* The pages are organized in allocation chunks in ring-0, this is a necessity
301	* if we wish to have an OS agnostic approach to this whole thing. (On Linux we
302	* could easily work on a page-by-page basis if we liked. Whether this is possible
303	* or efficient on NT I don't quite know.) Fragmentation within these chunks may
304	* become a problem as part of the idea here is that we wish to return memory to
305	* the host system.
306	*
307	* For instance, starting two VMs at the same time, they will both allocate the
308	* guest memory on-demand and if permitted their page allocations will be
309	* intermixed. Shut down one of the two VMs and it will be difficult to return
310	* any memory to the host system because the page allocation for the two VMs are
311	* mixed up in the same allocation chunks.
312	*
313	* To further complicate matters, when pages are freed because they have been
314	* ballooned or become shared/zero the whole idea is that the page is supposed
315	* to be reused by another VM or returned to the host system. This will cause
316	* allocation chunks to contain pages belonging to different VMs and prevent
317	* returning memory to the host when one of those VM shuts down.
318	*
319	* The only way to really deal with this problem is to move pages. This can
320	* either be done at VM shutdown and or by the idle priority worker thread
321	* that will be responsible for finding sharable/zero pages. The mechanisms
322	* involved for coercing a VM to move a page (or to do it for it) will be
323	* the same as when telling it to share/zero a page.
324	*
325	*
326	* @subsection subsec_pgmPhys_Tracking Tracking Structures And Their Cost
327	*
328	* There's a difficult balance between keeping the per-page tracking structures
329	* (global and guest page) easy to use and keeping them from eating too much
330	* memory. We have limited virtual memory resources available when operating in
331	* 32-bit kernel space (on 64-bit there'll it's quite a different story). The
332	* tracking structures will be attemted designed such that we can deal with up
333	* to 32GB of memory on a 32-bit system and essentially unlimited on 64-bit ones.
334	*
335	*
336	* @subsubsection subsubsec_pgmPhys_Tracking_Kernel Kernel Space
337	*
338	* @see pg_GMM
339	*
340	* @subsubsection subsubsec_pgmPhys_Tracking_PerVM Per-VM
341	*
342	* Fixed info is the physical address of the page (HCPhys) and the page id
343	* (described above). Theoretically we'll need 48(-12) bits for the HCPhys part.
344	* Today we've restricting ourselves to 40(-12) bits because this is the current
345	* restrictions of all AMD64 implementations (I think Barcelona will up this
346	* to 48(-12) bits, not that it really matters) and I needed the bits for
347	* tracking mappings of a page. 48-12 = 36. That leaves 28 bits, which means a
348	* decent range for the page id: 2^(28+12) = 1024TB.
349	*
350	* In additions to these, we'll have to keep maintaining the page flags as we
351	* currently do. Although it wouldn't harm to optimize these quite a bit, like
352	* for instance the ROM shouldn't depend on having a write handler installed
353	* in order for it to become read-only. A RO/RW bit should be considered so
354	* that the page syncing code doesn't have to mess about checking multiple
355	* flag combinations (ROM \|\| RW handler \|\| write monitored) in order to
356	* figure out how to setup a shadow PTE. But this of course, is second
357	* priority at present. Current this requires 12 bits, but could probably
358	* be optimized to ~8.
359	*
360	* Then there's the 24 bits used to track which shadow page tables are
361	* currently mapping a page for the purpose of speeding up physical
362	* access handlers, and thereby the page pool cache. More bit for this
363	* purpose wouldn't hurt IIRC.
364	*
365	* Then there is a new bit in which we need to record what kind of page
366	* this is, shared, zero, normal or write-monitored-normal. This'll
367	* require 2 bits. One bit might be needed for indicating whether a
368	* write monitored page has been written to. And yet another one or
369	* two for tracking migration status. 3-4 bits total then.
370	*
371	* Whatever is left will can be used to record the sharabilitiy of a
372	* page. The page checksum will not be stored in the per-VM table as
373	* the idle thread will not be permitted to do modifications to it.
374	* It will instead have to keep its own working set of potentially
375	* shareable pages and their check sums and stuff.
376	*
377	* For the present we'll keep the current packing of the
378	* PGMRAMRANGE::aHCPhys to keep the changes simple, only of course,
379	* we'll have to change it to a struct with a total of 128-bits at
380	* our disposal.
381	*
382	* The initial layout will be like this:
383	* @verbatim
384	RTHCPHYS HCPhys; The current stuff.
385	63:40 Current shadow PT tracking stuff.
386	39:12 The physical page frame number.
387	11:0 The current flags.
388	uint32_t u28PageId : 28; The page id.
389	uint32_t u2State : 2; The page state { zero, shared, normal, write monitored }.
390	uint32_t fWrittenTo : 1; Whether a write monitored page was written to.
391	uint32_t u1Reserved : 1; Reserved for later.
392	uint32_t u32Reserved; Reserved for later, mostly sharing stats.
393	@endverbatim
394	*
395	* The final layout will be something like this:
396	* @verbatim
397	RTHCPHYS HCPhys; The current stuff.
398	63:48 High page id (12+).
399	47:12 The physical page frame number.
400	11:0 Low page id.
401	uint32_t fReadOnly : 1; Whether it's readonly page (rom or monitored in some way).
402	uint32_t u3Type : 3; The page type {RESERVED, MMIO, MMIO2, ROM, shadowed ROM, RAM}.
403	uint32_t u2PhysMon : 2; Physical access handler type {none, read, write, all}.
404	uint32_t u2VirtMon : 2; Virtual access handler type {none, read, write, all}..
405	uint32_t u2State : 2; The page state { zero, shared, normal, write monitored }.
406	uint32_t fWrittenTo : 1; Whether a write monitored page was written to.
407	uint32_t u20Reserved : 20; Reserved for later, mostly sharing stats.
408	uint32_t u32Tracking; The shadow PT tracking stuff, roughly.
409	@endverbatim
410	*
411	* Cost wise, this means we'll double the cost for guest memory. There isn't anyway
412	* around that I'm afraid. It means that the cost of dealing out 32GB of memory
413	* to one or more VMs is: (32GB >> PAGE_SHIFT) * 16 bytes, or 128MBs. Or another
414	* example, the VM heap cost when assigning 1GB to a VM will be: 4MB.
415	*
416	* A couple of cost examples for the total cost per-VM + kernel.
417	* 32-bit Windows and 32-bit linux:
418	* 1GB guest ram, 256K pages: 4MB + 2MB(+) = 6MB
419	* 4GB guest ram, 1M pages: 16MB + 8MB(+) = 24MB
420	* 32GB guest ram, 8M pages: 128MB + 64MB(+) = 192MB
421	* 64-bit Windows and 64-bit linux:
422	* 1GB guest ram, 256K pages: 4MB + 3MB(+) = 7MB
423	* 4GB guest ram, 1M pages: 16MB + 12MB(+) = 28MB
424	* 32GB guest ram, 8M pages: 128MB + 96MB(+) = 224MB
425	*
426	* UPDATE - 2007-09-27:
427	* Will need a ballooned flag/state too because we cannot
428	* trust the guest 100% and reporting the same page as ballooned more
429	* than once will put the GMM off balance.
430	*
431	*
432	* @subsection subsec_pgmPhys_Serializing Serializing Access
433	*
434	* Initially, we'll try a simple scheme:
435	*
436	* - The per-VM RAM tracking structures (PGMRAMRANGE) is only modified
437	* by the EMT thread of that VM while in the pgm critsect.
438	* - Other threads in the VM process that needs to make reliable use of
439	* the per-VM RAM tracking structures will enter the critsect.
440	* - No process external thread or kernel thread will ever try enter
441	* the pgm critical section, as that just won't work.
442	* - The idle thread (and similar threads) doesn't not need 100% reliable
443	* data when performing it tasks as the EMT thread will be the one to
444	* do the actual changes later anyway. So, as long as it only accesses
445	* the main ram range, it can do so by somehow preventing the VM from
446	* being destroyed while it works on it...
447	*
448	* - The over-commitment management, including the allocating/freeing
449	* chunks, is serialized by a ring-0 mutex lock (a fast one since the
450	* more mundane mutex implementation is broken on Linux).
451	* - A separeate mutex is protecting the set of allocation chunks so
452	* that pages can be shared or/and freed up while some other VM is
453	* allocating more chunks. This mutex can be take from under the other
454	* one, but not the otherway around.
455	*
456	*
457	* @subsection subsec_pgmPhys_Request VM Request interface
458	*
459	* When in ring-0 it will become necessary to send requests to a VM so it can
460	* for instance move a page while defragmenting during VM destroy. The idle
461	* thread will make use of this interface to request VMs to setup shared
462	* pages and to perform write monitoring of pages.
463	*
464	* I would propose an interface similar to the current VMReq interface, similar
465	* in that it doesn't require locking and that the one sending the request may
466	* wait for completion if it wishes to. This shouldn't be very difficult to
467	* realize.
468	*
469	* The requests themselves are also pretty simple. They are basically:
470	* -# Check that some precondition is still true.
471	* -# Do the update.
472	* -# Update all shadow page tables involved with the page.
473	*
474	* The 3rd step is identical to what we're already doing when updating a
475	* physical handler, see pgmHandlerPhysicalSetRamFlagsAndFlushShadowPTs.
476	*
477	*
478	*
479	* @section sec_pgmPhys_MappingCaches Mapping Caches
480	*
481	* In order to be able to map in and out memory and to be able to support
482	* guest with more RAM than we've got virtual address space, we'll employing
483	* a mapping cache. There is already a tiny one for GC (see PGMGCDynMapGCPageEx)
484	* and we'll create a similar one for ring-0 unless we decide to setup a dedicate
485	* memory context for the HWACCM execution.
486	*
487	*
488	* @subsection subsec_pgmPhys_MappingCaches_R3 Ring-3
489	*
490	* We've considered implementing the ring-3 mapping cache page based but found
491	* that this was bother some when one had to take into account TLBs+SMP and
492	* portability (missing the necessary APIs on several platforms). There were
493	* also some performance concerns with this approach which hadn't quite been
494	* worked out.
495	*
496	* Instead, we'll be mapping allocation chunks into the VM process. This simplifies
497	* matters greatly quite a bit since we don't need to invent any new ring-0 stuff,
498	* only some minor RTR0MEMOBJ mapping stuff. The main concern here is that mapping
499	* compared to the previous idea is that mapping or unmapping a 1MB chunk is more
500	* costly than a single page, although how much more costly is uncertain. We'll
501	* try address this by using a very big cache, preferably bigger than the actual
502	* VM RAM size if possible. The current VM RAM sizes should give some idea for
503	* 32-bit boxes, while on 64-bit we can probably get away with employing an
504	* unlimited cache.
505	*
506	* The cache have to parts, as already indicated, the ring-3 side and the
507	* ring-0 side.
508	*
509	* The ring-0 will be tied to the page allocator since it will operate on the
510	* memory objects it contains. It will therefore require the first ring-0 mutex
511	* discussed in @ref subsec_pgmPhys_Serializing. We
512	* some double house keeping wrt to who has mapped what I think, since both
513	* VMMR0.r0 and RTR0MemObj will keep track of mapping relataions
514	*
515	* The ring-3 part will be protected by the pgm critsect. For simplicity, we'll
516	* require anyone that desires to do changes to the mapping cache to do that
517	* from within this critsect. Alternatively, we could employ a separate critsect
518	* for serializing changes to the mapping cache as this would reduce potential
519	* contention with other threads accessing mappings unrelated to the changes
520	* that are in process. We can see about this later, contention will show
521	* up in the statistics anyway, so it'll be simple to tell.
522	*
523	* The organization of the ring-3 part will be very much like how the allocation
524	* chunks are organized in ring-0, that is in an AVL tree by chunk id. To avoid
525	* having to walk the tree all the time, we'll have a couple of lookaside entries
526	* like in we do for I/O ports and MMIO in IOM.
527	*
528	* The simplified flow of a PGMPhysRead/Write function:
529	* -# Enter the PGM critsect.
530	* -# Lookup GCPhys in the ram ranges and get the Page ID.
531	* -# Calc the Allocation Chunk ID from the Page ID.
532	* -# Check the lookaside entries and then the AVL tree for the Chunk ID.
533	* If not found in cache:
534	* -# Call ring-0 and request it to be mapped and supply
535	* a chunk to be unmapped if the cache is maxed out already.
536	* -# Insert the new mapping into the AVL tree (id + R3 address).
537	* -# Update the relevant lookaside entry and return the mapping address.
538	* -# Do the read/write according to monitoring flags and everything.
539	* -# Leave the critsect.
540	*
541	*
542	* @section sec_pgmPhys_Fallback Fallback
543	*
544	* Current all the "second tier" hosts will not support the RTR0MemObjAllocPhysNC
545	* API and thus require a fallback.
546	*
547	* So, when RTR0MemObjAllocPhysNC returns VERR_NOT_SUPPORTED the page allocator
548	* will return to the ring-3 caller (and later ring-0) and asking it to seed
549	* the page allocator with some fresh pages (VERR_GMM_SEED_ME). Ring-3 will
550	* then perform an SUPPageAlloc(cbChunk >> PAGE_SHIFT) call and make a
551	* "SeededAllocPages" call to ring-0.
552	*
553	* The first time ring-0 sees the VERR_NOT_SUPPORTED failure it will disable
554	* all page sharing (zero page detection will continue). It will also force
555	* all allocations to come from the VM which seeded the page. Both these
556	* measures are taken to make sure that there will never be any need for
557	* mapping anything into ring-3 - everything will be mapped already.
558	*
559	* Whether we'll continue to use the current MM locked memory management
560	* for this I don't quite know (I'd prefer not to and just ditch that all
561	* togther), we'll see what's simplest to do.
562	*
563	*
564	*
565	* @section sec_pgmPhys_Changes Changes
566	*
567	* Breakdown of the changes involved?
568	*/
569
570
571	/** Saved state data unit version. */
572	#define PGM_SAVED_STATE_VERSION 6
573
574	/*******************************************************************************
575	* Header Files *
576	*******************************************************************************/
577	#define LOG_GROUP LOG_GROUP_PGM
578	#include <VBox/dbgf.h>
579	#include <VBox/pgm.h>
580	#include <VBox/cpum.h>
581	#include <VBox/iom.h>
582	#include <VBox/sup.h>
583	#include <VBox/mm.h>
584	#include <VBox/em.h>
585	#include <VBox/stam.h>
586	#include <VBox/rem.h>
587	#include <VBox/dbgf.h>
588	#include <VBox/rem.h>
589	#include <VBox/selm.h>
590	#include <VBox/ssm.h>
591	#include "PGMInternal.h"
592	#include <VBox/vm.h>
593	#include <VBox/dbg.h>
594	#include <VBox/hwaccm.h>
595
596	#include <iprt/assert.h>
597	#include <iprt/alloc.h>
598	#include <iprt/asm.h>
599	#include <iprt/thread.h>
600	#include <iprt/string.h>
601	#include <VBox/param.h>
602	#include <VBox/err.h>
603
604
605
606	/*******************************************************************************
607	* Internal Functions *
608	*******************************************************************************/
609	static int pgmR3InitPaging(PVM pVM);
610	static DECLCALLBACK(void) pgmR3PhysInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
611	static DECLCALLBACK(void) pgmR3InfoMode(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
612	static DECLCALLBACK(void) pgmR3InfoCr3(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
613	static DECLCALLBACK(int) pgmR3RelocatePhysHandler(PAVLROGCPHYSNODECORE pNode, void *pvUser);
614	static DECLCALLBACK(int) pgmR3RelocateVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser);
615	static DECLCALLBACK(int) pgmR3RelocateHyperVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser);
616	#ifdef VBOX_STRICT
617	static DECLCALLBACK(void) pgmR3ResetNoMorePhysWritesFlag(PVM pVM, VMSTATE enmState, VMSTATE enmOldState, void *pvUser);
618	#endif
619	static DECLCALLBACK(int) pgmR3Save(PVM pVM, PSSMHANDLE pSSM);
620	static DECLCALLBACK(int) pgmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version);
621	static int pgmR3ModeDataInit(PVM pVM, bool fResolveGCAndR0);
622	static void pgmR3ModeDataSwitch(PVM pVM, PGMMODE enmShw, PGMMODE enmGst);
623	static PGMMODE pgmR3CalcShadowMode(PVM pVM, PGMMODE enmGuestMode, SUPPAGINGMODE enmHostMode, PGMMODE enmShadowMode, VMMSWITCHER *penmSwitcher);
624
625	#ifdef VBOX_WITH_STATISTICS
626	static void pgmR3InitStats(PVM pVM);
627	#endif
628
629	#ifdef VBOX_WITH_DEBUGGER
630	/** @todo all but the two last commands must be converted to 'info'. */
631	static DECLCALLBACK(int) pgmR3CmdRam(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
632	static DECLCALLBACK(int) pgmR3CmdMap(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
633	static DECLCALLBACK(int) pgmR3CmdSync(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
634	static DECLCALLBACK(int) pgmR3CmdSyncAlways(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
635	# ifdef VBOX_STRICT
636	static DECLCALLBACK(int) pgmR3CmdAssertCR3(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
637	# endif
638	#endif
639
640
641	/*******************************************************************************
642	* Global Variables *
643	*******************************************************************************/
644	#ifdef VBOX_WITH_DEBUGGER
645	/** Command descriptors. */
646	static const DBGCCMD g_aCmds[] =
647	{
648	/* pszCmd, cArgsMin, cArgsMax, paArgDesc, cArgDescs, pResultDesc, fFlags, pfnHandler pszSyntax, ....pszDescription */
649	{ "pgmram", 0, 0, NULL, 0, NULL, 0, pgmR3CmdRam, "", "Display the ram ranges." },
650	{ "pgmmap", 0, 0, NULL, 0, NULL, 0, pgmR3CmdMap, "", "Display the mapping ranges." },
651	{ "pgmsync", 0, 0, NULL, 0, NULL, 0, pgmR3CmdSync, "", "Sync the CR3 page." },
652	#ifdef VBOX_STRICT
653	{ "pgmassertcr3", 0, 0, NULL, 0, NULL, 0, pgmR3CmdAssertCR3, "", "Check the shadow CR3 mapping." },
654	#endif
655	{ "pgmsyncalways", 0, 0, NULL, 0, NULL, 0, pgmR3CmdSyncAlways, "", "Toggle permanent CR3 syncing." },
656	};
657	#endif
658
659
660
661
662	/*
663	* Shadow - 32-bit mode
664	*/
665	#define PGM_SHW_TYPE PGM_TYPE_32BIT
666	#define PGM_SHW_NAME(name) PGM_SHW_NAME_32BIT(name)
667	#define PGM_SHW_NAME_GC_STR(name) PGM_SHW_NAME_GC_32BIT_STR(name)
668	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_32BIT_STR(name)
669	#include "PGMShw.h"
670
671	/* Guest - real mode */
672	#define PGM_GST_TYPE PGM_TYPE_REAL
673	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
674	#define PGM_GST_NAME_GC_STR(name) PGM_GST_NAME_GC_REAL_STR(name)
675	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
676	#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_REAL(name)
677	#define PGM_BTH_NAME_GC_STR(name) PGM_BTH_NAME_GC_32BIT_REAL_STR(name)
678	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_32BIT_REAL_STR(name)
679	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_PHYS
680	#include "PGMGst.h"
681	#include "PGMBth.h"
682	#undef BTH_PGMPOOLKIND_PT_FOR_PT
683	#undef PGM_BTH_NAME
684	#undef PGM_BTH_NAME_GC_STR
685	#undef PGM_BTH_NAME_R0_STR
686	#undef PGM_GST_TYPE
687	#undef PGM_GST_NAME
688	#undef PGM_GST_NAME_GC_STR
689	#undef PGM_GST_NAME_R0_STR
690
691	/* Guest - protected mode */
692	#define PGM_GST_TYPE PGM_TYPE_PROT
693	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
694	#define PGM_GST_NAME_GC_STR(name) PGM_GST_NAME_GC_PROT_STR(name)
695	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
696	#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_PROT(name)
697	#define PGM_BTH_NAME_GC_STR(name) PGM_BTH_NAME_GC_32BIT_PROT_STR(name)
698	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_32BIT_PROT_STR(name)
699	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_PHYS
700	#include "PGMGst.h"
701	#include "PGMBth.h"
702	#undef BTH_PGMPOOLKIND_PT_FOR_PT
703	#undef PGM_BTH_NAME
704	#undef PGM_BTH_NAME_GC_STR
705	#undef PGM_BTH_NAME_R0_STR
706	#undef PGM_GST_TYPE
707	#undef PGM_GST_NAME
708	#undef PGM_GST_NAME_GC_STR
709	#undef PGM_GST_NAME_R0_STR
710
711	/* Guest - 32-bit mode */
712	#define PGM_GST_TYPE PGM_TYPE_32BIT
713	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
714	#define PGM_GST_NAME_GC_STR(name) PGM_GST_NAME_GC_32BIT_STR(name)
715	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
716	#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_32BIT(name)
717	#define PGM_BTH_NAME_GC_STR(name) PGM_BTH_NAME_GC_32BIT_32BIT_STR(name)
718	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_32BIT_32BIT_STR(name)
719	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT
720	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB
721	#include "PGMGst.h"
722	#include "PGMBth.h"
723	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
724	#undef BTH_PGMPOOLKIND_PT_FOR_PT
725	#undef PGM_BTH_NAME
726	#undef PGM_BTH_NAME_GC_STR
727	#undef PGM_BTH_NAME_R0_STR
728	#undef PGM_GST_TYPE
729	#undef PGM_GST_NAME
730	#undef PGM_GST_NAME_GC_STR
731	#undef PGM_GST_NAME_R0_STR
732
733	#undef PGM_SHW_TYPE
734	#undef PGM_SHW_NAME
735	#undef PGM_SHW_NAME_GC_STR
736	#undef PGM_SHW_NAME_R0_STR
737
738
739	/*
740	* Shadow - PAE mode
741	*/
742	#define PGM_SHW_TYPE PGM_TYPE_PAE
743	#define PGM_SHW_NAME(name) PGM_SHW_NAME_PAE(name)
744	#define PGM_SHW_NAME_GC_STR(name) PGM_SHW_NAME_GC_PAE_STR(name)
745	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_PAE_STR(name)
746	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_REAL(name)
747	#include "PGMShw.h"
748
749	/* Guest - real mode */
750	#define PGM_GST_TYPE PGM_TYPE_REAL
751	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
752	#define PGM_GST_NAME_GC_STR(name) PGM_GST_NAME_GC_REAL_STR(name)
753	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
754	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_REAL(name)
755	#define PGM_BTH_NAME_GC_STR(name) PGM_BTH_NAME_GC_PAE_REAL_STR(name)
756	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_REAL_STR(name)
757	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
758	#include "PGMBth.h"
759	#undef BTH_PGMPOOLKIND_PT_FOR_PT
760	#undef PGM_BTH_NAME
761	#undef PGM_BTH_NAME_GC_STR
762	#undef PGM_BTH_NAME_R0_STR
763	#undef PGM_GST_TYPE
764	#undef PGM_GST_NAME
765	#undef PGM_GST_NAME_GC_STR
766	#undef PGM_GST_NAME_R0_STR
767
768	/* Guest - protected mode */
769	#define PGM_GST_TYPE PGM_TYPE_PROT
770	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
771	#define PGM_GST_NAME_GC_STR(name) PGM_GST_NAME_GC_PROT_STR(name)
772	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
773	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_PROT(name)
774	#define PGM_BTH_NAME_GC_STR(name) PGM_BTH_NAME_GC_PAE_PROT_STR(name)
775	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_PROT_STR(name)
776	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
777	#include "PGMBth.h"
778	#undef BTH_PGMPOOLKIND_PT_FOR_PT
779	#undef PGM_BTH_NAME
780	#undef PGM_BTH_NAME_GC_STR
781	#undef PGM_BTH_NAME_R0_STR
782	#undef PGM_GST_TYPE
783	#undef PGM_GST_NAME
784	#undef PGM_GST_NAME_GC_STR
785	#undef PGM_GST_NAME_R0_STR
786
787	/* Guest - 32-bit mode */
788	#define PGM_GST_TYPE PGM_TYPE_32BIT
789	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
790	#define PGM_GST_NAME_GC_STR(name) PGM_GST_NAME_GC_32BIT_STR(name)
791	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
792	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_32BIT(name)
793	#define PGM_BTH_NAME_GC_STR(name) PGM_BTH_NAME_GC_PAE_32BIT_STR(name)
794	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_32BIT_STR(name)
795	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_32BIT_PT
796	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB
797	#include "PGMBth.h"
798	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
799	#undef BTH_PGMPOOLKIND_PT_FOR_PT
800	#undef PGM_BTH_NAME
801	#undef PGM_BTH_NAME_GC_STR
802	#undef PGM_BTH_NAME_R0_STR
803	#undef PGM_GST_TYPE
804	#undef PGM_GST_NAME
805	#undef PGM_GST_NAME_GC_STR
806	#undef PGM_GST_NAME_R0_STR
807
808	/* Guest - PAE mode */
809	#define PGM_GST_TYPE PGM_TYPE_PAE
810	#define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
811	#define PGM_GST_NAME_GC_STR(name) PGM_GST_NAME_GC_PAE_STR(name)
812	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PAE_STR(name)
813	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_PAE(name)
814	#define PGM_BTH_NAME_GC_STR(name) PGM_BTH_NAME_GC_PAE_PAE_STR(name)
815	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_PAE_STR(name)
816	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
817	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
818	#include "PGMGst.h"
819	#include "PGMBth.h"
820	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
821	#undef BTH_PGMPOOLKIND_PT_FOR_PT
822	#undef PGM_BTH_NAME
823	#undef PGM_BTH_NAME_GC_STR
824	#undef PGM_BTH_NAME_R0_STR
825	#undef PGM_GST_TYPE
826	#undef PGM_GST_NAME
827	#undef PGM_GST_NAME_GC_STR
828	#undef PGM_GST_NAME_R0_STR
829
830	#undef PGM_SHW_TYPE
831	#undef PGM_SHW_NAME
832	#undef PGM_SHW_NAME_GC_STR
833	#undef PGM_SHW_NAME_R0_STR
834
835
836	/*
837	* Shadow - AMD64 mode
838	*/
839	#define PGM_SHW_TYPE PGM_TYPE_AMD64
840	#define PGM_SHW_NAME(name) PGM_SHW_NAME_AMD64(name)
841	#define PGM_SHW_NAME_GC_STR(name) PGM_SHW_NAME_GC_AMD64_STR(name)
842	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_AMD64_STR(name)
843	#include "PGMShw.h"
844
845	/* Guest - AMD64 mode */
846	#define PGM_GST_TYPE PGM_TYPE_AMD64
847	#define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
848	#define PGM_GST_NAME_GC_STR(name) PGM_GST_NAME_GC_AMD64_STR(name)
849	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_AMD64_STR(name)
850	#define PGM_BTH_NAME(name) PGM_BTH_NAME_AMD64_AMD64(name)
851	#define PGM_BTH_NAME_GC_STR(name) PGM_BTH_NAME_GC_AMD64_AMD64_STR(name)
852	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_AMD64_AMD64_STR(name)
853	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
854	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
855	#include "PGMGst.h"
856	#include "PGMBth.h"
857	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
858	#undef BTH_PGMPOOLKIND_PT_FOR_PT
859	#undef PGM_BTH_NAME
860	#undef PGM_BTH_NAME_GC_STR
861	#undef PGM_BTH_NAME_R0_STR
862	#undef PGM_GST_TYPE
863	#undef PGM_GST_NAME
864	#undef PGM_GST_NAME_GC_STR
865	#undef PGM_GST_NAME_R0_STR
866
867	#undef PGM_SHW_TYPE
868	#undef PGM_SHW_NAME
869	#undef PGM_SHW_NAME_GC_STR
870	#undef PGM_SHW_NAME_R0_STR
871
872	/*
873	* Shadow - Nested paging mode
874	*/
875	#define PGM_SHW_TYPE PGM_TYPE_NESTED
876	#define PGM_SHW_NAME(name) PGM_SHW_NAME_NESTED(name)
877	#define PGM_SHW_NAME_GC_STR(name) PGM_SHW_NAME_GC_NESTED_STR(name)
878	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_NESTED_STR(name)
879	#include "PGMShw.h"
880
881	/* Guest - real mode */
882	#define PGM_GST_TYPE PGM_TYPE_REAL
883	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
884	#define PGM_GST_NAME_GC_STR(name) PGM_GST_NAME_GC_REAL_STR(name)
885	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
886	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_REAL(name)
887	#define PGM_BTH_NAME_GC_STR(name) PGM_BTH_NAME_GC_NESTED_REAL_STR(name)
888	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_REAL_STR(name)
889	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
890	#include "PGMBth.h"
891	#undef BTH_PGMPOOLKIND_PT_FOR_PT
892	#undef PGM_BTH_NAME
893	#undef PGM_BTH_NAME_GC_STR
894	#undef PGM_BTH_NAME_R0_STR
895	#undef PGM_GST_TYPE
896	#undef PGM_GST_NAME
897	#undef PGM_GST_NAME_GC_STR
898	#undef PGM_GST_NAME_R0_STR
899
900	/* Guest - protected mode */
901	#define PGM_GST_TYPE PGM_TYPE_PROT
902	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
903	#define PGM_GST_NAME_GC_STR(name) PGM_GST_NAME_GC_PROT_STR(name)
904	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
905	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_PROT(name)
906	#define PGM_BTH_NAME_GC_STR(name) PGM_BTH_NAME_GC_NESTED_PROT_STR(name)
907	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_PROT_STR(name)
908	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
909	#include "PGMBth.h"
910	#undef BTH_PGMPOOLKIND_PT_FOR_PT
911	#undef PGM_BTH_NAME
912	#undef PGM_BTH_NAME_GC_STR
913	#undef PGM_BTH_NAME_R0_STR
914	#undef PGM_GST_TYPE
915	#undef PGM_GST_NAME
916	#undef PGM_GST_NAME_GC_STR
917	#undef PGM_GST_NAME_R0_STR
918
919	/* Guest - 32-bit mode */
920	#define PGM_GST_TYPE PGM_TYPE_32BIT
921	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
922	#define PGM_GST_NAME_GC_STR(name) PGM_GST_NAME_GC_32BIT_STR(name)
923	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
924	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_32BIT(name)
925	#define PGM_BTH_NAME_GC_STR(name) PGM_BTH_NAME_GC_NESTED_32BIT_STR(name)
926	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_32BIT_STR(name)
927	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_32BIT_PT
928	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB
929	#include "PGMBth.h"
930	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
931	#undef BTH_PGMPOOLKIND_PT_FOR_PT
932	#undef PGM_BTH_NAME
933	#undef PGM_BTH_NAME_GC_STR
934	#undef PGM_BTH_NAME_R0_STR
935	#undef PGM_GST_TYPE
936	#undef PGM_GST_NAME
937	#undef PGM_GST_NAME_GC_STR
938	#undef PGM_GST_NAME_R0_STR
939
940	/* Guest - PAE mode */
941	#define PGM_GST_TYPE PGM_TYPE_PAE
942	#define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
943	#define PGM_GST_NAME_GC_STR(name) PGM_GST_NAME_GC_PAE_STR(name)
944	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PAE_STR(name)
945	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_PAE(name)
946	#define PGM_BTH_NAME_GC_STR(name) PGM_BTH_NAME_GC_NESTED_PAE_STR(name)
947	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_PAE_STR(name)
948	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
949	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
950	#include "PGMBth.h"
951	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
952	#undef BTH_PGMPOOLKIND_PT_FOR_PT
953	#undef PGM_BTH_NAME
954	#undef PGM_BTH_NAME_GC_STR
955	#undef PGM_BTH_NAME_R0_STR
956	#undef PGM_GST_TYPE
957	#undef PGM_GST_NAME
958	#undef PGM_GST_NAME_GC_STR
959	#undef PGM_GST_NAME_R0_STR
960
961	/* Guest - AMD64 mode */
962	#define PGM_GST_TYPE PGM_TYPE_AMD64
963	#define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
964	#define PGM_GST_NAME_GC_STR(name) PGM_GST_NAME_GC_AMD64_STR(name)
965	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_AMD64_STR(name)
966	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_AMD64(name)
967	#define PGM_BTH_NAME_GC_STR(name) PGM_BTH_NAME_GC_NESTED_AMD64_STR(name)
968	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_AMD64_STR(name)
969	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
970	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
971	#include "PGMBth.h"
972	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
973	#undef BTH_PGMPOOLKIND_PT_FOR_PT
974	#undef PGM_BTH_NAME
975	#undef PGM_BTH_NAME_GC_STR
976	#undef PGM_BTH_NAME_R0_STR
977	#undef PGM_GST_TYPE
978	#undef PGM_GST_NAME
979	#undef PGM_GST_NAME_GC_STR
980	#undef PGM_GST_NAME_R0_STR
981
982	#undef PGM_SHW_TYPE
983	#undef PGM_SHW_NAME
984	#undef PGM_SHW_NAME_GC_STR
985	#undef PGM_SHW_NAME_R0_STR
986
987
988	#ifdef PGM_WITH_EPT
989	/*
990	* Shadow - EPT
991	*/
992	#define PGM_SHW_TYPE PGM_TYPE_EPT
993	#define PGM_SHW_NAME(name) PGM_SHW_NAME_EPT(name)
994	#define PGM_SHW_NAME_GC_STR(name) PGM_SHW_NAME_GC_EPT_STR(name)
995	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_EPT_STR(name)
996	#include "PGMShw.h"
997
998	/* Guest - real mode */
999	#define PGM_GST_TYPE PGM_TYPE_REAL
1000	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
1001	#define PGM_GST_NAME_GC_STR(name) PGM_GST_NAME_GC_REAL_STR(name)
1002	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
1003	#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_REAL(name)
1004	#define PGM_BTH_NAME_GC_STR(name) PGM_BTH_NAME_GC_EPT_REAL_STR(name)
1005	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_REAL_STR(name)
1006	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
1007	#include "PGMBth.h"
1008	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1009	#undef PGM_BTH_NAME
1010	#undef PGM_BTH_NAME_GC_STR
1011	#undef PGM_BTH_NAME_R0_STR
1012	#undef PGM_GST_TYPE
1013	#undef PGM_GST_NAME
1014	#undef PGM_GST_NAME_GC_STR
1015	#undef PGM_GST_NAME_R0_STR
1016
1017	/* Guest - protected mode */
1018	#define PGM_GST_TYPE PGM_TYPE_PROT
1019	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
1020	#define PGM_GST_NAME_GC_STR(name) PGM_GST_NAME_GC_PROT_STR(name)
1021	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
1022	#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_PROT(name)
1023	#define PGM_BTH_NAME_GC_STR(name) PGM_BTH_NAME_GC_EPT_PROT_STR(name)
1024	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_PROT_STR(name)
1025	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
1026	#include "PGMBth.h"
1027	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1028	#undef PGM_BTH_NAME
1029	#undef PGM_BTH_NAME_GC_STR
1030	#undef PGM_BTH_NAME_R0_STR
1031	#undef PGM_GST_TYPE
1032	#undef PGM_GST_NAME
1033	#undef PGM_GST_NAME_GC_STR
1034	#undef PGM_GST_NAME_R0_STR
1035
1036	/* Guest - 32-bit mode */
1037	#define PGM_GST_TYPE PGM_TYPE_32BIT
1038	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
1039	#define PGM_GST_NAME_GC_STR(name) PGM_GST_NAME_GC_32BIT_STR(name)
1040	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
1041	#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_32BIT(name)
1042	#define PGM_BTH_NAME_GC_STR(name) PGM_BTH_NAME_GC_EPT_32BIT_STR(name)
1043	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_32BIT_STR(name)
1044	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_32BIT_PT
1045	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB
1046	#include "PGMBth.h"
1047	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
1048	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1049	#undef PGM_BTH_NAME
1050	#undef PGM_BTH_NAME_GC_STR
1051	#undef PGM_BTH_NAME_R0_STR
1052	#undef PGM_GST_TYPE
1053	#undef PGM_GST_NAME
1054	#undef PGM_GST_NAME_GC_STR
1055	#undef PGM_GST_NAME_R0_STR
1056
1057	/* Guest - PAE mode */
1058	#define PGM_GST_TYPE PGM_TYPE_PAE
1059	#define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
1060	#define PGM_GST_NAME_GC_STR(name) PGM_GST_NAME_GC_PAE_STR(name)
1061	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PAE_STR(name)
1062	#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_PAE(name)
1063	#define PGM_BTH_NAME_GC_STR(name) PGM_BTH_NAME_GC_EPT_PAE_STR(name)
1064	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_PAE_STR(name)
1065	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
1066	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
1067	#include "PGMBth.h"
1068	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
1069	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1070	#undef PGM_BTH_NAME
1071	#undef PGM_BTH_NAME_GC_STR
1072	#undef PGM_BTH_NAME_R0_STR
1073	#undef PGM_GST_TYPE
1074	#undef PGM_GST_NAME
1075	#undef PGM_GST_NAME_GC_STR
1076	#undef PGM_GST_NAME_R0_STR
1077
1078	/* Guest - AMD64 mode */
1079	#define PGM_GST_TYPE PGM_TYPE_AMD64
1080	#define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
1081	#define PGM_GST_NAME_GC_STR(name) PGM_GST_NAME_GC_AMD64_STR(name)
1082	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_AMD64_STR(name)
1083	#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_AMD64(name)
1084	#define PGM_BTH_NAME_GC_STR(name) PGM_BTH_NAME_GC_EPT_AMD64_STR(name)
1085	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_AMD64_STR(name)
1086	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
1087	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
1088	#include "PGMBth.h"
1089	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
1090	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1091	#undef PGM_BTH_NAME
1092	#undef PGM_BTH_NAME_GC_STR
1093	#undef PGM_BTH_NAME_R0_STR
1094	#undef PGM_GST_TYPE
1095	#undef PGM_GST_NAME
1096	#undef PGM_GST_NAME_GC_STR
1097	#undef PGM_GST_NAME_R0_STR
1098
1099	#undef PGM_SHW_TYPE
1100	#undef PGM_SHW_NAME
1101	#undef PGM_SHW_NAME_GC_STR
1102	#undef PGM_SHW_NAME_R0_STR
1103	#endif /* PGM_WITH_EPT */
1104
1105	/**
1106	* Initiates the paging of VM.
1107	*
1108	* @returns VBox status code.
1109	* @param pVM Pointer to VM structure.
1110	*/
1111	PGMR3DECL(int) PGMR3Init(PVM pVM)
1112	{
1113	LogFlow(("PGMR3Init:\n"));
1114
1115	/*
1116	* Assert alignment and sizes.
1117	*/
1118	AssertRelease(sizeof(pVM->pgm.s) <= sizeof(pVM->pgm.padding));
1119
1120	/*
1121	* Init the structure.
1122	*/
1123	pVM->pgm.s.offVM = RT_OFFSETOF(VM, pgm.s);
1124	pVM->pgm.s.enmShadowMode = PGMMODE_INVALID;
1125	pVM->pgm.s.enmGuestMode = PGMMODE_INVALID;
1126	pVM->pgm.s.enmHostMode = SUPPAGINGMODE_INVALID;
1127	pVM->pgm.s.GCPhysCR3 = NIL_RTGCPHYS;
1128	pVM->pgm.s.GCPhysGstCR3Monitored = NIL_RTGCPHYS;
1129	pVM->pgm.s.fA20Enabled = true;
1130	pVM->pgm.s.pGstPaePDPTHC = NULL;
1131	pVM->pgm.s.pGstPaePDPTGC = 0;
1132	for (unsigned i = 0; i < ELEMENTS(pVM->pgm.s.apGstPaePDsHC); i++)
1133	{
1134	pVM->pgm.s.apGstPaePDsHC[i] = NULL;
1135	pVM->pgm.s.apGstPaePDsGC[i] = 0;
1136	pVM->pgm.s.aGCPhysGstPaePDs[i] = NIL_RTGCPHYS;
1137	pVM->pgm.s.aGCPhysGstPaePDsMonitored[i] = NIL_RTGCPHYS;
1138	}
1139
1140	#ifdef VBOX_STRICT
1141	VMR3AtStateRegister(pVM, pgmR3ResetNoMorePhysWritesFlag, NULL);
1142	#endif
1143
1144	/*
1145	* Get the configured RAM size - to estimate saved state size.
1146	*/
1147	uint64_t cbRam;
1148	int rc = CFGMR3QueryU64(CFGMR3GetRoot(pVM), "RamSize", &cbRam);
1149	if (rc == VERR_CFGM_VALUE_NOT_FOUND)
1150	cbRam = pVM->pgm.s.cbRamSize = 0;
1151	else if (VBOX_SUCCESS(rc))
1152	{
1153	if (cbRam < PAGE_SIZE)
1154	cbRam = 0;
1155	cbRam = RT_ALIGN_64(cbRam, PAGE_SIZE);
1156	pVM->pgm.s.cbRamSize = (RTUINT)cbRam;
1157	}
1158	else
1159	{
1160	AssertMsgFailed(("Configuration error: Failed to query integer \"RamSize\", rc=%Vrc.\n", rc));
1161	return rc;
1162	}
1163
1164	/*
1165	* Register saved state data unit.
1166	*/
1167	rc = SSMR3RegisterInternal(pVM, "pgm", 1, PGM_SAVED_STATE_VERSION, (size_t)cbRam + sizeof(PGM),
1168	NULL, pgmR3Save, NULL,
1169	NULL, pgmR3Load, NULL);
1170	if (VBOX_FAILURE(rc))
1171	return rc;
1172
1173	/*
1174	* Initialize the PGM critical section and flush the phys TLBs
1175	*/
1176	rc = PDMR3CritSectInit(pVM, &pVM->pgm.s.CritSect, "PGM");
1177	AssertRCReturn(rc, rc);
1178
1179	PGMR3PhysChunkInvalidateTLB(pVM);
1180	PGMPhysInvalidatePageR3MapTLB(pVM);
1181	PGMPhysInvalidatePageR0MapTLB(pVM);
1182	PGMPhysInvalidatePageGCMapTLB(pVM);
1183
1184	/*
1185	* Trees
1186	*/
1187	rc = MMHyperAlloc(pVM, sizeof(PGMTREES), 0, MM_TAG_PGM, (void **)&pVM->pgm.s.pTreesHC);
1188	if (VBOX_SUCCESS(rc))
1189	{
1190	pVM->pgm.s.pTreesGC = MMHyperHC2GC(pVM, pVM->pgm.s.pTreesHC);
1191
1192	/*
1193	* Alocate the zero page.
1194	*/
1195	rc = MMHyperAlloc(pVM, PAGE_SIZE, PAGE_SIZE, MM_TAG_PGM, &pVM->pgm.s.pvZeroPgR3);
1196	}
1197	if (VBOX_SUCCESS(rc))
1198	{
1199	pVM->pgm.s.pvZeroPgGC = MMHyperR3ToGC(pVM, pVM->pgm.s.pvZeroPgR3);
1200	pVM->pgm.s.pvZeroPgR0 = MMHyperR3ToR0(pVM, pVM->pgm.s.pvZeroPgR3);
1201	AssertRelease(pVM->pgm.s.pvZeroPgR0 != NIL_RTHCPHYS);
1202	pVM->pgm.s.HCPhysZeroPg = MMR3HyperHCVirt2HCPhys(pVM, pVM->pgm.s.pvZeroPgR3);
1203	AssertRelease(pVM->pgm.s.HCPhysZeroPg != NIL_RTHCPHYS);
1204
1205	/*
1206	* Init the paging.
1207	*/
1208	rc = pgmR3InitPaging(pVM);
1209	}
1210	if (VBOX_SUCCESS(rc))
1211	{
1212	/*
1213	* Init the page pool.
1214	*/
1215	rc = pgmR3PoolInit(pVM);
1216	}
1217	if (VBOX_SUCCESS(rc))
1218	{
1219	/*
1220	* Info & statistics
1221	*/
1222	DBGFR3InfoRegisterInternal(pVM, "mode",
1223	"Shows the current paging mode. "
1224	"Recognizes 'all', 'guest', 'shadow' and 'host' as arguments, defaulting to 'all' if nothing's given.",
1225	pgmR3InfoMode);
1226	DBGFR3InfoRegisterInternal(pVM, "pgmcr3",
1227	"Dumps all the entries in the top level paging table. No arguments.",
1228	pgmR3InfoCr3);
1229	DBGFR3InfoRegisterInternal(pVM, "phys",
1230	"Dumps all the physical address ranges. No arguments.",
1231	pgmR3PhysInfo);
1232	DBGFR3InfoRegisterInternal(pVM, "handlers",
1233	"Dumps physical, virtual and hyper virtual handlers. "
1234	"Pass 'phys', 'virt', 'hyper' as argument if only one kind is wanted."
1235	"Add 'nost' if the statistics are unwanted, use together with 'all' or explicit selection.",
1236	pgmR3InfoHandlers);
1237	DBGFR3InfoRegisterInternal(pVM, "mappings",
1238	"Dumps guest mappings.",
1239	pgmR3MapInfo);
1240
1241	STAM_REL_REG(pVM, &pVM->pgm.s.cGuestModeChanges, STAMTYPE_COUNTER, "/PGM/cGuestModeChanges", STAMUNIT_OCCURENCES, "Number of guest mode changes.");
1242	#ifdef VBOX_WITH_STATISTICS
1243	pgmR3InitStats(pVM);
1244	#endif
1245	#ifdef VBOX_WITH_DEBUGGER
1246	/*
1247	* Debugger commands.
1248	*/
1249	static bool fRegisteredCmds = false;
1250	if (!fRegisteredCmds)
1251	{
1252	int rc = DBGCRegisterCommands(&g_aCmds[0], ELEMENTS(g_aCmds));
1253	if (VBOX_SUCCESS(rc))
1254	fRegisteredCmds = true;
1255	}
1256	#endif
1257	return VINF_SUCCESS;
1258	}
1259
1260	/* Almost no cleanup necessary, MM frees all memory. */
1261	PDMR3CritSectDelete(&pVM->pgm.s.CritSect);
1262
1263	return rc;
1264	}
1265
1266
1267	/**
1268	* Init paging.
1269	*
1270	* Since we need to check what mode the host is operating in before we can choose
1271	* the right paging functions for the host we have to delay this until R0 has
1272	* been initialized.
1273	*
1274	* @returns VBox status code.
1275	* @param pVM VM handle.
1276	*/
1277	static int pgmR3InitPaging(PVM pVM)
1278	{
1279	/*
1280	* Force a recalculation of modes and switcher so everyone gets notified.
1281	*/
1282	pVM->pgm.s.enmShadowMode = PGMMODE_INVALID;
1283	pVM->pgm.s.enmGuestMode = PGMMODE_INVALID;
1284	pVM->pgm.s.enmHostMode = SUPPAGINGMODE_INVALID;
1285
1286	/*
1287	* Allocate static mapping space for whatever the cr3 register
1288	* points to and in the case of PAE mode to the 4 PDs.
1289	*/
1290	int rc = MMR3HyperReserve(pVM, PAGE_SIZE * 5, "CR3 mapping", &pVM->pgm.s.GCPtrCR3Mapping);
1291	if (VBOX_FAILURE(rc))
1292	{
1293	AssertMsgFailed(("Failed to reserve two pages for cr mapping in HMA, rc=%Vrc\n", rc));
1294	return rc;
1295	}
1296	MMR3HyperReserve(pVM, PAGE_SIZE, "fence", NULL);
1297
1298	/*
1299	* Allocate pages for the three possible intermediate contexts
1300	* (AMD64, PAE and plain 32-Bit). We maintain all three contexts
1301	* for the sake of simplicity. The AMD64 uses the PAE for the
1302	* lower levels, making the total number of pages 11 (3 + 7 + 1).
1303	*
1304	* We assume that two page tables will be enought for the core code
1305	* mappings (HC virtual and identity).
1306	*/
1307	pVM->pgm.s.pInterPD = (PX86PD)MMR3PageAllocLow(pVM);
1308	pVM->pgm.s.apInterPTs[0] = (PX86PT)MMR3PageAllocLow(pVM);
1309	pVM->pgm.s.apInterPTs[1] = (PX86PT)MMR3PageAllocLow(pVM);
1310	pVM->pgm.s.apInterPaePTs[0] = (PX86PTPAE)MMR3PageAlloc(pVM);
1311	pVM->pgm.s.apInterPaePTs[1] = (PX86PTPAE)MMR3PageAlloc(pVM);
1312	pVM->pgm.s.apInterPaePDs[0] = (PX86PDPAE)MMR3PageAlloc(pVM);
1313	pVM->pgm.s.apInterPaePDs[1] = (PX86PDPAE)MMR3PageAlloc(pVM);
1314	pVM->pgm.s.apInterPaePDs[2] = (PX86PDPAE)MMR3PageAlloc(pVM);
1315	pVM->pgm.s.apInterPaePDs[3] = (PX86PDPAE)MMR3PageAlloc(pVM);
1316	pVM->pgm.s.pInterPaePDPT = (PX86PDPT)MMR3PageAllocLow(pVM);
1317	pVM->pgm.s.pInterPaePDPT64 = (PX86PDPT)MMR3PageAllocLow(pVM);
1318	pVM->pgm.s.pInterPaePML4 = (PX86PML4)MMR3PageAllocLow(pVM);
1319	if ( !pVM->pgm.s.pInterPD
1320	\|\| !pVM->pgm.s.apInterPTs[0]
1321	\|\| !pVM->pgm.s.apInterPTs[1]
1322	\|\| !pVM->pgm.s.apInterPaePTs[0]
1323	\|\| !pVM->pgm.s.apInterPaePTs[1]
1324	\|\| !pVM->pgm.s.apInterPaePDs[0]
1325	\|\| !pVM->pgm.s.apInterPaePDs[1]
1326	\|\| !pVM->pgm.s.apInterPaePDs[2]
1327	\|\| !pVM->pgm.s.apInterPaePDs[3]
1328	\|\| !pVM->pgm.s.pInterPaePDPT
1329	\|\| !pVM->pgm.s.pInterPaePDPT64
1330	\|\| !pVM->pgm.s.pInterPaePML4)
1331	{
1332	AssertMsgFailed(("Failed to allocate pages for the intermediate context!\n"));
1333	return VERR_NO_PAGE_MEMORY;
1334	}
1335
1336	pVM->pgm.s.HCPhysInterPD = MMPage2Phys(pVM, pVM->pgm.s.pInterPD);
1337	AssertRelease(pVM->pgm.s.HCPhysInterPD != NIL_RTHCPHYS && !(pVM->pgm.s.HCPhysInterPD & PAGE_OFFSET_MASK));
1338	pVM->pgm.s.HCPhysInterPaePDPT = MMPage2Phys(pVM, pVM->pgm.s.pInterPaePDPT);
1339	AssertRelease(pVM->pgm.s.HCPhysInterPaePDPT != NIL_RTHCPHYS && !(pVM->pgm.s.HCPhysInterPaePDPT & PAGE_OFFSET_MASK));
1340	pVM->pgm.s.HCPhysInterPaePML4 = MMPage2Phys(pVM, pVM->pgm.s.pInterPaePML4);
1341	AssertRelease(pVM->pgm.s.HCPhysInterPaePML4 != NIL_RTHCPHYS && !(pVM->pgm.s.HCPhysInterPaePML4 & PAGE_OFFSET_MASK));
1342
1343	/*
1344	* Initialize the pages, setting up the PML4 and PDPT for repetitive 4GB action.
1345	*/
1346	ASMMemZeroPage(pVM->pgm.s.pInterPD);
1347	ASMMemZeroPage(pVM->pgm.s.apInterPTs[0]);
1348	ASMMemZeroPage(pVM->pgm.s.apInterPTs[1]);
1349
1350	ASMMemZeroPage(pVM->pgm.s.apInterPaePTs[0]);
1351	ASMMemZeroPage(pVM->pgm.s.apInterPaePTs[1]);
1352
1353	ASMMemZeroPage(pVM->pgm.s.pInterPaePDPT);
1354	for (unsigned i = 0; i < ELEMENTS(pVM->pgm.s.apInterPaePDs); i++)
1355	{
1356	ASMMemZeroPage(pVM->pgm.s.apInterPaePDs[i]);
1357	pVM->pgm.s.pInterPaePDPT->a[i].u = X86_PDPE_P \| PGM_PLXFLAGS_PERMANENT
1358	\| MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[i]);
1359	}
1360
1361	for (unsigned i = 0; i < ELEMENTS(pVM->pgm.s.pInterPaePDPT64->a); i++)
1362	{
1363	const unsigned iPD = i % ELEMENTS(pVM->pgm.s.apInterPaePDs);
1364	pVM->pgm.s.pInterPaePDPT64->a[i].u = X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_A \| PGM_PLXFLAGS_PERMANENT
1365	\| MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[iPD]);
1366	}
1367
1368	RTHCPHYS HCPhysInterPaePDPT64 = MMPage2Phys(pVM, pVM->pgm.s.pInterPaePDPT64);
1369	for (unsigned i = 0; i < ELEMENTS(pVM->pgm.s.pInterPaePML4->a); i++)
1370	pVM->pgm.s.pInterPaePML4->a[i].u = X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_A \| PGM_PLXFLAGS_PERMANENT
1371	\| HCPhysInterPaePDPT64;
1372
1373	/*
1374	* Allocate pages for the three possible guest contexts (AMD64, PAE and plain 32-Bit).
1375	* We allocate pages for all three posibilities to in order to simplify mappings and
1376	* avoid resource failure during mode switches. So, we need to cover all levels of the
1377	* of the first 4GB down to PD level.
1378	* As with the intermediate context, AMD64 uses the PAE PDPT and PDs.
1379	*/
1380	pVM->pgm.s.pHC32BitPD = (PX86PD)MMR3PageAllocLow(pVM);
1381	pVM->pgm.s.apHCPaePDs[0] = (PX86PDPAE)MMR3PageAlloc(pVM);
1382	pVM->pgm.s.apHCPaePDs[1] = (PX86PDPAE)MMR3PageAlloc(pVM);
1383	AssertRelease((uintptr_t)pVM->pgm.s.apHCPaePDs[0] + PAGE_SIZE == (uintptr_t)pVM->pgm.s.apHCPaePDs[1]);
1384	pVM->pgm.s.apHCPaePDs[2] = (PX86PDPAE)MMR3PageAlloc(pVM);
1385	AssertRelease((uintptr_t)pVM->pgm.s.apHCPaePDs[1] + PAGE_SIZE == (uintptr_t)pVM->pgm.s.apHCPaePDs[2]);
1386	pVM->pgm.s.apHCPaePDs[3] = (PX86PDPAE)MMR3PageAlloc(pVM);
1387	AssertRelease((uintptr_t)pVM->pgm.s.apHCPaePDs[2] + PAGE_SIZE == (uintptr_t)pVM->pgm.s.apHCPaePDs[3]);
1388	pVM->pgm.s.pHCPaePDPT = (PX86PDPT)MMR3PageAllocLow(pVM);
1389	pVM->pgm.s.pHCNestedRoot = MMR3PageAllocLow(pVM);
1390
1391	if ( !pVM->pgm.s.pHC32BitPD
1392	\|\| !pVM->pgm.s.apHCPaePDs[0]
1393	\|\| !pVM->pgm.s.apHCPaePDs[1]
1394	\|\| !pVM->pgm.s.apHCPaePDs[2]
1395	\|\| !pVM->pgm.s.apHCPaePDs[3]
1396	\|\| !pVM->pgm.s.pHCPaePDPT
1397	\|\| !pVM->pgm.s.pHCNestedRoot)
1398	{
1399	AssertMsgFailed(("Failed to allocate pages for the intermediate context!\n"));
1400	return VERR_NO_PAGE_MEMORY;
1401	}
1402
1403	/* get physical addresses. */
1404	pVM->pgm.s.HCPhys32BitPD = MMPage2Phys(pVM, pVM->pgm.s.pHC32BitPD);
1405	Assert(MMPagePhys2Page(pVM, pVM->pgm.s.HCPhys32BitPD) == pVM->pgm.s.pHC32BitPD);
1406	pVM->pgm.s.aHCPhysPaePDs[0] = MMPage2Phys(pVM, pVM->pgm.s.apHCPaePDs[0]);
1407	pVM->pgm.s.aHCPhysPaePDs[1] = MMPage2Phys(pVM, pVM->pgm.s.apHCPaePDs[1]);
1408	pVM->pgm.s.aHCPhysPaePDs[2] = MMPage2Phys(pVM, pVM->pgm.s.apHCPaePDs[2]);
1409	pVM->pgm.s.aHCPhysPaePDs[3] = MMPage2Phys(pVM, pVM->pgm.s.apHCPaePDs[3]);
1410	pVM->pgm.s.HCPhysPaePDPT = MMPage2Phys(pVM, pVM->pgm.s.pHCPaePDPT);
1411	pVM->pgm.s.HCPhysNestedRoot = MMPage2Phys(pVM, pVM->pgm.s.pHCNestedRoot);
1412
1413	/*
1414	* Initialize the pages, setting up the PML4 and PDPT for action below 4GB.
1415	*/
1416	ASMMemZero32(pVM->pgm.s.pHC32BitPD, PAGE_SIZE);
1417	ASMMemZero32(pVM->pgm.s.pHCPaePDPT, PAGE_SIZE);
1418	ASMMemZero32(pVM->pgm.s.pHCNestedRoot, PAGE_SIZE);
1419	for (unsigned i = 0; i < ELEMENTS(pVM->pgm.s.apHCPaePDs); i++)
1420	{
1421	ASMMemZero32(pVM->pgm.s.apHCPaePDs[i], PAGE_SIZE);
1422	pVM->pgm.s.pHCPaePDPT->a[i].u = X86_PDPE_P \| PGM_PLXFLAGS_PERMANENT \| pVM->pgm.s.aHCPhysPaePDs[i];
1423	/* The flags will be corrected when entering and leaving long mode. */
1424	}
1425
1426	CPUMSetHyperCR3(pVM, (uint32_t)pVM->pgm.s.HCPhys32BitPD);
1427
1428	/*
1429	* Initialize paging workers and mode from current host mode
1430	* and the guest running in real mode.
1431	*/
1432	pVM->pgm.s.enmHostMode = SUPGetPagingMode();
1433	switch (pVM->pgm.s.enmHostMode)
1434	{
1435	case SUPPAGINGMODE_32_BIT:
1436	case SUPPAGINGMODE_32_BIT_GLOBAL:
1437	case SUPPAGINGMODE_PAE:
1438	case SUPPAGINGMODE_PAE_GLOBAL:
1439	case SUPPAGINGMODE_PAE_NX:
1440	case SUPPAGINGMODE_PAE_GLOBAL_NX:
1441	break;
1442
1443	case SUPPAGINGMODE_AMD64:
1444	case SUPPAGINGMODE_AMD64_GLOBAL:
1445	case SUPPAGINGMODE_AMD64_NX:
1446	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
1447	#ifndef VBOX_WITH_HYBIRD_32BIT_KERNEL
1448	if (ARCH_BITS != 64)
1449	{
1450	AssertMsgFailed(("Host mode %d (64-bit) is not supported by non-64bit builds\n", pVM->pgm.s.enmHostMode));
1451	LogRel(("Host mode %d (64-bit) is not supported by non-64bit builds\n", pVM->pgm.s.enmHostMode));
1452	return VERR_PGM_UNSUPPORTED_HOST_PAGING_MODE;
1453	}
1454	#endif
1455	break;
1456	default:
1457	AssertMsgFailed(("Host mode %d is not supported\n", pVM->pgm.s.enmHostMode));
1458	return VERR_PGM_UNSUPPORTED_HOST_PAGING_MODE;
1459	}
1460	rc = pgmR3ModeDataInit(pVM, false /* don't resolve GC and R0 syms yet */);
1461	if (VBOX_SUCCESS(rc))
1462	rc = PGMR3ChangeMode(pVM, PGMMODE_REAL);
1463	if (VBOX_SUCCESS(rc))
1464	{
1465	LogFlow(("pgmR3InitPaging: returns successfully\n"));
1466	#if HC_ARCH_BITS == 64
1467	LogRel(("Debug: HCPhys32BitPD=%VHp aHCPhysPaePDs={%VHp,%VHp,%VHp,%VHp} HCPhysPaePDPT=%VHp HCPhysPaePML4=%VHp\n",
1468	pVM->pgm.s.HCPhys32BitPD, pVM->pgm.s.aHCPhysPaePDs[0], pVM->pgm.s.aHCPhysPaePDs[1], pVM->pgm.s.aHCPhysPaePDs[2], pVM->pgm.s.aHCPhysPaePDs[3],
1469	pVM->pgm.s.HCPhysPaePDPT, pVM->pgm.s.HCPhysPaePML4));
1470	LogRel(("Debug: HCPhysInterPD=%VHp HCPhysInterPaePDPT=%VHp HCPhysInterPaePML4=%VHp\n",
1471	pVM->pgm.s.HCPhysInterPD, pVM->pgm.s.HCPhysInterPaePDPT, pVM->pgm.s.HCPhysInterPaePML4));
1472	LogRel(("Debug: apInterPTs={%VHp,%VHp} apInterPaePTs={%VHp,%VHp} apInterPaePDs={%VHp,%VHp,%VHp,%VHp} pInterPaePDPT64=%VHp\n",
1473	MMPage2Phys(pVM, pVM->pgm.s.apInterPTs[0]), MMPage2Phys(pVM, pVM->pgm.s.apInterPTs[1]),
1474	MMPage2Phys(pVM, pVM->pgm.s.apInterPaePTs[0]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePTs[1]),
1475	MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[0]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[1]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[2]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[3]),
1476	MMPage2Phys(pVM, pVM->pgm.s.pInterPaePDPT64)));
1477	#endif
1478
1479	return VINF_SUCCESS;
1480	}
1481
1482	LogFlow(("pgmR3InitPaging: returns %Vrc\n", rc));
1483	return rc;
1484	}
1485
1486
1487	#ifdef VBOX_WITH_STATISTICS
1488	/**
1489	* Init statistics
1490	*/
1491	static void pgmR3InitStats(PVM pVM)
1492	{
1493	PPGM pPGM = &pVM->pgm.s;
1494	STAM_REG(pVM, &pPGM->StatGCInvalidatePage, STAMTYPE_PROFILE, "/PGM/GC/InvalidatePage", STAMUNIT_TICKS_PER_CALL, "PGMGCInvalidatePage() profiling.");
1495	STAM_REG(pVM, &pPGM->StatGCInvalidatePage4KBPages, STAMTYPE_COUNTER, "/PGM/GC/InvalidatePage/4KBPages", STAMUNIT_OCCURENCES, "The number of times PGMGCInvalidatePage() was called for a 4KB page.");
1496	STAM_REG(pVM, &pPGM->StatGCInvalidatePage4MBPages, STAMTYPE_COUNTER, "/PGM/GC/InvalidatePage/4MBPages", STAMUNIT_OCCURENCES, "The number of times PGMGCInvalidatePage() was called for a 4MB page.");
1497	STAM_REG(pVM, &pPGM->StatGCInvalidatePage4MBPagesSkip, STAMTYPE_COUNTER, "/PGM/GC/InvalidatePage/4MBPagesSkip",STAMUNIT_OCCURENCES, "The number of times PGMGCInvalidatePage() skipped a 4MB page.");
1498	STAM_REG(pVM, &pPGM->StatGCInvalidatePagePDMappings, STAMTYPE_COUNTER, "/PGM/GC/InvalidatePage/PDMappings", STAMUNIT_OCCURENCES, "The number of times PGMGCInvalidatePage() was called for a page directory containing mappings (no conflict).");
1499	STAM_REG(pVM, &pPGM->StatGCInvalidatePagePDNAs, STAMTYPE_COUNTER, "/PGM/GC/InvalidatePage/PDNAs", STAMUNIT_OCCURENCES, "The number of times PGMGCInvalidatePage() was called for a not accessed page directory.");
1500	STAM_REG(pVM, &pPGM->StatGCInvalidatePagePDNPs, STAMTYPE_COUNTER, "/PGM/GC/InvalidatePage/PDNPs", STAMUNIT_OCCURENCES, "The number of times PGMGCInvalidatePage() was called for a not present page directory.");
1501	STAM_REG(pVM, &pPGM->StatGCInvalidatePagePDOutOfSync, STAMTYPE_COUNTER, "/PGM/GC/InvalidatePage/PDOutOfSync", STAMUNIT_OCCURENCES, "The number of times PGMGCInvalidatePage() was called for an out of sync page directory.");
1502	STAM_REG(pVM, &pPGM->StatGCInvalidatePageSkipped, STAMTYPE_COUNTER, "/PGM/GC/InvalidatePage/Skipped", STAMUNIT_OCCURENCES, "The number of times PGMGCInvalidatePage() was skipped due to not present shw or pending pending SyncCR3.");
1503	STAM_REG(pVM, &pPGM->StatGCSyncPT, STAMTYPE_PROFILE, "/PGM/GC/SyncPT", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMGCSyncPT() body.");
1504	STAM_REG(pVM, &pPGM->StatGCAccessedPage, STAMTYPE_COUNTER, "/PGM/GC/AccessedPage", STAMUNIT_OCCURENCES, "The number of pages marked not present for accessed bit emulation.");
1505	STAM_REG(pVM, &pPGM->StatGCDirtyPage, STAMTYPE_COUNTER, "/PGM/GC/DirtyPage/Mark", STAMUNIT_OCCURENCES, "The number of pages marked read-only for dirty bit tracking.");
1506	STAM_REG(pVM, &pPGM->StatGCDirtyPageBig, STAMTYPE_COUNTER, "/PGM/GC/DirtyPage/MarkBig", STAMUNIT_OCCURENCES, "The number of 4MB pages marked read-only for dirty bit tracking.");
1507	STAM_REG(pVM, &pPGM->StatGCDirtyPageTrap, STAMTYPE_COUNTER, "/PGM/GC/DirtyPage/Trap", STAMUNIT_OCCURENCES, "The number of traps generated for dirty bit tracking.");
1508	STAM_REG(pVM, &pPGM->StatGCDirtyPageSkipped, STAMTYPE_COUNTER, "/PGM/GC/DirtyPage/Skipped", STAMUNIT_OCCURENCES, "The number of pages already dirty or readonly.");
1509	STAM_REG(pVM, &pPGM->StatGCDirtiedPage, STAMTYPE_COUNTER, "/PGM/GC/DirtyPage/SetDirty", STAMUNIT_OCCURENCES, "The number of pages marked dirty because of write accesses.");
1510	STAM_REG(pVM, &pPGM->StatGCDirtyTrackRealPF, STAMTYPE_COUNTER, "/PGM/GC/DirtyPage/RealPF", STAMUNIT_OCCURENCES, "The number of real pages faults during dirty bit tracking.");
1511	STAM_REG(pVM, &pPGM->StatGCPageAlreadyDirty, STAMTYPE_COUNTER, "/PGM/GC/DirtyPage/AlreadySet", STAMUNIT_OCCURENCES, "The number of pages already marked dirty because of write accesses.");
1512	STAM_REG(pVM, &pPGM->StatGCDirtyBitTracking, STAMTYPE_PROFILE, "/PGM/GC/DirtyPage", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMTrackDirtyBit() body.");
1513	STAM_REG(pVM, &pPGM->StatGCSyncPTAlloc, STAMTYPE_COUNTER, "/PGM/GC/SyncPT/Alloc", STAMUNIT_OCCURENCES, "The number of times PGMGCSyncPT() needed to allocate page tables.");
1514	STAM_REG(pVM, &pPGM->StatGCSyncPTConflict, STAMTYPE_COUNTER, "/PGM/GC/SyncPT/Conflicts", STAMUNIT_OCCURENCES, "The number of times PGMGCSyncPT() detected conflicts.");
1515	STAM_REG(pVM, &pPGM->StatGCSyncPTFailed, STAMTYPE_COUNTER, "/PGM/GC/SyncPT/Failed", STAMUNIT_OCCURENCES, "The number of times PGMGCSyncPT() failed.");
1516
1517	STAM_REG(pVM, &pPGM->StatGCTrap0e, STAMTYPE_PROFILE, "/PGM/GC/Trap0e", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMGCTrap0eHandler() body.");
1518	STAM_REG(pVM, &pPGM->StatCheckPageFault, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time/CheckPageFault", STAMUNIT_TICKS_PER_CALL, "Profiling of checking for dirty/access emulation faults.");
1519	STAM_REG(pVM, &pPGM->StatLazySyncPT, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time/SyncPT", STAMUNIT_TICKS_PER_CALL, "Profiling of lazy page table syncing.");
1520	STAM_REG(pVM, &pPGM->StatMapping, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time/Mapping", STAMUNIT_TICKS_PER_CALL, "Profiling of checking virtual mappings.");
1521	STAM_REG(pVM, &pPGM->StatOutOfSync, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time/OutOfSync", STAMUNIT_TICKS_PER_CALL, "Profiling of out of sync page handling.");
1522	STAM_REG(pVM, &pPGM->StatHandlers, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time/Handlers", STAMUNIT_TICKS_PER_CALL, "Profiling of checking handlers.");
1523	STAM_REG(pVM, &pPGM->StatEIPHandlers, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time/EIPHandlers", STAMUNIT_TICKS_PER_CALL, "Profiling of checking eip handlers.");
1524	STAM_REG(pVM, &pPGM->StatTrap0eCSAM, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time2/CSAM", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is CSAM.");
1525	STAM_REG(pVM, &pPGM->StatTrap0eDirtyAndAccessedBits, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time2/DirtyAndAccessedBits", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is dirty and/or accessed bit emulation.");
1526	STAM_REG(pVM, &pPGM->StatTrap0eGuestTrap, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time2/GuestTrap", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is a guest trap.");
1527	STAM_REG(pVM, &pPGM->StatTrap0eHndPhys, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time2/HandlerPhysical", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is a physical handler.");
1528	STAM_REG(pVM, &pPGM->StatTrap0eHndVirt, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time2/HandlerVirtual",STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is a virtual handler.");
1529	STAM_REG(pVM, &pPGM->StatTrap0eHndUnhandled, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time2/HandlerUnhandled", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is access outside the monitored areas of a monitored page.");
1530	STAM_REG(pVM, &pPGM->StatTrap0eMisc, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time2/Misc", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is not known.");
1531	STAM_REG(pVM, &pPGM->StatTrap0eOutOfSync, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time2/OutOfSync", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is an out-of-sync page.");
1532	STAM_REG(pVM, &pPGM->StatTrap0eOutOfSyncHndPhys, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time2/OutOfSyncHndPhys", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is an out-of-sync physical handler page.");
1533	STAM_REG(pVM, &pPGM->StatTrap0eOutOfSyncHndVirt, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time2/OutOfSyncHndVirt", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is an out-of-sync virtual handler page.");
1534	STAM_REG(pVM, &pPGM->StatTrap0eOutOfSyncObsHnd, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time2/OutOfSyncObsHnd", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is an obsolete handler page.");
1535	STAM_REG(pVM, &pPGM->StatTrap0eSyncPT, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time2/SyncPT", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is lazy syncing of a PT.");
1536
1537	STAM_REG(pVM, &pPGM->StatTrap0eMapHandler, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/Handlers/Mapping", STAMUNIT_OCCURENCES, "Number of traps due to access handlers in mappings.");
1538	STAM_REG(pVM, &pPGM->StatHandlersOutOfSync, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/Handlers/OutOfSync", STAMUNIT_OCCURENCES, "Number of traps due to out-of-sync handled pages.");
1539	STAM_REG(pVM, &pPGM->StatHandlersPhysical, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/Handlers/Physical", STAMUNIT_OCCURENCES, "Number of traps due to physical access handlers.");
1540	STAM_REG(pVM, &pPGM->StatHandlersVirtual, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/Handlers/Virtual", STAMUNIT_OCCURENCES, "Number of traps due to virtual access handlers.");
1541	STAM_REG(pVM, &pPGM->StatHandlersVirtualByPhys, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/Handlers/VirtualByPhys", STAMUNIT_OCCURENCES, "Number of traps due to virtual access handlers by physical address.");
1542	STAM_REG(pVM, &pPGM->StatHandlersVirtualUnmarked, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/Handlers/VirtualUnmarked", STAMUNIT_OCCURENCES,"Number of traps due to virtual access handlers by virtual address (without proper physical flags).");
1543	STAM_REG(pVM, &pPGM->StatHandlersUnhandled, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/Handlers/Unhandled", STAMUNIT_OCCURENCES, "Number of traps due to access outside range of monitored page(s).");
1544	STAM_REG(pVM, &pPGM->StatHandlersInvalid, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/Handlers/Invalid", STAMUNIT_OCCURENCES, "Number of traps due to access to invalid physical memory.");
1545
1546	STAM_REG(pVM, &pPGM->StatGCTrap0eConflicts, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/Conflicts", STAMUNIT_OCCURENCES, "The number of times #PF was caused by an undetected conflict.");
1547	STAM_REG(pVM, &pPGM->StatGCTrap0eUSNotPresentRead, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/User/NPRead", STAMUNIT_OCCURENCES, "Number of user mode not present read page faults.");
1548	STAM_REG(pVM, &pPGM->StatGCTrap0eUSNotPresentWrite, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/User/NPWrite", STAMUNIT_OCCURENCES, "Number of user mode not present write page faults.");
1549	STAM_REG(pVM, &pPGM->StatGCTrap0eUSWrite, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/User/Write", STAMUNIT_OCCURENCES, "Number of user mode write page faults.");
1550	STAM_REG(pVM, &pPGM->StatGCTrap0eUSReserved, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/User/Reserved", STAMUNIT_OCCURENCES, "Number of user mode reserved bit page faults.");
1551	STAM_REG(pVM, &pPGM->StatGCTrap0eUSNXE, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/User/NXE", STAMUNIT_OCCURENCES, "Number of user mode NXE page faults.");
1552	STAM_REG(pVM, &pPGM->StatGCTrap0eUSRead, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/User/Read", STAMUNIT_OCCURENCES, "Number of user mode read page faults.");
1553
1554	STAM_REG(pVM, &pPGM->StatGCTrap0eSVNotPresentRead, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/Supervisor/NPRead", STAMUNIT_OCCURENCES, "Number of supervisor mode not present read page faults.");
1555	STAM_REG(pVM, &pPGM->StatGCTrap0eSVNotPresentWrite, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/Supervisor/NPWrite", STAMUNIT_OCCURENCES, "Number of supervisor mode not present write page faults.");
1556	STAM_REG(pVM, &pPGM->StatGCTrap0eSVWrite, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/Supervisor/Write", STAMUNIT_OCCURENCES, "Number of supervisor mode write page faults.");
1557	STAM_REG(pVM, &pPGM->StatGCTrap0eSVReserved, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/Supervisor/Reserved", STAMUNIT_OCCURENCES, "Number of supervisor mode reserved bit page faults.");
1558	STAM_REG(pVM, &pPGM->StatGCTrap0eSNXE, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/Supervisor/NXE", STAMUNIT_OCCURENCES, "Number of supervisor mode NXE page faults.");
1559	STAM_REG(pVM, &pPGM->StatGCTrap0eUnhandled, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/GuestPF/Unhandled", STAMUNIT_OCCURENCES, "Number of guest real page faults.");
1560	STAM_REG(pVM, &pPGM->StatGCTrap0eMap, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/GuestPF/Map", STAMUNIT_OCCURENCES, "Number of guest page faults due to map accesses.");
1561
1562	STAM_REG(pVM, &pPGM->StatTrap0eWPEmulGC, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/WP/InGC", STAMUNIT_OCCURENCES, "Number of guest page faults due to X86_CR0_WP emulation.");
1563	STAM_REG(pVM, &pPGM->StatTrap0eWPEmulR3, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/WP/ToR3", STAMUNIT_OCCURENCES, "Number of guest page faults due to X86_CR0_WP emulation (forward to R3 for emulation).");
1564
1565	STAM_REG(pVM, &pPGM->StatGCGuestCR3WriteHandled, STAMTYPE_COUNTER, "/PGM/GC/CR3WriteInt", STAMUNIT_OCCURENCES, "The number of times the Guest CR3 change was successfully handled.");
1566	STAM_REG(pVM, &pPGM->StatGCGuestCR3WriteUnhandled, STAMTYPE_COUNTER, "/PGM/GC/CR3WriteEmu", STAMUNIT_OCCURENCES, "The number of times the Guest CR3 change was passed back to the recompiler.");
1567	STAM_REG(pVM, &pPGM->StatGCGuestCR3WriteConflict, STAMTYPE_COUNTER, "/PGM/GC/CR3WriteConflict", STAMUNIT_OCCURENCES, "The number of times the Guest CR3 monitoring detected a conflict.");
1568
1569	STAM_REG(pVM, &pPGM->StatGCPageOutOfSyncSupervisor, STAMTYPE_COUNTER, "/PGM/GC/OutOfSync/SuperVisor", STAMUNIT_OCCURENCES, "Number of traps due to pages out of sync.");
1570	STAM_REG(pVM, &pPGM->StatGCPageOutOfSyncUser, STAMTYPE_COUNTER, "/PGM/GC/OutOfSync/User", STAMUNIT_OCCURENCES, "Number of traps due to pages out of sync.");
1571
1572	STAM_REG(pVM, &pPGM->StatGCGuestROMWriteHandled, STAMTYPE_COUNTER, "/PGM/GC/ROMWriteInt", STAMUNIT_OCCURENCES, "The number of times the Guest ROM change was successfully handled.");
1573	STAM_REG(pVM, &pPGM->StatGCGuestROMWriteUnhandled, STAMTYPE_COUNTER, "/PGM/GC/ROMWriteEmu", STAMUNIT_OCCURENCES, "The number of times the Guest ROM change was passed back to the recompiler.");
1574
1575	STAM_REG(pVM, &pPGM->StatDynMapCacheHits, STAMTYPE_COUNTER, "/PGM/GC/DynMapCache/Hits" , STAMUNIT_OCCURENCES, "Number of dynamic page mapping cache hits.");
1576	STAM_REG(pVM, &pPGM->StatDynMapCacheMisses, STAMTYPE_COUNTER, "/PGM/GC/DynMapCache/Misses" , STAMUNIT_OCCURENCES, "Number of dynamic page mapping cache misses.");
1577
1578	STAM_REG(pVM, &pPGM->StatHCDetectedConflicts, STAMTYPE_COUNTER, "/PGM/HC/DetectedConflicts", STAMUNIT_OCCURENCES, "The number of times PGMR3CheckMappingConflicts() detected a conflict.");
1579	STAM_REG(pVM, &pPGM->StatHCGuestPDWrite, STAMTYPE_COUNTER, "/PGM/HC/PDWrite", STAMUNIT_OCCURENCES, "The total number of times pgmHCGuestPDWriteHandler() was called.");
1580	STAM_REG(pVM, &pPGM->StatHCGuestPDWriteConflict, STAMTYPE_COUNTER, "/PGM/HC/PDWriteConflict", STAMUNIT_OCCURENCES, "The number of times pgmHCGuestPDWriteHandler() detected a conflict.");
1581
1582	STAM_REG(pVM, &pPGM->StatHCInvalidatePage, STAMTYPE_PROFILE, "/PGM/HC/InvalidatePage", STAMUNIT_TICKS_PER_CALL, "PGMHCInvalidatePage() profiling.");
1583	STAM_REG(pVM, &pPGM->StatHCInvalidatePage4KBPages, STAMTYPE_COUNTER, "/PGM/HC/InvalidatePage/4KBPages", STAMUNIT_OCCURENCES, "The number of times PGMHCInvalidatePage() was called for a 4KB page.");
1584	STAM_REG(pVM, &pPGM->StatHCInvalidatePage4MBPages, STAMTYPE_COUNTER, "/PGM/HC/InvalidatePage/4MBPages", STAMUNIT_OCCURENCES, "The number of times PGMHCInvalidatePage() was called for a 4MB page.");
1585	STAM_REG(pVM, &pPGM->StatHCInvalidatePage4MBPagesSkip, STAMTYPE_COUNTER, "/PGM/HC/InvalidatePage/4MBPagesSkip",STAMUNIT_OCCURENCES, "The number of times PGMHCInvalidatePage() skipped a 4MB page.");
1586	STAM_REG(pVM, &pPGM->StatHCInvalidatePagePDMappings, STAMTYPE_COUNTER, "/PGM/HC/InvalidatePage/PDMappings", STAMUNIT_OCCURENCES, "The number of times PGMHCInvalidatePage() was called for a page directory containing mappings (no conflict).");
1587	STAM_REG(pVM, &pPGM->StatHCInvalidatePagePDNAs, STAMTYPE_COUNTER, "/PGM/HC/InvalidatePage/PDNAs", STAMUNIT_OCCURENCES, "The number of times PGMHCInvalidatePage() was called for a not accessed page directory.");
1588	STAM_REG(pVM, &pPGM->StatHCInvalidatePagePDNPs, STAMTYPE_COUNTER, "/PGM/HC/InvalidatePage/PDNPs", STAMUNIT_OCCURENCES, "The number of times PGMHCInvalidatePage() was called for a not present page directory.");
1589	STAM_REG(pVM, &pPGM->StatHCInvalidatePagePDOutOfSync, STAMTYPE_COUNTER, "/PGM/HC/InvalidatePage/PDOutOfSync", STAMUNIT_OCCURENCES, "The number of times PGMGCInvalidatePage() was called for an out of sync page directory.");
1590	STAM_REG(pVM, &pPGM->StatHCInvalidatePageSkipped, STAMTYPE_COUNTER, "/PGM/HC/InvalidatePage/Skipped", STAMUNIT_OCCURENCES, "The number of times PGMHCInvalidatePage() was skipped due to not present shw or pending pending SyncCR3.");
1591	STAM_REG(pVM, &pPGM->StatHCResolveConflict, STAMTYPE_PROFILE, "/PGM/HC/ResolveConflict", STAMUNIT_TICKS_PER_CALL, "pgmR3SyncPTResolveConflict() profiling (includes the entire relocation).");
1592	STAM_REG(pVM, &pPGM->StatHCPrefetch, STAMTYPE_PROFILE, "/PGM/HC/Prefetch", STAMUNIT_TICKS_PER_CALL, "PGMR3PrefetchPage profiling.");
1593
1594	STAM_REG(pVM, &pPGM->StatHCSyncPT, STAMTYPE_PROFILE, "/PGM/HC/SyncPT", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMR3SyncPT() body.");
1595	STAM_REG(pVM, &pPGM->StatHCAccessedPage, STAMTYPE_COUNTER, "/PGM/HC/AccessedPage", STAMUNIT_OCCURENCES, "The number of pages marked not present for accessed bit emulation.");
1596	STAM_REG(pVM, &pPGM->StatHCDirtyPage, STAMTYPE_COUNTER, "/PGM/HC/DirtyPage/Mark", STAMUNIT_OCCURENCES, "The number of pages marked read-only for dirty bit tracking.");
1597	STAM_REG(pVM, &pPGM->StatHCDirtyPageBig, STAMTYPE_COUNTER, "/PGM/HC/DirtyPage/MarkBig", STAMUNIT_OCCURENCES, "The number of 4MB pages marked read-only for dirty bit tracking.");
1598	STAM_REG(pVM, &pPGM->StatHCDirtyPageTrap, STAMTYPE_COUNTER, "/PGM/HC/DirtyPage/Trap", STAMUNIT_OCCURENCES, "The number of traps generated for dirty bit tracking.");
1599	STAM_REG(pVM, &pPGM->StatHCDirtyPageSkipped, STAMTYPE_COUNTER, "/PGM/HC/DirtyPage/Skipped", STAMUNIT_OCCURENCES, "The number of pages already dirty or readonly.");
1600	STAM_REG(pVM, &pPGM->StatHCDirtyBitTracking, STAMTYPE_PROFILE, "/PGM/HC/DirtyPage", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMTrackDirtyBit() body.");
1601
1602	STAM_REG(pVM, &pPGM->StatGCSyncPagePDNAs, STAMTYPE_COUNTER, "/PGM/GC/SyncPagePDNAs", STAMUNIT_OCCURENCES, "The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit.");
1603	STAM_REG(pVM, &pPGM->StatGCSyncPagePDOutOfSync, STAMTYPE_COUNTER, "/PGM/GC/SyncPagePDOutOfSync", STAMUNIT_OCCURENCES, "The number of time we've encountered an out-of-sync PD in SyncPage.");
1604	STAM_REG(pVM, &pPGM->StatHCSyncPagePDNAs, STAMTYPE_COUNTER, "/PGM/HC/SyncPagePDNAs", STAMUNIT_OCCURENCES, "The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit.");
1605	STAM_REG(pVM, &pPGM->StatHCSyncPagePDOutOfSync, STAMTYPE_COUNTER, "/PGM/HC/SyncPagePDOutOfSync", STAMUNIT_OCCURENCES, "The number of time we've encountered an out-of-sync PD in SyncPage.");
1606
1607	STAM_REG(pVM, &pPGM->StatFlushTLB, STAMTYPE_PROFILE, "/PGM/FlushTLB", STAMUNIT_OCCURENCES, "Profiling of the PGMFlushTLB() body.");
1608	STAM_REG(pVM, &pPGM->StatFlushTLBNewCR3, STAMTYPE_COUNTER, "/PGM/FlushTLB/NewCR3", STAMUNIT_OCCURENCES, "The number of times PGMFlushTLB was called with a new CR3, non-global. (switch)");
1609	STAM_REG(pVM, &pPGM->StatFlushTLBNewCR3Global, STAMTYPE_COUNTER, "/PGM/FlushTLB/NewCR3Global", STAMUNIT_OCCURENCES, "The number of times PGMFlushTLB was called with a new CR3, global. (switch)");
1610	STAM_REG(pVM, &pPGM->StatFlushTLBSameCR3, STAMTYPE_COUNTER, "/PGM/FlushTLB/SameCR3", STAMUNIT_OCCURENCES, "The number of times PGMFlushTLB was called with the same CR3, non-global. (flush)");
1611	STAM_REG(pVM, &pPGM->StatFlushTLBSameCR3Global, STAMTYPE_COUNTER, "/PGM/FlushTLB/SameCR3Global", STAMUNIT_OCCURENCES, "The number of times PGMFlushTLB was called with the same CR3, global. (flush)");
1612
1613	STAM_REG(pVM, &pPGM->StatGCSyncCR3, STAMTYPE_PROFILE, "/PGM/GC/SyncCR3", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMSyncCR3() body.");
1614	STAM_REG(pVM, &pPGM->StatGCSyncCR3Handlers, STAMTYPE_PROFILE, "/PGM/GC/SyncCR3/Handlers", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMSyncCR3() update handler section.");
1615	STAM_REG(pVM, &pPGM->StatGCSyncCR3HandlerVirtualUpdate, STAMTYPE_PROFILE, "/PGM/GC/SyncCR3/Handlers/VirtualUpdate",STAMUNIT_TICKS_PER_CALL, "Profiling of the virtual handler updates.");
1616	STAM_REG(pVM, &pPGM->StatGCSyncCR3HandlerVirtualReset, STAMTYPE_PROFILE, "/PGM/GC/SyncCR3/Handlers/VirtualReset", STAMUNIT_TICKS_PER_CALL, "Profiling of the virtual handler resets.");
1617	STAM_REG(pVM, &pPGM->StatGCSyncCR3Global, STAMTYPE_COUNTER, "/PGM/GC/SyncCR3/Global", STAMUNIT_OCCURENCES, "The number of global CR3 syncs.");
1618	STAM_REG(pVM, &pPGM->StatGCSyncCR3NotGlobal, STAMTYPE_COUNTER, "/PGM/GC/SyncCR3/NotGlobal", STAMUNIT_OCCURENCES, "The number of non-global CR3 syncs.");
1619	STAM_REG(pVM, &pPGM->StatGCSyncCR3DstCacheHit, STAMTYPE_COUNTER, "/PGM/GC/SyncCR3/DstChacheHit", STAMUNIT_OCCURENCES, "The number of times we got some kind of a cache hit.");
1620	STAM_REG(pVM, &pPGM->StatGCSyncCR3DstFreed, STAMTYPE_COUNTER, "/PGM/GC/SyncCR3/DstFreed", STAMUNIT_OCCURENCES, "The number of times we've had to free a shadow entry.");
1621	STAM_REG(pVM, &pPGM->StatGCSyncCR3DstFreedSrcNP, STAMTYPE_COUNTER, "/PGM/GC/SyncCR3/DstFreedSrcNP", STAMUNIT_OCCURENCES, "The number of times we've had to free a shadow entry for which the source entry was not present.");
1622	STAM_REG(pVM, &pPGM->StatGCSyncCR3DstNotPresent, STAMTYPE_COUNTER, "/PGM/GC/SyncCR3/DstNotPresent", STAMUNIT_OCCURENCES, "The number of times we've encountered a not present shadow entry for a present guest entry.");
1623	STAM_REG(pVM, &pPGM->StatGCSyncCR3DstSkippedGlobalPD, STAMTYPE_COUNTER, "/PGM/GC/SyncCR3/DstSkippedGlobalPD", STAMUNIT_OCCURENCES, "The number of times a global page directory wasn't flushed.");
1624	STAM_REG(pVM, &pPGM->StatGCSyncCR3DstSkippedGlobalPT, STAMTYPE_COUNTER, "/PGM/GC/SyncCR3/DstSkippedGlobalPT", STAMUNIT_OCCURENCES, "The number of times a page table with only global entries wasn't flushed.");
1625
1626	STAM_REG(pVM, &pPGM->StatHCSyncCR3, STAMTYPE_PROFILE, "/PGM/HC/SyncCR3", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMSyncCR3() body.");
1627	STAM_REG(pVM, &pPGM->StatHCSyncCR3Handlers, STAMTYPE_PROFILE, "/PGM/HC/SyncCR3/Handlers", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMSyncCR3() update handler section.");
1628	STAM_REG(pVM, &pPGM->StatHCSyncCR3HandlerVirtualUpdate, STAMTYPE_PROFILE, "/PGM/HC/SyncCR3/Handlers/VirtualUpdate",STAMUNIT_TICKS_PER_CALL, "Profiling of the virtual handler updates.");
1629	STAM_REG(pVM, &pPGM->StatHCSyncCR3HandlerVirtualReset, STAMTYPE_PROFILE, "/PGM/HC/SyncCR3/Handlers/VirtualReset", STAMUNIT_TICKS_PER_CALL, "Profiling of the virtual handler resets.");
1630	STAM_REG(pVM, &pPGM->StatHCSyncCR3Global, STAMTYPE_COUNTER, "/PGM/HC/SyncCR3/Global", STAMUNIT_OCCURENCES, "The number of global CR3 syncs.");
1631	STAM_REG(pVM, &pPGM->StatHCSyncCR3NotGlobal, STAMTYPE_COUNTER, "/PGM/HC/SyncCR3/NotGlobal", STAMUNIT_OCCURENCES, "The number of non-global CR3 syncs.");
1632	STAM_REG(pVM, &pPGM->StatHCSyncCR3DstCacheHit, STAMTYPE_COUNTER, "/PGM/HC/SyncCR3/DstChacheHit", STAMUNIT_OCCURENCES, "The number of times we got some kind of a cache hit.");
1633	STAM_REG(pVM, &pPGM->StatHCSyncCR3DstFreed, STAMTYPE_COUNTER, "/PGM/HC/SyncCR3/DstFreed", STAMUNIT_OCCURENCES, "The number of times we've had to free a shadow entry.");
1634	STAM_REG(pVM, &pPGM->StatHCSyncCR3DstFreedSrcNP, STAMTYPE_COUNTER, "/PGM/HC/SyncCR3/DstFreedSrcNP", STAMUNIT_OCCURENCES, "The number of times we've had to free a shadow entry for which the source entry was not present.");
1635	STAM_REG(pVM, &pPGM->StatHCSyncCR3DstNotPresent, STAMTYPE_COUNTER, "/PGM/HC/SyncCR3/DstNotPresent", STAMUNIT_OCCURENCES, "The number of times we've encountered a not present shadow entry for a present guest entry.");
1636	STAM_REG(pVM, &pPGM->StatHCSyncCR3DstSkippedGlobalPD, STAMTYPE_COUNTER, "/PGM/HC/SyncCR3/DstSkippedGlobalPD", STAMUNIT_OCCURENCES, "The number of times a global page directory wasn't flushed.");
1637	STAM_REG(pVM, &pPGM->StatHCSyncCR3DstSkippedGlobalPT, STAMTYPE_COUNTER, "/PGM/HC/SyncCR3/DstSkippedGlobalPT", STAMUNIT_OCCURENCES, "The number of times a page table with only global entries wasn't flushed.");
1638
1639	STAM_REG(pVM, &pPGM->StatVirtHandleSearchByPhysGC, STAMTYPE_PROFILE, "/PGM/VirtHandler/SearchByPhys/GC", STAMUNIT_TICKS_PER_CALL, "Profiling of pgmHandlerVirtualFindByPhysAddr in GC.");
1640	STAM_REG(pVM, &pPGM->StatVirtHandleSearchByPhysHC, STAMTYPE_PROFILE, "/PGM/VirtHandler/SearchByPhys/HC", STAMUNIT_TICKS_PER_CALL, "Profiling of pgmHandlerVirtualFindByPhysAddr in HC.");
1641	STAM_REG(pVM, &pPGM->StatHandlePhysicalReset, STAMTYPE_COUNTER, "/PGM/HC/HandlerPhysicalReset", STAMUNIT_OCCURENCES, "The number of times PGMR3HandlerPhysicalReset is called.");
1642
1643	STAM_REG(pVM, &pPGM->StatHCGstModifyPage, STAMTYPE_PROFILE, "/PGM/HC/GstModifyPage", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMGstModifyPage() body.");
1644	STAM_REG(pVM, &pPGM->StatGCGstModifyPage, STAMTYPE_PROFILE, "/PGM/GC/GstModifyPage", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMGstModifyPage() body.");
1645
1646	STAM_REG(pVM, &pPGM->StatSynPT4kGC, STAMTYPE_COUNTER, "/PGM/GC/SyncPT/4k", STAMUNIT_OCCURENCES, "Nr of 4k PT syncs");
1647	STAM_REG(pVM, &pPGM->StatSynPT4kHC, STAMTYPE_COUNTER, "/PGM/HC/SyncPT/4k", STAMUNIT_OCCURENCES, "Nr of 4k PT syncs");
1648	STAM_REG(pVM, &pPGM->StatSynPT4MGC, STAMTYPE_COUNTER, "/PGM/GC/SyncPT/4M", STAMUNIT_OCCURENCES, "Nr of 4M PT syncs");
1649	STAM_REG(pVM, &pPGM->StatSynPT4MHC, STAMTYPE_COUNTER, "/PGM/HC/SyncPT/4M", STAMUNIT_OCCURENCES, "Nr of 4M PT syncs");
1650
1651	STAM_REG(pVM, &pPGM->StatDynRamTotal, STAMTYPE_COUNTER, "/PGM/RAM/TotalAlloc", STAMUNIT_MEGABYTES, "Allocated mbs of guest ram.");
1652	STAM_REG(pVM, &pPGM->StatDynRamGrow, STAMTYPE_COUNTER, "/PGM/RAM/Grow", STAMUNIT_OCCURENCES, "Nr of pgmr3PhysGrowRange calls.");
1653
1654	STAM_REG(pVM, &pPGM->StatPageHCMapTlbHits, STAMTYPE_COUNTER, "/PGM/PageHCMap/TlbHits", STAMUNIT_OCCURENCES, "TLB hits.");
1655	STAM_REG(pVM, &pPGM->StatPageHCMapTlbMisses, STAMTYPE_COUNTER, "/PGM/PageHCMap/TlbMisses", STAMUNIT_OCCURENCES, "TLB misses.");
1656	STAM_REG(pVM, &pPGM->ChunkR3Map.c, STAMTYPE_U32, "/PGM/ChunkR3Map/c", STAMUNIT_OCCURENCES, "Number of mapped chunks.");
1657	STAM_REG(pVM, &pPGM->ChunkR3Map.cMax, STAMTYPE_U32, "/PGM/ChunkR3Map/cMax", STAMUNIT_OCCURENCES, "Maximum number of mapped chunks.");
1658	STAM_REG(pVM, &pPGM->StatChunkR3MapTlbHits, STAMTYPE_COUNTER, "/PGM/ChunkR3Map/TlbHits", STAMUNIT_OCCURENCES, "TLB hits.");
1659	STAM_REG(pVM, &pPGM->StatChunkR3MapTlbMisses, STAMTYPE_COUNTER, "/PGM/ChunkR3Map/TlbMisses", STAMUNIT_OCCURENCES, "TLB misses.");
1660	STAM_REG(pVM, &pPGM->StatPageReplaceShared, STAMTYPE_COUNTER, "/PGM/Page/ReplacedShared", STAMUNIT_OCCURENCES, "Times a shared page was replaced.");
1661	STAM_REG(pVM, &pPGM->StatPageReplaceZero, STAMTYPE_COUNTER, "/PGM/Page/ReplacedZero", STAMUNIT_OCCURENCES, "Times the zero page was replaced.");
1662	STAM_REG(pVM, &pPGM->StatPageHandyAllocs, STAMTYPE_COUNTER, "/PGM/Page/HandyAllocs", STAMUNIT_OCCURENCES, "Number of times we've allocated more handy pages.");
1663	STAM_REG(pVM, &pPGM->cAllPages, STAMTYPE_U32, "/PGM/Page/cAllPages", STAMUNIT_OCCURENCES, "The total number of pages.");
1664	STAM_REG(pVM, &pPGM->cPrivatePages, STAMTYPE_U32, "/PGM/Page/cPrivatePages", STAMUNIT_OCCURENCES, "The number of private pages.");
1665	STAM_REG(pVM, &pPGM->cSharedPages, STAMTYPE_U32, "/PGM/Page/cSharedPages", STAMUNIT_OCCURENCES, "The number of shared pages.");
1666	STAM_REG(pVM, &pPGM->cZeroPages, STAMTYPE_U32, "/PGM/Page/cZeroPages", STAMUNIT_OCCURENCES, "The number of zero backed pages.");
1667
1668	#ifdef PGMPOOL_WITH_GCPHYS_TRACKING
1669	STAM_REG(pVM, &pPGM->StatTrackVirgin, STAMTYPE_COUNTER, "/PGM/Track/Virgin", STAMUNIT_OCCURENCES, "The number of first time shadowings");
1670	STAM_REG(pVM, &pPGM->StatTrackAliased, STAMTYPE_COUNTER, "/PGM/Track/Aliased", STAMUNIT_OCCURENCES, "The number of times switching to cRef2, i.e. the page is being shadowed by two PTs.");
1671	STAM_REG(pVM, &pPGM->StatTrackAliasedMany, STAMTYPE_COUNTER, "/PGM/Track/AliasedMany", STAMUNIT_OCCURENCES, "The number of times we're tracking using cRef2.");
1672	STAM_REG(pVM, &pPGM->StatTrackAliasedLots, STAMTYPE_COUNTER, "/PGM/Track/AliasedLots", STAMUNIT_OCCURENCES, "The number of times we're hitting pages which has overflowed cRef2");
1673	STAM_REG(pVM, &pPGM->StatTrackOverflows, STAMTYPE_COUNTER, "/PGM/Track/Overflows", STAMUNIT_OCCURENCES, "The number of times the extent list grows to long.");
1674	STAM_REG(pVM, &pPGM->StatTrackDeref, STAMTYPE_PROFILE, "/PGM/Track/Deref", STAMUNIT_OCCURENCES, "Profiling of SyncPageWorkerTrackDeref (expensive).");
1675	#endif
1676
1677	for (unsigned i = 0; i < X86_PG_ENTRIES; i++)
1678	{
1679	/** @todo r=bird: We need a STAMR3RegisterF()! */
1680	char szName[32];
1681
1682	RTStrPrintf(szName, sizeof(szName), "/PGM/GC/PD/Trap0e/%04X", i);
1683	int rc = STAMR3Register(pVM, &pPGM->StatGCTrap0ePD[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, szName, STAMUNIT_OCCURENCES, "The number of traps in page directory n.");
1684	AssertRC(rc);
1685
1686	RTStrPrintf(szName, sizeof(szName), "/PGM/GC/PD/SyncPt/%04X", i);
1687	rc = STAMR3Register(pVM, &pPGM->StatGCSyncPtPD[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, szName, STAMUNIT_OCCURENCES, "The number of syncs per PD n.");
1688	AssertRC(rc);
1689
1690	RTStrPrintf(szName, sizeof(szName), "/PGM/GC/PD/SyncPage/%04X", i);
1691	rc = STAMR3Register(pVM, &pPGM->StatGCSyncPagePD[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, szName, STAMUNIT_OCCURENCES, "The number of out of sync pages per page directory n.");
1692	AssertRC(rc);
1693	}
1694	}
1695	#endif /* VBOX_WITH_STATISTICS */
1696
1697	/**
1698	* Init the PGM bits that rely on VMMR0 and MM to be fully initialized.
1699	*
1700	* The dynamic mapping area will also be allocated and initialized at this
1701	* time. We could allocate it during PGMR3Init of course, but the mapping
1702	* wouldn't be allocated at that time preventing us from setting up the
1703	* page table entries with the dummy page.
1704	*
1705	* @returns VBox status code.
1706	* @param pVM VM handle.
1707	*/
1708	PGMR3DECL(int) PGMR3InitDynMap(PVM pVM)
1709	{
1710	RTGCPTR GCPtr;
1711	/*
1712	* Reserve space for mapping the paging pages into guest context.
1713	*/
1714	int rc = MMR3HyperReserve(pVM, PAGE_SIZE * (2 + ELEMENTS(pVM->pgm.s.apHCPaePDs) + 1 + 2 + 2), "Paging", &GCPtr);
1715	AssertRCReturn(rc, rc);
1716	pVM->pgm.s.pGC32BitPD = GCPtr;
1717	MMR3HyperReserve(pVM, PAGE_SIZE, "fence", NULL);
1718
1719	/*
1720	* Reserve space for the dynamic mappings.
1721	*/
1722	/** @todo r=bird: Need to verify that the checks for crossing PTs are correct here. They seems to be assuming 4MB PTs.. */
1723	rc = MMR3HyperReserve(pVM, MM_HYPER_DYNAMIC_SIZE, "Dynamic mapping", &GCPtr);
1724	if (VBOX_SUCCESS(rc))
1725	pVM->pgm.s.pbDynPageMapBaseGC = GCPtr;
1726
1727	if ( VBOX_SUCCESS(rc)
1728	&& (pVM->pgm.s.pbDynPageMapBaseGC >> X86_PD_SHIFT) != ((pVM->pgm.s.pbDynPageMapBaseGC + MM_HYPER_DYNAMIC_SIZE - 1) >> X86_PD_SHIFT))
1729	{
1730	rc = MMR3HyperReserve(pVM, MM_HYPER_DYNAMIC_SIZE, "Dynamic mapping not crossing", &GCPtr);
1731	if (VBOX_SUCCESS(rc))
1732	pVM->pgm.s.pbDynPageMapBaseGC = GCPtr;
1733	}
1734	if (VBOX_SUCCESS(rc))
1735	{
1736	AssertRelease((pVM->pgm.s.pbDynPageMapBaseGC >> X86_PD_SHIFT) == ((pVM->pgm.s.pbDynPageMapBaseGC + MM_HYPER_DYNAMIC_SIZE - 1) >> X86_PD_SHIFT));
1737	MMR3HyperReserve(pVM, PAGE_SIZE, "fence", NULL);
1738	}
1739	return rc;
1740	}
1741
1742
1743	/**
1744	* Ring-3 init finalizing.
1745	*
1746	* @returns VBox status code.
1747	* @param pVM The VM handle.
1748	*/
1749	PGMR3DECL(int) PGMR3InitFinalize(PVM pVM)
1750	{
1751	/*
1752	* Map the paging pages into the guest context.
1753	*/
1754	RTGCPTR GCPtr = pVM->pgm.s.pGC32BitPD;
1755	AssertReleaseReturn(GCPtr, VERR_INTERNAL_ERROR);
1756
1757	int rc = PGMMap(pVM, GCPtr, pVM->pgm.s.HCPhys32BitPD, PAGE_SIZE, 0);
1758	AssertRCReturn(rc, rc);
1759	pVM->pgm.s.pGC32BitPD = GCPtr;
1760	GCPtr += PAGE_SIZE;
1761	GCPtr += PAGE_SIZE; /* reserved page */
1762
1763	for (unsigned i = 0; i < ELEMENTS(pVM->pgm.s.apHCPaePDs); i++)
1764	{
1765	rc = PGMMap(pVM, GCPtr, pVM->pgm.s.aHCPhysPaePDs[i], PAGE_SIZE, 0);
1766	AssertRCReturn(rc, rc);
1767	pVM->pgm.s.apGCPaePDs[i] = GCPtr;
1768	GCPtr += PAGE_SIZE;
1769	}
1770	/* A bit of paranoia is justified. */
1771	AssertRelease((RTGCUINTPTR)pVM->pgm.s.apGCPaePDs[0] + PAGE_SIZE == (RTGCUINTPTR)pVM->pgm.s.apGCPaePDs[1]);
1772	AssertRelease((RTGCUINTPTR)pVM->pgm.s.apGCPaePDs[1] + PAGE_SIZE == (RTGCUINTPTR)pVM->pgm.s.apGCPaePDs[2]);
1773	AssertRelease((RTGCUINTPTR)pVM->pgm.s.apGCPaePDs[2] + PAGE_SIZE == (RTGCUINTPTR)pVM->pgm.s.apGCPaePDs[3]);
1774	GCPtr += PAGE_SIZE; /* reserved page */
1775
1776	rc = PGMMap(pVM, GCPtr, pVM->pgm.s.HCPhysPaePDPT, PAGE_SIZE, 0);
1777	AssertRCReturn(rc, rc);
1778	pVM->pgm.s.pGCPaePDPT = GCPtr;
1779	GCPtr += PAGE_SIZE;
1780	GCPtr += PAGE_SIZE; /* reserved page */
1781
1782
1783	/*
1784	* Reserve space for the dynamic mappings.
1785	* Initialize the dynamic mapping pages with dummy pages to simply the cache.
1786	*/
1787	/* get the pointer to the page table entries. */
1788	PPGMMAPPING pMapping = pgmGetMapping(pVM, pVM->pgm.s.pbDynPageMapBaseGC);
1789	AssertRelease(pMapping);
1790	const uintptr_t off = pVM->pgm.s.pbDynPageMapBaseGC - pMapping->GCPtr;
1791	const unsigned iPT = off >> X86_PD_SHIFT;
1792	const unsigned iPG = (off >> X86_PT_SHIFT) & X86_PT_MASK;
1793	pVM->pgm.s.paDynPageMap32BitPTEsGC = pMapping->aPTs[iPT].pPTGC + iPG * sizeof(pMapping->aPTs[0].pPTR3->a[0]);
1794	pVM->pgm.s.paDynPageMapPaePTEsGC = pMapping->aPTs[iPT].paPaePTsGC + iPG * sizeof(pMapping->aPTs[0].paPaePTsR3->a[0]);
1795
1796	/* init cache */
1797	RTHCPHYS HCPhysDummy = MMR3PageDummyHCPhys(pVM);
1798	for (unsigned i = 0; i < ELEMENTS(pVM->pgm.s.aHCPhysDynPageMapCache); i++)
1799	pVM->pgm.s.aHCPhysDynPageMapCache[i] = HCPhysDummy;
1800
1801	for (unsigned i = 0; i < MM_HYPER_DYNAMIC_SIZE; i += PAGE_SIZE)
1802	{
1803	rc = PGMMap(pVM, pVM->pgm.s.pbDynPageMapBaseGC + i, HCPhysDummy, PAGE_SIZE, 0);
1804	AssertRCReturn(rc, rc);
1805	}
1806
1807	return rc;
1808	}
1809
1810
1811	/**
1812	* Applies relocations to data and code managed by this
1813	* component. This function will be called at init and
1814	* whenever the VMM need to relocate it self inside the GC.
1815	*
1816	* @param pVM The VM.
1817	* @param offDelta Relocation delta relative to old location.
1818	*/
1819	PGMR3DECL(void) PGMR3Relocate(PVM pVM, RTGCINTPTR offDelta)
1820	{
1821	LogFlow(("PGMR3Relocate\n"));
1822
1823	/*
1824	* Paging stuff.
1825	*/
1826	pVM->pgm.s.GCPtrCR3Mapping += offDelta;
1827	/** @todo move this into shadow and guest specific relocation functions. */
1828	AssertMsg(pVM->pgm.s.pGC32BitPD, ("Init order, no relocation before paging is initialized!\n"));
1829	pVM->pgm.s.pGC32BitPD += offDelta;
1830	pVM->pgm.s.pGuestPDGC += offDelta;
1831	AssertCompile(ELEMENTS(pVM->pgm.s.apGCPaePDs) == ELEMENTS(pVM->pgm.s.apGstPaePDsGC));
1832	for (unsigned i = 0; i < ELEMENTS(pVM->pgm.s.apGCPaePDs); i++)
1833	{
1834	pVM->pgm.s.apGCPaePDs[i] += offDelta;
1835	pVM->pgm.s.apGstPaePDsGC[i] += offDelta;
1836	}
1837	pVM->pgm.s.pGstPaePDPTGC += offDelta;
1838	pVM->pgm.s.pGCPaePDPT += offDelta;
1839
1840	pgmR3ModeDataInit(pVM, true /* resolve GC/R0 symbols */);
1841	pgmR3ModeDataSwitch(pVM, pVM->pgm.s.enmShadowMode, pVM->pgm.s.enmGuestMode);
1842
1843	PGM_SHW_PFN(Relocate, pVM)(pVM, offDelta);
1844	PGM_GST_PFN(Relocate, pVM)(pVM, offDelta);
1845	PGM_BTH_PFN(Relocate, pVM)(pVM, offDelta);
1846
1847	/*
1848	* Trees.
1849	*/
1850	pVM->pgm.s.pTreesGC = MMHyperHC2GC(pVM, pVM->pgm.s.pTreesHC);
1851
1852	/*
1853	* Ram ranges.
1854	*/
1855	if (pVM->pgm.s.pRamRangesR3)
1856	{
1857	pVM->pgm.s.pRamRangesGC = MMHyperHC2GC(pVM, pVM->pgm.s.pRamRangesR3);
1858	for (PPGMRAMRANGE pCur = pVM->pgm.s.pRamRangesR3; pCur->pNextR3; pCur = pCur->pNextR3)
1859	#ifdef VBOX_WITH_NEW_PHYS_CODE
1860	pCur->pNextGC = MMHyperR3ToGC(pVM, pCur->pNextR3);
1861	#else
1862	{
1863	pCur->pNextGC = MMHyperR3ToGC(pVM, pCur->pNextR3);
1864	if (pCur->pavHCChunkGC)
1865	pCur->pavHCChunkGC = MMHyperHC2GC(pVM, pCur->pavHCChunkHC);
1866	}
1867	#endif
1868	}
1869
1870	/*
1871	* Update the two page directories with all page table mappings.
1872	* (One or more of them have changed, that's why we're here.)
1873	*/
1874	pVM->pgm.s.pMappingsGC = MMHyperHC2GC(pVM, pVM->pgm.s.pMappingsR3);
1875	for (PPGMMAPPING pCur = pVM->pgm.s.pMappingsR3; pCur->pNextR3; pCur = pCur->pNextR3)
1876	pCur->pNextGC = MMHyperHC2GC(pVM, pCur->pNextR3);
1877
1878	/* Relocate GC addresses of Page Tables. */
1879	for (PPGMMAPPING pCur = pVM->pgm.s.pMappingsR3; pCur; pCur = pCur->pNextR3)
1880	{
1881	for (RTHCUINT i = 0; i < pCur->cPTs; i++)
1882	{
1883	pCur->aPTs[i].pPTGC = MMHyperR3ToGC(pVM, pCur->aPTs[i].pPTR3);
1884	pCur->aPTs[i].paPaePTsGC = MMHyperR3ToGC(pVM, pCur->aPTs[i].paPaePTsR3);
1885	}
1886	}
1887
1888	/*
1889	* Dynamic page mapping area.
1890	*/
1891	pVM->pgm.s.paDynPageMap32BitPTEsGC += offDelta;
1892	pVM->pgm.s.paDynPageMapPaePTEsGC += offDelta;
1893	pVM->pgm.s.pbDynPageMapBaseGC += offDelta;
1894
1895	/*
1896	* The Zero page.
1897	*/
1898	pVM->pgm.s.pvZeroPgR0 = MMHyperR3ToR0(pVM, pVM->pgm.s.pvZeroPgR3);
1899	AssertRelease(pVM->pgm.s.pvZeroPgR0);
1900
1901	/*
1902	* Physical and virtual handlers.
1903	*/
1904	RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesHC->PhysHandlers, true, pgmR3RelocatePhysHandler, &offDelta);
1905	RTAvlroGCPtrDoWithAll(&pVM->pgm.s.pTreesHC->VirtHandlers, true, pgmR3RelocateVirtHandler, &offDelta);
1906	RTAvlroGCPtrDoWithAll(&pVM->pgm.s.pTreesHC->HyperVirtHandlers, true, pgmR3RelocateHyperVirtHandler, &offDelta);
1907
1908	/*
1909	* The page pool.
1910	*/
1911	pgmR3PoolRelocate(pVM);
1912	}
1913
1914
1915	/**
1916	* Callback function for relocating a physical access handler.
1917	*
1918	* @returns 0 (continue enum)
1919	* @param pNode Pointer to a PGMPHYSHANDLER node.
1920	* @param pvUser Pointer to the offDelta. This is a pointer to the delta since we're
1921	* not certain the delta will fit in a void pointer for all possible configs.
1922	*/
1923	static DECLCALLBACK(int) pgmR3RelocatePhysHandler(PAVLROGCPHYSNODECORE pNode, void *pvUser)
1924	{
1925	PPGMPHYSHANDLER pHandler = (PPGMPHYSHANDLER)pNode;
1926	RTGCINTPTR offDelta = *(PRTGCINTPTR)pvUser;
1927	if (pHandler->pfnHandlerGC)
1928	pHandler->pfnHandlerGC += offDelta;
1929	if ((RTGCUINTPTR)pHandler->pvUserGC >= 0x10000)
1930	pHandler->pvUserGC += offDelta;
1931	return 0;
1932	}
1933
1934
1935	/**
1936	* Callback function for relocating a virtual access handler.
1937	*
1938	* @returns 0 (continue enum)
1939	* @param pNode Pointer to a PGMVIRTHANDLER node.
1940	* @param pvUser Pointer to the offDelta. This is a pointer to the delta since we're
1941	* not certain the delta will fit in a void pointer for all possible configs.
1942	*/
1943	static DECLCALLBACK(int) pgmR3RelocateVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser)
1944	{
1945	PPGMVIRTHANDLER pHandler = (PPGMVIRTHANDLER)pNode;
1946	RTGCINTPTR offDelta = *(PRTGCINTPTR)pvUser;
1947	Assert( pHandler->enmType == PGMVIRTHANDLERTYPE_ALL
1948	\|\| pHandler->enmType == PGMVIRTHANDLERTYPE_WRITE);
1949	Assert(pHandler->pfnHandlerGC);
1950	pHandler->pfnHandlerGC += offDelta;
1951	return 0;
1952	}
1953
1954
1955	/**
1956	* Callback function for relocating a virtual access handler for the hypervisor mapping.
1957	*
1958	* @returns 0 (continue enum)
1959	* @param pNode Pointer to a PGMVIRTHANDLER node.
1960	* @param pvUser Pointer to the offDelta. This is a pointer to the delta since we're
1961	* not certain the delta will fit in a void pointer for all possible configs.
1962	*/
1963	static DECLCALLBACK(int) pgmR3RelocateHyperVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser)
1964	{
1965	PPGMVIRTHANDLER pHandler = (PPGMVIRTHANDLER)pNode;
1966	RTGCINTPTR offDelta = *(PRTGCINTPTR)pvUser;
1967	Assert(pHandler->enmType == PGMVIRTHANDLERTYPE_HYPERVISOR);
1968	Assert(pHandler->pfnHandlerGC);
1969	pHandler->pfnHandlerGC += offDelta;
1970	return 0;
1971	}
1972
1973
1974	/**
1975	* The VM is being reset.
1976	*
1977	* For the PGM component this means that any PD write monitors
1978	* needs to be removed.
1979	*
1980	* @param pVM VM handle.
1981	*/
1982	PGMR3DECL(void) PGMR3Reset(PVM pVM)
1983	{
1984	LogFlow(("PGMR3Reset:\n"));
1985	VM_ASSERT_EMT(pVM);
1986
1987	pgmLock(pVM);
1988
1989	/*
1990	* Unfix any fixed mappings and disable CR3 monitoring.
1991	*/
1992	pVM->pgm.s.fMappingsFixed = false;
1993	pVM->pgm.s.GCPtrMappingFixed = 0;
1994	pVM->pgm.s.cbMappingFixed = 0;
1995
1996	/* Exit the guest paging mode before the pgm pool gets reset.
1997	* Important to clean up the amd64 case.
1998	*/
1999	int rc = PGM_GST_PFN(Exit, pVM)(pVM);
2000	AssertRC(rc);
2001	#ifdef DEBUG
2002	DBGFR3InfoLog(pVM, "mappings", NULL);
2003	DBGFR3InfoLog(pVM, "handlers", "all nostat");
2004	#endif
2005
2006	/*
2007	* Reset the shadow page pool.
2008	*/
2009	pgmR3PoolReset(pVM);
2010
2011	/*
2012	* Re-init other members.
2013	*/
2014	pVM->pgm.s.fA20Enabled = true;
2015
2016	/*
2017	* Clear the FFs PGM owns.
2018	*/
2019	VM_FF_CLEAR(pVM, VM_FF_PGM_SYNC_CR3);
2020	VM_FF_CLEAR(pVM, VM_FF_PGM_SYNC_CR3_NON_GLOBAL);
2021
2022	/*
2023	* Reset (zero) RAM pages.
2024	*/
2025	rc = pgmR3PhysRamReset(pVM);
2026	if (RT_SUCCESS(rc))
2027	{
2028	#ifdef VBOX_WITH_NEW_PHYS_CODE
2029	/*
2030	* Reset (zero) shadow ROM pages.
2031	*/
2032	rc = pgmR3PhysRomReset(pVM);
2033	#endif
2034	if (RT_SUCCESS(rc))
2035	{
2036	/*
2037	* Switch mode back to real mode.
2038	*/
2039	rc = PGMR3ChangeMode(pVM, PGMMODE_REAL);
2040	STAM_REL_COUNTER_RESET(&pVM->pgm.s.cGuestModeChanges);
2041	}
2042	}
2043
2044	pgmUnlock(pVM);
2045	//return rc;
2046	AssertReleaseRC(rc);
2047	}
2048
2049
2050	#ifdef VBOX_STRICT
2051	/**
2052	* VM state change callback for clearing fNoMorePhysWrites after
2053	* a snapshot has been created.
2054	*/
2055	static DECLCALLBACK(void) pgmR3ResetNoMorePhysWritesFlag(PVM pVM, VMSTATE enmState, VMSTATE enmOldState, void *pvUser)
2056	{
2057	if (enmState == VMSTATE_RUNNING)
2058	pVM->pgm.s.fNoMorePhysWrites = false;
2059	}
2060	#endif
2061
2062
2063	/**
2064	* Terminates the PGM.
2065	*
2066	* @returns VBox status code.
2067	* @param pVM Pointer to VM structure.
2068	*/
2069	PGMR3DECL(int) PGMR3Term(PVM pVM)
2070	{
2071	return PDMR3CritSectDelete(&pVM->pgm.s.CritSect);
2072	}
2073
2074
2075	/**
2076	* Execute state save operation.
2077	*
2078	* @returns VBox status code.
2079	* @param pVM VM Handle.
2080	* @param pSSM SSM operation handle.
2081	*/
2082	static DECLCALLBACK(int) pgmR3Save(PVM pVM, PSSMHANDLE pSSM)
2083	{
2084	PPGM pPGM = &pVM->pgm.s;
2085
2086	/* No more writes to physical memory after this point! */
2087	pVM->pgm.s.fNoMorePhysWrites = true;
2088
2089	/*
2090	* Save basic data (required / unaffected by relocation).
2091	*/
2092	#if 1
2093	SSMR3PutBool(pSSM, pPGM->fMappingsFixed);
2094	#else
2095	SSMR3PutUInt(pSSM, pPGM->fMappingsFixed);
2096	#endif
2097	SSMR3PutGCPtr(pSSM, pPGM->GCPtrMappingFixed);
2098	SSMR3PutU32(pSSM, pPGM->cbMappingFixed);
2099	SSMR3PutUInt(pSSM, pPGM->cbRamSize);
2100	SSMR3PutGCPhys(pSSM, pPGM->GCPhysA20Mask);
2101	SSMR3PutUInt(pSSM, pPGM->fA20Enabled);
2102	SSMR3PutUInt(pSSM, pPGM->fSyncFlags);
2103	SSMR3PutUInt(pSSM, pPGM->enmGuestMode);
2104	SSMR3PutU32(pSSM, ~0); /* Separator. */
2105
2106	/*
2107	* The guest mappings.
2108	*/
2109	uint32_t i = 0;
2110	for (PPGMMAPPING pMapping = pPGM->pMappingsR3; pMapping; pMapping = pMapping->pNextR3, i++)
2111	{
2112	SSMR3PutU32(pSSM, i);
2113	SSMR3PutStrZ(pSSM, pMapping->pszDesc); /* This is the best unique id we have... */
2114	SSMR3PutGCPtr(pSSM, pMapping->GCPtr);
2115	SSMR3PutGCUIntPtr(pSSM, pMapping->cPTs);
2116	/* flags are done by the mapping owners! */
2117	}
2118	SSMR3PutU32(pSSM, ~0); /* terminator. */
2119
2120	/*
2121	* Ram range flags and bits.
2122	*/
2123	i = 0;
2124	for (PPGMRAMRANGE pRam = pPGM->pRamRangesR3; pRam; pRam = pRam->pNextR3, i++)
2125	{
2126	/** @todo MMIO ranges may move (PCI reconfig), we currently assume they don't. */
2127
2128	SSMR3PutU32(pSSM, i);
2129	SSMR3PutGCPhys(pSSM, pRam->GCPhys);
2130	SSMR3PutGCPhys(pSSM, pRam->GCPhysLast);
2131	SSMR3PutGCPhys(pSSM, pRam->cb);
2132	SSMR3PutU8(pSSM, !!pRam->pvHC); /* boolean indicating memory or not. */
2133
2134	/* Flags. */
2135	const unsigned cPages = pRam->cb >> PAGE_SHIFT;
2136	for (unsigned iPage = 0; iPage < cPages; iPage++)
2137	SSMR3PutU16(pSSM, (uint16_t)(pRam->aPages[iPage].HCPhys & ~X86_PTE_PAE_PG_MASK)); /** @todo PAGE FLAGS */
2138
2139	/* any memory associated with the range. */
2140	if (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)
2141	{
2142	for (unsigned iChunk = 0; iChunk < (pRam->cb >> PGM_DYNAMIC_CHUNK_SHIFT); iChunk++)
2143	{
2144	if (pRam->pavHCChunkHC[iChunk])
2145	{
2146	SSMR3PutU8(pSSM, 1); /* chunk present */
2147	SSMR3PutMem(pSSM, pRam->pavHCChunkHC[iChunk], PGM_DYNAMIC_CHUNK_SIZE);
2148	}
2149	else
2150	SSMR3PutU8(pSSM, 0); /* no chunk present */
2151	}
2152	}
2153	else if (pRam->pvHC)
2154	{
2155	int rc = SSMR3PutMem(pSSM, pRam->pvHC, pRam->cb);
2156	if (VBOX_FAILURE(rc))
2157	{
2158	Log(("pgmR3Save: SSMR3PutMem(, %p, %#x) -> %Vrc\n", pRam->pvHC, pRam->cb, rc));
2159	return rc;
2160	}
2161	}
2162	}
2163	return SSMR3PutU32(pSSM, ~0); /* terminator. */
2164	}
2165
2166
2167	/**
2168	* Execute state load operation.
2169	*
2170	* @returns VBox status code.
2171	* @param pVM VM Handle.
2172	* @param pSSM SSM operation handle.
2173	* @param u32Version Data layout version.
2174	*/
2175	static DECLCALLBACK(int) pgmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version)
2176	{
2177	/*
2178	* Validate version.
2179	*/
2180	if (u32Version != PGM_SAVED_STATE_VERSION)
2181	{
2182	Log(("pgmR3Load: Invalid version u32Version=%d (current %d)!\n", u32Version, PGM_SAVED_STATE_VERSION));
2183	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
2184	}
2185
2186	/*
2187	* Call the reset function to make sure all the memory is cleared.
2188	*/
2189	PGMR3Reset(pVM);
2190
2191	/*
2192	* Load basic data (required / unaffected by relocation).
2193	*/
2194	PPGM pPGM = &pVM->pgm.s;
2195	#if 1
2196	SSMR3GetBool(pSSM, &pPGM->fMappingsFixed);
2197	#else
2198	uint32_t u;
2199	SSMR3GetU32(pSSM, &u);
2200	pPGM->fMappingsFixed = u;
2201	#endif
2202	SSMR3GetGCPtr(pSSM, &pPGM->GCPtrMappingFixed);
2203	SSMR3GetU32(pSSM, &pPGM->cbMappingFixed);
2204
2205	RTUINT cbRamSize;
2206	int rc = SSMR3GetU32(pSSM, &cbRamSize);
2207	if (VBOX_FAILURE(rc))
2208	return rc;
2209	if (cbRamSize != pPGM->cbRamSize)
2210	return VERR_SSM_LOAD_MEMORY_SIZE_MISMATCH;
2211	SSMR3GetGCPhys(pSSM, &pPGM->GCPhysA20Mask);
2212	SSMR3GetUInt(pSSM, &pPGM->fA20Enabled);
2213	SSMR3GetUInt(pSSM, &pPGM->fSyncFlags);
2214	RTUINT uGuestMode;
2215	SSMR3GetUInt(pSSM, &uGuestMode);
2216	pPGM->enmGuestMode = (PGMMODE)uGuestMode;
2217
2218	/* check separator. */
2219	uint32_t u32Sep;
2220	SSMR3GetU32(pSSM, &u32Sep);
2221	if (VBOX_FAILURE(rc))
2222	return rc;
2223	if (u32Sep != (uint32_t)~0)
2224	{
2225	AssertMsgFailed(("u32Sep=%#x (first)\n", u32Sep));
2226	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2227	}
2228
2229	/*
2230	* The guest mappings.
2231	*/
2232	uint32_t i = 0;
2233	for (;; i++)
2234	{
2235	/* Check the seqence number / separator. */
2236	rc = SSMR3GetU32(pSSM, &u32Sep);
2237	if (VBOX_FAILURE(rc))
2238	return rc;
2239	if (u32Sep == ~0U)
2240	break;
2241	if (u32Sep != i)
2242	{
2243	AssertMsgFailed(("u32Sep=%#x (last)\n", u32Sep));
2244	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2245	}
2246
2247	/* get the mapping details. */
2248	char szDesc[256];
2249	szDesc[0] = '\0';
2250	rc = SSMR3GetStrZ(pSSM, szDesc, sizeof(szDesc));
2251	if (VBOX_FAILURE(rc))
2252	return rc;
2253	RTGCPTR GCPtr;
2254	SSMR3GetGCPtr(pSSM, &GCPtr);
2255	RTGCUINTPTR cPTs;
2256	rc = SSMR3GetGCUIntPtr(pSSM, &cPTs);
2257	if (VBOX_FAILURE(rc))
2258	return rc;
2259
2260	/* find matching range. */
2261	PPGMMAPPING pMapping;
2262	for (pMapping = pPGM->pMappingsR3; pMapping; pMapping = pMapping->pNextR3)
2263	if ( pMapping->cPTs == cPTs
2264	&& !strcmp(pMapping->pszDesc, szDesc))
2265	break;
2266	if (!pMapping)
2267	{
2268	LogRel(("Couldn't find mapping: cPTs=%#x szDesc=%s (GCPtr=%VGv)\n",
2269	cPTs, szDesc, GCPtr));
2270	AssertFailed();
2271	return VERR_SSM_LOAD_CONFIG_MISMATCH;
2272	}
2273
2274	/* relocate it. */
2275	if (pMapping->GCPtr != GCPtr)
2276	{
2277	AssertMsg((GCPtr >> X86_PD_SHIFT << X86_PD_SHIFT) == GCPtr, ("GCPtr=%VGv\n", GCPtr));
2278	#if HC_ARCH_BITS == 64
2279	LogRel(("Mapping: %VGv -> %VGv %s\n", pMapping->GCPtr, GCPtr, pMapping->pszDesc));
2280	#endif
2281	pgmR3MapRelocate(pVM, pMapping, pMapping->GCPtr, GCPtr);
2282	}
2283	else
2284	Log(("pgmR3Load: '%s' needed no relocation (%VGv)\n", szDesc, GCPtr));
2285	}
2286
2287	/*
2288	* Ram range flags and bits.
2289	*/
2290	i = 0;
2291	for (PPGMRAMRANGE pRam = pPGM->pRamRangesR3; pRam; pRam = pRam->pNextR3, i++)
2292	{
2293	/** @todo MMIO ranges may move (PCI reconfig), we currently assume they don't. */
2294	/* Check the seqence number / separator. */
2295	rc = SSMR3GetU32(pSSM, &u32Sep);
2296	if (VBOX_FAILURE(rc))
2297	return rc;
2298	if (u32Sep == ~0U)
2299	break;
2300	if (u32Sep != i)
2301	{
2302	AssertMsgFailed(("u32Sep=%#x (last)\n", u32Sep));
2303	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2304	}
2305
2306	/* Get the range details. */
2307	RTGCPHYS GCPhys;
2308	SSMR3GetGCPhys(pSSM, &GCPhys);
2309	RTGCPHYS GCPhysLast;
2310	SSMR3GetGCPhys(pSSM, &GCPhysLast);
2311	RTGCPHYS cb;
2312	SSMR3GetGCPhys(pSSM, &cb);
2313	uint8_t fHaveBits;
2314	rc = SSMR3GetU8(pSSM, &fHaveBits);
2315	if (VBOX_FAILURE(rc))
2316	return rc;
2317	if (fHaveBits & ~1)
2318	{
2319	AssertMsgFailed(("u32Sep=%#x (last)\n", u32Sep));
2320	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2321	}
2322
2323	/* Match it up with the current range. */
2324	if ( GCPhys != pRam->GCPhys
2325	\|\| GCPhysLast != pRam->GCPhysLast
2326	\|\| cb != pRam->cb
2327	\|\| fHaveBits != !!pRam->pvHC)
2328	{
2329	LogRel(("Ram range: %VGp-%VGp %VGp bytes %s\n"
2330	"State : %VGp-%VGp %VGp bytes %s\n",
2331	pRam->GCPhys, pRam->GCPhysLast, pRam->cb, pRam->pvHC ? "bits" : "nobits",
2332	GCPhys, GCPhysLast, cb, fHaveBits ? "bits" : "nobits"));
2333	/*
2334	* If we're loading a state for debugging purpose, don't make a fuss if
2335	* the MMIO[2] and ROM stuff isn't 100% right, just skip the mismatches.
2336	*/
2337	if ( SSMR3HandleGetAfter(pSSM) != SSMAFTER_DEBUG_IT
2338	\|\| GCPhys < 8 * _1M)
2339	AssertFailedReturn(VERR_SSM_LOAD_CONFIG_MISMATCH);
2340
2341	RTGCPHYS cPages = ((GCPhysLast - GCPhys) + 1) >> PAGE_SHIFT;
2342	while (cPages-- > 0)
2343	{
2344	uint16_t u16Ignore;
2345	SSMR3GetU16(pSSM, &u16Ignore);
2346	}
2347	continue;
2348	}
2349
2350	/* Flags. */
2351	const unsigned cPages = pRam->cb >> PAGE_SHIFT;
2352	for (unsigned iPage = 0; iPage < cPages; iPage++)
2353	{
2354	uint16_t u16 = 0;
2355	SSMR3GetU16(pSSM, &u16);
2356	u16 &= PAGE_OFFSET_MASK & ~( RT_BIT(4) \| RT_BIT(5) \| RT_BIT(6)
2357	\| RT_BIT(7) \| RT_BIT(8) \| RT_BIT(9) \| RT_BIT(10) );
2358	// &= MM_RAM_FLAGS_DYNAMIC_ALLOC \| MM_RAM_FLAGS_RESERVED \| MM_RAM_FLAGS_ROM \| MM_RAM_FLAGS_MMIO \| MM_RAM_FLAGS_MMIO2
2359	pRam->aPages[iPage].HCPhys = PGM_PAGE_GET_HCPHYS(&pRam->aPages[iPage]) \| (RTHCPHYS)u16; /** @todo PAGE FLAGS */
2360	}
2361
2362	/* any memory associated with the range. */
2363	if (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)
2364	{
2365	for (unsigned iChunk = 0; iChunk < (pRam->cb >> PGM_DYNAMIC_CHUNK_SHIFT); iChunk++)
2366	{
2367	uint8_t fValidChunk;
2368
2369	rc = SSMR3GetU8(pSSM, &fValidChunk);
2370	if (VBOX_FAILURE(rc))
2371	return rc;
2372	if (fValidChunk > 1)
2373	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2374
2375	if (fValidChunk)
2376	{
2377	if (!pRam->pavHCChunkHC[iChunk])
2378	{
2379	rc = pgmr3PhysGrowRange(pVM, pRam->GCPhys + iChunk * PGM_DYNAMIC_CHUNK_SIZE);
2380	if (VBOX_FAILURE(rc))
2381	return rc;
2382	}
2383	Assert(pRam->pavHCChunkHC[iChunk]);
2384
2385	SSMR3GetMem(pSSM, pRam->pavHCChunkHC[iChunk], PGM_DYNAMIC_CHUNK_SIZE);
2386	}
2387	/* else nothing to do */
2388	}
2389	}
2390	else if (pRam->pvHC)
2391	{
2392	int rc = SSMR3GetMem(pSSM, pRam->pvHC, pRam->cb);
2393	if (VBOX_FAILURE(rc))
2394	{
2395	Log(("pgmR3Save: SSMR3GetMem(, %p, %#x) -> %Vrc\n", pRam->pvHC, pRam->cb, rc));
2396	return rc;
2397	}
2398	}
2399	}
2400
2401	/*
2402	* We require a full resync now.
2403	*/
2404	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3_NON_GLOBAL);
2405	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
2406	pPGM->fSyncFlags \|= PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL;
2407	pPGM->fPhysCacheFlushPending = true;
2408	pgmR3HandlerPhysicalUpdateAll(pVM);
2409
2410	/*
2411	* Change the paging mode.
2412	*/
2413	rc = PGMR3ChangeMode(pVM, pPGM->enmGuestMode);
2414
2415	/* Restore pVM->pgm.s.GCPhysCR3. */
2416	Assert(pVM->pgm.s.GCPhysCR3 == NIL_RTGCPHYS);
2417	RTGCPHYS GCPhysCR3 = CPUMGetGuestCR3(pVM);
2418	if ( pVM->pgm.s.enmGuestMode == PGMMODE_PAE
2419	\|\| pVM->pgm.s.enmGuestMode == PGMMODE_PAE_NX
2420	\|\| pVM->pgm.s.enmGuestMode == PGMMODE_AMD64
2421	\|\| pVM->pgm.s.enmGuestMode == PGMMODE_AMD64_NX)
2422	GCPhysCR3 = (GCPhysCR3 & X86_CR3_PAE_PAGE_MASK);
2423	else
2424	GCPhysCR3 = (GCPhysCR3 & X86_CR3_PAGE_MASK);
2425	pVM->pgm.s.GCPhysCR3 = GCPhysCR3;
2426
2427	return rc;
2428	}
2429
2430
2431	/**
2432	* Show paging mode.
2433	*
2434	* @param pVM VM Handle.
2435	* @param pHlp The info helpers.
2436	* @param pszArgs "all" (default), "guest", "shadow" or "host".
2437	*/
2438	static DECLCALLBACK(void) pgmR3InfoMode(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2439	{
2440	/* digest argument. */
2441	bool fGuest, fShadow, fHost;
2442	if (pszArgs)
2443	pszArgs = RTStrStripL(pszArgs);
2444	if (!pszArgs \|\| !*pszArgs \|\| strstr(pszArgs, "all"))
2445	fShadow = fHost = fGuest = true;
2446	else
2447	{
2448	fShadow = fHost = fGuest = false;
2449	if (strstr(pszArgs, "guest"))
2450	fGuest = true;
2451	if (strstr(pszArgs, "shadow"))
2452	fShadow = true;
2453	if (strstr(pszArgs, "host"))
2454	fHost = true;
2455	}
2456
2457	/* print info. */
2458	if (fGuest)
2459	pHlp->pfnPrintf(pHlp, "Guest paging mode: %s, changed %RU64 times, A20 %s\n",
2460	PGMGetModeName(pVM->pgm.s.enmGuestMode), pVM->pgm.s.cGuestModeChanges.c,
2461	pVM->pgm.s.fA20Enabled ? "enabled" : "disabled");
2462	if (fShadow)
2463	pHlp->pfnPrintf(pHlp, "Shadow paging mode: %s\n", PGMGetModeName(pVM->pgm.s.enmShadowMode));
2464	if (fHost)
2465	{
2466	const char *psz;
2467	switch (pVM->pgm.s.enmHostMode)
2468	{
2469	case SUPPAGINGMODE_INVALID: psz = "invalid"; break;
2470	case SUPPAGINGMODE_32_BIT: psz = "32-bit"; break;
2471	case SUPPAGINGMODE_32_BIT_GLOBAL: psz = "32-bit+G"; break;
2472	case SUPPAGINGMODE_PAE: psz = "PAE"; break;
2473	case SUPPAGINGMODE_PAE_GLOBAL: psz = "PAE+G"; break;
2474	case SUPPAGINGMODE_PAE_NX: psz = "PAE+NX"; break;
2475	case SUPPAGINGMODE_PAE_GLOBAL_NX: psz = "PAE+G+NX"; break;
2476	case SUPPAGINGMODE_AMD64: psz = "AMD64"; break;
2477	case SUPPAGINGMODE_AMD64_GLOBAL: psz = "AMD64+G"; break;
2478	case SUPPAGINGMODE_AMD64_NX: psz = "AMD64+NX"; break;
2479	case SUPPAGINGMODE_AMD64_GLOBAL_NX: psz = "AMD64+G+NX"; break;
2480	default: psz = "unknown"; break;
2481	}
2482	pHlp->pfnPrintf(pHlp, "Host paging mode: %s\n", psz);
2483	}
2484	}
2485
2486
2487	/**
2488	* Dump registered MMIO ranges to the log.
2489	*
2490	* @param pVM VM Handle.
2491	* @param pHlp The info helpers.
2492	* @param pszArgs Arguments, ignored.
2493	*/
2494	static DECLCALLBACK(void) pgmR3PhysInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2495	{
2496	NOREF(pszArgs);
2497	pHlp->pfnPrintf(pHlp,
2498	"RAM ranges (pVM=%p)\n"
2499	"%.s %.s\n",
2500	pVM,
2501	sizeof(RTGCPHYS) * 4 + 1, "GC Phys Range ",
2502	sizeof(RTHCPTR) * 2, "pvHC ");
2503
2504	for (PPGMRAMRANGE pCur = pVM->pgm.s.pRamRangesR3; pCur; pCur = pCur->pNextR3)
2505	pHlp->pfnPrintf(pHlp,
2506	"%RGp-%RGp %RHv %s\n",
2507	pCur->GCPhys,
2508	pCur->GCPhysLast,
2509	pCur->pvHC,
2510	pCur->pszDesc);
2511	}
2512
2513	/**
2514	* Dump the page directory to the log.
2515	*
2516	* @param pVM VM Handle.
2517	* @param pHlp The info helpers.
2518	* @param pszArgs Arguments, ignored.
2519	*/
2520	static DECLCALLBACK(void) pgmR3InfoCr3(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2521	{
2522	/** @todo fix this! Convert the PGMR3DumpHierarchyHC functions to do guest stuff. */
2523	/* Big pages supported? */
2524	const bool fPSE = !!(CPUMGetGuestCR4(pVM) & X86_CR4_PSE);
2525
2526	/* Global pages supported? */
2527	const bool fPGE = !!(CPUMGetGuestCR4(pVM) & X86_CR4_PGE);
2528
2529	NOREF(pszArgs);
2530
2531	/*
2532	* Get page directory addresses.
2533	*/
2534	PX86PD pPDSrc = pVM->pgm.s.pGuestPDHC;
2535	Assert(pPDSrc);
2536	Assert(MMPhysGCPhys2HCVirt(pVM, (RTGCPHYS)(CPUMGetGuestCR3(pVM) & X86_CR3_PAGE_MASK), sizeof(*pPDSrc)) == pPDSrc);
2537
2538	/*
2539	* Iterate the page directory.
2540	*/
2541	for (unsigned iPD = 0; iPD < ELEMENTS(pPDSrc->a); iPD++)
2542	{
2543	X86PDE PdeSrc = pPDSrc->a[iPD];
2544	if (PdeSrc.n.u1Present)
2545	{
2546	if (PdeSrc.b.u1Size && fPSE)
2547	{
2548	pHlp->pfnPrintf(pHlp,
2549	"%04X - %VGp P=%d U=%d RW=%d G=%d - BIG\n",
2550	iPD,
2551	PdeSrc.u & X86_PDE_PG_MASK,
2552	PdeSrc.b.u1Present, PdeSrc.b.u1User, PdeSrc.b.u1Write, PdeSrc.b.u1Global && fPGE);
2553	}
2554	else
2555	{
2556	pHlp->pfnPrintf(pHlp,
2557	"%04X - %VGp P=%d U=%d RW=%d [G=%d]\n",
2558	iPD,
2559	PdeSrc.u & X86_PDE4M_PG_MASK,
2560	PdeSrc.n.u1Present, PdeSrc.n.u1User, PdeSrc.n.u1Write, PdeSrc.b.u1Global && fPGE);
2561	}
2562	}
2563	}
2564	}
2565
2566
2567	/**
2568	* Serivce a VMMCALLHOST_PGM_LOCK call.
2569	*
2570	* @returns VBox status code.
2571	* @param pVM The VM handle.
2572	*/
2573	PDMR3DECL(int) PGMR3LockCall(PVM pVM)
2574	{
2575	int rc = PDMR3CritSectEnterEx(&pVM->pgm.s.CritSect, true /* fHostCall */);
2576	AssertRC(rc);
2577	return rc;
2578	}
2579
2580
2581	/**
2582	* Converts a PGMMODE value to a PGM_TYPE_* \#define.
2583	*
2584	* @returns PGM_TYPE_*.
2585	* @param pgmMode The mode value to convert.
2586	*/
2587	DECLINLINE(unsigned) pgmModeToType(PGMMODE pgmMode)
2588	{
2589	switch (pgmMode)
2590	{
2591	case PGMMODE_REAL: return PGM_TYPE_REAL;
2592	case PGMMODE_PROTECTED: return PGM_TYPE_PROT;
2593	case PGMMODE_32_BIT: return PGM_TYPE_32BIT;
2594	case PGMMODE_PAE:
2595	case PGMMODE_PAE_NX: return PGM_TYPE_PAE;
2596	case PGMMODE_AMD64:
2597	case PGMMODE_AMD64_NX: return PGM_TYPE_AMD64;
2598	case PGMMODE_NESTED: return PGM_TYPE_NESTED;
2599	case PGMMODE_EPT: return PGM_TYPE_EPT;
2600	default:
2601	AssertFatalMsgFailed(("pgmMode=%d\n", pgmMode));
2602	}
2603	}
2604
2605
2606	/**
2607	* Gets the index into the paging mode data array of a SHW+GST mode.
2608	*
2609	* @returns PGM::paPagingData index.
2610	* @param uShwType The shadow paging mode type.
2611	* @param uGstType The guest paging mode type.
2612	*/
2613	DECLINLINE(unsigned) pgmModeDataIndex(unsigned uShwType, unsigned uGstType)
2614	{
2615	Assert(uShwType >= PGM_TYPE_32BIT && uShwType <= PGM_TYPE_NESTED);
2616	Assert(uGstType >= PGM_TYPE_REAL && uGstType <= PGM_TYPE_AMD64);
2617	return (uShwType - PGM_TYPE_32BIT) * (PGM_TYPE_AMD64 - PGM_TYPE_REAL + 1)
2618	+ (uGstType - PGM_TYPE_REAL);
2619	}
2620
2621
2622	/**
2623	* Gets the index into the paging mode data array of a SHW+GST mode.
2624	*
2625	* @returns PGM::paPagingData index.
2626	* @param enmShw The shadow paging mode.
2627	* @param enmGst The guest paging mode.
2628	*/
2629	DECLINLINE(unsigned) pgmModeDataIndexByMode(PGMMODE enmShw, PGMMODE enmGst)
2630	{
2631	Assert(enmShw >= PGMMODE_32_BIT && enmShw <= PGMMODE_MAX);
2632	Assert(enmGst > PGMMODE_INVALID && enmGst < PGMMODE_MAX);
2633	return pgmModeDataIndex(pgmModeToType(enmShw), pgmModeToType(enmGst));
2634	}
2635
2636
2637	/**
2638	* Calculates the max data index.
2639	* @returns The number of entries in the paging data array.
2640	*/
2641	DECLINLINE(unsigned) pgmModeDataMaxIndex(void)
2642	{
2643	return pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_AMD64) + 1;
2644	}
2645
2646
2647	/**
2648	* Initializes the paging mode data kept in PGM::paModeData.
2649	*
2650	* @param pVM The VM handle.
2651	* @param fResolveGCAndR0 Indicate whether or not GC and Ring-0 symbols can be resolved now.
2652	* This is used early in the init process to avoid trouble with PDM
2653	* not being initialized yet.
2654	*/
2655	static int pgmR3ModeDataInit(PVM pVM, bool fResolveGCAndR0)
2656	{
2657	PPGMMODEDATA pModeData;
2658	int rc;
2659
2660	/*
2661	* Allocate the array on the first call.
2662	*/
2663	if (!pVM->pgm.s.paModeData)
2664	{
2665	pVM->pgm.s.paModeData = (PPGMMODEDATA)MMR3HeapAllocZ(pVM, MM_TAG_PGM, sizeof(PGMMODEDATA) * pgmModeDataMaxIndex());
2666	AssertReturn(pVM->pgm.s.paModeData, VERR_NO_MEMORY);
2667	}
2668
2669	/*
2670	* Initialize the array entries.
2671	*/
2672	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_32BIT, PGM_TYPE_REAL)];
2673	pModeData->uShwType = PGM_TYPE_32BIT;
2674	pModeData->uGstType = PGM_TYPE_REAL;
2675	rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2676	rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2677	rc = PGM_BTH_NAME_32BIT_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2678
2679	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_32BIT, PGMMODE_PROTECTED)];
2680	pModeData->uShwType = PGM_TYPE_32BIT;
2681	pModeData->uGstType = PGM_TYPE_PROT;
2682	rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2683	rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2684	rc = PGM_BTH_NAME_32BIT_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2685
2686	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_32BIT, PGM_TYPE_32BIT)];
2687	pModeData->uShwType = PGM_TYPE_32BIT;
2688	pModeData->uGstType = PGM_TYPE_32BIT;
2689	rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2690	rc = PGM_GST_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2691	rc = PGM_BTH_NAME_32BIT_32BIT(InitData)(pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2692
2693	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_REAL)];
2694	pModeData->uShwType = PGM_TYPE_PAE;
2695	pModeData->uGstType = PGM_TYPE_REAL;
2696	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2697	rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2698	rc = PGM_BTH_NAME_PAE_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2699
2700	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_PROT)];
2701	pModeData->uShwType = PGM_TYPE_PAE;
2702	pModeData->uGstType = PGM_TYPE_PROT;
2703	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2704	rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2705	rc = PGM_BTH_NAME_PAE_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2706
2707	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_32BIT)];
2708	pModeData->uShwType = PGM_TYPE_PAE;
2709	pModeData->uGstType = PGM_TYPE_32BIT;
2710	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2711	rc = PGM_GST_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2712	rc = PGM_BTH_NAME_PAE_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2713
2714	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_PAE)];
2715	pModeData->uShwType = PGM_TYPE_PAE;
2716	pModeData->uGstType = PGM_TYPE_PAE;
2717	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2718	rc = PGM_GST_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2719	rc = PGM_BTH_NAME_PAE_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2720
2721	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_AMD64, PGM_TYPE_AMD64)];
2722	pModeData->uShwType = PGM_TYPE_AMD64;
2723	pModeData->uGstType = PGM_TYPE_AMD64;
2724	rc = PGM_SHW_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2725	rc = PGM_GST_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2726	rc = PGM_BTH_NAME_AMD64_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2727
2728	/* The nested paging mode. */
2729	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_REAL)];
2730	pModeData->uShwType = PGM_TYPE_NESTED;
2731	pModeData->uGstType = PGM_TYPE_REAL;
2732	rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2733	rc = PGM_BTH_NAME_NESTED_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2734
2735	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGMMODE_PROTECTED)];
2736	pModeData->uShwType = PGM_TYPE_NESTED;
2737	pModeData->uGstType = PGM_TYPE_PROT;
2738	rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2739	rc = PGM_BTH_NAME_NESTED_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2740
2741	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_32BIT)];
2742	pModeData->uShwType = PGM_TYPE_NESTED;
2743	pModeData->uGstType = PGM_TYPE_32BIT;
2744	rc = PGM_GST_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2745	rc = PGM_BTH_NAME_NESTED_32BIT(InitData)(pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2746
2747	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_PAE)];
2748	pModeData->uShwType = PGM_TYPE_NESTED;
2749	pModeData->uGstType = PGM_TYPE_PAE;
2750	rc = PGM_GST_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2751	rc = PGM_BTH_NAME_NESTED_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2752
2753	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_AMD64)];
2754	pModeData->uShwType = PGM_TYPE_NESTED;
2755	pModeData->uGstType = PGM_TYPE_AMD64;
2756	rc = PGM_GST_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2757	rc = PGM_BTH_NAME_NESTED_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2758
2759	/* The shadow part of the nested callback mode depends on the host paging mode (AMD-V only). */
2760	switch(pVM->pgm.s.enmHostMode)
2761	{
2762	case SUPPAGINGMODE_32_BIT:
2763	case SUPPAGINGMODE_32_BIT_GLOBAL:
2764	for (unsigned i=PGM_TYPE_REAL;i<=PGM_TYPE_AMD64;i++)
2765	{
2766	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, i)];
2767	rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2768	}
2769	break;
2770
2771	case SUPPAGINGMODE_PAE:
2772	case SUPPAGINGMODE_PAE_NX:
2773	case SUPPAGINGMODE_PAE_GLOBAL:
2774	case SUPPAGINGMODE_PAE_GLOBAL_NX:
2775	for (unsigned i=PGM_TYPE_REAL;i<=PGM_TYPE_AMD64;i++)
2776	{
2777	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, i)];
2778	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2779	}
2780	break;
2781
2782	case SUPPAGINGMODE_AMD64:
2783	case SUPPAGINGMODE_AMD64_GLOBAL:
2784	case SUPPAGINGMODE_AMD64_NX:
2785	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
2786	for (unsigned i=PGM_TYPE_REAL;i<=PGM_TYPE_AMD64;i++)
2787	{
2788	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, i)];
2789	rc = PGM_SHW_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2790	}
2791	break;
2792	default:
2793	AssertFailed();
2794	break;
2795	}
2796
2797	#ifdef PGM_WITH_EPT
2798	/* Extended paging (EPT) / Intel VT-x */
2799	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_REAL)];
2800	pModeData->uShwType = PGM_TYPE_EPT;
2801	pModeData->uGstType = PGM_TYPE_REAL;
2802	rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2803	rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2804	rc = PGM_BTH_NAME_EPT_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2805
2806	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_PROT)];
2807	pModeData->uShwType = PGM_TYPE_EPT;
2808	pModeData->uGstType = PGM_TYPE_PROT;
2809	rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2810	rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2811	rc = PGM_BTH_NAME_EPT_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2812
2813	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_32BIT)];
2814	pModeData->uShwType = PGM_TYPE_EPT;
2815	pModeData->uGstType = PGM_TYPE_32BIT;
2816	rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2817	rc = PGM_GST_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2818	rc = PGM_BTH_NAME_EPT_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2819
2820	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_PAE)];
2821	pModeData->uShwType = PGM_TYPE_EPT;
2822	pModeData->uGstType = PGM_TYPE_PAE;
2823	rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2824	rc = PGM_GST_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2825	rc = PGM_BTH_NAME_EPT_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2826
2827	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_AMD64)];
2828	pModeData->uShwType = PGM_TYPE_EPT;
2829	pModeData->uGstType = PGM_TYPE_AMD64;
2830	rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2831	rc = PGM_GST_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2832	rc = PGM_BTH_NAME_EPT_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2833	#endif /* PGM_WITH_EPT */
2834	return VINF_SUCCESS;
2835	}
2836
2837
2838	/**
2839	* Switch to different (or relocated in the relocate case) mode data.
2840	*
2841	* @param pVM The VM handle.
2842	* @param enmShw The the shadow paging mode.
2843	* @param enmGst The the guest paging mode.
2844	*/
2845	static void pgmR3ModeDataSwitch(PVM pVM, PGMMODE enmShw, PGMMODE enmGst)
2846	{
2847	PPGMMODEDATA pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndexByMode(enmShw, enmGst)];
2848
2849	Assert(pModeData->uGstType == pgmModeToType(enmGst));
2850	Assert(pModeData->uShwType == pgmModeToType(enmShw));
2851
2852	/* shadow */
2853	pVM->pgm.s.pfnR3ShwRelocate = pModeData->pfnR3ShwRelocate;
2854	pVM->pgm.s.pfnR3ShwExit = pModeData->pfnR3ShwExit;
2855	pVM->pgm.s.pfnR3ShwGetPage = pModeData->pfnR3ShwGetPage;
2856	Assert(pVM->pgm.s.pfnR3ShwGetPage);
2857	pVM->pgm.s.pfnR3ShwModifyPage = pModeData->pfnR3ShwModifyPage;
2858
2859	pVM->pgm.s.pfnGCShwGetPage = pModeData->pfnGCShwGetPage;
2860	pVM->pgm.s.pfnGCShwModifyPage = pModeData->pfnGCShwModifyPage;
2861
2862	pVM->pgm.s.pfnR0ShwGetPage = pModeData->pfnR0ShwGetPage;
2863	pVM->pgm.s.pfnR0ShwModifyPage = pModeData->pfnR0ShwModifyPage;
2864
2865
2866	/* guest */
2867	pVM->pgm.s.pfnR3GstRelocate = pModeData->pfnR3GstRelocate;
2868	pVM->pgm.s.pfnR3GstExit = pModeData->pfnR3GstExit;
2869	pVM->pgm.s.pfnR3GstGetPage = pModeData->pfnR3GstGetPage;
2870	Assert(pVM->pgm.s.pfnR3GstGetPage);
2871	pVM->pgm.s.pfnR3GstModifyPage = pModeData->pfnR3GstModifyPage;
2872	pVM->pgm.s.pfnR3GstGetPDE = pModeData->pfnR3GstGetPDE;
2873	pVM->pgm.s.pfnR3GstMonitorCR3 = pModeData->pfnR3GstMonitorCR3;
2874	pVM->pgm.s.pfnR3GstUnmonitorCR3 = pModeData->pfnR3GstUnmonitorCR3;
2875	pVM->pgm.s.pfnR3GstMapCR3 = pModeData->pfnR3GstMapCR3;
2876	pVM->pgm.s.pfnR3GstUnmapCR3 = pModeData->pfnR3GstUnmapCR3;
2877	pVM->pgm.s.pfnR3GstWriteHandlerCR3 = pModeData->pfnR3GstWriteHandlerCR3;
2878	pVM->pgm.s.pszR3GstWriteHandlerCR3 = pModeData->pszR3GstWriteHandlerCR3;
2879	pVM->pgm.s.pfnR3GstPAEWriteHandlerCR3 = pModeData->pfnR3GstPAEWriteHandlerCR3;
2880	pVM->pgm.s.pszR3GstPAEWriteHandlerCR3 = pModeData->pszR3GstPAEWriteHandlerCR3;
2881
2882	pVM->pgm.s.pfnGCGstGetPage = pModeData->pfnGCGstGetPage;
2883	pVM->pgm.s.pfnGCGstModifyPage = pModeData->pfnGCGstModifyPage;
2884	pVM->pgm.s.pfnGCGstGetPDE = pModeData->pfnGCGstGetPDE;
2885	pVM->pgm.s.pfnGCGstMonitorCR3 = pModeData->pfnGCGstMonitorCR3;
2886	pVM->pgm.s.pfnGCGstUnmonitorCR3 = pModeData->pfnGCGstUnmonitorCR3;
2887	pVM->pgm.s.pfnGCGstMapCR3 = pModeData->pfnGCGstMapCR3;
2888	pVM->pgm.s.pfnGCGstUnmapCR3 = pModeData->pfnGCGstUnmapCR3;
2889	pVM->pgm.s.pfnGCGstWriteHandlerCR3 = pModeData->pfnGCGstWriteHandlerCR3;
2890	pVM->pgm.s.pfnGCGstPAEWriteHandlerCR3 = pModeData->pfnGCGstPAEWriteHandlerCR3;
2891
2892	pVM->pgm.s.pfnR0GstGetPage = pModeData->pfnR0GstGetPage;
2893	pVM->pgm.s.pfnR0GstModifyPage = pModeData->pfnR0GstModifyPage;
2894	pVM->pgm.s.pfnR0GstGetPDE = pModeData->pfnR0GstGetPDE;
2895	pVM->pgm.s.pfnR0GstMonitorCR3 = pModeData->pfnR0GstMonitorCR3;
2896	pVM->pgm.s.pfnR0GstUnmonitorCR3 = pModeData->pfnR0GstUnmonitorCR3;
2897	pVM->pgm.s.pfnR0GstMapCR3 = pModeData->pfnR0GstMapCR3;
2898	pVM->pgm.s.pfnR0GstUnmapCR3 = pModeData->pfnR0GstUnmapCR3;
2899	pVM->pgm.s.pfnR0GstWriteHandlerCR3 = pModeData->pfnR0GstWriteHandlerCR3;
2900	pVM->pgm.s.pfnR0GstPAEWriteHandlerCR3 = pModeData->pfnR0GstPAEWriteHandlerCR3;
2901
2902
2903	/* both */
2904	pVM->pgm.s.pfnR3BthRelocate = pModeData->pfnR3BthRelocate;
2905	pVM->pgm.s.pfnR3BthTrap0eHandler = pModeData->pfnR3BthTrap0eHandler;
2906	pVM->pgm.s.pfnR3BthInvalidatePage = pModeData->pfnR3BthInvalidatePage;
2907	pVM->pgm.s.pfnR3BthSyncCR3 = pModeData->pfnR3BthSyncCR3;
2908	Assert(pVM->pgm.s.pfnR3BthSyncCR3);
2909	pVM->pgm.s.pfnR3BthSyncPage = pModeData->pfnR3BthSyncPage;
2910	pVM->pgm.s.pfnR3BthPrefetchPage = pModeData->pfnR3BthPrefetchPage;
2911	pVM->pgm.s.pfnR3BthVerifyAccessSyncPage = pModeData->pfnR3BthVerifyAccessSyncPage;
2912	#ifdef VBOX_STRICT
2913	pVM->pgm.s.pfnR3BthAssertCR3 = pModeData->pfnR3BthAssertCR3;
2914	#endif
2915
2916	pVM->pgm.s.pfnGCBthTrap0eHandler = pModeData->pfnGCBthTrap0eHandler;
2917	pVM->pgm.s.pfnGCBthInvalidatePage = pModeData->pfnGCBthInvalidatePage;
2918	pVM->pgm.s.pfnGCBthSyncCR3 = pModeData->pfnGCBthSyncCR3;
2919	pVM->pgm.s.pfnGCBthSyncPage = pModeData->pfnGCBthSyncPage;
2920	pVM->pgm.s.pfnGCBthPrefetchPage = pModeData->pfnGCBthPrefetchPage;
2921	pVM->pgm.s.pfnGCBthVerifyAccessSyncPage = pModeData->pfnGCBthVerifyAccessSyncPage;
2922	#ifdef VBOX_STRICT
2923	pVM->pgm.s.pfnGCBthAssertCR3 = pModeData->pfnGCBthAssertCR3;
2924	#endif
2925
2926	pVM->pgm.s.pfnR0BthTrap0eHandler = pModeData->pfnR0BthTrap0eHandler;
2927	pVM->pgm.s.pfnR0BthInvalidatePage = pModeData->pfnR0BthInvalidatePage;
2928	pVM->pgm.s.pfnR0BthSyncCR3 = pModeData->pfnR0BthSyncCR3;
2929	pVM->pgm.s.pfnR0BthSyncPage = pModeData->pfnR0BthSyncPage;
2930	pVM->pgm.s.pfnR0BthPrefetchPage = pModeData->pfnR0BthPrefetchPage;
2931	pVM->pgm.s.pfnR0BthVerifyAccessSyncPage = pModeData->pfnR0BthVerifyAccessSyncPage;
2932	#ifdef VBOX_STRICT
2933	pVM->pgm.s.pfnR0BthAssertCR3 = pModeData->pfnR0BthAssertCR3;
2934	#endif
2935	}
2936
2937
2938	#ifdef DEBUG_bird
2939	#include <stdlib.h> /* getenv() remove me! */
2940	#endif
2941
2942	/**
2943	* Calculates the shadow paging mode.
2944	*
2945	* @returns The shadow paging mode.
2946	* @param pVM VM handle.
2947	* @param enmGuestMode The guest mode.
2948	* @param enmHostMode The host mode.
2949	* @param enmShadowMode The current shadow mode.
2950	* @param penmSwitcher Where to store the switcher to use.
2951	* VMMSWITCHER_INVALID means no change.
2952	*/
2953	static PGMMODE pgmR3CalcShadowMode(PVM pVM, PGMMODE enmGuestMode, SUPPAGINGMODE enmHostMode, PGMMODE enmShadowMode, VMMSWITCHER *penmSwitcher)
2954	{
2955	VMMSWITCHER enmSwitcher = VMMSWITCHER_INVALID;
2956	switch (enmGuestMode)
2957	{
2958	/*
2959	* When switching to real or protected mode we don't change
2960	* anything since it's likely that we'll switch back pretty soon.
2961	*
2962	* During pgmR3InitPaging we'll end up here with PGMMODE_INVALID
2963	* and is supposed to determine which shadow paging and switcher to
2964	* use during init.
2965	*/
2966	case PGMMODE_REAL:
2967	case PGMMODE_PROTECTED:
2968	if ( enmShadowMode != PGMMODE_INVALID
2969	&& !HWACCMIsEnabled(pVM) /* always switch in hwaccm mode! */)
2970	break; /* (no change) */
2971
2972	switch (enmHostMode)
2973	{
2974	case SUPPAGINGMODE_32_BIT:
2975	case SUPPAGINGMODE_32_BIT_GLOBAL:
2976	enmShadowMode = PGMMODE_32_BIT;
2977	enmSwitcher = VMMSWITCHER_32_TO_32;
2978	break;
2979
2980	case SUPPAGINGMODE_PAE:
2981	case SUPPAGINGMODE_PAE_NX:
2982	case SUPPAGINGMODE_PAE_GLOBAL:
2983	case SUPPAGINGMODE_PAE_GLOBAL_NX:
2984	enmShadowMode = PGMMODE_PAE;
2985	enmSwitcher = VMMSWITCHER_PAE_TO_PAE;
2986	#ifdef DEBUG_bird
2987	if (getenv("VBOX_32BIT"))
2988	{
2989	enmShadowMode = PGMMODE_32_BIT;
2990	enmSwitcher = VMMSWITCHER_PAE_TO_32;
2991	}
2992	#endif
2993	break;
2994
2995	case SUPPAGINGMODE_AMD64:
2996	case SUPPAGINGMODE_AMD64_GLOBAL:
2997	case SUPPAGINGMODE_AMD64_NX:
2998	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
2999	enmShadowMode = PGMMODE_PAE;
3000	enmSwitcher = VMMSWITCHER_AMD64_TO_PAE;
3001	break;
3002
3003	default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
3004	}
3005	break;
3006
3007	case PGMMODE_32_BIT:
3008	switch (enmHostMode)
3009	{
3010	case SUPPAGINGMODE_32_BIT:
3011	case SUPPAGINGMODE_32_BIT_GLOBAL:
3012	enmShadowMode = PGMMODE_32_BIT;
3013	enmSwitcher = VMMSWITCHER_32_TO_32;
3014	break;
3015
3016	case SUPPAGINGMODE_PAE:
3017	case SUPPAGINGMODE_PAE_NX:
3018	case SUPPAGINGMODE_PAE_GLOBAL:
3019	case SUPPAGINGMODE_PAE_GLOBAL_NX:
3020	enmShadowMode = PGMMODE_PAE;
3021	enmSwitcher = VMMSWITCHER_PAE_TO_PAE;
3022	#ifdef DEBUG_bird
3023	if (getenv("VBOX_32BIT"))
3024	{
3025	enmShadowMode = PGMMODE_32_BIT;
3026	enmSwitcher = VMMSWITCHER_PAE_TO_32;
3027	}
3028	#endif
3029	break;
3030
3031	case SUPPAGINGMODE_AMD64:
3032	case SUPPAGINGMODE_AMD64_GLOBAL:
3033	case SUPPAGINGMODE_AMD64_NX:
3034	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
3035	enmShadowMode = PGMMODE_PAE;
3036	enmSwitcher = VMMSWITCHER_AMD64_TO_PAE;
3037	break;
3038
3039	default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
3040	}
3041	break;
3042
3043	case PGMMODE_PAE:
3044	case PGMMODE_PAE_NX: /** @todo This might require more switchers and guest+both modes. */
3045	switch (enmHostMode)
3046	{
3047	case SUPPAGINGMODE_32_BIT:
3048	case SUPPAGINGMODE_32_BIT_GLOBAL:
3049	enmShadowMode = PGMMODE_PAE;
3050	enmSwitcher = VMMSWITCHER_32_TO_PAE;
3051	break;
3052
3053	case SUPPAGINGMODE_PAE:
3054	case SUPPAGINGMODE_PAE_NX:
3055	case SUPPAGINGMODE_PAE_GLOBAL:
3056	case SUPPAGINGMODE_PAE_GLOBAL_NX:
3057	enmShadowMode = PGMMODE_PAE;
3058	enmSwitcher = VMMSWITCHER_PAE_TO_PAE;
3059	break;
3060
3061	case SUPPAGINGMODE_AMD64:
3062	case SUPPAGINGMODE_AMD64_GLOBAL:
3063	case SUPPAGINGMODE_AMD64_NX:
3064	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
3065	enmShadowMode = PGMMODE_PAE;
3066	enmSwitcher = VMMSWITCHER_AMD64_TO_PAE;
3067	break;
3068
3069	default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
3070	}
3071	break;
3072
3073	case PGMMODE_AMD64:
3074	case PGMMODE_AMD64_NX:
3075	switch (enmHostMode)
3076	{
3077	case SUPPAGINGMODE_32_BIT:
3078	case SUPPAGINGMODE_32_BIT_GLOBAL:
3079	enmShadowMode = PGMMODE_PAE;
3080	enmSwitcher = VMMSWITCHER_32_TO_AMD64;
3081	break;
3082
3083	case SUPPAGINGMODE_PAE:
3084	case SUPPAGINGMODE_PAE_NX:
3085	case SUPPAGINGMODE_PAE_GLOBAL:
3086	case SUPPAGINGMODE_PAE_GLOBAL_NX:
3087	enmShadowMode = PGMMODE_PAE;
3088	enmSwitcher = VMMSWITCHER_PAE_TO_AMD64;
3089	break;
3090
3091	case SUPPAGINGMODE_AMD64:
3092	case SUPPAGINGMODE_AMD64_GLOBAL:
3093	case SUPPAGINGMODE_AMD64_NX:
3094	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
3095	enmShadowMode = PGMMODE_AMD64;
3096	enmSwitcher = VMMSWITCHER_AMD64_TO_AMD64;
3097	break;
3098
3099	default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
3100	}
3101	break;
3102
3103
3104	default:
3105	AssertReleaseMsgFailed(("enmGuestMode=%d\n", enmGuestMode));
3106	return PGMMODE_INVALID;
3107	}
3108	/* Override the shadow mode is nested paging is active. */
3109	if (HWACCMIsNestedPagingActive(pVM))
3110	enmShadowMode = HWACCMGetPagingMode(pVM);
3111
3112	*penmSwitcher = enmSwitcher;
3113	return enmShadowMode;
3114	}
3115
3116	/**
3117	* Performs the actual mode change.
3118	* This is called by PGMChangeMode and pgmR3InitPaging().
3119	*
3120	* @returns VBox status code.
3121	* @param pVM VM handle.
3122	* @param enmGuestMode The new guest mode. This is assumed to be different from
3123	* the current mode.
3124	*/
3125	PGMR3DECL(int) PGMR3ChangeMode(PVM pVM, PGMMODE enmGuestMode)
3126	{
3127	LogFlow(("PGMR3ChangeMode: Guest mode: %s -> %s\n", PGMGetModeName(pVM->pgm.s.enmGuestMode), PGMGetModeName(enmGuestMode)));
3128	STAM_REL_COUNTER_INC(&pVM->pgm.s.cGuestModeChanges);
3129
3130	/*
3131	* Calc the shadow mode and switcher.
3132	*/
3133	VMMSWITCHER enmSwitcher;
3134	PGMMODE enmShadowMode = pgmR3CalcShadowMode(pVM, enmGuestMode, pVM->pgm.s.enmHostMode, pVM->pgm.s.enmShadowMode, &enmSwitcher);
3135	if (enmSwitcher != VMMSWITCHER_INVALID)
3136	{
3137	/*
3138	* Select new switcher.
3139	*/
3140	int rc = VMMR3SelectSwitcher(pVM, enmSwitcher);
3141	if (VBOX_FAILURE(rc))
3142	{
3143	AssertReleaseMsgFailed(("VMMR3SelectSwitcher(%d) -> %Vrc\n", enmSwitcher, rc));
3144	return rc;
3145	}
3146	}
3147
3148	/*
3149	* Exit old mode(s).
3150	*/
3151	/* shadow */
3152	if (enmShadowMode != pVM->pgm.s.enmShadowMode)
3153	{
3154	LogFlow(("PGMR3ChangeMode: Shadow mode: %s -> %s\n", PGMGetModeName(pVM->pgm.s.enmShadowMode), PGMGetModeName(enmShadowMode)));
3155	if (PGM_SHW_PFN(Exit, pVM))
3156	{
3157	int rc = PGM_SHW_PFN(Exit, pVM)(pVM);
3158	if (VBOX_FAILURE(rc))
3159	{
3160	AssertMsgFailed(("Exit failed for shadow mode %d: %Vrc\n", pVM->pgm.s.enmShadowMode, rc));
3161	return rc;
3162	}
3163	}
3164
3165	}
3166
3167	/* guest */
3168	if (PGM_GST_PFN(Exit, pVM))
3169	{
3170	int rc = PGM_GST_PFN(Exit, pVM)(pVM);
3171	if (VBOX_FAILURE(rc))
3172	{
3173	AssertMsgFailed(("Exit failed for guest mode %d: %Vrc\n", pVM->pgm.s.enmGuestMode, rc));
3174	return rc;
3175	}
3176	}
3177
3178	/*
3179	* Load new paging mode data.
3180	*/
3181	pgmR3ModeDataSwitch(pVM, enmShadowMode, enmGuestMode);
3182
3183	/*
3184	* Enter new shadow mode (if changed).
3185	*/
3186	if (enmShadowMode != pVM->pgm.s.enmShadowMode)
3187	{
3188	int rc;
3189	pVM->pgm.s.enmShadowMode = enmShadowMode;
3190	switch (enmShadowMode)
3191	{
3192	case PGMMODE_32_BIT:
3193	rc = PGM_SHW_NAME_32BIT(Enter)(pVM);
3194	break;
3195	case PGMMODE_PAE:
3196	case PGMMODE_PAE_NX:
3197	rc = PGM_SHW_NAME_PAE(Enter)(pVM);
3198	break;
3199	case PGMMODE_AMD64:
3200	case PGMMODE_AMD64_NX:
3201	rc = PGM_SHW_NAME_AMD64(Enter)(pVM);
3202	break;
3203	case PGMMODE_NESTED:
3204	rc = PGM_SHW_NAME_NESTED(Enter)(pVM);
3205	break;
3206	#ifdef PGM_WITH_EPT
3207	case PGMMODE_EPT:
3208	rc = PGM_SHW_NAME_EPT(Enter)(pVM);
3209	break;
3210	#endif
3211	case PGMMODE_REAL:
3212	case PGMMODE_PROTECTED:
3213	default:
3214	AssertReleaseMsgFailed(("enmShadowMode=%d\n", enmShadowMode));
3215	return VERR_INTERNAL_ERROR;
3216	}
3217	if (VBOX_FAILURE(rc))
3218	{
3219	AssertReleaseMsgFailed(("Entering enmShadowMode=%d failed: %Vrc\n", enmShadowMode, rc));
3220	pVM->pgm.s.enmShadowMode = PGMMODE_INVALID;
3221	return rc;
3222	}
3223	}
3224
3225	/*
3226	* Enter the new guest and shadow+guest modes.
3227	*/
3228	int rc = -1;
3229	int rc2 = -1;
3230	RTGCPHYS GCPhysCR3 = NIL_RTGCPHYS;
3231	pVM->pgm.s.enmGuestMode = enmGuestMode;
3232	switch (enmGuestMode)
3233	{
3234	case PGMMODE_REAL:
3235	rc = PGM_GST_NAME_REAL(Enter)(pVM, NIL_RTGCPHYS);
3236	switch (pVM->pgm.s.enmShadowMode)
3237	{
3238	case PGMMODE_32_BIT:
3239	rc2 = PGM_BTH_NAME_32BIT_REAL(Enter)(pVM, NIL_RTGCPHYS);
3240	break;
3241	case PGMMODE_PAE:
3242	case PGMMODE_PAE_NX:
3243	rc2 = PGM_BTH_NAME_PAE_REAL(Enter)(pVM, NIL_RTGCPHYS);
3244	break;
3245	case PGMMODE_NESTED:
3246	rc2 = PGM_BTH_NAME_NESTED_REAL(Enter)(pVM, NIL_RTGCPHYS);
3247	break;
3248	#ifdef PGM_WITH_EPT
3249	case PGMMODE_EPT:
3250	rc2 = PGM_BTH_NAME_EPT_REAL(Enter)(pVM, NIL_RTGCPHYS);
3251	break;
3252	#endif
3253	case PGMMODE_AMD64:
3254	case PGMMODE_AMD64_NX:
3255	AssertMsgFailed(("Should use PAE shadow mode!\n"));
3256	default: AssertFailed(); break;
3257	}
3258	break;
3259
3260	case PGMMODE_PROTECTED:
3261	rc = PGM_GST_NAME_PROT(Enter)(pVM, NIL_RTGCPHYS);
3262	switch (pVM->pgm.s.enmShadowMode)
3263	{
3264	case PGMMODE_32_BIT:
3265	rc2 = PGM_BTH_NAME_32BIT_PROT(Enter)(pVM, NIL_RTGCPHYS);
3266	break;
3267	case PGMMODE_PAE:
3268	case PGMMODE_PAE_NX:
3269	rc2 = PGM_BTH_NAME_PAE_PROT(Enter)(pVM, NIL_RTGCPHYS);
3270	break;
3271	case PGMMODE_NESTED:
3272	rc2 = PGM_BTH_NAME_NESTED_PROT(Enter)(pVM, NIL_RTGCPHYS);
3273	break;
3274	#ifdef PGM_WITH_EPT
3275	case PGMMODE_EPT:
3276	rc2 = PGM_BTH_NAME_EPT_PROT(Enter)(pVM, NIL_RTGCPHYS);
3277	break;
3278	#endif
3279	case PGMMODE_AMD64:
3280	case PGMMODE_AMD64_NX:
3281	AssertMsgFailed(("Should use PAE shadow mode!\n"));
3282	default: AssertFailed(); break;
3283	}
3284	break;
3285
3286	case PGMMODE_32_BIT:
3287	GCPhysCR3 = CPUMGetGuestCR3(pVM) & X86_CR3_PAGE_MASK;
3288	rc = PGM_GST_NAME_32BIT(Enter)(pVM, GCPhysCR3);
3289	switch (pVM->pgm.s.enmShadowMode)
3290	{
3291	case PGMMODE_32_BIT:
3292	rc2 = PGM_BTH_NAME_32BIT_32BIT(Enter)(pVM, GCPhysCR3);
3293	break;
3294	case PGMMODE_PAE:
3295	case PGMMODE_PAE_NX:
3296	rc2 = PGM_BTH_NAME_PAE_32BIT(Enter)(pVM, GCPhysCR3);
3297	break;
3298	case PGMMODE_NESTED:
3299	rc2 = PGM_BTH_NAME_NESTED_32BIT(Enter)(pVM, GCPhysCR3);
3300	break;
3301	#ifdef PGM_WITH_EPT
3302	case PGMMODE_EPT:
3303	rc2 = PGM_BTH_NAME_EPT_32BIT(Enter)(pVM, GCPhysCR3);
3304	break;
3305	#endif
3306	case PGMMODE_AMD64:
3307	case PGMMODE_AMD64_NX:
3308	AssertMsgFailed(("Should use PAE shadow mode!\n"));
3309	default: AssertFailed(); break;
3310	}
3311	break;
3312
3313	case PGMMODE_PAE_NX: /* VT-x/AMD-V only */
3314	Assert(HWACCMIsEnabled(pVM));
3315	/* no break */
3316
3317	case PGMMODE_PAE:
3318	{
3319	uint32_t u32Dummy, u32Features;
3320
3321	CPUMGetGuestCpuId(pVM, 1, &u32Dummy, &u32Dummy, &u32Dummy, &u32Features);
3322	if (!(u32Features & X86_CPUID_FEATURE_EDX_PAE))
3323	{
3324	/* Pause first, then inform Main. */
3325	rc = VMR3SuspendNoSave(pVM);
3326	AssertRC(rc);
3327
3328	VMSetRuntimeError(pVM, true, "PAEmode",
3329	N_("The guest is trying to switch to the PAE mode which is currently disabled by default in VirtualBox. Experimental PAE support can be enabled using the -pae option with VBoxManage."));
3330	/* we must return TRUE here otherwise the recompiler will assert */
3331	return VINF_SUCCESS;
3332	}
3333	GCPhysCR3 = CPUMGetGuestCR3(pVM) & X86_CR3_PAE_PAGE_MASK;
3334	rc = PGM_GST_NAME_PAE(Enter)(pVM, GCPhysCR3);
3335	switch (pVM->pgm.s.enmShadowMode)
3336	{
3337	case PGMMODE_PAE:
3338	case PGMMODE_PAE_NX:
3339	rc2 = PGM_BTH_NAME_PAE_PAE(Enter)(pVM, GCPhysCR3);
3340	break;
3341	case PGMMODE_NESTED:
3342	rc2 = PGM_BTH_NAME_NESTED_PAE(Enter)(pVM, GCPhysCR3);
3343	break;
3344	#ifdef PGM_WITH_EPT
3345	case PGMMODE_EPT:
3346	rc2 = PGM_BTH_NAME_EPT_PAE(Enter)(pVM, GCPhysCR3);
3347	break;
3348	#endif
3349	case PGMMODE_32_BIT:
3350	case PGMMODE_AMD64:
3351	case PGMMODE_AMD64_NX:
3352	AssertMsgFailed(("Should use PAE shadow mode!\n"));
3353	default: AssertFailed(); break;
3354	}
3355	break;
3356	}
3357
3358	case PGMMODE_AMD64_NX:
3359	case PGMMODE_AMD64:
3360	GCPhysCR3 = CPUMGetGuestCR3(pVM) & 0xfffffffffffff000ULL; /** @todo define this mask! */
3361	rc = PGM_GST_NAME_AMD64(Enter)(pVM, GCPhysCR3);
3362	switch (pVM->pgm.s.enmShadowMode)
3363	{
3364	case PGMMODE_AMD64:
3365	case PGMMODE_AMD64_NX:
3366	rc2 = PGM_BTH_NAME_AMD64_AMD64(Enter)(pVM, GCPhysCR3);
3367	break;
3368	case PGMMODE_NESTED:
3369	rc2 = PGM_BTH_NAME_NESTED_AMD64(Enter)(pVM, GCPhysCR3);
3370	break;
3371	#ifdef PGM_WITH_EPT
3372	case PGMMODE_EPT:
3373	rc2 = PGM_BTH_NAME_EPT_AMD64(Enter)(pVM, GCPhysCR3);
3374	break;
3375	#endif
3376	case PGMMODE_32_BIT:
3377	case PGMMODE_PAE:
3378	case PGMMODE_PAE_NX:
3379	AssertMsgFailed(("Should use AMD64 shadow mode!\n"));
3380	default: AssertFailed(); break;
3381	}
3382	break;
3383
3384	default:
3385	AssertReleaseMsgFailed(("enmGuestMode=%d\n", enmGuestMode));
3386	rc = VERR_NOT_IMPLEMENTED;
3387	break;
3388	}
3389
3390	/* status codes. */
3391	AssertRC(rc);
3392	AssertRC(rc2);
3393	if (VBOX_SUCCESS(rc))
3394	{
3395	rc = rc2;
3396	if (VBOX_SUCCESS(rc)) /* no informational status codes. */
3397	rc = VINF_SUCCESS;
3398	}
3399
3400	/*
3401	* Notify SELM so it can update the TSSes with correct CR3s.
3402	*/
3403	SELMR3PagingModeChanged(pVM);
3404
3405	/* Notify HWACCM as well. */
3406	HWACCMR3PagingModeChanged(pVM, pVM->pgm.s.enmShadowMode);
3407	return rc;
3408	}
3409
3410
3411	/**
3412	* Dumps a PAE shadow page table.
3413	*
3414	* @returns VBox status code (VINF_SUCCESS).
3415	* @param pVM The VM handle.
3416	* @param pPT Pointer to the page table.
3417	* @param u64Address The virtual address of the page table starts.
3418	* @param fLongMode Set if this a long mode table; clear if it's a legacy mode table.
3419	* @param cMaxDepth The maxium depth.
3420	* @param pHlp Pointer to the output functions.
3421	*/
3422	static int pgmR3DumpHierarchyHCPaePT(PVM pVM, PX86PTPAE pPT, uint64_t u64Address, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
3423	{
3424	for (unsigned i = 0; i < ELEMENTS(pPT->a); i++)
3425	{
3426	X86PTEPAE Pte = pPT->a[i];
3427	if (Pte.n.u1Present)
3428	{
3429	pHlp->pfnPrintf(pHlp,
3430	fLongMode /P R S A D G WT CD AT NX 4M a p ? /
3431	? "%016llx 3 \| P %c %c %c %c %c %s %s %s %s 4K %c%c%c %016llx\n"
3432	: "%08llx 2 \| P %c %c %c %c %c %s %s %s %s 4K %c%c%c %016llx\n",
3433	u64Address + ((uint64_t)i << X86_PT_PAE_SHIFT),
3434	Pte.n.u1Write ? 'W' : 'R',
3435	Pte.n.u1User ? 'U' : 'S',
3436	Pte.n.u1Accessed ? 'A' : '-',
3437	Pte.n.u1Dirty ? 'D' : '-',
3438	Pte.n.u1Global ? 'G' : '-',
3439	Pte.n.u1WriteThru ? "WT" : "--",
3440	Pte.n.u1CacheDisable? "CD" : "--",
3441	Pte.n.u1PAT ? "AT" : "--",
3442	Pte.n.u1NoExecute ? "NX" : "--",
3443	Pte.u & PGM_PTFLAGS_TRACK_DIRTY ? 'd' : '-',
3444	Pte.u & RT_BIT(10) ? '1' : '0',
3445	Pte.u & PGM_PTFLAGS_CSAM_VALIDATED? 'v' : '-',
3446	Pte.u & X86_PTE_PAE_PG_MASK);
3447	}
3448	}
3449	return VINF_SUCCESS;
3450	}
3451
3452
3453	/**
3454	* Dumps a PAE shadow page directory table.
3455	*
3456	* @returns VBox status code (VINF_SUCCESS).
3457	* @param pVM The VM handle.
3458	* @param HCPhys The physical address of the page directory table.
3459	* @param u64Address The virtual address of the page table starts.
3460	* @param cr4 The CR4, PSE is currently used.
3461	* @param fLongMode Set if this a long mode table; clear if it's a legacy mode table.
3462	* @param cMaxDepth The maxium depth.
3463	* @param pHlp Pointer to the output functions.
3464	*/
3465	static int pgmR3DumpHierarchyHCPaePD(PVM pVM, RTHCPHYS HCPhys, uint64_t u64Address, uint32_t cr4, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
3466	{
3467	PX86PDPAE pPD = (PX86PDPAE)MMPagePhys2Page(pVM, HCPhys);
3468	if (!pPD)
3469	{
3470	pHlp->pfnPrintf(pHlp, "%0*llx error! Page directory at HCPhys=%#VHp was not found in the page pool!\n",
3471	fLongMode ? 16 : 8, u64Address, HCPhys);
3472	return VERR_INVALID_PARAMETER;
3473	}
3474	const bool fBigPagesSupported = fLongMode \|\| !!(cr4 & X86_CR4_PSE);
3475
3476	int rc = VINF_SUCCESS;
3477	for (unsigned i = 0; i < ELEMENTS(pPD->a); i++)
3478	{
3479	X86PDEPAE Pde = pPD->a[i];
3480	if (Pde.n.u1Present)
3481	{
3482	if (fBigPagesSupported && Pde.b.u1Size)
3483	pHlp->pfnPrintf(pHlp,
3484	fLongMode /P R S A D G WT CD AT NX 4M a p ? /
3485	? "%016llx 2 \| P %c %c %c %c %c %s %s %s %s 4M %c%c%c %016llx\n"
3486	: "%08llx 1 \| P %c %c %c %c %c %s %s %s %s 4M %c%c%c %016llx\n",
3487	u64Address + ((uint64_t)i << X86_PD_PAE_SHIFT),
3488	Pde.b.u1Write ? 'W' : 'R',
3489	Pde.b.u1User ? 'U' : 'S',
3490	Pde.b.u1Accessed ? 'A' : '-',
3491	Pde.b.u1Dirty ? 'D' : '-',
3492	Pde.b.u1Global ? 'G' : '-',
3493	Pde.b.u1WriteThru ? "WT" : "--",
3494	Pde.b.u1CacheDisable? "CD" : "--",
3495	Pde.b.u1PAT ? "AT" : "--",
3496	Pde.b.u1NoExecute ? "NX" : "--",
3497	Pde.u & RT_BIT_64(9) ? '1' : '0',
3498	Pde.u & PGM_PDFLAGS_MAPPING ? 'm' : '-',
3499	Pde.u & PGM_PDFLAGS_TRACK_DIRTY ? 'd' : '-',
3500	Pde.u & X86_PDE_PAE_PG_MASK);
3501	else
3502	{
3503	pHlp->pfnPrintf(pHlp,
3504	fLongMode /P R S A D G WT CD AT NX 4M a p ? /
3505	? "%016llx 2 \| P %c %c %c %c %c %s %s .. %s 4K %c%c%c %016llx\n"
3506	: "%08llx 1 \| P %c %c %c %c %c %s %s .. %s 4K %c%c%c %016llx\n",
3507	u64Address + ((uint64_t)i << X86_PD_PAE_SHIFT),
3508	Pde.n.u1Write ? 'W' : 'R',
3509	Pde.n.u1User ? 'U' : 'S',
3510	Pde.n.u1Accessed ? 'A' : '-',
3511	Pde.n.u1Reserved0 ? '?' : '.', /* ignored */
3512	Pde.n.u1Reserved1 ? '?' : '.', /* ignored */
3513	Pde.n.u1WriteThru ? "WT" : "--",
3514	Pde.n.u1CacheDisable? "CD" : "--",
3515	Pde.n.u1NoExecute ? "NX" : "--",
3516	Pde.u & RT_BIT_64(9) ? '1' : '0',
3517	Pde.u & PGM_PDFLAGS_MAPPING ? 'm' : '-',
3518	Pde.u & PGM_PDFLAGS_TRACK_DIRTY ? 'd' : '-',
3519	Pde.u & X86_PDE_PAE_PG_MASK);
3520	if (cMaxDepth >= 1)
3521	{
3522	/** @todo what about using the page pool for mapping PTs? */
3523	uint64_t u64AddressPT = u64Address + ((uint64_t)i << X86_PD_PAE_SHIFT);
3524	RTHCPHYS HCPhysPT = Pde.u & X86_PDE_PAE_PG_MASK;
3525	PX86PTPAE pPT = NULL;
3526	if (!(Pde.u & PGM_PDFLAGS_MAPPING))
3527	pPT = (PX86PTPAE)MMPagePhys2Page(pVM, HCPhysPT);
3528	else
3529	{
3530	for (PPGMMAPPING pMap = pVM->pgm.s.pMappingsR3; pMap; pMap = pMap->pNextR3)
3531	{
3532	uint64_t off = u64AddressPT - pMap->GCPtr;
3533	if (off < pMap->cb)
3534	{
3535	const int iPDE = (uint32_t)(off >> X86_PD_SHIFT);
3536	const int iSub = (int)((off >> X86_PD_PAE_SHIFT) & 1); /* MSC is a pain sometimes */
3537	if ((iSub ? pMap->aPTs[iPDE].HCPhysPaePT1 : pMap->aPTs[iPDE].HCPhysPaePT0) != HCPhysPT)
3538	pHlp->pfnPrintf(pHlp, "%0*llx error! Mapping error! PT %d has HCPhysPT=%VHp not %VHp is in the PD.\n",
3539	fLongMode ? 16 : 8, u64AddressPT, iPDE,
3540	iSub ? pMap->aPTs[iPDE].HCPhysPaePT1 : pMap->aPTs[iPDE].HCPhysPaePT0, HCPhysPT);
3541	pPT = &pMap->aPTs[iPDE].paPaePTsR3[iSub];
3542	}
3543	}
3544	}
3545	int rc2 = VERR_INVALID_PARAMETER;
3546	if (pPT)
3547	rc2 = pgmR3DumpHierarchyHCPaePT(pVM, pPT, u64AddressPT, fLongMode, cMaxDepth - 1, pHlp);
3548	else
3549	pHlp->pfnPrintf(pHlp, "%0*llx error! Page table at HCPhys=%#VHp was not found in the page pool!\n",
3550	fLongMode ? 16 : 8, u64AddressPT, HCPhysPT);
3551	if (rc2 < rc && VBOX_SUCCESS(rc))
3552	rc = rc2;
3553	}
3554	}
3555	}
3556	}
3557	return rc;
3558	}
3559
3560
3561	/**
3562	* Dumps a PAE shadow page directory pointer table.
3563	*
3564	* @returns VBox status code (VINF_SUCCESS).
3565	* @param pVM The VM handle.
3566	* @param HCPhys The physical address of the page directory pointer table.
3567	* @param u64Address The virtual address of the page table starts.
3568	* @param cr4 The CR4, PSE is currently used.
3569	* @param fLongMode Set if this a long mode table; clear if it's a legacy mode table.
3570	* @param cMaxDepth The maxium depth.
3571	* @param pHlp Pointer to the output functions.
3572	*/
3573	static int pgmR3DumpHierarchyHCPaePDPT(PVM pVM, RTHCPHYS HCPhys, uint64_t u64Address, uint32_t cr4, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
3574	{
3575	PX86PDPT pPDPT = (PX86PDPT)MMPagePhys2Page(pVM, HCPhys);
3576	if (!pPDPT)
3577	{
3578	pHlp->pfnPrintf(pHlp, "%0*llx error! Page directory pointer table at HCPhys=%#VHp was not found in the page pool!\n",
3579	fLongMode ? 16 : 8, u64Address, HCPhys);
3580	return VERR_INVALID_PARAMETER;
3581	}
3582
3583	int rc = VINF_SUCCESS;
3584	const unsigned c = fLongMode ? ELEMENTS(pPDPT->a) : X86_PG_PAE_PDPE_ENTRIES;
3585	for (unsigned i = 0; i < c; i++)
3586	{
3587	X86PDPE Pdpe = pPDPT->a[i];
3588	if (Pdpe.n.u1Present)
3589	{
3590	if (fLongMode)
3591	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a p ? /
3592	"%016llx 1 \| P %c %c %c %c %c %s %s %s %s .. %c%c%c %016llx\n",
3593	u64Address + ((uint64_t)i << X86_PDPT_SHIFT),
3594	Pdpe.lm.u1Write ? 'W' : 'R',
3595	Pdpe.lm.u1User ? 'U' : 'S',
3596	Pdpe.lm.u1Accessed ? 'A' : '-',
3597	Pdpe.lm.u3Reserved & 1? '?' : '.', /* ignored */
3598	Pdpe.lm.u3Reserved & 4? '!' : '.', /* mbz */
3599	Pdpe.lm.u1WriteThru ? "WT" : "--",
3600	Pdpe.lm.u1CacheDisable? "CD" : "--",
3601	Pdpe.lm.u3Reserved & 2? "!" : "..",/* mbz */
3602	Pdpe.lm.u1NoExecute ? "NX" : "--",
3603	Pdpe.u & RT_BIT(9) ? '1' : '0',
3604	Pdpe.u & PGM_PLXFLAGS_PERMANENT ? 'p' : '-',
3605	Pdpe.u & RT_BIT(11) ? '1' : '0',
3606	Pdpe.u & X86_PDPE_PG_MASK);
3607	else
3608	pHlp->pfnPrintf(pHlp, /P G WT CD AT NX 4M a p ? /
3609	"%08x 0 \| P %c %s %s %s %s .. %c%c%c %016llx\n",
3610	i << X86_PDPT_SHIFT,
3611	Pdpe.n.u4Reserved & 1? '!' : '.', /* mbz */
3612	Pdpe.n.u4Reserved & 4? '!' : '.', /* mbz */
3613	Pdpe.n.u1WriteThru ? "WT" : "--",
3614	Pdpe.n.u1CacheDisable? "CD" : "--",
3615	Pdpe.n.u4Reserved & 2? "!" : "..",/* mbz */
3616	Pdpe.u & RT_BIT(9) ? '1' : '0',
3617	Pdpe.u & PGM_PLXFLAGS_PERMANENT ? 'p' : '-',
3618	Pdpe.u & RT_BIT(11) ? '1' : '0',
3619	Pdpe.u & X86_PDPE_PG_MASK);
3620	if (cMaxDepth >= 1)
3621	{
3622	int rc2 = pgmR3DumpHierarchyHCPaePD(pVM, Pdpe.u & X86_PDPE_PG_MASK, u64Address + ((uint64_t)i << X86_PDPT_SHIFT),
3623	cr4, fLongMode, cMaxDepth - 1, pHlp);
3624	if (rc2 < rc && VBOX_SUCCESS(rc))
3625	rc = rc2;
3626	}
3627	}
3628	}
3629	return rc;
3630	}
3631
3632
3633	/**
3634	* Dumps a 32-bit shadow page table.
3635	*
3636	* @returns VBox status code (VINF_SUCCESS).
3637	* @param pVM The VM handle.
3638	* @param HCPhys The physical address of the table.
3639	* @param cr4 The CR4, PSE is currently used.
3640	* @param cMaxDepth The maxium depth.
3641	* @param pHlp Pointer to the output functions.
3642	*/
3643	static int pgmR3DumpHierarchyHcPaePML4(PVM pVM, RTHCPHYS HCPhys, uint32_t cr4, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
3644	{
3645	PX86PML4 pPML4 = (PX86PML4)MMPagePhys2Page(pVM, HCPhys);
3646	if (!pPML4)
3647	{
3648	pHlp->pfnPrintf(pHlp, "Page map level 4 at HCPhys=%#VHp was not found in the page pool!\n", HCPhys);
3649	return VERR_INVALID_PARAMETER;
3650	}
3651
3652	int rc = VINF_SUCCESS;
3653	for (unsigned i = 0; i < ELEMENTS(pPML4->a); i++)
3654	{
3655	X86PML4E Pml4e = pPML4->a[i];
3656	if (Pml4e.n.u1Present)
3657	{
3658	uint64_t u64Address = ((uint64_t)i << X86_PML4_SHIFT) \| (((uint64_t)i >> (X86_PML4_SHIFT - X86_PDPT_SHIFT - 1)) * 0xffff000000000000ULL);
3659	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a p ? /
3660	"%016llx 0 \| P %c %c %c %c %c %s %s %s %s .. %c%c%c %016llx\n",
3661	u64Address,
3662	Pml4e.n.u1Write ? 'W' : 'R',
3663	Pml4e.n.u1User ? 'U' : 'S',
3664	Pml4e.n.u1Accessed ? 'A' : '-',
3665	Pml4e.n.u3Reserved & 1? '?' : '.', /* ignored */
3666	Pml4e.n.u3Reserved & 4? '!' : '.', /* mbz */
3667	Pml4e.n.u1WriteThru ? "WT" : "--",
3668	Pml4e.n.u1CacheDisable? "CD" : "--",
3669	Pml4e.n.u3Reserved & 2? "!" : "..",/* mbz */
3670	Pml4e.n.u1NoExecute ? "NX" : "--",
3671	Pml4e.u & RT_BIT(9) ? '1' : '0',
3672	Pml4e.u & PGM_PLXFLAGS_PERMANENT ? 'p' : '-',
3673	Pml4e.u & RT_BIT(11) ? '1' : '0',
3674	Pml4e.u & X86_PML4E_PG_MASK);
3675
3676	if (cMaxDepth >= 1)
3677	{
3678	int rc2 = pgmR3DumpHierarchyHCPaePDPT(pVM, Pml4e.u & X86_PML4E_PG_MASK, u64Address, cr4, true, cMaxDepth - 1, pHlp);
3679	if (rc2 < rc && VBOX_SUCCESS(rc))
3680	rc = rc2;
3681	}
3682	}
3683	}
3684	return rc;
3685	}
3686
3687
3688	/**
3689	* Dumps a 32-bit shadow page table.
3690	*
3691	* @returns VBox status code (VINF_SUCCESS).
3692	* @param pVM The VM handle.
3693	* @param pPT Pointer to the page table.
3694	* @param u32Address The virtual address this table starts at.
3695	* @param pHlp Pointer to the output functions.
3696	*/
3697	int pgmR3DumpHierarchyHC32BitPT(PVM pVM, PX86PT pPT, uint32_t u32Address, PCDBGFINFOHLP pHlp)
3698	{
3699	for (unsigned i = 0; i < ELEMENTS(pPT->a); i++)
3700	{
3701	X86PTE Pte = pPT->a[i];
3702	if (Pte.n.u1Present)
3703	{
3704	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a m d /
3705	"%08x 1 \| P %c %c %c %c %c %s %s %s .. 4K %c%c%c %08x\n",
3706	u32Address + (i << X86_PT_SHIFT),
3707	Pte.n.u1Write ? 'W' : 'R',
3708	Pte.n.u1User ? 'U' : 'S',
3709	Pte.n.u1Accessed ? 'A' : '-',
3710	Pte.n.u1Dirty ? 'D' : '-',
3711	Pte.n.u1Global ? 'G' : '-',
3712	Pte.n.u1WriteThru ? "WT" : "--",
3713	Pte.n.u1CacheDisable? "CD" : "--",
3714	Pte.n.u1PAT ? "AT" : "--",
3715	Pte.u & PGM_PTFLAGS_TRACK_DIRTY ? 'd' : '-',
3716	Pte.u & RT_BIT(10) ? '1' : '0',
3717	Pte.u & PGM_PTFLAGS_CSAM_VALIDATED ? 'v' : '-',
3718	Pte.u & X86_PDE_PG_MASK);
3719	}
3720	}
3721	return VINF_SUCCESS;
3722	}
3723
3724
3725	/**
3726	* Dumps a 32-bit shadow page directory and page tables.
3727	*
3728	* @returns VBox status code (VINF_SUCCESS).
3729	* @param pVM The VM handle.
3730	* @param cr3 The root of the hierarchy.
3731	* @param cr4 The CR4, PSE is currently used.
3732	* @param cMaxDepth How deep into the hierarchy the dumper should go.
3733	* @param pHlp Pointer to the output functions.
3734	*/
3735	int pgmR3DumpHierarchyHC32BitPD(PVM pVM, uint32_t cr3, uint32_t cr4, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
3736	{
3737	PX86PD pPD = (PX86PD)MMPagePhys2Page(pVM, cr3 & X86_CR3_PAGE_MASK);
3738	if (!pPD)
3739	{
3740	pHlp->pfnPrintf(pHlp, "Page directory at %#x was not found in the page pool!\n", cr3 & X86_CR3_PAGE_MASK);
3741	return VERR_INVALID_PARAMETER;
3742	}
3743
3744	int rc = VINF_SUCCESS;
3745	for (unsigned i = 0; i < ELEMENTS(pPD->a); i++)
3746	{
3747	X86PDE Pde = pPD->a[i];
3748	if (Pde.n.u1Present)
3749	{
3750	const uint32_t u32Address = i << X86_PD_SHIFT;
3751	if ((cr4 & X86_CR4_PSE) && Pde.b.u1Size)
3752	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a m d /
3753	"%08x 0 \| P %c %c %c %c %c %s %s %s .. 4M %c%c%c %08x\n",
3754	u32Address,
3755	Pde.b.u1Write ? 'W' : 'R',
3756	Pde.b.u1User ? 'U' : 'S',
3757	Pde.b.u1Accessed ? 'A' : '-',
3758	Pde.b.u1Dirty ? 'D' : '-',
3759	Pde.b.u1Global ? 'G' : '-',
3760	Pde.b.u1WriteThru ? "WT" : "--",
3761	Pde.b.u1CacheDisable? "CD" : "--",
3762	Pde.b.u1PAT ? "AT" : "--",
3763	Pde.u & RT_BIT_64(9) ? '1' : '0',
3764	Pde.u & PGM_PDFLAGS_MAPPING ? 'm' : '-',
3765	Pde.u & PGM_PDFLAGS_TRACK_DIRTY ? 'd' : '-',
3766	Pde.u & X86_PDE4M_PG_MASK);
3767	else
3768	{
3769	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a m d /
3770	"%08x 0 \| P %c %c %c %c %c %s %s .. .. 4K %c%c%c %08x\n",
3771	u32Address,
3772	Pde.n.u1Write ? 'W' : 'R',
3773	Pde.n.u1User ? 'U' : 'S',
3774	Pde.n.u1Accessed ? 'A' : '-',
3775	Pde.n.u1Reserved0 ? '?' : '.', /* ignored */
3776	Pde.n.u1Reserved1 ? '?' : '.', /* ignored */
3777	Pde.n.u1WriteThru ? "WT" : "--",
3778	Pde.n.u1CacheDisable? "CD" : "--",
3779	Pde.u & RT_BIT_64(9) ? '1' : '0',
3780	Pde.u & PGM_PDFLAGS_MAPPING ? 'm' : '-',
3781	Pde.u & PGM_PDFLAGS_TRACK_DIRTY ? 'd' : '-',
3782	Pde.u & X86_PDE_PG_MASK);
3783	if (cMaxDepth >= 1)
3784	{
3785	/** @todo what about using the page pool for mapping PTs? */
3786	RTHCPHYS HCPhys = Pde.u & X86_PDE_PG_MASK;
3787	PX86PT pPT = NULL;
3788	if (!(Pde.u & PGM_PDFLAGS_MAPPING))
3789	pPT = (PX86PT)MMPagePhys2Page(pVM, HCPhys);
3790	else
3791	{
3792	for (PPGMMAPPING pMap = pVM->pgm.s.pMappingsR3; pMap; pMap = pMap->pNextR3)
3793	if (u32Address - pMap->GCPtr < pMap->cb)
3794	{
3795	int iPDE = (u32Address - pMap->GCPtr) >> X86_PD_SHIFT;
3796	if (pMap->aPTs[iPDE].HCPhysPT != HCPhys)
3797	pHlp->pfnPrintf(pHlp, "%08x error! Mapping error! PT %d has HCPhysPT=%VHp not %VHp is in the PD.\n",
3798	u32Address, iPDE, pMap->aPTs[iPDE].HCPhysPT, HCPhys);
3799	pPT = pMap->aPTs[iPDE].pPTR3;
3800	}
3801	}
3802	int rc2 = VERR_INVALID_PARAMETER;
3803	if (pPT)
3804	rc2 = pgmR3DumpHierarchyHC32BitPT(pVM, pPT, u32Address, pHlp);
3805	else
3806	pHlp->pfnPrintf(pHlp, "%08x error! Page table at %#x was not found in the page pool!\n", u32Address, HCPhys);
3807	if (rc2 < rc && VBOX_SUCCESS(rc))
3808	rc = rc2;
3809	}
3810	}
3811	}
3812	}
3813
3814	return rc;
3815	}
3816
3817
3818	/**
3819	* Dumps a 32-bit shadow page table.
3820	*
3821	* @returns VBox status code (VINF_SUCCESS).
3822	* @param pVM The VM handle.
3823	* @param pPT Pointer to the page table.
3824	* @param u32Address The virtual address this table starts at.
3825	* @param PhysSearch Address to search for.
3826	*/
3827	int pgmR3DumpHierarchyGC32BitPT(PVM pVM, PX86PT pPT, uint32_t u32Address, RTGCPHYS PhysSearch)
3828	{
3829	for (unsigned i = 0; i < ELEMENTS(pPT->a); i++)
3830	{
3831	X86PTE Pte = pPT->a[i];
3832	if (Pte.n.u1Present)
3833	{
3834	Log(( /P R S A D G WT CD AT NX 4M a m d /
3835	"%08x 1 \| P %c %c %c %c %c %s %s %s .. 4K %c%c%c %08x\n",
3836	u32Address + (i << X86_PT_SHIFT),
3837	Pte.n.u1Write ? 'W' : 'R',
3838	Pte.n.u1User ? 'U' : 'S',
3839	Pte.n.u1Accessed ? 'A' : '-',
3840	Pte.n.u1Dirty ? 'D' : '-',
3841	Pte.n.u1Global ? 'G' : '-',
3842	Pte.n.u1WriteThru ? "WT" : "--",
3843	Pte.n.u1CacheDisable? "CD" : "--",
3844	Pte.n.u1PAT ? "AT" : "--",
3845	Pte.u & PGM_PTFLAGS_TRACK_DIRTY ? 'd' : '-',
3846	Pte.u & RT_BIT(10) ? '1' : '0',
3847	Pte.u & PGM_PTFLAGS_CSAM_VALIDATED ? 'v' : '-',
3848	Pte.u & X86_PDE_PG_MASK));
3849
3850	if ((Pte.u & X86_PDE_PG_MASK) == PhysSearch)
3851	{
3852	uint64_t fPageShw = 0;
3853	RTHCPHYS pPhysHC = 0;
3854
3855	PGMShwGetPage(pVM, (RTGCPTR)(u32Address + (i << X86_PT_SHIFT)), &fPageShw, &pPhysHC);
3856	Log(("Found %VGp at %VGv -> flags=%llx\n", PhysSearch, (RTGCPTR)(u32Address + (i << X86_PT_SHIFT)), fPageShw));
3857	}
3858	}
3859	}
3860	return VINF_SUCCESS;
3861	}
3862
3863
3864	/**
3865	* Dumps a 32-bit guest page directory and page tables.
3866	*
3867	* @returns VBox status code (VINF_SUCCESS).
3868	* @param pVM The VM handle.
3869	* @param cr3 The root of the hierarchy.
3870	* @param cr4 The CR4, PSE is currently used.
3871	* @param PhysSearch Address to search for.
3872	*/
3873	PGMR3DECL(int) PGMR3DumpHierarchyGC(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCPHYS PhysSearch)
3874	{
3875	bool fLongMode = false;
3876	const unsigned cch = fLongMode ? 16 : 8; NOREF(cch);
3877	PX86PD pPD = 0;
3878
3879	int rc = PGM_GCPHYS_2_PTR(pVM, cr3 & X86_CR3_PAGE_MASK, &pPD);
3880	if (VBOX_FAILURE(rc) \|\| !pPD)
3881	{
3882	Log(("Page directory at %#x was not found in the page pool!\n", cr3 & X86_CR3_PAGE_MASK));
3883	return VERR_INVALID_PARAMETER;
3884	}
3885
3886	Log(("cr3=%08x cr4=%08x%s\n"
3887	"%-*s P - Present\n"
3888	"%-*s \| R/W - Read (0) / Write (1)\n"
3889	"%-*s \| \| U/S - User (1) / Supervisor (0)\n"
3890	"%-*s \| \| \| A - Accessed\n"
3891	"%-*s \| \| \| \| D - Dirty\n"
3892	"%-*s \| \| \| \| \| G - Global\n"
3893	"%-*s \| \| \| \| \| \| WT - Write thru\n"
3894	"%-*s \| \| \| \| \| \| \| CD - Cache disable\n"
3895	"%-*s \| \| \| \| \| \| \| \| AT - Attribute table (PAT)\n"
3896	"%-*s \| \| \| \| \| \| \| \| \| NX - No execute (K8)\n"
3897	"%-*s \| \| \| \| \| \| \| \| \| \| 4K/4M/2M - Page size.\n"
3898	"%-*s \| \| \| \| \| \| \| \| \| \| \| AVL - a=allocated; m=mapping; d=track dirty;\n"
3899	"%-*s \| \| \| \| \| \| \| \| \| \| \| \| p=permanent; v=validated;\n"
3900	"%-*s Level \| \| \| \| \| \| \| \| \| \| \| \| Page\n"
3901	/* xxxx n **** P R S A D G WT CD AT NX 4M AVL xxxxxxxxxxxxx
3902	- W U - - - -- -- -- -- -- 010 */
3903	, cr3, cr4, fLongMode ? " Long Mode" : "",
3904	cch, "", cch, "", cch, "", cch, "", cch, "", cch, "", cch, "",
3905	cch, "", cch, "", cch, "", cch, "", cch, "", cch, "", cch, "Address"));
3906
3907	for (unsigned i = 0; i < ELEMENTS(pPD->a); i++)
3908	{
3909	X86PDE Pde = pPD->a[i];
3910	if (Pde.n.u1Present)
3911	{
3912	const uint32_t u32Address = i << X86_PD_SHIFT;
3913
3914	if ((cr4 & X86_CR4_PSE) && Pde.b.u1Size)
3915	Log(( /P R S A D G WT CD AT NX 4M a m d /
3916	"%08x 0 \| P %c %c %c %c %c %s %s %s .. 4M %c%c%c %08x\n",
3917	u32Address,
3918	Pde.b.u1Write ? 'W' : 'R',
3919	Pde.b.u1User ? 'U' : 'S',
3920	Pde.b.u1Accessed ? 'A' : '-',
3921	Pde.b.u1Dirty ? 'D' : '-',
3922	Pde.b.u1Global ? 'G' : '-',
3923	Pde.b.u1WriteThru ? "WT" : "--",
3924	Pde.b.u1CacheDisable? "CD" : "--",
3925	Pde.b.u1PAT ? "AT" : "--",
3926	Pde.u & RT_BIT(9) ? '1' : '0',
3927	Pde.u & RT_BIT(10) ? '1' : '0',
3928	Pde.u & RT_BIT(11) ? '1' : '0',
3929	Pde.u & X86_PDE4M_PG_MASK));
3930	/** @todo PhysSearch */
3931	else
3932	{
3933	Log(( /P R S A D G WT CD AT NX 4M a m d /
3934	"%08x 0 \| P %c %c %c %c %c %s %s .. .. 4K %c%c%c %08x\n",
3935	u32Address,
3936	Pde.n.u1Write ? 'W' : 'R',
3937	Pde.n.u1User ? 'U' : 'S',
3938	Pde.n.u1Accessed ? 'A' : '-',
3939	Pde.n.u1Reserved0 ? '?' : '.', /* ignored */
3940	Pde.n.u1Reserved1 ? '?' : '.', /* ignored */
3941	Pde.n.u1WriteThru ? "WT" : "--",
3942	Pde.n.u1CacheDisable? "CD" : "--",
3943	Pde.u & RT_BIT(9) ? '1' : '0',
3944	Pde.u & RT_BIT(10) ? '1' : '0',
3945	Pde.u & RT_BIT(11) ? '1' : '0',
3946	Pde.u & X86_PDE_PG_MASK));
3947	////if (cMaxDepth >= 1)
3948	{
3949	/** @todo what about using the page pool for mapping PTs? */
3950	RTGCPHYS GCPhys = Pde.u & X86_PDE_PG_MASK;
3951	PX86PT pPT = NULL;
3952
3953	rc = PGM_GCPHYS_2_PTR(pVM, GCPhys, &pPT);
3954
3955	int rc2 = VERR_INVALID_PARAMETER;
3956	if (pPT)
3957	rc2 = pgmR3DumpHierarchyGC32BitPT(pVM, pPT, u32Address, PhysSearch);
3958	else
3959	Log(("%08x error! Page table at %#x was not found in the page pool!\n", u32Address, GCPhys));
3960	if (rc2 < rc && VBOX_SUCCESS(rc))
3961	rc = rc2;
3962	}
3963	}
3964	}
3965	}
3966
3967	return rc;
3968	}
3969
3970
3971	/**
3972	* Dumps a page table hierarchy use only physical addresses and cr4/lm flags.
3973	*
3974	* @returns VBox status code (VINF_SUCCESS).
3975	* @param pVM The VM handle.
3976	* @param cr3 The root of the hierarchy.
3977	* @param cr4 The cr4, only PAE and PSE is currently used.
3978	* @param fLongMode Set if long mode, false if not long mode.
3979	* @param cMaxDepth Number of levels to dump.
3980	* @param pHlp Pointer to the output functions.
3981	*/
3982	PGMR3DECL(int) PGMR3DumpHierarchyHC(PVM pVM, uint64_t cr3, uint64_t cr4, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
3983	{
3984	if (!pHlp)
3985	pHlp = DBGFR3InfoLogHlp();
3986	if (!cMaxDepth)
3987	return VINF_SUCCESS;
3988	const unsigned cch = fLongMode ? 16 : 8;
3989	pHlp->pfnPrintf(pHlp,
3990	"cr3=%08x cr4=%08x%s\n"
3991	"%-*s P - Present\n"
3992	"%-*s \| R/W - Read (0) / Write (1)\n"
3993	"%-*s \| \| U/S - User (1) / Supervisor (0)\n"
3994	"%-*s \| \| \| A - Accessed\n"
3995	"%-*s \| \| \| \| D - Dirty\n"
3996	"%-*s \| \| \| \| \| G - Global\n"
3997	"%-*s \| \| \| \| \| \| WT - Write thru\n"
3998	"%-*s \| \| \| \| \| \| \| CD - Cache disable\n"
3999	"%-*s \| \| \| \| \| \| \| \| AT - Attribute table (PAT)\n"
4000	"%-*s \| \| \| \| \| \| \| \| \| NX - No execute (K8)\n"
4001	"%-*s \| \| \| \| \| \| \| \| \| \| 4K/4M/2M - Page size.\n"
4002	"%-*s \| \| \| \| \| \| \| \| \| \| \| AVL - a=allocated; m=mapping; d=track dirty;\n"
4003	"%-*s \| \| \| \| \| \| \| \| \| \| \| \| p=permanent; v=validated;\n"
4004	"%-*s Level \| \| \| \| \| \| \| \| \| \| \| \| Page\n"
4005	/* xxxx n **** P R S A D G WT CD AT NX 4M AVL xxxxxxxxxxxxx
4006	- W U - - - -- -- -- -- -- 010 */
4007	, cr3, cr4, fLongMode ? " Long Mode" : "",
4008	cch, "", cch, "", cch, "", cch, "", cch, "", cch, "", cch, "",
4009	cch, "", cch, "", cch, "", cch, "", cch, "", cch, "", cch, "Address");
4010	if (cr4 & X86_CR4_PAE)
4011	{
4012	if (fLongMode)
4013	return pgmR3DumpHierarchyHcPaePML4(pVM, cr3 & X86_CR3_PAGE_MASK, cr4, cMaxDepth, pHlp);
4014	return pgmR3DumpHierarchyHCPaePDPT(pVM, cr3 & X86_CR3_PAE_PAGE_MASK, 0, cr4, false, cMaxDepth, pHlp);
4015	}
4016	return pgmR3DumpHierarchyHC32BitPD(pVM, cr3 & X86_CR3_PAGE_MASK, cr4, cMaxDepth, pHlp);
4017	}
4018
4019
4020
4021	#ifdef VBOX_WITH_DEBUGGER
4022	/**
4023	* The '.pgmram' command.
4024	*
4025	* @returns VBox status.
4026	* @param pCmd Pointer to the command descriptor (as registered).
4027	* @param pCmdHlp Pointer to command helper functions.
4028	* @param pVM Pointer to the current VM (if any).
4029	* @param paArgs Pointer to (readonly) array of arguments.
4030	* @param cArgs Number of arguments in the array.
4031	*/
4032	static DECLCALLBACK(int) pgmR3CmdRam(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4033	{
4034	/*
4035	* Validate input.
4036	*/
4037	if (!pVM)
4038	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4039	if (!pVM->pgm.s.pRamRangesGC)
4040	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Sorry, no Ram is registered.\n");
4041
4042	/*
4043	* Dump the ranges.
4044	*/
4045	int rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL, "From - To (incl) pvHC\n");
4046	PPGMRAMRANGE pRam;
4047	for (pRam = pVM->pgm.s.pRamRangesR3; pRam; pRam = pRam->pNextR3)
4048	{
4049	rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL,
4050	"%VGp - %VGp %p\n",
4051	pRam->GCPhys, pRam->GCPhysLast, pRam->pvHC);
4052	if (VBOX_FAILURE(rc))
4053	return rc;
4054	}
4055
4056	return VINF_SUCCESS;
4057	}
4058
4059
4060	/**
4061	* The '.pgmmap' command.
4062	*
4063	* @returns VBox status.
4064	* @param pCmd Pointer to the command descriptor (as registered).
4065	* @param pCmdHlp Pointer to command helper functions.
4066	* @param pVM Pointer to the current VM (if any).
4067	* @param paArgs Pointer to (readonly) array of arguments.
4068	* @param cArgs Number of arguments in the array.
4069	*/
4070	static DECLCALLBACK(int) pgmR3CmdMap(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4071	{
4072	/*
4073	* Validate input.
4074	*/
4075	if (!pVM)
4076	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4077	if (!pVM->pgm.s.pMappingsR3)
4078	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Sorry, no mappings are registered.\n");
4079
4080	/*
4081	* Print message about the fixedness of the mappings.
4082	*/
4083	int rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL, pVM->pgm.s.fMappingsFixed ? "The mappings are FIXED.\n" : "The mappings are FLOATING.\n");
4084	if (VBOX_FAILURE(rc))
4085	return rc;
4086
4087	/*
4088	* Dump the ranges.
4089	*/
4090	PPGMMAPPING pCur;
4091	for (pCur = pVM->pgm.s.pMappingsR3; pCur; pCur = pCur->pNextR3)
4092	{
4093	rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL,
4094	"%08x - %08x %s\n",
4095	pCur->GCPtr, pCur->GCPtrLast, pCur->pszDesc);
4096	if (VBOX_FAILURE(rc))
4097	return rc;
4098	}
4099
4100	return VINF_SUCCESS;
4101	}
4102
4103
4104	/**
4105	* The '.pgmsync' command.
4106	*
4107	* @returns VBox status.
4108	* @param pCmd Pointer to the command descriptor (as registered).
4109	* @param pCmdHlp Pointer to command helper functions.
4110	* @param pVM Pointer to the current VM (if any).
4111	* @param paArgs Pointer to (readonly) array of arguments.
4112	* @param cArgs Number of arguments in the array.
4113	*/
4114	static DECLCALLBACK(int) pgmR3CmdSync(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4115	{
4116	/*
4117	* Validate input.
4118	*/
4119	if (!pVM)
4120	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4121
4122	/*
4123	* Force page directory sync.
4124	*/
4125	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
4126
4127	int rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Forcing page directory sync.\n");
4128	if (VBOX_FAILURE(rc))
4129	return rc;
4130
4131	return VINF_SUCCESS;
4132	}
4133
4134
4135	#ifdef VBOX_STRICT
4136	/**
4137	* The '.pgmassertcr3' command.
4138	*
4139	* @returns VBox status.
4140	* @param pCmd Pointer to the command descriptor (as registered).
4141	* @param pCmdHlp Pointer to command helper functions.
4142	* @param pVM Pointer to the current VM (if any).
4143	* @param paArgs Pointer to (readonly) array of arguments.
4144	* @param cArgs Number of arguments in the array.
4145	*/
4146	static DECLCALLBACK(int) pgmR3CmdAssertCR3(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4147	{
4148	/*
4149	* Validate input.
4150	*/
4151	if (!pVM)
4152	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4153
4154	int rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Checking shadow CR3 page tables for consistency.\n");
4155	if (VBOX_FAILURE(rc))
4156	return rc;
4157
4158	PGMAssertCR3(pVM, CPUMGetGuestCR3(pVM), CPUMGetGuestCR4(pVM));
4159
4160	return VINF_SUCCESS;
4161	}
4162	#endif
4163
4164	/**
4165	* The '.pgmsyncalways' command.
4166	*
4167	* @returns VBox status.
4168	* @param pCmd Pointer to the command descriptor (as registered).
4169	* @param pCmdHlp Pointer to command helper functions.
4170	* @param pVM Pointer to the current VM (if any).
4171	* @param paArgs Pointer to (readonly) array of arguments.
4172	* @param cArgs Number of arguments in the array.
4173	*/
4174	static DECLCALLBACK(int) pgmR3CmdSyncAlways(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4175	{
4176	/*
4177	* Validate input.
4178	*/
4179	if (!pVM)
4180	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4181
4182	/*
4183	* Force page directory sync.
4184	*/
4185	if (pVM->pgm.s.fSyncFlags & PGM_SYNC_ALWAYS)
4186	{
4187	ASMAtomicAndU32(&pVM->pgm.s.fSyncFlags, ~PGM_SYNC_ALWAYS);
4188	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Disabled permanent forced page directory syncing.\n");
4189	}
4190	else
4191	{
4192	ASMAtomicOrU32(&pVM->pgm.s.fSyncFlags, PGM_SYNC_ALWAYS);
4193	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
4194	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Enabled permanent forced page directory syncing.\n");
4195	}
4196	}
4197
4198	#endif
4199
4200	/**
4201	* pvUser argument of the pgmR3CheckIntegrity*Node callbacks.
4202	*/
4203	typedef struct PGMCHECKINTARGS
4204	{
4205	bool fLeftToRight; /*< true: left-to-right; false: right-to-left. /
4206	PPGMPHYSHANDLER pPrevPhys;
4207	PPGMVIRTHANDLER pPrevVirt;
4208	PPGMPHYS2VIRTHANDLER pPrevPhys2Virt;
4209	PVM pVM;
4210	} PGMCHECKINTARGS, *PPGMCHECKINTARGS;
4211
4212	/**
4213	* Validate a node in the physical handler tree.
4214	*
4215	* @returns 0 on if ok, other wise 1.
4216	* @param pNode The handler node.
4217	* @param pvUser pVM.
4218	*/
4219	static DECLCALLBACK(int) pgmR3CheckIntegrityPhysHandlerNode(PAVLROGCPHYSNODECORE pNode, void *pvUser)
4220	{
4221	PPGMCHECKINTARGS pArgs = (PPGMCHECKINTARGS)pvUser;
4222	PPGMPHYSHANDLER pCur = (PPGMPHYSHANDLER)pNode;
4223	AssertReleaseReturn(!((uintptr_t)pCur & 7), 1);
4224	AssertReleaseMsg(pCur->Core.Key <= pCur->Core.KeyLast,("pCur=%p %VGp-%VGp %s\n", pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
4225	AssertReleaseMsg( !pArgs->pPrevPhys
4226	\|\| (pArgs->fLeftToRight ? pArgs->pPrevPhys->Core.KeyLast < pCur->Core.Key : pArgs->pPrevPhys->Core.KeyLast > pCur->Core.Key),
4227	("pPrevPhys=%p %VGp-%VGp %s\n"
4228	" pCur=%p %VGp-%VGp %s\n",
4229	pArgs->pPrevPhys, pArgs->pPrevPhys->Core.Key, pArgs->pPrevPhys->Core.KeyLast, pArgs->pPrevPhys->pszDesc,
4230	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
4231	pArgs->pPrevPhys = pCur;
4232	return 0;
4233	}
4234
4235
4236	/**
4237	* Validate a node in the virtual handler tree.
4238	*
4239	* @returns 0 on if ok, other wise 1.
4240	* @param pNode The handler node.
4241	* @param pvUser pVM.
4242	*/
4243	static DECLCALLBACK(int) pgmR3CheckIntegrityVirtHandlerNode(PAVLROGCPTRNODECORE pNode, void *pvUser)
4244	{
4245	PPGMCHECKINTARGS pArgs = (PPGMCHECKINTARGS)pvUser;
4246	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)pNode;
4247	AssertReleaseReturn(!((uintptr_t)pCur & 7), 1);
4248	AssertReleaseMsg(pCur->Core.Key <= pCur->Core.KeyLast,("pCur=%p %VGv-%VGv %s\n", pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
4249	AssertReleaseMsg( !pArgs->pPrevVirt
4250	\|\| (pArgs->fLeftToRight ? pArgs->pPrevVirt->Core.KeyLast < pCur->Core.Key : pArgs->pPrevVirt->Core.KeyLast > pCur->Core.Key),
4251	("pPrevVirt=%p %VGv-%VGv %s\n"
4252	" pCur=%p %VGv-%VGv %s\n",
4253	pArgs->pPrevVirt, pArgs->pPrevVirt->Core.Key, pArgs->pPrevVirt->Core.KeyLast, pArgs->pPrevVirt->pszDesc,
4254	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
4255	for (unsigned iPage = 0; iPage < pCur->cPages; iPage++)
4256	{
4257	AssertReleaseMsg(pCur->aPhysToVirt[iPage].offVirtHandler == -RT_OFFSETOF(PGMVIRTHANDLER, aPhysToVirt[iPage]),
4258	("pCur=%p %VGv-%VGv %s\n"
4259	"iPage=%d offVirtHandle=%#x expected %#x\n",
4260	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc,
4261	iPage, pCur->aPhysToVirt[iPage].offVirtHandler, -RT_OFFSETOF(PGMVIRTHANDLER, aPhysToVirt[iPage])));
4262	}
4263	pArgs->pPrevVirt = pCur;
4264	return 0;
4265	}
4266
4267
4268	/**
4269	* Validate a node in the virtual handler tree.
4270	*
4271	* @returns 0 on if ok, other wise 1.
4272	* @param pNode The handler node.
4273	* @param pvUser pVM.
4274	*/
4275	static DECLCALLBACK(int) pgmR3CheckIntegrityPhysToVirtHandlerNode(PAVLROGCPHYSNODECORE pNode, void *pvUser)
4276	{
4277	PPGMCHECKINTARGS pArgs = (PPGMCHECKINTARGS)pvUser;
4278	PPGMPHYS2VIRTHANDLER pCur = (PPGMPHYS2VIRTHANDLER)pNode;
4279	AssertReleaseMsgReturn(!((uintptr_t)pCur & 3), ("\n"), 1);
4280	AssertReleaseMsgReturn(!(pCur->offVirtHandler & 3), ("\n"), 1);
4281	AssertReleaseMsg(pCur->Core.Key <= pCur->Core.KeyLast,("pCur=%p %VGp-%VGp\n", pCur, pCur->Core.Key, pCur->Core.KeyLast));
4282	AssertReleaseMsg( !pArgs->pPrevPhys2Virt
4283	\|\| (pArgs->fLeftToRight ? pArgs->pPrevPhys2Virt->Core.KeyLast < pCur->Core.Key : pArgs->pPrevPhys2Virt->Core.KeyLast > pCur->Core.Key),
4284	("pPrevPhys2Virt=%p %VGp-%VGp\n"
4285	" pCur=%p %VGp-%VGp\n",
4286	pArgs->pPrevPhys2Virt, pArgs->pPrevPhys2Virt->Core.Key, pArgs->pPrevPhys2Virt->Core.KeyLast,
4287	pCur, pCur->Core.Key, pCur->Core.KeyLast));
4288	AssertReleaseMsg( !pArgs->pPrevPhys2Virt
4289	\|\| (pArgs->fLeftToRight ? pArgs->pPrevPhys2Virt->Core.KeyLast < pCur->Core.Key : pArgs->pPrevPhys2Virt->Core.KeyLast > pCur->Core.Key),
4290	("pPrevPhys2Virt=%p %VGp-%VGp\n"
4291	" pCur=%p %VGp-%VGp\n",
4292	pArgs->pPrevPhys2Virt, pArgs->pPrevPhys2Virt->Core.Key, pArgs->pPrevPhys2Virt->Core.KeyLast,
4293	pCur, pCur->Core.Key, pCur->Core.KeyLast));
4294	AssertReleaseMsg((pCur->offNextAlias & (PGMPHYS2VIRTHANDLER_IN_TREE \| PGMPHYS2VIRTHANDLER_IS_HEAD)) == (PGMPHYS2VIRTHANDLER_IN_TREE \| PGMPHYS2VIRTHANDLER_IS_HEAD),
4295	("pCur=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4296	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias));
4297	if (pCur->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK)
4298	{
4299	PPGMPHYS2VIRTHANDLER pCur2 = pCur;
4300	for (;;)
4301	{
4302	pCur2 = (PPGMPHYS2VIRTHANDLER)((intptr_t)pCur + (pCur->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK));
4303	AssertReleaseMsg(pCur2 != pCur,
4304	(" pCur=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4305	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias));
4306	AssertReleaseMsg((pCur2->offNextAlias & (PGMPHYS2VIRTHANDLER_IN_TREE \| PGMPHYS2VIRTHANDLER_IS_HEAD)) == PGMPHYS2VIRTHANDLER_IN_TREE,
4307	(" pCur=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
4308	"pCur2=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4309	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias,
4310	pCur2, pCur2->Core.Key, pCur2->Core.KeyLast, pCur2->offVirtHandler, pCur2->offNextAlias));
4311	AssertReleaseMsg((pCur2->Core.Key ^ pCur->Core.Key) < PAGE_SIZE,
4312	(" pCur=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
4313	"pCur2=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4314	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias,
4315	pCur2, pCur2->Core.Key, pCur2->Core.KeyLast, pCur2->offVirtHandler, pCur2->offNextAlias));
4316	AssertReleaseMsg((pCur2->Core.KeyLast ^ pCur->Core.KeyLast) < PAGE_SIZE,
4317	(" pCur=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
4318	"pCur2=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4319	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias,
4320	pCur2, pCur2->Core.Key, pCur2->Core.KeyLast, pCur2->offVirtHandler, pCur2->offNextAlias));
4321	if (!(pCur2->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK))
4322	break;
4323	}
4324	}
4325
4326	pArgs->pPrevPhys2Virt = pCur;
4327	return 0;
4328	}
4329
4330
4331	/**
4332	* Perform an integrity check on the PGM component.
4333	*
4334	* @returns VINF_SUCCESS if everything is fine.
4335	* @returns VBox error status after asserting on integrity breach.
4336	* @param pVM The VM handle.
4337	*/
4338	PDMR3DECL(int) PGMR3CheckIntegrity(PVM pVM)
4339	{
4340	AssertReleaseReturn(pVM->pgm.s.offVM, VERR_INTERNAL_ERROR);
4341
4342	/*
4343	* Check the trees.
4344	*/
4345	int cErrors = 0;
4346	const static PGMCHECKINTARGS s_LeftToRight = { true, NULL, NULL, NULL, pVM };
4347	const static PGMCHECKINTARGS s_RightToLeft = { false, NULL, NULL, NULL, pVM };
4348	PGMCHECKINTARGS Args = s_LeftToRight;
4349	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesHC->PhysHandlers, true, pgmR3CheckIntegrityPhysHandlerNode, &Args);
4350	Args = s_RightToLeft;
4351	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesHC->PhysHandlers, false, pgmR3CheckIntegrityPhysHandlerNode, &Args);
4352	Args = s_LeftToRight;
4353	cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesHC->VirtHandlers, true, pgmR3CheckIntegrityVirtHandlerNode, &Args);
4354	Args = s_RightToLeft;
4355	cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesHC->VirtHandlers, false, pgmR3CheckIntegrityVirtHandlerNode, &Args);
4356	Args = s_LeftToRight;
4357	cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesHC->HyperVirtHandlers, true, pgmR3CheckIntegrityVirtHandlerNode, &Args);
4358	Args = s_RightToLeft;
4359	cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesHC->HyperVirtHandlers, false, pgmR3CheckIntegrityVirtHandlerNode, &Args);
4360	Args = s_LeftToRight;
4361	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesHC->PhysToVirtHandlers, true, pgmR3CheckIntegrityPhysToVirtHandlerNode, &Args);
4362	Args = s_RightToLeft;
4363	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesHC->PhysToVirtHandlers, false, pgmR3CheckIntegrityPhysToVirtHandlerNode, &Args);
4364
4365	return !cErrors ? VINF_SUCCESS : VERR_INTERNAL_ERROR;
4366	}
4367
4368
4369	/**
4370	* Inform PGM if we want all mappings to be put into the shadow page table. (necessary for e.g. VMX)
4371	*
4372	* @returns VBox status code.
4373	* @param pVM VM handle.
4374	* @param fEnable Enable or disable shadow mappings
4375	*/
4376	PGMR3DECL(int) PGMR3ChangeShwPDMappings(PVM pVM, bool fEnable)
4377	{
4378	pVM->pgm.s.fDisableMappings = !fEnable;
4379
4380	uint32_t cb;
4381	int rc = PGMR3MappingsSize(pVM, &cb);
4382	AssertRCReturn(rc, rc);
4383
4384	/* Pretend the mappings are now fixed; to force a refresh of the reserved PDEs. */
4385	rc = PGMR3MappingsFix(pVM, MM_HYPER_AREA_ADDRESS, cb);
4386	AssertRCReturn(rc, rc);
4387
4388	return VINF_SUCCESS;
4389	}

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source: vbox/trunk/src/VBox/VMM/PGM.cpp@ 11162

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