PGM.cpp@ 1224

Last change on this file since 1224 was 1210, checked in by vboxsync, 18 years ago
Added PGMR3ChangeShwPDMappings. Added VMX/SVM test case.
Property svn:eol-style set to `native` Property svn:keywords set to `Id`
File size: 157.3 KB

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1	/* $Id: PGM.cpp 1210 2007-03-05 12:36:53Z vboxsync $ */
2	/** @file
3	* PGM - Page Manager and Monitor. (Mixing stuff here, not good?)
4	*/
5
6	/*
7	* Copyright (C) 2006 InnoTek Systemberatung GmbH
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License as published by the Free Software Foundation,
13	* in version 2 as it comes in the "COPYING" file of the VirtualBox OSE
14	* distribution. VirtualBox OSE is distributed in the hope that it will
15	* be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* If you received this file as part of a commercial VirtualBox
18	* distribution, then only the terms of your commercial VirtualBox
19	* license agreement apply instead of the previous paragraph.
20	*/
21
22
23	/** @page pg_pgm PGM - The Page Manager and Monitor
24	*
25	*
26	*
27	* @section sec_pg_modes Paging Modes
28	*
29	* There are three memory contexts: Host Context (HC), Guest Context (GC)
30	* and intermediate context. When talking about paging HC can also be refered to
31	* as "host paging", and GC refered to as "shadow paging".
32	*
33	* We define three basic paging modes: 32-bit, PAE and AMD64. The host paging mode
34	* is defined by the host operating system. The mode used in the shadow paging mode
35	* depends on the host paging mode and what the mode the guest is currently in. The
36	* following relation between the two is defined:
37	*
38	* @verbatim
39	Host > 32-bit \| PAE \| AMD64 \|
40	Guest \| \| \| \|
41	==v================================
42	32-bit 32-bit PAE PAE
43	-------\|--------\|--------\|--------\|
44	PAE PAE PAE PAE
45	-------\|--------\|--------\|--------\|
46	AMD64 AMD64 AMD64 AMD64
47	-------\|--------\|--------\|--------\| @endverbatim
48	*
49	* All configuration except those in the diagonal (upper left) are expected to
50	* require special effort from the switcher (i.e. a bit slower).
51	*
52	*
53	*
54	*
55	* @section sec_pg_shw The Shadow Memory Context
56	*
57	*
58	* [..]
59	*
60	* Because of guest context mappings requires PDPTR and PML4 entries to allow
61	* writing on AMD64, the two upper levels will have fixed flags whatever the
62	* guest is thinking of using there. So, when shadowing the PD level we will
63	* calculate the effective flags of PD and all the higher levels. In legacy
64	* PAE mode this only applies to the PWT and PCD bits (the rest are
65	* ignored/reserved/MBZ). We will ignore those bits for the present.
66	*
67	*
68	*
69	* @section sec_pg_int The Intermediate Memory Context
70	*
71	* The world switch goes thru an intermediate memory context which purpose it is
72	* to provide different mappings of the switcher code. All guest mappings are also
73	* present in this context.
74	*
75	* The switcher code is mapped at the same location as on the host, at an
76	* identity mapped location (physical equals virtual address), and at the
77	* hypervisor location.
78	*
79	* PGM maintain page tables for 32-bit, PAE and AMD64 paging modes. This
80	* simplifies switching guest CPU mode and consistency at the cost of more
81	* code to do the work. All memory use for those page tables is located below
82	* 4GB (this includes page tables for guest context mappings).
83	*
84	*
85	* @subsection subsec_pg_int_gc Guest Context Mappings
86	*
87	* During assignment and relocation of a guest context mapping the intermediate
88	* memory context is used to verify the new location.
89	*
90	* Guest context mappings are currently restricted to below 4GB, for reasons
91	* of simplicity. This may change when we implement AMD64 support.
92	*
93	*
94	*
95	*
96	* @section sec_pg_misc Misc
97	*
98	* @subsection subsec_pg_misc_diff Differences Between Legacy PAE and Long Mode PAE
99	*
100	* The differences between legacy PAE and long mode PAE are:
101	* -# PDPE bits 1, 2, 5 and 6 are defined differently. In leagcy mode they are
102	* all marked down as must-be-zero, while in long mode 1, 2 and 5 have the
103	* usual meanings while 6 is ignored (AMD). This means that upon switching to
104	* legacy PAE mode we'll have to clear these bits and when going to long mode
105	* they must be set. This applies to both intermediate and shadow contexts,
106	* however we don't need to do it for the intermediate one since we're
107	* executing with CR0.WP at that time.
108	* -# CR3 allows a 32-byte aligned address in legacy mode, while in long mode
109	* a page aligned one is required.
110	*/
111
112
113
114	/** Saved state data unit version. */
115	#define PGM_SAVED_STATE_VERSION 5
116
117	/*******************************************************************************
118	* Header Files *
119	*******************************************************************************/
120	#define LOG_GROUP LOG_GROUP_PGM
121	#include <VBox/dbgf.h>
122	#include <VBox/pgm.h>
123	#include <VBox/cpum.h>
124	#include <VBox/iom.h>
125	#include <VBox/sup.h>
126	#include <VBox/mm.h>
127	#include <VBox/pdm.h>
128	#include <VBox/em.h>
129	#include <VBox/stam.h>
130	#include <VBox/rem.h>
131	#include <VBox/dbgf.h>
132	#include <VBox/rem.h>
133	#include <VBox/selm.h>
134	#include <VBox/ssm.h>
135	#include "PGMInternal.h"
136	#include <VBox/vm.h>
137	#include <VBox/dbg.h>
138	#include <VBox/hwaccm.h>
139
140	#include <VBox/log.h>
141	#include <iprt/assert.h>
142	#include <iprt/alloc.h>
143	#include <iprt/asm.h>
144	#include <iprt/thread.h>
145	#include <iprt/string.h>
146	#include <VBox/param.h>
147	#include <VBox/err.h>
148
149
150
151	/*******************************************************************************
152	* Internal Functions *
153	*******************************************************************************/
154	static int pgmR3InitPaging(PVM pVM);
155	static DECLCALLBACK(void) pgmR3PhysInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
156	static DECLCALLBACK(void) pgmR3InfoMode(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
157	static DECLCALLBACK(void) pgmR3InfoCr3(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
158	static DECLCALLBACK(int) pgmR3RelocatePhysHandler(PAVLROGCPHYSNODECORE pNode, void *pvUser);
159	static DECLCALLBACK(int) pgmR3RelocateVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser);
160	static DECLCALLBACK(int) pgmR3Save(PVM pVM, PSSMHANDLE pSSM);
161	static DECLCALLBACK(int) pgmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version);
162	static int pgmR3ModeDataInit(PVM pVM, bool fResolveGCAndR0);
163	static void pgmR3ModeDataSwitch(PVM pVM, PGMMODE enmShw, PGMMODE enmGst);
164	static PGMMODE pgmR3CalcShadowMode(PGMMODE enmGuestMode, SUPPAGINGMODE enmHostMode, PGMMODE enmShadowMode, VMMSWITCHER *penmSwitcher);
165
166	#ifdef VBOX_WITH_STATISTICS
167	static void pgmR3InitStats(PVM pVM);
168	#endif
169
170	#ifdef VBOX_WITH_DEBUGGER
171	/** @todo all but the two last commands must be converted to 'info'. */
172	static DECLCALLBACK(int) pgmR3CmdRam(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
173	static DECLCALLBACK(int) pgmR3CmdMap(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
174	static DECLCALLBACK(int) pgmR3CmdSync(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
175	static DECLCALLBACK(int) pgmR3CmdSyncAlways(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
176	#endif
177
178
179	/*******************************************************************************
180	* Global Variables *
181	*******************************************************************************/
182	#ifdef VBOX_WITH_DEBUGGER
183	/** Command descriptors. */
184	static const DBGCCMD g_aCmds[] =
185	{
186	/* pszCmd, cArgsMin, cArgsMax, paArgDesc, cArgDescs, pResultDesc, fFlags, pfnHandler pszSyntax, ....pszDescription */
187	{ "pgmram", 0, 0, NULL, 0, NULL, 0, pgmR3CmdRam, "", "Display the ram ranges." },
188	{ "pgmmap", 0, 0, NULL, 0, NULL, 0, pgmR3CmdMap, "", "Display the mapping ranges." },
189	{ "pgmsync", 0, 0, NULL, 0, NULL, 0, pgmR3CmdSync, "", "Sync the CR3 page." },
190	{ "pgmsyncalways", 0, 0, NULL, 0, NULL, 0, pgmR3CmdSyncAlways, "", "Toggle permanent CR3 syncing." },
191	};
192	#endif
193
194
195
196
197	#if 1/// @todo ndef __AMD64__
198	/*
199	* Shadow - 32-bit mode
200	*/
201	#define PGM_SHW_TYPE PGM_TYPE_32BIT
202	#define PGM_SHW_NAME(name) PGM_SHW_NAME_32BIT(name)
203	#define PGM_SHW_NAME_GC_STR(name) PGM_SHW_NAME_GC_32BIT_STR(name)
204	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_32BIT_STR(name)
205	#include "PGMShw.h"
206
207	/* Guest - real mode */
208	#define PGM_GST_TYPE PGM_TYPE_REAL
209	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
210	#define PGM_GST_NAME_GC_STR(name) PGM_GST_NAME_GC_REAL_STR(name)
211	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
212	#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_REAL(name)
213	#define PGM_BTH_NAME_GC_STR(name) PGM_BTH_NAME_GC_32BIT_REAL_STR(name)
214	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_32BIT_REAL_STR(name)
215	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_PHYS
216	#include "PGMGst.h"
217	#include "PGMBth.h"
218	#undef BTH_PGMPOOLKIND_PT_FOR_PT
219	#undef PGM_BTH_NAME
220	#undef PGM_BTH_NAME_GC_STR
221	#undef PGM_BTH_NAME_R0_STR
222	#undef PGM_GST_TYPE
223	#undef PGM_GST_NAME
224	#undef PGM_GST_NAME_GC_STR
225	#undef PGM_GST_NAME_R0_STR
226
227	/* Guest - protected mode */
228	#define PGM_GST_TYPE PGM_TYPE_PROT
229	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
230	#define PGM_GST_NAME_GC_STR(name) PGM_GST_NAME_GC_PROT_STR(name)
231	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
232	#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_PROT(name)
233	#define PGM_BTH_NAME_GC_STR(name) PGM_BTH_NAME_GC_32BIT_PROT_STR(name)
234	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_32BIT_PROT_STR(name)
235	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_PHYS
236	#include "PGMGst.h"
237	#include "PGMBth.h"
238	#undef BTH_PGMPOOLKIND_PT_FOR_PT
239	#undef PGM_BTH_NAME
240	#undef PGM_BTH_NAME_GC_STR
241	#undef PGM_BTH_NAME_R0_STR
242	#undef PGM_GST_TYPE
243	#undef PGM_GST_NAME
244	#undef PGM_GST_NAME_GC_STR
245	#undef PGM_GST_NAME_R0_STR
246
247	/* Guest - 32-bit mode */
248	#define PGM_GST_TYPE PGM_TYPE_32BIT
249	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
250	#define PGM_GST_NAME_GC_STR(name) PGM_GST_NAME_GC_32BIT_STR(name)
251	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
252	#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_32BIT(name)
253	#define PGM_BTH_NAME_GC_STR(name) PGM_BTH_NAME_GC_32BIT_32BIT_STR(name)
254	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_32BIT_32BIT_STR(name)
255	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT
256	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB
257	#include "PGMGst.h"
258	#include "PGMBth.h"
259	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
260	#undef BTH_PGMPOOLKIND_PT_FOR_PT
261	#undef PGM_BTH_NAME
262	#undef PGM_BTH_NAME_GC_STR
263	#undef PGM_BTH_NAME_R0_STR
264	#undef PGM_GST_TYPE
265	#undef PGM_GST_NAME
266	#undef PGM_GST_NAME_GC_STR
267	#undef PGM_GST_NAME_R0_STR
268
269	#undef PGM_SHW_TYPE
270	#undef PGM_SHW_NAME
271	#undef PGM_SHW_NAME_GC_STR
272	#undef PGM_SHW_NAME_R0_STR
273	#endif /* !__AMD64__ */
274
275
276	/*
277	* Shadow - PAE mode
278	*/
279	#define PGM_SHW_TYPE PGM_TYPE_PAE
280	#define PGM_SHW_NAME(name) PGM_SHW_NAME_PAE(name)
281	#define PGM_SHW_NAME_GC_STR(name) PGM_SHW_NAME_GC_PAE_STR(name)
282	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_PAE_STR(name)
283	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_REAL(name)
284	#include "PGMShw.h"
285
286	/* Guest - real mode */
287	#define PGM_GST_TYPE PGM_TYPE_REAL
288	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
289	#define PGM_GST_NAME_GC_STR(name) PGM_GST_NAME_GC_REAL_STR(name)
290	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
291	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_REAL(name)
292	#define PGM_BTH_NAME_GC_STR(name) PGM_BTH_NAME_GC_PAE_REAL_STR(name)
293	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_REAL_STR(name)
294	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
295	#include "PGMBth.h"
296	#undef BTH_PGMPOOLKIND_PT_FOR_PT
297	#undef PGM_BTH_NAME
298	#undef PGM_BTH_NAME_GC_STR
299	#undef PGM_BTH_NAME_R0_STR
300	#undef PGM_GST_TYPE
301	#undef PGM_GST_NAME
302	#undef PGM_GST_NAME_GC_STR
303	#undef PGM_GST_NAME_R0_STR
304
305	/* Guest - protected mode */
306	#define PGM_GST_TYPE PGM_TYPE_PROT
307	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
308	#define PGM_GST_NAME_GC_STR(name) PGM_GST_NAME_GC_PROT_STR(name)
309	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
310	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_PROT(name)
311	#define PGM_BTH_NAME_GC_STR(name) PGM_BTH_NAME_GC_PAE_PROT_STR(name)
312	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_PROT_STR(name)
313	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
314	#include "PGMBth.h"
315	#undef BTH_PGMPOOLKIND_PT_FOR_PT
316	#undef PGM_BTH_NAME
317	#undef PGM_BTH_NAME_GC_STR
318	#undef PGM_BTH_NAME_R0_STR
319	#undef PGM_GST_TYPE
320	#undef PGM_GST_NAME
321	#undef PGM_GST_NAME_GC_STR
322	#undef PGM_GST_NAME_R0_STR
323
324	/* Guest - 32-bit mode */
325	#define PGM_GST_TYPE PGM_TYPE_32BIT
326	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
327	#define PGM_GST_NAME_GC_STR(name) PGM_GST_NAME_GC_32BIT_STR(name)
328	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
329	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_32BIT(name)
330	#define PGM_BTH_NAME_GC_STR(name) PGM_BTH_NAME_GC_PAE_32BIT_STR(name)
331	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_32BIT_STR(name)
332	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_32BIT_PT
333	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB
334	#include "PGMBth.h"
335	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
336	#undef BTH_PGMPOOLKIND_PT_FOR_PT
337	#undef PGM_BTH_NAME
338	#undef PGM_BTH_NAME_GC_STR
339	#undef PGM_BTH_NAME_R0_STR
340	#undef PGM_GST_TYPE
341	#undef PGM_GST_NAME
342	#undef PGM_GST_NAME_GC_STR
343	#undef PGM_GST_NAME_R0_STR
344
345	/* Guest - PAE mode */
346	#define PGM_GST_TYPE PGM_TYPE_PAE
347	#define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
348	#define PGM_GST_NAME_GC_STR(name) PGM_GST_NAME_GC_PAE_STR(name)
349	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PAE_STR(name)
350	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_PAE(name)
351	#define PGM_BTH_NAME_GC_STR(name) PGM_BTH_NAME_GC_PAE_PAE_STR(name)
352	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_PAE_STR(name)
353	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
354	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
355	#include "PGMGst.h"
356	#include "PGMBth.h"
357	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
358	#undef BTH_PGMPOOLKIND_PT_FOR_PT
359	#undef PGM_BTH_NAME
360	#undef PGM_BTH_NAME_GC_STR
361	#undef PGM_BTH_NAME_R0_STR
362	#undef PGM_GST_TYPE
363	#undef PGM_GST_NAME
364	#undef PGM_GST_NAME_GC_STR
365	#undef PGM_GST_NAME_R0_STR
366
367	#undef PGM_SHW_TYPE
368	#undef PGM_SHW_NAME
369	#undef PGM_SHW_NAME_GC_STR
370	#undef PGM_SHW_NAME_R0_STR
371
372
373	/*
374	* Shadow - AMD64 mode
375	*/
376	#define PGM_SHW_TYPE PGM_TYPE_AMD64
377	#define PGM_SHW_NAME(name) PGM_SHW_NAME_AMD64(name)
378	#define PGM_SHW_NAME_GC_STR(name) PGM_SHW_NAME_GC_AMD64_STR(name)
379	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_AMD64_STR(name)
380	#include "PGMShw.h"
381
382	/* Guest - real mode */
383	#define PGM_GST_TYPE PGM_TYPE_REAL
384	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
385	#define PGM_GST_NAME_GC_STR(name) PGM_GST_NAME_GC_REAL_STR(name)
386	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
387	#define PGM_BTH_NAME(name) PGM_BTH_NAME_AMD64_REAL(name)
388	#define PGM_BTH_NAME_GC_STR(name) PGM_BTH_NAME_GC_AMD64_REAL_STR(name)
389	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_AMD64_REAL_STR(name)
390	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
391	#include "PGMBth.h"
392	#undef BTH_PGMPOOLKIND_PT_FOR_PT
393	#undef PGM_BTH_NAME
394	#undef PGM_BTH_NAME_GC_STR
395	#undef PGM_BTH_NAME_R0_STR
396	#undef PGM_GST_TYPE
397	#undef PGM_GST_NAME
398	#undef PGM_GST_NAME_GC_STR
399	#undef PGM_GST_NAME_R0_STR
400
401	/* Guest - protected mode */
402	#define PGM_GST_TYPE PGM_TYPE_PROT
403	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
404	#define PGM_GST_NAME_GC_STR(name) PGM_GST_NAME_GC_PROT_STR(name)
405	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
406	#define PGM_BTH_NAME(name) PGM_BTH_NAME_AMD64_PROT(name)
407	#define PGM_BTH_NAME_GC_STR(name) PGM_BTH_NAME_GC_AMD64_PROT_STR(name)
408	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_AMD64_PROT_STR(name)
409	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
410	#include "PGMBth.h"
411	#undef BTH_PGMPOOLKIND_PT_FOR_PT
412	#undef PGM_BTH_NAME
413	#undef PGM_BTH_NAME_GC_STR
414	#undef PGM_BTH_NAME_R0_STR
415	#undef PGM_GST_TYPE
416	#undef PGM_GST_NAME
417	#undef PGM_GST_NAME_GC_STR
418	#undef PGM_GST_NAME_R0_STR
419
420	/* Guest - AMD64 mode */
421	#define PGM_GST_TYPE PGM_TYPE_AMD64
422	#define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
423	#define PGM_GST_NAME_GC_STR(name) PGM_GST_NAME_GC_AMD64_STR(name)
424	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_AMD64_STR(name)
425	#define PGM_BTH_NAME(name) PGM_BTH_NAME_AMD64_AMD64(name)
426	#define PGM_BTH_NAME_GC_STR(name) PGM_BTH_NAME_GC_AMD64_AMD64_STR(name)
427	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_AMD64_AMD64_STR(name)
428	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
429	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
430	#include "PGMGst.h"
431	#include "PGMBth.h"
432	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
433	#undef BTH_PGMPOOLKIND_PT_FOR_PT
434	#undef PGM_BTH_NAME
435	#undef PGM_BTH_NAME_GC_STR
436	#undef PGM_BTH_NAME_R0_STR
437	#undef PGM_GST_TYPE
438	#undef PGM_GST_NAME
439	#undef PGM_GST_NAME_GC_STR
440	#undef PGM_GST_NAME_R0_STR
441
442	#undef PGM_SHW_TYPE
443	#undef PGM_SHW_NAME
444	#undef PGM_SHW_NAME_GC_STR
445	#undef PGM_SHW_NAME_R0_STR
446
447
448
449
450	/**
451	* Initiates the paging of VM.
452	*
453	* @returns VBox status code.
454	* @param pVM Pointer to VM structure.
455	*/
456	PGMR3DECL(int) PGMR3Init(PVM pVM)
457	{
458	LogFlow(("PGMR3Init:\n"));
459
460	/*
461	* Assert alignment and sizes.
462	*/
463	AssertRelease(sizeof(pVM->pgm.s) <= sizeof(pVM->pgm.padding));
464
465	/*
466	* Init the structure.
467	*/
468	pVM->pgm.s.offVM = RT_OFFSETOF(VM, pgm.s);
469	pVM->pgm.s.enmShadowMode = PGMMODE_INVALID;
470	pVM->pgm.s.enmGuestMode = PGMMODE_INVALID;
471	pVM->pgm.s.enmHostMode = SUPPAGINGMODE_INVALID;
472	pVM->pgm.s.GCPhysCR3 = NIL_RTGCPHYS;
473	pVM->pgm.s.GCPhysGstCR3Monitored = NIL_RTGCPHYS;
474	pVM->pgm.s.fA20Enabled = true;
475	pVM->pgm.s.pGstPaePDPTRHC = NULL;
476	pVM->pgm.s.pGstPaePDPTRGC = 0;
477	for (unsigned i = 0; i < ELEMENTS(pVM->pgm.s.apGstPaePDsHC); i++)
478	{
479	pVM->pgm.s.apGstPaePDsHC[i] = NULL;
480	pVM->pgm.s.apGstPaePDsGC[i] = 0;
481	pVM->pgm.s.aGCPhysGstPaePDs[i] = NIL_RTGCPHYS;
482	}
483
484	/*
485	* Get the configured RAM size - to estimate saved state size.
486	*/
487	uint64_t cbRam;
488	int rc = CFGMR3QueryU64(CFGMR3GetRoot(pVM), "RamSize", &cbRam);
489	if (rc == VERR_CFGM_VALUE_NOT_FOUND)
490	cbRam = pVM->pgm.s.cbRamSize = 0;
491	else if (VBOX_SUCCESS(rc))
492	{
493	if (cbRam < PAGE_SIZE)
494	cbRam = 0;
495	cbRam = RT_ALIGN_64(cbRam, PAGE_SIZE);
496	pVM->pgm.s.cbRamSize = (RTUINT)cbRam;
497	}
498	else
499	{
500	AssertMsgFailed(("Configuration error: Failed to query integer \"RamSize\", rc=%Vrc.\n", rc));
501	return rc;
502	}
503
504	/*
505	* Register saved state data unit.
506	*/
507	rc = SSMR3RegisterInternal(pVM, "pgm", 1, PGM_SAVED_STATE_VERSION, (size_t)cbRam + sizeof(PGM),
508	NULL, pgmR3Save, NULL,
509	NULL, pgmR3Load, NULL);
510	if (VBOX_FAILURE(rc))
511	return rc;
512
513	/* Initialise PGM critical section. */
514	rc = PDMR3CritSectInit(pVM, &pVM->pgm.s.CritSect, "PGM");
515	AssertRCReturn(rc, rc);
516
517	/*
518	* Trees
519	*/
520	rc = MMHyperAlloc(pVM, sizeof(PGMTREES), 0, MM_TAG_PGM, (void **)&pVM->pgm.s.pTreesHC);
521	if (VBOX_SUCCESS(rc))
522	{
523	pVM->pgm.s.pTreesGC = MMHyperHC2GC(pVM, pVM->pgm.s.pTreesHC);
524
525	/*
526	* Init the paging.
527	*/
528	rc = pgmR3InitPaging(pVM);
529	}
530	if (VBOX_SUCCESS(rc))
531	{
532	/*
533	* Init the page pool.
534	*/
535	rc = pgmR3PoolInit(pVM);
536	}
537	if (VBOX_SUCCESS(rc))
538	{
539	/*
540	* Info & statistics
541	*/
542	DBGFR3InfoRegisterInternal(pVM, "mode",
543	"Shows the current paging mode. "
544	"Recognizes 'all', 'guest', 'shadow' and 'host' as arguments, defaulting to 'all' if nothing's given.",
545	pgmR3InfoMode);
546	DBGFR3InfoRegisterInternal(pVM, "pgmcr3",
547	"Dumps all the entries in the top level paging table. No arguments.",
548	pgmR3InfoCr3);
549	DBGFR3InfoRegisterInternal(pVM, "phys",
550	"Dumps all the physical address ranges. No arguments.",
551	pgmR3PhysInfo);
552	DBGFR3InfoRegisterInternal(pVM, "handlers",
553	"Dumps physical and virtual handlers. "
554	"Pass 'phys' or 'virt' as argument if only one kind is wanted.",
555	pgmR3InfoHandlers);
556
557	STAM_REL_REG(pVM, &pVM->pgm.s.cGuestModeChanges, STAMTYPE_COUNTER, "/PGM/cGuestModeChanges", STAMUNIT_OCCURENCES, "Number of guest mode changes.");
558	#ifdef VBOX_WITH_STATISTICS
559	pgmR3InitStats(pVM);
560	#endif
561	#ifdef VBOX_WITH_DEBUGGER
562	/*
563	* Debugger commands.
564	*/
565	static bool fRegisteredCmds = false;
566	if (!fRegisteredCmds)
567	{
568	int rc = DBGCRegisterCommands(&g_aCmds[0], ELEMENTS(g_aCmds));
569	if (VBOX_SUCCESS(rc))
570	fRegisteredCmds = true;
571	}
572	#endif
573	return VINF_SUCCESS;
574	}
575	/* No cleanup necessary, MM frees all memory. */
576
577	return rc;
578	}
579
580
581	/**
582	* Init paging.
583	*
584	* Since we need to check what mode the host is operating in before we can choose
585	* the right paging functions for the host we have to delay this until R0 has
586	* been initialized.
587	*
588	* @returns VBox status code.
589	* @param pVM VM handle.
590	*/
591	static int pgmR3InitPaging(PVM pVM)
592	{
593	/*
594	* Force a recalculation of modes and switcher so everyone gets notified.
595	*/
596	pVM->pgm.s.enmShadowMode = PGMMODE_INVALID;
597	pVM->pgm.s.enmGuestMode = PGMMODE_INVALID;
598	pVM->pgm.s.enmHostMode = SUPPAGINGMODE_INVALID;
599
600	/*
601	* Allocate static mapping space for whatever the cr3 register
602	* points to and in the case of PAE mode to the 4 PDs.
603	*/
604	int rc = MMR3HyperReserve(pVM, PAGE_SIZE * 5, "CR3 mapping", &pVM->pgm.s.GCPtrCR3Mapping);
605	if (VBOX_FAILURE(rc))
606	{
607	AssertMsgFailed(("Failed to reserve two pages for cr mapping in HMA, rc=%Vrc\n", rc));
608	return rc;
609	}
610	MMR3HyperReserve(pVM, PAGE_SIZE, "fence", NULL);
611
612	/*
613	* Allocate pages for the three possible intermediate contexts
614	* (AMD64, PAE and plain 32-Bit). We maintain all three contexts
615	* for the sake of simplicity. The AMD64 uses the PAE for the
616	* lower levels, making the total number of pages 11 (3 + 7 + 1).
617	*
618	* We assume that two page tables will be enought for the core code
619	* mappings (HC virtual and identity).
620	*/
621	pVM->pgm.s.pInterPD = (PX86PD)MMR3PageAllocLow(pVM);
622	pVM->pgm.s.apInterPTs[0] = (PX86PT)MMR3PageAllocLow(pVM);
623	pVM->pgm.s.apInterPTs[1] = (PX86PT)MMR3PageAllocLow(pVM);
624	pVM->pgm.s.apInterPaePTs[0] = (PX86PTPAE)MMR3PageAlloc(pVM);
625	pVM->pgm.s.apInterPaePTs[1] = (PX86PTPAE)MMR3PageAlloc(pVM);
626	pVM->pgm.s.apInterPaePDs[0] = (PX86PDPAE)MMR3PageAlloc(pVM);
627	pVM->pgm.s.apInterPaePDs[1] = (PX86PDPAE)MMR3PageAlloc(pVM);
628	pVM->pgm.s.apInterPaePDs[2] = (PX86PDPAE)MMR3PageAlloc(pVM);
629	pVM->pgm.s.apInterPaePDs[3] = (PX86PDPAE)MMR3PageAlloc(pVM);
630	pVM->pgm.s.pInterPaePDPTR = (PX86PDPTR)MMR3PageAllocLow(pVM);
631	pVM->pgm.s.pInterPaePDPTR64 = (PX86PDPTR)MMR3PageAllocLow(pVM);
632	pVM->pgm.s.pInterPaePML4 = (PX86PML4)MMR3PageAllocLow(pVM);
633	if ( !pVM->pgm.s.pInterPD
634	\|\| !pVM->pgm.s.apInterPTs[0]
635	\|\| !pVM->pgm.s.apInterPTs[1]
636	\|\| !pVM->pgm.s.apInterPaePTs[0]
637	\|\| !pVM->pgm.s.apInterPaePTs[1]
638	\|\| !pVM->pgm.s.apInterPaePDs[0]
639	\|\| !pVM->pgm.s.apInterPaePDs[1]
640	\|\| !pVM->pgm.s.apInterPaePDs[2]
641	\|\| !pVM->pgm.s.apInterPaePDs[3]
642	\|\| !pVM->pgm.s.pInterPaePDPTR
643	\|\| !pVM->pgm.s.pInterPaePDPTR64
644	\|\| !pVM->pgm.s.pInterPaePML4)
645	{
646	AssertMsgFailed(("Failed to allocate pages for the intermediate context!\n"));
647	return VERR_NO_PAGE_MEMORY;
648	}
649
650	pVM->pgm.s.HCPhysInterPD = MMPage2Phys(pVM, pVM->pgm.s.pInterPD);
651	AssertRelease(pVM->pgm.s.HCPhysInterPD != NIL_RTHCPHYS && !(pVM->pgm.s.HCPhysInterPD & PAGE_OFFSET_MASK));
652	pVM->pgm.s.HCPhysInterPaePDPTR = MMPage2Phys(pVM, pVM->pgm.s.pInterPaePDPTR);
653	AssertRelease(pVM->pgm.s.HCPhysInterPaePDPTR != NIL_RTHCPHYS && !(pVM->pgm.s.HCPhysInterPaePDPTR & PAGE_OFFSET_MASK));
654	pVM->pgm.s.HCPhysInterPaePML4 = MMPage2Phys(pVM, pVM->pgm.s.pInterPaePML4);
655	AssertRelease(pVM->pgm.s.HCPhysInterPaePML4 != NIL_RTHCPHYS && !(pVM->pgm.s.HCPhysInterPaePML4 & PAGE_OFFSET_MASK));
656
657	/*
658	* Initialize the pages, setting up the PML4 and PDPTR for repetitive 4GB action.
659	*/
660	ASMMemZeroPage(pVM->pgm.s.pInterPD);
661	ASMMemZeroPage(pVM->pgm.s.apInterPTs[0]);
662	ASMMemZeroPage(pVM->pgm.s.apInterPTs[1]);
663
664	ASMMemZeroPage(pVM->pgm.s.apInterPaePTs[0]);
665	ASMMemZeroPage(pVM->pgm.s.apInterPaePTs[1]);
666
667	ASMMemZeroPage(pVM->pgm.s.pInterPaePDPTR);
668	for (unsigned i = 0; i < ELEMENTS(pVM->pgm.s.apInterPaePDs); i++)
669	{
670	ASMMemZeroPage(pVM->pgm.s.apInterPaePDs[i]);
671	pVM->pgm.s.pInterPaePDPTR->a[i].u = X86_PDPE_P \| PGM_PLXFLAGS_PERMANENT
672	\| MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[i]);
673	}
674
675	for (unsigned i = 0; i < ELEMENTS(pVM->pgm.s.pInterPaePDPTR64->a); i++)
676	{
677	const unsigned iPD = i % ELEMENTS(pVM->pgm.s.apInterPaePDs);
678	pVM->pgm.s.pInterPaePDPTR64->a[i].u = X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_A \| PGM_PLXFLAGS_PERMANENT
679	\| MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[iPD]);
680	}
681
682	RTHCPHYS HCPhysInterPaePDPTR64 = MMPage2Phys(pVM, pVM->pgm.s.pInterPaePDPTR64);
683	for (unsigned i = 0; i < ELEMENTS(pVM->pgm.s.pInterPaePML4->a); i++)
684	pVM->pgm.s.pInterPaePML4->a[i].u = X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_A \| PGM_PLXFLAGS_PERMANENT
685	\| HCPhysInterPaePDPTR64;
686
687	/*
688	* Allocate pages for the three possible guest contexts (AMD64, PAE and plain 32-Bit).
689	* We allocate pages for all three posibilities to in order to simplify mappings and
690	* avoid resource failure during mode switches. So, we need to cover all levels of the
691	* of the first 4GB down to PD level.
692	* As with the intermediate context, AMD64 uses the PAE PDPTR and PDs.
693	*/
694	pVM->pgm.s.pHC32BitPD = (PX86PD)MMR3PageAllocLow(pVM);
695	pVM->pgm.s.apHCPaePDs[0] = (PX86PDPAE)MMR3PageAlloc(pVM);
696	pVM->pgm.s.apHCPaePDs[1] = (PX86PDPAE)MMR3PageAlloc(pVM);
697	AssertRelease((uintptr_t)pVM->pgm.s.apHCPaePDs[0] + PAGE_SIZE == (uintptr_t)pVM->pgm.s.apHCPaePDs[1]);
698	pVM->pgm.s.apHCPaePDs[2] = (PX86PDPAE)MMR3PageAlloc(pVM);
699	AssertRelease((uintptr_t)pVM->pgm.s.apHCPaePDs[1] + PAGE_SIZE == (uintptr_t)pVM->pgm.s.apHCPaePDs[2]);
700	pVM->pgm.s.apHCPaePDs[3] = (PX86PDPAE)MMR3PageAlloc(pVM);
701	AssertRelease((uintptr_t)pVM->pgm.s.apHCPaePDs[2] + PAGE_SIZE == (uintptr_t)pVM->pgm.s.apHCPaePDs[3]);
702	pVM->pgm.s.pHCPaePDPTR = (PX86PDPTR)MMR3PageAllocLow(pVM);
703	pVM->pgm.s.pHCPaePML4 = (PX86PML4)MMR3PageAllocLow(pVM);
704	if ( !pVM->pgm.s.pHC32BitPD
705	\|\| !pVM->pgm.s.apHCPaePDs[0]
706	\|\| !pVM->pgm.s.apHCPaePDs[1]
707	\|\| !pVM->pgm.s.apHCPaePDs[2]
708	\|\| !pVM->pgm.s.apHCPaePDs[3]
709	\|\| !pVM->pgm.s.pHCPaePDPTR
710	\|\| !pVM->pgm.s.pHCPaePML4)
711	{
712	AssertMsgFailed(("Failed to allocate pages for the intermediate context!\n"));
713	return VERR_NO_PAGE_MEMORY;
714	}
715
716	/* get physical addresses. */
717	pVM->pgm.s.HCPhys32BitPD = MMPage2Phys(pVM, pVM->pgm.s.pHC32BitPD);
718	Assert(MMPagePhys2Page(pVM, pVM->pgm.s.HCPhys32BitPD) == pVM->pgm.s.pHC32BitPD);
719	pVM->pgm.s.aHCPhysPaePDs[0] = MMPage2Phys(pVM, pVM->pgm.s.apHCPaePDs[0]);
720	pVM->pgm.s.aHCPhysPaePDs[1] = MMPage2Phys(pVM, pVM->pgm.s.apHCPaePDs[1]);
721	pVM->pgm.s.aHCPhysPaePDs[2] = MMPage2Phys(pVM, pVM->pgm.s.apHCPaePDs[2]);
722	pVM->pgm.s.aHCPhysPaePDs[3] = MMPage2Phys(pVM, pVM->pgm.s.apHCPaePDs[3]);
723	pVM->pgm.s.HCPhysPaePDPTR = MMPage2Phys(pVM, pVM->pgm.s.pHCPaePDPTR);
724	pVM->pgm.s.HCPhysPaePML4 = MMPage2Phys(pVM, pVM->pgm.s.pHCPaePML4);
725
726	/*
727	* Initialize the pages, setting up the PML4 and PDPTR for action below 4GB.
728	*/
729	ASMMemZero32(pVM->pgm.s.pHC32BitPD, PAGE_SIZE);
730
731	ASMMemZero32(pVM->pgm.s.pHCPaePDPTR, PAGE_SIZE);
732	for (unsigned i = 0; i < ELEMENTS(pVM->pgm.s.apHCPaePDs); i++)
733	{
734	ASMMemZero32(pVM->pgm.s.apHCPaePDs[i], PAGE_SIZE);
735	pVM->pgm.s.pHCPaePDPTR->a[i].u = X86_PDPE_P \| PGM_PLXFLAGS_PERMANENT \| pVM->pgm.s.aHCPhysPaePDs[i];
736	/* The flags will be corrected when entering and leaving long mode. */
737	}
738
739	ASMMemZero32(pVM->pgm.s.pHCPaePML4, PAGE_SIZE);
740	pVM->pgm.s.pHCPaePML4->a[0].u = X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_A
741	\| PGM_PLXFLAGS_PERMANENT \| pVM->pgm.s.HCPhysPaePDPTR;
742
743	CPUMSetHyperCR3(pVM, (uint32_t)pVM->pgm.s.HCPhys32BitPD);
744
745	/*
746	* Initialize paging workers and mode from current host mode
747	* and the guest running in real mode.
748	*/
749	pVM->pgm.s.enmHostMode = SUPGetPagingMode();
750	switch (pVM->pgm.s.enmHostMode)
751	{
752	case SUPPAGINGMODE_32_BIT:
753	case SUPPAGINGMODE_32_BIT_GLOBAL:
754	case SUPPAGINGMODE_PAE:
755	case SUPPAGINGMODE_PAE_GLOBAL:
756	case SUPPAGINGMODE_PAE_NX:
757	case SUPPAGINGMODE_PAE_GLOBAL_NX:
758	break;
759
760	case SUPPAGINGMODE_AMD64:
761	case SUPPAGINGMODE_AMD64_GLOBAL:
762	case SUPPAGINGMODE_AMD64_NX:
763	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
764	if (ARCH_BITS != 64)
765	{
766	AssertMsgFailed(("Host mode %d (64-bit) is not supported by non-64bit builds\n", pVM->pgm.s.enmHostMode));
767	LogRel(("Host mode %d (64-bit) is not supported by non-64bit builds\n", pVM->pgm.s.enmHostMode));
768	return VERR_PGM_UNSUPPORTED_HOST_PAGING_MODE;
769	}
770	break;
771	default:
772	AssertMsgFailed(("Host mode %d is not supported\n", pVM->pgm.s.enmHostMode));
773	return VERR_PGM_UNSUPPORTED_HOST_PAGING_MODE;
774	}
775	rc = pgmR3ModeDataInit(pVM, false /* don't resolve GC and R0 syms yet */);
776	if (VBOX_SUCCESS(rc))
777	rc = pgmR3ChangeMode(pVM, PGMMODE_REAL);
778	if (VBOX_SUCCESS(rc))
779	{
780	LogFlow(("pgmR3InitPaging: returns successfully\n"));
781	#if HC_ARCH_BITS == 64
782	LogRel(("Debug: HCPhys32BitPD=%VHp aHCPhysPaePDs={%VHp,%VHp,%VHp,%VHp} HCPhysPaePDPTR=%VHp HCPhysPaePML4=%VHp\n",
783	pVM->pgm.s.HCPhys32BitPD, pVM->pgm.s.aHCPhysPaePDs[0], pVM->pgm.s.aHCPhysPaePDs[1], pVM->pgm.s.aHCPhysPaePDs[2], pVM->pgm.s.aHCPhysPaePDs[3],
784	pVM->pgm.s.HCPhysPaePDPTR, pVM->pgm.s.HCPhysPaePML4));
785	LogRel(("Debug: HCPhysInterPD=%VHp HCPhysInterPaePDPTR=%VHp HCPhysInterPaePML4=%VHp\n",
786	pVM->pgm.s.HCPhysInterPD, pVM->pgm.s.HCPhysInterPaePDPTR, pVM->pgm.s.HCPhysInterPaePML4));
787	LogRel(("Debug: apInterPTs={%VHp,%VHp} apInterPaePTs={%VHp,%VHp} apInterPaePDs={%VHp,%VHp,%VHp,%VHp} pInterPaePDPTR64=%VHp\n",
788	MMPage2Phys(pVM, pVM->pgm.s.apInterPTs[0]), MMPage2Phys(pVM, pVM->pgm.s.apInterPTs[1]),
789	MMPage2Phys(pVM, pVM->pgm.s.apInterPaePTs[0]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePTs[1]),
790	MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[0]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[1]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[2]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[3]),
791	MMPage2Phys(pVM, pVM->pgm.s.pInterPaePDPTR64)));
792	#endif
793
794	return VINF_SUCCESS;
795	}
796
797	LogFlow(("pgmR3InitPaging: returns %Vrc\n", rc));
798	return rc;
799	}
800
801
802	#ifdef VBOX_WITH_STATISTICS
803	/**
804	* Init statistics
805	*/
806	static void pgmR3InitStats(PVM pVM)
807	{
808	PPGM pPGM = &pVM->pgm.s;
809	STAM_REG(pVM, &pPGM->StatGCInvalidatePage, STAMTYPE_PROFILE, "/PGM/GC/InvalidatePage", STAMUNIT_TICKS_PER_CALL, "PGMGCInvalidatePage() profiling.");
810	STAM_REG(pVM, &pPGM->StatGCInvalidatePage4KBPages, STAMTYPE_COUNTER, "/PGM/GC/InvalidatePage/4KBPages", STAMUNIT_OCCURENCES, "The number of times PGMGCInvalidatePage() was called for a 4KB page.");
811	STAM_REG(pVM, &pPGM->StatGCInvalidatePage4MBPages, STAMTYPE_COUNTER, "/PGM/GC/InvalidatePage/4MBPages", STAMUNIT_OCCURENCES, "The number of times PGMGCInvalidatePage() was called for a 4MB page.");
812	STAM_REG(pVM, &pPGM->StatGCInvalidatePage4MBPagesSkip, STAMTYPE_COUNTER, "/PGM/GC/InvalidatePage/4MBPagesSkip",STAMUNIT_OCCURENCES, "The number of times PGMGCInvalidatePage() skipped a 4MB page.");
813	STAM_REG(pVM, &pPGM->StatGCInvalidatePagePDMappings, STAMTYPE_COUNTER, "/PGM/GC/InvalidatePage/PDMappings", STAMUNIT_OCCURENCES, "The number of times PGMGCInvalidatePage() was called for a page directory containing mappings (no conflict).");
814	STAM_REG(pVM, &pPGM->StatGCInvalidatePagePDNAs, STAMTYPE_COUNTER, "/PGM/GC/InvalidatePage/PDNAs", STAMUNIT_OCCURENCES, "The number of times PGMGCInvalidatePage() was called for a not accessed page directory.");
815	STAM_REG(pVM, &pPGM->StatGCInvalidatePagePDNPs, STAMTYPE_COUNTER, "/PGM/GC/InvalidatePage/PDNPs", STAMUNIT_OCCURENCES, "The number of times PGMGCInvalidatePage() was called for a not present page directory.");
816	STAM_REG(pVM, &pPGM->StatGCInvalidatePagePDOutOfSync, STAMTYPE_COUNTER, "/PGM/GC/InvalidatePage/PDOutOfSync", STAMUNIT_OCCURENCES, "The number of times PGMGCInvalidatePage() was called for an out of sync page directory.");
817	STAM_REG(pVM, &pPGM->StatGCInvalidatePageSkipped, STAMTYPE_COUNTER, "/PGM/GC/InvalidatePage/Skipped", STAMUNIT_OCCURENCES, "The number of times PGMGCInvalidatePage() was skipped due to not present shw or pending pending SyncCR3.");
818	STAM_REG(pVM, &pPGM->StatGCSyncPT, STAMTYPE_PROFILE, "/PGM/GC/SyncPT", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMGCSyncPT() body.");
819	STAM_REG(pVM, &pPGM->StatGCAccessedPage, STAMTYPE_COUNTER, "/PGM/GC/AccessedPage", STAMUNIT_OCCURENCES, "The number of pages marked not present for accessed bit emulation.");
820	STAM_REG(pVM, &pPGM->StatGCDirtyPage, STAMTYPE_COUNTER, "/PGM/GC/DirtyPage/Mark", STAMUNIT_OCCURENCES, "The number of pages marked read-only for dirty bit tracking.");
821	STAM_REG(pVM, &pPGM->StatGCDirtyPageBig, STAMTYPE_COUNTER, "/PGM/GC/DirtyPage/MarkBig", STAMUNIT_OCCURENCES, "The number of 4MB pages marked read-only for dirty bit tracking.");
822	STAM_REG(pVM, &pPGM->StatGCDirtyPageTrap, STAMTYPE_COUNTER, "/PGM/GC/DirtyPage/Trap", STAMUNIT_OCCURENCES, "The number of traps generated for dirty bit tracking.");
823	STAM_REG(pVM, &pPGM->StatGCDirtyPageSkipped, STAMTYPE_COUNTER, "/PGM/GC/DirtyPage/Skipped", STAMUNIT_OCCURENCES, "The number of pages already dirty or readonly.");
824	STAM_REG(pVM, &pPGM->StatGCDirtiedPage, STAMTYPE_COUNTER, "/PGM/GC/DirtyPage/SetDirty", STAMUNIT_OCCURENCES, "The number of pages marked dirty because of write accesses.");
825	STAM_REG(pVM, &pPGM->StatGCDirtyTrackRealPF, STAMTYPE_COUNTER, "/PGM/GC/DirtyPage/RealPF", STAMUNIT_OCCURENCES, "The number of real pages faults during dirty bit tracking.");
826	STAM_REG(pVM, &pPGM->StatGCPageAlreadyDirty, STAMTYPE_COUNTER, "/PGM/GC/DirtyPage/AlreadySet", STAMUNIT_OCCURENCES, "The number of pages already marked dirty because of write accesses.");
827	STAM_REG(pVM, &pPGM->StatGCDirtyBitTracking, STAMTYPE_PROFILE, "/PGM/GC/DirtyPage", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMTrackDirtyBit() body.");
828	STAM_REG(pVM, &pPGM->StatGCSyncPTAlloc, STAMTYPE_COUNTER, "/PGM/GC/SyncPT/Alloc", STAMUNIT_OCCURENCES, "The number of times PGMGCSyncPT() needed to allocate page tables.");
829	STAM_REG(pVM, &pPGM->StatGCSyncPTConflict, STAMTYPE_COUNTER, "/PGM/GC/SyncPT/Conflicts", STAMUNIT_OCCURENCES, "The number of times PGMGCSyncPT() detected conflicts.");
830	STAM_REG(pVM, &pPGM->StatGCSyncPTFailed, STAMTYPE_COUNTER, "/PGM/GC/SyncPT/Failed", STAMUNIT_OCCURENCES, "The number of times PGMGCSyncPT() failed.");
831
832	STAM_REG(pVM, &pPGM->StatGCTrap0e, STAMTYPE_PROFILE, "/PGM/GC/Trap0e", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMGCTrap0eHandler() body.");
833	STAM_REG(pVM, &pPGM->StatCheckPageFault, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time/CheckPageFault", STAMUNIT_TICKS_PER_CALL, "Profiling of checking for dirty/access emulation faults.");
834	STAM_REG(pVM, &pPGM->StatLazySyncPT, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time/SyncPT", STAMUNIT_TICKS_PER_CALL, "Profiling of lazy page table syncing.");
835	STAM_REG(pVM, &pPGM->StatMapping, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time/Mapping", STAMUNIT_TICKS_PER_CALL, "Profiling of checking virtual mappings.");
836	STAM_REG(pVM, &pPGM->StatOutOfSync, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time/OutOfSync", STAMUNIT_TICKS_PER_CALL, "Profiling of out of sync page handling.");
837	STAM_REG(pVM, &pPGM->StatHandlers, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time/Handlers", STAMUNIT_TICKS_PER_CALL, "Profiling of checking handlers.");
838	STAM_REG(pVM, &pPGM->StatEIPHandlers, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time/EIPHandlers", STAMUNIT_TICKS_PER_CALL, "Profiling of checking eip handlers.");
839	STAM_REG(pVM, &pPGM->StatTrap0eCSAM, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time2/CSAM", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is CSAM.");
840	STAM_REG(pVM, &pPGM->StatTrap0eDirtyAndAccessedBits, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time2/DirtyAndAccessedBits", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is dirty and/or accessed bit emulation.");
841	STAM_REG(pVM, &pPGM->StatTrap0eGuestTrap, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time2/GuestTrap", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is a guest trap.");
842	STAM_REG(pVM, &pPGM->StatTrap0eHndPhys, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time2/HandlerPhysical", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is a physical handler.");
843	STAM_REG(pVM, &pPGM->StatTrap0eHndVirt, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time2/HandlerVirtual",STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is a virtual handler.");
844	STAM_REG(pVM, &pPGM->StatTrap0eHndUnhandled, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time2/HandlerUnhandled", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is access outside the monitored areas of a monitored page.");
845	STAM_REG(pVM, &pPGM->StatTrap0eMisc, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time2/Misc", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is not known.");
846	STAM_REG(pVM, &pPGM->StatTrap0eOutOfSync, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time2/OutOfSync", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is an out-of-sync page.");
847	STAM_REG(pVM, &pPGM->StatTrap0eOutOfSyncHndPhys, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time2/OutOfSyncHndPhys", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is an out-of-sync physical handler page.");
848	STAM_REG(pVM, &pPGM->StatTrap0eOutOfSyncHndVirt, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time2/OutOfSyncHndVirt", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is an out-of-sync virtual handler page.");
849	STAM_REG(pVM, &pPGM->StatTrap0eOutOfSyncObsHnd, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time2/OutOfSyncObsHnd", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is an obsolete handler page.");
850	STAM_REG(pVM, &pPGM->StatTrap0eSyncPT, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time2/SyncPT", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is lazy syncing of a PT.");
851
852	STAM_REG(pVM, &pPGM->StatTrap0eMapHandler, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/Handlers/Mapping", STAMUNIT_OCCURENCES, "Number of traps due to access handlers in mappings.");
853	STAM_REG(pVM, &pPGM->StatHandlersOutOfSync, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/Handlers/OutOfSync", STAMUNIT_OCCURENCES, "Number of traps due to out-of-sync handled pages.");
854	STAM_REG(pVM, &pPGM->StatHandlersPhysical, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/Handlers/Physical", STAMUNIT_OCCURENCES, "Number of traps due to physical access handlers.");
855	STAM_REG(pVM, &pPGM->StatHandlersVirtual, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/Handlers/Virtual", STAMUNIT_OCCURENCES, "Number of traps due to virtual access handlers.");
856	STAM_REG(pVM, &pPGM->StatHandlersVirtualByPhys, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/Handlers/VirtualByPhys", STAMUNIT_OCCURENCES, "Number of traps due to virtual access handlers by physical address.");
857	STAM_REG(pVM, &pPGM->StatHandlersVirtualUnmarked, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/Handlers/VirtualUnmarked", STAMUNIT_OCCURENCES,"Number of traps due to virtual access handlers by virtual address (without proper physical flags).");
858	STAM_REG(pVM, &pPGM->StatHandlersUnhandled, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/Handlers/Unhandled", STAMUNIT_OCCURENCES, "Number of traps due to access outside range of monitored page(s).");
859
860	STAM_REG(pVM, &pPGM->StatGCTrap0eConflicts, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/Conflicts", STAMUNIT_OCCURENCES, "The number of times #PF was caused by an undetected conflict.");
861	STAM_REG(pVM, &pPGM->StatGCTrap0eUSNotPresentRead, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/User/NPRead", STAMUNIT_OCCURENCES, "Number of user mode not present read page faults.");
862	STAM_REG(pVM, &pPGM->StatGCTrap0eUSNotPresentWrite, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/User/NPWrite", STAMUNIT_OCCURENCES, "Number of user mode not present write page faults.");
863	STAM_REG(pVM, &pPGM->StatGCTrap0eUSWrite, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/User/Write", STAMUNIT_OCCURENCES, "Number of user mode write page faults.");
864	STAM_REG(pVM, &pPGM->StatGCTrap0eUSReserved, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/User/Reserved", STAMUNIT_OCCURENCES, "Number of user mode reserved bit page faults.");
865	STAM_REG(pVM, &pPGM->StatGCTrap0eUSRead, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/User/Read", STAMUNIT_OCCURENCES, "Number of user mode read page faults.");
866
867	STAM_REG(pVM, &pPGM->StatGCTrap0eSVNotPresentRead, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/Supervisor/NPRead", STAMUNIT_OCCURENCES, "Number of supervisor mode not present read page faults.");
868	STAM_REG(pVM, &pPGM->StatGCTrap0eSVNotPresentWrite, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/Supervisor/NPWrite", STAMUNIT_OCCURENCES, "Number of supervisor mode not present write page faults.");
869	STAM_REG(pVM, &pPGM->StatGCTrap0eSVWrite, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/Supervisor/Write", STAMUNIT_OCCURENCES, "Number of supervisor mode write page faults.");
870	STAM_REG(pVM, &pPGM->StatGCTrap0eSVReserved, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/Supervisor/Reserved", STAMUNIT_OCCURENCES, "Number of supervisor mode reserved bit page faults.");
871	STAM_REG(pVM, &pPGM->StatGCTrap0eUnhandled, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/GuestPF/Unhandled", STAMUNIT_OCCURENCES, "Number of guest real page faults.");
872	STAM_REG(pVM, &pPGM->StatGCTrap0eMap, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/GuestPF/Map", STAMUNIT_OCCURENCES, "Number of guest page faults due to map accesses.");
873
874
875	STAM_REG(pVM, &pPGM->StatGCGuestCR3WriteHandled, STAMTYPE_COUNTER, "/PGM/GC/CR3WriteInt", STAMUNIT_OCCURENCES, "The number of times the Guest CR3 change was successfully handled.");
876	STAM_REG(pVM, &pPGM->StatGCGuestCR3WriteUnhandled, STAMTYPE_COUNTER, "/PGM/GC/CR3WriteEmu", STAMUNIT_OCCURENCES, "The number of times the Guest CR3 change was passed back to the recompiler.");
877	STAM_REG(pVM, &pPGM->StatGCGuestCR3WriteConflict, STAMTYPE_COUNTER, "/PGM/GC/CR3WriteConflict", STAMUNIT_OCCURENCES, "The number of times the Guest CR3 monitoring detected a conflict.");
878
879	STAM_REG(pVM, &pPGM->StatGCPageOutOfSyncSupervisor, STAMTYPE_COUNTER, "/PGM/GC/OutOfSync/SuperVisor", STAMUNIT_OCCURENCES, "Number of traps due to pages out of sync.");
880	STAM_REG(pVM, &pPGM->StatGCPageOutOfSyncUser, STAMTYPE_COUNTER, "/PGM/GC/OutOfSync/User", STAMUNIT_OCCURENCES, "Number of traps due to pages out of sync.");
881
882	STAM_REG(pVM, &pPGM->StatGCGuestROMWriteHandled, STAMTYPE_COUNTER, "/PGM/GC/ROMWriteInt", STAMUNIT_OCCURENCES, "The number of times the Guest ROM change was successfully handled.");
883	STAM_REG(pVM, &pPGM->StatGCGuestROMWriteUnhandled, STAMTYPE_COUNTER, "/PGM/GC/ROMWriteEmu", STAMUNIT_OCCURENCES, "The number of times the Guest ROM change was passed back to the recompiler.");
884
885	STAM_REG(pVM, &pPGM->StatDynMapCacheHits, STAMTYPE_COUNTER, "/PGM/GC/DynMapCache/Hits" , STAMUNIT_OCCURENCES, "Number of dynamic page mapping cache hits.");
886	STAM_REG(pVM, &pPGM->StatDynMapCacheMisses, STAMTYPE_COUNTER, "/PGM/GC/DynMapCache/Misses" , STAMUNIT_OCCURENCES, "Number of dynamic page mapping cache misses.");
887
888	STAM_REG(pVM, &pPGM->StatHCDetectedConflicts, STAMTYPE_COUNTER, "/PGM/HC/DetectedConflicts", STAMUNIT_OCCURENCES, "The number of times PGMR3CheckMappingConflicts() detected a conflict.");
889	STAM_REG(pVM, &pPGM->StatHCGuestPDWrite, STAMTYPE_COUNTER, "/PGM/HC/PDWrite", STAMUNIT_OCCURENCES, "The total number of times pgmHCGuestPDWriteHandler() was called.");
890	STAM_REG(pVM, &pPGM->StatHCGuestPDWriteConflict, STAMTYPE_COUNTER, "/PGM/HC/PDWriteConflict", STAMUNIT_OCCURENCES, "The number of times pgmHCGuestPDWriteHandler() detected a conflict.");
891
892	STAM_REG(pVM, &pPGM->StatHCInvalidatePage, STAMTYPE_PROFILE, "/PGM/HC/InvalidatePage", STAMUNIT_TICKS_PER_CALL, "PGMHCInvalidatePage() profiling.");
893	STAM_REG(pVM, &pPGM->StatHCInvalidatePage4KBPages, STAMTYPE_COUNTER, "/PGM/HC/InvalidatePage/4KBPages", STAMUNIT_OCCURENCES, "The number of times PGMHCInvalidatePage() was called for a 4KB page.");
894	STAM_REG(pVM, &pPGM->StatHCInvalidatePage4MBPages, STAMTYPE_COUNTER, "/PGM/HC/InvalidatePage/4MBPages", STAMUNIT_OCCURENCES, "The number of times PGMHCInvalidatePage() was called for a 4MB page.");
895	STAM_REG(pVM, &pPGM->StatHCInvalidatePage4MBPagesSkip, STAMTYPE_COUNTER, "/PGM/HC/InvalidatePage/4MBPagesSkip",STAMUNIT_OCCURENCES, "The number of times PGMHCInvalidatePage() skipped a 4MB page.");
896	STAM_REG(pVM, &pPGM->StatHCInvalidatePagePDMappings, STAMTYPE_COUNTER, "/PGM/HC/InvalidatePage/PDMappings", STAMUNIT_OCCURENCES, "The number of times PGMHCInvalidatePage() was called for a page directory containing mappings (no conflict).");
897	STAM_REG(pVM, &pPGM->StatHCInvalidatePagePDNAs, STAMTYPE_COUNTER, "/PGM/HC/InvalidatePage/PDNAs", STAMUNIT_OCCURENCES, "The number of times PGMHCInvalidatePage() was called for a not accessed page directory.");
898	STAM_REG(pVM, &pPGM->StatHCInvalidatePagePDNPs, STAMTYPE_COUNTER, "/PGM/HC/InvalidatePage/PDNPs", STAMUNIT_OCCURENCES, "The number of times PGMHCInvalidatePage() was called for a not present page directory.");
899	STAM_REG(pVM, &pPGM->StatHCInvalidatePagePDOutOfSync, STAMTYPE_COUNTER, "/PGM/HC/InvalidatePage/PDOutOfSync", STAMUNIT_OCCURENCES, "The number of times PGMGCInvalidatePage() was called for an out of sync page directory.");
900	STAM_REG(pVM, &pPGM->StatHCInvalidatePageSkipped, STAMTYPE_COUNTER, "/PGM/HC/InvalidatePage/Skipped", STAMUNIT_OCCURENCES, "The number of times PGMHCInvalidatePage() was skipped due to not present shw or pending pending SyncCR3.");
901	STAM_REG(pVM, &pPGM->StatHCResolveConflict, STAMTYPE_PROFILE, "/PGM/HC/ResolveConflict", STAMUNIT_TICKS_PER_CALL, "pgmR3SyncPTResolveConflict() profiling (includes the entire relocation).");
902	STAM_REG(pVM, &pPGM->StatHCPrefetch, STAMTYPE_PROFILE, "/PGM/HC/Prefetch", STAMUNIT_TICKS_PER_CALL, "PGMR3PrefetchPage profiling.");
903
904	STAM_REG(pVM, &pPGM->StatHCSyncPT, STAMTYPE_PROFILE, "/PGM/HC/SyncPT", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMR3SyncPT() body.");
905	STAM_REG(pVM, &pPGM->StatHCAccessedPage, STAMTYPE_COUNTER, "/PGM/HC/AccessedPage", STAMUNIT_OCCURENCES, "The number of pages marked not present for accessed bit emulation.");
906	STAM_REG(pVM, &pPGM->StatHCDirtyPage, STAMTYPE_COUNTER, "/PGM/HC/DirtyPage/Mark", STAMUNIT_OCCURENCES, "The number of pages marked read-only for dirty bit tracking.");
907	STAM_REG(pVM, &pPGM->StatHCDirtyPageBig, STAMTYPE_COUNTER, "/PGM/HC/DirtyPage/MarkBig", STAMUNIT_OCCURENCES, "The number of 4MB pages marked read-only for dirty bit tracking.");
908	STAM_REG(pVM, &pPGM->StatHCDirtyPageTrap, STAMTYPE_COUNTER, "/PGM/HC/DirtyPage/Trap", STAMUNIT_OCCURENCES, "The number of traps generated for dirty bit tracking.");
909	STAM_REG(pVM, &pPGM->StatHCDirtyPageSkipped, STAMTYPE_COUNTER, "/PGM/HC/DirtyPage/Skipped", STAMUNIT_OCCURENCES, "The number of pages already dirty or readonly.");
910	STAM_REG(pVM, &pPGM->StatHCDirtyBitTracking, STAMTYPE_PROFILE, "/PGM/HC/DirtyPage", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMTrackDirtyBit() body.");
911
912	STAM_REG(pVM, &pPGM->StatGCSyncPagePDNAs, STAMTYPE_COUNTER, "/PGM/GC/SyncPagePDNAs", STAMUNIT_OCCURENCES, "The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit.");
913	STAM_REG(pVM, &pPGM->StatGCSyncPagePDOutOfSync, STAMTYPE_COUNTER, "/PGM/GC/SyncPagePDOutOfSync", STAMUNIT_OCCURENCES, "The number of time we've encountered an out-of-sync PD in SyncPage.");
914	STAM_REG(pVM, &pPGM->StatHCSyncPagePDNAs, STAMTYPE_COUNTER, "/PGM/HC/SyncPagePDNAs", STAMUNIT_OCCURENCES, "The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit.");
915	STAM_REG(pVM, &pPGM->StatHCSyncPagePDOutOfSync, STAMTYPE_COUNTER, "/PGM/HC/SyncPagePDOutOfSync", STAMUNIT_OCCURENCES, "The number of time we've encountered an out-of-sync PD in SyncPage.");
916
917	STAM_REG(pVM, &pPGM->StatFlushTLB, STAMTYPE_PROFILE, "/PGM/FlushTLB", STAMUNIT_OCCURENCES, "Profiling of the PGMFlushTLB() body.");
918	STAM_REG(pVM, &pPGM->StatFlushTLBNewCR3, STAMTYPE_COUNTER, "/PGM/FlushTLB/NewCR3", STAMUNIT_OCCURENCES, "The number of times PGMFlushTLB was called with a new CR3, non-global. (switch)");
919	STAM_REG(pVM, &pPGM->StatFlushTLBNewCR3Global, STAMTYPE_COUNTER, "/PGM/FlushTLB/NewCR3Global", STAMUNIT_OCCURENCES, "The number of times PGMFlushTLB was called with a new CR3, global. (switch)");
920	STAM_REG(pVM, &pPGM->StatFlushTLBSameCR3, STAMTYPE_COUNTER, "/PGM/FlushTLB/SameCR3", STAMUNIT_OCCURENCES, "The number of times PGMFlushTLB was called with the same CR3, non-global. (flush)");
921	STAM_REG(pVM, &pPGM->StatFlushTLBSameCR3Global, STAMTYPE_COUNTER, "/PGM/FlushTLB/SameCR3Global", STAMUNIT_OCCURENCES, "The number of times PGMFlushTLB was called with the same CR3, global. (flush)");
922
923	STAM_REG(pVM, &pPGM->StatGCSyncCR3, STAMTYPE_PROFILE, "/PGM/GC/SyncCR3", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMSyncCR3() body.");
924	STAM_REG(pVM, &pPGM->StatGCSyncCR3Handlers, STAMTYPE_PROFILE, "/PGM/GC/SyncCR3/Handlers", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMSyncCR3() update handler section.");
925	STAM_REG(pVM, &pPGM->StatGCSyncCR3HandlerVirtualUpdate, STAMTYPE_PROFILE, "/PGM/GC/SyncCR3/Handlers/VirtualUpdate",STAMUNIT_TICKS_PER_CALL, "Profiling of the virtual handler updates.");
926	STAM_REG(pVM, &pPGM->StatGCSyncCR3HandlerVirtualReset, STAMTYPE_PROFILE, "/PGM/GC/SyncCR3/Handlers/VirtualReset", STAMUNIT_TICKS_PER_CALL, "Profiling of the virtual handler resets.");
927	STAM_REG(pVM, &pPGM->StatGCSyncCR3Global, STAMTYPE_COUNTER, "/PGM/GC/SyncCR3/Global", STAMUNIT_OCCURENCES, "The number of global CR3 syncs.");
928	STAM_REG(pVM, &pPGM->StatGCSyncCR3NotGlobal, STAMTYPE_COUNTER, "/PGM/GC/SyncCR3/NotGlobal", STAMUNIT_OCCURENCES, "The number of non-global CR3 syncs.");
929	STAM_REG(pVM, &pPGM->StatGCSyncCR3DstCacheHit, STAMTYPE_COUNTER, "/PGM/GC/SyncCR3/DstChacheHit", STAMUNIT_OCCURENCES, "The number of times we got some kind of a cache hit.");
930	STAM_REG(pVM, &pPGM->StatGCSyncCR3DstFreed, STAMTYPE_COUNTER, "/PGM/GC/SyncCR3/DstFreed", STAMUNIT_OCCURENCES, "The number of times we've had to free a shadow entry.");
931	STAM_REG(pVM, &pPGM->StatGCSyncCR3DstFreedSrcNP, STAMTYPE_COUNTER, "/PGM/GC/SyncCR3/DstFreedSrcNP", STAMUNIT_OCCURENCES, "The number of times we've had to free a shadow entry for which the source entry was not present.");
932	STAM_REG(pVM, &pPGM->StatGCSyncCR3DstNotPresent, STAMTYPE_COUNTER, "/PGM/GC/SyncCR3/DstNotPresent", STAMUNIT_OCCURENCES, "The number of times we've encountered a not present shadow entry for a present guest entry.");
933	STAM_REG(pVM, &pPGM->StatGCSyncCR3DstSkippedGlobalPD, STAMTYPE_COUNTER, "/PGM/GC/SyncCR3/DstSkippedGlobalPD", STAMUNIT_OCCURENCES, "The number of times a global page directory wasn't flushed.");
934	STAM_REG(pVM, &pPGM->StatGCSyncCR3DstSkippedGlobalPT, STAMTYPE_COUNTER, "/PGM/GC/SyncCR3/DstSkippedGlobalPT", STAMUNIT_OCCURENCES, "The number of times a page table with only global entries wasn't flushed.");
935
936	STAM_REG(pVM, &pPGM->StatHCSyncCR3, STAMTYPE_PROFILE, "/PGM/HC/SyncCR3", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMSyncCR3() body.");
937	STAM_REG(pVM, &pPGM->StatHCSyncCR3Handlers, STAMTYPE_PROFILE, "/PGM/HC/SyncCR3/Handlers", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMSyncCR3() update handler section.");
938	STAM_REG(pVM, &pPGM->StatHCSyncCR3HandlerVirtualUpdate, STAMTYPE_PROFILE, "/PGM/HC/SyncCR3/Handlers/VirtualUpdate",STAMUNIT_TICKS_PER_CALL, "Profiling of the virtual handler updates.");
939	STAM_REG(pVM, &pPGM->StatHCSyncCR3HandlerVirtualReset, STAMTYPE_PROFILE, "/PGM/HC/SyncCR3/Handlers/VirtualReset", STAMUNIT_TICKS_PER_CALL, "Profiling of the virtual handler resets.");
940	STAM_REG(pVM, &pPGM->StatHCSyncCR3Global, STAMTYPE_COUNTER, "/PGM/HC/SyncCR3/Global", STAMUNIT_OCCURENCES, "The number of global CR3 syncs.");
941	STAM_REG(pVM, &pPGM->StatHCSyncCR3NotGlobal, STAMTYPE_COUNTER, "/PGM/HC/SyncCR3/NotGlobal", STAMUNIT_OCCURENCES, "The number of non-global CR3 syncs.");
942	STAM_REG(pVM, &pPGM->StatHCSyncCR3DstCacheHit, STAMTYPE_COUNTER, "/PGM/HC/SyncCR3/DstChacheHit", STAMUNIT_OCCURENCES, "The number of times we got some kind of a cache hit.");
943	STAM_REG(pVM, &pPGM->StatHCSyncCR3DstFreed, STAMTYPE_COUNTER, "/PGM/HC/SyncCR3/DstFreed", STAMUNIT_OCCURENCES, "The number of times we've had to free a shadow entry.");
944	STAM_REG(pVM, &pPGM->StatHCSyncCR3DstFreedSrcNP, STAMTYPE_COUNTER, "/PGM/HC/SyncCR3/DstFreedSrcNP", STAMUNIT_OCCURENCES, "The number of times we've had to free a shadow entry for which the source entry was not present.");
945	STAM_REG(pVM, &pPGM->StatHCSyncCR3DstNotPresent, STAMTYPE_COUNTER, "/PGM/HC/SyncCR3/DstNotPresent", STAMUNIT_OCCURENCES, "The number of times we've encountered a not present shadow entry for a present guest entry.");
946	STAM_REG(pVM, &pPGM->StatHCSyncCR3DstSkippedGlobalPD, STAMTYPE_COUNTER, "/PGM/HC/SyncCR3/DstSkippedGlobalPD", STAMUNIT_OCCURENCES, "The number of times a global page directory wasn't flushed.");
947	STAM_REG(pVM, &pPGM->StatHCSyncCR3DstSkippedGlobalPT, STAMTYPE_COUNTER, "/PGM/HC/SyncCR3/DstSkippedGlobalPT", STAMUNIT_OCCURENCES, "The number of times a page table with only global entries wasn't flushed.");
948
949	STAM_REG(pVM, &pPGM->StatVirtHandleSearchByPhysGC, STAMTYPE_PROFILE, "/PGM/VirtHandler/SearchByPhys/GC", STAMUNIT_TICKS_PER_CALL, "Profiling of pgmHandlerVirtualFindByPhysAddr in GC.");
950	STAM_REG(pVM, &pPGM->StatVirtHandleSearchByPhysHC, STAMTYPE_PROFILE, "/PGM/VirtHandler/SearchByPhys/HC", STAMUNIT_TICKS_PER_CALL, "Profiling of pgmHandlerVirtualFindByPhysAddr in HC.");
951	STAM_REG(pVM, &pPGM->StatHandlePhysicalReset, STAMTYPE_COUNTER, "/PGM/HC/HandlerPhysicalReset", STAMUNIT_OCCURENCES, "The number of times PGMR3HandlerPhysicalReset is called.");
952
953	STAM_REG(pVM, &pPGM->StatHCGstModifyPage, STAMTYPE_PROFILE, "/PGM/HC/GstModifyPage", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMGstModifyPage() body.");
954	STAM_REG(pVM, &pPGM->StatGCGstModifyPage, STAMTYPE_PROFILE, "/PGM/GC/GstModifyPage", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMGstModifyPage() body.");
955
956	STAM_REG(pVM, &pPGM->StatSynPT4kGC, STAMTYPE_COUNTER, "/PGM/GC/SyncPT/4k", STAMUNIT_OCCURENCES, "Nr of 4k PT syncs");
957	STAM_REG(pVM, &pPGM->StatSynPT4kHC, STAMTYPE_COUNTER, "/PGM/HC/SyncPT/4k", STAMUNIT_OCCURENCES, "Nr of 4k PT syncs");
958	STAM_REG(pVM, &pPGM->StatSynPT4MGC, STAMTYPE_COUNTER, "/PGM/GC/SyncPT/4M", STAMUNIT_OCCURENCES, "Nr of 4M PT syncs");
959	STAM_REG(pVM, &pPGM->StatSynPT4MHC, STAMTYPE_COUNTER, "/PGM/HC/SyncPT/4M", STAMUNIT_OCCURENCES, "Nr of 4M PT syncs");
960
961	STAM_REG(pVM, &pPGM->StatDynRamTotal, STAMTYPE_COUNTER, "/PGM/RAM/TotalAlloc", STAMUNIT_MEGABYTES, "Allocated mbs of guest ram.");
962	STAM_REG(pVM, &pPGM->StatDynRamGrow, STAMTYPE_COUNTER, "/PGM/RAM/Grow", STAMUNIT_OCCURENCES, "Nr of pgmr3PhysGrowRange calls.");
963
964	#ifdef PGMPOOL_WITH_GCPHYS_TRACKING
965	STAM_REG(pVM, &pPGM->StatTrackVirgin, STAMTYPE_COUNTER, "/PGM/Track/Virgin", STAMUNIT_OCCURENCES, "The number of first time shadowings");
966	STAM_REG(pVM, &pPGM->StatTrackAliased, STAMTYPE_COUNTER, "/PGM/Track/Aliased", STAMUNIT_OCCURENCES, "The number of times switching to cRef2, i.e. the page is being shadowed by two PTs.");
967	STAM_REG(pVM, &pPGM->StatTrackAliasedMany, STAMTYPE_COUNTER, "/PGM/Track/AliasedMany", STAMUNIT_OCCURENCES, "The number of times we're tracking using cRef2.");
968	STAM_REG(pVM, &pPGM->StatTrackAliasedLots, STAMTYPE_COUNTER, "/PGM/Track/AliasedLots", STAMUNIT_OCCURENCES, "The number of times we're hitting pages which has overflowed cRef2");
969	STAM_REG(pVM, &pPGM->StatTrackOverflows, STAMTYPE_COUNTER, "/PGM/Track/Overflows", STAMUNIT_OCCURENCES, "The number of times the extent list grows to long.");
970	STAM_REG(pVM, &pPGM->StatTrackDeref, STAMTYPE_PROFILE, "/PGM/Track/Deref", STAMUNIT_OCCURENCES, "Profiling of SyncPageWorkerTrackDeref (expensive).");
971	#endif
972
973	for (unsigned i = 0; i < PAGE_ENTRIES; i++)
974	{
975	/** @todo r=bird: We need a STAMR3RegisterF()! */
976	char szName[32];
977
978	RTStrPrintf(szName, sizeof(szName), "/PGM/GC/PD/Trap0e/%04X", i);
979	int rc = STAMR3Register(pVM, &pPGM->StatGCTrap0ePD[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, szName, STAMUNIT_OCCURENCES, "The number of traps in page directory n.");
980	AssertRC(rc);
981
982	RTStrPrintf(szName, sizeof(szName), "/PGM/GC/PD/SyncPt/%04X", i);
983	rc = STAMR3Register(pVM, &pPGM->StatGCSyncPtPD[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, szName, STAMUNIT_OCCURENCES, "The number of syncs per PD n.");
984	AssertRC(rc);
985
986	RTStrPrintf(szName, sizeof(szName), "/PGM/GC/PD/SyncPage/%04X", i);
987	rc = STAMR3Register(pVM, &pPGM->StatGCSyncPagePD[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, szName, STAMUNIT_OCCURENCES, "The number of out of sync pages per page directory n.");
988	AssertRC(rc);
989	}
990	}
991	#endif /* VBOX_WITH_STATISTICS */
992
993	/**
994	* Init the PGM bits that rely on VMMR0 and MM to be fully initialized.
995	*
996	* The dynamic mapping area will also be allocated and initialized at this
997	* time. We could allocate it during PGMR3Init of course, but the mapping
998	* wouldn't be allocated at that time preventing us from setting up the
999	* page table entries with the dummy page.
1000	*
1001	* @returns VBox status code.
1002	* @param pVM VM handle.
1003	*/
1004	PGMR3DECL(int) PGMR3InitDynMap(PVM pVM)
1005	{
1006	/*
1007	* Reserve space for mapping the paging pages into guest context.
1008	*/
1009	int rc = MMR3HyperReserve(pVM, PAGE_SIZE * (2 + ELEMENTS(pVM->pgm.s.apHCPaePDs) + 1 + 2 + 2), "Paging", &pVM->pgm.s.pGC32BitPD);
1010	AssertRCReturn(rc, rc);
1011	MMR3HyperReserve(pVM, PAGE_SIZE, "fence", NULL);
1012
1013	/*
1014	* Reserve space for the dynamic mappings.
1015	*/
1016	/** @todo r=bird: Need to verify that the checks for crossing PTs are correct here. They seems to be assuming 4MB PTs.. */
1017	rc = MMR3HyperReserve(pVM, MM_HYPER_DYNAMIC_SIZE, "Dynamic mapping", &pVM->pgm.s.pbDynPageMapBaseGC);
1018	if ( VBOX_SUCCESS(rc)
1019	&& (pVM->pgm.s.pbDynPageMapBaseGC >> PGDIR_SHIFT) != ((pVM->pgm.s.pbDynPageMapBaseGC + MM_HYPER_DYNAMIC_SIZE - 1) >> PGDIR_SHIFT))
1020	rc = MMR3HyperReserve(pVM, MM_HYPER_DYNAMIC_SIZE, "Dynamic mapping not crossing", &pVM->pgm.s.pbDynPageMapBaseGC);
1021	if (VBOX_SUCCESS(rc))
1022	{
1023	AssertRelease((pVM->pgm.s.pbDynPageMapBaseGC >> PGDIR_SHIFT) == ((pVM->pgm.s.pbDynPageMapBaseGC + MM_HYPER_DYNAMIC_SIZE - 1) >> PGDIR_SHIFT));
1024	MMR3HyperReserve(pVM, PAGE_SIZE, "fence", NULL);
1025	}
1026	return rc;
1027	}
1028
1029
1030	/**
1031	* Ring-3 init finalizing.
1032	*
1033	* @returns VBox status code.
1034	* @param pVM The VM handle.
1035	*/
1036	PGMR3DECL(int) PGMR3InitFinalize(PVM pVM)
1037	{
1038	/*
1039	* Map the paging pages into the guest context.
1040	*/
1041	RTGCPTR GCPtr = pVM->pgm.s.pGC32BitPD;
1042	AssertReleaseReturn(GCPtr, VERR_INTERNAL_ERROR);
1043
1044	int rc = PGMMap(pVM, GCPtr, pVM->pgm.s.HCPhys32BitPD, PAGE_SIZE, 0);
1045	AssertRCReturn(rc, rc);
1046	pVM->pgm.s.pGC32BitPD = GCPtr;
1047	GCPtr += PAGE_SIZE;
1048	GCPtr += PAGE_SIZE; /* reserved page */
1049
1050	for (unsigned i = 0; i < ELEMENTS(pVM->pgm.s.apHCPaePDs); i++)
1051	{
1052	rc = PGMMap(pVM, GCPtr, pVM->pgm.s.aHCPhysPaePDs[i], PAGE_SIZE, 0);
1053	AssertRCReturn(rc, rc);
1054	pVM->pgm.s.apGCPaePDs[i] = GCPtr;
1055	GCPtr += PAGE_SIZE;
1056	}
1057	/* A bit of paranoia is justified. */
1058	AssertRelease((RTGCUINTPTR)pVM->pgm.s.apGCPaePDs[0] + PAGE_SIZE == (RTGCUINTPTR)pVM->pgm.s.apGCPaePDs[1]);
1059	AssertRelease((RTGCUINTPTR)pVM->pgm.s.apGCPaePDs[1] + PAGE_SIZE == (RTGCUINTPTR)pVM->pgm.s.apGCPaePDs[2]);
1060	AssertRelease((RTGCUINTPTR)pVM->pgm.s.apGCPaePDs[2] + PAGE_SIZE == (RTGCUINTPTR)pVM->pgm.s.apGCPaePDs[3]);
1061	GCPtr += PAGE_SIZE; /* reserved page */
1062
1063	rc = PGMMap(pVM, GCPtr, pVM->pgm.s.HCPhysPaePDPTR, PAGE_SIZE, 0);
1064	AssertRCReturn(rc, rc);
1065	pVM->pgm.s.pGCPaePDPTR = GCPtr;
1066	GCPtr += PAGE_SIZE;
1067	GCPtr += PAGE_SIZE; /* reserved page */
1068
1069	rc = PGMMap(pVM, GCPtr, pVM->pgm.s.HCPhysPaePML4, PAGE_SIZE, 0);
1070	AssertRCReturn(rc, rc);
1071	pVM->pgm.s.pGCPaePML4 = GCPtr;
1072	GCPtr += PAGE_SIZE;
1073	GCPtr += PAGE_SIZE; /* reserved page */
1074
1075
1076	/*
1077	* Reserve space for the dynamic mappings.
1078	* Initialize the dynamic mapping pages with dummy pages to simply the cache.
1079	*/
1080	/* get the pointer to the page table entries. */
1081	PPGMMAPPING pMapping = pgmGetMapping(pVM, pVM->pgm.s.pbDynPageMapBaseGC);
1082	AssertRelease(pMapping);
1083	const uintptr_t off = pVM->pgm.s.pbDynPageMapBaseGC - pMapping->GCPtr;
1084	const unsigned iPT = off >> X86_PD_SHIFT;
1085	const unsigned iPG = (off >> X86_PT_SHIFT) & X86_PT_MASK;
1086	pVM->pgm.s.paDynPageMap32BitPTEsGC = pMapping->aPTs[iPT].pPTGC + iPG * sizeof(pMapping->aPTs[0].pPTHC->a[0]);
1087	pVM->pgm.s.paDynPageMapPaePTEsGC = pMapping->aPTs[iPT].paPaePTsGC + iPG * sizeof(pMapping->aPTs[0].paPaePTsHC->a[0]);
1088
1089	/* init cache */
1090	RTHCPHYS HCPhysDummy = MMR3PageDummyHCPhys(pVM);
1091	for (unsigned i = 0; i < ELEMENTS(pVM->pgm.s.aHCPhysDynPageMapCache); i++)
1092	pVM->pgm.s.aHCPhysDynPageMapCache[i] = HCPhysDummy;
1093
1094	for (unsigned i = 0; i < MM_HYPER_DYNAMIC_SIZE; i += PAGE_SIZE)
1095	{
1096	rc = PGMMap(pVM, pVM->pgm.s.pbDynPageMapBaseGC + i, HCPhysDummy, PAGE_SIZE, 0);
1097	AssertRCReturn(rc, rc);
1098	}
1099
1100	return rc;
1101	}
1102
1103
1104	/**
1105	* Applies relocations to data and code managed by this
1106	* component. This function will be called at init and
1107	* whenever the VMM need to relocate it self inside the GC.
1108	*
1109	* @param pVM The VM.
1110	* @param offDelta Relocation delta relative to old location.
1111	*/
1112	PGMR3DECL(void) PGMR3Relocate(PVM pVM, RTGCINTPTR offDelta)
1113	{
1114	LogFlow(("PGMR3Relocate\n"));
1115
1116	/*
1117	* Paging stuff.
1118	*/
1119	pVM->pgm.s.GCPtrCR3Mapping += offDelta;
1120	/** @todo move this into shadow and guest specific relocation functions. */
1121	AssertMsg(pVM->pgm.s.pGC32BitPD, ("Init order, no relocation before paging is initialized!\n"));
1122	pVM->pgm.s.pGC32BitPD += offDelta;
1123	pVM->pgm.s.pGuestPDGC += offDelta;
1124	for (unsigned i = 0; i < ELEMENTS(pVM->pgm.s.apGCPaePDs); i++)
1125	pVM->pgm.s.apGCPaePDs[i] += offDelta;
1126	pVM->pgm.s.pGCPaePDPTR += offDelta;
1127	pVM->pgm.s.pGCPaePML4 += offDelta;
1128
1129	pgmR3ModeDataInit(pVM, true /* resolve GC/R0 symbols */);
1130	pgmR3ModeDataSwitch(pVM, pVM->pgm.s.enmShadowMode, pVM->pgm.s.enmGuestMode);
1131
1132	PGM_SHW_PFN(Relocate, pVM)(pVM, offDelta);
1133	PGM_GST_PFN(Relocate, pVM)(pVM, offDelta);
1134	PGM_BTH_PFN(Relocate, pVM)(pVM, offDelta);
1135
1136	/*
1137	* Trees.
1138	*/
1139	pVM->pgm.s.pTreesGC = MMHyperHC2GC(pVM, pVM->pgm.s.pTreesHC);
1140
1141	/*
1142	* Ram ranges.
1143	*/
1144	if (pVM->pgm.s.pRamRangesHC)
1145	{
1146	pVM->pgm.s.pRamRangesGC = MMHyperHC2GC(pVM, pVM->pgm.s.pRamRangesHC);
1147	for (PPGMRAMRANGE pCur = pVM->pgm.s.pRamRangesHC; pCur->pNextHC; pCur = pCur->pNextHC)
1148	{
1149	pCur->pNextGC = MMHyperHC2GC(pVM, pCur->pNextHC);
1150	if (pCur->pavHCChunkGC)
1151	pCur->pavHCChunkGC = MMHyperHC2GC(pVM, pCur->pavHCChunkHC);
1152	}
1153	}
1154
1155	/*
1156	* Update the two page directories with all page table mappings.
1157	* (One or more of them have changed, that's why we're here.)
1158	*/
1159	pVM->pgm.s.pMappingsGC = MMHyperHC2GC(pVM, pVM->pgm.s.pMappingsHC);
1160	for (PPGMMAPPING pCur = pVM->pgm.s.pMappingsHC; pCur->pNextHC; pCur = pCur->pNextHC)
1161	pCur->pNextGC = MMHyperHC2GC(pVM, pCur->pNextHC);
1162
1163	/* Relocate GC addresses of Page Tables. */
1164	for (PPGMMAPPING pCur = pVM->pgm.s.pMappingsHC; pCur; pCur = pCur->pNextHC)
1165	{
1166	for (RTHCUINT i = 0; i < pCur->cPTs; i++)
1167	{
1168	pCur->aPTs[i].pPTGC = MMHyperHC2GC(pVM, pCur->aPTs[i].pPTHC);
1169	pCur->aPTs[i].paPaePTsGC = MMHyperHC2GC(pVM, pCur->aPTs[i].paPaePTsHC);
1170	}
1171	}
1172
1173	/*
1174	* Dynamic page mapping area.
1175	*/
1176	pVM->pgm.s.paDynPageMap32BitPTEsGC += offDelta;
1177	pVM->pgm.s.paDynPageMapPaePTEsGC += offDelta;
1178	pVM->pgm.s.pbDynPageMapBaseGC += offDelta;
1179
1180	/*
1181	* Physical and virtual handlers.
1182	*/
1183	RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesHC->PhysHandlers, true, pgmR3RelocatePhysHandler, &offDelta);
1184	RTAvlroGCPtrDoWithAll(&pVM->pgm.s.pTreesHC->VirtHandlers, true, pgmR3RelocateVirtHandler, &offDelta);
1185
1186	/*
1187	* The page pool.
1188	*/
1189	pgmR3PoolRelocate(pVM);
1190	}
1191
1192
1193	/**
1194	* Callback function for relocating a physical access handler.
1195	*
1196	* @returns 0 (continue enum)
1197	* @param pNode Pointer to a PGMPHYSHANDLER node.
1198	* @param pvUser Pointer to the offDelta. This is a pointer to the delta since we're
1199	* not certain the delta will fit in a void pointer for all possible configs.
1200	*/
1201	static DECLCALLBACK(int) pgmR3RelocatePhysHandler(PAVLROGCPHYSNODECORE pNode, void *pvUser)
1202	{
1203	PPGMPHYSHANDLER pHandler = (PPGMPHYSHANDLER)pNode;
1204	RTGCINTPTR offDelta = *(PRTGCINTPTR)pvUser;
1205	Assert(pHandler->pfnHandlerGC);
1206	pHandler->pfnHandlerGC += offDelta;
1207	if (pHandler->pvUserGC)
1208	pHandler->pvUserGC += offDelta;
1209	return 0;
1210	}
1211
1212	/**
1213	* Callback function for relocating a virtual access handler.
1214	*
1215	* @returns 0 (continue enum)
1216	* @param pNode Pointer to a PGMVIRTHANDLER node.
1217	* @param pvUser Pointer to the offDelta. This is a pointer to the delta since we're
1218	* not certain the delta will fit in a void pointer for all possible configs.
1219	*/
1220	static DECLCALLBACK(int) pgmR3RelocateVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser)
1221	{
1222	PPGMVIRTHANDLER pHandler = (PPGMVIRTHANDLER)pNode;
1223	RTGCINTPTR offDelta = *(PRTGCINTPTR)pvUser;
1224	Assert(pHandler->pfnHandlerGC);
1225	pHandler->pfnHandlerGC += offDelta;
1226	return 0;
1227	}
1228
1229
1230	/**
1231	* The VM is being reset.
1232	*
1233	* For the PGM component this means that any PD write monitors
1234	* needs to be removed.
1235	*
1236	* @param pVM VM handle.
1237	*/
1238	PGMR3DECL(void) PGMR3Reset(PVM pVM)
1239	{
1240	LogFlow(("PGMR3Reset:\n"));
1241	VM_ASSERT_EMT(pVM);
1242
1243	/*
1244	* Unfix any fixed mappings and disable CR3 monitoring.
1245	*/
1246	pVM->pgm.s.fMappingsFixed = false;
1247	pVM->pgm.s.GCPtrMappingFixed = 0;
1248	pVM->pgm.s.cbMappingFixed = 0;
1249
1250	int rc = PGM_GST_PFN(UnmonitorCR3, pVM)(pVM);
1251	AssertRC(rc);
1252	#ifdef DEBUG
1253	PGMR3DumpMappings(pVM);
1254	#endif
1255
1256	/*
1257	* Reset the shadow page pool.
1258	*/
1259	pgmR3PoolReset(pVM);
1260
1261	/*
1262	* Re-init other members.
1263	*/
1264	pVM->pgm.s.fA20Enabled = true;
1265
1266	/*
1267	* Clear the FFs PGM owns.
1268	*/
1269	VM_FF_CLEAR(pVM, VM_FF_PGM_SYNC_CR3);
1270	VM_FF_CLEAR(pVM, VM_FF_PGM_SYNC_CR3_NON_GLOBAL);
1271
1272	/*
1273	* Zero memory.
1274	*/
1275	for (PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesHC; pRam; pRam = pRam->pNextHC)
1276	{
1277	unsigned iPage = pRam->cb >> PAGE_SHIFT;
1278	while (iPage-- > 0)
1279	{
1280	if (pRam->aHCPhys[iPage] & (MM_RAM_FLAGS_RESERVED \| MM_RAM_FLAGS_ROM \| MM_RAM_FLAGS_MMIO \| MM_RAM_FLAGS_MMIO2))
1281	{
1282	Log4(("PGMR3Reset: not clearing phys page %RGp due to flags %RHp\n", pRam->GCPhys + (iPage << PAGE_SHIFT), pRam->aHCPhys[iPage] & (MM_RAM_FLAGS_RESERVED \| MM_RAM_FLAGS_ROM \| MM_RAM_FLAGS_MMIO)));
1283	continue;
1284	}
1285	if (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)
1286	{
1287	unsigned iChunk = iPage >> (PGM_DYNAMIC_CHUNK_SHIFT - PAGE_SHIFT);
1288	if (pRam->pavHCChunkHC[iChunk])
1289	ASMMemZero32((char *)pRam->pavHCChunkHC[iChunk] + ((iPage << PAGE_SHIFT) & PGM_DYNAMIC_CHUNK_OFFSET_MASK), PAGE_SIZE);
1290	}
1291	else
1292	ASMMemZero32((char *)pRam->pvHC + (iPage << PAGE_SHIFT), PAGE_SIZE);
1293	}
1294	}
1295
1296	/*
1297	* Switch mode back to real mode.
1298	*/
1299	rc = pgmR3ChangeMode(pVM, PGMMODE_REAL);
1300	AssertReleaseRC(rc);
1301	STAM_REL_COUNTER_RESET(&pVM->pgm.s.cGuestModeChanges);
1302	}
1303
1304
1305	/**
1306	* Terminates the PGM.
1307	*
1308	* @returns VBox status code.
1309	* @param pVM Pointer to VM structure.
1310	*/
1311	PGMR3DECL(int) PGMR3Term(PVM pVM)
1312	{
1313	return PDMR3CritSectDelete(&pVM->pgm.s.CritSect);
1314	}
1315
1316
1317	/**
1318	* Execute state save operation.
1319	*
1320	* @returns VBox status code.
1321	* @param pVM VM Handle.
1322	* @param pSSM SSM operation handle.
1323	*/
1324	static DECLCALLBACK(int) pgmR3Save(PVM pVM, PSSMHANDLE pSSM)
1325	{
1326	PPGM pPGM = &pVM->pgm.s;
1327
1328	/*
1329	* Save basic data (required / unaffected by relocation).
1330	*/
1331	#if 1
1332	SSMR3PutBool(pSSM, pPGM->fMappingsFixed);
1333	#else
1334	SSMR3PutUInt(pSSM, pPGM->fMappingsFixed);
1335	#endif
1336	SSMR3PutGCPtr(pSSM, pPGM->GCPtrMappingFixed);
1337	SSMR3PutU32(pSSM, pPGM->cbMappingFixed);
1338	SSMR3PutUInt(pSSM, pPGM->cbRamSize);
1339	SSMR3PutGCPhys(pSSM, pPGM->GCPhysA20Mask);
1340	SSMR3PutUInt(pSSM, pPGM->fA20Enabled);
1341	SSMR3PutUInt(pSSM, pPGM->fSyncFlags);
1342	SSMR3PutUInt(pSSM, pPGM->enmGuestMode);
1343	SSMR3PutU32(pSSM, ~0); /* Separator. */
1344
1345	/*
1346	* The guest mappings.
1347	*/
1348	uint32_t i = 0;
1349	for (PPGMMAPPING pMapping = pPGM->pMappingsHC; pMapping; pMapping = pMapping->pNextHC, i++)
1350	{
1351	SSMR3PutU32(pSSM, i);
1352	SSMR3PutStrZ(pSSM, pMapping->pszDesc); /* This is the best unique id we have... */
1353	SSMR3PutGCPtr(pSSM, pMapping->GCPtr);
1354	SSMR3PutGCUIntPtr(pSSM, pMapping->cPTs);
1355	/* flags are done by the mapping owners! */
1356	}
1357	SSMR3PutU32(pSSM, ~0); /* terminator. */
1358
1359	/*
1360	* Ram range flags and bits.
1361	*/
1362	i = 0;
1363	for (PPGMRAMRANGE pRam = pPGM->pRamRangesHC; pRam; pRam = pRam->pNextHC, i++)
1364	{
1365	/** @todo MMIO ranges may move (PCI reconfig), we currently assume they don't. */
1366
1367	SSMR3PutU32(pSSM, i);
1368	SSMR3PutGCPhys(pSSM, pRam->GCPhys);
1369	SSMR3PutGCPhys(pSSM, pRam->GCPhysLast);
1370	SSMR3PutGCPhys(pSSM, pRam->cb);
1371	SSMR3PutU8(pSSM, !!pRam->pvHC); /* boolean indicating memory or not. */
1372
1373	/* Flags. */
1374	const unsigned cPages = pRam->cb >> PAGE_SHIFT;
1375	for (unsigned iPage = 0; iPage < cPages; iPage++)
1376	SSMR3PutU16(pSSM, (uint16_t)(pRam->aHCPhys[iPage] & ~X86_PTE_PAE_PG_MASK));
1377
1378	/* any memory associated with the range. */
1379	if (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)
1380	{
1381	for (unsigned iChunk = 0; iChunk < (pRam->cb >> PGM_DYNAMIC_CHUNK_SHIFT); iChunk++)
1382	{
1383	if (pRam->pavHCChunkHC[iChunk])
1384	{
1385	SSMR3PutU8(pSSM, 1); /* chunk present */
1386	SSMR3PutMem(pSSM, pRam->pavHCChunkHC[iChunk], PGM_DYNAMIC_CHUNK_SIZE);
1387	}
1388	else
1389	SSMR3PutU8(pSSM, 0); /* no chunk present */
1390	}
1391	}
1392	else if (pRam->pvHC)
1393	{
1394	int rc = SSMR3PutMem(pSSM, pRam->pvHC, pRam->cb);
1395	if (VBOX_FAILURE(rc))
1396	{
1397	Log(("pgmR3Save: SSMR3PutMem(, %p, %#x) -> %Vrc\n", pRam->pvHC, pRam->cb, rc));
1398	return rc;
1399	}
1400	}
1401	}
1402	return SSMR3PutU32(pSSM, ~0); /* terminator. */
1403	}
1404
1405
1406	/**
1407	* Execute state load operation.
1408	*
1409	* @returns VBox status code.
1410	* @param pVM VM Handle.
1411	* @param pSSM SSM operation handle.
1412	* @param u32Version Data layout version.
1413	*/
1414	static DECLCALLBACK(int) pgmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version)
1415	{
1416	/*
1417	* Validate version.
1418	*/
1419	if (u32Version != PGM_SAVED_STATE_VERSION)
1420	{
1421	Log(("pgmR3Load: Invalid version u32Version=%d (current %d)!\n", u32Version, PGM_SAVED_STATE_VERSION));
1422	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
1423	}
1424
1425	/*
1426	* Call the reset function to make sure all the memory is cleared.
1427	*/
1428	PGMR3Reset(pVM);
1429
1430	/*
1431	* Load basic data (required / unaffected by relocation).
1432	*/
1433	PPGM pPGM = &pVM->pgm.s;
1434	#if 1
1435	SSMR3GetBool(pSSM, &pPGM->fMappingsFixed);
1436	#else
1437	uint32_t u;
1438	SSMR3GetU32(pSSM, &u);
1439	pPGM->fMappingsFixed = u;
1440	#endif
1441	SSMR3GetGCPtr(pSSM, &pPGM->GCPtrMappingFixed);
1442	SSMR3GetU32(pSSM, &pPGM->cbMappingFixed);
1443
1444	RTUINT cbRamSize;
1445	int rc = SSMR3GetU32(pSSM, &cbRamSize);
1446	if (VBOX_FAILURE(rc))
1447	return rc;
1448	if (cbRamSize != pPGM->cbRamSize)
1449	return VERR_SSM_LOAD_MEMORY_SIZE_MISMATCH;
1450	SSMR3GetGCPhys(pSSM, &pPGM->GCPhysA20Mask);
1451	SSMR3GetUInt(pSSM, &pPGM->fA20Enabled);
1452	SSMR3GetUInt(pSSM, &pPGM->fSyncFlags);
1453	RTUINT uGuestMode;
1454	SSMR3GetUInt(pSSM, &uGuestMode);
1455	pPGM->enmGuestMode = (PGMMODE)uGuestMode;
1456
1457	/* check separator. */
1458	uint32_t u32Sep;
1459	SSMR3GetU32(pSSM, &u32Sep);
1460	if (VBOX_FAILURE(rc))
1461	return rc;
1462	if (u32Sep != (uint32_t)~0)
1463	{
1464	AssertMsgFailed(("u32Sep=%#x (first)\n", u32Sep));
1465	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1466	}
1467
1468	/*
1469	* The guest mappings.
1470	*/
1471	uint32_t i = 0;
1472	for (;; i++)
1473	{
1474	/* Check the seqence number / separator. */
1475	rc = SSMR3GetU32(pSSM, &u32Sep);
1476	if (VBOX_FAILURE(rc))
1477	return rc;
1478	if (u32Sep == ~0U)
1479	break;
1480	if (u32Sep != i)
1481	{
1482	AssertMsgFailed(("u32Sep=%#x (last)\n", u32Sep));
1483	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1484	}
1485
1486	/* get the mapping details. */
1487	char szDesc[256];
1488	szDesc[0] = '\0';
1489	rc = SSMR3GetStrZ(pSSM, szDesc, sizeof(szDesc));
1490	if (VBOX_FAILURE(rc))
1491	return rc;
1492	RTGCPTR GCPtr;
1493	SSMR3GetGCPtr(pSSM, &GCPtr);
1494	RTGCUINTPTR cPTs;
1495	rc = SSMR3GetU32(pSSM, &cPTs);
1496	if (VBOX_FAILURE(rc))
1497	return rc;
1498
1499	/* find matching range. */
1500	PPGMMAPPING pMapping;
1501	for (pMapping = pPGM->pMappingsHC; pMapping; pMapping = pMapping->pNextHC)
1502	if ( pMapping->cPTs == cPTs
1503	&& !strcmp(pMapping->pszDesc, szDesc))
1504	break;
1505	if (!pMapping)
1506	{
1507	LogRel(("Couldn't find mapping: cPTs=%#x szDesc=%s (GCPtr=%VGv)\n",
1508	cPTs, szDesc, GCPtr));
1509	AssertFailed();
1510	return VERR_SSM_LOAD_CONFIG_MISMATCH;
1511	}
1512
1513	/* relocate it. */
1514	if (pMapping->GCPtr != GCPtr)
1515	{
1516	AssertMsg((GCPtr >> PGDIR_SHIFT << PGDIR_SHIFT) == GCPtr, ("GCPtr=%VGv\n", GCPtr));
1517	#if HC_ARCH_BITS == 64
1518	LogRel(("Mapping: %VGv -> %VGv %s\n", pMapping->GCPtr, GCPtr, pMapping->pszDesc));
1519	#endif
1520	pgmR3MapRelocate(pVM, pMapping, pMapping->GCPtr >> PGDIR_SHIFT, GCPtr >> PGDIR_SHIFT);
1521	}
1522	else
1523	Log(("pgmR3Load: '%s' needed no relocation (%VGv)\n", szDesc, GCPtr));
1524	}
1525
1526	/*
1527	* Ram range flags and bits.
1528	*/
1529	i = 0;
1530	for (PPGMRAMRANGE pRam = pPGM->pRamRangesHC; pRam; pRam = pRam->pNextHC, i++)
1531	{
1532	/** @todo MMIO ranges may move (PCI reconfig), we currently assume they don't. */
1533	/* Check the seqence number / separator. */
1534	rc = SSMR3GetU32(pSSM, &u32Sep);
1535	if (VBOX_FAILURE(rc))
1536	return rc;
1537	if (u32Sep == ~0U)
1538	break;
1539	if (u32Sep != i)
1540	{
1541	AssertMsgFailed(("u32Sep=%#x (last)\n", u32Sep));
1542	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1543	}
1544
1545	/* Get the range details. */
1546	RTGCPHYS GCPhys;
1547	SSMR3GetGCPhys(pSSM, &GCPhys);
1548	RTGCPHYS GCPhysLast;
1549	SSMR3GetGCPhys(pSSM, &GCPhysLast);
1550	RTGCPHYS cb;
1551	SSMR3GetGCPhys(pSSM, &cb);
1552	uint8_t fHaveBits;
1553	rc = SSMR3GetU8(pSSM, &fHaveBits);
1554	if (VBOX_FAILURE(rc))
1555	return rc;
1556	if (fHaveBits & ~1)
1557	{
1558	AssertMsgFailed(("u32Sep=%#x (last)\n", u32Sep));
1559	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1560	}
1561
1562	/* Match it up with the current range. */
1563	if ( GCPhys != pRam->GCPhys
1564	\|\| GCPhysLast != pRam->GCPhysLast
1565	\|\| cb != pRam->cb
1566	\|\| fHaveBits != !!pRam->pvHC)
1567	{
1568	LogRel(("Ram range: %VGp-%VGp %VGp bytes %s\n"
1569	"State : %VGp-%VGp %VGp bytes %s\n",
1570	pRam->GCPhys, pRam->GCPhysLast, pRam->cb, pRam->pvHC ? "bits" : "nobits",
1571	GCPhys, GCPhysLast, cb, fHaveBits ? "bits" : "nobits"));
1572	AssertFailed();
1573	return VERR_SSM_LOAD_CONFIG_MISMATCH;
1574	}
1575
1576	/* Flags. */
1577	const unsigned cPages = pRam->cb >> PAGE_SHIFT;
1578	for (unsigned iPage = 0; iPage < cPages; iPage++)
1579	{
1580	uint16_t u16 = 0;
1581	SSMR3GetU16(pSSM, &u16);
1582	u16 &= PAGE_OFFSET_MASK & ~( MM_RAM_FLAGS_VIRTUAL_HANDLER \| MM_RAM_FLAGS_VIRTUAL_WRITE \| MM_RAM_FLAGS_VIRTUAL_ALL
1583	\| MM_RAM_FLAGS_PHYSICAL_HANDLER \| MM_RAM_FLAGS_PHYSICAL_WRITE \| MM_RAM_FLAGS_PHYSICAL_ALL
1584	\| MM_RAM_FLAGS_PHYSICAL_TEMP_OFF );
1585	pRam->aHCPhys[iPage] = (pRam->aHCPhys[iPage] & X86_PTE_PAE_PG_MASK) \| (RTHCPHYS)u16;
1586	}
1587
1588	/* any memory associated with the range. */
1589	if (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)
1590	{
1591	for (unsigned iChunk = 0; iChunk < (pRam->cb >> PGM_DYNAMIC_CHUNK_SHIFT); iChunk++)
1592	{
1593	uint8_t fValidChunk;
1594
1595	rc = SSMR3GetU8(pSSM, &fValidChunk);
1596	if (VBOX_FAILURE(rc))
1597	return rc;
1598	if (fValidChunk > 1)
1599	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
1600
1601	if (fValidChunk)
1602	{
1603	if (!pRam->pavHCChunkHC[iChunk])
1604	{
1605	rc = pgmr3PhysGrowRange(pVM, pRam->GCPhys + iChunk * PGM_DYNAMIC_CHUNK_SIZE);
1606	if (VBOX_FAILURE(rc))
1607	return rc;
1608	}
1609	Assert(pRam->pavHCChunkHC[iChunk]);
1610
1611	SSMR3GetMem(pSSM, pRam->pavHCChunkHC[iChunk], PGM_DYNAMIC_CHUNK_SIZE);
1612	}
1613	/* else nothing to do */
1614	}
1615	}
1616	else if (pRam->pvHC)
1617	{
1618	int rc = SSMR3GetMem(pSSM, pRam->pvHC, pRam->cb);
1619	if (VBOX_FAILURE(rc))
1620	{
1621	Log(("pgmR3Save: SSMR3GetMem(, %p, %#x) -> %Vrc\n", pRam->pvHC, pRam->cb, rc));
1622	return rc;
1623	}
1624	}
1625	}
1626
1627	/*
1628	* We require a full resync now.
1629	*/
1630	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3_NON_GLOBAL);
1631	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
1632	pPGM->fSyncFlags \|= PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL;
1633	pPGM->fPhysCacheFlushPending = true;
1634	pgmR3HandlerPhysicalUpdateAll(pVM);
1635
1636	/*
1637	* Change the paging mode.
1638	*/
1639	return pgmR3ChangeMode(pVM, pPGM->enmGuestMode);
1640	}
1641
1642
1643	/**
1644	* Show paging mode.
1645	*
1646	* @param pVM VM Handle.
1647	* @param pHlp The info helpers.
1648	* @param pszArgs "all" (default), "guest", "shadow" or "host".
1649	*/
1650	static DECLCALLBACK(void) pgmR3InfoMode(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1651	{
1652	/* digest argument. */
1653	bool fGuest, fShadow, fHost;
1654	if (pszArgs)
1655	pszArgs = RTStrStripL(pszArgs);
1656	if (!pszArgs \|\| !*pszArgs \|\| strstr(pszArgs, "all"))
1657	fShadow = fHost = fGuest = true;
1658	else
1659	{
1660	fShadow = fHost = fGuest = false;
1661	if (strstr(pszArgs, "guest"))
1662	fGuest = true;
1663	if (strstr(pszArgs, "shadow"))
1664	fShadow = true;
1665	if (strstr(pszArgs, "host"))
1666	fHost = true;
1667	}
1668
1669	/* print info. */
1670	if (fGuest)
1671	pHlp->pfnPrintf(pHlp, "Guest paging mode: %s, changed %RU64 times, A20 %s\n",
1672	PGMGetModeName(pVM->pgm.s.enmGuestMode), pVM->pgm.s.cGuestModeChanges.c,
1673	pVM->pgm.s.fA20Enabled ? "enabled" : "disabled");
1674	if (fShadow)
1675	pHlp->pfnPrintf(pHlp, "Shadow paging mode: %s\n", PGMGetModeName(pVM->pgm.s.enmShadowMode));
1676	if (fHost)
1677	{
1678	const char *psz;
1679	switch (pVM->pgm.s.enmHostMode)
1680	{
1681	case SUPPAGINGMODE_INVALID: psz = "invalid"; break;
1682	case SUPPAGINGMODE_32_BIT: psz = "32-bit"; break;
1683	case SUPPAGINGMODE_32_BIT_GLOBAL: psz = "32-bit+G"; break;
1684	case SUPPAGINGMODE_PAE: psz = "PAE"; break;
1685	case SUPPAGINGMODE_PAE_GLOBAL: psz = "PAE+G"; break;
1686	case SUPPAGINGMODE_PAE_NX: psz = "PAE+NX"; break;
1687	case SUPPAGINGMODE_PAE_GLOBAL_NX: psz = "PAE+G+NX"; break;
1688	case SUPPAGINGMODE_AMD64: psz = "AMD64"; break;
1689	case SUPPAGINGMODE_AMD64_GLOBAL: psz = "AMD64+G"; break;
1690	case SUPPAGINGMODE_AMD64_NX: psz = "AMD64+NX"; break;
1691	case SUPPAGINGMODE_AMD64_GLOBAL_NX: psz = "AMD64+G+NX"; break;
1692	default: psz = "unknown"; break;
1693	}
1694	pHlp->pfnPrintf(pHlp, "Host paging mode: %s\n", psz);
1695	}
1696	}
1697
1698
1699	/**
1700	* Dump registered MMIO ranges to the log.
1701	*
1702	* @param pVM VM Handle.
1703	* @param pHlp The info helpers.
1704	* @param pszArgs Arguments, ignored.
1705	*/
1706	static DECLCALLBACK(void) pgmR3PhysInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1707	{
1708	NOREF(pszArgs);
1709	pHlp->pfnPrintf(pHlp,
1710	"RAM ranges (pVM=%p)\n"
1711	"%.s %.s\n",
1712	pVM,
1713	sizeof(RTGCPHYS) * 4 + 1, "GC Phys Range ",
1714	sizeof(RTHCPTR) * 2, "pvHC ");
1715
1716	for (PPGMRAMRANGE pCur = pVM->pgm.s.pRamRangesHC; pCur; pCur = pCur->pNextHC)
1717	pHlp->pfnPrintf(pHlp,
1718	"%VGp-%VGp %VHv\n",
1719	pCur->GCPhys,
1720	pCur->GCPhysLast,
1721	pCur->pvHC);
1722	}
1723
1724	/**
1725	* Dump the page directory to the log.
1726	*
1727	* @param pVM VM Handle.
1728	* @param pHlp The info helpers.
1729	* @param pszArgs Arguments, ignored.
1730	*/
1731	static DECLCALLBACK(void) pgmR3InfoCr3(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
1732	{
1733	/** @todo fix this! Convert the PGMR3DumpHierarchyHC functions to do guest stuff. */
1734	/* Big pages supported? */
1735	const bool fPSE = !!(CPUMGetGuestCR4(pVM) & X86_CR4_PSE);
1736	/* Global pages supported? */
1737	const bool fPGE = !!(CPUMGetGuestCR4(pVM) & X86_CR4_PGE);
1738
1739	NOREF(pszArgs);
1740
1741	/*
1742	* Get page directory addresses.
1743	*/
1744	PVBOXPD pPDSrc = pVM->pgm.s.pGuestPDHC;
1745	Assert(pPDSrc);
1746	Assert(MMPhysGCPhys2HCVirt(pVM, (RTGCPHYS)(CPUMGetGuestCR3(pVM) & X86_CR3_PAGE_MASK), sizeof(*pPDSrc)) == pPDSrc);
1747
1748	/*
1749	* Iterate the page directory.
1750	*/
1751	for (unsigned iPD = 0; iPD < ELEMENTS(pPDSrc->a); iPD++)
1752	{
1753	VBOXPDE PdeSrc = pPDSrc->a[iPD];
1754	if (PdeSrc.n.u1Present)
1755	{
1756	if (PdeSrc.b.u1Size && fPSE)
1757	{
1758	pHlp->pfnPrintf(pHlp,
1759	"%04X - %VGp P=%d U=%d RW=%d G=%d - BIG\n",
1760	iPD,
1761	PdeSrc.u & X86_PDE_PG_MASK,
1762	PdeSrc.b.u1Present, PdeSrc.b.u1User, PdeSrc.b.u1Write, PdeSrc.b.u1Global && fPGE);
1763	}
1764	else
1765	{
1766	pHlp->pfnPrintf(pHlp,
1767	"%04X - %VGp P=%d U=%d RW=%d [G=%d]\n",
1768	iPD,
1769	PdeSrc.u & X86_PDE4M_PG_MASK,
1770	PdeSrc.n.u1Present, PdeSrc.n.u1User, PdeSrc.n.u1Write, PdeSrc.b.u1Global && fPGE);
1771	}
1772	}
1773	}
1774	}
1775
1776
1777	/**
1778	* Serivce a VMMCALLHOST_PGM_LOCK call.
1779	*
1780	* @returns VBox status code.
1781	* @param pVM The VM handle.
1782	*/
1783	PDMR3DECL(int) PGMR3LockCall(PVM pVM)
1784	{
1785	return pgmLock(pVM);
1786	}
1787
1788
1789	/**
1790	* Converts a PGMMODE value to a PGM_TYPE_* \#define.
1791	*
1792	* @returns PGM_TYPE_*.
1793	* @param pgmMode The mode value to convert.
1794	*/
1795	DECLINLINE(unsigned) pgmModeToType(PGMMODE pgmMode)
1796	{
1797	switch (pgmMode)
1798	{
1799	case PGMMODE_REAL: return PGM_TYPE_REAL;
1800	case PGMMODE_PROTECTED: return PGM_TYPE_PROT;
1801	case PGMMODE_32_BIT: return PGM_TYPE_32BIT;
1802	case PGMMODE_PAE:
1803	case PGMMODE_PAE_NX: return PGM_TYPE_PAE;
1804	case PGMMODE_AMD64:
1805	case PGMMODE_AMD64_NX: return PGM_TYPE_AMD64;
1806	default:
1807	AssertFatalMsgFailed(("pgmMode=%d\n", pgmMode));
1808	}
1809	}
1810
1811
1812	/**
1813	* Gets the index into the paging mode data array of a SHW+GST mode.
1814	*
1815	* @returns PGM::paPagingData index.
1816	* @param uShwType The shadow paging mode type.
1817	* @param uGstType The guest paging mode type.
1818	*/
1819	DECLINLINE(unsigned) pgmModeDataIndex(unsigned uShwType, unsigned uGstType)
1820	{
1821	Assert(uShwType >= PGM_TYPE_32BIT && uShwType <= PGM_TYPE_AMD64);
1822	Assert(uGstType >= PGM_TYPE_REAL && uGstType <= PGM_TYPE_AMD64);
1823	return (uShwType - PGM_TYPE_32BIT) * (PGM_TYPE_AMD64 - PGM_TYPE_32BIT + 1)
1824	+ (uGstType - PGM_TYPE_REAL);
1825	}
1826
1827
1828	/**
1829	* Gets the index into the paging mode data array of a SHW+GST mode.
1830	*
1831	* @returns PGM::paPagingData index.
1832	* @param enmShw The shadow paging mode.
1833	* @param enmGst The guest paging mode.
1834	*/
1835	DECLINLINE(unsigned) pgmModeDataIndexByMode(PGMMODE enmShw, PGMMODE enmGst)
1836	{
1837	Assert(enmShw >= PGMMODE_32_BIT && enmShw <= PGMMODE_MAX);
1838	Assert(enmGst > PGMMODE_INVALID && enmGst < PGMMODE_MAX);
1839	return pgmModeDataIndex(pgmModeToType(enmShw), pgmModeToType(enmGst));
1840	}
1841
1842
1843	/**
1844	* Calculates the max data index.
1845	* @returns The number of entries in the pagaing data array.
1846	*/
1847	DECLINLINE(unsigned) pgmModeDataMaxIndex(void)
1848	{
1849	return pgmModeDataIndex(PGM_TYPE_AMD64, PGM_TYPE_AMD64) + 1;
1850	}
1851
1852
1853	/**
1854	* Initializes the paging mode data kept in PGM::paModeData.
1855	*
1856	* @param pVM The VM handle.
1857	* @param fResolveGCAndR0 Indicate whether or not GC and Ring-0 symbols can be resolved now.
1858	* This is used early in the init process to avoid trouble with PDM
1859	* not being initialized yet.
1860	*/
1861	static int pgmR3ModeDataInit(PVM pVM, bool fResolveGCAndR0)
1862	{
1863	PPGMMODEDATA pModeData;
1864	int rc;
1865
1866	/*
1867	* Allocate the array on the first call.
1868	*/
1869	if (!pVM->pgm.s.paModeData)
1870	{
1871	pVM->pgm.s.paModeData = (PPGMMODEDATA)MMR3HeapAllocZ(pVM, MM_TAG_PGM, sizeof(PGMMODEDATA) * pgmModeDataMaxIndex());
1872	AssertReturn(pVM->pgm.s.paModeData, VERR_NO_MEMORY);
1873	}
1874
1875	/*
1876	* Initialize the array entries.
1877	*/
1878	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_32BIT, PGM_TYPE_REAL)];
1879	pModeData->uShwType = PGM_TYPE_32BIT;
1880	pModeData->uGstType = PGM_TYPE_REAL;
1881	rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
1882	rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
1883	rc = PGM_BTH_NAME_32BIT_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
1884
1885	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_32BIT, PGMMODE_PROTECTED)];
1886	pModeData->uShwType = PGM_TYPE_32BIT;
1887	pModeData->uGstType = PGM_TYPE_PROT;
1888	rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
1889	rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
1890	rc = PGM_BTH_NAME_32BIT_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
1891
1892	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_32BIT, PGM_TYPE_32BIT)];
1893	pModeData->uShwType = PGM_TYPE_32BIT;
1894	pModeData->uGstType = PGM_TYPE_32BIT;
1895	rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
1896	rc = PGM_GST_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
1897	rc = PGM_BTH_NAME_32BIT_32BIT(InitData)(pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
1898
1899	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_REAL)];
1900	pModeData->uShwType = PGM_TYPE_PAE;
1901	pModeData->uGstType = PGM_TYPE_REAL;
1902	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
1903	rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
1904	rc = PGM_BTH_NAME_PAE_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
1905
1906	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_PROT)];
1907	pModeData->uShwType = PGM_TYPE_PAE;
1908	pModeData->uGstType = PGM_TYPE_PROT;
1909	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
1910	rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
1911	rc = PGM_BTH_NAME_PAE_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
1912
1913	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_32BIT)];
1914	pModeData->uShwType = PGM_TYPE_PAE;
1915	pModeData->uGstType = PGM_TYPE_32BIT;
1916	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
1917	rc = PGM_GST_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
1918	rc = PGM_BTH_NAME_PAE_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
1919
1920	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_PAE)];
1921	pModeData->uShwType = PGM_TYPE_PAE;
1922	pModeData->uGstType = PGM_TYPE_PAE;
1923	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
1924	rc = PGM_GST_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
1925	rc = PGM_BTH_NAME_PAE_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
1926
1927	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_AMD64, PGM_TYPE_REAL)];
1928	pModeData->uShwType = PGM_TYPE_AMD64;
1929	pModeData->uGstType = PGM_TYPE_REAL;
1930	rc = PGM_SHW_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
1931	rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
1932	rc = PGM_BTH_NAME_AMD64_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
1933
1934	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_AMD64, PGM_TYPE_PROT)];
1935	pModeData->uShwType = PGM_TYPE_AMD64;
1936	pModeData->uGstType = PGM_TYPE_PROT;
1937	rc = PGM_SHW_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
1938	rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
1939	rc = PGM_BTH_NAME_AMD64_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
1940
1941	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_AMD64, PGM_TYPE_AMD64)];
1942	pModeData->uShwType = PGM_TYPE_AMD64;
1943	pModeData->uGstType = PGM_TYPE_AMD64;
1944	rc = PGM_SHW_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
1945	rc = PGM_GST_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
1946	rc = PGM_BTH_NAME_AMD64_AMD64(InitData)(pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
1947
1948	return VINF_SUCCESS;
1949	}
1950
1951
1952	/**
1953	* Swtich to different (or relocated in the relocate case) mode data.
1954	*
1955	* @param pVM The VM handle.
1956	* @param enmShw The the shadow paging mode.
1957	* @param enmGst The the guest paging mode.
1958	*/
1959	static void pgmR3ModeDataSwitch(PVM pVM, PGMMODE enmShw, PGMMODE enmGst)
1960	{
1961	PPGMMODEDATA pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(enmShw, enmGst)];
1962
1963	Assert(pModeData->uGstType == pgmModeToType(enmGst));
1964	Assert(pModeData->uShwType == pgmModeToType(enmShw));
1965
1966	/* shadow */
1967	pVM->pgm.s.pfnR3ShwRelocate = pModeData->pfnR3ShwRelocate;
1968	pVM->pgm.s.pfnR3ShwExit = pModeData->pfnR3ShwExit;
1969	pVM->pgm.s.pfnR3ShwGetPage = pModeData->pfnR3ShwGetPage;
1970	Assert(pVM->pgm.s.pfnR3ShwGetPage);
1971	pVM->pgm.s.pfnR3ShwModifyPage = pModeData->pfnR3ShwModifyPage;
1972	pVM->pgm.s.pfnR3ShwGetPDEByIndex = pModeData->pfnR3ShwGetPDEByIndex;
1973	pVM->pgm.s.pfnR3ShwSetPDEByIndex = pModeData->pfnR3ShwSetPDEByIndex;
1974	pVM->pgm.s.pfnR3ShwModifyPDEByIndex = pModeData->pfnR3ShwModifyPDEByIndex;
1975
1976	pVM->pgm.s.pfnGCShwGetPage = pModeData->pfnGCShwGetPage;
1977	pVM->pgm.s.pfnGCShwModifyPage = pModeData->pfnGCShwModifyPage;
1978	pVM->pgm.s.pfnGCShwGetPDEByIndex = pModeData->pfnGCShwGetPDEByIndex;
1979	pVM->pgm.s.pfnGCShwSetPDEByIndex = pModeData->pfnGCShwSetPDEByIndex;
1980	pVM->pgm.s.pfnGCShwModifyPDEByIndex = pModeData->pfnGCShwModifyPDEByIndex;
1981
1982	pVM->pgm.s.pfnR0ShwGetPage = pModeData->pfnR0ShwGetPage;
1983	pVM->pgm.s.pfnR0ShwModifyPage = pModeData->pfnR0ShwModifyPage;
1984	pVM->pgm.s.pfnR0ShwGetPDEByIndex = pModeData->pfnR0ShwGetPDEByIndex;
1985	pVM->pgm.s.pfnR0ShwSetPDEByIndex = pModeData->pfnR0ShwSetPDEByIndex;
1986	pVM->pgm.s.pfnR0ShwModifyPDEByIndex = pModeData->pfnR0ShwModifyPDEByIndex;
1987
1988
1989	/* guest */
1990	pVM->pgm.s.pfnR3GstRelocate = pModeData->pfnR3GstRelocate;
1991	pVM->pgm.s.pfnR3GstExit = pModeData->pfnR3GstExit;
1992	pVM->pgm.s.pfnR3GstGetPage = pModeData->pfnR3GstGetPage;
1993	Assert(pVM->pgm.s.pfnR3GstGetPage);
1994	pVM->pgm.s.pfnR3GstModifyPage = pModeData->pfnR3GstModifyPage;
1995	pVM->pgm.s.pfnR3GstGetPDE = pModeData->pfnR3GstGetPDE;
1996	pVM->pgm.s.pfnR3GstMonitorCR3 = pModeData->pfnR3GstMonitorCR3;
1997	pVM->pgm.s.pfnR3GstUnmonitorCR3 = pModeData->pfnR3GstUnmonitorCR3;
1998	pVM->pgm.s.pfnR3GstMapCR3 = pModeData->pfnR3GstMapCR3;
1999	pVM->pgm.s.pfnR3GstUnmapCR3 = pModeData->pfnR3GstUnmapCR3;
2000	pVM->pgm.s.pfnHCGstWriteHandlerCR3 = pModeData->pfnHCGstWriteHandlerCR3;
2001	pVM->pgm.s.pszHCGstWriteHandlerCR3 = pModeData->pszHCGstWriteHandlerCR3;
2002
2003	pVM->pgm.s.pfnGCGstGetPage = pModeData->pfnGCGstGetPage;
2004	pVM->pgm.s.pfnGCGstModifyPage = pModeData->pfnGCGstModifyPage;
2005	pVM->pgm.s.pfnGCGstGetPDE = pModeData->pfnGCGstGetPDE;
2006	pVM->pgm.s.pfnGCGstMonitorCR3 = pModeData->pfnGCGstMonitorCR3;
2007	pVM->pgm.s.pfnGCGstUnmonitorCR3 = pModeData->pfnGCGstUnmonitorCR3;
2008	pVM->pgm.s.pfnGCGstMapCR3 = pModeData->pfnGCGstMapCR3;
2009	pVM->pgm.s.pfnGCGstUnmapCR3 = pModeData->pfnGCGstUnmapCR3;
2010	pVM->pgm.s.pfnGCGstWriteHandlerCR3 = pModeData->pfnGCGstWriteHandlerCR3;
2011
2012	pVM->pgm.s.pfnR0GstGetPage = pModeData->pfnR0GstGetPage;
2013	pVM->pgm.s.pfnR0GstModifyPage = pModeData->pfnR0GstModifyPage;
2014	pVM->pgm.s.pfnR0GstGetPDE = pModeData->pfnR0GstGetPDE;
2015	pVM->pgm.s.pfnR0GstMonitorCR3 = pModeData->pfnR0GstMonitorCR3;
2016	pVM->pgm.s.pfnR0GstUnmonitorCR3 = pModeData->pfnR0GstUnmonitorCR3;
2017	pVM->pgm.s.pfnR0GstMapCR3 = pModeData->pfnR0GstMapCR3;
2018	pVM->pgm.s.pfnR0GstUnmapCR3 = pModeData->pfnR0GstUnmapCR3;
2019	pVM->pgm.s.pfnR0GstWriteHandlerCR3 = pModeData->pfnR0GstWriteHandlerCR3;
2020
2021
2022	/* both */
2023	pVM->pgm.s.pfnR3BthRelocate = pModeData->pfnR3BthRelocate;
2024	pVM->pgm.s.pfnR3BthTrap0eHandler = pModeData->pfnR3BthTrap0eHandler;
2025	pVM->pgm.s.pfnR3BthInvalidatePage = pModeData->pfnR3BthInvalidatePage;
2026	pVM->pgm.s.pfnR3BthSyncCR3 = pModeData->pfnR3BthSyncCR3;
2027	Assert(pVM->pgm.s.pfnR3BthSyncCR3);
2028	pVM->pgm.s.pfnR3BthSyncPage = pModeData->pfnR3BthSyncPage;
2029	pVM->pgm.s.pfnR3BthPrefetchPage = pModeData->pfnR3BthPrefetchPage;
2030	pVM->pgm.s.pfnR3BthVerifyAccessSyncPage = pModeData->pfnR3BthVerifyAccessSyncPage;
2031	#ifdef VBOX_STRICT
2032	pVM->pgm.s.pfnR3BthAssertCR3 = pModeData->pfnR3BthAssertCR3;
2033	#endif
2034
2035	pVM->pgm.s.pfnGCBthTrap0eHandler = pModeData->pfnGCBthTrap0eHandler;
2036	pVM->pgm.s.pfnGCBthInvalidatePage = pModeData->pfnGCBthInvalidatePage;
2037	pVM->pgm.s.pfnGCBthSyncCR3 = pModeData->pfnGCBthSyncCR3;
2038	pVM->pgm.s.pfnGCBthSyncPage = pModeData->pfnGCBthSyncPage;
2039	pVM->pgm.s.pfnGCBthPrefetchPage = pModeData->pfnGCBthPrefetchPage;
2040	pVM->pgm.s.pfnGCBthVerifyAccessSyncPage = pModeData->pfnGCBthVerifyAccessSyncPage;
2041	#ifdef VBOX_STRICT
2042	pVM->pgm.s.pfnGCBthAssertCR3 = pModeData->pfnGCBthAssertCR3;
2043	#endif
2044
2045	pVM->pgm.s.pfnR0BthTrap0eHandler = pModeData->pfnR0BthTrap0eHandler;
2046	pVM->pgm.s.pfnR0BthInvalidatePage = pModeData->pfnR0BthInvalidatePage;
2047	pVM->pgm.s.pfnR0BthSyncCR3 = pModeData->pfnR0BthSyncCR3;
2048	pVM->pgm.s.pfnR0BthSyncPage = pModeData->pfnR0BthSyncPage;
2049	pVM->pgm.s.pfnR0BthPrefetchPage = pModeData->pfnR0BthPrefetchPage;
2050	pVM->pgm.s.pfnR0BthVerifyAccessSyncPage = pModeData->pfnR0BthVerifyAccessSyncPage;
2051	#ifdef VBOX_STRICT
2052	pVM->pgm.s.pfnR0BthAssertCR3 = pModeData->pfnR0BthAssertCR3;
2053	#endif
2054	}
2055
2056
2057	#ifdef DEBUG_bird
2058	#include <stdlib.h> /* getenv() remove me! */
2059	#endif
2060
2061	/**
2062	* Calculates the shadow paging mode.
2063	*
2064	* @returns The shadow paging mode.
2065	* @param enmGuestMode The guest mode.
2066	* @param enmHostMode The host mode.
2067	* @param enmShadowMode The current shadow mode.
2068	* @param penmSwitcher Where to store the switcher to use.
2069	* VMMSWITCHER_INVALID means no change.
2070	*/
2071	static PGMMODE pgmR3CalcShadowMode(PGMMODE enmGuestMode, SUPPAGINGMODE enmHostMode, PGMMODE enmShadowMode, VMMSWITCHER *penmSwitcher)
2072	{
2073	VMMSWITCHER enmSwitcher = VMMSWITCHER_INVALID;
2074	switch (enmGuestMode)
2075	{
2076	/*
2077	* When switching to real or protected mode we don't change
2078	* anything since it's likely that we'll switch back pretty soon.
2079	*
2080	* During pgmR3InitPaging we'll end up here with PGMMODE_INVALID
2081	* and is supposed to determin which shadow paging and switcher to
2082	* use during init.
2083	*/
2084	case PGMMODE_REAL:
2085	case PGMMODE_PROTECTED:
2086	if (enmShadowMode != PGMMODE_INVALID)
2087	break; /* (no change) */
2088	switch (enmHostMode)
2089	{
2090	case SUPPAGINGMODE_32_BIT:
2091	case SUPPAGINGMODE_32_BIT_GLOBAL:
2092	enmShadowMode = PGMMODE_32_BIT;
2093	enmSwitcher = VMMSWITCHER_32_TO_32;
2094	break;
2095
2096	case SUPPAGINGMODE_PAE:
2097	case SUPPAGINGMODE_PAE_NX:
2098	case SUPPAGINGMODE_PAE_GLOBAL:
2099	case SUPPAGINGMODE_PAE_GLOBAL_NX:
2100	enmShadowMode = PGMMODE_PAE;
2101	enmSwitcher = VMMSWITCHER_PAE_TO_PAE;
2102	#ifdef DEBUG_bird
2103	if (getenv("VBOX_32BIT"))
2104	{
2105	enmShadowMode = PGMMODE_32_BIT;
2106	enmSwitcher = VMMSWITCHER_PAE_TO_32;
2107	}
2108	#endif
2109	break;
2110
2111	case SUPPAGINGMODE_AMD64:
2112	case SUPPAGINGMODE_AMD64_GLOBAL:
2113	case SUPPAGINGMODE_AMD64_NX:
2114	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
2115	enmShadowMode = PGMMODE_PAE;
2116	enmSwitcher = VMMSWITCHER_AMD64_TO_PAE;
2117	break;
2118
2119	default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
2120	}
2121	break;
2122
2123	case PGMMODE_32_BIT:
2124	switch (enmHostMode)
2125	{
2126	case SUPPAGINGMODE_32_BIT:
2127	case SUPPAGINGMODE_32_BIT_GLOBAL:
2128	enmShadowMode = PGMMODE_32_BIT;
2129	enmSwitcher = VMMSWITCHER_32_TO_32;
2130	break;
2131
2132	case SUPPAGINGMODE_PAE:
2133	case SUPPAGINGMODE_PAE_NX:
2134	case SUPPAGINGMODE_PAE_GLOBAL:
2135	case SUPPAGINGMODE_PAE_GLOBAL_NX:
2136	enmShadowMode = PGMMODE_PAE;
2137	enmSwitcher = VMMSWITCHER_PAE_TO_PAE;
2138	#ifdef DEBUG_bird
2139	if (getenv("VBOX_32BIT"))
2140	{
2141	enmShadowMode = PGMMODE_32_BIT;
2142	enmSwitcher = VMMSWITCHER_PAE_TO_32;
2143	}
2144	#endif
2145	break;
2146
2147	case SUPPAGINGMODE_AMD64:
2148	case SUPPAGINGMODE_AMD64_GLOBAL:
2149	case SUPPAGINGMODE_AMD64_NX:
2150	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
2151	enmShadowMode = PGMMODE_PAE;
2152	enmSwitcher = VMMSWITCHER_AMD64_TO_PAE;
2153	break;
2154
2155	default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
2156	}
2157	break;
2158
2159	case PGMMODE_PAE:
2160	case PGMMODE_PAE_NX: /** @todo This might require more switchers and guest+both modes. */
2161	switch (enmHostMode)
2162	{
2163	case SUPPAGINGMODE_32_BIT:
2164	case SUPPAGINGMODE_32_BIT_GLOBAL:
2165	enmShadowMode = PGMMODE_PAE;
2166	enmSwitcher = VMMSWITCHER_32_TO_PAE;
2167	break;
2168
2169	case SUPPAGINGMODE_PAE:
2170	case SUPPAGINGMODE_PAE_NX:
2171	case SUPPAGINGMODE_PAE_GLOBAL:
2172	case SUPPAGINGMODE_PAE_GLOBAL_NX:
2173	enmShadowMode = PGMMODE_PAE;
2174	enmSwitcher = VMMSWITCHER_PAE_TO_PAE;
2175	break;
2176
2177	case SUPPAGINGMODE_AMD64:
2178	case SUPPAGINGMODE_AMD64_GLOBAL:
2179	case SUPPAGINGMODE_AMD64_NX:
2180	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
2181	enmShadowMode = PGMMODE_PAE;
2182	enmSwitcher = VMMSWITCHER_AMD64_TO_PAE;
2183	break;
2184
2185	default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
2186	}
2187	break;
2188
2189	case PGMMODE_AMD64:
2190	case PGMMODE_AMD64_NX:
2191	switch (enmHostMode)
2192	{
2193	case SUPPAGINGMODE_32_BIT:
2194	case SUPPAGINGMODE_32_BIT_GLOBAL:
2195	enmShadowMode = PGMMODE_PAE;
2196	enmSwitcher = VMMSWITCHER_32_TO_AMD64;
2197	break;
2198
2199	case SUPPAGINGMODE_PAE:
2200	case SUPPAGINGMODE_PAE_NX:
2201	case SUPPAGINGMODE_PAE_GLOBAL:
2202	case SUPPAGINGMODE_PAE_GLOBAL_NX:
2203	enmShadowMode = PGMMODE_PAE;
2204	enmSwitcher = VMMSWITCHER_PAE_TO_AMD64;
2205	break;
2206
2207	case SUPPAGINGMODE_AMD64:
2208	case SUPPAGINGMODE_AMD64_GLOBAL:
2209	case SUPPAGINGMODE_AMD64_NX:
2210	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
2211	enmShadowMode = PGMMODE_PAE;
2212	enmSwitcher = VMMSWITCHER_AMD64_TO_AMD64;
2213	break;
2214
2215	default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
2216	}
2217	break;
2218
2219
2220	default:
2221	AssertReleaseMsgFailed(("enmGuestMode=%d\n", enmGuestMode));
2222	return PGMMODE_INVALID;
2223	}
2224
2225	*penmSwitcher = enmSwitcher;
2226	return enmShadowMode;
2227	}
2228
2229
2230	/**
2231	* Performs the actual mode change.
2232	* This is called by PGMChangeMode and pgmR3InitPaging().
2233	*
2234	* @returns VBox status code.
2235	* @param pVM VM handle.
2236	* @param enmGuestMode The new guest mode. This is assumed to be different from
2237	* the current mode.
2238	*/
2239	int pgmR3ChangeMode(PVM pVM, PGMMODE enmGuestMode)
2240	{
2241	LogFlow(("pgmR3ChangeMode: Guest mode: %d -> %d\n", pVM->pgm.s.enmGuestMode, enmGuestMode));
2242	STAM_REL_COUNTER_INC(&pVM->pgm.s.cGuestModeChanges);
2243
2244	/*
2245	* Calc the shadow mode and switcher.
2246	*/
2247	VMMSWITCHER enmSwitcher;
2248	PGMMODE enmShadowMode = pgmR3CalcShadowMode(enmGuestMode, pVM->pgm.s.enmHostMode, pVM->pgm.s.enmShadowMode, &enmSwitcher);
2249	if (enmSwitcher != VMMSWITCHER_INVALID)
2250	{
2251	/*
2252	* Select new switcher.
2253	*/
2254	int rc = VMMR3SelectSwitcher(pVM, enmSwitcher);
2255	if (VBOX_FAILURE(rc))
2256	{
2257	AssertReleaseMsgFailed(("VMMR3SelectSwitcher(%d) -> %Vrc\n", enmSwitcher, rc));
2258	return rc;
2259	}
2260	}
2261
2262	/*
2263	* Exit old mode(s).
2264	*/
2265	/* shadow */
2266	if (enmShadowMode != pVM->pgm.s.enmShadowMode)
2267	{
2268	LogFlow(("pgmR3ChangeMode: Shadow mode: %d -> %d\n", pVM->pgm.s.enmShadowMode, enmShadowMode));
2269	if (PGM_SHW_PFN(Exit, pVM))
2270	{
2271	int rc = PGM_SHW_PFN(Exit, pVM)(pVM);
2272	if (VBOX_FAILURE(rc))
2273	{
2274	AssertMsgFailed(("Exit failed for shadow mode %d: %Vrc\n", pVM->pgm.s.enmShadowMode, rc));
2275	return rc;
2276	}
2277	}
2278
2279	}
2280
2281	/* guest */
2282	if (PGM_GST_PFN(Exit, pVM))
2283	{
2284	int rc = PGM_GST_PFN(Exit, pVM)(pVM);
2285	if (VBOX_FAILURE(rc))
2286	{
2287	AssertMsgFailed(("Exit failed for guest mode %d: %Vrc\n", pVM->pgm.s.enmGuestMode, rc));
2288	return rc;
2289	}
2290	}
2291
2292	/*
2293	* Load new paging mode data.
2294	*/
2295	pgmR3ModeDataSwitch(pVM, enmShadowMode, enmGuestMode);
2296
2297	/*
2298	* Enter new shadow mode (if changed).
2299	*/
2300	if (enmShadowMode != pVM->pgm.s.enmShadowMode)
2301	{
2302	int rc;
2303	pVM->pgm.s.enmShadowMode = enmShadowMode;
2304	switch (enmShadowMode)
2305	{
2306	case PGMMODE_32_BIT:
2307	rc = PGM_SHW_NAME_32BIT(Enter)(pVM);
2308	break;
2309	case PGMMODE_PAE:
2310	case PGMMODE_PAE_NX:
2311	rc = PGM_SHW_NAME_PAE(Enter)(pVM);
2312	break;
2313	case PGMMODE_AMD64:
2314	case PGMMODE_AMD64_NX:
2315	rc = PGM_SHW_NAME_AMD64(Enter)(pVM);
2316	break;
2317	case PGMMODE_REAL:
2318	case PGMMODE_PROTECTED:
2319	default:
2320	AssertReleaseMsgFailed(("enmShadowMode=%d\n", enmShadowMode));
2321	return VERR_INTERNAL_ERROR;
2322	}
2323	if (VBOX_FAILURE(rc))
2324	{
2325	AssertReleaseMsgFailed(("Entering enmShadowMode=%d failed: %Vrc\n", enmShadowMode, rc));
2326	pVM->pgm.s.enmShadowMode = PGMMODE_INVALID;
2327	return rc;
2328	}
2329	}
2330
2331	/*
2332	* Enter the new guest and shadow+guest modes.
2333	*/
2334	int rc = -1;
2335	int rc2 = -1;
2336	RTGCPHYS GCPhysCR3 = NIL_RTGCPHYS;
2337	pVM->pgm.s.enmGuestMode = enmGuestMode;
2338	switch (enmGuestMode)
2339	{
2340	case PGMMODE_REAL:
2341	rc = PGM_GST_NAME_REAL(Enter)(pVM, NIL_RTGCPHYS);
2342	switch (pVM->pgm.s.enmShadowMode)
2343	{
2344	case PGMMODE_32_BIT:
2345	rc2 = PGM_BTH_NAME_32BIT_REAL(Enter)(pVM, NIL_RTGCPHYS);
2346	break;
2347	case PGMMODE_PAE:
2348	case PGMMODE_PAE_NX:
2349	rc2 = PGM_BTH_NAME_PAE_REAL(Enter)(pVM, NIL_RTGCPHYS);
2350	break;
2351	case PGMMODE_AMD64:
2352	case PGMMODE_AMD64_NX:
2353	rc2 = PGM_BTH_NAME_AMD64_REAL(Enter)(pVM, NIL_RTGCPHYS);
2354	break;
2355	default: AssertFailed(); break;
2356	}
2357	break;
2358
2359	case PGMMODE_PROTECTED:
2360	rc = PGM_GST_NAME_PROT(Enter)(pVM, NIL_RTGCPHYS);
2361	switch (pVM->pgm.s.enmShadowMode)
2362	{
2363	case PGMMODE_32_BIT:
2364	rc2 = PGM_BTH_NAME_32BIT_PROT(Enter)(pVM, NIL_RTGCPHYS);
2365	break;
2366	case PGMMODE_PAE:
2367	case PGMMODE_PAE_NX:
2368	rc2 = PGM_BTH_NAME_PAE_PROT(Enter)(pVM, NIL_RTGCPHYS);
2369	break;
2370	case PGMMODE_AMD64:
2371	case PGMMODE_AMD64_NX:
2372	rc2 = PGM_BTH_NAME_AMD64_PROT(Enter)(pVM, NIL_RTGCPHYS);
2373	break;
2374	default: AssertFailed(); break;
2375	}
2376	break;
2377
2378	case PGMMODE_32_BIT:
2379	GCPhysCR3 = CPUMGetGuestCR3(pVM) & X86_CR3_PAGE_MASK;
2380	rc = PGM_GST_NAME_32BIT(Enter)(pVM, GCPhysCR3);
2381	switch (pVM->pgm.s.enmShadowMode)
2382	{
2383	case PGMMODE_32_BIT:
2384	rc2 = PGM_BTH_NAME_32BIT_32BIT(Enter)(pVM, GCPhysCR3);
2385	break;
2386	case PGMMODE_PAE:
2387	case PGMMODE_PAE_NX:
2388	rc2 = PGM_BTH_NAME_PAE_32BIT(Enter)(pVM, GCPhysCR3);
2389	break;
2390	case PGMMODE_AMD64:
2391	case PGMMODE_AMD64_NX:
2392	AssertMsgFailed(("Should use PAE shadow mode!\n"));
2393	default: AssertFailed(); break;
2394	}
2395	break;
2396
2397	//case PGMMODE_PAE_NX:
2398	case PGMMODE_PAE:
2399	GCPhysCR3 = CPUMGetGuestCR3(pVM) & X86_CR3_PAE_PAGE_MASK;
2400	rc = PGM_GST_NAME_PAE(Enter)(pVM, GCPhysCR3);
2401	switch (pVM->pgm.s.enmShadowMode)
2402	{
2403	case PGMMODE_PAE:
2404	case PGMMODE_PAE_NX:
2405	rc2 = PGM_BTH_NAME_PAE_PAE(Enter)(pVM, GCPhysCR3);
2406	break;
2407	case PGMMODE_32_BIT:
2408	case PGMMODE_AMD64:
2409	case PGMMODE_AMD64_NX:
2410	AssertMsgFailed(("Should use PAE shadow mode!\n"));
2411	default: AssertFailed(); break;
2412	}
2413	break;
2414
2415	//case PGMMODE_AMD64_NX:
2416	case PGMMODE_AMD64:
2417	GCPhysCR3 = CPUMGetGuestCR3(pVM) & 0xfffffffffffff000ULL; /** @todo define this mask and make CR3 64-bit in this case! */
2418	rc = PGM_GST_NAME_AMD64(Enter)(pVM, GCPhysCR3);
2419	switch (pVM->pgm.s.enmShadowMode)
2420	{
2421	case PGMMODE_AMD64:
2422	case PGMMODE_AMD64_NX:
2423	rc2 = PGM_BTH_NAME_AMD64_AMD64(Enter)(pVM, GCPhysCR3);
2424	break;
2425	case PGMMODE_32_BIT:
2426	case PGMMODE_PAE:
2427	case PGMMODE_PAE_NX:
2428	AssertMsgFailed(("Should use AMD64 shadow mode!\n"));
2429	default: AssertFailed(); break;
2430	}
2431	break;
2432
2433	default:
2434	AssertReleaseMsgFailed(("enmGuestMode=%d\n", enmGuestMode));
2435	rc = VERR_NOT_IMPLEMENTED;
2436	break;
2437	}
2438
2439	/* status codes. */
2440	AssertRC(rc);
2441	AssertRC(rc2);
2442	if (VBOX_SUCCESS(rc))
2443	{
2444	rc = rc2;
2445	if (VBOX_SUCCESS(rc)) /* no informational status codes. */
2446	rc = VINF_SUCCESS;
2447	}
2448
2449	/*
2450	* Notify SELM so it can update the TSSes with correct CR3s.
2451	*/
2452	SELMR3PagingModeChanged(pVM);
2453
2454	/* Notify HWACCM as well. */
2455	HWACCMR3PagingModeChanged(pVM, pVM->pgm.s.enmShadowMode);
2456	return rc;
2457	}
2458
2459
2460	/**
2461	* Dumps a PAE shadow page table.
2462	*
2463	* @returns VBox status code (VINF_SUCCESS).
2464	* @param pVM The VM handle.
2465	* @param pPT Pointer to the page table.
2466	* @param u64Address The virtual address of the page table starts.
2467	* @param fLongMode Set if this a long mode table; clear if it's a legacy mode table.
2468	* @param cMaxDepth The maxium depth.
2469	* @param pHlp Pointer to the output functions.
2470	*/
2471	static int pgmR3DumpHierarchyHCPaePT(PVM pVM, PX86PTPAE pPT, uint64_t u64Address, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
2472	{
2473	for (unsigned i = 0; i < ELEMENTS(pPT->a); i++)
2474	{
2475	X86PTEPAE Pte = pPT->a[i];
2476	if (Pte.n.u1Present)
2477	{
2478	pHlp->pfnPrintf(pHlp,
2479	fLongMode /P R S A D G WT CD AT NX 4M a p ? /
2480	? "%016llx 3 \| P %c %c %c %c %c %s %s %s %s 4K %c%c%c %016llx\n"
2481	: "%08llx 2 \| P %c %c %c %c %c %s %s %s %s 4K %c%c%c %016llx\n",
2482	u64Address + ((uint64_t)i << X86_PT_PAE_SHIFT),
2483	Pte.n.u1Write ? 'W' : 'R',
2484	Pte.n.u1User ? 'U' : 'S',
2485	Pte.n.u1Accessed ? 'A' : '-',
2486	Pte.n.u1Dirty ? 'D' : '-',
2487	Pte.n.u1Global ? 'G' : '-',
2488	Pte.n.u1WriteThru ? "WT" : "--",
2489	Pte.n.u1CacheDisable? "CD" : "--",
2490	Pte.n.u1PAT ? "AT" : "--",
2491	Pte.n.u1NoExecute ? "NX" : "--",
2492	Pte.u & PGM_PTFLAGS_TRACK_DIRTY ? 'd' : '-',
2493	Pte.u & BIT(10) ? '1' : '0',
2494	Pte.u & PGM_PTFLAGS_CSAM_VALIDATED? 'v' : '-',
2495	Pte.u & X86_PTE_PAE_PG_MASK);
2496	}
2497	}
2498	return VINF_SUCCESS;
2499	}
2500
2501
2502	/**
2503	* Dumps a PAE shadow page directory table.
2504	*
2505	* @returns VBox status code (VINF_SUCCESS).
2506	* @param pVM The VM handle.
2507	* @param HCPhys The physical address of the page directory table.
2508	* @param u64Address The virtual address of the page table starts.
2509	* @param cr4 The CR4, PSE is currently used.
2510	* @param fLongMode Set if this a long mode table; clear if it's a legacy mode table.
2511	* @param cMaxDepth The maxium depth.
2512	* @param pHlp Pointer to the output functions.
2513	*/
2514	static int pgmR3DumpHierarchyHCPaePD(PVM pVM, RTHCPHYS HCPhys, uint64_t u64Address, uint32_t cr4, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
2515	{
2516	PX86PDPAE pPD = (PX86PDPAE)MMPagePhys2Page(pVM, HCPhys);
2517	if (!pPD)
2518	{
2519	pHlp->pfnPrintf(pHlp, "%0*llx error! Page directory at HCPhys=%#VHp was not found in the page pool!\n",
2520	fLongMode ? 16 : 8, u64Address, HCPhys);
2521	return VERR_INVALID_PARAMETER;
2522	}
2523	int rc = VINF_SUCCESS;
2524	for (unsigned i = 0; i < ELEMENTS(pPD->a); i++)
2525	{
2526	X86PDEPAE Pde = pPD->a[i];
2527	if (Pde.n.u1Present)
2528	{
2529	if ((cr4 & X86_CR4_PSE) && Pde.b.u1Size)
2530	pHlp->pfnPrintf(pHlp,
2531	fLongMode /P R S A D G WT CD AT NX 4M a p ? /
2532	? "%016llx 2 \| P %c %c %c %c %c %s %s %s %s 4M %c%c%c %016llx\n"
2533	: "%08llx 1 \| P %c %c %c %c %c %s %s %s %s 4M %c%c%c %016llx\n",
2534	u64Address + ((uint64_t)i << X86_PD_PAE_SHIFT),
2535	Pde.b.u1Write ? 'W' : 'R',
2536	Pde.b.u1User ? 'U' : 'S',
2537	Pde.b.u1Accessed ? 'A' : '-',
2538	Pde.b.u1Dirty ? 'D' : '-',
2539	Pde.b.u1Global ? 'G' : '-',
2540	Pde.b.u1WriteThru ? "WT" : "--",
2541	Pde.b.u1CacheDisable? "CD" : "--",
2542	Pde.b.u1PAT ? "AT" : "--",
2543	Pde.b.u1NoExecute ? "NX" : "--",
2544	Pde.u & BIT64(9) ? '1' : '0',
2545	Pde.u & PGM_PDFLAGS_MAPPING ? 'm' : '-',
2546	Pde.u & PGM_PDFLAGS_TRACK_DIRTY ? 'd' : '-',
2547	Pde.u & X86_PDE_PAE_PG_MASK);
2548	else
2549	{
2550	pHlp->pfnPrintf(pHlp,
2551	fLongMode /P R S A D G WT CD AT NX 4M a p ? /
2552	? "%016llx 2 \| P %c %c %c %c %c %s %s .. %s 4K %c%c%c %016llx\n"
2553	: "%08llx 1 \| P %c %c %c %c %c %s %s .. %s 4K %c%c%c %016llx\n",
2554	u64Address + ((uint64_t)i << X86_PD_PAE_SHIFT),
2555	Pde.n.u1Write ? 'W' : 'R',
2556	Pde.n.u1User ? 'U' : 'S',
2557	Pde.n.u1Accessed ? 'A' : '-',
2558	Pde.n.u1Reserved0 ? '?' : '.', /* ignored */
2559	Pde.n.u1Reserved1 ? '?' : '.', /* ignored */
2560	Pde.n.u1WriteThru ? "WT" : "--",
2561	Pde.n.u1CacheDisable? "CD" : "--",
2562	Pde.n.u1NoExecute ? "NX" : "--",
2563	Pde.u & BIT64(9) ? '1' : '0',
2564	Pde.u & PGM_PDFLAGS_MAPPING ? 'm' : '-',
2565	Pde.u & PGM_PDFLAGS_TRACK_DIRTY ? 'd' : '-',
2566	Pde.u & X86_PDE_PAE_PG_MASK);
2567	if (cMaxDepth >= 1)
2568	{
2569	/** @todo what about using the page pool for mapping PTs? */
2570	uint64_t u64AddressPT = u64Address + ((uint64_t)i << X86_PD_PAE_SHIFT);
2571	RTHCPHYS HCPhysPT = Pde.u & X86_PDE_PAE_PG_MASK;
2572	PX86PTPAE pPT = NULL;
2573	if (!(Pde.u & PGM_PDFLAGS_MAPPING))
2574	pPT = (PX86PTPAE)MMPagePhys2Page(pVM, HCPhysPT);
2575	else
2576	{
2577	for (PPGMMAPPING pMap = pVM->pgm.s.pMappingsHC; pMap; pMap = pMap->pNextHC)
2578	{
2579	uint64_t off = u64AddressPT - pMap->GCPtr;
2580	if (off < pMap->cb)
2581	{
2582	const int iPDE = (uint32_t)(off >> X86_PD_SHIFT);
2583	const int iSub = (int)((off >> X86_PD_PAE_SHIFT) & 1); /* MSC is a pain sometimes */
2584	if ((iSub ? pMap->aPTs[iPDE].HCPhysPaePT1 : pMap->aPTs[iPDE].HCPhysPaePT0) != HCPhysPT)
2585	pHlp->pfnPrintf(pHlp, "%0*llx error! Mapping error! PT %d has HCPhysPT=%VHp not %VHp is in the PD.\n",
2586	fLongMode ? 16 : 8, u64AddressPT, iPDE,
2587	iSub ? pMap->aPTs[iPDE].HCPhysPaePT1 : pMap->aPTs[iPDE].HCPhysPaePT0, HCPhysPT);
2588	pPT = &pMap->aPTs[iPDE].paPaePTsHC[iSub];
2589	}
2590	}
2591	}
2592	int rc2 = VERR_INVALID_PARAMETER;
2593	if (pPT)
2594	rc2 = pgmR3DumpHierarchyHCPaePT(pVM, pPT, u64AddressPT, fLongMode, cMaxDepth - 1, pHlp);
2595	else
2596	pHlp->pfnPrintf(pHlp, "%0*llx error! Page table at HCPhys=%#VHp was not found in the page pool!\n",
2597	fLongMode ? 16 : 8, u64AddressPT, HCPhysPT);
2598	if (rc2 < rc && VBOX_SUCCESS(rc))
2599	rc = rc2;
2600	}
2601	}
2602	}
2603	}
2604	return rc;
2605	}
2606
2607
2608	/**
2609	* Dumps a PAE shadow page directory pointer table.
2610	*
2611	* @returns VBox status code (VINF_SUCCESS).
2612	* @param pVM The VM handle.
2613	* @param HCPhys The physical address of the page directory pointer table.
2614	* @param u64Address The virtual address of the page table starts.
2615	* @param cr4 The CR4, PSE is currently used.
2616	* @param fLongMode Set if this a long mode table; clear if it's a legacy mode table.
2617	* @param cMaxDepth The maxium depth.
2618	* @param pHlp Pointer to the output functions.
2619	*/
2620	static int pgmR3DumpHierarchyHCPaePDPTR(PVM pVM, RTHCPHYS HCPhys, uint64_t u64Address, uint32_t cr4, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
2621	{
2622	PX86PDPTR pPDPTR = (PX86PDPTR)MMPagePhys2Page(pVM, HCPhys);
2623	if (!pPDPTR)
2624	{
2625	pHlp->pfnPrintf(pHlp, "%0*llx error! Page directory pointer table at HCPhys=%#VHp was not found in the page pool!\n",
2626	fLongMode ? 16 : 8, u64Address, HCPhys);
2627	return VERR_INVALID_PARAMETER;
2628	}
2629
2630	int rc = VINF_SUCCESS;
2631	const unsigned c = fLongMode ? ELEMENTS(pPDPTR->a) : 4;
2632	for (unsigned i = 0; i < c; i++)
2633	{
2634	X86PDPE Pdpe = pPDPTR->a[i];
2635	if (Pdpe.n.u1Present)
2636	{
2637	if (fLongMode)
2638	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a p ? /
2639	"%016llx 1 \| P %c %c %c %c %c %s %s %s %s .. %c%c%c %016llx\n",
2640	u64Address + ((uint64_t)i << X86_PDPTR_SHIFT),
2641	Pdpe.n.u1Write ? 'W' : 'R',
2642	Pdpe.n.u1User ? 'U' : 'S',
2643	Pdpe.n.u1Accessed ? 'A' : '-',
2644	Pdpe.n.u3Reserved & 1? '?' : '.', /* ignored */
2645	Pdpe.n.u3Reserved & 4? '!' : '.', /* mbz */
2646	Pdpe.n.u1WriteThru ? "WT" : "--",
2647	Pdpe.n.u1CacheDisable? "CD" : "--",
2648	Pdpe.n.u3Reserved & 2? "!" : "..",/* mbz */
2649	Pdpe.n.u1NoExecute ? "NX" : "--",
2650	Pdpe.u & BIT(9) ? '1' : '0',
2651	Pdpe.u & PGM_PLXFLAGS_PERMANENT ? 'p' : '-',
2652	Pdpe.u & BIT(11) ? '1' : '0',
2653	Pdpe.u & X86_PDPE_PG_MASK);
2654	else
2655	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a p ? /
2656	"%08x 0 \| P %c %c %c %c %c %s %s %s %s .. %c%c%c %016llx\n",
2657	i << X86_PDPTR_SHIFT,
2658	Pdpe.n.u1Write ? '!' : '.', /* mbz */
2659	Pdpe.n.u1User ? '!' : '.', /* mbz */
2660	Pdpe.n.u1Accessed ? '!' : '.', /* mbz */
2661	Pdpe.n.u3Reserved & 1? '!' : '.', /* mbz */
2662	Pdpe.n.u3Reserved & 4? '!' : '.', /* mbz */
2663	Pdpe.n.u1WriteThru ? "WT" : "--",
2664	Pdpe.n.u1CacheDisable? "CD" : "--",
2665	Pdpe.n.u3Reserved & 2? "!" : "..",/* mbz */
2666	Pdpe.n.u1NoExecute ? "NX" : "--",
2667	Pdpe.u & BIT(9) ? '1' : '0',
2668	Pdpe.u & PGM_PLXFLAGS_PERMANENT ? 'p' : '-',
2669	Pdpe.u & BIT(11) ? '1' : '0',
2670	Pdpe.u & X86_PDPE_PG_MASK);
2671	if (cMaxDepth >= 1)
2672	{
2673	int rc2 = pgmR3DumpHierarchyHCPaePD(pVM, Pdpe.u & X86_PDPE_PG_MASK, u64Address + ((uint64_t)i << X86_PDPTR_SHIFT),
2674	cr4, fLongMode, cMaxDepth - 1, pHlp);
2675	if (rc2 < rc && VBOX_SUCCESS(rc))
2676	rc = rc2;
2677	}
2678	}
2679	}
2680	return rc;
2681	}
2682
2683
2684	/**
2685	* Dumps a 32-bit shadow page table.
2686	*
2687	* @returns VBox status code (VINF_SUCCESS).
2688	* @param pVM The VM handle.
2689	* @param HCPhys The physical address of the table.
2690	* @param cr4 The CR4, PSE is currently used.
2691	* @param cMaxDepth The maxium depth.
2692	* @param pHlp Pointer to the output functions.
2693	*/
2694	static int pgmR3DumpHierarchyHcPaePML4(PVM pVM, RTHCPHYS HCPhys, uint32_t cr4, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
2695	{
2696	PX86PML4 pPML4 = (PX86PML4)MMPagePhys2Page(pVM, HCPhys);
2697	if (!pPML4)
2698	{
2699	pHlp->pfnPrintf(pHlp, "Page map level 4 at HCPhys=%#VHp was not found in the page pool!\n", HCPhys);
2700	return VERR_INVALID_PARAMETER;
2701	}
2702
2703	int rc = VINF_SUCCESS;
2704	for (unsigned i = 0; i < ELEMENTS(pPML4->a); i++)
2705	{
2706	X86PML4E Pml4e = pPML4->a[i];
2707	if (Pml4e.n.u1Present)
2708	{
2709	uint64_t u64Address = ((uint64_t)i << X86_PML4_SHIFT) \| (((uint64_t)i >> (X86_PML4_SHIFT - X86_PDPTR_SHIFT - 1)) * 0xffff000000000000ULL);
2710	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a p ? /
2711	"%016llx 0 \| P %c %c %c %c %c %s %s %s %s .. %c%c%c %016llx\n",
2712	u64Address,
2713	Pml4e.n.u1Write ? 'W' : 'R',
2714	Pml4e.n.u1User ? 'U' : 'S',
2715	Pml4e.n.u1Accessed ? 'A' : '-',
2716	Pml4e.n.u3Reserved & 1? '?' : '.', /* ignored */
2717	Pml4e.n.u3Reserved & 4? '!' : '.', /* mbz */
2718	Pml4e.n.u1WriteThru ? "WT" : "--",
2719	Pml4e.n.u1CacheDisable? "CD" : "--",
2720	Pml4e.n.u3Reserved & 2? "!" : "..",/* mbz */
2721	Pml4e.n.u1NoExecute ? "NX" : "--",
2722	Pml4e.u & BIT(9) ? '1' : '0',
2723	Pml4e.u & PGM_PLXFLAGS_PERMANENT ? 'p' : '-',
2724	Pml4e.u & BIT(11) ? '1' : '0',
2725	Pml4e.u & X86_PML4E_PG_MASK);
2726
2727	if (cMaxDepth >= 1)
2728	{
2729	int rc2 = pgmR3DumpHierarchyHCPaePDPTR(pVM, Pml4e.u & X86_PML4E_PG_MASK, u64Address, cr4, true, cMaxDepth - 1, pHlp);
2730	if (rc2 < rc && VBOX_SUCCESS(rc))
2731	rc = rc2;
2732	}
2733	}
2734	}
2735	return rc;
2736	}
2737
2738
2739	/**
2740	* Dumps a 32-bit shadow page table.
2741	*
2742	* @returns VBox status code (VINF_SUCCESS).
2743	* @param pVM The VM handle.
2744	* @param pPT Pointer to the page table.
2745	* @param u32Address The virtual address this table starts at.
2746	* @param pHlp Pointer to the output functions.
2747	*/
2748	int pgmR3DumpHierarchyHC32BitPT(PVM pVM, PX86PT pPT, uint32_t u32Address, PCDBGFINFOHLP pHlp)
2749	{
2750	for (unsigned i = 0; i < ELEMENTS(pPT->a); i++)
2751	{
2752	X86PTE Pte = pPT->a[i];
2753	if (Pte.n.u1Present)
2754	{
2755	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a m d /
2756	"%08x 1 \| P %c %c %c %c %c %s %s %s .. 4K %c%c%c %08x\n",
2757	u32Address + (i << X86_PT_SHIFT),
2758	Pte.n.u1Write ? 'W' : 'R',
2759	Pte.n.u1User ? 'U' : 'S',
2760	Pte.n.u1Accessed ? 'A' : '-',
2761	Pte.n.u1Dirty ? 'D' : '-',
2762	Pte.n.u1Global ? 'G' : '-',
2763	Pte.n.u1WriteThru ? "WT" : "--",
2764	Pte.n.u1CacheDisable? "CD" : "--",
2765	Pte.n.u1PAT ? "AT" : "--",
2766	Pte.u & PGM_PTFLAGS_TRACK_DIRTY ? 'd' : '-',
2767	Pte.u & BIT(10) ? '1' : '0',
2768	Pte.u & PGM_PTFLAGS_CSAM_VALIDATED ? 'v' : '-',
2769	Pte.u & X86_PDE_PG_MASK);
2770	}
2771	}
2772	return VINF_SUCCESS;
2773	}
2774
2775
2776	/**
2777	* Dumps a 32-bit shadow page directory and page tables.
2778	*
2779	* @returns VBox status code (VINF_SUCCESS).
2780	* @param pVM The VM handle.
2781	* @param cr3 The root of the hierarchy.
2782	* @param cr4 The CR4, PSE is currently used.
2783	* @param cMaxDepth How deep into the hierarchy the dumper should go.
2784	* @param pHlp Pointer to the output functions.
2785	*/
2786	int pgmR3DumpHierarchyHC32BitPD(PVM pVM, uint32_t cr3, uint32_t cr4, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
2787	{
2788	PX86PD pPD = (PX86PD)MMPagePhys2Page(pVM, cr3 & X86_CR3_PAGE_MASK);
2789	if (!pPD)
2790	{
2791	pHlp->pfnPrintf(pHlp, "Page directory at %#x was not found in the page pool!\n", cr3 & X86_CR3_PAGE_MASK);
2792	return VERR_INVALID_PARAMETER;
2793	}
2794
2795	int rc = VINF_SUCCESS;
2796	for (unsigned i = 0; i < ELEMENTS(pPD->a); i++)
2797	{
2798	X86PDE Pde = pPD->a[i];
2799	if (Pde.n.u1Present)
2800	{
2801	const uint32_t u32Address = i << X86_PD_SHIFT;
2802	if ((cr4 & X86_CR4_PSE) && Pde.b.u1Size)
2803	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a m d /
2804	"%08x 0 \| P %c %c %c %c %c %s %s %s .. 4M %c%c%c %08x\n",
2805	u32Address,
2806	Pde.b.u1Write ? 'W' : 'R',
2807	Pde.b.u1User ? 'U' : 'S',
2808	Pde.b.u1Accessed ? 'A' : '-',
2809	Pde.b.u1Dirty ? 'D' : '-',
2810	Pde.b.u1Global ? 'G' : '-',
2811	Pde.b.u1WriteThru ? "WT" : "--",
2812	Pde.b.u1CacheDisable? "CD" : "--",
2813	Pde.b.u1PAT ? "AT" : "--",
2814	Pde.u & BIT64(9) ? '1' : '0',
2815	Pde.u & PGM_PDFLAGS_MAPPING ? 'm' : '-',
2816	Pde.u & PGM_PDFLAGS_TRACK_DIRTY ? 'd' : '-',
2817	Pde.u & X86_PDE4M_PG_MASK);
2818	else
2819	{
2820	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a m d /
2821	"%08x 0 \| P %c %c %c %c %c %s %s .. .. 4K %c%c%c %08x\n",
2822	u32Address,
2823	Pde.n.u1Write ? 'W' : 'R',
2824	Pde.n.u1User ? 'U' : 'S',
2825	Pde.n.u1Accessed ? 'A' : '-',
2826	Pde.n.u1Reserved0 ? '?' : '.', /* ignored */
2827	Pde.n.u1Reserved1 ? '?' : '.', /* ignored */
2828	Pde.n.u1WriteThru ? "WT" : "--",
2829	Pde.n.u1CacheDisable? "CD" : "--",
2830	Pde.u & BIT64(9) ? '1' : '0',
2831	Pde.u & PGM_PDFLAGS_MAPPING ? 'm' : '-',
2832	Pde.u & PGM_PDFLAGS_TRACK_DIRTY ? 'd' : '-',
2833	Pde.u & X86_PDE_PG_MASK);
2834	if (cMaxDepth >= 1)
2835	{
2836	/** @todo what about using the page pool for mapping PTs? */
2837	RTHCPHYS HCPhys = Pde.u & X86_PDE_PG_MASK;
2838	PX86PT pPT = NULL;
2839	if (!(Pde.u & PGM_PDFLAGS_MAPPING))
2840	pPT = (PX86PT)MMPagePhys2Page(pVM, HCPhys);
2841	else
2842	{
2843	for (PPGMMAPPING pMap = pVM->pgm.s.pMappingsHC; pMap; pMap = pMap->pNextHC)
2844	if (u32Address - pMap->GCPtr < pMap->cb)
2845	{
2846	int iPDE = (u32Address - pMap->GCPtr) >> X86_PD_SHIFT;
2847	if (pMap->aPTs[iPDE].HCPhysPT != HCPhys)
2848	pHlp->pfnPrintf(pHlp, "%08x error! Mapping error! PT %d has HCPhysPT=%VHp not %VHp is in the PD.\n",
2849	u32Address, iPDE, pMap->aPTs[iPDE].HCPhysPT, HCPhys);
2850	pPT = pMap->aPTs[iPDE].pPTHC;
2851	}
2852	}
2853	int rc2 = VERR_INVALID_PARAMETER;
2854	if (pPT)
2855	rc2 = pgmR3DumpHierarchyHC32BitPT(pVM, pPT, u32Address, pHlp);
2856	else
2857	pHlp->pfnPrintf(pHlp, "%08x error! Page table at %#x was not found in the page pool!\n", u32Address, HCPhys);
2858	if (rc2 < rc && VBOX_SUCCESS(rc))
2859	rc = rc2;
2860	}
2861	}
2862	}
2863	}
2864
2865	return rc;
2866	}
2867
2868
2869	/**
2870	* Dumps a 32-bit shadow page table.
2871	*
2872	* @returns VBox status code (VINF_SUCCESS).
2873	* @param pVM The VM handle.
2874	* @param pPT Pointer to the page table.
2875	* @param u32Address The virtual address this table starts at.
2876	* @param PhysSearch Address to search for.
2877	*/
2878	int pgmR3DumpHierarchyGC32BitPT(PVM pVM, PX86PT pPT, uint32_t u32Address, RTGCPHYS PhysSearch)
2879	{
2880	for (unsigned i = 0; i < ELEMENTS(pPT->a); i++)
2881	{
2882	X86PTE Pte = pPT->a[i];
2883	if (Pte.n.u1Present)
2884	{
2885	Log(( /P R S A D G WT CD AT NX 4M a m d /
2886	"%08x 1 \| P %c %c %c %c %c %s %s %s .. 4K %c%c%c %08x\n",
2887	u32Address + (i << X86_PT_SHIFT),
2888	Pte.n.u1Write ? 'W' : 'R',
2889	Pte.n.u1User ? 'U' : 'S',
2890	Pte.n.u1Accessed ? 'A' : '-',
2891	Pte.n.u1Dirty ? 'D' : '-',
2892	Pte.n.u1Global ? 'G' : '-',
2893	Pte.n.u1WriteThru ? "WT" : "--",
2894	Pte.n.u1CacheDisable? "CD" : "--",
2895	Pte.n.u1PAT ? "AT" : "--",
2896	Pte.u & PGM_PTFLAGS_TRACK_DIRTY ? 'd' : '-',
2897	Pte.u & BIT(10) ? '1' : '0',
2898	Pte.u & PGM_PTFLAGS_CSAM_VALIDATED ? 'v' : '-',
2899	Pte.u & X86_PDE_PG_MASK));
2900
2901	if ((Pte.u & X86_PDE_PG_MASK) == PhysSearch)
2902	{
2903	uint64_t fPageShw = 0;
2904	RTHCPHYS pPhysHC = 0;
2905
2906	PGMShwGetPage(pVM, (RTGCPTR)(u32Address + (i << X86_PT_SHIFT)), &fPageShw, &pPhysHC);
2907	Log(("Found %VGp at %VGv -> flags=%llx\n", PhysSearch, (RTGCPTR)(u32Address + (i << X86_PT_SHIFT)), fPageShw));
2908	}
2909	}
2910	}
2911	return VINF_SUCCESS;
2912	}
2913
2914
2915	/**
2916	* Dumps a 32-bit guest page directory and page tables.
2917	*
2918	* @returns VBox status code (VINF_SUCCESS).
2919	* @param pVM The VM handle.
2920	* @param cr3 The root of the hierarchy.
2921	* @param cr4 The CR4, PSE is currently used.
2922	* @param PhysSearch Address to search for.
2923	*/
2924	PGMR3DECL(int) PGMR3DumpHierarchyGC(PVM pVM, uint32_t cr3, uint32_t cr4, RTGCPHYS PhysSearch)
2925	{
2926	bool fLongMode = false;
2927	const unsigned cch = fLongMode ? 16 : 8; NOREF(cch);
2928	PX86PD pPD = 0;
2929
2930	int rc = PGM_GCPHYS_2_PTR(pVM, cr3 & X86_CR3_PAGE_MASK, &pPD);
2931	if (VBOX_FAILURE(rc) \|\| !pPD)
2932	{
2933	Log(("Page directory at %#x was not found in the page pool!\n", cr3 & X86_CR3_PAGE_MASK));
2934	return VERR_INVALID_PARAMETER;
2935	}
2936
2937	Log(("cr3=%08x cr4=%08x%s\n"
2938	"%-*s P - Present\n"
2939	"%-*s \| R/W - Read (0) / Write (1)\n"
2940	"%-*s \| \| U/S - User (1) / Supervisor (0)\n"
2941	"%-*s \| \| \| A - Accessed\n"
2942	"%-*s \| \| \| \| D - Dirty\n"
2943	"%-*s \| \| \| \| \| G - Global\n"
2944	"%-*s \| \| \| \| \| \| WT - Write thru\n"
2945	"%-*s \| \| \| \| \| \| \| CD - Cache disable\n"
2946	"%-*s \| \| \| \| \| \| \| \| AT - Attribute table (PAT)\n"
2947	"%-*s \| \| \| \| \| \| \| \| \| NX - No execute (K8)\n"
2948	"%-*s \| \| \| \| \| \| \| \| \| \| 4K/4M/2M - Page size.\n"
2949	"%-*s \| \| \| \| \| \| \| \| \| \| \| AVL - a=allocated; m=mapping; d=track dirty;\n"
2950	"%-*s \| \| \| \| \| \| \| \| \| \| \| \| p=permanent; v=validated;\n"
2951	"%-*s Level \| \| \| \| \| \| \| \| \| \| \| \| Page\n"
2952	/* xxxx n **** P R S A D G WT CD AT NX 4M AVL xxxxxxxxxxxxx
2953	- W U - - - -- -- -- -- -- 010 */
2954	, cr3, cr4, fLongMode ? " Long Mode" : "",
2955	cch, "", cch, "", cch, "", cch, "", cch, "", cch, "", cch, "",
2956	cch, "", cch, "", cch, "", cch, "", cch, "", cch, "", cch, "Address"));
2957
2958	for (unsigned i = 0; i < ELEMENTS(pPD->a); i++)
2959	{
2960	X86PDE Pde = pPD->a[i];
2961	if (Pde.n.u1Present)
2962	{
2963	const uint32_t u32Address = i << X86_PD_SHIFT;
2964
2965	if ((cr4 & X86_CR4_PSE) && Pde.b.u1Size)
2966	Log(( /P R S A D G WT CD AT NX 4M a m d /
2967	"%08x 0 \| P %c %c %c %c %c %s %s %s .. 4M %c%c%c %08x\n",
2968	u32Address,
2969	Pde.b.u1Write ? 'W' : 'R',
2970	Pde.b.u1User ? 'U' : 'S',
2971	Pde.b.u1Accessed ? 'A' : '-',
2972	Pde.b.u1Dirty ? 'D' : '-',
2973	Pde.b.u1Global ? 'G' : '-',
2974	Pde.b.u1WriteThru ? "WT" : "--",
2975	Pde.b.u1CacheDisable? "CD" : "--",
2976	Pde.b.u1PAT ? "AT" : "--",
2977	Pde.u & BIT(9) ? '1' : '0',
2978	Pde.u & BIT(10) ? '1' : '0',
2979	Pde.u & BIT(11) ? '1' : '0',
2980	Pde.u & X86_PDE4M_PG_MASK));
2981	/** @todo PhysSearch */
2982	else
2983	{
2984	Log(( /P R S A D G WT CD AT NX 4M a m d /
2985	"%08x 0 \| P %c %c %c %c %c %s %s .. .. 4K %c%c%c %08x\n",
2986	u32Address,
2987	Pde.n.u1Write ? 'W' : 'R',
2988	Pde.n.u1User ? 'U' : 'S',
2989	Pde.n.u1Accessed ? 'A' : '-',
2990	Pde.n.u1Reserved0 ? '?' : '.', /* ignored */
2991	Pde.n.u1Reserved1 ? '?' : '.', /* ignored */
2992	Pde.n.u1WriteThru ? "WT" : "--",
2993	Pde.n.u1CacheDisable? "CD" : "--",
2994	Pde.u & BIT(9) ? '1' : '0',
2995	Pde.u & BIT(10) ? '1' : '0',
2996	Pde.u & BIT(11) ? '1' : '0',
2997	Pde.u & X86_PDE_PG_MASK));
2998	////if (cMaxDepth >= 1)
2999	{
3000	/** @todo what about using the page pool for mapping PTs? */
3001	RTGCPHYS GCPhys = Pde.u & X86_PDE_PG_MASK;
3002	PX86PT pPT = NULL;
3003
3004	rc = PGM_GCPHYS_2_PTR(pVM, GCPhys, &pPT);
3005
3006	int rc2 = VERR_INVALID_PARAMETER;
3007	if (pPT)
3008	rc2 = pgmR3DumpHierarchyGC32BitPT(pVM, pPT, u32Address, PhysSearch);
3009	else
3010	Log(("%08x error! Page table at %#x was not found in the page pool!\n", u32Address, GCPhys));
3011	if (rc2 < rc && VBOX_SUCCESS(rc))
3012	rc = rc2;
3013	}
3014	}
3015	}
3016	}
3017
3018	return rc;
3019	}
3020
3021
3022	/**
3023	* Dumps a page table hierarchy use only physical addresses and cr4/lm flags.
3024	*
3025	* @returns VBox status code (VINF_SUCCESS).
3026	* @param pVM The VM handle.
3027	* @param cr3 The root of the hierarchy.
3028	* @param cr4 The cr4, only PAE and PSE is currently used.
3029	* @param fLongMode Set if long mode, false if not long mode.
3030	* @param cMaxDepth Number of levels to dump.
3031	* @param pHlp Pointer to the output functions.
3032	*/
3033	PGMR3DECL(int) PGMR3DumpHierarchyHC(PVM pVM, uint32_t cr3, uint32_t cr4, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
3034	{
3035	if (!pHlp)
3036	pHlp = DBGFR3InfoLogHlp();
3037	if (!cMaxDepth)
3038	return VINF_SUCCESS;
3039	const unsigned cch = fLongMode ? 16 : 8;
3040	pHlp->pfnPrintf(pHlp,
3041	"cr3=%08x cr4=%08x%s\n"
3042	"%-*s P - Present\n"
3043	"%-*s \| R/W - Read (0) / Write (1)\n"
3044	"%-*s \| \| U/S - User (1) / Supervisor (0)\n"
3045	"%-*s \| \| \| A - Accessed\n"
3046	"%-*s \| \| \| \| D - Dirty\n"
3047	"%-*s \| \| \| \| \| G - Global\n"
3048	"%-*s \| \| \| \| \| \| WT - Write thru\n"
3049	"%-*s \| \| \| \| \| \| \| CD - Cache disable\n"
3050	"%-*s \| \| \| \| \| \| \| \| AT - Attribute table (PAT)\n"
3051	"%-*s \| \| \| \| \| \| \| \| \| NX - No execute (K8)\n"
3052	"%-*s \| \| \| \| \| \| \| \| \| \| 4K/4M/2M - Page size.\n"
3053	"%-*s \| \| \| \| \| \| \| \| \| \| \| AVL - a=allocated; m=mapping; d=track dirty;\n"
3054	"%-*s \| \| \| \| \| \| \| \| \| \| \| \| p=permanent; v=validated;\n"
3055	"%-*s Level \| \| \| \| \| \| \| \| \| \| \| \| Page\n"
3056	/* xxxx n **** P R S A D G WT CD AT NX 4M AVL xxxxxxxxxxxxx
3057	- W U - - - -- -- -- -- -- 010 */
3058	, cr3, cr4, fLongMode ? " Long Mode" : "",
3059	cch, "", cch, "", cch, "", cch, "", cch, "", cch, "", cch, "",
3060	cch, "", cch, "", cch, "", cch, "", cch, "", cch, "", cch, "Address");
3061	if (cr4 & X86_CR4_PAE)
3062	{
3063	if (fLongMode)
3064	return pgmR3DumpHierarchyHcPaePML4(pVM, cr3 & X86_CR3_PAGE_MASK, cr4, cMaxDepth, pHlp);
3065	return pgmR3DumpHierarchyHCPaePDPTR(pVM, cr3 & X86_CR3_PAE_PAGE_MASK, 0, cr4, false, cMaxDepth, pHlp);
3066	}
3067	return pgmR3DumpHierarchyHC32BitPD(pVM, cr3 & X86_CR3_PAGE_MASK, cr4, cMaxDepth, pHlp);
3068	}
3069
3070
3071
3072	#ifdef VBOX_WITH_DEBUGGER
3073	/**
3074	* The '.pgmram' command.
3075	*
3076	* @returns VBox status.
3077	* @param pCmd Pointer to the command descriptor (as registered).
3078	* @param pCmdHlp Pointer to command helper functions.
3079	* @param pVM Pointer to the current VM (if any).
3080	* @param paArgs Pointer to (readonly) array of arguments.
3081	* @param cArgs Number of arguments in the array.
3082	*/
3083	static DECLCALLBACK(int) pgmR3CmdRam(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
3084	{
3085	/*
3086	* Validate input.
3087	*/
3088	if (!pVM)
3089	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires VM to be selected.\n");
3090	if (!pVM->pgm.s.pRamRangesGC)
3091	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Sorry, no Ram is registered.\n");
3092
3093	/*
3094	* Dump the ranges.
3095	*/
3096	int rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL, "From - To (incl) pvHC\n");
3097	PPGMRAMRANGE pRam;
3098	for (pRam = pVM->pgm.s.pRamRangesHC; pRam; pRam = pRam->pNextHC)
3099	{
3100	rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL,
3101	"%VGp - %VGp %p\n",
3102	pRam->GCPhys, pRam->GCPhysLast, pRam->pvHC);
3103	if (VBOX_FAILURE(rc))
3104	return rc;
3105	}
3106
3107	return VINF_SUCCESS;
3108	}
3109
3110
3111	/**
3112	* The '.pgmmap' command.
3113	*
3114	* @returns VBox status.
3115	* @param pCmd Pointer to the command descriptor (as registered).
3116	* @param pCmdHlp Pointer to command helper functions.
3117	* @param pVM Pointer to the current VM (if any).
3118	* @param paArgs Pointer to (readonly) array of arguments.
3119	* @param cArgs Number of arguments in the array.
3120	*/
3121	static DECLCALLBACK(int) pgmR3CmdMap(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
3122	{
3123	/*
3124	* Validate input.
3125	*/
3126	if (!pVM)
3127	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires VM to be selected.\n");
3128	if (!pVM->pgm.s.pMappingsHC)
3129	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Sorry, no mappings are registered.\n");
3130
3131	/*
3132	* Print message about the fixedness of the mappings.
3133	*/
3134	int rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL, pVM->pgm.s.fMappingsFixed ? "The mappings are FIXED.\n" : "The mappings are FLOATING.\n");
3135	if (VBOX_FAILURE(rc))
3136	return rc;
3137
3138	/*
3139	* Dump the ranges.
3140	*/
3141	PPGMMAPPING pCur;
3142	for (pCur = pVM->pgm.s.pMappingsHC; pCur; pCur = pCur->pNextHC)
3143	{
3144	rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL,
3145	"%08x - %08x %s\n",
3146	pCur->GCPtr, pCur->GCPtrLast, pCur->pszDesc);
3147	if (VBOX_FAILURE(rc))
3148	return rc;
3149	}
3150
3151	return VINF_SUCCESS;
3152	}
3153
3154
3155	/**
3156	* The '.pgmsync' command.
3157	*
3158	* @returns VBox status.
3159	* @param pCmd Pointer to the command descriptor (as registered).
3160	* @param pCmdHlp Pointer to command helper functions.
3161	* @param pVM Pointer to the current VM (if any).
3162	* @param paArgs Pointer to (readonly) array of arguments.
3163	* @param cArgs Number of arguments in the array.
3164	*/
3165	static DECLCALLBACK(int) pgmR3CmdSync(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
3166	{
3167	/*
3168	* Validate input.
3169	*/
3170	if (!pVM)
3171	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires VM to be selected.\n");
3172
3173	/*
3174	* Force page directory sync.
3175	*/
3176	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
3177
3178	int rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Forcing page directory sync.\n");
3179	if (VBOX_FAILURE(rc))
3180	return rc;
3181
3182	return VINF_SUCCESS;
3183	}
3184
3185
3186	/**
3187	* The '.pgmsyncalways' command.
3188	*
3189	* @returns VBox status.
3190	* @param pCmd Pointer to the command descriptor (as registered).
3191	* @param pCmdHlp Pointer to command helper functions.
3192	* @param pVM Pointer to the current VM (if any).
3193	* @param paArgs Pointer to (readonly) array of arguments.
3194	* @param cArgs Number of arguments in the array.
3195	*/
3196	static DECLCALLBACK(int) pgmR3CmdSyncAlways(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
3197	{
3198	/*
3199	* Validate input.
3200	*/
3201	if (!pVM)
3202	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires VM to be selected.\n");
3203
3204	/*
3205	* Force page directory sync.
3206	*/
3207	if (pVM->pgm.s.fSyncFlags & PGM_SYNC_ALWAYS)
3208	{
3209	ASMAtomicAndU32(&pVM->pgm.s.fSyncFlags, ~PGM_SYNC_ALWAYS);
3210	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Disabled permanent forced page directory syncing.\n");
3211	}
3212	else
3213	{
3214	ASMAtomicOrU32(&pVM->pgm.s.fSyncFlags, PGM_SYNC_ALWAYS);
3215	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
3216	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Enabled permanent forced page directory syncing.\n");
3217	}
3218	}
3219
3220	#endif
3221
3222	/**
3223	* pvUser argument of the pgmR3CheckIntegrity*Node callbacks.
3224	*/
3225	typedef struct PGMCHECKINTARGS
3226	{
3227	bool fLeftToRight; /*< true: left-to-right; false: right-to-left. /
3228	PPGMPHYSHANDLER pPrevPhys;
3229	PPGMVIRTHANDLER pPrevVirt;
3230	PPGMPHYS2VIRTHANDLER pPrevPhys2Virt;
3231	PVM pVM;
3232	} PGMCHECKINTARGS, *PPGMCHECKINTARGS;
3233
3234	/**
3235	* Validate a node in the physical handler tree.
3236	*
3237	* @returns 0 on if ok, other wise 1.
3238	* @param pNode The handler node.
3239	* @param pvUser pVM.
3240	*/
3241	static DECLCALLBACK(int) pgmR3CheckIntegrityPhysHandlerNode(PAVLROGCPHYSNODECORE pNode, void *pvUser)
3242	{
3243	PPGMCHECKINTARGS pArgs = (PPGMCHECKINTARGS)pvUser;
3244	PPGMPHYSHANDLER pCur = (PPGMPHYSHANDLER)pNode;
3245	AssertReleaseReturn(!((uintptr_t)pCur & 7), 1);
3246	AssertReleaseMsg(pCur->Core.Key <= pCur->Core.KeyLast,("pCur=%p %VGp-%VGp %s\n", pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
3247	AssertReleaseMsg( !pArgs->pPrevPhys
3248	\|\| (pArgs->fLeftToRight ? pArgs->pPrevPhys->Core.KeyLast < pCur->Core.Key : pArgs->pPrevPhys->Core.KeyLast > pCur->Core.Key),
3249	("pPrevPhys=%p %VGp-%VGp %s\n"
3250	" pCur=%p %VGp-%VGp %s\n",
3251	pArgs->pPrevPhys, pArgs->pPrevPhys->Core.Key, pArgs->pPrevPhys->Core.KeyLast, pArgs->pPrevPhys->pszDesc,
3252	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
3253	pArgs->pPrevPhys = pCur;
3254	return 0;
3255	}
3256
3257
3258	/**
3259	* Validate a node in the virtual handler tree.
3260	*
3261	* @returns 0 on if ok, other wise 1.
3262	* @param pNode The handler node.
3263	* @param pvUser pVM.
3264	*/
3265	static DECLCALLBACK(int) pgmR3CheckIntegrityVirtHandlerNode(PAVLROGCPTRNODECORE pNode, void *pvUser)
3266	{
3267	PPGMCHECKINTARGS pArgs = (PPGMCHECKINTARGS)pvUser;
3268	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)pNode;
3269	AssertReleaseReturn(!((uintptr_t)pCur & 7), 1);
3270	AssertReleaseMsg(pCur->Core.Key <= pCur->Core.KeyLast,("pCur=%p %VGv-%VGv %s\n", pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
3271	AssertReleaseMsg( !pArgs->pPrevVirt
3272	\|\| (pArgs->fLeftToRight ? pArgs->pPrevVirt->Core.KeyLast < pCur->Core.Key : pArgs->pPrevVirt->Core.KeyLast > pCur->Core.Key),
3273	("pPrevVirt=%p %VGv-%VGv %s\n"
3274	" pCur=%p %VGv-%VGv %s\n",
3275	pArgs->pPrevVirt, pArgs->pPrevVirt->Core.Key, pArgs->pPrevVirt->Core.KeyLast, pArgs->pPrevVirt->pszDesc,
3276	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
3277	for (unsigned iPage = 0; iPage < pCur->cPages; iPage++)
3278	{
3279	AssertReleaseMsg(pCur->aPhysToVirt[iPage].offVirtHandler == -RT_OFFSETOF(PGMVIRTHANDLER, aPhysToVirt[iPage]),
3280	("pCur=%p %VGv-%VGv %s\n"
3281	"iPage=%d offVirtHandle=%#x expected %#x\n",
3282	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc,
3283	iPage, pCur->aPhysToVirt[iPage].offVirtHandler, -RT_OFFSETOF(PGMVIRTHANDLER, aPhysToVirt[iPage])));
3284	}
3285	pArgs->pPrevVirt = pCur;
3286	return 0;
3287	}
3288
3289
3290	/**
3291	* Validate a node in the virtual handler tree.
3292	*
3293	* @returns 0 on if ok, other wise 1.
3294	* @param pNode The handler node.
3295	* @param pvUser pVM.
3296	*/
3297	static DECLCALLBACK(int) pgmR3CheckIntegrityPhysToVirtHandlerNode(PAVLROGCPHYSNODECORE pNode, void *pvUser)
3298	{
3299	PPGMCHECKINTARGS pArgs = (PPGMCHECKINTARGS)pvUser;
3300	PPGMPHYS2VIRTHANDLER pCur = (PPGMPHYS2VIRTHANDLER)pNode;
3301	AssertReleaseMsgReturn(!((uintptr_t)pCur & 3), ("\n"), 1);
3302	AssertReleaseMsgReturn(!(pCur->offVirtHandler & 3), ("\n"), 1);
3303	AssertReleaseMsg(pCur->Core.Key <= pCur->Core.KeyLast,("pCur=%p %VGp-%VGp\n", pCur, pCur->Core.Key, pCur->Core.KeyLast));
3304	AssertReleaseMsg( !pArgs->pPrevPhys2Virt
3305	\|\| (pArgs->fLeftToRight ? pArgs->pPrevPhys2Virt->Core.KeyLast < pCur->Core.Key : pArgs->pPrevPhys2Virt->Core.KeyLast > pCur->Core.Key),
3306	("pPrevPhys2Virt=%p %VGp-%VGp\n"
3307	" pCur=%p %VGp-%VGp\n",
3308	pArgs->pPrevPhys2Virt, pArgs->pPrevPhys2Virt->Core.Key, pArgs->pPrevPhys2Virt->Core.KeyLast,
3309	pCur, pCur->Core.Key, pCur->Core.KeyLast));
3310	AssertReleaseMsg( !pArgs->pPrevPhys2Virt
3311	\|\| (pArgs->fLeftToRight ? pArgs->pPrevPhys2Virt->Core.KeyLast < pCur->Core.Key : pArgs->pPrevPhys2Virt->Core.KeyLast > pCur->Core.Key),
3312	("pPrevPhys2Virt=%p %VGp-%VGp\n"
3313	" pCur=%p %VGp-%VGp\n",
3314	pArgs->pPrevPhys2Virt, pArgs->pPrevPhys2Virt->Core.Key, pArgs->pPrevPhys2Virt->Core.KeyLast,
3315	pCur, pCur->Core.Key, pCur->Core.KeyLast));
3316	AssertReleaseMsg((pCur->offNextAlias & (PGMPHYS2VIRTHANDLER_IN_TREE \| PGMPHYS2VIRTHANDLER_IS_HEAD)) == (PGMPHYS2VIRTHANDLER_IN_TREE \| PGMPHYS2VIRTHANDLER_IS_HEAD),
3317	("pCur=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
3318	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias));
3319	if (pCur->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK)
3320	{
3321	PPGMPHYS2VIRTHANDLER pCur2 = pCur;
3322	for (;;)
3323	{
3324	pCur2 = (PPGMPHYS2VIRTHANDLER)((intptr_t)pCur + (pCur->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK));
3325	AssertReleaseMsg(pCur2 != pCur,
3326	(" pCur=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
3327	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias));
3328	AssertReleaseMsg((pCur2->offNextAlias & (PGMPHYS2VIRTHANDLER_IN_TREE \| PGMPHYS2VIRTHANDLER_IS_HEAD)) == PGMPHYS2VIRTHANDLER_IN_TREE,
3329	(" pCur=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
3330	"pCur2=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
3331	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias,
3332	pCur2, pCur2->Core.Key, pCur2->Core.KeyLast, pCur2->offVirtHandler, pCur2->offNextAlias));
3333	AssertReleaseMsg((pCur2->Core.Key ^ pCur->Core.Key) < PAGE_SIZE,
3334	(" pCur=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
3335	"pCur2=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
3336	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias,
3337	pCur2, pCur2->Core.Key, pCur2->Core.KeyLast, pCur2->offVirtHandler, pCur2->offNextAlias));
3338	AssertReleaseMsg((pCur2->Core.KeyLast ^ pCur->Core.KeyLast) < PAGE_SIZE,
3339	(" pCur=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
3340	"pCur2=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
3341	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias,
3342	pCur2, pCur2->Core.Key, pCur2->Core.KeyLast, pCur2->offVirtHandler, pCur2->offNextAlias));
3343	if (!(pCur2->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK))
3344	break;
3345	}
3346	}
3347
3348	pArgs->pPrevPhys2Virt = pCur;
3349	return 0;
3350	}
3351
3352
3353	/**
3354	* Perform an integrity check on the PGM component.
3355	*
3356	* @returns VINF_SUCCESS if everything is fine.
3357	* @returns VBox error status after asserting on integrity breach.
3358	* @param pVM The VM handle.
3359	*/
3360	PDMR3DECL(int) PGMR3CheckIntegrity(PVM pVM)
3361	{
3362	AssertReleaseReturn(pVM->pgm.s.offVM, VERR_INTERNAL_ERROR);
3363
3364	/*
3365	* Check the trees.
3366	*/
3367	int cErrors = 0;
3368	PGMCHECKINTARGS Args = { true, NULL, NULL, NULL, pVM };
3369	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesHC->PhysHandlers, true, pgmR3CheckIntegrityPhysHandlerNode, &Args);
3370	Args.fLeftToRight = false;
3371	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesHC->PhysHandlers, false, pgmR3CheckIntegrityPhysHandlerNode, &Args);
3372	Args.fLeftToRight = true;
3373	cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesHC->VirtHandlers, true, pgmR3CheckIntegrityVirtHandlerNode, &Args);
3374	Args.fLeftToRight = false;
3375	cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesHC->VirtHandlers, false, pgmR3CheckIntegrityVirtHandlerNode, &Args);
3376	Args.fLeftToRight = true;
3377	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesHC->PhysToVirtHandlers, true, pgmR3CheckIntegrityPhysToVirtHandlerNode, &Args);
3378	Args.fLeftToRight = false;
3379	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesHC->PhysToVirtHandlers, false, pgmR3CheckIntegrityPhysToVirtHandlerNode, &Args);
3380
3381	return !cErrors ? VINF_SUCCESS : VERR_INTERNAL_ERROR;
3382	}
3383
3384
3385	/**
3386	* Inform PGM if we want all mappings to be put into the shadow page table. (necessary for e.g. VMX)
3387	*
3388	* @returns VBox status code.
3389	* @param pVM VM handle.
3390	* @param fEnable Enable or disable shadow mappings
3391	*/
3392	PGMR3DECL(int) PGMR3ChangeShwPDMappings(PVM pVM, bool fEnable)
3393	{
3394	pVM->pgm.s.fDisableMappings = fEnable;
3395
3396	size_t cb;
3397	int rc = PGMR3MappingsSize(pVM, &cb);
3398	AssertRCReturn(rc, rc);
3399
3400	/* Pretend the mappings are now fixed; to force a refresh of the reserved PDEs. */
3401	rc = PGMR3MappingsFix(pVM, MM_HYPER_AREA_ADDRESS, cb);
3402	AssertRCReturn(rc, rc);
3403
3404	return VINF_SUCCESS;
3405	}

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source: vbox/trunk/src/VBox/VMM/PGM.cpp@ 1224

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