PGM.cpp@ 13071

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1	/* $Id: PGM.cpp 13067 2008-10-08 10:11:24Z vboxsync $ */
2	/** @file
3	* PGM - Page Manager and Monitor. (Mixing stuff here, not good?)
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22
23	/** @page pg_pgm PGM - The Page Manager and Monitor
24	*
25	* @see grp_pgm,
26	* @ref pg_pgm_pool,
27	* @ref pg_pgm_phys.
28	*
29	*
30	* @section sec_pgm_modes Paging Modes
31	*
32	* There are three memory contexts: Host Context (HC), Guest Context (GC)
33	* and intermediate context. When talking about paging HC can also be refered to
34	* as "host paging", and GC refered to as "shadow paging".
35	*
36	* We define three basic paging modes: 32-bit, PAE and AMD64. The host paging mode
37	* is defined by the host operating system. The mode used in the shadow paging mode
38	* depends on the host paging mode and what the mode the guest is currently in. The
39	* following relation between the two is defined:
40	*
41	* @verbatim
42	Host > 32-bit \| PAE \| AMD64 \|
43	Guest \| \| \| \|
44	==v================================
45	32-bit 32-bit PAE PAE
46	-------\|--------\|--------\|--------\|
47	PAE PAE PAE PAE
48	-------\|--------\|--------\|--------\|
49	AMD64 AMD64 AMD64 AMD64
50	-------\|--------\|--------\|--------\| @endverbatim
51	*
52	* All configuration except those in the diagonal (upper left) are expected to
53	* require special effort from the switcher (i.e. a bit slower).
54	*
55	*
56	*
57	*
58	* @section sec_pgm_shw The Shadow Memory Context
59	*
60	*
61	* [..]
62	*
63	* Because of guest context mappings requires PDPT and PML4 entries to allow
64	* writing on AMD64, the two upper levels will have fixed flags whatever the
65	* guest is thinking of using there. So, when shadowing the PD level we will
66	* calculate the effective flags of PD and all the higher levels. In legacy
67	* PAE mode this only applies to the PWT and PCD bits (the rest are
68	* ignored/reserved/MBZ). We will ignore those bits for the present.
69	*
70	*
71	*
72	* @section sec_pgm_int The Intermediate Memory Context
73	*
74	* The world switch goes thru an intermediate memory context which purpose it is
75	* to provide different mappings of the switcher code. All guest mappings are also
76	* present in this context.
77	*
78	* The switcher code is mapped at the same location as on the host, at an
79	* identity mapped location (physical equals virtual address), and at the
80	* hypervisor location.
81	*
82	* PGM maintain page tables for 32-bit, PAE and AMD64 paging modes. This
83	* simplifies switching guest CPU mode and consistency at the cost of more
84	* code to do the work. All memory use for those page tables is located below
85	* 4GB (this includes page tables for guest context mappings).
86	*
87	*
88	* @subsection subsec_pgm_int_gc Guest Context Mappings
89	*
90	* During assignment and relocation of a guest context mapping the intermediate
91	* memory context is used to verify the new location.
92	*
93	* Guest context mappings are currently restricted to below 4GB, for reasons
94	* of simplicity. This may change when we implement AMD64 support.
95	*
96	*
97	*
98	*
99	* @section sec_pgm_misc Misc
100	*
101	* @subsection subsec_pgm_misc_diff Differences Between Legacy PAE and Long Mode PAE
102	*
103	* The differences between legacy PAE and long mode PAE are:
104	* -# PDPE bits 1, 2, 5 and 6 are defined differently. In leagcy mode they are
105	* all marked down as must-be-zero, while in long mode 1, 2 and 5 have the
106	* usual meanings while 6 is ignored (AMD). This means that upon switching to
107	* legacy PAE mode we'll have to clear these bits and when going to long mode
108	* they must be set. This applies to both intermediate and shadow contexts,
109	* however we don't need to do it for the intermediate one since we're
110	* executing with CR0.WP at that time.
111	* -# CR3 allows a 32-byte aligned address in legacy mode, while in long mode
112	* a page aligned one is required.
113	*
114	*
115	* @section sec_pgm_handlers Access Handlers
116	*
117	* Placeholder.
118	*
119	*
120	* @subsection sec_pgm_handlers_virt Virtual Access Handlers
121	*
122	* Placeholder.
123	*
124	*
125	* @subsection sec_pgm_handlers_virt Virtual Access Handlers
126	*
127	* We currently implement three types of virtual access handlers: ALL, WRITE
128	* and HYPERVISOR (WRITE). See PGMVIRTHANDLERTYPE for some more details.
129	*
130	* The HYPERVISOR access handlers is kept in a separate tree since it doesn't apply
131	* to physical pages (PGMTREES::HyperVirtHandlers) and only needs to be consulted in
132	* a special \#PF case. The ALL and WRITE are in the PGMTREES::VirtHandlers tree, the
133	* rest of this section is going to be about these handlers.
134	*
135	* We'll go thru the life cycle of a handler and try make sense of it all, don't know
136	* how successfull this is gonna be...
137	*
138	* 1. A handler is registered thru the PGMR3HandlerVirtualRegister and
139	* PGMHandlerVirtualRegisterEx APIs. We check for conflicting virtual handlers
140	* and create a new node that is inserted into the AVL tree (range key). Then
141	* a full PGM resync is flagged (clear pool, sync cr3, update virtual bit of PGMPAGE).
142	*
143	* 2. The following PGMSyncCR3/SyncCR3 operation will first make invoke HandlerVirtualUpdate.
144	*
145	* 2a. HandlerVirtualUpdate will will lookup all the pages covered by virtual handlers
146	* via the current guest CR3 and update the physical page -> virtual handler
147	* translation. Needless to say, this doesn't exactly scale very well. If any changes
148	* are detected, it will flag a virtual bit update just like we did on registration.
149	* PGMPHYS pages with changes will have their virtual handler state reset to NONE.
150	*
151	* 2b. The virtual bit update process will iterate all the pages covered by all the
152	* virtual handlers and update the PGMPAGE virtual handler state to the max of all
153	* virtual handlers on that page.
154	*
155	* 2c. Back in SyncCR3 we will now flush the entire shadow page cache to make sure
156	* we don't miss any alias mappings of the monitored pages.
157	*
158	* 2d. SyncCR3 will then proceed with syncing the CR3 table.
159	*
160	* 3. \#PF(np,read) on a page in the range. This will cause it to be synced
161	* read-only and resumed if it's a WRITE handler. If it's an ALL handler we
162	* will call the handlers like in the next step. If the physical mapping has
163	* changed we will - some time in the future - perform a handler callback
164	* (optional) and update the physical -> virtual handler cache.
165	*
166	* 4. \#PF(,write) on a page in the range. This will cause the handler to
167	* be invoked.
168	*
169	* 5. The guest invalidates the page and changes the physical backing or
170	* unmaps it. This should cause the invalidation callback to be invoked
171	* (it might not yet be 100% perfect). Exactly what happens next... is
172	* this where we mess up and end up out of sync for a while?
173	*
174	* 6. The handler is deregistered by the client via PGMHandlerVirtualDeregister.
175	* We will then set all PGMPAGEs in the physical -> virtual handler cache for
176	* this handler to NONE and trigger a full PGM resync (basically the same
177	* as int step 1). Which means 2 is executed again.
178	*
179	*
180	* @subsubsection sub_sec_pgm_handler_virt_todo TODOs
181	*
182	* There is a bunch of things that needs to be done to make the virtual handlers
183	* work 100% correctly and work more efficiently.
184	*
185	* The first bit hasn't been implemented yet because it's going to slow the
186	* whole mess down even more, and besides it seems to be working reliably for
187	* our current uses. OTOH, some of the optimizations might end up more or less
188	* implementing the missing bits, so we'll see.
189	*
190	* On the optimization side, the first thing to do is to try avoid unnecessary
191	* cache flushing. Then try team up with the shadowing code to track changes
192	* in mappings by means of access to them (shadow in), updates to shadows pages,
193	* invlpg, and shadow PT discarding (perhaps).
194	*
195	* Some idea that have popped up for optimization for current and new features:
196	* - bitmap indicating where there are virtual handlers installed.
197	* (4KB => 220 pages, page 212 => covers 32-bit address space 1:1!)
198	* - Further optimize this by min/max (needs min/max avl getters).
199	* - Shadow page table entry bit (if any left)?
200	*
201	*/
202
203
204	/** @page pg_pgm_phys PGM Physical Guest Memory Management
205	*
206	*
207	* Objectives:
208	* - Guest RAM over-commitment using memory ballooning,
209	* zero pages and general page sharing.
210	* - Moving or mirroring a VM onto a different physical machine.
211	*
212	*
213	* @subsection subsec_pgmPhys_Definitions Definitions
214	*
215	* Allocation chunk - A RTR0MemObjAllocPhysNC object and the tracking
216	* machinery assoicated with it.
217	*
218	*
219	*
220	*
221	* @subsection subsec_pgmPhys_AllocPage Allocating a page.
222	*
223	* Initially we map all guest memory to the (per VM) zero page, which
224	* means that none of the read functions will cause pages to be allocated.
225	*
226	* Exception, access bit in page tables that have been shared. This must
227	* be handled, but we must also make sure PGMGst*Modify doesn't make
228	* unnecessary modifications.
229	*
230	* Allocation points:
231	* - PGMPhysWriteGCPhys and PGMPhysWrite.
232	* - Replacing a zero page mapping at \#PF.
233	* - Replacing a shared page mapping at \#PF.
234	* - ROM registration (currently MMR3RomRegister).
235	* - VM restore (pgmR3Load).
236	*
237	* For the first three it would make sense to keep a few pages handy
238	* until we've reached the max memory commitment for the VM.
239	*
240	* For the ROM registration, we know exactly how many pages we need
241	* and will request these from ring-0. For restore, we will save
242	* the number of non-zero pages in the saved state and allocate
243	* them up front. This would allow the ring-0 component to refuse
244	* the request if the isn't sufficient memory available for VM use.
245	*
246	* Btw. for both ROM and restore allocations we won't be requiring
247	* zeroed pages as they are going to be filled instantly.
248	*
249	*
250	* @subsection subsec_pgmPhys_FreePage Freeing a page
251	*
252	* There are a few points where a page can be freed:
253	* - After being replaced by the zero page.
254	* - After being replaced by a shared page.
255	* - After being ballooned by the guest additions.
256	* - At reset.
257	* - At restore.
258	*
259	* When freeing one or more pages they will be returned to the ring-0
260	* component and replaced by the zero page.
261	*
262	* The reasoning for clearing out all the pages on reset is that it will
263	* return us to the exact same state as on power on, and may thereby help
264	* us reduce the memory load on the system. Further it might have a
265	* (temporary) positive influence on memory fragmentation (@see subsec_pgmPhys_Fragmentation).
266	*
267	* On restore, as mention under the allocation topic, pages should be
268	* freed / allocated depending on how many is actually required by the
269	* new VM state. The simplest approach is to do like on reset, and free
270	* all non-ROM pages and then allocate what we need.
271	*
272	* A measure to prevent some fragmentation, would be to let each allocation
273	* chunk have some affinity towards the VM having allocated the most pages
274	* from it. Also, try make sure to allocate from allocation chunks that
275	* are almost full. Admittedly, both these measures might work counter to
276	* our intentions and its probably not worth putting a lot of effort,
277	* cpu time or memory into this.
278	*
279	*
280	* @subsection subsec_pgmPhys_SharePage Sharing a page
281	*
282	* The basic idea is that there there will be a idle priority kernel
283	* thread walking the non-shared VM pages hashing them and looking for
284	* pages with the same checksum. If such pages are found, it will compare
285	* them byte-by-byte to see if they actually are identical. If found to be
286	* identical it will allocate a shared page, copy the content, check that
287	* the page didn't change while doing this, and finally request both the
288	* VMs to use the shared page instead. If the page is all zeros (special
289	* checksum and byte-by-byte check) it will request the VM that owns it
290	* to replace it with the zero page.
291	*
292	* To make this efficient, we will have to make sure not to try share a page
293	* that will change its contents soon. This part requires the most work.
294	* A simple idea would be to request the VM to write monitor the page for
295	* a while to make sure it isn't modified any time soon. Also, it may
296	* make sense to skip pages that are being write monitored since this
297	* information is readily available to the thread if it works on the
298	* per-VM guest memory structures (presently called PGMRAMRANGE).
299	*
300	*
301	* @subsection subsec_pgmPhys_Fragmentation Fragmentation Concerns and Counter Measures
302	*
303	* The pages are organized in allocation chunks in ring-0, this is a necessity
304	* if we wish to have an OS agnostic approach to this whole thing. (On Linux we
305	* could easily work on a page-by-page basis if we liked. Whether this is possible
306	* or efficient on NT I don't quite know.) Fragmentation within these chunks may
307	* become a problem as part of the idea here is that we wish to return memory to
308	* the host system.
309	*
310	* For instance, starting two VMs at the same time, they will both allocate the
311	* guest memory on-demand and if permitted their page allocations will be
312	* intermixed. Shut down one of the two VMs and it will be difficult to return
313	* any memory to the host system because the page allocation for the two VMs are
314	* mixed up in the same allocation chunks.
315	*
316	* To further complicate matters, when pages are freed because they have been
317	* ballooned or become shared/zero the whole idea is that the page is supposed
318	* to be reused by another VM or returned to the host system. This will cause
319	* allocation chunks to contain pages belonging to different VMs and prevent
320	* returning memory to the host when one of those VM shuts down.
321	*
322	* The only way to really deal with this problem is to move pages. This can
323	* either be done at VM shutdown and or by the idle priority worker thread
324	* that will be responsible for finding sharable/zero pages. The mechanisms
325	* involved for coercing a VM to move a page (or to do it for it) will be
326	* the same as when telling it to share/zero a page.
327	*
328	*
329	* @subsection subsec_pgmPhys_Tracking Tracking Structures And Their Cost
330	*
331	* There's a difficult balance between keeping the per-page tracking structures
332	* (global and guest page) easy to use and keeping them from eating too much
333	* memory. We have limited virtual memory resources available when operating in
334	* 32-bit kernel space (on 64-bit there'll it's quite a different story). The
335	* tracking structures will be attemted designed such that we can deal with up
336	* to 32GB of memory on a 32-bit system and essentially unlimited on 64-bit ones.
337	*
338	*
339	* @subsubsection subsubsec_pgmPhys_Tracking_Kernel Kernel Space
340	*
341	* @see pg_GMM
342	*
343	* @subsubsection subsubsec_pgmPhys_Tracking_PerVM Per-VM
344	*
345	* Fixed info is the physical address of the page (HCPhys) and the page id
346	* (described above). Theoretically we'll need 48(-12) bits for the HCPhys part.
347	* Today we've restricting ourselves to 40(-12) bits because this is the current
348	* restrictions of all AMD64 implementations (I think Barcelona will up this
349	* to 48(-12) bits, not that it really matters) and I needed the bits for
350	* tracking mappings of a page. 48-12 = 36. That leaves 28 bits, which means a
351	* decent range for the page id: 2^(28+12) = 1024TB.
352	*
353	* In additions to these, we'll have to keep maintaining the page flags as we
354	* currently do. Although it wouldn't harm to optimize these quite a bit, like
355	* for instance the ROM shouldn't depend on having a write handler installed
356	* in order for it to become read-only. A RO/RW bit should be considered so
357	* that the page syncing code doesn't have to mess about checking multiple
358	* flag combinations (ROM \|\| RW handler \|\| write monitored) in order to
359	* figure out how to setup a shadow PTE. But this of course, is second
360	* priority at present. Current this requires 12 bits, but could probably
361	* be optimized to ~8.
362	*
363	* Then there's the 24 bits used to track which shadow page tables are
364	* currently mapping a page for the purpose of speeding up physical
365	* access handlers, and thereby the page pool cache. More bit for this
366	* purpose wouldn't hurt IIRC.
367	*
368	* Then there is a new bit in which we need to record what kind of page
369	* this is, shared, zero, normal or write-monitored-normal. This'll
370	* require 2 bits. One bit might be needed for indicating whether a
371	* write monitored page has been written to. And yet another one or
372	* two for tracking migration status. 3-4 bits total then.
373	*
374	* Whatever is left will can be used to record the sharabilitiy of a
375	* page. The page checksum will not be stored in the per-VM table as
376	* the idle thread will not be permitted to do modifications to it.
377	* It will instead have to keep its own working set of potentially
378	* shareable pages and their check sums and stuff.
379	*
380	* For the present we'll keep the current packing of the
381	* PGMRAMRANGE::aHCPhys to keep the changes simple, only of course,
382	* we'll have to change it to a struct with a total of 128-bits at
383	* our disposal.
384	*
385	* The initial layout will be like this:
386	* @verbatim
387	RTHCPHYS HCPhys; The current stuff.
388	63:40 Current shadow PT tracking stuff.
389	39:12 The physical page frame number.
390	11:0 The current flags.
391	uint32_t u28PageId : 28; The page id.
392	uint32_t u2State : 2; The page state { zero, shared, normal, write monitored }.
393	uint32_t fWrittenTo : 1; Whether a write monitored page was written to.
394	uint32_t u1Reserved : 1; Reserved for later.
395	uint32_t u32Reserved; Reserved for later, mostly sharing stats.
396	@endverbatim
397	*
398	* The final layout will be something like this:
399	* @verbatim
400	RTHCPHYS HCPhys; The current stuff.
401	63:48 High page id (12+).
402	47:12 The physical page frame number.
403	11:0 Low page id.
404	uint32_t fReadOnly : 1; Whether it's readonly page (rom or monitored in some way).
405	uint32_t u3Type : 3; The page type {RESERVED, MMIO, MMIO2, ROM, shadowed ROM, RAM}.
406	uint32_t u2PhysMon : 2; Physical access handler type {none, read, write, all}.
407	uint32_t u2VirtMon : 2; Virtual access handler type {none, read, write, all}..
408	uint32_t u2State : 2; The page state { zero, shared, normal, write monitored }.
409	uint32_t fWrittenTo : 1; Whether a write monitored page was written to.
410	uint32_t u20Reserved : 20; Reserved for later, mostly sharing stats.
411	uint32_t u32Tracking; The shadow PT tracking stuff, roughly.
412	@endverbatim
413	*
414	* Cost wise, this means we'll double the cost for guest memory. There isn't anyway
415	* around that I'm afraid. It means that the cost of dealing out 32GB of memory
416	* to one or more VMs is: (32GB >> PAGE_SHIFT) * 16 bytes, or 128MBs. Or another
417	* example, the VM heap cost when assigning 1GB to a VM will be: 4MB.
418	*
419	* A couple of cost examples for the total cost per-VM + kernel.
420	* 32-bit Windows and 32-bit linux:
421	* 1GB guest ram, 256K pages: 4MB + 2MB(+) = 6MB
422	* 4GB guest ram, 1M pages: 16MB + 8MB(+) = 24MB
423	* 32GB guest ram, 8M pages: 128MB + 64MB(+) = 192MB
424	* 64-bit Windows and 64-bit linux:
425	* 1GB guest ram, 256K pages: 4MB + 3MB(+) = 7MB
426	* 4GB guest ram, 1M pages: 16MB + 12MB(+) = 28MB
427	* 32GB guest ram, 8M pages: 128MB + 96MB(+) = 224MB
428	*
429	* UPDATE - 2007-09-27:
430	* Will need a ballooned flag/state too because we cannot
431	* trust the guest 100% and reporting the same page as ballooned more
432	* than once will put the GMM off balance.
433	*
434	*
435	* @subsection subsec_pgmPhys_Serializing Serializing Access
436	*
437	* Initially, we'll try a simple scheme:
438	*
439	* - The per-VM RAM tracking structures (PGMRAMRANGE) is only modified
440	* by the EMT thread of that VM while in the pgm critsect.
441	* - Other threads in the VM process that needs to make reliable use of
442	* the per-VM RAM tracking structures will enter the critsect.
443	* - No process external thread or kernel thread will ever try enter
444	* the pgm critical section, as that just won't work.
445	* - The idle thread (and similar threads) doesn't not need 100% reliable
446	* data when performing it tasks as the EMT thread will be the one to
447	* do the actual changes later anyway. So, as long as it only accesses
448	* the main ram range, it can do so by somehow preventing the VM from
449	* being destroyed while it works on it...
450	*
451	* - The over-commitment management, including the allocating/freeing
452	* chunks, is serialized by a ring-0 mutex lock (a fast one since the
453	* more mundane mutex implementation is broken on Linux).
454	* - A separeate mutex is protecting the set of allocation chunks so
455	* that pages can be shared or/and freed up while some other VM is
456	* allocating more chunks. This mutex can be take from under the other
457	* one, but not the otherway around.
458	*
459	*
460	* @subsection subsec_pgmPhys_Request VM Request interface
461	*
462	* When in ring-0 it will become necessary to send requests to a VM so it can
463	* for instance move a page while defragmenting during VM destroy. The idle
464	* thread will make use of this interface to request VMs to setup shared
465	* pages and to perform write monitoring of pages.
466	*
467	* I would propose an interface similar to the current VMReq interface, similar
468	* in that it doesn't require locking and that the one sending the request may
469	* wait for completion if it wishes to. This shouldn't be very difficult to
470	* realize.
471	*
472	* The requests themselves are also pretty simple. They are basically:
473	* -# Check that some precondition is still true.
474	* -# Do the update.
475	* -# Update all shadow page tables involved with the page.
476	*
477	* The 3rd step is identical to what we're already doing when updating a
478	* physical handler, see pgmHandlerPhysicalSetRamFlagsAndFlushShadowPTs.
479	*
480	*
481	*
482	* @section sec_pgmPhys_MappingCaches Mapping Caches
483	*
484	* In order to be able to map in and out memory and to be able to support
485	* guest with more RAM than we've got virtual address space, we'll employing
486	* a mapping cache. There is already a tiny one for GC (see PGMGCDynMapGCPageEx)
487	* and we'll create a similar one for ring-0 unless we decide to setup a dedicate
488	* memory context for the HWACCM execution.
489	*
490	*
491	* @subsection subsec_pgmPhys_MappingCaches_R3 Ring-3
492	*
493	* We've considered implementing the ring-3 mapping cache page based but found
494	* that this was bother some when one had to take into account TLBs+SMP and
495	* portability (missing the necessary APIs on several platforms). There were
496	* also some performance concerns with this approach which hadn't quite been
497	* worked out.
498	*
499	* Instead, we'll be mapping allocation chunks into the VM process. This simplifies
500	* matters greatly quite a bit since we don't need to invent any new ring-0 stuff,
501	* only some minor RTR0MEMOBJ mapping stuff. The main concern here is that mapping
502	* compared to the previous idea is that mapping or unmapping a 1MB chunk is more
503	* costly than a single page, although how much more costly is uncertain. We'll
504	* try address this by using a very big cache, preferably bigger than the actual
505	* VM RAM size if possible. The current VM RAM sizes should give some idea for
506	* 32-bit boxes, while on 64-bit we can probably get away with employing an
507	* unlimited cache.
508	*
509	* The cache have to parts, as already indicated, the ring-3 side and the
510	* ring-0 side.
511	*
512	* The ring-0 will be tied to the page allocator since it will operate on the
513	* memory objects it contains. It will therefore require the first ring-0 mutex
514	* discussed in @ref subsec_pgmPhys_Serializing. We
515	* some double house keeping wrt to who has mapped what I think, since both
516	* VMMR0.r0 and RTR0MemObj will keep track of mapping relataions
517	*
518	* The ring-3 part will be protected by the pgm critsect. For simplicity, we'll
519	* require anyone that desires to do changes to the mapping cache to do that
520	* from within this critsect. Alternatively, we could employ a separate critsect
521	* for serializing changes to the mapping cache as this would reduce potential
522	* contention with other threads accessing mappings unrelated to the changes
523	* that are in process. We can see about this later, contention will show
524	* up in the statistics anyway, so it'll be simple to tell.
525	*
526	* The organization of the ring-3 part will be very much like how the allocation
527	* chunks are organized in ring-0, that is in an AVL tree by chunk id. To avoid
528	* having to walk the tree all the time, we'll have a couple of lookaside entries
529	* like in we do for I/O ports and MMIO in IOM.
530	*
531	* The simplified flow of a PGMPhysRead/Write function:
532	* -# Enter the PGM critsect.
533	* -# Lookup GCPhys in the ram ranges and get the Page ID.
534	* -# Calc the Allocation Chunk ID from the Page ID.
535	* -# Check the lookaside entries and then the AVL tree for the Chunk ID.
536	* If not found in cache:
537	* -# Call ring-0 and request it to be mapped and supply
538	* a chunk to be unmapped if the cache is maxed out already.
539	* -# Insert the new mapping into the AVL tree (id + R3 address).
540	* -# Update the relevant lookaside entry and return the mapping address.
541	* -# Do the read/write according to monitoring flags and everything.
542	* -# Leave the critsect.
543	*
544	*
545	* @section sec_pgmPhys_Fallback Fallback
546	*
547	* Current all the "second tier" hosts will not support the RTR0MemObjAllocPhysNC
548	* API and thus require a fallback.
549	*
550	* So, when RTR0MemObjAllocPhysNC returns VERR_NOT_SUPPORTED the page allocator
551	* will return to the ring-3 caller (and later ring-0) and asking it to seed
552	* the page allocator with some fresh pages (VERR_GMM_SEED_ME). Ring-3 will
553	* then perform an SUPPageAlloc(cbChunk >> PAGE_SHIFT) call and make a
554	* "SeededAllocPages" call to ring-0.
555	*
556	* The first time ring-0 sees the VERR_NOT_SUPPORTED failure it will disable
557	* all page sharing (zero page detection will continue). It will also force
558	* all allocations to come from the VM which seeded the page. Both these
559	* measures are taken to make sure that there will never be any need for
560	* mapping anything into ring-3 - everything will be mapped already.
561	*
562	* Whether we'll continue to use the current MM locked memory management
563	* for this I don't quite know (I'd prefer not to and just ditch that all
564	* togther), we'll see what's simplest to do.
565	*
566	*
567	*
568	* @section sec_pgmPhys_Changes Changes
569	*
570	* Breakdown of the changes involved?
571	*/
572
573
574	/** Saved state data unit version. */
575	#define PGM_SAVED_STATE_VERSION 6
576
577	/*******************************************************************************
578	* Header Files *
579	*******************************************************************************/
580	#define LOG_GROUP LOG_GROUP_PGM
581	#include <VBox/dbgf.h>
582	#include <VBox/pgm.h>
583	#include <VBox/cpum.h>
584	#include <VBox/iom.h>
585	#include <VBox/sup.h>
586	#include <VBox/mm.h>
587	#include <VBox/em.h>
588	#include <VBox/stam.h>
589	#include <VBox/rem.h>
590	#include <VBox/dbgf.h>
591	#include <VBox/rem.h>
592	#include <VBox/selm.h>
593	#include <VBox/ssm.h>
594	#include "PGMInternal.h"
595	#include <VBox/vm.h>
596	#include <VBox/dbg.h>
597	#include <VBox/hwaccm.h>
598
599	#include <iprt/assert.h>
600	#include <iprt/alloc.h>
601	#include <iprt/asm.h>
602	#include <iprt/thread.h>
603	#include <iprt/string.h>
604	#include <VBox/param.h>
605	#include <VBox/err.h>
606
607
608
609	/*******************************************************************************
610	* Internal Functions *
611	*******************************************************************************/
612	static int pgmR3InitPaging(PVM pVM);
613	static DECLCALLBACK(void) pgmR3PhysInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
614	static DECLCALLBACK(void) pgmR3InfoMode(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
615	static DECLCALLBACK(void) pgmR3InfoCr3(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
616	static DECLCALLBACK(int) pgmR3RelocatePhysHandler(PAVLROGCPHYSNODECORE pNode, void *pvUser);
617	static DECLCALLBACK(int) pgmR3RelocateVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser);
618	static DECLCALLBACK(int) pgmR3RelocateHyperVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser);
619	#ifdef VBOX_STRICT
620	static DECLCALLBACK(void) pgmR3ResetNoMorePhysWritesFlag(PVM pVM, VMSTATE enmState, VMSTATE enmOldState, void *pvUser);
621	#endif
622	static DECLCALLBACK(int) pgmR3Save(PVM pVM, PSSMHANDLE pSSM);
623	static DECLCALLBACK(int) pgmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version);
624	static int pgmR3ModeDataInit(PVM pVM, bool fResolveGCAndR0);
625	static void pgmR3ModeDataSwitch(PVM pVM, PGMMODE enmShw, PGMMODE enmGst);
626	static PGMMODE pgmR3CalcShadowMode(PVM pVM, PGMMODE enmGuestMode, SUPPAGINGMODE enmHostMode, PGMMODE enmShadowMode, VMMSWITCHER *penmSwitcher);
627
628	#ifdef VBOX_WITH_STATISTICS
629	static void pgmR3InitStats(PVM pVM);
630	#endif
631
632	#ifdef VBOX_WITH_DEBUGGER
633	/** @todo all but the two last commands must be converted to 'info'. */
634	static DECLCALLBACK(int) pgmR3CmdRam(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
635	static DECLCALLBACK(int) pgmR3CmdMap(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
636	static DECLCALLBACK(int) pgmR3CmdSync(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
637	static DECLCALLBACK(int) pgmR3CmdSyncAlways(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
638	# ifdef VBOX_STRICT
639	static DECLCALLBACK(int) pgmR3CmdAssertCR3(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
640	# endif
641	#endif
642
643
644	/*******************************************************************************
645	* Global Variables *
646	*******************************************************************************/
647	#ifdef VBOX_WITH_DEBUGGER
648	/** Command descriptors. */
649	static const DBGCCMD g_aCmds[] =
650	{
651	/* pszCmd, cArgsMin, cArgsMax, paArgDesc, cArgDescs, pResultDesc, fFlags, pfnHandler pszSyntax, ....pszDescription */
652	{ "pgmram", 0, 0, NULL, 0, NULL, 0, pgmR3CmdRam, "", "Display the ram ranges." },
653	{ "pgmmap", 0, 0, NULL, 0, NULL, 0, pgmR3CmdMap, "", "Display the mapping ranges." },
654	{ "pgmsync", 0, 0, NULL, 0, NULL, 0, pgmR3CmdSync, "", "Sync the CR3 page." },
655	#ifdef VBOX_STRICT
656	{ "pgmassertcr3", 0, 0, NULL, 0, NULL, 0, pgmR3CmdAssertCR3, "", "Check the shadow CR3 mapping." },
657	#endif
658	{ "pgmsyncalways", 0, 0, NULL, 0, NULL, 0, pgmR3CmdSyncAlways, "", "Toggle permanent CR3 syncing." },
659	};
660	#endif
661
662
663
664
665	/*
666	* Shadow - 32-bit mode
667	*/
668	#define PGM_SHW_TYPE PGM_TYPE_32BIT
669	#define PGM_SHW_NAME(name) PGM_SHW_NAME_32BIT(name)
670	#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_32BIT_STR(name)
671	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_32BIT_STR(name)
672	#include "PGMShw.h"
673
674	/* Guest - real mode */
675	#define PGM_GST_TYPE PGM_TYPE_REAL
676	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
677	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_REAL_STR(name)
678	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
679	#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_REAL(name)
680	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_32BIT_REAL_STR(name)
681	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_32BIT_REAL_STR(name)
682	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_PHYS
683	#include "PGMGst.h"
684	#include "PGMBth.h"
685	#undef BTH_PGMPOOLKIND_PT_FOR_PT
686	#undef PGM_BTH_NAME
687	#undef PGM_BTH_NAME_RC_STR
688	#undef PGM_BTH_NAME_R0_STR
689	#undef PGM_GST_TYPE
690	#undef PGM_GST_NAME
691	#undef PGM_GST_NAME_RC_STR
692	#undef PGM_GST_NAME_R0_STR
693
694	/* Guest - protected mode */
695	#define PGM_GST_TYPE PGM_TYPE_PROT
696	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
697	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PROT_STR(name)
698	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
699	#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_PROT(name)
700	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_32BIT_PROT_STR(name)
701	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_32BIT_PROT_STR(name)
702	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_PHYS
703	#include "PGMGst.h"
704	#include "PGMBth.h"
705	#undef BTH_PGMPOOLKIND_PT_FOR_PT
706	#undef PGM_BTH_NAME
707	#undef PGM_BTH_NAME_RC_STR
708	#undef PGM_BTH_NAME_R0_STR
709	#undef PGM_GST_TYPE
710	#undef PGM_GST_NAME
711	#undef PGM_GST_NAME_RC_STR
712	#undef PGM_GST_NAME_R0_STR
713
714	/* Guest - 32-bit mode */
715	#define PGM_GST_TYPE PGM_TYPE_32BIT
716	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
717	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_32BIT_STR(name)
718	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
719	#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_32BIT(name)
720	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_32BIT_32BIT_STR(name)
721	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_32BIT_32BIT_STR(name)
722	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT
723	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB
724	#include "PGMGst.h"
725	#include "PGMBth.h"
726	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
727	#undef BTH_PGMPOOLKIND_PT_FOR_PT
728	#undef PGM_BTH_NAME
729	#undef PGM_BTH_NAME_RC_STR
730	#undef PGM_BTH_NAME_R0_STR
731	#undef PGM_GST_TYPE
732	#undef PGM_GST_NAME
733	#undef PGM_GST_NAME_RC_STR
734	#undef PGM_GST_NAME_R0_STR
735
736	#undef PGM_SHW_TYPE
737	#undef PGM_SHW_NAME
738	#undef PGM_SHW_NAME_RC_STR
739	#undef PGM_SHW_NAME_R0_STR
740
741
742	/*
743	* Shadow - PAE mode
744	*/
745	#define PGM_SHW_TYPE PGM_TYPE_PAE
746	#define PGM_SHW_NAME(name) PGM_SHW_NAME_PAE(name)
747	#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_PAE_STR(name)
748	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_PAE_STR(name)
749	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_REAL(name)
750	#include "PGMShw.h"
751
752	/* Guest - real mode */
753	#define PGM_GST_TYPE PGM_TYPE_REAL
754	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
755	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_REAL_STR(name)
756	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
757	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_REAL(name)
758	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_PAE_REAL_STR(name)
759	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_REAL_STR(name)
760	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
761	#include "PGMBth.h"
762	#undef BTH_PGMPOOLKIND_PT_FOR_PT
763	#undef PGM_BTH_NAME
764	#undef PGM_BTH_NAME_RC_STR
765	#undef PGM_BTH_NAME_R0_STR
766	#undef PGM_GST_TYPE
767	#undef PGM_GST_NAME
768	#undef PGM_GST_NAME_RC_STR
769	#undef PGM_GST_NAME_R0_STR
770
771	/* Guest - protected mode */
772	#define PGM_GST_TYPE PGM_TYPE_PROT
773	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
774	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PROT_STR(name)
775	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
776	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_PROT(name)
777	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_PAE_PROT_STR(name)
778	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_PROT_STR(name)
779	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
780	#include "PGMBth.h"
781	#undef BTH_PGMPOOLKIND_PT_FOR_PT
782	#undef PGM_BTH_NAME
783	#undef PGM_BTH_NAME_RC_STR
784	#undef PGM_BTH_NAME_R0_STR
785	#undef PGM_GST_TYPE
786	#undef PGM_GST_NAME
787	#undef PGM_GST_NAME_RC_STR
788	#undef PGM_GST_NAME_R0_STR
789
790	/* Guest - 32-bit mode */
791	#define PGM_GST_TYPE PGM_TYPE_32BIT
792	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
793	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_32BIT_STR(name)
794	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
795	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_32BIT(name)
796	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_PAE_32BIT_STR(name)
797	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_32BIT_STR(name)
798	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_32BIT_PT
799	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB
800	#include "PGMBth.h"
801	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
802	#undef BTH_PGMPOOLKIND_PT_FOR_PT
803	#undef PGM_BTH_NAME
804	#undef PGM_BTH_NAME_RC_STR
805	#undef PGM_BTH_NAME_R0_STR
806	#undef PGM_GST_TYPE
807	#undef PGM_GST_NAME
808	#undef PGM_GST_NAME_RC_STR
809	#undef PGM_GST_NAME_R0_STR
810
811	/* Guest - PAE mode */
812	#define PGM_GST_TYPE PGM_TYPE_PAE
813	#define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
814	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PAE_STR(name)
815	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PAE_STR(name)
816	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_PAE(name)
817	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_PAE_PAE_STR(name)
818	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_PAE_STR(name)
819	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
820	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
821	#include "PGMGst.h"
822	#include "PGMBth.h"
823	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
824	#undef BTH_PGMPOOLKIND_PT_FOR_PT
825	#undef PGM_BTH_NAME
826	#undef PGM_BTH_NAME_RC_STR
827	#undef PGM_BTH_NAME_R0_STR
828	#undef PGM_GST_TYPE
829	#undef PGM_GST_NAME
830	#undef PGM_GST_NAME_RC_STR
831	#undef PGM_GST_NAME_R0_STR
832
833	#undef PGM_SHW_TYPE
834	#undef PGM_SHW_NAME
835	#undef PGM_SHW_NAME_RC_STR
836	#undef PGM_SHW_NAME_R0_STR
837
838
839	/*
840	* Shadow - AMD64 mode
841	*/
842	#define PGM_SHW_TYPE PGM_TYPE_AMD64
843	#define PGM_SHW_NAME(name) PGM_SHW_NAME_AMD64(name)
844	#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_AMD64_STR(name)
845	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_AMD64_STR(name)
846	#include "PGMShw.h"
847
848	/* Guest - AMD64 mode */
849	#define PGM_GST_TYPE PGM_TYPE_AMD64
850	#define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
851	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_AMD64_STR(name)
852	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_AMD64_STR(name)
853	#define PGM_BTH_NAME(name) PGM_BTH_NAME_AMD64_AMD64(name)
854	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_AMD64_AMD64_STR(name)
855	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_AMD64_AMD64_STR(name)
856	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
857	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
858	#include "PGMGst.h"
859	#include "PGMBth.h"
860	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
861	#undef BTH_PGMPOOLKIND_PT_FOR_PT
862	#undef PGM_BTH_NAME
863	#undef PGM_BTH_NAME_RC_STR
864	#undef PGM_BTH_NAME_R0_STR
865	#undef PGM_GST_TYPE
866	#undef PGM_GST_NAME
867	#undef PGM_GST_NAME_RC_STR
868	#undef PGM_GST_NAME_R0_STR
869
870	#undef PGM_SHW_TYPE
871	#undef PGM_SHW_NAME
872	#undef PGM_SHW_NAME_RC_STR
873	#undef PGM_SHW_NAME_R0_STR
874
875	/*
876	* Shadow - Nested paging mode
877	*/
878	#define PGM_SHW_TYPE PGM_TYPE_NESTED
879	#define PGM_SHW_NAME(name) PGM_SHW_NAME_NESTED(name)
880	#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_NESTED_STR(name)
881	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_NESTED_STR(name)
882	#include "PGMShw.h"
883
884	/* Guest - real mode */
885	#define PGM_GST_TYPE PGM_TYPE_REAL
886	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
887	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_REAL_STR(name)
888	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
889	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_REAL(name)
890	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_REAL_STR(name)
891	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_REAL_STR(name)
892	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
893	#include "PGMBth.h"
894	#undef BTH_PGMPOOLKIND_PT_FOR_PT
895	#undef PGM_BTH_NAME
896	#undef PGM_BTH_NAME_RC_STR
897	#undef PGM_BTH_NAME_R0_STR
898	#undef PGM_GST_TYPE
899	#undef PGM_GST_NAME
900	#undef PGM_GST_NAME_RC_STR
901	#undef PGM_GST_NAME_R0_STR
902
903	/* Guest - protected mode */
904	#define PGM_GST_TYPE PGM_TYPE_PROT
905	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
906	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PROT_STR(name)
907	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
908	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_PROT(name)
909	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_PROT_STR(name)
910	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_PROT_STR(name)
911	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
912	#include "PGMBth.h"
913	#undef BTH_PGMPOOLKIND_PT_FOR_PT
914	#undef PGM_BTH_NAME
915	#undef PGM_BTH_NAME_RC_STR
916	#undef PGM_BTH_NAME_R0_STR
917	#undef PGM_GST_TYPE
918	#undef PGM_GST_NAME
919	#undef PGM_GST_NAME_RC_STR
920	#undef PGM_GST_NAME_R0_STR
921
922	/* Guest - 32-bit mode */
923	#define PGM_GST_TYPE PGM_TYPE_32BIT
924	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
925	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_32BIT_STR(name)
926	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
927	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_32BIT(name)
928	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_32BIT_STR(name)
929	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_32BIT_STR(name)
930	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_32BIT_PT
931	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB
932	#include "PGMBth.h"
933	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
934	#undef BTH_PGMPOOLKIND_PT_FOR_PT
935	#undef PGM_BTH_NAME
936	#undef PGM_BTH_NAME_RC_STR
937	#undef PGM_BTH_NAME_R0_STR
938	#undef PGM_GST_TYPE
939	#undef PGM_GST_NAME
940	#undef PGM_GST_NAME_RC_STR
941	#undef PGM_GST_NAME_R0_STR
942
943	/* Guest - PAE mode */
944	#define PGM_GST_TYPE PGM_TYPE_PAE
945	#define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
946	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PAE_STR(name)
947	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PAE_STR(name)
948	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_PAE(name)
949	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_PAE_STR(name)
950	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_PAE_STR(name)
951	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
952	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
953	#include "PGMBth.h"
954	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
955	#undef BTH_PGMPOOLKIND_PT_FOR_PT
956	#undef PGM_BTH_NAME
957	#undef PGM_BTH_NAME_RC_STR
958	#undef PGM_BTH_NAME_R0_STR
959	#undef PGM_GST_TYPE
960	#undef PGM_GST_NAME
961	#undef PGM_GST_NAME_RC_STR
962	#undef PGM_GST_NAME_R0_STR
963
964	/* Guest - AMD64 mode */
965	#define PGM_GST_TYPE PGM_TYPE_AMD64
966	#define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
967	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_AMD64_STR(name)
968	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_AMD64_STR(name)
969	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_AMD64(name)
970	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_AMD64_STR(name)
971	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_AMD64_STR(name)
972	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
973	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
974	#include "PGMBth.h"
975	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
976	#undef BTH_PGMPOOLKIND_PT_FOR_PT
977	#undef PGM_BTH_NAME
978	#undef PGM_BTH_NAME_RC_STR
979	#undef PGM_BTH_NAME_R0_STR
980	#undef PGM_GST_TYPE
981	#undef PGM_GST_NAME
982	#undef PGM_GST_NAME_RC_STR
983	#undef PGM_GST_NAME_R0_STR
984
985	#undef PGM_SHW_TYPE
986	#undef PGM_SHW_NAME
987	#undef PGM_SHW_NAME_RC_STR
988	#undef PGM_SHW_NAME_R0_STR
989
990	/*
991	* Shadow - EPT
992	*/
993	#define PGM_SHW_TYPE PGM_TYPE_EPT
994	#define PGM_SHW_NAME(name) PGM_SHW_NAME_EPT(name)
995	#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_EPT_STR(name)
996	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_EPT_STR(name)
997	#include "PGMShw.h"
998
999	/* Guest - real mode */
1000	#define PGM_GST_TYPE PGM_TYPE_REAL
1001	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
1002	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_REAL_STR(name)
1003	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
1004	#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_REAL(name)
1005	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_REAL_STR(name)
1006	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_REAL_STR(name)
1007	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
1008	#include "PGMBth.h"
1009	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1010	#undef PGM_BTH_NAME
1011	#undef PGM_BTH_NAME_RC_STR
1012	#undef PGM_BTH_NAME_R0_STR
1013	#undef PGM_GST_TYPE
1014	#undef PGM_GST_NAME
1015	#undef PGM_GST_NAME_RC_STR
1016	#undef PGM_GST_NAME_R0_STR
1017
1018	/* Guest - protected mode */
1019	#define PGM_GST_TYPE PGM_TYPE_PROT
1020	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
1021	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PROT_STR(name)
1022	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
1023	#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_PROT(name)
1024	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_PROT_STR(name)
1025	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_PROT_STR(name)
1026	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
1027	#include "PGMBth.h"
1028	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1029	#undef PGM_BTH_NAME
1030	#undef PGM_BTH_NAME_RC_STR
1031	#undef PGM_BTH_NAME_R0_STR
1032	#undef PGM_GST_TYPE
1033	#undef PGM_GST_NAME
1034	#undef PGM_GST_NAME_RC_STR
1035	#undef PGM_GST_NAME_R0_STR
1036
1037	/* Guest - 32-bit mode */
1038	#define PGM_GST_TYPE PGM_TYPE_32BIT
1039	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
1040	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_32BIT_STR(name)
1041	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
1042	#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_32BIT(name)
1043	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_32BIT_STR(name)
1044	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_32BIT_STR(name)
1045	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_32BIT_PT
1046	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB
1047	#include "PGMBth.h"
1048	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
1049	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1050	#undef PGM_BTH_NAME
1051	#undef PGM_BTH_NAME_RC_STR
1052	#undef PGM_BTH_NAME_R0_STR
1053	#undef PGM_GST_TYPE
1054	#undef PGM_GST_NAME
1055	#undef PGM_GST_NAME_RC_STR
1056	#undef PGM_GST_NAME_R0_STR
1057
1058	/* Guest - PAE mode */
1059	#define PGM_GST_TYPE PGM_TYPE_PAE
1060	#define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
1061	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PAE_STR(name)
1062	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PAE_STR(name)
1063	#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_PAE(name)
1064	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_PAE_STR(name)
1065	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_PAE_STR(name)
1066	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
1067	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
1068	#include "PGMBth.h"
1069	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
1070	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1071	#undef PGM_BTH_NAME
1072	#undef PGM_BTH_NAME_RC_STR
1073	#undef PGM_BTH_NAME_R0_STR
1074	#undef PGM_GST_TYPE
1075	#undef PGM_GST_NAME
1076	#undef PGM_GST_NAME_RC_STR
1077	#undef PGM_GST_NAME_R0_STR
1078
1079	/* Guest - AMD64 mode */
1080	#define PGM_GST_TYPE PGM_TYPE_AMD64
1081	#define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
1082	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_AMD64_STR(name)
1083	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_AMD64_STR(name)
1084	#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_AMD64(name)
1085	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_AMD64_STR(name)
1086	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_AMD64_STR(name)
1087	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
1088	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
1089	#include "PGMBth.h"
1090	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
1091	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1092	#undef PGM_BTH_NAME
1093	#undef PGM_BTH_NAME_RC_STR
1094	#undef PGM_BTH_NAME_R0_STR
1095	#undef PGM_GST_TYPE
1096	#undef PGM_GST_NAME
1097	#undef PGM_GST_NAME_RC_STR
1098	#undef PGM_GST_NAME_R0_STR
1099
1100	#undef PGM_SHW_TYPE
1101	#undef PGM_SHW_NAME
1102	#undef PGM_SHW_NAME_RC_STR
1103	#undef PGM_SHW_NAME_R0_STR
1104
1105	/**
1106	* Initiates the paging of VM.
1107	*
1108	* @returns VBox status code.
1109	* @param pVM Pointer to VM structure.
1110	*/
1111	VMMR3DECL(int) PGMR3Init(PVM pVM)
1112	{
1113	LogFlow(("PGMR3Init:\n"));
1114
1115	/*
1116	* Assert alignment and sizes.
1117	*/
1118	AssertRelease(sizeof(pVM->pgm.s) <= sizeof(pVM->pgm.padding));
1119
1120	/*
1121	* Init the structure.
1122	*/
1123	pVM->pgm.s.offVM = RT_OFFSETOF(VM, pgm.s);
1124	pVM->pgm.s.enmShadowMode = PGMMODE_INVALID;
1125	pVM->pgm.s.enmGuestMode = PGMMODE_INVALID;
1126	pVM->pgm.s.enmHostMode = SUPPAGINGMODE_INVALID;
1127	pVM->pgm.s.GCPhysCR3 = NIL_RTGCPHYS;
1128	pVM->pgm.s.GCPhysGstCR3Monitored = NIL_RTGCPHYS;
1129	pVM->pgm.s.fA20Enabled = true;
1130	pVM->pgm.s.GCPhys4MBPSEMask = RT_BIT_64(32) - 1; /* default; checked later */
1131	pVM->pgm.s.pGstPaePDPTHC = NULL;
1132	pVM->pgm.s.pGstPaePDPTGC = 0;
1133	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.apGstPaePDsHC); i++)
1134	{
1135	pVM->pgm.s.apGstPaePDsHC[i] = NULL;
1136	pVM->pgm.s.apGstPaePDsGC[i] = 0;
1137	pVM->pgm.s.aGCPhysGstPaePDs[i] = NIL_RTGCPHYS;
1138	pVM->pgm.s.aGCPhysGstPaePDsMonitored[i] = NIL_RTGCPHYS;
1139	}
1140
1141	#ifdef VBOX_STRICT
1142	VMR3AtStateRegister(pVM, pgmR3ResetNoMorePhysWritesFlag, NULL);
1143	#endif
1144
1145	/*
1146	* Get the configured RAM size - to estimate saved state size.
1147	*/
1148	uint64_t cbRam;
1149	int rc = CFGMR3QueryU64(CFGMR3GetRoot(pVM), "RamSize", &cbRam);
1150	if (rc == VERR_CFGM_VALUE_NOT_FOUND)
1151	cbRam = pVM->pgm.s.cbRamSize = 0;
1152	else if (VBOX_SUCCESS(rc))
1153	{
1154	if (cbRam < PAGE_SIZE)
1155	cbRam = 0;
1156	cbRam = RT_ALIGN_64(cbRam, PAGE_SIZE);
1157	pVM->pgm.s.cbRamSize = (RTUINT)cbRam;
1158	}
1159	else
1160	{
1161	AssertMsgFailed(("Configuration error: Failed to query integer \"RamSize\", rc=%Vrc.\n", rc));
1162	return rc;
1163	}
1164
1165	/*
1166	* Register saved state data unit.
1167	*/
1168	rc = SSMR3RegisterInternal(pVM, "pgm", 1, PGM_SAVED_STATE_VERSION, (size_t)cbRam + sizeof(PGM),
1169	NULL, pgmR3Save, NULL,
1170	NULL, pgmR3Load, NULL);
1171	if (VBOX_FAILURE(rc))
1172	return rc;
1173
1174	/*
1175	* Initialize the PGM critical section and flush the phys TLBs
1176	*/
1177	rc = PDMR3CritSectInit(pVM, &pVM->pgm.s.CritSect, "PGM");
1178	AssertRCReturn(rc, rc);
1179
1180	PGMR3PhysChunkInvalidateTLB(pVM);
1181	PGMPhysInvalidatePageR3MapTLB(pVM);
1182	PGMPhysInvalidatePageR0MapTLB(pVM);
1183	PGMPhysInvalidatePageGCMapTLB(pVM);
1184
1185	/*
1186	* Trees
1187	*/
1188	rc = MMHyperAlloc(pVM, sizeof(PGMTREES), 0, MM_TAG_PGM, (void **)&pVM->pgm.s.pTreesR3);
1189	if (VBOX_SUCCESS(rc))
1190	{
1191	pVM->pgm.s.pTreesR0 = MMHyperR3ToR0(pVM, pVM->pgm.s.pTreesR3);
1192	pVM->pgm.s.pTreesRC = MMHyperR3ToRC(pVM, pVM->pgm.s.pTreesR3);
1193
1194	/*
1195	* Alocate the zero page.
1196	*/
1197	rc = MMHyperAlloc(pVM, PAGE_SIZE, PAGE_SIZE, MM_TAG_PGM, &pVM->pgm.s.pvZeroPgR3);
1198	}
1199	if (VBOX_SUCCESS(rc))
1200	{
1201	pVM->pgm.s.pvZeroPgGC = MMHyperR3ToRC(pVM, pVM->pgm.s.pvZeroPgR3);
1202	pVM->pgm.s.pvZeroPgR0 = MMHyperR3ToR0(pVM, pVM->pgm.s.pvZeroPgR3);
1203	AssertRelease(pVM->pgm.s.pvZeroPgR0 != NIL_RTHCPHYS);
1204	pVM->pgm.s.HCPhysZeroPg = MMR3HyperHCVirt2HCPhys(pVM, pVM->pgm.s.pvZeroPgR3);
1205	AssertRelease(pVM->pgm.s.HCPhysZeroPg != NIL_RTHCPHYS);
1206
1207	/*
1208	* Init the paging.
1209	*/
1210	rc = pgmR3InitPaging(pVM);
1211	}
1212	if (VBOX_SUCCESS(rc))
1213	{
1214	/*
1215	* Init the page pool.
1216	*/
1217	rc = pgmR3PoolInit(pVM);
1218	}
1219	if (VBOX_SUCCESS(rc))
1220	{
1221	/*
1222	* Info & statistics
1223	*/
1224	DBGFR3InfoRegisterInternal(pVM, "mode",
1225	"Shows the current paging mode. "
1226	"Recognizes 'all', 'guest', 'shadow' and 'host' as arguments, defaulting to 'all' if nothing's given.",
1227	pgmR3InfoMode);
1228	DBGFR3InfoRegisterInternal(pVM, "pgmcr3",
1229	"Dumps all the entries in the top level paging table. No arguments.",
1230	pgmR3InfoCr3);
1231	DBGFR3InfoRegisterInternal(pVM, "phys",
1232	"Dumps all the physical address ranges. No arguments.",
1233	pgmR3PhysInfo);
1234	DBGFR3InfoRegisterInternal(pVM, "handlers",
1235	"Dumps physical, virtual and hyper virtual handlers. "
1236	"Pass 'phys', 'virt', 'hyper' as argument if only one kind is wanted."
1237	"Add 'nost' if the statistics are unwanted, use together with 'all' or explicit selection.",
1238	pgmR3InfoHandlers);
1239	DBGFR3InfoRegisterInternal(pVM, "mappings",
1240	"Dumps guest mappings.",
1241	pgmR3MapInfo);
1242
1243	STAM_REL_REG(pVM, &pVM->pgm.s.cGuestModeChanges, STAMTYPE_COUNTER, "/PGM/cGuestModeChanges", STAMUNIT_OCCURENCES, "Number of guest mode changes.");
1244	#ifdef VBOX_WITH_STATISTICS
1245	pgmR3InitStats(pVM);
1246	#endif
1247	#ifdef VBOX_WITH_DEBUGGER
1248	/*
1249	* Debugger commands.
1250	*/
1251	static bool fRegisteredCmds = false;
1252	if (!fRegisteredCmds)
1253	{
1254	int rc = DBGCRegisterCommands(&g_aCmds[0], RT_ELEMENTS(g_aCmds));
1255	if (VBOX_SUCCESS(rc))
1256	fRegisteredCmds = true;
1257	}
1258	#endif
1259	return VINF_SUCCESS;
1260	}
1261
1262	/* Almost no cleanup necessary, MM frees all memory. */
1263	PDMR3CritSectDelete(&pVM->pgm.s.CritSect);
1264
1265	return rc;
1266	}
1267
1268
1269	/**
1270	* Init paging.
1271	*
1272	* Since we need to check what mode the host is operating in before we can choose
1273	* the right paging functions for the host we have to delay this until R0 has
1274	* been initialized.
1275	*
1276	* @returns VBox status code.
1277	* @param pVM VM handle.
1278	*/
1279	static int pgmR3InitPaging(PVM pVM)
1280	{
1281	/*
1282	* Force a recalculation of modes and switcher so everyone gets notified.
1283	*/
1284	pVM->pgm.s.enmShadowMode = PGMMODE_INVALID;
1285	pVM->pgm.s.enmGuestMode = PGMMODE_INVALID;
1286	pVM->pgm.s.enmHostMode = SUPPAGINGMODE_INVALID;
1287
1288	/*
1289	* Allocate static mapping space for whatever the cr3 register
1290	* points to and in the case of PAE mode to the 4 PDs.
1291	*/
1292	int rc = MMR3HyperReserve(pVM, PAGE_SIZE * 5, "CR3 mapping", &pVM->pgm.s.GCPtrCR3Mapping);
1293	if (VBOX_FAILURE(rc))
1294	{
1295	AssertMsgFailed(("Failed to reserve two pages for cr mapping in HMA, rc=%Vrc\n", rc));
1296	return rc;
1297	}
1298	MMR3HyperReserve(pVM, PAGE_SIZE, "fence", NULL);
1299
1300	/*
1301	* Allocate pages for the three possible intermediate contexts
1302	* (AMD64, PAE and plain 32-Bit). We maintain all three contexts
1303	* for the sake of simplicity. The AMD64 uses the PAE for the
1304	* lower levels, making the total number of pages 11 (3 + 7 + 1).
1305	*
1306	* We assume that two page tables will be enought for the core code
1307	* mappings (HC virtual and identity).
1308	*/
1309	pVM->pgm.s.pInterPD = (PX86PD)MMR3PageAllocLow(pVM);
1310	pVM->pgm.s.apInterPTs[0] = (PX86PT)MMR3PageAllocLow(pVM);
1311	pVM->pgm.s.apInterPTs[1] = (PX86PT)MMR3PageAllocLow(pVM);
1312	pVM->pgm.s.apInterPaePTs[0] = (PX86PTPAE)MMR3PageAlloc(pVM);
1313	pVM->pgm.s.apInterPaePTs[1] = (PX86PTPAE)MMR3PageAlloc(pVM);
1314	pVM->pgm.s.apInterPaePDs[0] = (PX86PDPAE)MMR3PageAlloc(pVM);
1315	pVM->pgm.s.apInterPaePDs[1] = (PX86PDPAE)MMR3PageAlloc(pVM);
1316	pVM->pgm.s.apInterPaePDs[2] = (PX86PDPAE)MMR3PageAlloc(pVM);
1317	pVM->pgm.s.apInterPaePDs[3] = (PX86PDPAE)MMR3PageAlloc(pVM);
1318	pVM->pgm.s.pInterPaePDPT = (PX86PDPT)MMR3PageAllocLow(pVM);
1319	pVM->pgm.s.pInterPaePDPT64 = (PX86PDPT)MMR3PageAllocLow(pVM);
1320	pVM->pgm.s.pInterPaePML4 = (PX86PML4)MMR3PageAllocLow(pVM);
1321	if ( !pVM->pgm.s.pInterPD
1322	\|\| !pVM->pgm.s.apInterPTs[0]
1323	\|\| !pVM->pgm.s.apInterPTs[1]
1324	\|\| !pVM->pgm.s.apInterPaePTs[0]
1325	\|\| !pVM->pgm.s.apInterPaePTs[1]
1326	\|\| !pVM->pgm.s.apInterPaePDs[0]
1327	\|\| !pVM->pgm.s.apInterPaePDs[1]
1328	\|\| !pVM->pgm.s.apInterPaePDs[2]
1329	\|\| !pVM->pgm.s.apInterPaePDs[3]
1330	\|\| !pVM->pgm.s.pInterPaePDPT
1331	\|\| !pVM->pgm.s.pInterPaePDPT64
1332	\|\| !pVM->pgm.s.pInterPaePML4)
1333	{
1334	AssertMsgFailed(("Failed to allocate pages for the intermediate context!\n"));
1335	return VERR_NO_PAGE_MEMORY;
1336	}
1337
1338	pVM->pgm.s.HCPhysInterPD = MMPage2Phys(pVM, pVM->pgm.s.pInterPD);
1339	AssertRelease(pVM->pgm.s.HCPhysInterPD != NIL_RTHCPHYS && !(pVM->pgm.s.HCPhysInterPD & PAGE_OFFSET_MASK));
1340	pVM->pgm.s.HCPhysInterPaePDPT = MMPage2Phys(pVM, pVM->pgm.s.pInterPaePDPT);
1341	AssertRelease(pVM->pgm.s.HCPhysInterPaePDPT != NIL_RTHCPHYS && !(pVM->pgm.s.HCPhysInterPaePDPT & PAGE_OFFSET_MASK));
1342	pVM->pgm.s.HCPhysInterPaePML4 = MMPage2Phys(pVM, pVM->pgm.s.pInterPaePML4);
1343	AssertRelease(pVM->pgm.s.HCPhysInterPaePML4 != NIL_RTHCPHYS && !(pVM->pgm.s.HCPhysInterPaePML4 & PAGE_OFFSET_MASK));
1344
1345	/*
1346	* Initialize the pages, setting up the PML4 and PDPT for repetitive 4GB action.
1347	*/
1348	ASMMemZeroPage(pVM->pgm.s.pInterPD);
1349	ASMMemZeroPage(pVM->pgm.s.apInterPTs[0]);
1350	ASMMemZeroPage(pVM->pgm.s.apInterPTs[1]);
1351
1352	ASMMemZeroPage(pVM->pgm.s.apInterPaePTs[0]);
1353	ASMMemZeroPage(pVM->pgm.s.apInterPaePTs[1]);
1354
1355	ASMMemZeroPage(pVM->pgm.s.pInterPaePDPT);
1356	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.apInterPaePDs); i++)
1357	{
1358	ASMMemZeroPage(pVM->pgm.s.apInterPaePDs[i]);
1359	pVM->pgm.s.pInterPaePDPT->a[i].u = X86_PDPE_P \| PGM_PLXFLAGS_PERMANENT
1360	\| MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[i]);
1361	}
1362
1363	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.pInterPaePDPT64->a); i++)
1364	{
1365	const unsigned iPD = i % RT_ELEMENTS(pVM->pgm.s.apInterPaePDs);
1366	pVM->pgm.s.pInterPaePDPT64->a[i].u = X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_A \| PGM_PLXFLAGS_PERMANENT
1367	\| MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[iPD]);
1368	}
1369
1370	RTHCPHYS HCPhysInterPaePDPT64 = MMPage2Phys(pVM, pVM->pgm.s.pInterPaePDPT64);
1371	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.pInterPaePML4->a); i++)
1372	pVM->pgm.s.pInterPaePML4->a[i].u = X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_A \| PGM_PLXFLAGS_PERMANENT
1373	\| HCPhysInterPaePDPT64;
1374
1375	/*
1376	* Allocate pages for the three possible guest contexts (AMD64, PAE and plain 32-Bit).
1377	* We allocate pages for all three posibilities to in order to simplify mappings and
1378	* avoid resource failure during mode switches. So, we need to cover all levels of the
1379	* of the first 4GB down to PD level.
1380	* As with the intermediate context, AMD64 uses the PAE PDPT and PDs.
1381	*/
1382	pVM->pgm.s.pHC32BitPD = (PX86PD)MMR3PageAllocLow(pVM);
1383	pVM->pgm.s.apHCPaePDs[0] = (PX86PDPAE)MMR3PageAlloc(pVM);
1384	pVM->pgm.s.apHCPaePDs[1] = (PX86PDPAE)MMR3PageAlloc(pVM);
1385	AssertRelease((uintptr_t)pVM->pgm.s.apHCPaePDs[0] + PAGE_SIZE == (uintptr_t)pVM->pgm.s.apHCPaePDs[1]);
1386	pVM->pgm.s.apHCPaePDs[2] = (PX86PDPAE)MMR3PageAlloc(pVM);
1387	AssertRelease((uintptr_t)pVM->pgm.s.apHCPaePDs[1] + PAGE_SIZE == (uintptr_t)pVM->pgm.s.apHCPaePDs[2]);
1388	pVM->pgm.s.apHCPaePDs[3] = (PX86PDPAE)MMR3PageAlloc(pVM);
1389	AssertRelease((uintptr_t)pVM->pgm.s.apHCPaePDs[2] + PAGE_SIZE == (uintptr_t)pVM->pgm.s.apHCPaePDs[3]);
1390	pVM->pgm.s.pHCPaePDPT = (PX86PDPT)MMR3PageAllocLow(pVM);
1391	pVM->pgm.s.pHCNestedRoot = MMR3PageAllocLow(pVM);
1392
1393	if ( !pVM->pgm.s.pHC32BitPD
1394	\|\| !pVM->pgm.s.apHCPaePDs[0]
1395	\|\| !pVM->pgm.s.apHCPaePDs[1]
1396	\|\| !pVM->pgm.s.apHCPaePDs[2]
1397	\|\| !pVM->pgm.s.apHCPaePDs[3]
1398	\|\| !pVM->pgm.s.pHCPaePDPT
1399	\|\| !pVM->pgm.s.pHCNestedRoot)
1400	{
1401	AssertMsgFailed(("Failed to allocate pages for the intermediate context!\n"));
1402	return VERR_NO_PAGE_MEMORY;
1403	}
1404
1405	/* get physical addresses. */
1406	pVM->pgm.s.HCPhys32BitPD = MMPage2Phys(pVM, pVM->pgm.s.pHC32BitPD);
1407	Assert(MMPagePhys2Page(pVM, pVM->pgm.s.HCPhys32BitPD) == pVM->pgm.s.pHC32BitPD);
1408	pVM->pgm.s.aHCPhysPaePDs[0] = MMPage2Phys(pVM, pVM->pgm.s.apHCPaePDs[0]);
1409	pVM->pgm.s.aHCPhysPaePDs[1] = MMPage2Phys(pVM, pVM->pgm.s.apHCPaePDs[1]);
1410	pVM->pgm.s.aHCPhysPaePDs[2] = MMPage2Phys(pVM, pVM->pgm.s.apHCPaePDs[2]);
1411	pVM->pgm.s.aHCPhysPaePDs[3] = MMPage2Phys(pVM, pVM->pgm.s.apHCPaePDs[3]);
1412	pVM->pgm.s.HCPhysPaePDPT = MMPage2Phys(pVM, pVM->pgm.s.pHCPaePDPT);
1413	pVM->pgm.s.HCPhysNestedRoot = MMPage2Phys(pVM, pVM->pgm.s.pHCNestedRoot);
1414
1415	/*
1416	* Initialize the pages, setting up the PML4 and PDPT for action below 4GB.
1417	*/
1418	ASMMemZero32(pVM->pgm.s.pHC32BitPD, PAGE_SIZE);
1419	ASMMemZero32(pVM->pgm.s.pHCPaePDPT, PAGE_SIZE);
1420	ASMMemZero32(pVM->pgm.s.pHCNestedRoot, PAGE_SIZE);
1421	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.apHCPaePDs); i++)
1422	{
1423	ASMMemZero32(pVM->pgm.s.apHCPaePDs[i], PAGE_SIZE);
1424	pVM->pgm.s.pHCPaePDPT->a[i].u = X86_PDPE_P \| PGM_PLXFLAGS_PERMANENT \| pVM->pgm.s.aHCPhysPaePDs[i];
1425	/* The flags will be corrected when entering and leaving long mode. */
1426	}
1427
1428	CPUMSetHyperCR3(pVM, (uint32_t)pVM->pgm.s.HCPhys32BitPD);
1429
1430	/*
1431	* Initialize paging workers and mode from current host mode
1432	* and the guest running in real mode.
1433	*/
1434	pVM->pgm.s.enmHostMode = SUPGetPagingMode();
1435	switch (pVM->pgm.s.enmHostMode)
1436	{
1437	case SUPPAGINGMODE_32_BIT:
1438	case SUPPAGINGMODE_32_BIT_GLOBAL:
1439	case SUPPAGINGMODE_PAE:
1440	case SUPPAGINGMODE_PAE_GLOBAL:
1441	case SUPPAGINGMODE_PAE_NX:
1442	case SUPPAGINGMODE_PAE_GLOBAL_NX:
1443	break;
1444
1445	case SUPPAGINGMODE_AMD64:
1446	case SUPPAGINGMODE_AMD64_GLOBAL:
1447	case SUPPAGINGMODE_AMD64_NX:
1448	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
1449	#ifndef VBOX_WITH_HYBIRD_32BIT_KERNEL
1450	if (ARCH_BITS != 64)
1451	{
1452	AssertMsgFailed(("Host mode %d (64-bit) is not supported by non-64bit builds\n", pVM->pgm.s.enmHostMode));
1453	LogRel(("Host mode %d (64-bit) is not supported by non-64bit builds\n", pVM->pgm.s.enmHostMode));
1454	return VERR_PGM_UNSUPPORTED_HOST_PAGING_MODE;
1455	}
1456	#endif
1457	break;
1458	default:
1459	AssertMsgFailed(("Host mode %d is not supported\n", pVM->pgm.s.enmHostMode));
1460	return VERR_PGM_UNSUPPORTED_HOST_PAGING_MODE;
1461	}
1462	rc = pgmR3ModeDataInit(pVM, false /* don't resolve GC and R0 syms yet */);
1463	if (VBOX_SUCCESS(rc))
1464	rc = PGMR3ChangeMode(pVM, PGMMODE_REAL);
1465	if (VBOX_SUCCESS(rc))
1466	{
1467	LogFlow(("pgmR3InitPaging: returns successfully\n"));
1468	#if HC_ARCH_BITS == 64
1469	LogRel(("Debug: HCPhys32BitPD=%VHp aHCPhysPaePDs={%VHp,%VHp,%VHp,%VHp} HCPhysPaePDPT=%VHp HCPhysPaePML4=%VHp\n",
1470	pVM->pgm.s.HCPhys32BitPD, pVM->pgm.s.aHCPhysPaePDs[0], pVM->pgm.s.aHCPhysPaePDs[1], pVM->pgm.s.aHCPhysPaePDs[2], pVM->pgm.s.aHCPhysPaePDs[3],
1471	pVM->pgm.s.HCPhysPaePDPT, pVM->pgm.s.HCPhysPaePML4));
1472	LogRel(("Debug: HCPhysInterPD=%VHp HCPhysInterPaePDPT=%VHp HCPhysInterPaePML4=%VHp\n",
1473	pVM->pgm.s.HCPhysInterPD, pVM->pgm.s.HCPhysInterPaePDPT, pVM->pgm.s.HCPhysInterPaePML4));
1474	LogRel(("Debug: apInterPTs={%VHp,%VHp} apInterPaePTs={%VHp,%VHp} apInterPaePDs={%VHp,%VHp,%VHp,%VHp} pInterPaePDPT64=%VHp\n",
1475	MMPage2Phys(pVM, pVM->pgm.s.apInterPTs[0]), MMPage2Phys(pVM, pVM->pgm.s.apInterPTs[1]),
1476	MMPage2Phys(pVM, pVM->pgm.s.apInterPaePTs[0]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePTs[1]),
1477	MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[0]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[1]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[2]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[3]),
1478	MMPage2Phys(pVM, pVM->pgm.s.pInterPaePDPT64)));
1479	#endif
1480
1481	return VINF_SUCCESS;
1482	}
1483
1484	LogFlow(("pgmR3InitPaging: returns %Vrc\n", rc));
1485	return rc;
1486	}
1487
1488
1489	#ifdef VBOX_WITH_STATISTICS
1490	/**
1491	* Init statistics
1492	*/
1493	static void pgmR3InitStats(PVM pVM)
1494	{
1495	PPGM pPGM = &pVM->pgm.s;
1496
1497	/*
1498	* Note! The layout of this function matches the member layout exactly!
1499	*/
1500
1501	/* R3 only: */
1502
1503	/* GC only: */
1504	STAM_REG(pVM, &pPGM->StatGCInvalidatePage, STAMTYPE_PROFILE, "/PGM/GCInvalidatePage", STAMUNIT_TICKS_PER_CALL, "PGMGCInvalidatePage() profiling.");
1505
1506	/* RZ only: */
1507
1508	/* R0 only: */
1509
1510	/* RZ & R3: */
1511	STAM_REG(pVM, &pPGM->StatRZSyncCR3, STAMTYPE_PROFILE, "/PGM/RZ/SyncCR3", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMSyncCR3() body.");
1512	STAM_REG(pVM, &pPGM->StatRZSyncCR3Handlers, STAMTYPE_PROFILE, "/PGM/RZ/SyncCR3/Handlers", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMSyncCR3() update handler section.");
1513	STAM_REG(pVM, &pPGM->StatRZSyncCR3HandlerVirtualUpdate, STAMTYPE_PROFILE, "/PGM/RZ/SyncCR3/Handlers/VirtualUpdate", STAMUNIT_TICKS_PER_CALL, "Profiling of the virtual handler updates.");
1514	STAM_REG(pVM, &pPGM->StatRZSyncCR3HandlerVirtualReset, STAMTYPE_PROFILE, "/PGM/RZ/SyncCR3/Handlers/VirtualReset", STAMUNIT_TICKS_PER_CALL, "Profiling of the virtual handler resets.");
1515	STAM_REG(pVM, &pPGM->StatRZSyncCR3Global, STAMTYPE_COUNTER, "/PGM/RZ/SyncCR3/Global", STAMUNIT_OCCURENCES, "The number of global CR3 syncs.");
1516	STAM_REG(pVM, &pPGM->StatRZSyncCR3NotGlobal, STAMTYPE_COUNTER, "/PGM/RZ/SyncCR3/NotGlobal", STAMUNIT_OCCURENCES, "The number of non-global CR3 syncs.");
1517	STAM_REG(pVM, &pPGM->StatRZSyncCR3DstCacheHit, STAMTYPE_COUNTER, "/PGM/RZ/SyncCR3/DstChacheHit", STAMUNIT_OCCURENCES, "The number of times we got some kind of a cache hit.");
1518	STAM_REG(pVM, &pPGM->StatRZSyncCR3DstFreed, STAMTYPE_COUNTER, "/PGM/RZ/SyncCR3/DstFreed", STAMUNIT_OCCURENCES, "The number of times we've had to free a shadow entry.");
1519	STAM_REG(pVM, &pPGM->StatRZSyncCR3DstFreedSrcNP, STAMTYPE_COUNTER, "/PGM/RZ/SyncCR3/DstFreedSrcNP", STAMUNIT_OCCURENCES, "The number of times we've had to free a shadow entry for which the source entry was not present.");
1520	STAM_REG(pVM, &pPGM->StatRZSyncCR3DstNotPresent, STAMTYPE_COUNTER, "/PGM/RZ/SyncCR3/DstNotPresent", STAMUNIT_OCCURENCES, "The number of times we've encountered a not present shadow entry for a present guest entry.");
1521	STAM_REG(pVM, &pPGM->StatRZSyncCR3DstSkippedGlobalPD, STAMTYPE_COUNTER, "/PGM/RZ/SyncCR3/DstSkippedGlobalPD", STAMUNIT_OCCURENCES, "The number of times a global page directory wasn't flushed.");
1522	STAM_REG(pVM, &pPGM->StatRZSyncCR3DstSkippedGlobalPT, STAMTYPE_COUNTER, "/PGM/RZ/SyncCR3/DstSkippedGlobalPT", STAMUNIT_OCCURENCES, "The number of times a page table with only global entries wasn't flushed.");
1523	STAM_REG(pVM, &pPGM->StatRZSyncPT, STAMTYPE_PROFILE, "/PGM/RZ/SyncPT", STAMUNIT_TICKS_PER_CALL, "Profiling of the pfnSyncPT() body.");
1524	STAM_REG(pVM, &pPGM->StatRZSyncPTFailed, STAMTYPE_COUNTER, "/PGM/RZ/SyncPT/Failed", STAMUNIT_OCCURENCES, "The number of times pfnSyncPT() failed.");
1525	STAM_REG(pVM, &pPGM->StatRZSyncPagePDNAs, STAMTYPE_COUNTER, "/PGM/GC/SyncPagePDNAs", STAMUNIT_OCCURENCES, "The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit.");
1526	STAM_REG(pVM, &pPGM->StatRZSyncPagePDOutOfSync, STAMTYPE_COUNTER, "/PGM/GC/SyncPagePDOutOfSync", STAMUNIT_OCCURENCES, "The number of time we've encountered an out-of-sync PD in SyncPage.");
1527	STAM_REG(pVM, &pPGM->StatRZAccessedPage, STAMTYPE_COUNTER, "/PGM/RZ/AccessedPage", STAMUNIT_OCCURENCES, "The number of pages marked not present for accessed bit emulation.");
1528	STAM_REG(pVM, &pPGM->StatRZDirtyBitTracking, STAMTYPE_PROFILE, "/PGM/RZ/DirtyPage", STAMUNIT_TICKS_PER_CALL, "Profiling the dirty bit tracking in CheckPageFault().");
1529	STAM_REG(pVM, &pPGM->StatRZDirtyPage, STAMTYPE_COUNTER, "/PGM/RZ/DirtyPage/Mark", STAMUNIT_OCCURENCES, "The number of pages marked read-only for dirty bit tracking.");
1530	STAM_REG(pVM, &pPGM->StatRZDirtyPageBig, STAMTYPE_COUNTER, "/PGM/RZ/DirtyPage/MarkBig", STAMUNIT_OCCURENCES, "The number of 4MB pages marked read-only for dirty bit tracking.");
1531	STAM_REG(pVM, &pPGM->StatRZDirtyPageSkipped, STAMTYPE_COUNTER, "/PGM/RZ/DirtyPage/Skipped", STAMUNIT_OCCURENCES, "The number of pages already dirty or readonly.");
1532	STAM_REG(pVM, &pPGM->StatRZDirtyPageTrap, STAMTYPE_COUNTER, "/PGM/RZ/DirtyPage/Trap", STAMUNIT_OCCURENCES, "The number of traps generated for dirty bit tracking.");
1533	STAM_REG(pVM, &pPGM->StatRZDirtiedPage, STAMTYPE_COUNTER, "/PGM/RZ/DirtyPage/SetDirty", STAMUNIT_OCCURENCES, "The number of pages marked dirty because of write accesses.");
1534	STAM_REG(pVM, &pPGM->StatRZDirtyTrackRealPF, STAMTYPE_COUNTER, "/PGM/RZ/DirtyPage/RealPF", STAMUNIT_OCCURENCES, "The number of real pages faults during dirty bit tracking.");
1535	STAM_REG(pVM, &pPGM->StatRZPageAlreadyDirty, STAMTYPE_COUNTER, "/PGM/RZ/DirtyPage/AlreadySet", STAMUNIT_OCCURENCES, "The number of pages already marked dirty because of write accesses.");
1536	STAM_REG(pVM, &pPGM->StatRZInvalidatePage, STAMTYPE_PROFILE, "/PGM/RZ/InvalidatePage", STAMUNIT_TICKS_PER_CALL, "PGMInvalidatePage() profiling.");
1537	STAM_REG(pVM, &pPGM->StatRZInvalidatePage4KBPages, STAMTYPE_COUNTER, "/PGM/RZ/InvalidatePage/4KBPages", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was called for a 4KB page.");
1538	STAM_REG(pVM, &pPGM->StatRZInvalidatePage4MBPages, STAMTYPE_COUNTER, "/PGM/RZ/InvalidatePage/4MBPages", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was called for a 4MB page.");
1539	STAM_REG(pVM, &pPGM->StatRZInvalidatePage4MBPagesSkip, STAMTYPE_COUNTER, "/PGM/RZ/InvalidatePage/4MBPagesSkip",STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() skipped a 4MB page.");
1540	STAM_REG(pVM, &pPGM->StatRZInvalidatePagePDMappings, STAMTYPE_COUNTER, "/PGM/RZ/InvalidatePage/PDMappings", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict).");
1541	STAM_REG(pVM, &pPGM->StatRZInvalidatePagePDNAs, STAMTYPE_COUNTER, "/PGM/RZ/InvalidatePage/PDNAs", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was called for a not accessed page directory.");
1542	STAM_REG(pVM, &pPGM->StatRZInvalidatePagePDNPs, STAMTYPE_COUNTER, "/PGM/RZ/InvalidatePage/PDNPs", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was called for a not present page directory.");
1543	STAM_REG(pVM, &pPGM->StatRZInvalidatePagePDOutOfSync, STAMTYPE_COUNTER, "/PGM/RZ/InvalidatePage/PDOutOfSync", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was called for an out of sync page directory.");
1544	STAM_REG(pVM, &pPGM->StatRZInvalidatePageSkipped, STAMTYPE_COUNTER, "/PGM/RZ/InvalidatePage/Skipped", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3.");
1545
1546
1547	/* TODO: */
1548
1549	STAM_REG(pVM, &pPGM->StatGCTrap0e, STAMTYPE_PROFILE, "/PGM/GC/Trap0e", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMGCTrap0eHandler() body.");
1550	STAM_REG(pVM, &pPGM->StatCheckPageFault, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time/CheckPageFault", STAMUNIT_TICKS_PER_CALL, "Profiling of checking for dirty/access emulation faults.");
1551	STAM_REG(pVM, &pPGM->StatLazySyncPT, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time/SyncPT", STAMUNIT_TICKS_PER_CALL, "Profiling of lazy page table syncing.");
1552	STAM_REG(pVM, &pPGM->StatMapping, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time/Mapping", STAMUNIT_TICKS_PER_CALL, "Profiling of checking virtual mappings.");
1553	STAM_REG(pVM, &pPGM->StatOutOfSync, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time/OutOfSync", STAMUNIT_TICKS_PER_CALL, "Profiling of out of sync page handling.");
1554	STAM_REG(pVM, &pPGM->StatHandlers, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time/Handlers", STAMUNIT_TICKS_PER_CALL, "Profiling of checking handlers.");
1555	STAM_REG(pVM, &pPGM->StatEIPHandlers, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time/EIPHandlers", STAMUNIT_TICKS_PER_CALL, "Profiling of checking eip handlers.");
1556	STAM_REG(pVM, &pPGM->StatTrap0eCSAM, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time2/CSAM", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is CSAM.");
1557	STAM_REG(pVM, &pPGM->StatTrap0eDirtyAndAccessedBits, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time2/DirtyAndAccessedBits", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is dirty and/or accessed bit emulation.");
1558	STAM_REG(pVM, &pPGM->StatTrap0eGuestTrap, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time2/GuestTrap", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is a guest trap.");
1559	STAM_REG(pVM, &pPGM->StatTrap0eHndPhys, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time2/HandlerPhysical", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is a physical handler.");
1560	STAM_REG(pVM, &pPGM->StatTrap0eHndVirt, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time2/HandlerVirtual",STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is a virtual handler.");
1561	STAM_REG(pVM, &pPGM->StatTrap0eHndUnhandled, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time2/HandlerUnhandled", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is access outside the monitored areas of a monitored page.");
1562	STAM_REG(pVM, &pPGM->StatTrap0eMisc, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time2/Misc", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is not known.");
1563	STAM_REG(pVM, &pPGM->StatTrap0eOutOfSync, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time2/OutOfSync", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is an out-of-sync page.");
1564	STAM_REG(pVM, &pPGM->StatTrap0eOutOfSyncHndPhys, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time2/OutOfSyncHndPhys", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is an out-of-sync physical handler page.");
1565	STAM_REG(pVM, &pPGM->StatTrap0eOutOfSyncHndVirt, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time2/OutOfSyncHndVirt", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is an out-of-sync virtual handler page.");
1566	STAM_REG(pVM, &pPGM->StatTrap0eOutOfSyncObsHnd, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time2/OutOfSyncObsHnd", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is an obsolete handler page.");
1567	STAM_REG(pVM, &pPGM->StatTrap0eSyncPT, STAMTYPE_PROFILE, "/PGM/GC/Trap0e/Time2/SyncPT", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is lazy syncing of a PT.");
1568
1569	STAM_REG(pVM, &pPGM->StatTrap0eMapHandler, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/Handlers/Mapping", STAMUNIT_OCCURENCES, "Number of traps due to access handlers in mappings.");
1570	STAM_REG(pVM, &pPGM->StatHandlersOutOfSync, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/Handlers/OutOfSync", STAMUNIT_OCCURENCES, "Number of traps due to out-of-sync handled pages.");
1571	STAM_REG(pVM, &pPGM->StatHandlersPhysical, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/Handlers/Physical", STAMUNIT_OCCURENCES, "Number of traps due to physical access handlers.");
1572	STAM_REG(pVM, &pPGM->StatHandlersVirtual, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/Handlers/Virtual", STAMUNIT_OCCURENCES, "Number of traps due to virtual access handlers.");
1573	STAM_REG(pVM, &pPGM->StatHandlersVirtualByPhys, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/Handlers/VirtualByPhys", STAMUNIT_OCCURENCES, "Number of traps due to virtual access handlers by physical address.");
1574	STAM_REG(pVM, &pPGM->StatHandlersVirtualUnmarked, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/Handlers/VirtualUnmarked", STAMUNIT_OCCURENCES,"Number of traps due to virtual access handlers by virtual address (without proper physical flags).");
1575	STAM_REG(pVM, &pPGM->StatHandlersUnhandled, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/Handlers/Unhandled", STAMUNIT_OCCURENCES, "Number of traps due to access outside range of monitored page(s).");
1576	STAM_REG(pVM, &pPGM->StatHandlersInvalid, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/Handlers/Invalid", STAMUNIT_OCCURENCES, "Number of traps due to access to invalid physical memory.");
1577
1578	STAM_REG(pVM, &pPGM->StatGCTrap0eConflicts, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/Conflicts", STAMUNIT_OCCURENCES, "The number of times #PF was caused by an undetected conflict.");
1579	STAM_REG(pVM, &pPGM->StatGCTrap0eUSNotPresentRead, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/User/NPRead", STAMUNIT_OCCURENCES, "Number of user mode not present read page faults.");
1580	STAM_REG(pVM, &pPGM->StatGCTrap0eUSNotPresentWrite, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/User/NPWrite", STAMUNIT_OCCURENCES, "Number of user mode not present write page faults.");
1581	STAM_REG(pVM, &pPGM->StatGCTrap0eUSWrite, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/User/Write", STAMUNIT_OCCURENCES, "Number of user mode write page faults.");
1582	STAM_REG(pVM, &pPGM->StatGCTrap0eUSReserved, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/User/Reserved", STAMUNIT_OCCURENCES, "Number of user mode reserved bit page faults.");
1583	STAM_REG(pVM, &pPGM->StatGCTrap0eUSNXE, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/User/NXE", STAMUNIT_OCCURENCES, "Number of user mode NXE page faults.");
1584	STAM_REG(pVM, &pPGM->StatGCTrap0eUSRead, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/User/Read", STAMUNIT_OCCURENCES, "Number of user mode read page faults.");
1585
1586	STAM_REG(pVM, &pPGM->StatGCTrap0eSVNotPresentRead, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/Supervisor/NPRead", STAMUNIT_OCCURENCES, "Number of supervisor mode not present read page faults.");
1587	STAM_REG(pVM, &pPGM->StatGCTrap0eSVNotPresentWrite, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/Supervisor/NPWrite", STAMUNIT_OCCURENCES, "Number of supervisor mode not present write page faults.");
1588	STAM_REG(pVM, &pPGM->StatGCTrap0eSVWrite, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/Supervisor/Write", STAMUNIT_OCCURENCES, "Number of supervisor mode write page faults.");
1589	STAM_REG(pVM, &pPGM->StatGCTrap0eSVReserved, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/Supervisor/Reserved", STAMUNIT_OCCURENCES, "Number of supervisor mode reserved bit page faults.");
1590	STAM_REG(pVM, &pPGM->StatGCTrap0eSNXE, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/Supervisor/NXE", STAMUNIT_OCCURENCES, "Number of supervisor mode NXE page faults.");
1591	STAM_REG(pVM, &pPGM->StatGCTrap0eUnhandled, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/GuestPF/Unhandled", STAMUNIT_OCCURENCES, "Number of guest real page faults.");
1592	STAM_REG(pVM, &pPGM->StatGCTrap0eMap, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/GuestPF/Map", STAMUNIT_OCCURENCES, "Number of guest page faults due to map accesses.");
1593
1594	STAM_REG(pVM, &pPGM->StatTrap0eWPEmulGC, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/WP/InGC", STAMUNIT_OCCURENCES, "Number of guest page faults due to X86_CR0_WP emulation.");
1595	STAM_REG(pVM, &pPGM->StatTrap0eWPEmulR3, STAMTYPE_COUNTER, "/PGM/GC/Trap0e/WP/ToR3", STAMUNIT_OCCURENCES, "Number of guest page faults due to X86_CR0_WP emulation (forward to R3 for emulation).");
1596
1597	STAM_REG(pVM, &pPGM->StatGCGuestCR3WriteHandled, STAMTYPE_COUNTER, "/PGM/GC/CR3WriteInt", STAMUNIT_OCCURENCES, "The number of times the Guest CR3 change was successfully handled.");
1598	STAM_REG(pVM, &pPGM->StatGCGuestCR3WriteUnhandled, STAMTYPE_COUNTER, "/PGM/GC/CR3WriteEmu", STAMUNIT_OCCURENCES, "The number of times the Guest CR3 change was passed back to the recompiler.");
1599	STAM_REG(pVM, &pPGM->StatGCGuestCR3WriteConflict, STAMTYPE_COUNTER, "/PGM/GC/CR3WriteConflict", STAMUNIT_OCCURENCES, "The number of times the Guest CR3 monitoring detected a conflict.");
1600
1601	STAM_REG(pVM, &pPGM->StatGCPageOutOfSyncSupervisor, STAMTYPE_COUNTER, "/PGM/GC/OutOfSync/SuperVisor", STAMUNIT_OCCURENCES, "Number of traps due to pages out of sync.");
1602	STAM_REG(pVM, &pPGM->StatGCPageOutOfSyncUser, STAMTYPE_COUNTER, "/PGM/GC/OutOfSync/User", STAMUNIT_OCCURENCES, "Number of traps due to pages out of sync.");
1603
1604	STAM_REG(pVM, &pPGM->StatGCGuestROMWriteHandled, STAMTYPE_COUNTER, "/PGM/GC/ROMWriteInt", STAMUNIT_OCCURENCES, "The number of times the Guest ROM change was successfully handled.");
1605	STAM_REG(pVM, &pPGM->StatGCGuestROMWriteUnhandled, STAMTYPE_COUNTER, "/PGM/GC/ROMWriteEmu", STAMUNIT_OCCURENCES, "The number of times the Guest ROM change was passed back to the recompiler.");
1606
1607	STAM_REG(pVM, &pPGM->StatDynMapCacheHits, STAMTYPE_COUNTER, "/PGM/GC/DynMapCache/Hits" , STAMUNIT_OCCURENCES, "Number of dynamic page mapping cache hits.");
1608	STAM_REG(pVM, &pPGM->StatDynMapCacheMisses, STAMTYPE_COUNTER, "/PGM/GC/DynMapCache/Misses" , STAMUNIT_OCCURENCES, "Number of dynamic page mapping cache misses.");
1609
1610	STAM_REG(pVM, &pPGM->StatHCDetectedConflicts, STAMTYPE_COUNTER, "/PGM/HC/DetectedConflicts", STAMUNIT_OCCURENCES, "The number of times PGMR3CheckMappingConflicts() detected a conflict.");
1611	STAM_REG(pVM, &pPGM->StatHCGuestPDWrite, STAMTYPE_COUNTER, "/PGM/HC/PDWrite", STAMUNIT_OCCURENCES, "The total number of times pgmHCGuestPDWriteHandler() was called.");
1612	STAM_REG(pVM, &pPGM->StatHCGuestPDWriteConflict, STAMTYPE_COUNTER, "/PGM/HC/PDWriteConflict", STAMUNIT_OCCURENCES, "The number of times pgmHCGuestPDWriteHandler() detected a conflict.");
1613
1614	STAM_REG(pVM, &pPGM->StatHCResolveConflict, STAMTYPE_PROFILE, "/PGM/HC/ResolveConflict", STAMUNIT_TICKS_PER_CALL, "pgmR3SyncPTResolveConflict() profiling (includes the entire relocation).");
1615	STAM_REG(pVM, &pPGM->StatHCPrefetch, STAMTYPE_PROFILE, "/PGM/HC/Prefetch", STAMUNIT_TICKS_PER_CALL, "PGMR3PrefetchPage profiling.");
1616
1617	STAM_REG(pVM, &pPGM->StatR3SyncPT, STAMTYPE_PROFILE, "/PGM/R3/SyncPT", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMR3SyncPT() body.");
1618
1619
1620	STAM_REG(pVM, &pPGM->StatFlushTLB, STAMTYPE_PROFILE, "/PGM/FlushTLB", STAMUNIT_OCCURENCES, "Profiling of the PGMFlushTLB() body.");
1621	STAM_REG(pVM, &pPGM->StatFlushTLBNewCR3, STAMTYPE_COUNTER, "/PGM/FlushTLB/NewCR3", STAMUNIT_OCCURENCES, "The number of times PGMFlushTLB was called with a new CR3, non-global. (switch)");
1622	STAM_REG(pVM, &pPGM->StatFlushTLBNewCR3Global, STAMTYPE_COUNTER, "/PGM/FlushTLB/NewCR3Global", STAMUNIT_OCCURENCES, "The number of times PGMFlushTLB was called with a new CR3, global. (switch)");
1623	STAM_REG(pVM, &pPGM->StatFlushTLBSameCR3, STAMTYPE_COUNTER, "/PGM/FlushTLB/SameCR3", STAMUNIT_OCCURENCES, "The number of times PGMFlushTLB was called with the same CR3, non-global. (flush)");
1624	STAM_REG(pVM, &pPGM->StatFlushTLBSameCR3Global, STAMTYPE_COUNTER, "/PGM/FlushTLB/SameCR3Global", STAMUNIT_OCCURENCES, "The number of times PGMFlushTLB was called with the same CR3, global. (flush)");
1625
1626
1627	STAM_REG(pVM, &pPGM->StatVirtHandleSearchByPhysGC, STAMTYPE_PROFILE, "/PGM/VirtHandler/SearchByPhys/GC", STAMUNIT_TICKS_PER_CALL, "Profiling of pgmHandlerVirtualFindByPhysAddr in GC.");
1628	STAM_REG(pVM, &pPGM->StatVirtHandleSearchByPhysHC, STAMTYPE_PROFILE, "/PGM/VirtHandler/SearchByPhys/HC", STAMUNIT_TICKS_PER_CALL, "Profiling of pgmHandlerVirtualFindByPhysAddr in HC.");
1629	STAM_REG(pVM, &pPGM->StatHandlePhysicalReset, STAMTYPE_COUNTER, "/PGM/HC/HandlerPhysicalReset", STAMUNIT_OCCURENCES, "The number of times PGMR3HandlerPhysicalReset is called.");
1630
1631	STAM_REG(pVM, &pPGM->StatHCGstModifyPage, STAMTYPE_PROFILE, "/PGM/HC/GstModifyPage", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMGstModifyPage() body.");
1632	STAM_REG(pVM, &pPGM->StatGCGstModifyPage, STAMTYPE_PROFILE, "/PGM/GC/GstModifyPage", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMGstModifyPage() body.");
1633
1634	STAM_REG(pVM, &pPGM->StatSynPT4kGC, STAMTYPE_COUNTER, "/PGM/GC/SyncPT/4k", STAMUNIT_OCCURENCES, "Nr of 4k PT syncs");
1635	STAM_REG(pVM, &pPGM->StatSynPT4kHC, STAMTYPE_COUNTER, "/PGM/HC/SyncPT/4k", STAMUNIT_OCCURENCES, "Nr of 4k PT syncs");
1636	STAM_REG(pVM, &pPGM->StatSynPT4MGC, STAMTYPE_COUNTER, "/PGM/GC/SyncPT/4M", STAMUNIT_OCCURENCES, "Nr of 4M PT syncs");
1637	STAM_REG(pVM, &pPGM->StatSynPT4MHC, STAMTYPE_COUNTER, "/PGM/HC/SyncPT/4M", STAMUNIT_OCCURENCES, "Nr of 4M PT syncs");
1638
1639	STAM_REG(pVM, &pPGM->StatDynRamTotal, STAMTYPE_COUNTER, "/PGM/RAM/TotalAlloc", STAMUNIT_MEGABYTES, "Allocated mbs of guest ram.");
1640	STAM_REG(pVM, &pPGM->StatDynRamGrow, STAMTYPE_COUNTER, "/PGM/RAM/Grow", STAMUNIT_OCCURENCES, "Nr of pgmr3PhysGrowRange calls.");
1641
1642	STAM_REG(pVM, &pPGM->StatPageHCMapTlbHits, STAMTYPE_COUNTER, "/PGM/PageHCMap/TlbHits", STAMUNIT_OCCURENCES, "TLB hits.");
1643	STAM_REG(pVM, &pPGM->StatPageHCMapTlbMisses, STAMTYPE_COUNTER, "/PGM/PageHCMap/TlbMisses", STAMUNIT_OCCURENCES, "TLB misses.");
1644	STAM_REG(pVM, &pPGM->ChunkR3Map.c, STAMTYPE_U32, "/PGM/ChunkR3Map/c", STAMUNIT_OCCURENCES, "Number of mapped chunks.");
1645	STAM_REG(pVM, &pPGM->ChunkR3Map.cMax, STAMTYPE_U32, "/PGM/ChunkR3Map/cMax", STAMUNIT_OCCURENCES, "Maximum number of mapped chunks.");
1646	STAM_REG(pVM, &pPGM->StatChunkR3MapTlbHits, STAMTYPE_COUNTER, "/PGM/ChunkR3Map/TlbHits", STAMUNIT_OCCURENCES, "TLB hits.");
1647	STAM_REG(pVM, &pPGM->StatChunkR3MapTlbMisses, STAMTYPE_COUNTER, "/PGM/ChunkR3Map/TlbMisses", STAMUNIT_OCCURENCES, "TLB misses.");
1648	STAM_REG(pVM, &pPGM->StatPageReplaceShared, STAMTYPE_COUNTER, "/PGM/Page/ReplacedShared", STAMUNIT_OCCURENCES, "Times a shared page was replaced.");
1649	STAM_REG(pVM, &pPGM->StatPageReplaceZero, STAMTYPE_COUNTER, "/PGM/Page/ReplacedZero", STAMUNIT_OCCURENCES, "Times the zero page was replaced.");
1650	STAM_REG(pVM, &pPGM->StatPageHandyAllocs, STAMTYPE_COUNTER, "/PGM/Page/HandyAllocs", STAMUNIT_OCCURENCES, "Number of times we've allocated more handy pages.");
1651	STAM_REG(pVM, &pPGM->cAllPages, STAMTYPE_U32, "/PGM/Page/cAllPages", STAMUNIT_OCCURENCES, "The total number of pages.");
1652	STAM_REG(pVM, &pPGM->cPrivatePages, STAMTYPE_U32, "/PGM/Page/cPrivatePages", STAMUNIT_OCCURENCES, "The number of private pages.");
1653	STAM_REG(pVM, &pPGM->cSharedPages, STAMTYPE_U32, "/PGM/Page/cSharedPages", STAMUNIT_OCCURENCES, "The number of shared pages.");
1654	STAM_REG(pVM, &pPGM->cZeroPages, STAMTYPE_U32, "/PGM/Page/cZeroPages", STAMUNIT_OCCURENCES, "The number of zero backed pages.");
1655
1656	#ifdef PGMPOOL_WITH_GCPHYS_TRACKING
1657	STAM_REG(pVM, &pPGM->StatTrackVirgin, STAMTYPE_COUNTER, "/PGM/Track/Virgin", STAMUNIT_OCCURENCES, "The number of first time shadowings");
1658	STAM_REG(pVM, &pPGM->StatTrackAliased, STAMTYPE_COUNTER, "/PGM/Track/Aliased", STAMUNIT_OCCURENCES, "The number of times switching to cRef2, i.e. the page is being shadowed by two PTs.");
1659	STAM_REG(pVM, &pPGM->StatTrackAliasedMany, STAMTYPE_COUNTER, "/PGM/Track/AliasedMany", STAMUNIT_OCCURENCES, "The number of times we're tracking using cRef2.");
1660	STAM_REG(pVM, &pPGM->StatTrackAliasedLots, STAMTYPE_COUNTER, "/PGM/Track/AliasedLots", STAMUNIT_OCCURENCES, "The number of times we're hitting pages which has overflowed cRef2");
1661	STAM_REG(pVM, &pPGM->StatTrackOverflows, STAMTYPE_COUNTER, "/PGM/Track/Overflows", STAMUNIT_OCCURENCES, "The number of times the extent list grows to long.");
1662	STAM_REG(pVM, &pPGM->StatTrackDeref, STAMTYPE_PROFILE, "/PGM/Track/Deref", STAMUNIT_OCCURENCES, "Profiling of SyncPageWorkerTrackDeref (expensive).");
1663	#endif
1664
1665	for (unsigned i = 0; i < X86_PG_ENTRIES; i++)
1666	{
1667	/** @todo r=bird: We need a STAMR3RegisterF()! */
1668	char szName[32];
1669
1670	RTStrPrintf(szName, sizeof(szName), "/PGM/GC/PD/Trap0e/%04X", i);
1671	int rc = STAMR3Register(pVM, &pPGM->StatGCTrap0ePD[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, szName, STAMUNIT_OCCURENCES, "The number of traps in page directory n.");
1672	AssertRC(rc);
1673
1674	RTStrPrintf(szName, sizeof(szName), "/PGM/GC/PD/SyncPt/%04X", i);
1675	rc = STAMR3Register(pVM, &pPGM->StatGCSyncPtPD[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, szName, STAMUNIT_OCCURENCES, "The number of syncs per PD n.");
1676	AssertRC(rc);
1677
1678	RTStrPrintf(szName, sizeof(szName), "/PGM/GC/PD/SyncPage/%04X", i);
1679	rc = STAMR3Register(pVM, &pPGM->StatGCSyncPagePD[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, szName, STAMUNIT_OCCURENCES, "The number of out of sync pages per page directory n.");
1680	AssertRC(rc);
1681	}
1682	}
1683	#endif /* VBOX_WITH_STATISTICS */
1684
1685	/**
1686	* Init the PGM bits that rely on VMMR0 and MM to be fully initialized.
1687	*
1688	* The dynamic mapping area will also be allocated and initialized at this
1689	* time. We could allocate it during PGMR3Init of course, but the mapping
1690	* wouldn't be allocated at that time preventing us from setting up the
1691	* page table entries with the dummy page.
1692	*
1693	* @returns VBox status code.
1694	* @param pVM VM handle.
1695	*/
1696	VMMR3DECL(int) PGMR3InitDynMap(PVM pVM)
1697	{
1698	RTGCPTR GCPtr;
1699	/*
1700	* Reserve space for mapping the paging pages into guest context.
1701	*/
1702	int rc = MMR3HyperReserve(pVM, PAGE_SIZE * (2 + RT_ELEMENTS(pVM->pgm.s.apHCPaePDs) + 1 + 2 + 2), "Paging", &GCPtr);
1703	AssertRCReturn(rc, rc);
1704	pVM->pgm.s.pGC32BitPD = GCPtr;
1705	MMR3HyperReserve(pVM, PAGE_SIZE, "fence", NULL);
1706
1707	/*
1708	* Reserve space for the dynamic mappings.
1709	*/
1710	/** @todo r=bird: Need to verify that the checks for crossing PTs are correct here. They seems to be assuming 4MB PTs.. */
1711	rc = MMR3HyperReserve(pVM, MM_HYPER_DYNAMIC_SIZE, "Dynamic mapping", &GCPtr);
1712	if (VBOX_SUCCESS(rc))
1713	pVM->pgm.s.pbDynPageMapBaseGC = GCPtr;
1714
1715	if ( VBOX_SUCCESS(rc)
1716	&& (pVM->pgm.s.pbDynPageMapBaseGC >> X86_PD_SHIFT) != ((pVM->pgm.s.pbDynPageMapBaseGC + MM_HYPER_DYNAMIC_SIZE - 1) >> X86_PD_SHIFT))
1717	{
1718	rc = MMR3HyperReserve(pVM, MM_HYPER_DYNAMIC_SIZE, "Dynamic mapping not crossing", &GCPtr);
1719	if (VBOX_SUCCESS(rc))
1720	pVM->pgm.s.pbDynPageMapBaseGC = GCPtr;
1721	}
1722	if (VBOX_SUCCESS(rc))
1723	{
1724	AssertRelease((pVM->pgm.s.pbDynPageMapBaseGC >> X86_PD_SHIFT) == ((pVM->pgm.s.pbDynPageMapBaseGC + MM_HYPER_DYNAMIC_SIZE - 1) >> X86_PD_SHIFT));
1725	MMR3HyperReserve(pVM, PAGE_SIZE, "fence", NULL);
1726	}
1727	return rc;
1728	}
1729
1730
1731	/**
1732	* Ring-3 init finalizing.
1733	*
1734	* @returns VBox status code.
1735	* @param pVM The VM handle.
1736	*/
1737	VMMR3DECL(int) PGMR3InitFinalize(PVM pVM)
1738	{
1739	/*
1740	* Map the paging pages into the guest context.
1741	*/
1742	RTGCPTR GCPtr = pVM->pgm.s.pGC32BitPD;
1743	AssertReleaseReturn(GCPtr, VERR_INTERNAL_ERROR);
1744
1745	int rc = PGMMap(pVM, GCPtr, pVM->pgm.s.HCPhys32BitPD, PAGE_SIZE, 0);
1746	AssertRCReturn(rc, rc);
1747	pVM->pgm.s.pGC32BitPD = GCPtr;
1748	GCPtr += PAGE_SIZE;
1749	GCPtr += PAGE_SIZE; /* reserved page */
1750
1751	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.apHCPaePDs); i++)
1752	{
1753	rc = PGMMap(pVM, GCPtr, pVM->pgm.s.aHCPhysPaePDs[i], PAGE_SIZE, 0);
1754	AssertRCReturn(rc, rc);
1755	pVM->pgm.s.apGCPaePDs[i] = GCPtr;
1756	GCPtr += PAGE_SIZE;
1757	}
1758	/* A bit of paranoia is justified. */
1759	AssertRelease((RTGCUINTPTR)pVM->pgm.s.apGCPaePDs[0] + PAGE_SIZE == (RTGCUINTPTR)pVM->pgm.s.apGCPaePDs[1]);
1760	AssertRelease((RTGCUINTPTR)pVM->pgm.s.apGCPaePDs[1] + PAGE_SIZE == (RTGCUINTPTR)pVM->pgm.s.apGCPaePDs[2]);
1761	AssertRelease((RTGCUINTPTR)pVM->pgm.s.apGCPaePDs[2] + PAGE_SIZE == (RTGCUINTPTR)pVM->pgm.s.apGCPaePDs[3]);
1762	GCPtr += PAGE_SIZE; /* reserved page */
1763
1764	rc = PGMMap(pVM, GCPtr, pVM->pgm.s.HCPhysPaePDPT, PAGE_SIZE, 0);
1765	AssertRCReturn(rc, rc);
1766	pVM->pgm.s.pGCPaePDPT = GCPtr;
1767	GCPtr += PAGE_SIZE;
1768	GCPtr += PAGE_SIZE; /* reserved page */
1769
1770
1771	/*
1772	* Reserve space for the dynamic mappings.
1773	* Initialize the dynamic mapping pages with dummy pages to simply the cache.
1774	*/
1775	/* get the pointer to the page table entries. */
1776	PPGMMAPPING pMapping = pgmGetMapping(pVM, pVM->pgm.s.pbDynPageMapBaseGC);
1777	AssertRelease(pMapping);
1778	const uintptr_t off = pVM->pgm.s.pbDynPageMapBaseGC - pMapping->GCPtr;
1779	const unsigned iPT = off >> X86_PD_SHIFT;
1780	const unsigned iPG = (off >> X86_PT_SHIFT) & X86_PT_MASK;
1781	pVM->pgm.s.paDynPageMap32BitPTEsGC = pMapping->aPTs[iPT].pPTRC + iPG * sizeof(pMapping->aPTs[0].pPTR3->a[0]);
1782	pVM->pgm.s.paDynPageMapPaePTEsGC = pMapping->aPTs[iPT].paPaePTsRC + iPG * sizeof(pMapping->aPTs[0].paPaePTsR3->a[0]);
1783
1784	/* init cache */
1785	RTHCPHYS HCPhysDummy = MMR3PageDummyHCPhys(pVM);
1786	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.aHCPhysDynPageMapCache); i++)
1787	pVM->pgm.s.aHCPhysDynPageMapCache[i] = HCPhysDummy;
1788
1789	for (unsigned i = 0; i < MM_HYPER_DYNAMIC_SIZE; i += PAGE_SIZE)
1790	{
1791	rc = PGMMap(pVM, pVM->pgm.s.pbDynPageMapBaseGC + i, HCPhysDummy, PAGE_SIZE, 0);
1792	AssertRCReturn(rc, rc);
1793	}
1794
1795	/* Note that AMD uses all the 8 reserved bits for the address (so 40 bits in total); Intel only goes up to 36 bits, so
1796	* we stick to 36 as well.
1797	*
1798	* @todo How to test for the 40 bits support? Long mode seems to be the test criterium.
1799	*/
1800	uint32_t u32Dummy, u32Features;
1801	CPUMGetGuestCpuId(pVM, 1, &u32Dummy, &u32Dummy, &u32Dummy, &u32Features);
1802
1803	if (u32Features & X86_CPUID_FEATURE_EDX_PSE36)
1804	pVM->pgm.s.GCPhys4MBPSEMask = RT_BIT_64(36) - 1;
1805	else
1806	pVM->pgm.s.GCPhys4MBPSEMask = RT_BIT_64(32) - 1;
1807
1808	LogRel(("PGMR3InitFinalize: 4 MB PSE mask %VGp\n", pVM->pgm.s.GCPhys4MBPSEMask));
1809
1810	return rc;
1811	}
1812
1813
1814	/**
1815	* Applies relocations to data and code managed by this
1816	* component. This function will be called at init and
1817	* whenever the VMM need to relocate it self inside the GC.
1818	*
1819	* @param pVM The VM.
1820	* @param offDelta Relocation delta relative to old location.
1821	*/
1822	VMMR3DECL(void) PGMR3Relocate(PVM pVM, RTGCINTPTR offDelta)
1823	{
1824	LogFlow(("PGMR3Relocate\n"));
1825
1826	/*
1827	* Paging stuff.
1828	*/
1829	pVM->pgm.s.GCPtrCR3Mapping += offDelta;
1830	/** @todo move this into shadow and guest specific relocation functions. */
1831	AssertMsg(pVM->pgm.s.pGC32BitPD, ("Init order, no relocation before paging is initialized!\n"));
1832	pVM->pgm.s.pGC32BitPD += offDelta;
1833	pVM->pgm.s.pGuestPDGC += offDelta;
1834	AssertCompile(RT_ELEMENTS(pVM->pgm.s.apGCPaePDs) == RT_ELEMENTS(pVM->pgm.s.apGstPaePDsGC));
1835	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.apGCPaePDs); i++)
1836	{
1837	pVM->pgm.s.apGCPaePDs[i] += offDelta;
1838	pVM->pgm.s.apGstPaePDsGC[i] += offDelta;
1839	}
1840	pVM->pgm.s.pGstPaePDPTGC += offDelta;
1841	pVM->pgm.s.pGCPaePDPT += offDelta;
1842
1843	pgmR3ModeDataInit(pVM, true /* resolve GC/R0 symbols */);
1844	pgmR3ModeDataSwitch(pVM, pVM->pgm.s.enmShadowMode, pVM->pgm.s.enmGuestMode);
1845
1846	PGM_SHW_PFN(Relocate, pVM)(pVM, offDelta);
1847	PGM_GST_PFN(Relocate, pVM)(pVM, offDelta);
1848	PGM_BTH_PFN(Relocate, pVM)(pVM, offDelta);
1849
1850	/*
1851	* Trees.
1852	*/
1853	pVM->pgm.s.pTreesRC = MMHyperR3ToRC(pVM, pVM->pgm.s.pTreesR3);
1854
1855	/*
1856	* Ram ranges.
1857	*/
1858	if (pVM->pgm.s.pRamRangesR3)
1859	{
1860	pVM->pgm.s.pRamRangesRC = MMHyperR3ToRC(pVM, pVM->pgm.s.pRamRangesR3);
1861	for (PPGMRAMRANGE pCur = pVM->pgm.s.pRamRangesR3; pCur->pNextR3; pCur = pCur->pNextR3)
1862	pCur->pNextRC = MMHyperR3ToRC(pVM, pCur->pNextR3);
1863	}
1864
1865	/*
1866	* Update the two page directories with all page table mappings.
1867	* (One or more of them have changed, that's why we're here.)
1868	*/
1869	pVM->pgm.s.pMappingsRC = MMHyperR3ToRC(pVM, pVM->pgm.s.pMappingsR3);
1870	for (PPGMMAPPING pCur = pVM->pgm.s.pMappingsR3; pCur->pNextR3; pCur = pCur->pNextR3)
1871	pCur->pNextRC = MMHyperR3ToRC(pVM, pCur->pNextR3);
1872
1873	/* Relocate GC addresses of Page Tables. */
1874	for (PPGMMAPPING pCur = pVM->pgm.s.pMappingsR3; pCur; pCur = pCur->pNextR3)
1875	{
1876	for (RTHCUINT i = 0; i < pCur->cPTs; i++)
1877	{
1878	pCur->aPTs[i].pPTRC = MMHyperR3ToRC(pVM, pCur->aPTs[i].pPTR3);
1879	pCur->aPTs[i].paPaePTsRC = MMHyperR3ToRC(pVM, pCur->aPTs[i].paPaePTsR3);
1880	}
1881	}
1882
1883	/*
1884	* Dynamic page mapping area.
1885	*/
1886	pVM->pgm.s.paDynPageMap32BitPTEsGC += offDelta;
1887	pVM->pgm.s.paDynPageMapPaePTEsGC += offDelta;
1888	pVM->pgm.s.pbDynPageMapBaseGC += offDelta;
1889
1890	/*
1891	* The Zero page.
1892	*/
1893	pVM->pgm.s.pvZeroPgR0 = MMHyperR3ToR0(pVM, pVM->pgm.s.pvZeroPgR3);
1894	AssertRelease(pVM->pgm.s.pvZeroPgR0);
1895
1896	/*
1897	* Physical and virtual handlers.
1898	*/
1899	RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysHandlers, true, pgmR3RelocatePhysHandler, &offDelta);
1900	RTAvlroGCPtrDoWithAll(&pVM->pgm.s.pTreesR3->VirtHandlers, true, pgmR3RelocateVirtHandler, &offDelta);
1901	RTAvlroGCPtrDoWithAll(&pVM->pgm.s.pTreesR3->HyperVirtHandlers, true, pgmR3RelocateHyperVirtHandler, &offDelta);
1902
1903	/*
1904	* The page pool.
1905	*/
1906	pgmR3PoolRelocate(pVM);
1907	}
1908
1909
1910	/**
1911	* Callback function for relocating a physical access handler.
1912	*
1913	* @returns 0 (continue enum)
1914	* @param pNode Pointer to a PGMPHYSHANDLER node.
1915	* @param pvUser Pointer to the offDelta. This is a pointer to the delta since we're
1916	* not certain the delta will fit in a void pointer for all possible configs.
1917	*/
1918	static DECLCALLBACK(int) pgmR3RelocatePhysHandler(PAVLROGCPHYSNODECORE pNode, void *pvUser)
1919	{
1920	PPGMPHYSHANDLER pHandler = (PPGMPHYSHANDLER)pNode;
1921	RTGCINTPTR offDelta = *(PRTGCINTPTR)pvUser;
1922	if (pHandler->pfnHandlerRC)
1923	pHandler->pfnHandlerRC += offDelta;
1924	if (pHandler->pvUserRC >= 0x10000)
1925	pHandler->pvUserRC += offDelta;
1926	return 0;
1927	}
1928
1929
1930	/**
1931	* Callback function for relocating a virtual access handler.
1932	*
1933	* @returns 0 (continue enum)
1934	* @param pNode Pointer to a PGMVIRTHANDLER node.
1935	* @param pvUser Pointer to the offDelta. This is a pointer to the delta since we're
1936	* not certain the delta will fit in a void pointer for all possible configs.
1937	*/
1938	static DECLCALLBACK(int) pgmR3RelocateVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser)
1939	{
1940	PPGMVIRTHANDLER pHandler = (PPGMVIRTHANDLER)pNode;
1941	RTGCINTPTR offDelta = *(PRTGCINTPTR)pvUser;
1942	Assert( pHandler->enmType == PGMVIRTHANDLERTYPE_ALL
1943	\|\| pHandler->enmType == PGMVIRTHANDLERTYPE_WRITE);
1944	Assert(pHandler->pfnHandlerRC);
1945	pHandler->pfnHandlerRC += offDelta;
1946	return 0;
1947	}
1948
1949
1950	/**
1951	* Callback function for relocating a virtual access handler for the hypervisor mapping.
1952	*
1953	* @returns 0 (continue enum)
1954	* @param pNode Pointer to a PGMVIRTHANDLER node.
1955	* @param pvUser Pointer to the offDelta. This is a pointer to the delta since we're
1956	* not certain the delta will fit in a void pointer for all possible configs.
1957	*/
1958	static DECLCALLBACK(int) pgmR3RelocateHyperVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser)
1959	{
1960	PPGMVIRTHANDLER pHandler = (PPGMVIRTHANDLER)pNode;
1961	RTGCINTPTR offDelta = *(PRTGCINTPTR)pvUser;
1962	Assert(pHandler->enmType == PGMVIRTHANDLERTYPE_HYPERVISOR);
1963	Assert(pHandler->pfnHandlerRC);
1964	pHandler->pfnHandlerRC += offDelta;
1965	return 0;
1966	}
1967
1968
1969	/**
1970	* The VM is being reset.
1971	*
1972	* For the PGM component this means that any PD write monitors
1973	* needs to be removed.
1974	*
1975	* @param pVM VM handle.
1976	*/
1977	VMMR3DECL(void) PGMR3Reset(PVM pVM)
1978	{
1979	LogFlow(("PGMR3Reset:\n"));
1980	VM_ASSERT_EMT(pVM);
1981
1982	pgmLock(pVM);
1983
1984	/*
1985	* Unfix any fixed mappings and disable CR3 monitoring.
1986	*/
1987	pVM->pgm.s.fMappingsFixed = false;
1988	pVM->pgm.s.GCPtrMappingFixed = 0;
1989	pVM->pgm.s.cbMappingFixed = 0;
1990
1991	/* Exit the guest paging mode before the pgm pool gets reset.
1992	* Important to clean up the amd64 case.
1993	*/
1994	int rc = PGM_GST_PFN(Exit, pVM)(pVM);
1995	AssertRC(rc);
1996	#ifdef DEBUG
1997	DBGFR3InfoLog(pVM, "mappings", NULL);
1998	DBGFR3InfoLog(pVM, "handlers", "all nostat");
1999	#endif
2000
2001	/*
2002	* Reset the shadow page pool.
2003	*/
2004	pgmR3PoolReset(pVM);
2005
2006	/*
2007	* Re-init other members.
2008	*/
2009	pVM->pgm.s.fA20Enabled = true;
2010
2011	/*
2012	* Clear the FFs PGM owns.
2013	*/
2014	VM_FF_CLEAR(pVM, VM_FF_PGM_SYNC_CR3);
2015	VM_FF_CLEAR(pVM, VM_FF_PGM_SYNC_CR3_NON_GLOBAL);
2016
2017	/*
2018	* Reset (zero) RAM pages.
2019	*/
2020	rc = pgmR3PhysRamReset(pVM);
2021	if (RT_SUCCESS(rc))
2022	{
2023	#ifdef VBOX_WITH_NEW_PHYS_CODE
2024	/*
2025	* Reset (zero) shadow ROM pages.
2026	*/
2027	rc = pgmR3PhysRomReset(pVM);
2028	#endif
2029	if (RT_SUCCESS(rc))
2030	{
2031	/*
2032	* Switch mode back to real mode.
2033	*/
2034	rc = PGMR3ChangeMode(pVM, PGMMODE_REAL);
2035	STAM_REL_COUNTER_RESET(&pVM->pgm.s.cGuestModeChanges);
2036	}
2037	}
2038
2039	pgmUnlock(pVM);
2040	//return rc;
2041	AssertReleaseRC(rc);
2042	}
2043
2044
2045	#ifdef VBOX_STRICT
2046	/**
2047	* VM state change callback for clearing fNoMorePhysWrites after
2048	* a snapshot has been created.
2049	*/
2050	static DECLCALLBACK(void) pgmR3ResetNoMorePhysWritesFlag(PVM pVM, VMSTATE enmState, VMSTATE enmOldState, void *pvUser)
2051	{
2052	if (enmState == VMSTATE_RUNNING)
2053	pVM->pgm.s.fNoMorePhysWrites = false;
2054	}
2055	#endif
2056
2057
2058	/**
2059	* Terminates the PGM.
2060	*
2061	* @returns VBox status code.
2062	* @param pVM Pointer to VM structure.
2063	*/
2064	VMMR3DECL(int) PGMR3Term(PVM pVM)
2065	{
2066	return PDMR3CritSectDelete(&pVM->pgm.s.CritSect);
2067	}
2068
2069
2070	/**
2071	* Execute state save operation.
2072	*
2073	* @returns VBox status code.
2074	* @param pVM VM Handle.
2075	* @param pSSM SSM operation handle.
2076	*/
2077	static DECLCALLBACK(int) pgmR3Save(PVM pVM, PSSMHANDLE pSSM)
2078	{
2079	PPGM pPGM = &pVM->pgm.s;
2080
2081	/* No more writes to physical memory after this point! */
2082	pVM->pgm.s.fNoMorePhysWrites = true;
2083
2084	/*
2085	* Save basic data (required / unaffected by relocation).
2086	*/
2087	#if 1
2088	SSMR3PutBool(pSSM, pPGM->fMappingsFixed);
2089	#else
2090	SSMR3PutUInt(pSSM, pPGM->fMappingsFixed);
2091	#endif
2092	SSMR3PutGCPtr(pSSM, pPGM->GCPtrMappingFixed);
2093	SSMR3PutU32(pSSM, pPGM->cbMappingFixed);
2094	SSMR3PutUInt(pSSM, pPGM->cbRamSize);
2095	SSMR3PutGCPhys(pSSM, pPGM->GCPhysA20Mask);
2096	SSMR3PutUInt(pSSM, pPGM->fA20Enabled);
2097	SSMR3PutUInt(pSSM, pPGM->fSyncFlags);
2098	SSMR3PutUInt(pSSM, pPGM->enmGuestMode);
2099	SSMR3PutU32(pSSM, ~0); /* Separator. */
2100
2101	/*
2102	* The guest mappings.
2103	*/
2104	uint32_t i = 0;
2105	for (PPGMMAPPING pMapping = pPGM->pMappingsR3; pMapping; pMapping = pMapping->pNextR3, i++)
2106	{
2107	SSMR3PutU32(pSSM, i);
2108	SSMR3PutStrZ(pSSM, pMapping->pszDesc); /* This is the best unique id we have... */
2109	SSMR3PutGCPtr(pSSM, pMapping->GCPtr);
2110	SSMR3PutGCUIntPtr(pSSM, pMapping->cPTs);
2111	/* flags are done by the mapping owners! */
2112	}
2113	SSMR3PutU32(pSSM, ~0); /* terminator. */
2114
2115	/*
2116	* Ram range flags and bits.
2117	*/
2118	i = 0;
2119	for (PPGMRAMRANGE pRam = pPGM->pRamRangesR3; pRam; pRam = pRam->pNextR3, i++)
2120	{
2121	/** @todo MMIO ranges may move (PCI reconfig), we currently assume they don't. */
2122
2123	SSMR3PutU32(pSSM, i);
2124	SSMR3PutGCPhys(pSSM, pRam->GCPhys);
2125	SSMR3PutGCPhys(pSSM, pRam->GCPhysLast);
2126	SSMR3PutGCPhys(pSSM, pRam->cb);
2127	SSMR3PutU8(pSSM, !!pRam->pvR3); /* boolean indicating memory or not. */
2128
2129	/* Flags. */
2130	const unsigned cPages = pRam->cb >> PAGE_SHIFT;
2131	for (unsigned iPage = 0; iPage < cPages; iPage++)
2132	SSMR3PutU16(pSSM, (uint16_t)(pRam->aPages[iPage].HCPhys & ~X86_PTE_PAE_PG_MASK)); /** @todo PAGE FLAGS */
2133
2134	/* any memory associated with the range. */
2135	if (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)
2136	{
2137	for (unsigned iChunk = 0; iChunk < (pRam->cb >> PGM_DYNAMIC_CHUNK_SHIFT); iChunk++)
2138	{
2139	if (pRam->paChunkR3Ptrs[iChunk])
2140	{
2141	SSMR3PutU8(pSSM, 1); /* chunk present */
2142	SSMR3PutMem(pSSM, (void *)pRam->paChunkR3Ptrs[iChunk], PGM_DYNAMIC_CHUNK_SIZE);
2143	}
2144	else
2145	SSMR3PutU8(pSSM, 0); /* no chunk present */
2146	}
2147	}
2148	else if (pRam->pvR3)
2149	{
2150	int rc = SSMR3PutMem(pSSM, pRam->pvR3, pRam->cb);
2151	if (VBOX_FAILURE(rc))
2152	{
2153	Log(("pgmR3Save: SSMR3PutMem(, %p, %#x) -> %Vrc\n", pRam->pvR3, pRam->cb, rc));
2154	return rc;
2155	}
2156	}
2157	}
2158	return SSMR3PutU32(pSSM, ~0); /* terminator. */
2159	}
2160
2161
2162	/**
2163	* Execute state load operation.
2164	*
2165	* @returns VBox status code.
2166	* @param pVM VM Handle.
2167	* @param pSSM SSM operation handle.
2168	* @param u32Version Data layout version.
2169	*/
2170	static DECLCALLBACK(int) pgmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version)
2171	{
2172	/*
2173	* Validate version.
2174	*/
2175	if (u32Version != PGM_SAVED_STATE_VERSION)
2176	{
2177	AssertMsgFailed(("pgmR3Load: Invalid version u32Version=%d (current %d)!\n", u32Version, PGM_SAVED_STATE_VERSION));
2178	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
2179	}
2180
2181	/*
2182	* Call the reset function to make sure all the memory is cleared.
2183	*/
2184	PGMR3Reset(pVM);
2185
2186	/*
2187	* Load basic data (required / unaffected by relocation).
2188	*/
2189	PPGM pPGM = &pVM->pgm.s;
2190	#if 1
2191	SSMR3GetBool(pSSM, &pPGM->fMappingsFixed);
2192	#else
2193	uint32_t u;
2194	SSMR3GetU32(pSSM, &u);
2195	pPGM->fMappingsFixed = u;
2196	#endif
2197	SSMR3GetGCPtr(pSSM, &pPGM->GCPtrMappingFixed);
2198	SSMR3GetU32(pSSM, &pPGM->cbMappingFixed);
2199
2200	RTUINT cbRamSize;
2201	int rc = SSMR3GetU32(pSSM, &cbRamSize);
2202	if (VBOX_FAILURE(rc))
2203	return rc;
2204	if (cbRamSize != pPGM->cbRamSize)
2205	return VERR_SSM_LOAD_MEMORY_SIZE_MISMATCH;
2206	SSMR3GetGCPhys(pSSM, &pPGM->GCPhysA20Mask);
2207	SSMR3GetUInt(pSSM, &pPGM->fA20Enabled);
2208	SSMR3GetUInt(pSSM, &pPGM->fSyncFlags);
2209	RTUINT uGuestMode;
2210	SSMR3GetUInt(pSSM, &uGuestMode);
2211	pPGM->enmGuestMode = (PGMMODE)uGuestMode;
2212
2213	/* check separator. */
2214	uint32_t u32Sep;
2215	SSMR3GetU32(pSSM, &u32Sep);
2216	if (VBOX_FAILURE(rc))
2217	return rc;
2218	if (u32Sep != (uint32_t)~0)
2219	{
2220	AssertMsgFailed(("u32Sep=%#x (first)\n", u32Sep));
2221	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2222	}
2223
2224	/*
2225	* The guest mappings.
2226	*/
2227	uint32_t i = 0;
2228	for (;; i++)
2229	{
2230	/* Check the seqence number / separator. */
2231	rc = SSMR3GetU32(pSSM, &u32Sep);
2232	if (VBOX_FAILURE(rc))
2233	return rc;
2234	if (u32Sep == ~0U)
2235	break;
2236	if (u32Sep != i)
2237	{
2238	AssertMsgFailed(("u32Sep=%#x (last)\n", u32Sep));
2239	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2240	}
2241
2242	/* get the mapping details. */
2243	char szDesc[256];
2244	szDesc[0] = '\0';
2245	rc = SSMR3GetStrZ(pSSM, szDesc, sizeof(szDesc));
2246	if (VBOX_FAILURE(rc))
2247	return rc;
2248	RTGCPTR GCPtr;
2249	SSMR3GetGCPtr(pSSM, &GCPtr);
2250	RTGCUINTPTR cPTs;
2251	rc = SSMR3GetGCUIntPtr(pSSM, &cPTs);
2252	if (VBOX_FAILURE(rc))
2253	return rc;
2254
2255	/* find matching range. */
2256	PPGMMAPPING pMapping;
2257	for (pMapping = pPGM->pMappingsR3; pMapping; pMapping = pMapping->pNextR3)
2258	if ( pMapping->cPTs == cPTs
2259	&& !strcmp(pMapping->pszDesc, szDesc))
2260	break;
2261	if (!pMapping)
2262	{
2263	LogRel(("Couldn't find mapping: cPTs=%#x szDesc=%s (GCPtr=%VGv)\n",
2264	cPTs, szDesc, GCPtr));
2265	AssertFailed();
2266	return VERR_SSM_LOAD_CONFIG_MISMATCH;
2267	}
2268
2269	/* relocate it. */
2270	if (pMapping->GCPtr != GCPtr)
2271	{
2272	AssertMsg((GCPtr >> X86_PD_SHIFT << X86_PD_SHIFT) == GCPtr, ("GCPtr=%VGv\n", GCPtr));
2273	#if HC_ARCH_BITS == 64
2274	LogRel(("Mapping: %VGv -> %VGv %s\n", pMapping->GCPtr, GCPtr, pMapping->pszDesc));
2275	#endif
2276	pgmR3MapRelocate(pVM, pMapping, pMapping->GCPtr, GCPtr);
2277	}
2278	else
2279	Log(("pgmR3Load: '%s' needed no relocation (%VGv)\n", szDesc, GCPtr));
2280	}
2281
2282	/*
2283	* Ram range flags and bits.
2284	*/
2285	i = 0;
2286	for (PPGMRAMRANGE pRam = pPGM->pRamRangesR3; pRam; pRam = pRam->pNextR3, i++)
2287	{
2288	/** @todo MMIO ranges may move (PCI reconfig), we currently assume they don't. */
2289	/* Check the seqence number / separator. */
2290	rc = SSMR3GetU32(pSSM, &u32Sep);
2291	if (VBOX_FAILURE(rc))
2292	return rc;
2293	if (u32Sep == ~0U)
2294	break;
2295	if (u32Sep != i)
2296	{
2297	AssertMsgFailed(("u32Sep=%#x (last)\n", u32Sep));
2298	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2299	}
2300
2301	/* Get the range details. */
2302	RTGCPHYS GCPhys;
2303	SSMR3GetGCPhys(pSSM, &GCPhys);
2304	RTGCPHYS GCPhysLast;
2305	SSMR3GetGCPhys(pSSM, &GCPhysLast);
2306	RTGCPHYS cb;
2307	SSMR3GetGCPhys(pSSM, &cb);
2308	uint8_t fHaveBits;
2309	rc = SSMR3GetU8(pSSM, &fHaveBits);
2310	if (VBOX_FAILURE(rc))
2311	return rc;
2312	if (fHaveBits & ~1)
2313	{
2314	AssertMsgFailed(("u32Sep=%#x (last)\n", u32Sep));
2315	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2316	}
2317
2318	/* Match it up with the current range. */
2319	if ( GCPhys != pRam->GCPhys
2320	\|\| GCPhysLast != pRam->GCPhysLast
2321	\|\| cb != pRam->cb
2322	\|\| fHaveBits != !!pRam->pvR3)
2323	{
2324	LogRel(("Ram range: %RGp-%RGp %RGp bytes %s\n"
2325	"State : %RGp-%RGp %RGp bytes %s\n",
2326	pRam->GCPhys, pRam->GCPhysLast, pRam->cb, pRam->pvR3 ? "bits" : "nobits",
2327	GCPhys, GCPhysLast, cb, fHaveBits ? "bits" : "nobits"));
2328	/*
2329	* If we're loading a state for debugging purpose, don't make a fuss if
2330	* the MMIO[2] and ROM stuff isn't 100% right, just skip the mismatches.
2331	*/
2332	if ( SSMR3HandleGetAfter(pSSM) != SSMAFTER_DEBUG_IT
2333	\|\| GCPhys < 8 * _1M)
2334	AssertFailedReturn(VERR_SSM_LOAD_CONFIG_MISMATCH);
2335
2336	RTGCPHYS cPages = ((GCPhysLast - GCPhys) + 1) >> PAGE_SHIFT;
2337	while (cPages-- > 0)
2338	{
2339	uint16_t u16Ignore;
2340	SSMR3GetU16(pSSM, &u16Ignore);
2341	}
2342	continue;
2343	}
2344
2345	/* Flags. */
2346	const unsigned cPages = pRam->cb >> PAGE_SHIFT;
2347	for (unsigned iPage = 0; iPage < cPages; iPage++)
2348	{
2349	uint16_t u16 = 0;
2350	SSMR3GetU16(pSSM, &u16);
2351	u16 &= PAGE_OFFSET_MASK & ~( RT_BIT(4) \| RT_BIT(5) \| RT_BIT(6)
2352	\| RT_BIT(7) \| RT_BIT(8) \| RT_BIT(9) \| RT_BIT(10) );
2353	// &= MM_RAM_FLAGS_DYNAMIC_ALLOC \| MM_RAM_FLAGS_RESERVED \| MM_RAM_FLAGS_ROM \| MM_RAM_FLAGS_MMIO \| MM_RAM_FLAGS_MMIO2
2354	pRam->aPages[iPage].HCPhys = PGM_PAGE_GET_HCPHYS(&pRam->aPages[iPage]) \| (RTHCPHYS)u16; /** @todo PAGE FLAGS */
2355	}
2356
2357	/* any memory associated with the range. */
2358	if (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)
2359	{
2360	for (unsigned iChunk = 0; iChunk < (pRam->cb >> PGM_DYNAMIC_CHUNK_SHIFT); iChunk++)
2361	{
2362	uint8_t fValidChunk;
2363
2364	rc = SSMR3GetU8(pSSM, &fValidChunk);
2365	if (VBOX_FAILURE(rc))
2366	return rc;
2367	if (fValidChunk > 1)
2368	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2369
2370	if (fValidChunk)
2371	{
2372	if (!pRam->paChunkR3Ptrs[iChunk])
2373	{
2374	rc = pgmr3PhysGrowRange(pVM, pRam->GCPhys + iChunk * PGM_DYNAMIC_CHUNK_SIZE);
2375	if (VBOX_FAILURE(rc))
2376	return rc;
2377	}
2378	Assert(pRam->paChunkR3Ptrs[iChunk]);
2379
2380	SSMR3GetMem(pSSM, (void *)pRam->paChunkR3Ptrs[iChunk], PGM_DYNAMIC_CHUNK_SIZE);
2381	}
2382	/* else nothing to do */
2383	}
2384	}
2385	else if (pRam->pvR3)
2386	{
2387	int rc = SSMR3GetMem(pSSM, pRam->pvR3, pRam->cb);
2388	if (VBOX_FAILURE(rc))
2389	{
2390	Log(("pgmR3Save: SSMR3GetMem(, %p, %#x) -> %Vrc\n", pRam->pvR3, pRam->cb, rc));
2391	return rc;
2392	}
2393	}
2394	}
2395
2396	/*
2397	* We require a full resync now.
2398	*/
2399	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3_NON_GLOBAL);
2400	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
2401	pPGM->fSyncFlags \|= PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL;
2402	pPGM->fPhysCacheFlushPending = true;
2403	pgmR3HandlerPhysicalUpdateAll(pVM);
2404
2405	/*
2406	* Change the paging mode.
2407	*/
2408	rc = PGMR3ChangeMode(pVM, pPGM->enmGuestMode);
2409
2410	/* Restore pVM->pgm.s.GCPhysCR3. */
2411	Assert(pVM->pgm.s.GCPhysCR3 == NIL_RTGCPHYS);
2412	RTGCPHYS GCPhysCR3 = CPUMGetGuestCR3(pVM);
2413	if ( pVM->pgm.s.enmGuestMode == PGMMODE_PAE
2414	\|\| pVM->pgm.s.enmGuestMode == PGMMODE_PAE_NX
2415	\|\| pVM->pgm.s.enmGuestMode == PGMMODE_AMD64
2416	\|\| pVM->pgm.s.enmGuestMode == PGMMODE_AMD64_NX)
2417	GCPhysCR3 = (GCPhysCR3 & X86_CR3_PAE_PAGE_MASK);
2418	else
2419	GCPhysCR3 = (GCPhysCR3 & X86_CR3_PAGE_MASK);
2420	pVM->pgm.s.GCPhysCR3 = GCPhysCR3;
2421
2422	return rc;
2423	}
2424
2425
2426	/**
2427	* Show paging mode.
2428	*
2429	* @param pVM VM Handle.
2430	* @param pHlp The info helpers.
2431	* @param pszArgs "all" (default), "guest", "shadow" or "host".
2432	*/
2433	static DECLCALLBACK(void) pgmR3InfoMode(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2434	{
2435	/* digest argument. */
2436	bool fGuest, fShadow, fHost;
2437	if (pszArgs)
2438	pszArgs = RTStrStripL(pszArgs);
2439	if (!pszArgs \|\| !*pszArgs \|\| strstr(pszArgs, "all"))
2440	fShadow = fHost = fGuest = true;
2441	else
2442	{
2443	fShadow = fHost = fGuest = false;
2444	if (strstr(pszArgs, "guest"))
2445	fGuest = true;
2446	if (strstr(pszArgs, "shadow"))
2447	fShadow = true;
2448	if (strstr(pszArgs, "host"))
2449	fHost = true;
2450	}
2451
2452	/* print info. */
2453	if (fGuest)
2454	pHlp->pfnPrintf(pHlp, "Guest paging mode: %s, changed %RU64 times, A20 %s\n",
2455	PGMGetModeName(pVM->pgm.s.enmGuestMode), pVM->pgm.s.cGuestModeChanges.c,
2456	pVM->pgm.s.fA20Enabled ? "enabled" : "disabled");
2457	if (fShadow)
2458	pHlp->pfnPrintf(pHlp, "Shadow paging mode: %s\n", PGMGetModeName(pVM->pgm.s.enmShadowMode));
2459	if (fHost)
2460	{
2461	const char *psz;
2462	switch (pVM->pgm.s.enmHostMode)
2463	{
2464	case SUPPAGINGMODE_INVALID: psz = "invalid"; break;
2465	case SUPPAGINGMODE_32_BIT: psz = "32-bit"; break;
2466	case SUPPAGINGMODE_32_BIT_GLOBAL: psz = "32-bit+G"; break;
2467	case SUPPAGINGMODE_PAE: psz = "PAE"; break;
2468	case SUPPAGINGMODE_PAE_GLOBAL: psz = "PAE+G"; break;
2469	case SUPPAGINGMODE_PAE_NX: psz = "PAE+NX"; break;
2470	case SUPPAGINGMODE_PAE_GLOBAL_NX: psz = "PAE+G+NX"; break;
2471	case SUPPAGINGMODE_AMD64: psz = "AMD64"; break;
2472	case SUPPAGINGMODE_AMD64_GLOBAL: psz = "AMD64+G"; break;
2473	case SUPPAGINGMODE_AMD64_NX: psz = "AMD64+NX"; break;
2474	case SUPPAGINGMODE_AMD64_GLOBAL_NX: psz = "AMD64+G+NX"; break;
2475	default: psz = "unknown"; break;
2476	}
2477	pHlp->pfnPrintf(pHlp, "Host paging mode: %s\n", psz);
2478	}
2479	}
2480
2481
2482	/**
2483	* Dump registered MMIO ranges to the log.
2484	*
2485	* @param pVM VM Handle.
2486	* @param pHlp The info helpers.
2487	* @param pszArgs Arguments, ignored.
2488	*/
2489	static DECLCALLBACK(void) pgmR3PhysInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2490	{
2491	NOREF(pszArgs);
2492	pHlp->pfnPrintf(pHlp,
2493	"RAM ranges (pVM=%p)\n"
2494	"%.s %.s\n",
2495	pVM,
2496	sizeof(RTGCPHYS) * 4 + 1, "GC Phys Range ",
2497	sizeof(RTHCPTR) * 2, "pvHC ");
2498
2499	for (PPGMRAMRANGE pCur = pVM->pgm.s.pRamRangesR3; pCur; pCur = pCur->pNextR3)
2500	pHlp->pfnPrintf(pHlp,
2501	"%RGp-%RGp %RHv %s\n",
2502	pCur->GCPhys,
2503	pCur->GCPhysLast,
2504	pCur->pvR3,
2505	pCur->pszDesc);
2506	}
2507
2508	/**
2509	* Dump the page directory to the log.
2510	*
2511	* @param pVM VM Handle.
2512	* @param pHlp The info helpers.
2513	* @param pszArgs Arguments, ignored.
2514	*/
2515	static DECLCALLBACK(void) pgmR3InfoCr3(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2516	{
2517	/** @todo fix this! Convert the PGMR3DumpHierarchyHC functions to do guest stuff. */
2518	/* Big pages supported? */
2519	const bool fPSE = !!(CPUMGetGuestCR4(pVM) & X86_CR4_PSE);
2520
2521	/* Global pages supported? */
2522	const bool fPGE = !!(CPUMGetGuestCR4(pVM) & X86_CR4_PGE);
2523
2524	NOREF(pszArgs);
2525
2526	/*
2527	* Get page directory addresses.
2528	*/
2529	PX86PD pPDSrc = pVM->pgm.s.pGuestPDHC;
2530	Assert(pPDSrc);
2531	Assert(PGMPhysGCPhys2HCPtrAssert(pVM, (RTGCPHYS)(CPUMGetGuestCR3(pVM) & X86_CR3_PAGE_MASK), sizeof(*pPDSrc)) == pPDSrc);
2532
2533	/*
2534	* Iterate the page directory.
2535	*/
2536	for (unsigned iPD = 0; iPD < RT_ELEMENTS(pPDSrc->a); iPD++)
2537	{
2538	X86PDE PdeSrc = pPDSrc->a[iPD];
2539	if (PdeSrc.n.u1Present)
2540	{
2541	if (PdeSrc.b.u1Size && fPSE)
2542	{
2543	pHlp->pfnPrintf(pHlp,
2544	"%04X - %VGp P=%d U=%d RW=%d G=%d - BIG\n",
2545	iPD,
2546	pgmGstGet4MBPhysPage(&pVM->pgm.s, PdeSrc),
2547	PdeSrc.b.u1Present, PdeSrc.b.u1User, PdeSrc.b.u1Write, PdeSrc.b.u1Global && fPGE);
2548	}
2549	else
2550	{
2551	pHlp->pfnPrintf(pHlp,
2552	"%04X - %VGp P=%d U=%d RW=%d [G=%d]\n",
2553	iPD,
2554	PdeSrc.u & X86_PDE_PG_MASK,
2555	PdeSrc.n.u1Present, PdeSrc.n.u1User, PdeSrc.n.u1Write, PdeSrc.b.u1Global && fPGE);
2556	}
2557	}
2558	}
2559	}
2560
2561
2562	/**
2563	* Serivce a VMMCALLHOST_PGM_LOCK call.
2564	*
2565	* @returns VBox status code.
2566	* @param pVM The VM handle.
2567	*/
2568	VMMR3DECL(int) PGMR3LockCall(PVM pVM)
2569	{
2570	int rc = PDMR3CritSectEnterEx(&pVM->pgm.s.CritSect, true /* fHostCall */);
2571	AssertRC(rc);
2572	return rc;
2573	}
2574
2575
2576	/**
2577	* Converts a PGMMODE value to a PGM_TYPE_* \#define.
2578	*
2579	* @returns PGM_TYPE_*.
2580	* @param pgmMode The mode value to convert.
2581	*/
2582	DECLINLINE(unsigned) pgmModeToType(PGMMODE pgmMode)
2583	{
2584	switch (pgmMode)
2585	{
2586	case PGMMODE_REAL: return PGM_TYPE_REAL;
2587	case PGMMODE_PROTECTED: return PGM_TYPE_PROT;
2588	case PGMMODE_32_BIT: return PGM_TYPE_32BIT;
2589	case PGMMODE_PAE:
2590	case PGMMODE_PAE_NX: return PGM_TYPE_PAE;
2591	case PGMMODE_AMD64:
2592	case PGMMODE_AMD64_NX: return PGM_TYPE_AMD64;
2593	case PGMMODE_NESTED: return PGM_TYPE_NESTED;
2594	case PGMMODE_EPT: return PGM_TYPE_EPT;
2595	default:
2596	AssertFatalMsgFailed(("pgmMode=%d\n", pgmMode));
2597	}
2598	}
2599
2600
2601	/**
2602	* Gets the index into the paging mode data array of a SHW+GST mode.
2603	*
2604	* @returns PGM::paPagingData index.
2605	* @param uShwType The shadow paging mode type.
2606	* @param uGstType The guest paging mode type.
2607	*/
2608	DECLINLINE(unsigned) pgmModeDataIndex(unsigned uShwType, unsigned uGstType)
2609	{
2610	Assert(uShwType >= PGM_TYPE_32BIT && uShwType <= PGM_TYPE_MAX);
2611	Assert(uGstType >= PGM_TYPE_REAL && uGstType <= PGM_TYPE_AMD64);
2612	return (uShwType - PGM_TYPE_32BIT) * (PGM_TYPE_AMD64 - PGM_TYPE_REAL + 1)
2613	+ (uGstType - PGM_TYPE_REAL);
2614	}
2615
2616
2617	/**
2618	* Gets the index into the paging mode data array of a SHW+GST mode.
2619	*
2620	* @returns PGM::paPagingData index.
2621	* @param enmShw The shadow paging mode.
2622	* @param enmGst The guest paging mode.
2623	*/
2624	DECLINLINE(unsigned) pgmModeDataIndexByMode(PGMMODE enmShw, PGMMODE enmGst)
2625	{
2626	Assert(enmShw >= PGMMODE_32_BIT && enmShw <= PGMMODE_MAX);
2627	Assert(enmGst > PGMMODE_INVALID && enmGst < PGMMODE_MAX);
2628	return pgmModeDataIndex(pgmModeToType(enmShw), pgmModeToType(enmGst));
2629	}
2630
2631
2632	/**
2633	* Calculates the max data index.
2634	* @returns The number of entries in the paging data array.
2635	*/
2636	DECLINLINE(unsigned) pgmModeDataMaxIndex(void)
2637	{
2638	return pgmModeDataIndex(PGM_TYPE_MAX, PGM_TYPE_AMD64) + 1;
2639	}
2640
2641
2642	/**
2643	* Initializes the paging mode data kept in PGM::paModeData.
2644	*
2645	* @param pVM The VM handle.
2646	* @param fResolveGCAndR0 Indicate whether or not GC and Ring-0 symbols can be resolved now.
2647	* This is used early in the init process to avoid trouble with PDM
2648	* not being initialized yet.
2649	*/
2650	static int pgmR3ModeDataInit(PVM pVM, bool fResolveGCAndR0)
2651	{
2652	PPGMMODEDATA pModeData;
2653	int rc;
2654
2655	/*
2656	* Allocate the array on the first call.
2657	*/
2658	if (!pVM->pgm.s.paModeData)
2659	{
2660	pVM->pgm.s.paModeData = (PPGMMODEDATA)MMR3HeapAllocZ(pVM, MM_TAG_PGM, sizeof(PGMMODEDATA) * pgmModeDataMaxIndex());
2661	AssertReturn(pVM->pgm.s.paModeData, VERR_NO_MEMORY);
2662	}
2663
2664	/*
2665	* Initialize the array entries.
2666	*/
2667	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_32BIT, PGM_TYPE_REAL)];
2668	pModeData->uShwType = PGM_TYPE_32BIT;
2669	pModeData->uGstType = PGM_TYPE_REAL;
2670	rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2671	rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2672	rc = PGM_BTH_NAME_32BIT_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2673
2674	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_32BIT, PGMMODE_PROTECTED)];
2675	pModeData->uShwType = PGM_TYPE_32BIT;
2676	pModeData->uGstType = PGM_TYPE_PROT;
2677	rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2678	rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2679	rc = PGM_BTH_NAME_32BIT_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2680
2681	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_32BIT, PGM_TYPE_32BIT)];
2682	pModeData->uShwType = PGM_TYPE_32BIT;
2683	pModeData->uGstType = PGM_TYPE_32BIT;
2684	rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2685	rc = PGM_GST_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2686	rc = PGM_BTH_NAME_32BIT_32BIT(InitData)(pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2687
2688	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_REAL)];
2689	pModeData->uShwType = PGM_TYPE_PAE;
2690	pModeData->uGstType = PGM_TYPE_REAL;
2691	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2692	rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2693	rc = PGM_BTH_NAME_PAE_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2694
2695	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_PROT)];
2696	pModeData->uShwType = PGM_TYPE_PAE;
2697	pModeData->uGstType = PGM_TYPE_PROT;
2698	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2699	rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2700	rc = PGM_BTH_NAME_PAE_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2701
2702	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_32BIT)];
2703	pModeData->uShwType = PGM_TYPE_PAE;
2704	pModeData->uGstType = PGM_TYPE_32BIT;
2705	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2706	rc = PGM_GST_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2707	rc = PGM_BTH_NAME_PAE_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2708
2709	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_PAE)];
2710	pModeData->uShwType = PGM_TYPE_PAE;
2711	pModeData->uGstType = PGM_TYPE_PAE;
2712	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2713	rc = PGM_GST_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2714	rc = PGM_BTH_NAME_PAE_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2715
2716	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_AMD64, PGM_TYPE_AMD64)];
2717	pModeData->uShwType = PGM_TYPE_AMD64;
2718	pModeData->uGstType = PGM_TYPE_AMD64;
2719	rc = PGM_SHW_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2720	rc = PGM_GST_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2721	rc = PGM_BTH_NAME_AMD64_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2722
2723	/* The nested paging mode. */
2724	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_REAL)];
2725	pModeData->uShwType = PGM_TYPE_NESTED;
2726	pModeData->uGstType = PGM_TYPE_REAL;
2727	rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2728	rc = PGM_BTH_NAME_NESTED_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2729
2730	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGMMODE_PROTECTED)];
2731	pModeData->uShwType = PGM_TYPE_NESTED;
2732	pModeData->uGstType = PGM_TYPE_PROT;
2733	rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2734	rc = PGM_BTH_NAME_NESTED_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2735
2736	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_32BIT)];
2737	pModeData->uShwType = PGM_TYPE_NESTED;
2738	pModeData->uGstType = PGM_TYPE_32BIT;
2739	rc = PGM_GST_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2740	rc = PGM_BTH_NAME_NESTED_32BIT(InitData)(pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2741
2742	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_PAE)];
2743	pModeData->uShwType = PGM_TYPE_NESTED;
2744	pModeData->uGstType = PGM_TYPE_PAE;
2745	rc = PGM_GST_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2746	rc = PGM_BTH_NAME_NESTED_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2747
2748	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_AMD64)];
2749	pModeData->uShwType = PGM_TYPE_NESTED;
2750	pModeData->uGstType = PGM_TYPE_AMD64;
2751	rc = PGM_GST_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2752	rc = PGM_BTH_NAME_NESTED_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2753
2754	/* The shadow part of the nested callback mode depends on the host paging mode (AMD-V only). */
2755	switch(pVM->pgm.s.enmHostMode)
2756	{
2757	case SUPPAGINGMODE_32_BIT:
2758	case SUPPAGINGMODE_32_BIT_GLOBAL:
2759	for (unsigned i=PGM_TYPE_REAL;i<=PGM_TYPE_AMD64;i++)
2760	{
2761	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, i)];
2762	rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2763	}
2764	break;
2765
2766	case SUPPAGINGMODE_PAE:
2767	case SUPPAGINGMODE_PAE_NX:
2768	case SUPPAGINGMODE_PAE_GLOBAL:
2769	case SUPPAGINGMODE_PAE_GLOBAL_NX:
2770	for (unsigned i=PGM_TYPE_REAL;i<=PGM_TYPE_AMD64;i++)
2771	{
2772	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, i)];
2773	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2774	}
2775	break;
2776
2777	case SUPPAGINGMODE_AMD64:
2778	case SUPPAGINGMODE_AMD64_GLOBAL:
2779	case SUPPAGINGMODE_AMD64_NX:
2780	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
2781	for (unsigned i=PGM_TYPE_REAL;i<=PGM_TYPE_AMD64;i++)
2782	{
2783	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, i)];
2784	rc = PGM_SHW_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2785	}
2786	break;
2787	default:
2788	AssertFailed();
2789	break;
2790	}
2791
2792	/* Extended paging (EPT) / Intel VT-x */
2793	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_REAL)];
2794	pModeData->uShwType = PGM_TYPE_EPT;
2795	pModeData->uGstType = PGM_TYPE_REAL;
2796	rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2797	rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2798	rc = PGM_BTH_NAME_EPT_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2799
2800	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_PROT)];
2801	pModeData->uShwType = PGM_TYPE_EPT;
2802	pModeData->uGstType = PGM_TYPE_PROT;
2803	rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2804	rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2805	rc = PGM_BTH_NAME_EPT_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2806
2807	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_32BIT)];
2808	pModeData->uShwType = PGM_TYPE_EPT;
2809	pModeData->uGstType = PGM_TYPE_32BIT;
2810	rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2811	rc = PGM_GST_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2812	rc = PGM_BTH_NAME_EPT_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2813
2814	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_PAE)];
2815	pModeData->uShwType = PGM_TYPE_EPT;
2816	pModeData->uGstType = PGM_TYPE_PAE;
2817	rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2818	rc = PGM_GST_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2819	rc = PGM_BTH_NAME_EPT_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2820
2821	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_AMD64)];
2822	pModeData->uShwType = PGM_TYPE_EPT;
2823	pModeData->uGstType = PGM_TYPE_AMD64;
2824	rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2825	rc = PGM_GST_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2826	rc = PGM_BTH_NAME_EPT_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2827	return VINF_SUCCESS;
2828	}
2829
2830
2831	/**
2832	* Switch to different (or relocated in the relocate case) mode data.
2833	*
2834	* @param pVM The VM handle.
2835	* @param enmShw The the shadow paging mode.
2836	* @param enmGst The the guest paging mode.
2837	*/
2838	static void pgmR3ModeDataSwitch(PVM pVM, PGMMODE enmShw, PGMMODE enmGst)
2839	{
2840	PPGMMODEDATA pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndexByMode(enmShw, enmGst)];
2841
2842	Assert(pModeData->uGstType == pgmModeToType(enmGst));
2843	Assert(pModeData->uShwType == pgmModeToType(enmShw));
2844
2845	/* shadow */
2846	pVM->pgm.s.pfnR3ShwRelocate = pModeData->pfnR3ShwRelocate;
2847	pVM->pgm.s.pfnR3ShwExit = pModeData->pfnR3ShwExit;
2848	pVM->pgm.s.pfnR3ShwGetPage = pModeData->pfnR3ShwGetPage;
2849	Assert(pVM->pgm.s.pfnR3ShwGetPage);
2850	pVM->pgm.s.pfnR3ShwModifyPage = pModeData->pfnR3ShwModifyPage;
2851
2852	pVM->pgm.s.pfnRCShwGetPage = pModeData->pfnRCShwGetPage;
2853	pVM->pgm.s.pfnRCShwModifyPage = pModeData->pfnRCShwModifyPage;
2854
2855	pVM->pgm.s.pfnR0ShwGetPage = pModeData->pfnR0ShwGetPage;
2856	pVM->pgm.s.pfnR0ShwModifyPage = pModeData->pfnR0ShwModifyPage;
2857
2858
2859	/* guest */
2860	pVM->pgm.s.pfnR3GstRelocate = pModeData->pfnR3GstRelocate;
2861	pVM->pgm.s.pfnR3GstExit = pModeData->pfnR3GstExit;
2862	pVM->pgm.s.pfnR3GstGetPage = pModeData->pfnR3GstGetPage;
2863	Assert(pVM->pgm.s.pfnR3GstGetPage);
2864	pVM->pgm.s.pfnR3GstModifyPage = pModeData->pfnR3GstModifyPage;
2865	pVM->pgm.s.pfnR3GstGetPDE = pModeData->pfnR3GstGetPDE;
2866	pVM->pgm.s.pfnR3GstMonitorCR3 = pModeData->pfnR3GstMonitorCR3;
2867	pVM->pgm.s.pfnR3GstUnmonitorCR3 = pModeData->pfnR3GstUnmonitorCR3;
2868	pVM->pgm.s.pfnR3GstMapCR3 = pModeData->pfnR3GstMapCR3;
2869	pVM->pgm.s.pfnR3GstUnmapCR3 = pModeData->pfnR3GstUnmapCR3;
2870	pVM->pgm.s.pfnR3GstWriteHandlerCR3 = pModeData->pfnR3GstWriteHandlerCR3;
2871	pVM->pgm.s.pszR3GstWriteHandlerCR3 = pModeData->pszR3GstWriteHandlerCR3;
2872	pVM->pgm.s.pfnR3GstPAEWriteHandlerCR3 = pModeData->pfnR3GstPAEWriteHandlerCR3;
2873	pVM->pgm.s.pszR3GstPAEWriteHandlerCR3 = pModeData->pszR3GstPAEWriteHandlerCR3;
2874
2875	pVM->pgm.s.pfnRCGstGetPage = pModeData->pfnRCGstGetPage;
2876	pVM->pgm.s.pfnRCGstModifyPage = pModeData->pfnRCGstModifyPage;
2877	pVM->pgm.s.pfnRCGstGetPDE = pModeData->pfnRCGstGetPDE;
2878	pVM->pgm.s.pfnRCGstMonitorCR3 = pModeData->pfnRCGstMonitorCR3;
2879	pVM->pgm.s.pfnRCGstUnmonitorCR3 = pModeData->pfnRCGstUnmonitorCR3;
2880	pVM->pgm.s.pfnRCGstMapCR3 = pModeData->pfnRCGstMapCR3;
2881	pVM->pgm.s.pfnRCGstUnmapCR3 = pModeData->pfnRCGstUnmapCR3;
2882	pVM->pgm.s.pfnRCGstWriteHandlerCR3 = pModeData->pfnRCGstWriteHandlerCR3;
2883	pVM->pgm.s.pfnRCGstPAEWriteHandlerCR3 = pModeData->pfnRCGstPAEWriteHandlerCR3;
2884
2885	pVM->pgm.s.pfnR0GstGetPage = pModeData->pfnR0GstGetPage;
2886	pVM->pgm.s.pfnR0GstModifyPage = pModeData->pfnR0GstModifyPage;
2887	pVM->pgm.s.pfnR0GstGetPDE = pModeData->pfnR0GstGetPDE;
2888	pVM->pgm.s.pfnR0GstMonitorCR3 = pModeData->pfnR0GstMonitorCR3;
2889	pVM->pgm.s.pfnR0GstUnmonitorCR3 = pModeData->pfnR0GstUnmonitorCR3;
2890	pVM->pgm.s.pfnR0GstMapCR3 = pModeData->pfnR0GstMapCR3;
2891	pVM->pgm.s.pfnR0GstUnmapCR3 = pModeData->pfnR0GstUnmapCR3;
2892	pVM->pgm.s.pfnR0GstWriteHandlerCR3 = pModeData->pfnR0GstWriteHandlerCR3;
2893	pVM->pgm.s.pfnR0GstPAEWriteHandlerCR3 = pModeData->pfnR0GstPAEWriteHandlerCR3;
2894
2895
2896	/* both */
2897	pVM->pgm.s.pfnR3BthRelocate = pModeData->pfnR3BthRelocate;
2898	pVM->pgm.s.pfnR3BthInvalidatePage = pModeData->pfnR3BthInvalidatePage;
2899	pVM->pgm.s.pfnR3BthSyncCR3 = pModeData->pfnR3BthSyncCR3;
2900	Assert(pVM->pgm.s.pfnR3BthSyncCR3);
2901	pVM->pgm.s.pfnR3BthSyncPage = pModeData->pfnR3BthSyncPage;
2902	pVM->pgm.s.pfnR3BthPrefetchPage = pModeData->pfnR3BthPrefetchPage;
2903	pVM->pgm.s.pfnR3BthVerifyAccessSyncPage = pModeData->pfnR3BthVerifyAccessSyncPage;
2904	#ifdef VBOX_STRICT
2905	pVM->pgm.s.pfnR3BthAssertCR3 = pModeData->pfnR3BthAssertCR3;
2906	#endif
2907
2908	pVM->pgm.s.pfnRCBthTrap0eHandler = pModeData->pfnRCBthTrap0eHandler;
2909	pVM->pgm.s.pfnRCBthInvalidatePage = pModeData->pfnRCBthInvalidatePage;
2910	pVM->pgm.s.pfnRCBthSyncCR3 = pModeData->pfnRCBthSyncCR3;
2911	pVM->pgm.s.pfnRCBthSyncPage = pModeData->pfnRCBthSyncPage;
2912	pVM->pgm.s.pfnRCBthPrefetchPage = pModeData->pfnRCBthPrefetchPage;
2913	pVM->pgm.s.pfnRCBthVerifyAccessSyncPage = pModeData->pfnRCBthVerifyAccessSyncPage;
2914	#ifdef VBOX_STRICT
2915	pVM->pgm.s.pfnRCBthAssertCR3 = pModeData->pfnRCBthAssertCR3;
2916	#endif
2917
2918	pVM->pgm.s.pfnR0BthTrap0eHandler = pModeData->pfnR0BthTrap0eHandler;
2919	pVM->pgm.s.pfnR0BthInvalidatePage = pModeData->pfnR0BthInvalidatePage;
2920	pVM->pgm.s.pfnR0BthSyncCR3 = pModeData->pfnR0BthSyncCR3;
2921	pVM->pgm.s.pfnR0BthSyncPage = pModeData->pfnR0BthSyncPage;
2922	pVM->pgm.s.pfnR0BthPrefetchPage = pModeData->pfnR0BthPrefetchPage;
2923	pVM->pgm.s.pfnR0BthVerifyAccessSyncPage = pModeData->pfnR0BthVerifyAccessSyncPage;
2924	#ifdef VBOX_STRICT
2925	pVM->pgm.s.pfnR0BthAssertCR3 = pModeData->pfnR0BthAssertCR3;
2926	#endif
2927	}
2928
2929
2930	#ifdef DEBUG_bird
2931	#include <stdlib.h> /* getenv() remove me! */
2932	#endif
2933
2934	/**
2935	* Calculates the shadow paging mode.
2936	*
2937	* @returns The shadow paging mode.
2938	* @param pVM VM handle.
2939	* @param enmGuestMode The guest mode.
2940	* @param enmHostMode The host mode.
2941	* @param enmShadowMode The current shadow mode.
2942	* @param penmSwitcher Where to store the switcher to use.
2943	* VMMSWITCHER_INVALID means no change.
2944	*/
2945	static PGMMODE pgmR3CalcShadowMode(PVM pVM, PGMMODE enmGuestMode, SUPPAGINGMODE enmHostMode, PGMMODE enmShadowMode, VMMSWITCHER *penmSwitcher)
2946	{
2947	VMMSWITCHER enmSwitcher = VMMSWITCHER_INVALID;
2948	switch (enmGuestMode)
2949	{
2950	/*
2951	* When switching to real or protected mode we don't change
2952	* anything since it's likely that we'll switch back pretty soon.
2953	*
2954	* During pgmR3InitPaging we'll end up here with PGMMODE_INVALID
2955	* and is supposed to determine which shadow paging and switcher to
2956	* use during init.
2957	*/
2958	case PGMMODE_REAL:
2959	case PGMMODE_PROTECTED:
2960	if ( enmShadowMode != PGMMODE_INVALID
2961	&& !HWACCMIsEnabled(pVM) /* always switch in hwaccm mode! */)
2962	break; /* (no change) */
2963
2964	switch (enmHostMode)
2965	{
2966	case SUPPAGINGMODE_32_BIT:
2967	case SUPPAGINGMODE_32_BIT_GLOBAL:
2968	enmShadowMode = PGMMODE_32_BIT;
2969	enmSwitcher = VMMSWITCHER_32_TO_32;
2970	break;
2971
2972	case SUPPAGINGMODE_PAE:
2973	case SUPPAGINGMODE_PAE_NX:
2974	case SUPPAGINGMODE_PAE_GLOBAL:
2975	case SUPPAGINGMODE_PAE_GLOBAL_NX:
2976	enmShadowMode = PGMMODE_PAE;
2977	enmSwitcher = VMMSWITCHER_PAE_TO_PAE;
2978	#ifdef DEBUG_bird
2979	if (getenv("VBOX_32BIT"))
2980	{
2981	enmShadowMode = PGMMODE_32_BIT;
2982	enmSwitcher = VMMSWITCHER_PAE_TO_32;
2983	}
2984	#endif
2985	break;
2986
2987	case SUPPAGINGMODE_AMD64:
2988	case SUPPAGINGMODE_AMD64_GLOBAL:
2989	case SUPPAGINGMODE_AMD64_NX:
2990	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
2991	enmShadowMode = PGMMODE_PAE;
2992	enmSwitcher = VMMSWITCHER_AMD64_TO_PAE;
2993	break;
2994
2995	default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
2996	}
2997	break;
2998
2999	case PGMMODE_32_BIT:
3000	switch (enmHostMode)
3001	{
3002	case SUPPAGINGMODE_32_BIT:
3003	case SUPPAGINGMODE_32_BIT_GLOBAL:
3004	enmShadowMode = PGMMODE_32_BIT;
3005	enmSwitcher = VMMSWITCHER_32_TO_32;
3006	break;
3007
3008	case SUPPAGINGMODE_PAE:
3009	case SUPPAGINGMODE_PAE_NX:
3010	case SUPPAGINGMODE_PAE_GLOBAL:
3011	case SUPPAGINGMODE_PAE_GLOBAL_NX:
3012	enmShadowMode = PGMMODE_PAE;
3013	enmSwitcher = VMMSWITCHER_PAE_TO_PAE;
3014	#ifdef DEBUG_bird
3015	if (getenv("VBOX_32BIT"))
3016	{
3017	enmShadowMode = PGMMODE_32_BIT;
3018	enmSwitcher = VMMSWITCHER_PAE_TO_32;
3019	}
3020	#endif
3021	break;
3022
3023	case SUPPAGINGMODE_AMD64:
3024	case SUPPAGINGMODE_AMD64_GLOBAL:
3025	case SUPPAGINGMODE_AMD64_NX:
3026	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
3027	enmShadowMode = PGMMODE_PAE;
3028	enmSwitcher = VMMSWITCHER_AMD64_TO_PAE;
3029	break;
3030
3031	default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
3032	}
3033	break;
3034
3035	case PGMMODE_PAE:
3036	case PGMMODE_PAE_NX: /** @todo This might require more switchers and guest+both modes. */
3037	switch (enmHostMode)
3038	{
3039	case SUPPAGINGMODE_32_BIT:
3040	case SUPPAGINGMODE_32_BIT_GLOBAL:
3041	enmShadowMode = PGMMODE_PAE;
3042	enmSwitcher = VMMSWITCHER_32_TO_PAE;
3043	break;
3044
3045	case SUPPAGINGMODE_PAE:
3046	case SUPPAGINGMODE_PAE_NX:
3047	case SUPPAGINGMODE_PAE_GLOBAL:
3048	case SUPPAGINGMODE_PAE_GLOBAL_NX:
3049	enmShadowMode = PGMMODE_PAE;
3050	enmSwitcher = VMMSWITCHER_PAE_TO_PAE;
3051	break;
3052
3053	case SUPPAGINGMODE_AMD64:
3054	case SUPPAGINGMODE_AMD64_GLOBAL:
3055	case SUPPAGINGMODE_AMD64_NX:
3056	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
3057	enmShadowMode = PGMMODE_PAE;
3058	enmSwitcher = VMMSWITCHER_AMD64_TO_PAE;
3059	break;
3060
3061	default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
3062	}
3063	break;
3064
3065	case PGMMODE_AMD64:
3066	case PGMMODE_AMD64_NX:
3067	switch (enmHostMode)
3068	{
3069	case SUPPAGINGMODE_32_BIT:
3070	case SUPPAGINGMODE_32_BIT_GLOBAL:
3071	enmShadowMode = PGMMODE_PAE;
3072	enmSwitcher = VMMSWITCHER_32_TO_AMD64;
3073	break;
3074
3075	case SUPPAGINGMODE_PAE:
3076	case SUPPAGINGMODE_PAE_NX:
3077	case SUPPAGINGMODE_PAE_GLOBAL:
3078	case SUPPAGINGMODE_PAE_GLOBAL_NX:
3079	enmShadowMode = PGMMODE_PAE;
3080	enmSwitcher = VMMSWITCHER_PAE_TO_AMD64;
3081	break;
3082
3083	case SUPPAGINGMODE_AMD64:
3084	case SUPPAGINGMODE_AMD64_GLOBAL:
3085	case SUPPAGINGMODE_AMD64_NX:
3086	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
3087	enmShadowMode = PGMMODE_AMD64;
3088	enmSwitcher = VMMSWITCHER_AMD64_TO_AMD64;
3089	break;
3090
3091	default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
3092	}
3093	break;
3094
3095
3096	default:
3097	AssertReleaseMsgFailed(("enmGuestMode=%d\n", enmGuestMode));
3098	return PGMMODE_INVALID;
3099	}
3100	/* Override the shadow mode is nested paging is active. */
3101	if (HWACCMIsNestedPagingActive(pVM))
3102	enmShadowMode = HWACCMGetPagingMode(pVM);
3103
3104	*penmSwitcher = enmSwitcher;
3105	return enmShadowMode;
3106	}
3107
3108	/**
3109	* Performs the actual mode change.
3110	* This is called by PGMChangeMode and pgmR3InitPaging().
3111	*
3112	* @returns VBox status code.
3113	* @param pVM VM handle.
3114	* @param enmGuestMode The new guest mode. This is assumed to be different from
3115	* the current mode.
3116	*/
3117	VMMR3DECL(int) PGMR3ChangeMode(PVM pVM, PGMMODE enmGuestMode)
3118	{
3119	Log(("PGMR3ChangeMode: Guest mode: %s -> %s\n", PGMGetModeName(pVM->pgm.s.enmGuestMode), PGMGetModeName(enmGuestMode)));
3120	STAM_REL_COUNTER_INC(&pVM->pgm.s.cGuestModeChanges);
3121
3122	/*
3123	* Calc the shadow mode and switcher.
3124	*/
3125	VMMSWITCHER enmSwitcher;
3126	PGMMODE enmShadowMode = pgmR3CalcShadowMode(pVM, enmGuestMode, pVM->pgm.s.enmHostMode, pVM->pgm.s.enmShadowMode, &enmSwitcher);
3127	if (enmSwitcher != VMMSWITCHER_INVALID)
3128	{
3129	/*
3130	* Select new switcher.
3131	*/
3132	int rc = VMMR3SelectSwitcher(pVM, enmSwitcher);
3133	if (VBOX_FAILURE(rc))
3134	{
3135	AssertReleaseMsgFailed(("VMMR3SelectSwitcher(%d) -> %Vrc\n", enmSwitcher, rc));
3136	return rc;
3137	}
3138	}
3139
3140	/*
3141	* Exit old mode(s).
3142	*/
3143	/* shadow */
3144	if (enmShadowMode != pVM->pgm.s.enmShadowMode)
3145	{
3146	LogFlow(("PGMR3ChangeMode: Shadow mode: %s -> %s\n", PGMGetModeName(pVM->pgm.s.enmShadowMode), PGMGetModeName(enmShadowMode)));
3147	if (PGM_SHW_PFN(Exit, pVM))
3148	{
3149	int rc = PGM_SHW_PFN(Exit, pVM)(pVM);
3150	if (VBOX_FAILURE(rc))
3151	{
3152	AssertMsgFailed(("Exit failed for shadow mode %d: %Vrc\n", pVM->pgm.s.enmShadowMode, rc));
3153	return rc;
3154	}
3155	}
3156
3157	}
3158	else
3159	LogFlow(("PGMR3ChangeMode: Shadow mode remains: %s\n", PGMGetModeName(pVM->pgm.s.enmShadowMode)));
3160
3161	/* guest */
3162	if (PGM_GST_PFN(Exit, pVM))
3163	{
3164	int rc = PGM_GST_PFN(Exit, pVM)(pVM);
3165	if (VBOX_FAILURE(rc))
3166	{
3167	AssertMsgFailed(("Exit failed for guest mode %d: %Vrc\n", pVM->pgm.s.enmGuestMode, rc));
3168	return rc;
3169	}
3170	}
3171
3172	/*
3173	* Load new paging mode data.
3174	*/
3175	pgmR3ModeDataSwitch(pVM, enmShadowMode, enmGuestMode);
3176
3177	/*
3178	* Enter new shadow mode (if changed).
3179	*/
3180	if (enmShadowMode != pVM->pgm.s.enmShadowMode)
3181	{
3182	int rc;
3183	pVM->pgm.s.enmShadowMode = enmShadowMode;
3184	switch (enmShadowMode)
3185	{
3186	case PGMMODE_32_BIT:
3187	rc = PGM_SHW_NAME_32BIT(Enter)(pVM);
3188	break;
3189	case PGMMODE_PAE:
3190	case PGMMODE_PAE_NX:
3191	rc = PGM_SHW_NAME_PAE(Enter)(pVM);
3192	break;
3193	case PGMMODE_AMD64:
3194	case PGMMODE_AMD64_NX:
3195	rc = PGM_SHW_NAME_AMD64(Enter)(pVM);
3196	break;
3197	case PGMMODE_NESTED:
3198	rc = PGM_SHW_NAME_NESTED(Enter)(pVM);
3199	break;
3200	case PGMMODE_EPT:
3201	rc = PGM_SHW_NAME_EPT(Enter)(pVM);
3202	break;
3203	case PGMMODE_REAL:
3204	case PGMMODE_PROTECTED:
3205	default:
3206	AssertReleaseMsgFailed(("enmShadowMode=%d\n", enmShadowMode));
3207	return VERR_INTERNAL_ERROR;
3208	}
3209	if (VBOX_FAILURE(rc))
3210	{
3211	AssertReleaseMsgFailed(("Entering enmShadowMode=%d failed: %Vrc\n", enmShadowMode, rc));
3212	pVM->pgm.s.enmShadowMode = PGMMODE_INVALID;
3213	return rc;
3214	}
3215	}
3216
3217	/* We must flush the PGM pool cache if the guest mode changes; we don't always
3218	* switch shadow paging mode (e.g. protected->32-bit) and shouldn't reuse
3219	* the shadow page tables.
3220	*
3221	* That only applies when switching between paging and non-paging modes.
3222	*
3223	* @todo A20 setting
3224	*/
3225	if ( pVM->pgm.s.CTX_SUFF(pPool)
3226	&& !HWACCMIsNestedPagingActive(pVM)
3227	&& PGMMODE_WITH_PAGING(pVM->pgm.s.enmGuestMode) != PGMMODE_WITH_PAGING(enmGuestMode))
3228	{
3229	Log(("PGMR3ChangeMode: changing guest paging mode -> flush pgm pool cache!\n"));
3230	pgmPoolFlushAll(pVM);
3231	}
3232
3233	/*
3234	* Enter the new guest and shadow+guest modes.
3235	*/
3236	int rc = -1;
3237	int rc2 = -1;
3238	RTGCPHYS GCPhysCR3 = NIL_RTGCPHYS;
3239	pVM->pgm.s.enmGuestMode = enmGuestMode;
3240	switch (enmGuestMode)
3241	{
3242	case PGMMODE_REAL:
3243	rc = PGM_GST_NAME_REAL(Enter)(pVM, NIL_RTGCPHYS);
3244	switch (pVM->pgm.s.enmShadowMode)
3245	{
3246	case PGMMODE_32_BIT:
3247	rc2 = PGM_BTH_NAME_32BIT_REAL(Enter)(pVM, NIL_RTGCPHYS);
3248	break;
3249	case PGMMODE_PAE:
3250	case PGMMODE_PAE_NX:
3251	rc2 = PGM_BTH_NAME_PAE_REAL(Enter)(pVM, NIL_RTGCPHYS);
3252	break;
3253	case PGMMODE_NESTED:
3254	rc2 = PGM_BTH_NAME_NESTED_REAL(Enter)(pVM, NIL_RTGCPHYS);
3255	break;
3256	case PGMMODE_EPT:
3257	rc2 = PGM_BTH_NAME_EPT_REAL(Enter)(pVM, NIL_RTGCPHYS);
3258	break;
3259	case PGMMODE_AMD64:
3260	case PGMMODE_AMD64_NX:
3261	AssertMsgFailed(("Should use PAE shadow mode!\n"));
3262	default: AssertFailed(); break;
3263	}
3264	break;
3265
3266	case PGMMODE_PROTECTED:
3267	rc = PGM_GST_NAME_PROT(Enter)(pVM, NIL_RTGCPHYS);
3268	switch (pVM->pgm.s.enmShadowMode)
3269	{
3270	case PGMMODE_32_BIT:
3271	rc2 = PGM_BTH_NAME_32BIT_PROT(Enter)(pVM, NIL_RTGCPHYS);
3272	break;
3273	case PGMMODE_PAE:
3274	case PGMMODE_PAE_NX:
3275	rc2 = PGM_BTH_NAME_PAE_PROT(Enter)(pVM, NIL_RTGCPHYS);
3276	break;
3277	case PGMMODE_NESTED:
3278	rc2 = PGM_BTH_NAME_NESTED_PROT(Enter)(pVM, NIL_RTGCPHYS);
3279	break;
3280	case PGMMODE_EPT:
3281	rc2 = PGM_BTH_NAME_EPT_PROT(Enter)(pVM, NIL_RTGCPHYS);
3282	break;
3283	case PGMMODE_AMD64:
3284	case PGMMODE_AMD64_NX:
3285	AssertMsgFailed(("Should use PAE shadow mode!\n"));
3286	default: AssertFailed(); break;
3287	}
3288	break;
3289
3290	case PGMMODE_32_BIT:
3291	GCPhysCR3 = CPUMGetGuestCR3(pVM) & X86_CR3_PAGE_MASK;
3292	rc = PGM_GST_NAME_32BIT(Enter)(pVM, GCPhysCR3);
3293	switch (pVM->pgm.s.enmShadowMode)
3294	{
3295	case PGMMODE_32_BIT:
3296	rc2 = PGM_BTH_NAME_32BIT_32BIT(Enter)(pVM, GCPhysCR3);
3297	break;
3298	case PGMMODE_PAE:
3299	case PGMMODE_PAE_NX:
3300	rc2 = PGM_BTH_NAME_PAE_32BIT(Enter)(pVM, GCPhysCR3);
3301	break;
3302	case PGMMODE_NESTED:
3303	rc2 = PGM_BTH_NAME_NESTED_32BIT(Enter)(pVM, GCPhysCR3);
3304	break;
3305	case PGMMODE_EPT:
3306	rc2 = PGM_BTH_NAME_EPT_32BIT(Enter)(pVM, GCPhysCR3);
3307	break;
3308	case PGMMODE_AMD64:
3309	case PGMMODE_AMD64_NX:
3310	AssertMsgFailed(("Should use PAE shadow mode!\n"));
3311	default: AssertFailed(); break;
3312	}
3313	break;
3314
3315	case PGMMODE_PAE_NX:
3316	case PGMMODE_PAE:
3317	{
3318	uint32_t u32Dummy, u32Features;
3319
3320	CPUMGetGuestCpuId(pVM, 1, &u32Dummy, &u32Dummy, &u32Dummy, &u32Features);
3321	if (!(u32Features & X86_CPUID_FEATURE_EDX_PAE))
3322	{
3323	/* Pause first, then inform Main. */
3324	rc = VMR3SuspendNoSave(pVM);
3325	AssertRC(rc);
3326
3327	VMSetRuntimeError(pVM, true, "PAEmode",
3328	N_("The guest is trying to switch to the PAE mode which is currently disabled by default in VirtualBox. Experimental PAE support can be enabled using the -pae option with VBoxManage"));
3329	/* we must return TRUE here otherwise the recompiler will assert */
3330	return VINF_SUCCESS;
3331	}
3332	GCPhysCR3 = CPUMGetGuestCR3(pVM) & X86_CR3_PAE_PAGE_MASK;
3333	rc = PGM_GST_NAME_PAE(Enter)(pVM, GCPhysCR3);
3334	switch (pVM->pgm.s.enmShadowMode)
3335	{
3336	case PGMMODE_PAE:
3337	case PGMMODE_PAE_NX:
3338	rc2 = PGM_BTH_NAME_PAE_PAE(Enter)(pVM, GCPhysCR3);
3339	break;
3340	case PGMMODE_NESTED:
3341	rc2 = PGM_BTH_NAME_NESTED_PAE(Enter)(pVM, GCPhysCR3);
3342	break;
3343	case PGMMODE_EPT:
3344	rc2 = PGM_BTH_NAME_EPT_PAE(Enter)(pVM, GCPhysCR3);
3345	break;
3346	case PGMMODE_32_BIT:
3347	case PGMMODE_AMD64:
3348	case PGMMODE_AMD64_NX:
3349	AssertMsgFailed(("Should use PAE shadow mode!\n"));
3350	default: AssertFailed(); break;
3351	}
3352	break;
3353	}
3354
3355	case PGMMODE_AMD64_NX:
3356	case PGMMODE_AMD64:
3357	GCPhysCR3 = CPUMGetGuestCR3(pVM) & 0xfffffffffffff000ULL; /** @todo define this mask! */
3358	rc = PGM_GST_NAME_AMD64(Enter)(pVM, GCPhysCR3);
3359	switch (pVM->pgm.s.enmShadowMode)
3360	{
3361	case PGMMODE_AMD64:
3362	case PGMMODE_AMD64_NX:
3363	rc2 = PGM_BTH_NAME_AMD64_AMD64(Enter)(pVM, GCPhysCR3);
3364	break;
3365	case PGMMODE_NESTED:
3366	rc2 = PGM_BTH_NAME_NESTED_AMD64(Enter)(pVM, GCPhysCR3);
3367	break;
3368	case PGMMODE_EPT:
3369	rc2 = PGM_BTH_NAME_EPT_AMD64(Enter)(pVM, GCPhysCR3);
3370	break;
3371	case PGMMODE_32_BIT:
3372	case PGMMODE_PAE:
3373	case PGMMODE_PAE_NX:
3374	AssertMsgFailed(("Should use AMD64 shadow mode!\n"));
3375	default: AssertFailed(); break;
3376	}
3377	break;
3378
3379	default:
3380	AssertReleaseMsgFailed(("enmGuestMode=%d\n", enmGuestMode));
3381	rc = VERR_NOT_IMPLEMENTED;
3382	break;
3383	}
3384
3385	/* status codes. */
3386	AssertRC(rc);
3387	AssertRC(rc2);
3388	if (VBOX_SUCCESS(rc))
3389	{
3390	rc = rc2;
3391	if (VBOX_SUCCESS(rc)) /* no informational status codes. */
3392	rc = VINF_SUCCESS;
3393	}
3394
3395	/*
3396	* Notify SELM so it can update the TSSes with correct CR3s.
3397	*/
3398	SELMR3PagingModeChanged(pVM);
3399
3400	/* Notify HWACCM as well. */
3401	HWACCMR3PagingModeChanged(pVM, pVM->pgm.s.enmShadowMode);
3402	return rc;
3403	}
3404
3405
3406	/**
3407	* Dumps a PAE shadow page table.
3408	*
3409	* @returns VBox status code (VINF_SUCCESS).
3410	* @param pVM The VM handle.
3411	* @param pPT Pointer to the page table.
3412	* @param u64Address The virtual address of the page table starts.
3413	* @param fLongMode Set if this a long mode table; clear if it's a legacy mode table.
3414	* @param cMaxDepth The maxium depth.
3415	* @param pHlp Pointer to the output functions.
3416	*/
3417	static int pgmR3DumpHierarchyHCPaePT(PVM pVM, PX86PTPAE pPT, uint64_t u64Address, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
3418	{
3419	for (unsigned i = 0; i < RT_ELEMENTS(pPT->a); i++)
3420	{
3421	X86PTEPAE Pte = pPT->a[i];
3422	if (Pte.n.u1Present)
3423	{
3424	pHlp->pfnPrintf(pHlp,
3425	fLongMode /P R S A D G WT CD AT NX 4M a p ? /
3426	? "%016llx 3 \| P %c %c %c %c %c %s %s %s %s 4K %c%c%c %016llx\n"
3427	: "%08llx 2 \| P %c %c %c %c %c %s %s %s %s 4K %c%c%c %016llx\n",
3428	u64Address + ((uint64_t)i << X86_PT_PAE_SHIFT),
3429	Pte.n.u1Write ? 'W' : 'R',
3430	Pte.n.u1User ? 'U' : 'S',
3431	Pte.n.u1Accessed ? 'A' : '-',
3432	Pte.n.u1Dirty ? 'D' : '-',
3433	Pte.n.u1Global ? 'G' : '-',
3434	Pte.n.u1WriteThru ? "WT" : "--",
3435	Pte.n.u1CacheDisable? "CD" : "--",
3436	Pte.n.u1PAT ? "AT" : "--",
3437	Pte.n.u1NoExecute ? "NX" : "--",
3438	Pte.u & PGM_PTFLAGS_TRACK_DIRTY ? 'd' : '-',
3439	Pte.u & RT_BIT(10) ? '1' : '0',
3440	Pte.u & PGM_PTFLAGS_CSAM_VALIDATED? 'v' : '-',
3441	Pte.u & X86_PTE_PAE_PG_MASK);
3442	}
3443	}
3444	return VINF_SUCCESS;
3445	}
3446
3447
3448	/**
3449	* Dumps a PAE shadow page directory table.
3450	*
3451	* @returns VBox status code (VINF_SUCCESS).
3452	* @param pVM The VM handle.
3453	* @param HCPhys The physical address of the page directory table.
3454	* @param u64Address The virtual address of the page table starts.
3455	* @param cr4 The CR4, PSE is currently used.
3456	* @param fLongMode Set if this a long mode table; clear if it's a legacy mode table.
3457	* @param cMaxDepth The maxium depth.
3458	* @param pHlp Pointer to the output functions.
3459	*/
3460	static int pgmR3DumpHierarchyHCPaePD(PVM pVM, RTHCPHYS HCPhys, uint64_t u64Address, uint32_t cr4, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
3461	{
3462	PX86PDPAE pPD = (PX86PDPAE)MMPagePhys2Page(pVM, HCPhys);
3463	if (!pPD)
3464	{
3465	pHlp->pfnPrintf(pHlp, "%0*llx error! Page directory at HCPhys=%#VHp was not found in the page pool!\n",
3466	fLongMode ? 16 : 8, u64Address, HCPhys);
3467	return VERR_INVALID_PARAMETER;
3468	}
3469	const bool fBigPagesSupported = fLongMode \|\| !!(cr4 & X86_CR4_PSE);
3470
3471	int rc = VINF_SUCCESS;
3472	for (unsigned i = 0; i < RT_ELEMENTS(pPD->a); i++)
3473	{
3474	X86PDEPAE Pde = pPD->a[i];
3475	if (Pde.n.u1Present)
3476	{
3477	if (fBigPagesSupported && Pde.b.u1Size)
3478	pHlp->pfnPrintf(pHlp,
3479	fLongMode /P R S A D G WT CD AT NX 4M a p ? /
3480	? "%016llx 2 \| P %c %c %c %c %c %s %s %s %s 4M %c%c%c %016llx\n"
3481	: "%08llx 1 \| P %c %c %c %c %c %s %s %s %s 4M %c%c%c %016llx\n",
3482	u64Address + ((uint64_t)i << X86_PD_PAE_SHIFT),
3483	Pde.b.u1Write ? 'W' : 'R',
3484	Pde.b.u1User ? 'U' : 'S',
3485	Pde.b.u1Accessed ? 'A' : '-',
3486	Pde.b.u1Dirty ? 'D' : '-',
3487	Pde.b.u1Global ? 'G' : '-',
3488	Pde.b.u1WriteThru ? "WT" : "--",
3489	Pde.b.u1CacheDisable? "CD" : "--",
3490	Pde.b.u1PAT ? "AT" : "--",
3491	Pde.b.u1NoExecute ? "NX" : "--",
3492	Pde.u & RT_BIT_64(9) ? '1' : '0',
3493	Pde.u & PGM_PDFLAGS_MAPPING ? 'm' : '-',
3494	Pde.u & PGM_PDFLAGS_TRACK_DIRTY ? 'd' : '-',
3495	Pde.u & X86_PDE_PAE_PG_MASK);
3496	else
3497	{
3498	pHlp->pfnPrintf(pHlp,
3499	fLongMode /P R S A D G WT CD AT NX 4M a p ? /
3500	? "%016llx 2 \| P %c %c %c %c %c %s %s .. %s 4K %c%c%c %016llx\n"
3501	: "%08llx 1 \| P %c %c %c %c %c %s %s .. %s 4K %c%c%c %016llx\n",
3502	u64Address + ((uint64_t)i << X86_PD_PAE_SHIFT),
3503	Pde.n.u1Write ? 'W' : 'R',
3504	Pde.n.u1User ? 'U' : 'S',
3505	Pde.n.u1Accessed ? 'A' : '-',
3506	Pde.n.u1Reserved0 ? '?' : '.', /* ignored */
3507	Pde.n.u1Reserved1 ? '?' : '.', /* ignored */
3508	Pde.n.u1WriteThru ? "WT" : "--",
3509	Pde.n.u1CacheDisable? "CD" : "--",
3510	Pde.n.u1NoExecute ? "NX" : "--",
3511	Pde.u & RT_BIT_64(9) ? '1' : '0',
3512	Pde.u & PGM_PDFLAGS_MAPPING ? 'm' : '-',
3513	Pde.u & PGM_PDFLAGS_TRACK_DIRTY ? 'd' : '-',
3514	Pde.u & X86_PDE_PAE_PG_MASK);
3515	if (cMaxDepth >= 1)
3516	{
3517	/** @todo what about using the page pool for mapping PTs? */
3518	uint64_t u64AddressPT = u64Address + ((uint64_t)i << X86_PD_PAE_SHIFT);
3519	RTHCPHYS HCPhysPT = Pde.u & X86_PDE_PAE_PG_MASK;
3520	PX86PTPAE pPT = NULL;
3521	if (!(Pde.u & PGM_PDFLAGS_MAPPING))
3522	pPT = (PX86PTPAE)MMPagePhys2Page(pVM, HCPhysPT);
3523	else
3524	{
3525	for (PPGMMAPPING pMap = pVM->pgm.s.pMappingsR3; pMap; pMap = pMap->pNextR3)
3526	{
3527	uint64_t off = u64AddressPT - pMap->GCPtr;
3528	if (off < pMap->cb)
3529	{
3530	const int iPDE = (uint32_t)(off >> X86_PD_SHIFT);
3531	const int iSub = (int)((off >> X86_PD_PAE_SHIFT) & 1); /* MSC is a pain sometimes */
3532	if ((iSub ? pMap->aPTs[iPDE].HCPhysPaePT1 : pMap->aPTs[iPDE].HCPhysPaePT0) != HCPhysPT)
3533	pHlp->pfnPrintf(pHlp, "%0*llx error! Mapping error! PT %d has HCPhysPT=%VHp not %VHp is in the PD.\n",
3534	fLongMode ? 16 : 8, u64AddressPT, iPDE,
3535	iSub ? pMap->aPTs[iPDE].HCPhysPaePT1 : pMap->aPTs[iPDE].HCPhysPaePT0, HCPhysPT);
3536	pPT = &pMap->aPTs[iPDE].paPaePTsR3[iSub];
3537	}
3538	}
3539	}
3540	int rc2 = VERR_INVALID_PARAMETER;
3541	if (pPT)
3542	rc2 = pgmR3DumpHierarchyHCPaePT(pVM, pPT, u64AddressPT, fLongMode, cMaxDepth - 1, pHlp);
3543	else
3544	pHlp->pfnPrintf(pHlp, "%0*llx error! Page table at HCPhys=%#VHp was not found in the page pool!\n",
3545	fLongMode ? 16 : 8, u64AddressPT, HCPhysPT);
3546	if (rc2 < rc && VBOX_SUCCESS(rc))
3547	rc = rc2;
3548	}
3549	}
3550	}
3551	}
3552	return rc;
3553	}
3554
3555
3556	/**
3557	* Dumps a PAE shadow page directory pointer table.
3558	*
3559	* @returns VBox status code (VINF_SUCCESS).
3560	* @param pVM The VM handle.
3561	* @param HCPhys The physical address of the page directory pointer table.
3562	* @param u64Address The virtual address of the page table starts.
3563	* @param cr4 The CR4, PSE is currently used.
3564	* @param fLongMode Set if this a long mode table; clear if it's a legacy mode table.
3565	* @param cMaxDepth The maxium depth.
3566	* @param pHlp Pointer to the output functions.
3567	*/
3568	static int pgmR3DumpHierarchyHCPaePDPT(PVM pVM, RTHCPHYS HCPhys, uint64_t u64Address, uint32_t cr4, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
3569	{
3570	PX86PDPT pPDPT = (PX86PDPT)MMPagePhys2Page(pVM, HCPhys);
3571	if (!pPDPT)
3572	{
3573	pHlp->pfnPrintf(pHlp, "%0*llx error! Page directory pointer table at HCPhys=%#VHp was not found in the page pool!\n",
3574	fLongMode ? 16 : 8, u64Address, HCPhys);
3575	return VERR_INVALID_PARAMETER;
3576	}
3577
3578	int rc = VINF_SUCCESS;
3579	const unsigned c = fLongMode ? RT_ELEMENTS(pPDPT->a) : X86_PG_PAE_PDPE_ENTRIES;
3580	for (unsigned i = 0; i < c; i++)
3581	{
3582	X86PDPE Pdpe = pPDPT->a[i];
3583	if (Pdpe.n.u1Present)
3584	{
3585	if (fLongMode)
3586	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a p ? /
3587	"%016llx 1 \| P %c %c %c %c %c %s %s %s %s .. %c%c%c %016llx\n",
3588	u64Address + ((uint64_t)i << X86_PDPT_SHIFT),
3589	Pdpe.lm.u1Write ? 'W' : 'R',
3590	Pdpe.lm.u1User ? 'U' : 'S',
3591	Pdpe.lm.u1Accessed ? 'A' : '-',
3592	Pdpe.lm.u3Reserved & 1? '?' : '.', /* ignored */
3593	Pdpe.lm.u3Reserved & 4? '!' : '.', /* mbz */
3594	Pdpe.lm.u1WriteThru ? "WT" : "--",
3595	Pdpe.lm.u1CacheDisable? "CD" : "--",
3596	Pdpe.lm.u3Reserved & 2? "!" : "..",/* mbz */
3597	Pdpe.lm.u1NoExecute ? "NX" : "--",
3598	Pdpe.u & RT_BIT(9) ? '1' : '0',
3599	Pdpe.u & PGM_PLXFLAGS_PERMANENT ? 'p' : '-',
3600	Pdpe.u & RT_BIT(11) ? '1' : '0',
3601	Pdpe.u & X86_PDPE_PG_MASK);
3602	else
3603	pHlp->pfnPrintf(pHlp, /P G WT CD AT NX 4M a p ? /
3604	"%08x 0 \| P %c %s %s %s %s .. %c%c%c %016llx\n",
3605	i << X86_PDPT_SHIFT,
3606	Pdpe.n.u4Reserved & 1? '!' : '.', /* mbz */
3607	Pdpe.n.u4Reserved & 4? '!' : '.', /* mbz */
3608	Pdpe.n.u1WriteThru ? "WT" : "--",
3609	Pdpe.n.u1CacheDisable? "CD" : "--",
3610	Pdpe.n.u4Reserved & 2? "!" : "..",/* mbz */
3611	Pdpe.u & RT_BIT(9) ? '1' : '0',
3612	Pdpe.u & PGM_PLXFLAGS_PERMANENT ? 'p' : '-',
3613	Pdpe.u & RT_BIT(11) ? '1' : '0',
3614	Pdpe.u & X86_PDPE_PG_MASK);
3615	if (cMaxDepth >= 1)
3616	{
3617	int rc2 = pgmR3DumpHierarchyHCPaePD(pVM, Pdpe.u & X86_PDPE_PG_MASK, u64Address + ((uint64_t)i << X86_PDPT_SHIFT),
3618	cr4, fLongMode, cMaxDepth - 1, pHlp);
3619	if (rc2 < rc && VBOX_SUCCESS(rc))
3620	rc = rc2;
3621	}
3622	}
3623	}
3624	return rc;
3625	}
3626
3627
3628	/**
3629	* Dumps a 32-bit shadow page table.
3630	*
3631	* @returns VBox status code (VINF_SUCCESS).
3632	* @param pVM The VM handle.
3633	* @param HCPhys The physical address of the table.
3634	* @param cr4 The CR4, PSE is currently used.
3635	* @param cMaxDepth The maxium depth.
3636	* @param pHlp Pointer to the output functions.
3637	*/
3638	static int pgmR3DumpHierarchyHcPaePML4(PVM pVM, RTHCPHYS HCPhys, uint32_t cr4, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
3639	{
3640	PX86PML4 pPML4 = (PX86PML4)MMPagePhys2Page(pVM, HCPhys);
3641	if (!pPML4)
3642	{
3643	pHlp->pfnPrintf(pHlp, "Page map level 4 at HCPhys=%#VHp was not found in the page pool!\n", HCPhys);
3644	return VERR_INVALID_PARAMETER;
3645	}
3646
3647	int rc = VINF_SUCCESS;
3648	for (unsigned i = 0; i < RT_ELEMENTS(pPML4->a); i++)
3649	{
3650	X86PML4E Pml4e = pPML4->a[i];
3651	if (Pml4e.n.u1Present)
3652	{
3653	uint64_t u64Address = ((uint64_t)i << X86_PML4_SHIFT) \| (((uint64_t)i >> (X86_PML4_SHIFT - X86_PDPT_SHIFT - 1)) * 0xffff000000000000ULL);
3654	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a p ? /
3655	"%016llx 0 \| P %c %c %c %c %c %s %s %s %s .. %c%c%c %016llx\n",
3656	u64Address,
3657	Pml4e.n.u1Write ? 'W' : 'R',
3658	Pml4e.n.u1User ? 'U' : 'S',
3659	Pml4e.n.u1Accessed ? 'A' : '-',
3660	Pml4e.n.u3Reserved & 1? '?' : '.', /* ignored */
3661	Pml4e.n.u3Reserved & 4? '!' : '.', /* mbz */
3662	Pml4e.n.u1WriteThru ? "WT" : "--",
3663	Pml4e.n.u1CacheDisable? "CD" : "--",
3664	Pml4e.n.u3Reserved & 2? "!" : "..",/* mbz */
3665	Pml4e.n.u1NoExecute ? "NX" : "--",
3666	Pml4e.u & RT_BIT(9) ? '1' : '0',
3667	Pml4e.u & PGM_PLXFLAGS_PERMANENT ? 'p' : '-',
3668	Pml4e.u & RT_BIT(11) ? '1' : '0',
3669	Pml4e.u & X86_PML4E_PG_MASK);
3670
3671	if (cMaxDepth >= 1)
3672	{
3673	int rc2 = pgmR3DumpHierarchyHCPaePDPT(pVM, Pml4e.u & X86_PML4E_PG_MASK, u64Address, cr4, true, cMaxDepth - 1, pHlp);
3674	if (rc2 < rc && VBOX_SUCCESS(rc))
3675	rc = rc2;
3676	}
3677	}
3678	}
3679	return rc;
3680	}
3681
3682
3683	/**
3684	* Dumps a 32-bit shadow page table.
3685	*
3686	* @returns VBox status code (VINF_SUCCESS).
3687	* @param pVM The VM handle.
3688	* @param pPT Pointer to the page table.
3689	* @param u32Address The virtual address this table starts at.
3690	* @param pHlp Pointer to the output functions.
3691	*/
3692	int pgmR3DumpHierarchyHC32BitPT(PVM pVM, PX86PT pPT, uint32_t u32Address, PCDBGFINFOHLP pHlp)
3693	{
3694	for (unsigned i = 0; i < RT_ELEMENTS(pPT->a); i++)
3695	{
3696	X86PTE Pte = pPT->a[i];
3697	if (Pte.n.u1Present)
3698	{
3699	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a m d /
3700	"%08x 1 \| P %c %c %c %c %c %s %s %s .. 4K %c%c%c %08x\n",
3701	u32Address + (i << X86_PT_SHIFT),
3702	Pte.n.u1Write ? 'W' : 'R',
3703	Pte.n.u1User ? 'U' : 'S',
3704	Pte.n.u1Accessed ? 'A' : '-',
3705	Pte.n.u1Dirty ? 'D' : '-',
3706	Pte.n.u1Global ? 'G' : '-',
3707	Pte.n.u1WriteThru ? "WT" : "--",
3708	Pte.n.u1CacheDisable? "CD" : "--",
3709	Pte.n.u1PAT ? "AT" : "--",
3710	Pte.u & PGM_PTFLAGS_TRACK_DIRTY ? 'd' : '-',
3711	Pte.u & RT_BIT(10) ? '1' : '0',
3712	Pte.u & PGM_PTFLAGS_CSAM_VALIDATED ? 'v' : '-',
3713	Pte.u & X86_PDE_PG_MASK);
3714	}
3715	}
3716	return VINF_SUCCESS;
3717	}
3718
3719
3720	/**
3721	* Dumps a 32-bit shadow page directory and page tables.
3722	*
3723	* @returns VBox status code (VINF_SUCCESS).
3724	* @param pVM The VM handle.
3725	* @param cr3 The root of the hierarchy.
3726	* @param cr4 The CR4, PSE is currently used.
3727	* @param cMaxDepth How deep into the hierarchy the dumper should go.
3728	* @param pHlp Pointer to the output functions.
3729	*/
3730	int pgmR3DumpHierarchyHC32BitPD(PVM pVM, uint32_t cr3, uint32_t cr4, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
3731	{
3732	PX86PD pPD = (PX86PD)MMPagePhys2Page(pVM, cr3 & X86_CR3_PAGE_MASK);
3733	if (!pPD)
3734	{
3735	pHlp->pfnPrintf(pHlp, "Page directory at %#x was not found in the page pool!\n", cr3 & X86_CR3_PAGE_MASK);
3736	return VERR_INVALID_PARAMETER;
3737	}
3738
3739	int rc = VINF_SUCCESS;
3740	for (unsigned i = 0; i < RT_ELEMENTS(pPD->a); i++)
3741	{
3742	X86PDE Pde = pPD->a[i];
3743	if (Pde.n.u1Present)
3744	{
3745	const uint32_t u32Address = i << X86_PD_SHIFT;
3746	if ((cr4 & X86_CR4_PSE) && Pde.b.u1Size)
3747	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a m d /
3748	"%08x 0 \| P %c %c %c %c %c %s %s %s .. 4M %c%c%c %08x\n",
3749	u32Address,
3750	Pde.b.u1Write ? 'W' : 'R',
3751	Pde.b.u1User ? 'U' : 'S',
3752	Pde.b.u1Accessed ? 'A' : '-',
3753	Pde.b.u1Dirty ? 'D' : '-',
3754	Pde.b.u1Global ? 'G' : '-',
3755	Pde.b.u1WriteThru ? "WT" : "--",
3756	Pde.b.u1CacheDisable? "CD" : "--",
3757	Pde.b.u1PAT ? "AT" : "--",
3758	Pde.u & RT_BIT_64(9) ? '1' : '0',
3759	Pde.u & PGM_PDFLAGS_MAPPING ? 'm' : '-',
3760	Pde.u & PGM_PDFLAGS_TRACK_DIRTY ? 'd' : '-',
3761	Pde.u & X86_PDE4M_PG_MASK);
3762	else
3763	{
3764	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a m d /
3765	"%08x 0 \| P %c %c %c %c %c %s %s .. .. 4K %c%c%c %08x\n",
3766	u32Address,
3767	Pde.n.u1Write ? 'W' : 'R',
3768	Pde.n.u1User ? 'U' : 'S',
3769	Pde.n.u1Accessed ? 'A' : '-',
3770	Pde.n.u1Reserved0 ? '?' : '.', /* ignored */
3771	Pde.n.u1Reserved1 ? '?' : '.', /* ignored */
3772	Pde.n.u1WriteThru ? "WT" : "--",
3773	Pde.n.u1CacheDisable? "CD" : "--",
3774	Pde.u & RT_BIT_64(9) ? '1' : '0',
3775	Pde.u & PGM_PDFLAGS_MAPPING ? 'm' : '-',
3776	Pde.u & PGM_PDFLAGS_TRACK_DIRTY ? 'd' : '-',
3777	Pde.u & X86_PDE_PG_MASK);
3778	if (cMaxDepth >= 1)
3779	{
3780	/** @todo what about using the page pool for mapping PTs? */
3781	RTHCPHYS HCPhys = Pde.u & X86_PDE_PG_MASK;
3782	PX86PT pPT = NULL;
3783	if (!(Pde.u & PGM_PDFLAGS_MAPPING))
3784	pPT = (PX86PT)MMPagePhys2Page(pVM, HCPhys);
3785	else
3786	{
3787	for (PPGMMAPPING pMap = pVM->pgm.s.pMappingsR3; pMap; pMap = pMap->pNextR3)
3788	if (u32Address - pMap->GCPtr < pMap->cb)
3789	{
3790	int iPDE = (u32Address - pMap->GCPtr) >> X86_PD_SHIFT;
3791	if (pMap->aPTs[iPDE].HCPhysPT != HCPhys)
3792	pHlp->pfnPrintf(pHlp, "%08x error! Mapping error! PT %d has HCPhysPT=%VHp not %VHp is in the PD.\n",
3793	u32Address, iPDE, pMap->aPTs[iPDE].HCPhysPT, HCPhys);
3794	pPT = pMap->aPTs[iPDE].pPTR3;
3795	}
3796	}
3797	int rc2 = VERR_INVALID_PARAMETER;
3798	if (pPT)
3799	rc2 = pgmR3DumpHierarchyHC32BitPT(pVM, pPT, u32Address, pHlp);
3800	else
3801	pHlp->pfnPrintf(pHlp, "%08x error! Page table at %#x was not found in the page pool!\n", u32Address, HCPhys);
3802	if (rc2 < rc && VBOX_SUCCESS(rc))
3803	rc = rc2;
3804	}
3805	}
3806	}
3807	}
3808
3809	return rc;
3810	}
3811
3812
3813	/**
3814	* Dumps a 32-bit shadow page table.
3815	*
3816	* @returns VBox status code (VINF_SUCCESS).
3817	* @param pVM The VM handle.
3818	* @param pPT Pointer to the page table.
3819	* @param u32Address The virtual address this table starts at.
3820	* @param PhysSearch Address to search for.
3821	*/
3822	int pgmR3DumpHierarchyGC32BitPT(PVM pVM, PX86PT pPT, uint32_t u32Address, RTGCPHYS PhysSearch)
3823	{
3824	for (unsigned i = 0; i < RT_ELEMENTS(pPT->a); i++)
3825	{
3826	X86PTE Pte = pPT->a[i];
3827	if (Pte.n.u1Present)
3828	{
3829	Log(( /P R S A D G WT CD AT NX 4M a m d /
3830	"%08x 1 \| P %c %c %c %c %c %s %s %s .. 4K %c%c%c %08x\n",
3831	u32Address + (i << X86_PT_SHIFT),
3832	Pte.n.u1Write ? 'W' : 'R',
3833	Pte.n.u1User ? 'U' : 'S',
3834	Pte.n.u1Accessed ? 'A' : '-',
3835	Pte.n.u1Dirty ? 'D' : '-',
3836	Pte.n.u1Global ? 'G' : '-',
3837	Pte.n.u1WriteThru ? "WT" : "--",
3838	Pte.n.u1CacheDisable? "CD" : "--",
3839	Pte.n.u1PAT ? "AT" : "--",
3840	Pte.u & PGM_PTFLAGS_TRACK_DIRTY ? 'd' : '-',
3841	Pte.u & RT_BIT(10) ? '1' : '0',
3842	Pte.u & PGM_PTFLAGS_CSAM_VALIDATED ? 'v' : '-',
3843	Pte.u & X86_PDE_PG_MASK));
3844
3845	if ((Pte.u & X86_PDE_PG_MASK) == PhysSearch)
3846	{
3847	uint64_t fPageShw = 0;
3848	RTHCPHYS pPhysHC = 0;
3849
3850	PGMShwGetPage(pVM, (RTGCPTR)(u32Address + (i << X86_PT_SHIFT)), &fPageShw, &pPhysHC);
3851	Log(("Found %VGp at %VGv -> flags=%llx\n", PhysSearch, (RTGCPTR)(u32Address + (i << X86_PT_SHIFT)), fPageShw));
3852	}
3853	}
3854	}
3855	return VINF_SUCCESS;
3856	}
3857
3858
3859	/**
3860	* Dumps a 32-bit guest page directory and page tables.
3861	*
3862	* @returns VBox status code (VINF_SUCCESS).
3863	* @param pVM The VM handle.
3864	* @param cr3 The root of the hierarchy.
3865	* @param cr4 The CR4, PSE is currently used.
3866	* @param PhysSearch Address to search for.
3867	*/
3868	VMMR3DECL(int) PGMR3DumpHierarchyGC(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCPHYS PhysSearch)
3869	{
3870	bool fLongMode = false;
3871	const unsigned cch = fLongMode ? 16 : 8; NOREF(cch);
3872	PX86PD pPD = 0;
3873
3874	int rc = PGM_GCPHYS_2_PTR(pVM, cr3 & X86_CR3_PAGE_MASK, &pPD);
3875	if (VBOX_FAILURE(rc) \|\| !pPD)
3876	{
3877	Log(("Page directory at %#x was not found in the page pool!\n", cr3 & X86_CR3_PAGE_MASK));
3878	return VERR_INVALID_PARAMETER;
3879	}
3880
3881	Log(("cr3=%08x cr4=%08x%s\n"
3882	"%-*s P - Present\n"
3883	"%-*s \| R/W - Read (0) / Write (1)\n"
3884	"%-*s \| \| U/S - User (1) / Supervisor (0)\n"
3885	"%-*s \| \| \| A - Accessed\n"
3886	"%-*s \| \| \| \| D - Dirty\n"
3887	"%-*s \| \| \| \| \| G - Global\n"
3888	"%-*s \| \| \| \| \| \| WT - Write thru\n"
3889	"%-*s \| \| \| \| \| \| \| CD - Cache disable\n"
3890	"%-*s \| \| \| \| \| \| \| \| AT - Attribute table (PAT)\n"
3891	"%-*s \| \| \| \| \| \| \| \| \| NX - No execute (K8)\n"
3892	"%-*s \| \| \| \| \| \| \| \| \| \| 4K/4M/2M - Page size.\n"
3893	"%-*s \| \| \| \| \| \| \| \| \| \| \| AVL - a=allocated; m=mapping; d=track dirty;\n"
3894	"%-*s \| \| \| \| \| \| \| \| \| \| \| \| p=permanent; v=validated;\n"
3895	"%-*s Level \| \| \| \| \| \| \| \| \| \| \| \| Page\n"
3896	/* xxxx n **** P R S A D G WT CD AT NX 4M AVL xxxxxxxxxxxxx
3897	- W U - - - -- -- -- -- -- 010 */
3898	, cr3, cr4, fLongMode ? " Long Mode" : "",
3899	cch, "", cch, "", cch, "", cch, "", cch, "", cch, "", cch, "",
3900	cch, "", cch, "", cch, "", cch, "", cch, "", cch, "", cch, "Address"));
3901
3902	for (unsigned i = 0; i < RT_ELEMENTS(pPD->a); i++)
3903	{
3904	X86PDE Pde = pPD->a[i];
3905	if (Pde.n.u1Present)
3906	{
3907	const uint32_t u32Address = i << X86_PD_SHIFT;
3908
3909	if ((cr4 & X86_CR4_PSE) && Pde.b.u1Size)
3910	Log(( /P R S A D G WT CD AT NX 4M a m d /
3911	"%08x 0 \| P %c %c %c %c %c %s %s %s .. 4M %c%c%c %08x\n",
3912	u32Address,
3913	Pde.b.u1Write ? 'W' : 'R',
3914	Pde.b.u1User ? 'U' : 'S',
3915	Pde.b.u1Accessed ? 'A' : '-',
3916	Pde.b.u1Dirty ? 'D' : '-',
3917	Pde.b.u1Global ? 'G' : '-',
3918	Pde.b.u1WriteThru ? "WT" : "--",
3919	Pde.b.u1CacheDisable? "CD" : "--",
3920	Pde.b.u1PAT ? "AT" : "--",
3921	Pde.u & RT_BIT(9) ? '1' : '0',
3922	Pde.u & RT_BIT(10) ? '1' : '0',
3923	Pde.u & RT_BIT(11) ? '1' : '0',
3924	pgmGstGet4MBPhysPage(&pVM->pgm.s, Pde)));
3925	/** @todo PhysSearch */
3926	else
3927	{
3928	Log(( /P R S A D G WT CD AT NX 4M a m d /
3929	"%08x 0 \| P %c %c %c %c %c %s %s .. .. 4K %c%c%c %08x\n",
3930	u32Address,
3931	Pde.n.u1Write ? 'W' : 'R',
3932	Pde.n.u1User ? 'U' : 'S',
3933	Pde.n.u1Accessed ? 'A' : '-',
3934	Pde.n.u1Reserved0 ? '?' : '.', /* ignored */
3935	Pde.n.u1Reserved1 ? '?' : '.', /* ignored */
3936	Pde.n.u1WriteThru ? "WT" : "--",
3937	Pde.n.u1CacheDisable? "CD" : "--",
3938	Pde.u & RT_BIT(9) ? '1' : '0',
3939	Pde.u & RT_BIT(10) ? '1' : '0',
3940	Pde.u & RT_BIT(11) ? '1' : '0',
3941	Pde.u & X86_PDE_PG_MASK));
3942	////if (cMaxDepth >= 1)
3943	{
3944	/** @todo what about using the page pool for mapping PTs? */
3945	RTGCPHYS GCPhys = Pde.u & X86_PDE_PG_MASK;
3946	PX86PT pPT = NULL;
3947
3948	rc = PGM_GCPHYS_2_PTR(pVM, GCPhys, &pPT);
3949
3950	int rc2 = VERR_INVALID_PARAMETER;
3951	if (pPT)
3952	rc2 = pgmR3DumpHierarchyGC32BitPT(pVM, pPT, u32Address, PhysSearch);
3953	else
3954	Log(("%08x error! Page table at %#x was not found in the page pool!\n", u32Address, GCPhys));
3955	if (rc2 < rc && VBOX_SUCCESS(rc))
3956	rc = rc2;
3957	}
3958	}
3959	}
3960	}
3961
3962	return rc;
3963	}
3964
3965
3966	/**
3967	* Dumps a page table hierarchy use only physical addresses and cr4/lm flags.
3968	*
3969	* @returns VBox status code (VINF_SUCCESS).
3970	* @param pVM The VM handle.
3971	* @param cr3 The root of the hierarchy.
3972	* @param cr4 The cr4, only PAE and PSE is currently used.
3973	* @param fLongMode Set if long mode, false if not long mode.
3974	* @param cMaxDepth Number of levels to dump.
3975	* @param pHlp Pointer to the output functions.
3976	*/
3977	VMMR3DECL(int) PGMR3DumpHierarchyHC(PVM pVM, uint64_t cr3, uint64_t cr4, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
3978	{
3979	if (!pHlp)
3980	pHlp = DBGFR3InfoLogHlp();
3981	if (!cMaxDepth)
3982	return VINF_SUCCESS;
3983	const unsigned cch = fLongMode ? 16 : 8;
3984	pHlp->pfnPrintf(pHlp,
3985	"cr3=%08x cr4=%08x%s\n"
3986	"%-*s P - Present\n"
3987	"%-*s \| R/W - Read (0) / Write (1)\n"
3988	"%-*s \| \| U/S - User (1) / Supervisor (0)\n"
3989	"%-*s \| \| \| A - Accessed\n"
3990	"%-*s \| \| \| \| D - Dirty\n"
3991	"%-*s \| \| \| \| \| G - Global\n"
3992	"%-*s \| \| \| \| \| \| WT - Write thru\n"
3993	"%-*s \| \| \| \| \| \| \| CD - Cache disable\n"
3994	"%-*s \| \| \| \| \| \| \| \| AT - Attribute table (PAT)\n"
3995	"%-*s \| \| \| \| \| \| \| \| \| NX - No execute (K8)\n"
3996	"%-*s \| \| \| \| \| \| \| \| \| \| 4K/4M/2M - Page size.\n"
3997	"%-*s \| \| \| \| \| \| \| \| \| \| \| AVL - a=allocated; m=mapping; d=track dirty;\n"
3998	"%-*s \| \| \| \| \| \| \| \| \| \| \| \| p=permanent; v=validated;\n"
3999	"%-*s Level \| \| \| \| \| \| \| \| \| \| \| \| Page\n"
4000	/* xxxx n **** P R S A D G WT CD AT NX 4M AVL xxxxxxxxxxxxx
4001	- W U - - - -- -- -- -- -- 010 */
4002	, cr3, cr4, fLongMode ? " Long Mode" : "",
4003	cch, "", cch, "", cch, "", cch, "", cch, "", cch, "", cch, "",
4004	cch, "", cch, "", cch, "", cch, "", cch, "", cch, "", cch, "Address");
4005	if (cr4 & X86_CR4_PAE)
4006	{
4007	if (fLongMode)
4008	return pgmR3DumpHierarchyHcPaePML4(pVM, cr3 & X86_CR3_PAGE_MASK, cr4, cMaxDepth, pHlp);
4009	return pgmR3DumpHierarchyHCPaePDPT(pVM, cr3 & X86_CR3_PAE_PAGE_MASK, 0, cr4, false, cMaxDepth, pHlp);
4010	}
4011	return pgmR3DumpHierarchyHC32BitPD(pVM, cr3 & X86_CR3_PAGE_MASK, cr4, cMaxDepth, pHlp);
4012	}
4013
4014
4015
4016	#ifdef VBOX_WITH_DEBUGGER
4017	/**
4018	* The '.pgmram' command.
4019	*
4020	* @returns VBox status.
4021	* @param pCmd Pointer to the command descriptor (as registered).
4022	* @param pCmdHlp Pointer to command helper functions.
4023	* @param pVM Pointer to the current VM (if any).
4024	* @param paArgs Pointer to (readonly) array of arguments.
4025	* @param cArgs Number of arguments in the array.
4026	*/
4027	static DECLCALLBACK(int) pgmR3CmdRam(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4028	{
4029	/*
4030	* Validate input.
4031	*/
4032	if (!pVM)
4033	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4034	if (!pVM->pgm.s.pRamRangesRC)
4035	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Sorry, no Ram is registered.\n");
4036
4037	/*
4038	* Dump the ranges.
4039	*/
4040	int rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL, "From - To (incl) pvHC\n");
4041	PPGMRAMRANGE pRam;
4042	for (pRam = pVM->pgm.s.pRamRangesR3; pRam; pRam = pRam->pNextR3)
4043	{
4044	rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL,
4045	"%RGp - %RGp %p\n",
4046	pRam->GCPhys, pRam->GCPhysLast, pRam->pvR3);
4047	if (VBOX_FAILURE(rc))
4048	return rc;
4049	}
4050
4051	return VINF_SUCCESS;
4052	}
4053
4054
4055	/**
4056	* The '.pgmmap' command.
4057	*
4058	* @returns VBox status.
4059	* @param pCmd Pointer to the command descriptor (as registered).
4060	* @param pCmdHlp Pointer to command helper functions.
4061	* @param pVM Pointer to the current VM (if any).
4062	* @param paArgs Pointer to (readonly) array of arguments.
4063	* @param cArgs Number of arguments in the array.
4064	*/
4065	static DECLCALLBACK(int) pgmR3CmdMap(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4066	{
4067	/*
4068	* Validate input.
4069	*/
4070	if (!pVM)
4071	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4072	if (!pVM->pgm.s.pMappingsR3)
4073	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Sorry, no mappings are registered.\n");
4074
4075	/*
4076	* Print message about the fixedness of the mappings.
4077	*/
4078	int rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL, pVM->pgm.s.fMappingsFixed ? "The mappings are FIXED.\n" : "The mappings are FLOATING.\n");
4079	if (VBOX_FAILURE(rc))
4080	return rc;
4081
4082	/*
4083	* Dump the ranges.
4084	*/
4085	PPGMMAPPING pCur;
4086	for (pCur = pVM->pgm.s.pMappingsR3; pCur; pCur = pCur->pNextR3)
4087	{
4088	rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL,
4089	"%08x - %08x %s\n",
4090	pCur->GCPtr, pCur->GCPtrLast, pCur->pszDesc);
4091	if (VBOX_FAILURE(rc))
4092	return rc;
4093	}
4094
4095	return VINF_SUCCESS;
4096	}
4097
4098
4099	/**
4100	* The '.pgmsync' command.
4101	*
4102	* @returns VBox status.
4103	* @param pCmd Pointer to the command descriptor (as registered).
4104	* @param pCmdHlp Pointer to command helper functions.
4105	* @param pVM Pointer to the current VM (if any).
4106	* @param paArgs Pointer to (readonly) array of arguments.
4107	* @param cArgs Number of arguments in the array.
4108	*/
4109	static DECLCALLBACK(int) pgmR3CmdSync(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4110	{
4111	/*
4112	* Validate input.
4113	*/
4114	if (!pVM)
4115	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4116
4117	/*
4118	* Force page directory sync.
4119	*/
4120	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
4121
4122	int rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Forcing page directory sync.\n");
4123	if (VBOX_FAILURE(rc))
4124	return rc;
4125
4126	return VINF_SUCCESS;
4127	}
4128
4129
4130	#ifdef VBOX_STRICT
4131	/**
4132	* The '.pgmassertcr3' command.
4133	*
4134	* @returns VBox status.
4135	* @param pCmd Pointer to the command descriptor (as registered).
4136	* @param pCmdHlp Pointer to command helper functions.
4137	* @param pVM Pointer to the current VM (if any).
4138	* @param paArgs Pointer to (readonly) array of arguments.
4139	* @param cArgs Number of arguments in the array.
4140	*/
4141	static DECLCALLBACK(int) pgmR3CmdAssertCR3(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4142	{
4143	/*
4144	* Validate input.
4145	*/
4146	if (!pVM)
4147	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4148
4149	int rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Checking shadow CR3 page tables for consistency.\n");
4150	if (VBOX_FAILURE(rc))
4151	return rc;
4152
4153	PGMAssertCR3(pVM, CPUMGetGuestCR3(pVM), CPUMGetGuestCR4(pVM));
4154
4155	return VINF_SUCCESS;
4156	}
4157	#endif
4158
4159	/**
4160	* The '.pgmsyncalways' command.
4161	*
4162	* @returns VBox status.
4163	* @param pCmd Pointer to the command descriptor (as registered).
4164	* @param pCmdHlp Pointer to command helper functions.
4165	* @param pVM Pointer to the current VM (if any).
4166	* @param paArgs Pointer to (readonly) array of arguments.
4167	* @param cArgs Number of arguments in the array.
4168	*/
4169	static DECLCALLBACK(int) pgmR3CmdSyncAlways(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4170	{
4171	/*
4172	* Validate input.
4173	*/
4174	if (!pVM)
4175	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4176
4177	/*
4178	* Force page directory sync.
4179	*/
4180	if (pVM->pgm.s.fSyncFlags & PGM_SYNC_ALWAYS)
4181	{
4182	ASMAtomicAndU32(&pVM->pgm.s.fSyncFlags, ~PGM_SYNC_ALWAYS);
4183	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Disabled permanent forced page directory syncing.\n");
4184	}
4185	else
4186	{
4187	ASMAtomicOrU32(&pVM->pgm.s.fSyncFlags, PGM_SYNC_ALWAYS);
4188	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
4189	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Enabled permanent forced page directory syncing.\n");
4190	}
4191	}
4192
4193	#endif
4194
4195	/**
4196	* pvUser argument of the pgmR3CheckIntegrity*Node callbacks.
4197	*/
4198	typedef struct PGMCHECKINTARGS
4199	{
4200	bool fLeftToRight; /*< true: left-to-right; false: right-to-left. /
4201	PPGMPHYSHANDLER pPrevPhys;
4202	PPGMVIRTHANDLER pPrevVirt;
4203	PPGMPHYS2VIRTHANDLER pPrevPhys2Virt;
4204	PVM pVM;
4205	} PGMCHECKINTARGS, *PPGMCHECKINTARGS;
4206
4207	/**
4208	* Validate a node in the physical handler tree.
4209	*
4210	* @returns 0 on if ok, other wise 1.
4211	* @param pNode The handler node.
4212	* @param pvUser pVM.
4213	*/
4214	static DECLCALLBACK(int) pgmR3CheckIntegrityPhysHandlerNode(PAVLROGCPHYSNODECORE pNode, void *pvUser)
4215	{
4216	PPGMCHECKINTARGS pArgs = (PPGMCHECKINTARGS)pvUser;
4217	PPGMPHYSHANDLER pCur = (PPGMPHYSHANDLER)pNode;
4218	AssertReleaseReturn(!((uintptr_t)pCur & 7), 1);
4219	AssertReleaseMsg(pCur->Core.Key <= pCur->Core.KeyLast,("pCur=%p %VGp-%VGp %s\n", pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
4220	AssertReleaseMsg( !pArgs->pPrevPhys
4221	\|\| (pArgs->fLeftToRight ? pArgs->pPrevPhys->Core.KeyLast < pCur->Core.Key : pArgs->pPrevPhys->Core.KeyLast > pCur->Core.Key),
4222	("pPrevPhys=%p %VGp-%VGp %s\n"
4223	" pCur=%p %VGp-%VGp %s\n",
4224	pArgs->pPrevPhys, pArgs->pPrevPhys->Core.Key, pArgs->pPrevPhys->Core.KeyLast, pArgs->pPrevPhys->pszDesc,
4225	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
4226	pArgs->pPrevPhys = pCur;
4227	return 0;
4228	}
4229
4230
4231	/**
4232	* Validate a node in the virtual handler tree.
4233	*
4234	* @returns 0 on if ok, other wise 1.
4235	* @param pNode The handler node.
4236	* @param pvUser pVM.
4237	*/
4238	static DECLCALLBACK(int) pgmR3CheckIntegrityVirtHandlerNode(PAVLROGCPTRNODECORE pNode, void *pvUser)
4239	{
4240	PPGMCHECKINTARGS pArgs = (PPGMCHECKINTARGS)pvUser;
4241	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)pNode;
4242	AssertReleaseReturn(!((uintptr_t)pCur & 7), 1);
4243	AssertReleaseMsg(pCur->Core.Key <= pCur->Core.KeyLast,("pCur=%p %VGv-%VGv %s\n", pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
4244	AssertReleaseMsg( !pArgs->pPrevVirt
4245	\|\| (pArgs->fLeftToRight ? pArgs->pPrevVirt->Core.KeyLast < pCur->Core.Key : pArgs->pPrevVirt->Core.KeyLast > pCur->Core.Key),
4246	("pPrevVirt=%p %VGv-%VGv %s\n"
4247	" pCur=%p %VGv-%VGv %s\n",
4248	pArgs->pPrevVirt, pArgs->pPrevVirt->Core.Key, pArgs->pPrevVirt->Core.KeyLast, pArgs->pPrevVirt->pszDesc,
4249	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
4250	for (unsigned iPage = 0; iPage < pCur->cPages; iPage++)
4251	{
4252	AssertReleaseMsg(pCur->aPhysToVirt[iPage].offVirtHandler == -RT_OFFSETOF(PGMVIRTHANDLER, aPhysToVirt[iPage]),
4253	("pCur=%p %VGv-%VGv %s\n"
4254	"iPage=%d offVirtHandle=%#x expected %#x\n",
4255	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc,
4256	iPage, pCur->aPhysToVirt[iPage].offVirtHandler, -RT_OFFSETOF(PGMVIRTHANDLER, aPhysToVirt[iPage])));
4257	}
4258	pArgs->pPrevVirt = pCur;
4259	return 0;
4260	}
4261
4262
4263	/**
4264	* Validate a node in the virtual handler tree.
4265	*
4266	* @returns 0 on if ok, other wise 1.
4267	* @param pNode The handler node.
4268	* @param pvUser pVM.
4269	*/
4270	static DECLCALLBACK(int) pgmR3CheckIntegrityPhysToVirtHandlerNode(PAVLROGCPHYSNODECORE pNode, void *pvUser)
4271	{
4272	PPGMCHECKINTARGS pArgs = (PPGMCHECKINTARGS)pvUser;
4273	PPGMPHYS2VIRTHANDLER pCur = (PPGMPHYS2VIRTHANDLER)pNode;
4274	AssertReleaseMsgReturn(!((uintptr_t)pCur & 3), ("\n"), 1);
4275	AssertReleaseMsgReturn(!(pCur->offVirtHandler & 3), ("\n"), 1);
4276	AssertReleaseMsg(pCur->Core.Key <= pCur->Core.KeyLast,("pCur=%p %VGp-%VGp\n", pCur, pCur->Core.Key, pCur->Core.KeyLast));
4277	AssertReleaseMsg( !pArgs->pPrevPhys2Virt
4278	\|\| (pArgs->fLeftToRight ? pArgs->pPrevPhys2Virt->Core.KeyLast < pCur->Core.Key : pArgs->pPrevPhys2Virt->Core.KeyLast > pCur->Core.Key),
4279	("pPrevPhys2Virt=%p %VGp-%VGp\n"
4280	" pCur=%p %VGp-%VGp\n",
4281	pArgs->pPrevPhys2Virt, pArgs->pPrevPhys2Virt->Core.Key, pArgs->pPrevPhys2Virt->Core.KeyLast,
4282	pCur, pCur->Core.Key, pCur->Core.KeyLast));
4283	AssertReleaseMsg( !pArgs->pPrevPhys2Virt
4284	\|\| (pArgs->fLeftToRight ? pArgs->pPrevPhys2Virt->Core.KeyLast < pCur->Core.Key : pArgs->pPrevPhys2Virt->Core.KeyLast > pCur->Core.Key),
4285	("pPrevPhys2Virt=%p %VGp-%VGp\n"
4286	" pCur=%p %VGp-%VGp\n",
4287	pArgs->pPrevPhys2Virt, pArgs->pPrevPhys2Virt->Core.Key, pArgs->pPrevPhys2Virt->Core.KeyLast,
4288	pCur, pCur->Core.Key, pCur->Core.KeyLast));
4289	AssertReleaseMsg((pCur->offNextAlias & (PGMPHYS2VIRTHANDLER_IN_TREE \| PGMPHYS2VIRTHANDLER_IS_HEAD)) == (PGMPHYS2VIRTHANDLER_IN_TREE \| PGMPHYS2VIRTHANDLER_IS_HEAD),
4290	("pCur=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4291	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias));
4292	if (pCur->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK)
4293	{
4294	PPGMPHYS2VIRTHANDLER pCur2 = pCur;
4295	for (;;)
4296	{
4297	pCur2 = (PPGMPHYS2VIRTHANDLER)((intptr_t)pCur + (pCur->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK));
4298	AssertReleaseMsg(pCur2 != pCur,
4299	(" pCur=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4300	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias));
4301	AssertReleaseMsg((pCur2->offNextAlias & (PGMPHYS2VIRTHANDLER_IN_TREE \| PGMPHYS2VIRTHANDLER_IS_HEAD)) == PGMPHYS2VIRTHANDLER_IN_TREE,
4302	(" pCur=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
4303	"pCur2=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4304	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias,
4305	pCur2, pCur2->Core.Key, pCur2->Core.KeyLast, pCur2->offVirtHandler, pCur2->offNextAlias));
4306	AssertReleaseMsg((pCur2->Core.Key ^ pCur->Core.Key) < PAGE_SIZE,
4307	(" pCur=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
4308	"pCur2=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4309	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias,
4310	pCur2, pCur2->Core.Key, pCur2->Core.KeyLast, pCur2->offVirtHandler, pCur2->offNextAlias));
4311	AssertReleaseMsg((pCur2->Core.KeyLast ^ pCur->Core.KeyLast) < PAGE_SIZE,
4312	(" pCur=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
4313	"pCur2=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4314	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias,
4315	pCur2, pCur2->Core.Key, pCur2->Core.KeyLast, pCur2->offVirtHandler, pCur2->offNextAlias));
4316	if (!(pCur2->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK))
4317	break;
4318	}
4319	}
4320
4321	pArgs->pPrevPhys2Virt = pCur;
4322	return 0;
4323	}
4324
4325
4326	/**
4327	* Perform an integrity check on the PGM component.
4328	*
4329	* @returns VINF_SUCCESS if everything is fine.
4330	* @returns VBox error status after asserting on integrity breach.
4331	* @param pVM The VM handle.
4332	*/
4333	VMMR3DECL(int) PGMR3CheckIntegrity(PVM pVM)
4334	{
4335	AssertReleaseReturn(pVM->pgm.s.offVM, VERR_INTERNAL_ERROR);
4336
4337	/*
4338	* Check the trees.
4339	*/
4340	int cErrors = 0;
4341	const static PGMCHECKINTARGS s_LeftToRight = { true, NULL, NULL, NULL, pVM };
4342	const static PGMCHECKINTARGS s_RightToLeft = { false, NULL, NULL, NULL, pVM };
4343	PGMCHECKINTARGS Args = s_LeftToRight;
4344	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysHandlers, true, pgmR3CheckIntegrityPhysHandlerNode, &Args);
4345	Args = s_RightToLeft;
4346	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysHandlers, false, pgmR3CheckIntegrityPhysHandlerNode, &Args);
4347	Args = s_LeftToRight;
4348	cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesR3->VirtHandlers, true, pgmR3CheckIntegrityVirtHandlerNode, &Args);
4349	Args = s_RightToLeft;
4350	cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesR3->VirtHandlers, false, pgmR3CheckIntegrityVirtHandlerNode, &Args);
4351	Args = s_LeftToRight;
4352	cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesR3->HyperVirtHandlers, true, pgmR3CheckIntegrityVirtHandlerNode, &Args);
4353	Args = s_RightToLeft;
4354	cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesR3->HyperVirtHandlers, false, pgmR3CheckIntegrityVirtHandlerNode, &Args);
4355	Args = s_LeftToRight;
4356	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysToVirtHandlers, true, pgmR3CheckIntegrityPhysToVirtHandlerNode, &Args);
4357	Args = s_RightToLeft;
4358	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysToVirtHandlers, false, pgmR3CheckIntegrityPhysToVirtHandlerNode, &Args);
4359
4360	return !cErrors ? VINF_SUCCESS : VERR_INTERNAL_ERROR;
4361	}
4362
4363
4364	/**
4365	* Inform PGM if we want all mappings to be put into the shadow page table. (necessary for e.g. VMX)
4366	*
4367	* @returns VBox status code.
4368	* @param pVM VM handle.
4369	* @param fEnable Enable or disable shadow mappings
4370	*/
4371	VMMR3DECL(int) PGMR3ChangeShwPDMappings(PVM pVM, bool fEnable)
4372	{
4373	pVM->pgm.s.fDisableMappings = !fEnable;
4374
4375	uint32_t cb;
4376	int rc = PGMR3MappingsSize(pVM, &cb);
4377	AssertRCReturn(rc, rc);
4378
4379	/* Pretend the mappings are now fixed; to force a refresh of the reserved PDEs. */
4380	rc = PGMR3MappingsFix(pVM, MM_HYPER_AREA_ADDRESS, cb);
4381	AssertRCReturn(rc, rc);
4382
4383	return VINF_SUCCESS;
4384	}

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source: vbox/trunk/src/VBox/VMM/PGM.cpp@ 13071

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