PGM.cpp@ 13085

Last change on this file since 13085 was 13085, checked in by vboxsync, 16 years ago
#1865: More PGM changes.
Property svn:eol-style set to `native` Property svn:keywords set to `Id`
File size: 197.6 KB

Line
1	/* $Id: PGM.cpp 13085 2008-10-08 15:12:13Z vboxsync $ */
2	/** @file
3	* PGM - Page Manager and Monitor. (Mixing stuff here, not good?)
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22
23	/** @page pg_pgm PGM - The Page Manager and Monitor
24	*
25	* @see grp_pgm,
26	* @ref pg_pgm_pool,
27	* @ref pg_pgm_phys.
28	*
29	*
30	* @section sec_pgm_modes Paging Modes
31	*
32	* There are three memory contexts: Host Context (HC), Guest Context (GC)
33	* and intermediate context. When talking about paging HC can also be refered to
34	* as "host paging", and GC refered to as "shadow paging".
35	*
36	* We define three basic paging modes: 32-bit, PAE and AMD64. The host paging mode
37	* is defined by the host operating system. The mode used in the shadow paging mode
38	* depends on the host paging mode and what the mode the guest is currently in. The
39	* following relation between the two is defined:
40	*
41	* @verbatim
42	Host > 32-bit \| PAE \| AMD64 \|
43	Guest \| \| \| \|
44	==v================================
45	32-bit 32-bit PAE PAE
46	-------\|--------\|--------\|--------\|
47	PAE PAE PAE PAE
48	-------\|--------\|--------\|--------\|
49	AMD64 AMD64 AMD64 AMD64
50	-------\|--------\|--------\|--------\| @endverbatim
51	*
52	* All configuration except those in the diagonal (upper left) are expected to
53	* require special effort from the switcher (i.e. a bit slower).
54	*
55	*
56	*
57	*
58	* @section sec_pgm_shw The Shadow Memory Context
59	*
60	*
61	* [..]
62	*
63	* Because of guest context mappings requires PDPT and PML4 entries to allow
64	* writing on AMD64, the two upper levels will have fixed flags whatever the
65	* guest is thinking of using there. So, when shadowing the PD level we will
66	* calculate the effective flags of PD and all the higher levels. In legacy
67	* PAE mode this only applies to the PWT and PCD bits (the rest are
68	* ignored/reserved/MBZ). We will ignore those bits for the present.
69	*
70	*
71	*
72	* @section sec_pgm_int The Intermediate Memory Context
73	*
74	* The world switch goes thru an intermediate memory context which purpose it is
75	* to provide different mappings of the switcher code. All guest mappings are also
76	* present in this context.
77	*
78	* The switcher code is mapped at the same location as on the host, at an
79	* identity mapped location (physical equals virtual address), and at the
80	* hypervisor location.
81	*
82	* PGM maintain page tables for 32-bit, PAE and AMD64 paging modes. This
83	* simplifies switching guest CPU mode and consistency at the cost of more
84	* code to do the work. All memory use for those page tables is located below
85	* 4GB (this includes page tables for guest context mappings).
86	*
87	*
88	* @subsection subsec_pgm_int_gc Guest Context Mappings
89	*
90	* During assignment and relocation of a guest context mapping the intermediate
91	* memory context is used to verify the new location.
92	*
93	* Guest context mappings are currently restricted to below 4GB, for reasons
94	* of simplicity. This may change when we implement AMD64 support.
95	*
96	*
97	*
98	*
99	* @section sec_pgm_misc Misc
100	*
101	* @subsection subsec_pgm_misc_diff Differences Between Legacy PAE and Long Mode PAE
102	*
103	* The differences between legacy PAE and long mode PAE are:
104	* -# PDPE bits 1, 2, 5 and 6 are defined differently. In leagcy mode they are
105	* all marked down as must-be-zero, while in long mode 1, 2 and 5 have the
106	* usual meanings while 6 is ignored (AMD). This means that upon switching to
107	* legacy PAE mode we'll have to clear these bits and when going to long mode
108	* they must be set. This applies to both intermediate and shadow contexts,
109	* however we don't need to do it for the intermediate one since we're
110	* executing with CR0.WP at that time.
111	* -# CR3 allows a 32-byte aligned address in legacy mode, while in long mode
112	* a page aligned one is required.
113	*
114	*
115	* @section sec_pgm_handlers Access Handlers
116	*
117	* Placeholder.
118	*
119	*
120	* @subsection sec_pgm_handlers_virt Virtual Access Handlers
121	*
122	* Placeholder.
123	*
124	*
125	* @subsection sec_pgm_handlers_virt Virtual Access Handlers
126	*
127	* We currently implement three types of virtual access handlers: ALL, WRITE
128	* and HYPERVISOR (WRITE). See PGMVIRTHANDLERTYPE for some more details.
129	*
130	* The HYPERVISOR access handlers is kept in a separate tree since it doesn't apply
131	* to physical pages (PGMTREES::HyperVirtHandlers) and only needs to be consulted in
132	* a special \#PF case. The ALL and WRITE are in the PGMTREES::VirtHandlers tree, the
133	* rest of this section is going to be about these handlers.
134	*
135	* We'll go thru the life cycle of a handler and try make sense of it all, don't know
136	* how successfull this is gonna be...
137	*
138	* 1. A handler is registered thru the PGMR3HandlerVirtualRegister and
139	* PGMHandlerVirtualRegisterEx APIs. We check for conflicting virtual handlers
140	* and create a new node that is inserted into the AVL tree (range key). Then
141	* a full PGM resync is flagged (clear pool, sync cr3, update virtual bit of PGMPAGE).
142	*
143	* 2. The following PGMSyncCR3/SyncCR3 operation will first make invoke HandlerVirtualUpdate.
144	*
145	* 2a. HandlerVirtualUpdate will will lookup all the pages covered by virtual handlers
146	* via the current guest CR3 and update the physical page -> virtual handler
147	* translation. Needless to say, this doesn't exactly scale very well. If any changes
148	* are detected, it will flag a virtual bit update just like we did on registration.
149	* PGMPHYS pages with changes will have their virtual handler state reset to NONE.
150	*
151	* 2b. The virtual bit update process will iterate all the pages covered by all the
152	* virtual handlers and update the PGMPAGE virtual handler state to the max of all
153	* virtual handlers on that page.
154	*
155	* 2c. Back in SyncCR3 we will now flush the entire shadow page cache to make sure
156	* we don't miss any alias mappings of the monitored pages.
157	*
158	* 2d. SyncCR3 will then proceed with syncing the CR3 table.
159	*
160	* 3. \#PF(np,read) on a page in the range. This will cause it to be synced
161	* read-only and resumed if it's a WRITE handler. If it's an ALL handler we
162	* will call the handlers like in the next step. If the physical mapping has
163	* changed we will - some time in the future - perform a handler callback
164	* (optional) and update the physical -> virtual handler cache.
165	*
166	* 4. \#PF(,write) on a page in the range. This will cause the handler to
167	* be invoked.
168	*
169	* 5. The guest invalidates the page and changes the physical backing or
170	* unmaps it. This should cause the invalidation callback to be invoked
171	* (it might not yet be 100% perfect). Exactly what happens next... is
172	* this where we mess up and end up out of sync for a while?
173	*
174	* 6. The handler is deregistered by the client via PGMHandlerVirtualDeregister.
175	* We will then set all PGMPAGEs in the physical -> virtual handler cache for
176	* this handler to NONE and trigger a full PGM resync (basically the same
177	* as int step 1). Which means 2 is executed again.
178	*
179	*
180	* @subsubsection sub_sec_pgm_handler_virt_todo TODOs
181	*
182	* There is a bunch of things that needs to be done to make the virtual handlers
183	* work 100% correctly and work more efficiently.
184	*
185	* The first bit hasn't been implemented yet because it's going to slow the
186	* whole mess down even more, and besides it seems to be working reliably for
187	* our current uses. OTOH, some of the optimizations might end up more or less
188	* implementing the missing bits, so we'll see.
189	*
190	* On the optimization side, the first thing to do is to try avoid unnecessary
191	* cache flushing. Then try team up with the shadowing code to track changes
192	* in mappings by means of access to them (shadow in), updates to shadows pages,
193	* invlpg, and shadow PT discarding (perhaps).
194	*
195	* Some idea that have popped up for optimization for current and new features:
196	* - bitmap indicating where there are virtual handlers installed.
197	* (4KB => 220 pages, page 212 => covers 32-bit address space 1:1!)
198	* - Further optimize this by min/max (needs min/max avl getters).
199	* - Shadow page table entry bit (if any left)?
200	*
201	*/
202
203
204	/** @page pg_pgm_phys PGM Physical Guest Memory Management
205	*
206	*
207	* Objectives:
208	* - Guest RAM over-commitment using memory ballooning,
209	* zero pages and general page sharing.
210	* - Moving or mirroring a VM onto a different physical machine.
211	*
212	*
213	* @subsection subsec_pgmPhys_Definitions Definitions
214	*
215	* Allocation chunk - A RTR0MemObjAllocPhysNC object and the tracking
216	* machinery assoicated with it.
217	*
218	*
219	*
220	*
221	* @subsection subsec_pgmPhys_AllocPage Allocating a page.
222	*
223	* Initially we map all guest memory to the (per VM) zero page, which
224	* means that none of the read functions will cause pages to be allocated.
225	*
226	* Exception, access bit in page tables that have been shared. This must
227	* be handled, but we must also make sure PGMGst*Modify doesn't make
228	* unnecessary modifications.
229	*
230	* Allocation points:
231	* - PGMPhysWriteGCPhys and PGMPhysWrite.
232	* - Replacing a zero page mapping at \#PF.
233	* - Replacing a shared page mapping at \#PF.
234	* - ROM registration (currently MMR3RomRegister).
235	* - VM restore (pgmR3Load).
236	*
237	* For the first three it would make sense to keep a few pages handy
238	* until we've reached the max memory commitment for the VM.
239	*
240	* For the ROM registration, we know exactly how many pages we need
241	* and will request these from ring-0. For restore, we will save
242	* the number of non-zero pages in the saved state and allocate
243	* them up front. This would allow the ring-0 component to refuse
244	* the request if the isn't sufficient memory available for VM use.
245	*
246	* Btw. for both ROM and restore allocations we won't be requiring
247	* zeroed pages as they are going to be filled instantly.
248	*
249	*
250	* @subsection subsec_pgmPhys_FreePage Freeing a page
251	*
252	* There are a few points where a page can be freed:
253	* - After being replaced by the zero page.
254	* - After being replaced by a shared page.
255	* - After being ballooned by the guest additions.
256	* - At reset.
257	* - At restore.
258	*
259	* When freeing one or more pages they will be returned to the ring-0
260	* component and replaced by the zero page.
261	*
262	* The reasoning for clearing out all the pages on reset is that it will
263	* return us to the exact same state as on power on, and may thereby help
264	* us reduce the memory load on the system. Further it might have a
265	* (temporary) positive influence on memory fragmentation (@see subsec_pgmPhys_Fragmentation).
266	*
267	* On restore, as mention under the allocation topic, pages should be
268	* freed / allocated depending on how many is actually required by the
269	* new VM state. The simplest approach is to do like on reset, and free
270	* all non-ROM pages and then allocate what we need.
271	*
272	* A measure to prevent some fragmentation, would be to let each allocation
273	* chunk have some affinity towards the VM having allocated the most pages
274	* from it. Also, try make sure to allocate from allocation chunks that
275	* are almost full. Admittedly, both these measures might work counter to
276	* our intentions and its probably not worth putting a lot of effort,
277	* cpu time or memory into this.
278	*
279	*
280	* @subsection subsec_pgmPhys_SharePage Sharing a page
281	*
282	* The basic idea is that there there will be a idle priority kernel
283	* thread walking the non-shared VM pages hashing them and looking for
284	* pages with the same checksum. If such pages are found, it will compare
285	* them byte-by-byte to see if they actually are identical. If found to be
286	* identical it will allocate a shared page, copy the content, check that
287	* the page didn't change while doing this, and finally request both the
288	* VMs to use the shared page instead. If the page is all zeros (special
289	* checksum and byte-by-byte check) it will request the VM that owns it
290	* to replace it with the zero page.
291	*
292	* To make this efficient, we will have to make sure not to try share a page
293	* that will change its contents soon. This part requires the most work.
294	* A simple idea would be to request the VM to write monitor the page for
295	* a while to make sure it isn't modified any time soon. Also, it may
296	* make sense to skip pages that are being write monitored since this
297	* information is readily available to the thread if it works on the
298	* per-VM guest memory structures (presently called PGMRAMRANGE).
299	*
300	*
301	* @subsection subsec_pgmPhys_Fragmentation Fragmentation Concerns and Counter Measures
302	*
303	* The pages are organized in allocation chunks in ring-0, this is a necessity
304	* if we wish to have an OS agnostic approach to this whole thing. (On Linux we
305	* could easily work on a page-by-page basis if we liked. Whether this is possible
306	* or efficient on NT I don't quite know.) Fragmentation within these chunks may
307	* become a problem as part of the idea here is that we wish to return memory to
308	* the host system.
309	*
310	* For instance, starting two VMs at the same time, they will both allocate the
311	* guest memory on-demand and if permitted their page allocations will be
312	* intermixed. Shut down one of the two VMs and it will be difficult to return
313	* any memory to the host system because the page allocation for the two VMs are
314	* mixed up in the same allocation chunks.
315	*
316	* To further complicate matters, when pages are freed because they have been
317	* ballooned or become shared/zero the whole idea is that the page is supposed
318	* to be reused by another VM or returned to the host system. This will cause
319	* allocation chunks to contain pages belonging to different VMs and prevent
320	* returning memory to the host when one of those VM shuts down.
321	*
322	* The only way to really deal with this problem is to move pages. This can
323	* either be done at VM shutdown and or by the idle priority worker thread
324	* that will be responsible for finding sharable/zero pages. The mechanisms
325	* involved for coercing a VM to move a page (or to do it for it) will be
326	* the same as when telling it to share/zero a page.
327	*
328	*
329	* @subsection subsec_pgmPhys_Tracking Tracking Structures And Their Cost
330	*
331	* There's a difficult balance between keeping the per-page tracking structures
332	* (global and guest page) easy to use and keeping them from eating too much
333	* memory. We have limited virtual memory resources available when operating in
334	* 32-bit kernel space (on 64-bit there'll it's quite a different story). The
335	* tracking structures will be attemted designed such that we can deal with up
336	* to 32GB of memory on a 32-bit system and essentially unlimited on 64-bit ones.
337	*
338	*
339	* @subsubsection subsubsec_pgmPhys_Tracking_Kernel Kernel Space
340	*
341	* @see pg_GMM
342	*
343	* @subsubsection subsubsec_pgmPhys_Tracking_PerVM Per-VM
344	*
345	* Fixed info is the physical address of the page (HCPhys) and the page id
346	* (described above). Theoretically we'll need 48(-12) bits for the HCPhys part.
347	* Today we've restricting ourselves to 40(-12) bits because this is the current
348	* restrictions of all AMD64 implementations (I think Barcelona will up this
349	* to 48(-12) bits, not that it really matters) and I needed the bits for
350	* tracking mappings of a page. 48-12 = 36. That leaves 28 bits, which means a
351	* decent range for the page id: 2^(28+12) = 1024TB.
352	*
353	* In additions to these, we'll have to keep maintaining the page flags as we
354	* currently do. Although it wouldn't harm to optimize these quite a bit, like
355	* for instance the ROM shouldn't depend on having a write handler installed
356	* in order for it to become read-only. A RO/RW bit should be considered so
357	* that the page syncing code doesn't have to mess about checking multiple
358	* flag combinations (ROM \|\| RW handler \|\| write monitored) in order to
359	* figure out how to setup a shadow PTE. But this of course, is second
360	* priority at present. Current this requires 12 bits, but could probably
361	* be optimized to ~8.
362	*
363	* Then there's the 24 bits used to track which shadow page tables are
364	* currently mapping a page for the purpose of speeding up physical
365	* access handlers, and thereby the page pool cache. More bit for this
366	* purpose wouldn't hurt IIRC.
367	*
368	* Then there is a new bit in which we need to record what kind of page
369	* this is, shared, zero, normal or write-monitored-normal. This'll
370	* require 2 bits. One bit might be needed for indicating whether a
371	* write monitored page has been written to. And yet another one or
372	* two for tracking migration status. 3-4 bits total then.
373	*
374	* Whatever is left will can be used to record the sharabilitiy of a
375	* page. The page checksum will not be stored in the per-VM table as
376	* the idle thread will not be permitted to do modifications to it.
377	* It will instead have to keep its own working set of potentially
378	* shareable pages and their check sums and stuff.
379	*
380	* For the present we'll keep the current packing of the
381	* PGMRAMRANGE::aHCPhys to keep the changes simple, only of course,
382	* we'll have to change it to a struct with a total of 128-bits at
383	* our disposal.
384	*
385	* The initial layout will be like this:
386	* @verbatim
387	RTHCPHYS HCPhys; The current stuff.
388	63:40 Current shadow PT tracking stuff.
389	39:12 The physical page frame number.
390	11:0 The current flags.
391	uint32_t u28PageId : 28; The page id.
392	uint32_t u2State : 2; The page state { zero, shared, normal, write monitored }.
393	uint32_t fWrittenTo : 1; Whether a write monitored page was written to.
394	uint32_t u1Reserved : 1; Reserved for later.
395	uint32_t u32Reserved; Reserved for later, mostly sharing stats.
396	@endverbatim
397	*
398	* The final layout will be something like this:
399	* @verbatim
400	RTHCPHYS HCPhys; The current stuff.
401	63:48 High page id (12+).
402	47:12 The physical page frame number.
403	11:0 Low page id.
404	uint32_t fReadOnly : 1; Whether it's readonly page (rom or monitored in some way).
405	uint32_t u3Type : 3; The page type {RESERVED, MMIO, MMIO2, ROM, shadowed ROM, RAM}.
406	uint32_t u2PhysMon : 2; Physical access handler type {none, read, write, all}.
407	uint32_t u2VirtMon : 2; Virtual access handler type {none, read, write, all}..
408	uint32_t u2State : 2; The page state { zero, shared, normal, write monitored }.
409	uint32_t fWrittenTo : 1; Whether a write monitored page was written to.
410	uint32_t u20Reserved : 20; Reserved for later, mostly sharing stats.
411	uint32_t u32Tracking; The shadow PT tracking stuff, roughly.
412	@endverbatim
413	*
414	* Cost wise, this means we'll double the cost for guest memory. There isn't anyway
415	* around that I'm afraid. It means that the cost of dealing out 32GB of memory
416	* to one or more VMs is: (32GB >> PAGE_SHIFT) * 16 bytes, or 128MBs. Or another
417	* example, the VM heap cost when assigning 1GB to a VM will be: 4MB.
418	*
419	* A couple of cost examples for the total cost per-VM + kernel.
420	* 32-bit Windows and 32-bit linux:
421	* 1GB guest ram, 256K pages: 4MB + 2MB(+) = 6MB
422	* 4GB guest ram, 1M pages: 16MB + 8MB(+) = 24MB
423	* 32GB guest ram, 8M pages: 128MB + 64MB(+) = 192MB
424	* 64-bit Windows and 64-bit linux:
425	* 1GB guest ram, 256K pages: 4MB + 3MB(+) = 7MB
426	* 4GB guest ram, 1M pages: 16MB + 12MB(+) = 28MB
427	* 32GB guest ram, 8M pages: 128MB + 96MB(+) = 224MB
428	*
429	* UPDATE - 2007-09-27:
430	* Will need a ballooned flag/state too because we cannot
431	* trust the guest 100% and reporting the same page as ballooned more
432	* than once will put the GMM off balance.
433	*
434	*
435	* @subsection subsec_pgmPhys_Serializing Serializing Access
436	*
437	* Initially, we'll try a simple scheme:
438	*
439	* - The per-VM RAM tracking structures (PGMRAMRANGE) is only modified
440	* by the EMT thread of that VM while in the pgm critsect.
441	* - Other threads in the VM process that needs to make reliable use of
442	* the per-VM RAM tracking structures will enter the critsect.
443	* - No process external thread or kernel thread will ever try enter
444	* the pgm critical section, as that just won't work.
445	* - The idle thread (and similar threads) doesn't not need 100% reliable
446	* data when performing it tasks as the EMT thread will be the one to
447	* do the actual changes later anyway. So, as long as it only accesses
448	* the main ram range, it can do so by somehow preventing the VM from
449	* being destroyed while it works on it...
450	*
451	* - The over-commitment management, including the allocating/freeing
452	* chunks, is serialized by a ring-0 mutex lock (a fast one since the
453	* more mundane mutex implementation is broken on Linux).
454	* - A separeate mutex is protecting the set of allocation chunks so
455	* that pages can be shared or/and freed up while some other VM is
456	* allocating more chunks. This mutex can be take from under the other
457	* one, but not the otherway around.
458	*
459	*
460	* @subsection subsec_pgmPhys_Request VM Request interface
461	*
462	* When in ring-0 it will become necessary to send requests to a VM so it can
463	* for instance move a page while defragmenting during VM destroy. The idle
464	* thread will make use of this interface to request VMs to setup shared
465	* pages and to perform write monitoring of pages.
466	*
467	* I would propose an interface similar to the current VMReq interface, similar
468	* in that it doesn't require locking and that the one sending the request may
469	* wait for completion if it wishes to. This shouldn't be very difficult to
470	* realize.
471	*
472	* The requests themselves are also pretty simple. They are basically:
473	* -# Check that some precondition is still true.
474	* -# Do the update.
475	* -# Update all shadow page tables involved with the page.
476	*
477	* The 3rd step is identical to what we're already doing when updating a
478	* physical handler, see pgmHandlerPhysicalSetRamFlagsAndFlushShadowPTs.
479	*
480	*
481	*
482	* @section sec_pgmPhys_MappingCaches Mapping Caches
483	*
484	* In order to be able to map in and out memory and to be able to support
485	* guest with more RAM than we've got virtual address space, we'll employing
486	* a mapping cache. There is already a tiny one for GC (see PGMGCDynMapGCPageEx)
487	* and we'll create a similar one for ring-0 unless we decide to setup a dedicate
488	* memory context for the HWACCM execution.
489	*
490	*
491	* @subsection subsec_pgmPhys_MappingCaches_R3 Ring-3
492	*
493	* We've considered implementing the ring-3 mapping cache page based but found
494	* that this was bother some when one had to take into account TLBs+SMP and
495	* portability (missing the necessary APIs on several platforms). There were
496	* also some performance concerns with this approach which hadn't quite been
497	* worked out.
498	*
499	* Instead, we'll be mapping allocation chunks into the VM process. This simplifies
500	* matters greatly quite a bit since we don't need to invent any new ring-0 stuff,
501	* only some minor RTR0MEMOBJ mapping stuff. The main concern here is that mapping
502	* compared to the previous idea is that mapping or unmapping a 1MB chunk is more
503	* costly than a single page, although how much more costly is uncertain. We'll
504	* try address this by using a very big cache, preferably bigger than the actual
505	* VM RAM size if possible. The current VM RAM sizes should give some idea for
506	* 32-bit boxes, while on 64-bit we can probably get away with employing an
507	* unlimited cache.
508	*
509	* The cache have to parts, as already indicated, the ring-3 side and the
510	* ring-0 side.
511	*
512	* The ring-0 will be tied to the page allocator since it will operate on the
513	* memory objects it contains. It will therefore require the first ring-0 mutex
514	* discussed in @ref subsec_pgmPhys_Serializing. We
515	* some double house keeping wrt to who has mapped what I think, since both
516	* VMMR0.r0 and RTR0MemObj will keep track of mapping relataions
517	*
518	* The ring-3 part will be protected by the pgm critsect. For simplicity, we'll
519	* require anyone that desires to do changes to the mapping cache to do that
520	* from within this critsect. Alternatively, we could employ a separate critsect
521	* for serializing changes to the mapping cache as this would reduce potential
522	* contention with other threads accessing mappings unrelated to the changes
523	* that are in process. We can see about this later, contention will show
524	* up in the statistics anyway, so it'll be simple to tell.
525	*
526	* The organization of the ring-3 part will be very much like how the allocation
527	* chunks are organized in ring-0, that is in an AVL tree by chunk id. To avoid
528	* having to walk the tree all the time, we'll have a couple of lookaside entries
529	* like in we do for I/O ports and MMIO in IOM.
530	*
531	* The simplified flow of a PGMPhysRead/Write function:
532	* -# Enter the PGM critsect.
533	* -# Lookup GCPhys in the ram ranges and get the Page ID.
534	* -# Calc the Allocation Chunk ID from the Page ID.
535	* -# Check the lookaside entries and then the AVL tree for the Chunk ID.
536	* If not found in cache:
537	* -# Call ring-0 and request it to be mapped and supply
538	* a chunk to be unmapped if the cache is maxed out already.
539	* -# Insert the new mapping into the AVL tree (id + R3 address).
540	* -# Update the relevant lookaside entry and return the mapping address.
541	* -# Do the read/write according to monitoring flags and everything.
542	* -# Leave the critsect.
543	*
544	*
545	* @section sec_pgmPhys_Fallback Fallback
546	*
547	* Current all the "second tier" hosts will not support the RTR0MemObjAllocPhysNC
548	* API and thus require a fallback.
549	*
550	* So, when RTR0MemObjAllocPhysNC returns VERR_NOT_SUPPORTED the page allocator
551	* will return to the ring-3 caller (and later ring-0) and asking it to seed
552	* the page allocator with some fresh pages (VERR_GMM_SEED_ME). Ring-3 will
553	* then perform an SUPPageAlloc(cbChunk >> PAGE_SHIFT) call and make a
554	* "SeededAllocPages" call to ring-0.
555	*
556	* The first time ring-0 sees the VERR_NOT_SUPPORTED failure it will disable
557	* all page sharing (zero page detection will continue). It will also force
558	* all allocations to come from the VM which seeded the page. Both these
559	* measures are taken to make sure that there will never be any need for
560	* mapping anything into ring-3 - everything will be mapped already.
561	*
562	* Whether we'll continue to use the current MM locked memory management
563	* for this I don't quite know (I'd prefer not to and just ditch that all
564	* togther), we'll see what's simplest to do.
565	*
566	*
567	*
568	* @section sec_pgmPhys_Changes Changes
569	*
570	* Breakdown of the changes involved?
571	*/
572
573
574	/** Saved state data unit version. */
575	#define PGM_SAVED_STATE_VERSION 6
576
577	/*******************************************************************************
578	* Header Files *
579	*******************************************************************************/
580	#define LOG_GROUP LOG_GROUP_PGM
581	#include <VBox/dbgf.h>
582	#include <VBox/pgm.h>
583	#include <VBox/cpum.h>
584	#include <VBox/iom.h>
585	#include <VBox/sup.h>
586	#include <VBox/mm.h>
587	#include <VBox/em.h>
588	#include <VBox/stam.h>
589	#include <VBox/rem.h>
590	#include <VBox/dbgf.h>
591	#include <VBox/rem.h>
592	#include <VBox/selm.h>
593	#include <VBox/ssm.h>
594	#include "PGMInternal.h"
595	#include <VBox/vm.h>
596	#include <VBox/dbg.h>
597	#include <VBox/hwaccm.h>
598
599	#include <iprt/assert.h>
600	#include <iprt/alloc.h>
601	#include <iprt/asm.h>
602	#include <iprt/thread.h>
603	#include <iprt/string.h>
604	#include <VBox/param.h>
605	#include <VBox/err.h>
606
607
608
609	/*******************************************************************************
610	* Internal Functions *
611	*******************************************************************************/
612	static int pgmR3InitPaging(PVM pVM);
613	static DECLCALLBACK(void) pgmR3PhysInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
614	static DECLCALLBACK(void) pgmR3InfoMode(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
615	static DECLCALLBACK(void) pgmR3InfoCr3(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
616	static DECLCALLBACK(int) pgmR3RelocatePhysHandler(PAVLROGCPHYSNODECORE pNode, void *pvUser);
617	static DECLCALLBACK(int) pgmR3RelocateVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser);
618	static DECLCALLBACK(int) pgmR3RelocateHyperVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser);
619	#ifdef VBOX_STRICT
620	static DECLCALLBACK(void) pgmR3ResetNoMorePhysWritesFlag(PVM pVM, VMSTATE enmState, VMSTATE enmOldState, void *pvUser);
621	#endif
622	static DECLCALLBACK(int) pgmR3Save(PVM pVM, PSSMHANDLE pSSM);
623	static DECLCALLBACK(int) pgmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version);
624	static int pgmR3ModeDataInit(PVM pVM, bool fResolveGCAndR0);
625	static void pgmR3ModeDataSwitch(PVM pVM, PGMMODE enmShw, PGMMODE enmGst);
626	static PGMMODE pgmR3CalcShadowMode(PVM pVM, PGMMODE enmGuestMode, SUPPAGINGMODE enmHostMode, PGMMODE enmShadowMode, VMMSWITCHER *penmSwitcher);
627
628	#ifdef VBOX_WITH_STATISTICS
629	static void pgmR3InitStats(PVM pVM);
630	#endif
631
632	#ifdef VBOX_WITH_DEBUGGER
633	/** @todo all but the two last commands must be converted to 'info'. */
634	static DECLCALLBACK(int) pgmR3CmdRam(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
635	static DECLCALLBACK(int) pgmR3CmdMap(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
636	static DECLCALLBACK(int) pgmR3CmdSync(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
637	static DECLCALLBACK(int) pgmR3CmdSyncAlways(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
638	# ifdef VBOX_STRICT
639	static DECLCALLBACK(int) pgmR3CmdAssertCR3(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
640	# endif
641	#endif
642
643
644	/*******************************************************************************
645	* Global Variables *
646	*******************************************************************************/
647	#ifdef VBOX_WITH_DEBUGGER
648	/** Command descriptors. */
649	static const DBGCCMD g_aCmds[] =
650	{
651	/* pszCmd, cArgsMin, cArgsMax, paArgDesc, cArgDescs, pResultDesc, fFlags, pfnHandler pszSyntax, ....pszDescription */
652	{ "pgmram", 0, 0, NULL, 0, NULL, 0, pgmR3CmdRam, "", "Display the ram ranges." },
653	{ "pgmmap", 0, 0, NULL, 0, NULL, 0, pgmR3CmdMap, "", "Display the mapping ranges." },
654	{ "pgmsync", 0, 0, NULL, 0, NULL, 0, pgmR3CmdSync, "", "Sync the CR3 page." },
655	#ifdef VBOX_STRICT
656	{ "pgmassertcr3", 0, 0, NULL, 0, NULL, 0, pgmR3CmdAssertCR3, "", "Check the shadow CR3 mapping." },
657	#endif
658	{ "pgmsyncalways", 0, 0, NULL, 0, NULL, 0, pgmR3CmdSyncAlways, "", "Toggle permanent CR3 syncing." },
659	};
660	#endif
661
662
663
664
665	/*
666	* Shadow - 32-bit mode
667	*/
668	#define PGM_SHW_TYPE PGM_TYPE_32BIT
669	#define PGM_SHW_NAME(name) PGM_SHW_NAME_32BIT(name)
670	#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_32BIT_STR(name)
671	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_32BIT_STR(name)
672	#include "PGMShw.h"
673
674	/* Guest - real mode */
675	#define PGM_GST_TYPE PGM_TYPE_REAL
676	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
677	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_REAL_STR(name)
678	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
679	#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_REAL(name)
680	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_32BIT_REAL_STR(name)
681	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_32BIT_REAL_STR(name)
682	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_PHYS
683	#include "PGMGst.h"
684	#include "PGMBth.h"
685	#undef BTH_PGMPOOLKIND_PT_FOR_PT
686	#undef PGM_BTH_NAME
687	#undef PGM_BTH_NAME_RC_STR
688	#undef PGM_BTH_NAME_R0_STR
689	#undef PGM_GST_TYPE
690	#undef PGM_GST_NAME
691	#undef PGM_GST_NAME_RC_STR
692	#undef PGM_GST_NAME_R0_STR
693
694	/* Guest - protected mode */
695	#define PGM_GST_TYPE PGM_TYPE_PROT
696	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
697	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PROT_STR(name)
698	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
699	#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_PROT(name)
700	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_32BIT_PROT_STR(name)
701	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_32BIT_PROT_STR(name)
702	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_PHYS
703	#include "PGMGst.h"
704	#include "PGMBth.h"
705	#undef BTH_PGMPOOLKIND_PT_FOR_PT
706	#undef PGM_BTH_NAME
707	#undef PGM_BTH_NAME_RC_STR
708	#undef PGM_BTH_NAME_R0_STR
709	#undef PGM_GST_TYPE
710	#undef PGM_GST_NAME
711	#undef PGM_GST_NAME_RC_STR
712	#undef PGM_GST_NAME_R0_STR
713
714	/* Guest - 32-bit mode */
715	#define PGM_GST_TYPE PGM_TYPE_32BIT
716	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
717	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_32BIT_STR(name)
718	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
719	#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_32BIT(name)
720	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_32BIT_32BIT_STR(name)
721	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_32BIT_32BIT_STR(name)
722	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT
723	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB
724	#include "PGMGst.h"
725	#include "PGMBth.h"
726	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
727	#undef BTH_PGMPOOLKIND_PT_FOR_PT
728	#undef PGM_BTH_NAME
729	#undef PGM_BTH_NAME_RC_STR
730	#undef PGM_BTH_NAME_R0_STR
731	#undef PGM_GST_TYPE
732	#undef PGM_GST_NAME
733	#undef PGM_GST_NAME_RC_STR
734	#undef PGM_GST_NAME_R0_STR
735
736	#undef PGM_SHW_TYPE
737	#undef PGM_SHW_NAME
738	#undef PGM_SHW_NAME_RC_STR
739	#undef PGM_SHW_NAME_R0_STR
740
741
742	/*
743	* Shadow - PAE mode
744	*/
745	#define PGM_SHW_TYPE PGM_TYPE_PAE
746	#define PGM_SHW_NAME(name) PGM_SHW_NAME_PAE(name)
747	#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_PAE_STR(name)
748	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_PAE_STR(name)
749	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_REAL(name)
750	#include "PGMShw.h"
751
752	/* Guest - real mode */
753	#define PGM_GST_TYPE PGM_TYPE_REAL
754	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
755	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_REAL_STR(name)
756	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
757	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_REAL(name)
758	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_PAE_REAL_STR(name)
759	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_REAL_STR(name)
760	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
761	#include "PGMBth.h"
762	#undef BTH_PGMPOOLKIND_PT_FOR_PT
763	#undef PGM_BTH_NAME
764	#undef PGM_BTH_NAME_RC_STR
765	#undef PGM_BTH_NAME_R0_STR
766	#undef PGM_GST_TYPE
767	#undef PGM_GST_NAME
768	#undef PGM_GST_NAME_RC_STR
769	#undef PGM_GST_NAME_R0_STR
770
771	/* Guest - protected mode */
772	#define PGM_GST_TYPE PGM_TYPE_PROT
773	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
774	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PROT_STR(name)
775	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
776	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_PROT(name)
777	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_PAE_PROT_STR(name)
778	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_PROT_STR(name)
779	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
780	#include "PGMBth.h"
781	#undef BTH_PGMPOOLKIND_PT_FOR_PT
782	#undef PGM_BTH_NAME
783	#undef PGM_BTH_NAME_RC_STR
784	#undef PGM_BTH_NAME_R0_STR
785	#undef PGM_GST_TYPE
786	#undef PGM_GST_NAME
787	#undef PGM_GST_NAME_RC_STR
788	#undef PGM_GST_NAME_R0_STR
789
790	/* Guest - 32-bit mode */
791	#define PGM_GST_TYPE PGM_TYPE_32BIT
792	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
793	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_32BIT_STR(name)
794	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
795	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_32BIT(name)
796	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_PAE_32BIT_STR(name)
797	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_32BIT_STR(name)
798	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_32BIT_PT
799	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB
800	#include "PGMBth.h"
801	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
802	#undef BTH_PGMPOOLKIND_PT_FOR_PT
803	#undef PGM_BTH_NAME
804	#undef PGM_BTH_NAME_RC_STR
805	#undef PGM_BTH_NAME_R0_STR
806	#undef PGM_GST_TYPE
807	#undef PGM_GST_NAME
808	#undef PGM_GST_NAME_RC_STR
809	#undef PGM_GST_NAME_R0_STR
810
811	/* Guest - PAE mode */
812	#define PGM_GST_TYPE PGM_TYPE_PAE
813	#define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
814	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PAE_STR(name)
815	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PAE_STR(name)
816	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_PAE(name)
817	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_PAE_PAE_STR(name)
818	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_PAE_STR(name)
819	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
820	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
821	#include "PGMGst.h"
822	#include "PGMBth.h"
823	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
824	#undef BTH_PGMPOOLKIND_PT_FOR_PT
825	#undef PGM_BTH_NAME
826	#undef PGM_BTH_NAME_RC_STR
827	#undef PGM_BTH_NAME_R0_STR
828	#undef PGM_GST_TYPE
829	#undef PGM_GST_NAME
830	#undef PGM_GST_NAME_RC_STR
831	#undef PGM_GST_NAME_R0_STR
832
833	#undef PGM_SHW_TYPE
834	#undef PGM_SHW_NAME
835	#undef PGM_SHW_NAME_RC_STR
836	#undef PGM_SHW_NAME_R0_STR
837
838
839	/*
840	* Shadow - AMD64 mode
841	*/
842	#define PGM_SHW_TYPE PGM_TYPE_AMD64
843	#define PGM_SHW_NAME(name) PGM_SHW_NAME_AMD64(name)
844	#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_AMD64_STR(name)
845	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_AMD64_STR(name)
846	#include "PGMShw.h"
847
848	/* Guest - AMD64 mode */
849	#define PGM_GST_TYPE PGM_TYPE_AMD64
850	#define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
851	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_AMD64_STR(name)
852	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_AMD64_STR(name)
853	#define PGM_BTH_NAME(name) PGM_BTH_NAME_AMD64_AMD64(name)
854	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_AMD64_AMD64_STR(name)
855	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_AMD64_AMD64_STR(name)
856	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
857	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
858	#include "PGMGst.h"
859	#include "PGMBth.h"
860	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
861	#undef BTH_PGMPOOLKIND_PT_FOR_PT
862	#undef PGM_BTH_NAME
863	#undef PGM_BTH_NAME_RC_STR
864	#undef PGM_BTH_NAME_R0_STR
865	#undef PGM_GST_TYPE
866	#undef PGM_GST_NAME
867	#undef PGM_GST_NAME_RC_STR
868	#undef PGM_GST_NAME_R0_STR
869
870	#undef PGM_SHW_TYPE
871	#undef PGM_SHW_NAME
872	#undef PGM_SHW_NAME_RC_STR
873	#undef PGM_SHW_NAME_R0_STR
874
875	/*
876	* Shadow - Nested paging mode
877	*/
878	#define PGM_SHW_TYPE PGM_TYPE_NESTED
879	#define PGM_SHW_NAME(name) PGM_SHW_NAME_NESTED(name)
880	#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_NESTED_STR(name)
881	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_NESTED_STR(name)
882	#include "PGMShw.h"
883
884	/* Guest - real mode */
885	#define PGM_GST_TYPE PGM_TYPE_REAL
886	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
887	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_REAL_STR(name)
888	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
889	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_REAL(name)
890	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_REAL_STR(name)
891	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_REAL_STR(name)
892	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
893	#include "PGMBth.h"
894	#undef BTH_PGMPOOLKIND_PT_FOR_PT
895	#undef PGM_BTH_NAME
896	#undef PGM_BTH_NAME_RC_STR
897	#undef PGM_BTH_NAME_R0_STR
898	#undef PGM_GST_TYPE
899	#undef PGM_GST_NAME
900	#undef PGM_GST_NAME_RC_STR
901	#undef PGM_GST_NAME_R0_STR
902
903	/* Guest - protected mode */
904	#define PGM_GST_TYPE PGM_TYPE_PROT
905	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
906	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PROT_STR(name)
907	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
908	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_PROT(name)
909	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_PROT_STR(name)
910	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_PROT_STR(name)
911	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
912	#include "PGMBth.h"
913	#undef BTH_PGMPOOLKIND_PT_FOR_PT
914	#undef PGM_BTH_NAME
915	#undef PGM_BTH_NAME_RC_STR
916	#undef PGM_BTH_NAME_R0_STR
917	#undef PGM_GST_TYPE
918	#undef PGM_GST_NAME
919	#undef PGM_GST_NAME_RC_STR
920	#undef PGM_GST_NAME_R0_STR
921
922	/* Guest - 32-bit mode */
923	#define PGM_GST_TYPE PGM_TYPE_32BIT
924	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
925	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_32BIT_STR(name)
926	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
927	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_32BIT(name)
928	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_32BIT_STR(name)
929	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_32BIT_STR(name)
930	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_32BIT_PT
931	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB
932	#include "PGMBth.h"
933	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
934	#undef BTH_PGMPOOLKIND_PT_FOR_PT
935	#undef PGM_BTH_NAME
936	#undef PGM_BTH_NAME_RC_STR
937	#undef PGM_BTH_NAME_R0_STR
938	#undef PGM_GST_TYPE
939	#undef PGM_GST_NAME
940	#undef PGM_GST_NAME_RC_STR
941	#undef PGM_GST_NAME_R0_STR
942
943	/* Guest - PAE mode */
944	#define PGM_GST_TYPE PGM_TYPE_PAE
945	#define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
946	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PAE_STR(name)
947	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PAE_STR(name)
948	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_PAE(name)
949	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_PAE_STR(name)
950	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_PAE_STR(name)
951	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
952	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
953	#include "PGMBth.h"
954	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
955	#undef BTH_PGMPOOLKIND_PT_FOR_PT
956	#undef PGM_BTH_NAME
957	#undef PGM_BTH_NAME_RC_STR
958	#undef PGM_BTH_NAME_R0_STR
959	#undef PGM_GST_TYPE
960	#undef PGM_GST_NAME
961	#undef PGM_GST_NAME_RC_STR
962	#undef PGM_GST_NAME_R0_STR
963
964	/* Guest - AMD64 mode */
965	#define PGM_GST_TYPE PGM_TYPE_AMD64
966	#define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
967	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_AMD64_STR(name)
968	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_AMD64_STR(name)
969	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_AMD64(name)
970	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_AMD64_STR(name)
971	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_AMD64_STR(name)
972	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
973	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
974	#include "PGMBth.h"
975	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
976	#undef BTH_PGMPOOLKIND_PT_FOR_PT
977	#undef PGM_BTH_NAME
978	#undef PGM_BTH_NAME_RC_STR
979	#undef PGM_BTH_NAME_R0_STR
980	#undef PGM_GST_TYPE
981	#undef PGM_GST_NAME
982	#undef PGM_GST_NAME_RC_STR
983	#undef PGM_GST_NAME_R0_STR
984
985	#undef PGM_SHW_TYPE
986	#undef PGM_SHW_NAME
987	#undef PGM_SHW_NAME_RC_STR
988	#undef PGM_SHW_NAME_R0_STR
989
990	/*
991	* Shadow - EPT
992	*/
993	#define PGM_SHW_TYPE PGM_TYPE_EPT
994	#define PGM_SHW_NAME(name) PGM_SHW_NAME_EPT(name)
995	#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_EPT_STR(name)
996	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_EPT_STR(name)
997	#include "PGMShw.h"
998
999	/* Guest - real mode */
1000	#define PGM_GST_TYPE PGM_TYPE_REAL
1001	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
1002	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_REAL_STR(name)
1003	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
1004	#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_REAL(name)
1005	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_REAL_STR(name)
1006	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_REAL_STR(name)
1007	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
1008	#include "PGMBth.h"
1009	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1010	#undef PGM_BTH_NAME
1011	#undef PGM_BTH_NAME_RC_STR
1012	#undef PGM_BTH_NAME_R0_STR
1013	#undef PGM_GST_TYPE
1014	#undef PGM_GST_NAME
1015	#undef PGM_GST_NAME_RC_STR
1016	#undef PGM_GST_NAME_R0_STR
1017
1018	/* Guest - protected mode */
1019	#define PGM_GST_TYPE PGM_TYPE_PROT
1020	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
1021	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PROT_STR(name)
1022	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
1023	#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_PROT(name)
1024	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_PROT_STR(name)
1025	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_PROT_STR(name)
1026	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
1027	#include "PGMBth.h"
1028	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1029	#undef PGM_BTH_NAME
1030	#undef PGM_BTH_NAME_RC_STR
1031	#undef PGM_BTH_NAME_R0_STR
1032	#undef PGM_GST_TYPE
1033	#undef PGM_GST_NAME
1034	#undef PGM_GST_NAME_RC_STR
1035	#undef PGM_GST_NAME_R0_STR
1036
1037	/* Guest - 32-bit mode */
1038	#define PGM_GST_TYPE PGM_TYPE_32BIT
1039	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
1040	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_32BIT_STR(name)
1041	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
1042	#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_32BIT(name)
1043	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_32BIT_STR(name)
1044	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_32BIT_STR(name)
1045	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_32BIT_PT
1046	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB
1047	#include "PGMBth.h"
1048	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
1049	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1050	#undef PGM_BTH_NAME
1051	#undef PGM_BTH_NAME_RC_STR
1052	#undef PGM_BTH_NAME_R0_STR
1053	#undef PGM_GST_TYPE
1054	#undef PGM_GST_NAME
1055	#undef PGM_GST_NAME_RC_STR
1056	#undef PGM_GST_NAME_R0_STR
1057
1058	/* Guest - PAE mode */
1059	#define PGM_GST_TYPE PGM_TYPE_PAE
1060	#define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
1061	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PAE_STR(name)
1062	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PAE_STR(name)
1063	#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_PAE(name)
1064	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_PAE_STR(name)
1065	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_PAE_STR(name)
1066	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
1067	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
1068	#include "PGMBth.h"
1069	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
1070	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1071	#undef PGM_BTH_NAME
1072	#undef PGM_BTH_NAME_RC_STR
1073	#undef PGM_BTH_NAME_R0_STR
1074	#undef PGM_GST_TYPE
1075	#undef PGM_GST_NAME
1076	#undef PGM_GST_NAME_RC_STR
1077	#undef PGM_GST_NAME_R0_STR
1078
1079	/* Guest - AMD64 mode */
1080	#define PGM_GST_TYPE PGM_TYPE_AMD64
1081	#define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
1082	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_AMD64_STR(name)
1083	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_AMD64_STR(name)
1084	#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_AMD64(name)
1085	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_AMD64_STR(name)
1086	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_AMD64_STR(name)
1087	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
1088	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
1089	#include "PGMBth.h"
1090	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
1091	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1092	#undef PGM_BTH_NAME
1093	#undef PGM_BTH_NAME_RC_STR
1094	#undef PGM_BTH_NAME_R0_STR
1095	#undef PGM_GST_TYPE
1096	#undef PGM_GST_NAME
1097	#undef PGM_GST_NAME_RC_STR
1098	#undef PGM_GST_NAME_R0_STR
1099
1100	#undef PGM_SHW_TYPE
1101	#undef PGM_SHW_NAME
1102	#undef PGM_SHW_NAME_RC_STR
1103	#undef PGM_SHW_NAME_R0_STR
1104
1105	/**
1106	* Initiates the paging of VM.
1107	*
1108	* @returns VBox status code.
1109	* @param pVM Pointer to VM structure.
1110	*/
1111	VMMR3DECL(int) PGMR3Init(PVM pVM)
1112	{
1113	LogFlow(("PGMR3Init:\n"));
1114
1115	/*
1116	* Assert alignment and sizes.
1117	*/
1118	AssertRelease(sizeof(pVM->pgm.s) <= sizeof(pVM->pgm.padding));
1119
1120	/*
1121	* Init the structure.
1122	*/
1123	pVM->pgm.s.offVM = RT_OFFSETOF(VM, pgm.s);
1124	pVM->pgm.s.enmShadowMode = PGMMODE_INVALID;
1125	pVM->pgm.s.enmGuestMode = PGMMODE_INVALID;
1126	pVM->pgm.s.enmHostMode = SUPPAGINGMODE_INVALID;
1127	pVM->pgm.s.GCPhysCR3 = NIL_RTGCPHYS;
1128	pVM->pgm.s.GCPhysGstCR3Monitored = NIL_RTGCPHYS;
1129	pVM->pgm.s.fA20Enabled = true;
1130	pVM->pgm.s.GCPhys4MBPSEMask = RT_BIT_64(32) - 1; /* default; checked later */
1131	pVM->pgm.s.pGstPaePDPTHC = NULL;
1132	pVM->pgm.s.pGstPaePDPTGC = 0;
1133	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.apGstPaePDsHC); i++)
1134	{
1135	pVM->pgm.s.apGstPaePDsHC[i] = NULL;
1136	pVM->pgm.s.apGstPaePDsGC[i] = 0;
1137	pVM->pgm.s.aGCPhysGstPaePDs[i] = NIL_RTGCPHYS;
1138	pVM->pgm.s.aGCPhysGstPaePDsMonitored[i] = NIL_RTGCPHYS;
1139	}
1140
1141	#ifdef VBOX_STRICT
1142	VMR3AtStateRegister(pVM, pgmR3ResetNoMorePhysWritesFlag, NULL);
1143	#endif
1144
1145	/*
1146	* Get the configured RAM size - to estimate saved state size.
1147	*/
1148	uint64_t cbRam;
1149	int rc = CFGMR3QueryU64(CFGMR3GetRoot(pVM), "RamSize", &cbRam);
1150	if (rc == VERR_CFGM_VALUE_NOT_FOUND)
1151	cbRam = pVM->pgm.s.cbRamSize = 0;
1152	else if (VBOX_SUCCESS(rc))
1153	{
1154	if (cbRam < PAGE_SIZE)
1155	cbRam = 0;
1156	cbRam = RT_ALIGN_64(cbRam, PAGE_SIZE);
1157	pVM->pgm.s.cbRamSize = (RTUINT)cbRam;
1158	}
1159	else
1160	{
1161	AssertMsgFailed(("Configuration error: Failed to query integer \"RamSize\", rc=%Vrc.\n", rc));
1162	return rc;
1163	}
1164
1165	/*
1166	* Register saved state data unit.
1167	*/
1168	rc = SSMR3RegisterInternal(pVM, "pgm", 1, PGM_SAVED_STATE_VERSION, (size_t)cbRam + sizeof(PGM),
1169	NULL, pgmR3Save, NULL,
1170	NULL, pgmR3Load, NULL);
1171	if (VBOX_FAILURE(rc))
1172	return rc;
1173
1174	/*
1175	* Initialize the PGM critical section and flush the phys TLBs
1176	*/
1177	rc = PDMR3CritSectInit(pVM, &pVM->pgm.s.CritSect, "PGM");
1178	AssertRCReturn(rc, rc);
1179
1180	PGMR3PhysChunkInvalidateTLB(pVM);
1181	PGMPhysInvalidatePageR3MapTLB(pVM);
1182	PGMPhysInvalidatePageR0MapTLB(pVM);
1183	PGMPhysInvalidatePageGCMapTLB(pVM);
1184
1185	/*
1186	* Trees
1187	*/
1188	rc = MMHyperAlloc(pVM, sizeof(PGMTREES), 0, MM_TAG_PGM, (void **)&pVM->pgm.s.pTreesR3);
1189	if (VBOX_SUCCESS(rc))
1190	{
1191	pVM->pgm.s.pTreesR0 = MMHyperR3ToR0(pVM, pVM->pgm.s.pTreesR3);
1192	pVM->pgm.s.pTreesRC = MMHyperR3ToRC(pVM, pVM->pgm.s.pTreesR3);
1193
1194	/*
1195	* Alocate the zero page.
1196	*/
1197	rc = MMHyperAlloc(pVM, PAGE_SIZE, PAGE_SIZE, MM_TAG_PGM, &pVM->pgm.s.pvZeroPgR3);
1198	}
1199	if (VBOX_SUCCESS(rc))
1200	{
1201	pVM->pgm.s.pvZeroPgGC = MMHyperR3ToRC(pVM, pVM->pgm.s.pvZeroPgR3);
1202	pVM->pgm.s.pvZeroPgR0 = MMHyperR3ToR0(pVM, pVM->pgm.s.pvZeroPgR3);
1203	AssertRelease(pVM->pgm.s.pvZeroPgR0 != NIL_RTHCPHYS);
1204	pVM->pgm.s.HCPhysZeroPg = MMR3HyperHCVirt2HCPhys(pVM, pVM->pgm.s.pvZeroPgR3);
1205	AssertRelease(pVM->pgm.s.HCPhysZeroPg != NIL_RTHCPHYS);
1206
1207	/*
1208	* Init the paging.
1209	*/
1210	rc = pgmR3InitPaging(pVM);
1211	}
1212	if (VBOX_SUCCESS(rc))
1213	{
1214	/*
1215	* Init the page pool.
1216	*/
1217	rc = pgmR3PoolInit(pVM);
1218	}
1219	if (VBOX_SUCCESS(rc))
1220	{
1221	/*
1222	* Info & statistics
1223	*/
1224	DBGFR3InfoRegisterInternal(pVM, "mode",
1225	"Shows the current paging mode. "
1226	"Recognizes 'all', 'guest', 'shadow' and 'host' as arguments, defaulting to 'all' if nothing's given.",
1227	pgmR3InfoMode);
1228	DBGFR3InfoRegisterInternal(pVM, "pgmcr3",
1229	"Dumps all the entries in the top level paging table. No arguments.",
1230	pgmR3InfoCr3);
1231	DBGFR3InfoRegisterInternal(pVM, "phys",
1232	"Dumps all the physical address ranges. No arguments.",
1233	pgmR3PhysInfo);
1234	DBGFR3InfoRegisterInternal(pVM, "handlers",
1235	"Dumps physical, virtual and hyper virtual handlers. "
1236	"Pass 'phys', 'virt', 'hyper' as argument if only one kind is wanted."
1237	"Add 'nost' if the statistics are unwanted, use together with 'all' or explicit selection.",
1238	pgmR3InfoHandlers);
1239	DBGFR3InfoRegisterInternal(pVM, "mappings",
1240	"Dumps guest mappings.",
1241	pgmR3MapInfo);
1242
1243	STAM_REL_REG(pVM, &pVM->pgm.s.cGuestModeChanges, STAMTYPE_COUNTER, "/PGM/cGuestModeChanges", STAMUNIT_OCCURENCES, "Number of guest mode changes.");
1244	#ifdef VBOX_WITH_STATISTICS
1245	pgmR3InitStats(pVM);
1246	#endif
1247	#ifdef VBOX_WITH_DEBUGGER
1248	/*
1249	* Debugger commands.
1250	*/
1251	static bool fRegisteredCmds = false;
1252	if (!fRegisteredCmds)
1253	{
1254	int rc = DBGCRegisterCommands(&g_aCmds[0], RT_ELEMENTS(g_aCmds));
1255	if (VBOX_SUCCESS(rc))
1256	fRegisteredCmds = true;
1257	}
1258	#endif
1259	return VINF_SUCCESS;
1260	}
1261
1262	/* Almost no cleanup necessary, MM frees all memory. */
1263	PDMR3CritSectDelete(&pVM->pgm.s.CritSect);
1264
1265	return rc;
1266	}
1267
1268
1269	/**
1270	* Init paging.
1271	*
1272	* Since we need to check what mode the host is operating in before we can choose
1273	* the right paging functions for the host we have to delay this until R0 has
1274	* been initialized.
1275	*
1276	* @returns VBox status code.
1277	* @param pVM VM handle.
1278	*/
1279	static int pgmR3InitPaging(PVM pVM)
1280	{
1281	/*
1282	* Force a recalculation of modes and switcher so everyone gets notified.
1283	*/
1284	pVM->pgm.s.enmShadowMode = PGMMODE_INVALID;
1285	pVM->pgm.s.enmGuestMode = PGMMODE_INVALID;
1286	pVM->pgm.s.enmHostMode = SUPPAGINGMODE_INVALID;
1287
1288	/*
1289	* Allocate static mapping space for whatever the cr3 register
1290	* points to and in the case of PAE mode to the 4 PDs.
1291	*/
1292	int rc = MMR3HyperReserve(pVM, PAGE_SIZE * 5, "CR3 mapping", &pVM->pgm.s.GCPtrCR3Mapping);
1293	if (VBOX_FAILURE(rc))
1294	{
1295	AssertMsgFailed(("Failed to reserve two pages for cr mapping in HMA, rc=%Vrc\n", rc));
1296	return rc;
1297	}
1298	MMR3HyperReserve(pVM, PAGE_SIZE, "fence", NULL);
1299
1300	/*
1301	* Allocate pages for the three possible intermediate contexts
1302	* (AMD64, PAE and plain 32-Bit). We maintain all three contexts
1303	* for the sake of simplicity. The AMD64 uses the PAE for the
1304	* lower levels, making the total number of pages 11 (3 + 7 + 1).
1305	*
1306	* We assume that two page tables will be enought for the core code
1307	* mappings (HC virtual and identity).
1308	*/
1309	pVM->pgm.s.pInterPD = (PX86PD)MMR3PageAllocLow(pVM);
1310	pVM->pgm.s.apInterPTs[0] = (PX86PT)MMR3PageAllocLow(pVM);
1311	pVM->pgm.s.apInterPTs[1] = (PX86PT)MMR3PageAllocLow(pVM);
1312	pVM->pgm.s.apInterPaePTs[0] = (PX86PTPAE)MMR3PageAlloc(pVM);
1313	pVM->pgm.s.apInterPaePTs[1] = (PX86PTPAE)MMR3PageAlloc(pVM);
1314	pVM->pgm.s.apInterPaePDs[0] = (PX86PDPAE)MMR3PageAlloc(pVM);
1315	pVM->pgm.s.apInterPaePDs[1] = (PX86PDPAE)MMR3PageAlloc(pVM);
1316	pVM->pgm.s.apInterPaePDs[2] = (PX86PDPAE)MMR3PageAlloc(pVM);
1317	pVM->pgm.s.apInterPaePDs[3] = (PX86PDPAE)MMR3PageAlloc(pVM);
1318	pVM->pgm.s.pInterPaePDPT = (PX86PDPT)MMR3PageAllocLow(pVM);
1319	pVM->pgm.s.pInterPaePDPT64 = (PX86PDPT)MMR3PageAllocLow(pVM);
1320	pVM->pgm.s.pInterPaePML4 = (PX86PML4)MMR3PageAllocLow(pVM);
1321	if ( !pVM->pgm.s.pInterPD
1322	\|\| !pVM->pgm.s.apInterPTs[0]
1323	\|\| !pVM->pgm.s.apInterPTs[1]
1324	\|\| !pVM->pgm.s.apInterPaePTs[0]
1325	\|\| !pVM->pgm.s.apInterPaePTs[1]
1326	\|\| !pVM->pgm.s.apInterPaePDs[0]
1327	\|\| !pVM->pgm.s.apInterPaePDs[1]
1328	\|\| !pVM->pgm.s.apInterPaePDs[2]
1329	\|\| !pVM->pgm.s.apInterPaePDs[3]
1330	\|\| !pVM->pgm.s.pInterPaePDPT
1331	\|\| !pVM->pgm.s.pInterPaePDPT64
1332	\|\| !pVM->pgm.s.pInterPaePML4)
1333	{
1334	AssertMsgFailed(("Failed to allocate pages for the intermediate context!\n"));
1335	return VERR_NO_PAGE_MEMORY;
1336	}
1337
1338	pVM->pgm.s.HCPhysInterPD = MMPage2Phys(pVM, pVM->pgm.s.pInterPD);
1339	AssertRelease(pVM->pgm.s.HCPhysInterPD != NIL_RTHCPHYS && !(pVM->pgm.s.HCPhysInterPD & PAGE_OFFSET_MASK));
1340	pVM->pgm.s.HCPhysInterPaePDPT = MMPage2Phys(pVM, pVM->pgm.s.pInterPaePDPT);
1341	AssertRelease(pVM->pgm.s.HCPhysInterPaePDPT != NIL_RTHCPHYS && !(pVM->pgm.s.HCPhysInterPaePDPT & PAGE_OFFSET_MASK));
1342	pVM->pgm.s.HCPhysInterPaePML4 = MMPage2Phys(pVM, pVM->pgm.s.pInterPaePML4);
1343	AssertRelease(pVM->pgm.s.HCPhysInterPaePML4 != NIL_RTHCPHYS && !(pVM->pgm.s.HCPhysInterPaePML4 & PAGE_OFFSET_MASK));
1344
1345	/*
1346	* Initialize the pages, setting up the PML4 and PDPT for repetitive 4GB action.
1347	*/
1348	ASMMemZeroPage(pVM->pgm.s.pInterPD);
1349	ASMMemZeroPage(pVM->pgm.s.apInterPTs[0]);
1350	ASMMemZeroPage(pVM->pgm.s.apInterPTs[1]);
1351
1352	ASMMemZeroPage(pVM->pgm.s.apInterPaePTs[0]);
1353	ASMMemZeroPage(pVM->pgm.s.apInterPaePTs[1]);
1354
1355	ASMMemZeroPage(pVM->pgm.s.pInterPaePDPT);
1356	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.apInterPaePDs); i++)
1357	{
1358	ASMMemZeroPage(pVM->pgm.s.apInterPaePDs[i]);
1359	pVM->pgm.s.pInterPaePDPT->a[i].u = X86_PDPE_P \| PGM_PLXFLAGS_PERMANENT
1360	\| MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[i]);
1361	}
1362
1363	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.pInterPaePDPT64->a); i++)
1364	{
1365	const unsigned iPD = i % RT_ELEMENTS(pVM->pgm.s.apInterPaePDs);
1366	pVM->pgm.s.pInterPaePDPT64->a[i].u = X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_A \| PGM_PLXFLAGS_PERMANENT
1367	\| MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[iPD]);
1368	}
1369
1370	RTHCPHYS HCPhysInterPaePDPT64 = MMPage2Phys(pVM, pVM->pgm.s.pInterPaePDPT64);
1371	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.pInterPaePML4->a); i++)
1372	pVM->pgm.s.pInterPaePML4->a[i].u = X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_A \| PGM_PLXFLAGS_PERMANENT
1373	\| HCPhysInterPaePDPT64;
1374
1375	/*
1376	* Allocate pages for the three possible guest contexts (AMD64, PAE and plain 32-Bit).
1377	* We allocate pages for all three posibilities to in order to simplify mappings and
1378	* avoid resource failure during mode switches. So, we need to cover all levels of the
1379	* of the first 4GB down to PD level.
1380	* As with the intermediate context, AMD64 uses the PAE PDPT and PDs.
1381	*/
1382	pVM->pgm.s.pHC32BitPD = (PX86PD)MMR3PageAllocLow(pVM);
1383	pVM->pgm.s.apHCPaePDs[0] = (PX86PDPAE)MMR3PageAlloc(pVM);
1384	pVM->pgm.s.apHCPaePDs[1] = (PX86PDPAE)MMR3PageAlloc(pVM);
1385	AssertRelease((uintptr_t)pVM->pgm.s.apHCPaePDs[0] + PAGE_SIZE == (uintptr_t)pVM->pgm.s.apHCPaePDs[1]);
1386	pVM->pgm.s.apHCPaePDs[2] = (PX86PDPAE)MMR3PageAlloc(pVM);
1387	AssertRelease((uintptr_t)pVM->pgm.s.apHCPaePDs[1] + PAGE_SIZE == (uintptr_t)pVM->pgm.s.apHCPaePDs[2]);
1388	pVM->pgm.s.apHCPaePDs[3] = (PX86PDPAE)MMR3PageAlloc(pVM);
1389	AssertRelease((uintptr_t)pVM->pgm.s.apHCPaePDs[2] + PAGE_SIZE == (uintptr_t)pVM->pgm.s.apHCPaePDs[3]);
1390	pVM->pgm.s.pHCPaePDPT = (PX86PDPT)MMR3PageAllocLow(pVM);
1391	pVM->pgm.s.pHCNestedRoot = MMR3PageAllocLow(pVM);
1392
1393	if ( !pVM->pgm.s.pHC32BitPD
1394	\|\| !pVM->pgm.s.apHCPaePDs[0]
1395	\|\| !pVM->pgm.s.apHCPaePDs[1]
1396	\|\| !pVM->pgm.s.apHCPaePDs[2]
1397	\|\| !pVM->pgm.s.apHCPaePDs[3]
1398	\|\| !pVM->pgm.s.pHCPaePDPT
1399	\|\| !pVM->pgm.s.pHCNestedRoot)
1400	{
1401	AssertMsgFailed(("Failed to allocate pages for the intermediate context!\n"));
1402	return VERR_NO_PAGE_MEMORY;
1403	}
1404
1405	/* get physical addresses. */
1406	pVM->pgm.s.HCPhys32BitPD = MMPage2Phys(pVM, pVM->pgm.s.pHC32BitPD);
1407	Assert(MMPagePhys2Page(pVM, pVM->pgm.s.HCPhys32BitPD) == pVM->pgm.s.pHC32BitPD);
1408	pVM->pgm.s.aHCPhysPaePDs[0] = MMPage2Phys(pVM, pVM->pgm.s.apHCPaePDs[0]);
1409	pVM->pgm.s.aHCPhysPaePDs[1] = MMPage2Phys(pVM, pVM->pgm.s.apHCPaePDs[1]);
1410	pVM->pgm.s.aHCPhysPaePDs[2] = MMPage2Phys(pVM, pVM->pgm.s.apHCPaePDs[2]);
1411	pVM->pgm.s.aHCPhysPaePDs[3] = MMPage2Phys(pVM, pVM->pgm.s.apHCPaePDs[3]);
1412	pVM->pgm.s.HCPhysPaePDPT = MMPage2Phys(pVM, pVM->pgm.s.pHCPaePDPT);
1413	pVM->pgm.s.HCPhysNestedRoot = MMPage2Phys(pVM, pVM->pgm.s.pHCNestedRoot);
1414
1415	/*
1416	* Initialize the pages, setting up the PML4 and PDPT for action below 4GB.
1417	*/
1418	ASMMemZero32(pVM->pgm.s.pHC32BitPD, PAGE_SIZE);
1419	ASMMemZero32(pVM->pgm.s.pHCPaePDPT, PAGE_SIZE);
1420	ASMMemZero32(pVM->pgm.s.pHCNestedRoot, PAGE_SIZE);
1421	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.apHCPaePDs); i++)
1422	{
1423	ASMMemZero32(pVM->pgm.s.apHCPaePDs[i], PAGE_SIZE);
1424	pVM->pgm.s.pHCPaePDPT->a[i].u = X86_PDPE_P \| PGM_PLXFLAGS_PERMANENT \| pVM->pgm.s.aHCPhysPaePDs[i];
1425	/* The flags will be corrected when entering and leaving long mode. */
1426	}
1427
1428	CPUMSetHyperCR3(pVM, (uint32_t)pVM->pgm.s.HCPhys32BitPD);
1429
1430	/*
1431	* Initialize paging workers and mode from current host mode
1432	* and the guest running in real mode.
1433	*/
1434	pVM->pgm.s.enmHostMode = SUPGetPagingMode();
1435	switch (pVM->pgm.s.enmHostMode)
1436	{
1437	case SUPPAGINGMODE_32_BIT:
1438	case SUPPAGINGMODE_32_BIT_GLOBAL:
1439	case SUPPAGINGMODE_PAE:
1440	case SUPPAGINGMODE_PAE_GLOBAL:
1441	case SUPPAGINGMODE_PAE_NX:
1442	case SUPPAGINGMODE_PAE_GLOBAL_NX:
1443	break;
1444
1445	case SUPPAGINGMODE_AMD64:
1446	case SUPPAGINGMODE_AMD64_GLOBAL:
1447	case SUPPAGINGMODE_AMD64_NX:
1448	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
1449	#ifndef VBOX_WITH_HYBIRD_32BIT_KERNEL
1450	if (ARCH_BITS != 64)
1451	{
1452	AssertMsgFailed(("Host mode %d (64-bit) is not supported by non-64bit builds\n", pVM->pgm.s.enmHostMode));
1453	LogRel(("Host mode %d (64-bit) is not supported by non-64bit builds\n", pVM->pgm.s.enmHostMode));
1454	return VERR_PGM_UNSUPPORTED_HOST_PAGING_MODE;
1455	}
1456	#endif
1457	break;
1458	default:
1459	AssertMsgFailed(("Host mode %d is not supported\n", pVM->pgm.s.enmHostMode));
1460	return VERR_PGM_UNSUPPORTED_HOST_PAGING_MODE;
1461	}
1462	rc = pgmR3ModeDataInit(pVM, false /* don't resolve GC and R0 syms yet */);
1463	if (VBOX_SUCCESS(rc))
1464	rc = PGMR3ChangeMode(pVM, PGMMODE_REAL);
1465	if (VBOX_SUCCESS(rc))
1466	{
1467	LogFlow(("pgmR3InitPaging: returns successfully\n"));
1468	#if HC_ARCH_BITS == 64
1469	LogRel(("Debug: HCPhys32BitPD=%VHp aHCPhysPaePDs={%VHp,%VHp,%VHp,%VHp} HCPhysPaePDPT=%VHp HCPhysPaePML4=%VHp\n",
1470	pVM->pgm.s.HCPhys32BitPD, pVM->pgm.s.aHCPhysPaePDs[0], pVM->pgm.s.aHCPhysPaePDs[1], pVM->pgm.s.aHCPhysPaePDs[2], pVM->pgm.s.aHCPhysPaePDs[3],
1471	pVM->pgm.s.HCPhysPaePDPT, pVM->pgm.s.HCPhysPaePML4));
1472	LogRel(("Debug: HCPhysInterPD=%VHp HCPhysInterPaePDPT=%VHp HCPhysInterPaePML4=%VHp\n",
1473	pVM->pgm.s.HCPhysInterPD, pVM->pgm.s.HCPhysInterPaePDPT, pVM->pgm.s.HCPhysInterPaePML4));
1474	LogRel(("Debug: apInterPTs={%VHp,%VHp} apInterPaePTs={%VHp,%VHp} apInterPaePDs={%VHp,%VHp,%VHp,%VHp} pInterPaePDPT64=%VHp\n",
1475	MMPage2Phys(pVM, pVM->pgm.s.apInterPTs[0]), MMPage2Phys(pVM, pVM->pgm.s.apInterPTs[1]),
1476	MMPage2Phys(pVM, pVM->pgm.s.apInterPaePTs[0]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePTs[1]),
1477	MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[0]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[1]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[2]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[3]),
1478	MMPage2Phys(pVM, pVM->pgm.s.pInterPaePDPT64)));
1479	#endif
1480
1481	return VINF_SUCCESS;
1482	}
1483
1484	LogFlow(("pgmR3InitPaging: returns %Vrc\n", rc));
1485	return rc;
1486	}
1487
1488
1489	#ifdef VBOX_WITH_STATISTICS
1490	/**
1491	* Init statistics
1492	*/
1493	static void pgmR3InitStats(PVM pVM)
1494	{
1495	PPGM pPGM = &pVM->pgm.s;
1496
1497	/*
1498	* Note! The layout of this function matches the member layout exactly!
1499	*/
1500
1501	/* R3 only: */
1502
1503	/* GC only: */
1504	STAM_REG(pVM, &pPGM->StatGCInvalidatePage, STAMTYPE_PROFILE, "/PGM/GCInvalidatePage", STAMUNIT_TICKS_PER_CALL, "PGMGCInvalidatePage() profiling.");
1505
1506	/* RZ only: */
1507	STAM_REG(pVM, &pPGM->StatRZTrap0e, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMTrap0eHandler() body.");
1508	STAM_REG(pVM, &pPGM->StatRZTrap0eTimeCheckPageFault, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time/CheckPageFault", STAMUNIT_TICKS_PER_CALL, "Profiling of checking for dirty/access emulation faults.");
1509	STAM_REG(pVM, &pPGM->StatRZTrap0eTimeSyncPT, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time/SyncPT", STAMUNIT_TICKS_PER_CALL, "Profiling of lazy page table syncing.");
1510	STAM_REG(pVM, &pPGM->StatRZTrap0eTimeMapping, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time/Mapping", STAMUNIT_TICKS_PER_CALL, "Profiling of checking virtual mappings.");
1511	STAM_REG(pVM, &pPGM->StatRZTrap0eTimeOutOfSync, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time/OutOfSync", STAMUNIT_TICKS_PER_CALL, "Profiling of out of sync page handling.");
1512	STAM_REG(pVM, &pPGM->StatRZTrap0eTimeHandlers, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time/Handlers", STAMUNIT_TICKS_PER_CALL, "Profiling of checking handlers.");
1513	STAM_REG(pVM, &pPGM->StatRZTrap0eTime2CSAM, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time2/CSAM", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is CSAM.");
1514	STAM_REG(pVM, &pPGM->StatRZTrap0eTime2DirtyAndAccessed, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time2/DirtyAndAccessedBits", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is dirty and/or accessed bit emulation.");
1515	STAM_REG(pVM, &pPGM->StatRZTrap0eTime2GuestTrap, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time2/GuestTrap", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is a guest trap.");
1516	STAM_REG(pVM, &pPGM->StatRZTrap0eTime2HndPhys, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time2/HandlerPhysical", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is a physical handler.");
1517	STAM_REG(pVM, &pPGM->StatRZTrap0eTime2HndVirt, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time2/HandlerVirtual", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is a virtual handler.");
1518	STAM_REG(pVM, &pPGM->StatRZTrap0eTime2HndUnhandled, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time2/HandlerUnhandled", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is access outside the monitored areas of a monitored page.");
1519	STAM_REG(pVM, &pPGM->StatRZTrap0eTime2Misc, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time2/Misc", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is not known.");
1520	STAM_REG(pVM, &pPGM->StatRZTrap0eTime2OutOfSync, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time2/OutOfSync", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is an out-of-sync page.");
1521	STAM_REG(pVM, &pPGM->StatRZTrap0eTime2OutOfSyncHndPhys, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time2/OutOfSyncHndPhys", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is an out-of-sync physical handler page.");
1522	STAM_REG(pVM, &pPGM->StatRZTrap0eTime2OutOfSyncHndVirt, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time2/OutOfSyncHndVirt", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is an out-of-sync virtual handler page.");
1523	STAM_REG(pVM, &pPGM->StatRZTrap0eTime2OutOfSyncHndObs, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time2/OutOfSyncObsHnd", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is an obsolete handler page.");
1524	STAM_REG(pVM, &pPGM->StatRZTrap0eTime2SyncPT, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time2/SyncPT", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is lazy syncing of a PT.");
1525	STAM_REG(pVM, &pPGM->StatRZTrap0eConflicts, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Conflicts", STAMUNIT_OCCURENCES, "The number of times #PF was caused by an undetected conflict.");
1526	STAM_REG(pVM, &pPGM->StatRZTrap0eHandlersMapping, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Handlers/Mapping", STAMUNIT_OCCURENCES, "Number of traps due to access handlers in mappings.");
1527	STAM_REG(pVM, &pPGM->StatRZTrap0eHandlersOutOfSync, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Handlers/OutOfSync", STAMUNIT_OCCURENCES, "Number of traps due to out-of-sync handled pages.");
1528	STAM_REG(pVM, &pPGM->StatRZTrap0eHandlersPhysical, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Handlers/Physical", STAMUNIT_OCCURENCES, "Number of traps due to physical access handlers.");
1529	STAM_REG(pVM, &pPGM->StatRZTrap0eHandlersVirtual, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Handlers/Virtual", STAMUNIT_OCCURENCES, "Number of traps due to virtual access handlers.");
1530	STAM_REG(pVM, &pPGM->StatRZTrap0eHandlersVirtualByPhys, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Handlers/VirtualByPhys", STAMUNIT_OCCURENCES, "Number of traps due to virtual access handlers by physical address.");
1531	STAM_REG(pVM, &pPGM->StatRZTrap0eHandlersVirtualUnmarked,STAMTYPE_COUNTER,"/PGM/RZ/Trap0e/Handlers/VirtualUnmarked",STAMUNIT_OCCURENCES, "Number of traps due to virtual access handlers by virtual address (without proper physical flags).");
1532	STAM_REG(pVM, &pPGM->StatRZTrap0eHandlersUnhandled, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Handlers/Unhandled", STAMUNIT_OCCURENCES, "Number of traps due to access outside range of monitored page(s).");
1533	STAM_REG(pVM, &pPGM->StatRZTrap0eHandlersInvalid, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Handlers/Invalid", STAMUNIT_OCCURENCES, "Number of traps due to access to invalid physical memory.");
1534	STAM_REG(pVM, &pPGM->StatRZTrap0eUSNotPresentRead, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/User/NPRead", STAMUNIT_OCCURENCES, "Number of user mode not present read page faults.");
1535	STAM_REG(pVM, &pPGM->StatRZTrap0eUSNotPresentWrite, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/User/NPWrite", STAMUNIT_OCCURENCES, "Number of user mode not present write page faults.");
1536	STAM_REG(pVM, &pPGM->StatRZTrap0eUSWrite, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/User/Write", STAMUNIT_OCCURENCES, "Number of user mode write page faults.");
1537	STAM_REG(pVM, &pPGM->StatRZTrap0eUSReserved, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/User/Reserved", STAMUNIT_OCCURENCES, "Number of user mode reserved bit page faults.");
1538	STAM_REG(pVM, &pPGM->StatRZTrap0eUSNXE, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/User/NXE", STAMUNIT_OCCURENCES, "Number of user mode NXE page faults.");
1539	STAM_REG(pVM, &pPGM->StatRZTrap0eUSRead, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/User/Read", STAMUNIT_OCCURENCES, "Number of user mode read page faults.");
1540	STAM_REG(pVM, &pPGM->StatRZTrap0eSVNotPresentRead, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Supervisor/NPRead", STAMUNIT_OCCURENCES, "Number of supervisor mode not present read page faults.");
1541	STAM_REG(pVM, &pPGM->StatRZTrap0eSVNotPresentWrite, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Supervisor/NPWrite", STAMUNIT_OCCURENCES, "Number of supervisor mode not present write page faults.");
1542	STAM_REG(pVM, &pPGM->StatRZTrap0eSVWrite, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Supervisor/Write", STAMUNIT_OCCURENCES, "Number of supervisor mode write page faults.");
1543	STAM_REG(pVM, &pPGM->StatRZTrap0eSVReserved, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Supervisor/Reserved", STAMUNIT_OCCURENCES, "Number of supervisor mode reserved bit page faults.");
1544	STAM_REG(pVM, &pPGM->StatRZTrap0eSNXE, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Supervisor/NXE", STAMUNIT_OCCURENCES, "Number of supervisor mode NXE page faults.");
1545	STAM_REG(pVM, &pPGM->StatRZTrap0eGuestPF, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/GuestPF", STAMUNIT_OCCURENCES, "Number of real guest page faults.");
1546	STAM_REG(pVM, &pPGM->StatRZTrap0eGuestPFMapping, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/GuestPFInMapping", STAMUNIT_OCCURENCES, "Number of real guest page faults in a mapping.");
1547	STAM_REG(pVM, &pPGM->StatRZTrap0eWPEmulInRZ, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/WP/InRZ", STAMUNIT_OCCURENCES, "Number of guest page faults due to X86_CR0_WP emulation.");
1548	STAM_REG(pVM, &pPGM->StatRZTrap0eWPEmulToR3, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/WP/ToR3", STAMUNIT_OCCURENCES, "Number of guest page faults due to X86_CR0_WP emulation (forward to R3 for emulation).");
1549
1550	/* R0 only: */
1551
1552	/* RZ & R3: */
1553	STAM_REG(pVM, &pPGM->StatRZSyncCR3, STAMTYPE_PROFILE, "/PGM/RZ/SyncCR3", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMSyncCR3() body.");
1554	STAM_REG(pVM, &pPGM->StatRZSyncCR3Handlers, STAMTYPE_PROFILE, "/PGM/RZ/SyncCR3/Handlers", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMSyncCR3() update handler section.");
1555	STAM_REG(pVM, &pPGM->StatRZSyncCR3HandlerVirtualUpdate, STAMTYPE_PROFILE, "/PGM/RZ/SyncCR3/Handlers/VirtualUpdate", STAMUNIT_TICKS_PER_CALL, "Profiling of the virtual handler updates.");
1556	STAM_REG(pVM, &pPGM->StatRZSyncCR3HandlerVirtualReset, STAMTYPE_PROFILE, "/PGM/RZ/SyncCR3/Handlers/VirtualReset", STAMUNIT_TICKS_PER_CALL, "Profiling of the virtual handler resets.");
1557	STAM_REG(pVM, &pPGM->StatRZSyncCR3Global, STAMTYPE_COUNTER, "/PGM/RZ/SyncCR3/Global", STAMUNIT_OCCURENCES, "The number of global CR3 syncs.");
1558	STAM_REG(pVM, &pPGM->StatRZSyncCR3NotGlobal, STAMTYPE_COUNTER, "/PGM/RZ/SyncCR3/NotGlobal", STAMUNIT_OCCURENCES, "The number of non-global CR3 syncs.");
1559	STAM_REG(pVM, &pPGM->StatRZSyncCR3DstCacheHit, STAMTYPE_COUNTER, "/PGM/RZ/SyncCR3/DstChacheHit", STAMUNIT_OCCURENCES, "The number of times we got some kind of a cache hit.");
1560	STAM_REG(pVM, &pPGM->StatRZSyncCR3DstFreed, STAMTYPE_COUNTER, "/PGM/RZ/SyncCR3/DstFreed", STAMUNIT_OCCURENCES, "The number of times we've had to free a shadow entry.");
1561	STAM_REG(pVM, &pPGM->StatRZSyncCR3DstFreedSrcNP, STAMTYPE_COUNTER, "/PGM/RZ/SyncCR3/DstFreedSrcNP", STAMUNIT_OCCURENCES, "The number of times we've had to free a shadow entry for which the source entry was not present.");
1562	STAM_REG(pVM, &pPGM->StatRZSyncCR3DstNotPresent, STAMTYPE_COUNTER, "/PGM/RZ/SyncCR3/DstNotPresent", STAMUNIT_OCCURENCES, "The number of times we've encountered a not present shadow entry for a present guest entry.");
1563	STAM_REG(pVM, &pPGM->StatRZSyncCR3DstSkippedGlobalPD, STAMTYPE_COUNTER, "/PGM/RZ/SyncCR3/DstSkippedGlobalPD", STAMUNIT_OCCURENCES, "The number of times a global page directory wasn't flushed.");
1564	STAM_REG(pVM, &pPGM->StatRZSyncCR3DstSkippedGlobalPT, STAMTYPE_COUNTER, "/PGM/RZ/SyncCR3/DstSkippedGlobalPT", STAMUNIT_OCCURENCES, "The number of times a page table with only global entries wasn't flushed.");
1565	STAM_REG(pVM, &pPGM->StatRZSyncPT, STAMTYPE_PROFILE, "/PGM/RZ/SyncPT", STAMUNIT_TICKS_PER_CALL, "Profiling of the pfnSyncPT() body.");
1566	STAM_REG(pVM, &pPGM->StatRZSyncPTFailed, STAMTYPE_COUNTER, "/PGM/RZ/SyncPT/Failed", STAMUNIT_OCCURENCES, "The number of times pfnSyncPT() failed.");
1567	STAM_REG(pVM, &pPGM->StatRZSyncPagePDNAs, STAMTYPE_COUNTER, "/PGM/RZ/SyncPagePDNAs", STAMUNIT_OCCURENCES, "The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit.");
1568	STAM_REG(pVM, &pPGM->StatRZSyncPagePDOutOfSync, STAMTYPE_COUNTER, "/PGM/RZ/SyncPagePDOutOfSync", STAMUNIT_OCCURENCES, "The number of time we've encountered an out-of-sync PD in SyncPage.");
1569	STAM_REG(pVM, &pPGM->StatRZAccessedPage, STAMTYPE_COUNTER, "/PGM/RZ/AccessedPage", STAMUNIT_OCCURENCES, "The number of pages marked not present for accessed bit emulation.");
1570	STAM_REG(pVM, &pPGM->StatRZDirtyBitTracking, STAMTYPE_PROFILE, "/PGM/RZ/DirtyPage", STAMUNIT_TICKS_PER_CALL, "Profiling the dirty bit tracking in CheckPageFault().");
1571	STAM_REG(pVM, &pPGM->StatRZDirtyPage, STAMTYPE_COUNTER, "/PGM/RZ/DirtyPage/Mark", STAMUNIT_OCCURENCES, "The number of pages marked read-only for dirty bit tracking.");
1572	STAM_REG(pVM, &pPGM->StatRZDirtyPageBig, STAMTYPE_COUNTER, "/PGM/RZ/DirtyPage/MarkBig", STAMUNIT_OCCURENCES, "The number of 4MB pages marked read-only for dirty bit tracking.");
1573	STAM_REG(pVM, &pPGM->StatRZDirtyPageSkipped, STAMTYPE_COUNTER, "/PGM/RZ/DirtyPage/Skipped", STAMUNIT_OCCURENCES, "The number of pages already dirty or readonly.");
1574	STAM_REG(pVM, &pPGM->StatRZDirtyPageTrap, STAMTYPE_COUNTER, "/PGM/RZ/DirtyPage/Trap", STAMUNIT_OCCURENCES, "The number of traps generated for dirty bit tracking.");
1575	STAM_REG(pVM, &pPGM->StatRZDirtiedPage, STAMTYPE_COUNTER, "/PGM/RZ/DirtyPage/SetDirty", STAMUNIT_OCCURENCES, "The number of pages marked dirty because of write accesses.");
1576	STAM_REG(pVM, &pPGM->StatRZDirtyTrackRealPF, STAMTYPE_COUNTER, "/PGM/RZ/DirtyPage/RealPF", STAMUNIT_OCCURENCES, "The number of real pages faults during dirty bit tracking.");
1577	STAM_REG(pVM, &pPGM->StatRZPageAlreadyDirty, STAMTYPE_COUNTER, "/PGM/RZ/DirtyPage/AlreadySet", STAMUNIT_OCCURENCES, "The number of pages already marked dirty because of write accesses.");
1578	STAM_REG(pVM, &pPGM->StatRZInvalidatePage, STAMTYPE_PROFILE, "/PGM/RZ/InvalidatePage", STAMUNIT_TICKS_PER_CALL, "PGMInvalidatePage() profiling.");
1579	STAM_REG(pVM, &pPGM->StatRZInvalidatePage4KBPages, STAMTYPE_COUNTER, "/PGM/RZ/InvalidatePage/4KBPages", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was called for a 4KB page.");
1580	STAM_REG(pVM, &pPGM->StatRZInvalidatePage4MBPages, STAMTYPE_COUNTER, "/PGM/RZ/InvalidatePage/4MBPages", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was called for a 4MB page.");
1581	STAM_REG(pVM, &pPGM->StatRZInvalidatePage4MBPagesSkip, STAMTYPE_COUNTER, "/PGM/RZ/InvalidatePage/4MBPagesSkip",STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() skipped a 4MB page.");
1582	STAM_REG(pVM, &pPGM->StatRZInvalidatePagePDMappings, STAMTYPE_COUNTER, "/PGM/RZ/InvalidatePage/PDMappings", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict).");
1583	STAM_REG(pVM, &pPGM->StatRZInvalidatePagePDNAs, STAMTYPE_COUNTER, "/PGM/RZ/InvalidatePage/PDNAs", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was called for a not accessed page directory.");
1584	STAM_REG(pVM, &pPGM->StatRZInvalidatePagePDNPs, STAMTYPE_COUNTER, "/PGM/RZ/InvalidatePage/PDNPs", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was called for a not present page directory.");
1585	STAM_REG(pVM, &pPGM->StatRZInvalidatePagePDOutOfSync, STAMTYPE_COUNTER, "/PGM/RZ/InvalidatePage/PDOutOfSync", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was called for an out of sync page directory.");
1586	STAM_REG(pVM, &pPGM->StatRZInvalidatePageSkipped, STAMTYPE_COUNTER, "/PGM/RZ/InvalidatePage/Skipped", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3.");
1587	STAM_REG(pVM, &pPGM->StatRZVirtHandlerSearchByPhys, STAMTYPE_PROFILE, "/PGM/RZ/VirtHandlerSearchByPhys", STAMUNIT_TICKS_PER_CALL, "Profiling of pgmHandlerVirtualFindByPhysAddr.");
1588	STAM_REG(pVM, &pPGM->StatRZPhysHandlerReset, STAMTYPE_COUNTER, "/PGM/RZ/PhysHandlerReset", STAMUNIT_OCCURENCES, "The number of times PGMHandlerPhysicalReset is called.");
1589
1590	/* TODO: */
1591
1592
1593	STAM_REG(pVM, &pPGM->StatGCGuestCR3WriteHandled, STAMTYPE_COUNTER, "/PGM/GC/CR3WriteInt", STAMUNIT_OCCURENCES, "The number of times the Guest CR3 change was successfully handled.");
1594	STAM_REG(pVM, &pPGM->StatGCGuestCR3WriteUnhandled, STAMTYPE_COUNTER, "/PGM/GC/CR3WriteEmu", STAMUNIT_OCCURENCES, "The number of times the Guest CR3 change was passed back to the recompiler.");
1595	STAM_REG(pVM, &pPGM->StatGCGuestCR3WriteConflict, STAMTYPE_COUNTER, "/PGM/GC/CR3WriteConflict", STAMUNIT_OCCURENCES, "The number of times the Guest CR3 monitoring detected a conflict.");
1596
1597	STAM_REG(pVM, &pPGM->StatGCPageOutOfSyncSupervisor, STAMTYPE_COUNTER, "/PGM/GC/OutOfSync/SuperVisor", STAMUNIT_OCCURENCES, "Number of traps due to pages out of sync.");
1598	STAM_REG(pVM, &pPGM->StatGCPageOutOfSyncUser, STAMTYPE_COUNTER, "/PGM/GC/OutOfSync/User", STAMUNIT_OCCURENCES, "Number of traps due to pages out of sync.");
1599
1600	STAM_REG(pVM, &pPGM->StatGCGuestROMWriteHandled, STAMTYPE_COUNTER, "/PGM/GC/ROMWriteInt", STAMUNIT_OCCURENCES, "The number of times the Guest ROM change was successfully handled.");
1601	STAM_REG(pVM, &pPGM->StatGCGuestROMWriteUnhandled, STAMTYPE_COUNTER, "/PGM/GC/ROMWriteEmu", STAMUNIT_OCCURENCES, "The number of times the Guest ROM change was passed back to the recompiler.");
1602
1603	STAM_REG(pVM, &pPGM->StatDynMapCacheHits, STAMTYPE_COUNTER, "/PGM/GC/DynMapCache/Hits" , STAMUNIT_OCCURENCES, "Number of dynamic page mapping cache hits.");
1604	STAM_REG(pVM, &pPGM->StatDynMapCacheMisses, STAMTYPE_COUNTER, "/PGM/GC/DynMapCache/Misses" , STAMUNIT_OCCURENCES, "Number of dynamic page mapping cache misses.");
1605
1606	STAM_REG(pVM, &pPGM->StatHCDetectedConflicts, STAMTYPE_COUNTER, "/PGM/HC/DetectedConflicts", STAMUNIT_OCCURENCES, "The number of times PGMR3CheckMappingConflicts() detected a conflict.");
1607	STAM_REG(pVM, &pPGM->StatHCGuestPDWrite, STAMTYPE_COUNTER, "/PGM/HC/PDWrite", STAMUNIT_OCCURENCES, "The total number of times pgmHCGuestPDWriteHandler() was called.");
1608	STAM_REG(pVM, &pPGM->StatHCGuestPDWriteConflict, STAMTYPE_COUNTER, "/PGM/HC/PDWriteConflict", STAMUNIT_OCCURENCES, "The number of times pgmHCGuestPDWriteHandler() detected a conflict.");
1609
1610	STAM_REG(pVM, &pPGM->StatHCResolveConflict, STAMTYPE_PROFILE, "/PGM/HC/ResolveConflict", STAMUNIT_TICKS_PER_CALL, "pgmR3SyncPTResolveConflict() profiling (includes the entire relocation).");
1611	STAM_REG(pVM, &pPGM->StatHCPrefetch, STAMTYPE_PROFILE, "/PGM/HC/Prefetch", STAMUNIT_TICKS_PER_CALL, "PGMR3PrefetchPage profiling.");
1612
1613
1614
1615	STAM_REG(pVM, &pPGM->StatFlushTLB, STAMTYPE_PROFILE, "/PGM/FlushTLB", STAMUNIT_OCCURENCES, "Profiling of the PGMFlushTLB() body.");
1616	STAM_REG(pVM, &pPGM->StatFlushTLBNewCR3, STAMTYPE_COUNTER, "/PGM/FlushTLB/NewCR3", STAMUNIT_OCCURENCES, "The number of times PGMFlushTLB was called with a new CR3, non-global. (switch)");
1617	STAM_REG(pVM, &pPGM->StatFlushTLBNewCR3Global, STAMTYPE_COUNTER, "/PGM/FlushTLB/NewCR3Global", STAMUNIT_OCCURENCES, "The number of times PGMFlushTLB was called with a new CR3, global. (switch)");
1618	STAM_REG(pVM, &pPGM->StatFlushTLBSameCR3, STAMTYPE_COUNTER, "/PGM/FlushTLB/SameCR3", STAMUNIT_OCCURENCES, "The number of times PGMFlushTLB was called with the same CR3, non-global. (flush)");
1619	STAM_REG(pVM, &pPGM->StatFlushTLBSameCR3Global, STAMTYPE_COUNTER, "/PGM/FlushTLB/SameCR3Global", STAMUNIT_OCCURENCES, "The number of times PGMFlushTLB was called with the same CR3, global. (flush)");
1620
1621
1622	STAM_REG(pVM, &pPGM->StatHCGstModifyPage, STAMTYPE_PROFILE, "/PGM/HC/GstModifyPage", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMGstModifyPage() body.");
1623	STAM_REG(pVM, &pPGM->StatGCGstModifyPage, STAMTYPE_PROFILE, "/PGM/GC/GstModifyPage", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMGstModifyPage() body.");
1624
1625	STAM_REG(pVM, &pPGM->StatR3SyncPT, STAMTYPE_PROFILE, "/PGM/R3/SyncPT", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMR3SyncPT() body.");
1626	STAM_REG(pVM, &pPGM->StatSynPT4kGC, STAMTYPE_COUNTER, "/PGM/GC/SyncPT/4k", STAMUNIT_OCCURENCES, "Nr of 4k PT syncs");
1627	STAM_REG(pVM, &pPGM->StatSynPT4kHC, STAMTYPE_COUNTER, "/PGM/HC/SyncPT/4k", STAMUNIT_OCCURENCES, "Nr of 4k PT syncs");
1628	STAM_REG(pVM, &pPGM->StatSynPT4MGC, STAMTYPE_COUNTER, "/PGM/GC/SyncPT/4M", STAMUNIT_OCCURENCES, "Nr of 4M PT syncs");
1629	STAM_REG(pVM, &pPGM->StatSynPT4MHC, STAMTYPE_COUNTER, "/PGM/HC/SyncPT/4M", STAMUNIT_OCCURENCES, "Nr of 4M PT syncs");
1630
1631	STAM_REG(pVM, &pPGM->StatDynRamTotal, STAMTYPE_COUNTER, "/PGM/RAM/TotalAlloc", STAMUNIT_MEGABYTES, "Allocated mbs of guest ram.");
1632	STAM_REG(pVM, &pPGM->StatDynRamGrow, STAMTYPE_COUNTER, "/PGM/RAM/Grow", STAMUNIT_OCCURENCES, "Nr of pgmr3PhysGrowRange calls.");
1633
1634	STAM_REG(pVM, &pPGM->StatPageHCMapTlbHits, STAMTYPE_COUNTER, "/PGM/PageHCMap/TlbHits", STAMUNIT_OCCURENCES, "TLB hits.");
1635	STAM_REG(pVM, &pPGM->StatPageHCMapTlbMisses, STAMTYPE_COUNTER, "/PGM/PageHCMap/TlbMisses", STAMUNIT_OCCURENCES, "TLB misses.");
1636	STAM_REG(pVM, &pPGM->ChunkR3Map.c, STAMTYPE_U32, "/PGM/ChunkR3Map/c", STAMUNIT_OCCURENCES, "Number of mapped chunks.");
1637	STAM_REG(pVM, &pPGM->ChunkR3Map.cMax, STAMTYPE_U32, "/PGM/ChunkR3Map/cMax", STAMUNIT_OCCURENCES, "Maximum number of mapped chunks.");
1638	STAM_REG(pVM, &pPGM->StatChunkR3MapTlbHits, STAMTYPE_COUNTER, "/PGM/ChunkR3Map/TlbHits", STAMUNIT_OCCURENCES, "TLB hits.");
1639	STAM_REG(pVM, &pPGM->StatChunkR3MapTlbMisses, STAMTYPE_COUNTER, "/PGM/ChunkR3Map/TlbMisses", STAMUNIT_OCCURENCES, "TLB misses.");
1640	STAM_REG(pVM, &pPGM->StatPageReplaceShared, STAMTYPE_COUNTER, "/PGM/Page/ReplacedShared", STAMUNIT_OCCURENCES, "Times a shared page was replaced.");
1641	STAM_REG(pVM, &pPGM->StatPageReplaceZero, STAMTYPE_COUNTER, "/PGM/Page/ReplacedZero", STAMUNIT_OCCURENCES, "Times the zero page was replaced.");
1642	STAM_REG(pVM, &pPGM->StatPageHandyAllocs, STAMTYPE_COUNTER, "/PGM/Page/HandyAllocs", STAMUNIT_OCCURENCES, "Number of times we've allocated more handy pages.");
1643	STAM_REG(pVM, &pPGM->cAllPages, STAMTYPE_U32, "/PGM/Page/cAllPages", STAMUNIT_OCCURENCES, "The total number of pages.");
1644	STAM_REG(pVM, &pPGM->cPrivatePages, STAMTYPE_U32, "/PGM/Page/cPrivatePages", STAMUNIT_OCCURENCES, "The number of private pages.");
1645	STAM_REG(pVM, &pPGM->cSharedPages, STAMTYPE_U32, "/PGM/Page/cSharedPages", STAMUNIT_OCCURENCES, "The number of shared pages.");
1646	STAM_REG(pVM, &pPGM->cZeroPages, STAMTYPE_U32, "/PGM/Page/cZeroPages", STAMUNIT_OCCURENCES, "The number of zero backed pages.");
1647
1648	#ifdef PGMPOOL_WITH_GCPHYS_TRACKING
1649	STAM_REG(pVM, &pPGM->StatTrackVirgin, STAMTYPE_COUNTER, "/PGM/Track/Virgin", STAMUNIT_OCCURENCES, "The number of first time shadowings");
1650	STAM_REG(pVM, &pPGM->StatTrackAliased, STAMTYPE_COUNTER, "/PGM/Track/Aliased", STAMUNIT_OCCURENCES, "The number of times switching to cRef2, i.e. the page is being shadowed by two PTs.");
1651	STAM_REG(pVM, &pPGM->StatTrackAliasedMany, STAMTYPE_COUNTER, "/PGM/Track/AliasedMany", STAMUNIT_OCCURENCES, "The number of times we're tracking using cRef2.");
1652	STAM_REG(pVM, &pPGM->StatTrackAliasedLots, STAMTYPE_COUNTER, "/PGM/Track/AliasedLots", STAMUNIT_OCCURENCES, "The number of times we're hitting pages which has overflowed cRef2");
1653	STAM_REG(pVM, &pPGM->StatTrackOverflows, STAMTYPE_COUNTER, "/PGM/Track/Overflows", STAMUNIT_OCCURENCES, "The number of times the extent list grows to long.");
1654	STAM_REG(pVM, &pPGM->StatTrackDeref, STAMTYPE_PROFILE, "/PGM/Track/Deref", STAMUNIT_OCCURENCES, "Profiling of SyncPageWorkerTrackDeref (expensive).");
1655	#endif
1656
1657	for (unsigned i = 0; i < X86_PG_ENTRIES; i++)
1658	{
1659	/** @todo r=bird: We need a STAMR3RegisterF()! */
1660	char szName[32];
1661
1662	RTStrPrintf(szName, sizeof(szName), "/PGM/GC/PD/Trap0e/%04X", i);
1663	int rc = STAMR3Register(pVM, &pPGM->StatRZTrap0ePD[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, szName, STAMUNIT_OCCURENCES, "The number of traps in page directory n.");
1664	AssertRC(rc);
1665
1666	RTStrPrintf(szName, sizeof(szName), "/PGM/GC/PD/SyncPt/%04X", i);
1667	rc = STAMR3Register(pVM, &pPGM->StatGCSyncPtPD[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, szName, STAMUNIT_OCCURENCES, "The number of syncs per PD n.");
1668	AssertRC(rc);
1669
1670	RTStrPrintf(szName, sizeof(szName), "/PGM/GC/PD/SyncPage/%04X", i);
1671	rc = STAMR3Register(pVM, &pPGM->StatGCSyncPagePD[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, szName, STAMUNIT_OCCURENCES, "The number of out of sync pages per page directory n.");
1672	AssertRC(rc);
1673	}
1674	}
1675	#endif /* VBOX_WITH_STATISTICS */
1676
1677	/**
1678	* Init the PGM bits that rely on VMMR0 and MM to be fully initialized.
1679	*
1680	* The dynamic mapping area will also be allocated and initialized at this
1681	* time. We could allocate it during PGMR3Init of course, but the mapping
1682	* wouldn't be allocated at that time preventing us from setting up the
1683	* page table entries with the dummy page.
1684	*
1685	* @returns VBox status code.
1686	* @param pVM VM handle.
1687	*/
1688	VMMR3DECL(int) PGMR3InitDynMap(PVM pVM)
1689	{
1690	RTGCPTR GCPtr;
1691	/*
1692	* Reserve space for mapping the paging pages into guest context.
1693	*/
1694	int rc = MMR3HyperReserve(pVM, PAGE_SIZE * (2 + RT_ELEMENTS(pVM->pgm.s.apHCPaePDs) + 1 + 2 + 2), "Paging", &GCPtr);
1695	AssertRCReturn(rc, rc);
1696	pVM->pgm.s.pGC32BitPD = GCPtr;
1697	MMR3HyperReserve(pVM, PAGE_SIZE, "fence", NULL);
1698
1699	/*
1700	* Reserve space for the dynamic mappings.
1701	*/
1702	/** @todo r=bird: Need to verify that the checks for crossing PTs are correct here. They seems to be assuming 4MB PTs.. */
1703	rc = MMR3HyperReserve(pVM, MM_HYPER_DYNAMIC_SIZE, "Dynamic mapping", &GCPtr);
1704	if (VBOX_SUCCESS(rc))
1705	pVM->pgm.s.pbDynPageMapBaseGC = GCPtr;
1706
1707	if ( VBOX_SUCCESS(rc)
1708	&& (pVM->pgm.s.pbDynPageMapBaseGC >> X86_PD_SHIFT) != ((pVM->pgm.s.pbDynPageMapBaseGC + MM_HYPER_DYNAMIC_SIZE - 1) >> X86_PD_SHIFT))
1709	{
1710	rc = MMR3HyperReserve(pVM, MM_HYPER_DYNAMIC_SIZE, "Dynamic mapping not crossing", &GCPtr);
1711	if (VBOX_SUCCESS(rc))
1712	pVM->pgm.s.pbDynPageMapBaseGC = GCPtr;
1713	}
1714	if (VBOX_SUCCESS(rc))
1715	{
1716	AssertRelease((pVM->pgm.s.pbDynPageMapBaseGC >> X86_PD_SHIFT) == ((pVM->pgm.s.pbDynPageMapBaseGC + MM_HYPER_DYNAMIC_SIZE - 1) >> X86_PD_SHIFT));
1717	MMR3HyperReserve(pVM, PAGE_SIZE, "fence", NULL);
1718	}
1719	return rc;
1720	}
1721
1722
1723	/**
1724	* Ring-3 init finalizing.
1725	*
1726	* @returns VBox status code.
1727	* @param pVM The VM handle.
1728	*/
1729	VMMR3DECL(int) PGMR3InitFinalize(PVM pVM)
1730	{
1731	/*
1732	* Map the paging pages into the guest context.
1733	*/
1734	RTGCPTR GCPtr = pVM->pgm.s.pGC32BitPD;
1735	AssertReleaseReturn(GCPtr, VERR_INTERNAL_ERROR);
1736
1737	int rc = PGMMap(pVM, GCPtr, pVM->pgm.s.HCPhys32BitPD, PAGE_SIZE, 0);
1738	AssertRCReturn(rc, rc);
1739	pVM->pgm.s.pGC32BitPD = GCPtr;
1740	GCPtr += PAGE_SIZE;
1741	GCPtr += PAGE_SIZE; /* reserved page */
1742
1743	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.apHCPaePDs); i++)
1744	{
1745	rc = PGMMap(pVM, GCPtr, pVM->pgm.s.aHCPhysPaePDs[i], PAGE_SIZE, 0);
1746	AssertRCReturn(rc, rc);
1747	pVM->pgm.s.apGCPaePDs[i] = GCPtr;
1748	GCPtr += PAGE_SIZE;
1749	}
1750	/* A bit of paranoia is justified. */
1751	AssertRelease((RTGCUINTPTR)pVM->pgm.s.apGCPaePDs[0] + PAGE_SIZE == (RTGCUINTPTR)pVM->pgm.s.apGCPaePDs[1]);
1752	AssertRelease((RTGCUINTPTR)pVM->pgm.s.apGCPaePDs[1] + PAGE_SIZE == (RTGCUINTPTR)pVM->pgm.s.apGCPaePDs[2]);
1753	AssertRelease((RTGCUINTPTR)pVM->pgm.s.apGCPaePDs[2] + PAGE_SIZE == (RTGCUINTPTR)pVM->pgm.s.apGCPaePDs[3]);
1754	GCPtr += PAGE_SIZE; /* reserved page */
1755
1756	rc = PGMMap(pVM, GCPtr, pVM->pgm.s.HCPhysPaePDPT, PAGE_SIZE, 0);
1757	AssertRCReturn(rc, rc);
1758	pVM->pgm.s.pGCPaePDPT = GCPtr;
1759	GCPtr += PAGE_SIZE;
1760	GCPtr += PAGE_SIZE; /* reserved page */
1761
1762
1763	/*
1764	* Reserve space for the dynamic mappings.
1765	* Initialize the dynamic mapping pages with dummy pages to simply the cache.
1766	*/
1767	/* get the pointer to the page table entries. */
1768	PPGMMAPPING pMapping = pgmGetMapping(pVM, pVM->pgm.s.pbDynPageMapBaseGC);
1769	AssertRelease(pMapping);
1770	const uintptr_t off = pVM->pgm.s.pbDynPageMapBaseGC - pMapping->GCPtr;
1771	const unsigned iPT = off >> X86_PD_SHIFT;
1772	const unsigned iPG = (off >> X86_PT_SHIFT) & X86_PT_MASK;
1773	pVM->pgm.s.paDynPageMap32BitPTEsGC = pMapping->aPTs[iPT].pPTRC + iPG * sizeof(pMapping->aPTs[0].pPTR3->a[0]);
1774	pVM->pgm.s.paDynPageMapPaePTEsGC = pMapping->aPTs[iPT].paPaePTsRC + iPG * sizeof(pMapping->aPTs[0].paPaePTsR3->a[0]);
1775
1776	/* init cache */
1777	RTHCPHYS HCPhysDummy = MMR3PageDummyHCPhys(pVM);
1778	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.aHCPhysDynPageMapCache); i++)
1779	pVM->pgm.s.aHCPhysDynPageMapCache[i] = HCPhysDummy;
1780
1781	for (unsigned i = 0; i < MM_HYPER_DYNAMIC_SIZE; i += PAGE_SIZE)
1782	{
1783	rc = PGMMap(pVM, pVM->pgm.s.pbDynPageMapBaseGC + i, HCPhysDummy, PAGE_SIZE, 0);
1784	AssertRCReturn(rc, rc);
1785	}
1786
1787	/* Note that AMD uses all the 8 reserved bits for the address (so 40 bits in total); Intel only goes up to 36 bits, so
1788	* we stick to 36 as well.
1789	*
1790	* @todo How to test for the 40 bits support? Long mode seems to be the test criterium.
1791	*/
1792	uint32_t u32Dummy, u32Features;
1793	CPUMGetGuestCpuId(pVM, 1, &u32Dummy, &u32Dummy, &u32Dummy, &u32Features);
1794
1795	if (u32Features & X86_CPUID_FEATURE_EDX_PSE36)
1796	pVM->pgm.s.GCPhys4MBPSEMask = RT_BIT_64(36) - 1;
1797	else
1798	pVM->pgm.s.GCPhys4MBPSEMask = RT_BIT_64(32) - 1;
1799
1800	LogRel(("PGMR3InitFinalize: 4 MB PSE mask %VGp\n", pVM->pgm.s.GCPhys4MBPSEMask));
1801
1802	return rc;
1803	}
1804
1805
1806	/**
1807	* Applies relocations to data and code managed by this
1808	* component. This function will be called at init and
1809	* whenever the VMM need to relocate it self inside the GC.
1810	*
1811	* @param pVM The VM.
1812	* @param offDelta Relocation delta relative to old location.
1813	*/
1814	VMMR3DECL(void) PGMR3Relocate(PVM pVM, RTGCINTPTR offDelta)
1815	{
1816	LogFlow(("PGMR3Relocate\n"));
1817
1818	/*
1819	* Paging stuff.
1820	*/
1821	pVM->pgm.s.GCPtrCR3Mapping += offDelta;
1822	/** @todo move this into shadow and guest specific relocation functions. */
1823	AssertMsg(pVM->pgm.s.pGC32BitPD, ("Init order, no relocation before paging is initialized!\n"));
1824	pVM->pgm.s.pGC32BitPD += offDelta;
1825	pVM->pgm.s.pGuestPDGC += offDelta;
1826	AssertCompile(RT_ELEMENTS(pVM->pgm.s.apGCPaePDs) == RT_ELEMENTS(pVM->pgm.s.apGstPaePDsGC));
1827	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.apGCPaePDs); i++)
1828	{
1829	pVM->pgm.s.apGCPaePDs[i] += offDelta;
1830	pVM->pgm.s.apGstPaePDsGC[i] += offDelta;
1831	}
1832	pVM->pgm.s.pGstPaePDPTGC += offDelta;
1833	pVM->pgm.s.pGCPaePDPT += offDelta;
1834
1835	pgmR3ModeDataInit(pVM, true /* resolve GC/R0 symbols */);
1836	pgmR3ModeDataSwitch(pVM, pVM->pgm.s.enmShadowMode, pVM->pgm.s.enmGuestMode);
1837
1838	PGM_SHW_PFN(Relocate, pVM)(pVM, offDelta);
1839	PGM_GST_PFN(Relocate, pVM)(pVM, offDelta);
1840	PGM_BTH_PFN(Relocate, pVM)(pVM, offDelta);
1841
1842	/*
1843	* Trees.
1844	*/
1845	pVM->pgm.s.pTreesRC = MMHyperR3ToRC(pVM, pVM->pgm.s.pTreesR3);
1846
1847	/*
1848	* Ram ranges.
1849	*/
1850	if (pVM->pgm.s.pRamRangesR3)
1851	{
1852	pVM->pgm.s.pRamRangesRC = MMHyperR3ToRC(pVM, pVM->pgm.s.pRamRangesR3);
1853	for (PPGMRAMRANGE pCur = pVM->pgm.s.pRamRangesR3; pCur->pNextR3; pCur = pCur->pNextR3)
1854	pCur->pNextRC = MMHyperR3ToRC(pVM, pCur->pNextR3);
1855	}
1856
1857	/*
1858	* Update the two page directories with all page table mappings.
1859	* (One or more of them have changed, that's why we're here.)
1860	*/
1861	pVM->pgm.s.pMappingsRC = MMHyperR3ToRC(pVM, pVM->pgm.s.pMappingsR3);
1862	for (PPGMMAPPING pCur = pVM->pgm.s.pMappingsR3; pCur->pNextR3; pCur = pCur->pNextR3)
1863	pCur->pNextRC = MMHyperR3ToRC(pVM, pCur->pNextR3);
1864
1865	/* Relocate GC addresses of Page Tables. */
1866	for (PPGMMAPPING pCur = pVM->pgm.s.pMappingsR3; pCur; pCur = pCur->pNextR3)
1867	{
1868	for (RTHCUINT i = 0; i < pCur->cPTs; i++)
1869	{
1870	pCur->aPTs[i].pPTRC = MMHyperR3ToRC(pVM, pCur->aPTs[i].pPTR3);
1871	pCur->aPTs[i].paPaePTsRC = MMHyperR3ToRC(pVM, pCur->aPTs[i].paPaePTsR3);
1872	}
1873	}
1874
1875	/*
1876	* Dynamic page mapping area.
1877	*/
1878	pVM->pgm.s.paDynPageMap32BitPTEsGC += offDelta;
1879	pVM->pgm.s.paDynPageMapPaePTEsGC += offDelta;
1880	pVM->pgm.s.pbDynPageMapBaseGC += offDelta;
1881
1882	/*
1883	* The Zero page.
1884	*/
1885	pVM->pgm.s.pvZeroPgR0 = MMHyperR3ToR0(pVM, pVM->pgm.s.pvZeroPgR3);
1886	AssertRelease(pVM->pgm.s.pvZeroPgR0);
1887
1888	/*
1889	* Physical and virtual handlers.
1890	*/
1891	RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysHandlers, true, pgmR3RelocatePhysHandler, &offDelta);
1892	RTAvlroGCPtrDoWithAll(&pVM->pgm.s.pTreesR3->VirtHandlers, true, pgmR3RelocateVirtHandler, &offDelta);
1893	RTAvlroGCPtrDoWithAll(&pVM->pgm.s.pTreesR3->HyperVirtHandlers, true, pgmR3RelocateHyperVirtHandler, &offDelta);
1894
1895	/*
1896	* The page pool.
1897	*/
1898	pgmR3PoolRelocate(pVM);
1899	}
1900
1901
1902	/**
1903	* Callback function for relocating a physical access handler.
1904	*
1905	* @returns 0 (continue enum)
1906	* @param pNode Pointer to a PGMPHYSHANDLER node.
1907	* @param pvUser Pointer to the offDelta. This is a pointer to the delta since we're
1908	* not certain the delta will fit in a void pointer for all possible configs.
1909	*/
1910	static DECLCALLBACK(int) pgmR3RelocatePhysHandler(PAVLROGCPHYSNODECORE pNode, void *pvUser)
1911	{
1912	PPGMPHYSHANDLER pHandler = (PPGMPHYSHANDLER)pNode;
1913	RTGCINTPTR offDelta = *(PRTGCINTPTR)pvUser;
1914	if (pHandler->pfnHandlerRC)
1915	pHandler->pfnHandlerRC += offDelta;
1916	if (pHandler->pvUserRC >= 0x10000)
1917	pHandler->pvUserRC += offDelta;
1918	return 0;
1919	}
1920
1921
1922	/**
1923	* Callback function for relocating a virtual access handler.
1924	*
1925	* @returns 0 (continue enum)
1926	* @param pNode Pointer to a PGMVIRTHANDLER node.
1927	* @param pvUser Pointer to the offDelta. This is a pointer to the delta since we're
1928	* not certain the delta will fit in a void pointer for all possible configs.
1929	*/
1930	static DECLCALLBACK(int) pgmR3RelocateVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser)
1931	{
1932	PPGMVIRTHANDLER pHandler = (PPGMVIRTHANDLER)pNode;
1933	RTGCINTPTR offDelta = *(PRTGCINTPTR)pvUser;
1934	Assert( pHandler->enmType == PGMVIRTHANDLERTYPE_ALL
1935	\|\| pHandler->enmType == PGMVIRTHANDLERTYPE_WRITE);
1936	Assert(pHandler->pfnHandlerRC);
1937	pHandler->pfnHandlerRC += offDelta;
1938	return 0;
1939	}
1940
1941
1942	/**
1943	* Callback function for relocating a virtual access handler for the hypervisor mapping.
1944	*
1945	* @returns 0 (continue enum)
1946	* @param pNode Pointer to a PGMVIRTHANDLER node.
1947	* @param pvUser Pointer to the offDelta. This is a pointer to the delta since we're
1948	* not certain the delta will fit in a void pointer for all possible configs.
1949	*/
1950	static DECLCALLBACK(int) pgmR3RelocateHyperVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser)
1951	{
1952	PPGMVIRTHANDLER pHandler = (PPGMVIRTHANDLER)pNode;
1953	RTGCINTPTR offDelta = *(PRTGCINTPTR)pvUser;
1954	Assert(pHandler->enmType == PGMVIRTHANDLERTYPE_HYPERVISOR);
1955	Assert(pHandler->pfnHandlerRC);
1956	pHandler->pfnHandlerRC += offDelta;
1957	return 0;
1958	}
1959
1960
1961	/**
1962	* The VM is being reset.
1963	*
1964	* For the PGM component this means that any PD write monitors
1965	* needs to be removed.
1966	*
1967	* @param pVM VM handle.
1968	*/
1969	VMMR3DECL(void) PGMR3Reset(PVM pVM)
1970	{
1971	LogFlow(("PGMR3Reset:\n"));
1972	VM_ASSERT_EMT(pVM);
1973
1974	pgmLock(pVM);
1975
1976	/*
1977	* Unfix any fixed mappings and disable CR3 monitoring.
1978	*/
1979	pVM->pgm.s.fMappingsFixed = false;
1980	pVM->pgm.s.GCPtrMappingFixed = 0;
1981	pVM->pgm.s.cbMappingFixed = 0;
1982
1983	/* Exit the guest paging mode before the pgm pool gets reset.
1984	* Important to clean up the amd64 case.
1985	*/
1986	int rc = PGM_GST_PFN(Exit, pVM)(pVM);
1987	AssertRC(rc);
1988	#ifdef DEBUG
1989	DBGFR3InfoLog(pVM, "mappings", NULL);
1990	DBGFR3InfoLog(pVM, "handlers", "all nostat");
1991	#endif
1992
1993	/*
1994	* Reset the shadow page pool.
1995	*/
1996	pgmR3PoolReset(pVM);
1997
1998	/*
1999	* Re-init other members.
2000	*/
2001	pVM->pgm.s.fA20Enabled = true;
2002
2003	/*
2004	* Clear the FFs PGM owns.
2005	*/
2006	VM_FF_CLEAR(pVM, VM_FF_PGM_SYNC_CR3);
2007	VM_FF_CLEAR(pVM, VM_FF_PGM_SYNC_CR3_NON_GLOBAL);
2008
2009	/*
2010	* Reset (zero) RAM pages.
2011	*/
2012	rc = pgmR3PhysRamReset(pVM);
2013	if (RT_SUCCESS(rc))
2014	{
2015	#ifdef VBOX_WITH_NEW_PHYS_CODE
2016	/*
2017	* Reset (zero) shadow ROM pages.
2018	*/
2019	rc = pgmR3PhysRomReset(pVM);
2020	#endif
2021	if (RT_SUCCESS(rc))
2022	{
2023	/*
2024	* Switch mode back to real mode.
2025	*/
2026	rc = PGMR3ChangeMode(pVM, PGMMODE_REAL);
2027	STAM_REL_COUNTER_RESET(&pVM->pgm.s.cGuestModeChanges);
2028	}
2029	}
2030
2031	pgmUnlock(pVM);
2032	//return rc;
2033	AssertReleaseRC(rc);
2034	}
2035
2036
2037	#ifdef VBOX_STRICT
2038	/**
2039	* VM state change callback for clearing fNoMorePhysWrites after
2040	* a snapshot has been created.
2041	*/
2042	static DECLCALLBACK(void) pgmR3ResetNoMorePhysWritesFlag(PVM pVM, VMSTATE enmState, VMSTATE enmOldState, void *pvUser)
2043	{
2044	if (enmState == VMSTATE_RUNNING)
2045	pVM->pgm.s.fNoMorePhysWrites = false;
2046	}
2047	#endif
2048
2049
2050	/**
2051	* Terminates the PGM.
2052	*
2053	* @returns VBox status code.
2054	* @param pVM Pointer to VM structure.
2055	*/
2056	VMMR3DECL(int) PGMR3Term(PVM pVM)
2057	{
2058	return PDMR3CritSectDelete(&pVM->pgm.s.CritSect);
2059	}
2060
2061
2062	/**
2063	* Execute state save operation.
2064	*
2065	* @returns VBox status code.
2066	* @param pVM VM Handle.
2067	* @param pSSM SSM operation handle.
2068	*/
2069	static DECLCALLBACK(int) pgmR3Save(PVM pVM, PSSMHANDLE pSSM)
2070	{
2071	PPGM pPGM = &pVM->pgm.s;
2072
2073	/* No more writes to physical memory after this point! */
2074	pVM->pgm.s.fNoMorePhysWrites = true;
2075
2076	/*
2077	* Save basic data (required / unaffected by relocation).
2078	*/
2079	#if 1
2080	SSMR3PutBool(pSSM, pPGM->fMappingsFixed);
2081	#else
2082	SSMR3PutUInt(pSSM, pPGM->fMappingsFixed);
2083	#endif
2084	SSMR3PutGCPtr(pSSM, pPGM->GCPtrMappingFixed);
2085	SSMR3PutU32(pSSM, pPGM->cbMappingFixed);
2086	SSMR3PutUInt(pSSM, pPGM->cbRamSize);
2087	SSMR3PutGCPhys(pSSM, pPGM->GCPhysA20Mask);
2088	SSMR3PutUInt(pSSM, pPGM->fA20Enabled);
2089	SSMR3PutUInt(pSSM, pPGM->fSyncFlags);
2090	SSMR3PutUInt(pSSM, pPGM->enmGuestMode);
2091	SSMR3PutU32(pSSM, ~0); /* Separator. */
2092
2093	/*
2094	* The guest mappings.
2095	*/
2096	uint32_t i = 0;
2097	for (PPGMMAPPING pMapping = pPGM->pMappingsR3; pMapping; pMapping = pMapping->pNextR3, i++)
2098	{
2099	SSMR3PutU32(pSSM, i);
2100	SSMR3PutStrZ(pSSM, pMapping->pszDesc); /* This is the best unique id we have... */
2101	SSMR3PutGCPtr(pSSM, pMapping->GCPtr);
2102	SSMR3PutGCUIntPtr(pSSM, pMapping->cPTs);
2103	/* flags are done by the mapping owners! */
2104	}
2105	SSMR3PutU32(pSSM, ~0); /* terminator. */
2106
2107	/*
2108	* Ram range flags and bits.
2109	*/
2110	i = 0;
2111	for (PPGMRAMRANGE pRam = pPGM->pRamRangesR3; pRam; pRam = pRam->pNextR3, i++)
2112	{
2113	/** @todo MMIO ranges may move (PCI reconfig), we currently assume they don't. */
2114
2115	SSMR3PutU32(pSSM, i);
2116	SSMR3PutGCPhys(pSSM, pRam->GCPhys);
2117	SSMR3PutGCPhys(pSSM, pRam->GCPhysLast);
2118	SSMR3PutGCPhys(pSSM, pRam->cb);
2119	SSMR3PutU8(pSSM, !!pRam->pvR3); /* boolean indicating memory or not. */
2120
2121	/* Flags. */
2122	const unsigned cPages = pRam->cb >> PAGE_SHIFT;
2123	for (unsigned iPage = 0; iPage < cPages; iPage++)
2124	SSMR3PutU16(pSSM, (uint16_t)(pRam->aPages[iPage].HCPhys & ~X86_PTE_PAE_PG_MASK)); /** @todo PAGE FLAGS */
2125
2126	/* any memory associated with the range. */
2127	if (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)
2128	{
2129	for (unsigned iChunk = 0; iChunk < (pRam->cb >> PGM_DYNAMIC_CHUNK_SHIFT); iChunk++)
2130	{
2131	if (pRam->paChunkR3Ptrs[iChunk])
2132	{
2133	SSMR3PutU8(pSSM, 1); /* chunk present */
2134	SSMR3PutMem(pSSM, (void *)pRam->paChunkR3Ptrs[iChunk], PGM_DYNAMIC_CHUNK_SIZE);
2135	}
2136	else
2137	SSMR3PutU8(pSSM, 0); /* no chunk present */
2138	}
2139	}
2140	else if (pRam->pvR3)
2141	{
2142	int rc = SSMR3PutMem(pSSM, pRam->pvR3, pRam->cb);
2143	if (VBOX_FAILURE(rc))
2144	{
2145	Log(("pgmR3Save: SSMR3PutMem(, %p, %#x) -> %Vrc\n", pRam->pvR3, pRam->cb, rc));
2146	return rc;
2147	}
2148	}
2149	}
2150	return SSMR3PutU32(pSSM, ~0); /* terminator. */
2151	}
2152
2153
2154	/**
2155	* Execute state load operation.
2156	*
2157	* @returns VBox status code.
2158	* @param pVM VM Handle.
2159	* @param pSSM SSM operation handle.
2160	* @param u32Version Data layout version.
2161	*/
2162	static DECLCALLBACK(int) pgmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version)
2163	{
2164	/*
2165	* Validate version.
2166	*/
2167	if (u32Version != PGM_SAVED_STATE_VERSION)
2168	{
2169	AssertMsgFailed(("pgmR3Load: Invalid version u32Version=%d (current %d)!\n", u32Version, PGM_SAVED_STATE_VERSION));
2170	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
2171	}
2172
2173	/*
2174	* Call the reset function to make sure all the memory is cleared.
2175	*/
2176	PGMR3Reset(pVM);
2177
2178	/*
2179	* Load basic data (required / unaffected by relocation).
2180	*/
2181	PPGM pPGM = &pVM->pgm.s;
2182	#if 1
2183	SSMR3GetBool(pSSM, &pPGM->fMappingsFixed);
2184	#else
2185	uint32_t u;
2186	SSMR3GetU32(pSSM, &u);
2187	pPGM->fMappingsFixed = u;
2188	#endif
2189	SSMR3GetGCPtr(pSSM, &pPGM->GCPtrMappingFixed);
2190	SSMR3GetU32(pSSM, &pPGM->cbMappingFixed);
2191
2192	RTUINT cbRamSize;
2193	int rc = SSMR3GetU32(pSSM, &cbRamSize);
2194	if (VBOX_FAILURE(rc))
2195	return rc;
2196	if (cbRamSize != pPGM->cbRamSize)
2197	return VERR_SSM_LOAD_MEMORY_SIZE_MISMATCH;
2198	SSMR3GetGCPhys(pSSM, &pPGM->GCPhysA20Mask);
2199	SSMR3GetUInt(pSSM, &pPGM->fA20Enabled);
2200	SSMR3GetUInt(pSSM, &pPGM->fSyncFlags);
2201	RTUINT uGuestMode;
2202	SSMR3GetUInt(pSSM, &uGuestMode);
2203	pPGM->enmGuestMode = (PGMMODE)uGuestMode;
2204
2205	/* check separator. */
2206	uint32_t u32Sep;
2207	SSMR3GetU32(pSSM, &u32Sep);
2208	if (VBOX_FAILURE(rc))
2209	return rc;
2210	if (u32Sep != (uint32_t)~0)
2211	{
2212	AssertMsgFailed(("u32Sep=%#x (first)\n", u32Sep));
2213	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2214	}
2215
2216	/*
2217	* The guest mappings.
2218	*/
2219	uint32_t i = 0;
2220	for (;; i++)
2221	{
2222	/* Check the seqence number / separator. */
2223	rc = SSMR3GetU32(pSSM, &u32Sep);
2224	if (VBOX_FAILURE(rc))
2225	return rc;
2226	if (u32Sep == ~0U)
2227	break;
2228	if (u32Sep != i)
2229	{
2230	AssertMsgFailed(("u32Sep=%#x (last)\n", u32Sep));
2231	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2232	}
2233
2234	/* get the mapping details. */
2235	char szDesc[256];
2236	szDesc[0] = '\0';
2237	rc = SSMR3GetStrZ(pSSM, szDesc, sizeof(szDesc));
2238	if (VBOX_FAILURE(rc))
2239	return rc;
2240	RTGCPTR GCPtr;
2241	SSMR3GetGCPtr(pSSM, &GCPtr);
2242	RTGCUINTPTR cPTs;
2243	rc = SSMR3GetGCUIntPtr(pSSM, &cPTs);
2244	if (VBOX_FAILURE(rc))
2245	return rc;
2246
2247	/* find matching range. */
2248	PPGMMAPPING pMapping;
2249	for (pMapping = pPGM->pMappingsR3; pMapping; pMapping = pMapping->pNextR3)
2250	if ( pMapping->cPTs == cPTs
2251	&& !strcmp(pMapping->pszDesc, szDesc))
2252	break;
2253	if (!pMapping)
2254	{
2255	LogRel(("Couldn't find mapping: cPTs=%#x szDesc=%s (GCPtr=%VGv)\n",
2256	cPTs, szDesc, GCPtr));
2257	AssertFailed();
2258	return VERR_SSM_LOAD_CONFIG_MISMATCH;
2259	}
2260
2261	/* relocate it. */
2262	if (pMapping->GCPtr != GCPtr)
2263	{
2264	AssertMsg((GCPtr >> X86_PD_SHIFT << X86_PD_SHIFT) == GCPtr, ("GCPtr=%VGv\n", GCPtr));
2265	#if HC_ARCH_BITS == 64
2266	LogRel(("Mapping: %VGv -> %VGv %s\n", pMapping->GCPtr, GCPtr, pMapping->pszDesc));
2267	#endif
2268	pgmR3MapRelocate(pVM, pMapping, pMapping->GCPtr, GCPtr);
2269	}
2270	else
2271	Log(("pgmR3Load: '%s' needed no relocation (%VGv)\n", szDesc, GCPtr));
2272	}
2273
2274	/*
2275	* Ram range flags and bits.
2276	*/
2277	i = 0;
2278	for (PPGMRAMRANGE pRam = pPGM->pRamRangesR3; pRam; pRam = pRam->pNextR3, i++)
2279	{
2280	/** @todo MMIO ranges may move (PCI reconfig), we currently assume they don't. */
2281	/* Check the seqence number / separator. */
2282	rc = SSMR3GetU32(pSSM, &u32Sep);
2283	if (VBOX_FAILURE(rc))
2284	return rc;
2285	if (u32Sep == ~0U)
2286	break;
2287	if (u32Sep != i)
2288	{
2289	AssertMsgFailed(("u32Sep=%#x (last)\n", u32Sep));
2290	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2291	}
2292
2293	/* Get the range details. */
2294	RTGCPHYS GCPhys;
2295	SSMR3GetGCPhys(pSSM, &GCPhys);
2296	RTGCPHYS GCPhysLast;
2297	SSMR3GetGCPhys(pSSM, &GCPhysLast);
2298	RTGCPHYS cb;
2299	SSMR3GetGCPhys(pSSM, &cb);
2300	uint8_t fHaveBits;
2301	rc = SSMR3GetU8(pSSM, &fHaveBits);
2302	if (VBOX_FAILURE(rc))
2303	return rc;
2304	if (fHaveBits & ~1)
2305	{
2306	AssertMsgFailed(("u32Sep=%#x (last)\n", u32Sep));
2307	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2308	}
2309
2310	/* Match it up with the current range. */
2311	if ( GCPhys != pRam->GCPhys
2312	\|\| GCPhysLast != pRam->GCPhysLast
2313	\|\| cb != pRam->cb
2314	\|\| fHaveBits != !!pRam->pvR3)
2315	{
2316	LogRel(("Ram range: %RGp-%RGp %RGp bytes %s\n"
2317	"State : %RGp-%RGp %RGp bytes %s\n",
2318	pRam->GCPhys, pRam->GCPhysLast, pRam->cb, pRam->pvR3 ? "bits" : "nobits",
2319	GCPhys, GCPhysLast, cb, fHaveBits ? "bits" : "nobits"));
2320	/*
2321	* If we're loading a state for debugging purpose, don't make a fuss if
2322	* the MMIO[2] and ROM stuff isn't 100% right, just skip the mismatches.
2323	*/
2324	if ( SSMR3HandleGetAfter(pSSM) != SSMAFTER_DEBUG_IT
2325	\|\| GCPhys < 8 * _1M)
2326	AssertFailedReturn(VERR_SSM_LOAD_CONFIG_MISMATCH);
2327
2328	RTGCPHYS cPages = ((GCPhysLast - GCPhys) + 1) >> PAGE_SHIFT;
2329	while (cPages-- > 0)
2330	{
2331	uint16_t u16Ignore;
2332	SSMR3GetU16(pSSM, &u16Ignore);
2333	}
2334	continue;
2335	}
2336
2337	/* Flags. */
2338	const unsigned cPages = pRam->cb >> PAGE_SHIFT;
2339	for (unsigned iPage = 0; iPage < cPages; iPage++)
2340	{
2341	uint16_t u16 = 0;
2342	SSMR3GetU16(pSSM, &u16);
2343	u16 &= PAGE_OFFSET_MASK & ~( RT_BIT(4) \| RT_BIT(5) \| RT_BIT(6)
2344	\| RT_BIT(7) \| RT_BIT(8) \| RT_BIT(9) \| RT_BIT(10) );
2345	// &= MM_RAM_FLAGS_DYNAMIC_ALLOC \| MM_RAM_FLAGS_RESERVED \| MM_RAM_FLAGS_ROM \| MM_RAM_FLAGS_MMIO \| MM_RAM_FLAGS_MMIO2
2346	pRam->aPages[iPage].HCPhys = PGM_PAGE_GET_HCPHYS(&pRam->aPages[iPage]) \| (RTHCPHYS)u16; /** @todo PAGE FLAGS */
2347	}
2348
2349	/* any memory associated with the range. */
2350	if (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)
2351	{
2352	for (unsigned iChunk = 0; iChunk < (pRam->cb >> PGM_DYNAMIC_CHUNK_SHIFT); iChunk++)
2353	{
2354	uint8_t fValidChunk;
2355
2356	rc = SSMR3GetU8(pSSM, &fValidChunk);
2357	if (VBOX_FAILURE(rc))
2358	return rc;
2359	if (fValidChunk > 1)
2360	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2361
2362	if (fValidChunk)
2363	{
2364	if (!pRam->paChunkR3Ptrs[iChunk])
2365	{
2366	rc = pgmr3PhysGrowRange(pVM, pRam->GCPhys + iChunk * PGM_DYNAMIC_CHUNK_SIZE);
2367	if (VBOX_FAILURE(rc))
2368	return rc;
2369	}
2370	Assert(pRam->paChunkR3Ptrs[iChunk]);
2371
2372	SSMR3GetMem(pSSM, (void *)pRam->paChunkR3Ptrs[iChunk], PGM_DYNAMIC_CHUNK_SIZE);
2373	}
2374	/* else nothing to do */
2375	}
2376	}
2377	else if (pRam->pvR3)
2378	{
2379	int rc = SSMR3GetMem(pSSM, pRam->pvR3, pRam->cb);
2380	if (VBOX_FAILURE(rc))
2381	{
2382	Log(("pgmR3Save: SSMR3GetMem(, %p, %#x) -> %Vrc\n", pRam->pvR3, pRam->cb, rc));
2383	return rc;
2384	}
2385	}
2386	}
2387
2388	/*
2389	* We require a full resync now.
2390	*/
2391	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3_NON_GLOBAL);
2392	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
2393	pPGM->fSyncFlags \|= PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL;
2394	pPGM->fPhysCacheFlushPending = true;
2395	pgmR3HandlerPhysicalUpdateAll(pVM);
2396
2397	/*
2398	* Change the paging mode.
2399	*/
2400	rc = PGMR3ChangeMode(pVM, pPGM->enmGuestMode);
2401
2402	/* Restore pVM->pgm.s.GCPhysCR3. */
2403	Assert(pVM->pgm.s.GCPhysCR3 == NIL_RTGCPHYS);
2404	RTGCPHYS GCPhysCR3 = CPUMGetGuestCR3(pVM);
2405	if ( pVM->pgm.s.enmGuestMode == PGMMODE_PAE
2406	\|\| pVM->pgm.s.enmGuestMode == PGMMODE_PAE_NX
2407	\|\| pVM->pgm.s.enmGuestMode == PGMMODE_AMD64
2408	\|\| pVM->pgm.s.enmGuestMode == PGMMODE_AMD64_NX)
2409	GCPhysCR3 = (GCPhysCR3 & X86_CR3_PAE_PAGE_MASK);
2410	else
2411	GCPhysCR3 = (GCPhysCR3 & X86_CR3_PAGE_MASK);
2412	pVM->pgm.s.GCPhysCR3 = GCPhysCR3;
2413
2414	return rc;
2415	}
2416
2417
2418	/**
2419	* Show paging mode.
2420	*
2421	* @param pVM VM Handle.
2422	* @param pHlp The info helpers.
2423	* @param pszArgs "all" (default), "guest", "shadow" or "host".
2424	*/
2425	static DECLCALLBACK(void) pgmR3InfoMode(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2426	{
2427	/* digest argument. */
2428	bool fGuest, fShadow, fHost;
2429	if (pszArgs)
2430	pszArgs = RTStrStripL(pszArgs);
2431	if (!pszArgs \|\| !*pszArgs \|\| strstr(pszArgs, "all"))
2432	fShadow = fHost = fGuest = true;
2433	else
2434	{
2435	fShadow = fHost = fGuest = false;
2436	if (strstr(pszArgs, "guest"))
2437	fGuest = true;
2438	if (strstr(pszArgs, "shadow"))
2439	fShadow = true;
2440	if (strstr(pszArgs, "host"))
2441	fHost = true;
2442	}
2443
2444	/* print info. */
2445	if (fGuest)
2446	pHlp->pfnPrintf(pHlp, "Guest paging mode: %s, changed %RU64 times, A20 %s\n",
2447	PGMGetModeName(pVM->pgm.s.enmGuestMode), pVM->pgm.s.cGuestModeChanges.c,
2448	pVM->pgm.s.fA20Enabled ? "enabled" : "disabled");
2449	if (fShadow)
2450	pHlp->pfnPrintf(pHlp, "Shadow paging mode: %s\n", PGMGetModeName(pVM->pgm.s.enmShadowMode));
2451	if (fHost)
2452	{
2453	const char *psz;
2454	switch (pVM->pgm.s.enmHostMode)
2455	{
2456	case SUPPAGINGMODE_INVALID: psz = "invalid"; break;
2457	case SUPPAGINGMODE_32_BIT: psz = "32-bit"; break;
2458	case SUPPAGINGMODE_32_BIT_GLOBAL: psz = "32-bit+G"; break;
2459	case SUPPAGINGMODE_PAE: psz = "PAE"; break;
2460	case SUPPAGINGMODE_PAE_GLOBAL: psz = "PAE+G"; break;
2461	case SUPPAGINGMODE_PAE_NX: psz = "PAE+NX"; break;
2462	case SUPPAGINGMODE_PAE_GLOBAL_NX: psz = "PAE+G+NX"; break;
2463	case SUPPAGINGMODE_AMD64: psz = "AMD64"; break;
2464	case SUPPAGINGMODE_AMD64_GLOBAL: psz = "AMD64+G"; break;
2465	case SUPPAGINGMODE_AMD64_NX: psz = "AMD64+NX"; break;
2466	case SUPPAGINGMODE_AMD64_GLOBAL_NX: psz = "AMD64+G+NX"; break;
2467	default: psz = "unknown"; break;
2468	}
2469	pHlp->pfnPrintf(pHlp, "Host paging mode: %s\n", psz);
2470	}
2471	}
2472
2473
2474	/**
2475	* Dump registered MMIO ranges to the log.
2476	*
2477	* @param pVM VM Handle.
2478	* @param pHlp The info helpers.
2479	* @param pszArgs Arguments, ignored.
2480	*/
2481	static DECLCALLBACK(void) pgmR3PhysInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2482	{
2483	NOREF(pszArgs);
2484	pHlp->pfnPrintf(pHlp,
2485	"RAM ranges (pVM=%p)\n"
2486	"%.s %.s\n",
2487	pVM,
2488	sizeof(RTGCPHYS) * 4 + 1, "GC Phys Range ",
2489	sizeof(RTHCPTR) * 2, "pvHC ");
2490
2491	for (PPGMRAMRANGE pCur = pVM->pgm.s.pRamRangesR3; pCur; pCur = pCur->pNextR3)
2492	pHlp->pfnPrintf(pHlp,
2493	"%RGp-%RGp %RHv %s\n",
2494	pCur->GCPhys,
2495	pCur->GCPhysLast,
2496	pCur->pvR3,
2497	pCur->pszDesc);
2498	}
2499
2500	/**
2501	* Dump the page directory to the log.
2502	*
2503	* @param pVM VM Handle.
2504	* @param pHlp The info helpers.
2505	* @param pszArgs Arguments, ignored.
2506	*/
2507	static DECLCALLBACK(void) pgmR3InfoCr3(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2508	{
2509	/** @todo fix this! Convert the PGMR3DumpHierarchyHC functions to do guest stuff. */
2510	/* Big pages supported? */
2511	const bool fPSE = !!(CPUMGetGuestCR4(pVM) & X86_CR4_PSE);
2512
2513	/* Global pages supported? */
2514	const bool fPGE = !!(CPUMGetGuestCR4(pVM) & X86_CR4_PGE);
2515
2516	NOREF(pszArgs);
2517
2518	/*
2519	* Get page directory addresses.
2520	*/
2521	PX86PD pPDSrc = pVM->pgm.s.pGuestPDHC;
2522	Assert(pPDSrc);
2523	Assert(PGMPhysGCPhys2HCPtrAssert(pVM, (RTGCPHYS)(CPUMGetGuestCR3(pVM) & X86_CR3_PAGE_MASK), sizeof(*pPDSrc)) == pPDSrc);
2524
2525	/*
2526	* Iterate the page directory.
2527	*/
2528	for (unsigned iPD = 0; iPD < RT_ELEMENTS(pPDSrc->a); iPD++)
2529	{
2530	X86PDE PdeSrc = pPDSrc->a[iPD];
2531	if (PdeSrc.n.u1Present)
2532	{
2533	if (PdeSrc.b.u1Size && fPSE)
2534	{
2535	pHlp->pfnPrintf(pHlp,
2536	"%04X - %VGp P=%d U=%d RW=%d G=%d - BIG\n",
2537	iPD,
2538	pgmGstGet4MBPhysPage(&pVM->pgm.s, PdeSrc),
2539	PdeSrc.b.u1Present, PdeSrc.b.u1User, PdeSrc.b.u1Write, PdeSrc.b.u1Global && fPGE);
2540	}
2541	else
2542	{
2543	pHlp->pfnPrintf(pHlp,
2544	"%04X - %VGp P=%d U=%d RW=%d [G=%d]\n",
2545	iPD,
2546	PdeSrc.u & X86_PDE_PG_MASK,
2547	PdeSrc.n.u1Present, PdeSrc.n.u1User, PdeSrc.n.u1Write, PdeSrc.b.u1Global && fPGE);
2548	}
2549	}
2550	}
2551	}
2552
2553
2554	/**
2555	* Serivce a VMMCALLHOST_PGM_LOCK call.
2556	*
2557	* @returns VBox status code.
2558	* @param pVM The VM handle.
2559	*/
2560	VMMR3DECL(int) PGMR3LockCall(PVM pVM)
2561	{
2562	int rc = PDMR3CritSectEnterEx(&pVM->pgm.s.CritSect, true /* fHostCall */);
2563	AssertRC(rc);
2564	return rc;
2565	}
2566
2567
2568	/**
2569	* Converts a PGMMODE value to a PGM_TYPE_* \#define.
2570	*
2571	* @returns PGM_TYPE_*.
2572	* @param pgmMode The mode value to convert.
2573	*/
2574	DECLINLINE(unsigned) pgmModeToType(PGMMODE pgmMode)
2575	{
2576	switch (pgmMode)
2577	{
2578	case PGMMODE_REAL: return PGM_TYPE_REAL;
2579	case PGMMODE_PROTECTED: return PGM_TYPE_PROT;
2580	case PGMMODE_32_BIT: return PGM_TYPE_32BIT;
2581	case PGMMODE_PAE:
2582	case PGMMODE_PAE_NX: return PGM_TYPE_PAE;
2583	case PGMMODE_AMD64:
2584	case PGMMODE_AMD64_NX: return PGM_TYPE_AMD64;
2585	case PGMMODE_NESTED: return PGM_TYPE_NESTED;
2586	case PGMMODE_EPT: return PGM_TYPE_EPT;
2587	default:
2588	AssertFatalMsgFailed(("pgmMode=%d\n", pgmMode));
2589	}
2590	}
2591
2592
2593	/**
2594	* Gets the index into the paging mode data array of a SHW+GST mode.
2595	*
2596	* @returns PGM::paPagingData index.
2597	* @param uShwType The shadow paging mode type.
2598	* @param uGstType The guest paging mode type.
2599	*/
2600	DECLINLINE(unsigned) pgmModeDataIndex(unsigned uShwType, unsigned uGstType)
2601	{
2602	Assert(uShwType >= PGM_TYPE_32BIT && uShwType <= PGM_TYPE_MAX);
2603	Assert(uGstType >= PGM_TYPE_REAL && uGstType <= PGM_TYPE_AMD64);
2604	return (uShwType - PGM_TYPE_32BIT) * (PGM_TYPE_AMD64 - PGM_TYPE_REAL + 1)
2605	+ (uGstType - PGM_TYPE_REAL);
2606	}
2607
2608
2609	/**
2610	* Gets the index into the paging mode data array of a SHW+GST mode.
2611	*
2612	* @returns PGM::paPagingData index.
2613	* @param enmShw The shadow paging mode.
2614	* @param enmGst The guest paging mode.
2615	*/
2616	DECLINLINE(unsigned) pgmModeDataIndexByMode(PGMMODE enmShw, PGMMODE enmGst)
2617	{
2618	Assert(enmShw >= PGMMODE_32_BIT && enmShw <= PGMMODE_MAX);
2619	Assert(enmGst > PGMMODE_INVALID && enmGst < PGMMODE_MAX);
2620	return pgmModeDataIndex(pgmModeToType(enmShw), pgmModeToType(enmGst));
2621	}
2622
2623
2624	/**
2625	* Calculates the max data index.
2626	* @returns The number of entries in the paging data array.
2627	*/
2628	DECLINLINE(unsigned) pgmModeDataMaxIndex(void)
2629	{
2630	return pgmModeDataIndex(PGM_TYPE_MAX, PGM_TYPE_AMD64) + 1;
2631	}
2632
2633
2634	/**
2635	* Initializes the paging mode data kept in PGM::paModeData.
2636	*
2637	* @param pVM The VM handle.
2638	* @param fResolveGCAndR0 Indicate whether or not GC and Ring-0 symbols can be resolved now.
2639	* This is used early in the init process to avoid trouble with PDM
2640	* not being initialized yet.
2641	*/
2642	static int pgmR3ModeDataInit(PVM pVM, bool fResolveGCAndR0)
2643	{
2644	PPGMMODEDATA pModeData;
2645	int rc;
2646
2647	/*
2648	* Allocate the array on the first call.
2649	*/
2650	if (!pVM->pgm.s.paModeData)
2651	{
2652	pVM->pgm.s.paModeData = (PPGMMODEDATA)MMR3HeapAllocZ(pVM, MM_TAG_PGM, sizeof(PGMMODEDATA) * pgmModeDataMaxIndex());
2653	AssertReturn(pVM->pgm.s.paModeData, VERR_NO_MEMORY);
2654	}
2655
2656	/*
2657	* Initialize the array entries.
2658	*/
2659	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_32BIT, PGM_TYPE_REAL)];
2660	pModeData->uShwType = PGM_TYPE_32BIT;
2661	pModeData->uGstType = PGM_TYPE_REAL;
2662	rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2663	rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2664	rc = PGM_BTH_NAME_32BIT_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2665
2666	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_32BIT, PGMMODE_PROTECTED)];
2667	pModeData->uShwType = PGM_TYPE_32BIT;
2668	pModeData->uGstType = PGM_TYPE_PROT;
2669	rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2670	rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2671	rc = PGM_BTH_NAME_32BIT_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2672
2673	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_32BIT, PGM_TYPE_32BIT)];
2674	pModeData->uShwType = PGM_TYPE_32BIT;
2675	pModeData->uGstType = PGM_TYPE_32BIT;
2676	rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2677	rc = PGM_GST_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2678	rc = PGM_BTH_NAME_32BIT_32BIT(InitData)(pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2679
2680	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_REAL)];
2681	pModeData->uShwType = PGM_TYPE_PAE;
2682	pModeData->uGstType = PGM_TYPE_REAL;
2683	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2684	rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2685	rc = PGM_BTH_NAME_PAE_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2686
2687	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_PROT)];
2688	pModeData->uShwType = PGM_TYPE_PAE;
2689	pModeData->uGstType = PGM_TYPE_PROT;
2690	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2691	rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2692	rc = PGM_BTH_NAME_PAE_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2693
2694	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_32BIT)];
2695	pModeData->uShwType = PGM_TYPE_PAE;
2696	pModeData->uGstType = PGM_TYPE_32BIT;
2697	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2698	rc = PGM_GST_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2699	rc = PGM_BTH_NAME_PAE_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2700
2701	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_PAE)];
2702	pModeData->uShwType = PGM_TYPE_PAE;
2703	pModeData->uGstType = PGM_TYPE_PAE;
2704	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2705	rc = PGM_GST_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2706	rc = PGM_BTH_NAME_PAE_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2707
2708	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_AMD64, PGM_TYPE_AMD64)];
2709	pModeData->uShwType = PGM_TYPE_AMD64;
2710	pModeData->uGstType = PGM_TYPE_AMD64;
2711	rc = PGM_SHW_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2712	rc = PGM_GST_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2713	rc = PGM_BTH_NAME_AMD64_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2714
2715	/* The nested paging mode. */
2716	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_REAL)];
2717	pModeData->uShwType = PGM_TYPE_NESTED;
2718	pModeData->uGstType = PGM_TYPE_REAL;
2719	rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2720	rc = PGM_BTH_NAME_NESTED_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2721
2722	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGMMODE_PROTECTED)];
2723	pModeData->uShwType = PGM_TYPE_NESTED;
2724	pModeData->uGstType = PGM_TYPE_PROT;
2725	rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2726	rc = PGM_BTH_NAME_NESTED_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2727
2728	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_32BIT)];
2729	pModeData->uShwType = PGM_TYPE_NESTED;
2730	pModeData->uGstType = PGM_TYPE_32BIT;
2731	rc = PGM_GST_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2732	rc = PGM_BTH_NAME_NESTED_32BIT(InitData)(pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2733
2734	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_PAE)];
2735	pModeData->uShwType = PGM_TYPE_NESTED;
2736	pModeData->uGstType = PGM_TYPE_PAE;
2737	rc = PGM_GST_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2738	rc = PGM_BTH_NAME_NESTED_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2739
2740	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_AMD64)];
2741	pModeData->uShwType = PGM_TYPE_NESTED;
2742	pModeData->uGstType = PGM_TYPE_AMD64;
2743	rc = PGM_GST_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2744	rc = PGM_BTH_NAME_NESTED_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2745
2746	/* The shadow part of the nested callback mode depends on the host paging mode (AMD-V only). */
2747	switch(pVM->pgm.s.enmHostMode)
2748	{
2749	case SUPPAGINGMODE_32_BIT:
2750	case SUPPAGINGMODE_32_BIT_GLOBAL:
2751	for (unsigned i=PGM_TYPE_REAL;i<=PGM_TYPE_AMD64;i++)
2752	{
2753	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, i)];
2754	rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2755	}
2756	break;
2757
2758	case SUPPAGINGMODE_PAE:
2759	case SUPPAGINGMODE_PAE_NX:
2760	case SUPPAGINGMODE_PAE_GLOBAL:
2761	case SUPPAGINGMODE_PAE_GLOBAL_NX:
2762	for (unsigned i=PGM_TYPE_REAL;i<=PGM_TYPE_AMD64;i++)
2763	{
2764	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, i)];
2765	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2766	}
2767	break;
2768
2769	case SUPPAGINGMODE_AMD64:
2770	case SUPPAGINGMODE_AMD64_GLOBAL:
2771	case SUPPAGINGMODE_AMD64_NX:
2772	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
2773	for (unsigned i=PGM_TYPE_REAL;i<=PGM_TYPE_AMD64;i++)
2774	{
2775	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, i)];
2776	rc = PGM_SHW_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2777	}
2778	break;
2779	default:
2780	AssertFailed();
2781	break;
2782	}
2783
2784	/* Extended paging (EPT) / Intel VT-x */
2785	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_REAL)];
2786	pModeData->uShwType = PGM_TYPE_EPT;
2787	pModeData->uGstType = PGM_TYPE_REAL;
2788	rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2789	rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2790	rc = PGM_BTH_NAME_EPT_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2791
2792	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_PROT)];
2793	pModeData->uShwType = PGM_TYPE_EPT;
2794	pModeData->uGstType = PGM_TYPE_PROT;
2795	rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2796	rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2797	rc = PGM_BTH_NAME_EPT_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2798
2799	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_32BIT)];
2800	pModeData->uShwType = PGM_TYPE_EPT;
2801	pModeData->uGstType = PGM_TYPE_32BIT;
2802	rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2803	rc = PGM_GST_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2804	rc = PGM_BTH_NAME_EPT_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2805
2806	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_PAE)];
2807	pModeData->uShwType = PGM_TYPE_EPT;
2808	pModeData->uGstType = PGM_TYPE_PAE;
2809	rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2810	rc = PGM_GST_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2811	rc = PGM_BTH_NAME_EPT_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2812
2813	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_AMD64)];
2814	pModeData->uShwType = PGM_TYPE_EPT;
2815	pModeData->uGstType = PGM_TYPE_AMD64;
2816	rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2817	rc = PGM_GST_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2818	rc = PGM_BTH_NAME_EPT_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2819	return VINF_SUCCESS;
2820	}
2821
2822
2823	/**
2824	* Switch to different (or relocated in the relocate case) mode data.
2825	*
2826	* @param pVM The VM handle.
2827	* @param enmShw The the shadow paging mode.
2828	* @param enmGst The the guest paging mode.
2829	*/
2830	static void pgmR3ModeDataSwitch(PVM pVM, PGMMODE enmShw, PGMMODE enmGst)
2831	{
2832	PPGMMODEDATA pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndexByMode(enmShw, enmGst)];
2833
2834	Assert(pModeData->uGstType == pgmModeToType(enmGst));
2835	Assert(pModeData->uShwType == pgmModeToType(enmShw));
2836
2837	/* shadow */
2838	pVM->pgm.s.pfnR3ShwRelocate = pModeData->pfnR3ShwRelocate;
2839	pVM->pgm.s.pfnR3ShwExit = pModeData->pfnR3ShwExit;
2840	pVM->pgm.s.pfnR3ShwGetPage = pModeData->pfnR3ShwGetPage;
2841	Assert(pVM->pgm.s.pfnR3ShwGetPage);
2842	pVM->pgm.s.pfnR3ShwModifyPage = pModeData->pfnR3ShwModifyPage;
2843
2844	pVM->pgm.s.pfnRCShwGetPage = pModeData->pfnRCShwGetPage;
2845	pVM->pgm.s.pfnRCShwModifyPage = pModeData->pfnRCShwModifyPage;
2846
2847	pVM->pgm.s.pfnR0ShwGetPage = pModeData->pfnR0ShwGetPage;
2848	pVM->pgm.s.pfnR0ShwModifyPage = pModeData->pfnR0ShwModifyPage;
2849
2850
2851	/* guest */
2852	pVM->pgm.s.pfnR3GstRelocate = pModeData->pfnR3GstRelocate;
2853	pVM->pgm.s.pfnR3GstExit = pModeData->pfnR3GstExit;
2854	pVM->pgm.s.pfnR3GstGetPage = pModeData->pfnR3GstGetPage;
2855	Assert(pVM->pgm.s.pfnR3GstGetPage);
2856	pVM->pgm.s.pfnR3GstModifyPage = pModeData->pfnR3GstModifyPage;
2857	pVM->pgm.s.pfnR3GstGetPDE = pModeData->pfnR3GstGetPDE;
2858	pVM->pgm.s.pfnR3GstMonitorCR3 = pModeData->pfnR3GstMonitorCR3;
2859	pVM->pgm.s.pfnR3GstUnmonitorCR3 = pModeData->pfnR3GstUnmonitorCR3;
2860	pVM->pgm.s.pfnR3GstMapCR3 = pModeData->pfnR3GstMapCR3;
2861	pVM->pgm.s.pfnR3GstUnmapCR3 = pModeData->pfnR3GstUnmapCR3;
2862	pVM->pgm.s.pfnR3GstWriteHandlerCR3 = pModeData->pfnR3GstWriteHandlerCR3;
2863	pVM->pgm.s.pszR3GstWriteHandlerCR3 = pModeData->pszR3GstWriteHandlerCR3;
2864	pVM->pgm.s.pfnR3GstPAEWriteHandlerCR3 = pModeData->pfnR3GstPAEWriteHandlerCR3;
2865	pVM->pgm.s.pszR3GstPAEWriteHandlerCR3 = pModeData->pszR3GstPAEWriteHandlerCR3;
2866
2867	pVM->pgm.s.pfnRCGstGetPage = pModeData->pfnRCGstGetPage;
2868	pVM->pgm.s.pfnRCGstModifyPage = pModeData->pfnRCGstModifyPage;
2869	pVM->pgm.s.pfnRCGstGetPDE = pModeData->pfnRCGstGetPDE;
2870	pVM->pgm.s.pfnRCGstMonitorCR3 = pModeData->pfnRCGstMonitorCR3;
2871	pVM->pgm.s.pfnRCGstUnmonitorCR3 = pModeData->pfnRCGstUnmonitorCR3;
2872	pVM->pgm.s.pfnRCGstMapCR3 = pModeData->pfnRCGstMapCR3;
2873	pVM->pgm.s.pfnRCGstUnmapCR3 = pModeData->pfnRCGstUnmapCR3;
2874	pVM->pgm.s.pfnRCGstWriteHandlerCR3 = pModeData->pfnRCGstWriteHandlerCR3;
2875	pVM->pgm.s.pfnRCGstPAEWriteHandlerCR3 = pModeData->pfnRCGstPAEWriteHandlerCR3;
2876
2877	pVM->pgm.s.pfnR0GstGetPage = pModeData->pfnR0GstGetPage;
2878	pVM->pgm.s.pfnR0GstModifyPage = pModeData->pfnR0GstModifyPage;
2879	pVM->pgm.s.pfnR0GstGetPDE = pModeData->pfnR0GstGetPDE;
2880	pVM->pgm.s.pfnR0GstMonitorCR3 = pModeData->pfnR0GstMonitorCR3;
2881	pVM->pgm.s.pfnR0GstUnmonitorCR3 = pModeData->pfnR0GstUnmonitorCR3;
2882	pVM->pgm.s.pfnR0GstMapCR3 = pModeData->pfnR0GstMapCR3;
2883	pVM->pgm.s.pfnR0GstUnmapCR3 = pModeData->pfnR0GstUnmapCR3;
2884	pVM->pgm.s.pfnR0GstWriteHandlerCR3 = pModeData->pfnR0GstWriteHandlerCR3;
2885	pVM->pgm.s.pfnR0GstPAEWriteHandlerCR3 = pModeData->pfnR0GstPAEWriteHandlerCR3;
2886
2887
2888	/* both */
2889	pVM->pgm.s.pfnR3BthRelocate = pModeData->pfnR3BthRelocate;
2890	pVM->pgm.s.pfnR3BthInvalidatePage = pModeData->pfnR3BthInvalidatePage;
2891	pVM->pgm.s.pfnR3BthSyncCR3 = pModeData->pfnR3BthSyncCR3;
2892	Assert(pVM->pgm.s.pfnR3BthSyncCR3);
2893	pVM->pgm.s.pfnR3BthSyncPage = pModeData->pfnR3BthSyncPage;
2894	pVM->pgm.s.pfnR3BthPrefetchPage = pModeData->pfnR3BthPrefetchPage;
2895	pVM->pgm.s.pfnR3BthVerifyAccessSyncPage = pModeData->pfnR3BthVerifyAccessSyncPage;
2896	#ifdef VBOX_STRICT
2897	pVM->pgm.s.pfnR3BthAssertCR3 = pModeData->pfnR3BthAssertCR3;
2898	#endif
2899
2900	pVM->pgm.s.pfnRCBthTrap0eHandler = pModeData->pfnRCBthTrap0eHandler;
2901	pVM->pgm.s.pfnRCBthInvalidatePage = pModeData->pfnRCBthInvalidatePage;
2902	pVM->pgm.s.pfnRCBthSyncCR3 = pModeData->pfnRCBthSyncCR3;
2903	pVM->pgm.s.pfnRCBthSyncPage = pModeData->pfnRCBthSyncPage;
2904	pVM->pgm.s.pfnRCBthPrefetchPage = pModeData->pfnRCBthPrefetchPage;
2905	pVM->pgm.s.pfnRCBthVerifyAccessSyncPage = pModeData->pfnRCBthVerifyAccessSyncPage;
2906	#ifdef VBOX_STRICT
2907	pVM->pgm.s.pfnRCBthAssertCR3 = pModeData->pfnRCBthAssertCR3;
2908	#endif
2909
2910	pVM->pgm.s.pfnR0BthTrap0eHandler = pModeData->pfnR0BthTrap0eHandler;
2911	pVM->pgm.s.pfnR0BthInvalidatePage = pModeData->pfnR0BthInvalidatePage;
2912	pVM->pgm.s.pfnR0BthSyncCR3 = pModeData->pfnR0BthSyncCR3;
2913	pVM->pgm.s.pfnR0BthSyncPage = pModeData->pfnR0BthSyncPage;
2914	pVM->pgm.s.pfnR0BthPrefetchPage = pModeData->pfnR0BthPrefetchPage;
2915	pVM->pgm.s.pfnR0BthVerifyAccessSyncPage = pModeData->pfnR0BthVerifyAccessSyncPage;
2916	#ifdef VBOX_STRICT
2917	pVM->pgm.s.pfnR0BthAssertCR3 = pModeData->pfnR0BthAssertCR3;
2918	#endif
2919	}
2920
2921
2922	#ifdef DEBUG_bird
2923	#include <stdlib.h> /* getenv() remove me! */
2924	#endif
2925
2926	/**
2927	* Calculates the shadow paging mode.
2928	*
2929	* @returns The shadow paging mode.
2930	* @param pVM VM handle.
2931	* @param enmGuestMode The guest mode.
2932	* @param enmHostMode The host mode.
2933	* @param enmShadowMode The current shadow mode.
2934	* @param penmSwitcher Where to store the switcher to use.
2935	* VMMSWITCHER_INVALID means no change.
2936	*/
2937	static PGMMODE pgmR3CalcShadowMode(PVM pVM, PGMMODE enmGuestMode, SUPPAGINGMODE enmHostMode, PGMMODE enmShadowMode, VMMSWITCHER *penmSwitcher)
2938	{
2939	VMMSWITCHER enmSwitcher = VMMSWITCHER_INVALID;
2940	switch (enmGuestMode)
2941	{
2942	/*
2943	* When switching to real or protected mode we don't change
2944	* anything since it's likely that we'll switch back pretty soon.
2945	*
2946	* During pgmR3InitPaging we'll end up here with PGMMODE_INVALID
2947	* and is supposed to determine which shadow paging and switcher to
2948	* use during init.
2949	*/
2950	case PGMMODE_REAL:
2951	case PGMMODE_PROTECTED:
2952	if ( enmShadowMode != PGMMODE_INVALID
2953	&& !HWACCMIsEnabled(pVM) /* always switch in hwaccm mode! */)
2954	break; /* (no change) */
2955
2956	switch (enmHostMode)
2957	{
2958	case SUPPAGINGMODE_32_BIT:
2959	case SUPPAGINGMODE_32_BIT_GLOBAL:
2960	enmShadowMode = PGMMODE_32_BIT;
2961	enmSwitcher = VMMSWITCHER_32_TO_32;
2962	break;
2963
2964	case SUPPAGINGMODE_PAE:
2965	case SUPPAGINGMODE_PAE_NX:
2966	case SUPPAGINGMODE_PAE_GLOBAL:
2967	case SUPPAGINGMODE_PAE_GLOBAL_NX:
2968	enmShadowMode = PGMMODE_PAE;
2969	enmSwitcher = VMMSWITCHER_PAE_TO_PAE;
2970	#ifdef DEBUG_bird
2971	if (getenv("VBOX_32BIT"))
2972	{
2973	enmShadowMode = PGMMODE_32_BIT;
2974	enmSwitcher = VMMSWITCHER_PAE_TO_32;
2975	}
2976	#endif
2977	break;
2978
2979	case SUPPAGINGMODE_AMD64:
2980	case SUPPAGINGMODE_AMD64_GLOBAL:
2981	case SUPPAGINGMODE_AMD64_NX:
2982	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
2983	enmShadowMode = PGMMODE_PAE;
2984	enmSwitcher = VMMSWITCHER_AMD64_TO_PAE;
2985	break;
2986
2987	default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
2988	}
2989	break;
2990
2991	case PGMMODE_32_BIT:
2992	switch (enmHostMode)
2993	{
2994	case SUPPAGINGMODE_32_BIT:
2995	case SUPPAGINGMODE_32_BIT_GLOBAL:
2996	enmShadowMode = PGMMODE_32_BIT;
2997	enmSwitcher = VMMSWITCHER_32_TO_32;
2998	break;
2999
3000	case SUPPAGINGMODE_PAE:
3001	case SUPPAGINGMODE_PAE_NX:
3002	case SUPPAGINGMODE_PAE_GLOBAL:
3003	case SUPPAGINGMODE_PAE_GLOBAL_NX:
3004	enmShadowMode = PGMMODE_PAE;
3005	enmSwitcher = VMMSWITCHER_PAE_TO_PAE;
3006	#ifdef DEBUG_bird
3007	if (getenv("VBOX_32BIT"))
3008	{
3009	enmShadowMode = PGMMODE_32_BIT;
3010	enmSwitcher = VMMSWITCHER_PAE_TO_32;
3011	}
3012	#endif
3013	break;
3014
3015	case SUPPAGINGMODE_AMD64:
3016	case SUPPAGINGMODE_AMD64_GLOBAL:
3017	case SUPPAGINGMODE_AMD64_NX:
3018	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
3019	enmShadowMode = PGMMODE_PAE;
3020	enmSwitcher = VMMSWITCHER_AMD64_TO_PAE;
3021	break;
3022
3023	default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
3024	}
3025	break;
3026
3027	case PGMMODE_PAE:
3028	case PGMMODE_PAE_NX: /** @todo This might require more switchers and guest+both modes. */
3029	switch (enmHostMode)
3030	{
3031	case SUPPAGINGMODE_32_BIT:
3032	case SUPPAGINGMODE_32_BIT_GLOBAL:
3033	enmShadowMode = PGMMODE_PAE;
3034	enmSwitcher = VMMSWITCHER_32_TO_PAE;
3035	break;
3036
3037	case SUPPAGINGMODE_PAE:
3038	case SUPPAGINGMODE_PAE_NX:
3039	case SUPPAGINGMODE_PAE_GLOBAL:
3040	case SUPPAGINGMODE_PAE_GLOBAL_NX:
3041	enmShadowMode = PGMMODE_PAE;
3042	enmSwitcher = VMMSWITCHER_PAE_TO_PAE;
3043	break;
3044
3045	case SUPPAGINGMODE_AMD64:
3046	case SUPPAGINGMODE_AMD64_GLOBAL:
3047	case SUPPAGINGMODE_AMD64_NX:
3048	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
3049	enmShadowMode = PGMMODE_PAE;
3050	enmSwitcher = VMMSWITCHER_AMD64_TO_PAE;
3051	break;
3052
3053	default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
3054	}
3055	break;
3056
3057	case PGMMODE_AMD64:
3058	case PGMMODE_AMD64_NX:
3059	switch (enmHostMode)
3060	{
3061	case SUPPAGINGMODE_32_BIT:
3062	case SUPPAGINGMODE_32_BIT_GLOBAL:
3063	enmShadowMode = PGMMODE_PAE;
3064	enmSwitcher = VMMSWITCHER_32_TO_AMD64;
3065	break;
3066
3067	case SUPPAGINGMODE_PAE:
3068	case SUPPAGINGMODE_PAE_NX:
3069	case SUPPAGINGMODE_PAE_GLOBAL:
3070	case SUPPAGINGMODE_PAE_GLOBAL_NX:
3071	enmShadowMode = PGMMODE_PAE;
3072	enmSwitcher = VMMSWITCHER_PAE_TO_AMD64;
3073	break;
3074
3075	case SUPPAGINGMODE_AMD64:
3076	case SUPPAGINGMODE_AMD64_GLOBAL:
3077	case SUPPAGINGMODE_AMD64_NX:
3078	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
3079	enmShadowMode = PGMMODE_AMD64;
3080	enmSwitcher = VMMSWITCHER_AMD64_TO_AMD64;
3081	break;
3082
3083	default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
3084	}
3085	break;
3086
3087
3088	default:
3089	AssertReleaseMsgFailed(("enmGuestMode=%d\n", enmGuestMode));
3090	return PGMMODE_INVALID;
3091	}
3092	/* Override the shadow mode is nested paging is active. */
3093	if (HWACCMIsNestedPagingActive(pVM))
3094	enmShadowMode = HWACCMGetPagingMode(pVM);
3095
3096	*penmSwitcher = enmSwitcher;
3097	return enmShadowMode;
3098	}
3099
3100	/**
3101	* Performs the actual mode change.
3102	* This is called by PGMChangeMode and pgmR3InitPaging().
3103	*
3104	* @returns VBox status code.
3105	* @param pVM VM handle.
3106	* @param enmGuestMode The new guest mode. This is assumed to be different from
3107	* the current mode.
3108	*/
3109	VMMR3DECL(int) PGMR3ChangeMode(PVM pVM, PGMMODE enmGuestMode)
3110	{
3111	Log(("PGMR3ChangeMode: Guest mode: %s -> %s\n", PGMGetModeName(pVM->pgm.s.enmGuestMode), PGMGetModeName(enmGuestMode)));
3112	STAM_REL_COUNTER_INC(&pVM->pgm.s.cGuestModeChanges);
3113
3114	/*
3115	* Calc the shadow mode and switcher.
3116	*/
3117	VMMSWITCHER enmSwitcher;
3118	PGMMODE enmShadowMode = pgmR3CalcShadowMode(pVM, enmGuestMode, pVM->pgm.s.enmHostMode, pVM->pgm.s.enmShadowMode, &enmSwitcher);
3119	if (enmSwitcher != VMMSWITCHER_INVALID)
3120	{
3121	/*
3122	* Select new switcher.
3123	*/
3124	int rc = VMMR3SelectSwitcher(pVM, enmSwitcher);
3125	if (VBOX_FAILURE(rc))
3126	{
3127	AssertReleaseMsgFailed(("VMMR3SelectSwitcher(%d) -> %Vrc\n", enmSwitcher, rc));
3128	return rc;
3129	}
3130	}
3131
3132	/*
3133	* Exit old mode(s).
3134	*/
3135	/* shadow */
3136	if (enmShadowMode != pVM->pgm.s.enmShadowMode)
3137	{
3138	LogFlow(("PGMR3ChangeMode: Shadow mode: %s -> %s\n", PGMGetModeName(pVM->pgm.s.enmShadowMode), PGMGetModeName(enmShadowMode)));
3139	if (PGM_SHW_PFN(Exit, pVM))
3140	{
3141	int rc = PGM_SHW_PFN(Exit, pVM)(pVM);
3142	if (VBOX_FAILURE(rc))
3143	{
3144	AssertMsgFailed(("Exit failed for shadow mode %d: %Vrc\n", pVM->pgm.s.enmShadowMode, rc));
3145	return rc;
3146	}
3147	}
3148
3149	}
3150	else
3151	LogFlow(("PGMR3ChangeMode: Shadow mode remains: %s\n", PGMGetModeName(pVM->pgm.s.enmShadowMode)));
3152
3153	/* guest */
3154	if (PGM_GST_PFN(Exit, pVM))
3155	{
3156	int rc = PGM_GST_PFN(Exit, pVM)(pVM);
3157	if (VBOX_FAILURE(rc))
3158	{
3159	AssertMsgFailed(("Exit failed for guest mode %d: %Vrc\n", pVM->pgm.s.enmGuestMode, rc));
3160	return rc;
3161	}
3162	}
3163
3164	/*
3165	* Load new paging mode data.
3166	*/
3167	pgmR3ModeDataSwitch(pVM, enmShadowMode, enmGuestMode);
3168
3169	/*
3170	* Enter new shadow mode (if changed).
3171	*/
3172	if (enmShadowMode != pVM->pgm.s.enmShadowMode)
3173	{
3174	int rc;
3175	pVM->pgm.s.enmShadowMode = enmShadowMode;
3176	switch (enmShadowMode)
3177	{
3178	case PGMMODE_32_BIT:
3179	rc = PGM_SHW_NAME_32BIT(Enter)(pVM);
3180	break;
3181	case PGMMODE_PAE:
3182	case PGMMODE_PAE_NX:
3183	rc = PGM_SHW_NAME_PAE(Enter)(pVM);
3184	break;
3185	case PGMMODE_AMD64:
3186	case PGMMODE_AMD64_NX:
3187	rc = PGM_SHW_NAME_AMD64(Enter)(pVM);
3188	break;
3189	case PGMMODE_NESTED:
3190	rc = PGM_SHW_NAME_NESTED(Enter)(pVM);
3191	break;
3192	case PGMMODE_EPT:
3193	rc = PGM_SHW_NAME_EPT(Enter)(pVM);
3194	break;
3195	case PGMMODE_REAL:
3196	case PGMMODE_PROTECTED:
3197	default:
3198	AssertReleaseMsgFailed(("enmShadowMode=%d\n", enmShadowMode));
3199	return VERR_INTERNAL_ERROR;
3200	}
3201	if (VBOX_FAILURE(rc))
3202	{
3203	AssertReleaseMsgFailed(("Entering enmShadowMode=%d failed: %Vrc\n", enmShadowMode, rc));
3204	pVM->pgm.s.enmShadowMode = PGMMODE_INVALID;
3205	return rc;
3206	}
3207	}
3208
3209	/* We must flush the PGM pool cache if the guest mode changes; we don't always
3210	* switch shadow paging mode (e.g. protected->32-bit) and shouldn't reuse
3211	* the shadow page tables.
3212	*
3213	* That only applies when switching between paging and non-paging modes.
3214	*
3215	* @todo A20 setting
3216	*/
3217	if ( pVM->pgm.s.CTX_SUFF(pPool)
3218	&& !HWACCMIsNestedPagingActive(pVM)
3219	&& PGMMODE_WITH_PAGING(pVM->pgm.s.enmGuestMode) != PGMMODE_WITH_PAGING(enmGuestMode))
3220	{
3221	Log(("PGMR3ChangeMode: changing guest paging mode -> flush pgm pool cache!\n"));
3222	pgmPoolFlushAll(pVM);
3223	}
3224
3225	/*
3226	* Enter the new guest and shadow+guest modes.
3227	*/
3228	int rc = -1;
3229	int rc2 = -1;
3230	RTGCPHYS GCPhysCR3 = NIL_RTGCPHYS;
3231	pVM->pgm.s.enmGuestMode = enmGuestMode;
3232	switch (enmGuestMode)
3233	{
3234	case PGMMODE_REAL:
3235	rc = PGM_GST_NAME_REAL(Enter)(pVM, NIL_RTGCPHYS);
3236	switch (pVM->pgm.s.enmShadowMode)
3237	{
3238	case PGMMODE_32_BIT:
3239	rc2 = PGM_BTH_NAME_32BIT_REAL(Enter)(pVM, NIL_RTGCPHYS);
3240	break;
3241	case PGMMODE_PAE:
3242	case PGMMODE_PAE_NX:
3243	rc2 = PGM_BTH_NAME_PAE_REAL(Enter)(pVM, NIL_RTGCPHYS);
3244	break;
3245	case PGMMODE_NESTED:
3246	rc2 = PGM_BTH_NAME_NESTED_REAL(Enter)(pVM, NIL_RTGCPHYS);
3247	break;
3248	case PGMMODE_EPT:
3249	rc2 = PGM_BTH_NAME_EPT_REAL(Enter)(pVM, NIL_RTGCPHYS);
3250	break;
3251	case PGMMODE_AMD64:
3252	case PGMMODE_AMD64_NX:
3253	AssertMsgFailed(("Should use PAE shadow mode!\n"));
3254	default: AssertFailed(); break;
3255	}
3256	break;
3257
3258	case PGMMODE_PROTECTED:
3259	rc = PGM_GST_NAME_PROT(Enter)(pVM, NIL_RTGCPHYS);
3260	switch (pVM->pgm.s.enmShadowMode)
3261	{
3262	case PGMMODE_32_BIT:
3263	rc2 = PGM_BTH_NAME_32BIT_PROT(Enter)(pVM, NIL_RTGCPHYS);
3264	break;
3265	case PGMMODE_PAE:
3266	case PGMMODE_PAE_NX:
3267	rc2 = PGM_BTH_NAME_PAE_PROT(Enter)(pVM, NIL_RTGCPHYS);
3268	break;
3269	case PGMMODE_NESTED:
3270	rc2 = PGM_BTH_NAME_NESTED_PROT(Enter)(pVM, NIL_RTGCPHYS);
3271	break;
3272	case PGMMODE_EPT:
3273	rc2 = PGM_BTH_NAME_EPT_PROT(Enter)(pVM, NIL_RTGCPHYS);
3274	break;
3275	case PGMMODE_AMD64:
3276	case PGMMODE_AMD64_NX:
3277	AssertMsgFailed(("Should use PAE shadow mode!\n"));
3278	default: AssertFailed(); break;
3279	}
3280	break;
3281
3282	case PGMMODE_32_BIT:
3283	GCPhysCR3 = CPUMGetGuestCR3(pVM) & X86_CR3_PAGE_MASK;
3284	rc = PGM_GST_NAME_32BIT(Enter)(pVM, GCPhysCR3);
3285	switch (pVM->pgm.s.enmShadowMode)
3286	{
3287	case PGMMODE_32_BIT:
3288	rc2 = PGM_BTH_NAME_32BIT_32BIT(Enter)(pVM, GCPhysCR3);
3289	break;
3290	case PGMMODE_PAE:
3291	case PGMMODE_PAE_NX:
3292	rc2 = PGM_BTH_NAME_PAE_32BIT(Enter)(pVM, GCPhysCR3);
3293	break;
3294	case PGMMODE_NESTED:
3295	rc2 = PGM_BTH_NAME_NESTED_32BIT(Enter)(pVM, GCPhysCR3);
3296	break;
3297	case PGMMODE_EPT:
3298	rc2 = PGM_BTH_NAME_EPT_32BIT(Enter)(pVM, GCPhysCR3);
3299	break;
3300	case PGMMODE_AMD64:
3301	case PGMMODE_AMD64_NX:
3302	AssertMsgFailed(("Should use PAE shadow mode!\n"));
3303	default: AssertFailed(); break;
3304	}
3305	break;
3306
3307	case PGMMODE_PAE_NX:
3308	case PGMMODE_PAE:
3309	{
3310	uint32_t u32Dummy, u32Features;
3311
3312	CPUMGetGuestCpuId(pVM, 1, &u32Dummy, &u32Dummy, &u32Dummy, &u32Features);
3313	if (!(u32Features & X86_CPUID_FEATURE_EDX_PAE))
3314	{
3315	/* Pause first, then inform Main. */
3316	rc = VMR3SuspendNoSave(pVM);
3317	AssertRC(rc);
3318
3319	VMSetRuntimeError(pVM, true, "PAEmode",
3320	N_("The guest is trying to switch to the PAE mode which is currently disabled by default in VirtualBox. Experimental PAE support can be enabled using the -pae option with VBoxManage"));
3321	/* we must return TRUE here otherwise the recompiler will assert */
3322	return VINF_SUCCESS;
3323	}
3324	GCPhysCR3 = CPUMGetGuestCR3(pVM) & X86_CR3_PAE_PAGE_MASK;
3325	rc = PGM_GST_NAME_PAE(Enter)(pVM, GCPhysCR3);
3326	switch (pVM->pgm.s.enmShadowMode)
3327	{
3328	case PGMMODE_PAE:
3329	case PGMMODE_PAE_NX:
3330	rc2 = PGM_BTH_NAME_PAE_PAE(Enter)(pVM, GCPhysCR3);
3331	break;
3332	case PGMMODE_NESTED:
3333	rc2 = PGM_BTH_NAME_NESTED_PAE(Enter)(pVM, GCPhysCR3);
3334	break;
3335	case PGMMODE_EPT:
3336	rc2 = PGM_BTH_NAME_EPT_PAE(Enter)(pVM, GCPhysCR3);
3337	break;
3338	case PGMMODE_32_BIT:
3339	case PGMMODE_AMD64:
3340	case PGMMODE_AMD64_NX:
3341	AssertMsgFailed(("Should use PAE shadow mode!\n"));
3342	default: AssertFailed(); break;
3343	}
3344	break;
3345	}
3346
3347	case PGMMODE_AMD64_NX:
3348	case PGMMODE_AMD64:
3349	GCPhysCR3 = CPUMGetGuestCR3(pVM) & 0xfffffffffffff000ULL; /** @todo define this mask! */
3350	rc = PGM_GST_NAME_AMD64(Enter)(pVM, GCPhysCR3);
3351	switch (pVM->pgm.s.enmShadowMode)
3352	{
3353	case PGMMODE_AMD64:
3354	case PGMMODE_AMD64_NX:
3355	rc2 = PGM_BTH_NAME_AMD64_AMD64(Enter)(pVM, GCPhysCR3);
3356	break;
3357	case PGMMODE_NESTED:
3358	rc2 = PGM_BTH_NAME_NESTED_AMD64(Enter)(pVM, GCPhysCR3);
3359	break;
3360	case PGMMODE_EPT:
3361	rc2 = PGM_BTH_NAME_EPT_AMD64(Enter)(pVM, GCPhysCR3);
3362	break;
3363	case PGMMODE_32_BIT:
3364	case PGMMODE_PAE:
3365	case PGMMODE_PAE_NX:
3366	AssertMsgFailed(("Should use AMD64 shadow mode!\n"));
3367	default: AssertFailed(); break;
3368	}
3369	break;
3370
3371	default:
3372	AssertReleaseMsgFailed(("enmGuestMode=%d\n", enmGuestMode));
3373	rc = VERR_NOT_IMPLEMENTED;
3374	break;
3375	}
3376
3377	/* status codes. */
3378	AssertRC(rc);
3379	AssertRC(rc2);
3380	if (VBOX_SUCCESS(rc))
3381	{
3382	rc = rc2;
3383	if (VBOX_SUCCESS(rc)) /* no informational status codes. */
3384	rc = VINF_SUCCESS;
3385	}
3386
3387	/*
3388	* Notify SELM so it can update the TSSes with correct CR3s.
3389	*/
3390	SELMR3PagingModeChanged(pVM);
3391
3392	/* Notify HWACCM as well. */
3393	HWACCMR3PagingModeChanged(pVM, pVM->pgm.s.enmShadowMode);
3394	return rc;
3395	}
3396
3397
3398	/**
3399	* Dumps a PAE shadow page table.
3400	*
3401	* @returns VBox status code (VINF_SUCCESS).
3402	* @param pVM The VM handle.
3403	* @param pPT Pointer to the page table.
3404	* @param u64Address The virtual address of the page table starts.
3405	* @param fLongMode Set if this a long mode table; clear if it's a legacy mode table.
3406	* @param cMaxDepth The maxium depth.
3407	* @param pHlp Pointer to the output functions.
3408	*/
3409	static int pgmR3DumpHierarchyHCPaePT(PVM pVM, PX86PTPAE pPT, uint64_t u64Address, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
3410	{
3411	for (unsigned i = 0; i < RT_ELEMENTS(pPT->a); i++)
3412	{
3413	X86PTEPAE Pte = pPT->a[i];
3414	if (Pte.n.u1Present)
3415	{
3416	pHlp->pfnPrintf(pHlp,
3417	fLongMode /P R S A D G WT CD AT NX 4M a p ? /
3418	? "%016llx 3 \| P %c %c %c %c %c %s %s %s %s 4K %c%c%c %016llx\n"
3419	: "%08llx 2 \| P %c %c %c %c %c %s %s %s %s 4K %c%c%c %016llx\n",
3420	u64Address + ((uint64_t)i << X86_PT_PAE_SHIFT),
3421	Pte.n.u1Write ? 'W' : 'R',
3422	Pte.n.u1User ? 'U' : 'S',
3423	Pte.n.u1Accessed ? 'A' : '-',
3424	Pte.n.u1Dirty ? 'D' : '-',
3425	Pte.n.u1Global ? 'G' : '-',
3426	Pte.n.u1WriteThru ? "WT" : "--",
3427	Pte.n.u1CacheDisable? "CD" : "--",
3428	Pte.n.u1PAT ? "AT" : "--",
3429	Pte.n.u1NoExecute ? "NX" : "--",
3430	Pte.u & PGM_PTFLAGS_TRACK_DIRTY ? 'd' : '-',
3431	Pte.u & RT_BIT(10) ? '1' : '0',
3432	Pte.u & PGM_PTFLAGS_CSAM_VALIDATED? 'v' : '-',
3433	Pte.u & X86_PTE_PAE_PG_MASK);
3434	}
3435	}
3436	return VINF_SUCCESS;
3437	}
3438
3439
3440	/**
3441	* Dumps a PAE shadow page directory table.
3442	*
3443	* @returns VBox status code (VINF_SUCCESS).
3444	* @param pVM The VM handle.
3445	* @param HCPhys The physical address of the page directory table.
3446	* @param u64Address The virtual address of the page table starts.
3447	* @param cr4 The CR4, PSE is currently used.
3448	* @param fLongMode Set if this a long mode table; clear if it's a legacy mode table.
3449	* @param cMaxDepth The maxium depth.
3450	* @param pHlp Pointer to the output functions.
3451	*/
3452	static int pgmR3DumpHierarchyHCPaePD(PVM pVM, RTHCPHYS HCPhys, uint64_t u64Address, uint32_t cr4, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
3453	{
3454	PX86PDPAE pPD = (PX86PDPAE)MMPagePhys2Page(pVM, HCPhys);
3455	if (!pPD)
3456	{
3457	pHlp->pfnPrintf(pHlp, "%0*llx error! Page directory at HCPhys=%#VHp was not found in the page pool!\n",
3458	fLongMode ? 16 : 8, u64Address, HCPhys);
3459	return VERR_INVALID_PARAMETER;
3460	}
3461	const bool fBigPagesSupported = fLongMode \|\| !!(cr4 & X86_CR4_PSE);
3462
3463	int rc = VINF_SUCCESS;
3464	for (unsigned i = 0; i < RT_ELEMENTS(pPD->a); i++)
3465	{
3466	X86PDEPAE Pde = pPD->a[i];
3467	if (Pde.n.u1Present)
3468	{
3469	if (fBigPagesSupported && Pde.b.u1Size)
3470	pHlp->pfnPrintf(pHlp,
3471	fLongMode /P R S A D G WT CD AT NX 4M a p ? /
3472	? "%016llx 2 \| P %c %c %c %c %c %s %s %s %s 4M %c%c%c %016llx\n"
3473	: "%08llx 1 \| P %c %c %c %c %c %s %s %s %s 4M %c%c%c %016llx\n",
3474	u64Address + ((uint64_t)i << X86_PD_PAE_SHIFT),
3475	Pde.b.u1Write ? 'W' : 'R',
3476	Pde.b.u1User ? 'U' : 'S',
3477	Pde.b.u1Accessed ? 'A' : '-',
3478	Pde.b.u1Dirty ? 'D' : '-',
3479	Pde.b.u1Global ? 'G' : '-',
3480	Pde.b.u1WriteThru ? "WT" : "--",
3481	Pde.b.u1CacheDisable? "CD" : "--",
3482	Pde.b.u1PAT ? "AT" : "--",
3483	Pde.b.u1NoExecute ? "NX" : "--",
3484	Pde.u & RT_BIT_64(9) ? '1' : '0',
3485	Pde.u & PGM_PDFLAGS_MAPPING ? 'm' : '-',
3486	Pde.u & PGM_PDFLAGS_TRACK_DIRTY ? 'd' : '-',
3487	Pde.u & X86_PDE_PAE_PG_MASK);
3488	else
3489	{
3490	pHlp->pfnPrintf(pHlp,
3491	fLongMode /P R S A D G WT CD AT NX 4M a p ? /
3492	? "%016llx 2 \| P %c %c %c %c %c %s %s .. %s 4K %c%c%c %016llx\n"
3493	: "%08llx 1 \| P %c %c %c %c %c %s %s .. %s 4K %c%c%c %016llx\n",
3494	u64Address + ((uint64_t)i << X86_PD_PAE_SHIFT),
3495	Pde.n.u1Write ? 'W' : 'R',
3496	Pde.n.u1User ? 'U' : 'S',
3497	Pde.n.u1Accessed ? 'A' : '-',
3498	Pde.n.u1Reserved0 ? '?' : '.', /* ignored */
3499	Pde.n.u1Reserved1 ? '?' : '.', /* ignored */
3500	Pde.n.u1WriteThru ? "WT" : "--",
3501	Pde.n.u1CacheDisable? "CD" : "--",
3502	Pde.n.u1NoExecute ? "NX" : "--",
3503	Pde.u & RT_BIT_64(9) ? '1' : '0',
3504	Pde.u & PGM_PDFLAGS_MAPPING ? 'm' : '-',
3505	Pde.u & PGM_PDFLAGS_TRACK_DIRTY ? 'd' : '-',
3506	Pde.u & X86_PDE_PAE_PG_MASK);
3507	if (cMaxDepth >= 1)
3508	{
3509	/** @todo what about using the page pool for mapping PTs? */
3510	uint64_t u64AddressPT = u64Address + ((uint64_t)i << X86_PD_PAE_SHIFT);
3511	RTHCPHYS HCPhysPT = Pde.u & X86_PDE_PAE_PG_MASK;
3512	PX86PTPAE pPT = NULL;
3513	if (!(Pde.u & PGM_PDFLAGS_MAPPING))
3514	pPT = (PX86PTPAE)MMPagePhys2Page(pVM, HCPhysPT);
3515	else
3516	{
3517	for (PPGMMAPPING pMap = pVM->pgm.s.pMappingsR3; pMap; pMap = pMap->pNextR3)
3518	{
3519	uint64_t off = u64AddressPT - pMap->GCPtr;
3520	if (off < pMap->cb)
3521	{
3522	const int iPDE = (uint32_t)(off >> X86_PD_SHIFT);
3523	const int iSub = (int)((off >> X86_PD_PAE_SHIFT) & 1); /* MSC is a pain sometimes */
3524	if ((iSub ? pMap->aPTs[iPDE].HCPhysPaePT1 : pMap->aPTs[iPDE].HCPhysPaePT0) != HCPhysPT)
3525	pHlp->pfnPrintf(pHlp, "%0*llx error! Mapping error! PT %d has HCPhysPT=%VHp not %VHp is in the PD.\n",
3526	fLongMode ? 16 : 8, u64AddressPT, iPDE,
3527	iSub ? pMap->aPTs[iPDE].HCPhysPaePT1 : pMap->aPTs[iPDE].HCPhysPaePT0, HCPhysPT);
3528	pPT = &pMap->aPTs[iPDE].paPaePTsR3[iSub];
3529	}
3530	}
3531	}
3532	int rc2 = VERR_INVALID_PARAMETER;
3533	if (pPT)
3534	rc2 = pgmR3DumpHierarchyHCPaePT(pVM, pPT, u64AddressPT, fLongMode, cMaxDepth - 1, pHlp);
3535	else
3536	pHlp->pfnPrintf(pHlp, "%0*llx error! Page table at HCPhys=%#VHp was not found in the page pool!\n",
3537	fLongMode ? 16 : 8, u64AddressPT, HCPhysPT);
3538	if (rc2 < rc && VBOX_SUCCESS(rc))
3539	rc = rc2;
3540	}
3541	}
3542	}
3543	}
3544	return rc;
3545	}
3546
3547
3548	/**
3549	* Dumps a PAE shadow page directory pointer table.
3550	*
3551	* @returns VBox status code (VINF_SUCCESS).
3552	* @param pVM The VM handle.
3553	* @param HCPhys The physical address of the page directory pointer table.
3554	* @param u64Address The virtual address of the page table starts.
3555	* @param cr4 The CR4, PSE is currently used.
3556	* @param fLongMode Set if this a long mode table; clear if it's a legacy mode table.
3557	* @param cMaxDepth The maxium depth.
3558	* @param pHlp Pointer to the output functions.
3559	*/
3560	static int pgmR3DumpHierarchyHCPaePDPT(PVM pVM, RTHCPHYS HCPhys, uint64_t u64Address, uint32_t cr4, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
3561	{
3562	PX86PDPT pPDPT = (PX86PDPT)MMPagePhys2Page(pVM, HCPhys);
3563	if (!pPDPT)
3564	{
3565	pHlp->pfnPrintf(pHlp, "%0*llx error! Page directory pointer table at HCPhys=%#VHp was not found in the page pool!\n",
3566	fLongMode ? 16 : 8, u64Address, HCPhys);
3567	return VERR_INVALID_PARAMETER;
3568	}
3569
3570	int rc = VINF_SUCCESS;
3571	const unsigned c = fLongMode ? RT_ELEMENTS(pPDPT->a) : X86_PG_PAE_PDPE_ENTRIES;
3572	for (unsigned i = 0; i < c; i++)
3573	{
3574	X86PDPE Pdpe = pPDPT->a[i];
3575	if (Pdpe.n.u1Present)
3576	{
3577	if (fLongMode)
3578	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a p ? /
3579	"%016llx 1 \| P %c %c %c %c %c %s %s %s %s .. %c%c%c %016llx\n",
3580	u64Address + ((uint64_t)i << X86_PDPT_SHIFT),
3581	Pdpe.lm.u1Write ? 'W' : 'R',
3582	Pdpe.lm.u1User ? 'U' : 'S',
3583	Pdpe.lm.u1Accessed ? 'A' : '-',
3584	Pdpe.lm.u3Reserved & 1? '?' : '.', /* ignored */
3585	Pdpe.lm.u3Reserved & 4? '!' : '.', /* mbz */
3586	Pdpe.lm.u1WriteThru ? "WT" : "--",
3587	Pdpe.lm.u1CacheDisable? "CD" : "--",
3588	Pdpe.lm.u3Reserved & 2? "!" : "..",/* mbz */
3589	Pdpe.lm.u1NoExecute ? "NX" : "--",
3590	Pdpe.u & RT_BIT(9) ? '1' : '0',
3591	Pdpe.u & PGM_PLXFLAGS_PERMANENT ? 'p' : '-',
3592	Pdpe.u & RT_BIT(11) ? '1' : '0',
3593	Pdpe.u & X86_PDPE_PG_MASK);
3594	else
3595	pHlp->pfnPrintf(pHlp, /P G WT CD AT NX 4M a p ? /
3596	"%08x 0 \| P %c %s %s %s %s .. %c%c%c %016llx\n",
3597	i << X86_PDPT_SHIFT,
3598	Pdpe.n.u4Reserved & 1? '!' : '.', /* mbz */
3599	Pdpe.n.u4Reserved & 4? '!' : '.', /* mbz */
3600	Pdpe.n.u1WriteThru ? "WT" : "--",
3601	Pdpe.n.u1CacheDisable? "CD" : "--",
3602	Pdpe.n.u4Reserved & 2? "!" : "..",/* mbz */
3603	Pdpe.u & RT_BIT(9) ? '1' : '0',
3604	Pdpe.u & PGM_PLXFLAGS_PERMANENT ? 'p' : '-',
3605	Pdpe.u & RT_BIT(11) ? '1' : '0',
3606	Pdpe.u & X86_PDPE_PG_MASK);
3607	if (cMaxDepth >= 1)
3608	{
3609	int rc2 = pgmR3DumpHierarchyHCPaePD(pVM, Pdpe.u & X86_PDPE_PG_MASK, u64Address + ((uint64_t)i << X86_PDPT_SHIFT),
3610	cr4, fLongMode, cMaxDepth - 1, pHlp);
3611	if (rc2 < rc && VBOX_SUCCESS(rc))
3612	rc = rc2;
3613	}
3614	}
3615	}
3616	return rc;
3617	}
3618
3619
3620	/**
3621	* Dumps a 32-bit shadow page table.
3622	*
3623	* @returns VBox status code (VINF_SUCCESS).
3624	* @param pVM The VM handle.
3625	* @param HCPhys The physical address of the table.
3626	* @param cr4 The CR4, PSE is currently used.
3627	* @param cMaxDepth The maxium depth.
3628	* @param pHlp Pointer to the output functions.
3629	*/
3630	static int pgmR3DumpHierarchyHcPaePML4(PVM pVM, RTHCPHYS HCPhys, uint32_t cr4, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
3631	{
3632	PX86PML4 pPML4 = (PX86PML4)MMPagePhys2Page(pVM, HCPhys);
3633	if (!pPML4)
3634	{
3635	pHlp->pfnPrintf(pHlp, "Page map level 4 at HCPhys=%#VHp was not found in the page pool!\n", HCPhys);
3636	return VERR_INVALID_PARAMETER;
3637	}
3638
3639	int rc = VINF_SUCCESS;
3640	for (unsigned i = 0; i < RT_ELEMENTS(pPML4->a); i++)
3641	{
3642	X86PML4E Pml4e = pPML4->a[i];
3643	if (Pml4e.n.u1Present)
3644	{
3645	uint64_t u64Address = ((uint64_t)i << X86_PML4_SHIFT) \| (((uint64_t)i >> (X86_PML4_SHIFT - X86_PDPT_SHIFT - 1)) * 0xffff000000000000ULL);
3646	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a p ? /
3647	"%016llx 0 \| P %c %c %c %c %c %s %s %s %s .. %c%c%c %016llx\n",
3648	u64Address,
3649	Pml4e.n.u1Write ? 'W' : 'R',
3650	Pml4e.n.u1User ? 'U' : 'S',
3651	Pml4e.n.u1Accessed ? 'A' : '-',
3652	Pml4e.n.u3Reserved & 1? '?' : '.', /* ignored */
3653	Pml4e.n.u3Reserved & 4? '!' : '.', /* mbz */
3654	Pml4e.n.u1WriteThru ? "WT" : "--",
3655	Pml4e.n.u1CacheDisable? "CD" : "--",
3656	Pml4e.n.u3Reserved & 2? "!" : "..",/* mbz */
3657	Pml4e.n.u1NoExecute ? "NX" : "--",
3658	Pml4e.u & RT_BIT(9) ? '1' : '0',
3659	Pml4e.u & PGM_PLXFLAGS_PERMANENT ? 'p' : '-',
3660	Pml4e.u & RT_BIT(11) ? '1' : '0',
3661	Pml4e.u & X86_PML4E_PG_MASK);
3662
3663	if (cMaxDepth >= 1)
3664	{
3665	int rc2 = pgmR3DumpHierarchyHCPaePDPT(pVM, Pml4e.u & X86_PML4E_PG_MASK, u64Address, cr4, true, cMaxDepth - 1, pHlp);
3666	if (rc2 < rc && VBOX_SUCCESS(rc))
3667	rc = rc2;
3668	}
3669	}
3670	}
3671	return rc;
3672	}
3673
3674
3675	/**
3676	* Dumps a 32-bit shadow page table.
3677	*
3678	* @returns VBox status code (VINF_SUCCESS).
3679	* @param pVM The VM handle.
3680	* @param pPT Pointer to the page table.
3681	* @param u32Address The virtual address this table starts at.
3682	* @param pHlp Pointer to the output functions.
3683	*/
3684	int pgmR3DumpHierarchyHC32BitPT(PVM pVM, PX86PT pPT, uint32_t u32Address, PCDBGFINFOHLP pHlp)
3685	{
3686	for (unsigned i = 0; i < RT_ELEMENTS(pPT->a); i++)
3687	{
3688	X86PTE Pte = pPT->a[i];
3689	if (Pte.n.u1Present)
3690	{
3691	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a m d /
3692	"%08x 1 \| P %c %c %c %c %c %s %s %s .. 4K %c%c%c %08x\n",
3693	u32Address + (i << X86_PT_SHIFT),
3694	Pte.n.u1Write ? 'W' : 'R',
3695	Pte.n.u1User ? 'U' : 'S',
3696	Pte.n.u1Accessed ? 'A' : '-',
3697	Pte.n.u1Dirty ? 'D' : '-',
3698	Pte.n.u1Global ? 'G' : '-',
3699	Pte.n.u1WriteThru ? "WT" : "--",
3700	Pte.n.u1CacheDisable? "CD" : "--",
3701	Pte.n.u1PAT ? "AT" : "--",
3702	Pte.u & PGM_PTFLAGS_TRACK_DIRTY ? 'd' : '-',
3703	Pte.u & RT_BIT(10) ? '1' : '0',
3704	Pte.u & PGM_PTFLAGS_CSAM_VALIDATED ? 'v' : '-',
3705	Pte.u & X86_PDE_PG_MASK);
3706	}
3707	}
3708	return VINF_SUCCESS;
3709	}
3710
3711
3712	/**
3713	* Dumps a 32-bit shadow page directory and page tables.
3714	*
3715	* @returns VBox status code (VINF_SUCCESS).
3716	* @param pVM The VM handle.
3717	* @param cr3 The root of the hierarchy.
3718	* @param cr4 The CR4, PSE is currently used.
3719	* @param cMaxDepth How deep into the hierarchy the dumper should go.
3720	* @param pHlp Pointer to the output functions.
3721	*/
3722	int pgmR3DumpHierarchyHC32BitPD(PVM pVM, uint32_t cr3, uint32_t cr4, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
3723	{
3724	PX86PD pPD = (PX86PD)MMPagePhys2Page(pVM, cr3 & X86_CR3_PAGE_MASK);
3725	if (!pPD)
3726	{
3727	pHlp->pfnPrintf(pHlp, "Page directory at %#x was not found in the page pool!\n", cr3 & X86_CR3_PAGE_MASK);
3728	return VERR_INVALID_PARAMETER;
3729	}
3730
3731	int rc = VINF_SUCCESS;
3732	for (unsigned i = 0; i < RT_ELEMENTS(pPD->a); i++)
3733	{
3734	X86PDE Pde = pPD->a[i];
3735	if (Pde.n.u1Present)
3736	{
3737	const uint32_t u32Address = i << X86_PD_SHIFT;
3738	if ((cr4 & X86_CR4_PSE) && Pde.b.u1Size)
3739	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a m d /
3740	"%08x 0 \| P %c %c %c %c %c %s %s %s .. 4M %c%c%c %08x\n",
3741	u32Address,
3742	Pde.b.u1Write ? 'W' : 'R',
3743	Pde.b.u1User ? 'U' : 'S',
3744	Pde.b.u1Accessed ? 'A' : '-',
3745	Pde.b.u1Dirty ? 'D' : '-',
3746	Pde.b.u1Global ? 'G' : '-',
3747	Pde.b.u1WriteThru ? "WT" : "--",
3748	Pde.b.u1CacheDisable? "CD" : "--",
3749	Pde.b.u1PAT ? "AT" : "--",
3750	Pde.u & RT_BIT_64(9) ? '1' : '0',
3751	Pde.u & PGM_PDFLAGS_MAPPING ? 'm' : '-',
3752	Pde.u & PGM_PDFLAGS_TRACK_DIRTY ? 'd' : '-',
3753	Pde.u & X86_PDE4M_PG_MASK);
3754	else
3755	{
3756	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a m d /
3757	"%08x 0 \| P %c %c %c %c %c %s %s .. .. 4K %c%c%c %08x\n",
3758	u32Address,
3759	Pde.n.u1Write ? 'W' : 'R',
3760	Pde.n.u1User ? 'U' : 'S',
3761	Pde.n.u1Accessed ? 'A' : '-',
3762	Pde.n.u1Reserved0 ? '?' : '.', /* ignored */
3763	Pde.n.u1Reserved1 ? '?' : '.', /* ignored */
3764	Pde.n.u1WriteThru ? "WT" : "--",
3765	Pde.n.u1CacheDisable? "CD" : "--",
3766	Pde.u & RT_BIT_64(9) ? '1' : '0',
3767	Pde.u & PGM_PDFLAGS_MAPPING ? 'm' : '-',
3768	Pde.u & PGM_PDFLAGS_TRACK_DIRTY ? 'd' : '-',
3769	Pde.u & X86_PDE_PG_MASK);
3770	if (cMaxDepth >= 1)
3771	{
3772	/** @todo what about using the page pool for mapping PTs? */
3773	RTHCPHYS HCPhys = Pde.u & X86_PDE_PG_MASK;
3774	PX86PT pPT = NULL;
3775	if (!(Pde.u & PGM_PDFLAGS_MAPPING))
3776	pPT = (PX86PT)MMPagePhys2Page(pVM, HCPhys);
3777	else
3778	{
3779	for (PPGMMAPPING pMap = pVM->pgm.s.pMappingsR3; pMap; pMap = pMap->pNextR3)
3780	if (u32Address - pMap->GCPtr < pMap->cb)
3781	{
3782	int iPDE = (u32Address - pMap->GCPtr) >> X86_PD_SHIFT;
3783	if (pMap->aPTs[iPDE].HCPhysPT != HCPhys)
3784	pHlp->pfnPrintf(pHlp, "%08x error! Mapping error! PT %d has HCPhysPT=%VHp not %VHp is in the PD.\n",
3785	u32Address, iPDE, pMap->aPTs[iPDE].HCPhysPT, HCPhys);
3786	pPT = pMap->aPTs[iPDE].pPTR3;
3787	}
3788	}
3789	int rc2 = VERR_INVALID_PARAMETER;
3790	if (pPT)
3791	rc2 = pgmR3DumpHierarchyHC32BitPT(pVM, pPT, u32Address, pHlp);
3792	else
3793	pHlp->pfnPrintf(pHlp, "%08x error! Page table at %#x was not found in the page pool!\n", u32Address, HCPhys);
3794	if (rc2 < rc && VBOX_SUCCESS(rc))
3795	rc = rc2;
3796	}
3797	}
3798	}
3799	}
3800
3801	return rc;
3802	}
3803
3804
3805	/**
3806	* Dumps a 32-bit shadow page table.
3807	*
3808	* @returns VBox status code (VINF_SUCCESS).
3809	* @param pVM The VM handle.
3810	* @param pPT Pointer to the page table.
3811	* @param u32Address The virtual address this table starts at.
3812	* @param PhysSearch Address to search for.
3813	*/
3814	int pgmR3DumpHierarchyGC32BitPT(PVM pVM, PX86PT pPT, uint32_t u32Address, RTGCPHYS PhysSearch)
3815	{
3816	for (unsigned i = 0; i < RT_ELEMENTS(pPT->a); i++)
3817	{
3818	X86PTE Pte = pPT->a[i];
3819	if (Pte.n.u1Present)
3820	{
3821	Log(( /P R S A D G WT CD AT NX 4M a m d /
3822	"%08x 1 \| P %c %c %c %c %c %s %s %s .. 4K %c%c%c %08x\n",
3823	u32Address + (i << X86_PT_SHIFT),
3824	Pte.n.u1Write ? 'W' : 'R',
3825	Pte.n.u1User ? 'U' : 'S',
3826	Pte.n.u1Accessed ? 'A' : '-',
3827	Pte.n.u1Dirty ? 'D' : '-',
3828	Pte.n.u1Global ? 'G' : '-',
3829	Pte.n.u1WriteThru ? "WT" : "--",
3830	Pte.n.u1CacheDisable? "CD" : "--",
3831	Pte.n.u1PAT ? "AT" : "--",
3832	Pte.u & PGM_PTFLAGS_TRACK_DIRTY ? 'd' : '-',
3833	Pte.u & RT_BIT(10) ? '1' : '0',
3834	Pte.u & PGM_PTFLAGS_CSAM_VALIDATED ? 'v' : '-',
3835	Pte.u & X86_PDE_PG_MASK));
3836
3837	if ((Pte.u & X86_PDE_PG_MASK) == PhysSearch)
3838	{
3839	uint64_t fPageShw = 0;
3840	RTHCPHYS pPhysHC = 0;
3841
3842	PGMShwGetPage(pVM, (RTGCPTR)(u32Address + (i << X86_PT_SHIFT)), &fPageShw, &pPhysHC);
3843	Log(("Found %VGp at %VGv -> flags=%llx\n", PhysSearch, (RTGCPTR)(u32Address + (i << X86_PT_SHIFT)), fPageShw));
3844	}
3845	}
3846	}
3847	return VINF_SUCCESS;
3848	}
3849
3850
3851	/**
3852	* Dumps a 32-bit guest page directory and page tables.
3853	*
3854	* @returns VBox status code (VINF_SUCCESS).
3855	* @param pVM The VM handle.
3856	* @param cr3 The root of the hierarchy.
3857	* @param cr4 The CR4, PSE is currently used.
3858	* @param PhysSearch Address to search for.
3859	*/
3860	VMMR3DECL(int) PGMR3DumpHierarchyGC(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCPHYS PhysSearch)
3861	{
3862	bool fLongMode = false;
3863	const unsigned cch = fLongMode ? 16 : 8; NOREF(cch);
3864	PX86PD pPD = 0;
3865
3866	int rc = PGM_GCPHYS_2_PTR(pVM, cr3 & X86_CR3_PAGE_MASK, &pPD);
3867	if (VBOX_FAILURE(rc) \|\| !pPD)
3868	{
3869	Log(("Page directory at %#x was not found in the page pool!\n", cr3 & X86_CR3_PAGE_MASK));
3870	return VERR_INVALID_PARAMETER;
3871	}
3872
3873	Log(("cr3=%08x cr4=%08x%s\n"
3874	"%-*s P - Present\n"
3875	"%-*s \| R/W - Read (0) / Write (1)\n"
3876	"%-*s \| \| U/S - User (1) / Supervisor (0)\n"
3877	"%-*s \| \| \| A - Accessed\n"
3878	"%-*s \| \| \| \| D - Dirty\n"
3879	"%-*s \| \| \| \| \| G - Global\n"
3880	"%-*s \| \| \| \| \| \| WT - Write thru\n"
3881	"%-*s \| \| \| \| \| \| \| CD - Cache disable\n"
3882	"%-*s \| \| \| \| \| \| \| \| AT - Attribute table (PAT)\n"
3883	"%-*s \| \| \| \| \| \| \| \| \| NX - No execute (K8)\n"
3884	"%-*s \| \| \| \| \| \| \| \| \| \| 4K/4M/2M - Page size.\n"
3885	"%-*s \| \| \| \| \| \| \| \| \| \| \| AVL - a=allocated; m=mapping; d=track dirty;\n"
3886	"%-*s \| \| \| \| \| \| \| \| \| \| \| \| p=permanent; v=validated;\n"
3887	"%-*s Level \| \| \| \| \| \| \| \| \| \| \| \| Page\n"
3888	/* xxxx n **** P R S A D G WT CD AT NX 4M AVL xxxxxxxxxxxxx
3889	- W U - - - -- -- -- -- -- 010 */
3890	, cr3, cr4, fLongMode ? " Long Mode" : "",
3891	cch, "", cch, "", cch, "", cch, "", cch, "", cch, "", cch, "",
3892	cch, "", cch, "", cch, "", cch, "", cch, "", cch, "", cch, "Address"));
3893
3894	for (unsigned i = 0; i < RT_ELEMENTS(pPD->a); i++)
3895	{
3896	X86PDE Pde = pPD->a[i];
3897	if (Pde.n.u1Present)
3898	{
3899	const uint32_t u32Address = i << X86_PD_SHIFT;
3900
3901	if ((cr4 & X86_CR4_PSE) && Pde.b.u1Size)
3902	Log(( /P R S A D G WT CD AT NX 4M a m d /
3903	"%08x 0 \| P %c %c %c %c %c %s %s %s .. 4M %c%c%c %08x\n",
3904	u32Address,
3905	Pde.b.u1Write ? 'W' : 'R',
3906	Pde.b.u1User ? 'U' : 'S',
3907	Pde.b.u1Accessed ? 'A' : '-',
3908	Pde.b.u1Dirty ? 'D' : '-',
3909	Pde.b.u1Global ? 'G' : '-',
3910	Pde.b.u1WriteThru ? "WT" : "--",
3911	Pde.b.u1CacheDisable? "CD" : "--",
3912	Pde.b.u1PAT ? "AT" : "--",
3913	Pde.u & RT_BIT(9) ? '1' : '0',
3914	Pde.u & RT_BIT(10) ? '1' : '0',
3915	Pde.u & RT_BIT(11) ? '1' : '0',
3916	pgmGstGet4MBPhysPage(&pVM->pgm.s, Pde)));
3917	/** @todo PhysSearch */
3918	else
3919	{
3920	Log(( /P R S A D G WT CD AT NX 4M a m d /
3921	"%08x 0 \| P %c %c %c %c %c %s %s .. .. 4K %c%c%c %08x\n",
3922	u32Address,
3923	Pde.n.u1Write ? 'W' : 'R',
3924	Pde.n.u1User ? 'U' : 'S',
3925	Pde.n.u1Accessed ? 'A' : '-',
3926	Pde.n.u1Reserved0 ? '?' : '.', /* ignored */
3927	Pde.n.u1Reserved1 ? '?' : '.', /* ignored */
3928	Pde.n.u1WriteThru ? "WT" : "--",
3929	Pde.n.u1CacheDisable? "CD" : "--",
3930	Pde.u & RT_BIT(9) ? '1' : '0',
3931	Pde.u & RT_BIT(10) ? '1' : '0',
3932	Pde.u & RT_BIT(11) ? '1' : '0',
3933	Pde.u & X86_PDE_PG_MASK));
3934	////if (cMaxDepth >= 1)
3935	{
3936	/** @todo what about using the page pool for mapping PTs? */
3937	RTGCPHYS GCPhys = Pde.u & X86_PDE_PG_MASK;
3938	PX86PT pPT = NULL;
3939
3940	rc = PGM_GCPHYS_2_PTR(pVM, GCPhys, &pPT);
3941
3942	int rc2 = VERR_INVALID_PARAMETER;
3943	if (pPT)
3944	rc2 = pgmR3DumpHierarchyGC32BitPT(pVM, pPT, u32Address, PhysSearch);
3945	else
3946	Log(("%08x error! Page table at %#x was not found in the page pool!\n", u32Address, GCPhys));
3947	if (rc2 < rc && VBOX_SUCCESS(rc))
3948	rc = rc2;
3949	}
3950	}
3951	}
3952	}
3953
3954	return rc;
3955	}
3956
3957
3958	/**
3959	* Dumps a page table hierarchy use only physical addresses and cr4/lm flags.
3960	*
3961	* @returns VBox status code (VINF_SUCCESS).
3962	* @param pVM The VM handle.
3963	* @param cr3 The root of the hierarchy.
3964	* @param cr4 The cr4, only PAE and PSE is currently used.
3965	* @param fLongMode Set if long mode, false if not long mode.
3966	* @param cMaxDepth Number of levels to dump.
3967	* @param pHlp Pointer to the output functions.
3968	*/
3969	VMMR3DECL(int) PGMR3DumpHierarchyHC(PVM pVM, uint64_t cr3, uint64_t cr4, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
3970	{
3971	if (!pHlp)
3972	pHlp = DBGFR3InfoLogHlp();
3973	if (!cMaxDepth)
3974	return VINF_SUCCESS;
3975	const unsigned cch = fLongMode ? 16 : 8;
3976	pHlp->pfnPrintf(pHlp,
3977	"cr3=%08x cr4=%08x%s\n"
3978	"%-*s P - Present\n"
3979	"%-*s \| R/W - Read (0) / Write (1)\n"
3980	"%-*s \| \| U/S - User (1) / Supervisor (0)\n"
3981	"%-*s \| \| \| A - Accessed\n"
3982	"%-*s \| \| \| \| D - Dirty\n"
3983	"%-*s \| \| \| \| \| G - Global\n"
3984	"%-*s \| \| \| \| \| \| WT - Write thru\n"
3985	"%-*s \| \| \| \| \| \| \| CD - Cache disable\n"
3986	"%-*s \| \| \| \| \| \| \| \| AT - Attribute table (PAT)\n"
3987	"%-*s \| \| \| \| \| \| \| \| \| NX - No execute (K8)\n"
3988	"%-*s \| \| \| \| \| \| \| \| \| \| 4K/4M/2M - Page size.\n"
3989	"%-*s \| \| \| \| \| \| \| \| \| \| \| AVL - a=allocated; m=mapping; d=track dirty;\n"
3990	"%-*s \| \| \| \| \| \| \| \| \| \| \| \| p=permanent; v=validated;\n"
3991	"%-*s Level \| \| \| \| \| \| \| \| \| \| \| \| Page\n"
3992	/* xxxx n **** P R S A D G WT CD AT NX 4M AVL xxxxxxxxxxxxx
3993	- W U - - - -- -- -- -- -- 010 */
3994	, cr3, cr4, fLongMode ? " Long Mode" : "",
3995	cch, "", cch, "", cch, "", cch, "", cch, "", cch, "", cch, "",
3996	cch, "", cch, "", cch, "", cch, "", cch, "", cch, "", cch, "Address");
3997	if (cr4 & X86_CR4_PAE)
3998	{
3999	if (fLongMode)
4000	return pgmR3DumpHierarchyHcPaePML4(pVM, cr3 & X86_CR3_PAGE_MASK, cr4, cMaxDepth, pHlp);
4001	return pgmR3DumpHierarchyHCPaePDPT(pVM, cr3 & X86_CR3_PAE_PAGE_MASK, 0, cr4, false, cMaxDepth, pHlp);
4002	}
4003	return pgmR3DumpHierarchyHC32BitPD(pVM, cr3 & X86_CR3_PAGE_MASK, cr4, cMaxDepth, pHlp);
4004	}
4005
4006
4007
4008	#ifdef VBOX_WITH_DEBUGGER
4009	/**
4010	* The '.pgmram' command.
4011	*
4012	* @returns VBox status.
4013	* @param pCmd Pointer to the command descriptor (as registered).
4014	* @param pCmdHlp Pointer to command helper functions.
4015	* @param pVM Pointer to the current VM (if any).
4016	* @param paArgs Pointer to (readonly) array of arguments.
4017	* @param cArgs Number of arguments in the array.
4018	*/
4019	static DECLCALLBACK(int) pgmR3CmdRam(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4020	{
4021	/*
4022	* Validate input.
4023	*/
4024	if (!pVM)
4025	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4026	if (!pVM->pgm.s.pRamRangesRC)
4027	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Sorry, no Ram is registered.\n");
4028
4029	/*
4030	* Dump the ranges.
4031	*/
4032	int rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL, "From - To (incl) pvHC\n");
4033	PPGMRAMRANGE pRam;
4034	for (pRam = pVM->pgm.s.pRamRangesR3; pRam; pRam = pRam->pNextR3)
4035	{
4036	rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL,
4037	"%RGp - %RGp %p\n",
4038	pRam->GCPhys, pRam->GCPhysLast, pRam->pvR3);
4039	if (VBOX_FAILURE(rc))
4040	return rc;
4041	}
4042
4043	return VINF_SUCCESS;
4044	}
4045
4046
4047	/**
4048	* The '.pgmmap' command.
4049	*
4050	* @returns VBox status.
4051	* @param pCmd Pointer to the command descriptor (as registered).
4052	* @param pCmdHlp Pointer to command helper functions.
4053	* @param pVM Pointer to the current VM (if any).
4054	* @param paArgs Pointer to (readonly) array of arguments.
4055	* @param cArgs Number of arguments in the array.
4056	*/
4057	static DECLCALLBACK(int) pgmR3CmdMap(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4058	{
4059	/*
4060	* Validate input.
4061	*/
4062	if (!pVM)
4063	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4064	if (!pVM->pgm.s.pMappingsR3)
4065	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Sorry, no mappings are registered.\n");
4066
4067	/*
4068	* Print message about the fixedness of the mappings.
4069	*/
4070	int rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL, pVM->pgm.s.fMappingsFixed ? "The mappings are FIXED.\n" : "The mappings are FLOATING.\n");
4071	if (VBOX_FAILURE(rc))
4072	return rc;
4073
4074	/*
4075	* Dump the ranges.
4076	*/
4077	PPGMMAPPING pCur;
4078	for (pCur = pVM->pgm.s.pMappingsR3; pCur; pCur = pCur->pNextR3)
4079	{
4080	rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL,
4081	"%08x - %08x %s\n",
4082	pCur->GCPtr, pCur->GCPtrLast, pCur->pszDesc);
4083	if (VBOX_FAILURE(rc))
4084	return rc;
4085	}
4086
4087	return VINF_SUCCESS;
4088	}
4089
4090
4091	/**
4092	* The '.pgmsync' command.
4093	*
4094	* @returns VBox status.
4095	* @param pCmd Pointer to the command descriptor (as registered).
4096	* @param pCmdHlp Pointer to command helper functions.
4097	* @param pVM Pointer to the current VM (if any).
4098	* @param paArgs Pointer to (readonly) array of arguments.
4099	* @param cArgs Number of arguments in the array.
4100	*/
4101	static DECLCALLBACK(int) pgmR3CmdSync(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4102	{
4103	/*
4104	* Validate input.
4105	*/
4106	if (!pVM)
4107	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4108
4109	/*
4110	* Force page directory sync.
4111	*/
4112	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
4113
4114	int rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Forcing page directory sync.\n");
4115	if (VBOX_FAILURE(rc))
4116	return rc;
4117
4118	return VINF_SUCCESS;
4119	}
4120
4121
4122	#ifdef VBOX_STRICT
4123	/**
4124	* The '.pgmassertcr3' command.
4125	*
4126	* @returns VBox status.
4127	* @param pCmd Pointer to the command descriptor (as registered).
4128	* @param pCmdHlp Pointer to command helper functions.
4129	* @param pVM Pointer to the current VM (if any).
4130	* @param paArgs Pointer to (readonly) array of arguments.
4131	* @param cArgs Number of arguments in the array.
4132	*/
4133	static DECLCALLBACK(int) pgmR3CmdAssertCR3(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4134	{
4135	/*
4136	* Validate input.
4137	*/
4138	if (!pVM)
4139	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4140
4141	int rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Checking shadow CR3 page tables for consistency.\n");
4142	if (VBOX_FAILURE(rc))
4143	return rc;
4144
4145	PGMAssertCR3(pVM, CPUMGetGuestCR3(pVM), CPUMGetGuestCR4(pVM));
4146
4147	return VINF_SUCCESS;
4148	}
4149	#endif
4150
4151	/**
4152	* The '.pgmsyncalways' command.
4153	*
4154	* @returns VBox status.
4155	* @param pCmd Pointer to the command descriptor (as registered).
4156	* @param pCmdHlp Pointer to command helper functions.
4157	* @param pVM Pointer to the current VM (if any).
4158	* @param paArgs Pointer to (readonly) array of arguments.
4159	* @param cArgs Number of arguments in the array.
4160	*/
4161	static DECLCALLBACK(int) pgmR3CmdSyncAlways(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4162	{
4163	/*
4164	* Validate input.
4165	*/
4166	if (!pVM)
4167	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4168
4169	/*
4170	* Force page directory sync.
4171	*/
4172	if (pVM->pgm.s.fSyncFlags & PGM_SYNC_ALWAYS)
4173	{
4174	ASMAtomicAndU32(&pVM->pgm.s.fSyncFlags, ~PGM_SYNC_ALWAYS);
4175	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Disabled permanent forced page directory syncing.\n");
4176	}
4177	else
4178	{
4179	ASMAtomicOrU32(&pVM->pgm.s.fSyncFlags, PGM_SYNC_ALWAYS);
4180	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
4181	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Enabled permanent forced page directory syncing.\n");
4182	}
4183	}
4184
4185	#endif
4186
4187	/**
4188	* pvUser argument of the pgmR3CheckIntegrity*Node callbacks.
4189	*/
4190	typedef struct PGMCHECKINTARGS
4191	{
4192	bool fLeftToRight; /*< true: left-to-right; false: right-to-left. /
4193	PPGMPHYSHANDLER pPrevPhys;
4194	PPGMVIRTHANDLER pPrevVirt;
4195	PPGMPHYS2VIRTHANDLER pPrevPhys2Virt;
4196	PVM pVM;
4197	} PGMCHECKINTARGS, *PPGMCHECKINTARGS;
4198
4199	/**
4200	* Validate a node in the physical handler tree.
4201	*
4202	* @returns 0 on if ok, other wise 1.
4203	* @param pNode The handler node.
4204	* @param pvUser pVM.
4205	*/
4206	static DECLCALLBACK(int) pgmR3CheckIntegrityPhysHandlerNode(PAVLROGCPHYSNODECORE pNode, void *pvUser)
4207	{
4208	PPGMCHECKINTARGS pArgs = (PPGMCHECKINTARGS)pvUser;
4209	PPGMPHYSHANDLER pCur = (PPGMPHYSHANDLER)pNode;
4210	AssertReleaseReturn(!((uintptr_t)pCur & 7), 1);
4211	AssertReleaseMsg(pCur->Core.Key <= pCur->Core.KeyLast,("pCur=%p %VGp-%VGp %s\n", pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
4212	AssertReleaseMsg( !pArgs->pPrevPhys
4213	\|\| (pArgs->fLeftToRight ? pArgs->pPrevPhys->Core.KeyLast < pCur->Core.Key : pArgs->pPrevPhys->Core.KeyLast > pCur->Core.Key),
4214	("pPrevPhys=%p %VGp-%VGp %s\n"
4215	" pCur=%p %VGp-%VGp %s\n",
4216	pArgs->pPrevPhys, pArgs->pPrevPhys->Core.Key, pArgs->pPrevPhys->Core.KeyLast, pArgs->pPrevPhys->pszDesc,
4217	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
4218	pArgs->pPrevPhys = pCur;
4219	return 0;
4220	}
4221
4222
4223	/**
4224	* Validate a node in the virtual handler tree.
4225	*
4226	* @returns 0 on if ok, other wise 1.
4227	* @param pNode The handler node.
4228	* @param pvUser pVM.
4229	*/
4230	static DECLCALLBACK(int) pgmR3CheckIntegrityVirtHandlerNode(PAVLROGCPTRNODECORE pNode, void *pvUser)
4231	{
4232	PPGMCHECKINTARGS pArgs = (PPGMCHECKINTARGS)pvUser;
4233	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)pNode;
4234	AssertReleaseReturn(!((uintptr_t)pCur & 7), 1);
4235	AssertReleaseMsg(pCur->Core.Key <= pCur->Core.KeyLast,("pCur=%p %VGv-%VGv %s\n", pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
4236	AssertReleaseMsg( !pArgs->pPrevVirt
4237	\|\| (pArgs->fLeftToRight ? pArgs->pPrevVirt->Core.KeyLast < pCur->Core.Key : pArgs->pPrevVirt->Core.KeyLast > pCur->Core.Key),
4238	("pPrevVirt=%p %VGv-%VGv %s\n"
4239	" pCur=%p %VGv-%VGv %s\n",
4240	pArgs->pPrevVirt, pArgs->pPrevVirt->Core.Key, pArgs->pPrevVirt->Core.KeyLast, pArgs->pPrevVirt->pszDesc,
4241	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
4242	for (unsigned iPage = 0; iPage < pCur->cPages; iPage++)
4243	{
4244	AssertReleaseMsg(pCur->aPhysToVirt[iPage].offVirtHandler == -RT_OFFSETOF(PGMVIRTHANDLER, aPhysToVirt[iPage]),
4245	("pCur=%p %VGv-%VGv %s\n"
4246	"iPage=%d offVirtHandle=%#x expected %#x\n",
4247	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc,
4248	iPage, pCur->aPhysToVirt[iPage].offVirtHandler, -RT_OFFSETOF(PGMVIRTHANDLER, aPhysToVirt[iPage])));
4249	}
4250	pArgs->pPrevVirt = pCur;
4251	return 0;
4252	}
4253
4254
4255	/**
4256	* Validate a node in the virtual handler tree.
4257	*
4258	* @returns 0 on if ok, other wise 1.
4259	* @param pNode The handler node.
4260	* @param pvUser pVM.
4261	*/
4262	static DECLCALLBACK(int) pgmR3CheckIntegrityPhysToVirtHandlerNode(PAVLROGCPHYSNODECORE pNode, void *pvUser)
4263	{
4264	PPGMCHECKINTARGS pArgs = (PPGMCHECKINTARGS)pvUser;
4265	PPGMPHYS2VIRTHANDLER pCur = (PPGMPHYS2VIRTHANDLER)pNode;
4266	AssertReleaseMsgReturn(!((uintptr_t)pCur & 3), ("\n"), 1);
4267	AssertReleaseMsgReturn(!(pCur->offVirtHandler & 3), ("\n"), 1);
4268	AssertReleaseMsg(pCur->Core.Key <= pCur->Core.KeyLast,("pCur=%p %VGp-%VGp\n", pCur, pCur->Core.Key, pCur->Core.KeyLast));
4269	AssertReleaseMsg( !pArgs->pPrevPhys2Virt
4270	\|\| (pArgs->fLeftToRight ? pArgs->pPrevPhys2Virt->Core.KeyLast < pCur->Core.Key : pArgs->pPrevPhys2Virt->Core.KeyLast > pCur->Core.Key),
4271	("pPrevPhys2Virt=%p %VGp-%VGp\n"
4272	" pCur=%p %VGp-%VGp\n",
4273	pArgs->pPrevPhys2Virt, pArgs->pPrevPhys2Virt->Core.Key, pArgs->pPrevPhys2Virt->Core.KeyLast,
4274	pCur, pCur->Core.Key, pCur->Core.KeyLast));
4275	AssertReleaseMsg( !pArgs->pPrevPhys2Virt
4276	\|\| (pArgs->fLeftToRight ? pArgs->pPrevPhys2Virt->Core.KeyLast < pCur->Core.Key : pArgs->pPrevPhys2Virt->Core.KeyLast > pCur->Core.Key),
4277	("pPrevPhys2Virt=%p %VGp-%VGp\n"
4278	" pCur=%p %VGp-%VGp\n",
4279	pArgs->pPrevPhys2Virt, pArgs->pPrevPhys2Virt->Core.Key, pArgs->pPrevPhys2Virt->Core.KeyLast,
4280	pCur, pCur->Core.Key, pCur->Core.KeyLast));
4281	AssertReleaseMsg((pCur->offNextAlias & (PGMPHYS2VIRTHANDLER_IN_TREE \| PGMPHYS2VIRTHANDLER_IS_HEAD)) == (PGMPHYS2VIRTHANDLER_IN_TREE \| PGMPHYS2VIRTHANDLER_IS_HEAD),
4282	("pCur=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4283	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias));
4284	if (pCur->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK)
4285	{
4286	PPGMPHYS2VIRTHANDLER pCur2 = pCur;
4287	for (;;)
4288	{
4289	pCur2 = (PPGMPHYS2VIRTHANDLER)((intptr_t)pCur + (pCur->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK));
4290	AssertReleaseMsg(pCur2 != pCur,
4291	(" pCur=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4292	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias));
4293	AssertReleaseMsg((pCur2->offNextAlias & (PGMPHYS2VIRTHANDLER_IN_TREE \| PGMPHYS2VIRTHANDLER_IS_HEAD)) == PGMPHYS2VIRTHANDLER_IN_TREE,
4294	(" pCur=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
4295	"pCur2=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4296	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias,
4297	pCur2, pCur2->Core.Key, pCur2->Core.KeyLast, pCur2->offVirtHandler, pCur2->offNextAlias));
4298	AssertReleaseMsg((pCur2->Core.Key ^ pCur->Core.Key) < PAGE_SIZE,
4299	(" pCur=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
4300	"pCur2=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4301	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias,
4302	pCur2, pCur2->Core.Key, pCur2->Core.KeyLast, pCur2->offVirtHandler, pCur2->offNextAlias));
4303	AssertReleaseMsg((pCur2->Core.KeyLast ^ pCur->Core.KeyLast) < PAGE_SIZE,
4304	(" pCur=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
4305	"pCur2=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4306	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias,
4307	pCur2, pCur2->Core.Key, pCur2->Core.KeyLast, pCur2->offVirtHandler, pCur2->offNextAlias));
4308	if (!(pCur2->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK))
4309	break;
4310	}
4311	}
4312
4313	pArgs->pPrevPhys2Virt = pCur;
4314	return 0;
4315	}
4316
4317
4318	/**
4319	* Perform an integrity check on the PGM component.
4320	*
4321	* @returns VINF_SUCCESS if everything is fine.
4322	* @returns VBox error status after asserting on integrity breach.
4323	* @param pVM The VM handle.
4324	*/
4325	VMMR3DECL(int) PGMR3CheckIntegrity(PVM pVM)
4326	{
4327	AssertReleaseReturn(pVM->pgm.s.offVM, VERR_INTERNAL_ERROR);
4328
4329	/*
4330	* Check the trees.
4331	*/
4332	int cErrors = 0;
4333	const static PGMCHECKINTARGS s_LeftToRight = { true, NULL, NULL, NULL, pVM };
4334	const static PGMCHECKINTARGS s_RightToLeft = { false, NULL, NULL, NULL, pVM };
4335	PGMCHECKINTARGS Args = s_LeftToRight;
4336	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysHandlers, true, pgmR3CheckIntegrityPhysHandlerNode, &Args);
4337	Args = s_RightToLeft;
4338	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysHandlers, false, pgmR3CheckIntegrityPhysHandlerNode, &Args);
4339	Args = s_LeftToRight;
4340	cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesR3->VirtHandlers, true, pgmR3CheckIntegrityVirtHandlerNode, &Args);
4341	Args = s_RightToLeft;
4342	cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesR3->VirtHandlers, false, pgmR3CheckIntegrityVirtHandlerNode, &Args);
4343	Args = s_LeftToRight;
4344	cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesR3->HyperVirtHandlers, true, pgmR3CheckIntegrityVirtHandlerNode, &Args);
4345	Args = s_RightToLeft;
4346	cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesR3->HyperVirtHandlers, false, pgmR3CheckIntegrityVirtHandlerNode, &Args);
4347	Args = s_LeftToRight;
4348	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysToVirtHandlers, true, pgmR3CheckIntegrityPhysToVirtHandlerNode, &Args);
4349	Args = s_RightToLeft;
4350	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysToVirtHandlers, false, pgmR3CheckIntegrityPhysToVirtHandlerNode, &Args);
4351
4352	return !cErrors ? VINF_SUCCESS : VERR_INTERNAL_ERROR;
4353	}
4354
4355
4356	/**
4357	* Inform PGM if we want all mappings to be put into the shadow page table. (necessary for e.g. VMX)
4358	*
4359	* @returns VBox status code.
4360	* @param pVM VM handle.
4361	* @param fEnable Enable or disable shadow mappings
4362	*/
4363	VMMR3DECL(int) PGMR3ChangeShwPDMappings(PVM pVM, bool fEnable)
4364	{
4365	pVM->pgm.s.fDisableMappings = !fEnable;
4366
4367	uint32_t cb;
4368	int rc = PGMR3MappingsSize(pVM, &cb);
4369	AssertRCReturn(rc, rc);
4370
4371	/* Pretend the mappings are now fixed; to force a refresh of the reserved PDEs. */
4372	rc = PGMR3MappingsFix(pVM, MM_HYPER_AREA_ADDRESS, cb);
4373	AssertRCReturn(rc, rc);
4374
4375	return VINF_SUCCESS;
4376	}

Note: See TracBrowser for help on using the repository browser.

source: vbox/trunk/src/VBox/VMM/PGM.cpp@ 13085

Download in other formats: