PGM.cpp@ 13106

Last change on this file since 13106 was 13106, checked in by vboxsync, 16 years ago
leave some modes out if 64-bit guests are not enabled (so far on 32-bit hosts)
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1	/* $Id: PGM.cpp 13106 2008-10-09 08:46:19Z vboxsync $ */
2	/** @file
3	* PGM - Page Manager and Monitor. (Mixing stuff here, not good?)
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22
23	/** @page pg_pgm PGM - The Page Manager and Monitor
24	*
25	* @see grp_pgm,
26	* @ref pg_pgm_pool,
27	* @ref pg_pgm_phys.
28	*
29	*
30	* @section sec_pgm_modes Paging Modes
31	*
32	* There are three memory contexts: Host Context (HC), Guest Context (GC)
33	* and intermediate context. When talking about paging HC can also be refered to
34	* as "host paging", and GC refered to as "shadow paging".
35	*
36	* We define three basic paging modes: 32-bit, PAE and AMD64. The host paging mode
37	* is defined by the host operating system. The mode used in the shadow paging mode
38	* depends on the host paging mode and what the mode the guest is currently in. The
39	* following relation between the two is defined:
40	*
41	* @verbatim
42	Host > 32-bit \| PAE \| AMD64 \|
43	Guest \| \| \| \|
44	==v================================
45	32-bit 32-bit PAE PAE
46	-------\|--------\|--------\|--------\|
47	PAE PAE PAE PAE
48	-------\|--------\|--------\|--------\|
49	AMD64 AMD64 AMD64 AMD64
50	-------\|--------\|--------\|--------\| @endverbatim
51	*
52	* All configuration except those in the diagonal (upper left) are expected to
53	* require special effort from the switcher (i.e. a bit slower).
54	*
55	*
56	*
57	*
58	* @section sec_pgm_shw The Shadow Memory Context
59	*
60	*
61	* [..]
62	*
63	* Because of guest context mappings requires PDPT and PML4 entries to allow
64	* writing on AMD64, the two upper levels will have fixed flags whatever the
65	* guest is thinking of using there. So, when shadowing the PD level we will
66	* calculate the effective flags of PD and all the higher levels. In legacy
67	* PAE mode this only applies to the PWT and PCD bits (the rest are
68	* ignored/reserved/MBZ). We will ignore those bits for the present.
69	*
70	*
71	*
72	* @section sec_pgm_int The Intermediate Memory Context
73	*
74	* The world switch goes thru an intermediate memory context which purpose it is
75	* to provide different mappings of the switcher code. All guest mappings are also
76	* present in this context.
77	*
78	* The switcher code is mapped at the same location as on the host, at an
79	* identity mapped location (physical equals virtual address), and at the
80	* hypervisor location.
81	*
82	* PGM maintain page tables for 32-bit, PAE and AMD64 paging modes. This
83	* simplifies switching guest CPU mode and consistency at the cost of more
84	* code to do the work. All memory use for those page tables is located below
85	* 4GB (this includes page tables for guest context mappings).
86	*
87	*
88	* @subsection subsec_pgm_int_gc Guest Context Mappings
89	*
90	* During assignment and relocation of a guest context mapping the intermediate
91	* memory context is used to verify the new location.
92	*
93	* Guest context mappings are currently restricted to below 4GB, for reasons
94	* of simplicity. This may change when we implement AMD64 support.
95	*
96	*
97	*
98	*
99	* @section sec_pgm_misc Misc
100	*
101	* @subsection subsec_pgm_misc_diff Differences Between Legacy PAE and Long Mode PAE
102	*
103	* The differences between legacy PAE and long mode PAE are:
104	* -# PDPE bits 1, 2, 5 and 6 are defined differently. In leagcy mode they are
105	* all marked down as must-be-zero, while in long mode 1, 2 and 5 have the
106	* usual meanings while 6 is ignored (AMD). This means that upon switching to
107	* legacy PAE mode we'll have to clear these bits and when going to long mode
108	* they must be set. This applies to both intermediate and shadow contexts,
109	* however we don't need to do it for the intermediate one since we're
110	* executing with CR0.WP at that time.
111	* -# CR3 allows a 32-byte aligned address in legacy mode, while in long mode
112	* a page aligned one is required.
113	*
114	*
115	* @section sec_pgm_handlers Access Handlers
116	*
117	* Placeholder.
118	*
119	*
120	* @subsection sec_pgm_handlers_virt Virtual Access Handlers
121	*
122	* Placeholder.
123	*
124	*
125	* @subsection sec_pgm_handlers_virt Virtual Access Handlers
126	*
127	* We currently implement three types of virtual access handlers: ALL, WRITE
128	* and HYPERVISOR (WRITE). See PGMVIRTHANDLERTYPE for some more details.
129	*
130	* The HYPERVISOR access handlers is kept in a separate tree since it doesn't apply
131	* to physical pages (PGMTREES::HyperVirtHandlers) and only needs to be consulted in
132	* a special \#PF case. The ALL and WRITE are in the PGMTREES::VirtHandlers tree, the
133	* rest of this section is going to be about these handlers.
134	*
135	* We'll go thru the life cycle of a handler and try make sense of it all, don't know
136	* how successfull this is gonna be...
137	*
138	* 1. A handler is registered thru the PGMR3HandlerVirtualRegister and
139	* PGMHandlerVirtualRegisterEx APIs. We check for conflicting virtual handlers
140	* and create a new node that is inserted into the AVL tree (range key). Then
141	* a full PGM resync is flagged (clear pool, sync cr3, update virtual bit of PGMPAGE).
142	*
143	* 2. The following PGMSyncCR3/SyncCR3 operation will first make invoke HandlerVirtualUpdate.
144	*
145	* 2a. HandlerVirtualUpdate will will lookup all the pages covered by virtual handlers
146	* via the current guest CR3 and update the physical page -> virtual handler
147	* translation. Needless to say, this doesn't exactly scale very well. If any changes
148	* are detected, it will flag a virtual bit update just like we did on registration.
149	* PGMPHYS pages with changes will have their virtual handler state reset to NONE.
150	*
151	* 2b. The virtual bit update process will iterate all the pages covered by all the
152	* virtual handlers and update the PGMPAGE virtual handler state to the max of all
153	* virtual handlers on that page.
154	*
155	* 2c. Back in SyncCR3 we will now flush the entire shadow page cache to make sure
156	* we don't miss any alias mappings of the monitored pages.
157	*
158	* 2d. SyncCR3 will then proceed with syncing the CR3 table.
159	*
160	* 3. \#PF(np,read) on a page in the range. This will cause it to be synced
161	* read-only and resumed if it's a WRITE handler. If it's an ALL handler we
162	* will call the handlers like in the next step. If the physical mapping has
163	* changed we will - some time in the future - perform a handler callback
164	* (optional) and update the physical -> virtual handler cache.
165	*
166	* 4. \#PF(,write) on a page in the range. This will cause the handler to
167	* be invoked.
168	*
169	* 5. The guest invalidates the page and changes the physical backing or
170	* unmaps it. This should cause the invalidation callback to be invoked
171	* (it might not yet be 100% perfect). Exactly what happens next... is
172	* this where we mess up and end up out of sync for a while?
173	*
174	* 6. The handler is deregistered by the client via PGMHandlerVirtualDeregister.
175	* We will then set all PGMPAGEs in the physical -> virtual handler cache for
176	* this handler to NONE and trigger a full PGM resync (basically the same
177	* as int step 1). Which means 2 is executed again.
178	*
179	*
180	* @subsubsection sub_sec_pgm_handler_virt_todo TODOs
181	*
182	* There is a bunch of things that needs to be done to make the virtual handlers
183	* work 100% correctly and work more efficiently.
184	*
185	* The first bit hasn't been implemented yet because it's going to slow the
186	* whole mess down even more, and besides it seems to be working reliably for
187	* our current uses. OTOH, some of the optimizations might end up more or less
188	* implementing the missing bits, so we'll see.
189	*
190	* On the optimization side, the first thing to do is to try avoid unnecessary
191	* cache flushing. Then try team up with the shadowing code to track changes
192	* in mappings by means of access to them (shadow in), updates to shadows pages,
193	* invlpg, and shadow PT discarding (perhaps).
194	*
195	* Some idea that have popped up for optimization for current and new features:
196	* - bitmap indicating where there are virtual handlers installed.
197	* (4KB => 220 pages, page 212 => covers 32-bit address space 1:1!)
198	* - Further optimize this by min/max (needs min/max avl getters).
199	* - Shadow page table entry bit (if any left)?
200	*
201	*/
202
203
204	/** @page pg_pgm_phys PGM Physical Guest Memory Management
205	*
206	*
207	* Objectives:
208	* - Guest RAM over-commitment using memory ballooning,
209	* zero pages and general page sharing.
210	* - Moving or mirroring a VM onto a different physical machine.
211	*
212	*
213	* @subsection subsec_pgmPhys_Definitions Definitions
214	*
215	* Allocation chunk - A RTR0MemObjAllocPhysNC object and the tracking
216	* machinery assoicated with it.
217	*
218	*
219	*
220	*
221	* @subsection subsec_pgmPhys_AllocPage Allocating a page.
222	*
223	* Initially we map all guest memory to the (per VM) zero page, which
224	* means that none of the read functions will cause pages to be allocated.
225	*
226	* Exception, access bit in page tables that have been shared. This must
227	* be handled, but we must also make sure PGMGst*Modify doesn't make
228	* unnecessary modifications.
229	*
230	* Allocation points:
231	* - PGMPhysWriteGCPhys and PGMPhysWrite.
232	* - Replacing a zero page mapping at \#PF.
233	* - Replacing a shared page mapping at \#PF.
234	* - ROM registration (currently MMR3RomRegister).
235	* - VM restore (pgmR3Load).
236	*
237	* For the first three it would make sense to keep a few pages handy
238	* until we've reached the max memory commitment for the VM.
239	*
240	* For the ROM registration, we know exactly how many pages we need
241	* and will request these from ring-0. For restore, we will save
242	* the number of non-zero pages in the saved state and allocate
243	* them up front. This would allow the ring-0 component to refuse
244	* the request if the isn't sufficient memory available for VM use.
245	*
246	* Btw. for both ROM and restore allocations we won't be requiring
247	* zeroed pages as they are going to be filled instantly.
248	*
249	*
250	* @subsection subsec_pgmPhys_FreePage Freeing a page
251	*
252	* There are a few points where a page can be freed:
253	* - After being replaced by the zero page.
254	* - After being replaced by a shared page.
255	* - After being ballooned by the guest additions.
256	* - At reset.
257	* - At restore.
258	*
259	* When freeing one or more pages they will be returned to the ring-0
260	* component and replaced by the zero page.
261	*
262	* The reasoning for clearing out all the pages on reset is that it will
263	* return us to the exact same state as on power on, and may thereby help
264	* us reduce the memory load on the system. Further it might have a
265	* (temporary) positive influence on memory fragmentation (@see subsec_pgmPhys_Fragmentation).
266	*
267	* On restore, as mention under the allocation topic, pages should be
268	* freed / allocated depending on how many is actually required by the
269	* new VM state. The simplest approach is to do like on reset, and free
270	* all non-ROM pages and then allocate what we need.
271	*
272	* A measure to prevent some fragmentation, would be to let each allocation
273	* chunk have some affinity towards the VM having allocated the most pages
274	* from it. Also, try make sure to allocate from allocation chunks that
275	* are almost full. Admittedly, both these measures might work counter to
276	* our intentions and its probably not worth putting a lot of effort,
277	* cpu time or memory into this.
278	*
279	*
280	* @subsection subsec_pgmPhys_SharePage Sharing a page
281	*
282	* The basic idea is that there there will be a idle priority kernel
283	* thread walking the non-shared VM pages hashing them and looking for
284	* pages with the same checksum. If such pages are found, it will compare
285	* them byte-by-byte to see if they actually are identical. If found to be
286	* identical it will allocate a shared page, copy the content, check that
287	* the page didn't change while doing this, and finally request both the
288	* VMs to use the shared page instead. If the page is all zeros (special
289	* checksum and byte-by-byte check) it will request the VM that owns it
290	* to replace it with the zero page.
291	*
292	* To make this efficient, we will have to make sure not to try share a page
293	* that will change its contents soon. This part requires the most work.
294	* A simple idea would be to request the VM to write monitor the page for
295	* a while to make sure it isn't modified any time soon. Also, it may
296	* make sense to skip pages that are being write monitored since this
297	* information is readily available to the thread if it works on the
298	* per-VM guest memory structures (presently called PGMRAMRANGE).
299	*
300	*
301	* @subsection subsec_pgmPhys_Fragmentation Fragmentation Concerns and Counter Measures
302	*
303	* The pages are organized in allocation chunks in ring-0, this is a necessity
304	* if we wish to have an OS agnostic approach to this whole thing. (On Linux we
305	* could easily work on a page-by-page basis if we liked. Whether this is possible
306	* or efficient on NT I don't quite know.) Fragmentation within these chunks may
307	* become a problem as part of the idea here is that we wish to return memory to
308	* the host system.
309	*
310	* For instance, starting two VMs at the same time, they will both allocate the
311	* guest memory on-demand and if permitted their page allocations will be
312	* intermixed. Shut down one of the two VMs and it will be difficult to return
313	* any memory to the host system because the page allocation for the two VMs are
314	* mixed up in the same allocation chunks.
315	*
316	* To further complicate matters, when pages are freed because they have been
317	* ballooned or become shared/zero the whole idea is that the page is supposed
318	* to be reused by another VM or returned to the host system. This will cause
319	* allocation chunks to contain pages belonging to different VMs and prevent
320	* returning memory to the host when one of those VM shuts down.
321	*
322	* The only way to really deal with this problem is to move pages. This can
323	* either be done at VM shutdown and or by the idle priority worker thread
324	* that will be responsible for finding sharable/zero pages. The mechanisms
325	* involved for coercing a VM to move a page (or to do it for it) will be
326	* the same as when telling it to share/zero a page.
327	*
328	*
329	* @subsection subsec_pgmPhys_Tracking Tracking Structures And Their Cost
330	*
331	* There's a difficult balance between keeping the per-page tracking structures
332	* (global and guest page) easy to use and keeping them from eating too much
333	* memory. We have limited virtual memory resources available when operating in
334	* 32-bit kernel space (on 64-bit there'll it's quite a different story). The
335	* tracking structures will be attemted designed such that we can deal with up
336	* to 32GB of memory on a 32-bit system and essentially unlimited on 64-bit ones.
337	*
338	*
339	* @subsubsection subsubsec_pgmPhys_Tracking_Kernel Kernel Space
340	*
341	* @see pg_GMM
342	*
343	* @subsubsection subsubsec_pgmPhys_Tracking_PerVM Per-VM
344	*
345	* Fixed info is the physical address of the page (HCPhys) and the page id
346	* (described above). Theoretically we'll need 48(-12) bits for the HCPhys part.
347	* Today we've restricting ourselves to 40(-12) bits because this is the current
348	* restrictions of all AMD64 implementations (I think Barcelona will up this
349	* to 48(-12) bits, not that it really matters) and I needed the bits for
350	* tracking mappings of a page. 48-12 = 36. That leaves 28 bits, which means a
351	* decent range for the page id: 2^(28+12) = 1024TB.
352	*
353	* In additions to these, we'll have to keep maintaining the page flags as we
354	* currently do. Although it wouldn't harm to optimize these quite a bit, like
355	* for instance the ROM shouldn't depend on having a write handler installed
356	* in order for it to become read-only. A RO/RW bit should be considered so
357	* that the page syncing code doesn't have to mess about checking multiple
358	* flag combinations (ROM \|\| RW handler \|\| write monitored) in order to
359	* figure out how to setup a shadow PTE. But this of course, is second
360	* priority at present. Current this requires 12 bits, but could probably
361	* be optimized to ~8.
362	*
363	* Then there's the 24 bits used to track which shadow page tables are
364	* currently mapping a page for the purpose of speeding up physical
365	* access handlers, and thereby the page pool cache. More bit for this
366	* purpose wouldn't hurt IIRC.
367	*
368	* Then there is a new bit in which we need to record what kind of page
369	* this is, shared, zero, normal or write-monitored-normal. This'll
370	* require 2 bits. One bit might be needed for indicating whether a
371	* write monitored page has been written to. And yet another one or
372	* two for tracking migration status. 3-4 bits total then.
373	*
374	* Whatever is left will can be used to record the sharabilitiy of a
375	* page. The page checksum will not be stored in the per-VM table as
376	* the idle thread will not be permitted to do modifications to it.
377	* It will instead have to keep its own working set of potentially
378	* shareable pages and their check sums and stuff.
379	*
380	* For the present we'll keep the current packing of the
381	* PGMRAMRANGE::aHCPhys to keep the changes simple, only of course,
382	* we'll have to change it to a struct with a total of 128-bits at
383	* our disposal.
384	*
385	* The initial layout will be like this:
386	* @verbatim
387	RTHCPHYS HCPhys; The current stuff.
388	63:40 Current shadow PT tracking stuff.
389	39:12 The physical page frame number.
390	11:0 The current flags.
391	uint32_t u28PageId : 28; The page id.
392	uint32_t u2State : 2; The page state { zero, shared, normal, write monitored }.
393	uint32_t fWrittenTo : 1; Whether a write monitored page was written to.
394	uint32_t u1Reserved : 1; Reserved for later.
395	uint32_t u32Reserved; Reserved for later, mostly sharing stats.
396	@endverbatim
397	*
398	* The final layout will be something like this:
399	* @verbatim
400	RTHCPHYS HCPhys; The current stuff.
401	63:48 High page id (12+).
402	47:12 The physical page frame number.
403	11:0 Low page id.
404	uint32_t fReadOnly : 1; Whether it's readonly page (rom or monitored in some way).
405	uint32_t u3Type : 3; The page type {RESERVED, MMIO, MMIO2, ROM, shadowed ROM, RAM}.
406	uint32_t u2PhysMon : 2; Physical access handler type {none, read, write, all}.
407	uint32_t u2VirtMon : 2; Virtual access handler type {none, read, write, all}..
408	uint32_t u2State : 2; The page state { zero, shared, normal, write monitored }.
409	uint32_t fWrittenTo : 1; Whether a write monitored page was written to.
410	uint32_t u20Reserved : 20; Reserved for later, mostly sharing stats.
411	uint32_t u32Tracking; The shadow PT tracking stuff, roughly.
412	@endverbatim
413	*
414	* Cost wise, this means we'll double the cost for guest memory. There isn't anyway
415	* around that I'm afraid. It means that the cost of dealing out 32GB of memory
416	* to one or more VMs is: (32GB >> PAGE_SHIFT) * 16 bytes, or 128MBs. Or another
417	* example, the VM heap cost when assigning 1GB to a VM will be: 4MB.
418	*
419	* A couple of cost examples for the total cost per-VM + kernel.
420	* 32-bit Windows and 32-bit linux:
421	* 1GB guest ram, 256K pages: 4MB + 2MB(+) = 6MB
422	* 4GB guest ram, 1M pages: 16MB + 8MB(+) = 24MB
423	* 32GB guest ram, 8M pages: 128MB + 64MB(+) = 192MB
424	* 64-bit Windows and 64-bit linux:
425	* 1GB guest ram, 256K pages: 4MB + 3MB(+) = 7MB
426	* 4GB guest ram, 1M pages: 16MB + 12MB(+) = 28MB
427	* 32GB guest ram, 8M pages: 128MB + 96MB(+) = 224MB
428	*
429	* UPDATE - 2007-09-27:
430	* Will need a ballooned flag/state too because we cannot
431	* trust the guest 100% and reporting the same page as ballooned more
432	* than once will put the GMM off balance.
433	*
434	*
435	* @subsection subsec_pgmPhys_Serializing Serializing Access
436	*
437	* Initially, we'll try a simple scheme:
438	*
439	* - The per-VM RAM tracking structures (PGMRAMRANGE) is only modified
440	* by the EMT thread of that VM while in the pgm critsect.
441	* - Other threads in the VM process that needs to make reliable use of
442	* the per-VM RAM tracking structures will enter the critsect.
443	* - No process external thread or kernel thread will ever try enter
444	* the pgm critical section, as that just won't work.
445	* - The idle thread (and similar threads) doesn't not need 100% reliable
446	* data when performing it tasks as the EMT thread will be the one to
447	* do the actual changes later anyway. So, as long as it only accesses
448	* the main ram range, it can do so by somehow preventing the VM from
449	* being destroyed while it works on it...
450	*
451	* - The over-commitment management, including the allocating/freeing
452	* chunks, is serialized by a ring-0 mutex lock (a fast one since the
453	* more mundane mutex implementation is broken on Linux).
454	* - A separeate mutex is protecting the set of allocation chunks so
455	* that pages can be shared or/and freed up while some other VM is
456	* allocating more chunks. This mutex can be take from under the other
457	* one, but not the otherway around.
458	*
459	*
460	* @subsection subsec_pgmPhys_Request VM Request interface
461	*
462	* When in ring-0 it will become necessary to send requests to a VM so it can
463	* for instance move a page while defragmenting during VM destroy. The idle
464	* thread will make use of this interface to request VMs to setup shared
465	* pages and to perform write monitoring of pages.
466	*
467	* I would propose an interface similar to the current VMReq interface, similar
468	* in that it doesn't require locking and that the one sending the request may
469	* wait for completion if it wishes to. This shouldn't be very difficult to
470	* realize.
471	*
472	* The requests themselves are also pretty simple. They are basically:
473	* -# Check that some precondition is still true.
474	* -# Do the update.
475	* -# Update all shadow page tables involved with the page.
476	*
477	* The 3rd step is identical to what we're already doing when updating a
478	* physical handler, see pgmHandlerPhysicalSetRamFlagsAndFlushShadowPTs.
479	*
480	*
481	*
482	* @section sec_pgmPhys_MappingCaches Mapping Caches
483	*
484	* In order to be able to map in and out memory and to be able to support
485	* guest with more RAM than we've got virtual address space, we'll employing
486	* a mapping cache. There is already a tiny one for GC (see PGMGCDynMapGCPageEx)
487	* and we'll create a similar one for ring-0 unless we decide to setup a dedicate
488	* memory context for the HWACCM execution.
489	*
490	*
491	* @subsection subsec_pgmPhys_MappingCaches_R3 Ring-3
492	*
493	* We've considered implementing the ring-3 mapping cache page based but found
494	* that this was bother some when one had to take into account TLBs+SMP and
495	* portability (missing the necessary APIs on several platforms). There were
496	* also some performance concerns with this approach which hadn't quite been
497	* worked out.
498	*
499	* Instead, we'll be mapping allocation chunks into the VM process. This simplifies
500	* matters greatly quite a bit since we don't need to invent any new ring-0 stuff,
501	* only some minor RTR0MEMOBJ mapping stuff. The main concern here is that mapping
502	* compared to the previous idea is that mapping or unmapping a 1MB chunk is more
503	* costly than a single page, although how much more costly is uncertain. We'll
504	* try address this by using a very big cache, preferably bigger than the actual
505	* VM RAM size if possible. The current VM RAM sizes should give some idea for
506	* 32-bit boxes, while on 64-bit we can probably get away with employing an
507	* unlimited cache.
508	*
509	* The cache have to parts, as already indicated, the ring-3 side and the
510	* ring-0 side.
511	*
512	* The ring-0 will be tied to the page allocator since it will operate on the
513	* memory objects it contains. It will therefore require the first ring-0 mutex
514	* discussed in @ref subsec_pgmPhys_Serializing. We
515	* some double house keeping wrt to who has mapped what I think, since both
516	* VMMR0.r0 and RTR0MemObj will keep track of mapping relataions
517	*
518	* The ring-3 part will be protected by the pgm critsect. For simplicity, we'll
519	* require anyone that desires to do changes to the mapping cache to do that
520	* from within this critsect. Alternatively, we could employ a separate critsect
521	* for serializing changes to the mapping cache as this would reduce potential
522	* contention with other threads accessing mappings unrelated to the changes
523	* that are in process. We can see about this later, contention will show
524	* up in the statistics anyway, so it'll be simple to tell.
525	*
526	* The organization of the ring-3 part will be very much like how the allocation
527	* chunks are organized in ring-0, that is in an AVL tree by chunk id. To avoid
528	* having to walk the tree all the time, we'll have a couple of lookaside entries
529	* like in we do for I/O ports and MMIO in IOM.
530	*
531	* The simplified flow of a PGMPhysRead/Write function:
532	* -# Enter the PGM critsect.
533	* -# Lookup GCPhys in the ram ranges and get the Page ID.
534	* -# Calc the Allocation Chunk ID from the Page ID.
535	* -# Check the lookaside entries and then the AVL tree for the Chunk ID.
536	* If not found in cache:
537	* -# Call ring-0 and request it to be mapped and supply
538	* a chunk to be unmapped if the cache is maxed out already.
539	* -# Insert the new mapping into the AVL tree (id + R3 address).
540	* -# Update the relevant lookaside entry and return the mapping address.
541	* -# Do the read/write according to monitoring flags and everything.
542	* -# Leave the critsect.
543	*
544	*
545	* @section sec_pgmPhys_Fallback Fallback
546	*
547	* Current all the "second tier" hosts will not support the RTR0MemObjAllocPhysNC
548	* API and thus require a fallback.
549	*
550	* So, when RTR0MemObjAllocPhysNC returns VERR_NOT_SUPPORTED the page allocator
551	* will return to the ring-3 caller (and later ring-0) and asking it to seed
552	* the page allocator with some fresh pages (VERR_GMM_SEED_ME). Ring-3 will
553	* then perform an SUPPageAlloc(cbChunk >> PAGE_SHIFT) call and make a
554	* "SeededAllocPages" call to ring-0.
555	*
556	* The first time ring-0 sees the VERR_NOT_SUPPORTED failure it will disable
557	* all page sharing (zero page detection will continue). It will also force
558	* all allocations to come from the VM which seeded the page. Both these
559	* measures are taken to make sure that there will never be any need for
560	* mapping anything into ring-3 - everything will be mapped already.
561	*
562	* Whether we'll continue to use the current MM locked memory management
563	* for this I don't quite know (I'd prefer not to and just ditch that all
564	* togther), we'll see what's simplest to do.
565	*
566	*
567	*
568	* @section sec_pgmPhys_Changes Changes
569	*
570	* Breakdown of the changes involved?
571	*/
572
573
574	/** Saved state data unit version. */
575	#define PGM_SAVED_STATE_VERSION 6
576
577	/*******************************************************************************
578	* Header Files *
579	*******************************************************************************/
580	#define LOG_GROUP LOG_GROUP_PGM
581	#include <VBox/dbgf.h>
582	#include <VBox/pgm.h>
583	#include <VBox/cpum.h>
584	#include <VBox/iom.h>
585	#include <VBox/sup.h>
586	#include <VBox/mm.h>
587	#include <VBox/em.h>
588	#include <VBox/stam.h>
589	#include <VBox/rem.h>
590	#include <VBox/dbgf.h>
591	#include <VBox/rem.h>
592	#include <VBox/selm.h>
593	#include <VBox/ssm.h>
594	#include "PGMInternal.h"
595	#include <VBox/vm.h>
596	#include <VBox/dbg.h>
597	#include <VBox/hwaccm.h>
598
599	#include <iprt/assert.h>
600	#include <iprt/alloc.h>
601	#include <iprt/asm.h>
602	#include <iprt/thread.h>
603	#include <iprt/string.h>
604	#include <VBox/param.h>
605	#include <VBox/err.h>
606
607
608
609	/*******************************************************************************
610	* Internal Functions *
611	*******************************************************************************/
612	static int pgmR3InitPaging(PVM pVM);
613	static DECLCALLBACK(void) pgmR3PhysInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
614	static DECLCALLBACK(void) pgmR3InfoMode(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
615	static DECLCALLBACK(void) pgmR3InfoCr3(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
616	static DECLCALLBACK(int) pgmR3RelocatePhysHandler(PAVLROGCPHYSNODECORE pNode, void *pvUser);
617	static DECLCALLBACK(int) pgmR3RelocateVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser);
618	static DECLCALLBACK(int) pgmR3RelocateHyperVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser);
619	#ifdef VBOX_STRICT
620	static DECLCALLBACK(void) pgmR3ResetNoMorePhysWritesFlag(PVM pVM, VMSTATE enmState, VMSTATE enmOldState, void *pvUser);
621	#endif
622	static DECLCALLBACK(int) pgmR3Save(PVM pVM, PSSMHANDLE pSSM);
623	static DECLCALLBACK(int) pgmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version);
624	static int pgmR3ModeDataInit(PVM pVM, bool fResolveGCAndR0);
625	static void pgmR3ModeDataSwitch(PVM pVM, PGMMODE enmShw, PGMMODE enmGst);
626	static PGMMODE pgmR3CalcShadowMode(PVM pVM, PGMMODE enmGuestMode, SUPPAGINGMODE enmHostMode, PGMMODE enmShadowMode, VMMSWITCHER *penmSwitcher);
627
628	#ifdef VBOX_WITH_STATISTICS
629	static void pgmR3InitStats(PVM pVM);
630	#endif
631
632	#ifdef VBOX_WITH_DEBUGGER
633	/** @todo all but the two last commands must be converted to 'info'. */
634	static DECLCALLBACK(int) pgmR3CmdRam(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
635	static DECLCALLBACK(int) pgmR3CmdMap(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
636	static DECLCALLBACK(int) pgmR3CmdSync(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
637	static DECLCALLBACK(int) pgmR3CmdSyncAlways(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
638	# ifdef VBOX_STRICT
639	static DECLCALLBACK(int) pgmR3CmdAssertCR3(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
640	# endif
641	#endif
642
643
644	/*******************************************************************************
645	* Global Variables *
646	*******************************************************************************/
647	#ifdef VBOX_WITH_DEBUGGER
648	/** Command descriptors. */
649	static const DBGCCMD g_aCmds[] =
650	{
651	/* pszCmd, cArgsMin, cArgsMax, paArgDesc, cArgDescs, pResultDesc, fFlags, pfnHandler pszSyntax, ....pszDescription */
652	{ "pgmram", 0, 0, NULL, 0, NULL, 0, pgmR3CmdRam, "", "Display the ram ranges." },
653	{ "pgmmap", 0, 0, NULL, 0, NULL, 0, pgmR3CmdMap, "", "Display the mapping ranges." },
654	{ "pgmsync", 0, 0, NULL, 0, NULL, 0, pgmR3CmdSync, "", "Sync the CR3 page." },
655	#ifdef VBOX_STRICT
656	{ "pgmassertcr3", 0, 0, NULL, 0, NULL, 0, pgmR3CmdAssertCR3, "", "Check the shadow CR3 mapping." },
657	#endif
658	{ "pgmsyncalways", 0, 0, NULL, 0, NULL, 0, pgmR3CmdSyncAlways, "", "Toggle permanent CR3 syncing." },
659	};
660	#endif
661
662
663
664
665	/*
666	* Shadow - 32-bit mode
667	*/
668	#define PGM_SHW_TYPE PGM_TYPE_32BIT
669	#define PGM_SHW_NAME(name) PGM_SHW_NAME_32BIT(name)
670	#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_32BIT_STR(name)
671	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_32BIT_STR(name)
672	#include "PGMShw.h"
673
674	/* Guest - real mode */
675	#define PGM_GST_TYPE PGM_TYPE_REAL
676	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
677	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_REAL_STR(name)
678	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
679	#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_REAL(name)
680	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_32BIT_REAL_STR(name)
681	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_32BIT_REAL_STR(name)
682	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_PHYS
683	#include "PGMGst.h"
684	#include "PGMBth.h"
685	#undef BTH_PGMPOOLKIND_PT_FOR_PT
686	#undef PGM_BTH_NAME
687	#undef PGM_BTH_NAME_RC_STR
688	#undef PGM_BTH_NAME_R0_STR
689	#undef PGM_GST_TYPE
690	#undef PGM_GST_NAME
691	#undef PGM_GST_NAME_RC_STR
692	#undef PGM_GST_NAME_R0_STR
693
694	/* Guest - protected mode */
695	#define PGM_GST_TYPE PGM_TYPE_PROT
696	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
697	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PROT_STR(name)
698	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
699	#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_PROT(name)
700	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_32BIT_PROT_STR(name)
701	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_32BIT_PROT_STR(name)
702	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_PHYS
703	#include "PGMGst.h"
704	#include "PGMBth.h"
705	#undef BTH_PGMPOOLKIND_PT_FOR_PT
706	#undef PGM_BTH_NAME
707	#undef PGM_BTH_NAME_RC_STR
708	#undef PGM_BTH_NAME_R0_STR
709	#undef PGM_GST_TYPE
710	#undef PGM_GST_NAME
711	#undef PGM_GST_NAME_RC_STR
712	#undef PGM_GST_NAME_R0_STR
713
714	/* Guest - 32-bit mode */
715	#define PGM_GST_TYPE PGM_TYPE_32BIT
716	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
717	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_32BIT_STR(name)
718	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
719	#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_32BIT(name)
720	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_32BIT_32BIT_STR(name)
721	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_32BIT_32BIT_STR(name)
722	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT
723	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB
724	#include "PGMGst.h"
725	#include "PGMBth.h"
726	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
727	#undef BTH_PGMPOOLKIND_PT_FOR_PT
728	#undef PGM_BTH_NAME
729	#undef PGM_BTH_NAME_RC_STR
730	#undef PGM_BTH_NAME_R0_STR
731	#undef PGM_GST_TYPE
732	#undef PGM_GST_NAME
733	#undef PGM_GST_NAME_RC_STR
734	#undef PGM_GST_NAME_R0_STR
735
736	#undef PGM_SHW_TYPE
737	#undef PGM_SHW_NAME
738	#undef PGM_SHW_NAME_RC_STR
739	#undef PGM_SHW_NAME_R0_STR
740
741
742	/*
743	* Shadow - PAE mode
744	*/
745	#define PGM_SHW_TYPE PGM_TYPE_PAE
746	#define PGM_SHW_NAME(name) PGM_SHW_NAME_PAE(name)
747	#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_PAE_STR(name)
748	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_PAE_STR(name)
749	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_REAL(name)
750	#include "PGMShw.h"
751
752	/* Guest - real mode */
753	#define PGM_GST_TYPE PGM_TYPE_REAL
754	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
755	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_REAL_STR(name)
756	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
757	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_REAL(name)
758	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_PAE_REAL_STR(name)
759	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_REAL_STR(name)
760	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
761	#include "PGMBth.h"
762	#undef BTH_PGMPOOLKIND_PT_FOR_PT
763	#undef PGM_BTH_NAME
764	#undef PGM_BTH_NAME_RC_STR
765	#undef PGM_BTH_NAME_R0_STR
766	#undef PGM_GST_TYPE
767	#undef PGM_GST_NAME
768	#undef PGM_GST_NAME_RC_STR
769	#undef PGM_GST_NAME_R0_STR
770
771	/* Guest - protected mode */
772	#define PGM_GST_TYPE PGM_TYPE_PROT
773	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
774	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PROT_STR(name)
775	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
776	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_PROT(name)
777	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_PAE_PROT_STR(name)
778	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_PROT_STR(name)
779	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
780	#include "PGMBth.h"
781	#undef BTH_PGMPOOLKIND_PT_FOR_PT
782	#undef PGM_BTH_NAME
783	#undef PGM_BTH_NAME_RC_STR
784	#undef PGM_BTH_NAME_R0_STR
785	#undef PGM_GST_TYPE
786	#undef PGM_GST_NAME
787	#undef PGM_GST_NAME_RC_STR
788	#undef PGM_GST_NAME_R0_STR
789
790	/* Guest - 32-bit mode */
791	#define PGM_GST_TYPE PGM_TYPE_32BIT
792	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
793	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_32BIT_STR(name)
794	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
795	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_32BIT(name)
796	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_PAE_32BIT_STR(name)
797	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_32BIT_STR(name)
798	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_32BIT_PT
799	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB
800	#include "PGMBth.h"
801	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
802	#undef BTH_PGMPOOLKIND_PT_FOR_PT
803	#undef PGM_BTH_NAME
804	#undef PGM_BTH_NAME_RC_STR
805	#undef PGM_BTH_NAME_R0_STR
806	#undef PGM_GST_TYPE
807	#undef PGM_GST_NAME
808	#undef PGM_GST_NAME_RC_STR
809	#undef PGM_GST_NAME_R0_STR
810
811	/* Guest - PAE mode */
812	#define PGM_GST_TYPE PGM_TYPE_PAE
813	#define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
814	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PAE_STR(name)
815	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PAE_STR(name)
816	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_PAE(name)
817	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_PAE_PAE_STR(name)
818	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_PAE_STR(name)
819	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
820	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
821	#include "PGMGst.h"
822	#include "PGMBth.h"
823	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
824	#undef BTH_PGMPOOLKIND_PT_FOR_PT
825	#undef PGM_BTH_NAME
826	#undef PGM_BTH_NAME_RC_STR
827	#undef PGM_BTH_NAME_R0_STR
828	#undef PGM_GST_TYPE
829	#undef PGM_GST_NAME
830	#undef PGM_GST_NAME_RC_STR
831	#undef PGM_GST_NAME_R0_STR
832
833	#undef PGM_SHW_TYPE
834	#undef PGM_SHW_NAME
835	#undef PGM_SHW_NAME_RC_STR
836	#undef PGM_SHW_NAME_R0_STR
837
838
839	/*
840	* Shadow - AMD64 mode
841	*/
842	#define PGM_SHW_TYPE PGM_TYPE_AMD64
843	#define PGM_SHW_NAME(name) PGM_SHW_NAME_AMD64(name)
844	#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_AMD64_STR(name)
845	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_AMD64_STR(name)
846	#include "PGMShw.h"
847
848	#ifdef VBOX_WITH_64_BITS_GUESTS
849	/* Guest - AMD64 mode */
850	#define PGM_GST_TYPE PGM_TYPE_AMD64
851	#define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
852	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_AMD64_STR(name)
853	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_AMD64_STR(name)
854	#define PGM_BTH_NAME(name) PGM_BTH_NAME_AMD64_AMD64(name)
855	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_AMD64_AMD64_STR(name)
856	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_AMD64_AMD64_STR(name)
857	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
858	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
859	#include "PGMGst.h"
860	#include "PGMBth.h"
861	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
862	#undef BTH_PGMPOOLKIND_PT_FOR_PT
863	#undef PGM_BTH_NAME
864	#undef PGM_BTH_NAME_RC_STR
865	#undef PGM_BTH_NAME_R0_STR
866	#undef PGM_GST_TYPE
867	#undef PGM_GST_NAME
868	#undef PGM_GST_NAME_RC_STR
869	#undef PGM_GST_NAME_R0_STR
870	#endif
871
872	#undef PGM_SHW_TYPE
873	#undef PGM_SHW_NAME
874	#undef PGM_SHW_NAME_RC_STR
875	#undef PGM_SHW_NAME_R0_STR
876
877	/*
878	* Shadow - Nested paging mode
879	*/
880	#define PGM_SHW_TYPE PGM_TYPE_NESTED
881	#define PGM_SHW_NAME(name) PGM_SHW_NAME_NESTED(name)
882	#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_NESTED_STR(name)
883	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_NESTED_STR(name)
884	#include "PGMShw.h"
885
886	/* Guest - real mode */
887	#define PGM_GST_TYPE PGM_TYPE_REAL
888	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
889	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_REAL_STR(name)
890	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
891	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_REAL(name)
892	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_REAL_STR(name)
893	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_REAL_STR(name)
894	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
895	#include "PGMBth.h"
896	#undef BTH_PGMPOOLKIND_PT_FOR_PT
897	#undef PGM_BTH_NAME
898	#undef PGM_BTH_NAME_RC_STR
899	#undef PGM_BTH_NAME_R0_STR
900	#undef PGM_GST_TYPE
901	#undef PGM_GST_NAME
902	#undef PGM_GST_NAME_RC_STR
903	#undef PGM_GST_NAME_R0_STR
904
905	/* Guest - protected mode */
906	#define PGM_GST_TYPE PGM_TYPE_PROT
907	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
908	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PROT_STR(name)
909	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
910	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_PROT(name)
911	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_PROT_STR(name)
912	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_PROT_STR(name)
913	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
914	#include "PGMBth.h"
915	#undef BTH_PGMPOOLKIND_PT_FOR_PT
916	#undef PGM_BTH_NAME
917	#undef PGM_BTH_NAME_RC_STR
918	#undef PGM_BTH_NAME_R0_STR
919	#undef PGM_GST_TYPE
920	#undef PGM_GST_NAME
921	#undef PGM_GST_NAME_RC_STR
922	#undef PGM_GST_NAME_R0_STR
923
924	/* Guest - 32-bit mode */
925	#define PGM_GST_TYPE PGM_TYPE_32BIT
926	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
927	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_32BIT_STR(name)
928	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
929	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_32BIT(name)
930	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_32BIT_STR(name)
931	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_32BIT_STR(name)
932	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_32BIT_PT
933	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB
934	#include "PGMBth.h"
935	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
936	#undef BTH_PGMPOOLKIND_PT_FOR_PT
937	#undef PGM_BTH_NAME
938	#undef PGM_BTH_NAME_RC_STR
939	#undef PGM_BTH_NAME_R0_STR
940	#undef PGM_GST_TYPE
941	#undef PGM_GST_NAME
942	#undef PGM_GST_NAME_RC_STR
943	#undef PGM_GST_NAME_R0_STR
944
945	/* Guest - PAE mode */
946	#define PGM_GST_TYPE PGM_TYPE_PAE
947	#define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
948	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PAE_STR(name)
949	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PAE_STR(name)
950	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_PAE(name)
951	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_PAE_STR(name)
952	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_PAE_STR(name)
953	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
954	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
955	#include "PGMBth.h"
956	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
957	#undef BTH_PGMPOOLKIND_PT_FOR_PT
958	#undef PGM_BTH_NAME
959	#undef PGM_BTH_NAME_RC_STR
960	#undef PGM_BTH_NAME_R0_STR
961	#undef PGM_GST_TYPE
962	#undef PGM_GST_NAME
963	#undef PGM_GST_NAME_RC_STR
964	#undef PGM_GST_NAME_R0_STR
965
966	#ifdef VBOX_WITH_64_BITS_GUESTS
967	/* Guest - AMD64 mode */
968	#define PGM_GST_TYPE PGM_TYPE_AMD64
969	#define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
970	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_AMD64_STR(name)
971	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_AMD64_STR(name)
972	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_AMD64(name)
973	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_AMD64_STR(name)
974	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_AMD64_STR(name)
975	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
976	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
977	#include "PGMBth.h"
978	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
979	#undef BTH_PGMPOOLKIND_PT_FOR_PT
980	#undef PGM_BTH_NAME
981	#undef PGM_BTH_NAME_RC_STR
982	#undef PGM_BTH_NAME_R0_STR
983	#undef PGM_GST_TYPE
984	#undef PGM_GST_NAME
985	#undef PGM_GST_NAME_RC_STR
986	#undef PGM_GST_NAME_R0_STR
987	#endif
988
989	#undef PGM_SHW_TYPE
990	#undef PGM_SHW_NAME
991	#undef PGM_SHW_NAME_RC_STR
992	#undef PGM_SHW_NAME_R0_STR
993
994	/*
995	* Shadow - EPT
996	*/
997	#define PGM_SHW_TYPE PGM_TYPE_EPT
998	#define PGM_SHW_NAME(name) PGM_SHW_NAME_EPT(name)
999	#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_EPT_STR(name)
1000	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_EPT_STR(name)
1001	#include "PGMShw.h"
1002
1003	/* Guest - real mode */
1004	#define PGM_GST_TYPE PGM_TYPE_REAL
1005	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
1006	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_REAL_STR(name)
1007	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
1008	#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_REAL(name)
1009	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_REAL_STR(name)
1010	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_REAL_STR(name)
1011	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
1012	#include "PGMBth.h"
1013	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1014	#undef PGM_BTH_NAME
1015	#undef PGM_BTH_NAME_RC_STR
1016	#undef PGM_BTH_NAME_R0_STR
1017	#undef PGM_GST_TYPE
1018	#undef PGM_GST_NAME
1019	#undef PGM_GST_NAME_RC_STR
1020	#undef PGM_GST_NAME_R0_STR
1021
1022	/* Guest - protected mode */
1023	#define PGM_GST_TYPE PGM_TYPE_PROT
1024	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
1025	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PROT_STR(name)
1026	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
1027	#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_PROT(name)
1028	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_PROT_STR(name)
1029	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_PROT_STR(name)
1030	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
1031	#include "PGMBth.h"
1032	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1033	#undef PGM_BTH_NAME
1034	#undef PGM_BTH_NAME_RC_STR
1035	#undef PGM_BTH_NAME_R0_STR
1036	#undef PGM_GST_TYPE
1037	#undef PGM_GST_NAME
1038	#undef PGM_GST_NAME_RC_STR
1039	#undef PGM_GST_NAME_R0_STR
1040
1041	/* Guest - 32-bit mode */
1042	#define PGM_GST_TYPE PGM_TYPE_32BIT
1043	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
1044	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_32BIT_STR(name)
1045	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
1046	#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_32BIT(name)
1047	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_32BIT_STR(name)
1048	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_32BIT_STR(name)
1049	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_32BIT_PT
1050	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB
1051	#include "PGMBth.h"
1052	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
1053	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1054	#undef PGM_BTH_NAME
1055	#undef PGM_BTH_NAME_RC_STR
1056	#undef PGM_BTH_NAME_R0_STR
1057	#undef PGM_GST_TYPE
1058	#undef PGM_GST_NAME
1059	#undef PGM_GST_NAME_RC_STR
1060	#undef PGM_GST_NAME_R0_STR
1061
1062	/* Guest - PAE mode */
1063	#define PGM_GST_TYPE PGM_TYPE_PAE
1064	#define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
1065	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PAE_STR(name)
1066	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PAE_STR(name)
1067	#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_PAE(name)
1068	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_PAE_STR(name)
1069	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_PAE_STR(name)
1070	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
1071	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
1072	#include "PGMBth.h"
1073	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
1074	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1075	#undef PGM_BTH_NAME
1076	#undef PGM_BTH_NAME_RC_STR
1077	#undef PGM_BTH_NAME_R0_STR
1078	#undef PGM_GST_TYPE
1079	#undef PGM_GST_NAME
1080	#undef PGM_GST_NAME_RC_STR
1081	#undef PGM_GST_NAME_R0_STR
1082
1083	#ifdef VBOX_WITH_64_BITS_GUESTS
1084	/* Guest - AMD64 mode */
1085	#define PGM_GST_TYPE PGM_TYPE_AMD64
1086	#define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
1087	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_AMD64_STR(name)
1088	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_AMD64_STR(name)
1089	#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_AMD64(name)
1090	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_AMD64_STR(name)
1091	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_AMD64_STR(name)
1092	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
1093	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
1094	#include "PGMBth.h"
1095	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
1096	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1097	#undef PGM_BTH_NAME
1098	#undef PGM_BTH_NAME_RC_STR
1099	#undef PGM_BTH_NAME_R0_STR
1100	#undef PGM_GST_TYPE
1101	#undef PGM_GST_NAME
1102	#undef PGM_GST_NAME_RC_STR
1103	#undef PGM_GST_NAME_R0_STR
1104	#endif
1105
1106	#undef PGM_SHW_TYPE
1107	#undef PGM_SHW_NAME
1108	#undef PGM_SHW_NAME_RC_STR
1109	#undef PGM_SHW_NAME_R0_STR
1110
1111	/**
1112	* Initiates the paging of VM.
1113	*
1114	* @returns VBox status code.
1115	* @param pVM Pointer to VM structure.
1116	*/
1117	VMMR3DECL(int) PGMR3Init(PVM pVM)
1118	{
1119	LogFlow(("PGMR3Init:\n"));
1120
1121	/*
1122	* Assert alignment and sizes.
1123	*/
1124	AssertRelease(sizeof(pVM->pgm.s) <= sizeof(pVM->pgm.padding));
1125
1126	/*
1127	* Init the structure.
1128	*/
1129	pVM->pgm.s.offVM = RT_OFFSETOF(VM, pgm.s);
1130	pVM->pgm.s.enmShadowMode = PGMMODE_INVALID;
1131	pVM->pgm.s.enmGuestMode = PGMMODE_INVALID;
1132	pVM->pgm.s.enmHostMode = SUPPAGINGMODE_INVALID;
1133	pVM->pgm.s.GCPhysCR3 = NIL_RTGCPHYS;
1134	pVM->pgm.s.GCPhysGstCR3Monitored = NIL_RTGCPHYS;
1135	pVM->pgm.s.fA20Enabled = true;
1136	pVM->pgm.s.GCPhys4MBPSEMask = RT_BIT_64(32) - 1; /* default; checked later */
1137	pVM->pgm.s.pGstPaePDPTHC = NULL;
1138	pVM->pgm.s.pGstPaePDPTGC = 0;
1139	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.apGstPaePDsHC); i++)
1140	{
1141	pVM->pgm.s.apGstPaePDsHC[i] = NULL;
1142	pVM->pgm.s.apGstPaePDsGC[i] = 0;
1143	pVM->pgm.s.aGCPhysGstPaePDs[i] = NIL_RTGCPHYS;
1144	pVM->pgm.s.aGCPhysGstPaePDsMonitored[i] = NIL_RTGCPHYS;
1145	}
1146
1147	#ifdef VBOX_STRICT
1148	VMR3AtStateRegister(pVM, pgmR3ResetNoMorePhysWritesFlag, NULL);
1149	#endif
1150
1151	/*
1152	* Get the configured RAM size - to estimate saved state size.
1153	*/
1154	uint64_t cbRam;
1155	int rc = CFGMR3QueryU64(CFGMR3GetRoot(pVM), "RamSize", &cbRam);
1156	if (rc == VERR_CFGM_VALUE_NOT_FOUND)
1157	cbRam = pVM->pgm.s.cbRamSize = 0;
1158	else if (VBOX_SUCCESS(rc))
1159	{
1160	if (cbRam < PAGE_SIZE)
1161	cbRam = 0;
1162	cbRam = RT_ALIGN_64(cbRam, PAGE_SIZE);
1163	pVM->pgm.s.cbRamSize = (RTUINT)cbRam;
1164	}
1165	else
1166	{
1167	AssertMsgFailed(("Configuration error: Failed to query integer \"RamSize\", rc=%Vrc.\n", rc));
1168	return rc;
1169	}
1170
1171	/*
1172	* Register saved state data unit.
1173	*/
1174	rc = SSMR3RegisterInternal(pVM, "pgm", 1, PGM_SAVED_STATE_VERSION, (size_t)cbRam + sizeof(PGM),
1175	NULL, pgmR3Save, NULL,
1176	NULL, pgmR3Load, NULL);
1177	if (VBOX_FAILURE(rc))
1178	return rc;
1179
1180	/*
1181	* Initialize the PGM critical section and flush the phys TLBs
1182	*/
1183	rc = PDMR3CritSectInit(pVM, &pVM->pgm.s.CritSect, "PGM");
1184	AssertRCReturn(rc, rc);
1185
1186	PGMR3PhysChunkInvalidateTLB(pVM);
1187	PGMPhysInvalidatePageR3MapTLB(pVM);
1188	PGMPhysInvalidatePageR0MapTLB(pVM);
1189	PGMPhysInvalidatePageGCMapTLB(pVM);
1190
1191	/*
1192	* Trees
1193	*/
1194	rc = MMHyperAlloc(pVM, sizeof(PGMTREES), 0, MM_TAG_PGM, (void **)&pVM->pgm.s.pTreesR3);
1195	if (VBOX_SUCCESS(rc))
1196	{
1197	pVM->pgm.s.pTreesR0 = MMHyperR3ToR0(pVM, pVM->pgm.s.pTreesR3);
1198	pVM->pgm.s.pTreesRC = MMHyperR3ToRC(pVM, pVM->pgm.s.pTreesR3);
1199
1200	/*
1201	* Alocate the zero page.
1202	*/
1203	rc = MMHyperAlloc(pVM, PAGE_SIZE, PAGE_SIZE, MM_TAG_PGM, &pVM->pgm.s.pvZeroPgR3);
1204	}
1205	if (VBOX_SUCCESS(rc))
1206	{
1207	pVM->pgm.s.pvZeroPgGC = MMHyperR3ToRC(pVM, pVM->pgm.s.pvZeroPgR3);
1208	pVM->pgm.s.pvZeroPgR0 = MMHyperR3ToR0(pVM, pVM->pgm.s.pvZeroPgR3);
1209	AssertRelease(pVM->pgm.s.pvZeroPgR0 != NIL_RTHCPHYS);
1210	pVM->pgm.s.HCPhysZeroPg = MMR3HyperHCVirt2HCPhys(pVM, pVM->pgm.s.pvZeroPgR3);
1211	AssertRelease(pVM->pgm.s.HCPhysZeroPg != NIL_RTHCPHYS);
1212
1213	/*
1214	* Init the paging.
1215	*/
1216	rc = pgmR3InitPaging(pVM);
1217	}
1218	if (VBOX_SUCCESS(rc))
1219	{
1220	/*
1221	* Init the page pool.
1222	*/
1223	rc = pgmR3PoolInit(pVM);
1224	}
1225	if (VBOX_SUCCESS(rc))
1226	{
1227	/*
1228	* Info & statistics
1229	*/
1230	DBGFR3InfoRegisterInternal(pVM, "mode",
1231	"Shows the current paging mode. "
1232	"Recognizes 'all', 'guest', 'shadow' and 'host' as arguments, defaulting to 'all' if nothing's given.",
1233	pgmR3InfoMode);
1234	DBGFR3InfoRegisterInternal(pVM, "pgmcr3",
1235	"Dumps all the entries in the top level paging table. No arguments.",
1236	pgmR3InfoCr3);
1237	DBGFR3InfoRegisterInternal(pVM, "phys",
1238	"Dumps all the physical address ranges. No arguments.",
1239	pgmR3PhysInfo);
1240	DBGFR3InfoRegisterInternal(pVM, "handlers",
1241	"Dumps physical, virtual and hyper virtual handlers. "
1242	"Pass 'phys', 'virt', 'hyper' as argument if only one kind is wanted."
1243	"Add 'nost' if the statistics are unwanted, use together with 'all' or explicit selection.",
1244	pgmR3InfoHandlers);
1245	DBGFR3InfoRegisterInternal(pVM, "mappings",
1246	"Dumps guest mappings.",
1247	pgmR3MapInfo);
1248
1249	STAM_REL_REG(pVM, &pVM->pgm.s.cGuestModeChanges, STAMTYPE_COUNTER, "/PGM/cGuestModeChanges", STAMUNIT_OCCURENCES, "Number of guest mode changes.");
1250	#ifdef VBOX_WITH_STATISTICS
1251	pgmR3InitStats(pVM);
1252	#endif
1253	#ifdef VBOX_WITH_DEBUGGER
1254	/*
1255	* Debugger commands.
1256	*/
1257	static bool fRegisteredCmds = false;
1258	if (!fRegisteredCmds)
1259	{
1260	int rc = DBGCRegisterCommands(&g_aCmds[0], RT_ELEMENTS(g_aCmds));
1261	if (VBOX_SUCCESS(rc))
1262	fRegisteredCmds = true;
1263	}
1264	#endif
1265	return VINF_SUCCESS;
1266	}
1267
1268	/* Almost no cleanup necessary, MM frees all memory. */
1269	PDMR3CritSectDelete(&pVM->pgm.s.CritSect);
1270
1271	return rc;
1272	}
1273
1274
1275	/**
1276	* Init paging.
1277	*
1278	* Since we need to check what mode the host is operating in before we can choose
1279	* the right paging functions for the host we have to delay this until R0 has
1280	* been initialized.
1281	*
1282	* @returns VBox status code.
1283	* @param pVM VM handle.
1284	*/
1285	static int pgmR3InitPaging(PVM pVM)
1286	{
1287	/*
1288	* Force a recalculation of modes and switcher so everyone gets notified.
1289	*/
1290	pVM->pgm.s.enmShadowMode = PGMMODE_INVALID;
1291	pVM->pgm.s.enmGuestMode = PGMMODE_INVALID;
1292	pVM->pgm.s.enmHostMode = SUPPAGINGMODE_INVALID;
1293
1294	/*
1295	* Allocate static mapping space for whatever the cr3 register
1296	* points to and in the case of PAE mode to the 4 PDs.
1297	*/
1298	int rc = MMR3HyperReserve(pVM, PAGE_SIZE * 5, "CR3 mapping", &pVM->pgm.s.GCPtrCR3Mapping);
1299	if (VBOX_FAILURE(rc))
1300	{
1301	AssertMsgFailed(("Failed to reserve two pages for cr mapping in HMA, rc=%Vrc\n", rc));
1302	return rc;
1303	}
1304	MMR3HyperReserve(pVM, PAGE_SIZE, "fence", NULL);
1305
1306	/*
1307	* Allocate pages for the three possible intermediate contexts
1308	* (AMD64, PAE and plain 32-Bit). We maintain all three contexts
1309	* for the sake of simplicity. The AMD64 uses the PAE for the
1310	* lower levels, making the total number of pages 11 (3 + 7 + 1).
1311	*
1312	* We assume that two page tables will be enought for the core code
1313	* mappings (HC virtual and identity).
1314	*/
1315	pVM->pgm.s.pInterPD = (PX86PD)MMR3PageAllocLow(pVM);
1316	pVM->pgm.s.apInterPTs[0] = (PX86PT)MMR3PageAllocLow(pVM);
1317	pVM->pgm.s.apInterPTs[1] = (PX86PT)MMR3PageAllocLow(pVM);
1318	pVM->pgm.s.apInterPaePTs[0] = (PX86PTPAE)MMR3PageAlloc(pVM);
1319	pVM->pgm.s.apInterPaePTs[1] = (PX86PTPAE)MMR3PageAlloc(pVM);
1320	pVM->pgm.s.apInterPaePDs[0] = (PX86PDPAE)MMR3PageAlloc(pVM);
1321	pVM->pgm.s.apInterPaePDs[1] = (PX86PDPAE)MMR3PageAlloc(pVM);
1322	pVM->pgm.s.apInterPaePDs[2] = (PX86PDPAE)MMR3PageAlloc(pVM);
1323	pVM->pgm.s.apInterPaePDs[3] = (PX86PDPAE)MMR3PageAlloc(pVM);
1324	pVM->pgm.s.pInterPaePDPT = (PX86PDPT)MMR3PageAllocLow(pVM);
1325	pVM->pgm.s.pInterPaePDPT64 = (PX86PDPT)MMR3PageAllocLow(pVM);
1326	pVM->pgm.s.pInterPaePML4 = (PX86PML4)MMR3PageAllocLow(pVM);
1327	if ( !pVM->pgm.s.pInterPD
1328	\|\| !pVM->pgm.s.apInterPTs[0]
1329	\|\| !pVM->pgm.s.apInterPTs[1]
1330	\|\| !pVM->pgm.s.apInterPaePTs[0]
1331	\|\| !pVM->pgm.s.apInterPaePTs[1]
1332	\|\| !pVM->pgm.s.apInterPaePDs[0]
1333	\|\| !pVM->pgm.s.apInterPaePDs[1]
1334	\|\| !pVM->pgm.s.apInterPaePDs[2]
1335	\|\| !pVM->pgm.s.apInterPaePDs[3]
1336	\|\| !pVM->pgm.s.pInterPaePDPT
1337	\|\| !pVM->pgm.s.pInterPaePDPT64
1338	\|\| !pVM->pgm.s.pInterPaePML4)
1339	{
1340	AssertMsgFailed(("Failed to allocate pages for the intermediate context!\n"));
1341	return VERR_NO_PAGE_MEMORY;
1342	}
1343
1344	pVM->pgm.s.HCPhysInterPD = MMPage2Phys(pVM, pVM->pgm.s.pInterPD);
1345	AssertRelease(pVM->pgm.s.HCPhysInterPD != NIL_RTHCPHYS && !(pVM->pgm.s.HCPhysInterPD & PAGE_OFFSET_MASK));
1346	pVM->pgm.s.HCPhysInterPaePDPT = MMPage2Phys(pVM, pVM->pgm.s.pInterPaePDPT);
1347	AssertRelease(pVM->pgm.s.HCPhysInterPaePDPT != NIL_RTHCPHYS && !(pVM->pgm.s.HCPhysInterPaePDPT & PAGE_OFFSET_MASK));
1348	pVM->pgm.s.HCPhysInterPaePML4 = MMPage2Phys(pVM, pVM->pgm.s.pInterPaePML4);
1349	AssertRelease(pVM->pgm.s.HCPhysInterPaePML4 != NIL_RTHCPHYS && !(pVM->pgm.s.HCPhysInterPaePML4 & PAGE_OFFSET_MASK));
1350
1351	/*
1352	* Initialize the pages, setting up the PML4 and PDPT for repetitive 4GB action.
1353	*/
1354	ASMMemZeroPage(pVM->pgm.s.pInterPD);
1355	ASMMemZeroPage(pVM->pgm.s.apInterPTs[0]);
1356	ASMMemZeroPage(pVM->pgm.s.apInterPTs[1]);
1357
1358	ASMMemZeroPage(pVM->pgm.s.apInterPaePTs[0]);
1359	ASMMemZeroPage(pVM->pgm.s.apInterPaePTs[1]);
1360
1361	ASMMemZeroPage(pVM->pgm.s.pInterPaePDPT);
1362	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.apInterPaePDs); i++)
1363	{
1364	ASMMemZeroPage(pVM->pgm.s.apInterPaePDs[i]);
1365	pVM->pgm.s.pInterPaePDPT->a[i].u = X86_PDPE_P \| PGM_PLXFLAGS_PERMANENT
1366	\| MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[i]);
1367	}
1368
1369	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.pInterPaePDPT64->a); i++)
1370	{
1371	const unsigned iPD = i % RT_ELEMENTS(pVM->pgm.s.apInterPaePDs);
1372	pVM->pgm.s.pInterPaePDPT64->a[i].u = X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_A \| PGM_PLXFLAGS_PERMANENT
1373	\| MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[iPD]);
1374	}
1375
1376	RTHCPHYS HCPhysInterPaePDPT64 = MMPage2Phys(pVM, pVM->pgm.s.pInterPaePDPT64);
1377	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.pInterPaePML4->a); i++)
1378	pVM->pgm.s.pInterPaePML4->a[i].u = X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_A \| PGM_PLXFLAGS_PERMANENT
1379	\| HCPhysInterPaePDPT64;
1380
1381	/*
1382	* Allocate pages for the three possible guest contexts (AMD64, PAE and plain 32-Bit).
1383	* We allocate pages for all three posibilities to in order to simplify mappings and
1384	* avoid resource failure during mode switches. So, we need to cover all levels of the
1385	* of the first 4GB down to PD level.
1386	* As with the intermediate context, AMD64 uses the PAE PDPT and PDs.
1387	*/
1388	pVM->pgm.s.pHC32BitPD = (PX86PD)MMR3PageAllocLow(pVM);
1389	pVM->pgm.s.apHCPaePDs[0] = (PX86PDPAE)MMR3PageAlloc(pVM);
1390	pVM->pgm.s.apHCPaePDs[1] = (PX86PDPAE)MMR3PageAlloc(pVM);
1391	AssertRelease((uintptr_t)pVM->pgm.s.apHCPaePDs[0] + PAGE_SIZE == (uintptr_t)pVM->pgm.s.apHCPaePDs[1]);
1392	pVM->pgm.s.apHCPaePDs[2] = (PX86PDPAE)MMR3PageAlloc(pVM);
1393	AssertRelease((uintptr_t)pVM->pgm.s.apHCPaePDs[1] + PAGE_SIZE == (uintptr_t)pVM->pgm.s.apHCPaePDs[2]);
1394	pVM->pgm.s.apHCPaePDs[3] = (PX86PDPAE)MMR3PageAlloc(pVM);
1395	AssertRelease((uintptr_t)pVM->pgm.s.apHCPaePDs[2] + PAGE_SIZE == (uintptr_t)pVM->pgm.s.apHCPaePDs[3]);
1396	pVM->pgm.s.pHCPaePDPT = (PX86PDPT)MMR3PageAllocLow(pVM);
1397	pVM->pgm.s.pHCNestedRoot = MMR3PageAllocLow(pVM);
1398
1399	if ( !pVM->pgm.s.pHC32BitPD
1400	\|\| !pVM->pgm.s.apHCPaePDs[0]
1401	\|\| !pVM->pgm.s.apHCPaePDs[1]
1402	\|\| !pVM->pgm.s.apHCPaePDs[2]
1403	\|\| !pVM->pgm.s.apHCPaePDs[3]
1404	\|\| !pVM->pgm.s.pHCPaePDPT
1405	\|\| !pVM->pgm.s.pHCNestedRoot)
1406	{
1407	AssertMsgFailed(("Failed to allocate pages for the intermediate context!\n"));
1408	return VERR_NO_PAGE_MEMORY;
1409	}
1410
1411	/* get physical addresses. */
1412	pVM->pgm.s.HCPhys32BitPD = MMPage2Phys(pVM, pVM->pgm.s.pHC32BitPD);
1413	Assert(MMPagePhys2Page(pVM, pVM->pgm.s.HCPhys32BitPD) == pVM->pgm.s.pHC32BitPD);
1414	pVM->pgm.s.aHCPhysPaePDs[0] = MMPage2Phys(pVM, pVM->pgm.s.apHCPaePDs[0]);
1415	pVM->pgm.s.aHCPhysPaePDs[1] = MMPage2Phys(pVM, pVM->pgm.s.apHCPaePDs[1]);
1416	pVM->pgm.s.aHCPhysPaePDs[2] = MMPage2Phys(pVM, pVM->pgm.s.apHCPaePDs[2]);
1417	pVM->pgm.s.aHCPhysPaePDs[3] = MMPage2Phys(pVM, pVM->pgm.s.apHCPaePDs[3]);
1418	pVM->pgm.s.HCPhysPaePDPT = MMPage2Phys(pVM, pVM->pgm.s.pHCPaePDPT);
1419	pVM->pgm.s.HCPhysNestedRoot = MMPage2Phys(pVM, pVM->pgm.s.pHCNestedRoot);
1420
1421	/*
1422	* Initialize the pages, setting up the PML4 and PDPT for action below 4GB.
1423	*/
1424	ASMMemZero32(pVM->pgm.s.pHC32BitPD, PAGE_SIZE);
1425	ASMMemZero32(pVM->pgm.s.pHCPaePDPT, PAGE_SIZE);
1426	ASMMemZero32(pVM->pgm.s.pHCNestedRoot, PAGE_SIZE);
1427	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.apHCPaePDs); i++)
1428	{
1429	ASMMemZero32(pVM->pgm.s.apHCPaePDs[i], PAGE_SIZE);
1430	pVM->pgm.s.pHCPaePDPT->a[i].u = X86_PDPE_P \| PGM_PLXFLAGS_PERMANENT \| pVM->pgm.s.aHCPhysPaePDs[i];
1431	/* The flags will be corrected when entering and leaving long mode. */
1432	}
1433
1434	CPUMSetHyperCR3(pVM, (uint32_t)pVM->pgm.s.HCPhys32BitPD);
1435
1436	/*
1437	* Initialize paging workers and mode from current host mode
1438	* and the guest running in real mode.
1439	*/
1440	pVM->pgm.s.enmHostMode = SUPGetPagingMode();
1441	switch (pVM->pgm.s.enmHostMode)
1442	{
1443	case SUPPAGINGMODE_32_BIT:
1444	case SUPPAGINGMODE_32_BIT_GLOBAL:
1445	case SUPPAGINGMODE_PAE:
1446	case SUPPAGINGMODE_PAE_GLOBAL:
1447	case SUPPAGINGMODE_PAE_NX:
1448	case SUPPAGINGMODE_PAE_GLOBAL_NX:
1449	break;
1450
1451	case SUPPAGINGMODE_AMD64:
1452	case SUPPAGINGMODE_AMD64_GLOBAL:
1453	case SUPPAGINGMODE_AMD64_NX:
1454	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
1455	#ifndef VBOX_WITH_HYBIRD_32BIT_KERNEL
1456	if (ARCH_BITS != 64)
1457	{
1458	AssertMsgFailed(("Host mode %d (64-bit) is not supported by non-64bit builds\n", pVM->pgm.s.enmHostMode));
1459	LogRel(("Host mode %d (64-bit) is not supported by non-64bit builds\n", pVM->pgm.s.enmHostMode));
1460	return VERR_PGM_UNSUPPORTED_HOST_PAGING_MODE;
1461	}
1462	#endif
1463	break;
1464	default:
1465	AssertMsgFailed(("Host mode %d is not supported\n", pVM->pgm.s.enmHostMode));
1466	return VERR_PGM_UNSUPPORTED_HOST_PAGING_MODE;
1467	}
1468	rc = pgmR3ModeDataInit(pVM, false /* don't resolve GC and R0 syms yet */);
1469	if (VBOX_SUCCESS(rc))
1470	rc = PGMR3ChangeMode(pVM, PGMMODE_REAL);
1471	if (VBOX_SUCCESS(rc))
1472	{
1473	LogFlow(("pgmR3InitPaging: returns successfully\n"));
1474	#if HC_ARCH_BITS == 64
1475	LogRel(("Debug: HCPhys32BitPD=%VHp aHCPhysPaePDs={%VHp,%VHp,%VHp,%VHp} HCPhysPaePDPT=%VHp HCPhysPaePML4=%VHp\n",
1476	pVM->pgm.s.HCPhys32BitPD, pVM->pgm.s.aHCPhysPaePDs[0], pVM->pgm.s.aHCPhysPaePDs[1], pVM->pgm.s.aHCPhysPaePDs[2], pVM->pgm.s.aHCPhysPaePDs[3],
1477	pVM->pgm.s.HCPhysPaePDPT, pVM->pgm.s.HCPhysPaePML4));
1478	LogRel(("Debug: HCPhysInterPD=%VHp HCPhysInterPaePDPT=%VHp HCPhysInterPaePML4=%VHp\n",
1479	pVM->pgm.s.HCPhysInterPD, pVM->pgm.s.HCPhysInterPaePDPT, pVM->pgm.s.HCPhysInterPaePML4));
1480	LogRel(("Debug: apInterPTs={%VHp,%VHp} apInterPaePTs={%VHp,%VHp} apInterPaePDs={%VHp,%VHp,%VHp,%VHp} pInterPaePDPT64=%VHp\n",
1481	MMPage2Phys(pVM, pVM->pgm.s.apInterPTs[0]), MMPage2Phys(pVM, pVM->pgm.s.apInterPTs[1]),
1482	MMPage2Phys(pVM, pVM->pgm.s.apInterPaePTs[0]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePTs[1]),
1483	MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[0]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[1]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[2]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[3]),
1484	MMPage2Phys(pVM, pVM->pgm.s.pInterPaePDPT64)));
1485	#endif
1486
1487	return VINF_SUCCESS;
1488	}
1489
1490	LogFlow(("pgmR3InitPaging: returns %Vrc\n", rc));
1491	return rc;
1492	}
1493
1494
1495	#ifdef VBOX_WITH_STATISTICS
1496	/**
1497	* Init statistics
1498	*/
1499	static void pgmR3InitStats(PVM pVM)
1500	{
1501	PPGM pPGM = &pVM->pgm.s;
1502	unsigned i;
1503
1504	/*
1505	* Note! The layout of this function matches the member layout exactly!
1506	*/
1507
1508	/* Common - misc variables */
1509	STAM_REG(pVM, &pPGM->cAllPages, STAMTYPE_U32, "/PGM/Page/cAllPages", STAMUNIT_OCCURENCES, "The total number of pages.");
1510	STAM_REG(pVM, &pPGM->cPrivatePages, STAMTYPE_U32, "/PGM/Page/cPrivatePages", STAMUNIT_OCCURENCES, "The number of private pages.");
1511	STAM_REG(pVM, &pPGM->cSharedPages, STAMTYPE_U32, "/PGM/Page/cSharedPages", STAMUNIT_OCCURENCES, "The number of shared pages.");
1512	STAM_REG(pVM, &pPGM->cZeroPages, STAMTYPE_U32, "/PGM/Page/cZeroPages", STAMUNIT_OCCURENCES, "The number of zero backed pages.");
1513	STAM_REG(pVM, &pPGM->ChunkR3Map.c, STAMTYPE_U32, "/PGM/ChunkR3Map/c", STAMUNIT_OCCURENCES, "Number of mapped chunks.");
1514	STAM_REG(pVM, &pPGM->ChunkR3Map.cMax, STAMTYPE_U32, "/PGM/ChunkR3Map/cMax", STAMUNIT_OCCURENCES, "Maximum number of mapped chunks.");
1515
1516	/* Common - stats */
1517	#ifdef PGMPOOL_WITH_GCPHYS_TRACKING
1518	STAM_REG(pVM, &pPGM->StatTrackVirgin, STAMTYPE_COUNTER, "/PGM/Track/Virgin", STAMUNIT_OCCURENCES, "The number of first time shadowings");
1519	STAM_REG(pVM, &pPGM->StatTrackAliased, STAMTYPE_COUNTER, "/PGM/Track/Aliased", STAMUNIT_OCCURENCES, "The number of times switching to cRef2, i.e. the page is being shadowed by two PTs.");
1520	STAM_REG(pVM, &pPGM->StatTrackAliasedMany, STAMTYPE_COUNTER, "/PGM/Track/AliasedMany", STAMUNIT_OCCURENCES, "The number of times we're tracking using cRef2.");
1521	STAM_REG(pVM, &pPGM->StatTrackAliasedLots, STAMTYPE_COUNTER, "/PGM/Track/AliasedLots", STAMUNIT_OCCURENCES, "The number of times we're hitting pages which has overflowed cRef2");
1522	STAM_REG(pVM, &pPGM->StatTrackOverflows, STAMTYPE_COUNTER, "/PGM/Track/Overflows", STAMUNIT_OCCURENCES, "The number of times the extent list grows to long.");
1523	STAM_REG(pVM, &pPGM->StatTrackDeref, STAMTYPE_PROFILE, "/PGM/Track/Deref", STAMUNIT_OCCURENCES, "Profiling of SyncPageWorkerTrackDeref (expensive).");
1524	#endif
1525	for (i = 0; i < RT_ELEMENTS(pPGM->StatSyncPtPD); i++)
1526	STAMR3RegisterF(pVM, &pPGM->StatSyncPtPD[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
1527	"The number of SyncPT per PD n.", "/PGM/PDSyncPT/%04X", i);
1528	for (i = 0; i < RT_ELEMENTS(pPGM->StatSyncPagePD); i++)
1529	STAMR3RegisterF(pVM, &pPGM->StatSyncPagePD[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
1530	"The number of SyncPage per PD n.", "/PGM/PDSyncPage/%04X", i);
1531
1532	/* R3 only: */
1533	STAM_REG(pVM, &pPGM->StatR3DetectedConflicts, STAMTYPE_COUNTER, "/PGM/R3/DetectedConflicts", STAMUNIT_OCCURENCES, "The number of times PGMR3CheckMappingConflicts() detected a conflict.");
1534	STAM_REG(pVM, &pPGM->StatR3ResolveConflict, STAMTYPE_PROFILE, "/PGM/R3/ResolveConflict", STAMUNIT_TICKS_PER_CALL, "pgmR3SyncPTResolveConflict() profiling (includes the entire relocation).");
1535	STAM_REG(pVM, &pPGM->StatR3GuestPDWrite, STAMTYPE_COUNTER, "/PGM/R3/PDWrite", STAMUNIT_OCCURENCES, "The total number of times pgmHCGuestPDWriteHandler() was called.");
1536	STAM_REG(pVM, &pPGM->StatR3GuestPDWriteConflict, STAMTYPE_COUNTER, "/PGM/R3/PDWriteConflict", STAMUNIT_OCCURENCES, "The number of times pgmHCGuestPDWriteHandler() detected a conflict.");
1537	STAM_REG(pVM, &pPGM->StatR3DynRamTotal, STAMTYPE_COUNTER, "/PGM/DynAlloc/TotalAlloc", STAMUNIT_MEGABYTES, "Allocated MBs of guest ram.");
1538	STAM_REG(pVM, &pPGM->StatR3DynRamGrow, STAMTYPE_COUNTER, "/PGM/DynAlloc/Grow", STAMUNIT_OCCURENCES, "Nr of pgmr3PhysGrowRange calls.");
1539
1540	/* GC only: */
1541	STAM_REG(pVM, &pPGM->StatRCInvalidatePage, STAMTYPE_PROFILE, "/PGM/RC/InvalidatePage", STAMUNIT_TICKS_PER_CALL, "PGMGCInvalidatePage() profiling.");
1542	STAM_REG(pVM, &pPGM->StatRCDynMapCacheHits, STAMTYPE_COUNTER, "/PGM/RC/DynMapCache/Hits" , STAMUNIT_OCCURENCES, "Number of dynamic page mapping cache hits.");
1543	STAM_REG(pVM, &pPGM->StatRCDynMapCacheMisses, STAMTYPE_COUNTER, "/PGM/RC/DynMapCache/Misses" , STAMUNIT_OCCURENCES, "Number of dynamic page mapping cache misses.");
1544
1545	/* RZ only: */
1546	STAM_REG(pVM, &pPGM->StatRZTrap0e, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMTrap0eHandler() body.");
1547	STAM_REG(pVM, &pPGM->StatRZTrap0eTimeCheckPageFault, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time/CheckPageFault", STAMUNIT_TICKS_PER_CALL, "Profiling of checking for dirty/access emulation faults.");
1548	STAM_REG(pVM, &pPGM->StatRZTrap0eTimeSyncPT, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time/SyncPT", STAMUNIT_TICKS_PER_CALL, "Profiling of lazy page table syncing.");
1549	STAM_REG(pVM, &pPGM->StatRZTrap0eTimeMapping, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time/Mapping", STAMUNIT_TICKS_PER_CALL, "Profiling of checking virtual mappings.");
1550	STAM_REG(pVM, &pPGM->StatRZTrap0eTimeOutOfSync, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time/OutOfSync", STAMUNIT_TICKS_PER_CALL, "Profiling of out of sync page handling.");
1551	STAM_REG(pVM, &pPGM->StatRZTrap0eTimeHandlers, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time/Handlers", STAMUNIT_TICKS_PER_CALL, "Profiling of checking handlers.");
1552	STAM_REG(pVM, &pPGM->StatRZTrap0eTime2CSAM, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time2/CSAM", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is CSAM.");
1553	STAM_REG(pVM, &pPGM->StatRZTrap0eTime2DirtyAndAccessed, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time2/DirtyAndAccessedBits", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is dirty and/or accessed bit emulation.");
1554	STAM_REG(pVM, &pPGM->StatRZTrap0eTime2GuestTrap, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time2/GuestTrap", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is a guest trap.");
1555	STAM_REG(pVM, &pPGM->StatRZTrap0eTime2HndPhys, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time2/HandlerPhysical", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is a physical handler.");
1556	STAM_REG(pVM, &pPGM->StatRZTrap0eTime2HndVirt, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time2/HandlerVirtual", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is a virtual handler.");
1557	STAM_REG(pVM, &pPGM->StatRZTrap0eTime2HndUnhandled, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time2/HandlerUnhandled", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is access outside the monitored areas of a monitored page.");
1558	STAM_REG(pVM, &pPGM->StatRZTrap0eTime2Misc, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time2/Misc", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is not known.");
1559	STAM_REG(pVM, &pPGM->StatRZTrap0eTime2OutOfSync, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time2/OutOfSync", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is an out-of-sync page.");
1560	STAM_REG(pVM, &pPGM->StatRZTrap0eTime2OutOfSyncHndPhys, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time2/OutOfSyncHndPhys", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is an out-of-sync physical handler page.");
1561	STAM_REG(pVM, &pPGM->StatRZTrap0eTime2OutOfSyncHndVirt, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time2/OutOfSyncHndVirt", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is an out-of-sync virtual handler page.");
1562	STAM_REG(pVM, &pPGM->StatRZTrap0eTime2OutOfSyncHndObs, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time2/OutOfSyncObsHnd", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is an obsolete handler page.");
1563	STAM_REG(pVM, &pPGM->StatRZTrap0eTime2SyncPT, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time2/SyncPT", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is lazy syncing of a PT.");
1564	STAM_REG(pVM, &pPGM->StatRZTrap0eConflicts, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Conflicts", STAMUNIT_OCCURENCES, "The number of times #PF was caused by an undetected conflict.");
1565	STAM_REG(pVM, &pPGM->StatRZTrap0eHandlersMapping, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Handlers/Mapping", STAMUNIT_OCCURENCES, "Number of traps due to access handlers in mappings.");
1566	STAM_REG(pVM, &pPGM->StatRZTrap0eHandlersOutOfSync, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Handlers/OutOfSync", STAMUNIT_OCCURENCES, "Number of traps due to out-of-sync handled pages.");
1567	STAM_REG(pVM, &pPGM->StatRZTrap0eHandlersPhysical, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Handlers/Physical", STAMUNIT_OCCURENCES, "Number of traps due to physical access handlers.");
1568	STAM_REG(pVM, &pPGM->StatRZTrap0eHandlersVirtual, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Handlers/Virtual", STAMUNIT_OCCURENCES, "Number of traps due to virtual access handlers.");
1569	STAM_REG(pVM, &pPGM->StatRZTrap0eHandlersVirtualByPhys, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Handlers/VirtualByPhys", STAMUNIT_OCCURENCES, "Number of traps due to virtual access handlers by physical address.");
1570	STAM_REG(pVM, &pPGM->StatRZTrap0eHandlersVirtualUnmarked,STAMTYPE_COUNTER,"/PGM/RZ/Trap0e/Handlers/VirtualUnmarked",STAMUNIT_OCCURENCES, "Number of traps due to virtual access handlers by virtual address (without proper physical flags).");
1571	STAM_REG(pVM, &pPGM->StatRZTrap0eHandlersUnhandled, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Handlers/Unhandled", STAMUNIT_OCCURENCES, "Number of traps due to access outside range of monitored page(s).");
1572	STAM_REG(pVM, &pPGM->StatRZTrap0eHandlersInvalid, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Handlers/Invalid", STAMUNIT_OCCURENCES, "Number of traps due to access to invalid physical memory.");
1573	STAM_REG(pVM, &pPGM->StatRZTrap0eUSNotPresentRead, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Err/User/NPRead", STAMUNIT_OCCURENCES, "Number of user mode not present read page faults.");
1574	STAM_REG(pVM, &pPGM->StatRZTrap0eUSNotPresentWrite, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Err/User/NPWrite", STAMUNIT_OCCURENCES, "Number of user mode not present write page faults.");
1575	STAM_REG(pVM, &pPGM->StatRZTrap0eUSWrite, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Err/User/Write", STAMUNIT_OCCURENCES, "Number of user mode write page faults.");
1576	STAM_REG(pVM, &pPGM->StatRZTrap0eUSReserved, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Err/User/Reserved", STAMUNIT_OCCURENCES, "Number of user mode reserved bit page faults.");
1577	STAM_REG(pVM, &pPGM->StatRZTrap0eUSNXE, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Err/User/NXE", STAMUNIT_OCCURENCES, "Number of user mode NXE page faults.");
1578	STAM_REG(pVM, &pPGM->StatRZTrap0eUSRead, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Err/User/Read", STAMUNIT_OCCURENCES, "Number of user mode read page faults.");
1579	STAM_REG(pVM, &pPGM->StatRZTrap0eSVNotPresentRead, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Err/Supervisor/NPRead", STAMUNIT_OCCURENCES, "Number of supervisor mode not present read page faults.");
1580	STAM_REG(pVM, &pPGM->StatRZTrap0eSVNotPresentWrite, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Err/Supervisor/NPWrite", STAMUNIT_OCCURENCES, "Number of supervisor mode not present write page faults.");
1581	STAM_REG(pVM, &pPGM->StatRZTrap0eSVWrite, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Err/Supervisor/Write", STAMUNIT_OCCURENCES, "Number of supervisor mode write page faults.");
1582	STAM_REG(pVM, &pPGM->StatRZTrap0eSVReserved, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Err/Supervisor/Reserved", STAMUNIT_OCCURENCES, "Number of supervisor mode reserved bit page faults.");
1583	STAM_REG(pVM, &pPGM->StatRZTrap0eSNXE, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Err/Supervisor/NXE", STAMUNIT_OCCURENCES, "Number of supervisor mode NXE page faults.");
1584	STAM_REG(pVM, &pPGM->StatRZTrap0eGuestPF, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/GuestPF", STAMUNIT_OCCURENCES, "Number of real guest page faults.");
1585	STAM_REG(pVM, &pPGM->StatRZTrap0eGuestPFUnh, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/GuestPF/Unhandled", STAMUNIT_OCCURENCES, "Number of real guest page faults from the 'unhandled' case.");
1586	STAM_REG(pVM, &pPGM->StatRZTrap0eGuestPFMapping, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/GuestPF/InMapping", STAMUNIT_OCCURENCES, "Number of real guest page faults in a mapping.");
1587	STAM_REG(pVM, &pPGM->StatRZTrap0eWPEmulInRZ, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/WP/InRZ", STAMUNIT_OCCURENCES, "Number of guest page faults due to X86_CR0_WP emulation.");
1588	STAM_REG(pVM, &pPGM->StatRZTrap0eWPEmulToR3, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/WP/ToR3", STAMUNIT_OCCURENCES, "Number of guest page faults due to X86_CR0_WP emulation (forward to R3 for emulation).");
1589	for (i = 0; i < RT_ELEMENTS(pPGM->StatRZTrap0ePD); i++)
1590	STAMR3RegisterF(pVM, &pPGM->StatRZTrap0ePD[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
1591	"The number of traps in page directory n.", "/PGM/RZ/Trap0e/PD/%04X", i);
1592	STAM_REG(pVM, &pPGM->StatRZGuestCR3WriteHandled, STAMTYPE_COUNTER, "/PGM/RZ/CR3WriteHandled", STAMUNIT_OCCURENCES, "The number of times the Guest CR3 change was successfully handled.");
1593	STAM_REG(pVM, &pPGM->StatRZGuestCR3WriteUnhandled, STAMTYPE_COUNTER, "/PGM/RZ/CR3WriteUnhandled", STAMUNIT_OCCURENCES, "The number of times the Guest CR3 change was passed back to the recompiler.");
1594	STAM_REG(pVM, &pPGM->StatRZGuestCR3WriteConflict, STAMTYPE_COUNTER, "/PGM/RZ/CR3WriteConflict", STAMUNIT_OCCURENCES, "The number of times the Guest CR3 monitoring detected a conflict.");
1595	STAM_REG(pVM, &pPGM->StatRZGuestROMWriteHandled, STAMTYPE_COUNTER, "/PGM/RZ/ROMWriteHandled", STAMUNIT_OCCURENCES, "The number of times the Guest ROM change was successfully handled.");
1596	STAM_REG(pVM, &pPGM->StatRZGuestROMWriteUnhandled, STAMTYPE_COUNTER, "/PGM/RZ/ROMWriteUnhandled", STAMUNIT_OCCURENCES, "The number of times the Guest ROM change was passed back to the recompiler.");
1597
1598	/* HC only: */
1599
1600	/* RZ & R3: */
1601	STAM_REG(pVM, &pPGM->StatRZSyncCR3, STAMTYPE_PROFILE, "/PGM/RZ/SyncCR3", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMSyncCR3() body.");
1602	STAM_REG(pVM, &pPGM->StatRZSyncCR3Handlers, STAMTYPE_PROFILE, "/PGM/RZ/SyncCR3/Handlers", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMSyncCR3() update handler section.");
1603	STAM_REG(pVM, &pPGM->StatRZSyncCR3HandlerVirtualUpdate, STAMTYPE_PROFILE, "/PGM/RZ/SyncCR3/Handlers/VirtualUpdate", STAMUNIT_TICKS_PER_CALL, "Profiling of the virtual handler updates.");
1604	STAM_REG(pVM, &pPGM->StatRZSyncCR3HandlerVirtualReset, STAMTYPE_PROFILE, "/PGM/RZ/SyncCR3/Handlers/VirtualReset", STAMUNIT_TICKS_PER_CALL, "Profiling of the virtual handler resets.");
1605	STAM_REG(pVM, &pPGM->StatRZSyncCR3Global, STAMTYPE_COUNTER, "/PGM/RZ/SyncCR3/Global", STAMUNIT_OCCURENCES, "The number of global CR3 syncs.");
1606	STAM_REG(pVM, &pPGM->StatRZSyncCR3NotGlobal, STAMTYPE_COUNTER, "/PGM/RZ/SyncCR3/NotGlobal", STAMUNIT_OCCURENCES, "The number of non-global CR3 syncs.");
1607	STAM_REG(pVM, &pPGM->StatRZSyncCR3DstCacheHit, STAMTYPE_COUNTER, "/PGM/RZ/SyncCR3/DstChacheHit", STAMUNIT_OCCURENCES, "The number of times we got some kind of a cache hit.");
1608	STAM_REG(pVM, &pPGM->StatRZSyncCR3DstFreed, STAMTYPE_COUNTER, "/PGM/RZ/SyncCR3/DstFreed", STAMUNIT_OCCURENCES, "The number of times we've had to free a shadow entry.");
1609	STAM_REG(pVM, &pPGM->StatRZSyncCR3DstFreedSrcNP, STAMTYPE_COUNTER, "/PGM/RZ/SyncCR3/DstFreedSrcNP", STAMUNIT_OCCURENCES, "The number of times we've had to free a shadow entry for which the source entry was not present.");
1610	STAM_REG(pVM, &pPGM->StatRZSyncCR3DstNotPresent, STAMTYPE_COUNTER, "/PGM/RZ/SyncCR3/DstNotPresent", STAMUNIT_OCCURENCES, "The number of times we've encountered a not present shadow entry for a present guest entry.");
1611	STAM_REG(pVM, &pPGM->StatRZSyncCR3DstSkippedGlobalPD, STAMTYPE_COUNTER, "/PGM/RZ/SyncCR3/DstSkippedGlobalPD", STAMUNIT_OCCURENCES, "The number of times a global page directory wasn't flushed.");
1612	STAM_REG(pVM, &pPGM->StatRZSyncCR3DstSkippedGlobalPT, STAMTYPE_COUNTER, "/PGM/RZ/SyncCR3/DstSkippedGlobalPT", STAMUNIT_OCCURENCES, "The number of times a page table with only global entries wasn't flushed.");
1613	STAM_REG(pVM, &pPGM->StatRZSyncPT, STAMTYPE_PROFILE, "/PGM/RZ/SyncPT", STAMUNIT_TICKS_PER_CALL, "Profiling of the pfnSyncPT() body.");
1614	STAM_REG(pVM, &pPGM->StatRZSyncPTFailed, STAMTYPE_COUNTER, "/PGM/RZ/SyncPT/Failed", STAMUNIT_OCCURENCES, "The number of times pfnSyncPT() failed.");
1615	STAM_REG(pVM, &pPGM->StatRZSyncPT4K, STAMTYPE_COUNTER, "/PGM/RZ/SyncPT/4K", STAMUNIT_OCCURENCES, "Nr of 4K PT syncs");
1616	STAM_REG(pVM, &pPGM->StatRZSyncPT4M, STAMTYPE_COUNTER, "/PGM/RZ/SyncPT/4M", STAMUNIT_OCCURENCES, "Nr of 4M PT syncs");
1617	STAM_REG(pVM, &pPGM->StatRZSyncPagePDNAs, STAMTYPE_COUNTER, "/PGM/RZ/SyncPagePDNAs", STAMUNIT_OCCURENCES, "The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit.");
1618	STAM_REG(pVM, &pPGM->StatRZSyncPagePDOutOfSync, STAMTYPE_COUNTER, "/PGM/RZ/SyncPagePDOutOfSync", STAMUNIT_OCCURENCES, "The number of time we've encountered an out-of-sync PD in SyncPage.");
1619	STAM_REG(pVM, &pPGM->StatRZAccessedPage, STAMTYPE_COUNTER, "/PGM/RZ/AccessedPage", STAMUNIT_OCCURENCES, "The number of pages marked not present for accessed bit emulation.");
1620	STAM_REG(pVM, &pPGM->StatRZDirtyBitTracking, STAMTYPE_PROFILE, "/PGM/RZ/DirtyPage", STAMUNIT_TICKS_PER_CALL, "Profiling the dirty bit tracking in CheckPageFault().");
1621	STAM_REG(pVM, &pPGM->StatRZDirtyPage, STAMTYPE_COUNTER, "/PGM/RZ/DirtyPage/Mark", STAMUNIT_OCCURENCES, "The number of pages marked read-only for dirty bit tracking.");
1622	STAM_REG(pVM, &pPGM->StatRZDirtyPageBig, STAMTYPE_COUNTER, "/PGM/RZ/DirtyPage/MarkBig", STAMUNIT_OCCURENCES, "The number of 4MB pages marked read-only for dirty bit tracking.");
1623	STAM_REG(pVM, &pPGM->StatRZDirtyPageSkipped, STAMTYPE_COUNTER, "/PGM/RZ/DirtyPage/Skipped", STAMUNIT_OCCURENCES, "The number of pages already dirty or readonly.");
1624	STAM_REG(pVM, &pPGM->StatRZDirtyPageTrap, STAMTYPE_COUNTER, "/PGM/RZ/DirtyPage/Trap", STAMUNIT_OCCURENCES, "The number of traps generated for dirty bit tracking.");
1625	STAM_REG(pVM, &pPGM->StatRZDirtiedPage, STAMTYPE_COUNTER, "/PGM/RZ/DirtyPage/SetDirty", STAMUNIT_OCCURENCES, "The number of pages marked dirty because of write accesses.");
1626	STAM_REG(pVM, &pPGM->StatRZDirtyTrackRealPF, STAMTYPE_COUNTER, "/PGM/RZ/DirtyPage/RealPF", STAMUNIT_OCCURENCES, "The number of real pages faults during dirty bit tracking.");
1627	STAM_REG(pVM, &pPGM->StatRZPageAlreadyDirty, STAMTYPE_COUNTER, "/PGM/RZ/DirtyPage/AlreadySet", STAMUNIT_OCCURENCES, "The number of pages already marked dirty because of write accesses.");
1628	STAM_REG(pVM, &pPGM->StatRZInvalidatePage, STAMTYPE_PROFILE, "/PGM/RZ/InvalidatePage", STAMUNIT_TICKS_PER_CALL, "PGMInvalidatePage() profiling.");
1629	STAM_REG(pVM, &pPGM->StatRZInvalidatePage4KBPages, STAMTYPE_COUNTER, "/PGM/RZ/InvalidatePage/4KBPages", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was called for a 4KB page.");
1630	STAM_REG(pVM, &pPGM->StatRZInvalidatePage4MBPages, STAMTYPE_COUNTER, "/PGM/RZ/InvalidatePage/4MBPages", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was called for a 4MB page.");
1631	STAM_REG(pVM, &pPGM->StatRZInvalidatePage4MBPagesSkip, STAMTYPE_COUNTER, "/PGM/RZ/InvalidatePage/4MBPagesSkip",STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() skipped a 4MB page.");
1632	STAM_REG(pVM, &pPGM->StatRZInvalidatePagePDMappings, STAMTYPE_COUNTER, "/PGM/RZ/InvalidatePage/PDMappings", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict).");
1633	STAM_REG(pVM, &pPGM->StatRZInvalidatePagePDNAs, STAMTYPE_COUNTER, "/PGM/RZ/InvalidatePage/PDNAs", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was called for a not accessed page directory.");
1634	STAM_REG(pVM, &pPGM->StatRZInvalidatePagePDNPs, STAMTYPE_COUNTER, "/PGM/RZ/InvalidatePage/PDNPs", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was called for a not present page directory.");
1635	STAM_REG(pVM, &pPGM->StatRZInvalidatePagePDOutOfSync, STAMTYPE_COUNTER, "/PGM/RZ/InvalidatePage/PDOutOfSync", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was called for an out of sync page directory.");
1636	STAM_REG(pVM, &pPGM->StatRZInvalidatePageSkipped, STAMTYPE_COUNTER, "/PGM/RZ/InvalidatePage/Skipped", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3.");
1637	STAM_REG(pVM, &pPGM->StatRZVirtHandlerSearchByPhys, STAMTYPE_PROFILE, "/PGM/RZ/VirtHandlerSearchByPhys", STAMUNIT_TICKS_PER_CALL, "Profiling of pgmHandlerVirtualFindByPhysAddr.");
1638	STAM_REG(pVM, &pPGM->StatRZPhysHandlerReset, STAMTYPE_COUNTER, "/PGM/RZ/PhysHandlerReset", STAMUNIT_OCCURENCES, "The number of times PGMHandlerPhysicalReset is called.");
1639	STAM_REG(pVM, &pPGM->StatRZPageOutOfSyncSupervisor, STAMTYPE_COUNTER, "/PGM/RZ/OutOfSync/SuperVisor", STAMUNIT_OCCURENCES, "Number of traps due to pages out of sync and times VerifyAccessSyncPage calls SyncPage.");
1640	STAM_REG(pVM, &pPGM->StatRZPageOutOfSyncUser, STAMTYPE_COUNTER, "/PGM/RZ/OutOfSync/User", STAMUNIT_OCCURENCES, "Number of traps due to pages out of sync and times VerifyAccessSyncPage calls SyncPage.");
1641	STAM_REG(pVM, &pPGM->StatRZPrefetch, STAMTYPE_PROFILE, "/PGM/RZ/Prefetch", STAMUNIT_TICKS_PER_CALL, "PGMPrefetchPage profiling.");
1642	STAM_REG(pVM, &pPGM->StatRZChunkR3MapTlbHits, STAMTYPE_COUNTER, "/PGM/ChunkR3Map/TlbHitsRZ", STAMUNIT_OCCURENCES, "TLB hits.");
1643	STAM_REG(pVM, &pPGM->StatRZChunkR3MapTlbMisses, STAMTYPE_COUNTER, "/PGM/ChunkR3Map/TlbMissesRZ", STAMUNIT_OCCURENCES, "TLB misses.");
1644	STAM_REG(pVM, &pPGM->StatRZPageMapTlbHits, STAMTYPE_COUNTER, "/PGM/RZ/Page/MapTlbHits", STAMUNIT_OCCURENCES, "TLB hits.");
1645	STAM_REG(pVM, &pPGM->StatRZPageMapTlbMisses, STAMTYPE_COUNTER, "/PGM/RZ/Page/MapTlbMisses", STAMUNIT_OCCURENCES, "TLB misses.");
1646	STAM_REG(pVM, &pPGM->StatRZPageReplaceShared, STAMTYPE_COUNTER, "/PGM/RZ/Page/ReplacedShared", STAMUNIT_OCCURENCES, "Times a shared page was replaced.");
1647	STAM_REG(pVM, &pPGM->StatRZPageReplaceZero, STAMTYPE_COUNTER, "/PGM/RZ/Page/ReplacedZero", STAMUNIT_OCCURENCES, "Times the zero page was replaced.");
1648	/// @todo STAM_REG(pVM, &pPGM->StatRZPageHandyAllocs, STAMTYPE_COUNTER, "/PGM/RZ/Page/HandyAllocs", STAMUNIT_OCCURENCES, "Number of times we've allocated more handy pages.");
1649	STAM_REG(pVM, &pPGM->StatRZFlushTLB, STAMTYPE_PROFILE, "/PGM/RZ/FlushTLB", STAMUNIT_OCCURENCES, "Profiling of the PGMFlushTLB() body.");
1650	STAM_REG(pVM, &pPGM->StatRZFlushTLBNewCR3, STAMTYPE_COUNTER, "/PGM/RZ/FlushTLB/NewCR3", STAMUNIT_OCCURENCES, "The number of times PGMFlushTLB was called with a new CR3, non-global. (switch)");
1651	STAM_REG(pVM, &pPGM->StatRZFlushTLBNewCR3Global, STAMTYPE_COUNTER, "/PGM/RZ/FlushTLB/NewCR3Global", STAMUNIT_OCCURENCES, "The number of times PGMFlushTLB was called with a new CR3, global. (switch)");
1652	STAM_REG(pVM, &pPGM->StatRZFlushTLBSameCR3, STAMTYPE_COUNTER, "/PGM/RZ/FlushTLB/SameCR3", STAMUNIT_OCCURENCES, "The number of times PGMFlushTLB was called with the same CR3, non-global. (flush)");
1653	STAM_REG(pVM, &pPGM->StatRZFlushTLBSameCR3Global, STAMTYPE_COUNTER, "/PGM/RZ/FlushTLB/SameCR3Global", STAMUNIT_OCCURENCES, "The number of times PGMFlushTLB was called with the same CR3, global. (flush)");
1654	STAM_REG(pVM, &pPGM->StatRZGstModifyPage, STAMTYPE_PROFILE, "/PGM/RZ/GstModifyPage", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMGstModifyPage() body.");
1655
1656	STAM_REG(pVM, &pPGM->StatR3SyncCR3, STAMTYPE_PROFILE, "/PGM/R3/SyncCR3", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMSyncCR3() body.");
1657	STAM_REG(pVM, &pPGM->StatR3SyncCR3Handlers, STAMTYPE_PROFILE, "/PGM/R3/SyncCR3/Handlers", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMSyncCR3() update handler section.");
1658	STAM_REG(pVM, &pPGM->StatR3SyncCR3HandlerVirtualUpdate, STAMTYPE_PROFILE, "/PGM/R3/SyncCR3/Handlers/VirtualUpdate", STAMUNIT_TICKS_PER_CALL, "Profiling of the virtual handler updates.");
1659	STAM_REG(pVM, &pPGM->StatR3SyncCR3HandlerVirtualReset, STAMTYPE_PROFILE, "/PGM/R3/SyncCR3/Handlers/VirtualReset", STAMUNIT_TICKS_PER_CALL, "Profiling of the virtual handler resets.");
1660	STAM_REG(pVM, &pPGM->StatR3SyncCR3Global, STAMTYPE_COUNTER, "/PGM/R3/SyncCR3/Global", STAMUNIT_OCCURENCES, "The number of global CR3 syncs.");
1661	STAM_REG(pVM, &pPGM->StatR3SyncCR3NotGlobal, STAMTYPE_COUNTER, "/PGM/R3/SyncCR3/NotGlobal", STAMUNIT_OCCURENCES, "The number of non-global CR3 syncs.");
1662	STAM_REG(pVM, &pPGM->StatR3SyncCR3DstCacheHit, STAMTYPE_COUNTER, "/PGM/R3/SyncCR3/DstChacheHit", STAMUNIT_OCCURENCES, "The number of times we got some kind of a cache hit.");
1663	STAM_REG(pVM, &pPGM->StatR3SyncCR3DstFreed, STAMTYPE_COUNTER, "/PGM/R3/SyncCR3/DstFreed", STAMUNIT_OCCURENCES, "The number of times we've had to free a shadow entry.");
1664	STAM_REG(pVM, &pPGM->StatR3SyncCR3DstFreedSrcNP, STAMTYPE_COUNTER, "/PGM/R3/SyncCR3/DstFreedSrcNP", STAMUNIT_OCCURENCES, "The number of times we've had to free a shadow entry for which the source entry was not present.");
1665	STAM_REG(pVM, &pPGM->StatR3SyncCR3DstNotPresent, STAMTYPE_COUNTER, "/PGM/R3/SyncCR3/DstNotPresent", STAMUNIT_OCCURENCES, "The number of times we've encountered a not present shadow entry for a present guest entry.");
1666	STAM_REG(pVM, &pPGM->StatR3SyncCR3DstSkippedGlobalPD, STAMTYPE_COUNTER, "/PGM/R3/SyncCR3/DstSkippedGlobalPD", STAMUNIT_OCCURENCES, "The number of times a global page directory wasn't flushed.");
1667	STAM_REG(pVM, &pPGM->StatR3SyncCR3DstSkippedGlobalPT, STAMTYPE_COUNTER, "/PGM/R3/SyncCR3/DstSkippedGlobalPT", STAMUNIT_OCCURENCES, "The number of times a page table with only global entries wasn't flushed.");
1668	STAM_REG(pVM, &pPGM->StatR3SyncPT, STAMTYPE_PROFILE, "/PGM/R3/SyncPT", STAMUNIT_TICKS_PER_CALL, "Profiling of the pfnSyncPT() body.");
1669	STAM_REG(pVM, &pPGM->StatR3SyncPTFailed, STAMTYPE_COUNTER, "/PGM/R3/SyncPT/Failed", STAMUNIT_OCCURENCES, "The number of times pfnSyncPT() failed.");
1670	STAM_REG(pVM, &pPGM->StatR3SyncPT4K, STAMTYPE_COUNTER, "/PGM/R3/SyncPT/4K", STAMUNIT_OCCURENCES, "Nr of 4K PT syncs");
1671	STAM_REG(pVM, &pPGM->StatR3SyncPT4M, STAMTYPE_COUNTER, "/PGM/R3/SyncPT/4M", STAMUNIT_OCCURENCES, "Nr of 4M PT syncs");
1672	STAM_REG(pVM, &pPGM->StatR3SyncPagePDNAs, STAMTYPE_COUNTER, "/PGM/R3/SyncPagePDNAs", STAMUNIT_OCCURENCES, "The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit.");
1673	STAM_REG(pVM, &pPGM->StatR3SyncPagePDOutOfSync, STAMTYPE_COUNTER, "/PGM/R3/SyncPagePDOutOfSync", STAMUNIT_OCCURENCES, "The number of time we've encountered an out-of-sync PD in SyncPage.");
1674	STAM_REG(pVM, &pPGM->StatR3AccessedPage, STAMTYPE_COUNTER, "/PGM/R3/AccessedPage", STAMUNIT_OCCURENCES, "The number of pages marked not present for accessed bit emulation.");
1675	STAM_REG(pVM, &pPGM->StatR3DirtyBitTracking, STAMTYPE_PROFILE, "/PGM/R3/DirtyPage", STAMUNIT_TICKS_PER_CALL, "Profiling the dirty bit tracking in CheckPageFault().");
1676	STAM_REG(pVM, &pPGM->StatR3DirtyPage, STAMTYPE_COUNTER, "/PGM/R3/DirtyPage/Mark", STAMUNIT_OCCURENCES, "The number of pages marked read-only for dirty bit tracking.");
1677	STAM_REG(pVM, &pPGM->StatR3DirtyPageBig, STAMTYPE_COUNTER, "/PGM/R3/DirtyPage/MarkBig", STAMUNIT_OCCURENCES, "The number of 4MB pages marked read-only for dirty bit tracking.");
1678	STAM_REG(pVM, &pPGM->StatR3DirtyPageSkipped, STAMTYPE_COUNTER, "/PGM/R3/DirtyPage/Skipped", STAMUNIT_OCCURENCES, "The number of pages already dirty or readonly.");
1679	STAM_REG(pVM, &pPGM->StatR3DirtyPageTrap, STAMTYPE_COUNTER, "/PGM/R3/DirtyPage/Trap", STAMUNIT_OCCURENCES, "The number of traps generated for dirty bit tracking.");
1680	STAM_REG(pVM, &pPGM->StatR3DirtiedPage, STAMTYPE_COUNTER, "/PGM/R3/DirtyPage/SetDirty", STAMUNIT_OCCURENCES, "The number of pages marked dirty because of write accesses.");
1681	STAM_REG(pVM, &pPGM->StatR3DirtyTrackRealPF, STAMTYPE_COUNTER, "/PGM/R3/DirtyPage/RealPF", STAMUNIT_OCCURENCES, "The number of real pages faults during dirty bit tracking.");
1682	STAM_REG(pVM, &pPGM->StatR3PageAlreadyDirty, STAMTYPE_COUNTER, "/PGM/R3/DirtyPage/AlreadySet", STAMUNIT_OCCURENCES, "The number of pages already marked dirty because of write accesses.");
1683	STAM_REG(pVM, &pPGM->StatR3InvalidatePage, STAMTYPE_PROFILE, "/PGM/R3/InvalidatePage", STAMUNIT_TICKS_PER_CALL, "PGMInvalidatePage() profiling.");
1684	STAM_REG(pVM, &pPGM->StatR3InvalidatePage4KBPages, STAMTYPE_COUNTER, "/PGM/R3/InvalidatePage/4KBPages", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was called for a 4KB page.");
1685	STAM_REG(pVM, &pPGM->StatR3InvalidatePage4MBPages, STAMTYPE_COUNTER, "/PGM/R3/InvalidatePage/4MBPages", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was called for a 4MB page.");
1686	STAM_REG(pVM, &pPGM->StatR3InvalidatePage4MBPagesSkip, STAMTYPE_COUNTER, "/PGM/R3/InvalidatePage/4MBPagesSkip",STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() skipped a 4MB page.");
1687	STAM_REG(pVM, &pPGM->StatR3InvalidatePagePDMappings, STAMTYPE_COUNTER, "/PGM/R3/InvalidatePage/PDMappings", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict).");
1688	STAM_REG(pVM, &pPGM->StatR3InvalidatePagePDNAs, STAMTYPE_COUNTER, "/PGM/R3/InvalidatePage/PDNAs", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was called for a not accessed page directory.");
1689	STAM_REG(pVM, &pPGM->StatR3InvalidatePagePDNPs, STAMTYPE_COUNTER, "/PGM/R3/InvalidatePage/PDNPs", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was called for a not present page directory.");
1690	STAM_REG(pVM, &pPGM->StatR3InvalidatePagePDOutOfSync, STAMTYPE_COUNTER, "/PGM/R3/InvalidatePage/PDOutOfSync", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was called for an out of sync page directory.");
1691	STAM_REG(pVM, &pPGM->StatR3InvalidatePageSkipped, STAMTYPE_COUNTER, "/PGM/R3/InvalidatePage/Skipped", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3.");
1692	STAM_REG(pVM, &pPGM->StatR3VirtHandlerSearchByPhys, STAMTYPE_PROFILE, "/PGM/R3/VirtHandlerSearchByPhys", STAMUNIT_TICKS_PER_CALL, "Profiling of pgmHandlerVirtualFindByPhysAddr.");
1693	STAM_REG(pVM, &pPGM->StatR3PhysHandlerReset, STAMTYPE_COUNTER, "/PGM/R3/PhysHandlerReset", STAMUNIT_OCCURENCES, "The number of times PGMHandlerPhysicalReset is called.");
1694	STAM_REG(pVM, &pPGM->StatR3PageOutOfSyncSupervisor, STAMTYPE_COUNTER, "/PGM/R3/OutOfSync/SuperVisor", STAMUNIT_OCCURENCES, "Number of traps due to pages out of sync and times VerifyAccessSyncPage calls SyncPage.");
1695	STAM_REG(pVM, &pPGM->StatR3PageOutOfSyncUser, STAMTYPE_COUNTER, "/PGM/R3/OutOfSync/User", STAMUNIT_OCCURENCES, "Number of traps due to pages out of sync and times VerifyAccessSyncPage calls SyncPage.");
1696	STAM_REG(pVM, &pPGM->StatR3Prefetch, STAMTYPE_PROFILE, "/PGM/R3/Prefetch", STAMUNIT_TICKS_PER_CALL, "PGMPrefetchPage profiling.");
1697	STAM_REG(pVM, &pPGM->StatR3ChunkR3MapTlbHits, STAMTYPE_COUNTER, "/PGM/ChunkR3Map/TlbHitsR3", STAMUNIT_OCCURENCES, "TLB hits.");
1698	STAM_REG(pVM, &pPGM->StatR3ChunkR3MapTlbMisses, STAMTYPE_COUNTER, "/PGM/ChunkR3Map/TlbMissesR3", STAMUNIT_OCCURENCES, "TLB misses.");
1699	STAM_REG(pVM, &pPGM->StatR3PageMapTlbHits, STAMTYPE_COUNTER, "/PGM/R3/Page/MapTlbHits", STAMUNIT_OCCURENCES, "TLB hits.");
1700	STAM_REG(pVM, &pPGM->StatR3PageMapTlbMisses, STAMTYPE_COUNTER, "/PGM/R3/Page/MapTlbMisses", STAMUNIT_OCCURENCES, "TLB misses.");
1701	STAM_REG(pVM, &pPGM->StatR3PageReplaceShared, STAMTYPE_COUNTER, "/PGM/R3/Page/ReplacedShared", STAMUNIT_OCCURENCES, "Times a shared page was replaced.");
1702	STAM_REG(pVM, &pPGM->StatR3PageReplaceZero, STAMTYPE_COUNTER, "/PGM/R3/Page/ReplacedZero", STAMUNIT_OCCURENCES, "Times the zero page was replaced.");
1703	/// @todo STAM_REG(pVM, &pPGM->StatR3PageHandyAllocs, STAMTYPE_COUNTER, "/PGM/R3/Page/HandyAllocs", STAMUNIT_OCCURENCES, "Number of times we've allocated more handy pages.");
1704	STAM_REG(pVM, &pPGM->StatR3FlushTLB, STAMTYPE_PROFILE, "/PGM/R3/FlushTLB", STAMUNIT_OCCURENCES, "Profiling of the PGMFlushTLB() body.");
1705	STAM_REG(pVM, &pPGM->StatR3FlushTLBNewCR3, STAMTYPE_COUNTER, "/PGM/R3/FlushTLB/NewCR3", STAMUNIT_OCCURENCES, "The number of times PGMFlushTLB was called with a new CR3, non-global. (switch)");
1706	STAM_REG(pVM, &pPGM->StatR3FlushTLBNewCR3Global, STAMTYPE_COUNTER, "/PGM/R3/FlushTLB/NewCR3Global", STAMUNIT_OCCURENCES, "The number of times PGMFlushTLB was called with a new CR3, global. (switch)");
1707	STAM_REG(pVM, &pPGM->StatR3FlushTLBSameCR3, STAMTYPE_COUNTER, "/PGM/R3/FlushTLB/SameCR3", STAMUNIT_OCCURENCES, "The number of times PGMFlushTLB was called with the same CR3, non-global. (flush)");
1708	STAM_REG(pVM, &pPGM->StatR3FlushTLBSameCR3Global, STAMTYPE_COUNTER, "/PGM/R3/FlushTLB/SameCR3Global", STAMUNIT_OCCURENCES, "The number of times PGMFlushTLB was called with the same CR3, global. (flush)");
1709	STAM_REG(pVM, &pPGM->StatR3GstModifyPage, STAMTYPE_PROFILE, "/PGM/R3/GstModifyPage", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMGstModifyPage() body.");
1710
1711	}
1712	#endif /* VBOX_WITH_STATISTICS */
1713
1714	/**
1715	* Init the PGM bits that rely on VMMR0 and MM to be fully initialized.
1716	*
1717	* The dynamic mapping area will also be allocated and initialized at this
1718	* time. We could allocate it during PGMR3Init of course, but the mapping
1719	* wouldn't be allocated at that time preventing us from setting up the
1720	* page table entries with the dummy page.
1721	*
1722	* @returns VBox status code.
1723	* @param pVM VM handle.
1724	*/
1725	VMMR3DECL(int) PGMR3InitDynMap(PVM pVM)
1726	{
1727	RTGCPTR GCPtr;
1728	/*
1729	* Reserve space for mapping the paging pages into guest context.
1730	*/
1731	int rc = MMR3HyperReserve(pVM, PAGE_SIZE * (2 + RT_ELEMENTS(pVM->pgm.s.apHCPaePDs) + 1 + 2 + 2), "Paging", &GCPtr);
1732	AssertRCReturn(rc, rc);
1733	pVM->pgm.s.pGC32BitPD = GCPtr;
1734	MMR3HyperReserve(pVM, PAGE_SIZE, "fence", NULL);
1735
1736	/*
1737	* Reserve space for the dynamic mappings.
1738	*/
1739	/** @todo r=bird: Need to verify that the checks for crossing PTs are correct here. They seems to be assuming 4MB PTs.. */
1740	rc = MMR3HyperReserve(pVM, MM_HYPER_DYNAMIC_SIZE, "Dynamic mapping", &GCPtr);
1741	if (VBOX_SUCCESS(rc))
1742	pVM->pgm.s.pbDynPageMapBaseGC = GCPtr;
1743
1744	if ( VBOX_SUCCESS(rc)
1745	&& (pVM->pgm.s.pbDynPageMapBaseGC >> X86_PD_SHIFT) != ((pVM->pgm.s.pbDynPageMapBaseGC + MM_HYPER_DYNAMIC_SIZE - 1) >> X86_PD_SHIFT))
1746	{
1747	rc = MMR3HyperReserve(pVM, MM_HYPER_DYNAMIC_SIZE, "Dynamic mapping not crossing", &GCPtr);
1748	if (VBOX_SUCCESS(rc))
1749	pVM->pgm.s.pbDynPageMapBaseGC = GCPtr;
1750	}
1751	if (VBOX_SUCCESS(rc))
1752	{
1753	AssertRelease((pVM->pgm.s.pbDynPageMapBaseGC >> X86_PD_SHIFT) == ((pVM->pgm.s.pbDynPageMapBaseGC + MM_HYPER_DYNAMIC_SIZE - 1) >> X86_PD_SHIFT));
1754	MMR3HyperReserve(pVM, PAGE_SIZE, "fence", NULL);
1755	}
1756	return rc;
1757	}
1758
1759
1760	/**
1761	* Ring-3 init finalizing.
1762	*
1763	* @returns VBox status code.
1764	* @param pVM The VM handle.
1765	*/
1766	VMMR3DECL(int) PGMR3InitFinalize(PVM pVM)
1767	{
1768	/*
1769	* Map the paging pages into the guest context.
1770	*/
1771	RTGCPTR GCPtr = pVM->pgm.s.pGC32BitPD;
1772	AssertReleaseReturn(GCPtr, VERR_INTERNAL_ERROR);
1773
1774	int rc = PGMMap(pVM, GCPtr, pVM->pgm.s.HCPhys32BitPD, PAGE_SIZE, 0);
1775	AssertRCReturn(rc, rc);
1776	pVM->pgm.s.pGC32BitPD = GCPtr;
1777	GCPtr += PAGE_SIZE;
1778	GCPtr += PAGE_SIZE; /* reserved page */
1779
1780	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.apHCPaePDs); i++)
1781	{
1782	rc = PGMMap(pVM, GCPtr, pVM->pgm.s.aHCPhysPaePDs[i], PAGE_SIZE, 0);
1783	AssertRCReturn(rc, rc);
1784	pVM->pgm.s.apGCPaePDs[i] = GCPtr;
1785	GCPtr += PAGE_SIZE;
1786	}
1787	/* A bit of paranoia is justified. */
1788	AssertRelease((RTGCUINTPTR)pVM->pgm.s.apGCPaePDs[0] + PAGE_SIZE == (RTGCUINTPTR)pVM->pgm.s.apGCPaePDs[1]);
1789	AssertRelease((RTGCUINTPTR)pVM->pgm.s.apGCPaePDs[1] + PAGE_SIZE == (RTGCUINTPTR)pVM->pgm.s.apGCPaePDs[2]);
1790	AssertRelease((RTGCUINTPTR)pVM->pgm.s.apGCPaePDs[2] + PAGE_SIZE == (RTGCUINTPTR)pVM->pgm.s.apGCPaePDs[3]);
1791	GCPtr += PAGE_SIZE; /* reserved page */
1792
1793	rc = PGMMap(pVM, GCPtr, pVM->pgm.s.HCPhysPaePDPT, PAGE_SIZE, 0);
1794	AssertRCReturn(rc, rc);
1795	pVM->pgm.s.pGCPaePDPT = GCPtr;
1796	GCPtr += PAGE_SIZE;
1797	GCPtr += PAGE_SIZE; /* reserved page */
1798
1799
1800	/*
1801	* Reserve space for the dynamic mappings.
1802	* Initialize the dynamic mapping pages with dummy pages to simply the cache.
1803	*/
1804	/* get the pointer to the page table entries. */
1805	PPGMMAPPING pMapping = pgmGetMapping(pVM, pVM->pgm.s.pbDynPageMapBaseGC);
1806	AssertRelease(pMapping);
1807	const uintptr_t off = pVM->pgm.s.pbDynPageMapBaseGC - pMapping->GCPtr;
1808	const unsigned iPT = off >> X86_PD_SHIFT;
1809	const unsigned iPG = (off >> X86_PT_SHIFT) & X86_PT_MASK;
1810	pVM->pgm.s.paDynPageMap32BitPTEsGC = pMapping->aPTs[iPT].pPTRC + iPG * sizeof(pMapping->aPTs[0].pPTR3->a[0]);
1811	pVM->pgm.s.paDynPageMapPaePTEsGC = pMapping->aPTs[iPT].paPaePTsRC + iPG * sizeof(pMapping->aPTs[0].paPaePTsR3->a[0]);
1812
1813	/* init cache */
1814	RTHCPHYS HCPhysDummy = MMR3PageDummyHCPhys(pVM);
1815	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.aHCPhysDynPageMapCache); i++)
1816	pVM->pgm.s.aHCPhysDynPageMapCache[i] = HCPhysDummy;
1817
1818	for (unsigned i = 0; i < MM_HYPER_DYNAMIC_SIZE; i += PAGE_SIZE)
1819	{
1820	rc = PGMMap(pVM, pVM->pgm.s.pbDynPageMapBaseGC + i, HCPhysDummy, PAGE_SIZE, 0);
1821	AssertRCReturn(rc, rc);
1822	}
1823
1824	/* Note that AMD uses all the 8 reserved bits for the address (so 40 bits in total); Intel only goes up to 36 bits, so
1825	* we stick to 36 as well.
1826	*
1827	* @todo How to test for the 40 bits support? Long mode seems to be the test criterium.
1828	*/
1829	uint32_t u32Dummy, u32Features;
1830	CPUMGetGuestCpuId(pVM, 1, &u32Dummy, &u32Dummy, &u32Dummy, &u32Features);
1831
1832	if (u32Features & X86_CPUID_FEATURE_EDX_PSE36)
1833	pVM->pgm.s.GCPhys4MBPSEMask = RT_BIT_64(36) - 1;
1834	else
1835	pVM->pgm.s.GCPhys4MBPSEMask = RT_BIT_64(32) - 1;
1836
1837	LogRel(("PGMR3InitFinalize: 4 MB PSE mask %VGp\n", pVM->pgm.s.GCPhys4MBPSEMask));
1838
1839	return rc;
1840	}
1841
1842
1843	/**
1844	* Applies relocations to data and code managed by this
1845	* component. This function will be called at init and
1846	* whenever the VMM need to relocate it self inside the GC.
1847	*
1848	* @param pVM The VM.
1849	* @param offDelta Relocation delta relative to old location.
1850	*/
1851	VMMR3DECL(void) PGMR3Relocate(PVM pVM, RTGCINTPTR offDelta)
1852	{
1853	LogFlow(("PGMR3Relocate\n"));
1854
1855	/*
1856	* Paging stuff.
1857	*/
1858	pVM->pgm.s.GCPtrCR3Mapping += offDelta;
1859	/** @todo move this into shadow and guest specific relocation functions. */
1860	AssertMsg(pVM->pgm.s.pGC32BitPD, ("Init order, no relocation before paging is initialized!\n"));
1861	pVM->pgm.s.pGC32BitPD += offDelta;
1862	pVM->pgm.s.pGuestPDGC += offDelta;
1863	AssertCompile(RT_ELEMENTS(pVM->pgm.s.apGCPaePDs) == RT_ELEMENTS(pVM->pgm.s.apGstPaePDsGC));
1864	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.apGCPaePDs); i++)
1865	{
1866	pVM->pgm.s.apGCPaePDs[i] += offDelta;
1867	pVM->pgm.s.apGstPaePDsGC[i] += offDelta;
1868	}
1869	pVM->pgm.s.pGstPaePDPTGC += offDelta;
1870	pVM->pgm.s.pGCPaePDPT += offDelta;
1871
1872	pgmR3ModeDataInit(pVM, true /* resolve GC/R0 symbols */);
1873	pgmR3ModeDataSwitch(pVM, pVM->pgm.s.enmShadowMode, pVM->pgm.s.enmGuestMode);
1874
1875	PGM_SHW_PFN(Relocate, pVM)(pVM, offDelta);
1876	PGM_GST_PFN(Relocate, pVM)(pVM, offDelta);
1877	PGM_BTH_PFN(Relocate, pVM)(pVM, offDelta);
1878
1879	/*
1880	* Trees.
1881	*/
1882	pVM->pgm.s.pTreesRC = MMHyperR3ToRC(pVM, pVM->pgm.s.pTreesR3);
1883
1884	/*
1885	* Ram ranges.
1886	*/
1887	if (pVM->pgm.s.pRamRangesR3)
1888	{
1889	pVM->pgm.s.pRamRangesRC = MMHyperR3ToRC(pVM, pVM->pgm.s.pRamRangesR3);
1890	for (PPGMRAMRANGE pCur = pVM->pgm.s.pRamRangesR3; pCur->pNextR3; pCur = pCur->pNextR3)
1891	pCur->pNextRC = MMHyperR3ToRC(pVM, pCur->pNextR3);
1892	}
1893
1894	/*
1895	* Update the two page directories with all page table mappings.
1896	* (One or more of them have changed, that's why we're here.)
1897	*/
1898	pVM->pgm.s.pMappingsRC = MMHyperR3ToRC(pVM, pVM->pgm.s.pMappingsR3);
1899	for (PPGMMAPPING pCur = pVM->pgm.s.pMappingsR3; pCur->pNextR3; pCur = pCur->pNextR3)
1900	pCur->pNextRC = MMHyperR3ToRC(pVM, pCur->pNextR3);
1901
1902	/* Relocate GC addresses of Page Tables. */
1903	for (PPGMMAPPING pCur = pVM->pgm.s.pMappingsR3; pCur; pCur = pCur->pNextR3)
1904	{
1905	for (RTHCUINT i = 0; i < pCur->cPTs; i++)
1906	{
1907	pCur->aPTs[i].pPTRC = MMHyperR3ToRC(pVM, pCur->aPTs[i].pPTR3);
1908	pCur->aPTs[i].paPaePTsRC = MMHyperR3ToRC(pVM, pCur->aPTs[i].paPaePTsR3);
1909	}
1910	}
1911
1912	/*
1913	* Dynamic page mapping area.
1914	*/
1915	pVM->pgm.s.paDynPageMap32BitPTEsGC += offDelta;
1916	pVM->pgm.s.paDynPageMapPaePTEsGC += offDelta;
1917	pVM->pgm.s.pbDynPageMapBaseGC += offDelta;
1918
1919	/*
1920	* The Zero page.
1921	*/
1922	pVM->pgm.s.pvZeroPgR0 = MMHyperR3ToR0(pVM, pVM->pgm.s.pvZeroPgR3);
1923	AssertRelease(pVM->pgm.s.pvZeroPgR0);
1924
1925	/*
1926	* Physical and virtual handlers.
1927	*/
1928	RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysHandlers, true, pgmR3RelocatePhysHandler, &offDelta);
1929	RTAvlroGCPtrDoWithAll(&pVM->pgm.s.pTreesR3->VirtHandlers, true, pgmR3RelocateVirtHandler, &offDelta);
1930	RTAvlroGCPtrDoWithAll(&pVM->pgm.s.pTreesR3->HyperVirtHandlers, true, pgmR3RelocateHyperVirtHandler, &offDelta);
1931
1932	/*
1933	* The page pool.
1934	*/
1935	pgmR3PoolRelocate(pVM);
1936	}
1937
1938
1939	/**
1940	* Callback function for relocating a physical access handler.
1941	*
1942	* @returns 0 (continue enum)
1943	* @param pNode Pointer to a PGMPHYSHANDLER node.
1944	* @param pvUser Pointer to the offDelta. This is a pointer to the delta since we're
1945	* not certain the delta will fit in a void pointer for all possible configs.
1946	*/
1947	static DECLCALLBACK(int) pgmR3RelocatePhysHandler(PAVLROGCPHYSNODECORE pNode, void *pvUser)
1948	{
1949	PPGMPHYSHANDLER pHandler = (PPGMPHYSHANDLER)pNode;
1950	RTGCINTPTR offDelta = *(PRTGCINTPTR)pvUser;
1951	if (pHandler->pfnHandlerRC)
1952	pHandler->pfnHandlerRC += offDelta;
1953	if (pHandler->pvUserRC >= 0x10000)
1954	pHandler->pvUserRC += offDelta;
1955	return 0;
1956	}
1957
1958
1959	/**
1960	* Callback function for relocating a virtual access handler.
1961	*
1962	* @returns 0 (continue enum)
1963	* @param pNode Pointer to a PGMVIRTHANDLER node.
1964	* @param pvUser Pointer to the offDelta. This is a pointer to the delta since we're
1965	* not certain the delta will fit in a void pointer for all possible configs.
1966	*/
1967	static DECLCALLBACK(int) pgmR3RelocateVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser)
1968	{
1969	PPGMVIRTHANDLER pHandler = (PPGMVIRTHANDLER)pNode;
1970	RTGCINTPTR offDelta = *(PRTGCINTPTR)pvUser;
1971	Assert( pHandler->enmType == PGMVIRTHANDLERTYPE_ALL
1972	\|\| pHandler->enmType == PGMVIRTHANDLERTYPE_WRITE);
1973	Assert(pHandler->pfnHandlerRC);
1974	pHandler->pfnHandlerRC += offDelta;
1975	return 0;
1976	}
1977
1978
1979	/**
1980	* Callback function for relocating a virtual access handler for the hypervisor mapping.
1981	*
1982	* @returns 0 (continue enum)
1983	* @param pNode Pointer to a PGMVIRTHANDLER node.
1984	* @param pvUser Pointer to the offDelta. This is a pointer to the delta since we're
1985	* not certain the delta will fit in a void pointer for all possible configs.
1986	*/
1987	static DECLCALLBACK(int) pgmR3RelocateHyperVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser)
1988	{
1989	PPGMVIRTHANDLER pHandler = (PPGMVIRTHANDLER)pNode;
1990	RTGCINTPTR offDelta = *(PRTGCINTPTR)pvUser;
1991	Assert(pHandler->enmType == PGMVIRTHANDLERTYPE_HYPERVISOR);
1992	Assert(pHandler->pfnHandlerRC);
1993	pHandler->pfnHandlerRC += offDelta;
1994	return 0;
1995	}
1996
1997
1998	/**
1999	* The VM is being reset.
2000	*
2001	* For the PGM component this means that any PD write monitors
2002	* needs to be removed.
2003	*
2004	* @param pVM VM handle.
2005	*/
2006	VMMR3DECL(void) PGMR3Reset(PVM pVM)
2007	{
2008	LogFlow(("PGMR3Reset:\n"));
2009	VM_ASSERT_EMT(pVM);
2010
2011	pgmLock(pVM);
2012
2013	/*
2014	* Unfix any fixed mappings and disable CR3 monitoring.
2015	*/
2016	pVM->pgm.s.fMappingsFixed = false;
2017	pVM->pgm.s.GCPtrMappingFixed = 0;
2018	pVM->pgm.s.cbMappingFixed = 0;
2019
2020	/* Exit the guest paging mode before the pgm pool gets reset.
2021	* Important to clean up the amd64 case.
2022	*/
2023	int rc = PGM_GST_PFN(Exit, pVM)(pVM);
2024	AssertRC(rc);
2025	#ifdef DEBUG
2026	DBGFR3InfoLog(pVM, "mappings", NULL);
2027	DBGFR3InfoLog(pVM, "handlers", "all nostat");
2028	#endif
2029
2030	/*
2031	* Reset the shadow page pool.
2032	*/
2033	pgmR3PoolReset(pVM);
2034
2035	/*
2036	* Re-init other members.
2037	*/
2038	pVM->pgm.s.fA20Enabled = true;
2039
2040	/*
2041	* Clear the FFs PGM owns.
2042	*/
2043	VM_FF_CLEAR(pVM, VM_FF_PGM_SYNC_CR3);
2044	VM_FF_CLEAR(pVM, VM_FF_PGM_SYNC_CR3_NON_GLOBAL);
2045
2046	/*
2047	* Reset (zero) RAM pages.
2048	*/
2049	rc = pgmR3PhysRamReset(pVM);
2050	if (RT_SUCCESS(rc))
2051	{
2052	#ifdef VBOX_WITH_NEW_PHYS_CODE
2053	/*
2054	* Reset (zero) shadow ROM pages.
2055	*/
2056	rc = pgmR3PhysRomReset(pVM);
2057	#endif
2058	if (RT_SUCCESS(rc))
2059	{
2060	/*
2061	* Switch mode back to real mode.
2062	*/
2063	rc = PGMR3ChangeMode(pVM, PGMMODE_REAL);
2064	STAM_REL_COUNTER_RESET(&pVM->pgm.s.cGuestModeChanges);
2065	}
2066	}
2067
2068	pgmUnlock(pVM);
2069	//return rc;
2070	AssertReleaseRC(rc);
2071	}
2072
2073
2074	#ifdef VBOX_STRICT
2075	/**
2076	* VM state change callback for clearing fNoMorePhysWrites after
2077	* a snapshot has been created.
2078	*/
2079	static DECLCALLBACK(void) pgmR3ResetNoMorePhysWritesFlag(PVM pVM, VMSTATE enmState, VMSTATE enmOldState, void *pvUser)
2080	{
2081	if (enmState == VMSTATE_RUNNING)
2082	pVM->pgm.s.fNoMorePhysWrites = false;
2083	}
2084	#endif
2085
2086
2087	/**
2088	* Terminates the PGM.
2089	*
2090	* @returns VBox status code.
2091	* @param pVM Pointer to VM structure.
2092	*/
2093	VMMR3DECL(int) PGMR3Term(PVM pVM)
2094	{
2095	return PDMR3CritSectDelete(&pVM->pgm.s.CritSect);
2096	}
2097
2098
2099	/**
2100	* Execute state save operation.
2101	*
2102	* @returns VBox status code.
2103	* @param pVM VM Handle.
2104	* @param pSSM SSM operation handle.
2105	*/
2106	static DECLCALLBACK(int) pgmR3Save(PVM pVM, PSSMHANDLE pSSM)
2107	{
2108	PPGM pPGM = &pVM->pgm.s;
2109
2110	/* No more writes to physical memory after this point! */
2111	pVM->pgm.s.fNoMorePhysWrites = true;
2112
2113	/*
2114	* Save basic data (required / unaffected by relocation).
2115	*/
2116	#if 1
2117	SSMR3PutBool(pSSM, pPGM->fMappingsFixed);
2118	#else
2119	SSMR3PutUInt(pSSM, pPGM->fMappingsFixed);
2120	#endif
2121	SSMR3PutGCPtr(pSSM, pPGM->GCPtrMappingFixed);
2122	SSMR3PutU32(pSSM, pPGM->cbMappingFixed);
2123	SSMR3PutUInt(pSSM, pPGM->cbRamSize);
2124	SSMR3PutGCPhys(pSSM, pPGM->GCPhysA20Mask);
2125	SSMR3PutUInt(pSSM, pPGM->fA20Enabled);
2126	SSMR3PutUInt(pSSM, pPGM->fSyncFlags);
2127	SSMR3PutUInt(pSSM, pPGM->enmGuestMode);
2128	SSMR3PutU32(pSSM, ~0); /* Separator. */
2129
2130	/*
2131	* The guest mappings.
2132	*/
2133	uint32_t i = 0;
2134	for (PPGMMAPPING pMapping = pPGM->pMappingsR3; pMapping; pMapping = pMapping->pNextR3, i++)
2135	{
2136	SSMR3PutU32(pSSM, i);
2137	SSMR3PutStrZ(pSSM, pMapping->pszDesc); /* This is the best unique id we have... */
2138	SSMR3PutGCPtr(pSSM, pMapping->GCPtr);
2139	SSMR3PutGCUIntPtr(pSSM, pMapping->cPTs);
2140	/* flags are done by the mapping owners! */
2141	}
2142	SSMR3PutU32(pSSM, ~0); /* terminator. */
2143
2144	/*
2145	* Ram range flags and bits.
2146	*/
2147	i = 0;
2148	for (PPGMRAMRANGE pRam = pPGM->pRamRangesR3; pRam; pRam = pRam->pNextR3, i++)
2149	{
2150	/** @todo MMIO ranges may move (PCI reconfig), we currently assume they don't. */
2151
2152	SSMR3PutU32(pSSM, i);
2153	SSMR3PutGCPhys(pSSM, pRam->GCPhys);
2154	SSMR3PutGCPhys(pSSM, pRam->GCPhysLast);
2155	SSMR3PutGCPhys(pSSM, pRam->cb);
2156	SSMR3PutU8(pSSM, !!pRam->pvR3); /* boolean indicating memory or not. */
2157
2158	/* Flags. */
2159	const unsigned cPages = pRam->cb >> PAGE_SHIFT;
2160	for (unsigned iPage = 0; iPage < cPages; iPage++)
2161	SSMR3PutU16(pSSM, (uint16_t)(pRam->aPages[iPage].HCPhys & ~X86_PTE_PAE_PG_MASK)); /** @todo PAGE FLAGS */
2162
2163	/* any memory associated with the range. */
2164	if (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)
2165	{
2166	for (unsigned iChunk = 0; iChunk < (pRam->cb >> PGM_DYNAMIC_CHUNK_SHIFT); iChunk++)
2167	{
2168	if (pRam->paChunkR3Ptrs[iChunk])
2169	{
2170	SSMR3PutU8(pSSM, 1); /* chunk present */
2171	SSMR3PutMem(pSSM, (void *)pRam->paChunkR3Ptrs[iChunk], PGM_DYNAMIC_CHUNK_SIZE);
2172	}
2173	else
2174	SSMR3PutU8(pSSM, 0); /* no chunk present */
2175	}
2176	}
2177	else if (pRam->pvR3)
2178	{
2179	int rc = SSMR3PutMem(pSSM, pRam->pvR3, pRam->cb);
2180	if (VBOX_FAILURE(rc))
2181	{
2182	Log(("pgmR3Save: SSMR3PutMem(, %p, %#x) -> %Vrc\n", pRam->pvR3, pRam->cb, rc));
2183	return rc;
2184	}
2185	}
2186	}
2187	return SSMR3PutU32(pSSM, ~0); /* terminator. */
2188	}
2189
2190
2191	/**
2192	* Execute state load operation.
2193	*
2194	* @returns VBox status code.
2195	* @param pVM VM Handle.
2196	* @param pSSM SSM operation handle.
2197	* @param u32Version Data layout version.
2198	*/
2199	static DECLCALLBACK(int) pgmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version)
2200	{
2201	/*
2202	* Validate version.
2203	*/
2204	if (u32Version != PGM_SAVED_STATE_VERSION)
2205	{
2206	AssertMsgFailed(("pgmR3Load: Invalid version u32Version=%d (current %d)!\n", u32Version, PGM_SAVED_STATE_VERSION));
2207	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
2208	}
2209
2210	/*
2211	* Call the reset function to make sure all the memory is cleared.
2212	*/
2213	PGMR3Reset(pVM);
2214
2215	/*
2216	* Load basic data (required / unaffected by relocation).
2217	*/
2218	PPGM pPGM = &pVM->pgm.s;
2219	#if 1
2220	SSMR3GetBool(pSSM, &pPGM->fMappingsFixed);
2221	#else
2222	uint32_t u;
2223	SSMR3GetU32(pSSM, &u);
2224	pPGM->fMappingsFixed = u;
2225	#endif
2226	SSMR3GetGCPtr(pSSM, &pPGM->GCPtrMappingFixed);
2227	SSMR3GetU32(pSSM, &pPGM->cbMappingFixed);
2228
2229	RTUINT cbRamSize;
2230	int rc = SSMR3GetU32(pSSM, &cbRamSize);
2231	if (VBOX_FAILURE(rc))
2232	return rc;
2233	if (cbRamSize != pPGM->cbRamSize)
2234	return VERR_SSM_LOAD_MEMORY_SIZE_MISMATCH;
2235	SSMR3GetGCPhys(pSSM, &pPGM->GCPhysA20Mask);
2236	SSMR3GetUInt(pSSM, &pPGM->fA20Enabled);
2237	SSMR3GetUInt(pSSM, &pPGM->fSyncFlags);
2238	RTUINT uGuestMode;
2239	SSMR3GetUInt(pSSM, &uGuestMode);
2240	pPGM->enmGuestMode = (PGMMODE)uGuestMode;
2241
2242	/* check separator. */
2243	uint32_t u32Sep;
2244	SSMR3GetU32(pSSM, &u32Sep);
2245	if (VBOX_FAILURE(rc))
2246	return rc;
2247	if (u32Sep != (uint32_t)~0)
2248	{
2249	AssertMsgFailed(("u32Sep=%#x (first)\n", u32Sep));
2250	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2251	}
2252
2253	/*
2254	* The guest mappings.
2255	*/
2256	uint32_t i = 0;
2257	for (;; i++)
2258	{
2259	/* Check the seqence number / separator. */
2260	rc = SSMR3GetU32(pSSM, &u32Sep);
2261	if (VBOX_FAILURE(rc))
2262	return rc;
2263	if (u32Sep == ~0U)
2264	break;
2265	if (u32Sep != i)
2266	{
2267	AssertMsgFailed(("u32Sep=%#x (last)\n", u32Sep));
2268	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2269	}
2270
2271	/* get the mapping details. */
2272	char szDesc[256];
2273	szDesc[0] = '\0';
2274	rc = SSMR3GetStrZ(pSSM, szDesc, sizeof(szDesc));
2275	if (VBOX_FAILURE(rc))
2276	return rc;
2277	RTGCPTR GCPtr;
2278	SSMR3GetGCPtr(pSSM, &GCPtr);
2279	RTGCUINTPTR cPTs;
2280	rc = SSMR3GetGCUIntPtr(pSSM, &cPTs);
2281	if (VBOX_FAILURE(rc))
2282	return rc;
2283
2284	/* find matching range. */
2285	PPGMMAPPING pMapping;
2286	for (pMapping = pPGM->pMappingsR3; pMapping; pMapping = pMapping->pNextR3)
2287	if ( pMapping->cPTs == cPTs
2288	&& !strcmp(pMapping->pszDesc, szDesc))
2289	break;
2290	if (!pMapping)
2291	{
2292	LogRel(("Couldn't find mapping: cPTs=%#x szDesc=%s (GCPtr=%VGv)\n",
2293	cPTs, szDesc, GCPtr));
2294	AssertFailed();
2295	return VERR_SSM_LOAD_CONFIG_MISMATCH;
2296	}
2297
2298	/* relocate it. */
2299	if (pMapping->GCPtr != GCPtr)
2300	{
2301	AssertMsg((GCPtr >> X86_PD_SHIFT << X86_PD_SHIFT) == GCPtr, ("GCPtr=%VGv\n", GCPtr));
2302	#if HC_ARCH_BITS == 64
2303	LogRel(("Mapping: %VGv -> %VGv %s\n", pMapping->GCPtr, GCPtr, pMapping->pszDesc));
2304	#endif
2305	pgmR3MapRelocate(pVM, pMapping, pMapping->GCPtr, GCPtr);
2306	}
2307	else
2308	Log(("pgmR3Load: '%s' needed no relocation (%VGv)\n", szDesc, GCPtr));
2309	}
2310
2311	/*
2312	* Ram range flags and bits.
2313	*/
2314	i = 0;
2315	for (PPGMRAMRANGE pRam = pPGM->pRamRangesR3; pRam; pRam = pRam->pNextR3, i++)
2316	{
2317	/** @todo MMIO ranges may move (PCI reconfig), we currently assume they don't. */
2318	/* Check the seqence number / separator. */
2319	rc = SSMR3GetU32(pSSM, &u32Sep);
2320	if (VBOX_FAILURE(rc))
2321	return rc;
2322	if (u32Sep == ~0U)
2323	break;
2324	if (u32Sep != i)
2325	{
2326	AssertMsgFailed(("u32Sep=%#x (last)\n", u32Sep));
2327	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2328	}
2329
2330	/* Get the range details. */
2331	RTGCPHYS GCPhys;
2332	SSMR3GetGCPhys(pSSM, &GCPhys);
2333	RTGCPHYS GCPhysLast;
2334	SSMR3GetGCPhys(pSSM, &GCPhysLast);
2335	RTGCPHYS cb;
2336	SSMR3GetGCPhys(pSSM, &cb);
2337	uint8_t fHaveBits;
2338	rc = SSMR3GetU8(pSSM, &fHaveBits);
2339	if (VBOX_FAILURE(rc))
2340	return rc;
2341	if (fHaveBits & ~1)
2342	{
2343	AssertMsgFailed(("u32Sep=%#x (last)\n", u32Sep));
2344	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2345	}
2346
2347	/* Match it up with the current range. */
2348	if ( GCPhys != pRam->GCPhys
2349	\|\| GCPhysLast != pRam->GCPhysLast
2350	\|\| cb != pRam->cb
2351	\|\| fHaveBits != !!pRam->pvR3)
2352	{
2353	LogRel(("Ram range: %RGp-%RGp %RGp bytes %s\n"
2354	"State : %RGp-%RGp %RGp bytes %s\n",
2355	pRam->GCPhys, pRam->GCPhysLast, pRam->cb, pRam->pvR3 ? "bits" : "nobits",
2356	GCPhys, GCPhysLast, cb, fHaveBits ? "bits" : "nobits"));
2357	/*
2358	* If we're loading a state for debugging purpose, don't make a fuss if
2359	* the MMIO[2] and ROM stuff isn't 100% right, just skip the mismatches.
2360	*/
2361	if ( SSMR3HandleGetAfter(pSSM) != SSMAFTER_DEBUG_IT
2362	\|\| GCPhys < 8 * _1M)
2363	AssertFailedReturn(VERR_SSM_LOAD_CONFIG_MISMATCH);
2364
2365	RTGCPHYS cPages = ((GCPhysLast - GCPhys) + 1) >> PAGE_SHIFT;
2366	while (cPages-- > 0)
2367	{
2368	uint16_t u16Ignore;
2369	SSMR3GetU16(pSSM, &u16Ignore);
2370	}
2371	continue;
2372	}
2373
2374	/* Flags. */
2375	const unsigned cPages = pRam->cb >> PAGE_SHIFT;
2376	for (unsigned iPage = 0; iPage < cPages; iPage++)
2377	{
2378	uint16_t u16 = 0;
2379	SSMR3GetU16(pSSM, &u16);
2380	u16 &= PAGE_OFFSET_MASK & ~( RT_BIT(4) \| RT_BIT(5) \| RT_BIT(6)
2381	\| RT_BIT(7) \| RT_BIT(8) \| RT_BIT(9) \| RT_BIT(10) );
2382	// &= MM_RAM_FLAGS_DYNAMIC_ALLOC \| MM_RAM_FLAGS_RESERVED \| MM_RAM_FLAGS_ROM \| MM_RAM_FLAGS_MMIO \| MM_RAM_FLAGS_MMIO2
2383	pRam->aPages[iPage].HCPhys = PGM_PAGE_GET_HCPHYS(&pRam->aPages[iPage]) \| (RTHCPHYS)u16; /** @todo PAGE FLAGS */
2384	}
2385
2386	/* any memory associated with the range. */
2387	if (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)
2388	{
2389	for (unsigned iChunk = 0; iChunk < (pRam->cb >> PGM_DYNAMIC_CHUNK_SHIFT); iChunk++)
2390	{
2391	uint8_t fValidChunk;
2392
2393	rc = SSMR3GetU8(pSSM, &fValidChunk);
2394	if (VBOX_FAILURE(rc))
2395	return rc;
2396	if (fValidChunk > 1)
2397	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2398
2399	if (fValidChunk)
2400	{
2401	if (!pRam->paChunkR3Ptrs[iChunk])
2402	{
2403	rc = pgmr3PhysGrowRange(pVM, pRam->GCPhys + iChunk * PGM_DYNAMIC_CHUNK_SIZE);
2404	if (VBOX_FAILURE(rc))
2405	return rc;
2406	}
2407	Assert(pRam->paChunkR3Ptrs[iChunk]);
2408
2409	SSMR3GetMem(pSSM, (void *)pRam->paChunkR3Ptrs[iChunk], PGM_DYNAMIC_CHUNK_SIZE);
2410	}
2411	/* else nothing to do */
2412	}
2413	}
2414	else if (pRam->pvR3)
2415	{
2416	int rc = SSMR3GetMem(pSSM, pRam->pvR3, pRam->cb);
2417	if (VBOX_FAILURE(rc))
2418	{
2419	Log(("pgmR3Save: SSMR3GetMem(, %p, %#x) -> %Vrc\n", pRam->pvR3, pRam->cb, rc));
2420	return rc;
2421	}
2422	}
2423	}
2424
2425	/*
2426	* We require a full resync now.
2427	*/
2428	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3_NON_GLOBAL);
2429	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
2430	pPGM->fSyncFlags \|= PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL;
2431	pPGM->fPhysCacheFlushPending = true;
2432	pgmR3HandlerPhysicalUpdateAll(pVM);
2433
2434	/*
2435	* Change the paging mode.
2436	*/
2437	rc = PGMR3ChangeMode(pVM, pPGM->enmGuestMode);
2438
2439	/* Restore pVM->pgm.s.GCPhysCR3. */
2440	Assert(pVM->pgm.s.GCPhysCR3 == NIL_RTGCPHYS);
2441	RTGCPHYS GCPhysCR3 = CPUMGetGuestCR3(pVM);
2442	if ( pVM->pgm.s.enmGuestMode == PGMMODE_PAE
2443	\|\| pVM->pgm.s.enmGuestMode == PGMMODE_PAE_NX
2444	\|\| pVM->pgm.s.enmGuestMode == PGMMODE_AMD64
2445	\|\| pVM->pgm.s.enmGuestMode == PGMMODE_AMD64_NX)
2446	GCPhysCR3 = (GCPhysCR3 & X86_CR3_PAE_PAGE_MASK);
2447	else
2448	GCPhysCR3 = (GCPhysCR3 & X86_CR3_PAGE_MASK);
2449	pVM->pgm.s.GCPhysCR3 = GCPhysCR3;
2450
2451	return rc;
2452	}
2453
2454
2455	/**
2456	* Show paging mode.
2457	*
2458	* @param pVM VM Handle.
2459	* @param pHlp The info helpers.
2460	* @param pszArgs "all" (default), "guest", "shadow" or "host".
2461	*/
2462	static DECLCALLBACK(void) pgmR3InfoMode(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2463	{
2464	/* digest argument. */
2465	bool fGuest, fShadow, fHost;
2466	if (pszArgs)
2467	pszArgs = RTStrStripL(pszArgs);
2468	if (!pszArgs \|\| !*pszArgs \|\| strstr(pszArgs, "all"))
2469	fShadow = fHost = fGuest = true;
2470	else
2471	{
2472	fShadow = fHost = fGuest = false;
2473	if (strstr(pszArgs, "guest"))
2474	fGuest = true;
2475	if (strstr(pszArgs, "shadow"))
2476	fShadow = true;
2477	if (strstr(pszArgs, "host"))
2478	fHost = true;
2479	}
2480
2481	/* print info. */
2482	if (fGuest)
2483	pHlp->pfnPrintf(pHlp, "Guest paging mode: %s, changed %RU64 times, A20 %s\n",
2484	PGMGetModeName(pVM->pgm.s.enmGuestMode), pVM->pgm.s.cGuestModeChanges.c,
2485	pVM->pgm.s.fA20Enabled ? "enabled" : "disabled");
2486	if (fShadow)
2487	pHlp->pfnPrintf(pHlp, "Shadow paging mode: %s\n", PGMGetModeName(pVM->pgm.s.enmShadowMode));
2488	if (fHost)
2489	{
2490	const char *psz;
2491	switch (pVM->pgm.s.enmHostMode)
2492	{
2493	case SUPPAGINGMODE_INVALID: psz = "invalid"; break;
2494	case SUPPAGINGMODE_32_BIT: psz = "32-bit"; break;
2495	case SUPPAGINGMODE_32_BIT_GLOBAL: psz = "32-bit+G"; break;
2496	case SUPPAGINGMODE_PAE: psz = "PAE"; break;
2497	case SUPPAGINGMODE_PAE_GLOBAL: psz = "PAE+G"; break;
2498	case SUPPAGINGMODE_PAE_NX: psz = "PAE+NX"; break;
2499	case SUPPAGINGMODE_PAE_GLOBAL_NX: psz = "PAE+G+NX"; break;
2500	case SUPPAGINGMODE_AMD64: psz = "AMD64"; break;
2501	case SUPPAGINGMODE_AMD64_GLOBAL: psz = "AMD64+G"; break;
2502	case SUPPAGINGMODE_AMD64_NX: psz = "AMD64+NX"; break;
2503	case SUPPAGINGMODE_AMD64_GLOBAL_NX: psz = "AMD64+G+NX"; break;
2504	default: psz = "unknown"; break;
2505	}
2506	pHlp->pfnPrintf(pHlp, "Host paging mode: %s\n", psz);
2507	}
2508	}
2509
2510
2511	/**
2512	* Dump registered MMIO ranges to the log.
2513	*
2514	* @param pVM VM Handle.
2515	* @param pHlp The info helpers.
2516	* @param pszArgs Arguments, ignored.
2517	*/
2518	static DECLCALLBACK(void) pgmR3PhysInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2519	{
2520	NOREF(pszArgs);
2521	pHlp->pfnPrintf(pHlp,
2522	"RAM ranges (pVM=%p)\n"
2523	"%.s %.s\n",
2524	pVM,
2525	sizeof(RTGCPHYS) * 4 + 1, "GC Phys Range ",
2526	sizeof(RTHCPTR) * 2, "pvHC ");
2527
2528	for (PPGMRAMRANGE pCur = pVM->pgm.s.pRamRangesR3; pCur; pCur = pCur->pNextR3)
2529	pHlp->pfnPrintf(pHlp,
2530	"%RGp-%RGp %RHv %s\n",
2531	pCur->GCPhys,
2532	pCur->GCPhysLast,
2533	pCur->pvR3,
2534	pCur->pszDesc);
2535	}
2536
2537	/**
2538	* Dump the page directory to the log.
2539	*
2540	* @param pVM VM Handle.
2541	* @param pHlp The info helpers.
2542	* @param pszArgs Arguments, ignored.
2543	*/
2544	static DECLCALLBACK(void) pgmR3InfoCr3(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2545	{
2546	/** @todo fix this! Convert the PGMR3DumpHierarchyHC functions to do guest stuff. */
2547	/* Big pages supported? */
2548	const bool fPSE = !!(CPUMGetGuestCR4(pVM) & X86_CR4_PSE);
2549
2550	/* Global pages supported? */
2551	const bool fPGE = !!(CPUMGetGuestCR4(pVM) & X86_CR4_PGE);
2552
2553	NOREF(pszArgs);
2554
2555	/*
2556	* Get page directory addresses.
2557	*/
2558	PX86PD pPDSrc = pVM->pgm.s.pGuestPDHC;
2559	Assert(pPDSrc);
2560	Assert(PGMPhysGCPhys2HCPtrAssert(pVM, (RTGCPHYS)(CPUMGetGuestCR3(pVM) & X86_CR3_PAGE_MASK), sizeof(*pPDSrc)) == pPDSrc);
2561
2562	/*
2563	* Iterate the page directory.
2564	*/
2565	for (unsigned iPD = 0; iPD < RT_ELEMENTS(pPDSrc->a); iPD++)
2566	{
2567	X86PDE PdeSrc = pPDSrc->a[iPD];
2568	if (PdeSrc.n.u1Present)
2569	{
2570	if (PdeSrc.b.u1Size && fPSE)
2571	{
2572	pHlp->pfnPrintf(pHlp,
2573	"%04X - %VGp P=%d U=%d RW=%d G=%d - BIG\n",
2574	iPD,
2575	pgmGstGet4MBPhysPage(&pVM->pgm.s, PdeSrc),
2576	PdeSrc.b.u1Present, PdeSrc.b.u1User, PdeSrc.b.u1Write, PdeSrc.b.u1Global && fPGE);
2577	}
2578	else
2579	{
2580	pHlp->pfnPrintf(pHlp,
2581	"%04X - %VGp P=%d U=%d RW=%d [G=%d]\n",
2582	iPD,
2583	PdeSrc.u & X86_PDE_PG_MASK,
2584	PdeSrc.n.u1Present, PdeSrc.n.u1User, PdeSrc.n.u1Write, PdeSrc.b.u1Global && fPGE);
2585	}
2586	}
2587	}
2588	}
2589
2590
2591	/**
2592	* Serivce a VMMCALLHOST_PGM_LOCK call.
2593	*
2594	* @returns VBox status code.
2595	* @param pVM The VM handle.
2596	*/
2597	VMMR3DECL(int) PGMR3LockCall(PVM pVM)
2598	{
2599	int rc = PDMR3CritSectEnterEx(&pVM->pgm.s.CritSect, true /* fHostCall */);
2600	AssertRC(rc);
2601	return rc;
2602	}
2603
2604
2605	/**
2606	* Converts a PGMMODE value to a PGM_TYPE_* \#define.
2607	*
2608	* @returns PGM_TYPE_*.
2609	* @param pgmMode The mode value to convert.
2610	*/
2611	DECLINLINE(unsigned) pgmModeToType(PGMMODE pgmMode)
2612	{
2613	switch (pgmMode)
2614	{
2615	case PGMMODE_REAL: return PGM_TYPE_REAL;
2616	case PGMMODE_PROTECTED: return PGM_TYPE_PROT;
2617	case PGMMODE_32_BIT: return PGM_TYPE_32BIT;
2618	case PGMMODE_PAE:
2619	case PGMMODE_PAE_NX: return PGM_TYPE_PAE;
2620	case PGMMODE_AMD64:
2621	case PGMMODE_AMD64_NX: return PGM_TYPE_AMD64;
2622	case PGMMODE_NESTED: return PGM_TYPE_NESTED;
2623	case PGMMODE_EPT: return PGM_TYPE_EPT;
2624	default:
2625	AssertFatalMsgFailed(("pgmMode=%d\n", pgmMode));
2626	}
2627	}
2628
2629
2630	/**
2631	* Gets the index into the paging mode data array of a SHW+GST mode.
2632	*
2633	* @returns PGM::paPagingData index.
2634	* @param uShwType The shadow paging mode type.
2635	* @param uGstType The guest paging mode type.
2636	*/
2637	DECLINLINE(unsigned) pgmModeDataIndex(unsigned uShwType, unsigned uGstType)
2638	{
2639	Assert(uShwType >= PGM_TYPE_32BIT && uShwType <= PGM_TYPE_MAX);
2640	Assert(uGstType >= PGM_TYPE_REAL && uGstType <= PGM_TYPE_AMD64);
2641	return (uShwType - PGM_TYPE_32BIT) * (PGM_TYPE_AMD64 - PGM_TYPE_REAL + 1)
2642	+ (uGstType - PGM_TYPE_REAL);
2643	}
2644
2645
2646	/**
2647	* Gets the index into the paging mode data array of a SHW+GST mode.
2648	*
2649	* @returns PGM::paPagingData index.
2650	* @param enmShw The shadow paging mode.
2651	* @param enmGst The guest paging mode.
2652	*/
2653	DECLINLINE(unsigned) pgmModeDataIndexByMode(PGMMODE enmShw, PGMMODE enmGst)
2654	{
2655	Assert(enmShw >= PGMMODE_32_BIT && enmShw <= PGMMODE_MAX);
2656	Assert(enmGst > PGMMODE_INVALID && enmGst < PGMMODE_MAX);
2657	return pgmModeDataIndex(pgmModeToType(enmShw), pgmModeToType(enmGst));
2658	}
2659
2660
2661	/**
2662	* Calculates the max data index.
2663	* @returns The number of entries in the paging data array.
2664	*/
2665	DECLINLINE(unsigned) pgmModeDataMaxIndex(void)
2666	{
2667	return pgmModeDataIndex(PGM_TYPE_MAX, PGM_TYPE_AMD64) + 1;
2668	}
2669
2670
2671	/**
2672	* Initializes the paging mode data kept in PGM::paModeData.
2673	*
2674	* @param pVM The VM handle.
2675	* @param fResolveGCAndR0 Indicate whether or not GC and Ring-0 symbols can be resolved now.
2676	* This is used early in the init process to avoid trouble with PDM
2677	* not being initialized yet.
2678	*/
2679	static int pgmR3ModeDataInit(PVM pVM, bool fResolveGCAndR0)
2680	{
2681	PPGMMODEDATA pModeData;
2682	int rc;
2683
2684	/*
2685	* Allocate the array on the first call.
2686	*/
2687	if (!pVM->pgm.s.paModeData)
2688	{
2689	pVM->pgm.s.paModeData = (PPGMMODEDATA)MMR3HeapAllocZ(pVM, MM_TAG_PGM, sizeof(PGMMODEDATA) * pgmModeDataMaxIndex());
2690	AssertReturn(pVM->pgm.s.paModeData, VERR_NO_MEMORY);
2691	}
2692
2693	/*
2694	* Initialize the array entries.
2695	*/
2696	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_32BIT, PGM_TYPE_REAL)];
2697	pModeData->uShwType = PGM_TYPE_32BIT;
2698	pModeData->uGstType = PGM_TYPE_REAL;
2699	rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2700	rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2701	rc = PGM_BTH_NAME_32BIT_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2702
2703	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_32BIT, PGMMODE_PROTECTED)];
2704	pModeData->uShwType = PGM_TYPE_32BIT;
2705	pModeData->uGstType = PGM_TYPE_PROT;
2706	rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2707	rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2708	rc = PGM_BTH_NAME_32BIT_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2709
2710	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_32BIT, PGM_TYPE_32BIT)];
2711	pModeData->uShwType = PGM_TYPE_32BIT;
2712	pModeData->uGstType = PGM_TYPE_32BIT;
2713	rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2714	rc = PGM_GST_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2715	rc = PGM_BTH_NAME_32BIT_32BIT(InitData)(pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2716
2717	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_REAL)];
2718	pModeData->uShwType = PGM_TYPE_PAE;
2719	pModeData->uGstType = PGM_TYPE_REAL;
2720	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2721	rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2722	rc = PGM_BTH_NAME_PAE_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2723
2724	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_PROT)];
2725	pModeData->uShwType = PGM_TYPE_PAE;
2726	pModeData->uGstType = PGM_TYPE_PROT;
2727	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2728	rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2729	rc = PGM_BTH_NAME_PAE_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2730
2731	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_32BIT)];
2732	pModeData->uShwType = PGM_TYPE_PAE;
2733	pModeData->uGstType = PGM_TYPE_32BIT;
2734	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2735	rc = PGM_GST_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2736	rc = PGM_BTH_NAME_PAE_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2737
2738	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_PAE)];
2739	pModeData->uShwType = PGM_TYPE_PAE;
2740	pModeData->uGstType = PGM_TYPE_PAE;
2741	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2742	rc = PGM_GST_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2743	rc = PGM_BTH_NAME_PAE_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2744
2745	#ifdef VBOX_WITH_64_BITS_GUESTS
2746	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_AMD64, PGM_TYPE_AMD64)];
2747	pModeData->uShwType = PGM_TYPE_AMD64;
2748	pModeData->uGstType = PGM_TYPE_AMD64;
2749	rc = PGM_SHW_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2750	rc = PGM_GST_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2751	rc = PGM_BTH_NAME_AMD64_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2752	#endif
2753
2754	/* The nested paging mode. */
2755	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_REAL)];
2756	pModeData->uShwType = PGM_TYPE_NESTED;
2757	pModeData->uGstType = PGM_TYPE_REAL;
2758	rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2759	rc = PGM_BTH_NAME_NESTED_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2760
2761	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGMMODE_PROTECTED)];
2762	pModeData->uShwType = PGM_TYPE_NESTED;
2763	pModeData->uGstType = PGM_TYPE_PROT;
2764	rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2765	rc = PGM_BTH_NAME_NESTED_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2766
2767	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_32BIT)];
2768	pModeData->uShwType = PGM_TYPE_NESTED;
2769	pModeData->uGstType = PGM_TYPE_32BIT;
2770	rc = PGM_GST_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2771	rc = PGM_BTH_NAME_NESTED_32BIT(InitData)(pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2772
2773	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_PAE)];
2774	pModeData->uShwType = PGM_TYPE_NESTED;
2775	pModeData->uGstType = PGM_TYPE_PAE;
2776	rc = PGM_GST_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2777	rc = PGM_BTH_NAME_NESTED_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2778
2779	#ifdef VBOX_WITH_64_BITS_GUESTS
2780	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_AMD64)];
2781	pModeData->uShwType = PGM_TYPE_NESTED;
2782	pModeData->uGstType = PGM_TYPE_AMD64;
2783	rc = PGM_GST_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2784	rc = PGM_BTH_NAME_NESTED_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2785	#endif
2786
2787	#ifdef VBOX_WITH_64_BITS_GUESTS
2788	# define PGM_TYPE_MAX_SHADOW PGM_TYPE_AMD64
2789	#else
2790	# define PGM_TYPE_MAX_SHADOW PGM_TYPE_PAE
2791	#endif
2792
2793	/* The shadow part of the nested callback mode depends on the host paging mode (AMD-V only). */
2794	switch(pVM->pgm.s.enmHostMode)
2795	{
2796	case SUPPAGINGMODE_32_BIT:
2797	case SUPPAGINGMODE_32_BIT_GLOBAL:
2798	for (unsigned i=PGM_TYPE_REAL;i<=PGM_TYPE_MAX_SHADOW;i++)
2799	{
2800	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, i)];
2801	rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2802	}
2803	break;
2804
2805	case SUPPAGINGMODE_PAE:
2806	case SUPPAGINGMODE_PAE_NX:
2807	case SUPPAGINGMODE_PAE_GLOBAL:
2808	case SUPPAGINGMODE_PAE_GLOBAL_NX:
2809	for (unsigned i=PGM_TYPE_REAL;i<=PGM_TYPE_MAX_SHADOW;i++)
2810	{
2811	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, i)];
2812	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2813	}
2814	break;
2815
2816	case SUPPAGINGMODE_AMD64:
2817	case SUPPAGINGMODE_AMD64_GLOBAL:
2818	case SUPPAGINGMODE_AMD64_NX:
2819	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
2820	for (unsigned i=PGM_TYPE_REAL;i<=PGM_TYPE_MAX_SHADOW;i++)
2821	{
2822	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, i)];
2823	rc = PGM_SHW_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2824	}
2825	break;
2826	default:
2827	AssertFailed();
2828	break;
2829	}
2830
2831	/* Extended paging (EPT) / Intel VT-x */
2832	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_REAL)];
2833	pModeData->uShwType = PGM_TYPE_EPT;
2834	pModeData->uGstType = PGM_TYPE_REAL;
2835	rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2836	rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2837	rc = PGM_BTH_NAME_EPT_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2838
2839	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_PROT)];
2840	pModeData->uShwType = PGM_TYPE_EPT;
2841	pModeData->uGstType = PGM_TYPE_PROT;
2842	rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2843	rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2844	rc = PGM_BTH_NAME_EPT_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2845
2846	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_32BIT)];
2847	pModeData->uShwType = PGM_TYPE_EPT;
2848	pModeData->uGstType = PGM_TYPE_32BIT;
2849	rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2850	rc = PGM_GST_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2851	rc = PGM_BTH_NAME_EPT_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2852
2853	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_PAE)];
2854	pModeData->uShwType = PGM_TYPE_EPT;
2855	pModeData->uGstType = PGM_TYPE_PAE;
2856	rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2857	rc = PGM_GST_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2858	rc = PGM_BTH_NAME_EPT_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2859
2860	#ifdef VBOX_WITH_64_BITS_GUESTS
2861	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_AMD64)];
2862	pModeData->uShwType = PGM_TYPE_EPT;
2863	pModeData->uGstType = PGM_TYPE_AMD64;
2864	rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2865	rc = PGM_GST_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2866	rc = PGM_BTH_NAME_EPT_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2867	#endif
2868	return VINF_SUCCESS;
2869	}
2870
2871
2872	/**
2873	* Switch to different (or relocated in the relocate case) mode data.
2874	*
2875	* @param pVM The VM handle.
2876	* @param enmShw The the shadow paging mode.
2877	* @param enmGst The the guest paging mode.
2878	*/
2879	static void pgmR3ModeDataSwitch(PVM pVM, PGMMODE enmShw, PGMMODE enmGst)
2880	{
2881	PPGMMODEDATA pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndexByMode(enmShw, enmGst)];
2882
2883	Assert(pModeData->uGstType == pgmModeToType(enmGst));
2884	Assert(pModeData->uShwType == pgmModeToType(enmShw));
2885
2886	/* shadow */
2887	pVM->pgm.s.pfnR3ShwRelocate = pModeData->pfnR3ShwRelocate;
2888	pVM->pgm.s.pfnR3ShwExit = pModeData->pfnR3ShwExit;
2889	pVM->pgm.s.pfnR3ShwGetPage = pModeData->pfnR3ShwGetPage;
2890	Assert(pVM->pgm.s.pfnR3ShwGetPage);
2891	pVM->pgm.s.pfnR3ShwModifyPage = pModeData->pfnR3ShwModifyPage;
2892
2893	pVM->pgm.s.pfnRCShwGetPage = pModeData->pfnRCShwGetPage;
2894	pVM->pgm.s.pfnRCShwModifyPage = pModeData->pfnRCShwModifyPage;
2895
2896	pVM->pgm.s.pfnR0ShwGetPage = pModeData->pfnR0ShwGetPage;
2897	pVM->pgm.s.pfnR0ShwModifyPage = pModeData->pfnR0ShwModifyPage;
2898
2899
2900	/* guest */
2901	pVM->pgm.s.pfnR3GstRelocate = pModeData->pfnR3GstRelocate;
2902	pVM->pgm.s.pfnR3GstExit = pModeData->pfnR3GstExit;
2903	pVM->pgm.s.pfnR3GstGetPage = pModeData->pfnR3GstGetPage;
2904	Assert(pVM->pgm.s.pfnR3GstGetPage);
2905	pVM->pgm.s.pfnR3GstModifyPage = pModeData->pfnR3GstModifyPage;
2906	pVM->pgm.s.pfnR3GstGetPDE = pModeData->pfnR3GstGetPDE;
2907	pVM->pgm.s.pfnR3GstMonitorCR3 = pModeData->pfnR3GstMonitorCR3;
2908	pVM->pgm.s.pfnR3GstUnmonitorCR3 = pModeData->pfnR3GstUnmonitorCR3;
2909	pVM->pgm.s.pfnR3GstMapCR3 = pModeData->pfnR3GstMapCR3;
2910	pVM->pgm.s.pfnR3GstUnmapCR3 = pModeData->pfnR3GstUnmapCR3;
2911	pVM->pgm.s.pfnR3GstWriteHandlerCR3 = pModeData->pfnR3GstWriteHandlerCR3;
2912	pVM->pgm.s.pszR3GstWriteHandlerCR3 = pModeData->pszR3GstWriteHandlerCR3;
2913	pVM->pgm.s.pfnR3GstPAEWriteHandlerCR3 = pModeData->pfnR3GstPAEWriteHandlerCR3;
2914	pVM->pgm.s.pszR3GstPAEWriteHandlerCR3 = pModeData->pszR3GstPAEWriteHandlerCR3;
2915
2916	pVM->pgm.s.pfnRCGstGetPage = pModeData->pfnRCGstGetPage;
2917	pVM->pgm.s.pfnRCGstModifyPage = pModeData->pfnRCGstModifyPage;
2918	pVM->pgm.s.pfnRCGstGetPDE = pModeData->pfnRCGstGetPDE;
2919	pVM->pgm.s.pfnRCGstMonitorCR3 = pModeData->pfnRCGstMonitorCR3;
2920	pVM->pgm.s.pfnRCGstUnmonitorCR3 = pModeData->pfnRCGstUnmonitorCR3;
2921	pVM->pgm.s.pfnRCGstMapCR3 = pModeData->pfnRCGstMapCR3;
2922	pVM->pgm.s.pfnRCGstUnmapCR3 = pModeData->pfnRCGstUnmapCR3;
2923	pVM->pgm.s.pfnRCGstWriteHandlerCR3 = pModeData->pfnRCGstWriteHandlerCR3;
2924	pVM->pgm.s.pfnRCGstPAEWriteHandlerCR3 = pModeData->pfnRCGstPAEWriteHandlerCR3;
2925
2926	pVM->pgm.s.pfnR0GstGetPage = pModeData->pfnR0GstGetPage;
2927	pVM->pgm.s.pfnR0GstModifyPage = pModeData->pfnR0GstModifyPage;
2928	pVM->pgm.s.pfnR0GstGetPDE = pModeData->pfnR0GstGetPDE;
2929	pVM->pgm.s.pfnR0GstMonitorCR3 = pModeData->pfnR0GstMonitorCR3;
2930	pVM->pgm.s.pfnR0GstUnmonitorCR3 = pModeData->pfnR0GstUnmonitorCR3;
2931	pVM->pgm.s.pfnR0GstMapCR3 = pModeData->pfnR0GstMapCR3;
2932	pVM->pgm.s.pfnR0GstUnmapCR3 = pModeData->pfnR0GstUnmapCR3;
2933	pVM->pgm.s.pfnR0GstWriteHandlerCR3 = pModeData->pfnR0GstWriteHandlerCR3;
2934	pVM->pgm.s.pfnR0GstPAEWriteHandlerCR3 = pModeData->pfnR0GstPAEWriteHandlerCR3;
2935
2936
2937	/* both */
2938	pVM->pgm.s.pfnR3BthRelocate = pModeData->pfnR3BthRelocate;
2939	pVM->pgm.s.pfnR3BthInvalidatePage = pModeData->pfnR3BthInvalidatePage;
2940	pVM->pgm.s.pfnR3BthSyncCR3 = pModeData->pfnR3BthSyncCR3;
2941	Assert(pVM->pgm.s.pfnR3BthSyncCR3);
2942	pVM->pgm.s.pfnR3BthSyncPage = pModeData->pfnR3BthSyncPage;
2943	pVM->pgm.s.pfnR3BthPrefetchPage = pModeData->pfnR3BthPrefetchPage;
2944	pVM->pgm.s.pfnR3BthVerifyAccessSyncPage = pModeData->pfnR3BthVerifyAccessSyncPage;
2945	#ifdef VBOX_STRICT
2946	pVM->pgm.s.pfnR3BthAssertCR3 = pModeData->pfnR3BthAssertCR3;
2947	#endif
2948
2949	pVM->pgm.s.pfnRCBthTrap0eHandler = pModeData->pfnRCBthTrap0eHandler;
2950	pVM->pgm.s.pfnRCBthInvalidatePage = pModeData->pfnRCBthInvalidatePage;
2951	pVM->pgm.s.pfnRCBthSyncCR3 = pModeData->pfnRCBthSyncCR3;
2952	pVM->pgm.s.pfnRCBthSyncPage = pModeData->pfnRCBthSyncPage;
2953	pVM->pgm.s.pfnRCBthPrefetchPage = pModeData->pfnRCBthPrefetchPage;
2954	pVM->pgm.s.pfnRCBthVerifyAccessSyncPage = pModeData->pfnRCBthVerifyAccessSyncPage;
2955	#ifdef VBOX_STRICT
2956	pVM->pgm.s.pfnRCBthAssertCR3 = pModeData->pfnRCBthAssertCR3;
2957	#endif
2958
2959	pVM->pgm.s.pfnR0BthTrap0eHandler = pModeData->pfnR0BthTrap0eHandler;
2960	pVM->pgm.s.pfnR0BthInvalidatePage = pModeData->pfnR0BthInvalidatePage;
2961	pVM->pgm.s.pfnR0BthSyncCR3 = pModeData->pfnR0BthSyncCR3;
2962	pVM->pgm.s.pfnR0BthSyncPage = pModeData->pfnR0BthSyncPage;
2963	pVM->pgm.s.pfnR0BthPrefetchPage = pModeData->pfnR0BthPrefetchPage;
2964	pVM->pgm.s.pfnR0BthVerifyAccessSyncPage = pModeData->pfnR0BthVerifyAccessSyncPage;
2965	#ifdef VBOX_STRICT
2966	pVM->pgm.s.pfnR0BthAssertCR3 = pModeData->pfnR0BthAssertCR3;
2967	#endif
2968	}
2969
2970
2971	#ifdef DEBUG_bird
2972	#include <stdlib.h> /* getenv() remove me! */
2973	#endif
2974
2975	/**
2976	* Calculates the shadow paging mode.
2977	*
2978	* @returns The shadow paging mode.
2979	* @param pVM VM handle.
2980	* @param enmGuestMode The guest mode.
2981	* @param enmHostMode The host mode.
2982	* @param enmShadowMode The current shadow mode.
2983	* @param penmSwitcher Where to store the switcher to use.
2984	* VMMSWITCHER_INVALID means no change.
2985	*/
2986	static PGMMODE pgmR3CalcShadowMode(PVM pVM, PGMMODE enmGuestMode, SUPPAGINGMODE enmHostMode, PGMMODE enmShadowMode, VMMSWITCHER *penmSwitcher)
2987	{
2988	VMMSWITCHER enmSwitcher = VMMSWITCHER_INVALID;
2989	switch (enmGuestMode)
2990	{
2991	/*
2992	* When switching to real or protected mode we don't change
2993	* anything since it's likely that we'll switch back pretty soon.
2994	*
2995	* During pgmR3InitPaging we'll end up here with PGMMODE_INVALID
2996	* and is supposed to determine which shadow paging and switcher to
2997	* use during init.
2998	*/
2999	case PGMMODE_REAL:
3000	case PGMMODE_PROTECTED:
3001	if ( enmShadowMode != PGMMODE_INVALID
3002	&& !HWACCMIsEnabled(pVM) /* always switch in hwaccm mode! */)
3003	break; /* (no change) */
3004
3005	switch (enmHostMode)
3006	{
3007	case SUPPAGINGMODE_32_BIT:
3008	case SUPPAGINGMODE_32_BIT_GLOBAL:
3009	enmShadowMode = PGMMODE_32_BIT;
3010	enmSwitcher = VMMSWITCHER_32_TO_32;
3011	break;
3012
3013	case SUPPAGINGMODE_PAE:
3014	case SUPPAGINGMODE_PAE_NX:
3015	case SUPPAGINGMODE_PAE_GLOBAL:
3016	case SUPPAGINGMODE_PAE_GLOBAL_NX:
3017	enmShadowMode = PGMMODE_PAE;
3018	enmSwitcher = VMMSWITCHER_PAE_TO_PAE;
3019	#ifdef DEBUG_bird
3020	if (getenv("VBOX_32BIT"))
3021	{
3022	enmShadowMode = PGMMODE_32_BIT;
3023	enmSwitcher = VMMSWITCHER_PAE_TO_32;
3024	}
3025	#endif
3026	break;
3027
3028	case SUPPAGINGMODE_AMD64:
3029	case SUPPAGINGMODE_AMD64_GLOBAL:
3030	case SUPPAGINGMODE_AMD64_NX:
3031	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
3032	enmShadowMode = PGMMODE_PAE;
3033	enmSwitcher = VMMSWITCHER_AMD64_TO_PAE;
3034	break;
3035
3036	default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
3037	}
3038	break;
3039
3040	case PGMMODE_32_BIT:
3041	switch (enmHostMode)
3042	{
3043	case SUPPAGINGMODE_32_BIT:
3044	case SUPPAGINGMODE_32_BIT_GLOBAL:
3045	enmShadowMode = PGMMODE_32_BIT;
3046	enmSwitcher = VMMSWITCHER_32_TO_32;
3047	break;
3048
3049	case SUPPAGINGMODE_PAE:
3050	case SUPPAGINGMODE_PAE_NX:
3051	case SUPPAGINGMODE_PAE_GLOBAL:
3052	case SUPPAGINGMODE_PAE_GLOBAL_NX:
3053	enmShadowMode = PGMMODE_PAE;
3054	enmSwitcher = VMMSWITCHER_PAE_TO_PAE;
3055	#ifdef DEBUG_bird
3056	if (getenv("VBOX_32BIT"))
3057	{
3058	enmShadowMode = PGMMODE_32_BIT;
3059	enmSwitcher = VMMSWITCHER_PAE_TO_32;
3060	}
3061	#endif
3062	break;
3063
3064	case SUPPAGINGMODE_AMD64:
3065	case SUPPAGINGMODE_AMD64_GLOBAL:
3066	case SUPPAGINGMODE_AMD64_NX:
3067	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
3068	enmShadowMode = PGMMODE_PAE;
3069	enmSwitcher = VMMSWITCHER_AMD64_TO_PAE;
3070	break;
3071
3072	default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
3073	}
3074	break;
3075
3076	case PGMMODE_PAE:
3077	case PGMMODE_PAE_NX: /** @todo This might require more switchers and guest+both modes. */
3078	switch (enmHostMode)
3079	{
3080	case SUPPAGINGMODE_32_BIT:
3081	case SUPPAGINGMODE_32_BIT_GLOBAL:
3082	enmShadowMode = PGMMODE_PAE;
3083	enmSwitcher = VMMSWITCHER_32_TO_PAE;
3084	break;
3085
3086	case SUPPAGINGMODE_PAE:
3087	case SUPPAGINGMODE_PAE_NX:
3088	case SUPPAGINGMODE_PAE_GLOBAL:
3089	case SUPPAGINGMODE_PAE_GLOBAL_NX:
3090	enmShadowMode = PGMMODE_PAE;
3091	enmSwitcher = VMMSWITCHER_PAE_TO_PAE;
3092	break;
3093
3094	case SUPPAGINGMODE_AMD64:
3095	case SUPPAGINGMODE_AMD64_GLOBAL:
3096	case SUPPAGINGMODE_AMD64_NX:
3097	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
3098	enmShadowMode = PGMMODE_PAE;
3099	enmSwitcher = VMMSWITCHER_AMD64_TO_PAE;
3100	break;
3101
3102	default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
3103	}
3104	break;
3105
3106	case PGMMODE_AMD64:
3107	case PGMMODE_AMD64_NX:
3108	switch (enmHostMode)
3109	{
3110	case SUPPAGINGMODE_32_BIT:
3111	case SUPPAGINGMODE_32_BIT_GLOBAL:
3112	enmShadowMode = PGMMODE_PAE;
3113	enmSwitcher = VMMSWITCHER_32_TO_AMD64;
3114	break;
3115
3116	case SUPPAGINGMODE_PAE:
3117	case SUPPAGINGMODE_PAE_NX:
3118	case SUPPAGINGMODE_PAE_GLOBAL:
3119	case SUPPAGINGMODE_PAE_GLOBAL_NX:
3120	enmShadowMode = PGMMODE_PAE;
3121	enmSwitcher = VMMSWITCHER_PAE_TO_AMD64;
3122	break;
3123
3124	case SUPPAGINGMODE_AMD64:
3125	case SUPPAGINGMODE_AMD64_GLOBAL:
3126	case SUPPAGINGMODE_AMD64_NX:
3127	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
3128	enmShadowMode = PGMMODE_AMD64;
3129	enmSwitcher = VMMSWITCHER_AMD64_TO_AMD64;
3130	break;
3131
3132	default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
3133	}
3134	break;
3135
3136
3137	default:
3138	AssertReleaseMsgFailed(("enmGuestMode=%d\n", enmGuestMode));
3139	return PGMMODE_INVALID;
3140	}
3141	/* Override the shadow mode is nested paging is active. */
3142	if (HWACCMIsNestedPagingActive(pVM))
3143	enmShadowMode = HWACCMGetPagingMode(pVM);
3144
3145	*penmSwitcher = enmSwitcher;
3146	return enmShadowMode;
3147	}
3148
3149	/**
3150	* Performs the actual mode change.
3151	* This is called by PGMChangeMode and pgmR3InitPaging().
3152	*
3153	* @returns VBox status code.
3154	* @param pVM VM handle.
3155	* @param enmGuestMode The new guest mode. This is assumed to be different from
3156	* the current mode.
3157	*/
3158	VMMR3DECL(int) PGMR3ChangeMode(PVM pVM, PGMMODE enmGuestMode)
3159	{
3160	Log(("PGMR3ChangeMode: Guest mode: %s -> %s\n", PGMGetModeName(pVM->pgm.s.enmGuestMode), PGMGetModeName(enmGuestMode)));
3161	STAM_REL_COUNTER_INC(&pVM->pgm.s.cGuestModeChanges);
3162
3163	/*
3164	* Calc the shadow mode and switcher.
3165	*/
3166	VMMSWITCHER enmSwitcher;
3167	PGMMODE enmShadowMode = pgmR3CalcShadowMode(pVM, enmGuestMode, pVM->pgm.s.enmHostMode, pVM->pgm.s.enmShadowMode, &enmSwitcher);
3168	if (enmSwitcher != VMMSWITCHER_INVALID)
3169	{
3170	/*
3171	* Select new switcher.
3172	*/
3173	int rc = VMMR3SelectSwitcher(pVM, enmSwitcher);
3174	if (VBOX_FAILURE(rc))
3175	{
3176	AssertReleaseMsgFailed(("VMMR3SelectSwitcher(%d) -> %Vrc\n", enmSwitcher, rc));
3177	return rc;
3178	}
3179	}
3180
3181	/*
3182	* Exit old mode(s).
3183	*/
3184	/* shadow */
3185	if (enmShadowMode != pVM->pgm.s.enmShadowMode)
3186	{
3187	LogFlow(("PGMR3ChangeMode: Shadow mode: %s -> %s\n", PGMGetModeName(pVM->pgm.s.enmShadowMode), PGMGetModeName(enmShadowMode)));
3188	if (PGM_SHW_PFN(Exit, pVM))
3189	{
3190	int rc = PGM_SHW_PFN(Exit, pVM)(pVM);
3191	if (VBOX_FAILURE(rc))
3192	{
3193	AssertMsgFailed(("Exit failed for shadow mode %d: %Vrc\n", pVM->pgm.s.enmShadowMode, rc));
3194	return rc;
3195	}
3196	}
3197
3198	}
3199	else
3200	LogFlow(("PGMR3ChangeMode: Shadow mode remains: %s\n", PGMGetModeName(pVM->pgm.s.enmShadowMode)));
3201
3202	/* guest */
3203	if (PGM_GST_PFN(Exit, pVM))
3204	{
3205	int rc = PGM_GST_PFN(Exit, pVM)(pVM);
3206	if (VBOX_FAILURE(rc))
3207	{
3208	AssertMsgFailed(("Exit failed for guest mode %d: %Vrc\n", pVM->pgm.s.enmGuestMode, rc));
3209	return rc;
3210	}
3211	}
3212
3213	/*
3214	* Load new paging mode data.
3215	*/
3216	pgmR3ModeDataSwitch(pVM, enmShadowMode, enmGuestMode);
3217
3218	/*
3219	* Enter new shadow mode (if changed).
3220	*/
3221	if (enmShadowMode != pVM->pgm.s.enmShadowMode)
3222	{
3223	int rc;
3224	pVM->pgm.s.enmShadowMode = enmShadowMode;
3225	switch (enmShadowMode)
3226	{
3227	case PGMMODE_32_BIT:
3228	rc = PGM_SHW_NAME_32BIT(Enter)(pVM);
3229	break;
3230	case PGMMODE_PAE:
3231	case PGMMODE_PAE_NX:
3232	rc = PGM_SHW_NAME_PAE(Enter)(pVM);
3233	break;
3234	case PGMMODE_AMD64:
3235	case PGMMODE_AMD64_NX:
3236	rc = PGM_SHW_NAME_AMD64(Enter)(pVM);
3237	break;
3238	case PGMMODE_NESTED:
3239	rc = PGM_SHW_NAME_NESTED(Enter)(pVM);
3240	break;
3241	case PGMMODE_EPT:
3242	rc = PGM_SHW_NAME_EPT(Enter)(pVM);
3243	break;
3244	case PGMMODE_REAL:
3245	case PGMMODE_PROTECTED:
3246	default:
3247	AssertReleaseMsgFailed(("enmShadowMode=%d\n", enmShadowMode));
3248	return VERR_INTERNAL_ERROR;
3249	}
3250	if (VBOX_FAILURE(rc))
3251	{
3252	AssertReleaseMsgFailed(("Entering enmShadowMode=%d failed: %Vrc\n", enmShadowMode, rc));
3253	pVM->pgm.s.enmShadowMode = PGMMODE_INVALID;
3254	return rc;
3255	}
3256	}
3257
3258	/* We must flush the PGM pool cache if the guest mode changes; we don't always
3259	* switch shadow paging mode (e.g. protected->32-bit) and shouldn't reuse
3260	* the shadow page tables.
3261	*
3262	* That only applies when switching between paging and non-paging modes.
3263	*
3264	* @todo A20 setting
3265	*/
3266	if ( pVM->pgm.s.CTX_SUFF(pPool)
3267	&& !HWACCMIsNestedPagingActive(pVM)
3268	&& PGMMODE_WITH_PAGING(pVM->pgm.s.enmGuestMode) != PGMMODE_WITH_PAGING(enmGuestMode))
3269	{
3270	Log(("PGMR3ChangeMode: changing guest paging mode -> flush pgm pool cache!\n"));
3271	pgmPoolFlushAll(pVM);
3272	}
3273
3274	/*
3275	* Enter the new guest and shadow+guest modes.
3276	*/
3277	int rc = -1;
3278	int rc2 = -1;
3279	RTGCPHYS GCPhysCR3 = NIL_RTGCPHYS;
3280	pVM->pgm.s.enmGuestMode = enmGuestMode;
3281	switch (enmGuestMode)
3282	{
3283	case PGMMODE_REAL:
3284	rc = PGM_GST_NAME_REAL(Enter)(pVM, NIL_RTGCPHYS);
3285	switch (pVM->pgm.s.enmShadowMode)
3286	{
3287	case PGMMODE_32_BIT:
3288	rc2 = PGM_BTH_NAME_32BIT_REAL(Enter)(pVM, NIL_RTGCPHYS);
3289	break;
3290	case PGMMODE_PAE:
3291	case PGMMODE_PAE_NX:
3292	rc2 = PGM_BTH_NAME_PAE_REAL(Enter)(pVM, NIL_RTGCPHYS);
3293	break;
3294	case PGMMODE_NESTED:
3295	rc2 = PGM_BTH_NAME_NESTED_REAL(Enter)(pVM, NIL_RTGCPHYS);
3296	break;
3297	case PGMMODE_EPT:
3298	rc2 = PGM_BTH_NAME_EPT_REAL(Enter)(pVM, NIL_RTGCPHYS);
3299	break;
3300	case PGMMODE_AMD64:
3301	case PGMMODE_AMD64_NX:
3302	AssertMsgFailed(("Should use PAE shadow mode!\n"));
3303	default: AssertFailed(); break;
3304	}
3305	break;
3306
3307	case PGMMODE_PROTECTED:
3308	rc = PGM_GST_NAME_PROT(Enter)(pVM, NIL_RTGCPHYS);
3309	switch (pVM->pgm.s.enmShadowMode)
3310	{
3311	case PGMMODE_32_BIT:
3312	rc2 = PGM_BTH_NAME_32BIT_PROT(Enter)(pVM, NIL_RTGCPHYS);
3313	break;
3314	case PGMMODE_PAE:
3315	case PGMMODE_PAE_NX:
3316	rc2 = PGM_BTH_NAME_PAE_PROT(Enter)(pVM, NIL_RTGCPHYS);
3317	break;
3318	case PGMMODE_NESTED:
3319	rc2 = PGM_BTH_NAME_NESTED_PROT(Enter)(pVM, NIL_RTGCPHYS);
3320	break;
3321	case PGMMODE_EPT:
3322	rc2 = PGM_BTH_NAME_EPT_PROT(Enter)(pVM, NIL_RTGCPHYS);
3323	break;
3324	case PGMMODE_AMD64:
3325	case PGMMODE_AMD64_NX:
3326	AssertMsgFailed(("Should use PAE shadow mode!\n"));
3327	default: AssertFailed(); break;
3328	}
3329	break;
3330
3331	case PGMMODE_32_BIT:
3332	GCPhysCR3 = CPUMGetGuestCR3(pVM) & X86_CR3_PAGE_MASK;
3333	rc = PGM_GST_NAME_32BIT(Enter)(pVM, GCPhysCR3);
3334	switch (pVM->pgm.s.enmShadowMode)
3335	{
3336	case PGMMODE_32_BIT:
3337	rc2 = PGM_BTH_NAME_32BIT_32BIT(Enter)(pVM, GCPhysCR3);
3338	break;
3339	case PGMMODE_PAE:
3340	case PGMMODE_PAE_NX:
3341	rc2 = PGM_BTH_NAME_PAE_32BIT(Enter)(pVM, GCPhysCR3);
3342	break;
3343	case PGMMODE_NESTED:
3344	rc2 = PGM_BTH_NAME_NESTED_32BIT(Enter)(pVM, GCPhysCR3);
3345	break;
3346	case PGMMODE_EPT:
3347	rc2 = PGM_BTH_NAME_EPT_32BIT(Enter)(pVM, GCPhysCR3);
3348	break;
3349	case PGMMODE_AMD64:
3350	case PGMMODE_AMD64_NX:
3351	AssertMsgFailed(("Should use PAE shadow mode!\n"));
3352	default: AssertFailed(); break;
3353	}
3354	break;
3355
3356	case PGMMODE_PAE_NX:
3357	case PGMMODE_PAE:
3358	{
3359	uint32_t u32Dummy, u32Features;
3360
3361	CPUMGetGuestCpuId(pVM, 1, &u32Dummy, &u32Dummy, &u32Dummy, &u32Features);
3362	if (!(u32Features & X86_CPUID_FEATURE_EDX_PAE))
3363	{
3364	/* Pause first, then inform Main. */
3365	rc = VMR3SuspendNoSave(pVM);
3366	AssertRC(rc);
3367
3368	VMSetRuntimeError(pVM, true, "PAEmode",
3369	N_("The guest is trying to switch to the PAE mode which is currently disabled by default in VirtualBox. Experimental PAE support can be enabled using the -pae option with VBoxManage"));
3370	/* we must return TRUE here otherwise the recompiler will assert */
3371	return VINF_SUCCESS;
3372	}
3373	GCPhysCR3 = CPUMGetGuestCR3(pVM) & X86_CR3_PAE_PAGE_MASK;
3374	rc = PGM_GST_NAME_PAE(Enter)(pVM, GCPhysCR3);
3375	switch (pVM->pgm.s.enmShadowMode)
3376	{
3377	case PGMMODE_PAE:
3378	case PGMMODE_PAE_NX:
3379	rc2 = PGM_BTH_NAME_PAE_PAE(Enter)(pVM, GCPhysCR3);
3380	break;
3381	case PGMMODE_NESTED:
3382	rc2 = PGM_BTH_NAME_NESTED_PAE(Enter)(pVM, GCPhysCR3);
3383	break;
3384	case PGMMODE_EPT:
3385	rc2 = PGM_BTH_NAME_EPT_PAE(Enter)(pVM, GCPhysCR3);
3386	break;
3387	case PGMMODE_32_BIT:
3388	case PGMMODE_AMD64:
3389	case PGMMODE_AMD64_NX:
3390	AssertMsgFailed(("Should use PAE shadow mode!\n"));
3391	default: AssertFailed(); break;
3392	}
3393	break;
3394	}
3395
3396	#ifdef VBOX_WITH_64_BITS_GUESTS
3397	case PGMMODE_AMD64_NX:
3398	case PGMMODE_AMD64:
3399	GCPhysCR3 = CPUMGetGuestCR3(pVM) & 0xfffffffffffff000ULL; /** @todo define this mask! */
3400	rc = PGM_GST_NAME_AMD64(Enter)(pVM, GCPhysCR3);
3401	switch (pVM->pgm.s.enmShadowMode)
3402	{
3403	case PGMMODE_AMD64:
3404	case PGMMODE_AMD64_NX:
3405	rc2 = PGM_BTH_NAME_AMD64_AMD64(Enter)(pVM, GCPhysCR3);
3406	break;
3407	case PGMMODE_NESTED:
3408	rc2 = PGM_BTH_NAME_NESTED_AMD64(Enter)(pVM, GCPhysCR3);
3409	break;
3410	case PGMMODE_EPT:
3411	rc2 = PGM_BTH_NAME_EPT_AMD64(Enter)(pVM, GCPhysCR3);
3412	break;
3413	case PGMMODE_32_BIT:
3414	case PGMMODE_PAE:
3415	case PGMMODE_PAE_NX:
3416	AssertMsgFailed(("Should use AMD64 shadow mode!\n"));
3417	default: AssertFailed(); break;
3418	}
3419	break;
3420	#endif
3421
3422	default:
3423	AssertReleaseMsgFailed(("enmGuestMode=%d\n", enmGuestMode));
3424	rc = VERR_NOT_IMPLEMENTED;
3425	break;
3426	}
3427
3428	/* status codes. */
3429	AssertRC(rc);
3430	AssertRC(rc2);
3431	if (VBOX_SUCCESS(rc))
3432	{
3433	rc = rc2;
3434	if (VBOX_SUCCESS(rc)) /* no informational status codes. */
3435	rc = VINF_SUCCESS;
3436	}
3437
3438	/*
3439	* Notify SELM so it can update the TSSes with correct CR3s.
3440	*/
3441	SELMR3PagingModeChanged(pVM);
3442
3443	/* Notify HWACCM as well. */
3444	HWACCMR3PagingModeChanged(pVM, pVM->pgm.s.enmShadowMode);
3445	return rc;
3446	}
3447
3448
3449	/**
3450	* Dumps a PAE shadow page table.
3451	*
3452	* @returns VBox status code (VINF_SUCCESS).
3453	* @param pVM The VM handle.
3454	* @param pPT Pointer to the page table.
3455	* @param u64Address The virtual address of the page table starts.
3456	* @param fLongMode Set if this a long mode table; clear if it's a legacy mode table.
3457	* @param cMaxDepth The maxium depth.
3458	* @param pHlp Pointer to the output functions.
3459	*/
3460	static int pgmR3DumpHierarchyHCPaePT(PVM pVM, PX86PTPAE pPT, uint64_t u64Address, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
3461	{
3462	for (unsigned i = 0; i < RT_ELEMENTS(pPT->a); i++)
3463	{
3464	X86PTEPAE Pte = pPT->a[i];
3465	if (Pte.n.u1Present)
3466	{
3467	pHlp->pfnPrintf(pHlp,
3468	fLongMode /P R S A D G WT CD AT NX 4M a p ? /
3469	? "%016llx 3 \| P %c %c %c %c %c %s %s %s %s 4K %c%c%c %016llx\n"
3470	: "%08llx 2 \| P %c %c %c %c %c %s %s %s %s 4K %c%c%c %016llx\n",
3471	u64Address + ((uint64_t)i << X86_PT_PAE_SHIFT),
3472	Pte.n.u1Write ? 'W' : 'R',
3473	Pte.n.u1User ? 'U' : 'S',
3474	Pte.n.u1Accessed ? 'A' : '-',
3475	Pte.n.u1Dirty ? 'D' : '-',
3476	Pte.n.u1Global ? 'G' : '-',
3477	Pte.n.u1WriteThru ? "WT" : "--",
3478	Pte.n.u1CacheDisable? "CD" : "--",
3479	Pte.n.u1PAT ? "AT" : "--",
3480	Pte.n.u1NoExecute ? "NX" : "--",
3481	Pte.u & PGM_PTFLAGS_TRACK_DIRTY ? 'd' : '-',
3482	Pte.u & RT_BIT(10) ? '1' : '0',
3483	Pte.u & PGM_PTFLAGS_CSAM_VALIDATED? 'v' : '-',
3484	Pte.u & X86_PTE_PAE_PG_MASK);
3485	}
3486	}
3487	return VINF_SUCCESS;
3488	}
3489
3490
3491	/**
3492	* Dumps a PAE shadow page directory table.
3493	*
3494	* @returns VBox status code (VINF_SUCCESS).
3495	* @param pVM The VM handle.
3496	* @param HCPhys The physical address of the page directory table.
3497	* @param u64Address The virtual address of the page table starts.
3498	* @param cr4 The CR4, PSE is currently used.
3499	* @param fLongMode Set if this a long mode table; clear if it's a legacy mode table.
3500	* @param cMaxDepth The maxium depth.
3501	* @param pHlp Pointer to the output functions.
3502	*/
3503	static int pgmR3DumpHierarchyHCPaePD(PVM pVM, RTHCPHYS HCPhys, uint64_t u64Address, uint32_t cr4, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
3504	{
3505	PX86PDPAE pPD = (PX86PDPAE)MMPagePhys2Page(pVM, HCPhys);
3506	if (!pPD)
3507	{
3508	pHlp->pfnPrintf(pHlp, "%0*llx error! Page directory at HCPhys=%#VHp was not found in the page pool!\n",
3509	fLongMode ? 16 : 8, u64Address, HCPhys);
3510	return VERR_INVALID_PARAMETER;
3511	}
3512	const bool fBigPagesSupported = fLongMode \|\| !!(cr4 & X86_CR4_PSE);
3513
3514	int rc = VINF_SUCCESS;
3515	for (unsigned i = 0; i < RT_ELEMENTS(pPD->a); i++)
3516	{
3517	X86PDEPAE Pde = pPD->a[i];
3518	if (Pde.n.u1Present)
3519	{
3520	if (fBigPagesSupported && Pde.b.u1Size)
3521	pHlp->pfnPrintf(pHlp,
3522	fLongMode /P R S A D G WT CD AT NX 4M a p ? /
3523	? "%016llx 2 \| P %c %c %c %c %c %s %s %s %s 4M %c%c%c %016llx\n"
3524	: "%08llx 1 \| P %c %c %c %c %c %s %s %s %s 4M %c%c%c %016llx\n",
3525	u64Address + ((uint64_t)i << X86_PD_PAE_SHIFT),
3526	Pde.b.u1Write ? 'W' : 'R',
3527	Pde.b.u1User ? 'U' : 'S',
3528	Pde.b.u1Accessed ? 'A' : '-',
3529	Pde.b.u1Dirty ? 'D' : '-',
3530	Pde.b.u1Global ? 'G' : '-',
3531	Pde.b.u1WriteThru ? "WT" : "--",
3532	Pde.b.u1CacheDisable? "CD" : "--",
3533	Pde.b.u1PAT ? "AT" : "--",
3534	Pde.b.u1NoExecute ? "NX" : "--",
3535	Pde.u & RT_BIT_64(9) ? '1' : '0',
3536	Pde.u & PGM_PDFLAGS_MAPPING ? 'm' : '-',
3537	Pde.u & PGM_PDFLAGS_TRACK_DIRTY ? 'd' : '-',
3538	Pde.u & X86_PDE_PAE_PG_MASK);
3539	else
3540	{
3541	pHlp->pfnPrintf(pHlp,
3542	fLongMode /P R S A D G WT CD AT NX 4M a p ? /
3543	? "%016llx 2 \| P %c %c %c %c %c %s %s .. %s 4K %c%c%c %016llx\n"
3544	: "%08llx 1 \| P %c %c %c %c %c %s %s .. %s 4K %c%c%c %016llx\n",
3545	u64Address + ((uint64_t)i << X86_PD_PAE_SHIFT),
3546	Pde.n.u1Write ? 'W' : 'R',
3547	Pde.n.u1User ? 'U' : 'S',
3548	Pde.n.u1Accessed ? 'A' : '-',
3549	Pde.n.u1Reserved0 ? '?' : '.', /* ignored */
3550	Pde.n.u1Reserved1 ? '?' : '.', /* ignored */
3551	Pde.n.u1WriteThru ? "WT" : "--",
3552	Pde.n.u1CacheDisable? "CD" : "--",
3553	Pde.n.u1NoExecute ? "NX" : "--",
3554	Pde.u & RT_BIT_64(9) ? '1' : '0',
3555	Pde.u & PGM_PDFLAGS_MAPPING ? 'm' : '-',
3556	Pde.u & PGM_PDFLAGS_TRACK_DIRTY ? 'd' : '-',
3557	Pde.u & X86_PDE_PAE_PG_MASK);
3558	if (cMaxDepth >= 1)
3559	{
3560	/** @todo what about using the page pool for mapping PTs? */
3561	uint64_t u64AddressPT = u64Address + ((uint64_t)i << X86_PD_PAE_SHIFT);
3562	RTHCPHYS HCPhysPT = Pde.u & X86_PDE_PAE_PG_MASK;
3563	PX86PTPAE pPT = NULL;
3564	if (!(Pde.u & PGM_PDFLAGS_MAPPING))
3565	pPT = (PX86PTPAE)MMPagePhys2Page(pVM, HCPhysPT);
3566	else
3567	{
3568	for (PPGMMAPPING pMap = pVM->pgm.s.pMappingsR3; pMap; pMap = pMap->pNextR3)
3569	{
3570	uint64_t off = u64AddressPT - pMap->GCPtr;
3571	if (off < pMap->cb)
3572	{
3573	const int iPDE = (uint32_t)(off >> X86_PD_SHIFT);
3574	const int iSub = (int)((off >> X86_PD_PAE_SHIFT) & 1); /* MSC is a pain sometimes */
3575	if ((iSub ? pMap->aPTs[iPDE].HCPhysPaePT1 : pMap->aPTs[iPDE].HCPhysPaePT0) != HCPhysPT)
3576	pHlp->pfnPrintf(pHlp, "%0*llx error! Mapping error! PT %d has HCPhysPT=%VHp not %VHp is in the PD.\n",
3577	fLongMode ? 16 : 8, u64AddressPT, iPDE,
3578	iSub ? pMap->aPTs[iPDE].HCPhysPaePT1 : pMap->aPTs[iPDE].HCPhysPaePT0, HCPhysPT);
3579	pPT = &pMap->aPTs[iPDE].paPaePTsR3[iSub];
3580	}
3581	}
3582	}
3583	int rc2 = VERR_INVALID_PARAMETER;
3584	if (pPT)
3585	rc2 = pgmR3DumpHierarchyHCPaePT(pVM, pPT, u64AddressPT, fLongMode, cMaxDepth - 1, pHlp);
3586	else
3587	pHlp->pfnPrintf(pHlp, "%0*llx error! Page table at HCPhys=%#VHp was not found in the page pool!\n",
3588	fLongMode ? 16 : 8, u64AddressPT, HCPhysPT);
3589	if (rc2 < rc && VBOX_SUCCESS(rc))
3590	rc = rc2;
3591	}
3592	}
3593	}
3594	}
3595	return rc;
3596	}
3597
3598
3599	/**
3600	* Dumps a PAE shadow page directory pointer table.
3601	*
3602	* @returns VBox status code (VINF_SUCCESS).
3603	* @param pVM The VM handle.
3604	* @param HCPhys The physical address of the page directory pointer table.
3605	* @param u64Address The virtual address of the page table starts.
3606	* @param cr4 The CR4, PSE is currently used.
3607	* @param fLongMode Set if this a long mode table; clear if it's a legacy mode table.
3608	* @param cMaxDepth The maxium depth.
3609	* @param pHlp Pointer to the output functions.
3610	*/
3611	static int pgmR3DumpHierarchyHCPaePDPT(PVM pVM, RTHCPHYS HCPhys, uint64_t u64Address, uint32_t cr4, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
3612	{
3613	PX86PDPT pPDPT = (PX86PDPT)MMPagePhys2Page(pVM, HCPhys);
3614	if (!pPDPT)
3615	{
3616	pHlp->pfnPrintf(pHlp, "%0*llx error! Page directory pointer table at HCPhys=%#VHp was not found in the page pool!\n",
3617	fLongMode ? 16 : 8, u64Address, HCPhys);
3618	return VERR_INVALID_PARAMETER;
3619	}
3620
3621	int rc = VINF_SUCCESS;
3622	const unsigned c = fLongMode ? RT_ELEMENTS(pPDPT->a) : X86_PG_PAE_PDPE_ENTRIES;
3623	for (unsigned i = 0; i < c; i++)
3624	{
3625	X86PDPE Pdpe = pPDPT->a[i];
3626	if (Pdpe.n.u1Present)
3627	{
3628	if (fLongMode)
3629	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a p ? /
3630	"%016llx 1 \| P %c %c %c %c %c %s %s %s %s .. %c%c%c %016llx\n",
3631	u64Address + ((uint64_t)i << X86_PDPT_SHIFT),
3632	Pdpe.lm.u1Write ? 'W' : 'R',
3633	Pdpe.lm.u1User ? 'U' : 'S',
3634	Pdpe.lm.u1Accessed ? 'A' : '-',
3635	Pdpe.lm.u3Reserved & 1? '?' : '.', /* ignored */
3636	Pdpe.lm.u3Reserved & 4? '!' : '.', /* mbz */
3637	Pdpe.lm.u1WriteThru ? "WT" : "--",
3638	Pdpe.lm.u1CacheDisable? "CD" : "--",
3639	Pdpe.lm.u3Reserved & 2? "!" : "..",/* mbz */
3640	Pdpe.lm.u1NoExecute ? "NX" : "--",
3641	Pdpe.u & RT_BIT(9) ? '1' : '0',
3642	Pdpe.u & PGM_PLXFLAGS_PERMANENT ? 'p' : '-',
3643	Pdpe.u & RT_BIT(11) ? '1' : '0',
3644	Pdpe.u & X86_PDPE_PG_MASK);
3645	else
3646	pHlp->pfnPrintf(pHlp, /P G WT CD AT NX 4M a p ? /
3647	"%08x 0 \| P %c %s %s %s %s .. %c%c%c %016llx\n",
3648	i << X86_PDPT_SHIFT,
3649	Pdpe.n.u4Reserved & 1? '!' : '.', /* mbz */
3650	Pdpe.n.u4Reserved & 4? '!' : '.', /* mbz */
3651	Pdpe.n.u1WriteThru ? "WT" : "--",
3652	Pdpe.n.u1CacheDisable? "CD" : "--",
3653	Pdpe.n.u4Reserved & 2? "!" : "..",/* mbz */
3654	Pdpe.u & RT_BIT(9) ? '1' : '0',
3655	Pdpe.u & PGM_PLXFLAGS_PERMANENT ? 'p' : '-',
3656	Pdpe.u & RT_BIT(11) ? '1' : '0',
3657	Pdpe.u & X86_PDPE_PG_MASK);
3658	if (cMaxDepth >= 1)
3659	{
3660	int rc2 = pgmR3DumpHierarchyHCPaePD(pVM, Pdpe.u & X86_PDPE_PG_MASK, u64Address + ((uint64_t)i << X86_PDPT_SHIFT),
3661	cr4, fLongMode, cMaxDepth - 1, pHlp);
3662	if (rc2 < rc && VBOX_SUCCESS(rc))
3663	rc = rc2;
3664	}
3665	}
3666	}
3667	return rc;
3668	}
3669
3670
3671	/**
3672	* Dumps a 32-bit shadow page table.
3673	*
3674	* @returns VBox status code (VINF_SUCCESS).
3675	* @param pVM The VM handle.
3676	* @param HCPhys The physical address of the table.
3677	* @param cr4 The CR4, PSE is currently used.
3678	* @param cMaxDepth The maxium depth.
3679	* @param pHlp Pointer to the output functions.
3680	*/
3681	static int pgmR3DumpHierarchyHcPaePML4(PVM pVM, RTHCPHYS HCPhys, uint32_t cr4, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
3682	{
3683	PX86PML4 pPML4 = (PX86PML4)MMPagePhys2Page(pVM, HCPhys);
3684	if (!pPML4)
3685	{
3686	pHlp->pfnPrintf(pHlp, "Page map level 4 at HCPhys=%#VHp was not found in the page pool!\n", HCPhys);
3687	return VERR_INVALID_PARAMETER;
3688	}
3689
3690	int rc = VINF_SUCCESS;
3691	for (unsigned i = 0; i < RT_ELEMENTS(pPML4->a); i++)
3692	{
3693	X86PML4E Pml4e = pPML4->a[i];
3694	if (Pml4e.n.u1Present)
3695	{
3696	uint64_t u64Address = ((uint64_t)i << X86_PML4_SHIFT) \| (((uint64_t)i >> (X86_PML4_SHIFT - X86_PDPT_SHIFT - 1)) * 0xffff000000000000ULL);
3697	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a p ? /
3698	"%016llx 0 \| P %c %c %c %c %c %s %s %s %s .. %c%c%c %016llx\n",
3699	u64Address,
3700	Pml4e.n.u1Write ? 'W' : 'R',
3701	Pml4e.n.u1User ? 'U' : 'S',
3702	Pml4e.n.u1Accessed ? 'A' : '-',
3703	Pml4e.n.u3Reserved & 1? '?' : '.', /* ignored */
3704	Pml4e.n.u3Reserved & 4? '!' : '.', /* mbz */
3705	Pml4e.n.u1WriteThru ? "WT" : "--",
3706	Pml4e.n.u1CacheDisable? "CD" : "--",
3707	Pml4e.n.u3Reserved & 2? "!" : "..",/* mbz */
3708	Pml4e.n.u1NoExecute ? "NX" : "--",
3709	Pml4e.u & RT_BIT(9) ? '1' : '0',
3710	Pml4e.u & PGM_PLXFLAGS_PERMANENT ? 'p' : '-',
3711	Pml4e.u & RT_BIT(11) ? '1' : '0',
3712	Pml4e.u & X86_PML4E_PG_MASK);
3713
3714	if (cMaxDepth >= 1)
3715	{
3716	int rc2 = pgmR3DumpHierarchyHCPaePDPT(pVM, Pml4e.u & X86_PML4E_PG_MASK, u64Address, cr4, true, cMaxDepth - 1, pHlp);
3717	if (rc2 < rc && VBOX_SUCCESS(rc))
3718	rc = rc2;
3719	}
3720	}
3721	}
3722	return rc;
3723	}
3724
3725
3726	/**
3727	* Dumps a 32-bit shadow page table.
3728	*
3729	* @returns VBox status code (VINF_SUCCESS).
3730	* @param pVM The VM handle.
3731	* @param pPT Pointer to the page table.
3732	* @param u32Address The virtual address this table starts at.
3733	* @param pHlp Pointer to the output functions.
3734	*/
3735	int pgmR3DumpHierarchyHC32BitPT(PVM pVM, PX86PT pPT, uint32_t u32Address, PCDBGFINFOHLP pHlp)
3736	{
3737	for (unsigned i = 0; i < RT_ELEMENTS(pPT->a); i++)
3738	{
3739	X86PTE Pte = pPT->a[i];
3740	if (Pte.n.u1Present)
3741	{
3742	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a m d /
3743	"%08x 1 \| P %c %c %c %c %c %s %s %s .. 4K %c%c%c %08x\n",
3744	u32Address + (i << X86_PT_SHIFT),
3745	Pte.n.u1Write ? 'W' : 'R',
3746	Pte.n.u1User ? 'U' : 'S',
3747	Pte.n.u1Accessed ? 'A' : '-',
3748	Pte.n.u1Dirty ? 'D' : '-',
3749	Pte.n.u1Global ? 'G' : '-',
3750	Pte.n.u1WriteThru ? "WT" : "--",
3751	Pte.n.u1CacheDisable? "CD" : "--",
3752	Pte.n.u1PAT ? "AT" : "--",
3753	Pte.u & PGM_PTFLAGS_TRACK_DIRTY ? 'd' : '-',
3754	Pte.u & RT_BIT(10) ? '1' : '0',
3755	Pte.u & PGM_PTFLAGS_CSAM_VALIDATED ? 'v' : '-',
3756	Pte.u & X86_PDE_PG_MASK);
3757	}
3758	}
3759	return VINF_SUCCESS;
3760	}
3761
3762
3763	/**
3764	* Dumps a 32-bit shadow page directory and page tables.
3765	*
3766	* @returns VBox status code (VINF_SUCCESS).
3767	* @param pVM The VM handle.
3768	* @param cr3 The root of the hierarchy.
3769	* @param cr4 The CR4, PSE is currently used.
3770	* @param cMaxDepth How deep into the hierarchy the dumper should go.
3771	* @param pHlp Pointer to the output functions.
3772	*/
3773	int pgmR3DumpHierarchyHC32BitPD(PVM pVM, uint32_t cr3, uint32_t cr4, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
3774	{
3775	PX86PD pPD = (PX86PD)MMPagePhys2Page(pVM, cr3 & X86_CR3_PAGE_MASK);
3776	if (!pPD)
3777	{
3778	pHlp->pfnPrintf(pHlp, "Page directory at %#x was not found in the page pool!\n", cr3 & X86_CR3_PAGE_MASK);
3779	return VERR_INVALID_PARAMETER;
3780	}
3781
3782	int rc = VINF_SUCCESS;
3783	for (unsigned i = 0; i < RT_ELEMENTS(pPD->a); i++)
3784	{
3785	X86PDE Pde = pPD->a[i];
3786	if (Pde.n.u1Present)
3787	{
3788	const uint32_t u32Address = i << X86_PD_SHIFT;
3789	if ((cr4 & X86_CR4_PSE) && Pde.b.u1Size)
3790	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a m d /
3791	"%08x 0 \| P %c %c %c %c %c %s %s %s .. 4M %c%c%c %08x\n",
3792	u32Address,
3793	Pde.b.u1Write ? 'W' : 'R',
3794	Pde.b.u1User ? 'U' : 'S',
3795	Pde.b.u1Accessed ? 'A' : '-',
3796	Pde.b.u1Dirty ? 'D' : '-',
3797	Pde.b.u1Global ? 'G' : '-',
3798	Pde.b.u1WriteThru ? "WT" : "--",
3799	Pde.b.u1CacheDisable? "CD" : "--",
3800	Pde.b.u1PAT ? "AT" : "--",
3801	Pde.u & RT_BIT_64(9) ? '1' : '0',
3802	Pde.u & PGM_PDFLAGS_MAPPING ? 'm' : '-',
3803	Pde.u & PGM_PDFLAGS_TRACK_DIRTY ? 'd' : '-',
3804	Pde.u & X86_PDE4M_PG_MASK);
3805	else
3806	{
3807	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a m d /
3808	"%08x 0 \| P %c %c %c %c %c %s %s .. .. 4K %c%c%c %08x\n",
3809	u32Address,
3810	Pde.n.u1Write ? 'W' : 'R',
3811	Pde.n.u1User ? 'U' : 'S',
3812	Pde.n.u1Accessed ? 'A' : '-',
3813	Pde.n.u1Reserved0 ? '?' : '.', /* ignored */
3814	Pde.n.u1Reserved1 ? '?' : '.', /* ignored */
3815	Pde.n.u1WriteThru ? "WT" : "--",
3816	Pde.n.u1CacheDisable? "CD" : "--",
3817	Pde.u & RT_BIT_64(9) ? '1' : '0',
3818	Pde.u & PGM_PDFLAGS_MAPPING ? 'm' : '-',
3819	Pde.u & PGM_PDFLAGS_TRACK_DIRTY ? 'd' : '-',
3820	Pde.u & X86_PDE_PG_MASK);
3821	if (cMaxDepth >= 1)
3822	{
3823	/** @todo what about using the page pool for mapping PTs? */
3824	RTHCPHYS HCPhys = Pde.u & X86_PDE_PG_MASK;
3825	PX86PT pPT = NULL;
3826	if (!(Pde.u & PGM_PDFLAGS_MAPPING))
3827	pPT = (PX86PT)MMPagePhys2Page(pVM, HCPhys);
3828	else
3829	{
3830	for (PPGMMAPPING pMap = pVM->pgm.s.pMappingsR3; pMap; pMap = pMap->pNextR3)
3831	if (u32Address - pMap->GCPtr < pMap->cb)
3832	{
3833	int iPDE = (u32Address - pMap->GCPtr) >> X86_PD_SHIFT;
3834	if (pMap->aPTs[iPDE].HCPhysPT != HCPhys)
3835	pHlp->pfnPrintf(pHlp, "%08x error! Mapping error! PT %d has HCPhysPT=%VHp not %VHp is in the PD.\n",
3836	u32Address, iPDE, pMap->aPTs[iPDE].HCPhysPT, HCPhys);
3837	pPT = pMap->aPTs[iPDE].pPTR3;
3838	}
3839	}
3840	int rc2 = VERR_INVALID_PARAMETER;
3841	if (pPT)
3842	rc2 = pgmR3DumpHierarchyHC32BitPT(pVM, pPT, u32Address, pHlp);
3843	else
3844	pHlp->pfnPrintf(pHlp, "%08x error! Page table at %#x was not found in the page pool!\n", u32Address, HCPhys);
3845	if (rc2 < rc && VBOX_SUCCESS(rc))
3846	rc = rc2;
3847	}
3848	}
3849	}
3850	}
3851
3852	return rc;
3853	}
3854
3855
3856	/**
3857	* Dumps a 32-bit shadow page table.
3858	*
3859	* @returns VBox status code (VINF_SUCCESS).
3860	* @param pVM The VM handle.
3861	* @param pPT Pointer to the page table.
3862	* @param u32Address The virtual address this table starts at.
3863	* @param PhysSearch Address to search for.
3864	*/
3865	int pgmR3DumpHierarchyGC32BitPT(PVM pVM, PX86PT pPT, uint32_t u32Address, RTGCPHYS PhysSearch)
3866	{
3867	for (unsigned i = 0; i < RT_ELEMENTS(pPT->a); i++)
3868	{
3869	X86PTE Pte = pPT->a[i];
3870	if (Pte.n.u1Present)
3871	{
3872	Log(( /P R S A D G WT CD AT NX 4M a m d /
3873	"%08x 1 \| P %c %c %c %c %c %s %s %s .. 4K %c%c%c %08x\n",
3874	u32Address + (i << X86_PT_SHIFT),
3875	Pte.n.u1Write ? 'W' : 'R',
3876	Pte.n.u1User ? 'U' : 'S',
3877	Pte.n.u1Accessed ? 'A' : '-',
3878	Pte.n.u1Dirty ? 'D' : '-',
3879	Pte.n.u1Global ? 'G' : '-',
3880	Pte.n.u1WriteThru ? "WT" : "--",
3881	Pte.n.u1CacheDisable? "CD" : "--",
3882	Pte.n.u1PAT ? "AT" : "--",
3883	Pte.u & PGM_PTFLAGS_TRACK_DIRTY ? 'd' : '-',
3884	Pte.u & RT_BIT(10) ? '1' : '0',
3885	Pte.u & PGM_PTFLAGS_CSAM_VALIDATED ? 'v' : '-',
3886	Pte.u & X86_PDE_PG_MASK));
3887
3888	if ((Pte.u & X86_PDE_PG_MASK) == PhysSearch)
3889	{
3890	uint64_t fPageShw = 0;
3891	RTHCPHYS pPhysHC = 0;
3892
3893	PGMShwGetPage(pVM, (RTGCPTR)(u32Address + (i << X86_PT_SHIFT)), &fPageShw, &pPhysHC);
3894	Log(("Found %VGp at %VGv -> flags=%llx\n", PhysSearch, (RTGCPTR)(u32Address + (i << X86_PT_SHIFT)), fPageShw));
3895	}
3896	}
3897	}
3898	return VINF_SUCCESS;
3899	}
3900
3901
3902	/**
3903	* Dumps a 32-bit guest page directory and page tables.
3904	*
3905	* @returns VBox status code (VINF_SUCCESS).
3906	* @param pVM The VM handle.
3907	* @param cr3 The root of the hierarchy.
3908	* @param cr4 The CR4, PSE is currently used.
3909	* @param PhysSearch Address to search for.
3910	*/
3911	VMMR3DECL(int) PGMR3DumpHierarchyGC(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCPHYS PhysSearch)
3912	{
3913	bool fLongMode = false;
3914	const unsigned cch = fLongMode ? 16 : 8; NOREF(cch);
3915	PX86PD pPD = 0;
3916
3917	int rc = PGM_GCPHYS_2_PTR(pVM, cr3 & X86_CR3_PAGE_MASK, &pPD);
3918	if (VBOX_FAILURE(rc) \|\| !pPD)
3919	{
3920	Log(("Page directory at %#x was not found in the page pool!\n", cr3 & X86_CR3_PAGE_MASK));
3921	return VERR_INVALID_PARAMETER;
3922	}
3923
3924	Log(("cr3=%08x cr4=%08x%s\n"
3925	"%-*s P - Present\n"
3926	"%-*s \| R/W - Read (0) / Write (1)\n"
3927	"%-*s \| \| U/S - User (1) / Supervisor (0)\n"
3928	"%-*s \| \| \| A - Accessed\n"
3929	"%-*s \| \| \| \| D - Dirty\n"
3930	"%-*s \| \| \| \| \| G - Global\n"
3931	"%-*s \| \| \| \| \| \| WT - Write thru\n"
3932	"%-*s \| \| \| \| \| \| \| CD - Cache disable\n"
3933	"%-*s \| \| \| \| \| \| \| \| AT - Attribute table (PAT)\n"
3934	"%-*s \| \| \| \| \| \| \| \| \| NX - No execute (K8)\n"
3935	"%-*s \| \| \| \| \| \| \| \| \| \| 4K/4M/2M - Page size.\n"
3936	"%-*s \| \| \| \| \| \| \| \| \| \| \| AVL - a=allocated; m=mapping; d=track dirty;\n"
3937	"%-*s \| \| \| \| \| \| \| \| \| \| \| \| p=permanent; v=validated;\n"
3938	"%-*s Level \| \| \| \| \| \| \| \| \| \| \| \| Page\n"
3939	/* xxxx n **** P R S A D G WT CD AT NX 4M AVL xxxxxxxxxxxxx
3940	- W U - - - -- -- -- -- -- 010 */
3941	, cr3, cr4, fLongMode ? " Long Mode" : "",
3942	cch, "", cch, "", cch, "", cch, "", cch, "", cch, "", cch, "",
3943	cch, "", cch, "", cch, "", cch, "", cch, "", cch, "", cch, "Address"));
3944
3945	for (unsigned i = 0; i < RT_ELEMENTS(pPD->a); i++)
3946	{
3947	X86PDE Pde = pPD->a[i];
3948	if (Pde.n.u1Present)
3949	{
3950	const uint32_t u32Address = i << X86_PD_SHIFT;
3951
3952	if ((cr4 & X86_CR4_PSE) && Pde.b.u1Size)
3953	Log(( /P R S A D G WT CD AT NX 4M a m d /
3954	"%08x 0 \| P %c %c %c %c %c %s %s %s .. 4M %c%c%c %08x\n",
3955	u32Address,
3956	Pde.b.u1Write ? 'W' : 'R',
3957	Pde.b.u1User ? 'U' : 'S',
3958	Pde.b.u1Accessed ? 'A' : '-',
3959	Pde.b.u1Dirty ? 'D' : '-',
3960	Pde.b.u1Global ? 'G' : '-',
3961	Pde.b.u1WriteThru ? "WT" : "--",
3962	Pde.b.u1CacheDisable? "CD" : "--",
3963	Pde.b.u1PAT ? "AT" : "--",
3964	Pde.u & RT_BIT(9) ? '1' : '0',
3965	Pde.u & RT_BIT(10) ? '1' : '0',
3966	Pde.u & RT_BIT(11) ? '1' : '0',
3967	pgmGstGet4MBPhysPage(&pVM->pgm.s, Pde)));
3968	/** @todo PhysSearch */
3969	else
3970	{
3971	Log(( /P R S A D G WT CD AT NX 4M a m d /
3972	"%08x 0 \| P %c %c %c %c %c %s %s .. .. 4K %c%c%c %08x\n",
3973	u32Address,
3974	Pde.n.u1Write ? 'W' : 'R',
3975	Pde.n.u1User ? 'U' : 'S',
3976	Pde.n.u1Accessed ? 'A' : '-',
3977	Pde.n.u1Reserved0 ? '?' : '.', /* ignored */
3978	Pde.n.u1Reserved1 ? '?' : '.', /* ignored */
3979	Pde.n.u1WriteThru ? "WT" : "--",
3980	Pde.n.u1CacheDisable? "CD" : "--",
3981	Pde.u & RT_BIT(9) ? '1' : '0',
3982	Pde.u & RT_BIT(10) ? '1' : '0',
3983	Pde.u & RT_BIT(11) ? '1' : '0',
3984	Pde.u & X86_PDE_PG_MASK));
3985	////if (cMaxDepth >= 1)
3986	{
3987	/** @todo what about using the page pool for mapping PTs? */
3988	RTGCPHYS GCPhys = Pde.u & X86_PDE_PG_MASK;
3989	PX86PT pPT = NULL;
3990
3991	rc = PGM_GCPHYS_2_PTR(pVM, GCPhys, &pPT);
3992
3993	int rc2 = VERR_INVALID_PARAMETER;
3994	if (pPT)
3995	rc2 = pgmR3DumpHierarchyGC32BitPT(pVM, pPT, u32Address, PhysSearch);
3996	else
3997	Log(("%08x error! Page table at %#x was not found in the page pool!\n", u32Address, GCPhys));
3998	if (rc2 < rc && VBOX_SUCCESS(rc))
3999	rc = rc2;
4000	}
4001	}
4002	}
4003	}
4004
4005	return rc;
4006	}
4007
4008
4009	/**
4010	* Dumps a page table hierarchy use only physical addresses and cr4/lm flags.
4011	*
4012	* @returns VBox status code (VINF_SUCCESS).
4013	* @param pVM The VM handle.
4014	* @param cr3 The root of the hierarchy.
4015	* @param cr4 The cr4, only PAE and PSE is currently used.
4016	* @param fLongMode Set if long mode, false if not long mode.
4017	* @param cMaxDepth Number of levels to dump.
4018	* @param pHlp Pointer to the output functions.
4019	*/
4020	VMMR3DECL(int) PGMR3DumpHierarchyHC(PVM pVM, uint64_t cr3, uint64_t cr4, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
4021	{
4022	if (!pHlp)
4023	pHlp = DBGFR3InfoLogHlp();
4024	if (!cMaxDepth)
4025	return VINF_SUCCESS;
4026	const unsigned cch = fLongMode ? 16 : 8;
4027	pHlp->pfnPrintf(pHlp,
4028	"cr3=%08x cr4=%08x%s\n"
4029	"%-*s P - Present\n"
4030	"%-*s \| R/W - Read (0) / Write (1)\n"
4031	"%-*s \| \| U/S - User (1) / Supervisor (0)\n"
4032	"%-*s \| \| \| A - Accessed\n"
4033	"%-*s \| \| \| \| D - Dirty\n"
4034	"%-*s \| \| \| \| \| G - Global\n"
4035	"%-*s \| \| \| \| \| \| WT - Write thru\n"
4036	"%-*s \| \| \| \| \| \| \| CD - Cache disable\n"
4037	"%-*s \| \| \| \| \| \| \| \| AT - Attribute table (PAT)\n"
4038	"%-*s \| \| \| \| \| \| \| \| \| NX - No execute (K8)\n"
4039	"%-*s \| \| \| \| \| \| \| \| \| \| 4K/4M/2M - Page size.\n"
4040	"%-*s \| \| \| \| \| \| \| \| \| \| \| AVL - a=allocated; m=mapping; d=track dirty;\n"
4041	"%-*s \| \| \| \| \| \| \| \| \| \| \| \| p=permanent; v=validated;\n"
4042	"%-*s Level \| \| \| \| \| \| \| \| \| \| \| \| Page\n"
4043	/* xxxx n **** P R S A D G WT CD AT NX 4M AVL xxxxxxxxxxxxx
4044	- W U - - - -- -- -- -- -- 010 */
4045	, cr3, cr4, fLongMode ? " Long Mode" : "",
4046	cch, "", cch, "", cch, "", cch, "", cch, "", cch, "", cch, "",
4047	cch, "", cch, "", cch, "", cch, "", cch, "", cch, "", cch, "Address");
4048	if (cr4 & X86_CR4_PAE)
4049	{
4050	if (fLongMode)
4051	return pgmR3DumpHierarchyHcPaePML4(pVM, cr3 & X86_CR3_PAGE_MASK, cr4, cMaxDepth, pHlp);
4052	return pgmR3DumpHierarchyHCPaePDPT(pVM, cr3 & X86_CR3_PAE_PAGE_MASK, 0, cr4, false, cMaxDepth, pHlp);
4053	}
4054	return pgmR3DumpHierarchyHC32BitPD(pVM, cr3 & X86_CR3_PAGE_MASK, cr4, cMaxDepth, pHlp);
4055	}
4056
4057
4058
4059	#ifdef VBOX_WITH_DEBUGGER
4060	/**
4061	* The '.pgmram' command.
4062	*
4063	* @returns VBox status.
4064	* @param pCmd Pointer to the command descriptor (as registered).
4065	* @param pCmdHlp Pointer to command helper functions.
4066	* @param pVM Pointer to the current VM (if any).
4067	* @param paArgs Pointer to (readonly) array of arguments.
4068	* @param cArgs Number of arguments in the array.
4069	*/
4070	static DECLCALLBACK(int) pgmR3CmdRam(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4071	{
4072	/*
4073	* Validate input.
4074	*/
4075	if (!pVM)
4076	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4077	if (!pVM->pgm.s.pRamRangesRC)
4078	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Sorry, no Ram is registered.\n");
4079
4080	/*
4081	* Dump the ranges.
4082	*/
4083	int rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL, "From - To (incl) pvHC\n");
4084	PPGMRAMRANGE pRam;
4085	for (pRam = pVM->pgm.s.pRamRangesR3; pRam; pRam = pRam->pNextR3)
4086	{
4087	rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL,
4088	"%RGp - %RGp %p\n",
4089	pRam->GCPhys, pRam->GCPhysLast, pRam->pvR3);
4090	if (VBOX_FAILURE(rc))
4091	return rc;
4092	}
4093
4094	return VINF_SUCCESS;
4095	}
4096
4097
4098	/**
4099	* The '.pgmmap' command.
4100	*
4101	* @returns VBox status.
4102	* @param pCmd Pointer to the command descriptor (as registered).
4103	* @param pCmdHlp Pointer to command helper functions.
4104	* @param pVM Pointer to the current VM (if any).
4105	* @param paArgs Pointer to (readonly) array of arguments.
4106	* @param cArgs Number of arguments in the array.
4107	*/
4108	static DECLCALLBACK(int) pgmR3CmdMap(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4109	{
4110	/*
4111	* Validate input.
4112	*/
4113	if (!pVM)
4114	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4115	if (!pVM->pgm.s.pMappingsR3)
4116	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Sorry, no mappings are registered.\n");
4117
4118	/*
4119	* Print message about the fixedness of the mappings.
4120	*/
4121	int rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL, pVM->pgm.s.fMappingsFixed ? "The mappings are FIXED.\n" : "The mappings are FLOATING.\n");
4122	if (VBOX_FAILURE(rc))
4123	return rc;
4124
4125	/*
4126	* Dump the ranges.
4127	*/
4128	PPGMMAPPING pCur;
4129	for (pCur = pVM->pgm.s.pMappingsR3; pCur; pCur = pCur->pNextR3)
4130	{
4131	rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL,
4132	"%08x - %08x %s\n",
4133	pCur->GCPtr, pCur->GCPtrLast, pCur->pszDesc);
4134	if (VBOX_FAILURE(rc))
4135	return rc;
4136	}
4137
4138	return VINF_SUCCESS;
4139	}
4140
4141
4142	/**
4143	* The '.pgmsync' command.
4144	*
4145	* @returns VBox status.
4146	* @param pCmd Pointer to the command descriptor (as registered).
4147	* @param pCmdHlp Pointer to command helper functions.
4148	* @param pVM Pointer to the current VM (if any).
4149	* @param paArgs Pointer to (readonly) array of arguments.
4150	* @param cArgs Number of arguments in the array.
4151	*/
4152	static DECLCALLBACK(int) pgmR3CmdSync(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4153	{
4154	/*
4155	* Validate input.
4156	*/
4157	if (!pVM)
4158	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4159
4160	/*
4161	* Force page directory sync.
4162	*/
4163	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
4164
4165	int rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Forcing page directory sync.\n");
4166	if (VBOX_FAILURE(rc))
4167	return rc;
4168
4169	return VINF_SUCCESS;
4170	}
4171
4172
4173	#ifdef VBOX_STRICT
4174	/**
4175	* The '.pgmassertcr3' command.
4176	*
4177	* @returns VBox status.
4178	* @param pCmd Pointer to the command descriptor (as registered).
4179	* @param pCmdHlp Pointer to command helper functions.
4180	* @param pVM Pointer to the current VM (if any).
4181	* @param paArgs Pointer to (readonly) array of arguments.
4182	* @param cArgs Number of arguments in the array.
4183	*/
4184	static DECLCALLBACK(int) pgmR3CmdAssertCR3(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4185	{
4186	/*
4187	* Validate input.
4188	*/
4189	if (!pVM)
4190	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4191
4192	int rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Checking shadow CR3 page tables for consistency.\n");
4193	if (VBOX_FAILURE(rc))
4194	return rc;
4195
4196	PGMAssertCR3(pVM, CPUMGetGuestCR3(pVM), CPUMGetGuestCR4(pVM));
4197
4198	return VINF_SUCCESS;
4199	}
4200	#endif
4201
4202	/**
4203	* The '.pgmsyncalways' command.
4204	*
4205	* @returns VBox status.
4206	* @param pCmd Pointer to the command descriptor (as registered).
4207	* @param pCmdHlp Pointer to command helper functions.
4208	* @param pVM Pointer to the current VM (if any).
4209	* @param paArgs Pointer to (readonly) array of arguments.
4210	* @param cArgs Number of arguments in the array.
4211	*/
4212	static DECLCALLBACK(int) pgmR3CmdSyncAlways(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4213	{
4214	/*
4215	* Validate input.
4216	*/
4217	if (!pVM)
4218	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4219
4220	/*
4221	* Force page directory sync.
4222	*/
4223	if (pVM->pgm.s.fSyncFlags & PGM_SYNC_ALWAYS)
4224	{
4225	ASMAtomicAndU32(&pVM->pgm.s.fSyncFlags, ~PGM_SYNC_ALWAYS);
4226	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Disabled permanent forced page directory syncing.\n");
4227	}
4228	else
4229	{
4230	ASMAtomicOrU32(&pVM->pgm.s.fSyncFlags, PGM_SYNC_ALWAYS);
4231	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
4232	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Enabled permanent forced page directory syncing.\n");
4233	}
4234	}
4235
4236	#endif
4237
4238	/**
4239	* pvUser argument of the pgmR3CheckIntegrity*Node callbacks.
4240	*/
4241	typedef struct PGMCHECKINTARGS
4242	{
4243	bool fLeftToRight; /*< true: left-to-right; false: right-to-left. /
4244	PPGMPHYSHANDLER pPrevPhys;
4245	PPGMVIRTHANDLER pPrevVirt;
4246	PPGMPHYS2VIRTHANDLER pPrevPhys2Virt;
4247	PVM pVM;
4248	} PGMCHECKINTARGS, *PPGMCHECKINTARGS;
4249
4250	/**
4251	* Validate a node in the physical handler tree.
4252	*
4253	* @returns 0 on if ok, other wise 1.
4254	* @param pNode The handler node.
4255	* @param pvUser pVM.
4256	*/
4257	static DECLCALLBACK(int) pgmR3CheckIntegrityPhysHandlerNode(PAVLROGCPHYSNODECORE pNode, void *pvUser)
4258	{
4259	PPGMCHECKINTARGS pArgs = (PPGMCHECKINTARGS)pvUser;
4260	PPGMPHYSHANDLER pCur = (PPGMPHYSHANDLER)pNode;
4261	AssertReleaseReturn(!((uintptr_t)pCur & 7), 1);
4262	AssertReleaseMsg(pCur->Core.Key <= pCur->Core.KeyLast,("pCur=%p %VGp-%VGp %s\n", pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
4263	AssertReleaseMsg( !pArgs->pPrevPhys
4264	\|\| (pArgs->fLeftToRight ? pArgs->pPrevPhys->Core.KeyLast < pCur->Core.Key : pArgs->pPrevPhys->Core.KeyLast > pCur->Core.Key),
4265	("pPrevPhys=%p %VGp-%VGp %s\n"
4266	" pCur=%p %VGp-%VGp %s\n",
4267	pArgs->pPrevPhys, pArgs->pPrevPhys->Core.Key, pArgs->pPrevPhys->Core.KeyLast, pArgs->pPrevPhys->pszDesc,
4268	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
4269	pArgs->pPrevPhys = pCur;
4270	return 0;
4271	}
4272
4273
4274	/**
4275	* Validate a node in the virtual handler tree.
4276	*
4277	* @returns 0 on if ok, other wise 1.
4278	* @param pNode The handler node.
4279	* @param pvUser pVM.
4280	*/
4281	static DECLCALLBACK(int) pgmR3CheckIntegrityVirtHandlerNode(PAVLROGCPTRNODECORE pNode, void *pvUser)
4282	{
4283	PPGMCHECKINTARGS pArgs = (PPGMCHECKINTARGS)pvUser;
4284	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)pNode;
4285	AssertReleaseReturn(!((uintptr_t)pCur & 7), 1);
4286	AssertReleaseMsg(pCur->Core.Key <= pCur->Core.KeyLast,("pCur=%p %VGv-%VGv %s\n", pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
4287	AssertReleaseMsg( !pArgs->pPrevVirt
4288	\|\| (pArgs->fLeftToRight ? pArgs->pPrevVirt->Core.KeyLast < pCur->Core.Key : pArgs->pPrevVirt->Core.KeyLast > pCur->Core.Key),
4289	("pPrevVirt=%p %VGv-%VGv %s\n"
4290	" pCur=%p %VGv-%VGv %s\n",
4291	pArgs->pPrevVirt, pArgs->pPrevVirt->Core.Key, pArgs->pPrevVirt->Core.KeyLast, pArgs->pPrevVirt->pszDesc,
4292	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
4293	for (unsigned iPage = 0; iPage < pCur->cPages; iPage++)
4294	{
4295	AssertReleaseMsg(pCur->aPhysToVirt[iPage].offVirtHandler == -RT_OFFSETOF(PGMVIRTHANDLER, aPhysToVirt[iPage]),
4296	("pCur=%p %VGv-%VGv %s\n"
4297	"iPage=%d offVirtHandle=%#x expected %#x\n",
4298	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc,
4299	iPage, pCur->aPhysToVirt[iPage].offVirtHandler, -RT_OFFSETOF(PGMVIRTHANDLER, aPhysToVirt[iPage])));
4300	}
4301	pArgs->pPrevVirt = pCur;
4302	return 0;
4303	}
4304
4305
4306	/**
4307	* Validate a node in the virtual handler tree.
4308	*
4309	* @returns 0 on if ok, other wise 1.
4310	* @param pNode The handler node.
4311	* @param pvUser pVM.
4312	*/
4313	static DECLCALLBACK(int) pgmR3CheckIntegrityPhysToVirtHandlerNode(PAVLROGCPHYSNODECORE pNode, void *pvUser)
4314	{
4315	PPGMCHECKINTARGS pArgs = (PPGMCHECKINTARGS)pvUser;
4316	PPGMPHYS2VIRTHANDLER pCur = (PPGMPHYS2VIRTHANDLER)pNode;
4317	AssertReleaseMsgReturn(!((uintptr_t)pCur & 3), ("\n"), 1);
4318	AssertReleaseMsgReturn(!(pCur->offVirtHandler & 3), ("\n"), 1);
4319	AssertReleaseMsg(pCur->Core.Key <= pCur->Core.KeyLast,("pCur=%p %VGp-%VGp\n", pCur, pCur->Core.Key, pCur->Core.KeyLast));
4320	AssertReleaseMsg( !pArgs->pPrevPhys2Virt
4321	\|\| (pArgs->fLeftToRight ? pArgs->pPrevPhys2Virt->Core.KeyLast < pCur->Core.Key : pArgs->pPrevPhys2Virt->Core.KeyLast > pCur->Core.Key),
4322	("pPrevPhys2Virt=%p %VGp-%VGp\n"
4323	" pCur=%p %VGp-%VGp\n",
4324	pArgs->pPrevPhys2Virt, pArgs->pPrevPhys2Virt->Core.Key, pArgs->pPrevPhys2Virt->Core.KeyLast,
4325	pCur, pCur->Core.Key, pCur->Core.KeyLast));
4326	AssertReleaseMsg( !pArgs->pPrevPhys2Virt
4327	\|\| (pArgs->fLeftToRight ? pArgs->pPrevPhys2Virt->Core.KeyLast < pCur->Core.Key : pArgs->pPrevPhys2Virt->Core.KeyLast > pCur->Core.Key),
4328	("pPrevPhys2Virt=%p %VGp-%VGp\n"
4329	" pCur=%p %VGp-%VGp\n",
4330	pArgs->pPrevPhys2Virt, pArgs->pPrevPhys2Virt->Core.Key, pArgs->pPrevPhys2Virt->Core.KeyLast,
4331	pCur, pCur->Core.Key, pCur->Core.KeyLast));
4332	AssertReleaseMsg((pCur->offNextAlias & (PGMPHYS2VIRTHANDLER_IN_TREE \| PGMPHYS2VIRTHANDLER_IS_HEAD)) == (PGMPHYS2VIRTHANDLER_IN_TREE \| PGMPHYS2VIRTHANDLER_IS_HEAD),
4333	("pCur=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4334	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias));
4335	if (pCur->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK)
4336	{
4337	PPGMPHYS2VIRTHANDLER pCur2 = pCur;
4338	for (;;)
4339	{
4340	pCur2 = (PPGMPHYS2VIRTHANDLER)((intptr_t)pCur + (pCur->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK));
4341	AssertReleaseMsg(pCur2 != pCur,
4342	(" pCur=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4343	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias));
4344	AssertReleaseMsg((pCur2->offNextAlias & (PGMPHYS2VIRTHANDLER_IN_TREE \| PGMPHYS2VIRTHANDLER_IS_HEAD)) == PGMPHYS2VIRTHANDLER_IN_TREE,
4345	(" pCur=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
4346	"pCur2=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4347	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias,
4348	pCur2, pCur2->Core.Key, pCur2->Core.KeyLast, pCur2->offVirtHandler, pCur2->offNextAlias));
4349	AssertReleaseMsg((pCur2->Core.Key ^ pCur->Core.Key) < PAGE_SIZE,
4350	(" pCur=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
4351	"pCur2=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4352	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias,
4353	pCur2, pCur2->Core.Key, pCur2->Core.KeyLast, pCur2->offVirtHandler, pCur2->offNextAlias));
4354	AssertReleaseMsg((pCur2->Core.KeyLast ^ pCur->Core.KeyLast) < PAGE_SIZE,
4355	(" pCur=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
4356	"pCur2=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4357	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias,
4358	pCur2, pCur2->Core.Key, pCur2->Core.KeyLast, pCur2->offVirtHandler, pCur2->offNextAlias));
4359	if (!(pCur2->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK))
4360	break;
4361	}
4362	}
4363
4364	pArgs->pPrevPhys2Virt = pCur;
4365	return 0;
4366	}
4367
4368
4369	/**
4370	* Perform an integrity check on the PGM component.
4371	*
4372	* @returns VINF_SUCCESS if everything is fine.
4373	* @returns VBox error status after asserting on integrity breach.
4374	* @param pVM The VM handle.
4375	*/
4376	VMMR3DECL(int) PGMR3CheckIntegrity(PVM pVM)
4377	{
4378	AssertReleaseReturn(pVM->pgm.s.offVM, VERR_INTERNAL_ERROR);
4379
4380	/*
4381	* Check the trees.
4382	*/
4383	int cErrors = 0;
4384	const static PGMCHECKINTARGS s_LeftToRight = { true, NULL, NULL, NULL, pVM };
4385	const static PGMCHECKINTARGS s_RightToLeft = { false, NULL, NULL, NULL, pVM };
4386	PGMCHECKINTARGS Args = s_LeftToRight;
4387	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysHandlers, true, pgmR3CheckIntegrityPhysHandlerNode, &Args);
4388	Args = s_RightToLeft;
4389	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysHandlers, false, pgmR3CheckIntegrityPhysHandlerNode, &Args);
4390	Args = s_LeftToRight;
4391	cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesR3->VirtHandlers, true, pgmR3CheckIntegrityVirtHandlerNode, &Args);
4392	Args = s_RightToLeft;
4393	cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesR3->VirtHandlers, false, pgmR3CheckIntegrityVirtHandlerNode, &Args);
4394	Args = s_LeftToRight;
4395	cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesR3->HyperVirtHandlers, true, pgmR3CheckIntegrityVirtHandlerNode, &Args);
4396	Args = s_RightToLeft;
4397	cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesR3->HyperVirtHandlers, false, pgmR3CheckIntegrityVirtHandlerNode, &Args);
4398	Args = s_LeftToRight;
4399	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysToVirtHandlers, true, pgmR3CheckIntegrityPhysToVirtHandlerNode, &Args);
4400	Args = s_RightToLeft;
4401	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysToVirtHandlers, false, pgmR3CheckIntegrityPhysToVirtHandlerNode, &Args);
4402
4403	return !cErrors ? VINF_SUCCESS : VERR_INTERNAL_ERROR;
4404	}
4405
4406
4407	/**
4408	* Inform PGM if we want all mappings to be put into the shadow page table. (necessary for e.g. VMX)
4409	*
4410	* @returns VBox status code.
4411	* @param pVM VM handle.
4412	* @param fEnable Enable or disable shadow mappings
4413	*/
4414	VMMR3DECL(int) PGMR3ChangeShwPDMappings(PVM pVM, bool fEnable)
4415	{
4416	pVM->pgm.s.fDisableMappings = !fEnable;
4417
4418	uint32_t cb;
4419	int rc = PGMR3MappingsSize(pVM, &cb);
4420	AssertRCReturn(rc, rc);
4421
4422	/* Pretend the mappings are now fixed; to force a refresh of the reserved PDEs. */
4423	rc = PGMR3MappingsFix(pVM, MM_HYPER_AREA_ADDRESS, cb);
4424	AssertRCReturn(rc, rc);
4425
4426	return VINF_SUCCESS;
4427	}

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source: vbox/trunk/src/VBox/VMM/PGM.cpp@ 13106

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