PGM.cpp@ 13187

Last change on this file since 13187 was 13187, checked in by vboxsync, 16 years ago
PGMR3InitDynMap: check that the dynamic mapping area doesn't cross a 2MB (PAE PT) boundrary instead of 4MB (legacy PT). (ancient todo)
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1	/* $Id: PGM.cpp 13187 2008-10-10 23:18:46Z vboxsync $ */
2	/** @file
3	* PGM - Page Manager and Monitor. (Mixing stuff here, not good?)
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22
23	/** @page pg_pgm PGM - The Page Manager and Monitor
24	*
25	* @see grp_pgm,
26	* @ref pg_pgm_pool,
27	* @ref pg_pgm_phys.
28	*
29	*
30	* @section sec_pgm_modes Paging Modes
31	*
32	* There are three memory contexts: Host Context (HC), Guest Context (GC)
33	* and intermediate context. When talking about paging HC can also be refered to
34	* as "host paging", and GC refered to as "shadow paging".
35	*
36	* We define three basic paging modes: 32-bit, PAE and AMD64. The host paging mode
37	* is defined by the host operating system. The mode used in the shadow paging mode
38	* depends on the host paging mode and what the mode the guest is currently in. The
39	* following relation between the two is defined:
40	*
41	* @verbatim
42	Host > 32-bit \| PAE \| AMD64 \|
43	Guest \| \| \| \|
44	==v================================
45	32-bit 32-bit PAE PAE
46	-------\|--------\|--------\|--------\|
47	PAE PAE PAE PAE
48	-------\|--------\|--------\|--------\|
49	AMD64 AMD64 AMD64 AMD64
50	-------\|--------\|--------\|--------\| @endverbatim
51	*
52	* All configuration except those in the diagonal (upper left) are expected to
53	* require special effort from the switcher (i.e. a bit slower).
54	*
55	*
56	*
57	*
58	* @section sec_pgm_shw The Shadow Memory Context
59	*
60	*
61	* [..]
62	*
63	* Because of guest context mappings requires PDPT and PML4 entries to allow
64	* writing on AMD64, the two upper levels will have fixed flags whatever the
65	* guest is thinking of using there. So, when shadowing the PD level we will
66	* calculate the effective flags of PD and all the higher levels. In legacy
67	* PAE mode this only applies to the PWT and PCD bits (the rest are
68	* ignored/reserved/MBZ). We will ignore those bits for the present.
69	*
70	*
71	*
72	* @section sec_pgm_int The Intermediate Memory Context
73	*
74	* The world switch goes thru an intermediate memory context which purpose it is
75	* to provide different mappings of the switcher code. All guest mappings are also
76	* present in this context.
77	*
78	* The switcher code is mapped at the same location as on the host, at an
79	* identity mapped location (physical equals virtual address), and at the
80	* hypervisor location.
81	*
82	* PGM maintain page tables for 32-bit, PAE and AMD64 paging modes. This
83	* simplifies switching guest CPU mode and consistency at the cost of more
84	* code to do the work. All memory use for those page tables is located below
85	* 4GB (this includes page tables for guest context mappings).
86	*
87	*
88	* @subsection subsec_pgm_int_gc Guest Context Mappings
89	*
90	* During assignment and relocation of a guest context mapping the intermediate
91	* memory context is used to verify the new location.
92	*
93	* Guest context mappings are currently restricted to below 4GB, for reasons
94	* of simplicity. This may change when we implement AMD64 support.
95	*
96	*
97	*
98	*
99	* @section sec_pgm_misc Misc
100	*
101	* @subsection subsec_pgm_misc_diff Differences Between Legacy PAE and Long Mode PAE
102	*
103	* The differences between legacy PAE and long mode PAE are:
104	* -# PDPE bits 1, 2, 5 and 6 are defined differently. In leagcy mode they are
105	* all marked down as must-be-zero, while in long mode 1, 2 and 5 have the
106	* usual meanings while 6 is ignored (AMD). This means that upon switching to
107	* legacy PAE mode we'll have to clear these bits and when going to long mode
108	* they must be set. This applies to both intermediate and shadow contexts,
109	* however we don't need to do it for the intermediate one since we're
110	* executing with CR0.WP at that time.
111	* -# CR3 allows a 32-byte aligned address in legacy mode, while in long mode
112	* a page aligned one is required.
113	*
114	*
115	* @section sec_pgm_handlers Access Handlers
116	*
117	* Placeholder.
118	*
119	*
120	* @subsection sec_pgm_handlers_virt Virtual Access Handlers
121	*
122	* Placeholder.
123	*
124	*
125	* @subsection sec_pgm_handlers_virt Virtual Access Handlers
126	*
127	* We currently implement three types of virtual access handlers: ALL, WRITE
128	* and HYPERVISOR (WRITE). See PGMVIRTHANDLERTYPE for some more details.
129	*
130	* The HYPERVISOR access handlers is kept in a separate tree since it doesn't apply
131	* to physical pages (PGMTREES::HyperVirtHandlers) and only needs to be consulted in
132	* a special \#PF case. The ALL and WRITE are in the PGMTREES::VirtHandlers tree, the
133	* rest of this section is going to be about these handlers.
134	*
135	* We'll go thru the life cycle of a handler and try make sense of it all, don't know
136	* how successfull this is gonna be...
137	*
138	* 1. A handler is registered thru the PGMR3HandlerVirtualRegister and
139	* PGMHandlerVirtualRegisterEx APIs. We check for conflicting virtual handlers
140	* and create a new node that is inserted into the AVL tree (range key). Then
141	* a full PGM resync is flagged (clear pool, sync cr3, update virtual bit of PGMPAGE).
142	*
143	* 2. The following PGMSyncCR3/SyncCR3 operation will first make invoke HandlerVirtualUpdate.
144	*
145	* 2a. HandlerVirtualUpdate will will lookup all the pages covered by virtual handlers
146	* via the current guest CR3 and update the physical page -> virtual handler
147	* translation. Needless to say, this doesn't exactly scale very well. If any changes
148	* are detected, it will flag a virtual bit update just like we did on registration.
149	* PGMPHYS pages with changes will have their virtual handler state reset to NONE.
150	*
151	* 2b. The virtual bit update process will iterate all the pages covered by all the
152	* virtual handlers and update the PGMPAGE virtual handler state to the max of all
153	* virtual handlers on that page.
154	*
155	* 2c. Back in SyncCR3 we will now flush the entire shadow page cache to make sure
156	* we don't miss any alias mappings of the monitored pages.
157	*
158	* 2d. SyncCR3 will then proceed with syncing the CR3 table.
159	*
160	* 3. \#PF(np,read) on a page in the range. This will cause it to be synced
161	* read-only and resumed if it's a WRITE handler. If it's an ALL handler we
162	* will call the handlers like in the next step. If the physical mapping has
163	* changed we will - some time in the future - perform a handler callback
164	* (optional) and update the physical -> virtual handler cache.
165	*
166	* 4. \#PF(,write) on a page in the range. This will cause the handler to
167	* be invoked.
168	*
169	* 5. The guest invalidates the page and changes the physical backing or
170	* unmaps it. This should cause the invalidation callback to be invoked
171	* (it might not yet be 100% perfect). Exactly what happens next... is
172	* this where we mess up and end up out of sync for a while?
173	*
174	* 6. The handler is deregistered by the client via PGMHandlerVirtualDeregister.
175	* We will then set all PGMPAGEs in the physical -> virtual handler cache for
176	* this handler to NONE and trigger a full PGM resync (basically the same
177	* as int step 1). Which means 2 is executed again.
178	*
179	*
180	* @subsubsection sub_sec_pgm_handler_virt_todo TODOs
181	*
182	* There is a bunch of things that needs to be done to make the virtual handlers
183	* work 100% correctly and work more efficiently.
184	*
185	* The first bit hasn't been implemented yet because it's going to slow the
186	* whole mess down even more, and besides it seems to be working reliably for
187	* our current uses. OTOH, some of the optimizations might end up more or less
188	* implementing the missing bits, so we'll see.
189	*
190	* On the optimization side, the first thing to do is to try avoid unnecessary
191	* cache flushing. Then try team up with the shadowing code to track changes
192	* in mappings by means of access to them (shadow in), updates to shadows pages,
193	* invlpg, and shadow PT discarding (perhaps).
194	*
195	* Some idea that have popped up for optimization for current and new features:
196	* - bitmap indicating where there are virtual handlers installed.
197	* (4KB => 220 pages, page 212 => covers 32-bit address space 1:1!)
198	* - Further optimize this by min/max (needs min/max avl getters).
199	* - Shadow page table entry bit (if any left)?
200	*
201	*/
202
203
204	/** @page pg_pgm_phys PGM Physical Guest Memory Management
205	*
206	*
207	* Objectives:
208	* - Guest RAM over-commitment using memory ballooning,
209	* zero pages and general page sharing.
210	* - Moving or mirroring a VM onto a different physical machine.
211	*
212	*
213	* @subsection subsec_pgmPhys_Definitions Definitions
214	*
215	* Allocation chunk - A RTR0MemObjAllocPhysNC object and the tracking
216	* machinery assoicated with it.
217	*
218	*
219	*
220	*
221	* @subsection subsec_pgmPhys_AllocPage Allocating a page.
222	*
223	* Initially we map all guest memory to the (per VM) zero page, which
224	* means that none of the read functions will cause pages to be allocated.
225	*
226	* Exception, access bit in page tables that have been shared. This must
227	* be handled, but we must also make sure PGMGst*Modify doesn't make
228	* unnecessary modifications.
229	*
230	* Allocation points:
231	* - PGMPhysSimpleWriteGCPhys and PGMPhysWrite.
232	* - Replacing a zero page mapping at \#PF.
233	* - Replacing a shared page mapping at \#PF.
234	* - ROM registration (currently MMR3RomRegister).
235	* - VM restore (pgmR3Load).
236	*
237	* For the first three it would make sense to keep a few pages handy
238	* until we've reached the max memory commitment for the VM.
239	*
240	* For the ROM registration, we know exactly how many pages we need
241	* and will request these from ring-0. For restore, we will save
242	* the number of non-zero pages in the saved state and allocate
243	* them up front. This would allow the ring-0 component to refuse
244	* the request if the isn't sufficient memory available for VM use.
245	*
246	* Btw. for both ROM and restore allocations we won't be requiring
247	* zeroed pages as they are going to be filled instantly.
248	*
249	*
250	* @subsection subsec_pgmPhys_FreePage Freeing a page
251	*
252	* There are a few points where a page can be freed:
253	* - After being replaced by the zero page.
254	* - After being replaced by a shared page.
255	* - After being ballooned by the guest additions.
256	* - At reset.
257	* - At restore.
258	*
259	* When freeing one or more pages they will be returned to the ring-0
260	* component and replaced by the zero page.
261	*
262	* The reasoning for clearing out all the pages on reset is that it will
263	* return us to the exact same state as on power on, and may thereby help
264	* us reduce the memory load on the system. Further it might have a
265	* (temporary) positive influence on memory fragmentation (@see subsec_pgmPhys_Fragmentation).
266	*
267	* On restore, as mention under the allocation topic, pages should be
268	* freed / allocated depending on how many is actually required by the
269	* new VM state. The simplest approach is to do like on reset, and free
270	* all non-ROM pages and then allocate what we need.
271	*
272	* A measure to prevent some fragmentation, would be to let each allocation
273	* chunk have some affinity towards the VM having allocated the most pages
274	* from it. Also, try make sure to allocate from allocation chunks that
275	* are almost full. Admittedly, both these measures might work counter to
276	* our intentions and its probably not worth putting a lot of effort,
277	* cpu time or memory into this.
278	*
279	*
280	* @subsection subsec_pgmPhys_SharePage Sharing a page
281	*
282	* The basic idea is that there there will be a idle priority kernel
283	* thread walking the non-shared VM pages hashing them and looking for
284	* pages with the same checksum. If such pages are found, it will compare
285	* them byte-by-byte to see if they actually are identical. If found to be
286	* identical it will allocate a shared page, copy the content, check that
287	* the page didn't change while doing this, and finally request both the
288	* VMs to use the shared page instead. If the page is all zeros (special
289	* checksum and byte-by-byte check) it will request the VM that owns it
290	* to replace it with the zero page.
291	*
292	* To make this efficient, we will have to make sure not to try share a page
293	* that will change its contents soon. This part requires the most work.
294	* A simple idea would be to request the VM to write monitor the page for
295	* a while to make sure it isn't modified any time soon. Also, it may
296	* make sense to skip pages that are being write monitored since this
297	* information is readily available to the thread if it works on the
298	* per-VM guest memory structures (presently called PGMRAMRANGE).
299	*
300	*
301	* @subsection subsec_pgmPhys_Fragmentation Fragmentation Concerns and Counter Measures
302	*
303	* The pages are organized in allocation chunks in ring-0, this is a necessity
304	* if we wish to have an OS agnostic approach to this whole thing. (On Linux we
305	* could easily work on a page-by-page basis if we liked. Whether this is possible
306	* or efficient on NT I don't quite know.) Fragmentation within these chunks may
307	* become a problem as part of the idea here is that we wish to return memory to
308	* the host system.
309	*
310	* For instance, starting two VMs at the same time, they will both allocate the
311	* guest memory on-demand and if permitted their page allocations will be
312	* intermixed. Shut down one of the two VMs and it will be difficult to return
313	* any memory to the host system because the page allocation for the two VMs are
314	* mixed up in the same allocation chunks.
315	*
316	* To further complicate matters, when pages are freed because they have been
317	* ballooned or become shared/zero the whole idea is that the page is supposed
318	* to be reused by another VM or returned to the host system. This will cause
319	* allocation chunks to contain pages belonging to different VMs and prevent
320	* returning memory to the host when one of those VM shuts down.
321	*
322	* The only way to really deal with this problem is to move pages. This can
323	* either be done at VM shutdown and or by the idle priority worker thread
324	* that will be responsible for finding sharable/zero pages. The mechanisms
325	* involved for coercing a VM to move a page (or to do it for it) will be
326	* the same as when telling it to share/zero a page.
327	*
328	*
329	* @subsection subsec_pgmPhys_Tracking Tracking Structures And Their Cost
330	*
331	* There's a difficult balance between keeping the per-page tracking structures
332	* (global and guest page) easy to use and keeping them from eating too much
333	* memory. We have limited virtual memory resources available when operating in
334	* 32-bit kernel space (on 64-bit there'll it's quite a different story). The
335	* tracking structures will be attemted designed such that we can deal with up
336	* to 32GB of memory on a 32-bit system and essentially unlimited on 64-bit ones.
337	*
338	*
339	* @subsubsection subsubsec_pgmPhys_Tracking_Kernel Kernel Space
340	*
341	* @see pg_GMM
342	*
343	* @subsubsection subsubsec_pgmPhys_Tracking_PerVM Per-VM
344	*
345	* Fixed info is the physical address of the page (HCPhys) and the page id
346	* (described above). Theoretically we'll need 48(-12) bits for the HCPhys part.
347	* Today we've restricting ourselves to 40(-12) bits because this is the current
348	* restrictions of all AMD64 implementations (I think Barcelona will up this
349	* to 48(-12) bits, not that it really matters) and I needed the bits for
350	* tracking mappings of a page. 48-12 = 36. That leaves 28 bits, which means a
351	* decent range for the page id: 2^(28+12) = 1024TB.
352	*
353	* In additions to these, we'll have to keep maintaining the page flags as we
354	* currently do. Although it wouldn't harm to optimize these quite a bit, like
355	* for instance the ROM shouldn't depend on having a write handler installed
356	* in order for it to become read-only. A RO/RW bit should be considered so
357	* that the page syncing code doesn't have to mess about checking multiple
358	* flag combinations (ROM \|\| RW handler \|\| write monitored) in order to
359	* figure out how to setup a shadow PTE. But this of course, is second
360	* priority at present. Current this requires 12 bits, but could probably
361	* be optimized to ~8.
362	*
363	* Then there's the 24 bits used to track which shadow page tables are
364	* currently mapping a page for the purpose of speeding up physical
365	* access handlers, and thereby the page pool cache. More bit for this
366	* purpose wouldn't hurt IIRC.
367	*
368	* Then there is a new bit in which we need to record what kind of page
369	* this is, shared, zero, normal or write-monitored-normal. This'll
370	* require 2 bits. One bit might be needed for indicating whether a
371	* write monitored page has been written to. And yet another one or
372	* two for tracking migration status. 3-4 bits total then.
373	*
374	* Whatever is left will can be used to record the sharabilitiy of a
375	* page. The page checksum will not be stored in the per-VM table as
376	* the idle thread will not be permitted to do modifications to it.
377	* It will instead have to keep its own working set of potentially
378	* shareable pages and their check sums and stuff.
379	*
380	* For the present we'll keep the current packing of the
381	* PGMRAMRANGE::aHCPhys to keep the changes simple, only of course,
382	* we'll have to change it to a struct with a total of 128-bits at
383	* our disposal.
384	*
385	* The initial layout will be like this:
386	* @verbatim
387	RTHCPHYS HCPhys; The current stuff.
388	63:40 Current shadow PT tracking stuff.
389	39:12 The physical page frame number.
390	11:0 The current flags.
391	uint32_t u28PageId : 28; The page id.
392	uint32_t u2State : 2; The page state { zero, shared, normal, write monitored }.
393	uint32_t fWrittenTo : 1; Whether a write monitored page was written to.
394	uint32_t u1Reserved : 1; Reserved for later.
395	uint32_t u32Reserved; Reserved for later, mostly sharing stats.
396	@endverbatim
397	*
398	* The final layout will be something like this:
399	* @verbatim
400	RTHCPHYS HCPhys; The current stuff.
401	63:48 High page id (12+).
402	47:12 The physical page frame number.
403	11:0 Low page id.
404	uint32_t fReadOnly : 1; Whether it's readonly page (rom or monitored in some way).
405	uint32_t u3Type : 3; The page type {RESERVED, MMIO, MMIO2, ROM, shadowed ROM, RAM}.
406	uint32_t u2PhysMon : 2; Physical access handler type {none, read, write, all}.
407	uint32_t u2VirtMon : 2; Virtual access handler type {none, read, write, all}..
408	uint32_t u2State : 2; The page state { zero, shared, normal, write monitored }.
409	uint32_t fWrittenTo : 1; Whether a write monitored page was written to.
410	uint32_t u20Reserved : 20; Reserved for later, mostly sharing stats.
411	uint32_t u32Tracking; The shadow PT tracking stuff, roughly.
412	@endverbatim
413	*
414	* Cost wise, this means we'll double the cost for guest memory. There isn't anyway
415	* around that I'm afraid. It means that the cost of dealing out 32GB of memory
416	* to one or more VMs is: (32GB >> PAGE_SHIFT) * 16 bytes, or 128MBs. Or another
417	* example, the VM heap cost when assigning 1GB to a VM will be: 4MB.
418	*
419	* A couple of cost examples for the total cost per-VM + kernel.
420	* 32-bit Windows and 32-bit linux:
421	* 1GB guest ram, 256K pages: 4MB + 2MB(+) = 6MB
422	* 4GB guest ram, 1M pages: 16MB + 8MB(+) = 24MB
423	* 32GB guest ram, 8M pages: 128MB + 64MB(+) = 192MB
424	* 64-bit Windows and 64-bit linux:
425	* 1GB guest ram, 256K pages: 4MB + 3MB(+) = 7MB
426	* 4GB guest ram, 1M pages: 16MB + 12MB(+) = 28MB
427	* 32GB guest ram, 8M pages: 128MB + 96MB(+) = 224MB
428	*
429	* UPDATE - 2007-09-27:
430	* Will need a ballooned flag/state too because we cannot
431	* trust the guest 100% and reporting the same page as ballooned more
432	* than once will put the GMM off balance.
433	*
434	*
435	* @subsection subsec_pgmPhys_Serializing Serializing Access
436	*
437	* Initially, we'll try a simple scheme:
438	*
439	* - The per-VM RAM tracking structures (PGMRAMRANGE) is only modified
440	* by the EMT thread of that VM while in the pgm critsect.
441	* - Other threads in the VM process that needs to make reliable use of
442	* the per-VM RAM tracking structures will enter the critsect.
443	* - No process external thread or kernel thread will ever try enter
444	* the pgm critical section, as that just won't work.
445	* - The idle thread (and similar threads) doesn't not need 100% reliable
446	* data when performing it tasks as the EMT thread will be the one to
447	* do the actual changes later anyway. So, as long as it only accesses
448	* the main ram range, it can do so by somehow preventing the VM from
449	* being destroyed while it works on it...
450	*
451	* - The over-commitment management, including the allocating/freeing
452	* chunks, is serialized by a ring-0 mutex lock (a fast one since the
453	* more mundane mutex implementation is broken on Linux).
454	* - A separeate mutex is protecting the set of allocation chunks so
455	* that pages can be shared or/and freed up while some other VM is
456	* allocating more chunks. This mutex can be take from under the other
457	* one, but not the otherway around.
458	*
459	*
460	* @subsection subsec_pgmPhys_Request VM Request interface
461	*
462	* When in ring-0 it will become necessary to send requests to a VM so it can
463	* for instance move a page while defragmenting during VM destroy. The idle
464	* thread will make use of this interface to request VMs to setup shared
465	* pages and to perform write monitoring of pages.
466	*
467	* I would propose an interface similar to the current VMReq interface, similar
468	* in that it doesn't require locking and that the one sending the request may
469	* wait for completion if it wishes to. This shouldn't be very difficult to
470	* realize.
471	*
472	* The requests themselves are also pretty simple. They are basically:
473	* -# Check that some precondition is still true.
474	* -# Do the update.
475	* -# Update all shadow page tables involved with the page.
476	*
477	* The 3rd step is identical to what we're already doing when updating a
478	* physical handler, see pgmHandlerPhysicalSetRamFlagsAndFlushShadowPTs.
479	*
480	*
481	*
482	* @section sec_pgmPhys_MappingCaches Mapping Caches
483	*
484	* In order to be able to map in and out memory and to be able to support
485	* guest with more RAM than we've got virtual address space, we'll employing
486	* a mapping cache. There is already a tiny one for GC (see PGMGCDynMapGCPageEx)
487	* and we'll create a similar one for ring-0 unless we decide to setup a dedicate
488	* memory context for the HWACCM execution.
489	*
490	*
491	* @subsection subsec_pgmPhys_MappingCaches_R3 Ring-3
492	*
493	* We've considered implementing the ring-3 mapping cache page based but found
494	* that this was bother some when one had to take into account TLBs+SMP and
495	* portability (missing the necessary APIs on several platforms). There were
496	* also some performance concerns with this approach which hadn't quite been
497	* worked out.
498	*
499	* Instead, we'll be mapping allocation chunks into the VM process. This simplifies
500	* matters greatly quite a bit since we don't need to invent any new ring-0 stuff,
501	* only some minor RTR0MEMOBJ mapping stuff. The main concern here is that mapping
502	* compared to the previous idea is that mapping or unmapping a 1MB chunk is more
503	* costly than a single page, although how much more costly is uncertain. We'll
504	* try address this by using a very big cache, preferably bigger than the actual
505	* VM RAM size if possible. The current VM RAM sizes should give some idea for
506	* 32-bit boxes, while on 64-bit we can probably get away with employing an
507	* unlimited cache.
508	*
509	* The cache have to parts, as already indicated, the ring-3 side and the
510	* ring-0 side.
511	*
512	* The ring-0 will be tied to the page allocator since it will operate on the
513	* memory objects it contains. It will therefore require the first ring-0 mutex
514	* discussed in @ref subsec_pgmPhys_Serializing. We
515	* some double house keeping wrt to who has mapped what I think, since both
516	* VMMR0.r0 and RTR0MemObj will keep track of mapping relataions
517	*
518	* The ring-3 part will be protected by the pgm critsect. For simplicity, we'll
519	* require anyone that desires to do changes to the mapping cache to do that
520	* from within this critsect. Alternatively, we could employ a separate critsect
521	* for serializing changes to the mapping cache as this would reduce potential
522	* contention with other threads accessing mappings unrelated to the changes
523	* that are in process. We can see about this later, contention will show
524	* up in the statistics anyway, so it'll be simple to tell.
525	*
526	* The organization of the ring-3 part will be very much like how the allocation
527	* chunks are organized in ring-0, that is in an AVL tree by chunk id. To avoid
528	* having to walk the tree all the time, we'll have a couple of lookaside entries
529	* like in we do for I/O ports and MMIO in IOM.
530	*
531	* The simplified flow of a PGMPhysRead/Write function:
532	* -# Enter the PGM critsect.
533	* -# Lookup GCPhys in the ram ranges and get the Page ID.
534	* -# Calc the Allocation Chunk ID from the Page ID.
535	* -# Check the lookaside entries and then the AVL tree for the Chunk ID.
536	* If not found in cache:
537	* -# Call ring-0 and request it to be mapped and supply
538	* a chunk to be unmapped if the cache is maxed out already.
539	* -# Insert the new mapping into the AVL tree (id + R3 address).
540	* -# Update the relevant lookaside entry and return the mapping address.
541	* -# Do the read/write according to monitoring flags and everything.
542	* -# Leave the critsect.
543	*
544	*
545	* @section sec_pgmPhys_Fallback Fallback
546	*
547	* Current all the "second tier" hosts will not support the RTR0MemObjAllocPhysNC
548	* API and thus require a fallback.
549	*
550	* So, when RTR0MemObjAllocPhysNC returns VERR_NOT_SUPPORTED the page allocator
551	* will return to the ring-3 caller (and later ring-0) and asking it to seed
552	* the page allocator with some fresh pages (VERR_GMM_SEED_ME). Ring-3 will
553	* then perform an SUPPageAlloc(cbChunk >> PAGE_SHIFT) call and make a
554	* "SeededAllocPages" call to ring-0.
555	*
556	* The first time ring-0 sees the VERR_NOT_SUPPORTED failure it will disable
557	* all page sharing (zero page detection will continue). It will also force
558	* all allocations to come from the VM which seeded the page. Both these
559	* measures are taken to make sure that there will never be any need for
560	* mapping anything into ring-3 - everything will be mapped already.
561	*
562	* Whether we'll continue to use the current MM locked memory management
563	* for this I don't quite know (I'd prefer not to and just ditch that all
564	* togther), we'll see what's simplest to do.
565	*
566	*
567	*
568	* @section sec_pgmPhys_Changes Changes
569	*
570	* Breakdown of the changes involved?
571	*/
572
573
574	/** Saved state data unit version. */
575	#define PGM_SAVED_STATE_VERSION 6
576
577	/*******************************************************************************
578	* Header Files *
579	*******************************************************************************/
580	#define LOG_GROUP LOG_GROUP_PGM
581	#include <VBox/dbgf.h>
582	#include <VBox/pgm.h>
583	#include <VBox/cpum.h>
584	#include <VBox/iom.h>
585	#include <VBox/sup.h>
586	#include <VBox/mm.h>
587	#include <VBox/em.h>
588	#include <VBox/stam.h>
589	#include <VBox/rem.h>
590	#include <VBox/dbgf.h>
591	#include <VBox/rem.h>
592	#include <VBox/selm.h>
593	#include <VBox/ssm.h>
594	#include "PGMInternal.h"
595	#include <VBox/vm.h>
596	#include <VBox/dbg.h>
597	#include <VBox/hwaccm.h>
598
599	#include <iprt/assert.h>
600	#include <iprt/alloc.h>
601	#include <iprt/asm.h>
602	#include <iprt/thread.h>
603	#include <iprt/string.h>
604	#include <VBox/param.h>
605	#include <VBox/err.h>
606
607
608
609	/*******************************************************************************
610	* Internal Functions *
611	*******************************************************************************/
612	static int pgmR3InitPaging(PVM pVM);
613	static DECLCALLBACK(void) pgmR3PhysInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
614	static DECLCALLBACK(void) pgmR3InfoMode(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
615	static DECLCALLBACK(void) pgmR3InfoCr3(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
616	static DECLCALLBACK(int) pgmR3RelocatePhysHandler(PAVLROGCPHYSNODECORE pNode, void *pvUser);
617	static DECLCALLBACK(int) pgmR3RelocateVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser);
618	static DECLCALLBACK(int) pgmR3RelocateHyperVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser);
619	#ifdef VBOX_STRICT
620	static DECLCALLBACK(void) pgmR3ResetNoMorePhysWritesFlag(PVM pVM, VMSTATE enmState, VMSTATE enmOldState, void *pvUser);
621	#endif
622	static DECLCALLBACK(int) pgmR3Save(PVM pVM, PSSMHANDLE pSSM);
623	static DECLCALLBACK(int) pgmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version);
624	static int pgmR3ModeDataInit(PVM pVM, bool fResolveGCAndR0);
625	static void pgmR3ModeDataSwitch(PVM pVM, PGMMODE enmShw, PGMMODE enmGst);
626	static PGMMODE pgmR3CalcShadowMode(PVM pVM, PGMMODE enmGuestMode, SUPPAGINGMODE enmHostMode, PGMMODE enmShadowMode, VMMSWITCHER *penmSwitcher);
627
628	#ifdef VBOX_WITH_STATISTICS
629	static void pgmR3InitStats(PVM pVM);
630	#endif
631
632	#ifdef VBOX_WITH_DEBUGGER
633	/** @todo all but the two last commands must be converted to 'info'. */
634	static DECLCALLBACK(int) pgmR3CmdRam(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
635	static DECLCALLBACK(int) pgmR3CmdMap(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
636	static DECLCALLBACK(int) pgmR3CmdSync(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
637	static DECLCALLBACK(int) pgmR3CmdSyncAlways(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
638	# ifdef VBOX_STRICT
639	static DECLCALLBACK(int) pgmR3CmdAssertCR3(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
640	# endif
641	#endif
642
643
644	/*******************************************************************************
645	* Global Variables *
646	*******************************************************************************/
647	#ifdef VBOX_WITH_DEBUGGER
648	/** Command descriptors. */
649	static const DBGCCMD g_aCmds[] =
650	{
651	/* pszCmd, cArgsMin, cArgsMax, paArgDesc, cArgDescs, pResultDesc, fFlags, pfnHandler pszSyntax, ....pszDescription */
652	{ "pgmram", 0, 0, NULL, 0, NULL, 0, pgmR3CmdRam, "", "Display the ram ranges." },
653	{ "pgmmap", 0, 0, NULL, 0, NULL, 0, pgmR3CmdMap, "", "Display the mapping ranges." },
654	{ "pgmsync", 0, 0, NULL, 0, NULL, 0, pgmR3CmdSync, "", "Sync the CR3 page." },
655	#ifdef VBOX_STRICT
656	{ "pgmassertcr3", 0, 0, NULL, 0, NULL, 0, pgmR3CmdAssertCR3, "", "Check the shadow CR3 mapping." },
657	#endif
658	{ "pgmsyncalways", 0, 0, NULL, 0, NULL, 0, pgmR3CmdSyncAlways, "", "Toggle permanent CR3 syncing." },
659	};
660	#endif
661
662
663
664
665	/*
666	* Shadow - 32-bit mode
667	*/
668	#define PGM_SHW_TYPE PGM_TYPE_32BIT
669	#define PGM_SHW_NAME(name) PGM_SHW_NAME_32BIT(name)
670	#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_32BIT_STR(name)
671	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_32BIT_STR(name)
672	#include "PGMShw.h"
673
674	/* Guest - real mode */
675	#define PGM_GST_TYPE PGM_TYPE_REAL
676	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
677	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_REAL_STR(name)
678	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
679	#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_REAL(name)
680	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_32BIT_REAL_STR(name)
681	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_32BIT_REAL_STR(name)
682	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_PHYS
683	#include "PGMGst.h"
684	#include "PGMBth.h"
685	#undef BTH_PGMPOOLKIND_PT_FOR_PT
686	#undef PGM_BTH_NAME
687	#undef PGM_BTH_NAME_RC_STR
688	#undef PGM_BTH_NAME_R0_STR
689	#undef PGM_GST_TYPE
690	#undef PGM_GST_NAME
691	#undef PGM_GST_NAME_RC_STR
692	#undef PGM_GST_NAME_R0_STR
693
694	/* Guest - protected mode */
695	#define PGM_GST_TYPE PGM_TYPE_PROT
696	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
697	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PROT_STR(name)
698	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
699	#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_PROT(name)
700	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_32BIT_PROT_STR(name)
701	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_32BIT_PROT_STR(name)
702	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_PHYS
703	#include "PGMGst.h"
704	#include "PGMBth.h"
705	#undef BTH_PGMPOOLKIND_PT_FOR_PT
706	#undef PGM_BTH_NAME
707	#undef PGM_BTH_NAME_RC_STR
708	#undef PGM_BTH_NAME_R0_STR
709	#undef PGM_GST_TYPE
710	#undef PGM_GST_NAME
711	#undef PGM_GST_NAME_RC_STR
712	#undef PGM_GST_NAME_R0_STR
713
714	/* Guest - 32-bit mode */
715	#define PGM_GST_TYPE PGM_TYPE_32BIT
716	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
717	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_32BIT_STR(name)
718	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
719	#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_32BIT(name)
720	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_32BIT_32BIT_STR(name)
721	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_32BIT_32BIT_STR(name)
722	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT
723	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB
724	#include "PGMGst.h"
725	#include "PGMBth.h"
726	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
727	#undef BTH_PGMPOOLKIND_PT_FOR_PT
728	#undef PGM_BTH_NAME
729	#undef PGM_BTH_NAME_RC_STR
730	#undef PGM_BTH_NAME_R0_STR
731	#undef PGM_GST_TYPE
732	#undef PGM_GST_NAME
733	#undef PGM_GST_NAME_RC_STR
734	#undef PGM_GST_NAME_R0_STR
735
736	#undef PGM_SHW_TYPE
737	#undef PGM_SHW_NAME
738	#undef PGM_SHW_NAME_RC_STR
739	#undef PGM_SHW_NAME_R0_STR
740
741
742	/*
743	* Shadow - PAE mode
744	*/
745	#define PGM_SHW_TYPE PGM_TYPE_PAE
746	#define PGM_SHW_NAME(name) PGM_SHW_NAME_PAE(name)
747	#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_PAE_STR(name)
748	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_PAE_STR(name)
749	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_REAL(name)
750	#include "PGMShw.h"
751
752	/* Guest - real mode */
753	#define PGM_GST_TYPE PGM_TYPE_REAL
754	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
755	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_REAL_STR(name)
756	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
757	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_REAL(name)
758	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_PAE_REAL_STR(name)
759	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_REAL_STR(name)
760	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
761	#include "PGMBth.h"
762	#undef BTH_PGMPOOLKIND_PT_FOR_PT
763	#undef PGM_BTH_NAME
764	#undef PGM_BTH_NAME_RC_STR
765	#undef PGM_BTH_NAME_R0_STR
766	#undef PGM_GST_TYPE
767	#undef PGM_GST_NAME
768	#undef PGM_GST_NAME_RC_STR
769	#undef PGM_GST_NAME_R0_STR
770
771	/* Guest - protected mode */
772	#define PGM_GST_TYPE PGM_TYPE_PROT
773	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
774	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PROT_STR(name)
775	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
776	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_PROT(name)
777	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_PAE_PROT_STR(name)
778	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_PROT_STR(name)
779	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
780	#include "PGMBth.h"
781	#undef BTH_PGMPOOLKIND_PT_FOR_PT
782	#undef PGM_BTH_NAME
783	#undef PGM_BTH_NAME_RC_STR
784	#undef PGM_BTH_NAME_R0_STR
785	#undef PGM_GST_TYPE
786	#undef PGM_GST_NAME
787	#undef PGM_GST_NAME_RC_STR
788	#undef PGM_GST_NAME_R0_STR
789
790	/* Guest - 32-bit mode */
791	#define PGM_GST_TYPE PGM_TYPE_32BIT
792	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
793	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_32BIT_STR(name)
794	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
795	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_32BIT(name)
796	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_PAE_32BIT_STR(name)
797	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_32BIT_STR(name)
798	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_32BIT_PT
799	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB
800	#include "PGMBth.h"
801	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
802	#undef BTH_PGMPOOLKIND_PT_FOR_PT
803	#undef PGM_BTH_NAME
804	#undef PGM_BTH_NAME_RC_STR
805	#undef PGM_BTH_NAME_R0_STR
806	#undef PGM_GST_TYPE
807	#undef PGM_GST_NAME
808	#undef PGM_GST_NAME_RC_STR
809	#undef PGM_GST_NAME_R0_STR
810
811	/* Guest - PAE mode */
812	#define PGM_GST_TYPE PGM_TYPE_PAE
813	#define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
814	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PAE_STR(name)
815	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PAE_STR(name)
816	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_PAE(name)
817	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_PAE_PAE_STR(name)
818	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_PAE_STR(name)
819	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
820	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
821	#include "PGMGst.h"
822	#include "PGMBth.h"
823	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
824	#undef BTH_PGMPOOLKIND_PT_FOR_PT
825	#undef PGM_BTH_NAME
826	#undef PGM_BTH_NAME_RC_STR
827	#undef PGM_BTH_NAME_R0_STR
828	#undef PGM_GST_TYPE
829	#undef PGM_GST_NAME
830	#undef PGM_GST_NAME_RC_STR
831	#undef PGM_GST_NAME_R0_STR
832
833	#undef PGM_SHW_TYPE
834	#undef PGM_SHW_NAME
835	#undef PGM_SHW_NAME_RC_STR
836	#undef PGM_SHW_NAME_R0_STR
837
838
839	/*
840	* Shadow - AMD64 mode
841	*/
842	#define PGM_SHW_TYPE PGM_TYPE_AMD64
843	#define PGM_SHW_NAME(name) PGM_SHW_NAME_AMD64(name)
844	#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_AMD64_STR(name)
845	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_AMD64_STR(name)
846	#include "PGMShw.h"
847
848	#ifdef VBOX_WITH_64_BITS_GUESTS
849	/* Guest - AMD64 mode */
850	# define PGM_GST_TYPE PGM_TYPE_AMD64
851	# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
852	# define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_AMD64_STR(name)
853	# define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_AMD64_STR(name)
854	# define PGM_BTH_NAME(name) PGM_BTH_NAME_AMD64_AMD64(name)
855	# define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_AMD64_AMD64_STR(name)
856	# define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_AMD64_AMD64_STR(name)
857	# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
858	# define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
859	# include "PGMGst.h"
860	# include "PGMBth.h"
861	# undef BTH_PGMPOOLKIND_PT_FOR_BIG
862	# undef BTH_PGMPOOLKIND_PT_FOR_PT
863	# undef PGM_BTH_NAME
864	# undef PGM_BTH_NAME_RC_STR
865	# undef PGM_BTH_NAME_R0_STR
866	# undef PGM_GST_TYPE
867	# undef PGM_GST_NAME
868	# undef PGM_GST_NAME_RC_STR
869	# undef PGM_GST_NAME_R0_STR
870	#endif /* VBOX_WITH_64_BITS_GUESTS */
871
872	#undef PGM_SHW_TYPE
873	#undef PGM_SHW_NAME
874	#undef PGM_SHW_NAME_RC_STR
875	#undef PGM_SHW_NAME_R0_STR
876
877
878	/*
879	* Shadow - Nested paging mode
880	*/
881	#define PGM_SHW_TYPE PGM_TYPE_NESTED
882	#define PGM_SHW_NAME(name) PGM_SHW_NAME_NESTED(name)
883	#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_NESTED_STR(name)
884	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_NESTED_STR(name)
885	#include "PGMShw.h"
886
887	/* Guest - real mode */
888	#define PGM_GST_TYPE PGM_TYPE_REAL
889	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
890	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_REAL_STR(name)
891	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
892	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_REAL(name)
893	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_REAL_STR(name)
894	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_REAL_STR(name)
895	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
896	#include "PGMBth.h"
897	#undef BTH_PGMPOOLKIND_PT_FOR_PT
898	#undef PGM_BTH_NAME
899	#undef PGM_BTH_NAME_RC_STR
900	#undef PGM_BTH_NAME_R0_STR
901	#undef PGM_GST_TYPE
902	#undef PGM_GST_NAME
903	#undef PGM_GST_NAME_RC_STR
904	#undef PGM_GST_NAME_R0_STR
905
906	/* Guest - protected mode */
907	#define PGM_GST_TYPE PGM_TYPE_PROT
908	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
909	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PROT_STR(name)
910	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
911	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_PROT(name)
912	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_PROT_STR(name)
913	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_PROT_STR(name)
914	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
915	#include "PGMBth.h"
916	#undef BTH_PGMPOOLKIND_PT_FOR_PT
917	#undef PGM_BTH_NAME
918	#undef PGM_BTH_NAME_RC_STR
919	#undef PGM_BTH_NAME_R0_STR
920	#undef PGM_GST_TYPE
921	#undef PGM_GST_NAME
922	#undef PGM_GST_NAME_RC_STR
923	#undef PGM_GST_NAME_R0_STR
924
925	/* Guest - 32-bit mode */
926	#define PGM_GST_TYPE PGM_TYPE_32BIT
927	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
928	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_32BIT_STR(name)
929	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
930	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_32BIT(name)
931	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_32BIT_STR(name)
932	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_32BIT_STR(name)
933	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_32BIT_PT
934	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB
935	#include "PGMBth.h"
936	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
937	#undef BTH_PGMPOOLKIND_PT_FOR_PT
938	#undef PGM_BTH_NAME
939	#undef PGM_BTH_NAME_RC_STR
940	#undef PGM_BTH_NAME_R0_STR
941	#undef PGM_GST_TYPE
942	#undef PGM_GST_NAME
943	#undef PGM_GST_NAME_RC_STR
944	#undef PGM_GST_NAME_R0_STR
945
946	/* Guest - PAE mode */
947	#define PGM_GST_TYPE PGM_TYPE_PAE
948	#define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
949	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PAE_STR(name)
950	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PAE_STR(name)
951	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_PAE(name)
952	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_PAE_STR(name)
953	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_PAE_STR(name)
954	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
955	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
956	#include "PGMBth.h"
957	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
958	#undef BTH_PGMPOOLKIND_PT_FOR_PT
959	#undef PGM_BTH_NAME
960	#undef PGM_BTH_NAME_RC_STR
961	#undef PGM_BTH_NAME_R0_STR
962	#undef PGM_GST_TYPE
963	#undef PGM_GST_NAME
964	#undef PGM_GST_NAME_RC_STR
965	#undef PGM_GST_NAME_R0_STR
966
967	#ifdef VBOX_WITH_64_BITS_GUESTS
968	/* Guest - AMD64 mode */
969	# define PGM_GST_TYPE PGM_TYPE_AMD64
970	# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
971	# define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_AMD64_STR(name)
972	# define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_AMD64_STR(name)
973	# define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_AMD64(name)
974	# define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_AMD64_STR(name)
975	# define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_AMD64_STR(name)
976	# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
977	# define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
978	# include "PGMBth.h"
979	# undef BTH_PGMPOOLKIND_PT_FOR_BIG
980	# undef BTH_PGMPOOLKIND_PT_FOR_PT
981	# undef PGM_BTH_NAME
982	# undef PGM_BTH_NAME_RC_STR
983	# undef PGM_BTH_NAME_R0_STR
984	# undef PGM_GST_TYPE
985	# undef PGM_GST_NAME
986	# undef PGM_GST_NAME_RC_STR
987	# undef PGM_GST_NAME_R0_STR
988	#endif /* VBOX_WITH_64_BITS_GUESTS */
989
990	#undef PGM_SHW_TYPE
991	#undef PGM_SHW_NAME
992	#undef PGM_SHW_NAME_RC_STR
993	#undef PGM_SHW_NAME_R0_STR
994
995
996	/*
997	* Shadow - EPT
998	*/
999	#define PGM_SHW_TYPE PGM_TYPE_EPT
1000	#define PGM_SHW_NAME(name) PGM_SHW_NAME_EPT(name)
1001	#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_EPT_STR(name)
1002	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_EPT_STR(name)
1003	#include "PGMShw.h"
1004
1005	/* Guest - real mode */
1006	#define PGM_GST_TYPE PGM_TYPE_REAL
1007	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
1008	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_REAL_STR(name)
1009	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
1010	#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_REAL(name)
1011	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_REAL_STR(name)
1012	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_REAL_STR(name)
1013	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
1014	#include "PGMBth.h"
1015	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1016	#undef PGM_BTH_NAME
1017	#undef PGM_BTH_NAME_RC_STR
1018	#undef PGM_BTH_NAME_R0_STR
1019	#undef PGM_GST_TYPE
1020	#undef PGM_GST_NAME
1021	#undef PGM_GST_NAME_RC_STR
1022	#undef PGM_GST_NAME_R0_STR
1023
1024	/* Guest - protected mode */
1025	#define PGM_GST_TYPE PGM_TYPE_PROT
1026	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
1027	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PROT_STR(name)
1028	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
1029	#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_PROT(name)
1030	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_PROT_STR(name)
1031	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_PROT_STR(name)
1032	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
1033	#include "PGMBth.h"
1034	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1035	#undef PGM_BTH_NAME
1036	#undef PGM_BTH_NAME_RC_STR
1037	#undef PGM_BTH_NAME_R0_STR
1038	#undef PGM_GST_TYPE
1039	#undef PGM_GST_NAME
1040	#undef PGM_GST_NAME_RC_STR
1041	#undef PGM_GST_NAME_R0_STR
1042
1043	/* Guest - 32-bit mode */
1044	#define PGM_GST_TYPE PGM_TYPE_32BIT
1045	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
1046	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_32BIT_STR(name)
1047	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
1048	#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_32BIT(name)
1049	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_32BIT_STR(name)
1050	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_32BIT_STR(name)
1051	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_32BIT_PT
1052	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB
1053	#include "PGMBth.h"
1054	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
1055	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1056	#undef PGM_BTH_NAME
1057	#undef PGM_BTH_NAME_RC_STR
1058	#undef PGM_BTH_NAME_R0_STR
1059	#undef PGM_GST_TYPE
1060	#undef PGM_GST_NAME
1061	#undef PGM_GST_NAME_RC_STR
1062	#undef PGM_GST_NAME_R0_STR
1063
1064	/* Guest - PAE mode */
1065	#define PGM_GST_TYPE PGM_TYPE_PAE
1066	#define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
1067	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PAE_STR(name)
1068	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PAE_STR(name)
1069	#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_PAE(name)
1070	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_PAE_STR(name)
1071	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_PAE_STR(name)
1072	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
1073	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
1074	#include "PGMBth.h"
1075	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
1076	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1077	#undef PGM_BTH_NAME
1078	#undef PGM_BTH_NAME_RC_STR
1079	#undef PGM_BTH_NAME_R0_STR
1080	#undef PGM_GST_TYPE
1081	#undef PGM_GST_NAME
1082	#undef PGM_GST_NAME_RC_STR
1083	#undef PGM_GST_NAME_R0_STR
1084
1085	#ifdef VBOX_WITH_64_BITS_GUESTS
1086	/* Guest - AMD64 mode */
1087	# define PGM_GST_TYPE PGM_TYPE_AMD64
1088	# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
1089	# define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_AMD64_STR(name)
1090	# define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_AMD64_STR(name)
1091	# define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_AMD64(name)
1092	# define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_AMD64_STR(name)
1093	# define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_AMD64_STR(name)
1094	# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
1095	# define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
1096	# include "PGMBth.h"
1097	# undef BTH_PGMPOOLKIND_PT_FOR_BIG
1098	# undef BTH_PGMPOOLKIND_PT_FOR_PT
1099	# undef PGM_BTH_NAME
1100	# undef PGM_BTH_NAME_RC_STR
1101	# undef PGM_BTH_NAME_R0_STR
1102	# undef PGM_GST_TYPE
1103	# undef PGM_GST_NAME
1104	# undef PGM_GST_NAME_RC_STR
1105	# undef PGM_GST_NAME_R0_STR
1106	#endif /* VBOX_WITH_64_BITS_GUESTS */
1107
1108	#undef PGM_SHW_TYPE
1109	#undef PGM_SHW_NAME
1110	#undef PGM_SHW_NAME_RC_STR
1111	#undef PGM_SHW_NAME_R0_STR
1112
1113
1114
1115	/**
1116	* Initiates the paging of VM.
1117	*
1118	* @returns VBox status code.
1119	* @param pVM Pointer to VM structure.
1120	*/
1121	VMMR3DECL(int) PGMR3Init(PVM pVM)
1122	{
1123	LogFlow(("PGMR3Init:\n"));
1124
1125	/*
1126	* Assert alignment and sizes.
1127	*/
1128	AssertRelease(sizeof(pVM->pgm.s) <= sizeof(pVM->pgm.padding));
1129
1130	/*
1131	* Init the structure.
1132	*/
1133	pVM->pgm.s.offVM = RT_OFFSETOF(VM, pgm.s);
1134	pVM->pgm.s.enmShadowMode = PGMMODE_INVALID;
1135	pVM->pgm.s.enmGuestMode = PGMMODE_INVALID;
1136	pVM->pgm.s.enmHostMode = SUPPAGINGMODE_INVALID;
1137	pVM->pgm.s.GCPhysCR3 = NIL_RTGCPHYS;
1138	pVM->pgm.s.GCPhysGstCR3Monitored = NIL_RTGCPHYS;
1139	pVM->pgm.s.fA20Enabled = true;
1140	pVM->pgm.s.GCPhys4MBPSEMask = RT_BIT_64(32) - 1; /* default; checked later */
1141	pVM->pgm.s.pGstPaePDPTHC = NULL;
1142	pVM->pgm.s.pGstPaePDPTGC = 0;
1143	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.apGstPaePDsHC); i++)
1144	{
1145	pVM->pgm.s.apGstPaePDsHC[i] = NULL;
1146	pVM->pgm.s.apGstPaePDsGC[i] = 0;
1147	pVM->pgm.s.aGCPhysGstPaePDs[i] = NIL_RTGCPHYS;
1148	pVM->pgm.s.aGCPhysGstPaePDsMonitored[i] = NIL_RTGCPHYS;
1149	}
1150
1151	#ifdef VBOX_STRICT
1152	VMR3AtStateRegister(pVM, pgmR3ResetNoMorePhysWritesFlag, NULL);
1153	#endif
1154
1155	/*
1156	* Get the configured RAM size - to estimate saved state size.
1157	*/
1158	uint64_t cbRam;
1159	int rc = CFGMR3QueryU64(CFGMR3GetRoot(pVM), "RamSize", &cbRam);
1160	if (rc == VERR_CFGM_VALUE_NOT_FOUND)
1161	cbRam = pVM->pgm.s.cbRamSize = 0;
1162	else if (VBOX_SUCCESS(rc))
1163	{
1164	if (cbRam < PAGE_SIZE)
1165	cbRam = 0;
1166	cbRam = RT_ALIGN_64(cbRam, PAGE_SIZE);
1167	pVM->pgm.s.cbRamSize = (RTUINT)cbRam;
1168	}
1169	else
1170	{
1171	AssertMsgFailed(("Configuration error: Failed to query integer \"RamSize\", rc=%Vrc.\n", rc));
1172	return rc;
1173	}
1174
1175	/*
1176	* Register saved state data unit.
1177	*/
1178	rc = SSMR3RegisterInternal(pVM, "pgm", 1, PGM_SAVED_STATE_VERSION, (size_t)cbRam + sizeof(PGM),
1179	NULL, pgmR3Save, NULL,
1180	NULL, pgmR3Load, NULL);
1181	if (VBOX_FAILURE(rc))
1182	return rc;
1183
1184	/*
1185	* Initialize the PGM critical section and flush the phys TLBs
1186	*/
1187	rc = PDMR3CritSectInit(pVM, &pVM->pgm.s.CritSect, "PGM");
1188	AssertRCReturn(rc, rc);
1189
1190	PGMR3PhysChunkInvalidateTLB(pVM);
1191	PGMPhysInvalidatePageR3MapTLB(pVM);
1192	PGMPhysInvalidatePageR0MapTLB(pVM);
1193	PGMPhysInvalidatePageGCMapTLB(pVM);
1194
1195	/*
1196	* Trees
1197	*/
1198	rc = MMHyperAlloc(pVM, sizeof(PGMTREES), 0, MM_TAG_PGM, (void **)&pVM->pgm.s.pTreesR3);
1199	if (VBOX_SUCCESS(rc))
1200	{
1201	pVM->pgm.s.pTreesR0 = MMHyperR3ToR0(pVM, pVM->pgm.s.pTreesR3);
1202	pVM->pgm.s.pTreesRC = MMHyperR3ToRC(pVM, pVM->pgm.s.pTreesR3);
1203
1204	/*
1205	* Alocate the zero page.
1206	*/
1207	rc = MMHyperAlloc(pVM, PAGE_SIZE, PAGE_SIZE, MM_TAG_PGM, &pVM->pgm.s.pvZeroPgR3);
1208	}
1209	if (VBOX_SUCCESS(rc))
1210	{
1211	pVM->pgm.s.pvZeroPgGC = MMHyperR3ToRC(pVM, pVM->pgm.s.pvZeroPgR3);
1212	pVM->pgm.s.pvZeroPgR0 = MMHyperR3ToR0(pVM, pVM->pgm.s.pvZeroPgR3);
1213	AssertRelease(pVM->pgm.s.pvZeroPgR0 != NIL_RTHCPHYS);
1214	pVM->pgm.s.HCPhysZeroPg = MMR3HyperHCVirt2HCPhys(pVM, pVM->pgm.s.pvZeroPgR3);
1215	AssertRelease(pVM->pgm.s.HCPhysZeroPg != NIL_RTHCPHYS);
1216
1217	/*
1218	* Init the paging.
1219	*/
1220	rc = pgmR3InitPaging(pVM);
1221	}
1222	if (VBOX_SUCCESS(rc))
1223	{
1224	/*
1225	* Init the page pool.
1226	*/
1227	rc = pgmR3PoolInit(pVM);
1228	}
1229	if (VBOX_SUCCESS(rc))
1230	{
1231	/*
1232	* Info & statistics
1233	*/
1234	DBGFR3InfoRegisterInternal(pVM, "mode",
1235	"Shows the current paging mode. "
1236	"Recognizes 'all', 'guest', 'shadow' and 'host' as arguments, defaulting to 'all' if nothing's given.",
1237	pgmR3InfoMode);
1238	DBGFR3InfoRegisterInternal(pVM, "pgmcr3",
1239	"Dumps all the entries in the top level paging table. No arguments.",
1240	pgmR3InfoCr3);
1241	DBGFR3InfoRegisterInternal(pVM, "phys",
1242	"Dumps all the physical address ranges. No arguments.",
1243	pgmR3PhysInfo);
1244	DBGFR3InfoRegisterInternal(pVM, "handlers",
1245	"Dumps physical, virtual and hyper virtual handlers. "
1246	"Pass 'phys', 'virt', 'hyper' as argument if only one kind is wanted."
1247	"Add 'nost' if the statistics are unwanted, use together with 'all' or explicit selection.",
1248	pgmR3InfoHandlers);
1249	DBGFR3InfoRegisterInternal(pVM, "mappings",
1250	"Dumps guest mappings.",
1251	pgmR3MapInfo);
1252
1253	STAM_REL_REG(pVM, &pVM->pgm.s.cGuestModeChanges, STAMTYPE_COUNTER, "/PGM/cGuestModeChanges", STAMUNIT_OCCURENCES, "Number of guest mode changes.");
1254	#ifdef VBOX_WITH_STATISTICS
1255	pgmR3InitStats(pVM);
1256	#endif
1257	#ifdef VBOX_WITH_DEBUGGER
1258	/*
1259	* Debugger commands.
1260	*/
1261	static bool fRegisteredCmds = false;
1262	if (!fRegisteredCmds)
1263	{
1264	int rc = DBGCRegisterCommands(&g_aCmds[0], RT_ELEMENTS(g_aCmds));
1265	if (VBOX_SUCCESS(rc))
1266	fRegisteredCmds = true;
1267	}
1268	#endif
1269	return VINF_SUCCESS;
1270	}
1271
1272	/* Almost no cleanup necessary, MM frees all memory. */
1273	PDMR3CritSectDelete(&pVM->pgm.s.CritSect);
1274
1275	return rc;
1276	}
1277
1278
1279	/**
1280	* Init paging.
1281	*
1282	* Since we need to check what mode the host is operating in before we can choose
1283	* the right paging functions for the host we have to delay this until R0 has
1284	* been initialized.
1285	*
1286	* @returns VBox status code.
1287	* @param pVM VM handle.
1288	*/
1289	static int pgmR3InitPaging(PVM pVM)
1290	{
1291	/*
1292	* Force a recalculation of modes and switcher so everyone gets notified.
1293	*/
1294	pVM->pgm.s.enmShadowMode = PGMMODE_INVALID;
1295	pVM->pgm.s.enmGuestMode = PGMMODE_INVALID;
1296	pVM->pgm.s.enmHostMode = SUPPAGINGMODE_INVALID;
1297
1298	/*
1299	* Allocate static mapping space for whatever the cr3 register
1300	* points to and in the case of PAE mode to the 4 PDs.
1301	*/
1302	int rc = MMR3HyperReserve(pVM, PAGE_SIZE * 5, "CR3 mapping", &pVM->pgm.s.GCPtrCR3Mapping);
1303	if (VBOX_FAILURE(rc))
1304	{
1305	AssertMsgFailed(("Failed to reserve two pages for cr mapping in HMA, rc=%Vrc\n", rc));
1306	return rc;
1307	}
1308	MMR3HyperReserve(pVM, PAGE_SIZE, "fence", NULL);
1309
1310	/*
1311	* Allocate pages for the three possible intermediate contexts
1312	* (AMD64, PAE and plain 32-Bit). We maintain all three contexts
1313	* for the sake of simplicity. The AMD64 uses the PAE for the
1314	* lower levels, making the total number of pages 11 (3 + 7 + 1).
1315	*
1316	* We assume that two page tables will be enought for the core code
1317	* mappings (HC virtual and identity).
1318	*/
1319	pVM->pgm.s.pInterPD = (PX86PD)MMR3PageAllocLow(pVM);
1320	pVM->pgm.s.apInterPTs[0] = (PX86PT)MMR3PageAllocLow(pVM);
1321	pVM->pgm.s.apInterPTs[1] = (PX86PT)MMR3PageAllocLow(pVM);
1322	pVM->pgm.s.apInterPaePTs[0] = (PX86PTPAE)MMR3PageAlloc(pVM);
1323	pVM->pgm.s.apInterPaePTs[1] = (PX86PTPAE)MMR3PageAlloc(pVM);
1324	pVM->pgm.s.apInterPaePDs[0] = (PX86PDPAE)MMR3PageAlloc(pVM);
1325	pVM->pgm.s.apInterPaePDs[1] = (PX86PDPAE)MMR3PageAlloc(pVM);
1326	pVM->pgm.s.apInterPaePDs[2] = (PX86PDPAE)MMR3PageAlloc(pVM);
1327	pVM->pgm.s.apInterPaePDs[3] = (PX86PDPAE)MMR3PageAlloc(pVM);
1328	pVM->pgm.s.pInterPaePDPT = (PX86PDPT)MMR3PageAllocLow(pVM);
1329	pVM->pgm.s.pInterPaePDPT64 = (PX86PDPT)MMR3PageAllocLow(pVM);
1330	pVM->pgm.s.pInterPaePML4 = (PX86PML4)MMR3PageAllocLow(pVM);
1331	if ( !pVM->pgm.s.pInterPD
1332	\|\| !pVM->pgm.s.apInterPTs[0]
1333	\|\| !pVM->pgm.s.apInterPTs[1]
1334	\|\| !pVM->pgm.s.apInterPaePTs[0]
1335	\|\| !pVM->pgm.s.apInterPaePTs[1]
1336	\|\| !pVM->pgm.s.apInterPaePDs[0]
1337	\|\| !pVM->pgm.s.apInterPaePDs[1]
1338	\|\| !pVM->pgm.s.apInterPaePDs[2]
1339	\|\| !pVM->pgm.s.apInterPaePDs[3]
1340	\|\| !pVM->pgm.s.pInterPaePDPT
1341	\|\| !pVM->pgm.s.pInterPaePDPT64
1342	\|\| !pVM->pgm.s.pInterPaePML4)
1343	{
1344	AssertMsgFailed(("Failed to allocate pages for the intermediate context!\n"));
1345	return VERR_NO_PAGE_MEMORY;
1346	}
1347
1348	pVM->pgm.s.HCPhysInterPD = MMPage2Phys(pVM, pVM->pgm.s.pInterPD);
1349	AssertRelease(pVM->pgm.s.HCPhysInterPD != NIL_RTHCPHYS && !(pVM->pgm.s.HCPhysInterPD & PAGE_OFFSET_MASK));
1350	pVM->pgm.s.HCPhysInterPaePDPT = MMPage2Phys(pVM, pVM->pgm.s.pInterPaePDPT);
1351	AssertRelease(pVM->pgm.s.HCPhysInterPaePDPT != NIL_RTHCPHYS && !(pVM->pgm.s.HCPhysInterPaePDPT & PAGE_OFFSET_MASK));
1352	pVM->pgm.s.HCPhysInterPaePML4 = MMPage2Phys(pVM, pVM->pgm.s.pInterPaePML4);
1353	AssertRelease(pVM->pgm.s.HCPhysInterPaePML4 != NIL_RTHCPHYS && !(pVM->pgm.s.HCPhysInterPaePML4 & PAGE_OFFSET_MASK));
1354
1355	/*
1356	* Initialize the pages, setting up the PML4 and PDPT for repetitive 4GB action.
1357	*/
1358	ASMMemZeroPage(pVM->pgm.s.pInterPD);
1359	ASMMemZeroPage(pVM->pgm.s.apInterPTs[0]);
1360	ASMMemZeroPage(pVM->pgm.s.apInterPTs[1]);
1361
1362	ASMMemZeroPage(pVM->pgm.s.apInterPaePTs[0]);
1363	ASMMemZeroPage(pVM->pgm.s.apInterPaePTs[1]);
1364
1365	ASMMemZeroPage(pVM->pgm.s.pInterPaePDPT);
1366	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.apInterPaePDs); i++)
1367	{
1368	ASMMemZeroPage(pVM->pgm.s.apInterPaePDs[i]);
1369	pVM->pgm.s.pInterPaePDPT->a[i].u = X86_PDPE_P \| PGM_PLXFLAGS_PERMANENT
1370	\| MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[i]);
1371	}
1372
1373	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.pInterPaePDPT64->a); i++)
1374	{
1375	const unsigned iPD = i % RT_ELEMENTS(pVM->pgm.s.apInterPaePDs);
1376	pVM->pgm.s.pInterPaePDPT64->a[i].u = X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_A \| PGM_PLXFLAGS_PERMANENT
1377	\| MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[iPD]);
1378	}
1379
1380	RTHCPHYS HCPhysInterPaePDPT64 = MMPage2Phys(pVM, pVM->pgm.s.pInterPaePDPT64);
1381	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.pInterPaePML4->a); i++)
1382	pVM->pgm.s.pInterPaePML4->a[i].u = X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_A \| PGM_PLXFLAGS_PERMANENT
1383	\| HCPhysInterPaePDPT64;
1384
1385	/*
1386	* Allocate pages for the three possible guest contexts (AMD64, PAE and plain 32-Bit).
1387	* We allocate pages for all three posibilities in order to simplify mappings and
1388	* avoid resource failure during mode switches. So, we need to cover all levels of the
1389	* of the first 4GB down to PD level.
1390	* As with the intermediate context, AMD64 uses the PAE PDPT and PDs.
1391	*/
1392	pVM->pgm.s.pHC32BitPD = (PX86PD)MMR3PageAllocLow(pVM);
1393	pVM->pgm.s.apHCPaePDs[0] = (PX86PDPAE)MMR3PageAlloc(pVM);
1394	pVM->pgm.s.apHCPaePDs[1] = (PX86PDPAE)MMR3PageAlloc(pVM);
1395	AssertRelease((uintptr_t)pVM->pgm.s.apHCPaePDs[0] + PAGE_SIZE == (uintptr_t)pVM->pgm.s.apHCPaePDs[1]);
1396	pVM->pgm.s.apHCPaePDs[2] = (PX86PDPAE)MMR3PageAlloc(pVM);
1397	AssertRelease((uintptr_t)pVM->pgm.s.apHCPaePDs[1] + PAGE_SIZE == (uintptr_t)pVM->pgm.s.apHCPaePDs[2]);
1398	pVM->pgm.s.apHCPaePDs[3] = (PX86PDPAE)MMR3PageAlloc(pVM);
1399	AssertRelease((uintptr_t)pVM->pgm.s.apHCPaePDs[2] + PAGE_SIZE == (uintptr_t)pVM->pgm.s.apHCPaePDs[3]);
1400	pVM->pgm.s.pHCPaePDPT = (PX86PDPT)MMR3PageAllocLow(pVM);
1401	pVM->pgm.s.pHCNestedRoot = MMR3PageAllocLow(pVM);
1402
1403	if ( !pVM->pgm.s.pHC32BitPD
1404	\|\| !pVM->pgm.s.apHCPaePDs[0]
1405	\|\| !pVM->pgm.s.apHCPaePDs[1]
1406	\|\| !pVM->pgm.s.apHCPaePDs[2]
1407	\|\| !pVM->pgm.s.apHCPaePDs[3]
1408	\|\| !pVM->pgm.s.pHCPaePDPT
1409	\|\| !pVM->pgm.s.pHCNestedRoot)
1410	{
1411	AssertMsgFailed(("Failed to allocate pages for the intermediate context!\n"));
1412	return VERR_NO_PAGE_MEMORY;
1413	}
1414
1415	/* get physical addresses. */
1416	pVM->pgm.s.HCPhys32BitPD = MMPage2Phys(pVM, pVM->pgm.s.pHC32BitPD);
1417	Assert(MMPagePhys2Page(pVM, pVM->pgm.s.HCPhys32BitPD) == pVM->pgm.s.pHC32BitPD);
1418	pVM->pgm.s.aHCPhysPaePDs[0] = MMPage2Phys(pVM, pVM->pgm.s.apHCPaePDs[0]);
1419	pVM->pgm.s.aHCPhysPaePDs[1] = MMPage2Phys(pVM, pVM->pgm.s.apHCPaePDs[1]);
1420	pVM->pgm.s.aHCPhysPaePDs[2] = MMPage2Phys(pVM, pVM->pgm.s.apHCPaePDs[2]);
1421	pVM->pgm.s.aHCPhysPaePDs[3] = MMPage2Phys(pVM, pVM->pgm.s.apHCPaePDs[3]);
1422	pVM->pgm.s.HCPhysPaePDPT = MMPage2Phys(pVM, pVM->pgm.s.pHCPaePDPT);
1423	pVM->pgm.s.HCPhysNestedRoot = MMPage2Phys(pVM, pVM->pgm.s.pHCNestedRoot);
1424
1425	/*
1426	* Initialize the pages, setting up the PML4 and PDPT for action below 4GB.
1427	*/
1428	ASMMemZero32(pVM->pgm.s.pHC32BitPD, PAGE_SIZE);
1429	ASMMemZero32(pVM->pgm.s.pHCPaePDPT, PAGE_SIZE);
1430	ASMMemZero32(pVM->pgm.s.pHCNestedRoot, PAGE_SIZE);
1431	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.apHCPaePDs); i++)
1432	{
1433	ASMMemZero32(pVM->pgm.s.apHCPaePDs[i], PAGE_SIZE);
1434	pVM->pgm.s.pHCPaePDPT->a[i].u = X86_PDPE_P \| PGM_PLXFLAGS_PERMANENT \| pVM->pgm.s.aHCPhysPaePDs[i];
1435	/* The flags will be corrected when entering and leaving long mode. */
1436	}
1437
1438	CPUMSetHyperCR3(pVM, (uint32_t)pVM->pgm.s.HCPhys32BitPD);
1439
1440	/*
1441	* Initialize paging workers and mode from current host mode
1442	* and the guest running in real mode.
1443	*/
1444	pVM->pgm.s.enmHostMode = SUPGetPagingMode();
1445	switch (pVM->pgm.s.enmHostMode)
1446	{
1447	case SUPPAGINGMODE_32_BIT:
1448	case SUPPAGINGMODE_32_BIT_GLOBAL:
1449	case SUPPAGINGMODE_PAE:
1450	case SUPPAGINGMODE_PAE_GLOBAL:
1451	case SUPPAGINGMODE_PAE_NX:
1452	case SUPPAGINGMODE_PAE_GLOBAL_NX:
1453	break;
1454
1455	case SUPPAGINGMODE_AMD64:
1456	case SUPPAGINGMODE_AMD64_GLOBAL:
1457	case SUPPAGINGMODE_AMD64_NX:
1458	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
1459	#ifndef VBOX_WITH_HYBIRD_32BIT_KERNEL
1460	if (ARCH_BITS != 64)
1461	{
1462	AssertMsgFailed(("Host mode %d (64-bit) is not supported by non-64bit builds\n", pVM->pgm.s.enmHostMode));
1463	LogRel(("Host mode %d (64-bit) is not supported by non-64bit builds\n", pVM->pgm.s.enmHostMode));
1464	return VERR_PGM_UNSUPPORTED_HOST_PAGING_MODE;
1465	}
1466	#endif
1467	break;
1468	default:
1469	AssertMsgFailed(("Host mode %d is not supported\n", pVM->pgm.s.enmHostMode));
1470	return VERR_PGM_UNSUPPORTED_HOST_PAGING_MODE;
1471	}
1472	rc = pgmR3ModeDataInit(pVM, false /* don't resolve GC and R0 syms yet */);
1473	if (VBOX_SUCCESS(rc))
1474	rc = PGMR3ChangeMode(pVM, PGMMODE_REAL);
1475	if (VBOX_SUCCESS(rc))
1476	{
1477	LogFlow(("pgmR3InitPaging: returns successfully\n"));
1478	#if HC_ARCH_BITS == 64
1479	LogRel(("Debug: HCPhys32BitPD=%VHp aHCPhysPaePDs={%RHp,%RHp,%RHp,%RHp} HCPhysPaePDPT=%RHp HCPhysPaePML4=%RHp\n",
1480	pVM->pgm.s.HCPhys32BitPD,
1481	pVM->pgm.s.aHCPhysPaePDs[0], pVM->pgm.s.aHCPhysPaePDs[1], pVM->pgm.s.aHCPhysPaePDs[2], pVM->pgm.s.aHCPhysPaePDs[3],
1482	pVM->pgm.s.HCPhysPaePDPT,
1483	pVM->pgm.s.HCPhysPaePML4));
1484	LogRel(("Debug: HCPhysInterPD=%RHp HCPhysInterPaePDPT=%RHp HCPhysInterPaePML4=%RHp\n",
1485	pVM->pgm.s.HCPhysInterPD, pVM->pgm.s.HCPhysInterPaePDPT, pVM->pgm.s.HCPhysInterPaePML4));
1486	LogRel(("Debug: apInterPTs={%RHp,%RHp} apInterPaePTs={%RHp,%RHp} apInterPaePDs={%RHp,%RHp,%RHp,%RHp} pInterPaePDPT64=%RHp\n",
1487	MMPage2Phys(pVM, pVM->pgm.s.apInterPTs[0]), MMPage2Phys(pVM, pVM->pgm.s.apInterPTs[1]),
1488	MMPage2Phys(pVM, pVM->pgm.s.apInterPaePTs[0]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePTs[1]),
1489	MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[0]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[1]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[2]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[3]),
1490	MMPage2Phys(pVM, pVM->pgm.s.pInterPaePDPT64)));
1491	#endif
1492
1493	return VINF_SUCCESS;
1494	}
1495
1496	LogFlow(("pgmR3InitPaging: returns %Vrc\n", rc));
1497	return rc;
1498	}
1499
1500
1501	#ifdef VBOX_WITH_STATISTICS
1502	/**
1503	* Init statistics
1504	*/
1505	static void pgmR3InitStats(PVM pVM)
1506	{
1507	PPGM pPGM = &pVM->pgm.s;
1508	unsigned i;
1509
1510	/*
1511	* Note! The layout of this function matches the member layout exactly!
1512	*/
1513
1514	/* Common - misc variables */
1515	STAM_REG(pVM, &pPGM->cAllPages, STAMTYPE_U32, "/PGM/Page/cAllPages", STAMUNIT_OCCURENCES, "The total number of pages.");
1516	STAM_REG(pVM, &pPGM->cPrivatePages, STAMTYPE_U32, "/PGM/Page/cPrivatePages", STAMUNIT_OCCURENCES, "The number of private pages.");
1517	STAM_REG(pVM, &pPGM->cSharedPages, STAMTYPE_U32, "/PGM/Page/cSharedPages", STAMUNIT_OCCURENCES, "The number of shared pages.");
1518	STAM_REG(pVM, &pPGM->cZeroPages, STAMTYPE_U32, "/PGM/Page/cZeroPages", STAMUNIT_OCCURENCES, "The number of zero backed pages.");
1519	STAM_REG(pVM, &pPGM->ChunkR3Map.c, STAMTYPE_U32, "/PGM/ChunkR3Map/c", STAMUNIT_OCCURENCES, "Number of mapped chunks.");
1520	STAM_REG(pVM, &pPGM->ChunkR3Map.cMax, STAMTYPE_U32, "/PGM/ChunkR3Map/cMax", STAMUNIT_OCCURENCES, "Maximum number of mapped chunks.");
1521
1522	/* Common - stats */
1523	#ifdef PGMPOOL_WITH_GCPHYS_TRACKING
1524	STAM_REG(pVM, &pPGM->StatTrackVirgin, STAMTYPE_COUNTER, "/PGM/Track/Virgin", STAMUNIT_OCCURENCES, "The number of first time shadowings");
1525	STAM_REG(pVM, &pPGM->StatTrackAliased, STAMTYPE_COUNTER, "/PGM/Track/Aliased", STAMUNIT_OCCURENCES, "The number of times switching to cRef2, i.e. the page is being shadowed by two PTs.");
1526	STAM_REG(pVM, &pPGM->StatTrackAliasedMany, STAMTYPE_COUNTER, "/PGM/Track/AliasedMany", STAMUNIT_OCCURENCES, "The number of times we're tracking using cRef2.");
1527	STAM_REG(pVM, &pPGM->StatTrackAliasedLots, STAMTYPE_COUNTER, "/PGM/Track/AliasedLots", STAMUNIT_OCCURENCES, "The number of times we're hitting pages which has overflowed cRef2");
1528	STAM_REG(pVM, &pPGM->StatTrackOverflows, STAMTYPE_COUNTER, "/PGM/Track/Overflows", STAMUNIT_OCCURENCES, "The number of times the extent list grows to long.");
1529	STAM_REG(pVM, &pPGM->StatTrackDeref, STAMTYPE_PROFILE, "/PGM/Track/Deref", STAMUNIT_OCCURENCES, "Profiling of SyncPageWorkerTrackDeref (expensive).");
1530	#endif
1531	for (i = 0; i < RT_ELEMENTS(pPGM->StatSyncPtPD); i++)
1532	STAMR3RegisterF(pVM, &pPGM->StatSyncPtPD[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
1533	"The number of SyncPT per PD n.", "/PGM/PDSyncPT/%04X", i);
1534	for (i = 0; i < RT_ELEMENTS(pPGM->StatSyncPagePD); i++)
1535	STAMR3RegisterF(pVM, &pPGM->StatSyncPagePD[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
1536	"The number of SyncPage per PD n.", "/PGM/PDSyncPage/%04X", i);
1537
1538	/* R3 only: */
1539	STAM_REG(pVM, &pPGM->StatR3DetectedConflicts, STAMTYPE_COUNTER, "/PGM/R3/DetectedConflicts", STAMUNIT_OCCURENCES, "The number of times PGMR3CheckMappingConflicts() detected a conflict.");
1540	STAM_REG(pVM, &pPGM->StatR3ResolveConflict, STAMTYPE_PROFILE, "/PGM/R3/ResolveConflict", STAMUNIT_TICKS_PER_CALL, "pgmR3SyncPTResolveConflict() profiling (includes the entire relocation).");
1541	STAM_REG(pVM, &pPGM->StatR3GuestPDWrite, STAMTYPE_COUNTER, "/PGM/R3/PDWrite", STAMUNIT_OCCURENCES, "The total number of times pgmHCGuestPDWriteHandler() was called.");
1542	STAM_REG(pVM, &pPGM->StatR3GuestPDWriteConflict, STAMTYPE_COUNTER, "/PGM/R3/PDWriteConflict", STAMUNIT_OCCURENCES, "The number of times pgmHCGuestPDWriteHandler() detected a conflict.");
1543	STAM_REG(pVM, &pPGM->StatR3DynRamTotal, STAMTYPE_COUNTER, "/PGM/DynAlloc/TotalAlloc", STAMUNIT_MEGABYTES, "Allocated MBs of guest ram.");
1544	STAM_REG(pVM, &pPGM->StatR3DynRamGrow, STAMTYPE_COUNTER, "/PGM/DynAlloc/Grow", STAMUNIT_OCCURENCES, "Nr of pgmr3PhysGrowRange calls.");
1545
1546	/* GC only: */
1547	STAM_REG(pVM, &pPGM->StatRCInvalidatePage, STAMTYPE_PROFILE, "/PGM/RC/InvalidatePage", STAMUNIT_TICKS_PER_CALL, "PGMGCInvalidatePage() profiling.");
1548	STAM_REG(pVM, &pPGM->StatRCDynMapCacheHits, STAMTYPE_COUNTER, "/PGM/RC/DynMapCache/Hits" , STAMUNIT_OCCURENCES, "Number of dynamic page mapping cache hits.");
1549	STAM_REG(pVM, &pPGM->StatRCDynMapCacheMisses, STAMTYPE_COUNTER, "/PGM/RC/DynMapCache/Misses" , STAMUNIT_OCCURENCES, "Number of dynamic page mapping cache misses.");
1550
1551	/* RZ only: */
1552	STAM_REG(pVM, &pPGM->StatRZTrap0e, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMTrap0eHandler() body.");
1553	STAM_REG(pVM, &pPGM->StatRZTrap0eTimeCheckPageFault, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time/CheckPageFault", STAMUNIT_TICKS_PER_CALL, "Profiling of checking for dirty/access emulation faults.");
1554	STAM_REG(pVM, &pPGM->StatRZTrap0eTimeSyncPT, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time/SyncPT", STAMUNIT_TICKS_PER_CALL, "Profiling of lazy page table syncing.");
1555	STAM_REG(pVM, &pPGM->StatRZTrap0eTimeMapping, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time/Mapping", STAMUNIT_TICKS_PER_CALL, "Profiling of checking virtual mappings.");
1556	STAM_REG(pVM, &pPGM->StatRZTrap0eTimeOutOfSync, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time/OutOfSync", STAMUNIT_TICKS_PER_CALL, "Profiling of out of sync page handling.");
1557	STAM_REG(pVM, &pPGM->StatRZTrap0eTimeHandlers, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time/Handlers", STAMUNIT_TICKS_PER_CALL, "Profiling of checking handlers.");
1558	STAM_REG(pVM, &pPGM->StatRZTrap0eTime2CSAM, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time2/CSAM", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is CSAM.");
1559	STAM_REG(pVM, &pPGM->StatRZTrap0eTime2DirtyAndAccessed, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time2/DirtyAndAccessedBits", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is dirty and/or accessed bit emulation.");
1560	STAM_REG(pVM, &pPGM->StatRZTrap0eTime2GuestTrap, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time2/GuestTrap", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is a guest trap.");
1561	STAM_REG(pVM, &pPGM->StatRZTrap0eTime2HndPhys, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time2/HandlerPhysical", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is a physical handler.");
1562	STAM_REG(pVM, &pPGM->StatRZTrap0eTime2HndVirt, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time2/HandlerVirtual", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is a virtual handler.");
1563	STAM_REG(pVM, &pPGM->StatRZTrap0eTime2HndUnhandled, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time2/HandlerUnhandled", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is access outside the monitored areas of a monitored page.");
1564	STAM_REG(pVM, &pPGM->StatRZTrap0eTime2Misc, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time2/Misc", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is not known.");
1565	STAM_REG(pVM, &pPGM->StatRZTrap0eTime2OutOfSync, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time2/OutOfSync", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is an out-of-sync page.");
1566	STAM_REG(pVM, &pPGM->StatRZTrap0eTime2OutOfSyncHndPhys, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time2/OutOfSyncHndPhys", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is an out-of-sync physical handler page.");
1567	STAM_REG(pVM, &pPGM->StatRZTrap0eTime2OutOfSyncHndVirt, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time2/OutOfSyncHndVirt", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is an out-of-sync virtual handler page.");
1568	STAM_REG(pVM, &pPGM->StatRZTrap0eTime2OutOfSyncHndObs, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time2/OutOfSyncObsHnd", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is an obsolete handler page.");
1569	STAM_REG(pVM, &pPGM->StatRZTrap0eTime2SyncPT, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time2/SyncPT", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is lazy syncing of a PT.");
1570	STAM_REG(pVM, &pPGM->StatRZTrap0eConflicts, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Conflicts", STAMUNIT_OCCURENCES, "The number of times #PF was caused by an undetected conflict.");
1571	STAM_REG(pVM, &pPGM->StatRZTrap0eHandlersMapping, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Handlers/Mapping", STAMUNIT_OCCURENCES, "Number of traps due to access handlers in mappings.");
1572	STAM_REG(pVM, &pPGM->StatRZTrap0eHandlersOutOfSync, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Handlers/OutOfSync", STAMUNIT_OCCURENCES, "Number of traps due to out-of-sync handled pages.");
1573	STAM_REG(pVM, &pPGM->StatRZTrap0eHandlersPhysical, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Handlers/Physical", STAMUNIT_OCCURENCES, "Number of traps due to physical access handlers.");
1574	STAM_REG(pVM, &pPGM->StatRZTrap0eHandlersVirtual, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Handlers/Virtual", STAMUNIT_OCCURENCES, "Number of traps due to virtual access handlers.");
1575	STAM_REG(pVM, &pPGM->StatRZTrap0eHandlersVirtualByPhys, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Handlers/VirtualByPhys", STAMUNIT_OCCURENCES, "Number of traps due to virtual access handlers by physical address.");
1576	STAM_REG(pVM, &pPGM->StatRZTrap0eHandlersVirtualUnmarked,STAMTYPE_COUNTER,"/PGM/RZ/Trap0e/Handlers/VirtualUnmarked",STAMUNIT_OCCURENCES, "Number of traps due to virtual access handlers by virtual address (without proper physical flags).");
1577	STAM_REG(pVM, &pPGM->StatRZTrap0eHandlersUnhandled, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Handlers/Unhandled", STAMUNIT_OCCURENCES, "Number of traps due to access outside range of monitored page(s).");
1578	STAM_REG(pVM, &pPGM->StatRZTrap0eHandlersInvalid, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Handlers/Invalid", STAMUNIT_OCCURENCES, "Number of traps due to access to invalid physical memory.");
1579	STAM_REG(pVM, &pPGM->StatRZTrap0eUSNotPresentRead, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Err/User/NPRead", STAMUNIT_OCCURENCES, "Number of user mode not present read page faults.");
1580	STAM_REG(pVM, &pPGM->StatRZTrap0eUSNotPresentWrite, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Err/User/NPWrite", STAMUNIT_OCCURENCES, "Number of user mode not present write page faults.");
1581	STAM_REG(pVM, &pPGM->StatRZTrap0eUSWrite, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Err/User/Write", STAMUNIT_OCCURENCES, "Number of user mode write page faults.");
1582	STAM_REG(pVM, &pPGM->StatRZTrap0eUSReserved, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Err/User/Reserved", STAMUNIT_OCCURENCES, "Number of user mode reserved bit page faults.");
1583	STAM_REG(pVM, &pPGM->StatRZTrap0eUSNXE, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Err/User/NXE", STAMUNIT_OCCURENCES, "Number of user mode NXE page faults.");
1584	STAM_REG(pVM, &pPGM->StatRZTrap0eUSRead, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Err/User/Read", STAMUNIT_OCCURENCES, "Number of user mode read page faults.");
1585	STAM_REG(pVM, &pPGM->StatRZTrap0eSVNotPresentRead, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Err/Supervisor/NPRead", STAMUNIT_OCCURENCES, "Number of supervisor mode not present read page faults.");
1586	STAM_REG(pVM, &pPGM->StatRZTrap0eSVNotPresentWrite, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Err/Supervisor/NPWrite", STAMUNIT_OCCURENCES, "Number of supervisor mode not present write page faults.");
1587	STAM_REG(pVM, &pPGM->StatRZTrap0eSVWrite, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Err/Supervisor/Write", STAMUNIT_OCCURENCES, "Number of supervisor mode write page faults.");
1588	STAM_REG(pVM, &pPGM->StatRZTrap0eSVReserved, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Err/Supervisor/Reserved", STAMUNIT_OCCURENCES, "Number of supervisor mode reserved bit page faults.");
1589	STAM_REG(pVM, &pPGM->StatRZTrap0eSNXE, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Err/Supervisor/NXE", STAMUNIT_OCCURENCES, "Number of supervisor mode NXE page faults.");
1590	STAM_REG(pVM, &pPGM->StatRZTrap0eGuestPF, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/GuestPF", STAMUNIT_OCCURENCES, "Number of real guest page faults.");
1591	STAM_REG(pVM, &pPGM->StatRZTrap0eGuestPFUnh, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/GuestPF/Unhandled", STAMUNIT_OCCURENCES, "Number of real guest page faults from the 'unhandled' case.");
1592	STAM_REG(pVM, &pPGM->StatRZTrap0eGuestPFMapping, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/GuestPF/InMapping", STAMUNIT_OCCURENCES, "Number of real guest page faults in a mapping.");
1593	STAM_REG(pVM, &pPGM->StatRZTrap0eWPEmulInRZ, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/WP/InRZ", STAMUNIT_OCCURENCES, "Number of guest page faults due to X86_CR0_WP emulation.");
1594	STAM_REG(pVM, &pPGM->StatRZTrap0eWPEmulToR3, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/WP/ToR3", STAMUNIT_OCCURENCES, "Number of guest page faults due to X86_CR0_WP emulation (forward to R3 for emulation).");
1595	for (i = 0; i < RT_ELEMENTS(pPGM->StatRZTrap0ePD); i++)
1596	STAMR3RegisterF(pVM, &pPGM->StatRZTrap0ePD[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
1597	"The number of traps in page directory n.", "/PGM/RZ/Trap0e/PD/%04X", i);
1598	STAM_REG(pVM, &pPGM->StatRZGuestCR3WriteHandled, STAMTYPE_COUNTER, "/PGM/RZ/CR3WriteHandled", STAMUNIT_OCCURENCES, "The number of times the Guest CR3 change was successfully handled.");
1599	STAM_REG(pVM, &pPGM->StatRZGuestCR3WriteUnhandled, STAMTYPE_COUNTER, "/PGM/RZ/CR3WriteUnhandled", STAMUNIT_OCCURENCES, "The number of times the Guest CR3 change was passed back to the recompiler.");
1600	STAM_REG(pVM, &pPGM->StatRZGuestCR3WriteConflict, STAMTYPE_COUNTER, "/PGM/RZ/CR3WriteConflict", STAMUNIT_OCCURENCES, "The number of times the Guest CR3 monitoring detected a conflict.");
1601	STAM_REG(pVM, &pPGM->StatRZGuestROMWriteHandled, STAMTYPE_COUNTER, "/PGM/RZ/ROMWriteHandled", STAMUNIT_OCCURENCES, "The number of times the Guest ROM change was successfully handled.");
1602	STAM_REG(pVM, &pPGM->StatRZGuestROMWriteUnhandled, STAMTYPE_COUNTER, "/PGM/RZ/ROMWriteUnhandled", STAMUNIT_OCCURENCES, "The number of times the Guest ROM change was passed back to the recompiler.");
1603
1604	/* HC only: */
1605
1606	/* RZ & R3: */
1607	STAM_REG(pVM, &pPGM->StatRZSyncCR3, STAMTYPE_PROFILE, "/PGM/RZ/SyncCR3", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMSyncCR3() body.");
1608	STAM_REG(pVM, &pPGM->StatRZSyncCR3Handlers, STAMTYPE_PROFILE, "/PGM/RZ/SyncCR3/Handlers", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMSyncCR3() update handler section.");
1609	STAM_REG(pVM, &pPGM->StatRZSyncCR3HandlerVirtualUpdate, STAMTYPE_PROFILE, "/PGM/RZ/SyncCR3/Handlers/VirtualUpdate", STAMUNIT_TICKS_PER_CALL, "Profiling of the virtual handler updates.");
1610	STAM_REG(pVM, &pPGM->StatRZSyncCR3HandlerVirtualReset, STAMTYPE_PROFILE, "/PGM/RZ/SyncCR3/Handlers/VirtualReset", STAMUNIT_TICKS_PER_CALL, "Profiling of the virtual handler resets.");
1611	STAM_REG(pVM, &pPGM->StatRZSyncCR3Global, STAMTYPE_COUNTER, "/PGM/RZ/SyncCR3/Global", STAMUNIT_OCCURENCES, "The number of global CR3 syncs.");
1612	STAM_REG(pVM, &pPGM->StatRZSyncCR3NotGlobal, STAMTYPE_COUNTER, "/PGM/RZ/SyncCR3/NotGlobal", STAMUNIT_OCCURENCES, "The number of non-global CR3 syncs.");
1613	STAM_REG(pVM, &pPGM->StatRZSyncCR3DstCacheHit, STAMTYPE_COUNTER, "/PGM/RZ/SyncCR3/DstChacheHit", STAMUNIT_OCCURENCES, "The number of times we got some kind of a cache hit.");
1614	STAM_REG(pVM, &pPGM->StatRZSyncCR3DstFreed, STAMTYPE_COUNTER, "/PGM/RZ/SyncCR3/DstFreed", STAMUNIT_OCCURENCES, "The number of times we've had to free a shadow entry.");
1615	STAM_REG(pVM, &pPGM->StatRZSyncCR3DstFreedSrcNP, STAMTYPE_COUNTER, "/PGM/RZ/SyncCR3/DstFreedSrcNP", STAMUNIT_OCCURENCES, "The number of times we've had to free a shadow entry for which the source entry was not present.");
1616	STAM_REG(pVM, &pPGM->StatRZSyncCR3DstNotPresent, STAMTYPE_COUNTER, "/PGM/RZ/SyncCR3/DstNotPresent", STAMUNIT_OCCURENCES, "The number of times we've encountered a not present shadow entry for a present guest entry.");
1617	STAM_REG(pVM, &pPGM->StatRZSyncCR3DstSkippedGlobalPD, STAMTYPE_COUNTER, "/PGM/RZ/SyncCR3/DstSkippedGlobalPD", STAMUNIT_OCCURENCES, "The number of times a global page directory wasn't flushed.");
1618	STAM_REG(pVM, &pPGM->StatRZSyncCR3DstSkippedGlobalPT, STAMTYPE_COUNTER, "/PGM/RZ/SyncCR3/DstSkippedGlobalPT", STAMUNIT_OCCURENCES, "The number of times a page table with only global entries wasn't flushed.");
1619	STAM_REG(pVM, &pPGM->StatRZSyncPT, STAMTYPE_PROFILE, "/PGM/RZ/SyncPT", STAMUNIT_TICKS_PER_CALL, "Profiling of the pfnSyncPT() body.");
1620	STAM_REG(pVM, &pPGM->StatRZSyncPTFailed, STAMTYPE_COUNTER, "/PGM/RZ/SyncPT/Failed", STAMUNIT_OCCURENCES, "The number of times pfnSyncPT() failed.");
1621	STAM_REG(pVM, &pPGM->StatRZSyncPT4K, STAMTYPE_COUNTER, "/PGM/RZ/SyncPT/4K", STAMUNIT_OCCURENCES, "Nr of 4K PT syncs");
1622	STAM_REG(pVM, &pPGM->StatRZSyncPT4M, STAMTYPE_COUNTER, "/PGM/RZ/SyncPT/4M", STAMUNIT_OCCURENCES, "Nr of 4M PT syncs");
1623	STAM_REG(pVM, &pPGM->StatRZSyncPagePDNAs, STAMTYPE_COUNTER, "/PGM/RZ/SyncPagePDNAs", STAMUNIT_OCCURENCES, "The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit.");
1624	STAM_REG(pVM, &pPGM->StatRZSyncPagePDOutOfSync, STAMTYPE_COUNTER, "/PGM/RZ/SyncPagePDOutOfSync", STAMUNIT_OCCURENCES, "The number of time we've encountered an out-of-sync PD in SyncPage.");
1625	STAM_REG(pVM, &pPGM->StatRZAccessedPage, STAMTYPE_COUNTER, "/PGM/RZ/AccessedPage", STAMUNIT_OCCURENCES, "The number of pages marked not present for accessed bit emulation.");
1626	STAM_REG(pVM, &pPGM->StatRZDirtyBitTracking, STAMTYPE_PROFILE, "/PGM/RZ/DirtyPage", STAMUNIT_TICKS_PER_CALL, "Profiling the dirty bit tracking in CheckPageFault().");
1627	STAM_REG(pVM, &pPGM->StatRZDirtyPage, STAMTYPE_COUNTER, "/PGM/RZ/DirtyPage/Mark", STAMUNIT_OCCURENCES, "The number of pages marked read-only for dirty bit tracking.");
1628	STAM_REG(pVM, &pPGM->StatRZDirtyPageBig, STAMTYPE_COUNTER, "/PGM/RZ/DirtyPage/MarkBig", STAMUNIT_OCCURENCES, "The number of 4MB pages marked read-only for dirty bit tracking.");
1629	STAM_REG(pVM, &pPGM->StatRZDirtyPageSkipped, STAMTYPE_COUNTER, "/PGM/RZ/DirtyPage/Skipped", STAMUNIT_OCCURENCES, "The number of pages already dirty or readonly.");
1630	STAM_REG(pVM, &pPGM->StatRZDirtyPageTrap, STAMTYPE_COUNTER, "/PGM/RZ/DirtyPage/Trap", STAMUNIT_OCCURENCES, "The number of traps generated for dirty bit tracking.");
1631	STAM_REG(pVM, &pPGM->StatRZDirtiedPage, STAMTYPE_COUNTER, "/PGM/RZ/DirtyPage/SetDirty", STAMUNIT_OCCURENCES, "The number of pages marked dirty because of write accesses.");
1632	STAM_REG(pVM, &pPGM->StatRZDirtyTrackRealPF, STAMTYPE_COUNTER, "/PGM/RZ/DirtyPage/RealPF", STAMUNIT_OCCURENCES, "The number of real pages faults during dirty bit tracking.");
1633	STAM_REG(pVM, &pPGM->StatRZPageAlreadyDirty, STAMTYPE_COUNTER, "/PGM/RZ/DirtyPage/AlreadySet", STAMUNIT_OCCURENCES, "The number of pages already marked dirty because of write accesses.");
1634	STAM_REG(pVM, &pPGM->StatRZInvalidatePage, STAMTYPE_PROFILE, "/PGM/RZ/InvalidatePage", STAMUNIT_TICKS_PER_CALL, "PGMInvalidatePage() profiling.");
1635	STAM_REG(pVM, &pPGM->StatRZInvalidatePage4KBPages, STAMTYPE_COUNTER, "/PGM/RZ/InvalidatePage/4KBPages", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was called for a 4KB page.");
1636	STAM_REG(pVM, &pPGM->StatRZInvalidatePage4MBPages, STAMTYPE_COUNTER, "/PGM/RZ/InvalidatePage/4MBPages", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was called for a 4MB page.");
1637	STAM_REG(pVM, &pPGM->StatRZInvalidatePage4MBPagesSkip, STAMTYPE_COUNTER, "/PGM/RZ/InvalidatePage/4MBPagesSkip",STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() skipped a 4MB page.");
1638	STAM_REG(pVM, &pPGM->StatRZInvalidatePagePDMappings, STAMTYPE_COUNTER, "/PGM/RZ/InvalidatePage/PDMappings", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict).");
1639	STAM_REG(pVM, &pPGM->StatRZInvalidatePagePDNAs, STAMTYPE_COUNTER, "/PGM/RZ/InvalidatePage/PDNAs", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was called for a not accessed page directory.");
1640	STAM_REG(pVM, &pPGM->StatRZInvalidatePagePDNPs, STAMTYPE_COUNTER, "/PGM/RZ/InvalidatePage/PDNPs", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was called for a not present page directory.");
1641	STAM_REG(pVM, &pPGM->StatRZInvalidatePagePDOutOfSync, STAMTYPE_COUNTER, "/PGM/RZ/InvalidatePage/PDOutOfSync", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was called for an out of sync page directory.");
1642	STAM_REG(pVM, &pPGM->StatRZInvalidatePageSkipped, STAMTYPE_COUNTER, "/PGM/RZ/InvalidatePage/Skipped", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3.");
1643	STAM_REG(pVM, &pPGM->StatRZVirtHandlerSearchByPhys, STAMTYPE_PROFILE, "/PGM/RZ/VirtHandlerSearchByPhys", STAMUNIT_TICKS_PER_CALL, "Profiling of pgmHandlerVirtualFindByPhysAddr.");
1644	STAM_REG(pVM, &pPGM->StatRZPhysHandlerReset, STAMTYPE_COUNTER, "/PGM/RZ/PhysHandlerReset", STAMUNIT_OCCURENCES, "The number of times PGMHandlerPhysicalReset is called.");
1645	STAM_REG(pVM, &pPGM->StatRZPageOutOfSyncSupervisor, STAMTYPE_COUNTER, "/PGM/RZ/OutOfSync/SuperVisor", STAMUNIT_OCCURENCES, "Number of traps due to pages out of sync and times VerifyAccessSyncPage calls SyncPage.");
1646	STAM_REG(pVM, &pPGM->StatRZPageOutOfSyncUser, STAMTYPE_COUNTER, "/PGM/RZ/OutOfSync/User", STAMUNIT_OCCURENCES, "Number of traps due to pages out of sync and times VerifyAccessSyncPage calls SyncPage.");
1647	STAM_REG(pVM, &pPGM->StatRZPrefetch, STAMTYPE_PROFILE, "/PGM/RZ/Prefetch", STAMUNIT_TICKS_PER_CALL, "PGMPrefetchPage profiling.");
1648	STAM_REG(pVM, &pPGM->StatRZChunkR3MapTlbHits, STAMTYPE_COUNTER, "/PGM/ChunkR3Map/TlbHitsRZ", STAMUNIT_OCCURENCES, "TLB hits.");
1649	STAM_REG(pVM, &pPGM->StatRZChunkR3MapTlbMisses, STAMTYPE_COUNTER, "/PGM/ChunkR3Map/TlbMissesRZ", STAMUNIT_OCCURENCES, "TLB misses.");
1650	STAM_REG(pVM, &pPGM->StatRZPageMapTlbHits, STAMTYPE_COUNTER, "/PGM/RZ/Page/MapTlbHits", STAMUNIT_OCCURENCES, "TLB hits.");
1651	STAM_REG(pVM, &pPGM->StatRZPageMapTlbMisses, STAMTYPE_COUNTER, "/PGM/RZ/Page/MapTlbMisses", STAMUNIT_OCCURENCES, "TLB misses.");
1652	STAM_REG(pVM, &pPGM->StatRZPageReplaceShared, STAMTYPE_COUNTER, "/PGM/RZ/Page/ReplacedShared", STAMUNIT_OCCURENCES, "Times a shared page was replaced.");
1653	STAM_REG(pVM, &pPGM->StatRZPageReplaceZero, STAMTYPE_COUNTER, "/PGM/RZ/Page/ReplacedZero", STAMUNIT_OCCURENCES, "Times the zero page was replaced.");
1654	/// @todo STAM_REG(pVM, &pPGM->StatRZPageHandyAllocs, STAMTYPE_COUNTER, "/PGM/RZ/Page/HandyAllocs", STAMUNIT_OCCURENCES, "Number of times we've allocated more handy pages.");
1655	STAM_REG(pVM, &pPGM->StatRZFlushTLB, STAMTYPE_PROFILE, "/PGM/RZ/FlushTLB", STAMUNIT_OCCURENCES, "Profiling of the PGMFlushTLB() body.");
1656	STAM_REG(pVM, &pPGM->StatRZFlushTLBNewCR3, STAMTYPE_COUNTER, "/PGM/RZ/FlushTLB/NewCR3", STAMUNIT_OCCURENCES, "The number of times PGMFlushTLB was called with a new CR3, non-global. (switch)");
1657	STAM_REG(pVM, &pPGM->StatRZFlushTLBNewCR3Global, STAMTYPE_COUNTER, "/PGM/RZ/FlushTLB/NewCR3Global", STAMUNIT_OCCURENCES, "The number of times PGMFlushTLB was called with a new CR3, global. (switch)");
1658	STAM_REG(pVM, &pPGM->StatRZFlushTLBSameCR3, STAMTYPE_COUNTER, "/PGM/RZ/FlushTLB/SameCR3", STAMUNIT_OCCURENCES, "The number of times PGMFlushTLB was called with the same CR3, non-global. (flush)");
1659	STAM_REG(pVM, &pPGM->StatRZFlushTLBSameCR3Global, STAMTYPE_COUNTER, "/PGM/RZ/FlushTLB/SameCR3Global", STAMUNIT_OCCURENCES, "The number of times PGMFlushTLB was called with the same CR3, global. (flush)");
1660	STAM_REG(pVM, &pPGM->StatRZGstModifyPage, STAMTYPE_PROFILE, "/PGM/RZ/GstModifyPage", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMGstModifyPage() body.");
1661
1662	STAM_REG(pVM, &pPGM->StatR3SyncCR3, STAMTYPE_PROFILE, "/PGM/R3/SyncCR3", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMSyncCR3() body.");
1663	STAM_REG(pVM, &pPGM->StatR3SyncCR3Handlers, STAMTYPE_PROFILE, "/PGM/R3/SyncCR3/Handlers", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMSyncCR3() update handler section.");
1664	STAM_REG(pVM, &pPGM->StatR3SyncCR3HandlerVirtualUpdate, STAMTYPE_PROFILE, "/PGM/R3/SyncCR3/Handlers/VirtualUpdate", STAMUNIT_TICKS_PER_CALL, "Profiling of the virtual handler updates.");
1665	STAM_REG(pVM, &pPGM->StatR3SyncCR3HandlerVirtualReset, STAMTYPE_PROFILE, "/PGM/R3/SyncCR3/Handlers/VirtualReset", STAMUNIT_TICKS_PER_CALL, "Profiling of the virtual handler resets.");
1666	STAM_REG(pVM, &pPGM->StatR3SyncCR3Global, STAMTYPE_COUNTER, "/PGM/R3/SyncCR3/Global", STAMUNIT_OCCURENCES, "The number of global CR3 syncs.");
1667	STAM_REG(pVM, &pPGM->StatR3SyncCR3NotGlobal, STAMTYPE_COUNTER, "/PGM/R3/SyncCR3/NotGlobal", STAMUNIT_OCCURENCES, "The number of non-global CR3 syncs.");
1668	STAM_REG(pVM, &pPGM->StatR3SyncCR3DstCacheHit, STAMTYPE_COUNTER, "/PGM/R3/SyncCR3/DstChacheHit", STAMUNIT_OCCURENCES, "The number of times we got some kind of a cache hit.");
1669	STAM_REG(pVM, &pPGM->StatR3SyncCR3DstFreed, STAMTYPE_COUNTER, "/PGM/R3/SyncCR3/DstFreed", STAMUNIT_OCCURENCES, "The number of times we've had to free a shadow entry.");
1670	STAM_REG(pVM, &pPGM->StatR3SyncCR3DstFreedSrcNP, STAMTYPE_COUNTER, "/PGM/R3/SyncCR3/DstFreedSrcNP", STAMUNIT_OCCURENCES, "The number of times we've had to free a shadow entry for which the source entry was not present.");
1671	STAM_REG(pVM, &pPGM->StatR3SyncCR3DstNotPresent, STAMTYPE_COUNTER, "/PGM/R3/SyncCR3/DstNotPresent", STAMUNIT_OCCURENCES, "The number of times we've encountered a not present shadow entry for a present guest entry.");
1672	STAM_REG(pVM, &pPGM->StatR3SyncCR3DstSkippedGlobalPD, STAMTYPE_COUNTER, "/PGM/R3/SyncCR3/DstSkippedGlobalPD", STAMUNIT_OCCURENCES, "The number of times a global page directory wasn't flushed.");
1673	STAM_REG(pVM, &pPGM->StatR3SyncCR3DstSkippedGlobalPT, STAMTYPE_COUNTER, "/PGM/R3/SyncCR3/DstSkippedGlobalPT", STAMUNIT_OCCURENCES, "The number of times a page table with only global entries wasn't flushed.");
1674	STAM_REG(pVM, &pPGM->StatR3SyncPT, STAMTYPE_PROFILE, "/PGM/R3/SyncPT", STAMUNIT_TICKS_PER_CALL, "Profiling of the pfnSyncPT() body.");
1675	STAM_REG(pVM, &pPGM->StatR3SyncPTFailed, STAMTYPE_COUNTER, "/PGM/R3/SyncPT/Failed", STAMUNIT_OCCURENCES, "The number of times pfnSyncPT() failed.");
1676	STAM_REG(pVM, &pPGM->StatR3SyncPT4K, STAMTYPE_COUNTER, "/PGM/R3/SyncPT/4K", STAMUNIT_OCCURENCES, "Nr of 4K PT syncs");
1677	STAM_REG(pVM, &pPGM->StatR3SyncPT4M, STAMTYPE_COUNTER, "/PGM/R3/SyncPT/4M", STAMUNIT_OCCURENCES, "Nr of 4M PT syncs");
1678	STAM_REG(pVM, &pPGM->StatR3SyncPagePDNAs, STAMTYPE_COUNTER, "/PGM/R3/SyncPagePDNAs", STAMUNIT_OCCURENCES, "The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit.");
1679	STAM_REG(pVM, &pPGM->StatR3SyncPagePDOutOfSync, STAMTYPE_COUNTER, "/PGM/R3/SyncPagePDOutOfSync", STAMUNIT_OCCURENCES, "The number of time we've encountered an out-of-sync PD in SyncPage.");
1680	STAM_REG(pVM, &pPGM->StatR3AccessedPage, STAMTYPE_COUNTER, "/PGM/R3/AccessedPage", STAMUNIT_OCCURENCES, "The number of pages marked not present for accessed bit emulation.");
1681	STAM_REG(pVM, &pPGM->StatR3DirtyBitTracking, STAMTYPE_PROFILE, "/PGM/R3/DirtyPage", STAMUNIT_TICKS_PER_CALL, "Profiling the dirty bit tracking in CheckPageFault().");
1682	STAM_REG(pVM, &pPGM->StatR3DirtyPage, STAMTYPE_COUNTER, "/PGM/R3/DirtyPage/Mark", STAMUNIT_OCCURENCES, "The number of pages marked read-only for dirty bit tracking.");
1683	STAM_REG(pVM, &pPGM->StatR3DirtyPageBig, STAMTYPE_COUNTER, "/PGM/R3/DirtyPage/MarkBig", STAMUNIT_OCCURENCES, "The number of 4MB pages marked read-only for dirty bit tracking.");
1684	STAM_REG(pVM, &pPGM->StatR3DirtyPageSkipped, STAMTYPE_COUNTER, "/PGM/R3/DirtyPage/Skipped", STAMUNIT_OCCURENCES, "The number of pages already dirty or readonly.");
1685	STAM_REG(pVM, &pPGM->StatR3DirtyPageTrap, STAMTYPE_COUNTER, "/PGM/R3/DirtyPage/Trap", STAMUNIT_OCCURENCES, "The number of traps generated for dirty bit tracking.");
1686	STAM_REG(pVM, &pPGM->StatR3DirtiedPage, STAMTYPE_COUNTER, "/PGM/R3/DirtyPage/SetDirty", STAMUNIT_OCCURENCES, "The number of pages marked dirty because of write accesses.");
1687	STAM_REG(pVM, &pPGM->StatR3DirtyTrackRealPF, STAMTYPE_COUNTER, "/PGM/R3/DirtyPage/RealPF", STAMUNIT_OCCURENCES, "The number of real pages faults during dirty bit tracking.");
1688	STAM_REG(pVM, &pPGM->StatR3PageAlreadyDirty, STAMTYPE_COUNTER, "/PGM/R3/DirtyPage/AlreadySet", STAMUNIT_OCCURENCES, "The number of pages already marked dirty because of write accesses.");
1689	STAM_REG(pVM, &pPGM->StatR3InvalidatePage, STAMTYPE_PROFILE, "/PGM/R3/InvalidatePage", STAMUNIT_TICKS_PER_CALL, "PGMInvalidatePage() profiling.");
1690	STAM_REG(pVM, &pPGM->StatR3InvalidatePage4KBPages, STAMTYPE_COUNTER, "/PGM/R3/InvalidatePage/4KBPages", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was called for a 4KB page.");
1691	STAM_REG(pVM, &pPGM->StatR3InvalidatePage4MBPages, STAMTYPE_COUNTER, "/PGM/R3/InvalidatePage/4MBPages", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was called for a 4MB page.");
1692	STAM_REG(pVM, &pPGM->StatR3InvalidatePage4MBPagesSkip, STAMTYPE_COUNTER, "/PGM/R3/InvalidatePage/4MBPagesSkip",STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() skipped a 4MB page.");
1693	STAM_REG(pVM, &pPGM->StatR3InvalidatePagePDMappings, STAMTYPE_COUNTER, "/PGM/R3/InvalidatePage/PDMappings", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict).");
1694	STAM_REG(pVM, &pPGM->StatR3InvalidatePagePDNAs, STAMTYPE_COUNTER, "/PGM/R3/InvalidatePage/PDNAs", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was called for a not accessed page directory.");
1695	STAM_REG(pVM, &pPGM->StatR3InvalidatePagePDNPs, STAMTYPE_COUNTER, "/PGM/R3/InvalidatePage/PDNPs", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was called for a not present page directory.");
1696	STAM_REG(pVM, &pPGM->StatR3InvalidatePagePDOutOfSync, STAMTYPE_COUNTER, "/PGM/R3/InvalidatePage/PDOutOfSync", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was called for an out of sync page directory.");
1697	STAM_REG(pVM, &pPGM->StatR3InvalidatePageSkipped, STAMTYPE_COUNTER, "/PGM/R3/InvalidatePage/Skipped", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3.");
1698	STAM_REG(pVM, &pPGM->StatR3VirtHandlerSearchByPhys, STAMTYPE_PROFILE, "/PGM/R3/VirtHandlerSearchByPhys", STAMUNIT_TICKS_PER_CALL, "Profiling of pgmHandlerVirtualFindByPhysAddr.");
1699	STAM_REG(pVM, &pPGM->StatR3PhysHandlerReset, STAMTYPE_COUNTER, "/PGM/R3/PhysHandlerReset", STAMUNIT_OCCURENCES, "The number of times PGMHandlerPhysicalReset is called.");
1700	STAM_REG(pVM, &pPGM->StatR3PageOutOfSyncSupervisor, STAMTYPE_COUNTER, "/PGM/R3/OutOfSync/SuperVisor", STAMUNIT_OCCURENCES, "Number of traps due to pages out of sync and times VerifyAccessSyncPage calls SyncPage.");
1701	STAM_REG(pVM, &pPGM->StatR3PageOutOfSyncUser, STAMTYPE_COUNTER, "/PGM/R3/OutOfSync/User", STAMUNIT_OCCURENCES, "Number of traps due to pages out of sync and times VerifyAccessSyncPage calls SyncPage.");
1702	STAM_REG(pVM, &pPGM->StatR3Prefetch, STAMTYPE_PROFILE, "/PGM/R3/Prefetch", STAMUNIT_TICKS_PER_CALL, "PGMPrefetchPage profiling.");
1703	STAM_REG(pVM, &pPGM->StatR3ChunkR3MapTlbHits, STAMTYPE_COUNTER, "/PGM/ChunkR3Map/TlbHitsR3", STAMUNIT_OCCURENCES, "TLB hits.");
1704	STAM_REG(pVM, &pPGM->StatR3ChunkR3MapTlbMisses, STAMTYPE_COUNTER, "/PGM/ChunkR3Map/TlbMissesR3", STAMUNIT_OCCURENCES, "TLB misses.");
1705	STAM_REG(pVM, &pPGM->StatR3PageMapTlbHits, STAMTYPE_COUNTER, "/PGM/R3/Page/MapTlbHits", STAMUNIT_OCCURENCES, "TLB hits.");
1706	STAM_REG(pVM, &pPGM->StatR3PageMapTlbMisses, STAMTYPE_COUNTER, "/PGM/R3/Page/MapTlbMisses", STAMUNIT_OCCURENCES, "TLB misses.");
1707	STAM_REG(pVM, &pPGM->StatR3PageReplaceShared, STAMTYPE_COUNTER, "/PGM/R3/Page/ReplacedShared", STAMUNIT_OCCURENCES, "Times a shared page was replaced.");
1708	STAM_REG(pVM, &pPGM->StatR3PageReplaceZero, STAMTYPE_COUNTER, "/PGM/R3/Page/ReplacedZero", STAMUNIT_OCCURENCES, "Times the zero page was replaced.");
1709	/// @todo STAM_REG(pVM, &pPGM->StatR3PageHandyAllocs, STAMTYPE_COUNTER, "/PGM/R3/Page/HandyAllocs", STAMUNIT_OCCURENCES, "Number of times we've allocated more handy pages.");
1710	STAM_REG(pVM, &pPGM->StatR3FlushTLB, STAMTYPE_PROFILE, "/PGM/R3/FlushTLB", STAMUNIT_OCCURENCES, "Profiling of the PGMFlushTLB() body.");
1711	STAM_REG(pVM, &pPGM->StatR3FlushTLBNewCR3, STAMTYPE_COUNTER, "/PGM/R3/FlushTLB/NewCR3", STAMUNIT_OCCURENCES, "The number of times PGMFlushTLB was called with a new CR3, non-global. (switch)");
1712	STAM_REG(pVM, &pPGM->StatR3FlushTLBNewCR3Global, STAMTYPE_COUNTER, "/PGM/R3/FlushTLB/NewCR3Global", STAMUNIT_OCCURENCES, "The number of times PGMFlushTLB was called with a new CR3, global. (switch)");
1713	STAM_REG(pVM, &pPGM->StatR3FlushTLBSameCR3, STAMTYPE_COUNTER, "/PGM/R3/FlushTLB/SameCR3", STAMUNIT_OCCURENCES, "The number of times PGMFlushTLB was called with the same CR3, non-global. (flush)");
1714	STAM_REG(pVM, &pPGM->StatR3FlushTLBSameCR3Global, STAMTYPE_COUNTER, "/PGM/R3/FlushTLB/SameCR3Global", STAMUNIT_OCCURENCES, "The number of times PGMFlushTLB was called with the same CR3, global. (flush)");
1715	STAM_REG(pVM, &pPGM->StatR3GstModifyPage, STAMTYPE_PROFILE, "/PGM/R3/GstModifyPage", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMGstModifyPage() body.");
1716
1717	}
1718	#endif /* VBOX_WITH_STATISTICS */
1719
1720
1721	/**
1722	* Init the PGM bits that rely on VMMR0 and MM to be fully initialized.
1723	*
1724	* The dynamic mapping area will also be allocated and initialized at this
1725	* time. We could allocate it during PGMR3Init of course, but the mapping
1726	* wouldn't be allocated at that time preventing us from setting up the
1727	* page table entries with the dummy page.
1728	*
1729	* @returns VBox status code.
1730	* @param pVM VM handle.
1731	*/
1732	VMMR3DECL(int) PGMR3InitDynMap(PVM pVM)
1733	{
1734	RTGCPTR GCPtr;
1735	/*
1736	* Reserve space for mapping the paging pages into guest context.
1737	*/
1738	int rc = MMR3HyperReserve(pVM, PAGE_SIZE * (2 + RT_ELEMENTS(pVM->pgm.s.apHCPaePDs) + 1 + 2 + 2), "Paging", &GCPtr);
1739	AssertRCReturn(rc, rc);
1740	pVM->pgm.s.pGC32BitPD = GCPtr;
1741	MMR3HyperReserve(pVM, PAGE_SIZE, "fence", NULL);
1742
1743	/*
1744	* Reserve space for the dynamic mappings.
1745	*/
1746	rc = MMR3HyperReserve(pVM, MM_HYPER_DYNAMIC_SIZE, "Dynamic mapping", &GCPtr);
1747	if (VBOX_SUCCESS(rc))
1748	pVM->pgm.s.pbDynPageMapBaseGC = GCPtr;
1749
1750	if ( VBOX_SUCCESS(rc)
1751	&& (pVM->pgm.s.pbDynPageMapBaseGC >> X86_PD_PAE_SHIFT) != ((pVM->pgm.s.pbDynPageMapBaseGC + MM_HYPER_DYNAMIC_SIZE - 1) >> X86_PD_PAE_SHIFT))
1752	{
1753	rc = MMR3HyperReserve(pVM, MM_HYPER_DYNAMIC_SIZE, "Dynamic mapping not crossing", &GCPtr);
1754	if (VBOX_SUCCESS(rc))
1755	pVM->pgm.s.pbDynPageMapBaseGC = GCPtr;
1756	}
1757	if (VBOX_SUCCESS(rc))
1758	{
1759	AssertRelease((pVM->pgm.s.pbDynPageMapBaseGC >> X86_PD_PAE_SHIFT) == ((pVM->pgm.s.pbDynPageMapBaseGC + MM_HYPER_DYNAMIC_SIZE - 1) >> X86_PD_PAE_SHIFT));
1760	MMR3HyperReserve(pVM, PAGE_SIZE, "fence", NULL);
1761	}
1762	return rc;
1763	}
1764
1765
1766	/**
1767	* Ring-3 init finalizing.
1768	*
1769	* @returns VBox status code.
1770	* @param pVM The VM handle.
1771	*/
1772	VMMR3DECL(int) PGMR3InitFinalize(PVM pVM)
1773	{
1774	/*
1775	* Map the paging pages into the guest context.
1776	*/
1777	RTGCPTR GCPtr = pVM->pgm.s.pGC32BitPD;
1778	AssertReleaseReturn(GCPtr, VERR_INTERNAL_ERROR);
1779
1780	int rc = PGMMap(pVM, GCPtr, pVM->pgm.s.HCPhys32BitPD, PAGE_SIZE, 0);
1781	AssertRCReturn(rc, rc);
1782	pVM->pgm.s.pGC32BitPD = GCPtr;
1783	GCPtr += PAGE_SIZE;
1784	GCPtr += PAGE_SIZE; /* reserved page */
1785
1786	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.apHCPaePDs); i++)
1787	{
1788	rc = PGMMap(pVM, GCPtr, pVM->pgm.s.aHCPhysPaePDs[i], PAGE_SIZE, 0);
1789	AssertRCReturn(rc, rc);
1790	pVM->pgm.s.apGCPaePDs[i] = GCPtr;
1791	GCPtr += PAGE_SIZE;
1792	}
1793	/* A bit of paranoia is justified. */
1794	AssertRelease((RTGCUINTPTR)pVM->pgm.s.apGCPaePDs[0] + PAGE_SIZE == (RTGCUINTPTR)pVM->pgm.s.apGCPaePDs[1]);
1795	AssertRelease((RTGCUINTPTR)pVM->pgm.s.apGCPaePDs[1] + PAGE_SIZE == (RTGCUINTPTR)pVM->pgm.s.apGCPaePDs[2]);
1796	AssertRelease((RTGCUINTPTR)pVM->pgm.s.apGCPaePDs[2] + PAGE_SIZE == (RTGCUINTPTR)pVM->pgm.s.apGCPaePDs[3]);
1797	GCPtr += PAGE_SIZE; /* reserved page */
1798
1799	rc = PGMMap(pVM, GCPtr, pVM->pgm.s.HCPhysPaePDPT, PAGE_SIZE, 0);
1800	AssertRCReturn(rc, rc);
1801	pVM->pgm.s.pGCPaePDPT = GCPtr;
1802	GCPtr += PAGE_SIZE;
1803	GCPtr += PAGE_SIZE; /* reserved page */
1804
1805
1806	/*
1807	* Reserve space for the dynamic mappings.
1808	* Initialize the dynamic mapping pages with dummy pages to simply the cache.
1809	*/
1810	/* get the pointer to the page table entries. */
1811	PPGMMAPPING pMapping = pgmGetMapping(pVM, pVM->pgm.s.pbDynPageMapBaseGC);
1812	AssertRelease(pMapping);
1813	const uintptr_t off = pVM->pgm.s.pbDynPageMapBaseGC - pMapping->GCPtr;
1814	const unsigned iPT = off >> X86_PD_SHIFT;
1815	const unsigned iPG = (off >> X86_PT_SHIFT) & X86_PT_MASK;
1816	pVM->pgm.s.paDynPageMap32BitPTEsGC = pMapping->aPTs[iPT].pPTRC + iPG * sizeof(pMapping->aPTs[0].pPTR3->a[0]);
1817	pVM->pgm.s.paDynPageMapPaePTEsGC = pMapping->aPTs[iPT].paPaePTsRC + iPG * sizeof(pMapping->aPTs[0].paPaePTsR3->a[0]);
1818
1819	/* init cache */
1820	RTHCPHYS HCPhysDummy = MMR3PageDummyHCPhys(pVM);
1821	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.aHCPhysDynPageMapCache); i++)
1822	pVM->pgm.s.aHCPhysDynPageMapCache[i] = HCPhysDummy;
1823
1824	for (unsigned i = 0; i < MM_HYPER_DYNAMIC_SIZE; i += PAGE_SIZE)
1825	{
1826	rc = PGMMap(pVM, pVM->pgm.s.pbDynPageMapBaseGC + i, HCPhysDummy, PAGE_SIZE, 0);
1827	AssertRCReturn(rc, rc);
1828	}
1829
1830	/* Note that AMD uses all the 8 reserved bits for the address (so 40 bits in total); Intel only goes up to 36 bits, so
1831	* we stick to 36 as well.
1832	*
1833	* @todo How to test for the 40 bits support? Long mode seems to be the test criterium.
1834	*/
1835	uint32_t u32Dummy, u32Features;
1836	CPUMGetGuestCpuId(pVM, 1, &u32Dummy, &u32Dummy, &u32Dummy, &u32Features);
1837
1838	if (u32Features & X86_CPUID_FEATURE_EDX_PSE36)
1839	pVM->pgm.s.GCPhys4MBPSEMask = RT_BIT_64(36) - 1;
1840	else
1841	pVM->pgm.s.GCPhys4MBPSEMask = RT_BIT_64(32) - 1;
1842
1843	LogRel(("PGMR3InitFinalize: 4 MB PSE mask %VGp\n", pVM->pgm.s.GCPhys4MBPSEMask));
1844
1845	return rc;
1846	}
1847
1848
1849	/**
1850	* Applies relocations to data and code managed by this
1851	* component. This function will be called at init and
1852	* whenever the VMM need to relocate it self inside the GC.
1853	*
1854	* @param pVM The VM.
1855	* @param offDelta Relocation delta relative to old location.
1856	*/
1857	VMMR3DECL(void) PGMR3Relocate(PVM pVM, RTGCINTPTR offDelta)
1858	{
1859	LogFlow(("PGMR3Relocate\n"));
1860
1861	/*
1862	* Paging stuff.
1863	*/
1864	pVM->pgm.s.GCPtrCR3Mapping += offDelta;
1865	/** @todo move this into shadow and guest specific relocation functions. */
1866	AssertMsg(pVM->pgm.s.pGC32BitPD, ("Init order, no relocation before paging is initialized!\n"));
1867	pVM->pgm.s.pGC32BitPD += offDelta;
1868	pVM->pgm.s.pGuestPDGC += offDelta;
1869	AssertCompile(RT_ELEMENTS(pVM->pgm.s.apGCPaePDs) == RT_ELEMENTS(pVM->pgm.s.apGstPaePDsGC));
1870	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.apGCPaePDs); i++)
1871	{
1872	pVM->pgm.s.apGCPaePDs[i] += offDelta;
1873	pVM->pgm.s.apGstPaePDsGC[i] += offDelta;
1874	}
1875	pVM->pgm.s.pGstPaePDPTGC += offDelta;
1876	pVM->pgm.s.pGCPaePDPT += offDelta;
1877
1878	pgmR3ModeDataInit(pVM, true /* resolve GC/R0 symbols */);
1879	pgmR3ModeDataSwitch(pVM, pVM->pgm.s.enmShadowMode, pVM->pgm.s.enmGuestMode);
1880
1881	PGM_SHW_PFN(Relocate, pVM)(pVM, offDelta);
1882	PGM_GST_PFN(Relocate, pVM)(pVM, offDelta);
1883	PGM_BTH_PFN(Relocate, pVM)(pVM, offDelta);
1884
1885	/*
1886	* Trees.
1887	*/
1888	pVM->pgm.s.pTreesRC = MMHyperR3ToRC(pVM, pVM->pgm.s.pTreesR3);
1889
1890	/*
1891	* Ram ranges.
1892	*/
1893	if (pVM->pgm.s.pRamRangesR3)
1894	{
1895	pVM->pgm.s.pRamRangesRC = MMHyperR3ToRC(pVM, pVM->pgm.s.pRamRangesR3);
1896	for (PPGMRAMRANGE pCur = pVM->pgm.s.pRamRangesR3; pCur->pNextR3; pCur = pCur->pNextR3)
1897	pCur->pNextRC = MMHyperR3ToRC(pVM, pCur->pNextR3);
1898	}
1899
1900	/*
1901	* Update the two page directories with all page table mappings.
1902	* (One or more of them have changed, that's why we're here.)
1903	*/
1904	pVM->pgm.s.pMappingsRC = MMHyperR3ToRC(pVM, pVM->pgm.s.pMappingsR3);
1905	for (PPGMMAPPING pCur = pVM->pgm.s.pMappingsR3; pCur->pNextR3; pCur = pCur->pNextR3)
1906	pCur->pNextRC = MMHyperR3ToRC(pVM, pCur->pNextR3);
1907
1908	/* Relocate GC addresses of Page Tables. */
1909	for (PPGMMAPPING pCur = pVM->pgm.s.pMappingsR3; pCur; pCur = pCur->pNextR3)
1910	{
1911	for (RTHCUINT i = 0; i < pCur->cPTs; i++)
1912	{
1913	pCur->aPTs[i].pPTRC = MMHyperR3ToRC(pVM, pCur->aPTs[i].pPTR3);
1914	pCur->aPTs[i].paPaePTsRC = MMHyperR3ToRC(pVM, pCur->aPTs[i].paPaePTsR3);
1915	}
1916	}
1917
1918	/*
1919	* Dynamic page mapping area.
1920	*/
1921	pVM->pgm.s.paDynPageMap32BitPTEsGC += offDelta;
1922	pVM->pgm.s.paDynPageMapPaePTEsGC += offDelta;
1923	pVM->pgm.s.pbDynPageMapBaseGC += offDelta;
1924
1925	/*
1926	* The Zero page.
1927	*/
1928	pVM->pgm.s.pvZeroPgR0 = MMHyperR3ToR0(pVM, pVM->pgm.s.pvZeroPgR3);
1929	AssertRelease(pVM->pgm.s.pvZeroPgR0);
1930
1931	/*
1932	* Physical and virtual handlers.
1933	*/
1934	RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysHandlers, true, pgmR3RelocatePhysHandler, &offDelta);
1935	RTAvlroGCPtrDoWithAll(&pVM->pgm.s.pTreesR3->VirtHandlers, true, pgmR3RelocateVirtHandler, &offDelta);
1936	RTAvlroGCPtrDoWithAll(&pVM->pgm.s.pTreesR3->HyperVirtHandlers, true, pgmR3RelocateHyperVirtHandler, &offDelta);
1937
1938	/*
1939	* The page pool.
1940	*/
1941	pgmR3PoolRelocate(pVM);
1942	}
1943
1944
1945	/**
1946	* Callback function for relocating a physical access handler.
1947	*
1948	* @returns 0 (continue enum)
1949	* @param pNode Pointer to a PGMPHYSHANDLER node.
1950	* @param pvUser Pointer to the offDelta. This is a pointer to the delta since we're
1951	* not certain the delta will fit in a void pointer for all possible configs.
1952	*/
1953	static DECLCALLBACK(int) pgmR3RelocatePhysHandler(PAVLROGCPHYSNODECORE pNode, void *pvUser)
1954	{
1955	PPGMPHYSHANDLER pHandler = (PPGMPHYSHANDLER)pNode;
1956	RTGCINTPTR offDelta = *(PRTGCINTPTR)pvUser;
1957	if (pHandler->pfnHandlerRC)
1958	pHandler->pfnHandlerRC += offDelta;
1959	if (pHandler->pvUserRC >= 0x10000)
1960	pHandler->pvUserRC += offDelta;
1961	return 0;
1962	}
1963
1964
1965	/**
1966	* Callback function for relocating a virtual access handler.
1967	*
1968	* @returns 0 (continue enum)
1969	* @param pNode Pointer to a PGMVIRTHANDLER node.
1970	* @param pvUser Pointer to the offDelta. This is a pointer to the delta since we're
1971	* not certain the delta will fit in a void pointer for all possible configs.
1972	*/
1973	static DECLCALLBACK(int) pgmR3RelocateVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser)
1974	{
1975	PPGMVIRTHANDLER pHandler = (PPGMVIRTHANDLER)pNode;
1976	RTGCINTPTR offDelta = *(PRTGCINTPTR)pvUser;
1977	Assert( pHandler->enmType == PGMVIRTHANDLERTYPE_ALL
1978	\|\| pHandler->enmType == PGMVIRTHANDLERTYPE_WRITE);
1979	Assert(pHandler->pfnHandlerRC);
1980	pHandler->pfnHandlerRC += offDelta;
1981	return 0;
1982	}
1983
1984
1985	/**
1986	* Callback function for relocating a virtual access handler for the hypervisor mapping.
1987	*
1988	* @returns 0 (continue enum)
1989	* @param pNode Pointer to a PGMVIRTHANDLER node.
1990	* @param pvUser Pointer to the offDelta. This is a pointer to the delta since we're
1991	* not certain the delta will fit in a void pointer for all possible configs.
1992	*/
1993	static DECLCALLBACK(int) pgmR3RelocateHyperVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser)
1994	{
1995	PPGMVIRTHANDLER pHandler = (PPGMVIRTHANDLER)pNode;
1996	RTGCINTPTR offDelta = *(PRTGCINTPTR)pvUser;
1997	Assert(pHandler->enmType == PGMVIRTHANDLERTYPE_HYPERVISOR);
1998	Assert(pHandler->pfnHandlerRC);
1999	pHandler->pfnHandlerRC += offDelta;
2000	return 0;
2001	}
2002
2003
2004	/**
2005	* The VM is being reset.
2006	*
2007	* For the PGM component this means that any PD write monitors
2008	* needs to be removed.
2009	*
2010	* @param pVM VM handle.
2011	*/
2012	VMMR3DECL(void) PGMR3Reset(PVM pVM)
2013	{
2014	LogFlow(("PGMR3Reset:\n"));
2015	VM_ASSERT_EMT(pVM);
2016
2017	pgmLock(pVM);
2018
2019	/*
2020	* Unfix any fixed mappings and disable CR3 monitoring.
2021	*/
2022	pVM->pgm.s.fMappingsFixed = false;
2023	pVM->pgm.s.GCPtrMappingFixed = 0;
2024	pVM->pgm.s.cbMappingFixed = 0;
2025
2026	/* Exit the guest paging mode before the pgm pool gets reset.
2027	* Important to clean up the amd64 case.
2028	*/
2029	int rc = PGM_GST_PFN(Exit, pVM)(pVM);
2030	AssertRC(rc);
2031	#ifdef DEBUG
2032	DBGFR3InfoLog(pVM, "mappings", NULL);
2033	DBGFR3InfoLog(pVM, "handlers", "all nostat");
2034	#endif
2035
2036	/*
2037	* Reset the shadow page pool.
2038	*/
2039	pgmR3PoolReset(pVM);
2040
2041	/*
2042	* Re-init other members.
2043	*/
2044	pVM->pgm.s.fA20Enabled = true;
2045
2046	/*
2047	* Clear the FFs PGM owns.
2048	*/
2049	VM_FF_CLEAR(pVM, VM_FF_PGM_SYNC_CR3);
2050	VM_FF_CLEAR(pVM, VM_FF_PGM_SYNC_CR3_NON_GLOBAL);
2051
2052	/*
2053	* Reset (zero) RAM pages.
2054	*/
2055	rc = pgmR3PhysRamReset(pVM);
2056	if (RT_SUCCESS(rc))
2057	{
2058	#ifdef VBOX_WITH_NEW_PHYS_CODE
2059	/*
2060	* Reset (zero) shadow ROM pages.
2061	*/
2062	rc = pgmR3PhysRomReset(pVM);
2063	#endif
2064	if (RT_SUCCESS(rc))
2065	{
2066	/*
2067	* Switch mode back to real mode.
2068	*/
2069	rc = PGMR3ChangeMode(pVM, PGMMODE_REAL);
2070	STAM_REL_COUNTER_RESET(&pVM->pgm.s.cGuestModeChanges);
2071	}
2072	}
2073
2074	pgmUnlock(pVM);
2075	//return rc;
2076	AssertReleaseRC(rc);
2077	}
2078
2079
2080	#ifdef VBOX_STRICT
2081	/**
2082	* VM state change callback for clearing fNoMorePhysWrites after
2083	* a snapshot has been created.
2084	*/
2085	static DECLCALLBACK(void) pgmR3ResetNoMorePhysWritesFlag(PVM pVM, VMSTATE enmState, VMSTATE enmOldState, void *pvUser)
2086	{
2087	if (enmState == VMSTATE_RUNNING)
2088	pVM->pgm.s.fNoMorePhysWrites = false;
2089	}
2090	#endif
2091
2092
2093	/**
2094	* Terminates the PGM.
2095	*
2096	* @returns VBox status code.
2097	* @param pVM Pointer to VM structure.
2098	*/
2099	VMMR3DECL(int) PGMR3Term(PVM pVM)
2100	{
2101	return PDMR3CritSectDelete(&pVM->pgm.s.CritSect);
2102	}
2103
2104
2105	/**
2106	* Execute state save operation.
2107	*
2108	* @returns VBox status code.
2109	* @param pVM VM Handle.
2110	* @param pSSM SSM operation handle.
2111	*/
2112	static DECLCALLBACK(int) pgmR3Save(PVM pVM, PSSMHANDLE pSSM)
2113	{
2114	PPGM pPGM = &pVM->pgm.s;
2115
2116	/* No more writes to physical memory after this point! */
2117	pVM->pgm.s.fNoMorePhysWrites = true;
2118
2119	/*
2120	* Save basic data (required / unaffected by relocation).
2121	*/
2122	#if 1
2123	SSMR3PutBool(pSSM, pPGM->fMappingsFixed);
2124	#else
2125	SSMR3PutUInt(pSSM, pPGM->fMappingsFixed);
2126	#endif
2127	SSMR3PutGCPtr(pSSM, pPGM->GCPtrMappingFixed);
2128	SSMR3PutU32(pSSM, pPGM->cbMappingFixed);
2129	SSMR3PutUInt(pSSM, pPGM->cbRamSize);
2130	SSMR3PutGCPhys(pSSM, pPGM->GCPhysA20Mask);
2131	SSMR3PutUInt(pSSM, pPGM->fA20Enabled);
2132	SSMR3PutUInt(pSSM, pPGM->fSyncFlags);
2133	SSMR3PutUInt(pSSM, pPGM->enmGuestMode);
2134	SSMR3PutU32(pSSM, ~0); /* Separator. */
2135
2136	/*
2137	* The guest mappings.
2138	*/
2139	uint32_t i = 0;
2140	for (PPGMMAPPING pMapping = pPGM->pMappingsR3; pMapping; pMapping = pMapping->pNextR3, i++)
2141	{
2142	SSMR3PutU32(pSSM, i);
2143	SSMR3PutStrZ(pSSM, pMapping->pszDesc); /* This is the best unique id we have... */
2144	SSMR3PutGCPtr(pSSM, pMapping->GCPtr);
2145	SSMR3PutGCUIntPtr(pSSM, pMapping->cPTs);
2146	/* flags are done by the mapping owners! */
2147	}
2148	SSMR3PutU32(pSSM, ~0); /* terminator. */
2149
2150	/*
2151	* Ram range flags and bits.
2152	*/
2153	i = 0;
2154	for (PPGMRAMRANGE pRam = pPGM->pRamRangesR3; pRam; pRam = pRam->pNextR3, i++)
2155	{
2156	/** @todo MMIO ranges may move (PCI reconfig), we currently assume they don't. */
2157
2158	SSMR3PutU32(pSSM, i);
2159	SSMR3PutGCPhys(pSSM, pRam->GCPhys);
2160	SSMR3PutGCPhys(pSSM, pRam->GCPhysLast);
2161	SSMR3PutGCPhys(pSSM, pRam->cb);
2162	SSMR3PutU8(pSSM, !!pRam->pvR3); /* boolean indicating memory or not. */
2163
2164	/* Flags. */
2165	const unsigned cPages = pRam->cb >> PAGE_SHIFT;
2166	for (unsigned iPage = 0; iPage < cPages; iPage++)
2167	SSMR3PutU16(pSSM, (uint16_t)(pRam->aPages[iPage].HCPhys & ~X86_PTE_PAE_PG_MASK)); /** @todo PAGE FLAGS */
2168
2169	/* any memory associated with the range. */
2170	if (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)
2171	{
2172	for (unsigned iChunk = 0; iChunk < (pRam->cb >> PGM_DYNAMIC_CHUNK_SHIFT); iChunk++)
2173	{
2174	if (pRam->paChunkR3Ptrs[iChunk])
2175	{
2176	SSMR3PutU8(pSSM, 1); /* chunk present */
2177	SSMR3PutMem(pSSM, (void *)pRam->paChunkR3Ptrs[iChunk], PGM_DYNAMIC_CHUNK_SIZE);
2178	}
2179	else
2180	SSMR3PutU8(pSSM, 0); /* no chunk present */
2181	}
2182	}
2183	else if (pRam->pvR3)
2184	{
2185	int rc = SSMR3PutMem(pSSM, pRam->pvR3, pRam->cb);
2186	if (VBOX_FAILURE(rc))
2187	{
2188	Log(("pgmR3Save: SSMR3PutMem(, %p, %#x) -> %Vrc\n", pRam->pvR3, pRam->cb, rc));
2189	return rc;
2190	}
2191	}
2192	}
2193	return SSMR3PutU32(pSSM, ~0); /* terminator. */
2194	}
2195
2196
2197	/**
2198	* Execute state load operation.
2199	*
2200	* @returns VBox status code.
2201	* @param pVM VM Handle.
2202	* @param pSSM SSM operation handle.
2203	* @param u32Version Data layout version.
2204	*/
2205	static DECLCALLBACK(int) pgmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version)
2206	{
2207	/*
2208	* Validate version.
2209	*/
2210	if (u32Version != PGM_SAVED_STATE_VERSION)
2211	{
2212	AssertMsgFailed(("pgmR3Load: Invalid version u32Version=%d (current %d)!\n", u32Version, PGM_SAVED_STATE_VERSION));
2213	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
2214	}
2215
2216	/*
2217	* Call the reset function to make sure all the memory is cleared.
2218	*/
2219	PGMR3Reset(pVM);
2220
2221	/*
2222	* Load basic data (required / unaffected by relocation).
2223	*/
2224	PPGM pPGM = &pVM->pgm.s;
2225	#if 1
2226	SSMR3GetBool(pSSM, &pPGM->fMappingsFixed);
2227	#else
2228	uint32_t u;
2229	SSMR3GetU32(pSSM, &u);
2230	pPGM->fMappingsFixed = u;
2231	#endif
2232	SSMR3GetGCPtr(pSSM, &pPGM->GCPtrMappingFixed);
2233	SSMR3GetU32(pSSM, &pPGM->cbMappingFixed);
2234
2235	RTUINT cbRamSize;
2236	int rc = SSMR3GetU32(pSSM, &cbRamSize);
2237	if (VBOX_FAILURE(rc))
2238	return rc;
2239	if (cbRamSize != pPGM->cbRamSize)
2240	return VERR_SSM_LOAD_MEMORY_SIZE_MISMATCH;
2241	SSMR3GetGCPhys(pSSM, &pPGM->GCPhysA20Mask);
2242	SSMR3GetUInt(pSSM, &pPGM->fA20Enabled);
2243	SSMR3GetUInt(pSSM, &pPGM->fSyncFlags);
2244	RTUINT uGuestMode;
2245	SSMR3GetUInt(pSSM, &uGuestMode);
2246	pPGM->enmGuestMode = (PGMMODE)uGuestMode;
2247
2248	/* check separator. */
2249	uint32_t u32Sep;
2250	SSMR3GetU32(pSSM, &u32Sep);
2251	if (VBOX_FAILURE(rc))
2252	return rc;
2253	if (u32Sep != (uint32_t)~0)
2254	{
2255	AssertMsgFailed(("u32Sep=%#x (first)\n", u32Sep));
2256	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2257	}
2258
2259	/*
2260	* The guest mappings.
2261	*/
2262	uint32_t i = 0;
2263	for (;; i++)
2264	{
2265	/* Check the seqence number / separator. */
2266	rc = SSMR3GetU32(pSSM, &u32Sep);
2267	if (VBOX_FAILURE(rc))
2268	return rc;
2269	if (u32Sep == ~0U)
2270	break;
2271	if (u32Sep != i)
2272	{
2273	AssertMsgFailed(("u32Sep=%#x (last)\n", u32Sep));
2274	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2275	}
2276
2277	/* get the mapping details. */
2278	char szDesc[256];
2279	szDesc[0] = '\0';
2280	rc = SSMR3GetStrZ(pSSM, szDesc, sizeof(szDesc));
2281	if (VBOX_FAILURE(rc))
2282	return rc;
2283	RTGCPTR GCPtr;
2284	SSMR3GetGCPtr(pSSM, &GCPtr);
2285	RTGCUINTPTR cPTs;
2286	rc = SSMR3GetGCUIntPtr(pSSM, &cPTs);
2287	if (VBOX_FAILURE(rc))
2288	return rc;
2289
2290	/* find matching range. */
2291	PPGMMAPPING pMapping;
2292	for (pMapping = pPGM->pMappingsR3; pMapping; pMapping = pMapping->pNextR3)
2293	if ( pMapping->cPTs == cPTs
2294	&& !strcmp(pMapping->pszDesc, szDesc))
2295	break;
2296	if (!pMapping)
2297	{
2298	LogRel(("Couldn't find mapping: cPTs=%#x szDesc=%s (GCPtr=%VGv)\n",
2299	cPTs, szDesc, GCPtr));
2300	AssertFailed();
2301	return VERR_SSM_LOAD_CONFIG_MISMATCH;
2302	}
2303
2304	/* relocate it. */
2305	if (pMapping->GCPtr != GCPtr)
2306	{
2307	AssertMsg((GCPtr >> X86_PD_SHIFT << X86_PD_SHIFT) == GCPtr, ("GCPtr=%VGv\n", GCPtr));
2308	#if HC_ARCH_BITS == 64
2309	LogRel(("Mapping: %VGv -> %VGv %s\n", pMapping->GCPtr, GCPtr, pMapping->pszDesc));
2310	#endif
2311	pgmR3MapRelocate(pVM, pMapping, pMapping->GCPtr, GCPtr);
2312	}
2313	else
2314	Log(("pgmR3Load: '%s' needed no relocation (%VGv)\n", szDesc, GCPtr));
2315	}
2316
2317	/*
2318	* Ram range flags and bits.
2319	*/
2320	i = 0;
2321	for (PPGMRAMRANGE pRam = pPGM->pRamRangesR3; pRam; pRam = pRam->pNextR3, i++)
2322	{
2323	/** @todo MMIO ranges may move (PCI reconfig), we currently assume they don't. */
2324	/* Check the seqence number / separator. */
2325	rc = SSMR3GetU32(pSSM, &u32Sep);
2326	if (VBOX_FAILURE(rc))
2327	return rc;
2328	if (u32Sep == ~0U)
2329	break;
2330	if (u32Sep != i)
2331	{
2332	AssertMsgFailed(("u32Sep=%#x (last)\n", u32Sep));
2333	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2334	}
2335
2336	/* Get the range details. */
2337	RTGCPHYS GCPhys;
2338	SSMR3GetGCPhys(pSSM, &GCPhys);
2339	RTGCPHYS GCPhysLast;
2340	SSMR3GetGCPhys(pSSM, &GCPhysLast);
2341	RTGCPHYS cb;
2342	SSMR3GetGCPhys(pSSM, &cb);
2343	uint8_t fHaveBits;
2344	rc = SSMR3GetU8(pSSM, &fHaveBits);
2345	if (VBOX_FAILURE(rc))
2346	return rc;
2347	if (fHaveBits & ~1)
2348	{
2349	AssertMsgFailed(("u32Sep=%#x (last)\n", u32Sep));
2350	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2351	}
2352
2353	/* Match it up with the current range. */
2354	if ( GCPhys != pRam->GCPhys
2355	\|\| GCPhysLast != pRam->GCPhysLast
2356	\|\| cb != pRam->cb
2357	\|\| fHaveBits != !!pRam->pvR3)
2358	{
2359	LogRel(("Ram range: %RGp-%RGp %RGp bytes %s\n"
2360	"State : %RGp-%RGp %RGp bytes %s\n",
2361	pRam->GCPhys, pRam->GCPhysLast, pRam->cb, pRam->pvR3 ? "bits" : "nobits",
2362	GCPhys, GCPhysLast, cb, fHaveBits ? "bits" : "nobits"));
2363	/*
2364	* If we're loading a state for debugging purpose, don't make a fuss if
2365	* the MMIO[2] and ROM stuff isn't 100% right, just skip the mismatches.
2366	*/
2367	if ( SSMR3HandleGetAfter(pSSM) != SSMAFTER_DEBUG_IT
2368	\|\| GCPhys < 8 * _1M)
2369	AssertFailedReturn(VERR_SSM_LOAD_CONFIG_MISMATCH);
2370
2371	RTGCPHYS cPages = ((GCPhysLast - GCPhys) + 1) >> PAGE_SHIFT;
2372	while (cPages-- > 0)
2373	{
2374	uint16_t u16Ignore;
2375	SSMR3GetU16(pSSM, &u16Ignore);
2376	}
2377	continue;
2378	}
2379
2380	/* Flags. */
2381	const unsigned cPages = pRam->cb >> PAGE_SHIFT;
2382	for (unsigned iPage = 0; iPage < cPages; iPage++)
2383	{
2384	uint16_t u16 = 0;
2385	SSMR3GetU16(pSSM, &u16);
2386	u16 &= PAGE_OFFSET_MASK & ~( RT_BIT(4) \| RT_BIT(5) \| RT_BIT(6)
2387	\| RT_BIT(7) \| RT_BIT(8) \| RT_BIT(9) \| RT_BIT(10) );
2388	// &= MM_RAM_FLAGS_DYNAMIC_ALLOC \| MM_RAM_FLAGS_RESERVED \| MM_RAM_FLAGS_ROM \| MM_RAM_FLAGS_MMIO \| MM_RAM_FLAGS_MMIO2
2389	pRam->aPages[iPage].HCPhys = PGM_PAGE_GET_HCPHYS(&pRam->aPages[iPage]) \| (RTHCPHYS)u16; /** @todo PAGE FLAGS */
2390	}
2391
2392	/* any memory associated with the range. */
2393	if (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)
2394	{
2395	for (unsigned iChunk = 0; iChunk < (pRam->cb >> PGM_DYNAMIC_CHUNK_SHIFT); iChunk++)
2396	{
2397	uint8_t fValidChunk;
2398
2399	rc = SSMR3GetU8(pSSM, &fValidChunk);
2400	if (VBOX_FAILURE(rc))
2401	return rc;
2402	if (fValidChunk > 1)
2403	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2404
2405	if (fValidChunk)
2406	{
2407	if (!pRam->paChunkR3Ptrs[iChunk])
2408	{
2409	rc = pgmr3PhysGrowRange(pVM, pRam->GCPhys + iChunk * PGM_DYNAMIC_CHUNK_SIZE);
2410	if (VBOX_FAILURE(rc))
2411	return rc;
2412	}
2413	Assert(pRam->paChunkR3Ptrs[iChunk]);
2414
2415	SSMR3GetMem(pSSM, (void *)pRam->paChunkR3Ptrs[iChunk], PGM_DYNAMIC_CHUNK_SIZE);
2416	}
2417	/* else nothing to do */
2418	}
2419	}
2420	else if (pRam->pvR3)
2421	{
2422	int rc = SSMR3GetMem(pSSM, pRam->pvR3, pRam->cb);
2423	if (VBOX_FAILURE(rc))
2424	{
2425	Log(("pgmR3Save: SSMR3GetMem(, %p, %#x) -> %Vrc\n", pRam->pvR3, pRam->cb, rc));
2426	return rc;
2427	}
2428	}
2429	}
2430
2431	/*
2432	* We require a full resync now.
2433	*/
2434	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3_NON_GLOBAL);
2435	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
2436	pPGM->fSyncFlags \|= PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL;
2437	pPGM->fPhysCacheFlushPending = true;
2438	pgmR3HandlerPhysicalUpdateAll(pVM);
2439
2440	/*
2441	* Change the paging mode.
2442	*/
2443	rc = PGMR3ChangeMode(pVM, pPGM->enmGuestMode);
2444
2445	/* Restore pVM->pgm.s.GCPhysCR3. */
2446	Assert(pVM->pgm.s.GCPhysCR3 == NIL_RTGCPHYS);
2447	RTGCPHYS GCPhysCR3 = CPUMGetGuestCR3(pVM);
2448	if ( pVM->pgm.s.enmGuestMode == PGMMODE_PAE
2449	\|\| pVM->pgm.s.enmGuestMode == PGMMODE_PAE_NX
2450	\|\| pVM->pgm.s.enmGuestMode == PGMMODE_AMD64
2451	\|\| pVM->pgm.s.enmGuestMode == PGMMODE_AMD64_NX)
2452	GCPhysCR3 = (GCPhysCR3 & X86_CR3_PAE_PAGE_MASK);
2453	else
2454	GCPhysCR3 = (GCPhysCR3 & X86_CR3_PAGE_MASK);
2455	pVM->pgm.s.GCPhysCR3 = GCPhysCR3;
2456
2457	return rc;
2458	}
2459
2460
2461	/**
2462	* Show paging mode.
2463	*
2464	* @param pVM VM Handle.
2465	* @param pHlp The info helpers.
2466	* @param pszArgs "all" (default), "guest", "shadow" or "host".
2467	*/
2468	static DECLCALLBACK(void) pgmR3InfoMode(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2469	{
2470	/* digest argument. */
2471	bool fGuest, fShadow, fHost;
2472	if (pszArgs)
2473	pszArgs = RTStrStripL(pszArgs);
2474	if (!pszArgs \|\| !*pszArgs \|\| strstr(pszArgs, "all"))
2475	fShadow = fHost = fGuest = true;
2476	else
2477	{
2478	fShadow = fHost = fGuest = false;
2479	if (strstr(pszArgs, "guest"))
2480	fGuest = true;
2481	if (strstr(pszArgs, "shadow"))
2482	fShadow = true;
2483	if (strstr(pszArgs, "host"))
2484	fHost = true;
2485	}
2486
2487	/* print info. */
2488	if (fGuest)
2489	pHlp->pfnPrintf(pHlp, "Guest paging mode: %s, changed %RU64 times, A20 %s\n",
2490	PGMGetModeName(pVM->pgm.s.enmGuestMode), pVM->pgm.s.cGuestModeChanges.c,
2491	pVM->pgm.s.fA20Enabled ? "enabled" : "disabled");
2492	if (fShadow)
2493	pHlp->pfnPrintf(pHlp, "Shadow paging mode: %s\n", PGMGetModeName(pVM->pgm.s.enmShadowMode));
2494	if (fHost)
2495	{
2496	const char *psz;
2497	switch (pVM->pgm.s.enmHostMode)
2498	{
2499	case SUPPAGINGMODE_INVALID: psz = "invalid"; break;
2500	case SUPPAGINGMODE_32_BIT: psz = "32-bit"; break;
2501	case SUPPAGINGMODE_32_BIT_GLOBAL: psz = "32-bit+G"; break;
2502	case SUPPAGINGMODE_PAE: psz = "PAE"; break;
2503	case SUPPAGINGMODE_PAE_GLOBAL: psz = "PAE+G"; break;
2504	case SUPPAGINGMODE_PAE_NX: psz = "PAE+NX"; break;
2505	case SUPPAGINGMODE_PAE_GLOBAL_NX: psz = "PAE+G+NX"; break;
2506	case SUPPAGINGMODE_AMD64: psz = "AMD64"; break;
2507	case SUPPAGINGMODE_AMD64_GLOBAL: psz = "AMD64+G"; break;
2508	case SUPPAGINGMODE_AMD64_NX: psz = "AMD64+NX"; break;
2509	case SUPPAGINGMODE_AMD64_GLOBAL_NX: psz = "AMD64+G+NX"; break;
2510	default: psz = "unknown"; break;
2511	}
2512	pHlp->pfnPrintf(pHlp, "Host paging mode: %s\n", psz);
2513	}
2514	}
2515
2516
2517	/**
2518	* Dump registered MMIO ranges to the log.
2519	*
2520	* @param pVM VM Handle.
2521	* @param pHlp The info helpers.
2522	* @param pszArgs Arguments, ignored.
2523	*/
2524	static DECLCALLBACK(void) pgmR3PhysInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2525	{
2526	NOREF(pszArgs);
2527	pHlp->pfnPrintf(pHlp,
2528	"RAM ranges (pVM=%p)\n"
2529	"%.s %.s\n",
2530	pVM,
2531	sizeof(RTGCPHYS) * 4 + 1, "GC Phys Range ",
2532	sizeof(RTHCPTR) * 2, "pvHC ");
2533
2534	for (PPGMRAMRANGE pCur = pVM->pgm.s.pRamRangesR3; pCur; pCur = pCur->pNextR3)
2535	pHlp->pfnPrintf(pHlp,
2536	"%RGp-%RGp %RHv %s\n",
2537	pCur->GCPhys,
2538	pCur->GCPhysLast,
2539	pCur->pvR3,
2540	pCur->pszDesc);
2541	}
2542
2543	/**
2544	* Dump the page directory to the log.
2545	*
2546	* @param pVM VM Handle.
2547	* @param pHlp The info helpers.
2548	* @param pszArgs Arguments, ignored.
2549	*/
2550	static DECLCALLBACK(void) pgmR3InfoCr3(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2551	{
2552	/** @todo fix this! Convert the PGMR3DumpHierarchyHC functions to do guest stuff. */
2553	/* Big pages supported? */
2554	const bool fPSE = !!(CPUMGetGuestCR4(pVM) & X86_CR4_PSE);
2555
2556	/* Global pages supported? */
2557	const bool fPGE = !!(CPUMGetGuestCR4(pVM) & X86_CR4_PGE);
2558
2559	NOREF(pszArgs);
2560
2561	/*
2562	* Get page directory addresses.
2563	*/
2564	PX86PD pPDSrc = pVM->pgm.s.pGuestPDHC;
2565	Assert(pPDSrc);
2566	Assert(PGMPhysGCPhys2HCPtrAssert(pVM, (RTGCPHYS)(CPUMGetGuestCR3(pVM) & X86_CR3_PAGE_MASK), sizeof(*pPDSrc)) == pPDSrc);
2567
2568	/*
2569	* Iterate the page directory.
2570	*/
2571	for (unsigned iPD = 0; iPD < RT_ELEMENTS(pPDSrc->a); iPD++)
2572	{
2573	X86PDE PdeSrc = pPDSrc->a[iPD];
2574	if (PdeSrc.n.u1Present)
2575	{
2576	if (PdeSrc.b.u1Size && fPSE)
2577	{
2578	pHlp->pfnPrintf(pHlp,
2579	"%04X - %VGp P=%d U=%d RW=%d G=%d - BIG\n",
2580	iPD,
2581	pgmGstGet4MBPhysPage(&pVM->pgm.s, PdeSrc),
2582	PdeSrc.b.u1Present, PdeSrc.b.u1User, PdeSrc.b.u1Write, PdeSrc.b.u1Global && fPGE);
2583	}
2584	else
2585	{
2586	pHlp->pfnPrintf(pHlp,
2587	"%04X - %VGp P=%d U=%d RW=%d [G=%d]\n",
2588	iPD,
2589	PdeSrc.u & X86_PDE_PG_MASK,
2590	PdeSrc.n.u1Present, PdeSrc.n.u1User, PdeSrc.n.u1Write, PdeSrc.b.u1Global && fPGE);
2591	}
2592	}
2593	}
2594	}
2595
2596
2597	/**
2598	* Serivce a VMMCALLHOST_PGM_LOCK call.
2599	*
2600	* @returns VBox status code.
2601	* @param pVM The VM handle.
2602	*/
2603	VMMR3DECL(int) PGMR3LockCall(PVM pVM)
2604	{
2605	int rc = PDMR3CritSectEnterEx(&pVM->pgm.s.CritSect, true /* fHostCall */);
2606	AssertRC(rc);
2607	return rc;
2608	}
2609
2610
2611	/**
2612	* Converts a PGMMODE value to a PGM_TYPE_* \#define.
2613	*
2614	* @returns PGM_TYPE_*.
2615	* @param pgmMode The mode value to convert.
2616	*/
2617	DECLINLINE(unsigned) pgmModeToType(PGMMODE pgmMode)
2618	{
2619	switch (pgmMode)
2620	{
2621	case PGMMODE_REAL: return PGM_TYPE_REAL;
2622	case PGMMODE_PROTECTED: return PGM_TYPE_PROT;
2623	case PGMMODE_32_BIT: return PGM_TYPE_32BIT;
2624	case PGMMODE_PAE:
2625	case PGMMODE_PAE_NX: return PGM_TYPE_PAE;
2626	case PGMMODE_AMD64:
2627	case PGMMODE_AMD64_NX: return PGM_TYPE_AMD64;
2628	case PGMMODE_NESTED: return PGM_TYPE_NESTED;
2629	case PGMMODE_EPT: return PGM_TYPE_EPT;
2630	default:
2631	AssertFatalMsgFailed(("pgmMode=%d\n", pgmMode));
2632	}
2633	}
2634
2635
2636	/**
2637	* Gets the index into the paging mode data array of a SHW+GST mode.
2638	*
2639	* @returns PGM::paPagingData index.
2640	* @param uShwType The shadow paging mode type.
2641	* @param uGstType The guest paging mode type.
2642	*/
2643	DECLINLINE(unsigned) pgmModeDataIndex(unsigned uShwType, unsigned uGstType)
2644	{
2645	Assert(uShwType >= PGM_TYPE_32BIT && uShwType <= PGM_TYPE_MAX);
2646	Assert(uGstType >= PGM_TYPE_REAL && uGstType <= PGM_TYPE_AMD64);
2647	return (uShwType - PGM_TYPE_32BIT) * (PGM_TYPE_AMD64 - PGM_TYPE_REAL + 1)
2648	+ (uGstType - PGM_TYPE_REAL);
2649	}
2650
2651
2652	/**
2653	* Gets the index into the paging mode data array of a SHW+GST mode.
2654	*
2655	* @returns PGM::paPagingData index.
2656	* @param enmShw The shadow paging mode.
2657	* @param enmGst The guest paging mode.
2658	*/
2659	DECLINLINE(unsigned) pgmModeDataIndexByMode(PGMMODE enmShw, PGMMODE enmGst)
2660	{
2661	Assert(enmShw >= PGMMODE_32_BIT && enmShw <= PGMMODE_MAX);
2662	Assert(enmGst > PGMMODE_INVALID && enmGst < PGMMODE_MAX);
2663	return pgmModeDataIndex(pgmModeToType(enmShw), pgmModeToType(enmGst));
2664	}
2665
2666
2667	/**
2668	* Calculates the max data index.
2669	* @returns The number of entries in the paging data array.
2670	*/
2671	DECLINLINE(unsigned) pgmModeDataMaxIndex(void)
2672	{
2673	return pgmModeDataIndex(PGM_TYPE_MAX, PGM_TYPE_AMD64) + 1;
2674	}
2675
2676
2677	/**
2678	* Initializes the paging mode data kept in PGM::paModeData.
2679	*
2680	* @param pVM The VM handle.
2681	* @param fResolveGCAndR0 Indicate whether or not GC and Ring-0 symbols can be resolved now.
2682	* This is used early in the init process to avoid trouble with PDM
2683	* not being initialized yet.
2684	*/
2685	static int pgmR3ModeDataInit(PVM pVM, bool fResolveGCAndR0)
2686	{
2687	PPGMMODEDATA pModeData;
2688	int rc;
2689
2690	/*
2691	* Allocate the array on the first call.
2692	*/
2693	if (!pVM->pgm.s.paModeData)
2694	{
2695	pVM->pgm.s.paModeData = (PPGMMODEDATA)MMR3HeapAllocZ(pVM, MM_TAG_PGM, sizeof(PGMMODEDATA) * pgmModeDataMaxIndex());
2696	AssertReturn(pVM->pgm.s.paModeData, VERR_NO_MEMORY);
2697	}
2698
2699	/*
2700	* Initialize the array entries.
2701	*/
2702	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_32BIT, PGM_TYPE_REAL)];
2703	pModeData->uShwType = PGM_TYPE_32BIT;
2704	pModeData->uGstType = PGM_TYPE_REAL;
2705	rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2706	rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2707	rc = PGM_BTH_NAME_32BIT_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2708
2709	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_32BIT, PGMMODE_PROTECTED)];
2710	pModeData->uShwType = PGM_TYPE_32BIT;
2711	pModeData->uGstType = PGM_TYPE_PROT;
2712	rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2713	rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2714	rc = PGM_BTH_NAME_32BIT_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2715
2716	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_32BIT, PGM_TYPE_32BIT)];
2717	pModeData->uShwType = PGM_TYPE_32BIT;
2718	pModeData->uGstType = PGM_TYPE_32BIT;
2719	rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2720	rc = PGM_GST_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2721	rc = PGM_BTH_NAME_32BIT_32BIT(InitData)(pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2722
2723	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_REAL)];
2724	pModeData->uShwType = PGM_TYPE_PAE;
2725	pModeData->uGstType = PGM_TYPE_REAL;
2726	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2727	rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2728	rc = PGM_BTH_NAME_PAE_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2729
2730	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_PROT)];
2731	pModeData->uShwType = PGM_TYPE_PAE;
2732	pModeData->uGstType = PGM_TYPE_PROT;
2733	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2734	rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2735	rc = PGM_BTH_NAME_PAE_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2736
2737	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_32BIT)];
2738	pModeData->uShwType = PGM_TYPE_PAE;
2739	pModeData->uGstType = PGM_TYPE_32BIT;
2740	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2741	rc = PGM_GST_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2742	rc = PGM_BTH_NAME_PAE_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2743
2744	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_PAE)];
2745	pModeData->uShwType = PGM_TYPE_PAE;
2746	pModeData->uGstType = PGM_TYPE_PAE;
2747	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2748	rc = PGM_GST_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2749	rc = PGM_BTH_NAME_PAE_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2750
2751	#ifdef VBOX_WITH_64_BITS_GUESTS
2752	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_AMD64, PGM_TYPE_AMD64)];
2753	pModeData->uShwType = PGM_TYPE_AMD64;
2754	pModeData->uGstType = PGM_TYPE_AMD64;
2755	rc = PGM_SHW_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2756	rc = PGM_GST_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2757	rc = PGM_BTH_NAME_AMD64_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2758	#endif
2759
2760	/* The nested paging mode. */
2761	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_REAL)];
2762	pModeData->uShwType = PGM_TYPE_NESTED;
2763	pModeData->uGstType = PGM_TYPE_REAL;
2764	rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2765	rc = PGM_BTH_NAME_NESTED_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2766
2767	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGMMODE_PROTECTED)];
2768	pModeData->uShwType = PGM_TYPE_NESTED;
2769	pModeData->uGstType = PGM_TYPE_PROT;
2770	rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2771	rc = PGM_BTH_NAME_NESTED_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2772
2773	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_32BIT)];
2774	pModeData->uShwType = PGM_TYPE_NESTED;
2775	pModeData->uGstType = PGM_TYPE_32BIT;
2776	rc = PGM_GST_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2777	rc = PGM_BTH_NAME_NESTED_32BIT(InitData)(pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2778
2779	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_PAE)];
2780	pModeData->uShwType = PGM_TYPE_NESTED;
2781	pModeData->uGstType = PGM_TYPE_PAE;
2782	rc = PGM_GST_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2783	rc = PGM_BTH_NAME_NESTED_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2784
2785	#ifdef VBOX_WITH_64_BITS_GUESTS
2786	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_AMD64)];
2787	pModeData->uShwType = PGM_TYPE_NESTED;
2788	pModeData->uGstType = PGM_TYPE_AMD64;
2789	rc = PGM_GST_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2790	rc = PGM_BTH_NAME_NESTED_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2791	#endif
2792
2793	/* The shadow part of the nested callback mode depends on the host paging mode (AMD-V only). */
2794	switch(pVM->pgm.s.enmHostMode)
2795	{
2796	case SUPPAGINGMODE_32_BIT:
2797	case SUPPAGINGMODE_32_BIT_GLOBAL:
2798	#ifdef VBOX_WITH_64_BITS_GUESTS
2799	for (unsigned i=PGM_TYPE_REAL;i<=PGM_TYPE_AMD64;i++)
2800	#else
2801	for (unsigned i=PGM_TYPE_REAL;i<=PGM_TYPE_PAE;i++)
2802	#endif
2803	{
2804	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, i)];
2805	rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2806	}
2807	break;
2808
2809	case SUPPAGINGMODE_PAE:
2810	case SUPPAGINGMODE_PAE_NX:
2811	case SUPPAGINGMODE_PAE_GLOBAL:
2812	case SUPPAGINGMODE_PAE_GLOBAL_NX:
2813	#ifdef VBOX_WITH_64_BITS_GUESTS
2814	for (unsigned i=PGM_TYPE_REAL;i<=PGM_TYPE_AMD64;i++)
2815	#else
2816	for (unsigned i=PGM_TYPE_REAL;i<=PGM_TYPE_PAE;i++)
2817	#endif
2818	{
2819	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, i)];
2820	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2821	}
2822	break;
2823
2824	case SUPPAGINGMODE_AMD64:
2825	case SUPPAGINGMODE_AMD64_GLOBAL:
2826	case SUPPAGINGMODE_AMD64_NX:
2827	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
2828	#ifdef VBOX_WITH_64_BITS_GUESTS
2829	for (unsigned i=PGM_TYPE_REAL;i<=PGM_TYPE_AMD64;i++)
2830	#else
2831	for (unsigned i=PGM_TYPE_REAL;i<=PGM_TYPE_PAE;i++)
2832	#endif
2833	{
2834	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, i)];
2835	rc = PGM_SHW_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2836	}
2837	break;
2838	default:
2839	AssertFailed();
2840	break;
2841	}
2842
2843	/* Extended paging (EPT) / Intel VT-x */
2844	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_REAL)];
2845	pModeData->uShwType = PGM_TYPE_EPT;
2846	pModeData->uGstType = PGM_TYPE_REAL;
2847	rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2848	rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2849	rc = PGM_BTH_NAME_EPT_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2850
2851	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_PROT)];
2852	pModeData->uShwType = PGM_TYPE_EPT;
2853	pModeData->uGstType = PGM_TYPE_PROT;
2854	rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2855	rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2856	rc = PGM_BTH_NAME_EPT_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2857
2858	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_32BIT)];
2859	pModeData->uShwType = PGM_TYPE_EPT;
2860	pModeData->uGstType = PGM_TYPE_32BIT;
2861	rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2862	rc = PGM_GST_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2863	rc = PGM_BTH_NAME_EPT_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2864
2865	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_PAE)];
2866	pModeData->uShwType = PGM_TYPE_EPT;
2867	pModeData->uGstType = PGM_TYPE_PAE;
2868	rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2869	rc = PGM_GST_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2870	rc = PGM_BTH_NAME_EPT_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2871
2872	#ifdef VBOX_WITH_64_BITS_GUESTS
2873	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_AMD64)];
2874	pModeData->uShwType = PGM_TYPE_EPT;
2875	pModeData->uGstType = PGM_TYPE_AMD64;
2876	rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2877	rc = PGM_GST_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2878	rc = PGM_BTH_NAME_EPT_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2879	#endif
2880	return VINF_SUCCESS;
2881	}
2882
2883
2884	/**
2885	* Switch to different (or relocated in the relocate case) mode data.
2886	*
2887	* @param pVM The VM handle.
2888	* @param enmShw The the shadow paging mode.
2889	* @param enmGst The the guest paging mode.
2890	*/
2891	static void pgmR3ModeDataSwitch(PVM pVM, PGMMODE enmShw, PGMMODE enmGst)
2892	{
2893	PPGMMODEDATA pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndexByMode(enmShw, enmGst)];
2894
2895	Assert(pModeData->uGstType == pgmModeToType(enmGst));
2896	Assert(pModeData->uShwType == pgmModeToType(enmShw));
2897
2898	/* shadow */
2899	pVM->pgm.s.pfnR3ShwRelocate = pModeData->pfnR3ShwRelocate;
2900	pVM->pgm.s.pfnR3ShwExit = pModeData->pfnR3ShwExit;
2901	pVM->pgm.s.pfnR3ShwGetPage = pModeData->pfnR3ShwGetPage;
2902	Assert(pVM->pgm.s.pfnR3ShwGetPage);
2903	pVM->pgm.s.pfnR3ShwModifyPage = pModeData->pfnR3ShwModifyPage;
2904
2905	pVM->pgm.s.pfnRCShwGetPage = pModeData->pfnRCShwGetPage;
2906	pVM->pgm.s.pfnRCShwModifyPage = pModeData->pfnRCShwModifyPage;
2907
2908	pVM->pgm.s.pfnR0ShwGetPage = pModeData->pfnR0ShwGetPage;
2909	pVM->pgm.s.pfnR0ShwModifyPage = pModeData->pfnR0ShwModifyPage;
2910
2911
2912	/* guest */
2913	pVM->pgm.s.pfnR3GstRelocate = pModeData->pfnR3GstRelocate;
2914	pVM->pgm.s.pfnR3GstExit = pModeData->pfnR3GstExit;
2915	pVM->pgm.s.pfnR3GstGetPage = pModeData->pfnR3GstGetPage;
2916	Assert(pVM->pgm.s.pfnR3GstGetPage);
2917	pVM->pgm.s.pfnR3GstModifyPage = pModeData->pfnR3GstModifyPage;
2918	pVM->pgm.s.pfnR3GstGetPDE = pModeData->pfnR3GstGetPDE;
2919	pVM->pgm.s.pfnR3GstMonitorCR3 = pModeData->pfnR3GstMonitorCR3;
2920	pVM->pgm.s.pfnR3GstUnmonitorCR3 = pModeData->pfnR3GstUnmonitorCR3;
2921	pVM->pgm.s.pfnR3GstMapCR3 = pModeData->pfnR3GstMapCR3;
2922	pVM->pgm.s.pfnR3GstUnmapCR3 = pModeData->pfnR3GstUnmapCR3;
2923	pVM->pgm.s.pfnR3GstWriteHandlerCR3 = pModeData->pfnR3GstWriteHandlerCR3;
2924	pVM->pgm.s.pszR3GstWriteHandlerCR3 = pModeData->pszR3GstWriteHandlerCR3;
2925	pVM->pgm.s.pfnR3GstPAEWriteHandlerCR3 = pModeData->pfnR3GstPAEWriteHandlerCR3;
2926	pVM->pgm.s.pszR3GstPAEWriteHandlerCR3 = pModeData->pszR3GstPAEWriteHandlerCR3;
2927
2928	pVM->pgm.s.pfnRCGstGetPage = pModeData->pfnRCGstGetPage;
2929	pVM->pgm.s.pfnRCGstModifyPage = pModeData->pfnRCGstModifyPage;
2930	pVM->pgm.s.pfnRCGstGetPDE = pModeData->pfnRCGstGetPDE;
2931	pVM->pgm.s.pfnRCGstMonitorCR3 = pModeData->pfnRCGstMonitorCR3;
2932	pVM->pgm.s.pfnRCGstUnmonitorCR3 = pModeData->pfnRCGstUnmonitorCR3;
2933	pVM->pgm.s.pfnRCGstMapCR3 = pModeData->pfnRCGstMapCR3;
2934	pVM->pgm.s.pfnRCGstUnmapCR3 = pModeData->pfnRCGstUnmapCR3;
2935	pVM->pgm.s.pfnRCGstWriteHandlerCR3 = pModeData->pfnRCGstWriteHandlerCR3;
2936	pVM->pgm.s.pfnRCGstPAEWriteHandlerCR3 = pModeData->pfnRCGstPAEWriteHandlerCR3;
2937
2938	pVM->pgm.s.pfnR0GstGetPage = pModeData->pfnR0GstGetPage;
2939	pVM->pgm.s.pfnR0GstModifyPage = pModeData->pfnR0GstModifyPage;
2940	pVM->pgm.s.pfnR0GstGetPDE = pModeData->pfnR0GstGetPDE;
2941	pVM->pgm.s.pfnR0GstMonitorCR3 = pModeData->pfnR0GstMonitorCR3;
2942	pVM->pgm.s.pfnR0GstUnmonitorCR3 = pModeData->pfnR0GstUnmonitorCR3;
2943	pVM->pgm.s.pfnR0GstMapCR3 = pModeData->pfnR0GstMapCR3;
2944	pVM->pgm.s.pfnR0GstUnmapCR3 = pModeData->pfnR0GstUnmapCR3;
2945	pVM->pgm.s.pfnR0GstWriteHandlerCR3 = pModeData->pfnR0GstWriteHandlerCR3;
2946	pVM->pgm.s.pfnR0GstPAEWriteHandlerCR3 = pModeData->pfnR0GstPAEWriteHandlerCR3;
2947
2948
2949	/* both */
2950	pVM->pgm.s.pfnR3BthRelocate = pModeData->pfnR3BthRelocate;
2951	pVM->pgm.s.pfnR3BthInvalidatePage = pModeData->pfnR3BthInvalidatePage;
2952	pVM->pgm.s.pfnR3BthSyncCR3 = pModeData->pfnR3BthSyncCR3;
2953	Assert(pVM->pgm.s.pfnR3BthSyncCR3);
2954	pVM->pgm.s.pfnR3BthSyncPage = pModeData->pfnR3BthSyncPage;
2955	pVM->pgm.s.pfnR3BthPrefetchPage = pModeData->pfnR3BthPrefetchPage;
2956	pVM->pgm.s.pfnR3BthVerifyAccessSyncPage = pModeData->pfnR3BthVerifyAccessSyncPage;
2957	#ifdef VBOX_STRICT
2958	pVM->pgm.s.pfnR3BthAssertCR3 = pModeData->pfnR3BthAssertCR3;
2959	#endif
2960
2961	pVM->pgm.s.pfnRCBthTrap0eHandler = pModeData->pfnRCBthTrap0eHandler;
2962	pVM->pgm.s.pfnRCBthInvalidatePage = pModeData->pfnRCBthInvalidatePage;
2963	pVM->pgm.s.pfnRCBthSyncCR3 = pModeData->pfnRCBthSyncCR3;
2964	pVM->pgm.s.pfnRCBthSyncPage = pModeData->pfnRCBthSyncPage;
2965	pVM->pgm.s.pfnRCBthPrefetchPage = pModeData->pfnRCBthPrefetchPage;
2966	pVM->pgm.s.pfnRCBthVerifyAccessSyncPage = pModeData->pfnRCBthVerifyAccessSyncPage;
2967	#ifdef VBOX_STRICT
2968	pVM->pgm.s.pfnRCBthAssertCR3 = pModeData->pfnRCBthAssertCR3;
2969	#endif
2970
2971	pVM->pgm.s.pfnR0BthTrap0eHandler = pModeData->pfnR0BthTrap0eHandler;
2972	pVM->pgm.s.pfnR0BthInvalidatePage = pModeData->pfnR0BthInvalidatePage;
2973	pVM->pgm.s.pfnR0BthSyncCR3 = pModeData->pfnR0BthSyncCR3;
2974	pVM->pgm.s.pfnR0BthSyncPage = pModeData->pfnR0BthSyncPage;
2975	pVM->pgm.s.pfnR0BthPrefetchPage = pModeData->pfnR0BthPrefetchPage;
2976	pVM->pgm.s.pfnR0BthVerifyAccessSyncPage = pModeData->pfnR0BthVerifyAccessSyncPage;
2977	#ifdef VBOX_STRICT
2978	pVM->pgm.s.pfnR0BthAssertCR3 = pModeData->pfnR0BthAssertCR3;
2979	#endif
2980	}
2981
2982
2983	#ifdef DEBUG_bird
2984	#include <stdlib.h> /* getenv() remove me! */
2985	#endif
2986
2987	/**
2988	* Calculates the shadow paging mode.
2989	*
2990	* @returns The shadow paging mode.
2991	* @param pVM VM handle.
2992	* @param enmGuestMode The guest mode.
2993	* @param enmHostMode The host mode.
2994	* @param enmShadowMode The current shadow mode.
2995	* @param penmSwitcher Where to store the switcher to use.
2996	* VMMSWITCHER_INVALID means no change.
2997	*/
2998	static PGMMODE pgmR3CalcShadowMode(PVM pVM, PGMMODE enmGuestMode, SUPPAGINGMODE enmHostMode, PGMMODE enmShadowMode, VMMSWITCHER *penmSwitcher)
2999	{
3000	VMMSWITCHER enmSwitcher = VMMSWITCHER_INVALID;
3001	switch (enmGuestMode)
3002	{
3003	/*
3004	* When switching to real or protected mode we don't change
3005	* anything since it's likely that we'll switch back pretty soon.
3006	*
3007	* During pgmR3InitPaging we'll end up here with PGMMODE_INVALID
3008	* and is supposed to determine which shadow paging and switcher to
3009	* use during init.
3010	*/
3011	case PGMMODE_REAL:
3012	case PGMMODE_PROTECTED:
3013	if ( enmShadowMode != PGMMODE_INVALID
3014	&& !HWACCMIsEnabled(pVM) /* always switch in hwaccm mode! */)
3015	break; /* (no change) */
3016
3017	switch (enmHostMode)
3018	{
3019	case SUPPAGINGMODE_32_BIT:
3020	case SUPPAGINGMODE_32_BIT_GLOBAL:
3021	enmShadowMode = PGMMODE_32_BIT;
3022	enmSwitcher = VMMSWITCHER_32_TO_32;
3023	break;
3024
3025	case SUPPAGINGMODE_PAE:
3026	case SUPPAGINGMODE_PAE_NX:
3027	case SUPPAGINGMODE_PAE_GLOBAL:
3028	case SUPPAGINGMODE_PAE_GLOBAL_NX:
3029	enmShadowMode = PGMMODE_PAE;
3030	enmSwitcher = VMMSWITCHER_PAE_TO_PAE;
3031	#ifdef DEBUG_bird
3032	if (getenv("VBOX_32BIT"))
3033	{
3034	enmShadowMode = PGMMODE_32_BIT;
3035	enmSwitcher = VMMSWITCHER_PAE_TO_32;
3036	}
3037	#endif
3038	break;
3039
3040	case SUPPAGINGMODE_AMD64:
3041	case SUPPAGINGMODE_AMD64_GLOBAL:
3042	case SUPPAGINGMODE_AMD64_NX:
3043	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
3044	enmShadowMode = PGMMODE_PAE;
3045	enmSwitcher = VMMSWITCHER_AMD64_TO_PAE;
3046	break;
3047
3048	default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
3049	}
3050	break;
3051
3052	case PGMMODE_32_BIT:
3053	switch (enmHostMode)
3054	{
3055	case SUPPAGINGMODE_32_BIT:
3056	case SUPPAGINGMODE_32_BIT_GLOBAL:
3057	enmShadowMode = PGMMODE_32_BIT;
3058	enmSwitcher = VMMSWITCHER_32_TO_32;
3059	break;
3060
3061	case SUPPAGINGMODE_PAE:
3062	case SUPPAGINGMODE_PAE_NX:
3063	case SUPPAGINGMODE_PAE_GLOBAL:
3064	case SUPPAGINGMODE_PAE_GLOBAL_NX:
3065	enmShadowMode = PGMMODE_PAE;
3066	enmSwitcher = VMMSWITCHER_PAE_TO_PAE;
3067	#ifdef DEBUG_bird
3068	if (getenv("VBOX_32BIT"))
3069	{
3070	enmShadowMode = PGMMODE_32_BIT;
3071	enmSwitcher = VMMSWITCHER_PAE_TO_32;
3072	}
3073	#endif
3074	break;
3075
3076	case SUPPAGINGMODE_AMD64:
3077	case SUPPAGINGMODE_AMD64_GLOBAL:
3078	case SUPPAGINGMODE_AMD64_NX:
3079	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
3080	enmShadowMode = PGMMODE_PAE;
3081	enmSwitcher = VMMSWITCHER_AMD64_TO_PAE;
3082	break;
3083
3084	default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
3085	}
3086	break;
3087
3088	case PGMMODE_PAE:
3089	case PGMMODE_PAE_NX: /** @todo This might require more switchers and guest+both modes. */
3090	switch (enmHostMode)
3091	{
3092	case SUPPAGINGMODE_32_BIT:
3093	case SUPPAGINGMODE_32_BIT_GLOBAL:
3094	enmShadowMode = PGMMODE_PAE;
3095	enmSwitcher = VMMSWITCHER_32_TO_PAE;
3096	break;
3097
3098	case SUPPAGINGMODE_PAE:
3099	case SUPPAGINGMODE_PAE_NX:
3100	case SUPPAGINGMODE_PAE_GLOBAL:
3101	case SUPPAGINGMODE_PAE_GLOBAL_NX:
3102	enmShadowMode = PGMMODE_PAE;
3103	enmSwitcher = VMMSWITCHER_PAE_TO_PAE;
3104	break;
3105
3106	case SUPPAGINGMODE_AMD64:
3107	case SUPPAGINGMODE_AMD64_GLOBAL:
3108	case SUPPAGINGMODE_AMD64_NX:
3109	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
3110	enmShadowMode = PGMMODE_PAE;
3111	enmSwitcher = VMMSWITCHER_AMD64_TO_PAE;
3112	break;
3113
3114	default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
3115	}
3116	break;
3117
3118	case PGMMODE_AMD64:
3119	case PGMMODE_AMD64_NX:
3120	switch (enmHostMode)
3121	{
3122	case SUPPAGINGMODE_32_BIT:
3123	case SUPPAGINGMODE_32_BIT_GLOBAL:
3124	enmShadowMode = PGMMODE_PAE;
3125	enmSwitcher = VMMSWITCHER_32_TO_AMD64;
3126	break;
3127
3128	case SUPPAGINGMODE_PAE:
3129	case SUPPAGINGMODE_PAE_NX:
3130	case SUPPAGINGMODE_PAE_GLOBAL:
3131	case SUPPAGINGMODE_PAE_GLOBAL_NX:
3132	enmShadowMode = PGMMODE_PAE;
3133	enmSwitcher = VMMSWITCHER_PAE_TO_AMD64;
3134	break;
3135
3136	case SUPPAGINGMODE_AMD64:
3137	case SUPPAGINGMODE_AMD64_GLOBAL:
3138	case SUPPAGINGMODE_AMD64_NX:
3139	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
3140	enmShadowMode = PGMMODE_AMD64;
3141	enmSwitcher = VMMSWITCHER_AMD64_TO_AMD64;
3142	break;
3143
3144	default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
3145	}
3146	break;
3147
3148
3149	default:
3150	AssertReleaseMsgFailed(("enmGuestMode=%d\n", enmGuestMode));
3151	return PGMMODE_INVALID;
3152	}
3153	/* Override the shadow mode is nested paging is active. */
3154	if (HWACCMIsNestedPagingActive(pVM))
3155	enmShadowMode = HWACCMGetPagingMode(pVM);
3156
3157	*penmSwitcher = enmSwitcher;
3158	return enmShadowMode;
3159	}
3160
3161	/**
3162	* Performs the actual mode change.
3163	* This is called by PGMChangeMode and pgmR3InitPaging().
3164	*
3165	* @returns VBox status code.
3166	* @param pVM VM handle.
3167	* @param enmGuestMode The new guest mode. This is assumed to be different from
3168	* the current mode.
3169	*/
3170	VMMR3DECL(int) PGMR3ChangeMode(PVM pVM, PGMMODE enmGuestMode)
3171	{
3172	Log(("PGMR3ChangeMode: Guest mode: %s -> %s\n", PGMGetModeName(pVM->pgm.s.enmGuestMode), PGMGetModeName(enmGuestMode)));
3173	STAM_REL_COUNTER_INC(&pVM->pgm.s.cGuestModeChanges);
3174
3175	/*
3176	* Calc the shadow mode and switcher.
3177	*/
3178	VMMSWITCHER enmSwitcher;
3179	PGMMODE enmShadowMode = pgmR3CalcShadowMode(pVM, enmGuestMode, pVM->pgm.s.enmHostMode, pVM->pgm.s.enmShadowMode, &enmSwitcher);
3180	if (enmSwitcher != VMMSWITCHER_INVALID)
3181	{
3182	/*
3183	* Select new switcher.
3184	*/
3185	int rc = VMMR3SelectSwitcher(pVM, enmSwitcher);
3186	if (VBOX_FAILURE(rc))
3187	{
3188	AssertReleaseMsgFailed(("VMMR3SelectSwitcher(%d) -> %Vrc\n", enmSwitcher, rc));
3189	return rc;
3190	}
3191	}
3192
3193	/*
3194	* Exit old mode(s).
3195	*/
3196	/* shadow */
3197	if (enmShadowMode != pVM->pgm.s.enmShadowMode)
3198	{
3199	LogFlow(("PGMR3ChangeMode: Shadow mode: %s -> %s\n", PGMGetModeName(pVM->pgm.s.enmShadowMode), PGMGetModeName(enmShadowMode)));
3200	if (PGM_SHW_PFN(Exit, pVM))
3201	{
3202	int rc = PGM_SHW_PFN(Exit, pVM)(pVM);
3203	if (VBOX_FAILURE(rc))
3204	{
3205	AssertMsgFailed(("Exit failed for shadow mode %d: %Vrc\n", pVM->pgm.s.enmShadowMode, rc));
3206	return rc;
3207	}
3208	}
3209
3210	}
3211	else
3212	LogFlow(("PGMR3ChangeMode: Shadow mode remains: %s\n", PGMGetModeName(pVM->pgm.s.enmShadowMode)));
3213
3214	/* guest */
3215	if (PGM_GST_PFN(Exit, pVM))
3216	{
3217	int rc = PGM_GST_PFN(Exit, pVM)(pVM);
3218	if (VBOX_FAILURE(rc))
3219	{
3220	AssertMsgFailed(("Exit failed for guest mode %d: %Vrc\n", pVM->pgm.s.enmGuestMode, rc));
3221	return rc;
3222	}
3223	}
3224
3225	/*
3226	* Load new paging mode data.
3227	*/
3228	pgmR3ModeDataSwitch(pVM, enmShadowMode, enmGuestMode);
3229
3230	/*
3231	* Enter new shadow mode (if changed).
3232	*/
3233	if (enmShadowMode != pVM->pgm.s.enmShadowMode)
3234	{
3235	int rc;
3236	pVM->pgm.s.enmShadowMode = enmShadowMode;
3237	switch (enmShadowMode)
3238	{
3239	case PGMMODE_32_BIT:
3240	rc = PGM_SHW_NAME_32BIT(Enter)(pVM);
3241	break;
3242	case PGMMODE_PAE:
3243	case PGMMODE_PAE_NX:
3244	rc = PGM_SHW_NAME_PAE(Enter)(pVM);
3245	break;
3246	case PGMMODE_AMD64:
3247	case PGMMODE_AMD64_NX:
3248	rc = PGM_SHW_NAME_AMD64(Enter)(pVM);
3249	break;
3250	case PGMMODE_NESTED:
3251	rc = PGM_SHW_NAME_NESTED(Enter)(pVM);
3252	break;
3253	case PGMMODE_EPT:
3254	rc = PGM_SHW_NAME_EPT(Enter)(pVM);
3255	break;
3256	case PGMMODE_REAL:
3257	case PGMMODE_PROTECTED:
3258	default:
3259	AssertReleaseMsgFailed(("enmShadowMode=%d\n", enmShadowMode));
3260	return VERR_INTERNAL_ERROR;
3261	}
3262	if (VBOX_FAILURE(rc))
3263	{
3264	AssertReleaseMsgFailed(("Entering enmShadowMode=%d failed: %Vrc\n", enmShadowMode, rc));
3265	pVM->pgm.s.enmShadowMode = PGMMODE_INVALID;
3266	return rc;
3267	}
3268	}
3269
3270	/* We must flush the PGM pool cache if the guest mode changes; we don't always
3271	* switch shadow paging mode (e.g. protected->32-bit) and shouldn't reuse
3272	* the shadow page tables.
3273	*
3274	* That only applies when switching between paging and non-paging modes.
3275	*
3276	* @todo A20 setting
3277	*/
3278	if ( pVM->pgm.s.CTX_SUFF(pPool)
3279	&& !HWACCMIsNestedPagingActive(pVM)
3280	&& PGMMODE_WITH_PAGING(pVM->pgm.s.enmGuestMode) != PGMMODE_WITH_PAGING(enmGuestMode))
3281	{
3282	Log(("PGMR3ChangeMode: changing guest paging mode -> flush pgm pool cache!\n"));
3283	pgmPoolFlushAll(pVM);
3284	}
3285
3286	/*
3287	* Enter the new guest and shadow+guest modes.
3288	*/
3289	int rc = -1;
3290	int rc2 = -1;
3291	RTGCPHYS GCPhysCR3 = NIL_RTGCPHYS;
3292	pVM->pgm.s.enmGuestMode = enmGuestMode;
3293	switch (enmGuestMode)
3294	{
3295	case PGMMODE_REAL:
3296	rc = PGM_GST_NAME_REAL(Enter)(pVM, NIL_RTGCPHYS);
3297	switch (pVM->pgm.s.enmShadowMode)
3298	{
3299	case PGMMODE_32_BIT:
3300	rc2 = PGM_BTH_NAME_32BIT_REAL(Enter)(pVM, NIL_RTGCPHYS);
3301	break;
3302	case PGMMODE_PAE:
3303	case PGMMODE_PAE_NX:
3304	rc2 = PGM_BTH_NAME_PAE_REAL(Enter)(pVM, NIL_RTGCPHYS);
3305	break;
3306	case PGMMODE_NESTED:
3307	rc2 = PGM_BTH_NAME_NESTED_REAL(Enter)(pVM, NIL_RTGCPHYS);
3308	break;
3309	case PGMMODE_EPT:
3310	rc2 = PGM_BTH_NAME_EPT_REAL(Enter)(pVM, NIL_RTGCPHYS);
3311	break;
3312	case PGMMODE_AMD64:
3313	case PGMMODE_AMD64_NX:
3314	AssertMsgFailed(("Should use PAE shadow mode!\n"));
3315	default: AssertFailed(); break;
3316	}
3317	break;
3318
3319	case PGMMODE_PROTECTED:
3320	rc = PGM_GST_NAME_PROT(Enter)(pVM, NIL_RTGCPHYS);
3321	switch (pVM->pgm.s.enmShadowMode)
3322	{
3323	case PGMMODE_32_BIT:
3324	rc2 = PGM_BTH_NAME_32BIT_PROT(Enter)(pVM, NIL_RTGCPHYS);
3325	break;
3326	case PGMMODE_PAE:
3327	case PGMMODE_PAE_NX:
3328	rc2 = PGM_BTH_NAME_PAE_PROT(Enter)(pVM, NIL_RTGCPHYS);
3329	break;
3330	case PGMMODE_NESTED:
3331	rc2 = PGM_BTH_NAME_NESTED_PROT(Enter)(pVM, NIL_RTGCPHYS);
3332	break;
3333	case PGMMODE_EPT:
3334	rc2 = PGM_BTH_NAME_EPT_PROT(Enter)(pVM, NIL_RTGCPHYS);
3335	break;
3336	case PGMMODE_AMD64:
3337	case PGMMODE_AMD64_NX:
3338	AssertMsgFailed(("Should use PAE shadow mode!\n"));
3339	default: AssertFailed(); break;
3340	}
3341	break;
3342
3343	case PGMMODE_32_BIT:
3344	GCPhysCR3 = CPUMGetGuestCR3(pVM) & X86_CR3_PAGE_MASK;
3345	rc = PGM_GST_NAME_32BIT(Enter)(pVM, GCPhysCR3);
3346	switch (pVM->pgm.s.enmShadowMode)
3347	{
3348	case PGMMODE_32_BIT:
3349	rc2 = PGM_BTH_NAME_32BIT_32BIT(Enter)(pVM, GCPhysCR3);
3350	break;
3351	case PGMMODE_PAE:
3352	case PGMMODE_PAE_NX:
3353	rc2 = PGM_BTH_NAME_PAE_32BIT(Enter)(pVM, GCPhysCR3);
3354	break;
3355	case PGMMODE_NESTED:
3356	rc2 = PGM_BTH_NAME_NESTED_32BIT(Enter)(pVM, GCPhysCR3);
3357	break;
3358	case PGMMODE_EPT:
3359	rc2 = PGM_BTH_NAME_EPT_32BIT(Enter)(pVM, GCPhysCR3);
3360	break;
3361	case PGMMODE_AMD64:
3362	case PGMMODE_AMD64_NX:
3363	AssertMsgFailed(("Should use PAE shadow mode!\n"));
3364	default: AssertFailed(); break;
3365	}
3366	break;
3367
3368	case PGMMODE_PAE_NX:
3369	case PGMMODE_PAE:
3370	{
3371	uint32_t u32Dummy, u32Features;
3372
3373	CPUMGetGuestCpuId(pVM, 1, &u32Dummy, &u32Dummy, &u32Dummy, &u32Features);
3374	if (!(u32Features & X86_CPUID_FEATURE_EDX_PAE))
3375	{
3376	/* Pause first, then inform Main. */
3377	rc = VMR3SuspendNoSave(pVM);
3378	AssertRC(rc);
3379
3380	VMSetRuntimeError(pVM, true, "PAEmode",
3381	N_("The guest is trying to switch to the PAE mode which is currently disabled by default in VirtualBox. Experimental PAE support can be enabled using the -pae option with VBoxManage"));
3382	/* we must return TRUE here otherwise the recompiler will assert */
3383	return VINF_SUCCESS;
3384	}
3385	GCPhysCR3 = CPUMGetGuestCR3(pVM) & X86_CR3_PAE_PAGE_MASK;
3386	rc = PGM_GST_NAME_PAE(Enter)(pVM, GCPhysCR3);
3387	switch (pVM->pgm.s.enmShadowMode)
3388	{
3389	case PGMMODE_PAE:
3390	case PGMMODE_PAE_NX:
3391	rc2 = PGM_BTH_NAME_PAE_PAE(Enter)(pVM, GCPhysCR3);
3392	break;
3393	case PGMMODE_NESTED:
3394	rc2 = PGM_BTH_NAME_NESTED_PAE(Enter)(pVM, GCPhysCR3);
3395	break;
3396	case PGMMODE_EPT:
3397	rc2 = PGM_BTH_NAME_EPT_PAE(Enter)(pVM, GCPhysCR3);
3398	break;
3399	case PGMMODE_32_BIT:
3400	case PGMMODE_AMD64:
3401	case PGMMODE_AMD64_NX:
3402	AssertMsgFailed(("Should use PAE shadow mode!\n"));
3403	default: AssertFailed(); break;
3404	}
3405	break;
3406	}
3407
3408	#ifdef VBOX_WITH_64_BITS_GUESTS
3409	case PGMMODE_AMD64_NX:
3410	case PGMMODE_AMD64:
3411	GCPhysCR3 = CPUMGetGuestCR3(pVM) & 0xfffffffffffff000ULL; /** @todo define this mask! */
3412	rc = PGM_GST_NAME_AMD64(Enter)(pVM, GCPhysCR3);
3413	switch (pVM->pgm.s.enmShadowMode)
3414	{
3415	case PGMMODE_AMD64:
3416	case PGMMODE_AMD64_NX:
3417	rc2 = PGM_BTH_NAME_AMD64_AMD64(Enter)(pVM, GCPhysCR3);
3418	break;
3419	case PGMMODE_NESTED:
3420	rc2 = PGM_BTH_NAME_NESTED_AMD64(Enter)(pVM, GCPhysCR3);
3421	break;
3422	case PGMMODE_EPT:
3423	rc2 = PGM_BTH_NAME_EPT_AMD64(Enter)(pVM, GCPhysCR3);
3424	break;
3425	case PGMMODE_32_BIT:
3426	case PGMMODE_PAE:
3427	case PGMMODE_PAE_NX:
3428	AssertMsgFailed(("Should use AMD64 shadow mode!\n"));
3429	default: AssertFailed(); break;
3430	}
3431	break;
3432	#endif
3433
3434	default:
3435	AssertReleaseMsgFailed(("enmGuestMode=%d\n", enmGuestMode));
3436	rc = VERR_NOT_IMPLEMENTED;
3437	break;
3438	}
3439
3440	/* status codes. */
3441	AssertRC(rc);
3442	AssertRC(rc2);
3443	if (VBOX_SUCCESS(rc))
3444	{
3445	rc = rc2;
3446	if (VBOX_SUCCESS(rc)) /* no informational status codes. */
3447	rc = VINF_SUCCESS;
3448	}
3449
3450	/*
3451	* Notify SELM so it can update the TSSes with correct CR3s.
3452	*/
3453	SELMR3PagingModeChanged(pVM);
3454
3455	/* Notify HWACCM as well. */
3456	HWACCMR3PagingModeChanged(pVM, pVM->pgm.s.enmShadowMode);
3457	return rc;
3458	}
3459
3460
3461	/**
3462	* Dumps a PAE shadow page table.
3463	*
3464	* @returns VBox status code (VINF_SUCCESS).
3465	* @param pVM The VM handle.
3466	* @param pPT Pointer to the page table.
3467	* @param u64Address The virtual address of the page table starts.
3468	* @param fLongMode Set if this a long mode table; clear if it's a legacy mode table.
3469	* @param cMaxDepth The maxium depth.
3470	* @param pHlp Pointer to the output functions.
3471	*/
3472	static int pgmR3DumpHierarchyHCPaePT(PVM pVM, PX86PTPAE pPT, uint64_t u64Address, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
3473	{
3474	for (unsigned i = 0; i < RT_ELEMENTS(pPT->a); i++)
3475	{
3476	X86PTEPAE Pte = pPT->a[i];
3477	if (Pte.n.u1Present)
3478	{
3479	pHlp->pfnPrintf(pHlp,
3480	fLongMode /P R S A D G WT CD AT NX 4M a p ? /
3481	? "%016llx 3 \| P %c %c %c %c %c %s %s %s %s 4K %c%c%c %016llx\n"
3482	: "%08llx 2 \| P %c %c %c %c %c %s %s %s %s 4K %c%c%c %016llx\n",
3483	u64Address + ((uint64_t)i << X86_PT_PAE_SHIFT),
3484	Pte.n.u1Write ? 'W' : 'R',
3485	Pte.n.u1User ? 'U' : 'S',
3486	Pte.n.u1Accessed ? 'A' : '-',
3487	Pte.n.u1Dirty ? 'D' : '-',
3488	Pte.n.u1Global ? 'G' : '-',
3489	Pte.n.u1WriteThru ? "WT" : "--",
3490	Pte.n.u1CacheDisable? "CD" : "--",
3491	Pte.n.u1PAT ? "AT" : "--",
3492	Pte.n.u1NoExecute ? "NX" : "--",
3493	Pte.u & PGM_PTFLAGS_TRACK_DIRTY ? 'd' : '-',
3494	Pte.u & RT_BIT(10) ? '1' : '0',
3495	Pte.u & PGM_PTFLAGS_CSAM_VALIDATED? 'v' : '-',
3496	Pte.u & X86_PTE_PAE_PG_MASK);
3497	}
3498	}
3499	return VINF_SUCCESS;
3500	}
3501
3502
3503	/**
3504	* Dumps a PAE shadow page directory table.
3505	*
3506	* @returns VBox status code (VINF_SUCCESS).
3507	* @param pVM The VM handle.
3508	* @param HCPhys The physical address of the page directory table.
3509	* @param u64Address The virtual address of the page table starts.
3510	* @param cr4 The CR4, PSE is currently used.
3511	* @param fLongMode Set if this a long mode table; clear if it's a legacy mode table.
3512	* @param cMaxDepth The maxium depth.
3513	* @param pHlp Pointer to the output functions.
3514	*/
3515	static int pgmR3DumpHierarchyHCPaePD(PVM pVM, RTHCPHYS HCPhys, uint64_t u64Address, uint32_t cr4, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
3516	{
3517	PX86PDPAE pPD = (PX86PDPAE)MMPagePhys2Page(pVM, HCPhys);
3518	if (!pPD)
3519	{
3520	pHlp->pfnPrintf(pHlp, "%0*llx error! Page directory at HCPhys=%#VHp was not found in the page pool!\n",
3521	fLongMode ? 16 : 8, u64Address, HCPhys);
3522	return VERR_INVALID_PARAMETER;
3523	}
3524	const bool fBigPagesSupported = fLongMode \|\| !!(cr4 & X86_CR4_PSE);
3525
3526	int rc = VINF_SUCCESS;
3527	for (unsigned i = 0; i < RT_ELEMENTS(pPD->a); i++)
3528	{
3529	X86PDEPAE Pde = pPD->a[i];
3530	if (Pde.n.u1Present)
3531	{
3532	if (fBigPagesSupported && Pde.b.u1Size)
3533	pHlp->pfnPrintf(pHlp,
3534	fLongMode /P R S A D G WT CD AT NX 4M a p ? /
3535	? "%016llx 2 \| P %c %c %c %c %c %s %s %s %s 4M %c%c%c %016llx\n"
3536	: "%08llx 1 \| P %c %c %c %c %c %s %s %s %s 4M %c%c%c %016llx\n",
3537	u64Address + ((uint64_t)i << X86_PD_PAE_SHIFT),
3538	Pde.b.u1Write ? 'W' : 'R',
3539	Pde.b.u1User ? 'U' : 'S',
3540	Pde.b.u1Accessed ? 'A' : '-',
3541	Pde.b.u1Dirty ? 'D' : '-',
3542	Pde.b.u1Global ? 'G' : '-',
3543	Pde.b.u1WriteThru ? "WT" : "--",
3544	Pde.b.u1CacheDisable? "CD" : "--",
3545	Pde.b.u1PAT ? "AT" : "--",
3546	Pde.b.u1NoExecute ? "NX" : "--",
3547	Pde.u & RT_BIT_64(9) ? '1' : '0',
3548	Pde.u & PGM_PDFLAGS_MAPPING ? 'm' : '-',
3549	Pde.u & PGM_PDFLAGS_TRACK_DIRTY ? 'd' : '-',
3550	Pde.u & X86_PDE_PAE_PG_MASK);
3551	else
3552	{
3553	pHlp->pfnPrintf(pHlp,
3554	fLongMode /P R S A D G WT CD AT NX 4M a p ? /
3555	? "%016llx 2 \| P %c %c %c %c %c %s %s .. %s 4K %c%c%c %016llx\n"
3556	: "%08llx 1 \| P %c %c %c %c %c %s %s .. %s 4K %c%c%c %016llx\n",
3557	u64Address + ((uint64_t)i << X86_PD_PAE_SHIFT),
3558	Pde.n.u1Write ? 'W' : 'R',
3559	Pde.n.u1User ? 'U' : 'S',
3560	Pde.n.u1Accessed ? 'A' : '-',
3561	Pde.n.u1Reserved0 ? '?' : '.', /* ignored */
3562	Pde.n.u1Reserved1 ? '?' : '.', /* ignored */
3563	Pde.n.u1WriteThru ? "WT" : "--",
3564	Pde.n.u1CacheDisable? "CD" : "--",
3565	Pde.n.u1NoExecute ? "NX" : "--",
3566	Pde.u & RT_BIT_64(9) ? '1' : '0',
3567	Pde.u & PGM_PDFLAGS_MAPPING ? 'm' : '-',
3568	Pde.u & PGM_PDFLAGS_TRACK_DIRTY ? 'd' : '-',
3569	Pde.u & X86_PDE_PAE_PG_MASK);
3570	if (cMaxDepth >= 1)
3571	{
3572	/** @todo what about using the page pool for mapping PTs? */
3573	uint64_t u64AddressPT = u64Address + ((uint64_t)i << X86_PD_PAE_SHIFT);
3574	RTHCPHYS HCPhysPT = Pde.u & X86_PDE_PAE_PG_MASK;
3575	PX86PTPAE pPT = NULL;
3576	if (!(Pde.u & PGM_PDFLAGS_MAPPING))
3577	pPT = (PX86PTPAE)MMPagePhys2Page(pVM, HCPhysPT);
3578	else
3579	{
3580	for (PPGMMAPPING pMap = pVM->pgm.s.pMappingsR3; pMap; pMap = pMap->pNextR3)
3581	{
3582	uint64_t off = u64AddressPT - pMap->GCPtr;
3583	if (off < pMap->cb)
3584	{
3585	const int iPDE = (uint32_t)(off >> X86_PD_SHIFT);
3586	const int iSub = (int)((off >> X86_PD_PAE_SHIFT) & 1); /* MSC is a pain sometimes */
3587	if ((iSub ? pMap->aPTs[iPDE].HCPhysPaePT1 : pMap->aPTs[iPDE].HCPhysPaePT0) != HCPhysPT)
3588	pHlp->pfnPrintf(pHlp, "%0*llx error! Mapping error! PT %d has HCPhysPT=%VHp not %VHp is in the PD.\n",
3589	fLongMode ? 16 : 8, u64AddressPT, iPDE,
3590	iSub ? pMap->aPTs[iPDE].HCPhysPaePT1 : pMap->aPTs[iPDE].HCPhysPaePT0, HCPhysPT);
3591	pPT = &pMap->aPTs[iPDE].paPaePTsR3[iSub];
3592	}
3593	}
3594	}
3595	int rc2 = VERR_INVALID_PARAMETER;
3596	if (pPT)
3597	rc2 = pgmR3DumpHierarchyHCPaePT(pVM, pPT, u64AddressPT, fLongMode, cMaxDepth - 1, pHlp);
3598	else
3599	pHlp->pfnPrintf(pHlp, "%0*llx error! Page table at HCPhys=%#VHp was not found in the page pool!\n",
3600	fLongMode ? 16 : 8, u64AddressPT, HCPhysPT);
3601	if (rc2 < rc && VBOX_SUCCESS(rc))
3602	rc = rc2;
3603	}
3604	}
3605	}
3606	}
3607	return rc;
3608	}
3609
3610
3611	/**
3612	* Dumps a PAE shadow page directory pointer table.
3613	*
3614	* @returns VBox status code (VINF_SUCCESS).
3615	* @param pVM The VM handle.
3616	* @param HCPhys The physical address of the page directory pointer table.
3617	* @param u64Address The virtual address of the page table starts.
3618	* @param cr4 The CR4, PSE is currently used.
3619	* @param fLongMode Set if this a long mode table; clear if it's a legacy mode table.
3620	* @param cMaxDepth The maxium depth.
3621	* @param pHlp Pointer to the output functions.
3622	*/
3623	static int pgmR3DumpHierarchyHCPaePDPT(PVM pVM, RTHCPHYS HCPhys, uint64_t u64Address, uint32_t cr4, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
3624	{
3625	PX86PDPT pPDPT = (PX86PDPT)MMPagePhys2Page(pVM, HCPhys);
3626	if (!pPDPT)
3627	{
3628	pHlp->pfnPrintf(pHlp, "%0*llx error! Page directory pointer table at HCPhys=%#VHp was not found in the page pool!\n",
3629	fLongMode ? 16 : 8, u64Address, HCPhys);
3630	return VERR_INVALID_PARAMETER;
3631	}
3632
3633	int rc = VINF_SUCCESS;
3634	const unsigned c = fLongMode ? RT_ELEMENTS(pPDPT->a) : X86_PG_PAE_PDPE_ENTRIES;
3635	for (unsigned i = 0; i < c; i++)
3636	{
3637	X86PDPE Pdpe = pPDPT->a[i];
3638	if (Pdpe.n.u1Present)
3639	{
3640	if (fLongMode)
3641	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a p ? /
3642	"%016llx 1 \| P %c %c %c %c %c %s %s %s %s .. %c%c%c %016llx\n",
3643	u64Address + ((uint64_t)i << X86_PDPT_SHIFT),
3644	Pdpe.lm.u1Write ? 'W' : 'R',
3645	Pdpe.lm.u1User ? 'U' : 'S',
3646	Pdpe.lm.u1Accessed ? 'A' : '-',
3647	Pdpe.lm.u3Reserved & 1? '?' : '.', /* ignored */
3648	Pdpe.lm.u3Reserved & 4? '!' : '.', /* mbz */
3649	Pdpe.lm.u1WriteThru ? "WT" : "--",
3650	Pdpe.lm.u1CacheDisable? "CD" : "--",
3651	Pdpe.lm.u3Reserved & 2? "!" : "..",/* mbz */
3652	Pdpe.lm.u1NoExecute ? "NX" : "--",
3653	Pdpe.u & RT_BIT(9) ? '1' : '0',
3654	Pdpe.u & PGM_PLXFLAGS_PERMANENT ? 'p' : '-',
3655	Pdpe.u & RT_BIT(11) ? '1' : '0',
3656	Pdpe.u & X86_PDPE_PG_MASK);
3657	else
3658	pHlp->pfnPrintf(pHlp, /P G WT CD AT NX 4M a p ? /
3659	"%08x 0 \| P %c %s %s %s %s .. %c%c%c %016llx\n",
3660	i << X86_PDPT_SHIFT,
3661	Pdpe.n.u4Reserved & 1? '!' : '.', /* mbz */
3662	Pdpe.n.u4Reserved & 4? '!' : '.', /* mbz */
3663	Pdpe.n.u1WriteThru ? "WT" : "--",
3664	Pdpe.n.u1CacheDisable? "CD" : "--",
3665	Pdpe.n.u4Reserved & 2? "!" : "..",/* mbz */
3666	Pdpe.u & RT_BIT(9) ? '1' : '0',
3667	Pdpe.u & PGM_PLXFLAGS_PERMANENT ? 'p' : '-',
3668	Pdpe.u & RT_BIT(11) ? '1' : '0',
3669	Pdpe.u & X86_PDPE_PG_MASK);
3670	if (cMaxDepth >= 1)
3671	{
3672	int rc2 = pgmR3DumpHierarchyHCPaePD(pVM, Pdpe.u & X86_PDPE_PG_MASK, u64Address + ((uint64_t)i << X86_PDPT_SHIFT),
3673	cr4, fLongMode, cMaxDepth - 1, pHlp);
3674	if (rc2 < rc && VBOX_SUCCESS(rc))
3675	rc = rc2;
3676	}
3677	}
3678	}
3679	return rc;
3680	}
3681
3682
3683	/**
3684	* Dumps a 32-bit shadow page table.
3685	*
3686	* @returns VBox status code (VINF_SUCCESS).
3687	* @param pVM The VM handle.
3688	* @param HCPhys The physical address of the table.
3689	* @param cr4 The CR4, PSE is currently used.
3690	* @param cMaxDepth The maxium depth.
3691	* @param pHlp Pointer to the output functions.
3692	*/
3693	static int pgmR3DumpHierarchyHcPaePML4(PVM pVM, RTHCPHYS HCPhys, uint32_t cr4, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
3694	{
3695	PX86PML4 pPML4 = (PX86PML4)MMPagePhys2Page(pVM, HCPhys);
3696	if (!pPML4)
3697	{
3698	pHlp->pfnPrintf(pHlp, "Page map level 4 at HCPhys=%#VHp was not found in the page pool!\n", HCPhys);
3699	return VERR_INVALID_PARAMETER;
3700	}
3701
3702	int rc = VINF_SUCCESS;
3703	for (unsigned i = 0; i < RT_ELEMENTS(pPML4->a); i++)
3704	{
3705	X86PML4E Pml4e = pPML4->a[i];
3706	if (Pml4e.n.u1Present)
3707	{
3708	uint64_t u64Address = ((uint64_t)i << X86_PML4_SHIFT) \| (((uint64_t)i >> (X86_PML4_SHIFT - X86_PDPT_SHIFT - 1)) * 0xffff000000000000ULL);
3709	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a p ? /
3710	"%016llx 0 \| P %c %c %c %c %c %s %s %s %s .. %c%c%c %016llx\n",
3711	u64Address,
3712	Pml4e.n.u1Write ? 'W' : 'R',
3713	Pml4e.n.u1User ? 'U' : 'S',
3714	Pml4e.n.u1Accessed ? 'A' : '-',
3715	Pml4e.n.u3Reserved & 1? '?' : '.', /* ignored */
3716	Pml4e.n.u3Reserved & 4? '!' : '.', /* mbz */
3717	Pml4e.n.u1WriteThru ? "WT" : "--",
3718	Pml4e.n.u1CacheDisable? "CD" : "--",
3719	Pml4e.n.u3Reserved & 2? "!" : "..",/* mbz */
3720	Pml4e.n.u1NoExecute ? "NX" : "--",
3721	Pml4e.u & RT_BIT(9) ? '1' : '0',
3722	Pml4e.u & PGM_PLXFLAGS_PERMANENT ? 'p' : '-',
3723	Pml4e.u & RT_BIT(11) ? '1' : '0',
3724	Pml4e.u & X86_PML4E_PG_MASK);
3725
3726	if (cMaxDepth >= 1)
3727	{
3728	int rc2 = pgmR3DumpHierarchyHCPaePDPT(pVM, Pml4e.u & X86_PML4E_PG_MASK, u64Address, cr4, true, cMaxDepth - 1, pHlp);
3729	if (rc2 < rc && VBOX_SUCCESS(rc))
3730	rc = rc2;
3731	}
3732	}
3733	}
3734	return rc;
3735	}
3736
3737
3738	/**
3739	* Dumps a 32-bit shadow page table.
3740	*
3741	* @returns VBox status code (VINF_SUCCESS).
3742	* @param pVM The VM handle.
3743	* @param pPT Pointer to the page table.
3744	* @param u32Address The virtual address this table starts at.
3745	* @param pHlp Pointer to the output functions.
3746	*/
3747	int pgmR3DumpHierarchyHC32BitPT(PVM pVM, PX86PT pPT, uint32_t u32Address, PCDBGFINFOHLP pHlp)
3748	{
3749	for (unsigned i = 0; i < RT_ELEMENTS(pPT->a); i++)
3750	{
3751	X86PTE Pte = pPT->a[i];
3752	if (Pte.n.u1Present)
3753	{
3754	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a m d /
3755	"%08x 1 \| P %c %c %c %c %c %s %s %s .. 4K %c%c%c %08x\n",
3756	u32Address + (i << X86_PT_SHIFT),
3757	Pte.n.u1Write ? 'W' : 'R',
3758	Pte.n.u1User ? 'U' : 'S',
3759	Pte.n.u1Accessed ? 'A' : '-',
3760	Pte.n.u1Dirty ? 'D' : '-',
3761	Pte.n.u1Global ? 'G' : '-',
3762	Pte.n.u1WriteThru ? "WT" : "--",
3763	Pte.n.u1CacheDisable? "CD" : "--",
3764	Pte.n.u1PAT ? "AT" : "--",
3765	Pte.u & PGM_PTFLAGS_TRACK_DIRTY ? 'd' : '-',
3766	Pte.u & RT_BIT(10) ? '1' : '0',
3767	Pte.u & PGM_PTFLAGS_CSAM_VALIDATED ? 'v' : '-',
3768	Pte.u & X86_PDE_PG_MASK);
3769	}
3770	}
3771	return VINF_SUCCESS;
3772	}
3773
3774
3775	/**
3776	* Dumps a 32-bit shadow page directory and page tables.
3777	*
3778	* @returns VBox status code (VINF_SUCCESS).
3779	* @param pVM The VM handle.
3780	* @param cr3 The root of the hierarchy.
3781	* @param cr4 The CR4, PSE is currently used.
3782	* @param cMaxDepth How deep into the hierarchy the dumper should go.
3783	* @param pHlp Pointer to the output functions.
3784	*/
3785	int pgmR3DumpHierarchyHC32BitPD(PVM pVM, uint32_t cr3, uint32_t cr4, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
3786	{
3787	PX86PD pPD = (PX86PD)MMPagePhys2Page(pVM, cr3 & X86_CR3_PAGE_MASK);
3788	if (!pPD)
3789	{
3790	pHlp->pfnPrintf(pHlp, "Page directory at %#x was not found in the page pool!\n", cr3 & X86_CR3_PAGE_MASK);
3791	return VERR_INVALID_PARAMETER;
3792	}
3793
3794	int rc = VINF_SUCCESS;
3795	for (unsigned i = 0; i < RT_ELEMENTS(pPD->a); i++)
3796	{
3797	X86PDE Pde = pPD->a[i];
3798	if (Pde.n.u1Present)
3799	{
3800	const uint32_t u32Address = i << X86_PD_SHIFT;
3801	if ((cr4 & X86_CR4_PSE) && Pde.b.u1Size)
3802	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a m d /
3803	"%08x 0 \| P %c %c %c %c %c %s %s %s .. 4M %c%c%c %08x\n",
3804	u32Address,
3805	Pde.b.u1Write ? 'W' : 'R',
3806	Pde.b.u1User ? 'U' : 'S',
3807	Pde.b.u1Accessed ? 'A' : '-',
3808	Pde.b.u1Dirty ? 'D' : '-',
3809	Pde.b.u1Global ? 'G' : '-',
3810	Pde.b.u1WriteThru ? "WT" : "--",
3811	Pde.b.u1CacheDisable? "CD" : "--",
3812	Pde.b.u1PAT ? "AT" : "--",
3813	Pde.u & RT_BIT_64(9) ? '1' : '0',
3814	Pde.u & PGM_PDFLAGS_MAPPING ? 'm' : '-',
3815	Pde.u & PGM_PDFLAGS_TRACK_DIRTY ? 'd' : '-',
3816	Pde.u & X86_PDE4M_PG_MASK);
3817	else
3818	{
3819	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a m d /
3820	"%08x 0 \| P %c %c %c %c %c %s %s .. .. 4K %c%c%c %08x\n",
3821	u32Address,
3822	Pde.n.u1Write ? 'W' : 'R',
3823	Pde.n.u1User ? 'U' : 'S',
3824	Pde.n.u1Accessed ? 'A' : '-',
3825	Pde.n.u1Reserved0 ? '?' : '.', /* ignored */
3826	Pde.n.u1Reserved1 ? '?' : '.', /* ignored */
3827	Pde.n.u1WriteThru ? "WT" : "--",
3828	Pde.n.u1CacheDisable? "CD" : "--",
3829	Pde.u & RT_BIT_64(9) ? '1' : '0',
3830	Pde.u & PGM_PDFLAGS_MAPPING ? 'm' : '-',
3831	Pde.u & PGM_PDFLAGS_TRACK_DIRTY ? 'd' : '-',
3832	Pde.u & X86_PDE_PG_MASK);
3833	if (cMaxDepth >= 1)
3834	{
3835	/** @todo what about using the page pool for mapping PTs? */
3836	RTHCPHYS HCPhys = Pde.u & X86_PDE_PG_MASK;
3837	PX86PT pPT = NULL;
3838	if (!(Pde.u & PGM_PDFLAGS_MAPPING))
3839	pPT = (PX86PT)MMPagePhys2Page(pVM, HCPhys);
3840	else
3841	{
3842	for (PPGMMAPPING pMap = pVM->pgm.s.pMappingsR3; pMap; pMap = pMap->pNextR3)
3843	if (u32Address - pMap->GCPtr < pMap->cb)
3844	{
3845	int iPDE = (u32Address - pMap->GCPtr) >> X86_PD_SHIFT;
3846	if (pMap->aPTs[iPDE].HCPhysPT != HCPhys)
3847	pHlp->pfnPrintf(pHlp, "%08x error! Mapping error! PT %d has HCPhysPT=%VHp not %VHp is in the PD.\n",
3848	u32Address, iPDE, pMap->aPTs[iPDE].HCPhysPT, HCPhys);
3849	pPT = pMap->aPTs[iPDE].pPTR3;
3850	}
3851	}
3852	int rc2 = VERR_INVALID_PARAMETER;
3853	if (pPT)
3854	rc2 = pgmR3DumpHierarchyHC32BitPT(pVM, pPT, u32Address, pHlp);
3855	else
3856	pHlp->pfnPrintf(pHlp, "%08x error! Page table at %#x was not found in the page pool!\n", u32Address, HCPhys);
3857	if (rc2 < rc && VBOX_SUCCESS(rc))
3858	rc = rc2;
3859	}
3860	}
3861	}
3862	}
3863
3864	return rc;
3865	}
3866
3867
3868	/**
3869	* Dumps a 32-bit shadow page table.
3870	*
3871	* @returns VBox status code (VINF_SUCCESS).
3872	* @param pVM The VM handle.
3873	* @param pPT Pointer to the page table.
3874	* @param u32Address The virtual address this table starts at.
3875	* @param PhysSearch Address to search for.
3876	*/
3877	int pgmR3DumpHierarchyGC32BitPT(PVM pVM, PX86PT pPT, uint32_t u32Address, RTGCPHYS PhysSearch)
3878	{
3879	for (unsigned i = 0; i < RT_ELEMENTS(pPT->a); i++)
3880	{
3881	X86PTE Pte = pPT->a[i];
3882	if (Pte.n.u1Present)
3883	{
3884	Log(( /P R S A D G WT CD AT NX 4M a m d /
3885	"%08x 1 \| P %c %c %c %c %c %s %s %s .. 4K %c%c%c %08x\n",
3886	u32Address + (i << X86_PT_SHIFT),
3887	Pte.n.u1Write ? 'W' : 'R',
3888	Pte.n.u1User ? 'U' : 'S',
3889	Pte.n.u1Accessed ? 'A' : '-',
3890	Pte.n.u1Dirty ? 'D' : '-',
3891	Pte.n.u1Global ? 'G' : '-',
3892	Pte.n.u1WriteThru ? "WT" : "--",
3893	Pte.n.u1CacheDisable? "CD" : "--",
3894	Pte.n.u1PAT ? "AT" : "--",
3895	Pte.u & PGM_PTFLAGS_TRACK_DIRTY ? 'd' : '-',
3896	Pte.u & RT_BIT(10) ? '1' : '0',
3897	Pte.u & PGM_PTFLAGS_CSAM_VALIDATED ? 'v' : '-',
3898	Pte.u & X86_PDE_PG_MASK));
3899
3900	if ((Pte.u & X86_PDE_PG_MASK) == PhysSearch)
3901	{
3902	uint64_t fPageShw = 0;
3903	RTHCPHYS pPhysHC = 0;
3904
3905	PGMShwGetPage(pVM, (RTGCPTR)(u32Address + (i << X86_PT_SHIFT)), &fPageShw, &pPhysHC);
3906	Log(("Found %VGp at %VGv -> flags=%llx\n", PhysSearch, (RTGCPTR)(u32Address + (i << X86_PT_SHIFT)), fPageShw));
3907	}
3908	}
3909	}
3910	return VINF_SUCCESS;
3911	}
3912
3913
3914	/**
3915	* Dumps a 32-bit guest page directory and page tables.
3916	*
3917	* @returns VBox status code (VINF_SUCCESS).
3918	* @param pVM The VM handle.
3919	* @param cr3 The root of the hierarchy.
3920	* @param cr4 The CR4, PSE is currently used.
3921	* @param PhysSearch Address to search for.
3922	*/
3923	VMMR3DECL(int) PGMR3DumpHierarchyGC(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCPHYS PhysSearch)
3924	{
3925	bool fLongMode = false;
3926	const unsigned cch = fLongMode ? 16 : 8; NOREF(cch);
3927	PX86PD pPD = 0;
3928
3929	int rc = PGM_GCPHYS_2_PTR(pVM, cr3 & X86_CR3_PAGE_MASK, &pPD);
3930	if (VBOX_FAILURE(rc) \|\| !pPD)
3931	{
3932	Log(("Page directory at %#x was not found in the page pool!\n", cr3 & X86_CR3_PAGE_MASK));
3933	return VERR_INVALID_PARAMETER;
3934	}
3935
3936	Log(("cr3=%08x cr4=%08x%s\n"
3937	"%-*s P - Present\n"
3938	"%-*s \| R/W - Read (0) / Write (1)\n"
3939	"%-*s \| \| U/S - User (1) / Supervisor (0)\n"
3940	"%-*s \| \| \| A - Accessed\n"
3941	"%-*s \| \| \| \| D - Dirty\n"
3942	"%-*s \| \| \| \| \| G - Global\n"
3943	"%-*s \| \| \| \| \| \| WT - Write thru\n"
3944	"%-*s \| \| \| \| \| \| \| CD - Cache disable\n"
3945	"%-*s \| \| \| \| \| \| \| \| AT - Attribute table (PAT)\n"
3946	"%-*s \| \| \| \| \| \| \| \| \| NX - No execute (K8)\n"
3947	"%-*s \| \| \| \| \| \| \| \| \| \| 4K/4M/2M - Page size.\n"
3948	"%-*s \| \| \| \| \| \| \| \| \| \| \| AVL - a=allocated; m=mapping; d=track dirty;\n"
3949	"%-*s \| \| \| \| \| \| \| \| \| \| \| \| p=permanent; v=validated;\n"
3950	"%-*s Level \| \| \| \| \| \| \| \| \| \| \| \| Page\n"
3951	/* xxxx n **** P R S A D G WT CD AT NX 4M AVL xxxxxxxxxxxxx
3952	- W U - - - -- -- -- -- -- 010 */
3953	, cr3, cr4, fLongMode ? " Long Mode" : "",
3954	cch, "", cch, "", cch, "", cch, "", cch, "", cch, "", cch, "",
3955	cch, "", cch, "", cch, "", cch, "", cch, "", cch, "", cch, "Address"));
3956
3957	for (unsigned i = 0; i < RT_ELEMENTS(pPD->a); i++)
3958	{
3959	X86PDE Pde = pPD->a[i];
3960	if (Pde.n.u1Present)
3961	{
3962	const uint32_t u32Address = i << X86_PD_SHIFT;
3963
3964	if ((cr4 & X86_CR4_PSE) && Pde.b.u1Size)
3965	Log(( /P R S A D G WT CD AT NX 4M a m d /
3966	"%08x 0 \| P %c %c %c %c %c %s %s %s .. 4M %c%c%c %08x\n",
3967	u32Address,
3968	Pde.b.u1Write ? 'W' : 'R',
3969	Pde.b.u1User ? 'U' : 'S',
3970	Pde.b.u1Accessed ? 'A' : '-',
3971	Pde.b.u1Dirty ? 'D' : '-',
3972	Pde.b.u1Global ? 'G' : '-',
3973	Pde.b.u1WriteThru ? "WT" : "--",
3974	Pde.b.u1CacheDisable? "CD" : "--",
3975	Pde.b.u1PAT ? "AT" : "--",
3976	Pde.u & RT_BIT(9) ? '1' : '0',
3977	Pde.u & RT_BIT(10) ? '1' : '0',
3978	Pde.u & RT_BIT(11) ? '1' : '0',
3979	pgmGstGet4MBPhysPage(&pVM->pgm.s, Pde)));
3980	/** @todo PhysSearch */
3981	else
3982	{
3983	Log(( /P R S A D G WT CD AT NX 4M a m d /
3984	"%08x 0 \| P %c %c %c %c %c %s %s .. .. 4K %c%c%c %08x\n",
3985	u32Address,
3986	Pde.n.u1Write ? 'W' : 'R',
3987	Pde.n.u1User ? 'U' : 'S',
3988	Pde.n.u1Accessed ? 'A' : '-',
3989	Pde.n.u1Reserved0 ? '?' : '.', /* ignored */
3990	Pde.n.u1Reserved1 ? '?' : '.', /* ignored */
3991	Pde.n.u1WriteThru ? "WT" : "--",
3992	Pde.n.u1CacheDisable? "CD" : "--",
3993	Pde.u & RT_BIT(9) ? '1' : '0',
3994	Pde.u & RT_BIT(10) ? '1' : '0',
3995	Pde.u & RT_BIT(11) ? '1' : '0',
3996	Pde.u & X86_PDE_PG_MASK));
3997	////if (cMaxDepth >= 1)
3998	{
3999	/** @todo what about using the page pool for mapping PTs? */
4000	RTGCPHYS GCPhys = Pde.u & X86_PDE_PG_MASK;
4001	PX86PT pPT = NULL;
4002
4003	rc = PGM_GCPHYS_2_PTR(pVM, GCPhys, &pPT);
4004
4005	int rc2 = VERR_INVALID_PARAMETER;
4006	if (pPT)
4007	rc2 = pgmR3DumpHierarchyGC32BitPT(pVM, pPT, u32Address, PhysSearch);
4008	else
4009	Log(("%08x error! Page table at %#x was not found in the page pool!\n", u32Address, GCPhys));
4010	if (rc2 < rc && VBOX_SUCCESS(rc))
4011	rc = rc2;
4012	}
4013	}
4014	}
4015	}
4016
4017	return rc;
4018	}
4019
4020
4021	/**
4022	* Dumps a page table hierarchy use only physical addresses and cr4/lm flags.
4023	*
4024	* @returns VBox status code (VINF_SUCCESS).
4025	* @param pVM The VM handle.
4026	* @param cr3 The root of the hierarchy.
4027	* @param cr4 The cr4, only PAE and PSE is currently used.
4028	* @param fLongMode Set if long mode, false if not long mode.
4029	* @param cMaxDepth Number of levels to dump.
4030	* @param pHlp Pointer to the output functions.
4031	*/
4032	VMMR3DECL(int) PGMR3DumpHierarchyHC(PVM pVM, uint64_t cr3, uint64_t cr4, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
4033	{
4034	if (!pHlp)
4035	pHlp = DBGFR3InfoLogHlp();
4036	if (!cMaxDepth)
4037	return VINF_SUCCESS;
4038	const unsigned cch = fLongMode ? 16 : 8;
4039	pHlp->pfnPrintf(pHlp,
4040	"cr3=%08x cr4=%08x%s\n"
4041	"%-*s P - Present\n"
4042	"%-*s \| R/W - Read (0) / Write (1)\n"
4043	"%-*s \| \| U/S - User (1) / Supervisor (0)\n"
4044	"%-*s \| \| \| A - Accessed\n"
4045	"%-*s \| \| \| \| D - Dirty\n"
4046	"%-*s \| \| \| \| \| G - Global\n"
4047	"%-*s \| \| \| \| \| \| WT - Write thru\n"
4048	"%-*s \| \| \| \| \| \| \| CD - Cache disable\n"
4049	"%-*s \| \| \| \| \| \| \| \| AT - Attribute table (PAT)\n"
4050	"%-*s \| \| \| \| \| \| \| \| \| NX - No execute (K8)\n"
4051	"%-*s \| \| \| \| \| \| \| \| \| \| 4K/4M/2M - Page size.\n"
4052	"%-*s \| \| \| \| \| \| \| \| \| \| \| AVL - a=allocated; m=mapping; d=track dirty;\n"
4053	"%-*s \| \| \| \| \| \| \| \| \| \| \| \| p=permanent; v=validated;\n"
4054	"%-*s Level \| \| \| \| \| \| \| \| \| \| \| \| Page\n"
4055	/* xxxx n **** P R S A D G WT CD AT NX 4M AVL xxxxxxxxxxxxx
4056	- W U - - - -- -- -- -- -- 010 */
4057	, cr3, cr4, fLongMode ? " Long Mode" : "",
4058	cch, "", cch, "", cch, "", cch, "", cch, "", cch, "", cch, "",
4059	cch, "", cch, "", cch, "", cch, "", cch, "", cch, "", cch, "Address");
4060	if (cr4 & X86_CR4_PAE)
4061	{
4062	if (fLongMode)
4063	return pgmR3DumpHierarchyHcPaePML4(pVM, cr3 & X86_CR3_PAGE_MASK, cr4, cMaxDepth, pHlp);
4064	return pgmR3DumpHierarchyHCPaePDPT(pVM, cr3 & X86_CR3_PAE_PAGE_MASK, 0, cr4, false, cMaxDepth, pHlp);
4065	}
4066	return pgmR3DumpHierarchyHC32BitPD(pVM, cr3 & X86_CR3_PAGE_MASK, cr4, cMaxDepth, pHlp);
4067	}
4068
4069
4070
4071	#ifdef VBOX_WITH_DEBUGGER
4072	/**
4073	* The '.pgmram' command.
4074	*
4075	* @returns VBox status.
4076	* @param pCmd Pointer to the command descriptor (as registered).
4077	* @param pCmdHlp Pointer to command helper functions.
4078	* @param pVM Pointer to the current VM (if any).
4079	* @param paArgs Pointer to (readonly) array of arguments.
4080	* @param cArgs Number of arguments in the array.
4081	*/
4082	static DECLCALLBACK(int) pgmR3CmdRam(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4083	{
4084	/*
4085	* Validate input.
4086	*/
4087	if (!pVM)
4088	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4089	if (!pVM->pgm.s.pRamRangesRC)
4090	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Sorry, no Ram is registered.\n");
4091
4092	/*
4093	* Dump the ranges.
4094	*/
4095	int rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL, "From - To (incl) pvHC\n");
4096	PPGMRAMRANGE pRam;
4097	for (pRam = pVM->pgm.s.pRamRangesR3; pRam; pRam = pRam->pNextR3)
4098	{
4099	rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL,
4100	"%RGp - %RGp %p\n",
4101	pRam->GCPhys, pRam->GCPhysLast, pRam->pvR3);
4102	if (VBOX_FAILURE(rc))
4103	return rc;
4104	}
4105
4106	return VINF_SUCCESS;
4107	}
4108
4109
4110	/**
4111	* The '.pgmmap' command.
4112	*
4113	* @returns VBox status.
4114	* @param pCmd Pointer to the command descriptor (as registered).
4115	* @param pCmdHlp Pointer to command helper functions.
4116	* @param pVM Pointer to the current VM (if any).
4117	* @param paArgs Pointer to (readonly) array of arguments.
4118	* @param cArgs Number of arguments in the array.
4119	*/
4120	static DECLCALLBACK(int) pgmR3CmdMap(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4121	{
4122	/*
4123	* Validate input.
4124	*/
4125	if (!pVM)
4126	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4127	if (!pVM->pgm.s.pMappingsR3)
4128	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Sorry, no mappings are registered.\n");
4129
4130	/*
4131	* Print message about the fixedness of the mappings.
4132	*/
4133	int rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL, pVM->pgm.s.fMappingsFixed ? "The mappings are FIXED.\n" : "The mappings are FLOATING.\n");
4134	if (VBOX_FAILURE(rc))
4135	return rc;
4136
4137	/*
4138	* Dump the ranges.
4139	*/
4140	PPGMMAPPING pCur;
4141	for (pCur = pVM->pgm.s.pMappingsR3; pCur; pCur = pCur->pNextR3)
4142	{
4143	rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL,
4144	"%08x - %08x %s\n",
4145	pCur->GCPtr, pCur->GCPtrLast, pCur->pszDesc);
4146	if (VBOX_FAILURE(rc))
4147	return rc;
4148	}
4149
4150	return VINF_SUCCESS;
4151	}
4152
4153
4154	/**
4155	* The '.pgmsync' command.
4156	*
4157	* @returns VBox status.
4158	* @param pCmd Pointer to the command descriptor (as registered).
4159	* @param pCmdHlp Pointer to command helper functions.
4160	* @param pVM Pointer to the current VM (if any).
4161	* @param paArgs Pointer to (readonly) array of arguments.
4162	* @param cArgs Number of arguments in the array.
4163	*/
4164	static DECLCALLBACK(int) pgmR3CmdSync(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4165	{
4166	/*
4167	* Validate input.
4168	*/
4169	if (!pVM)
4170	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4171
4172	/*
4173	* Force page directory sync.
4174	*/
4175	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
4176
4177	int rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Forcing page directory sync.\n");
4178	if (VBOX_FAILURE(rc))
4179	return rc;
4180
4181	return VINF_SUCCESS;
4182	}
4183
4184
4185	#ifdef VBOX_STRICT
4186	/**
4187	* The '.pgmassertcr3' command.
4188	*
4189	* @returns VBox status.
4190	* @param pCmd Pointer to the command descriptor (as registered).
4191	* @param pCmdHlp Pointer to command helper functions.
4192	* @param pVM Pointer to the current VM (if any).
4193	* @param paArgs Pointer to (readonly) array of arguments.
4194	* @param cArgs Number of arguments in the array.
4195	*/
4196	static DECLCALLBACK(int) pgmR3CmdAssertCR3(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4197	{
4198	/*
4199	* Validate input.
4200	*/
4201	if (!pVM)
4202	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4203
4204	int rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Checking shadow CR3 page tables for consistency.\n");
4205	if (VBOX_FAILURE(rc))
4206	return rc;
4207
4208	PGMAssertCR3(pVM, CPUMGetGuestCR3(pVM), CPUMGetGuestCR4(pVM));
4209
4210	return VINF_SUCCESS;
4211	}
4212	#endif
4213
4214	/**
4215	* The '.pgmsyncalways' command.
4216	*
4217	* @returns VBox status.
4218	* @param pCmd Pointer to the command descriptor (as registered).
4219	* @param pCmdHlp Pointer to command helper functions.
4220	* @param pVM Pointer to the current VM (if any).
4221	* @param paArgs Pointer to (readonly) array of arguments.
4222	* @param cArgs Number of arguments in the array.
4223	*/
4224	static DECLCALLBACK(int) pgmR3CmdSyncAlways(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4225	{
4226	/*
4227	* Validate input.
4228	*/
4229	if (!pVM)
4230	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4231
4232	/*
4233	* Force page directory sync.
4234	*/
4235	if (pVM->pgm.s.fSyncFlags & PGM_SYNC_ALWAYS)
4236	{
4237	ASMAtomicAndU32(&pVM->pgm.s.fSyncFlags, ~PGM_SYNC_ALWAYS);
4238	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Disabled permanent forced page directory syncing.\n");
4239	}
4240	else
4241	{
4242	ASMAtomicOrU32(&pVM->pgm.s.fSyncFlags, PGM_SYNC_ALWAYS);
4243	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
4244	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Enabled permanent forced page directory syncing.\n");
4245	}
4246	}
4247
4248	#endif
4249
4250	/**
4251	* pvUser argument of the pgmR3CheckIntegrity*Node callbacks.
4252	*/
4253	typedef struct PGMCHECKINTARGS
4254	{
4255	bool fLeftToRight; /*< true: left-to-right; false: right-to-left. /
4256	PPGMPHYSHANDLER pPrevPhys;
4257	PPGMVIRTHANDLER pPrevVirt;
4258	PPGMPHYS2VIRTHANDLER pPrevPhys2Virt;
4259	PVM pVM;
4260	} PGMCHECKINTARGS, *PPGMCHECKINTARGS;
4261
4262	/**
4263	* Validate a node in the physical handler tree.
4264	*
4265	* @returns 0 on if ok, other wise 1.
4266	* @param pNode The handler node.
4267	* @param pvUser pVM.
4268	*/
4269	static DECLCALLBACK(int) pgmR3CheckIntegrityPhysHandlerNode(PAVLROGCPHYSNODECORE pNode, void *pvUser)
4270	{
4271	PPGMCHECKINTARGS pArgs = (PPGMCHECKINTARGS)pvUser;
4272	PPGMPHYSHANDLER pCur = (PPGMPHYSHANDLER)pNode;
4273	AssertReleaseReturn(!((uintptr_t)pCur & 7), 1);
4274	AssertReleaseMsg(pCur->Core.Key <= pCur->Core.KeyLast,("pCur=%p %VGp-%VGp %s\n", pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
4275	AssertReleaseMsg( !pArgs->pPrevPhys
4276	\|\| (pArgs->fLeftToRight ? pArgs->pPrevPhys->Core.KeyLast < pCur->Core.Key : pArgs->pPrevPhys->Core.KeyLast > pCur->Core.Key),
4277	("pPrevPhys=%p %VGp-%VGp %s\n"
4278	" pCur=%p %VGp-%VGp %s\n",
4279	pArgs->pPrevPhys, pArgs->pPrevPhys->Core.Key, pArgs->pPrevPhys->Core.KeyLast, pArgs->pPrevPhys->pszDesc,
4280	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
4281	pArgs->pPrevPhys = pCur;
4282	return 0;
4283	}
4284
4285
4286	/**
4287	* Validate a node in the virtual handler tree.
4288	*
4289	* @returns 0 on if ok, other wise 1.
4290	* @param pNode The handler node.
4291	* @param pvUser pVM.
4292	*/
4293	static DECLCALLBACK(int) pgmR3CheckIntegrityVirtHandlerNode(PAVLROGCPTRNODECORE pNode, void *pvUser)
4294	{
4295	PPGMCHECKINTARGS pArgs = (PPGMCHECKINTARGS)pvUser;
4296	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)pNode;
4297	AssertReleaseReturn(!((uintptr_t)pCur & 7), 1);
4298	AssertReleaseMsg(pCur->Core.Key <= pCur->Core.KeyLast,("pCur=%p %VGv-%VGv %s\n", pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
4299	AssertReleaseMsg( !pArgs->pPrevVirt
4300	\|\| (pArgs->fLeftToRight ? pArgs->pPrevVirt->Core.KeyLast < pCur->Core.Key : pArgs->pPrevVirt->Core.KeyLast > pCur->Core.Key),
4301	("pPrevVirt=%p %VGv-%VGv %s\n"
4302	" pCur=%p %VGv-%VGv %s\n",
4303	pArgs->pPrevVirt, pArgs->pPrevVirt->Core.Key, pArgs->pPrevVirt->Core.KeyLast, pArgs->pPrevVirt->pszDesc,
4304	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
4305	for (unsigned iPage = 0; iPage < pCur->cPages; iPage++)
4306	{
4307	AssertReleaseMsg(pCur->aPhysToVirt[iPage].offVirtHandler == -RT_OFFSETOF(PGMVIRTHANDLER, aPhysToVirt[iPage]),
4308	("pCur=%p %VGv-%VGv %s\n"
4309	"iPage=%d offVirtHandle=%#x expected %#x\n",
4310	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc,
4311	iPage, pCur->aPhysToVirt[iPage].offVirtHandler, -RT_OFFSETOF(PGMVIRTHANDLER, aPhysToVirt[iPage])));
4312	}
4313	pArgs->pPrevVirt = pCur;
4314	return 0;
4315	}
4316
4317
4318	/**
4319	* Validate a node in the virtual handler tree.
4320	*
4321	* @returns 0 on if ok, other wise 1.
4322	* @param pNode The handler node.
4323	* @param pvUser pVM.
4324	*/
4325	static DECLCALLBACK(int) pgmR3CheckIntegrityPhysToVirtHandlerNode(PAVLROGCPHYSNODECORE pNode, void *pvUser)
4326	{
4327	PPGMCHECKINTARGS pArgs = (PPGMCHECKINTARGS)pvUser;
4328	PPGMPHYS2VIRTHANDLER pCur = (PPGMPHYS2VIRTHANDLER)pNode;
4329	AssertReleaseMsgReturn(!((uintptr_t)pCur & 3), ("\n"), 1);
4330	AssertReleaseMsgReturn(!(pCur->offVirtHandler & 3), ("\n"), 1);
4331	AssertReleaseMsg(pCur->Core.Key <= pCur->Core.KeyLast,("pCur=%p %VGp-%VGp\n", pCur, pCur->Core.Key, pCur->Core.KeyLast));
4332	AssertReleaseMsg( !pArgs->pPrevPhys2Virt
4333	\|\| (pArgs->fLeftToRight ? pArgs->pPrevPhys2Virt->Core.KeyLast < pCur->Core.Key : pArgs->pPrevPhys2Virt->Core.KeyLast > pCur->Core.Key),
4334	("pPrevPhys2Virt=%p %VGp-%VGp\n"
4335	" pCur=%p %VGp-%VGp\n",
4336	pArgs->pPrevPhys2Virt, pArgs->pPrevPhys2Virt->Core.Key, pArgs->pPrevPhys2Virt->Core.KeyLast,
4337	pCur, pCur->Core.Key, pCur->Core.KeyLast));
4338	AssertReleaseMsg( !pArgs->pPrevPhys2Virt
4339	\|\| (pArgs->fLeftToRight ? pArgs->pPrevPhys2Virt->Core.KeyLast < pCur->Core.Key : pArgs->pPrevPhys2Virt->Core.KeyLast > pCur->Core.Key),
4340	("pPrevPhys2Virt=%p %VGp-%VGp\n"
4341	" pCur=%p %VGp-%VGp\n",
4342	pArgs->pPrevPhys2Virt, pArgs->pPrevPhys2Virt->Core.Key, pArgs->pPrevPhys2Virt->Core.KeyLast,
4343	pCur, pCur->Core.Key, pCur->Core.KeyLast));
4344	AssertReleaseMsg((pCur->offNextAlias & (PGMPHYS2VIRTHANDLER_IN_TREE \| PGMPHYS2VIRTHANDLER_IS_HEAD)) == (PGMPHYS2VIRTHANDLER_IN_TREE \| PGMPHYS2VIRTHANDLER_IS_HEAD),
4345	("pCur=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4346	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias));
4347	if (pCur->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK)
4348	{
4349	PPGMPHYS2VIRTHANDLER pCur2 = pCur;
4350	for (;;)
4351	{
4352	pCur2 = (PPGMPHYS2VIRTHANDLER)((intptr_t)pCur + (pCur->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK));
4353	AssertReleaseMsg(pCur2 != pCur,
4354	(" pCur=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4355	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias));
4356	AssertReleaseMsg((pCur2->offNextAlias & (PGMPHYS2VIRTHANDLER_IN_TREE \| PGMPHYS2VIRTHANDLER_IS_HEAD)) == PGMPHYS2VIRTHANDLER_IN_TREE,
4357	(" pCur=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
4358	"pCur2=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4359	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias,
4360	pCur2, pCur2->Core.Key, pCur2->Core.KeyLast, pCur2->offVirtHandler, pCur2->offNextAlias));
4361	AssertReleaseMsg((pCur2->Core.Key ^ pCur->Core.Key) < PAGE_SIZE,
4362	(" pCur=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
4363	"pCur2=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4364	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias,
4365	pCur2, pCur2->Core.Key, pCur2->Core.KeyLast, pCur2->offVirtHandler, pCur2->offNextAlias));
4366	AssertReleaseMsg((pCur2->Core.KeyLast ^ pCur->Core.KeyLast) < PAGE_SIZE,
4367	(" pCur=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
4368	"pCur2=%p:{.Core.Key=%VGp, .Core.KeyLast=%VGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4369	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias,
4370	pCur2, pCur2->Core.Key, pCur2->Core.KeyLast, pCur2->offVirtHandler, pCur2->offNextAlias));
4371	if (!(pCur2->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK))
4372	break;
4373	}
4374	}
4375
4376	pArgs->pPrevPhys2Virt = pCur;
4377	return 0;
4378	}
4379
4380
4381	/**
4382	* Perform an integrity check on the PGM component.
4383	*
4384	* @returns VINF_SUCCESS if everything is fine.
4385	* @returns VBox error status after asserting on integrity breach.
4386	* @param pVM The VM handle.
4387	*/
4388	VMMR3DECL(int) PGMR3CheckIntegrity(PVM pVM)
4389	{
4390	AssertReleaseReturn(pVM->pgm.s.offVM, VERR_INTERNAL_ERROR);
4391
4392	/*
4393	* Check the trees.
4394	*/
4395	int cErrors = 0;
4396	const static PGMCHECKINTARGS s_LeftToRight = { true, NULL, NULL, NULL, pVM };
4397	const static PGMCHECKINTARGS s_RightToLeft = { false, NULL, NULL, NULL, pVM };
4398	PGMCHECKINTARGS Args = s_LeftToRight;
4399	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysHandlers, true, pgmR3CheckIntegrityPhysHandlerNode, &Args);
4400	Args = s_RightToLeft;
4401	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysHandlers, false, pgmR3CheckIntegrityPhysHandlerNode, &Args);
4402	Args = s_LeftToRight;
4403	cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesR3->VirtHandlers, true, pgmR3CheckIntegrityVirtHandlerNode, &Args);
4404	Args = s_RightToLeft;
4405	cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesR3->VirtHandlers, false, pgmR3CheckIntegrityVirtHandlerNode, &Args);
4406	Args = s_LeftToRight;
4407	cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesR3->HyperVirtHandlers, true, pgmR3CheckIntegrityVirtHandlerNode, &Args);
4408	Args = s_RightToLeft;
4409	cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesR3->HyperVirtHandlers, false, pgmR3CheckIntegrityVirtHandlerNode, &Args);
4410	Args = s_LeftToRight;
4411	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysToVirtHandlers, true, pgmR3CheckIntegrityPhysToVirtHandlerNode, &Args);
4412	Args = s_RightToLeft;
4413	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysToVirtHandlers, false, pgmR3CheckIntegrityPhysToVirtHandlerNode, &Args);
4414
4415	return !cErrors ? VINF_SUCCESS : VERR_INTERNAL_ERROR;
4416	}
4417
4418
4419	/**
4420	* Inform PGM if we want all mappings to be put into the shadow page table. (necessary for e.g. VMX)
4421	*
4422	* @returns VBox status code.
4423	* @param pVM VM handle.
4424	* @param fEnable Enable or disable shadow mappings
4425	*/
4426	VMMR3DECL(int) PGMR3ChangeShwPDMappings(PVM pVM, bool fEnable)
4427	{
4428	pVM->pgm.s.fDisableMappings = !fEnable;
4429
4430	uint32_t cb;
4431	int rc = PGMR3MappingsSize(pVM, &cb);
4432	AssertRCReturn(rc, rc);
4433
4434	/* Pretend the mappings are now fixed; to force a refresh of the reserved PDEs. */
4435	rc = PGMR3MappingsFix(pVM, MM_HYPER_AREA_ADDRESS, cb);
4436	AssertRCReturn(rc, rc);
4437
4438	return VINF_SUCCESS;
4439	}

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source: vbox/trunk/src/VBox/VMM/PGM.cpp@ 13187

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