PGM.cpp@ 14038

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1	/* $Id: PGM.cpp 14038 2008-11-10 18:23:15Z vboxsync $ */
2	/** @file
3	* PGM - Page Manager and Monitor. (Mixing stuff here, not good?)
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22
23	/** @page pg_pgm PGM - The Page Manager and Monitor
24	*
25	* @see grp_pgm,
26	* @ref pg_pgm_pool,
27	* @ref pg_pgm_phys.
28	*
29	*
30	* @section sec_pgm_modes Paging Modes
31	*
32	* There are three memory contexts: Host Context (HC), Guest Context (GC)
33	* and intermediate context. When talking about paging HC can also be refered to
34	* as "host paging", and GC refered to as "shadow paging".
35	*
36	* We define three basic paging modes: 32-bit, PAE and AMD64. The host paging mode
37	* is defined by the host operating system. The mode used in the shadow paging mode
38	* depends on the host paging mode and what the mode the guest is currently in. The
39	* following relation between the two is defined:
40	*
41	* @verbatim
42	Host > 32-bit \| PAE \| AMD64 \|
43	Guest \| \| \| \|
44	==v================================
45	32-bit 32-bit PAE PAE
46	-------\|--------\|--------\|--------\|
47	PAE PAE PAE PAE
48	-------\|--------\|--------\|--------\|
49	AMD64 AMD64 AMD64 AMD64
50	-------\|--------\|--------\|--------\| @endverbatim
51	*
52	* All configuration except those in the diagonal (upper left) are expected to
53	* require special effort from the switcher (i.e. a bit slower).
54	*
55	*
56	*
57	*
58	* @section sec_pgm_shw The Shadow Memory Context
59	*
60	*
61	* [..]
62	*
63	* Because of guest context mappings requires PDPT and PML4 entries to allow
64	* writing on AMD64, the two upper levels will have fixed flags whatever the
65	* guest is thinking of using there. So, when shadowing the PD level we will
66	* calculate the effective flags of PD and all the higher levels. In legacy
67	* PAE mode this only applies to the PWT and PCD bits (the rest are
68	* ignored/reserved/MBZ). We will ignore those bits for the present.
69	*
70	*
71	*
72	* @section sec_pgm_int The Intermediate Memory Context
73	*
74	* The world switch goes thru an intermediate memory context which purpose it is
75	* to provide different mappings of the switcher code. All guest mappings are also
76	* present in this context.
77	*
78	* The switcher code is mapped at the same location as on the host, at an
79	* identity mapped location (physical equals virtual address), and at the
80	* hypervisor location.
81	*
82	* PGM maintain page tables for 32-bit, PAE and AMD64 paging modes. This
83	* simplifies switching guest CPU mode and consistency at the cost of more
84	* code to do the work. All memory use for those page tables is located below
85	* 4GB (this includes page tables for guest context mappings).
86	*
87	*
88	* @subsection subsec_pgm_int_gc Guest Context Mappings
89	*
90	* During assignment and relocation of a guest context mapping the intermediate
91	* memory context is used to verify the new location.
92	*
93	* Guest context mappings are currently restricted to below 4GB, for reasons
94	* of simplicity. This may change when we implement AMD64 support.
95	*
96	*
97	*
98	*
99	* @section sec_pgm_misc Misc
100	*
101	* @subsection subsec_pgm_misc_diff Differences Between Legacy PAE and Long Mode PAE
102	*
103	* The differences between legacy PAE and long mode PAE are:
104	* -# PDPE bits 1, 2, 5 and 6 are defined differently. In leagcy mode they are
105	* all marked down as must-be-zero, while in long mode 1, 2 and 5 have the
106	* usual meanings while 6 is ignored (AMD). This means that upon switching to
107	* legacy PAE mode we'll have to clear these bits and when going to long mode
108	* they must be set. This applies to both intermediate and shadow contexts,
109	* however we don't need to do it for the intermediate one since we're
110	* executing with CR0.WP at that time.
111	* -# CR3 allows a 32-byte aligned address in legacy mode, while in long mode
112	* a page aligned one is required.
113	*
114	*
115	* @section sec_pgm_handlers Access Handlers
116	*
117	* Placeholder.
118	*
119	*
120	* @subsection sec_pgm_handlers_virt Virtual Access Handlers
121	*
122	* Placeholder.
123	*
124	*
125	* @subsection sec_pgm_handlers_virt Virtual Access Handlers
126	*
127	* We currently implement three types of virtual access handlers: ALL, WRITE
128	* and HYPERVISOR (WRITE). See PGMVIRTHANDLERTYPE for some more details.
129	*
130	* The HYPERVISOR access handlers is kept in a separate tree since it doesn't apply
131	* to physical pages (PGMTREES::HyperVirtHandlers) and only needs to be consulted in
132	* a special \#PF case. The ALL and WRITE are in the PGMTREES::VirtHandlers tree, the
133	* rest of this section is going to be about these handlers.
134	*
135	* We'll go thru the life cycle of a handler and try make sense of it all, don't know
136	* how successfull this is gonna be...
137	*
138	* 1. A handler is registered thru the PGMR3HandlerVirtualRegister and
139	* PGMHandlerVirtualRegisterEx APIs. We check for conflicting virtual handlers
140	* and create a new node that is inserted into the AVL tree (range key). Then
141	* a full PGM resync is flagged (clear pool, sync cr3, update virtual bit of PGMPAGE).
142	*
143	* 2. The following PGMSyncCR3/SyncCR3 operation will first make invoke HandlerVirtualUpdate.
144	*
145	* 2a. HandlerVirtualUpdate will will lookup all the pages covered by virtual handlers
146	* via the current guest CR3 and update the physical page -> virtual handler
147	* translation. Needless to say, this doesn't exactly scale very well. If any changes
148	* are detected, it will flag a virtual bit update just like we did on registration.
149	* PGMPHYS pages with changes will have their virtual handler state reset to NONE.
150	*
151	* 2b. The virtual bit update process will iterate all the pages covered by all the
152	* virtual handlers and update the PGMPAGE virtual handler state to the max of all
153	* virtual handlers on that page.
154	*
155	* 2c. Back in SyncCR3 we will now flush the entire shadow page cache to make sure
156	* we don't miss any alias mappings of the monitored pages.
157	*
158	* 2d. SyncCR3 will then proceed with syncing the CR3 table.
159	*
160	* 3. \#PF(np,read) on a page in the range. This will cause it to be synced
161	* read-only and resumed if it's a WRITE handler. If it's an ALL handler we
162	* will call the handlers like in the next step. If the physical mapping has
163	* changed we will - some time in the future - perform a handler callback
164	* (optional) and update the physical -> virtual handler cache.
165	*
166	* 4. \#PF(,write) on a page in the range. This will cause the handler to
167	* be invoked.
168	*
169	* 5. The guest invalidates the page and changes the physical backing or
170	* unmaps it. This should cause the invalidation callback to be invoked
171	* (it might not yet be 100% perfect). Exactly what happens next... is
172	* this where we mess up and end up out of sync for a while?
173	*
174	* 6. The handler is deregistered by the client via PGMHandlerVirtualDeregister.
175	* We will then set all PGMPAGEs in the physical -> virtual handler cache for
176	* this handler to NONE and trigger a full PGM resync (basically the same
177	* as int step 1). Which means 2 is executed again.
178	*
179	*
180	* @subsubsection sub_sec_pgm_handler_virt_todo TODOs
181	*
182	* There is a bunch of things that needs to be done to make the virtual handlers
183	* work 100% correctly and work more efficiently.
184	*
185	* The first bit hasn't been implemented yet because it's going to slow the
186	* whole mess down even more, and besides it seems to be working reliably for
187	* our current uses. OTOH, some of the optimizations might end up more or less
188	* implementing the missing bits, so we'll see.
189	*
190	* On the optimization side, the first thing to do is to try avoid unnecessary
191	* cache flushing. Then try team up with the shadowing code to track changes
192	* in mappings by means of access to them (shadow in), updates to shadows pages,
193	* invlpg, and shadow PT discarding (perhaps).
194	*
195	* Some idea that have popped up for optimization for current and new features:
196	* - bitmap indicating where there are virtual handlers installed.
197	* (4KB => 220 pages, page 212 => covers 32-bit address space 1:1!)
198	* - Further optimize this by min/max (needs min/max avl getters).
199	* - Shadow page table entry bit (if any left)?
200	*
201	*/
202
203
204	/** @page pg_pgm_phys PGM Physical Guest Memory Management
205	*
206	*
207	* Objectives:
208	* - Guest RAM over-commitment using memory ballooning,
209	* zero pages and general page sharing.
210	* - Moving or mirroring a VM onto a different physical machine.
211	*
212	*
213	* @subsection subsec_pgmPhys_Definitions Definitions
214	*
215	* Allocation chunk - A RTR0MemObjAllocPhysNC object and the tracking
216	* machinery assoicated with it.
217	*
218	*
219	*
220	*
221	* @subsection subsec_pgmPhys_AllocPage Allocating a page.
222	*
223	* Initially we map all guest memory to the (per VM) zero page, which
224	* means that none of the read functions will cause pages to be allocated.
225	*
226	* Exception, access bit in page tables that have been shared. This must
227	* be handled, but we must also make sure PGMGst*Modify doesn't make
228	* unnecessary modifications.
229	*
230	* Allocation points:
231	* - PGMPhysSimpleWriteGCPhys and PGMPhysWrite.
232	* - Replacing a zero page mapping at \#PF.
233	* - Replacing a shared page mapping at \#PF.
234	* - ROM registration (currently MMR3RomRegister).
235	* - VM restore (pgmR3Load).
236	*
237	* For the first three it would make sense to keep a few pages handy
238	* until we've reached the max memory commitment for the VM.
239	*
240	* For the ROM registration, we know exactly how many pages we need
241	* and will request these from ring-0. For restore, we will save
242	* the number of non-zero pages in the saved state and allocate
243	* them up front. This would allow the ring-0 component to refuse
244	* the request if the isn't sufficient memory available for VM use.
245	*
246	* Btw. for both ROM and restore allocations we won't be requiring
247	* zeroed pages as they are going to be filled instantly.
248	*
249	*
250	* @subsection subsec_pgmPhys_FreePage Freeing a page
251	*
252	* There are a few points where a page can be freed:
253	* - After being replaced by the zero page.
254	* - After being replaced by a shared page.
255	* - After being ballooned by the guest additions.
256	* - At reset.
257	* - At restore.
258	*
259	* When freeing one or more pages they will be returned to the ring-0
260	* component and replaced by the zero page.
261	*
262	* The reasoning for clearing out all the pages on reset is that it will
263	* return us to the exact same state as on power on, and may thereby help
264	* us reduce the memory load on the system. Further it might have a
265	* (temporary) positive influence on memory fragmentation (@see subsec_pgmPhys_Fragmentation).
266	*
267	* On restore, as mention under the allocation topic, pages should be
268	* freed / allocated depending on how many is actually required by the
269	* new VM state. The simplest approach is to do like on reset, and free
270	* all non-ROM pages and then allocate what we need.
271	*
272	* A measure to prevent some fragmentation, would be to let each allocation
273	* chunk have some affinity towards the VM having allocated the most pages
274	* from it. Also, try make sure to allocate from allocation chunks that
275	* are almost full. Admittedly, both these measures might work counter to
276	* our intentions and its probably not worth putting a lot of effort,
277	* cpu time or memory into this.
278	*
279	*
280	* @subsection subsec_pgmPhys_SharePage Sharing a page
281	*
282	* The basic idea is that there there will be a idle priority kernel
283	* thread walking the non-shared VM pages hashing them and looking for
284	* pages with the same checksum. If such pages are found, it will compare
285	* them byte-by-byte to see if they actually are identical. If found to be
286	* identical it will allocate a shared page, copy the content, check that
287	* the page didn't change while doing this, and finally request both the
288	* VMs to use the shared page instead. If the page is all zeros (special
289	* checksum and byte-by-byte check) it will request the VM that owns it
290	* to replace it with the zero page.
291	*
292	* To make this efficient, we will have to make sure not to try share a page
293	* that will change its contents soon. This part requires the most work.
294	* A simple idea would be to request the VM to write monitor the page for
295	* a while to make sure it isn't modified any time soon. Also, it may
296	* make sense to skip pages that are being write monitored since this
297	* information is readily available to the thread if it works on the
298	* per-VM guest memory structures (presently called PGMRAMRANGE).
299	*
300	*
301	* @subsection subsec_pgmPhys_Fragmentation Fragmentation Concerns and Counter Measures
302	*
303	* The pages are organized in allocation chunks in ring-0, this is a necessity
304	* if we wish to have an OS agnostic approach to this whole thing. (On Linux we
305	* could easily work on a page-by-page basis if we liked. Whether this is possible
306	* or efficient on NT I don't quite know.) Fragmentation within these chunks may
307	* become a problem as part of the idea here is that we wish to return memory to
308	* the host system.
309	*
310	* For instance, starting two VMs at the same time, they will both allocate the
311	* guest memory on-demand and if permitted their page allocations will be
312	* intermixed. Shut down one of the two VMs and it will be difficult to return
313	* any memory to the host system because the page allocation for the two VMs are
314	* mixed up in the same allocation chunks.
315	*
316	* To further complicate matters, when pages are freed because they have been
317	* ballooned or become shared/zero the whole idea is that the page is supposed
318	* to be reused by another VM or returned to the host system. This will cause
319	* allocation chunks to contain pages belonging to different VMs and prevent
320	* returning memory to the host when one of those VM shuts down.
321	*
322	* The only way to really deal with this problem is to move pages. This can
323	* either be done at VM shutdown and or by the idle priority worker thread
324	* that will be responsible for finding sharable/zero pages. The mechanisms
325	* involved for coercing a VM to move a page (or to do it for it) will be
326	* the same as when telling it to share/zero a page.
327	*
328	*
329	* @subsection subsec_pgmPhys_Tracking Tracking Structures And Their Cost
330	*
331	* There's a difficult balance between keeping the per-page tracking structures
332	* (global and guest page) easy to use and keeping them from eating too much
333	* memory. We have limited virtual memory resources available when operating in
334	* 32-bit kernel space (on 64-bit there'll it's quite a different story). The
335	* tracking structures will be attemted designed such that we can deal with up
336	* to 32GB of memory on a 32-bit system and essentially unlimited on 64-bit ones.
337	*
338	*
339	* @subsubsection subsubsec_pgmPhys_Tracking_Kernel Kernel Space
340	*
341	* @see pg_GMM
342	*
343	* @subsubsection subsubsec_pgmPhys_Tracking_PerVM Per-VM
344	*
345	* Fixed info is the physical address of the page (HCPhys) and the page id
346	* (described above). Theoretically we'll need 48(-12) bits for the HCPhys part.
347	* Today we've restricting ourselves to 40(-12) bits because this is the current
348	* restrictions of all AMD64 implementations (I think Barcelona will up this
349	* to 48(-12) bits, not that it really matters) and I needed the bits for
350	* tracking mappings of a page. 48-12 = 36. That leaves 28 bits, which means a
351	* decent range for the page id: 2^(28+12) = 1024TB.
352	*
353	* In additions to these, we'll have to keep maintaining the page flags as we
354	* currently do. Although it wouldn't harm to optimize these quite a bit, like
355	* for instance the ROM shouldn't depend on having a write handler installed
356	* in order for it to become read-only. A RO/RW bit should be considered so
357	* that the page syncing code doesn't have to mess about checking multiple
358	* flag combinations (ROM \|\| RW handler \|\| write monitored) in order to
359	* figure out how to setup a shadow PTE. But this of course, is second
360	* priority at present. Current this requires 12 bits, but could probably
361	* be optimized to ~8.
362	*
363	* Then there's the 24 bits used to track which shadow page tables are
364	* currently mapping a page for the purpose of speeding up physical
365	* access handlers, and thereby the page pool cache. More bit for this
366	* purpose wouldn't hurt IIRC.
367	*
368	* Then there is a new bit in which we need to record what kind of page
369	* this is, shared, zero, normal or write-monitored-normal. This'll
370	* require 2 bits. One bit might be needed for indicating whether a
371	* write monitored page has been written to. And yet another one or
372	* two for tracking migration status. 3-4 bits total then.
373	*
374	* Whatever is left will can be used to record the sharabilitiy of a
375	* page. The page checksum will not be stored in the per-VM table as
376	* the idle thread will not be permitted to do modifications to it.
377	* It will instead have to keep its own working set of potentially
378	* shareable pages and their check sums and stuff.
379	*
380	* For the present we'll keep the current packing of the
381	* PGMRAMRANGE::aHCPhys to keep the changes simple, only of course,
382	* we'll have to change it to a struct with a total of 128-bits at
383	* our disposal.
384	*
385	* The initial layout will be like this:
386	* @verbatim
387	RTHCPHYS HCPhys; The current stuff.
388	63:40 Current shadow PT tracking stuff.
389	39:12 The physical page frame number.
390	11:0 The current flags.
391	uint32_t u28PageId : 28; The page id.
392	uint32_t u2State : 2; The page state { zero, shared, normal, write monitored }.
393	uint32_t fWrittenTo : 1; Whether a write monitored page was written to.
394	uint32_t u1Reserved : 1; Reserved for later.
395	uint32_t u32Reserved; Reserved for later, mostly sharing stats.
396	@endverbatim
397	*
398	* The final layout will be something like this:
399	* @verbatim
400	RTHCPHYS HCPhys; The current stuff.
401	63:48 High page id (12+).
402	47:12 The physical page frame number.
403	11:0 Low page id.
404	uint32_t fReadOnly : 1; Whether it's readonly page (rom or monitored in some way).
405	uint32_t u3Type : 3; The page type {RESERVED, MMIO, MMIO2, ROM, shadowed ROM, RAM}.
406	uint32_t u2PhysMon : 2; Physical access handler type {none, read, write, all}.
407	uint32_t u2VirtMon : 2; Virtual access handler type {none, read, write, all}..
408	uint32_t u2State : 2; The page state { zero, shared, normal, write monitored }.
409	uint32_t fWrittenTo : 1; Whether a write monitored page was written to.
410	uint32_t u20Reserved : 20; Reserved for later, mostly sharing stats.
411	uint32_t u32Tracking; The shadow PT tracking stuff, roughly.
412	@endverbatim
413	*
414	* Cost wise, this means we'll double the cost for guest memory. There isn't anyway
415	* around that I'm afraid. It means that the cost of dealing out 32GB of memory
416	* to one or more VMs is: (32GB >> PAGE_SHIFT) * 16 bytes, or 128MBs. Or another
417	* example, the VM heap cost when assigning 1GB to a VM will be: 4MB.
418	*
419	* A couple of cost examples for the total cost per-VM + kernel.
420	* 32-bit Windows and 32-bit linux:
421	* 1GB guest ram, 256K pages: 4MB + 2MB(+) = 6MB
422	* 4GB guest ram, 1M pages: 16MB + 8MB(+) = 24MB
423	* 32GB guest ram, 8M pages: 128MB + 64MB(+) = 192MB
424	* 64-bit Windows and 64-bit linux:
425	* 1GB guest ram, 256K pages: 4MB + 3MB(+) = 7MB
426	* 4GB guest ram, 1M pages: 16MB + 12MB(+) = 28MB
427	* 32GB guest ram, 8M pages: 128MB + 96MB(+) = 224MB
428	*
429	* UPDATE - 2007-09-27:
430	* Will need a ballooned flag/state too because we cannot
431	* trust the guest 100% and reporting the same page as ballooned more
432	* than once will put the GMM off balance.
433	*
434	*
435	* @subsection subsec_pgmPhys_Serializing Serializing Access
436	*
437	* Initially, we'll try a simple scheme:
438	*
439	* - The per-VM RAM tracking structures (PGMRAMRANGE) is only modified
440	* by the EMT thread of that VM while in the pgm critsect.
441	* - Other threads in the VM process that needs to make reliable use of
442	* the per-VM RAM tracking structures will enter the critsect.
443	* - No process external thread or kernel thread will ever try enter
444	* the pgm critical section, as that just won't work.
445	* - The idle thread (and similar threads) doesn't not need 100% reliable
446	* data when performing it tasks as the EMT thread will be the one to
447	* do the actual changes later anyway. So, as long as it only accesses
448	* the main ram range, it can do so by somehow preventing the VM from
449	* being destroyed while it works on it...
450	*
451	* - The over-commitment management, including the allocating/freeing
452	* chunks, is serialized by a ring-0 mutex lock (a fast one since the
453	* more mundane mutex implementation is broken on Linux).
454	* - A separeate mutex is protecting the set of allocation chunks so
455	* that pages can be shared or/and freed up while some other VM is
456	* allocating more chunks. This mutex can be take from under the other
457	* one, but not the otherway around.
458	*
459	*
460	* @subsection subsec_pgmPhys_Request VM Request interface
461	*
462	* When in ring-0 it will become necessary to send requests to a VM so it can
463	* for instance move a page while defragmenting during VM destroy. The idle
464	* thread will make use of this interface to request VMs to setup shared
465	* pages and to perform write monitoring of pages.
466	*
467	* I would propose an interface similar to the current VMReq interface, similar
468	* in that it doesn't require locking and that the one sending the request may
469	* wait for completion if it wishes to. This shouldn't be very difficult to
470	* realize.
471	*
472	* The requests themselves are also pretty simple. They are basically:
473	* -# Check that some precondition is still true.
474	* -# Do the update.
475	* -# Update all shadow page tables involved with the page.
476	*
477	* The 3rd step is identical to what we're already doing when updating a
478	* physical handler, see pgmHandlerPhysicalSetRamFlagsAndFlushShadowPTs.
479	*
480	*
481	*
482	* @section sec_pgmPhys_MappingCaches Mapping Caches
483	*
484	* In order to be able to map in and out memory and to be able to support
485	* guest with more RAM than we've got virtual address space, we'll employing
486	* a mapping cache. There is already a tiny one for GC (see PGMGCDynMapGCPageEx)
487	* and we'll create a similar one for ring-0 unless we decide to setup a dedicate
488	* memory context for the HWACCM execution.
489	*
490	*
491	* @subsection subsec_pgmPhys_MappingCaches_R3 Ring-3
492	*
493	* We've considered implementing the ring-3 mapping cache page based but found
494	* that this was bother some when one had to take into account TLBs+SMP and
495	* portability (missing the necessary APIs on several platforms). There were
496	* also some performance concerns with this approach which hadn't quite been
497	* worked out.
498	*
499	* Instead, we'll be mapping allocation chunks into the VM process. This simplifies
500	* matters greatly quite a bit since we don't need to invent any new ring-0 stuff,
501	* only some minor RTR0MEMOBJ mapping stuff. The main concern here is that mapping
502	* compared to the previous idea is that mapping or unmapping a 1MB chunk is more
503	* costly than a single page, although how much more costly is uncertain. We'll
504	* try address this by using a very big cache, preferably bigger than the actual
505	* VM RAM size if possible. The current VM RAM sizes should give some idea for
506	* 32-bit boxes, while on 64-bit we can probably get away with employing an
507	* unlimited cache.
508	*
509	* The cache have to parts, as already indicated, the ring-3 side and the
510	* ring-0 side.
511	*
512	* The ring-0 will be tied to the page allocator since it will operate on the
513	* memory objects it contains. It will therefore require the first ring-0 mutex
514	* discussed in @ref subsec_pgmPhys_Serializing. We
515	* some double house keeping wrt to who has mapped what I think, since both
516	* VMMR0.r0 and RTR0MemObj will keep track of mapping relataions
517	*
518	* The ring-3 part will be protected by the pgm critsect. For simplicity, we'll
519	* require anyone that desires to do changes to the mapping cache to do that
520	* from within this critsect. Alternatively, we could employ a separate critsect
521	* for serializing changes to the mapping cache as this would reduce potential
522	* contention with other threads accessing mappings unrelated to the changes
523	* that are in process. We can see about this later, contention will show
524	* up in the statistics anyway, so it'll be simple to tell.
525	*
526	* The organization of the ring-3 part will be very much like how the allocation
527	* chunks are organized in ring-0, that is in an AVL tree by chunk id. To avoid
528	* having to walk the tree all the time, we'll have a couple of lookaside entries
529	* like in we do for I/O ports and MMIO in IOM.
530	*
531	* The simplified flow of a PGMPhysRead/Write function:
532	* -# Enter the PGM critsect.
533	* -# Lookup GCPhys in the ram ranges and get the Page ID.
534	* -# Calc the Allocation Chunk ID from the Page ID.
535	* -# Check the lookaside entries and then the AVL tree for the Chunk ID.
536	* If not found in cache:
537	* -# Call ring-0 and request it to be mapped and supply
538	* a chunk to be unmapped if the cache is maxed out already.
539	* -# Insert the new mapping into the AVL tree (id + R3 address).
540	* -# Update the relevant lookaside entry and return the mapping address.
541	* -# Do the read/write according to monitoring flags and everything.
542	* -# Leave the critsect.
543	*
544	*
545	* @section sec_pgmPhys_Fallback Fallback
546	*
547	* Current all the "second tier" hosts will not support the RTR0MemObjAllocPhysNC
548	* API and thus require a fallback.
549	*
550	* So, when RTR0MemObjAllocPhysNC returns VERR_NOT_SUPPORTED the page allocator
551	* will return to the ring-3 caller (and later ring-0) and asking it to seed
552	* the page allocator with some fresh pages (VERR_GMM_SEED_ME). Ring-3 will
553	* then perform an SUPPageAlloc(cbChunk >> PAGE_SHIFT) call and make a
554	* "SeededAllocPages" call to ring-0.
555	*
556	* The first time ring-0 sees the VERR_NOT_SUPPORTED failure it will disable
557	* all page sharing (zero page detection will continue). It will also force
558	* all allocations to come from the VM which seeded the page. Both these
559	* measures are taken to make sure that there will never be any need for
560	* mapping anything into ring-3 - everything will be mapped already.
561	*
562	* Whether we'll continue to use the current MM locked memory management
563	* for this I don't quite know (I'd prefer not to and just ditch that all
564	* togther), we'll see what's simplest to do.
565	*
566	*
567	*
568	* @section sec_pgmPhys_Changes Changes
569	*
570	* Breakdown of the changes involved?
571	*/
572
573
574	/** Saved state data unit version. */
575	#define PGM_SAVED_STATE_VERSION 6
576
577	/*******************************************************************************
578	* Header Files *
579	*******************************************************************************/
580	#define LOG_GROUP LOG_GROUP_PGM
581	#include <VBox/dbgf.h>
582	#include <VBox/pgm.h>
583	#include <VBox/cpum.h>
584	#include <VBox/iom.h>
585	#include <VBox/sup.h>
586	#include <VBox/mm.h>
587	#include <VBox/em.h>
588	#include <VBox/stam.h>
589	#include <VBox/rem.h>
590	#include <VBox/dbgf.h>
591	#include <VBox/rem.h>
592	#include <VBox/selm.h>
593	#include <VBox/ssm.h>
594	#include "PGMInternal.h"
595	#include <VBox/vm.h>
596	#include <VBox/dbg.h>
597	#include <VBox/hwaccm.h>
598
599	#include <iprt/assert.h>
600	#include <iprt/alloc.h>
601	#include <iprt/asm.h>
602	#include <iprt/thread.h>
603	#include <iprt/string.h>
604	#ifdef DEBUG_bird
605	# include <iprt/env.h>
606	#endif
607	#include <VBox/param.h>
608	#include <VBox/err.h>
609
610
611
612	/*******************************************************************************
613	* Internal Functions *
614	*******************************************************************************/
615	static int pgmR3InitPaging(PVM pVM);
616	static DECLCALLBACK(void) pgmR3PhysInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
617	static DECLCALLBACK(void) pgmR3InfoMode(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
618	static DECLCALLBACK(void) pgmR3InfoCr3(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
619	static DECLCALLBACK(int) pgmR3RelocatePhysHandler(PAVLROGCPHYSNODECORE pNode, void *pvUser);
620	static DECLCALLBACK(int) pgmR3RelocateVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser);
621	static DECLCALLBACK(int) pgmR3RelocateHyperVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser);
622	#ifdef VBOX_STRICT
623	static DECLCALLBACK(void) pgmR3ResetNoMorePhysWritesFlag(PVM pVM, VMSTATE enmState, VMSTATE enmOldState, void *pvUser);
624	#endif
625	static DECLCALLBACK(int) pgmR3Save(PVM pVM, PSSMHANDLE pSSM);
626	static DECLCALLBACK(int) pgmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version);
627	static int pgmR3ModeDataInit(PVM pVM, bool fResolveGCAndR0);
628	static void pgmR3ModeDataSwitch(PVM pVM, PGMMODE enmShw, PGMMODE enmGst);
629	static PGMMODE pgmR3CalcShadowMode(PVM pVM, PGMMODE enmGuestMode, SUPPAGINGMODE enmHostMode, PGMMODE enmShadowMode, VMMSWITCHER *penmSwitcher);
630
631	#ifdef VBOX_WITH_STATISTICS
632	static void pgmR3InitStats(PVM pVM);
633	#endif
634
635	#ifdef VBOX_WITH_DEBUGGER
636	/** @todo all but the two last commands must be converted to 'info'. */
637	static DECLCALLBACK(int) pgmR3CmdRam(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
638	static DECLCALLBACK(int) pgmR3CmdMap(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
639	static DECLCALLBACK(int) pgmR3CmdSync(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
640	static DECLCALLBACK(int) pgmR3CmdSyncAlways(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
641	# ifdef VBOX_STRICT
642	static DECLCALLBACK(int) pgmR3CmdAssertCR3(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
643	# endif
644	#endif
645
646
647	/*******************************************************************************
648	* Global Variables *
649	*******************************************************************************/
650	#ifdef VBOX_WITH_DEBUGGER
651	/** Command descriptors. */
652	static const DBGCCMD g_aCmds[] =
653	{
654	/* pszCmd, cArgsMin, cArgsMax, paArgDesc, cArgDescs, pResultDesc, fFlags, pfnHandler pszSyntax, ....pszDescription */
655	{ "pgmram", 0, 0, NULL, 0, NULL, 0, pgmR3CmdRam, "", "Display the ram ranges." },
656	{ "pgmmap", 0, 0, NULL, 0, NULL, 0, pgmR3CmdMap, "", "Display the mapping ranges." },
657	{ "pgmsync", 0, 0, NULL, 0, NULL, 0, pgmR3CmdSync, "", "Sync the CR3 page." },
658	#ifdef VBOX_STRICT
659	{ "pgmassertcr3", 0, 0, NULL, 0, NULL, 0, pgmR3CmdAssertCR3, "", "Check the shadow CR3 mapping." },
660	#endif
661	{ "pgmsyncalways", 0, 0, NULL, 0, NULL, 0, pgmR3CmdSyncAlways, "", "Toggle permanent CR3 syncing." },
662	};
663	#endif
664
665
666
667
668	/*
669	* Shadow - 32-bit mode
670	*/
671	#define PGM_SHW_TYPE PGM_TYPE_32BIT
672	#define PGM_SHW_NAME(name) PGM_SHW_NAME_32BIT(name)
673	#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_32BIT_STR(name)
674	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_32BIT_STR(name)
675	#include "PGMShw.h"
676
677	/* Guest - real mode */
678	#define PGM_GST_TYPE PGM_TYPE_REAL
679	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
680	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_REAL_STR(name)
681	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
682	#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_REAL(name)
683	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_32BIT_REAL_STR(name)
684	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_32BIT_REAL_STR(name)
685	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_PHYS
686	#include "PGMGst.h"
687	#include "PGMBth.h"
688	#undef BTH_PGMPOOLKIND_PT_FOR_PT
689	#undef PGM_BTH_NAME
690	#undef PGM_BTH_NAME_RC_STR
691	#undef PGM_BTH_NAME_R0_STR
692	#undef PGM_GST_TYPE
693	#undef PGM_GST_NAME
694	#undef PGM_GST_NAME_RC_STR
695	#undef PGM_GST_NAME_R0_STR
696
697	/* Guest - protected mode */
698	#define PGM_GST_TYPE PGM_TYPE_PROT
699	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
700	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PROT_STR(name)
701	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
702	#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_PROT(name)
703	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_32BIT_PROT_STR(name)
704	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_32BIT_PROT_STR(name)
705	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_PHYS
706	#include "PGMGst.h"
707	#include "PGMBth.h"
708	#undef BTH_PGMPOOLKIND_PT_FOR_PT
709	#undef PGM_BTH_NAME
710	#undef PGM_BTH_NAME_RC_STR
711	#undef PGM_BTH_NAME_R0_STR
712	#undef PGM_GST_TYPE
713	#undef PGM_GST_NAME
714	#undef PGM_GST_NAME_RC_STR
715	#undef PGM_GST_NAME_R0_STR
716
717	/* Guest - 32-bit mode */
718	#define PGM_GST_TYPE PGM_TYPE_32BIT
719	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
720	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_32BIT_STR(name)
721	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
722	#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_32BIT(name)
723	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_32BIT_32BIT_STR(name)
724	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_32BIT_32BIT_STR(name)
725	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT
726	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB
727	#include "PGMGst.h"
728	#include "PGMBth.h"
729	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
730	#undef BTH_PGMPOOLKIND_PT_FOR_PT
731	#undef PGM_BTH_NAME
732	#undef PGM_BTH_NAME_RC_STR
733	#undef PGM_BTH_NAME_R0_STR
734	#undef PGM_GST_TYPE
735	#undef PGM_GST_NAME
736	#undef PGM_GST_NAME_RC_STR
737	#undef PGM_GST_NAME_R0_STR
738
739	#undef PGM_SHW_TYPE
740	#undef PGM_SHW_NAME
741	#undef PGM_SHW_NAME_RC_STR
742	#undef PGM_SHW_NAME_R0_STR
743
744
745	/*
746	* Shadow - PAE mode
747	*/
748	#define PGM_SHW_TYPE PGM_TYPE_PAE
749	#define PGM_SHW_NAME(name) PGM_SHW_NAME_PAE(name)
750	#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_PAE_STR(name)
751	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_PAE_STR(name)
752	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_REAL(name)
753	#include "PGMShw.h"
754
755	/* Guest - real mode */
756	#define PGM_GST_TYPE PGM_TYPE_REAL
757	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
758	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_REAL_STR(name)
759	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
760	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_REAL(name)
761	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_PAE_REAL_STR(name)
762	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_REAL_STR(name)
763	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
764	#include "PGMBth.h"
765	#undef BTH_PGMPOOLKIND_PT_FOR_PT
766	#undef PGM_BTH_NAME
767	#undef PGM_BTH_NAME_RC_STR
768	#undef PGM_BTH_NAME_R0_STR
769	#undef PGM_GST_TYPE
770	#undef PGM_GST_NAME
771	#undef PGM_GST_NAME_RC_STR
772	#undef PGM_GST_NAME_R0_STR
773
774	/* Guest - protected mode */
775	#define PGM_GST_TYPE PGM_TYPE_PROT
776	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
777	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PROT_STR(name)
778	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
779	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_PROT(name)
780	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_PAE_PROT_STR(name)
781	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_PROT_STR(name)
782	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
783	#include "PGMBth.h"
784	#undef BTH_PGMPOOLKIND_PT_FOR_PT
785	#undef PGM_BTH_NAME
786	#undef PGM_BTH_NAME_RC_STR
787	#undef PGM_BTH_NAME_R0_STR
788	#undef PGM_GST_TYPE
789	#undef PGM_GST_NAME
790	#undef PGM_GST_NAME_RC_STR
791	#undef PGM_GST_NAME_R0_STR
792
793	/* Guest - 32-bit mode */
794	#define PGM_GST_TYPE PGM_TYPE_32BIT
795	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
796	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_32BIT_STR(name)
797	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
798	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_32BIT(name)
799	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_PAE_32BIT_STR(name)
800	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_32BIT_STR(name)
801	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_32BIT_PT
802	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB
803	#include "PGMBth.h"
804	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
805	#undef BTH_PGMPOOLKIND_PT_FOR_PT
806	#undef PGM_BTH_NAME
807	#undef PGM_BTH_NAME_RC_STR
808	#undef PGM_BTH_NAME_R0_STR
809	#undef PGM_GST_TYPE
810	#undef PGM_GST_NAME
811	#undef PGM_GST_NAME_RC_STR
812	#undef PGM_GST_NAME_R0_STR
813
814	/* Guest - PAE mode */
815	#define PGM_GST_TYPE PGM_TYPE_PAE
816	#define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
817	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PAE_STR(name)
818	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PAE_STR(name)
819	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_PAE(name)
820	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_PAE_PAE_STR(name)
821	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_PAE_STR(name)
822	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
823	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
824	#include "PGMGst.h"
825	#include "PGMBth.h"
826	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
827	#undef BTH_PGMPOOLKIND_PT_FOR_PT
828	#undef PGM_BTH_NAME
829	#undef PGM_BTH_NAME_RC_STR
830	#undef PGM_BTH_NAME_R0_STR
831	#undef PGM_GST_TYPE
832	#undef PGM_GST_NAME
833	#undef PGM_GST_NAME_RC_STR
834	#undef PGM_GST_NAME_R0_STR
835
836	#undef PGM_SHW_TYPE
837	#undef PGM_SHW_NAME
838	#undef PGM_SHW_NAME_RC_STR
839	#undef PGM_SHW_NAME_R0_STR
840
841
842	/*
843	* Shadow - AMD64 mode
844	*/
845	#define PGM_SHW_TYPE PGM_TYPE_AMD64
846	#define PGM_SHW_NAME(name) PGM_SHW_NAME_AMD64(name)
847	#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_AMD64_STR(name)
848	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_AMD64_STR(name)
849	#include "PGMShw.h"
850
851	#ifdef VBOX_WITH_64_BITS_GUESTS
852	/* Guest - AMD64 mode */
853	# define PGM_GST_TYPE PGM_TYPE_AMD64
854	# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
855	# define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_AMD64_STR(name)
856	# define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_AMD64_STR(name)
857	# define PGM_BTH_NAME(name) PGM_BTH_NAME_AMD64_AMD64(name)
858	# define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_AMD64_AMD64_STR(name)
859	# define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_AMD64_AMD64_STR(name)
860	# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
861	# define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
862	# include "PGMGst.h"
863	# include "PGMBth.h"
864	# undef BTH_PGMPOOLKIND_PT_FOR_BIG
865	# undef BTH_PGMPOOLKIND_PT_FOR_PT
866	# undef PGM_BTH_NAME
867	# undef PGM_BTH_NAME_RC_STR
868	# undef PGM_BTH_NAME_R0_STR
869	# undef PGM_GST_TYPE
870	# undef PGM_GST_NAME
871	# undef PGM_GST_NAME_RC_STR
872	# undef PGM_GST_NAME_R0_STR
873	#endif /* VBOX_WITH_64_BITS_GUESTS */
874
875	#undef PGM_SHW_TYPE
876	#undef PGM_SHW_NAME
877	#undef PGM_SHW_NAME_RC_STR
878	#undef PGM_SHW_NAME_R0_STR
879
880
881	/*
882	* Shadow - Nested paging mode
883	*/
884	#define PGM_SHW_TYPE PGM_TYPE_NESTED
885	#define PGM_SHW_NAME(name) PGM_SHW_NAME_NESTED(name)
886	#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_NESTED_STR(name)
887	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_NESTED_STR(name)
888	#include "PGMShw.h"
889
890	/* Guest - real mode */
891	#define PGM_GST_TYPE PGM_TYPE_REAL
892	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
893	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_REAL_STR(name)
894	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
895	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_REAL(name)
896	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_REAL_STR(name)
897	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_REAL_STR(name)
898	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
899	#include "PGMBth.h"
900	#undef BTH_PGMPOOLKIND_PT_FOR_PT
901	#undef PGM_BTH_NAME
902	#undef PGM_BTH_NAME_RC_STR
903	#undef PGM_BTH_NAME_R0_STR
904	#undef PGM_GST_TYPE
905	#undef PGM_GST_NAME
906	#undef PGM_GST_NAME_RC_STR
907	#undef PGM_GST_NAME_R0_STR
908
909	/* Guest - protected mode */
910	#define PGM_GST_TYPE PGM_TYPE_PROT
911	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
912	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PROT_STR(name)
913	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
914	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_PROT(name)
915	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_PROT_STR(name)
916	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_PROT_STR(name)
917	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
918	#include "PGMBth.h"
919	#undef BTH_PGMPOOLKIND_PT_FOR_PT
920	#undef PGM_BTH_NAME
921	#undef PGM_BTH_NAME_RC_STR
922	#undef PGM_BTH_NAME_R0_STR
923	#undef PGM_GST_TYPE
924	#undef PGM_GST_NAME
925	#undef PGM_GST_NAME_RC_STR
926	#undef PGM_GST_NAME_R0_STR
927
928	/* Guest - 32-bit mode */
929	#define PGM_GST_TYPE PGM_TYPE_32BIT
930	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
931	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_32BIT_STR(name)
932	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
933	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_32BIT(name)
934	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_32BIT_STR(name)
935	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_32BIT_STR(name)
936	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_32BIT_PT
937	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB
938	#include "PGMBth.h"
939	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
940	#undef BTH_PGMPOOLKIND_PT_FOR_PT
941	#undef PGM_BTH_NAME
942	#undef PGM_BTH_NAME_RC_STR
943	#undef PGM_BTH_NAME_R0_STR
944	#undef PGM_GST_TYPE
945	#undef PGM_GST_NAME
946	#undef PGM_GST_NAME_RC_STR
947	#undef PGM_GST_NAME_R0_STR
948
949	/* Guest - PAE mode */
950	#define PGM_GST_TYPE PGM_TYPE_PAE
951	#define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
952	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PAE_STR(name)
953	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PAE_STR(name)
954	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_PAE(name)
955	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_PAE_STR(name)
956	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_PAE_STR(name)
957	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
958	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
959	#include "PGMBth.h"
960	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
961	#undef BTH_PGMPOOLKIND_PT_FOR_PT
962	#undef PGM_BTH_NAME
963	#undef PGM_BTH_NAME_RC_STR
964	#undef PGM_BTH_NAME_R0_STR
965	#undef PGM_GST_TYPE
966	#undef PGM_GST_NAME
967	#undef PGM_GST_NAME_RC_STR
968	#undef PGM_GST_NAME_R0_STR
969
970	#ifdef VBOX_WITH_64_BITS_GUESTS
971	/* Guest - AMD64 mode */
972	# define PGM_GST_TYPE PGM_TYPE_AMD64
973	# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
974	# define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_AMD64_STR(name)
975	# define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_AMD64_STR(name)
976	# define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_AMD64(name)
977	# define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_AMD64_STR(name)
978	# define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_AMD64_STR(name)
979	# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
980	# define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
981	# include "PGMBth.h"
982	# undef BTH_PGMPOOLKIND_PT_FOR_BIG
983	# undef BTH_PGMPOOLKIND_PT_FOR_PT
984	# undef PGM_BTH_NAME
985	# undef PGM_BTH_NAME_RC_STR
986	# undef PGM_BTH_NAME_R0_STR
987	# undef PGM_GST_TYPE
988	# undef PGM_GST_NAME
989	# undef PGM_GST_NAME_RC_STR
990	# undef PGM_GST_NAME_R0_STR
991	#endif /* VBOX_WITH_64_BITS_GUESTS */
992
993	#undef PGM_SHW_TYPE
994	#undef PGM_SHW_NAME
995	#undef PGM_SHW_NAME_RC_STR
996	#undef PGM_SHW_NAME_R0_STR
997
998
999	/*
1000	* Shadow - EPT
1001	*/
1002	#define PGM_SHW_TYPE PGM_TYPE_EPT
1003	#define PGM_SHW_NAME(name) PGM_SHW_NAME_EPT(name)
1004	#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_EPT_STR(name)
1005	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_EPT_STR(name)
1006	#include "PGMShw.h"
1007
1008	/* Guest - real mode */
1009	#define PGM_GST_TYPE PGM_TYPE_REAL
1010	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
1011	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_REAL_STR(name)
1012	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
1013	#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_REAL(name)
1014	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_REAL_STR(name)
1015	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_REAL_STR(name)
1016	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
1017	#include "PGMBth.h"
1018	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1019	#undef PGM_BTH_NAME
1020	#undef PGM_BTH_NAME_RC_STR
1021	#undef PGM_BTH_NAME_R0_STR
1022	#undef PGM_GST_TYPE
1023	#undef PGM_GST_NAME
1024	#undef PGM_GST_NAME_RC_STR
1025	#undef PGM_GST_NAME_R0_STR
1026
1027	/* Guest - protected mode */
1028	#define PGM_GST_TYPE PGM_TYPE_PROT
1029	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
1030	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PROT_STR(name)
1031	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
1032	#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_PROT(name)
1033	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_PROT_STR(name)
1034	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_PROT_STR(name)
1035	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
1036	#include "PGMBth.h"
1037	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1038	#undef PGM_BTH_NAME
1039	#undef PGM_BTH_NAME_RC_STR
1040	#undef PGM_BTH_NAME_R0_STR
1041	#undef PGM_GST_TYPE
1042	#undef PGM_GST_NAME
1043	#undef PGM_GST_NAME_RC_STR
1044	#undef PGM_GST_NAME_R0_STR
1045
1046	/* Guest - 32-bit mode */
1047	#define PGM_GST_TYPE PGM_TYPE_32BIT
1048	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
1049	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_32BIT_STR(name)
1050	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
1051	#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_32BIT(name)
1052	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_32BIT_STR(name)
1053	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_32BIT_STR(name)
1054	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_32BIT_PT
1055	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB
1056	#include "PGMBth.h"
1057	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
1058	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1059	#undef PGM_BTH_NAME
1060	#undef PGM_BTH_NAME_RC_STR
1061	#undef PGM_BTH_NAME_R0_STR
1062	#undef PGM_GST_TYPE
1063	#undef PGM_GST_NAME
1064	#undef PGM_GST_NAME_RC_STR
1065	#undef PGM_GST_NAME_R0_STR
1066
1067	/* Guest - PAE mode */
1068	#define PGM_GST_TYPE PGM_TYPE_PAE
1069	#define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
1070	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PAE_STR(name)
1071	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PAE_STR(name)
1072	#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_PAE(name)
1073	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_PAE_STR(name)
1074	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_PAE_STR(name)
1075	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
1076	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
1077	#include "PGMBth.h"
1078	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
1079	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1080	#undef PGM_BTH_NAME
1081	#undef PGM_BTH_NAME_RC_STR
1082	#undef PGM_BTH_NAME_R0_STR
1083	#undef PGM_GST_TYPE
1084	#undef PGM_GST_NAME
1085	#undef PGM_GST_NAME_RC_STR
1086	#undef PGM_GST_NAME_R0_STR
1087
1088	#ifdef VBOX_WITH_64_BITS_GUESTS
1089	/* Guest - AMD64 mode */
1090	# define PGM_GST_TYPE PGM_TYPE_AMD64
1091	# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
1092	# define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_AMD64_STR(name)
1093	# define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_AMD64_STR(name)
1094	# define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_AMD64(name)
1095	# define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_AMD64_STR(name)
1096	# define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_AMD64_STR(name)
1097	# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
1098	# define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
1099	# include "PGMBth.h"
1100	# undef BTH_PGMPOOLKIND_PT_FOR_BIG
1101	# undef BTH_PGMPOOLKIND_PT_FOR_PT
1102	# undef PGM_BTH_NAME
1103	# undef PGM_BTH_NAME_RC_STR
1104	# undef PGM_BTH_NAME_R0_STR
1105	# undef PGM_GST_TYPE
1106	# undef PGM_GST_NAME
1107	# undef PGM_GST_NAME_RC_STR
1108	# undef PGM_GST_NAME_R0_STR
1109	#endif /* VBOX_WITH_64_BITS_GUESTS */
1110
1111	#undef PGM_SHW_TYPE
1112	#undef PGM_SHW_NAME
1113	#undef PGM_SHW_NAME_RC_STR
1114	#undef PGM_SHW_NAME_R0_STR
1115
1116
1117
1118	/**
1119	* Initiates the paging of VM.
1120	*
1121	* @returns VBox status code.
1122	* @param pVM Pointer to VM structure.
1123	*/
1124	VMMR3DECL(int) PGMR3Init(PVM pVM)
1125	{
1126	LogFlow(("PGMR3Init:\n"));
1127
1128	/*
1129	* Assert alignment and sizes.
1130	*/
1131	AssertRelease(sizeof(pVM->pgm.s) <= sizeof(pVM->pgm.padding));
1132
1133	/*
1134	* Init the structure.
1135	*/
1136	pVM->pgm.s.offVM = RT_OFFSETOF(VM, pgm.s);
1137	pVM->pgm.s.enmShadowMode = PGMMODE_INVALID;
1138	pVM->pgm.s.enmGuestMode = PGMMODE_INVALID;
1139	pVM->pgm.s.enmHostMode = SUPPAGINGMODE_INVALID;
1140	pVM->pgm.s.GCPhysCR3 = NIL_RTGCPHYS;
1141	pVM->pgm.s.GCPhysGstCR3Monitored = NIL_RTGCPHYS;
1142	pVM->pgm.s.fA20Enabled = true;
1143	pVM->pgm.s.GCPhys4MBPSEMask = RT_BIT_64(32) - 1; /* default; checked later */
1144	pVM->pgm.s.pGstPaePDPTR3 = NULL;
1145	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
1146	pVM->pgm.s.pGstPaePDPTR0 = NIL_RTR0PTR;
1147	#endif
1148	pVM->pgm.s.pGstPaePDPTRC = NIL_RTRCPTR;
1149	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.apGstPaePDsR3); i++)
1150	{
1151	pVM->pgm.s.apGstPaePDsR3[i] = NULL;
1152	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
1153	pVM->pgm.s.apGstPaePDsR0[i] = NIL_RTR0PTR;
1154	#endif
1155	pVM->pgm.s.apGstPaePDsRC[i] = NIL_RTRCPTR;
1156	pVM->pgm.s.aGCPhysGstPaePDs[i] = NIL_RTGCPHYS;
1157	pVM->pgm.s.aGCPhysGstPaePDsMonitored[i] = NIL_RTGCPHYS;
1158	}
1159
1160	#ifdef VBOX_STRICT
1161	VMR3AtStateRegister(pVM, pgmR3ResetNoMorePhysWritesFlag, NULL);
1162	#endif
1163
1164	/*
1165	* Get the configured RAM size - to estimate saved state size.
1166	*/
1167	uint64_t cbRam;
1168	int rc = CFGMR3QueryU64(CFGMR3GetRoot(pVM), "RamSize", &cbRam);
1169	if (rc == VERR_CFGM_VALUE_NOT_FOUND)
1170	cbRam = pVM->pgm.s.cbRamSize = 0;
1171	else if (RT_SUCCESS(rc))
1172	{
1173	if (cbRam < PAGE_SIZE)
1174	cbRam = 0;
1175	cbRam = RT_ALIGN_64(cbRam, PAGE_SIZE);
1176	pVM->pgm.s.cbRamSize = (RTUINT)cbRam;
1177	}
1178	else
1179	{
1180	AssertMsgFailed(("Configuration error: Failed to query integer \"RamSize\", rc=%Rrc.\n", rc));
1181	return rc;
1182	}
1183
1184	/*
1185	* Register saved state data unit.
1186	*/
1187	rc = SSMR3RegisterInternal(pVM, "pgm", 1, PGM_SAVED_STATE_VERSION, (size_t)cbRam + sizeof(PGM),
1188	NULL, pgmR3Save, NULL,
1189	NULL, pgmR3Load, NULL);
1190	if (RT_FAILURE(rc))
1191	return rc;
1192
1193	/*
1194	* Initialize the PGM critical section and flush the phys TLBs
1195	*/
1196	rc = PDMR3CritSectInit(pVM, &pVM->pgm.s.CritSect, "PGM");
1197	AssertRCReturn(rc, rc);
1198
1199	PGMR3PhysChunkInvalidateTLB(pVM);
1200	PGMPhysInvalidatePageR3MapTLB(pVM);
1201	PGMPhysInvalidatePageR0MapTLB(pVM);
1202	PGMPhysInvalidatePageGCMapTLB(pVM);
1203
1204	/*
1205	* Trees
1206	*/
1207	rc = MMHyperAlloc(pVM, sizeof(PGMTREES), 0, MM_TAG_PGM, (void **)&pVM->pgm.s.pTreesR3);
1208	if (RT_SUCCESS(rc))
1209	{
1210	pVM->pgm.s.pTreesR0 = MMHyperR3ToR0(pVM, pVM->pgm.s.pTreesR3);
1211	pVM->pgm.s.pTreesRC = MMHyperR3ToRC(pVM, pVM->pgm.s.pTreesR3);
1212
1213	/*
1214	* Alocate the zero page.
1215	*/
1216	rc = MMHyperAlloc(pVM, PAGE_SIZE, PAGE_SIZE, MM_TAG_PGM, &pVM->pgm.s.pvZeroPgR3);
1217	}
1218	if (RT_SUCCESS(rc))
1219	{
1220	pVM->pgm.s.pvZeroPgGC = MMHyperR3ToRC(pVM, pVM->pgm.s.pvZeroPgR3);
1221	pVM->pgm.s.pvZeroPgR0 = MMHyperR3ToR0(pVM, pVM->pgm.s.pvZeroPgR3);
1222	AssertRelease(pVM->pgm.s.pvZeroPgR0 != NIL_RTHCPHYS);
1223	pVM->pgm.s.HCPhysZeroPg = MMR3HyperHCVirt2HCPhys(pVM, pVM->pgm.s.pvZeroPgR3);
1224	AssertRelease(pVM->pgm.s.HCPhysZeroPg != NIL_RTHCPHYS);
1225
1226	/*
1227	* Init the paging.
1228	*/
1229	rc = pgmR3InitPaging(pVM);
1230	}
1231	if (RT_SUCCESS(rc))
1232	{
1233	/*
1234	* Init the page pool.
1235	*/
1236	rc = pgmR3PoolInit(pVM);
1237	}
1238	if (RT_SUCCESS(rc))
1239	{
1240	/*
1241	* Info & statistics
1242	*/
1243	DBGFR3InfoRegisterInternal(pVM, "mode",
1244	"Shows the current paging mode. "
1245	"Recognizes 'all', 'guest', 'shadow' and 'host' as arguments, defaulting to 'all' if nothing's given.",
1246	pgmR3InfoMode);
1247	DBGFR3InfoRegisterInternal(pVM, "pgmcr3",
1248	"Dumps all the entries in the top level paging table. No arguments.",
1249	pgmR3InfoCr3);
1250	DBGFR3InfoRegisterInternal(pVM, "phys",
1251	"Dumps all the physical address ranges. No arguments.",
1252	pgmR3PhysInfo);
1253	DBGFR3InfoRegisterInternal(pVM, "handlers",
1254	"Dumps physical, virtual and hyper virtual handlers. "
1255	"Pass 'phys', 'virt', 'hyper' as argument if only one kind is wanted."
1256	"Add 'nost' if the statistics are unwanted, use together with 'all' or explicit selection.",
1257	pgmR3InfoHandlers);
1258	DBGFR3InfoRegisterInternal(pVM, "mappings",
1259	"Dumps guest mappings.",
1260	pgmR3MapInfo);
1261
1262	STAM_REL_REG(pVM, &pVM->pgm.s.cGuestModeChanges, STAMTYPE_COUNTER, "/PGM/cGuestModeChanges", STAMUNIT_OCCURENCES, "Number of guest mode changes.");
1263	#ifdef VBOX_WITH_STATISTICS
1264	pgmR3InitStats(pVM);
1265	#endif
1266	#ifdef VBOX_WITH_DEBUGGER
1267	/*
1268	* Debugger commands.
1269	*/
1270	static bool fRegisteredCmds = false;
1271	if (!fRegisteredCmds)
1272	{
1273	int rc = DBGCRegisterCommands(&g_aCmds[0], RT_ELEMENTS(g_aCmds));
1274	if (RT_SUCCESS(rc))
1275	fRegisteredCmds = true;
1276	}
1277	#endif
1278	return VINF_SUCCESS;
1279	}
1280
1281	/* Almost no cleanup necessary, MM frees all memory. */
1282	PDMR3CritSectDelete(&pVM->pgm.s.CritSect);
1283
1284	return rc;
1285	}
1286
1287
1288	/**
1289	* Initializes the per-VCPU PGM.
1290	*
1291	* @returns VBox status code.
1292	* @param pVM The VM to operate on.
1293	*/
1294	VMMR3DECL(int) PGMR3InitCPU(PVM pVM)
1295	{
1296	LogFlow(("PGMR3InitCPU\n"));
1297	return VINF_SUCCESS;
1298	}
1299
1300
1301	/**
1302	* Init paging.
1303	*
1304	* Since we need to check what mode the host is operating in before we can choose
1305	* the right paging functions for the host we have to delay this until R0 has
1306	* been initialized.
1307	*
1308	* @returns VBox status code.
1309	* @param pVM VM handle.
1310	*/
1311	static int pgmR3InitPaging(PVM pVM)
1312	{
1313	/*
1314	* Force a recalculation of modes and switcher so everyone gets notified.
1315	*/
1316	pVM->pgm.s.enmShadowMode = PGMMODE_INVALID;
1317	pVM->pgm.s.enmGuestMode = PGMMODE_INVALID;
1318	pVM->pgm.s.enmHostMode = SUPPAGINGMODE_INVALID;
1319
1320	/*
1321	* Allocate static mapping space for whatever the cr3 register
1322	* points to and in the case of PAE mode to the 4 PDs.
1323	*/
1324	int rc = MMR3HyperReserve(pVM, PAGE_SIZE * 5, "CR3 mapping", &pVM->pgm.s.GCPtrCR3Mapping);
1325	if (RT_FAILURE(rc))
1326	{
1327	AssertMsgFailed(("Failed to reserve two pages for cr mapping in HMA, rc=%Rrc\n", rc));
1328	return rc;
1329	}
1330	MMR3HyperReserve(pVM, PAGE_SIZE, "fence", NULL);
1331
1332	/*
1333	* Allocate pages for the three possible intermediate contexts
1334	* (AMD64, PAE and plain 32-Bit). We maintain all three contexts
1335	* for the sake of simplicity. The AMD64 uses the PAE for the
1336	* lower levels, making the total number of pages 11 (3 + 7 + 1).
1337	*
1338	* We assume that two page tables will be enought for the core code
1339	* mappings (HC virtual and identity).
1340	*/
1341	pVM->pgm.s.pInterPD = (PX86PD)MMR3PageAllocLow(pVM);
1342	pVM->pgm.s.apInterPTs[0] = (PX86PT)MMR3PageAllocLow(pVM);
1343	pVM->pgm.s.apInterPTs[1] = (PX86PT)MMR3PageAllocLow(pVM);
1344	pVM->pgm.s.apInterPaePTs[0] = (PX86PTPAE)MMR3PageAlloc(pVM);
1345	pVM->pgm.s.apInterPaePTs[1] = (PX86PTPAE)MMR3PageAlloc(pVM);
1346	pVM->pgm.s.apInterPaePDs[0] = (PX86PDPAE)MMR3PageAlloc(pVM);
1347	pVM->pgm.s.apInterPaePDs[1] = (PX86PDPAE)MMR3PageAlloc(pVM);
1348	pVM->pgm.s.apInterPaePDs[2] = (PX86PDPAE)MMR3PageAlloc(pVM);
1349	pVM->pgm.s.apInterPaePDs[3] = (PX86PDPAE)MMR3PageAlloc(pVM);
1350	pVM->pgm.s.pInterPaePDPT = (PX86PDPT)MMR3PageAllocLow(pVM);
1351	pVM->pgm.s.pInterPaePDPT64 = (PX86PDPT)MMR3PageAllocLow(pVM);
1352	pVM->pgm.s.pInterPaePML4 = (PX86PML4)MMR3PageAllocLow(pVM);
1353	if ( !pVM->pgm.s.pInterPD
1354	\|\| !pVM->pgm.s.apInterPTs[0]
1355	\|\| !pVM->pgm.s.apInterPTs[1]
1356	\|\| !pVM->pgm.s.apInterPaePTs[0]
1357	\|\| !pVM->pgm.s.apInterPaePTs[1]
1358	\|\| !pVM->pgm.s.apInterPaePDs[0]
1359	\|\| !pVM->pgm.s.apInterPaePDs[1]
1360	\|\| !pVM->pgm.s.apInterPaePDs[2]
1361	\|\| !pVM->pgm.s.apInterPaePDs[3]
1362	\|\| !pVM->pgm.s.pInterPaePDPT
1363	\|\| !pVM->pgm.s.pInterPaePDPT64
1364	\|\| !pVM->pgm.s.pInterPaePML4)
1365	{
1366	AssertMsgFailed(("Failed to allocate pages for the intermediate context!\n"));
1367	return VERR_NO_PAGE_MEMORY;
1368	}
1369
1370	pVM->pgm.s.HCPhysInterPD = MMPage2Phys(pVM, pVM->pgm.s.pInterPD);
1371	AssertRelease(pVM->pgm.s.HCPhysInterPD != NIL_RTHCPHYS && !(pVM->pgm.s.HCPhysInterPD & PAGE_OFFSET_MASK));
1372	pVM->pgm.s.HCPhysInterPaePDPT = MMPage2Phys(pVM, pVM->pgm.s.pInterPaePDPT);
1373	AssertRelease(pVM->pgm.s.HCPhysInterPaePDPT != NIL_RTHCPHYS && !(pVM->pgm.s.HCPhysInterPaePDPT & PAGE_OFFSET_MASK));
1374	pVM->pgm.s.HCPhysInterPaePML4 = MMPage2Phys(pVM, pVM->pgm.s.pInterPaePML4);
1375	AssertRelease(pVM->pgm.s.HCPhysInterPaePML4 != NIL_RTHCPHYS && !(pVM->pgm.s.HCPhysInterPaePML4 & PAGE_OFFSET_MASK));
1376
1377	/*
1378	* Initialize the pages, setting up the PML4 and PDPT for repetitive 4GB action.
1379	*/
1380	ASMMemZeroPage(pVM->pgm.s.pInterPD);
1381	ASMMemZeroPage(pVM->pgm.s.apInterPTs[0]);
1382	ASMMemZeroPage(pVM->pgm.s.apInterPTs[1]);
1383
1384	ASMMemZeroPage(pVM->pgm.s.apInterPaePTs[0]);
1385	ASMMemZeroPage(pVM->pgm.s.apInterPaePTs[1]);
1386
1387	ASMMemZeroPage(pVM->pgm.s.pInterPaePDPT);
1388	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.apInterPaePDs); i++)
1389	{
1390	ASMMemZeroPage(pVM->pgm.s.apInterPaePDs[i]);
1391	pVM->pgm.s.pInterPaePDPT->a[i].u = X86_PDPE_P \| PGM_PLXFLAGS_PERMANENT
1392	\| MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[i]);
1393	}
1394
1395	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.pInterPaePDPT64->a); i++)
1396	{
1397	const unsigned iPD = i % RT_ELEMENTS(pVM->pgm.s.apInterPaePDs);
1398	pVM->pgm.s.pInterPaePDPT64->a[i].u = X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_A \| PGM_PLXFLAGS_PERMANENT
1399	\| MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[iPD]);
1400	}
1401
1402	RTHCPHYS HCPhysInterPaePDPT64 = MMPage2Phys(pVM, pVM->pgm.s.pInterPaePDPT64);
1403	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.pInterPaePML4->a); i++)
1404	pVM->pgm.s.pInterPaePML4->a[i].u = X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_A \| PGM_PLXFLAGS_PERMANENT
1405	\| HCPhysInterPaePDPT64;
1406
1407	/*
1408	* Allocate pages for the three possible guest contexts (AMD64, PAE and plain 32-Bit).
1409	* We allocate pages for all three posibilities in order to simplify mappings and
1410	* avoid resource failure during mode switches. So, we need to cover all levels of the
1411	* of the first 4GB down to PD level.
1412	* As with the intermediate context, AMD64 uses the PAE PDPT and PDs.
1413	*/
1414	pVM->pgm.s.pHC32BitPD = (PX86PD)MMR3PageAllocLow(pVM);
1415	pVM->pgm.s.apHCPaePDs[0] = (PX86PDPAE)MMR3PageAlloc(pVM);
1416	pVM->pgm.s.apHCPaePDs[1] = (PX86PDPAE)MMR3PageAlloc(pVM);
1417	AssertRelease((uintptr_t)pVM->pgm.s.apHCPaePDs[0] + PAGE_SIZE == (uintptr_t)pVM->pgm.s.apHCPaePDs[1]);
1418	pVM->pgm.s.apHCPaePDs[2] = (PX86PDPAE)MMR3PageAlloc(pVM);
1419	AssertRelease((uintptr_t)pVM->pgm.s.apHCPaePDs[1] + PAGE_SIZE == (uintptr_t)pVM->pgm.s.apHCPaePDs[2]);
1420	pVM->pgm.s.apHCPaePDs[3] = (PX86PDPAE)MMR3PageAlloc(pVM);
1421	AssertRelease((uintptr_t)pVM->pgm.s.apHCPaePDs[2] + PAGE_SIZE == (uintptr_t)pVM->pgm.s.apHCPaePDs[3]);
1422	pVM->pgm.s.pShwPaePdptR3 = (PX86PDPT)MMR3PageAllocLow(pVM);
1423	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
1424	pVM->pgm.s.pShwPaePdptR0 = (uintptr_t)pVM->pgm.s.pShwPaePdptR3;
1425	#endif
1426	pVM->pgm.s.pShwNestedRootR3 = MMR3PageAllocLow(pVM);
1427	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
1428	pVM->pgm.s.pShwNestedRootR0 = (uintptr_t)pVM->pgm.s.pShwNestedRootR3;
1429	#endif
1430
1431	if ( !pVM->pgm.s.pHC32BitPD
1432	\|\| !pVM->pgm.s.apHCPaePDs[0]
1433	\|\| !pVM->pgm.s.apHCPaePDs[1]
1434	\|\| !pVM->pgm.s.apHCPaePDs[2]
1435	\|\| !pVM->pgm.s.apHCPaePDs[3]
1436	\|\| !pVM->pgm.s.pShwPaePdptR3
1437	\|\| !pVM->pgm.s.pShwNestedRootR3)
1438	{
1439	AssertMsgFailed(("Failed to allocate pages for the intermediate context!\n"));
1440	return VERR_NO_PAGE_MEMORY;
1441	}
1442
1443	/* get physical addresses. */
1444	pVM->pgm.s.HCPhys32BitPD = MMPage2Phys(pVM, pVM->pgm.s.pHC32BitPD);
1445	Assert(MMPagePhys2Page(pVM, pVM->pgm.s.HCPhys32BitPD) == pVM->pgm.s.pHC32BitPD);
1446	pVM->pgm.s.aHCPhysPaePDs[0] = MMPage2Phys(pVM, pVM->pgm.s.apHCPaePDs[0]);
1447	pVM->pgm.s.aHCPhysPaePDs[1] = MMPage2Phys(pVM, pVM->pgm.s.apHCPaePDs[1]);
1448	pVM->pgm.s.aHCPhysPaePDs[2] = MMPage2Phys(pVM, pVM->pgm.s.apHCPaePDs[2]);
1449	pVM->pgm.s.aHCPhysPaePDs[3] = MMPage2Phys(pVM, pVM->pgm.s.apHCPaePDs[3]);
1450	pVM->pgm.s.HCPhysPaePDPT = MMPage2Phys(pVM, pVM->pgm.s.pShwPaePdptR3);
1451	pVM->pgm.s.HCPhysNestedRoot = MMPage2Phys(pVM, pVM->pgm.s.pShwNestedRootR3);
1452
1453	/*
1454	* Initialize the pages, setting up the PML4 and PDPT for action below 4GB.
1455	*/
1456	ASMMemZero32(pVM->pgm.s.pHC32BitPD, PAGE_SIZE);
1457	ASMMemZero32(pVM->pgm.s.pShwPaePdptR3, PAGE_SIZE);
1458	ASMMemZero32(pVM->pgm.s.pShwNestedRootR3, PAGE_SIZE);
1459	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.apHCPaePDs); i++)
1460	{
1461	ASMMemZero32(pVM->pgm.s.apHCPaePDs[i], PAGE_SIZE);
1462	pVM->pgm.s.pShwPaePdptR3->a[i].u = X86_PDPE_P \| PGM_PLXFLAGS_PERMANENT \| pVM->pgm.s.aHCPhysPaePDs[i];
1463	/* The flags will be corrected when entering and leaving long mode. */
1464	}
1465
1466	CPUMSetHyperCR3(pVM, (uint32_t)pVM->pgm.s.HCPhys32BitPD);
1467
1468	/*
1469	* Initialize paging workers and mode from current host mode
1470	* and the guest running in real mode.
1471	*/
1472	pVM->pgm.s.enmHostMode = SUPGetPagingMode();
1473	switch (pVM->pgm.s.enmHostMode)
1474	{
1475	case SUPPAGINGMODE_32_BIT:
1476	case SUPPAGINGMODE_32_BIT_GLOBAL:
1477	case SUPPAGINGMODE_PAE:
1478	case SUPPAGINGMODE_PAE_GLOBAL:
1479	case SUPPAGINGMODE_PAE_NX:
1480	case SUPPAGINGMODE_PAE_GLOBAL_NX:
1481	break;
1482
1483	case SUPPAGINGMODE_AMD64:
1484	case SUPPAGINGMODE_AMD64_GLOBAL:
1485	case SUPPAGINGMODE_AMD64_NX:
1486	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
1487	#ifndef VBOX_WITH_HYBIRD_32BIT_KERNEL
1488	if (ARCH_BITS != 64)
1489	{
1490	AssertMsgFailed(("Host mode %d (64-bit) is not supported by non-64bit builds\n", pVM->pgm.s.enmHostMode));
1491	LogRel(("Host mode %d (64-bit) is not supported by non-64bit builds\n", pVM->pgm.s.enmHostMode));
1492	return VERR_PGM_UNSUPPORTED_HOST_PAGING_MODE;
1493	}
1494	#endif
1495	break;
1496	default:
1497	AssertMsgFailed(("Host mode %d is not supported\n", pVM->pgm.s.enmHostMode));
1498	return VERR_PGM_UNSUPPORTED_HOST_PAGING_MODE;
1499	}
1500	rc = pgmR3ModeDataInit(pVM, false /* don't resolve GC and R0 syms yet */);
1501	if (RT_SUCCESS(rc))
1502	rc = PGMR3ChangeMode(pVM, PGMMODE_REAL);
1503	if (RT_SUCCESS(rc))
1504	{
1505	LogFlow(("pgmR3InitPaging: returns successfully\n"));
1506	#if HC_ARCH_BITS == 64
1507	LogRel(("Debug: HCPhys32BitPD=%RHp aHCPhysPaePDs={%RHp,%RHp,%RHp,%RHp} HCPhysPaePDPT=%RHp HCPhysPaePML4=%RHp\n",
1508	pVM->pgm.s.HCPhys32BitPD,
1509	pVM->pgm.s.aHCPhysPaePDs[0], pVM->pgm.s.aHCPhysPaePDs[1], pVM->pgm.s.aHCPhysPaePDs[2], pVM->pgm.s.aHCPhysPaePDs[3],
1510	pVM->pgm.s.HCPhysPaePDPT,
1511	pVM->pgm.s.HCPhysPaePML4));
1512	LogRel(("Debug: HCPhysInterPD=%RHp HCPhysInterPaePDPT=%RHp HCPhysInterPaePML4=%RHp\n",
1513	pVM->pgm.s.HCPhysInterPD, pVM->pgm.s.HCPhysInterPaePDPT, pVM->pgm.s.HCPhysInterPaePML4));
1514	LogRel(("Debug: apInterPTs={%RHp,%RHp} apInterPaePTs={%RHp,%RHp} apInterPaePDs={%RHp,%RHp,%RHp,%RHp} pInterPaePDPT64=%RHp\n",
1515	MMPage2Phys(pVM, pVM->pgm.s.apInterPTs[0]), MMPage2Phys(pVM, pVM->pgm.s.apInterPTs[1]),
1516	MMPage2Phys(pVM, pVM->pgm.s.apInterPaePTs[0]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePTs[1]),
1517	MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[0]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[1]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[2]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[3]),
1518	MMPage2Phys(pVM, pVM->pgm.s.pInterPaePDPT64)));
1519	#endif
1520
1521	return VINF_SUCCESS;
1522	}
1523
1524	LogFlow(("pgmR3InitPaging: returns %Rrc\n", rc));
1525	return rc;
1526	}
1527
1528
1529	#ifdef VBOX_WITH_STATISTICS
1530	/**
1531	* Init statistics
1532	*/
1533	static void pgmR3InitStats(PVM pVM)
1534	{
1535	PPGM pPGM = &pVM->pgm.s;
1536	unsigned i;
1537
1538	/*
1539	* Note! The layout of this function matches the member layout exactly!
1540	*/
1541
1542	/* Common - misc variables */
1543	STAM_REG(pVM, &pPGM->cAllPages, STAMTYPE_U32, "/PGM/Page/cAllPages", STAMUNIT_OCCURENCES, "The total number of pages.");
1544	STAM_REG(pVM, &pPGM->cPrivatePages, STAMTYPE_U32, "/PGM/Page/cPrivatePages", STAMUNIT_OCCURENCES, "The number of private pages.");
1545	STAM_REG(pVM, &pPGM->cSharedPages, STAMTYPE_U32, "/PGM/Page/cSharedPages", STAMUNIT_OCCURENCES, "The number of shared pages.");
1546	STAM_REG(pVM, &pPGM->cZeroPages, STAMTYPE_U32, "/PGM/Page/cZeroPages", STAMUNIT_OCCURENCES, "The number of zero backed pages.");
1547	STAM_REG(pVM, &pPGM->ChunkR3Map.c, STAMTYPE_U32, "/PGM/ChunkR3Map/c", STAMUNIT_OCCURENCES, "Number of mapped chunks.");
1548	STAM_REG(pVM, &pPGM->ChunkR3Map.cMax, STAMTYPE_U32, "/PGM/ChunkR3Map/cMax", STAMUNIT_OCCURENCES, "Maximum number of mapped chunks.");
1549
1550	/* Common - stats */
1551	#ifdef PGMPOOL_WITH_GCPHYS_TRACKING
1552	STAM_REG(pVM, &pPGM->StatTrackVirgin, STAMTYPE_COUNTER, "/PGM/Track/Virgin", STAMUNIT_OCCURENCES, "The number of first time shadowings");
1553	STAM_REG(pVM, &pPGM->StatTrackAliased, STAMTYPE_COUNTER, "/PGM/Track/Aliased", STAMUNIT_OCCURENCES, "The number of times switching to cRef2, i.e. the page is being shadowed by two PTs.");
1554	STAM_REG(pVM, &pPGM->StatTrackAliasedMany, STAMTYPE_COUNTER, "/PGM/Track/AliasedMany", STAMUNIT_OCCURENCES, "The number of times we're tracking using cRef2.");
1555	STAM_REG(pVM, &pPGM->StatTrackAliasedLots, STAMTYPE_COUNTER, "/PGM/Track/AliasedLots", STAMUNIT_OCCURENCES, "The number of times we're hitting pages which has overflowed cRef2");
1556	STAM_REG(pVM, &pPGM->StatTrackOverflows, STAMTYPE_COUNTER, "/PGM/Track/Overflows", STAMUNIT_OCCURENCES, "The number of times the extent list grows to long.");
1557	STAM_REG(pVM, &pPGM->StatTrackDeref, STAMTYPE_PROFILE, "/PGM/Track/Deref", STAMUNIT_OCCURENCES, "Profiling of SyncPageWorkerTrackDeref (expensive).");
1558	#endif
1559	for (i = 0; i < RT_ELEMENTS(pPGM->StatSyncPtPD); i++)
1560	STAMR3RegisterF(pVM, &pPGM->StatSyncPtPD[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
1561	"The number of SyncPT per PD n.", "/PGM/PDSyncPT/%04X", i);
1562	for (i = 0; i < RT_ELEMENTS(pPGM->StatSyncPagePD); i++)
1563	STAMR3RegisterF(pVM, &pPGM->StatSyncPagePD[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
1564	"The number of SyncPage per PD n.", "/PGM/PDSyncPage/%04X", i);
1565
1566	/* R3 only: */
1567	STAM_REG(pVM, &pPGM->StatR3DetectedConflicts, STAMTYPE_COUNTER, "/PGM/R3/DetectedConflicts", STAMUNIT_OCCURENCES, "The number of times PGMR3CheckMappingConflicts() detected a conflict.");
1568	STAM_REG(pVM, &pPGM->StatR3ResolveConflict, STAMTYPE_PROFILE, "/PGM/R3/ResolveConflict", STAMUNIT_TICKS_PER_CALL, "pgmR3SyncPTResolveConflict() profiling (includes the entire relocation).");
1569	STAM_REG(pVM, &pPGM->StatR3GuestPDWrite, STAMTYPE_COUNTER, "/PGM/R3/PDWrite", STAMUNIT_OCCURENCES, "The total number of times pgmHCGuestPDWriteHandler() was called.");
1570	STAM_REG(pVM, &pPGM->StatR3GuestPDWriteConflict, STAMTYPE_COUNTER, "/PGM/R3/PDWriteConflict", STAMUNIT_OCCURENCES, "The number of times pgmHCGuestPDWriteHandler() detected a conflict.");
1571	STAM_REG(pVM, &pPGM->StatR3DynRamTotal, STAMTYPE_COUNTER, "/PGM/DynAlloc/TotalAlloc", STAMUNIT_MEGABYTES, "Allocated MBs of guest ram.");
1572	STAM_REG(pVM, &pPGM->StatR3DynRamGrow, STAMTYPE_COUNTER, "/PGM/DynAlloc/Grow", STAMUNIT_OCCURENCES, "Nr of pgmr3PhysGrowRange calls.");
1573
1574	/* GC only: */
1575	STAM_REG(pVM, &pPGM->StatRCDynMapCacheHits, STAMTYPE_COUNTER, "/PGM/RC/DynMapCache/Hits" , STAMUNIT_OCCURENCES, "Number of dynamic page mapping cache hits.");
1576	STAM_REG(pVM, &pPGM->StatRCDynMapCacheMisses, STAMTYPE_COUNTER, "/PGM/RC/DynMapCache/Misses" , STAMUNIT_OCCURENCES, "Number of dynamic page mapping cache misses.");
1577	STAM_REG(pVM, &pPGM->StatRCInvlPgConflict, STAMTYPE_COUNTER, "/PGM/RC/InvlPgConflict", STAMUNIT_OCCURENCES, "Number of times PGMInvalidatePage() detected a mapping conflict.");
1578	STAM_REG(pVM, &pPGM->StatRCInvlPgSyncMonCR3, STAMTYPE_COUNTER, "/PGM/RC/InvlPgSyncMonitorCR3", STAMUNIT_OCCURENCES, "Number of times PGMInvalidatePage() ran into PGM_SYNC_MONITOR_CR3.");
1579
1580	/* RZ only: */
1581	STAM_REG(pVM, &pPGM->StatRZTrap0e, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMTrap0eHandler() body.");
1582	STAM_REG(pVM, &pPGM->StatRZTrap0eTimeCheckPageFault, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time/CheckPageFault", STAMUNIT_TICKS_PER_CALL, "Profiling of checking for dirty/access emulation faults.");
1583	STAM_REG(pVM, &pPGM->StatRZTrap0eTimeSyncPT, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time/SyncPT", STAMUNIT_TICKS_PER_CALL, "Profiling of lazy page table syncing.");
1584	STAM_REG(pVM, &pPGM->StatRZTrap0eTimeMapping, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time/Mapping", STAMUNIT_TICKS_PER_CALL, "Profiling of checking virtual mappings.");
1585	STAM_REG(pVM, &pPGM->StatRZTrap0eTimeOutOfSync, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time/OutOfSync", STAMUNIT_TICKS_PER_CALL, "Profiling of out of sync page handling.");
1586	STAM_REG(pVM, &pPGM->StatRZTrap0eTimeHandlers, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time/Handlers", STAMUNIT_TICKS_PER_CALL, "Profiling of checking handlers.");
1587	STAM_REG(pVM, &pPGM->StatRZTrap0eTime2CSAM, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time2/CSAM", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is CSAM.");
1588	STAM_REG(pVM, &pPGM->StatRZTrap0eTime2DirtyAndAccessed, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time2/DirtyAndAccessedBits", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is dirty and/or accessed bit emulation.");
1589	STAM_REG(pVM, &pPGM->StatRZTrap0eTime2GuestTrap, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time2/GuestTrap", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is a guest trap.");
1590	STAM_REG(pVM, &pPGM->StatRZTrap0eTime2HndPhys, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time2/HandlerPhysical", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is a physical handler.");
1591	STAM_REG(pVM, &pPGM->StatRZTrap0eTime2HndVirt, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time2/HandlerVirtual", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is a virtual handler.");
1592	STAM_REG(pVM, &pPGM->StatRZTrap0eTime2HndUnhandled, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time2/HandlerUnhandled", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is access outside the monitored areas of a monitored page.");
1593	STAM_REG(pVM, &pPGM->StatRZTrap0eTime2Misc, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time2/Misc", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is not known.");
1594	STAM_REG(pVM, &pPGM->StatRZTrap0eTime2OutOfSync, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time2/OutOfSync", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is an out-of-sync page.");
1595	STAM_REG(pVM, &pPGM->StatRZTrap0eTime2OutOfSyncHndPhys, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time2/OutOfSyncHndPhys", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is an out-of-sync physical handler page.");
1596	STAM_REG(pVM, &pPGM->StatRZTrap0eTime2OutOfSyncHndVirt, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time2/OutOfSyncHndVirt", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is an out-of-sync virtual handler page.");
1597	STAM_REG(pVM, &pPGM->StatRZTrap0eTime2OutOfSyncHndObs, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time2/OutOfSyncObsHnd", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is an obsolete handler page.");
1598	STAM_REG(pVM, &pPGM->StatRZTrap0eTime2SyncPT, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time2/SyncPT", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is lazy syncing of a PT.");
1599	STAM_REG(pVM, &pPGM->StatRZTrap0eConflicts, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Conflicts", STAMUNIT_OCCURENCES, "The number of times #PF was caused by an undetected conflict.");
1600	STAM_REG(pVM, &pPGM->StatRZTrap0eHandlersMapping, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Handlers/Mapping", STAMUNIT_OCCURENCES, "Number of traps due to access handlers in mappings.");
1601	STAM_REG(pVM, &pPGM->StatRZTrap0eHandlersOutOfSync, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Handlers/OutOfSync", STAMUNIT_OCCURENCES, "Number of traps due to out-of-sync handled pages.");
1602	STAM_REG(pVM, &pPGM->StatRZTrap0eHandlersPhysical, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Handlers/Physical", STAMUNIT_OCCURENCES, "Number of traps due to physical access handlers.");
1603	STAM_REG(pVM, &pPGM->StatRZTrap0eHandlersVirtual, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Handlers/Virtual", STAMUNIT_OCCURENCES, "Number of traps due to virtual access handlers.");
1604	STAM_REG(pVM, &pPGM->StatRZTrap0eHandlersVirtualByPhys, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Handlers/VirtualByPhys", STAMUNIT_OCCURENCES, "Number of traps due to virtual access handlers by physical address.");
1605	STAM_REG(pVM, &pPGM->StatRZTrap0eHandlersVirtualUnmarked,STAMTYPE_COUNTER,"/PGM/RZ/Trap0e/Handlers/VirtualUnmarked",STAMUNIT_OCCURENCES, "Number of traps due to virtual access handlers by virtual address (without proper physical flags).");
1606	STAM_REG(pVM, &pPGM->StatRZTrap0eHandlersUnhandled, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Handlers/Unhandled", STAMUNIT_OCCURENCES, "Number of traps due to access outside range of monitored page(s).");
1607	STAM_REG(pVM, &pPGM->StatRZTrap0eHandlersInvalid, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Handlers/Invalid", STAMUNIT_OCCURENCES, "Number of traps due to access to invalid physical memory.");
1608	STAM_REG(pVM, &pPGM->StatRZTrap0eUSNotPresentRead, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Err/User/NPRead", STAMUNIT_OCCURENCES, "Number of user mode not present read page faults.");
1609	STAM_REG(pVM, &pPGM->StatRZTrap0eUSNotPresentWrite, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Err/User/NPWrite", STAMUNIT_OCCURENCES, "Number of user mode not present write page faults.");
1610	STAM_REG(pVM, &pPGM->StatRZTrap0eUSWrite, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Err/User/Write", STAMUNIT_OCCURENCES, "Number of user mode write page faults.");
1611	STAM_REG(pVM, &pPGM->StatRZTrap0eUSReserved, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Err/User/Reserved", STAMUNIT_OCCURENCES, "Number of user mode reserved bit page faults.");
1612	STAM_REG(pVM, &pPGM->StatRZTrap0eUSNXE, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Err/User/NXE", STAMUNIT_OCCURENCES, "Number of user mode NXE page faults.");
1613	STAM_REG(pVM, &pPGM->StatRZTrap0eUSRead, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Err/User/Read", STAMUNIT_OCCURENCES, "Number of user mode read page faults.");
1614	STAM_REG(pVM, &pPGM->StatRZTrap0eSVNotPresentRead, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Err/Supervisor/NPRead", STAMUNIT_OCCURENCES, "Number of supervisor mode not present read page faults.");
1615	STAM_REG(pVM, &pPGM->StatRZTrap0eSVNotPresentWrite, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Err/Supervisor/NPWrite", STAMUNIT_OCCURENCES, "Number of supervisor mode not present write page faults.");
1616	STAM_REG(pVM, &pPGM->StatRZTrap0eSVWrite, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Err/Supervisor/Write", STAMUNIT_OCCURENCES, "Number of supervisor mode write page faults.");
1617	STAM_REG(pVM, &pPGM->StatRZTrap0eSVReserved, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Err/Supervisor/Reserved", STAMUNIT_OCCURENCES, "Number of supervisor mode reserved bit page faults.");
1618	STAM_REG(pVM, &pPGM->StatRZTrap0eSNXE, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Err/Supervisor/NXE", STAMUNIT_OCCURENCES, "Number of supervisor mode NXE page faults.");
1619	STAM_REG(pVM, &pPGM->StatRZTrap0eGuestPF, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/GuestPF", STAMUNIT_OCCURENCES, "Number of real guest page faults.");
1620	STAM_REG(pVM, &pPGM->StatRZTrap0eGuestPFUnh, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/GuestPF/Unhandled", STAMUNIT_OCCURENCES, "Number of real guest page faults from the 'unhandled' case.");
1621	STAM_REG(pVM, &pPGM->StatRZTrap0eGuestPFMapping, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/GuestPF/InMapping", STAMUNIT_OCCURENCES, "Number of real guest page faults in a mapping.");
1622	STAM_REG(pVM, &pPGM->StatRZTrap0eWPEmulInRZ, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/WP/InRZ", STAMUNIT_OCCURENCES, "Number of guest page faults due to X86_CR0_WP emulation.");
1623	STAM_REG(pVM, &pPGM->StatRZTrap0eWPEmulToR3, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/WP/ToR3", STAMUNIT_OCCURENCES, "Number of guest page faults due to X86_CR0_WP emulation (forward to R3 for emulation).");
1624	for (i = 0; i < RT_ELEMENTS(pPGM->StatRZTrap0ePD); i++)
1625	STAMR3RegisterF(pVM, &pPGM->StatRZTrap0ePD[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
1626	"The number of traps in page directory n.", "/PGM/RZ/Trap0e/PD/%04X", i);
1627	STAM_REG(pVM, &pPGM->StatRZGuestCR3WriteHandled, STAMTYPE_COUNTER, "/PGM/RZ/CR3WriteHandled", STAMUNIT_OCCURENCES, "The number of times the Guest CR3 change was successfully handled.");
1628	STAM_REG(pVM, &pPGM->StatRZGuestCR3WriteUnhandled, STAMTYPE_COUNTER, "/PGM/RZ/CR3WriteUnhandled", STAMUNIT_OCCURENCES, "The number of times the Guest CR3 change was passed back to the recompiler.");
1629	STAM_REG(pVM, &pPGM->StatRZGuestCR3WriteConflict, STAMTYPE_COUNTER, "/PGM/RZ/CR3WriteConflict", STAMUNIT_OCCURENCES, "The number of times the Guest CR3 monitoring detected a conflict.");
1630	STAM_REG(pVM, &pPGM->StatRZGuestROMWriteHandled, STAMTYPE_COUNTER, "/PGM/RZ/ROMWriteHandled", STAMUNIT_OCCURENCES, "The number of times the Guest ROM change was successfully handled.");
1631	STAM_REG(pVM, &pPGM->StatRZGuestROMWriteUnhandled, STAMTYPE_COUNTER, "/PGM/RZ/ROMWriteUnhandled", STAMUNIT_OCCURENCES, "The number of times the Guest ROM change was passed back to the recompiler.");
1632
1633	/* HC only: */
1634
1635	/* RZ & R3: */
1636	STAM_REG(pVM, &pPGM->StatRZSyncCR3, STAMTYPE_PROFILE, "/PGM/RZ/SyncCR3", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMSyncCR3() body.");
1637	STAM_REG(pVM, &pPGM->StatRZSyncCR3Handlers, STAMTYPE_PROFILE, "/PGM/RZ/SyncCR3/Handlers", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMSyncCR3() update handler section.");
1638	STAM_REG(pVM, &pPGM->StatRZSyncCR3HandlerVirtualUpdate, STAMTYPE_PROFILE, "/PGM/RZ/SyncCR3/Handlers/VirtualUpdate", STAMUNIT_TICKS_PER_CALL, "Profiling of the virtual handler updates.");
1639	STAM_REG(pVM, &pPGM->StatRZSyncCR3HandlerVirtualReset, STAMTYPE_PROFILE, "/PGM/RZ/SyncCR3/Handlers/VirtualReset", STAMUNIT_TICKS_PER_CALL, "Profiling of the virtual handler resets.");
1640	STAM_REG(pVM, &pPGM->StatRZSyncCR3Global, STAMTYPE_COUNTER, "/PGM/RZ/SyncCR3/Global", STAMUNIT_OCCURENCES, "The number of global CR3 syncs.");
1641	STAM_REG(pVM, &pPGM->StatRZSyncCR3NotGlobal, STAMTYPE_COUNTER, "/PGM/RZ/SyncCR3/NotGlobal", STAMUNIT_OCCURENCES, "The number of non-global CR3 syncs.");
1642	STAM_REG(pVM, &pPGM->StatRZSyncCR3DstCacheHit, STAMTYPE_COUNTER, "/PGM/RZ/SyncCR3/DstChacheHit", STAMUNIT_OCCURENCES, "The number of times we got some kind of a cache hit.");
1643	STAM_REG(pVM, &pPGM->StatRZSyncCR3DstFreed, STAMTYPE_COUNTER, "/PGM/RZ/SyncCR3/DstFreed", STAMUNIT_OCCURENCES, "The number of times we've had to free a shadow entry.");
1644	STAM_REG(pVM, &pPGM->StatRZSyncCR3DstFreedSrcNP, STAMTYPE_COUNTER, "/PGM/RZ/SyncCR3/DstFreedSrcNP", STAMUNIT_OCCURENCES, "The number of times we've had to free a shadow entry for which the source entry was not present.");
1645	STAM_REG(pVM, &pPGM->StatRZSyncCR3DstNotPresent, STAMTYPE_COUNTER, "/PGM/RZ/SyncCR3/DstNotPresent", STAMUNIT_OCCURENCES, "The number of times we've encountered a not present shadow entry for a present guest entry.");
1646	STAM_REG(pVM, &pPGM->StatRZSyncCR3DstSkippedGlobalPD, STAMTYPE_COUNTER, "/PGM/RZ/SyncCR3/DstSkippedGlobalPD", STAMUNIT_OCCURENCES, "The number of times a global page directory wasn't flushed.");
1647	STAM_REG(pVM, &pPGM->StatRZSyncCR3DstSkippedGlobalPT, STAMTYPE_COUNTER, "/PGM/RZ/SyncCR3/DstSkippedGlobalPT", STAMUNIT_OCCURENCES, "The number of times a page table with only global entries wasn't flushed.");
1648	STAM_REG(pVM, &pPGM->StatRZSyncPT, STAMTYPE_PROFILE, "/PGM/RZ/SyncPT", STAMUNIT_TICKS_PER_CALL, "Profiling of the pfnSyncPT() body.");
1649	STAM_REG(pVM, &pPGM->StatRZSyncPTFailed, STAMTYPE_COUNTER, "/PGM/RZ/SyncPT/Failed", STAMUNIT_OCCURENCES, "The number of times pfnSyncPT() failed.");
1650	STAM_REG(pVM, &pPGM->StatRZSyncPT4K, STAMTYPE_COUNTER, "/PGM/RZ/SyncPT/4K", STAMUNIT_OCCURENCES, "Nr of 4K PT syncs");
1651	STAM_REG(pVM, &pPGM->StatRZSyncPT4M, STAMTYPE_COUNTER, "/PGM/RZ/SyncPT/4M", STAMUNIT_OCCURENCES, "Nr of 4M PT syncs");
1652	STAM_REG(pVM, &pPGM->StatRZSyncPagePDNAs, STAMTYPE_COUNTER, "/PGM/RZ/SyncPagePDNAs", STAMUNIT_OCCURENCES, "The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit.");
1653	STAM_REG(pVM, &pPGM->StatRZSyncPagePDOutOfSync, STAMTYPE_COUNTER, "/PGM/RZ/SyncPagePDOutOfSync", STAMUNIT_OCCURENCES, "The number of time we've encountered an out-of-sync PD in SyncPage.");
1654	STAM_REG(pVM, &pPGM->StatRZAccessedPage, STAMTYPE_COUNTER, "/PGM/RZ/AccessedPage", STAMUNIT_OCCURENCES, "The number of pages marked not present for accessed bit emulation.");
1655	STAM_REG(pVM, &pPGM->StatRZDirtyBitTracking, STAMTYPE_PROFILE, "/PGM/RZ/DirtyPage", STAMUNIT_TICKS_PER_CALL, "Profiling the dirty bit tracking in CheckPageFault().");
1656	STAM_REG(pVM, &pPGM->StatRZDirtyPage, STAMTYPE_COUNTER, "/PGM/RZ/DirtyPage/Mark", STAMUNIT_OCCURENCES, "The number of pages marked read-only for dirty bit tracking.");
1657	STAM_REG(pVM, &pPGM->StatRZDirtyPageBig, STAMTYPE_COUNTER, "/PGM/RZ/DirtyPage/MarkBig", STAMUNIT_OCCURENCES, "The number of 4MB pages marked read-only for dirty bit tracking.");
1658	STAM_REG(pVM, &pPGM->StatRZDirtyPageSkipped, STAMTYPE_COUNTER, "/PGM/RZ/DirtyPage/Skipped", STAMUNIT_OCCURENCES, "The number of pages already dirty or readonly.");
1659	STAM_REG(pVM, &pPGM->StatRZDirtyPageTrap, STAMTYPE_COUNTER, "/PGM/RZ/DirtyPage/Trap", STAMUNIT_OCCURENCES, "The number of traps generated for dirty bit tracking.");
1660	STAM_REG(pVM, &pPGM->StatRZDirtiedPage, STAMTYPE_COUNTER, "/PGM/RZ/DirtyPage/SetDirty", STAMUNIT_OCCURENCES, "The number of pages marked dirty because of write accesses.");
1661	STAM_REG(pVM, &pPGM->StatRZDirtyTrackRealPF, STAMTYPE_COUNTER, "/PGM/RZ/DirtyPage/RealPF", STAMUNIT_OCCURENCES, "The number of real pages faults during dirty bit tracking.");
1662	STAM_REG(pVM, &pPGM->StatRZPageAlreadyDirty, STAMTYPE_COUNTER, "/PGM/RZ/DirtyPage/AlreadySet", STAMUNIT_OCCURENCES, "The number of pages already marked dirty because of write accesses.");
1663	STAM_REG(pVM, &pPGM->StatRZInvalidatePage, STAMTYPE_PROFILE, "/PGM/RZ/InvalidatePage", STAMUNIT_TICKS_PER_CALL, "PGMInvalidatePage() profiling.");
1664	STAM_REG(pVM, &pPGM->StatRZInvalidatePage4KBPages, STAMTYPE_COUNTER, "/PGM/RZ/InvalidatePage/4KBPages", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was called for a 4KB page.");
1665	STAM_REG(pVM, &pPGM->StatRZInvalidatePage4MBPages, STAMTYPE_COUNTER, "/PGM/RZ/InvalidatePage/4MBPages", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was called for a 4MB page.");
1666	STAM_REG(pVM, &pPGM->StatRZInvalidatePage4MBPagesSkip, STAMTYPE_COUNTER, "/PGM/RZ/InvalidatePage/4MBPagesSkip",STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() skipped a 4MB page.");
1667	STAM_REG(pVM, &pPGM->StatRZInvalidatePagePDMappings, STAMTYPE_COUNTER, "/PGM/RZ/InvalidatePage/PDMappings", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict).");
1668	STAM_REG(pVM, &pPGM->StatRZInvalidatePagePDNAs, STAMTYPE_COUNTER, "/PGM/RZ/InvalidatePage/PDNAs", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was called for a not accessed page directory.");
1669	STAM_REG(pVM, &pPGM->StatRZInvalidatePagePDNPs, STAMTYPE_COUNTER, "/PGM/RZ/InvalidatePage/PDNPs", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was called for a not present page directory.");
1670	STAM_REG(pVM, &pPGM->StatRZInvalidatePagePDOutOfSync, STAMTYPE_COUNTER, "/PGM/RZ/InvalidatePage/PDOutOfSync", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was called for an out of sync page directory.");
1671	STAM_REG(pVM, &pPGM->StatRZInvalidatePageSkipped, STAMTYPE_COUNTER, "/PGM/RZ/InvalidatePage/Skipped", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3.");
1672	STAM_REG(pVM, &pPGM->StatRZVirtHandlerSearchByPhys, STAMTYPE_PROFILE, "/PGM/RZ/VirtHandlerSearchByPhys", STAMUNIT_TICKS_PER_CALL, "Profiling of pgmHandlerVirtualFindByPhysAddr.");
1673	STAM_REG(pVM, &pPGM->StatRZPhysHandlerReset, STAMTYPE_COUNTER, "/PGM/RZ/PhysHandlerReset", STAMUNIT_OCCURENCES, "The number of times PGMHandlerPhysicalReset is called.");
1674	STAM_REG(pVM, &pPGM->StatRZPageOutOfSyncSupervisor, STAMTYPE_COUNTER, "/PGM/RZ/OutOfSync/SuperVisor", STAMUNIT_OCCURENCES, "Number of traps due to pages out of sync and times VerifyAccessSyncPage calls SyncPage.");
1675	STAM_REG(pVM, &pPGM->StatRZPageOutOfSyncUser, STAMTYPE_COUNTER, "/PGM/RZ/OutOfSync/User", STAMUNIT_OCCURENCES, "Number of traps due to pages out of sync and times VerifyAccessSyncPage calls SyncPage.");
1676	STAM_REG(pVM, &pPGM->StatRZPrefetch, STAMTYPE_PROFILE, "/PGM/RZ/Prefetch", STAMUNIT_TICKS_PER_CALL, "PGMPrefetchPage profiling.");
1677	STAM_REG(pVM, &pPGM->StatRZChunkR3MapTlbHits, STAMTYPE_COUNTER, "/PGM/ChunkR3Map/TlbHitsRZ", STAMUNIT_OCCURENCES, "TLB hits.");
1678	STAM_REG(pVM, &pPGM->StatRZChunkR3MapTlbMisses, STAMTYPE_COUNTER, "/PGM/ChunkR3Map/TlbMissesRZ", STAMUNIT_OCCURENCES, "TLB misses.");
1679	STAM_REG(pVM, &pPGM->StatRZPageMapTlbHits, STAMTYPE_COUNTER, "/PGM/RZ/Page/MapTlbHits", STAMUNIT_OCCURENCES, "TLB hits.");
1680	STAM_REG(pVM, &pPGM->StatRZPageMapTlbMisses, STAMTYPE_COUNTER, "/PGM/RZ/Page/MapTlbMisses", STAMUNIT_OCCURENCES, "TLB misses.");
1681	STAM_REG(pVM, &pPGM->StatRZPageReplaceShared, STAMTYPE_COUNTER, "/PGM/RZ/Page/ReplacedShared", STAMUNIT_OCCURENCES, "Times a shared page was replaced.");
1682	STAM_REG(pVM, &pPGM->StatRZPageReplaceZero, STAMTYPE_COUNTER, "/PGM/RZ/Page/ReplacedZero", STAMUNIT_OCCURENCES, "Times the zero page was replaced.");
1683	/// @todo STAM_REG(pVM, &pPGM->StatRZPageHandyAllocs, STAMTYPE_COUNTER, "/PGM/RZ/Page/HandyAllocs", STAMUNIT_OCCURENCES, "Number of times we've allocated more handy pages.");
1684	STAM_REG(pVM, &pPGM->StatRZFlushTLB, STAMTYPE_PROFILE, "/PGM/RZ/FlushTLB", STAMUNIT_OCCURENCES, "Profiling of the PGMFlushTLB() body.");
1685	STAM_REG(pVM, &pPGM->StatRZFlushTLBNewCR3, STAMTYPE_COUNTER, "/PGM/RZ/FlushTLB/NewCR3", STAMUNIT_OCCURENCES, "The number of times PGMFlushTLB was called with a new CR3, non-global. (switch)");
1686	STAM_REG(pVM, &pPGM->StatRZFlushTLBNewCR3Global, STAMTYPE_COUNTER, "/PGM/RZ/FlushTLB/NewCR3Global", STAMUNIT_OCCURENCES, "The number of times PGMFlushTLB was called with a new CR3, global. (switch)");
1687	STAM_REG(pVM, &pPGM->StatRZFlushTLBSameCR3, STAMTYPE_COUNTER, "/PGM/RZ/FlushTLB/SameCR3", STAMUNIT_OCCURENCES, "The number of times PGMFlushTLB was called with the same CR3, non-global. (flush)");
1688	STAM_REG(pVM, &pPGM->StatRZFlushTLBSameCR3Global, STAMTYPE_COUNTER, "/PGM/RZ/FlushTLB/SameCR3Global", STAMUNIT_OCCURENCES, "The number of times PGMFlushTLB was called with the same CR3, global. (flush)");
1689	STAM_REG(pVM, &pPGM->StatRZGstModifyPage, STAMTYPE_PROFILE, "/PGM/RZ/GstModifyPage", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMGstModifyPage() body.");
1690
1691	STAM_REG(pVM, &pPGM->StatR3SyncCR3, STAMTYPE_PROFILE, "/PGM/R3/SyncCR3", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMSyncCR3() body.");
1692	STAM_REG(pVM, &pPGM->StatR3SyncCR3Handlers, STAMTYPE_PROFILE, "/PGM/R3/SyncCR3/Handlers", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMSyncCR3() update handler section.");
1693	STAM_REG(pVM, &pPGM->StatR3SyncCR3HandlerVirtualUpdate, STAMTYPE_PROFILE, "/PGM/R3/SyncCR3/Handlers/VirtualUpdate", STAMUNIT_TICKS_PER_CALL, "Profiling of the virtual handler updates.");
1694	STAM_REG(pVM, &pPGM->StatR3SyncCR3HandlerVirtualReset, STAMTYPE_PROFILE, "/PGM/R3/SyncCR3/Handlers/VirtualReset", STAMUNIT_TICKS_PER_CALL, "Profiling of the virtual handler resets.");
1695	STAM_REG(pVM, &pPGM->StatR3SyncCR3Global, STAMTYPE_COUNTER, "/PGM/R3/SyncCR3/Global", STAMUNIT_OCCURENCES, "The number of global CR3 syncs.");
1696	STAM_REG(pVM, &pPGM->StatR3SyncCR3NotGlobal, STAMTYPE_COUNTER, "/PGM/R3/SyncCR3/NotGlobal", STAMUNIT_OCCURENCES, "The number of non-global CR3 syncs.");
1697	STAM_REG(pVM, &pPGM->StatR3SyncCR3DstCacheHit, STAMTYPE_COUNTER, "/PGM/R3/SyncCR3/DstChacheHit", STAMUNIT_OCCURENCES, "The number of times we got some kind of a cache hit.");
1698	STAM_REG(pVM, &pPGM->StatR3SyncCR3DstFreed, STAMTYPE_COUNTER, "/PGM/R3/SyncCR3/DstFreed", STAMUNIT_OCCURENCES, "The number of times we've had to free a shadow entry.");
1699	STAM_REG(pVM, &pPGM->StatR3SyncCR3DstFreedSrcNP, STAMTYPE_COUNTER, "/PGM/R3/SyncCR3/DstFreedSrcNP", STAMUNIT_OCCURENCES, "The number of times we've had to free a shadow entry for which the source entry was not present.");
1700	STAM_REG(pVM, &pPGM->StatR3SyncCR3DstNotPresent, STAMTYPE_COUNTER, "/PGM/R3/SyncCR3/DstNotPresent", STAMUNIT_OCCURENCES, "The number of times we've encountered a not present shadow entry for a present guest entry.");
1701	STAM_REG(pVM, &pPGM->StatR3SyncCR3DstSkippedGlobalPD, STAMTYPE_COUNTER, "/PGM/R3/SyncCR3/DstSkippedGlobalPD", STAMUNIT_OCCURENCES, "The number of times a global page directory wasn't flushed.");
1702	STAM_REG(pVM, &pPGM->StatR3SyncCR3DstSkippedGlobalPT, STAMTYPE_COUNTER, "/PGM/R3/SyncCR3/DstSkippedGlobalPT", STAMUNIT_OCCURENCES, "The number of times a page table with only global entries wasn't flushed.");
1703	STAM_REG(pVM, &pPGM->StatR3SyncPT, STAMTYPE_PROFILE, "/PGM/R3/SyncPT", STAMUNIT_TICKS_PER_CALL, "Profiling of the pfnSyncPT() body.");
1704	STAM_REG(pVM, &pPGM->StatR3SyncPTFailed, STAMTYPE_COUNTER, "/PGM/R3/SyncPT/Failed", STAMUNIT_OCCURENCES, "The number of times pfnSyncPT() failed.");
1705	STAM_REG(pVM, &pPGM->StatR3SyncPT4K, STAMTYPE_COUNTER, "/PGM/R3/SyncPT/4K", STAMUNIT_OCCURENCES, "Nr of 4K PT syncs");
1706	STAM_REG(pVM, &pPGM->StatR3SyncPT4M, STAMTYPE_COUNTER, "/PGM/R3/SyncPT/4M", STAMUNIT_OCCURENCES, "Nr of 4M PT syncs");
1707	STAM_REG(pVM, &pPGM->StatR3SyncPagePDNAs, STAMTYPE_COUNTER, "/PGM/R3/SyncPagePDNAs", STAMUNIT_OCCURENCES, "The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit.");
1708	STAM_REG(pVM, &pPGM->StatR3SyncPagePDOutOfSync, STAMTYPE_COUNTER, "/PGM/R3/SyncPagePDOutOfSync", STAMUNIT_OCCURENCES, "The number of time we've encountered an out-of-sync PD in SyncPage.");
1709	STAM_REG(pVM, &pPGM->StatR3AccessedPage, STAMTYPE_COUNTER, "/PGM/R3/AccessedPage", STAMUNIT_OCCURENCES, "The number of pages marked not present for accessed bit emulation.");
1710	STAM_REG(pVM, &pPGM->StatR3DirtyBitTracking, STAMTYPE_PROFILE, "/PGM/R3/DirtyPage", STAMUNIT_TICKS_PER_CALL, "Profiling the dirty bit tracking in CheckPageFault().");
1711	STAM_REG(pVM, &pPGM->StatR3DirtyPage, STAMTYPE_COUNTER, "/PGM/R3/DirtyPage/Mark", STAMUNIT_OCCURENCES, "The number of pages marked read-only for dirty bit tracking.");
1712	STAM_REG(pVM, &pPGM->StatR3DirtyPageBig, STAMTYPE_COUNTER, "/PGM/R3/DirtyPage/MarkBig", STAMUNIT_OCCURENCES, "The number of 4MB pages marked read-only for dirty bit tracking.");
1713	STAM_REG(pVM, &pPGM->StatR3DirtyPageSkipped, STAMTYPE_COUNTER, "/PGM/R3/DirtyPage/Skipped", STAMUNIT_OCCURENCES, "The number of pages already dirty or readonly.");
1714	STAM_REG(pVM, &pPGM->StatR3DirtyPageTrap, STAMTYPE_COUNTER, "/PGM/R3/DirtyPage/Trap", STAMUNIT_OCCURENCES, "The number of traps generated for dirty bit tracking.");
1715	STAM_REG(pVM, &pPGM->StatR3DirtiedPage, STAMTYPE_COUNTER, "/PGM/R3/DirtyPage/SetDirty", STAMUNIT_OCCURENCES, "The number of pages marked dirty because of write accesses.");
1716	STAM_REG(pVM, &pPGM->StatR3DirtyTrackRealPF, STAMTYPE_COUNTER, "/PGM/R3/DirtyPage/RealPF", STAMUNIT_OCCURENCES, "The number of real pages faults during dirty bit tracking.");
1717	STAM_REG(pVM, &pPGM->StatR3PageAlreadyDirty, STAMTYPE_COUNTER, "/PGM/R3/DirtyPage/AlreadySet", STAMUNIT_OCCURENCES, "The number of pages already marked dirty because of write accesses.");
1718	STAM_REG(pVM, &pPGM->StatR3InvalidatePage, STAMTYPE_PROFILE, "/PGM/R3/InvalidatePage", STAMUNIT_TICKS_PER_CALL, "PGMInvalidatePage() profiling.");
1719	STAM_REG(pVM, &pPGM->StatR3InvalidatePage4KBPages, STAMTYPE_COUNTER, "/PGM/R3/InvalidatePage/4KBPages", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was called for a 4KB page.");
1720	STAM_REG(pVM, &pPGM->StatR3InvalidatePage4MBPages, STAMTYPE_COUNTER, "/PGM/R3/InvalidatePage/4MBPages", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was called for a 4MB page.");
1721	STAM_REG(pVM, &pPGM->StatR3InvalidatePage4MBPagesSkip, STAMTYPE_COUNTER, "/PGM/R3/InvalidatePage/4MBPagesSkip",STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() skipped a 4MB page.");
1722	STAM_REG(pVM, &pPGM->StatR3InvalidatePagePDMappings, STAMTYPE_COUNTER, "/PGM/R3/InvalidatePage/PDMappings", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict).");
1723	STAM_REG(pVM, &pPGM->StatR3InvalidatePagePDNAs, STAMTYPE_COUNTER, "/PGM/R3/InvalidatePage/PDNAs", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was called for a not accessed page directory.");
1724	STAM_REG(pVM, &pPGM->StatR3InvalidatePagePDNPs, STAMTYPE_COUNTER, "/PGM/R3/InvalidatePage/PDNPs", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was called for a not present page directory.");
1725	STAM_REG(pVM, &pPGM->StatR3InvalidatePagePDOutOfSync, STAMTYPE_COUNTER, "/PGM/R3/InvalidatePage/PDOutOfSync", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was called for an out of sync page directory.");
1726	STAM_REG(pVM, &pPGM->StatR3InvalidatePageSkipped, STAMTYPE_COUNTER, "/PGM/R3/InvalidatePage/Skipped", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3.");
1727	STAM_REG(pVM, &pPGM->StatR3VirtHandlerSearchByPhys, STAMTYPE_PROFILE, "/PGM/R3/VirtHandlerSearchByPhys", STAMUNIT_TICKS_PER_CALL, "Profiling of pgmHandlerVirtualFindByPhysAddr.");
1728	STAM_REG(pVM, &pPGM->StatR3PhysHandlerReset, STAMTYPE_COUNTER, "/PGM/R3/PhysHandlerReset", STAMUNIT_OCCURENCES, "The number of times PGMHandlerPhysicalReset is called.");
1729	STAM_REG(pVM, &pPGM->StatR3PageOutOfSyncSupervisor, STAMTYPE_COUNTER, "/PGM/R3/OutOfSync/SuperVisor", STAMUNIT_OCCURENCES, "Number of traps due to pages out of sync and times VerifyAccessSyncPage calls SyncPage.");
1730	STAM_REG(pVM, &pPGM->StatR3PageOutOfSyncUser, STAMTYPE_COUNTER, "/PGM/R3/OutOfSync/User", STAMUNIT_OCCURENCES, "Number of traps due to pages out of sync and times VerifyAccessSyncPage calls SyncPage.");
1731	STAM_REG(pVM, &pPGM->StatR3Prefetch, STAMTYPE_PROFILE, "/PGM/R3/Prefetch", STAMUNIT_TICKS_PER_CALL, "PGMPrefetchPage profiling.");
1732	STAM_REG(pVM, &pPGM->StatR3ChunkR3MapTlbHits, STAMTYPE_COUNTER, "/PGM/ChunkR3Map/TlbHitsR3", STAMUNIT_OCCURENCES, "TLB hits.");
1733	STAM_REG(pVM, &pPGM->StatR3ChunkR3MapTlbMisses, STAMTYPE_COUNTER, "/PGM/ChunkR3Map/TlbMissesR3", STAMUNIT_OCCURENCES, "TLB misses.");
1734	STAM_REG(pVM, &pPGM->StatR3PageMapTlbHits, STAMTYPE_COUNTER, "/PGM/R3/Page/MapTlbHits", STAMUNIT_OCCURENCES, "TLB hits.");
1735	STAM_REG(pVM, &pPGM->StatR3PageMapTlbMisses, STAMTYPE_COUNTER, "/PGM/R3/Page/MapTlbMisses", STAMUNIT_OCCURENCES, "TLB misses.");
1736	STAM_REG(pVM, &pPGM->StatR3PageReplaceShared, STAMTYPE_COUNTER, "/PGM/R3/Page/ReplacedShared", STAMUNIT_OCCURENCES, "Times a shared page was replaced.");
1737	STAM_REG(pVM, &pPGM->StatR3PageReplaceZero, STAMTYPE_COUNTER, "/PGM/R3/Page/ReplacedZero", STAMUNIT_OCCURENCES, "Times the zero page was replaced.");
1738	/// @todo STAM_REG(pVM, &pPGM->StatR3PageHandyAllocs, STAMTYPE_COUNTER, "/PGM/R3/Page/HandyAllocs", STAMUNIT_OCCURENCES, "Number of times we've allocated more handy pages.");
1739	STAM_REG(pVM, &pPGM->StatR3FlushTLB, STAMTYPE_PROFILE, "/PGM/R3/FlushTLB", STAMUNIT_OCCURENCES, "Profiling of the PGMFlushTLB() body.");
1740	STAM_REG(pVM, &pPGM->StatR3FlushTLBNewCR3, STAMTYPE_COUNTER, "/PGM/R3/FlushTLB/NewCR3", STAMUNIT_OCCURENCES, "The number of times PGMFlushTLB was called with a new CR3, non-global. (switch)");
1741	STAM_REG(pVM, &pPGM->StatR3FlushTLBNewCR3Global, STAMTYPE_COUNTER, "/PGM/R3/FlushTLB/NewCR3Global", STAMUNIT_OCCURENCES, "The number of times PGMFlushTLB was called with a new CR3, global. (switch)");
1742	STAM_REG(pVM, &pPGM->StatR3FlushTLBSameCR3, STAMTYPE_COUNTER, "/PGM/R3/FlushTLB/SameCR3", STAMUNIT_OCCURENCES, "The number of times PGMFlushTLB was called with the same CR3, non-global. (flush)");
1743	STAM_REG(pVM, &pPGM->StatR3FlushTLBSameCR3Global, STAMTYPE_COUNTER, "/PGM/R3/FlushTLB/SameCR3Global", STAMUNIT_OCCURENCES, "The number of times PGMFlushTLB was called with the same CR3, global. (flush)");
1744	STAM_REG(pVM, &pPGM->StatR3GstModifyPage, STAMTYPE_PROFILE, "/PGM/R3/GstModifyPage", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMGstModifyPage() body.");
1745
1746	}
1747	#endif /* VBOX_WITH_STATISTICS */
1748
1749
1750	/**
1751	* Init the PGM bits that rely on VMMR0 and MM to be fully initialized.
1752	*
1753	* The dynamic mapping area will also be allocated and initialized at this
1754	* time. We could allocate it during PGMR3Init of course, but the mapping
1755	* wouldn't be allocated at that time preventing us from setting up the
1756	* page table entries with the dummy page.
1757	*
1758	* @returns VBox status code.
1759	* @param pVM VM handle.
1760	*/
1761	VMMR3DECL(int) PGMR3InitDynMap(PVM pVM)
1762	{
1763	RTGCPTR GCPtr;
1764	/*
1765	* Reserve space for mapping the paging pages into guest context.
1766	*/
1767	int rc = MMR3HyperReserve(pVM, PAGE_SIZE * (2 + RT_ELEMENTS(pVM->pgm.s.apHCPaePDs) + 1 + 2 + 2), "Paging", &GCPtr);
1768	AssertRCReturn(rc, rc);
1769	pVM->pgm.s.pGC32BitPD = GCPtr;
1770	MMR3HyperReserve(pVM, PAGE_SIZE, "fence", NULL);
1771
1772	/*
1773	* Reserve space for the dynamic mappings.
1774	*/
1775	rc = MMR3HyperReserve(pVM, MM_HYPER_DYNAMIC_SIZE, "Dynamic mapping", &GCPtr);
1776	if (RT_SUCCESS(rc))
1777	pVM->pgm.s.pbDynPageMapBaseGC = GCPtr;
1778
1779	if ( RT_SUCCESS(rc)
1780	&& (pVM->pgm.s.pbDynPageMapBaseGC >> X86_PD_PAE_SHIFT) != ((pVM->pgm.s.pbDynPageMapBaseGC + MM_HYPER_DYNAMIC_SIZE - 1) >> X86_PD_PAE_SHIFT))
1781	{
1782	rc = MMR3HyperReserve(pVM, MM_HYPER_DYNAMIC_SIZE, "Dynamic mapping not crossing", &GCPtr);
1783	if (RT_SUCCESS(rc))
1784	pVM->pgm.s.pbDynPageMapBaseGC = GCPtr;
1785	}
1786	if (RT_SUCCESS(rc))
1787	{
1788	AssertRelease((pVM->pgm.s.pbDynPageMapBaseGC >> X86_PD_PAE_SHIFT) == ((pVM->pgm.s.pbDynPageMapBaseGC + MM_HYPER_DYNAMIC_SIZE - 1) >> X86_PD_PAE_SHIFT));
1789	MMR3HyperReserve(pVM, PAGE_SIZE, "fence", NULL);
1790	}
1791	return rc;
1792	}
1793
1794
1795	/**
1796	* Ring-3 init finalizing.
1797	*
1798	* @returns VBox status code.
1799	* @param pVM The VM handle.
1800	*/
1801	VMMR3DECL(int) PGMR3InitFinalize(PVM pVM)
1802	{
1803	/*
1804	* Map the paging pages into the guest context.
1805	*/
1806	RTGCPTR GCPtr = pVM->pgm.s.pGC32BitPD;
1807	AssertReleaseReturn(GCPtr, VERR_INTERNAL_ERROR);
1808
1809	int rc = PGMMap(pVM, GCPtr, pVM->pgm.s.HCPhys32BitPD, PAGE_SIZE, 0);
1810	AssertRCReturn(rc, rc);
1811	pVM->pgm.s.pGC32BitPD = GCPtr;
1812	GCPtr += PAGE_SIZE;
1813	GCPtr += PAGE_SIZE; /* reserved page */
1814
1815	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.apHCPaePDs); i++)
1816	{
1817	rc = PGMMap(pVM, GCPtr, pVM->pgm.s.aHCPhysPaePDs[i], PAGE_SIZE, 0);
1818	AssertRCReturn(rc, rc);
1819	pVM->pgm.s.apGCPaePDs[i] = GCPtr;
1820	GCPtr += PAGE_SIZE;
1821	}
1822	/* A bit of paranoia is justified. */
1823	AssertRelease(pVM->pgm.s.apGCPaePDs[0] + PAGE_SIZE == pVM->pgm.s.apGCPaePDs[1]);
1824	AssertRelease(pVM->pgm.s.apGCPaePDs[1] + PAGE_SIZE == pVM->pgm.s.apGCPaePDs[2]);
1825	AssertRelease(pVM->pgm.s.apGCPaePDs[2] + PAGE_SIZE == pVM->pgm.s.apGCPaePDs[3]);
1826	GCPtr += PAGE_SIZE; /* reserved page */
1827
1828	rc = PGMMap(pVM, GCPtr, pVM->pgm.s.HCPhysPaePDPT, PAGE_SIZE, 0);
1829	AssertRCReturn(rc, rc);
1830	pVM->pgm.s.pShwPaePdptRC = GCPtr;
1831	GCPtr += PAGE_SIZE;
1832	GCPtr += PAGE_SIZE; /* reserved page */
1833
1834
1835	/*
1836	* Reserve space for the dynamic mappings.
1837	* Initialize the dynamic mapping pages with dummy pages to simply the cache.
1838	*/
1839	/* get the pointer to the page table entries. */
1840	PPGMMAPPING pMapping = pgmGetMapping(pVM, pVM->pgm.s.pbDynPageMapBaseGC);
1841	AssertRelease(pMapping);
1842	const uintptr_t off = pVM->pgm.s.pbDynPageMapBaseGC - pMapping->GCPtr;
1843	const unsigned iPT = off >> X86_PD_SHIFT;
1844	const unsigned iPG = (off >> X86_PT_SHIFT) & X86_PT_MASK;
1845	pVM->pgm.s.paDynPageMap32BitPTEsGC = pMapping->aPTs[iPT].pPTRC + iPG * sizeof(pMapping->aPTs[0].pPTR3->a[0]);
1846	pVM->pgm.s.paDynPageMapPaePTEsGC = pMapping->aPTs[iPT].paPaePTsRC + iPG * sizeof(pMapping->aPTs[0].paPaePTsR3->a[0]);
1847
1848	/* init cache */
1849	RTHCPHYS HCPhysDummy = MMR3PageDummyHCPhys(pVM);
1850	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.aHCPhysDynPageMapCache); i++)
1851	pVM->pgm.s.aHCPhysDynPageMapCache[i] = HCPhysDummy;
1852
1853	for (unsigned i = 0; i < MM_HYPER_DYNAMIC_SIZE; i += PAGE_SIZE)
1854	{
1855	rc = PGMMap(pVM, pVM->pgm.s.pbDynPageMapBaseGC + i, HCPhysDummy, PAGE_SIZE, 0);
1856	AssertRCReturn(rc, rc);
1857	}
1858
1859	/*
1860	* Note that AMD uses all the 8 reserved bits for the address (so 40 bits in total);
1861	* Intel only goes up to 36 bits, so we stick to 36 as well.
1862	*/
1863	/** @todo How to test for the 40 bits support? Long mode seems to be the test criterium. */
1864	uint32_t u32Dummy, u32Features;
1865	CPUMGetGuestCpuId(pVM, 1, &u32Dummy, &u32Dummy, &u32Dummy, &u32Features);
1866
1867	if (u32Features & X86_CPUID_FEATURE_EDX_PSE36)
1868	pVM->pgm.s.GCPhys4MBPSEMask = RT_BIT_64(36) - 1;
1869	else
1870	pVM->pgm.s.GCPhys4MBPSEMask = RT_BIT_64(32) - 1;
1871
1872	LogRel(("PGMR3InitFinalize: 4 MB PSE mask %RGp\n", pVM->pgm.s.GCPhys4MBPSEMask));
1873
1874	return rc;
1875	}
1876
1877
1878	/**
1879	* Applies relocations to data and code managed by this component.
1880	*
1881	* This function will be called at init and whenever the VMM need to relocate it
1882	* self inside the GC.
1883	*
1884	* @param pVM The VM.
1885	* @param offDelta Relocation delta relative to old location.
1886	*/
1887	VMMR3DECL(void) PGMR3Relocate(PVM pVM, RTGCINTPTR offDelta)
1888	{
1889	LogFlow(("PGMR3Relocate\n"));
1890
1891	/*
1892	* Paging stuff.
1893	*/
1894	pVM->pgm.s.GCPtrCR3Mapping += offDelta;
1895	/** @todo move this into shadow and guest specific relocation functions. */
1896	AssertMsg(pVM->pgm.s.pGC32BitPD, ("Init order, no relocation before paging is initialized!\n"));
1897	pVM->pgm.s.pGC32BitPD += offDelta;
1898	pVM->pgm.s.pGuestPDRC += offDelta;
1899	AssertCompile(RT_ELEMENTS(pVM->pgm.s.apGCPaePDs) == RT_ELEMENTS(pVM->pgm.s.apGstPaePDsRC));
1900	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.apGCPaePDs); i++)
1901	{
1902	pVM->pgm.s.apGCPaePDs[i] += offDelta;
1903	pVM->pgm.s.apGstPaePDsRC[i] += offDelta;
1904	}
1905	pVM->pgm.s.pGstPaePDPTRC += offDelta;
1906	pVM->pgm.s.pShwPaePdptRC += offDelta;
1907
1908	pgmR3ModeDataInit(pVM, true /* resolve GC/R0 symbols */);
1909	pgmR3ModeDataSwitch(pVM, pVM->pgm.s.enmShadowMode, pVM->pgm.s.enmGuestMode);
1910
1911	PGM_SHW_PFN(Relocate, pVM)(pVM, offDelta);
1912	PGM_GST_PFN(Relocate, pVM)(pVM, offDelta);
1913	PGM_BTH_PFN(Relocate, pVM)(pVM, offDelta);
1914
1915	/*
1916	* Trees.
1917	*/
1918	pVM->pgm.s.pTreesRC = MMHyperR3ToRC(pVM, pVM->pgm.s.pTreesR3);
1919
1920	/*
1921	* Ram ranges.
1922	*/
1923	if (pVM->pgm.s.pRamRangesR3)
1924	{
1925	pVM->pgm.s.pRamRangesRC = MMHyperR3ToRC(pVM, pVM->pgm.s.pRamRangesR3);
1926	for (PPGMRAMRANGE pCur = pVM->pgm.s.pRamRangesR3; pCur->pNextR3; pCur = pCur->pNextR3)
1927	pCur->pNextRC = MMHyperR3ToRC(pVM, pCur->pNextR3);
1928	}
1929
1930	/*
1931	* Update the two page directories with all page table mappings.
1932	* (One or more of them have changed, that's why we're here.)
1933	*/
1934	pVM->pgm.s.pMappingsRC = MMHyperR3ToRC(pVM, pVM->pgm.s.pMappingsR3);
1935	for (PPGMMAPPING pCur = pVM->pgm.s.pMappingsR3; pCur->pNextR3; pCur = pCur->pNextR3)
1936	pCur->pNextRC = MMHyperR3ToRC(pVM, pCur->pNextR3);
1937
1938	/* Relocate GC addresses of Page Tables. */
1939	for (PPGMMAPPING pCur = pVM->pgm.s.pMappingsR3; pCur; pCur = pCur->pNextR3)
1940	{
1941	for (RTHCUINT i = 0; i < pCur->cPTs; i++)
1942	{
1943	pCur->aPTs[i].pPTRC = MMHyperR3ToRC(pVM, pCur->aPTs[i].pPTR3);
1944	pCur->aPTs[i].paPaePTsRC = MMHyperR3ToRC(pVM, pCur->aPTs[i].paPaePTsR3);
1945	}
1946	}
1947
1948	/*
1949	* Dynamic page mapping area.
1950	*/
1951	pVM->pgm.s.paDynPageMap32BitPTEsGC += offDelta;
1952	pVM->pgm.s.paDynPageMapPaePTEsGC += offDelta;
1953	pVM->pgm.s.pbDynPageMapBaseGC += offDelta;
1954
1955	/*
1956	* The Zero page.
1957	*/
1958	pVM->pgm.s.pvZeroPgR0 = MMHyperR3ToR0(pVM, pVM->pgm.s.pvZeroPgR3);
1959	AssertRelease(pVM->pgm.s.pvZeroPgR0);
1960
1961	/*
1962	* Physical and virtual handlers.
1963	*/
1964	RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysHandlers, true, pgmR3RelocatePhysHandler, &offDelta);
1965	RTAvlroGCPtrDoWithAll(&pVM->pgm.s.pTreesR3->VirtHandlers, true, pgmR3RelocateVirtHandler, &offDelta);
1966	RTAvlroGCPtrDoWithAll(&pVM->pgm.s.pTreesR3->HyperVirtHandlers, true, pgmR3RelocateHyperVirtHandler, &offDelta);
1967
1968	/*
1969	* The page pool.
1970	*/
1971	pgmR3PoolRelocate(pVM);
1972	}
1973
1974
1975	/**
1976	* Callback function for relocating a physical access handler.
1977	*
1978	* @returns 0 (continue enum)
1979	* @param pNode Pointer to a PGMPHYSHANDLER node.
1980	* @param pvUser Pointer to the offDelta. This is a pointer to the delta since we're
1981	* not certain the delta will fit in a void pointer for all possible configs.
1982	*/
1983	static DECLCALLBACK(int) pgmR3RelocatePhysHandler(PAVLROGCPHYSNODECORE pNode, void *pvUser)
1984	{
1985	PPGMPHYSHANDLER pHandler = (PPGMPHYSHANDLER)pNode;
1986	RTGCINTPTR offDelta = *(PRTGCINTPTR)pvUser;
1987	if (pHandler->pfnHandlerRC)
1988	pHandler->pfnHandlerRC += offDelta;
1989	if (pHandler->pvUserRC >= 0x10000)
1990	pHandler->pvUserRC += offDelta;
1991	return 0;
1992	}
1993
1994
1995	/**
1996	* Callback function for relocating a virtual access handler.
1997	*
1998	* @returns 0 (continue enum)
1999	* @param pNode Pointer to a PGMVIRTHANDLER node.
2000	* @param pvUser Pointer to the offDelta. This is a pointer to the delta since we're
2001	* not certain the delta will fit in a void pointer for all possible configs.
2002	*/
2003	static DECLCALLBACK(int) pgmR3RelocateVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser)
2004	{
2005	PPGMVIRTHANDLER pHandler = (PPGMVIRTHANDLER)pNode;
2006	RTGCINTPTR offDelta = *(PRTGCINTPTR)pvUser;
2007	Assert( pHandler->enmType == PGMVIRTHANDLERTYPE_ALL
2008	\|\| pHandler->enmType == PGMVIRTHANDLERTYPE_WRITE);
2009	Assert(pHandler->pfnHandlerRC);
2010	pHandler->pfnHandlerRC += offDelta;
2011	return 0;
2012	}
2013
2014
2015	/**
2016	* Callback function for relocating a virtual access handler for the hypervisor mapping.
2017	*
2018	* @returns 0 (continue enum)
2019	* @param pNode Pointer to a PGMVIRTHANDLER node.
2020	* @param pvUser Pointer to the offDelta. This is a pointer to the delta since we're
2021	* not certain the delta will fit in a void pointer for all possible configs.
2022	*/
2023	static DECLCALLBACK(int) pgmR3RelocateHyperVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser)
2024	{
2025	PPGMVIRTHANDLER pHandler = (PPGMVIRTHANDLER)pNode;
2026	RTGCINTPTR offDelta = *(PRTGCINTPTR)pvUser;
2027	Assert(pHandler->enmType == PGMVIRTHANDLERTYPE_HYPERVISOR);
2028	Assert(pHandler->pfnHandlerRC);
2029	pHandler->pfnHandlerRC += offDelta;
2030	return 0;
2031	}
2032
2033
2034	/**
2035	* The VM is being reset.
2036	*
2037	* For the PGM component this means that any PD write monitors
2038	* needs to be removed.
2039	*
2040	* @param pVM VM handle.
2041	*/
2042	VMMR3DECL(void) PGMR3Reset(PVM pVM)
2043	{
2044	LogFlow(("PGMR3Reset:\n"));
2045	VM_ASSERT_EMT(pVM);
2046
2047	pgmLock(pVM);
2048
2049	/*
2050	* Unfix any fixed mappings and disable CR3 monitoring.
2051	*/
2052	pVM->pgm.s.fMappingsFixed = false;
2053	pVM->pgm.s.GCPtrMappingFixed = 0;
2054	pVM->pgm.s.cbMappingFixed = 0;
2055
2056	/* Exit the guest paging mode before the pgm pool gets reset.
2057	* Important to clean up the amd64 case.
2058	*/
2059	int rc = PGM_GST_PFN(Exit, pVM)(pVM);
2060	AssertRC(rc);
2061	#ifdef DEBUG
2062	DBGFR3InfoLog(pVM, "mappings", NULL);
2063	DBGFR3InfoLog(pVM, "handlers", "all nostat");
2064	#endif
2065
2066	/*
2067	* Reset the shadow page pool.
2068	*/
2069	pgmR3PoolReset(pVM);
2070
2071	/*
2072	* Re-init other members.
2073	*/
2074	pVM->pgm.s.fA20Enabled = true;
2075
2076	/*
2077	* Clear the FFs PGM owns.
2078	*/
2079	VM_FF_CLEAR(pVM, VM_FF_PGM_SYNC_CR3);
2080	VM_FF_CLEAR(pVM, VM_FF_PGM_SYNC_CR3_NON_GLOBAL);
2081
2082	/*
2083	* Reset (zero) RAM pages.
2084	*/
2085	rc = pgmR3PhysRamReset(pVM);
2086	if (RT_SUCCESS(rc))
2087	{
2088	#ifdef VBOX_WITH_NEW_PHYS_CODE
2089	/*
2090	* Reset (zero) shadow ROM pages.
2091	*/
2092	rc = pgmR3PhysRomReset(pVM);
2093	#endif
2094	if (RT_SUCCESS(rc))
2095	{
2096	/*
2097	* Switch mode back to real mode.
2098	*/
2099	rc = PGMR3ChangeMode(pVM, PGMMODE_REAL);
2100	STAM_REL_COUNTER_RESET(&pVM->pgm.s.cGuestModeChanges);
2101	}
2102	}
2103
2104	pgmUnlock(pVM);
2105	//return rc;
2106	AssertReleaseRC(rc);
2107	}
2108
2109
2110	#ifdef VBOX_STRICT
2111	/**
2112	* VM state change callback for clearing fNoMorePhysWrites after
2113	* a snapshot has been created.
2114	*/
2115	static DECLCALLBACK(void) pgmR3ResetNoMorePhysWritesFlag(PVM pVM, VMSTATE enmState, VMSTATE enmOldState, void *pvUser)
2116	{
2117	if (enmState == VMSTATE_RUNNING)
2118	pVM->pgm.s.fNoMorePhysWrites = false;
2119	}
2120	#endif
2121
2122
2123	/**
2124	* Terminates the PGM.
2125	*
2126	* @returns VBox status code.
2127	* @param pVM Pointer to VM structure.
2128	*/
2129	VMMR3DECL(int) PGMR3Term(PVM pVM)
2130	{
2131	return PDMR3CritSectDelete(&pVM->pgm.s.CritSect);
2132	}
2133
2134
2135	/**
2136	* Terminates the per-VCPU PGM.
2137	*
2138	* Termination means cleaning up and freeing all resources,
2139	* the VM it self is at this point powered off or suspended.
2140	*
2141	* @returns VBox status code.
2142	* @param pVM The VM to operate on.
2143	*/
2144	VMMR3DECL(int) PGMR3TermCPU(PVM pVM)
2145	{
2146	return 0;
2147	}
2148
2149
2150	/**
2151	* Execute state save operation.
2152	*
2153	* @returns VBox status code.
2154	* @param pVM VM Handle.
2155	* @param pSSM SSM operation handle.
2156	*/
2157	static DECLCALLBACK(int) pgmR3Save(PVM pVM, PSSMHANDLE pSSM)
2158	{
2159	PPGM pPGM = &pVM->pgm.s;
2160
2161	/* No more writes to physical memory after this point! */
2162	pVM->pgm.s.fNoMorePhysWrites = true;
2163
2164	/*
2165	* Save basic data (required / unaffected by relocation).
2166	*/
2167	#if 1
2168	SSMR3PutBool(pSSM, pPGM->fMappingsFixed);
2169	#else
2170	SSMR3PutUInt(pSSM, pPGM->fMappingsFixed);
2171	#endif
2172	SSMR3PutGCPtr(pSSM, pPGM->GCPtrMappingFixed);
2173	SSMR3PutU32(pSSM, pPGM->cbMappingFixed);
2174	SSMR3PutUInt(pSSM, pPGM->cbRamSize);
2175	SSMR3PutGCPhys(pSSM, pPGM->GCPhysA20Mask);
2176	SSMR3PutUInt(pSSM, pPGM->fA20Enabled);
2177	SSMR3PutUInt(pSSM, pPGM->fSyncFlags);
2178	SSMR3PutUInt(pSSM, pPGM->enmGuestMode);
2179	SSMR3PutU32(pSSM, ~0); /* Separator. */
2180
2181	/*
2182	* The guest mappings.
2183	*/
2184	uint32_t i = 0;
2185	for (PPGMMAPPING pMapping = pPGM->pMappingsR3; pMapping; pMapping = pMapping->pNextR3, i++)
2186	{
2187	SSMR3PutU32(pSSM, i);
2188	SSMR3PutStrZ(pSSM, pMapping->pszDesc); /* This is the best unique id we have... */
2189	SSMR3PutGCPtr(pSSM, pMapping->GCPtr);
2190	SSMR3PutGCUIntPtr(pSSM, pMapping->cPTs);
2191	/* flags are done by the mapping owners! */
2192	}
2193	SSMR3PutU32(pSSM, ~0); /* terminator. */
2194
2195	/*
2196	* Ram range flags and bits.
2197	*/
2198	i = 0;
2199	for (PPGMRAMRANGE pRam = pPGM->pRamRangesR3; pRam; pRam = pRam->pNextR3, i++)
2200	{
2201	/** @todo MMIO ranges may move (PCI reconfig), we currently assume they don't. */
2202
2203	SSMR3PutU32(pSSM, i);
2204	SSMR3PutGCPhys(pSSM, pRam->GCPhys);
2205	SSMR3PutGCPhys(pSSM, pRam->GCPhysLast);
2206	SSMR3PutGCPhys(pSSM, pRam->cb);
2207	SSMR3PutU8(pSSM, !!pRam->pvR3); /* boolean indicating memory or not. */
2208
2209	/* Flags. */
2210	const unsigned cPages = pRam->cb >> PAGE_SHIFT;
2211	for (unsigned iPage = 0; iPage < cPages; iPage++)
2212	SSMR3PutU16(pSSM, (uint16_t)(pRam->aPages[iPage].HCPhys & ~X86_PTE_PAE_PG_MASK)); /** @todo PAGE FLAGS */
2213
2214	/* any memory associated with the range. */
2215	if (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)
2216	{
2217	for (unsigned iChunk = 0; iChunk < (pRam->cb >> PGM_DYNAMIC_CHUNK_SHIFT); iChunk++)
2218	{
2219	if (pRam->paChunkR3Ptrs[iChunk])
2220	{
2221	SSMR3PutU8(pSSM, 1); /* chunk present */
2222	SSMR3PutMem(pSSM, (void *)pRam->paChunkR3Ptrs[iChunk], PGM_DYNAMIC_CHUNK_SIZE);
2223	}
2224	else
2225	SSMR3PutU8(pSSM, 0); /* no chunk present */
2226	}
2227	}
2228	else if (pRam->pvR3)
2229	{
2230	int rc = SSMR3PutMem(pSSM, pRam->pvR3, pRam->cb);
2231	if (RT_FAILURE(rc))
2232	{
2233	Log(("pgmR3Save: SSMR3PutMem(, %p, %#x) -> %Rrc\n", pRam->pvR3, pRam->cb, rc));
2234	return rc;
2235	}
2236	}
2237	}
2238	return SSMR3PutU32(pSSM, ~0); /* terminator. */
2239	}
2240
2241
2242	/**
2243	* Execute state load operation.
2244	*
2245	* @returns VBox status code.
2246	* @param pVM VM Handle.
2247	* @param pSSM SSM operation handle.
2248	* @param u32Version Data layout version.
2249	*/
2250	static DECLCALLBACK(int) pgmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version)
2251	{
2252	/*
2253	* Validate version.
2254	*/
2255	if (u32Version != PGM_SAVED_STATE_VERSION)
2256	{
2257	AssertMsgFailed(("pgmR3Load: Invalid version u32Version=%d (current %d)!\n", u32Version, PGM_SAVED_STATE_VERSION));
2258	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
2259	}
2260
2261	/*
2262	* Call the reset function to make sure all the memory is cleared.
2263	*/
2264	PGMR3Reset(pVM);
2265
2266	/*
2267	* Load basic data (required / unaffected by relocation).
2268	*/
2269	PPGM pPGM = &pVM->pgm.s;
2270	#if 1
2271	SSMR3GetBool(pSSM, &pPGM->fMappingsFixed);
2272	#else
2273	uint32_t u;
2274	SSMR3GetU32(pSSM, &u);
2275	pPGM->fMappingsFixed = u;
2276	#endif
2277	SSMR3GetGCPtr(pSSM, &pPGM->GCPtrMappingFixed);
2278	SSMR3GetU32(pSSM, &pPGM->cbMappingFixed);
2279
2280	RTUINT cbRamSize;
2281	int rc = SSMR3GetU32(pSSM, &cbRamSize);
2282	if (RT_FAILURE(rc))
2283	return rc;
2284	if (cbRamSize != pPGM->cbRamSize)
2285	return VERR_SSM_LOAD_MEMORY_SIZE_MISMATCH;
2286	SSMR3GetGCPhys(pSSM, &pPGM->GCPhysA20Mask);
2287	SSMR3GetUInt(pSSM, &pPGM->fA20Enabled);
2288	SSMR3GetUInt(pSSM, &pPGM->fSyncFlags);
2289	RTUINT uGuestMode;
2290	SSMR3GetUInt(pSSM, &uGuestMode);
2291	pPGM->enmGuestMode = (PGMMODE)uGuestMode;
2292
2293	/* check separator. */
2294	uint32_t u32Sep;
2295	SSMR3GetU32(pSSM, &u32Sep);
2296	if (RT_FAILURE(rc))
2297	return rc;
2298	if (u32Sep != (uint32_t)~0)
2299	{
2300	AssertMsgFailed(("u32Sep=%#x (first)\n", u32Sep));
2301	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2302	}
2303
2304	/*
2305	* The guest mappings.
2306	*/
2307	uint32_t i = 0;
2308	for (;; i++)
2309	{
2310	/* Check the seqence number / separator. */
2311	rc = SSMR3GetU32(pSSM, &u32Sep);
2312	if (RT_FAILURE(rc))
2313	return rc;
2314	if (u32Sep == ~0U)
2315	break;
2316	if (u32Sep != i)
2317	{
2318	AssertMsgFailed(("u32Sep=%#x (last)\n", u32Sep));
2319	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2320	}
2321
2322	/* get the mapping details. */
2323	char szDesc[256];
2324	szDesc[0] = '\0';
2325	rc = SSMR3GetStrZ(pSSM, szDesc, sizeof(szDesc));
2326	if (RT_FAILURE(rc))
2327	return rc;
2328	RTGCPTR GCPtr;
2329	SSMR3GetGCPtr(pSSM, &GCPtr);
2330	RTGCPTR cPTs;
2331	rc = SSMR3GetGCUIntPtr(pSSM, &cPTs);
2332	if (RT_FAILURE(rc))
2333	return rc;
2334
2335	/* find matching range. */
2336	PPGMMAPPING pMapping;
2337	for (pMapping = pPGM->pMappingsR3; pMapping; pMapping = pMapping->pNextR3)
2338	if ( pMapping->cPTs == cPTs
2339	&& !strcmp(pMapping->pszDesc, szDesc))
2340	break;
2341	if (!pMapping)
2342	{
2343	LogRel(("Couldn't find mapping: cPTs=%#x szDesc=%s (GCPtr=%RGv)\n",
2344	cPTs, szDesc, GCPtr));
2345	AssertFailed();
2346	return VERR_SSM_LOAD_CONFIG_MISMATCH;
2347	}
2348
2349	/* relocate it. */
2350	if (pMapping->GCPtr != GCPtr)
2351	{
2352	AssertMsg((GCPtr >> X86_PD_SHIFT << X86_PD_SHIFT) == GCPtr, ("GCPtr=%RGv\n", GCPtr));
2353	pgmR3MapRelocate(pVM, pMapping, pMapping->GCPtr, GCPtr);
2354	}
2355	else
2356	Log(("pgmR3Load: '%s' needed no relocation (%RGv)\n", szDesc, GCPtr));
2357	}
2358
2359	/*
2360	* Ram range flags and bits.
2361	*/
2362	i = 0;
2363	for (PPGMRAMRANGE pRam = pPGM->pRamRangesR3; pRam; pRam = pRam->pNextR3, i++)
2364	{
2365	/** @todo MMIO ranges may move (PCI reconfig), we currently assume they don't. */
2366	/* Check the seqence number / separator. */
2367	rc = SSMR3GetU32(pSSM, &u32Sep);
2368	if (RT_FAILURE(rc))
2369	return rc;
2370	if (u32Sep == ~0U)
2371	break;
2372	if (u32Sep != i)
2373	{
2374	AssertMsgFailed(("u32Sep=%#x (last)\n", u32Sep));
2375	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2376	}
2377
2378	/* Get the range details. */
2379	RTGCPHYS GCPhys;
2380	SSMR3GetGCPhys(pSSM, &GCPhys);
2381	RTGCPHYS GCPhysLast;
2382	SSMR3GetGCPhys(pSSM, &GCPhysLast);
2383	RTGCPHYS cb;
2384	SSMR3GetGCPhys(pSSM, &cb);
2385	uint8_t fHaveBits;
2386	rc = SSMR3GetU8(pSSM, &fHaveBits);
2387	if (RT_FAILURE(rc))
2388	return rc;
2389	if (fHaveBits & ~1)
2390	{
2391	AssertMsgFailed(("u32Sep=%#x (last)\n", u32Sep));
2392	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2393	}
2394
2395	/* Match it up with the current range. */
2396	if ( GCPhys != pRam->GCPhys
2397	\|\| GCPhysLast != pRam->GCPhysLast
2398	\|\| cb != pRam->cb
2399	\|\| fHaveBits != !!pRam->pvR3)
2400	{
2401	LogRel(("Ram range: %RGp-%RGp %RGp bytes %s\n"
2402	"State : %RGp-%RGp %RGp bytes %s\n",
2403	pRam->GCPhys, pRam->GCPhysLast, pRam->cb, pRam->pvR3 ? "bits" : "nobits",
2404	GCPhys, GCPhysLast, cb, fHaveBits ? "bits" : "nobits"));
2405	/*
2406	* If we're loading a state for debugging purpose, don't make a fuss if
2407	* the MMIO[2] and ROM stuff isn't 100% right, just skip the mismatches.
2408	*/
2409	if ( SSMR3HandleGetAfter(pSSM) != SSMAFTER_DEBUG_IT
2410	\|\| GCPhys < 8 * _1M)
2411	AssertFailedReturn(VERR_SSM_LOAD_CONFIG_MISMATCH);
2412
2413	RTGCPHYS cPages = ((GCPhysLast - GCPhys) + 1) >> PAGE_SHIFT;
2414	while (cPages-- > 0)
2415	{
2416	uint16_t u16Ignore;
2417	SSMR3GetU16(pSSM, &u16Ignore);
2418	}
2419	continue;
2420	}
2421
2422	/* Flags. */
2423	const unsigned cPages = pRam->cb >> PAGE_SHIFT;
2424	for (unsigned iPage = 0; iPage < cPages; iPage++)
2425	{
2426	uint16_t u16 = 0;
2427	SSMR3GetU16(pSSM, &u16);
2428	u16 &= PAGE_OFFSET_MASK & ~( RT_BIT(4) \| RT_BIT(5) \| RT_BIT(6)
2429	\| RT_BIT(7) \| RT_BIT(8) \| RT_BIT(9) \| RT_BIT(10) );
2430	// &= MM_RAM_FLAGS_DYNAMIC_ALLOC \| MM_RAM_FLAGS_RESERVED \| MM_RAM_FLAGS_ROM \| MM_RAM_FLAGS_MMIO \| MM_RAM_FLAGS_MMIO2
2431	pRam->aPages[iPage].HCPhys = PGM_PAGE_GET_HCPHYS(&pRam->aPages[iPage]) \| (RTHCPHYS)u16; /** @todo PAGE FLAGS */
2432	}
2433
2434	/* any memory associated with the range. */
2435	if (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)
2436	{
2437	for (unsigned iChunk = 0; iChunk < (pRam->cb >> PGM_DYNAMIC_CHUNK_SHIFT); iChunk++)
2438	{
2439	uint8_t fValidChunk;
2440
2441	rc = SSMR3GetU8(pSSM, &fValidChunk);
2442	if (RT_FAILURE(rc))
2443	return rc;
2444	if (fValidChunk > 1)
2445	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2446
2447	if (fValidChunk)
2448	{
2449	if (!pRam->paChunkR3Ptrs[iChunk])
2450	{
2451	rc = pgmr3PhysGrowRange(pVM, pRam->GCPhys + iChunk * PGM_DYNAMIC_CHUNK_SIZE);
2452	if (RT_FAILURE(rc))
2453	return rc;
2454	}
2455	Assert(pRam->paChunkR3Ptrs[iChunk]);
2456
2457	SSMR3GetMem(pSSM, (void *)pRam->paChunkR3Ptrs[iChunk], PGM_DYNAMIC_CHUNK_SIZE);
2458	}
2459	/* else nothing to do */
2460	}
2461	}
2462	else if (pRam->pvR3)
2463	{
2464	int rc = SSMR3GetMem(pSSM, pRam->pvR3, pRam->cb);
2465	if (RT_FAILURE(rc))
2466	{
2467	Log(("pgmR3Save: SSMR3GetMem(, %p, %#x) -> %Rrc\n", pRam->pvR3, pRam->cb, rc));
2468	return rc;
2469	}
2470	}
2471	}
2472
2473	/*
2474	* We require a full resync now.
2475	*/
2476	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3_NON_GLOBAL);
2477	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
2478	pPGM->fSyncFlags \|= PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL;
2479	pPGM->fPhysCacheFlushPending = true;
2480	pgmR3HandlerPhysicalUpdateAll(pVM);
2481
2482	/*
2483	* Change the paging mode.
2484	*/
2485	rc = PGMR3ChangeMode(pVM, pPGM->enmGuestMode);
2486
2487	/* Restore pVM->pgm.s.GCPhysCR3. */
2488	Assert(pVM->pgm.s.GCPhysCR3 == NIL_RTGCPHYS);
2489	RTGCPHYS GCPhysCR3 = CPUMGetGuestCR3(pVM);
2490	if ( pVM->pgm.s.enmGuestMode == PGMMODE_PAE
2491	\|\| pVM->pgm.s.enmGuestMode == PGMMODE_PAE_NX
2492	\|\| pVM->pgm.s.enmGuestMode == PGMMODE_AMD64
2493	\|\| pVM->pgm.s.enmGuestMode == PGMMODE_AMD64_NX)
2494	GCPhysCR3 = (GCPhysCR3 & X86_CR3_PAE_PAGE_MASK);
2495	else
2496	GCPhysCR3 = (GCPhysCR3 & X86_CR3_PAGE_MASK);
2497	pVM->pgm.s.GCPhysCR3 = GCPhysCR3;
2498
2499	return rc;
2500	}
2501
2502
2503	/**
2504	* Show paging mode.
2505	*
2506	* @param pVM VM Handle.
2507	* @param pHlp The info helpers.
2508	* @param pszArgs "all" (default), "guest", "shadow" or "host".
2509	*/
2510	static DECLCALLBACK(void) pgmR3InfoMode(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2511	{
2512	/* digest argument. */
2513	bool fGuest, fShadow, fHost;
2514	if (pszArgs)
2515	pszArgs = RTStrStripL(pszArgs);
2516	if (!pszArgs \|\| !*pszArgs \|\| strstr(pszArgs, "all"))
2517	fShadow = fHost = fGuest = true;
2518	else
2519	{
2520	fShadow = fHost = fGuest = false;
2521	if (strstr(pszArgs, "guest"))
2522	fGuest = true;
2523	if (strstr(pszArgs, "shadow"))
2524	fShadow = true;
2525	if (strstr(pszArgs, "host"))
2526	fHost = true;
2527	}
2528
2529	/* print info. */
2530	if (fGuest)
2531	pHlp->pfnPrintf(pHlp, "Guest paging mode: %s, changed %RU64 times, A20 %s\n",
2532	PGMGetModeName(pVM->pgm.s.enmGuestMode), pVM->pgm.s.cGuestModeChanges.c,
2533	pVM->pgm.s.fA20Enabled ? "enabled" : "disabled");
2534	if (fShadow)
2535	pHlp->pfnPrintf(pHlp, "Shadow paging mode: %s\n", PGMGetModeName(pVM->pgm.s.enmShadowMode));
2536	if (fHost)
2537	{
2538	const char *psz;
2539	switch (pVM->pgm.s.enmHostMode)
2540	{
2541	case SUPPAGINGMODE_INVALID: psz = "invalid"; break;
2542	case SUPPAGINGMODE_32_BIT: psz = "32-bit"; break;
2543	case SUPPAGINGMODE_32_BIT_GLOBAL: psz = "32-bit+G"; break;
2544	case SUPPAGINGMODE_PAE: psz = "PAE"; break;
2545	case SUPPAGINGMODE_PAE_GLOBAL: psz = "PAE+G"; break;
2546	case SUPPAGINGMODE_PAE_NX: psz = "PAE+NX"; break;
2547	case SUPPAGINGMODE_PAE_GLOBAL_NX: psz = "PAE+G+NX"; break;
2548	case SUPPAGINGMODE_AMD64: psz = "AMD64"; break;
2549	case SUPPAGINGMODE_AMD64_GLOBAL: psz = "AMD64+G"; break;
2550	case SUPPAGINGMODE_AMD64_NX: psz = "AMD64+NX"; break;
2551	case SUPPAGINGMODE_AMD64_GLOBAL_NX: psz = "AMD64+G+NX"; break;
2552	default: psz = "unknown"; break;
2553	}
2554	pHlp->pfnPrintf(pHlp, "Host paging mode: %s\n", psz);
2555	}
2556	}
2557
2558
2559	/**
2560	* Dump registered MMIO ranges to the log.
2561	*
2562	* @param pVM VM Handle.
2563	* @param pHlp The info helpers.
2564	* @param pszArgs Arguments, ignored.
2565	*/
2566	static DECLCALLBACK(void) pgmR3PhysInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2567	{
2568	NOREF(pszArgs);
2569	pHlp->pfnPrintf(pHlp,
2570	"RAM ranges (pVM=%p)\n"
2571	"%.s %.s\n",
2572	pVM,
2573	sizeof(RTGCPHYS) * 4 + 1, "GC Phys Range ",
2574	sizeof(RTHCPTR) * 2, "pvHC ");
2575
2576	for (PPGMRAMRANGE pCur = pVM->pgm.s.pRamRangesR3; pCur; pCur = pCur->pNextR3)
2577	pHlp->pfnPrintf(pHlp,
2578	"%RGp-%RGp %RHv %s\n",
2579	pCur->GCPhys,
2580	pCur->GCPhysLast,
2581	pCur->pvR3,
2582	pCur->pszDesc);
2583	}
2584
2585	/**
2586	* Dump the page directory to the log.
2587	*
2588	* @param pVM VM Handle.
2589	* @param pHlp The info helpers.
2590	* @param pszArgs Arguments, ignored.
2591	*/
2592	static DECLCALLBACK(void) pgmR3InfoCr3(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2593	{
2594	/** @todo fix this! Convert the PGMR3DumpHierarchyHC functions to do guest stuff. */
2595	/* Big pages supported? */
2596	const bool fPSE = !!(CPUMGetGuestCR4(pVM) & X86_CR4_PSE);
2597
2598	/* Global pages supported? */
2599	const bool fPGE = !!(CPUMGetGuestCR4(pVM) & X86_CR4_PGE);
2600
2601	NOREF(pszArgs);
2602
2603	/*
2604	* Get page directory addresses.
2605	*/
2606	PX86PD pPDSrc = pVM->pgm.s.pGuestPDR3;
2607	Assert(pPDSrc);
2608	Assert(PGMPhysGCPhys2HCPtrAssert(pVM, (RTGCPHYS)(CPUMGetGuestCR3(pVM) & X86_CR3_PAGE_MASK), sizeof(*pPDSrc)) == pPDSrc);
2609
2610	/*
2611	* Iterate the page directory.
2612	*/
2613	for (unsigned iPD = 0; iPD < RT_ELEMENTS(pPDSrc->a); iPD++)
2614	{
2615	X86PDE PdeSrc = pPDSrc->a[iPD];
2616	if (PdeSrc.n.u1Present)
2617	{
2618	if (PdeSrc.b.u1Size && fPSE)
2619	pHlp->pfnPrintf(pHlp,
2620	"%04X - %RGp P=%d U=%d RW=%d G=%d - BIG\n",
2621	iPD,
2622	pgmGstGet4MBPhysPage(&pVM->pgm.s, PdeSrc),
2623	PdeSrc.b.u1Present, PdeSrc.b.u1User, PdeSrc.b.u1Write, PdeSrc.b.u1Global && fPGE);
2624	else
2625	pHlp->pfnPrintf(pHlp,
2626	"%04X - %RGp P=%d U=%d RW=%d [G=%d]\n",
2627	iPD,
2628	(RTGCPHYS)(PdeSrc.u & X86_PDE_PG_MASK),
2629	PdeSrc.n.u1Present, PdeSrc.n.u1User, PdeSrc.n.u1Write, PdeSrc.b.u1Global && fPGE);
2630	}
2631	}
2632	}
2633
2634
2635	/**
2636	* Serivce a VMMCALLHOST_PGM_LOCK call.
2637	*
2638	* @returns VBox status code.
2639	* @param pVM The VM handle.
2640	*/
2641	VMMR3DECL(int) PGMR3LockCall(PVM pVM)
2642	{
2643	int rc = PDMR3CritSectEnterEx(&pVM->pgm.s.CritSect, true /* fHostCall */);
2644	AssertRC(rc);
2645	return rc;
2646	}
2647
2648
2649	/**
2650	* Converts a PGMMODE value to a PGM_TYPE_* \#define.
2651	*
2652	* @returns PGM_TYPE_*.
2653	* @param pgmMode The mode value to convert.
2654	*/
2655	DECLINLINE(unsigned) pgmModeToType(PGMMODE pgmMode)
2656	{
2657	switch (pgmMode)
2658	{
2659	case PGMMODE_REAL: return PGM_TYPE_REAL;
2660	case PGMMODE_PROTECTED: return PGM_TYPE_PROT;
2661	case PGMMODE_32_BIT: return PGM_TYPE_32BIT;
2662	case PGMMODE_PAE:
2663	case PGMMODE_PAE_NX: return PGM_TYPE_PAE;
2664	case PGMMODE_AMD64:
2665	case PGMMODE_AMD64_NX: return PGM_TYPE_AMD64;
2666	case PGMMODE_NESTED: return PGM_TYPE_NESTED;
2667	case PGMMODE_EPT: return PGM_TYPE_EPT;
2668	default:
2669	AssertFatalMsgFailed(("pgmMode=%d\n", pgmMode));
2670	}
2671	}
2672
2673
2674	/**
2675	* Gets the index into the paging mode data array of a SHW+GST mode.
2676	*
2677	* @returns PGM::paPagingData index.
2678	* @param uShwType The shadow paging mode type.
2679	* @param uGstType The guest paging mode type.
2680	*/
2681	DECLINLINE(unsigned) pgmModeDataIndex(unsigned uShwType, unsigned uGstType)
2682	{
2683	Assert(uShwType >= PGM_TYPE_32BIT && uShwType <= PGM_TYPE_MAX);
2684	Assert(uGstType >= PGM_TYPE_REAL && uGstType <= PGM_TYPE_AMD64);
2685	return (uShwType - PGM_TYPE_32BIT) * (PGM_TYPE_AMD64 - PGM_TYPE_REAL + 1)
2686	+ (uGstType - PGM_TYPE_REAL);
2687	}
2688
2689
2690	/**
2691	* Gets the index into the paging mode data array of a SHW+GST mode.
2692	*
2693	* @returns PGM::paPagingData index.
2694	* @param enmShw The shadow paging mode.
2695	* @param enmGst The guest paging mode.
2696	*/
2697	DECLINLINE(unsigned) pgmModeDataIndexByMode(PGMMODE enmShw, PGMMODE enmGst)
2698	{
2699	Assert(enmShw >= PGMMODE_32_BIT && enmShw <= PGMMODE_MAX);
2700	Assert(enmGst > PGMMODE_INVALID && enmGst < PGMMODE_MAX);
2701	return pgmModeDataIndex(pgmModeToType(enmShw), pgmModeToType(enmGst));
2702	}
2703
2704
2705	/**
2706	* Calculates the max data index.
2707	* @returns The number of entries in the paging data array.
2708	*/
2709	DECLINLINE(unsigned) pgmModeDataMaxIndex(void)
2710	{
2711	return pgmModeDataIndex(PGM_TYPE_MAX, PGM_TYPE_AMD64) + 1;
2712	}
2713
2714
2715	/**
2716	* Initializes the paging mode data kept in PGM::paModeData.
2717	*
2718	* @param pVM The VM handle.
2719	* @param fResolveGCAndR0 Indicate whether or not GC and Ring-0 symbols can be resolved now.
2720	* This is used early in the init process to avoid trouble with PDM
2721	* not being initialized yet.
2722	*/
2723	static int pgmR3ModeDataInit(PVM pVM, bool fResolveGCAndR0)
2724	{
2725	PPGMMODEDATA pModeData;
2726	int rc;
2727
2728	/*
2729	* Allocate the array on the first call.
2730	*/
2731	if (!pVM->pgm.s.paModeData)
2732	{
2733	pVM->pgm.s.paModeData = (PPGMMODEDATA)MMR3HeapAllocZ(pVM, MM_TAG_PGM, sizeof(PGMMODEDATA) * pgmModeDataMaxIndex());
2734	AssertReturn(pVM->pgm.s.paModeData, VERR_NO_MEMORY);
2735	}
2736
2737	/*
2738	* Initialize the array entries.
2739	*/
2740	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_32BIT, PGM_TYPE_REAL)];
2741	pModeData->uShwType = PGM_TYPE_32BIT;
2742	pModeData->uGstType = PGM_TYPE_REAL;
2743	rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2744	rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2745	rc = PGM_BTH_NAME_32BIT_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2746
2747	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_32BIT, PGMMODE_PROTECTED)];
2748	pModeData->uShwType = PGM_TYPE_32BIT;
2749	pModeData->uGstType = PGM_TYPE_PROT;
2750	rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2751	rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2752	rc = PGM_BTH_NAME_32BIT_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2753
2754	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_32BIT, PGM_TYPE_32BIT)];
2755	pModeData->uShwType = PGM_TYPE_32BIT;
2756	pModeData->uGstType = PGM_TYPE_32BIT;
2757	rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2758	rc = PGM_GST_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2759	rc = PGM_BTH_NAME_32BIT_32BIT(InitData)(pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2760
2761	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_REAL)];
2762	pModeData->uShwType = PGM_TYPE_PAE;
2763	pModeData->uGstType = PGM_TYPE_REAL;
2764	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2765	rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2766	rc = PGM_BTH_NAME_PAE_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2767
2768	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_PROT)];
2769	pModeData->uShwType = PGM_TYPE_PAE;
2770	pModeData->uGstType = PGM_TYPE_PROT;
2771	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2772	rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2773	rc = PGM_BTH_NAME_PAE_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2774
2775	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_32BIT)];
2776	pModeData->uShwType = PGM_TYPE_PAE;
2777	pModeData->uGstType = PGM_TYPE_32BIT;
2778	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2779	rc = PGM_GST_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2780	rc = PGM_BTH_NAME_PAE_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2781
2782	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_PAE)];
2783	pModeData->uShwType = PGM_TYPE_PAE;
2784	pModeData->uGstType = PGM_TYPE_PAE;
2785	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2786	rc = PGM_GST_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2787	rc = PGM_BTH_NAME_PAE_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2788
2789	#ifdef VBOX_WITH_64_BITS_GUESTS
2790	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_AMD64, PGM_TYPE_AMD64)];
2791	pModeData->uShwType = PGM_TYPE_AMD64;
2792	pModeData->uGstType = PGM_TYPE_AMD64;
2793	rc = PGM_SHW_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2794	rc = PGM_GST_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2795	rc = PGM_BTH_NAME_AMD64_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2796	#endif
2797
2798	/* The nested paging mode. */
2799	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_REAL)];
2800	pModeData->uShwType = PGM_TYPE_NESTED;
2801	pModeData->uGstType = PGM_TYPE_REAL;
2802	rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2803	rc = PGM_BTH_NAME_NESTED_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2804
2805	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGMMODE_PROTECTED)];
2806	pModeData->uShwType = PGM_TYPE_NESTED;
2807	pModeData->uGstType = PGM_TYPE_PROT;
2808	rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2809	rc = PGM_BTH_NAME_NESTED_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2810
2811	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_32BIT)];
2812	pModeData->uShwType = PGM_TYPE_NESTED;
2813	pModeData->uGstType = PGM_TYPE_32BIT;
2814	rc = PGM_GST_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2815	rc = PGM_BTH_NAME_NESTED_32BIT(InitData)(pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2816
2817	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_PAE)];
2818	pModeData->uShwType = PGM_TYPE_NESTED;
2819	pModeData->uGstType = PGM_TYPE_PAE;
2820	rc = PGM_GST_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2821	rc = PGM_BTH_NAME_NESTED_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2822
2823	#ifdef VBOX_WITH_64_BITS_GUESTS
2824	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_AMD64)];
2825	pModeData->uShwType = PGM_TYPE_NESTED;
2826	pModeData->uGstType = PGM_TYPE_AMD64;
2827	rc = PGM_GST_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2828	rc = PGM_BTH_NAME_NESTED_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2829	#endif
2830
2831	/* The shadow part of the nested callback mode depends on the host paging mode (AMD-V only). */
2832	switch(pVM->pgm.s.enmHostMode)
2833	{
2834	case SUPPAGINGMODE_32_BIT:
2835	case SUPPAGINGMODE_32_BIT_GLOBAL:
2836	#ifdef VBOX_WITH_64_BITS_GUESTS
2837	for (unsigned i=PGM_TYPE_REAL;i<=PGM_TYPE_AMD64;i++)
2838	#else
2839	for (unsigned i=PGM_TYPE_REAL;i<=PGM_TYPE_PAE;i++)
2840	#endif
2841	{
2842	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, i)];
2843	rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2844	}
2845	break;
2846
2847	case SUPPAGINGMODE_PAE:
2848	case SUPPAGINGMODE_PAE_NX:
2849	case SUPPAGINGMODE_PAE_GLOBAL:
2850	case SUPPAGINGMODE_PAE_GLOBAL_NX:
2851	#ifdef VBOX_WITH_64_BITS_GUESTS
2852	for (unsigned i=PGM_TYPE_REAL;i<=PGM_TYPE_AMD64;i++)
2853	#else
2854	for (unsigned i=PGM_TYPE_REAL;i<=PGM_TYPE_PAE;i++)
2855	#endif
2856	{
2857	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, i)];
2858	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2859	}
2860	break;
2861
2862	case SUPPAGINGMODE_AMD64:
2863	case SUPPAGINGMODE_AMD64_GLOBAL:
2864	case SUPPAGINGMODE_AMD64_NX:
2865	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
2866	#ifdef VBOX_WITH_64_BITS_GUESTS
2867	for (unsigned i=PGM_TYPE_REAL;i<=PGM_TYPE_AMD64;i++)
2868	#else
2869	for (unsigned i=PGM_TYPE_REAL;i<=PGM_TYPE_PAE;i++)
2870	#endif
2871	{
2872	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, i)];
2873	rc = PGM_SHW_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2874	}
2875	break;
2876	default:
2877	AssertFailed();
2878	break;
2879	}
2880
2881	/* Extended paging (EPT) / Intel VT-x */
2882	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_REAL)];
2883	pModeData->uShwType = PGM_TYPE_EPT;
2884	pModeData->uGstType = PGM_TYPE_REAL;
2885	rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2886	rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2887	rc = PGM_BTH_NAME_EPT_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2888
2889	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_PROT)];
2890	pModeData->uShwType = PGM_TYPE_EPT;
2891	pModeData->uGstType = PGM_TYPE_PROT;
2892	rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2893	rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2894	rc = PGM_BTH_NAME_EPT_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2895
2896	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_32BIT)];
2897	pModeData->uShwType = PGM_TYPE_EPT;
2898	pModeData->uGstType = PGM_TYPE_32BIT;
2899	rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2900	rc = PGM_GST_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2901	rc = PGM_BTH_NAME_EPT_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2902
2903	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_PAE)];
2904	pModeData->uShwType = PGM_TYPE_EPT;
2905	pModeData->uGstType = PGM_TYPE_PAE;
2906	rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2907	rc = PGM_GST_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2908	rc = PGM_BTH_NAME_EPT_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2909
2910	#ifdef VBOX_WITH_64_BITS_GUESTS
2911	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_AMD64)];
2912	pModeData->uShwType = PGM_TYPE_EPT;
2913	pModeData->uGstType = PGM_TYPE_AMD64;
2914	rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2915	rc = PGM_GST_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2916	rc = PGM_BTH_NAME_EPT_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2917	#endif
2918	return VINF_SUCCESS;
2919	}
2920
2921
2922	/**
2923	* Switch to different (or relocated in the relocate case) mode data.
2924	*
2925	* @param pVM The VM handle.
2926	* @param enmShw The the shadow paging mode.
2927	* @param enmGst The the guest paging mode.
2928	*/
2929	static void pgmR3ModeDataSwitch(PVM pVM, PGMMODE enmShw, PGMMODE enmGst)
2930	{
2931	PPGMMODEDATA pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndexByMode(enmShw, enmGst)];
2932
2933	Assert(pModeData->uGstType == pgmModeToType(enmGst));
2934	Assert(pModeData->uShwType == pgmModeToType(enmShw));
2935
2936	/* shadow */
2937	pVM->pgm.s.pfnR3ShwRelocate = pModeData->pfnR3ShwRelocate;
2938	pVM->pgm.s.pfnR3ShwExit = pModeData->pfnR3ShwExit;
2939	pVM->pgm.s.pfnR3ShwGetPage = pModeData->pfnR3ShwGetPage;
2940	Assert(pVM->pgm.s.pfnR3ShwGetPage);
2941	pVM->pgm.s.pfnR3ShwModifyPage = pModeData->pfnR3ShwModifyPage;
2942
2943	pVM->pgm.s.pfnRCShwGetPage = pModeData->pfnRCShwGetPage;
2944	pVM->pgm.s.pfnRCShwModifyPage = pModeData->pfnRCShwModifyPage;
2945
2946	pVM->pgm.s.pfnR0ShwGetPage = pModeData->pfnR0ShwGetPage;
2947	pVM->pgm.s.pfnR0ShwModifyPage = pModeData->pfnR0ShwModifyPage;
2948
2949
2950	/* guest */
2951	pVM->pgm.s.pfnR3GstRelocate = pModeData->pfnR3GstRelocate;
2952	pVM->pgm.s.pfnR3GstExit = pModeData->pfnR3GstExit;
2953	pVM->pgm.s.pfnR3GstGetPage = pModeData->pfnR3GstGetPage;
2954	Assert(pVM->pgm.s.pfnR3GstGetPage);
2955	pVM->pgm.s.pfnR3GstModifyPage = pModeData->pfnR3GstModifyPage;
2956	pVM->pgm.s.pfnR3GstGetPDE = pModeData->pfnR3GstGetPDE;
2957	pVM->pgm.s.pfnR3GstMonitorCR3 = pModeData->pfnR3GstMonitorCR3;
2958	pVM->pgm.s.pfnR3GstUnmonitorCR3 = pModeData->pfnR3GstUnmonitorCR3;
2959	pVM->pgm.s.pfnR3GstMapCR3 = pModeData->pfnR3GstMapCR3;
2960	pVM->pgm.s.pfnR3GstUnmapCR3 = pModeData->pfnR3GstUnmapCR3;
2961	pVM->pgm.s.pfnR3GstWriteHandlerCR3 = pModeData->pfnR3GstWriteHandlerCR3;
2962	pVM->pgm.s.pszR3GstWriteHandlerCR3 = pModeData->pszR3GstWriteHandlerCR3;
2963	pVM->pgm.s.pfnR3GstPAEWriteHandlerCR3 = pModeData->pfnR3GstPAEWriteHandlerCR3;
2964	pVM->pgm.s.pszR3GstPAEWriteHandlerCR3 = pModeData->pszR3GstPAEWriteHandlerCR3;
2965
2966	pVM->pgm.s.pfnRCGstGetPage = pModeData->pfnRCGstGetPage;
2967	pVM->pgm.s.pfnRCGstModifyPage = pModeData->pfnRCGstModifyPage;
2968	pVM->pgm.s.pfnRCGstGetPDE = pModeData->pfnRCGstGetPDE;
2969	pVM->pgm.s.pfnRCGstMonitorCR3 = pModeData->pfnRCGstMonitorCR3;
2970	pVM->pgm.s.pfnRCGstUnmonitorCR3 = pModeData->pfnRCGstUnmonitorCR3;
2971	pVM->pgm.s.pfnRCGstMapCR3 = pModeData->pfnRCGstMapCR3;
2972	pVM->pgm.s.pfnRCGstUnmapCR3 = pModeData->pfnRCGstUnmapCR3;
2973	pVM->pgm.s.pfnRCGstWriteHandlerCR3 = pModeData->pfnRCGstWriteHandlerCR3;
2974	pVM->pgm.s.pfnRCGstPAEWriteHandlerCR3 = pModeData->pfnRCGstPAEWriteHandlerCR3;
2975
2976	pVM->pgm.s.pfnR0GstGetPage = pModeData->pfnR0GstGetPage;
2977	pVM->pgm.s.pfnR0GstModifyPage = pModeData->pfnR0GstModifyPage;
2978	pVM->pgm.s.pfnR0GstGetPDE = pModeData->pfnR0GstGetPDE;
2979	pVM->pgm.s.pfnR0GstMonitorCR3 = pModeData->pfnR0GstMonitorCR3;
2980	pVM->pgm.s.pfnR0GstUnmonitorCR3 = pModeData->pfnR0GstUnmonitorCR3;
2981	pVM->pgm.s.pfnR0GstMapCR3 = pModeData->pfnR0GstMapCR3;
2982	pVM->pgm.s.pfnR0GstUnmapCR3 = pModeData->pfnR0GstUnmapCR3;
2983	pVM->pgm.s.pfnR0GstWriteHandlerCR3 = pModeData->pfnR0GstWriteHandlerCR3;
2984	pVM->pgm.s.pfnR0GstPAEWriteHandlerCR3 = pModeData->pfnR0GstPAEWriteHandlerCR3;
2985
2986
2987	/* both */
2988	pVM->pgm.s.pfnR3BthRelocate = pModeData->pfnR3BthRelocate;
2989	pVM->pgm.s.pfnR3BthInvalidatePage = pModeData->pfnR3BthInvalidatePage;
2990	pVM->pgm.s.pfnR3BthSyncCR3 = pModeData->pfnR3BthSyncCR3;
2991	Assert(pVM->pgm.s.pfnR3BthSyncCR3);
2992	pVM->pgm.s.pfnR3BthSyncPage = pModeData->pfnR3BthSyncPage;
2993	pVM->pgm.s.pfnR3BthPrefetchPage = pModeData->pfnR3BthPrefetchPage;
2994	pVM->pgm.s.pfnR3BthVerifyAccessSyncPage = pModeData->pfnR3BthVerifyAccessSyncPage;
2995	#ifdef VBOX_STRICT
2996	pVM->pgm.s.pfnR3BthAssertCR3 = pModeData->pfnR3BthAssertCR3;
2997	#endif
2998
2999	pVM->pgm.s.pfnRCBthTrap0eHandler = pModeData->pfnRCBthTrap0eHandler;
3000	pVM->pgm.s.pfnRCBthInvalidatePage = pModeData->pfnRCBthInvalidatePage;
3001	pVM->pgm.s.pfnRCBthSyncCR3 = pModeData->pfnRCBthSyncCR3;
3002	pVM->pgm.s.pfnRCBthSyncPage = pModeData->pfnRCBthSyncPage;
3003	pVM->pgm.s.pfnRCBthPrefetchPage = pModeData->pfnRCBthPrefetchPage;
3004	pVM->pgm.s.pfnRCBthVerifyAccessSyncPage = pModeData->pfnRCBthVerifyAccessSyncPage;
3005	#ifdef VBOX_STRICT
3006	pVM->pgm.s.pfnRCBthAssertCR3 = pModeData->pfnRCBthAssertCR3;
3007	#endif
3008
3009	pVM->pgm.s.pfnR0BthTrap0eHandler = pModeData->pfnR0BthTrap0eHandler;
3010	pVM->pgm.s.pfnR0BthInvalidatePage = pModeData->pfnR0BthInvalidatePage;
3011	pVM->pgm.s.pfnR0BthSyncCR3 = pModeData->pfnR0BthSyncCR3;
3012	pVM->pgm.s.pfnR0BthSyncPage = pModeData->pfnR0BthSyncPage;
3013	pVM->pgm.s.pfnR0BthPrefetchPage = pModeData->pfnR0BthPrefetchPage;
3014	pVM->pgm.s.pfnR0BthVerifyAccessSyncPage = pModeData->pfnR0BthVerifyAccessSyncPage;
3015	#ifdef VBOX_STRICT
3016	pVM->pgm.s.pfnR0BthAssertCR3 = pModeData->pfnR0BthAssertCR3;
3017	#endif
3018	}
3019
3020
3021	/**
3022	* Calculates the shadow paging mode.
3023	*
3024	* @returns The shadow paging mode.
3025	* @param pVM VM handle.
3026	* @param enmGuestMode The guest mode.
3027	* @param enmHostMode The host mode.
3028	* @param enmShadowMode The current shadow mode.
3029	* @param penmSwitcher Where to store the switcher to use.
3030	* VMMSWITCHER_INVALID means no change.
3031	*/
3032	static PGMMODE pgmR3CalcShadowMode(PVM pVM, PGMMODE enmGuestMode, SUPPAGINGMODE enmHostMode, PGMMODE enmShadowMode, VMMSWITCHER *penmSwitcher)
3033	{
3034	VMMSWITCHER enmSwitcher = VMMSWITCHER_INVALID;
3035	switch (enmGuestMode)
3036	{
3037	/*
3038	* When switching to real or protected mode we don't change
3039	* anything since it's likely that we'll switch back pretty soon.
3040	*
3041	* During pgmR3InitPaging we'll end up here with PGMMODE_INVALID
3042	* and is supposed to determine which shadow paging and switcher to
3043	* use during init.
3044	*/
3045	case PGMMODE_REAL:
3046	case PGMMODE_PROTECTED:
3047	if ( enmShadowMode != PGMMODE_INVALID
3048	&& !HWACCMIsEnabled(pVM) /* always switch in hwaccm mode! */)
3049	break; /* (no change) */
3050
3051	switch (enmHostMode)
3052	{
3053	case SUPPAGINGMODE_32_BIT:
3054	case SUPPAGINGMODE_32_BIT_GLOBAL:
3055	enmShadowMode = PGMMODE_32_BIT;
3056	enmSwitcher = VMMSWITCHER_32_TO_32;
3057	break;
3058
3059	case SUPPAGINGMODE_PAE:
3060	case SUPPAGINGMODE_PAE_NX:
3061	case SUPPAGINGMODE_PAE_GLOBAL:
3062	case SUPPAGINGMODE_PAE_GLOBAL_NX:
3063	enmShadowMode = PGMMODE_PAE;
3064	enmSwitcher = VMMSWITCHER_PAE_TO_PAE;
3065	#ifdef DEBUG_bird
3066	if (RTEnvExist("VBOX_32BIT"))
3067	{
3068	enmShadowMode = PGMMODE_32_BIT;
3069	enmSwitcher = VMMSWITCHER_PAE_TO_32;
3070	}
3071	#endif
3072	break;
3073
3074	case SUPPAGINGMODE_AMD64:
3075	case SUPPAGINGMODE_AMD64_GLOBAL:
3076	case SUPPAGINGMODE_AMD64_NX:
3077	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
3078	enmShadowMode = PGMMODE_PAE;
3079	enmSwitcher = VMMSWITCHER_AMD64_TO_PAE;
3080	break;
3081
3082	default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
3083	}
3084	break;
3085
3086	case PGMMODE_32_BIT:
3087	switch (enmHostMode)
3088	{
3089	case SUPPAGINGMODE_32_BIT:
3090	case SUPPAGINGMODE_32_BIT_GLOBAL:
3091	enmShadowMode = PGMMODE_32_BIT;
3092	enmSwitcher = VMMSWITCHER_32_TO_32;
3093	break;
3094
3095	case SUPPAGINGMODE_PAE:
3096	case SUPPAGINGMODE_PAE_NX:
3097	case SUPPAGINGMODE_PAE_GLOBAL:
3098	case SUPPAGINGMODE_PAE_GLOBAL_NX:
3099	enmShadowMode = PGMMODE_PAE;
3100	enmSwitcher = VMMSWITCHER_PAE_TO_PAE;
3101	#ifdef DEBUG_bird
3102	if (RTEnvExist("VBOX_32BIT"))
3103	{
3104	enmShadowMode = PGMMODE_32_BIT;
3105	enmSwitcher = VMMSWITCHER_PAE_TO_32;
3106	}
3107	#endif
3108	break;
3109
3110	case SUPPAGINGMODE_AMD64:
3111	case SUPPAGINGMODE_AMD64_GLOBAL:
3112	case SUPPAGINGMODE_AMD64_NX:
3113	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
3114	enmShadowMode = PGMMODE_PAE;
3115	enmSwitcher = VMMSWITCHER_AMD64_TO_PAE;
3116	break;
3117
3118	default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
3119	}
3120	break;
3121
3122	case PGMMODE_PAE:
3123	case PGMMODE_PAE_NX: /** @todo This might require more switchers and guest+both modes. */
3124	switch (enmHostMode)
3125	{
3126	case SUPPAGINGMODE_32_BIT:
3127	case SUPPAGINGMODE_32_BIT_GLOBAL:
3128	enmShadowMode = PGMMODE_PAE;
3129	enmSwitcher = VMMSWITCHER_32_TO_PAE;
3130	break;
3131
3132	case SUPPAGINGMODE_PAE:
3133	case SUPPAGINGMODE_PAE_NX:
3134	case SUPPAGINGMODE_PAE_GLOBAL:
3135	case SUPPAGINGMODE_PAE_GLOBAL_NX:
3136	enmShadowMode = PGMMODE_PAE;
3137	enmSwitcher = VMMSWITCHER_PAE_TO_PAE;
3138	break;
3139
3140	case SUPPAGINGMODE_AMD64:
3141	case SUPPAGINGMODE_AMD64_GLOBAL:
3142	case SUPPAGINGMODE_AMD64_NX:
3143	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
3144	enmShadowMode = PGMMODE_PAE;
3145	enmSwitcher = VMMSWITCHER_AMD64_TO_PAE;
3146	break;
3147
3148	default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
3149	}
3150	break;
3151
3152	case PGMMODE_AMD64:
3153	case PGMMODE_AMD64_NX:
3154	switch (enmHostMode)
3155	{
3156	case SUPPAGINGMODE_32_BIT:
3157	case SUPPAGINGMODE_32_BIT_GLOBAL:
3158	enmShadowMode = PGMMODE_PAE;
3159	enmSwitcher = VMMSWITCHER_32_TO_AMD64;
3160	break;
3161
3162	case SUPPAGINGMODE_PAE:
3163	case SUPPAGINGMODE_PAE_NX:
3164	case SUPPAGINGMODE_PAE_GLOBAL:
3165	case SUPPAGINGMODE_PAE_GLOBAL_NX:
3166	enmShadowMode = PGMMODE_PAE;
3167	enmSwitcher = VMMSWITCHER_PAE_TO_AMD64;
3168	break;
3169
3170	case SUPPAGINGMODE_AMD64:
3171	case SUPPAGINGMODE_AMD64_GLOBAL:
3172	case SUPPAGINGMODE_AMD64_NX:
3173	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
3174	enmShadowMode = PGMMODE_AMD64;
3175	enmSwitcher = VMMSWITCHER_AMD64_TO_AMD64;
3176	break;
3177
3178	default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
3179	}
3180	break;
3181
3182
3183	default:
3184	AssertReleaseMsgFailed(("enmGuestMode=%d\n", enmGuestMode));
3185	return PGMMODE_INVALID;
3186	}
3187	/* Override the shadow mode is nested paging is active. */
3188	if (HWACCMIsNestedPagingActive(pVM))
3189	enmShadowMode = HWACCMGetPagingMode(pVM);
3190
3191	*penmSwitcher = enmSwitcher;
3192	return enmShadowMode;
3193	}
3194
3195
3196	/**
3197	* Performs the actual mode change.
3198	* This is called by PGMChangeMode and pgmR3InitPaging().
3199	*
3200	* @returns VBox status code.
3201	* @param pVM VM handle.
3202	* @param enmGuestMode The new guest mode. This is assumed to be different from
3203	* the current mode.
3204	*/
3205	VMMR3DECL(int) PGMR3ChangeMode(PVM pVM, PGMMODE enmGuestMode)
3206	{
3207	Log(("PGMR3ChangeMode: Guest mode: %s -> %s\n", PGMGetModeName(pVM->pgm.s.enmGuestMode), PGMGetModeName(enmGuestMode)));
3208	STAM_REL_COUNTER_INC(&pVM->pgm.s.cGuestModeChanges);
3209
3210	/*
3211	* Calc the shadow mode and switcher.
3212	*/
3213	VMMSWITCHER enmSwitcher;
3214	PGMMODE enmShadowMode = pgmR3CalcShadowMode(pVM, enmGuestMode, pVM->pgm.s.enmHostMode, pVM->pgm.s.enmShadowMode, &enmSwitcher);
3215	if (enmSwitcher != VMMSWITCHER_INVALID)
3216	{
3217	/*
3218	* Select new switcher.
3219	*/
3220	int rc = VMMR3SelectSwitcher(pVM, enmSwitcher);
3221	if (RT_FAILURE(rc))
3222	{
3223	AssertReleaseMsgFailed(("VMMR3SelectSwitcher(%d) -> %Rrc\n", enmSwitcher, rc));
3224	return rc;
3225	}
3226	}
3227
3228	/*
3229	* Exit old mode(s).
3230	*/
3231	/* shadow */
3232	if (enmShadowMode != pVM->pgm.s.enmShadowMode)
3233	{
3234	LogFlow(("PGMR3ChangeMode: Shadow mode: %s -> %s\n", PGMGetModeName(pVM->pgm.s.enmShadowMode), PGMGetModeName(enmShadowMode)));
3235	if (PGM_SHW_PFN(Exit, pVM))
3236	{
3237	int rc = PGM_SHW_PFN(Exit, pVM)(pVM);
3238	if (RT_FAILURE(rc))
3239	{
3240	AssertMsgFailed(("Exit failed for shadow mode %d: %Rrc\n", pVM->pgm.s.enmShadowMode, rc));
3241	return rc;
3242	}
3243	}
3244
3245	}
3246	else
3247	LogFlow(("PGMR3ChangeMode: Shadow mode remains: %s\n", PGMGetModeName(pVM->pgm.s.enmShadowMode)));
3248
3249	/* guest */
3250	if (PGM_GST_PFN(Exit, pVM))
3251	{
3252	int rc = PGM_GST_PFN(Exit, pVM)(pVM);
3253	if (RT_FAILURE(rc))
3254	{
3255	AssertMsgFailed(("Exit failed for guest mode %d: %Rrc\n", pVM->pgm.s.enmGuestMode, rc));
3256	return rc;
3257	}
3258	}
3259
3260	/*
3261	* Load new paging mode data.
3262	*/
3263	pgmR3ModeDataSwitch(pVM, enmShadowMode, enmGuestMode);
3264
3265	/*
3266	* Enter new shadow mode (if changed).
3267	*/
3268	if (enmShadowMode != pVM->pgm.s.enmShadowMode)
3269	{
3270	int rc;
3271	pVM->pgm.s.enmShadowMode = enmShadowMode;
3272	switch (enmShadowMode)
3273	{
3274	case PGMMODE_32_BIT:
3275	rc = PGM_SHW_NAME_32BIT(Enter)(pVM);
3276	break;
3277	case PGMMODE_PAE:
3278	case PGMMODE_PAE_NX:
3279	rc = PGM_SHW_NAME_PAE(Enter)(pVM);
3280	break;
3281	case PGMMODE_AMD64:
3282	case PGMMODE_AMD64_NX:
3283	rc = PGM_SHW_NAME_AMD64(Enter)(pVM);
3284	break;
3285	case PGMMODE_NESTED:
3286	rc = PGM_SHW_NAME_NESTED(Enter)(pVM);
3287	break;
3288	case PGMMODE_EPT:
3289	rc = PGM_SHW_NAME_EPT(Enter)(pVM);
3290	break;
3291	case PGMMODE_REAL:
3292	case PGMMODE_PROTECTED:
3293	default:
3294	AssertReleaseMsgFailed(("enmShadowMode=%d\n", enmShadowMode));
3295	return VERR_INTERNAL_ERROR;
3296	}
3297	if (RT_FAILURE(rc))
3298	{
3299	AssertReleaseMsgFailed(("Entering enmShadowMode=%d failed: %Rrc\n", enmShadowMode, rc));
3300	pVM->pgm.s.enmShadowMode = PGMMODE_INVALID;
3301	return rc;
3302	}
3303	}
3304
3305	/** @todo This is a bug!
3306	*
3307	* We must flush the PGM pool cache if the guest mode changes; we don't always
3308	* switch shadow paging mode (e.g. protected->32-bit) and shouldn't reuse
3309	* the shadow page tables.
3310	*
3311	* That only applies when switching between paging and non-paging modes.
3312	*/
3313	/** @todo A20 setting */
3314	if ( pVM->pgm.s.CTX_SUFF(pPool)
3315	&& !HWACCMIsNestedPagingActive(pVM)
3316	&& PGMMODE_WITH_PAGING(pVM->pgm.s.enmGuestMode) != PGMMODE_WITH_PAGING(enmGuestMode))
3317	{
3318	Log(("PGMR3ChangeMode: changing guest paging mode -> flush pgm pool cache!\n"));
3319	pgmPoolFlushAll(pVM);
3320	}
3321
3322	/*
3323	* Enter the new guest and shadow+guest modes.
3324	*/
3325	int rc = -1;
3326	int rc2 = -1;
3327	RTGCPHYS GCPhysCR3 = NIL_RTGCPHYS;
3328	pVM->pgm.s.enmGuestMode = enmGuestMode;
3329	switch (enmGuestMode)
3330	{
3331	case PGMMODE_REAL:
3332	rc = PGM_GST_NAME_REAL(Enter)(pVM, NIL_RTGCPHYS);
3333	switch (pVM->pgm.s.enmShadowMode)
3334	{
3335	case PGMMODE_32_BIT:
3336	rc2 = PGM_BTH_NAME_32BIT_REAL(Enter)(pVM, NIL_RTGCPHYS);
3337	break;
3338	case PGMMODE_PAE:
3339	case PGMMODE_PAE_NX:
3340	rc2 = PGM_BTH_NAME_PAE_REAL(Enter)(pVM, NIL_RTGCPHYS);
3341	break;
3342	case PGMMODE_NESTED:
3343	rc2 = PGM_BTH_NAME_NESTED_REAL(Enter)(pVM, NIL_RTGCPHYS);
3344	break;
3345	case PGMMODE_EPT:
3346	rc2 = PGM_BTH_NAME_EPT_REAL(Enter)(pVM, NIL_RTGCPHYS);
3347	break;
3348	case PGMMODE_AMD64:
3349	case PGMMODE_AMD64_NX:
3350	AssertMsgFailed(("Should use PAE shadow mode!\n"));
3351	default: AssertFailed(); break;
3352	}
3353	break;
3354
3355	case PGMMODE_PROTECTED:
3356	rc = PGM_GST_NAME_PROT(Enter)(pVM, NIL_RTGCPHYS);
3357	switch (pVM->pgm.s.enmShadowMode)
3358	{
3359	case PGMMODE_32_BIT:
3360	rc2 = PGM_BTH_NAME_32BIT_PROT(Enter)(pVM, NIL_RTGCPHYS);
3361	break;
3362	case PGMMODE_PAE:
3363	case PGMMODE_PAE_NX:
3364	rc2 = PGM_BTH_NAME_PAE_PROT(Enter)(pVM, NIL_RTGCPHYS);
3365	break;
3366	case PGMMODE_NESTED:
3367	rc2 = PGM_BTH_NAME_NESTED_PROT(Enter)(pVM, NIL_RTGCPHYS);
3368	break;
3369	case PGMMODE_EPT:
3370	rc2 = PGM_BTH_NAME_EPT_PROT(Enter)(pVM, NIL_RTGCPHYS);
3371	break;
3372	case PGMMODE_AMD64:
3373	case PGMMODE_AMD64_NX:
3374	AssertMsgFailed(("Should use PAE shadow mode!\n"));
3375	default: AssertFailed(); break;
3376	}
3377	break;
3378
3379	case PGMMODE_32_BIT:
3380	GCPhysCR3 = CPUMGetGuestCR3(pVM) & X86_CR3_PAGE_MASK;
3381	rc = PGM_GST_NAME_32BIT(Enter)(pVM, GCPhysCR3);
3382	switch (pVM->pgm.s.enmShadowMode)
3383	{
3384	case PGMMODE_32_BIT:
3385	rc2 = PGM_BTH_NAME_32BIT_32BIT(Enter)(pVM, GCPhysCR3);
3386	break;
3387	case PGMMODE_PAE:
3388	case PGMMODE_PAE_NX:
3389	rc2 = PGM_BTH_NAME_PAE_32BIT(Enter)(pVM, GCPhysCR3);
3390	break;
3391	case PGMMODE_NESTED:
3392	rc2 = PGM_BTH_NAME_NESTED_32BIT(Enter)(pVM, GCPhysCR3);
3393	break;
3394	case PGMMODE_EPT:
3395	rc2 = PGM_BTH_NAME_EPT_32BIT(Enter)(pVM, GCPhysCR3);
3396	break;
3397	case PGMMODE_AMD64:
3398	case PGMMODE_AMD64_NX:
3399	AssertMsgFailed(("Should use PAE shadow mode!\n"));
3400	default: AssertFailed(); break;
3401	}
3402	break;
3403
3404	case PGMMODE_PAE_NX:
3405	case PGMMODE_PAE:
3406	{
3407	uint32_t u32Dummy, u32Features;
3408
3409	CPUMGetGuestCpuId(pVM, 1, &u32Dummy, &u32Dummy, &u32Dummy, &u32Features);
3410	if (!(u32Features & X86_CPUID_FEATURE_EDX_PAE))
3411	{
3412	/* Pause first, then inform Main. */
3413	rc = VMR3SuspendNoSave(pVM);
3414	AssertRC(rc);
3415
3416	VMSetRuntimeError(pVM, true, "PAEmode",
3417	N_("The guest is trying to switch to the PAE mode which is currently disabled by default in VirtualBox. Experimental PAE support can be enabled using the -pae option with VBoxManage"));
3418	/* we must return VINF_SUCCESS here otherwise the recompiler will assert */
3419	return VINF_SUCCESS;
3420	}
3421	GCPhysCR3 = CPUMGetGuestCR3(pVM) & X86_CR3_PAE_PAGE_MASK;
3422	rc = PGM_GST_NAME_PAE(Enter)(pVM, GCPhysCR3);
3423	switch (pVM->pgm.s.enmShadowMode)
3424	{
3425	case PGMMODE_PAE:
3426	case PGMMODE_PAE_NX:
3427	rc2 = PGM_BTH_NAME_PAE_PAE(Enter)(pVM, GCPhysCR3);
3428	break;
3429	case PGMMODE_NESTED:
3430	rc2 = PGM_BTH_NAME_NESTED_PAE(Enter)(pVM, GCPhysCR3);
3431	break;
3432	case PGMMODE_EPT:
3433	rc2 = PGM_BTH_NAME_EPT_PAE(Enter)(pVM, GCPhysCR3);
3434	break;
3435	case PGMMODE_32_BIT:
3436	case PGMMODE_AMD64:
3437	case PGMMODE_AMD64_NX:
3438	AssertMsgFailed(("Should use PAE shadow mode!\n"));
3439	default: AssertFailed(); break;
3440	}
3441	break;
3442	}
3443
3444	#ifdef VBOX_WITH_64_BITS_GUESTS
3445	case PGMMODE_AMD64_NX:
3446	case PGMMODE_AMD64:
3447	GCPhysCR3 = CPUMGetGuestCR3(pVM) & 0xfffffffffffff000ULL; /** @todo define this mask! */
3448	rc = PGM_GST_NAME_AMD64(Enter)(pVM, GCPhysCR3);
3449	switch (pVM->pgm.s.enmShadowMode)
3450	{
3451	case PGMMODE_AMD64:
3452	case PGMMODE_AMD64_NX:
3453	rc2 = PGM_BTH_NAME_AMD64_AMD64(Enter)(pVM, GCPhysCR3);
3454	break;
3455	case PGMMODE_NESTED:
3456	rc2 = PGM_BTH_NAME_NESTED_AMD64(Enter)(pVM, GCPhysCR3);
3457	break;
3458	case PGMMODE_EPT:
3459	rc2 = PGM_BTH_NAME_EPT_AMD64(Enter)(pVM, GCPhysCR3);
3460	break;
3461	case PGMMODE_32_BIT:
3462	case PGMMODE_PAE:
3463	case PGMMODE_PAE_NX:
3464	AssertMsgFailed(("Should use AMD64 shadow mode!\n"));
3465	default: AssertFailed(); break;
3466	}
3467	break;
3468	#endif
3469
3470	default:
3471	AssertReleaseMsgFailed(("enmGuestMode=%d\n", enmGuestMode));
3472	rc = VERR_NOT_IMPLEMENTED;
3473	break;
3474	}
3475
3476	/* status codes. */
3477	AssertRC(rc);
3478	AssertRC(rc2);
3479	if (RT_SUCCESS(rc))
3480	{
3481	rc = rc2;
3482	if (RT_SUCCESS(rc)) /* no informational status codes. */
3483	rc = VINF_SUCCESS;
3484	}
3485
3486	/*
3487	* Notify SELM so it can update the TSSes with correct CR3s.
3488	*/
3489	SELMR3PagingModeChanged(pVM);
3490
3491	/* Notify HWACCM as well. */
3492	HWACCMR3PagingModeChanged(pVM, pVM->pgm.s.enmShadowMode, pVM->pgm.s.enmGuestMode);
3493	return rc;
3494	}
3495
3496
3497	/**
3498	* Dumps a PAE shadow page table.
3499	*
3500	* @returns VBox status code (VINF_SUCCESS).
3501	* @param pVM The VM handle.
3502	* @param pPT Pointer to the page table.
3503	* @param u64Address The virtual address of the page table starts.
3504	* @param fLongMode Set if this a long mode table; clear if it's a legacy mode table.
3505	* @param cMaxDepth The maxium depth.
3506	* @param pHlp Pointer to the output functions.
3507	*/
3508	static int pgmR3DumpHierarchyHCPaePT(PVM pVM, PX86PTPAE pPT, uint64_t u64Address, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
3509	{
3510	for (unsigned i = 0; i < RT_ELEMENTS(pPT->a); i++)
3511	{
3512	X86PTEPAE Pte = pPT->a[i];
3513	if (Pte.n.u1Present)
3514	{
3515	pHlp->pfnPrintf(pHlp,
3516	fLongMode /P R S A D G WT CD AT NX 4M a p ? /
3517	? "%016llx 3 \| P %c %c %c %c %c %s %s %s %s 4K %c%c%c %016llx\n"
3518	: "%08llx 2 \| P %c %c %c %c %c %s %s %s %s 4K %c%c%c %016llx\n",
3519	u64Address + ((uint64_t)i << X86_PT_PAE_SHIFT),
3520	Pte.n.u1Write ? 'W' : 'R',
3521	Pte.n.u1User ? 'U' : 'S',
3522	Pte.n.u1Accessed ? 'A' : '-',
3523	Pte.n.u1Dirty ? 'D' : '-',
3524	Pte.n.u1Global ? 'G' : '-',
3525	Pte.n.u1WriteThru ? "WT" : "--",
3526	Pte.n.u1CacheDisable? "CD" : "--",
3527	Pte.n.u1PAT ? "AT" : "--",
3528	Pte.n.u1NoExecute ? "NX" : "--",
3529	Pte.u & PGM_PTFLAGS_TRACK_DIRTY ? 'd' : '-',
3530	Pte.u & RT_BIT(10) ? '1' : '0',
3531	Pte.u & PGM_PTFLAGS_CSAM_VALIDATED? 'v' : '-',
3532	Pte.u & X86_PTE_PAE_PG_MASK);
3533	}
3534	}
3535	return VINF_SUCCESS;
3536	}
3537
3538
3539	/**
3540	* Dumps a PAE shadow page directory table.
3541	*
3542	* @returns VBox status code (VINF_SUCCESS).
3543	* @param pVM The VM handle.
3544	* @param HCPhys The physical address of the page directory table.
3545	* @param u64Address The virtual address of the page table starts.
3546	* @param cr4 The CR4, PSE is currently used.
3547	* @param fLongMode Set if this a long mode table; clear if it's a legacy mode table.
3548	* @param cMaxDepth The maxium depth.
3549	* @param pHlp Pointer to the output functions.
3550	*/
3551	static int pgmR3DumpHierarchyHCPaePD(PVM pVM, RTHCPHYS HCPhys, uint64_t u64Address, uint32_t cr4, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
3552	{
3553	PX86PDPAE pPD = (PX86PDPAE)MMPagePhys2Page(pVM, HCPhys);
3554	if (!pPD)
3555	{
3556	pHlp->pfnPrintf(pHlp, "%0*llx error! Page directory at HCPhys=%RHp was not found in the page pool!\n",
3557	fLongMode ? 16 : 8, u64Address, HCPhys);
3558	return VERR_INVALID_PARAMETER;
3559	}
3560	const bool fBigPagesSupported = fLongMode \|\| !!(cr4 & X86_CR4_PSE);
3561
3562	int rc = VINF_SUCCESS;
3563	for (unsigned i = 0; i < RT_ELEMENTS(pPD->a); i++)
3564	{
3565	X86PDEPAE Pde = pPD->a[i];
3566	if (Pde.n.u1Present)
3567	{
3568	if (fBigPagesSupported && Pde.b.u1Size)
3569	pHlp->pfnPrintf(pHlp,
3570	fLongMode /P R S A D G WT CD AT NX 4M a p ? /
3571	? "%016llx 2 \| P %c %c %c %c %c %s %s %s %s 4M %c%c%c %016llx\n"
3572	: "%08llx 1 \| P %c %c %c %c %c %s %s %s %s 4M %c%c%c %016llx\n",
3573	u64Address + ((uint64_t)i << X86_PD_PAE_SHIFT),
3574	Pde.b.u1Write ? 'W' : 'R',
3575	Pde.b.u1User ? 'U' : 'S',
3576	Pde.b.u1Accessed ? 'A' : '-',
3577	Pde.b.u1Dirty ? 'D' : '-',
3578	Pde.b.u1Global ? 'G' : '-',
3579	Pde.b.u1WriteThru ? "WT" : "--",
3580	Pde.b.u1CacheDisable? "CD" : "--",
3581	Pde.b.u1PAT ? "AT" : "--",
3582	Pde.b.u1NoExecute ? "NX" : "--",
3583	Pde.u & RT_BIT_64(9) ? '1' : '0',
3584	Pde.u & PGM_PDFLAGS_MAPPING ? 'm' : '-',
3585	Pde.u & PGM_PDFLAGS_TRACK_DIRTY ? 'd' : '-',
3586	Pde.u & X86_PDE_PAE_PG_MASK);
3587	else
3588	{
3589	pHlp->pfnPrintf(pHlp,
3590	fLongMode /P R S A D G WT CD AT NX 4M a p ? /
3591	? "%016llx 2 \| P %c %c %c %c %c %s %s .. %s 4K %c%c%c %016llx\n"
3592	: "%08llx 1 \| P %c %c %c %c %c %s %s .. %s 4K %c%c%c %016llx\n",
3593	u64Address + ((uint64_t)i << X86_PD_PAE_SHIFT),
3594	Pde.n.u1Write ? 'W' : 'R',
3595	Pde.n.u1User ? 'U' : 'S',
3596	Pde.n.u1Accessed ? 'A' : '-',
3597	Pde.n.u1Reserved0 ? '?' : '.', /* ignored */
3598	Pde.n.u1Reserved1 ? '?' : '.', /* ignored */
3599	Pde.n.u1WriteThru ? "WT" : "--",
3600	Pde.n.u1CacheDisable? "CD" : "--",
3601	Pde.n.u1NoExecute ? "NX" : "--",
3602	Pde.u & RT_BIT_64(9) ? '1' : '0',
3603	Pde.u & PGM_PDFLAGS_MAPPING ? 'm' : '-',
3604	Pde.u & PGM_PDFLAGS_TRACK_DIRTY ? 'd' : '-',
3605	Pde.u & X86_PDE_PAE_PG_MASK);
3606	if (cMaxDepth >= 1)
3607	{
3608	/** @todo what about using the page pool for mapping PTs? */
3609	uint64_t u64AddressPT = u64Address + ((uint64_t)i << X86_PD_PAE_SHIFT);
3610	RTHCPHYS HCPhysPT = Pde.u & X86_PDE_PAE_PG_MASK;
3611	PX86PTPAE pPT = NULL;
3612	if (!(Pde.u & PGM_PDFLAGS_MAPPING))
3613	pPT = (PX86PTPAE)MMPagePhys2Page(pVM, HCPhysPT);
3614	else
3615	{
3616	for (PPGMMAPPING pMap = pVM->pgm.s.pMappingsR3; pMap; pMap = pMap->pNextR3)
3617	{
3618	uint64_t off = u64AddressPT - pMap->GCPtr;
3619	if (off < pMap->cb)
3620	{
3621	const int iPDE = (uint32_t)(off >> X86_PD_SHIFT);
3622	const int iSub = (int)((off >> X86_PD_PAE_SHIFT) & 1); /* MSC is a pain sometimes */
3623	if ((iSub ? pMap->aPTs[iPDE].HCPhysPaePT1 : pMap->aPTs[iPDE].HCPhysPaePT0) != HCPhysPT)
3624	pHlp->pfnPrintf(pHlp, "%0*llx error! Mapping error! PT %d has HCPhysPT=%RHp not %RHp is in the PD.\n",
3625	fLongMode ? 16 : 8, u64AddressPT, iPDE,
3626	iSub ? pMap->aPTs[iPDE].HCPhysPaePT1 : pMap->aPTs[iPDE].HCPhysPaePT0, HCPhysPT);
3627	pPT = &pMap->aPTs[iPDE].paPaePTsR3[iSub];
3628	}
3629	}
3630	}
3631	int rc2 = VERR_INVALID_PARAMETER;
3632	if (pPT)
3633	rc2 = pgmR3DumpHierarchyHCPaePT(pVM, pPT, u64AddressPT, fLongMode, cMaxDepth - 1, pHlp);
3634	else
3635	pHlp->pfnPrintf(pHlp, "%0*llx error! Page table at HCPhys=%RHp was not found in the page pool!\n",
3636	fLongMode ? 16 : 8, u64AddressPT, HCPhysPT);
3637	if (rc2 < rc && RT_SUCCESS(rc))
3638	rc = rc2;
3639	}
3640	}
3641	}
3642	}
3643	return rc;
3644	}
3645
3646
3647	/**
3648	* Dumps a PAE shadow page directory pointer table.
3649	*
3650	* @returns VBox status code (VINF_SUCCESS).
3651	* @param pVM The VM handle.
3652	* @param HCPhys The physical address of the page directory pointer table.
3653	* @param u64Address The virtual address of the page table starts.
3654	* @param cr4 The CR4, PSE is currently used.
3655	* @param fLongMode Set if this a long mode table; clear if it's a legacy mode table.
3656	* @param cMaxDepth The maxium depth.
3657	* @param pHlp Pointer to the output functions.
3658	*/
3659	static int pgmR3DumpHierarchyHCPaePDPT(PVM pVM, RTHCPHYS HCPhys, uint64_t u64Address, uint32_t cr4, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
3660	{
3661	PX86PDPT pPDPT = (PX86PDPT)MMPagePhys2Page(pVM, HCPhys);
3662	if (!pPDPT)
3663	{
3664	pHlp->pfnPrintf(pHlp, "%0*llx error! Page directory pointer table at HCPhys=%RHp was not found in the page pool!\n",
3665	fLongMode ? 16 : 8, u64Address, HCPhys);
3666	return VERR_INVALID_PARAMETER;
3667	}
3668
3669	int rc = VINF_SUCCESS;
3670	const unsigned c = fLongMode ? RT_ELEMENTS(pPDPT->a) : X86_PG_PAE_PDPE_ENTRIES;
3671	for (unsigned i = 0; i < c; i++)
3672	{
3673	X86PDPE Pdpe = pPDPT->a[i];
3674	if (Pdpe.n.u1Present)
3675	{
3676	if (fLongMode)
3677	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a p ? /
3678	"%016llx 1 \| P %c %c %c %c %c %s %s %s %s .. %c%c%c %016llx\n",
3679	u64Address + ((uint64_t)i << X86_PDPT_SHIFT),
3680	Pdpe.lm.u1Write ? 'W' : 'R',
3681	Pdpe.lm.u1User ? 'U' : 'S',
3682	Pdpe.lm.u1Accessed ? 'A' : '-',
3683	Pdpe.lm.u3Reserved & 1? '?' : '.', /* ignored */
3684	Pdpe.lm.u3Reserved & 4? '!' : '.', /* mbz */
3685	Pdpe.lm.u1WriteThru ? "WT" : "--",
3686	Pdpe.lm.u1CacheDisable? "CD" : "--",
3687	Pdpe.lm.u3Reserved & 2? "!" : "..",/* mbz */
3688	Pdpe.lm.u1NoExecute ? "NX" : "--",
3689	Pdpe.u & RT_BIT(9) ? '1' : '0',
3690	Pdpe.u & PGM_PLXFLAGS_PERMANENT ? 'p' : '-',
3691	Pdpe.u & RT_BIT(11) ? '1' : '0',
3692	Pdpe.u & X86_PDPE_PG_MASK);
3693	else
3694	pHlp->pfnPrintf(pHlp, /P G WT CD AT NX 4M a p ? /
3695	"%08x 0 \| P %c %s %s %s %s .. %c%c%c %016llx\n",
3696	i << X86_PDPT_SHIFT,
3697	Pdpe.n.u4Reserved & 1? '!' : '.', /* mbz */
3698	Pdpe.n.u4Reserved & 4? '!' : '.', /* mbz */
3699	Pdpe.n.u1WriteThru ? "WT" : "--",
3700	Pdpe.n.u1CacheDisable? "CD" : "--",
3701	Pdpe.n.u4Reserved & 2? "!" : "..",/* mbz */
3702	Pdpe.u & RT_BIT(9) ? '1' : '0',
3703	Pdpe.u & PGM_PLXFLAGS_PERMANENT ? 'p' : '-',
3704	Pdpe.u & RT_BIT(11) ? '1' : '0',
3705	Pdpe.u & X86_PDPE_PG_MASK);
3706	if (cMaxDepth >= 1)
3707	{
3708	int rc2 = pgmR3DumpHierarchyHCPaePD(pVM, Pdpe.u & X86_PDPE_PG_MASK, u64Address + ((uint64_t)i << X86_PDPT_SHIFT),
3709	cr4, fLongMode, cMaxDepth - 1, pHlp);
3710	if (rc2 < rc && RT_SUCCESS(rc))
3711	rc = rc2;
3712	}
3713	}
3714	}
3715	return rc;
3716	}
3717
3718
3719	/**
3720	* Dumps a 32-bit shadow page table.
3721	*
3722	* @returns VBox status code (VINF_SUCCESS).
3723	* @param pVM The VM handle.
3724	* @param HCPhys The physical address of the table.
3725	* @param cr4 The CR4, PSE is currently used.
3726	* @param cMaxDepth The maxium depth.
3727	* @param pHlp Pointer to the output functions.
3728	*/
3729	static int pgmR3DumpHierarchyHcPaePML4(PVM pVM, RTHCPHYS HCPhys, uint32_t cr4, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
3730	{
3731	PX86PML4 pPML4 = (PX86PML4)MMPagePhys2Page(pVM, HCPhys);
3732	if (!pPML4)
3733	{
3734	pHlp->pfnPrintf(pHlp, "Page map level 4 at HCPhys=%RHp was not found in the page pool!\n", HCPhys);
3735	return VERR_INVALID_PARAMETER;
3736	}
3737
3738	int rc = VINF_SUCCESS;
3739	for (unsigned i = 0; i < RT_ELEMENTS(pPML4->a); i++)
3740	{
3741	X86PML4E Pml4e = pPML4->a[i];
3742	if (Pml4e.n.u1Present)
3743	{
3744	uint64_t u64Address = ((uint64_t)i << X86_PML4_SHIFT) \| (((uint64_t)i >> (X86_PML4_SHIFT - X86_PDPT_SHIFT - 1)) * 0xffff000000000000ULL);
3745	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a p ? /
3746	"%016llx 0 \| P %c %c %c %c %c %s %s %s %s .. %c%c%c %016llx\n",
3747	u64Address,
3748	Pml4e.n.u1Write ? 'W' : 'R',
3749	Pml4e.n.u1User ? 'U' : 'S',
3750	Pml4e.n.u1Accessed ? 'A' : '-',
3751	Pml4e.n.u3Reserved & 1? '?' : '.', /* ignored */
3752	Pml4e.n.u3Reserved & 4? '!' : '.', /* mbz */
3753	Pml4e.n.u1WriteThru ? "WT" : "--",
3754	Pml4e.n.u1CacheDisable? "CD" : "--",
3755	Pml4e.n.u3Reserved & 2? "!" : "..",/* mbz */
3756	Pml4e.n.u1NoExecute ? "NX" : "--",
3757	Pml4e.u & RT_BIT(9) ? '1' : '0',
3758	Pml4e.u & PGM_PLXFLAGS_PERMANENT ? 'p' : '-',
3759	Pml4e.u & RT_BIT(11) ? '1' : '0',
3760	Pml4e.u & X86_PML4E_PG_MASK);
3761
3762	if (cMaxDepth >= 1)
3763	{
3764	int rc2 = pgmR3DumpHierarchyHCPaePDPT(pVM, Pml4e.u & X86_PML4E_PG_MASK, u64Address, cr4, true, cMaxDepth - 1, pHlp);
3765	if (rc2 < rc && RT_SUCCESS(rc))
3766	rc = rc2;
3767	}
3768	}
3769	}
3770	return rc;
3771	}
3772
3773
3774	/**
3775	* Dumps a 32-bit shadow page table.
3776	*
3777	* @returns VBox status code (VINF_SUCCESS).
3778	* @param pVM The VM handle.
3779	* @param pPT Pointer to the page table.
3780	* @param u32Address The virtual address this table starts at.
3781	* @param pHlp Pointer to the output functions.
3782	*/
3783	int pgmR3DumpHierarchyHC32BitPT(PVM pVM, PX86PT pPT, uint32_t u32Address, PCDBGFINFOHLP pHlp)
3784	{
3785	for (unsigned i = 0; i < RT_ELEMENTS(pPT->a); i++)
3786	{
3787	X86PTE Pte = pPT->a[i];
3788	if (Pte.n.u1Present)
3789	{
3790	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a m d /
3791	"%08x 1 \| P %c %c %c %c %c %s %s %s .. 4K %c%c%c %08x\n",
3792	u32Address + (i << X86_PT_SHIFT),
3793	Pte.n.u1Write ? 'W' : 'R',
3794	Pte.n.u1User ? 'U' : 'S',
3795	Pte.n.u1Accessed ? 'A' : '-',
3796	Pte.n.u1Dirty ? 'D' : '-',
3797	Pte.n.u1Global ? 'G' : '-',
3798	Pte.n.u1WriteThru ? "WT" : "--",
3799	Pte.n.u1CacheDisable? "CD" : "--",
3800	Pte.n.u1PAT ? "AT" : "--",
3801	Pte.u & PGM_PTFLAGS_TRACK_DIRTY ? 'd' : '-',
3802	Pte.u & RT_BIT(10) ? '1' : '0',
3803	Pte.u & PGM_PTFLAGS_CSAM_VALIDATED ? 'v' : '-',
3804	Pte.u & X86_PDE_PG_MASK);
3805	}
3806	}
3807	return VINF_SUCCESS;
3808	}
3809
3810
3811	/**
3812	* Dumps a 32-bit shadow page directory and page tables.
3813	*
3814	* @returns VBox status code (VINF_SUCCESS).
3815	* @param pVM The VM handle.
3816	* @param cr3 The root of the hierarchy.
3817	* @param cr4 The CR4, PSE is currently used.
3818	* @param cMaxDepth How deep into the hierarchy the dumper should go.
3819	* @param pHlp Pointer to the output functions.
3820	*/
3821	int pgmR3DumpHierarchyHC32BitPD(PVM pVM, uint32_t cr3, uint32_t cr4, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
3822	{
3823	PX86PD pPD = (PX86PD)MMPagePhys2Page(pVM, cr3 & X86_CR3_PAGE_MASK);
3824	if (!pPD)
3825	{
3826	pHlp->pfnPrintf(pHlp, "Page directory at %#x was not found in the page pool!\n", cr3 & X86_CR3_PAGE_MASK);
3827	return VERR_INVALID_PARAMETER;
3828	}
3829
3830	int rc = VINF_SUCCESS;
3831	for (unsigned i = 0; i < RT_ELEMENTS(pPD->a); i++)
3832	{
3833	X86PDE Pde = pPD->a[i];
3834	if (Pde.n.u1Present)
3835	{
3836	const uint32_t u32Address = i << X86_PD_SHIFT;
3837	if ((cr4 & X86_CR4_PSE) && Pde.b.u1Size)
3838	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a m d /
3839	"%08x 0 \| P %c %c %c %c %c %s %s %s .. 4M %c%c%c %08x\n",
3840	u32Address,
3841	Pde.b.u1Write ? 'W' : 'R',
3842	Pde.b.u1User ? 'U' : 'S',
3843	Pde.b.u1Accessed ? 'A' : '-',
3844	Pde.b.u1Dirty ? 'D' : '-',
3845	Pde.b.u1Global ? 'G' : '-',
3846	Pde.b.u1WriteThru ? "WT" : "--",
3847	Pde.b.u1CacheDisable? "CD" : "--",
3848	Pde.b.u1PAT ? "AT" : "--",
3849	Pde.u & RT_BIT_64(9) ? '1' : '0',
3850	Pde.u & PGM_PDFLAGS_MAPPING ? 'm' : '-',
3851	Pde.u & PGM_PDFLAGS_TRACK_DIRTY ? 'd' : '-',
3852	Pde.u & X86_PDE4M_PG_MASK);
3853	else
3854	{
3855	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a m d /
3856	"%08x 0 \| P %c %c %c %c %c %s %s .. .. 4K %c%c%c %08x\n",
3857	u32Address,
3858	Pde.n.u1Write ? 'W' : 'R',
3859	Pde.n.u1User ? 'U' : 'S',
3860	Pde.n.u1Accessed ? 'A' : '-',
3861	Pde.n.u1Reserved0 ? '?' : '.', /* ignored */
3862	Pde.n.u1Reserved1 ? '?' : '.', /* ignored */
3863	Pde.n.u1WriteThru ? "WT" : "--",
3864	Pde.n.u1CacheDisable? "CD" : "--",
3865	Pde.u & RT_BIT_64(9) ? '1' : '0',
3866	Pde.u & PGM_PDFLAGS_MAPPING ? 'm' : '-',
3867	Pde.u & PGM_PDFLAGS_TRACK_DIRTY ? 'd' : '-',
3868	Pde.u & X86_PDE_PG_MASK);
3869	if (cMaxDepth >= 1)
3870	{
3871	/** @todo what about using the page pool for mapping PTs? */
3872	RTHCPHYS HCPhys = Pde.u & X86_PDE_PG_MASK;
3873	PX86PT pPT = NULL;
3874	if (!(Pde.u & PGM_PDFLAGS_MAPPING))
3875	pPT = (PX86PT)MMPagePhys2Page(pVM, HCPhys);
3876	else
3877	{
3878	for (PPGMMAPPING pMap = pVM->pgm.s.pMappingsR3; pMap; pMap = pMap->pNextR3)
3879	if (u32Address - pMap->GCPtr < pMap->cb)
3880	{
3881	int iPDE = (u32Address - pMap->GCPtr) >> X86_PD_SHIFT;
3882	if (pMap->aPTs[iPDE].HCPhysPT != HCPhys)
3883	pHlp->pfnPrintf(pHlp, "%08x error! Mapping error! PT %d has HCPhysPT=%RHp not %RHp is in the PD.\n",
3884	u32Address, iPDE, pMap->aPTs[iPDE].HCPhysPT, HCPhys);
3885	pPT = pMap->aPTs[iPDE].pPTR3;
3886	}
3887	}
3888	int rc2 = VERR_INVALID_PARAMETER;
3889	if (pPT)
3890	rc2 = pgmR3DumpHierarchyHC32BitPT(pVM, pPT, u32Address, pHlp);
3891	else
3892	pHlp->pfnPrintf(pHlp, "%08x error! Page table at %#x was not found in the page pool!\n", u32Address, HCPhys);
3893	if (rc2 < rc && RT_SUCCESS(rc))
3894	rc = rc2;
3895	}
3896	}
3897	}
3898	}
3899
3900	return rc;
3901	}
3902
3903
3904	/**
3905	* Dumps a 32-bit shadow page table.
3906	*
3907	* @returns VBox status code (VINF_SUCCESS).
3908	* @param pVM The VM handle.
3909	* @param pPT Pointer to the page table.
3910	* @param u32Address The virtual address this table starts at.
3911	* @param PhysSearch Address to search for.
3912	*/
3913	int pgmR3DumpHierarchyGC32BitPT(PVM pVM, PX86PT pPT, uint32_t u32Address, RTGCPHYS PhysSearch)
3914	{
3915	for (unsigned i = 0; i < RT_ELEMENTS(pPT->a); i++)
3916	{
3917	X86PTE Pte = pPT->a[i];
3918	if (Pte.n.u1Present)
3919	{
3920	Log(( /P R S A D G WT CD AT NX 4M a m d /
3921	"%08x 1 \| P %c %c %c %c %c %s %s %s .. 4K %c%c%c %08x\n",
3922	u32Address + (i << X86_PT_SHIFT),
3923	Pte.n.u1Write ? 'W' : 'R',
3924	Pte.n.u1User ? 'U' : 'S',
3925	Pte.n.u1Accessed ? 'A' : '-',
3926	Pte.n.u1Dirty ? 'D' : '-',
3927	Pte.n.u1Global ? 'G' : '-',
3928	Pte.n.u1WriteThru ? "WT" : "--",
3929	Pte.n.u1CacheDisable? "CD" : "--",
3930	Pte.n.u1PAT ? "AT" : "--",
3931	Pte.u & PGM_PTFLAGS_TRACK_DIRTY ? 'd' : '-',
3932	Pte.u & RT_BIT(10) ? '1' : '0',
3933	Pte.u & PGM_PTFLAGS_CSAM_VALIDATED ? 'v' : '-',
3934	Pte.u & X86_PDE_PG_MASK));
3935
3936	if ((Pte.u & X86_PDE_PG_MASK) == PhysSearch)
3937	{
3938	uint64_t fPageShw = 0;
3939	RTHCPHYS pPhysHC = 0;
3940
3941	PGMShwGetPage(pVM, (RTGCPTR)(u32Address + (i << X86_PT_SHIFT)), &fPageShw, &pPhysHC);
3942	Log(("Found %RGp at %RGv -> flags=%llx\n", PhysSearch, (RTGCPTR)(u32Address + (i << X86_PT_SHIFT)), fPageShw));
3943	}
3944	}
3945	}
3946	return VINF_SUCCESS;
3947	}
3948
3949
3950	/**
3951	* Dumps a 32-bit guest page directory and page tables.
3952	*
3953	* @returns VBox status code (VINF_SUCCESS).
3954	* @param pVM The VM handle.
3955	* @param cr3 The root of the hierarchy.
3956	* @param cr4 The CR4, PSE is currently used.
3957	* @param PhysSearch Address to search for.
3958	*/
3959	VMMR3DECL(int) PGMR3DumpHierarchyGC(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCPHYS PhysSearch)
3960	{
3961	bool fLongMode = false;
3962	const unsigned cch = fLongMode ? 16 : 8; NOREF(cch);
3963	PX86PD pPD = 0;
3964
3965	int rc = PGM_GCPHYS_2_PTR(pVM, cr3 & X86_CR3_PAGE_MASK, &pPD);
3966	if (RT_FAILURE(rc) \|\| !pPD)
3967	{
3968	Log(("Page directory at %#x was not found in the page pool!\n", cr3 & X86_CR3_PAGE_MASK));
3969	return VERR_INVALID_PARAMETER;
3970	}
3971
3972	Log(("cr3=%08x cr4=%08x%s\n"
3973	"%-*s P - Present\n"
3974	"%-*s \| R/W - Read (0) / Write (1)\n"
3975	"%-*s \| \| U/S - User (1) / Supervisor (0)\n"
3976	"%-*s \| \| \| A - Accessed\n"
3977	"%-*s \| \| \| \| D - Dirty\n"
3978	"%-*s \| \| \| \| \| G - Global\n"
3979	"%-*s \| \| \| \| \| \| WT - Write thru\n"
3980	"%-*s \| \| \| \| \| \| \| CD - Cache disable\n"
3981	"%-*s \| \| \| \| \| \| \| \| AT - Attribute table (PAT)\n"
3982	"%-*s \| \| \| \| \| \| \| \| \| NX - No execute (K8)\n"
3983	"%-*s \| \| \| \| \| \| \| \| \| \| 4K/4M/2M - Page size.\n"
3984	"%-*s \| \| \| \| \| \| \| \| \| \| \| AVL - a=allocated; m=mapping; d=track dirty;\n"
3985	"%-*s \| \| \| \| \| \| \| \| \| \| \| \| p=permanent; v=validated;\n"
3986	"%-*s Level \| \| \| \| \| \| \| \| \| \| \| \| Page\n"
3987	/* xxxx n **** P R S A D G WT CD AT NX 4M AVL xxxxxxxxxxxxx
3988	- W U - - - -- -- -- -- -- 010 */
3989	, cr3, cr4, fLongMode ? " Long Mode" : "",
3990	cch, "", cch, "", cch, "", cch, "", cch, "", cch, "", cch, "",
3991	cch, "", cch, "", cch, "", cch, "", cch, "", cch, "", cch, "Address"));
3992
3993	for (unsigned i = 0; i < RT_ELEMENTS(pPD->a); i++)
3994	{
3995	X86PDE Pde = pPD->a[i];
3996	if (Pde.n.u1Present)
3997	{
3998	const uint32_t u32Address = i << X86_PD_SHIFT;
3999
4000	if ((cr4 & X86_CR4_PSE) && Pde.b.u1Size)
4001	Log(( /P R S A D G WT CD AT NX 4M a m d /
4002	"%08x 0 \| P %c %c %c %c %c %s %s %s .. 4M %c%c%c %08x\n",
4003	u32Address,
4004	Pde.b.u1Write ? 'W' : 'R',
4005	Pde.b.u1User ? 'U' : 'S',
4006	Pde.b.u1Accessed ? 'A' : '-',
4007	Pde.b.u1Dirty ? 'D' : '-',
4008	Pde.b.u1Global ? 'G' : '-',
4009	Pde.b.u1WriteThru ? "WT" : "--",
4010	Pde.b.u1CacheDisable? "CD" : "--",
4011	Pde.b.u1PAT ? "AT" : "--",
4012	Pde.u & RT_BIT(9) ? '1' : '0',
4013	Pde.u & RT_BIT(10) ? '1' : '0',
4014	Pde.u & RT_BIT(11) ? '1' : '0',
4015	pgmGstGet4MBPhysPage(&pVM->pgm.s, Pde)));
4016	/** @todo PhysSearch */
4017	else
4018	{
4019	Log(( /P R S A D G WT CD AT NX 4M a m d /
4020	"%08x 0 \| P %c %c %c %c %c %s %s .. .. 4K %c%c%c %08x\n",
4021	u32Address,
4022	Pde.n.u1Write ? 'W' : 'R',
4023	Pde.n.u1User ? 'U' : 'S',
4024	Pde.n.u1Accessed ? 'A' : '-',
4025	Pde.n.u1Reserved0 ? '?' : '.', /* ignored */
4026	Pde.n.u1Reserved1 ? '?' : '.', /* ignored */
4027	Pde.n.u1WriteThru ? "WT" : "--",
4028	Pde.n.u1CacheDisable? "CD" : "--",
4029	Pde.u & RT_BIT(9) ? '1' : '0',
4030	Pde.u & RT_BIT(10) ? '1' : '0',
4031	Pde.u & RT_BIT(11) ? '1' : '0',
4032	Pde.u & X86_PDE_PG_MASK));
4033	////if (cMaxDepth >= 1)
4034	{
4035	/** @todo what about using the page pool for mapping PTs? */
4036	RTGCPHYS GCPhys = Pde.u & X86_PDE_PG_MASK;
4037	PX86PT pPT = NULL;
4038
4039	rc = PGM_GCPHYS_2_PTR(pVM, GCPhys, &pPT);
4040
4041	int rc2 = VERR_INVALID_PARAMETER;
4042	if (pPT)
4043	rc2 = pgmR3DumpHierarchyGC32BitPT(pVM, pPT, u32Address, PhysSearch);
4044	else
4045	Log(("%08x error! Page table at %#x was not found in the page pool!\n", u32Address, GCPhys));
4046	if (rc2 < rc && RT_SUCCESS(rc))
4047	rc = rc2;
4048	}
4049	}
4050	}
4051	}
4052
4053	return rc;
4054	}
4055
4056
4057	/**
4058	* Dumps a page table hierarchy use only physical addresses and cr4/lm flags.
4059	*
4060	* @returns VBox status code (VINF_SUCCESS).
4061	* @param pVM The VM handle.
4062	* @param cr3 The root of the hierarchy.
4063	* @param cr4 The cr4, only PAE and PSE is currently used.
4064	* @param fLongMode Set if long mode, false if not long mode.
4065	* @param cMaxDepth Number of levels to dump.
4066	* @param pHlp Pointer to the output functions.
4067	*/
4068	VMMR3DECL(int) PGMR3DumpHierarchyHC(PVM pVM, uint64_t cr3, uint64_t cr4, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
4069	{
4070	if (!pHlp)
4071	pHlp = DBGFR3InfoLogHlp();
4072	if (!cMaxDepth)
4073	return VINF_SUCCESS;
4074	const unsigned cch = fLongMode ? 16 : 8;
4075	pHlp->pfnPrintf(pHlp,
4076	"cr3=%08x cr4=%08x%s\n"
4077	"%-*s P - Present\n"
4078	"%-*s \| R/W - Read (0) / Write (1)\n"
4079	"%-*s \| \| U/S - User (1) / Supervisor (0)\n"
4080	"%-*s \| \| \| A - Accessed\n"
4081	"%-*s \| \| \| \| D - Dirty\n"
4082	"%-*s \| \| \| \| \| G - Global\n"
4083	"%-*s \| \| \| \| \| \| WT - Write thru\n"
4084	"%-*s \| \| \| \| \| \| \| CD - Cache disable\n"
4085	"%-*s \| \| \| \| \| \| \| \| AT - Attribute table (PAT)\n"
4086	"%-*s \| \| \| \| \| \| \| \| \| NX - No execute (K8)\n"
4087	"%-*s \| \| \| \| \| \| \| \| \| \| 4K/4M/2M - Page size.\n"
4088	"%-*s \| \| \| \| \| \| \| \| \| \| \| AVL - a=allocated; m=mapping; d=track dirty;\n"
4089	"%-*s \| \| \| \| \| \| \| \| \| \| \| \| p=permanent; v=validated;\n"
4090	"%-*s Level \| \| \| \| \| \| \| \| \| \| \| \| Page\n"
4091	/* xxxx n **** P R S A D G WT CD AT NX 4M AVL xxxxxxxxxxxxx
4092	- W U - - - -- -- -- -- -- 010 */
4093	, cr3, cr4, fLongMode ? " Long Mode" : "",
4094	cch, "", cch, "", cch, "", cch, "", cch, "", cch, "", cch, "",
4095	cch, "", cch, "", cch, "", cch, "", cch, "", cch, "", cch, "Address");
4096	if (cr4 & X86_CR4_PAE)
4097	{
4098	if (fLongMode)
4099	return pgmR3DumpHierarchyHcPaePML4(pVM, cr3 & X86_CR3_PAGE_MASK, cr4, cMaxDepth, pHlp);
4100	return pgmR3DumpHierarchyHCPaePDPT(pVM, cr3 & X86_CR3_PAE_PAGE_MASK, 0, cr4, false, cMaxDepth, pHlp);
4101	}
4102	return pgmR3DumpHierarchyHC32BitPD(pVM, cr3 & X86_CR3_PAGE_MASK, cr4, cMaxDepth, pHlp);
4103	}
4104
4105	#ifdef VBOX_WITH_DEBUGGER
4106
4107	/**
4108	* The '.pgmram' command.
4109	*
4110	* @returns VBox status.
4111	* @param pCmd Pointer to the command descriptor (as registered).
4112	* @param pCmdHlp Pointer to command helper functions.
4113	* @param pVM Pointer to the current VM (if any).
4114	* @param paArgs Pointer to (readonly) array of arguments.
4115	* @param cArgs Number of arguments in the array.
4116	*/
4117	static DECLCALLBACK(int) pgmR3CmdRam(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4118	{
4119	/*
4120	* Validate input.
4121	*/
4122	if (!pVM)
4123	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4124	if (!pVM->pgm.s.pRamRangesRC)
4125	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Sorry, no Ram is registered.\n");
4126
4127	/*
4128	* Dump the ranges.
4129	*/
4130	int rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL, "From - To (incl) pvHC\n");
4131	PPGMRAMRANGE pRam;
4132	for (pRam = pVM->pgm.s.pRamRangesR3; pRam; pRam = pRam->pNextR3)
4133	{
4134	rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL,
4135	"%RGp - %RGp %p\n",
4136	pRam->GCPhys, pRam->GCPhysLast, pRam->pvR3);
4137	if (RT_FAILURE(rc))
4138	return rc;
4139	}
4140
4141	return VINF_SUCCESS;
4142	}
4143
4144
4145	/**
4146	* The '.pgmmap' command.
4147	*
4148	* @returns VBox status.
4149	* @param pCmd Pointer to the command descriptor (as registered).
4150	* @param pCmdHlp Pointer to command helper functions.
4151	* @param pVM Pointer to the current VM (if any).
4152	* @param paArgs Pointer to (readonly) array of arguments.
4153	* @param cArgs Number of arguments in the array.
4154	*/
4155	static DECLCALLBACK(int) pgmR3CmdMap(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4156	{
4157	/*
4158	* Validate input.
4159	*/
4160	if (!pVM)
4161	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4162	if (!pVM->pgm.s.pMappingsR3)
4163	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Sorry, no mappings are registered.\n");
4164
4165	/*
4166	* Print message about the fixedness of the mappings.
4167	*/
4168	int rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL, pVM->pgm.s.fMappingsFixed ? "The mappings are FIXED.\n" : "The mappings are FLOATING.\n");
4169	if (RT_FAILURE(rc))
4170	return rc;
4171
4172	/*
4173	* Dump the ranges.
4174	*/
4175	PPGMMAPPING pCur;
4176	for (pCur = pVM->pgm.s.pMappingsR3; pCur; pCur = pCur->pNextR3)
4177	{
4178	rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL,
4179	"%08x - %08x %s\n",
4180	pCur->GCPtr, pCur->GCPtrLast, pCur->pszDesc);
4181	if (RT_FAILURE(rc))
4182	return rc;
4183	}
4184
4185	return VINF_SUCCESS;
4186	}
4187
4188
4189	/**
4190	* The '.pgmsync' command.
4191	*
4192	* @returns VBox status.
4193	* @param pCmd Pointer to the command descriptor (as registered).
4194	* @param pCmdHlp Pointer to command helper functions.
4195	* @param pVM Pointer to the current VM (if any).
4196	* @param paArgs Pointer to (readonly) array of arguments.
4197	* @param cArgs Number of arguments in the array.
4198	*/
4199	static DECLCALLBACK(int) pgmR3CmdSync(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4200	{
4201	/*
4202	* Validate input.
4203	*/
4204	if (!pVM)
4205	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4206
4207	/*
4208	* Force page directory sync.
4209	*/
4210	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
4211
4212	int rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Forcing page directory sync.\n");
4213	if (RT_FAILURE(rc))
4214	return rc;
4215
4216	return VINF_SUCCESS;
4217	}
4218
4219
4220	#ifdef VBOX_STRICT
4221	/**
4222	* The '.pgmassertcr3' command.
4223	*
4224	* @returns VBox status.
4225	* @param pCmd Pointer to the command descriptor (as registered).
4226	* @param pCmdHlp Pointer to command helper functions.
4227	* @param pVM Pointer to the current VM (if any).
4228	* @param paArgs Pointer to (readonly) array of arguments.
4229	* @param cArgs Number of arguments in the array.
4230	*/
4231	static DECLCALLBACK(int) pgmR3CmdAssertCR3(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4232	{
4233	/*
4234	* Validate input.
4235	*/
4236	if (!pVM)
4237	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4238
4239	int rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Checking shadow CR3 page tables for consistency.\n");
4240	if (RT_FAILURE(rc))
4241	return rc;
4242
4243	PGMAssertCR3(pVM, CPUMGetGuestCR3(pVM), CPUMGetGuestCR4(pVM));
4244
4245	return VINF_SUCCESS;
4246	}
4247	#endif /* VBOX_STRICT */
4248
4249
4250	/**
4251	* The '.pgmsyncalways' command.
4252	*
4253	* @returns VBox status.
4254	* @param pCmd Pointer to the command descriptor (as registered).
4255	* @param pCmdHlp Pointer to command helper functions.
4256	* @param pVM Pointer to the current VM (if any).
4257	* @param paArgs Pointer to (readonly) array of arguments.
4258	* @param cArgs Number of arguments in the array.
4259	*/
4260	static DECLCALLBACK(int) pgmR3CmdSyncAlways(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4261	{
4262	/*
4263	* Validate input.
4264	*/
4265	if (!pVM)
4266	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4267
4268	/*
4269	* Force page directory sync.
4270	*/
4271	if (pVM->pgm.s.fSyncFlags & PGM_SYNC_ALWAYS)
4272	{
4273	ASMAtomicAndU32(&pVM->pgm.s.fSyncFlags, ~PGM_SYNC_ALWAYS);
4274	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Disabled permanent forced page directory syncing.\n");
4275	}
4276	else
4277	{
4278	ASMAtomicOrU32(&pVM->pgm.s.fSyncFlags, PGM_SYNC_ALWAYS);
4279	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
4280	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Enabled permanent forced page directory syncing.\n");
4281	}
4282	}
4283
4284	#endif /* VBOX_WITH_DEBUGGER */
4285
4286	/**
4287	* pvUser argument of the pgmR3CheckIntegrity*Node callbacks.
4288	*/
4289	typedef struct PGMCHECKINTARGS
4290	{
4291	bool fLeftToRight; /*< true: left-to-right; false: right-to-left. /
4292	PPGMPHYSHANDLER pPrevPhys;
4293	PPGMVIRTHANDLER pPrevVirt;
4294	PPGMPHYS2VIRTHANDLER pPrevPhys2Virt;
4295	PVM pVM;
4296	} PGMCHECKINTARGS, *PPGMCHECKINTARGS;
4297
4298	/**
4299	* Validate a node in the physical handler tree.
4300	*
4301	* @returns 0 on if ok, other wise 1.
4302	* @param pNode The handler node.
4303	* @param pvUser pVM.
4304	*/
4305	static DECLCALLBACK(int) pgmR3CheckIntegrityPhysHandlerNode(PAVLROGCPHYSNODECORE pNode, void *pvUser)
4306	{
4307	PPGMCHECKINTARGS pArgs = (PPGMCHECKINTARGS)pvUser;
4308	PPGMPHYSHANDLER pCur = (PPGMPHYSHANDLER)pNode;
4309	AssertReleaseReturn(!((uintptr_t)pCur & 7), 1);
4310	AssertReleaseMsg(pCur->Core.Key <= pCur->Core.KeyLast,("pCur=%p %RGp-%RGp %s\n", pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
4311	AssertReleaseMsg( !pArgs->pPrevPhys
4312	\|\| (pArgs->fLeftToRight ? pArgs->pPrevPhys->Core.KeyLast < pCur->Core.Key : pArgs->pPrevPhys->Core.KeyLast > pCur->Core.Key),
4313	("pPrevPhys=%p %RGp-%RGp %s\n"
4314	" pCur=%p %RGp-%RGp %s\n",
4315	pArgs->pPrevPhys, pArgs->pPrevPhys->Core.Key, pArgs->pPrevPhys->Core.KeyLast, pArgs->pPrevPhys->pszDesc,
4316	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
4317	pArgs->pPrevPhys = pCur;
4318	return 0;
4319	}
4320
4321
4322	/**
4323	* Validate a node in the virtual handler tree.
4324	*
4325	* @returns 0 on if ok, other wise 1.
4326	* @param pNode The handler node.
4327	* @param pvUser pVM.
4328	*/
4329	static DECLCALLBACK(int) pgmR3CheckIntegrityVirtHandlerNode(PAVLROGCPTRNODECORE pNode, void *pvUser)
4330	{
4331	PPGMCHECKINTARGS pArgs = (PPGMCHECKINTARGS)pvUser;
4332	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)pNode;
4333	AssertReleaseReturn(!((uintptr_t)pCur & 7), 1);
4334	AssertReleaseMsg(pCur->Core.Key <= pCur->Core.KeyLast,("pCur=%p %RGv-%RGv %s\n", pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
4335	AssertReleaseMsg( !pArgs->pPrevVirt
4336	\|\| (pArgs->fLeftToRight ? pArgs->pPrevVirt->Core.KeyLast < pCur->Core.Key : pArgs->pPrevVirt->Core.KeyLast > pCur->Core.Key),
4337	("pPrevVirt=%p %RGv-%RGv %s\n"
4338	" pCur=%p %RGv-%RGv %s\n",
4339	pArgs->pPrevVirt, pArgs->pPrevVirt->Core.Key, pArgs->pPrevVirt->Core.KeyLast, pArgs->pPrevVirt->pszDesc,
4340	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
4341	for (unsigned iPage = 0; iPage < pCur->cPages; iPage++)
4342	{
4343	AssertReleaseMsg(pCur->aPhysToVirt[iPage].offVirtHandler == -RT_OFFSETOF(PGMVIRTHANDLER, aPhysToVirt[iPage]),
4344	("pCur=%p %RGv-%RGv %s\n"
4345	"iPage=%d offVirtHandle=%#x expected %#x\n",
4346	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc,
4347	iPage, pCur->aPhysToVirt[iPage].offVirtHandler, -RT_OFFSETOF(PGMVIRTHANDLER, aPhysToVirt[iPage])));
4348	}
4349	pArgs->pPrevVirt = pCur;
4350	return 0;
4351	}
4352
4353
4354	/**
4355	* Validate a node in the virtual handler tree.
4356	*
4357	* @returns 0 on if ok, other wise 1.
4358	* @param pNode The handler node.
4359	* @param pvUser pVM.
4360	*/
4361	static DECLCALLBACK(int) pgmR3CheckIntegrityPhysToVirtHandlerNode(PAVLROGCPHYSNODECORE pNode, void *pvUser)
4362	{
4363	PPGMCHECKINTARGS pArgs = (PPGMCHECKINTARGS)pvUser;
4364	PPGMPHYS2VIRTHANDLER pCur = (PPGMPHYS2VIRTHANDLER)pNode;
4365	AssertReleaseMsgReturn(!((uintptr_t)pCur & 3), ("\n"), 1);
4366	AssertReleaseMsgReturn(!(pCur->offVirtHandler & 3), ("\n"), 1);
4367	AssertReleaseMsg(pCur->Core.Key <= pCur->Core.KeyLast,("pCur=%p %RGp-%RGp\n", pCur, pCur->Core.Key, pCur->Core.KeyLast));
4368	AssertReleaseMsg( !pArgs->pPrevPhys2Virt
4369	\|\| (pArgs->fLeftToRight ? pArgs->pPrevPhys2Virt->Core.KeyLast < pCur->Core.Key : pArgs->pPrevPhys2Virt->Core.KeyLast > pCur->Core.Key),
4370	("pPrevPhys2Virt=%p %RGp-%RGp\n"
4371	" pCur=%p %RGp-%RGp\n",
4372	pArgs->pPrevPhys2Virt, pArgs->pPrevPhys2Virt->Core.Key, pArgs->pPrevPhys2Virt->Core.KeyLast,
4373	pCur, pCur->Core.Key, pCur->Core.KeyLast));
4374	AssertReleaseMsg( !pArgs->pPrevPhys2Virt
4375	\|\| (pArgs->fLeftToRight ? pArgs->pPrevPhys2Virt->Core.KeyLast < pCur->Core.Key : pArgs->pPrevPhys2Virt->Core.KeyLast > pCur->Core.Key),
4376	("pPrevPhys2Virt=%p %RGp-%RGp\n"
4377	" pCur=%p %RGp-%RGp\n",
4378	pArgs->pPrevPhys2Virt, pArgs->pPrevPhys2Virt->Core.Key, pArgs->pPrevPhys2Virt->Core.KeyLast,
4379	pCur, pCur->Core.Key, pCur->Core.KeyLast));
4380	AssertReleaseMsg((pCur->offNextAlias & (PGMPHYS2VIRTHANDLER_IN_TREE \| PGMPHYS2VIRTHANDLER_IS_HEAD)) == (PGMPHYS2VIRTHANDLER_IN_TREE \| PGMPHYS2VIRTHANDLER_IS_HEAD),
4381	("pCur=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4382	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias));
4383	if (pCur->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK)
4384	{
4385	PPGMPHYS2VIRTHANDLER pCur2 = pCur;
4386	for (;;)
4387	{
4388	pCur2 = (PPGMPHYS2VIRTHANDLER)((intptr_t)pCur + (pCur->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK));
4389	AssertReleaseMsg(pCur2 != pCur,
4390	(" pCur=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4391	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias));
4392	AssertReleaseMsg((pCur2->offNextAlias & (PGMPHYS2VIRTHANDLER_IN_TREE \| PGMPHYS2VIRTHANDLER_IS_HEAD)) == PGMPHYS2VIRTHANDLER_IN_TREE,
4393	(" pCur=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
4394	"pCur2=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4395	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias,
4396	pCur2, pCur2->Core.Key, pCur2->Core.KeyLast, pCur2->offVirtHandler, pCur2->offNextAlias));
4397	AssertReleaseMsg((pCur2->Core.Key ^ pCur->Core.Key) < PAGE_SIZE,
4398	(" pCur=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
4399	"pCur2=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4400	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias,
4401	pCur2, pCur2->Core.Key, pCur2->Core.KeyLast, pCur2->offVirtHandler, pCur2->offNextAlias));
4402	AssertReleaseMsg((pCur2->Core.KeyLast ^ pCur->Core.KeyLast) < PAGE_SIZE,
4403	(" pCur=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
4404	"pCur2=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4405	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias,
4406	pCur2, pCur2->Core.Key, pCur2->Core.KeyLast, pCur2->offVirtHandler, pCur2->offNextAlias));
4407	if (!(pCur2->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK))
4408	break;
4409	}
4410	}
4411
4412	pArgs->pPrevPhys2Virt = pCur;
4413	return 0;
4414	}
4415
4416
4417	/**
4418	* Perform an integrity check on the PGM component.
4419	*
4420	* @returns VINF_SUCCESS if everything is fine.
4421	* @returns VBox error status after asserting on integrity breach.
4422	* @param pVM The VM handle.
4423	*/
4424	VMMR3DECL(int) PGMR3CheckIntegrity(PVM pVM)
4425	{
4426	AssertReleaseReturn(pVM->pgm.s.offVM, VERR_INTERNAL_ERROR);
4427
4428	/*
4429	* Check the trees.
4430	*/
4431	int cErrors = 0;
4432	const static PGMCHECKINTARGS s_LeftToRight = { true, NULL, NULL, NULL, pVM };
4433	const static PGMCHECKINTARGS s_RightToLeft = { false, NULL, NULL, NULL, pVM };
4434	PGMCHECKINTARGS Args = s_LeftToRight;
4435	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysHandlers, true, pgmR3CheckIntegrityPhysHandlerNode, &Args);
4436	Args = s_RightToLeft;
4437	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysHandlers, false, pgmR3CheckIntegrityPhysHandlerNode, &Args);
4438	Args = s_LeftToRight;
4439	cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesR3->VirtHandlers, true, pgmR3CheckIntegrityVirtHandlerNode, &Args);
4440	Args = s_RightToLeft;
4441	cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesR3->VirtHandlers, false, pgmR3CheckIntegrityVirtHandlerNode, &Args);
4442	Args = s_LeftToRight;
4443	cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesR3->HyperVirtHandlers, true, pgmR3CheckIntegrityVirtHandlerNode, &Args);
4444	Args = s_RightToLeft;
4445	cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesR3->HyperVirtHandlers, false, pgmR3CheckIntegrityVirtHandlerNode, &Args);
4446	Args = s_LeftToRight;
4447	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysToVirtHandlers, true, pgmR3CheckIntegrityPhysToVirtHandlerNode, &Args);
4448	Args = s_RightToLeft;
4449	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysToVirtHandlers, false, pgmR3CheckIntegrityPhysToVirtHandlerNode, &Args);
4450
4451	return !cErrors ? VINF_SUCCESS : VERR_INTERNAL_ERROR;
4452	}
4453
4454
4455	/**
4456	* Inform PGM if we want all mappings to be put into the shadow page table. (necessary for e.g. VMX)
4457	*
4458	* @returns VBox status code.
4459	* @param pVM VM handle.
4460	* @param fEnable Enable or disable shadow mappings
4461	*/
4462	VMMR3DECL(int) PGMR3ChangeShwPDMappings(PVM pVM, bool fEnable)
4463	{
4464	pVM->pgm.s.fDisableMappings = !fEnable;
4465
4466	uint32_t cb;
4467	int rc = PGMR3MappingsSize(pVM, &cb);
4468	AssertRCReturn(rc, rc);
4469
4470	/* Pretend the mappings are now fixed; to force a refresh of the reserved PDEs. */
4471	rc = PGMR3MappingsFix(pVM, MM_HYPER_AREA_ADDRESS, cb);
4472	AssertRCReturn(rc, rc);
4473
4474	return VINF_SUCCESS;
4475	}
4476

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source: vbox/trunk/src/VBox/VMM/PGM.cpp@ 14038

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