PGM.cpp@ 14157

Last change on this file since 14157 was 14154, checked in by vboxsync, 16 years ago
PGM: pGuestPD* -> pGst32BitPd*
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1	/* $Id: PGM.cpp 14154 2008-11-12 23:34:50Z vboxsync $ */
2	/** @file
3	* PGM - Page Manager and Monitor. (Mixing stuff here, not good?)
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22
23	/** @page pg_pgm PGM - The Page Manager and Monitor
24	*
25	* @see grp_pgm,
26	* @ref pg_pgm_pool,
27	* @ref pg_pgm_phys.
28	*
29	*
30	* @section sec_pgm_modes Paging Modes
31	*
32	* There are three memory contexts: Host Context (HC), Guest Context (GC)
33	* and intermediate context. When talking about paging HC can also be refered to
34	* as "host paging", and GC refered to as "shadow paging".
35	*
36	* We define three basic paging modes: 32-bit, PAE and AMD64. The host paging mode
37	* is defined by the host operating system. The mode used in the shadow paging mode
38	* depends on the host paging mode and what the mode the guest is currently in. The
39	* following relation between the two is defined:
40	*
41	* @verbatim
42	Host > 32-bit \| PAE \| AMD64 \|
43	Guest \| \| \| \|
44	==v================================
45	32-bit 32-bit PAE PAE
46	-------\|--------\|--------\|--------\|
47	PAE PAE PAE PAE
48	-------\|--------\|--------\|--------\|
49	AMD64 AMD64 AMD64 AMD64
50	-------\|--------\|--------\|--------\| @endverbatim
51	*
52	* All configuration except those in the diagonal (upper left) are expected to
53	* require special effort from the switcher (i.e. a bit slower).
54	*
55	*
56	*
57	*
58	* @section sec_pgm_shw The Shadow Memory Context
59	*
60	*
61	* [..]
62	*
63	* Because of guest context mappings requires PDPT and PML4 entries to allow
64	* writing on AMD64, the two upper levels will have fixed flags whatever the
65	* guest is thinking of using there. So, when shadowing the PD level we will
66	* calculate the effective flags of PD and all the higher levels. In legacy
67	* PAE mode this only applies to the PWT and PCD bits (the rest are
68	* ignored/reserved/MBZ). We will ignore those bits for the present.
69	*
70	*
71	*
72	* @section sec_pgm_int The Intermediate Memory Context
73	*
74	* The world switch goes thru an intermediate memory context which purpose it is
75	* to provide different mappings of the switcher code. All guest mappings are also
76	* present in this context.
77	*
78	* The switcher code is mapped at the same location as on the host, at an
79	* identity mapped location (physical equals virtual address), and at the
80	* hypervisor location.
81	*
82	* PGM maintain page tables for 32-bit, PAE and AMD64 paging modes. This
83	* simplifies switching guest CPU mode and consistency at the cost of more
84	* code to do the work. All memory use for those page tables is located below
85	* 4GB (this includes page tables for guest context mappings).
86	*
87	*
88	* @subsection subsec_pgm_int_gc Guest Context Mappings
89	*
90	* During assignment and relocation of a guest context mapping the intermediate
91	* memory context is used to verify the new location.
92	*
93	* Guest context mappings are currently restricted to below 4GB, for reasons
94	* of simplicity. This may change when we implement AMD64 support.
95	*
96	*
97	*
98	*
99	* @section sec_pgm_misc Misc
100	*
101	* @subsection subsec_pgm_misc_diff Differences Between Legacy PAE and Long Mode PAE
102	*
103	* The differences between legacy PAE and long mode PAE are:
104	* -# PDPE bits 1, 2, 5 and 6 are defined differently. In leagcy mode they are
105	* all marked down as must-be-zero, while in long mode 1, 2 and 5 have the
106	* usual meanings while 6 is ignored (AMD). This means that upon switching to
107	* legacy PAE mode we'll have to clear these bits and when going to long mode
108	* they must be set. This applies to both intermediate and shadow contexts,
109	* however we don't need to do it for the intermediate one since we're
110	* executing with CR0.WP at that time.
111	* -# CR3 allows a 32-byte aligned address in legacy mode, while in long mode
112	* a page aligned one is required.
113	*
114	*
115	* @section sec_pgm_handlers Access Handlers
116	*
117	* Placeholder.
118	*
119	*
120	* @subsection sec_pgm_handlers_virt Virtual Access Handlers
121	*
122	* Placeholder.
123	*
124	*
125	* @subsection sec_pgm_handlers_virt Virtual Access Handlers
126	*
127	* We currently implement three types of virtual access handlers: ALL, WRITE
128	* and HYPERVISOR (WRITE). See PGMVIRTHANDLERTYPE for some more details.
129	*
130	* The HYPERVISOR access handlers is kept in a separate tree since it doesn't apply
131	* to physical pages (PGMTREES::HyperVirtHandlers) and only needs to be consulted in
132	* a special \#PF case. The ALL and WRITE are in the PGMTREES::VirtHandlers tree, the
133	* rest of this section is going to be about these handlers.
134	*
135	* We'll go thru the life cycle of a handler and try make sense of it all, don't know
136	* how successfull this is gonna be...
137	*
138	* 1. A handler is registered thru the PGMR3HandlerVirtualRegister and
139	* PGMHandlerVirtualRegisterEx APIs. We check for conflicting virtual handlers
140	* and create a new node that is inserted into the AVL tree (range key). Then
141	* a full PGM resync is flagged (clear pool, sync cr3, update virtual bit of PGMPAGE).
142	*
143	* 2. The following PGMSyncCR3/SyncCR3 operation will first make invoke HandlerVirtualUpdate.
144	*
145	* 2a. HandlerVirtualUpdate will will lookup all the pages covered by virtual handlers
146	* via the current guest CR3 and update the physical page -> virtual handler
147	* translation. Needless to say, this doesn't exactly scale very well. If any changes
148	* are detected, it will flag a virtual bit update just like we did on registration.
149	* PGMPHYS pages with changes will have their virtual handler state reset to NONE.
150	*
151	* 2b. The virtual bit update process will iterate all the pages covered by all the
152	* virtual handlers and update the PGMPAGE virtual handler state to the max of all
153	* virtual handlers on that page.
154	*
155	* 2c. Back in SyncCR3 we will now flush the entire shadow page cache to make sure
156	* we don't miss any alias mappings of the monitored pages.
157	*
158	* 2d. SyncCR3 will then proceed with syncing the CR3 table.
159	*
160	* 3. \#PF(np,read) on a page in the range. This will cause it to be synced
161	* read-only and resumed if it's a WRITE handler. If it's an ALL handler we
162	* will call the handlers like in the next step. If the physical mapping has
163	* changed we will - some time in the future - perform a handler callback
164	* (optional) and update the physical -> virtual handler cache.
165	*
166	* 4. \#PF(,write) on a page in the range. This will cause the handler to
167	* be invoked.
168	*
169	* 5. The guest invalidates the page and changes the physical backing or
170	* unmaps it. This should cause the invalidation callback to be invoked
171	* (it might not yet be 100% perfect). Exactly what happens next... is
172	* this where we mess up and end up out of sync for a while?
173	*
174	* 6. The handler is deregistered by the client via PGMHandlerVirtualDeregister.
175	* We will then set all PGMPAGEs in the physical -> virtual handler cache for
176	* this handler to NONE and trigger a full PGM resync (basically the same
177	* as int step 1). Which means 2 is executed again.
178	*
179	*
180	* @subsubsection sub_sec_pgm_handler_virt_todo TODOs
181	*
182	* There is a bunch of things that needs to be done to make the virtual handlers
183	* work 100% correctly and work more efficiently.
184	*
185	* The first bit hasn't been implemented yet because it's going to slow the
186	* whole mess down even more, and besides it seems to be working reliably for
187	* our current uses. OTOH, some of the optimizations might end up more or less
188	* implementing the missing bits, so we'll see.
189	*
190	* On the optimization side, the first thing to do is to try avoid unnecessary
191	* cache flushing. Then try team up with the shadowing code to track changes
192	* in mappings by means of access to them (shadow in), updates to shadows pages,
193	* invlpg, and shadow PT discarding (perhaps).
194	*
195	* Some idea that have popped up for optimization for current and new features:
196	* - bitmap indicating where there are virtual handlers installed.
197	* (4KB => 220 pages, page 212 => covers 32-bit address space 1:1!)
198	* - Further optimize this by min/max (needs min/max avl getters).
199	* - Shadow page table entry bit (if any left)?
200	*
201	*/
202
203
204	/** @page pg_pgm_phys PGM Physical Guest Memory Management
205	*
206	*
207	* Objectives:
208	* - Guest RAM over-commitment using memory ballooning,
209	* zero pages and general page sharing.
210	* - Moving or mirroring a VM onto a different physical machine.
211	*
212	*
213	* @subsection subsec_pgmPhys_Definitions Definitions
214	*
215	* Allocation chunk - A RTR0MemObjAllocPhysNC object and the tracking
216	* machinery assoicated with it.
217	*
218	*
219	*
220	*
221	* @subsection subsec_pgmPhys_AllocPage Allocating a page.
222	*
223	* Initially we map all guest memory to the (per VM) zero page, which
224	* means that none of the read functions will cause pages to be allocated.
225	*
226	* Exception, access bit in page tables that have been shared. This must
227	* be handled, but we must also make sure PGMGst*Modify doesn't make
228	* unnecessary modifications.
229	*
230	* Allocation points:
231	* - PGMPhysSimpleWriteGCPhys and PGMPhysWrite.
232	* - Replacing a zero page mapping at \#PF.
233	* - Replacing a shared page mapping at \#PF.
234	* - ROM registration (currently MMR3RomRegister).
235	* - VM restore (pgmR3Load).
236	*
237	* For the first three it would make sense to keep a few pages handy
238	* until we've reached the max memory commitment for the VM.
239	*
240	* For the ROM registration, we know exactly how many pages we need
241	* and will request these from ring-0. For restore, we will save
242	* the number of non-zero pages in the saved state and allocate
243	* them up front. This would allow the ring-0 component to refuse
244	* the request if the isn't sufficient memory available for VM use.
245	*
246	* Btw. for both ROM and restore allocations we won't be requiring
247	* zeroed pages as they are going to be filled instantly.
248	*
249	*
250	* @subsection subsec_pgmPhys_FreePage Freeing a page
251	*
252	* There are a few points where a page can be freed:
253	* - After being replaced by the zero page.
254	* - After being replaced by a shared page.
255	* - After being ballooned by the guest additions.
256	* - At reset.
257	* - At restore.
258	*
259	* When freeing one or more pages they will be returned to the ring-0
260	* component and replaced by the zero page.
261	*
262	* The reasoning for clearing out all the pages on reset is that it will
263	* return us to the exact same state as on power on, and may thereby help
264	* us reduce the memory load on the system. Further it might have a
265	* (temporary) positive influence on memory fragmentation (@see subsec_pgmPhys_Fragmentation).
266	*
267	* On restore, as mention under the allocation topic, pages should be
268	* freed / allocated depending on how many is actually required by the
269	* new VM state. The simplest approach is to do like on reset, and free
270	* all non-ROM pages and then allocate what we need.
271	*
272	* A measure to prevent some fragmentation, would be to let each allocation
273	* chunk have some affinity towards the VM having allocated the most pages
274	* from it. Also, try make sure to allocate from allocation chunks that
275	* are almost full. Admittedly, both these measures might work counter to
276	* our intentions and its probably not worth putting a lot of effort,
277	* cpu time or memory into this.
278	*
279	*
280	* @subsection subsec_pgmPhys_SharePage Sharing a page
281	*
282	* The basic idea is that there there will be a idle priority kernel
283	* thread walking the non-shared VM pages hashing them and looking for
284	* pages with the same checksum. If such pages are found, it will compare
285	* them byte-by-byte to see if they actually are identical. If found to be
286	* identical it will allocate a shared page, copy the content, check that
287	* the page didn't change while doing this, and finally request both the
288	* VMs to use the shared page instead. If the page is all zeros (special
289	* checksum and byte-by-byte check) it will request the VM that owns it
290	* to replace it with the zero page.
291	*
292	* To make this efficient, we will have to make sure not to try share a page
293	* that will change its contents soon. This part requires the most work.
294	* A simple idea would be to request the VM to write monitor the page for
295	* a while to make sure it isn't modified any time soon. Also, it may
296	* make sense to skip pages that are being write monitored since this
297	* information is readily available to the thread if it works on the
298	* per-VM guest memory structures (presently called PGMRAMRANGE).
299	*
300	*
301	* @subsection subsec_pgmPhys_Fragmentation Fragmentation Concerns and Counter Measures
302	*
303	* The pages are organized in allocation chunks in ring-0, this is a necessity
304	* if we wish to have an OS agnostic approach to this whole thing. (On Linux we
305	* could easily work on a page-by-page basis if we liked. Whether this is possible
306	* or efficient on NT I don't quite know.) Fragmentation within these chunks may
307	* become a problem as part of the idea here is that we wish to return memory to
308	* the host system.
309	*
310	* For instance, starting two VMs at the same time, they will both allocate the
311	* guest memory on-demand and if permitted their page allocations will be
312	* intermixed. Shut down one of the two VMs and it will be difficult to return
313	* any memory to the host system because the page allocation for the two VMs are
314	* mixed up in the same allocation chunks.
315	*
316	* To further complicate matters, when pages are freed because they have been
317	* ballooned or become shared/zero the whole idea is that the page is supposed
318	* to be reused by another VM or returned to the host system. This will cause
319	* allocation chunks to contain pages belonging to different VMs and prevent
320	* returning memory to the host when one of those VM shuts down.
321	*
322	* The only way to really deal with this problem is to move pages. This can
323	* either be done at VM shutdown and or by the idle priority worker thread
324	* that will be responsible for finding sharable/zero pages. The mechanisms
325	* involved for coercing a VM to move a page (or to do it for it) will be
326	* the same as when telling it to share/zero a page.
327	*
328	*
329	* @subsection subsec_pgmPhys_Tracking Tracking Structures And Their Cost
330	*
331	* There's a difficult balance between keeping the per-page tracking structures
332	* (global and guest page) easy to use and keeping them from eating too much
333	* memory. We have limited virtual memory resources available when operating in
334	* 32-bit kernel space (on 64-bit there'll it's quite a different story). The
335	* tracking structures will be attemted designed such that we can deal with up
336	* to 32GB of memory on a 32-bit system and essentially unlimited on 64-bit ones.
337	*
338	*
339	* @subsubsection subsubsec_pgmPhys_Tracking_Kernel Kernel Space
340	*
341	* @see pg_GMM
342	*
343	* @subsubsection subsubsec_pgmPhys_Tracking_PerVM Per-VM
344	*
345	* Fixed info is the physical address of the page (HCPhys) and the page id
346	* (described above). Theoretically we'll need 48(-12) bits for the HCPhys part.
347	* Today we've restricting ourselves to 40(-12) bits because this is the current
348	* restrictions of all AMD64 implementations (I think Barcelona will up this
349	* to 48(-12) bits, not that it really matters) and I needed the bits for
350	* tracking mappings of a page. 48-12 = 36. That leaves 28 bits, which means a
351	* decent range for the page id: 2^(28+12) = 1024TB.
352	*
353	* In additions to these, we'll have to keep maintaining the page flags as we
354	* currently do. Although it wouldn't harm to optimize these quite a bit, like
355	* for instance the ROM shouldn't depend on having a write handler installed
356	* in order for it to become read-only. A RO/RW bit should be considered so
357	* that the page syncing code doesn't have to mess about checking multiple
358	* flag combinations (ROM \|\| RW handler \|\| write monitored) in order to
359	* figure out how to setup a shadow PTE. But this of course, is second
360	* priority at present. Current this requires 12 bits, but could probably
361	* be optimized to ~8.
362	*
363	* Then there's the 24 bits used to track which shadow page tables are
364	* currently mapping a page for the purpose of speeding up physical
365	* access handlers, and thereby the page pool cache. More bit for this
366	* purpose wouldn't hurt IIRC.
367	*
368	* Then there is a new bit in which we need to record what kind of page
369	* this is, shared, zero, normal or write-monitored-normal. This'll
370	* require 2 bits. One bit might be needed for indicating whether a
371	* write monitored page has been written to. And yet another one or
372	* two for tracking migration status. 3-4 bits total then.
373	*
374	* Whatever is left will can be used to record the sharabilitiy of a
375	* page. The page checksum will not be stored in the per-VM table as
376	* the idle thread will not be permitted to do modifications to it.
377	* It will instead have to keep its own working set of potentially
378	* shareable pages and their check sums and stuff.
379	*
380	* For the present we'll keep the current packing of the
381	* PGMRAMRANGE::aHCPhys to keep the changes simple, only of course,
382	* we'll have to change it to a struct with a total of 128-bits at
383	* our disposal.
384	*
385	* The initial layout will be like this:
386	* @verbatim
387	RTHCPHYS HCPhys; The current stuff.
388	63:40 Current shadow PT tracking stuff.
389	39:12 The physical page frame number.
390	11:0 The current flags.
391	uint32_t u28PageId : 28; The page id.
392	uint32_t u2State : 2; The page state { zero, shared, normal, write monitored }.
393	uint32_t fWrittenTo : 1; Whether a write monitored page was written to.
394	uint32_t u1Reserved : 1; Reserved for later.
395	uint32_t u32Reserved; Reserved for later, mostly sharing stats.
396	@endverbatim
397	*
398	* The final layout will be something like this:
399	* @verbatim
400	RTHCPHYS HCPhys; The current stuff.
401	63:48 High page id (12+).
402	47:12 The physical page frame number.
403	11:0 Low page id.
404	uint32_t fReadOnly : 1; Whether it's readonly page (rom or monitored in some way).
405	uint32_t u3Type : 3; The page type {RESERVED, MMIO, MMIO2, ROM, shadowed ROM, RAM}.
406	uint32_t u2PhysMon : 2; Physical access handler type {none, read, write, all}.
407	uint32_t u2VirtMon : 2; Virtual access handler type {none, read, write, all}..
408	uint32_t u2State : 2; The page state { zero, shared, normal, write monitored }.
409	uint32_t fWrittenTo : 1; Whether a write monitored page was written to.
410	uint32_t u20Reserved : 20; Reserved for later, mostly sharing stats.
411	uint32_t u32Tracking; The shadow PT tracking stuff, roughly.
412	@endverbatim
413	*
414	* Cost wise, this means we'll double the cost for guest memory. There isn't anyway
415	* around that I'm afraid. It means that the cost of dealing out 32GB of memory
416	* to one or more VMs is: (32GB >> PAGE_SHIFT) * 16 bytes, or 128MBs. Or another
417	* example, the VM heap cost when assigning 1GB to a VM will be: 4MB.
418	*
419	* A couple of cost examples for the total cost per-VM + kernel.
420	* 32-bit Windows and 32-bit linux:
421	* 1GB guest ram, 256K pages: 4MB + 2MB(+) = 6MB
422	* 4GB guest ram, 1M pages: 16MB + 8MB(+) = 24MB
423	* 32GB guest ram, 8M pages: 128MB + 64MB(+) = 192MB
424	* 64-bit Windows and 64-bit linux:
425	* 1GB guest ram, 256K pages: 4MB + 3MB(+) = 7MB
426	* 4GB guest ram, 1M pages: 16MB + 12MB(+) = 28MB
427	* 32GB guest ram, 8M pages: 128MB + 96MB(+) = 224MB
428	*
429	* UPDATE - 2007-09-27:
430	* Will need a ballooned flag/state too because we cannot
431	* trust the guest 100% and reporting the same page as ballooned more
432	* than once will put the GMM off balance.
433	*
434	*
435	* @subsection subsec_pgmPhys_Serializing Serializing Access
436	*
437	* Initially, we'll try a simple scheme:
438	*
439	* - The per-VM RAM tracking structures (PGMRAMRANGE) is only modified
440	* by the EMT thread of that VM while in the pgm critsect.
441	* - Other threads in the VM process that needs to make reliable use of
442	* the per-VM RAM tracking structures will enter the critsect.
443	* - No process external thread or kernel thread will ever try enter
444	* the pgm critical section, as that just won't work.
445	* - The idle thread (and similar threads) doesn't not need 100% reliable
446	* data when performing it tasks as the EMT thread will be the one to
447	* do the actual changes later anyway. So, as long as it only accesses
448	* the main ram range, it can do so by somehow preventing the VM from
449	* being destroyed while it works on it...
450	*
451	* - The over-commitment management, including the allocating/freeing
452	* chunks, is serialized by a ring-0 mutex lock (a fast one since the
453	* more mundane mutex implementation is broken on Linux).
454	* - A separeate mutex is protecting the set of allocation chunks so
455	* that pages can be shared or/and freed up while some other VM is
456	* allocating more chunks. This mutex can be take from under the other
457	* one, but not the otherway around.
458	*
459	*
460	* @subsection subsec_pgmPhys_Request VM Request interface
461	*
462	* When in ring-0 it will become necessary to send requests to a VM so it can
463	* for instance move a page while defragmenting during VM destroy. The idle
464	* thread will make use of this interface to request VMs to setup shared
465	* pages and to perform write monitoring of pages.
466	*
467	* I would propose an interface similar to the current VMReq interface, similar
468	* in that it doesn't require locking and that the one sending the request may
469	* wait for completion if it wishes to. This shouldn't be very difficult to
470	* realize.
471	*
472	* The requests themselves are also pretty simple. They are basically:
473	* -# Check that some precondition is still true.
474	* -# Do the update.
475	* -# Update all shadow page tables involved with the page.
476	*
477	* The 3rd step is identical to what we're already doing when updating a
478	* physical handler, see pgmHandlerPhysicalSetRamFlagsAndFlushShadowPTs.
479	*
480	*
481	*
482	* @section sec_pgmPhys_MappingCaches Mapping Caches
483	*
484	* In order to be able to map in and out memory and to be able to support
485	* guest with more RAM than we've got virtual address space, we'll employing
486	* a mapping cache. There is already a tiny one for GC (see PGMGCDynMapGCPageEx)
487	* and we'll create a similar one for ring-0 unless we decide to setup a dedicate
488	* memory context for the HWACCM execution.
489	*
490	*
491	* @subsection subsec_pgmPhys_MappingCaches_R3 Ring-3
492	*
493	* We've considered implementing the ring-3 mapping cache page based but found
494	* that this was bother some when one had to take into account TLBs+SMP and
495	* portability (missing the necessary APIs on several platforms). There were
496	* also some performance concerns with this approach which hadn't quite been
497	* worked out.
498	*
499	* Instead, we'll be mapping allocation chunks into the VM process. This simplifies
500	* matters greatly quite a bit since we don't need to invent any new ring-0 stuff,
501	* only some minor RTR0MEMOBJ mapping stuff. The main concern here is that mapping
502	* compared to the previous idea is that mapping or unmapping a 1MB chunk is more
503	* costly than a single page, although how much more costly is uncertain. We'll
504	* try address this by using a very big cache, preferably bigger than the actual
505	* VM RAM size if possible. The current VM RAM sizes should give some idea for
506	* 32-bit boxes, while on 64-bit we can probably get away with employing an
507	* unlimited cache.
508	*
509	* The cache have to parts, as already indicated, the ring-3 side and the
510	* ring-0 side.
511	*
512	* The ring-0 will be tied to the page allocator since it will operate on the
513	* memory objects it contains. It will therefore require the first ring-0 mutex
514	* discussed in @ref subsec_pgmPhys_Serializing. We
515	* some double house keeping wrt to who has mapped what I think, since both
516	* VMMR0.r0 and RTR0MemObj will keep track of mapping relataions
517	*
518	* The ring-3 part will be protected by the pgm critsect. For simplicity, we'll
519	* require anyone that desires to do changes to the mapping cache to do that
520	* from within this critsect. Alternatively, we could employ a separate critsect
521	* for serializing changes to the mapping cache as this would reduce potential
522	* contention with other threads accessing mappings unrelated to the changes
523	* that are in process. We can see about this later, contention will show
524	* up in the statistics anyway, so it'll be simple to tell.
525	*
526	* The organization of the ring-3 part will be very much like how the allocation
527	* chunks are organized in ring-0, that is in an AVL tree by chunk id. To avoid
528	* having to walk the tree all the time, we'll have a couple of lookaside entries
529	* like in we do for I/O ports and MMIO in IOM.
530	*
531	* The simplified flow of a PGMPhysRead/Write function:
532	* -# Enter the PGM critsect.
533	* -# Lookup GCPhys in the ram ranges and get the Page ID.
534	* -# Calc the Allocation Chunk ID from the Page ID.
535	* -# Check the lookaside entries and then the AVL tree for the Chunk ID.
536	* If not found in cache:
537	* -# Call ring-0 and request it to be mapped and supply
538	* a chunk to be unmapped if the cache is maxed out already.
539	* -# Insert the new mapping into the AVL tree (id + R3 address).
540	* -# Update the relevant lookaside entry and return the mapping address.
541	* -# Do the read/write according to monitoring flags and everything.
542	* -# Leave the critsect.
543	*
544	*
545	* @section sec_pgmPhys_Fallback Fallback
546	*
547	* Current all the "second tier" hosts will not support the RTR0MemObjAllocPhysNC
548	* API and thus require a fallback.
549	*
550	* So, when RTR0MemObjAllocPhysNC returns VERR_NOT_SUPPORTED the page allocator
551	* will return to the ring-3 caller (and later ring-0) and asking it to seed
552	* the page allocator with some fresh pages (VERR_GMM_SEED_ME). Ring-3 will
553	* then perform an SUPPageAlloc(cbChunk >> PAGE_SHIFT) call and make a
554	* "SeededAllocPages" call to ring-0.
555	*
556	* The first time ring-0 sees the VERR_NOT_SUPPORTED failure it will disable
557	* all page sharing (zero page detection will continue). It will also force
558	* all allocations to come from the VM which seeded the page. Both these
559	* measures are taken to make sure that there will never be any need for
560	* mapping anything into ring-3 - everything will be mapped already.
561	*
562	* Whether we'll continue to use the current MM locked memory management
563	* for this I don't quite know (I'd prefer not to and just ditch that all
564	* togther), we'll see what's simplest to do.
565	*
566	*
567	*
568	* @section sec_pgmPhys_Changes Changes
569	*
570	* Breakdown of the changes involved?
571	*/
572
573
574	/** Saved state data unit version. */
575	#define PGM_SAVED_STATE_VERSION 6
576
577	/*******************************************************************************
578	* Header Files *
579	*******************************************************************************/
580	#define LOG_GROUP LOG_GROUP_PGM
581	#include <VBox/dbgf.h>
582	#include <VBox/pgm.h>
583	#include <VBox/cpum.h>
584	#include <VBox/iom.h>
585	#include <VBox/sup.h>
586	#include <VBox/mm.h>
587	#include <VBox/em.h>
588	#include <VBox/stam.h>
589	#include <VBox/rem.h>
590	#include <VBox/dbgf.h>
591	#include <VBox/rem.h>
592	#include <VBox/selm.h>
593	#include <VBox/ssm.h>
594	#include "PGMInternal.h"
595	#include <VBox/vm.h>
596	#include <VBox/dbg.h>
597	#include <VBox/hwaccm.h>
598
599	#include <iprt/assert.h>
600	#include <iprt/alloc.h>
601	#include <iprt/asm.h>
602	#include <iprt/thread.h>
603	#include <iprt/string.h>
604	#ifdef DEBUG_bird
605	# include <iprt/env.h>
606	#endif
607	#include <VBox/param.h>
608	#include <VBox/err.h>
609
610
611
612	/*******************************************************************************
613	* Internal Functions *
614	*******************************************************************************/
615	static int pgmR3InitPaging(PVM pVM);
616	static DECLCALLBACK(void) pgmR3PhysInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
617	static DECLCALLBACK(void) pgmR3InfoMode(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
618	static DECLCALLBACK(void) pgmR3InfoCr3(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
619	static DECLCALLBACK(int) pgmR3RelocatePhysHandler(PAVLROGCPHYSNODECORE pNode, void *pvUser);
620	static DECLCALLBACK(int) pgmR3RelocateVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser);
621	static DECLCALLBACK(int) pgmR3RelocateHyperVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser);
622	#ifdef VBOX_STRICT
623	static DECLCALLBACK(void) pgmR3ResetNoMorePhysWritesFlag(PVM pVM, VMSTATE enmState, VMSTATE enmOldState, void *pvUser);
624	#endif
625	static DECLCALLBACK(int) pgmR3Save(PVM pVM, PSSMHANDLE pSSM);
626	static DECLCALLBACK(int) pgmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version);
627	static int pgmR3ModeDataInit(PVM pVM, bool fResolveGCAndR0);
628	static void pgmR3ModeDataSwitch(PVM pVM, PGMMODE enmShw, PGMMODE enmGst);
629	static PGMMODE pgmR3CalcShadowMode(PVM pVM, PGMMODE enmGuestMode, SUPPAGINGMODE enmHostMode, PGMMODE enmShadowMode, VMMSWITCHER *penmSwitcher);
630
631	#ifdef VBOX_WITH_STATISTICS
632	static void pgmR3InitStats(PVM pVM);
633	#endif
634
635	#ifdef VBOX_WITH_DEBUGGER
636	/** @todo all but the two last commands must be converted to 'info'. */
637	static DECLCALLBACK(int) pgmR3CmdRam(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
638	static DECLCALLBACK(int) pgmR3CmdMap(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
639	static DECLCALLBACK(int) pgmR3CmdSync(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
640	static DECLCALLBACK(int) pgmR3CmdSyncAlways(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
641	# ifdef VBOX_STRICT
642	static DECLCALLBACK(int) pgmR3CmdAssertCR3(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
643	# endif
644	#endif
645
646
647	/*******************************************************************************
648	* Global Variables *
649	*******************************************************************************/
650	#ifdef VBOX_WITH_DEBUGGER
651	/** Command descriptors. */
652	static const DBGCCMD g_aCmds[] =
653	{
654	/* pszCmd, cArgsMin, cArgsMax, paArgDesc, cArgDescs, pResultDesc, fFlags, pfnHandler pszSyntax, ....pszDescription */
655	{ "pgmram", 0, 0, NULL, 0, NULL, 0, pgmR3CmdRam, "", "Display the ram ranges." },
656	{ "pgmmap", 0, 0, NULL, 0, NULL, 0, pgmR3CmdMap, "", "Display the mapping ranges." },
657	{ "pgmsync", 0, 0, NULL, 0, NULL, 0, pgmR3CmdSync, "", "Sync the CR3 page." },
658	#ifdef VBOX_STRICT
659	{ "pgmassertcr3", 0, 0, NULL, 0, NULL, 0, pgmR3CmdAssertCR3, "", "Check the shadow CR3 mapping." },
660	#endif
661	{ "pgmsyncalways", 0, 0, NULL, 0, NULL, 0, pgmR3CmdSyncAlways, "", "Toggle permanent CR3 syncing." },
662	};
663	#endif
664
665
666
667
668	/*
669	* Shadow - 32-bit mode
670	*/
671	#define PGM_SHW_TYPE PGM_TYPE_32BIT
672	#define PGM_SHW_NAME(name) PGM_SHW_NAME_32BIT(name)
673	#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_32BIT_STR(name)
674	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_32BIT_STR(name)
675	#include "PGMShw.h"
676
677	/* Guest - real mode */
678	#define PGM_GST_TYPE PGM_TYPE_REAL
679	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
680	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_REAL_STR(name)
681	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
682	#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_REAL(name)
683	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_32BIT_REAL_STR(name)
684	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_32BIT_REAL_STR(name)
685	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_PHYS
686	#include "PGMGst.h"
687	#include "PGMBth.h"
688	#undef BTH_PGMPOOLKIND_PT_FOR_PT
689	#undef PGM_BTH_NAME
690	#undef PGM_BTH_NAME_RC_STR
691	#undef PGM_BTH_NAME_R0_STR
692	#undef PGM_GST_TYPE
693	#undef PGM_GST_NAME
694	#undef PGM_GST_NAME_RC_STR
695	#undef PGM_GST_NAME_R0_STR
696
697	/* Guest - protected mode */
698	#define PGM_GST_TYPE PGM_TYPE_PROT
699	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
700	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PROT_STR(name)
701	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
702	#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_PROT(name)
703	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_32BIT_PROT_STR(name)
704	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_32BIT_PROT_STR(name)
705	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_PHYS
706	#include "PGMGst.h"
707	#include "PGMBth.h"
708	#undef BTH_PGMPOOLKIND_PT_FOR_PT
709	#undef PGM_BTH_NAME
710	#undef PGM_BTH_NAME_RC_STR
711	#undef PGM_BTH_NAME_R0_STR
712	#undef PGM_GST_TYPE
713	#undef PGM_GST_NAME
714	#undef PGM_GST_NAME_RC_STR
715	#undef PGM_GST_NAME_R0_STR
716
717	/* Guest - 32-bit mode */
718	#define PGM_GST_TYPE PGM_TYPE_32BIT
719	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
720	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_32BIT_STR(name)
721	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
722	#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_32BIT(name)
723	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_32BIT_32BIT_STR(name)
724	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_32BIT_32BIT_STR(name)
725	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT
726	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB
727	#include "PGMGst.h"
728	#include "PGMBth.h"
729	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
730	#undef BTH_PGMPOOLKIND_PT_FOR_PT
731	#undef PGM_BTH_NAME
732	#undef PGM_BTH_NAME_RC_STR
733	#undef PGM_BTH_NAME_R0_STR
734	#undef PGM_GST_TYPE
735	#undef PGM_GST_NAME
736	#undef PGM_GST_NAME_RC_STR
737	#undef PGM_GST_NAME_R0_STR
738
739	#undef PGM_SHW_TYPE
740	#undef PGM_SHW_NAME
741	#undef PGM_SHW_NAME_RC_STR
742	#undef PGM_SHW_NAME_R0_STR
743
744
745	/*
746	* Shadow - PAE mode
747	*/
748	#define PGM_SHW_TYPE PGM_TYPE_PAE
749	#define PGM_SHW_NAME(name) PGM_SHW_NAME_PAE(name)
750	#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_PAE_STR(name)
751	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_PAE_STR(name)
752	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_REAL(name)
753	#include "PGMShw.h"
754
755	/* Guest - real mode */
756	#define PGM_GST_TYPE PGM_TYPE_REAL
757	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
758	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_REAL_STR(name)
759	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
760	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_REAL(name)
761	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_PAE_REAL_STR(name)
762	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_REAL_STR(name)
763	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
764	#include "PGMBth.h"
765	#undef BTH_PGMPOOLKIND_PT_FOR_PT
766	#undef PGM_BTH_NAME
767	#undef PGM_BTH_NAME_RC_STR
768	#undef PGM_BTH_NAME_R0_STR
769	#undef PGM_GST_TYPE
770	#undef PGM_GST_NAME
771	#undef PGM_GST_NAME_RC_STR
772	#undef PGM_GST_NAME_R0_STR
773
774	/* Guest - protected mode */
775	#define PGM_GST_TYPE PGM_TYPE_PROT
776	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
777	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PROT_STR(name)
778	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
779	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_PROT(name)
780	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_PAE_PROT_STR(name)
781	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_PROT_STR(name)
782	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
783	#include "PGMBth.h"
784	#undef BTH_PGMPOOLKIND_PT_FOR_PT
785	#undef PGM_BTH_NAME
786	#undef PGM_BTH_NAME_RC_STR
787	#undef PGM_BTH_NAME_R0_STR
788	#undef PGM_GST_TYPE
789	#undef PGM_GST_NAME
790	#undef PGM_GST_NAME_RC_STR
791	#undef PGM_GST_NAME_R0_STR
792
793	/* Guest - 32-bit mode */
794	#define PGM_GST_TYPE PGM_TYPE_32BIT
795	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
796	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_32BIT_STR(name)
797	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
798	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_32BIT(name)
799	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_PAE_32BIT_STR(name)
800	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_32BIT_STR(name)
801	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_32BIT_PT
802	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB
803	#include "PGMBth.h"
804	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
805	#undef BTH_PGMPOOLKIND_PT_FOR_PT
806	#undef PGM_BTH_NAME
807	#undef PGM_BTH_NAME_RC_STR
808	#undef PGM_BTH_NAME_R0_STR
809	#undef PGM_GST_TYPE
810	#undef PGM_GST_NAME
811	#undef PGM_GST_NAME_RC_STR
812	#undef PGM_GST_NAME_R0_STR
813
814	/* Guest - PAE mode */
815	#define PGM_GST_TYPE PGM_TYPE_PAE
816	#define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
817	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PAE_STR(name)
818	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PAE_STR(name)
819	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_PAE(name)
820	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_PAE_PAE_STR(name)
821	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_PAE_STR(name)
822	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
823	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
824	#include "PGMGst.h"
825	#include "PGMBth.h"
826	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
827	#undef BTH_PGMPOOLKIND_PT_FOR_PT
828	#undef PGM_BTH_NAME
829	#undef PGM_BTH_NAME_RC_STR
830	#undef PGM_BTH_NAME_R0_STR
831	#undef PGM_GST_TYPE
832	#undef PGM_GST_NAME
833	#undef PGM_GST_NAME_RC_STR
834	#undef PGM_GST_NAME_R0_STR
835
836	#undef PGM_SHW_TYPE
837	#undef PGM_SHW_NAME
838	#undef PGM_SHW_NAME_RC_STR
839	#undef PGM_SHW_NAME_R0_STR
840
841
842	/*
843	* Shadow - AMD64 mode
844	*/
845	#define PGM_SHW_TYPE PGM_TYPE_AMD64
846	#define PGM_SHW_NAME(name) PGM_SHW_NAME_AMD64(name)
847	#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_AMD64_STR(name)
848	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_AMD64_STR(name)
849	#include "PGMShw.h"
850
851	#ifdef VBOX_WITH_64_BITS_GUESTS
852	/* Guest - AMD64 mode */
853	# define PGM_GST_TYPE PGM_TYPE_AMD64
854	# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
855	# define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_AMD64_STR(name)
856	# define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_AMD64_STR(name)
857	# define PGM_BTH_NAME(name) PGM_BTH_NAME_AMD64_AMD64(name)
858	# define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_AMD64_AMD64_STR(name)
859	# define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_AMD64_AMD64_STR(name)
860	# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
861	# define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
862	# include "PGMGst.h"
863	# include "PGMBth.h"
864	# undef BTH_PGMPOOLKIND_PT_FOR_BIG
865	# undef BTH_PGMPOOLKIND_PT_FOR_PT
866	# undef PGM_BTH_NAME
867	# undef PGM_BTH_NAME_RC_STR
868	# undef PGM_BTH_NAME_R0_STR
869	# undef PGM_GST_TYPE
870	# undef PGM_GST_NAME
871	# undef PGM_GST_NAME_RC_STR
872	# undef PGM_GST_NAME_R0_STR
873	#endif /* VBOX_WITH_64_BITS_GUESTS */
874
875	#undef PGM_SHW_TYPE
876	#undef PGM_SHW_NAME
877	#undef PGM_SHW_NAME_RC_STR
878	#undef PGM_SHW_NAME_R0_STR
879
880
881	/*
882	* Shadow - Nested paging mode
883	*/
884	#define PGM_SHW_TYPE PGM_TYPE_NESTED
885	#define PGM_SHW_NAME(name) PGM_SHW_NAME_NESTED(name)
886	#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_NESTED_STR(name)
887	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_NESTED_STR(name)
888	#include "PGMShw.h"
889
890	/* Guest - real mode */
891	#define PGM_GST_TYPE PGM_TYPE_REAL
892	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
893	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_REAL_STR(name)
894	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
895	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_REAL(name)
896	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_REAL_STR(name)
897	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_REAL_STR(name)
898	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
899	#include "PGMBth.h"
900	#undef BTH_PGMPOOLKIND_PT_FOR_PT
901	#undef PGM_BTH_NAME
902	#undef PGM_BTH_NAME_RC_STR
903	#undef PGM_BTH_NAME_R0_STR
904	#undef PGM_GST_TYPE
905	#undef PGM_GST_NAME
906	#undef PGM_GST_NAME_RC_STR
907	#undef PGM_GST_NAME_R0_STR
908
909	/* Guest - protected mode */
910	#define PGM_GST_TYPE PGM_TYPE_PROT
911	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
912	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PROT_STR(name)
913	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
914	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_PROT(name)
915	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_PROT_STR(name)
916	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_PROT_STR(name)
917	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
918	#include "PGMBth.h"
919	#undef BTH_PGMPOOLKIND_PT_FOR_PT
920	#undef PGM_BTH_NAME
921	#undef PGM_BTH_NAME_RC_STR
922	#undef PGM_BTH_NAME_R0_STR
923	#undef PGM_GST_TYPE
924	#undef PGM_GST_NAME
925	#undef PGM_GST_NAME_RC_STR
926	#undef PGM_GST_NAME_R0_STR
927
928	/* Guest - 32-bit mode */
929	#define PGM_GST_TYPE PGM_TYPE_32BIT
930	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
931	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_32BIT_STR(name)
932	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
933	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_32BIT(name)
934	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_32BIT_STR(name)
935	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_32BIT_STR(name)
936	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_32BIT_PT
937	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB
938	#include "PGMBth.h"
939	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
940	#undef BTH_PGMPOOLKIND_PT_FOR_PT
941	#undef PGM_BTH_NAME
942	#undef PGM_BTH_NAME_RC_STR
943	#undef PGM_BTH_NAME_R0_STR
944	#undef PGM_GST_TYPE
945	#undef PGM_GST_NAME
946	#undef PGM_GST_NAME_RC_STR
947	#undef PGM_GST_NAME_R0_STR
948
949	/* Guest - PAE mode */
950	#define PGM_GST_TYPE PGM_TYPE_PAE
951	#define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
952	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PAE_STR(name)
953	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PAE_STR(name)
954	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_PAE(name)
955	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_PAE_STR(name)
956	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_PAE_STR(name)
957	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
958	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
959	#include "PGMBth.h"
960	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
961	#undef BTH_PGMPOOLKIND_PT_FOR_PT
962	#undef PGM_BTH_NAME
963	#undef PGM_BTH_NAME_RC_STR
964	#undef PGM_BTH_NAME_R0_STR
965	#undef PGM_GST_TYPE
966	#undef PGM_GST_NAME
967	#undef PGM_GST_NAME_RC_STR
968	#undef PGM_GST_NAME_R0_STR
969
970	#ifdef VBOX_WITH_64_BITS_GUESTS
971	/* Guest - AMD64 mode */
972	# define PGM_GST_TYPE PGM_TYPE_AMD64
973	# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
974	# define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_AMD64_STR(name)
975	# define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_AMD64_STR(name)
976	# define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_AMD64(name)
977	# define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_AMD64_STR(name)
978	# define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_AMD64_STR(name)
979	# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
980	# define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
981	# include "PGMBth.h"
982	# undef BTH_PGMPOOLKIND_PT_FOR_BIG
983	# undef BTH_PGMPOOLKIND_PT_FOR_PT
984	# undef PGM_BTH_NAME
985	# undef PGM_BTH_NAME_RC_STR
986	# undef PGM_BTH_NAME_R0_STR
987	# undef PGM_GST_TYPE
988	# undef PGM_GST_NAME
989	# undef PGM_GST_NAME_RC_STR
990	# undef PGM_GST_NAME_R0_STR
991	#endif /* VBOX_WITH_64_BITS_GUESTS */
992
993	#undef PGM_SHW_TYPE
994	#undef PGM_SHW_NAME
995	#undef PGM_SHW_NAME_RC_STR
996	#undef PGM_SHW_NAME_R0_STR
997
998
999	/*
1000	* Shadow - EPT
1001	*/
1002	#define PGM_SHW_TYPE PGM_TYPE_EPT
1003	#define PGM_SHW_NAME(name) PGM_SHW_NAME_EPT(name)
1004	#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_EPT_STR(name)
1005	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_EPT_STR(name)
1006	#include "PGMShw.h"
1007
1008	/* Guest - real mode */
1009	#define PGM_GST_TYPE PGM_TYPE_REAL
1010	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
1011	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_REAL_STR(name)
1012	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
1013	#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_REAL(name)
1014	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_REAL_STR(name)
1015	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_REAL_STR(name)
1016	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
1017	#include "PGMBth.h"
1018	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1019	#undef PGM_BTH_NAME
1020	#undef PGM_BTH_NAME_RC_STR
1021	#undef PGM_BTH_NAME_R0_STR
1022	#undef PGM_GST_TYPE
1023	#undef PGM_GST_NAME
1024	#undef PGM_GST_NAME_RC_STR
1025	#undef PGM_GST_NAME_R0_STR
1026
1027	/* Guest - protected mode */
1028	#define PGM_GST_TYPE PGM_TYPE_PROT
1029	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
1030	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PROT_STR(name)
1031	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
1032	#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_PROT(name)
1033	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_PROT_STR(name)
1034	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_PROT_STR(name)
1035	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
1036	#include "PGMBth.h"
1037	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1038	#undef PGM_BTH_NAME
1039	#undef PGM_BTH_NAME_RC_STR
1040	#undef PGM_BTH_NAME_R0_STR
1041	#undef PGM_GST_TYPE
1042	#undef PGM_GST_NAME
1043	#undef PGM_GST_NAME_RC_STR
1044	#undef PGM_GST_NAME_R0_STR
1045
1046	/* Guest - 32-bit mode */
1047	#define PGM_GST_TYPE PGM_TYPE_32BIT
1048	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
1049	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_32BIT_STR(name)
1050	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
1051	#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_32BIT(name)
1052	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_32BIT_STR(name)
1053	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_32BIT_STR(name)
1054	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_32BIT_PT
1055	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB
1056	#include "PGMBth.h"
1057	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
1058	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1059	#undef PGM_BTH_NAME
1060	#undef PGM_BTH_NAME_RC_STR
1061	#undef PGM_BTH_NAME_R0_STR
1062	#undef PGM_GST_TYPE
1063	#undef PGM_GST_NAME
1064	#undef PGM_GST_NAME_RC_STR
1065	#undef PGM_GST_NAME_R0_STR
1066
1067	/* Guest - PAE mode */
1068	#define PGM_GST_TYPE PGM_TYPE_PAE
1069	#define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
1070	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PAE_STR(name)
1071	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PAE_STR(name)
1072	#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_PAE(name)
1073	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_PAE_STR(name)
1074	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_PAE_STR(name)
1075	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
1076	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
1077	#include "PGMBth.h"
1078	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
1079	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1080	#undef PGM_BTH_NAME
1081	#undef PGM_BTH_NAME_RC_STR
1082	#undef PGM_BTH_NAME_R0_STR
1083	#undef PGM_GST_TYPE
1084	#undef PGM_GST_NAME
1085	#undef PGM_GST_NAME_RC_STR
1086	#undef PGM_GST_NAME_R0_STR
1087
1088	#ifdef VBOX_WITH_64_BITS_GUESTS
1089	/* Guest - AMD64 mode */
1090	# define PGM_GST_TYPE PGM_TYPE_AMD64
1091	# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
1092	# define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_AMD64_STR(name)
1093	# define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_AMD64_STR(name)
1094	# define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_AMD64(name)
1095	# define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_AMD64_STR(name)
1096	# define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_AMD64_STR(name)
1097	# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
1098	# define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
1099	# include "PGMBth.h"
1100	# undef BTH_PGMPOOLKIND_PT_FOR_BIG
1101	# undef BTH_PGMPOOLKIND_PT_FOR_PT
1102	# undef PGM_BTH_NAME
1103	# undef PGM_BTH_NAME_RC_STR
1104	# undef PGM_BTH_NAME_R0_STR
1105	# undef PGM_GST_TYPE
1106	# undef PGM_GST_NAME
1107	# undef PGM_GST_NAME_RC_STR
1108	# undef PGM_GST_NAME_R0_STR
1109	#endif /* VBOX_WITH_64_BITS_GUESTS */
1110
1111	#undef PGM_SHW_TYPE
1112	#undef PGM_SHW_NAME
1113	#undef PGM_SHW_NAME_RC_STR
1114	#undef PGM_SHW_NAME_R0_STR
1115
1116
1117
1118	/**
1119	* Initiates the paging of VM.
1120	*
1121	* @returns VBox status code.
1122	* @param pVM Pointer to VM structure.
1123	*/
1124	VMMR3DECL(int) PGMR3Init(PVM pVM)
1125	{
1126	LogFlow(("PGMR3Init:\n"));
1127
1128	/*
1129	* Assert alignment and sizes.
1130	*/
1131	AssertRelease(sizeof(pVM->pgm.s) <= sizeof(pVM->pgm.padding));
1132
1133	/*
1134	* Init the structure.
1135	*/
1136	pVM->pgm.s.offVM = RT_OFFSETOF(VM, pgm.s);
1137	pVM->pgm.s.enmShadowMode = PGMMODE_INVALID;
1138	pVM->pgm.s.enmGuestMode = PGMMODE_INVALID;
1139	pVM->pgm.s.enmHostMode = SUPPAGINGMODE_INVALID;
1140	pVM->pgm.s.GCPhysCR3 = NIL_RTGCPHYS;
1141	pVM->pgm.s.GCPhysGstCR3Monitored = NIL_RTGCPHYS;
1142	pVM->pgm.s.fA20Enabled = true;
1143	pVM->pgm.s.GCPhys4MBPSEMask = RT_BIT_64(32) - 1; /* default; checked later */
1144	pVM->pgm.s.pGstPaePdptR3 = NULL;
1145	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
1146	pVM->pgm.s.pGstPaePdptR0 = NIL_RTR0PTR;
1147	#endif
1148	pVM->pgm.s.pGstPaePdptRC = NIL_RTRCPTR;
1149	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.apGstPaePDsR3); i++)
1150	{
1151	pVM->pgm.s.apGstPaePDsR3[i] = NULL;
1152	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
1153	pVM->pgm.s.apGstPaePDsR0[i] = NIL_RTR0PTR;
1154	#endif
1155	pVM->pgm.s.apGstPaePDsRC[i] = NIL_RTRCPTR;
1156	pVM->pgm.s.aGCPhysGstPaePDs[i] = NIL_RTGCPHYS;
1157	pVM->pgm.s.aGCPhysGstPaePDsMonitored[i] = NIL_RTGCPHYS;
1158	}
1159
1160	#ifdef VBOX_STRICT
1161	VMR3AtStateRegister(pVM, pgmR3ResetNoMorePhysWritesFlag, NULL);
1162	#endif
1163
1164	/*
1165	* Get the configured RAM size - to estimate saved state size.
1166	*/
1167	uint64_t cbRam;
1168	int rc = CFGMR3QueryU64(CFGMR3GetRoot(pVM), "RamSize", &cbRam);
1169	if (rc == VERR_CFGM_VALUE_NOT_FOUND)
1170	cbRam = pVM->pgm.s.cbRamSize = 0;
1171	else if (RT_SUCCESS(rc))
1172	{
1173	if (cbRam < PAGE_SIZE)
1174	cbRam = 0;
1175	cbRam = RT_ALIGN_64(cbRam, PAGE_SIZE);
1176	pVM->pgm.s.cbRamSize = (RTUINT)cbRam;
1177	}
1178	else
1179	{
1180	AssertMsgFailed(("Configuration error: Failed to query integer \"RamSize\", rc=%Rrc.\n", rc));
1181	return rc;
1182	}
1183
1184	/*
1185	* Register saved state data unit.
1186	*/
1187	rc = SSMR3RegisterInternal(pVM, "pgm", 1, PGM_SAVED_STATE_VERSION, (size_t)cbRam + sizeof(PGM),
1188	NULL, pgmR3Save, NULL,
1189	NULL, pgmR3Load, NULL);
1190	if (RT_FAILURE(rc))
1191	return rc;
1192
1193	/*
1194	* Initialize the PGM critical section and flush the phys TLBs
1195	*/
1196	rc = PDMR3CritSectInit(pVM, &pVM->pgm.s.CritSect, "PGM");
1197	AssertRCReturn(rc, rc);
1198
1199	PGMR3PhysChunkInvalidateTLB(pVM);
1200	PGMPhysInvalidatePageR3MapTLB(pVM);
1201	PGMPhysInvalidatePageR0MapTLB(pVM);
1202	PGMPhysInvalidatePageGCMapTLB(pVM);
1203
1204	/*
1205	* Trees
1206	*/
1207	rc = MMHyperAlloc(pVM, sizeof(PGMTREES), 0, MM_TAG_PGM, (void **)&pVM->pgm.s.pTreesR3);
1208	if (RT_SUCCESS(rc))
1209	{
1210	pVM->pgm.s.pTreesR0 = MMHyperR3ToR0(pVM, pVM->pgm.s.pTreesR3);
1211	pVM->pgm.s.pTreesRC = MMHyperR3ToRC(pVM, pVM->pgm.s.pTreesR3);
1212
1213	/*
1214	* Alocate the zero page.
1215	*/
1216	rc = MMHyperAlloc(pVM, PAGE_SIZE, PAGE_SIZE, MM_TAG_PGM, &pVM->pgm.s.pvZeroPgR3);
1217	}
1218	if (RT_SUCCESS(rc))
1219	{
1220	pVM->pgm.s.pvZeroPgGC = MMHyperR3ToRC(pVM, pVM->pgm.s.pvZeroPgR3);
1221	pVM->pgm.s.pvZeroPgR0 = MMHyperR3ToR0(pVM, pVM->pgm.s.pvZeroPgR3);
1222	AssertRelease(pVM->pgm.s.pvZeroPgR0 != NIL_RTHCPHYS);
1223	pVM->pgm.s.HCPhysZeroPg = MMR3HyperHCVirt2HCPhys(pVM, pVM->pgm.s.pvZeroPgR3);
1224	AssertRelease(pVM->pgm.s.HCPhysZeroPg != NIL_RTHCPHYS);
1225
1226	/*
1227	* Init the paging.
1228	*/
1229	rc = pgmR3InitPaging(pVM);
1230	}
1231	if (RT_SUCCESS(rc))
1232	{
1233	/*
1234	* Init the page pool.
1235	*/
1236	rc = pgmR3PoolInit(pVM);
1237	}
1238	if (RT_SUCCESS(rc))
1239	{
1240	/*
1241	* Info & statistics
1242	*/
1243	DBGFR3InfoRegisterInternal(pVM, "mode",
1244	"Shows the current paging mode. "
1245	"Recognizes 'all', 'guest', 'shadow' and 'host' as arguments, defaulting to 'all' if nothing's given.",
1246	pgmR3InfoMode);
1247	DBGFR3InfoRegisterInternal(pVM, "pgmcr3",
1248	"Dumps all the entries in the top level paging table. No arguments.",
1249	pgmR3InfoCr3);
1250	DBGFR3InfoRegisterInternal(pVM, "phys",
1251	"Dumps all the physical address ranges. No arguments.",
1252	pgmR3PhysInfo);
1253	DBGFR3InfoRegisterInternal(pVM, "handlers",
1254	"Dumps physical, virtual and hyper virtual handlers. "
1255	"Pass 'phys', 'virt', 'hyper' as argument if only one kind is wanted."
1256	"Add 'nost' if the statistics are unwanted, use together with 'all' or explicit selection.",
1257	pgmR3InfoHandlers);
1258	DBGFR3InfoRegisterInternal(pVM, "mappings",
1259	"Dumps guest mappings.",
1260	pgmR3MapInfo);
1261
1262	STAM_REL_REG(pVM, &pVM->pgm.s.cGuestModeChanges, STAMTYPE_COUNTER, "/PGM/cGuestModeChanges", STAMUNIT_OCCURENCES, "Number of guest mode changes.");
1263	#ifdef VBOX_WITH_STATISTICS
1264	pgmR3InitStats(pVM);
1265	#endif
1266	#ifdef VBOX_WITH_DEBUGGER
1267	/*
1268	* Debugger commands.
1269	*/
1270	static bool fRegisteredCmds = false;
1271	if (!fRegisteredCmds)
1272	{
1273	int rc = DBGCRegisterCommands(&g_aCmds[0], RT_ELEMENTS(g_aCmds));
1274	if (RT_SUCCESS(rc))
1275	fRegisteredCmds = true;
1276	}
1277	#endif
1278	return VINF_SUCCESS;
1279	}
1280
1281	/* Almost no cleanup necessary, MM frees all memory. */
1282	PDMR3CritSectDelete(&pVM->pgm.s.CritSect);
1283
1284	return rc;
1285	}
1286
1287
1288	/**
1289	* Initializes the per-VCPU PGM.
1290	*
1291	* @returns VBox status code.
1292	* @param pVM The VM to operate on.
1293	*/
1294	VMMR3DECL(int) PGMR3InitCPU(PVM pVM)
1295	{
1296	LogFlow(("PGMR3InitCPU\n"));
1297	return VINF_SUCCESS;
1298	}
1299
1300
1301	/**
1302	* Init paging.
1303	*
1304	* Since we need to check what mode the host is operating in before we can choose
1305	* the right paging functions for the host we have to delay this until R0 has
1306	* been initialized.
1307	*
1308	* @returns VBox status code.
1309	* @param pVM VM handle.
1310	*/
1311	static int pgmR3InitPaging(PVM pVM)
1312	{
1313	/*
1314	* Force a recalculation of modes and switcher so everyone gets notified.
1315	*/
1316	pVM->pgm.s.enmShadowMode = PGMMODE_INVALID;
1317	pVM->pgm.s.enmGuestMode = PGMMODE_INVALID;
1318	pVM->pgm.s.enmHostMode = SUPPAGINGMODE_INVALID;
1319
1320	/*
1321	* Allocate static mapping space for whatever the cr3 register
1322	* points to and in the case of PAE mode to the 4 PDs.
1323	*/
1324	int rc = MMR3HyperReserve(pVM, PAGE_SIZE * 5, "CR3 mapping", &pVM->pgm.s.GCPtrCR3Mapping);
1325	if (RT_FAILURE(rc))
1326	{
1327	AssertMsgFailed(("Failed to reserve two pages for cr mapping in HMA, rc=%Rrc\n", rc));
1328	return rc;
1329	}
1330	MMR3HyperReserve(pVM, PAGE_SIZE, "fence", NULL);
1331
1332	/*
1333	* Allocate pages for the three possible intermediate contexts
1334	* (AMD64, PAE and plain 32-Bit). We maintain all three contexts
1335	* for the sake of simplicity. The AMD64 uses the PAE for the
1336	* lower levels, making the total number of pages 11 (3 + 7 + 1).
1337	*
1338	* We assume that two page tables will be enought for the core code
1339	* mappings (HC virtual and identity).
1340	*/
1341	pVM->pgm.s.pInterPD = (PX86PD)MMR3PageAllocLow(pVM);
1342	pVM->pgm.s.apInterPTs[0] = (PX86PT)MMR3PageAllocLow(pVM);
1343	pVM->pgm.s.apInterPTs[1] = (PX86PT)MMR3PageAllocLow(pVM);
1344	pVM->pgm.s.apInterPaePTs[0] = (PX86PTPAE)MMR3PageAlloc(pVM);
1345	pVM->pgm.s.apInterPaePTs[1] = (PX86PTPAE)MMR3PageAlloc(pVM);
1346	pVM->pgm.s.apInterPaePDs[0] = (PX86PDPAE)MMR3PageAlloc(pVM);
1347	pVM->pgm.s.apInterPaePDs[1] = (PX86PDPAE)MMR3PageAlloc(pVM);
1348	pVM->pgm.s.apInterPaePDs[2] = (PX86PDPAE)MMR3PageAlloc(pVM);
1349	pVM->pgm.s.apInterPaePDs[3] = (PX86PDPAE)MMR3PageAlloc(pVM);
1350	pVM->pgm.s.pInterPaePDPT = (PX86PDPT)MMR3PageAllocLow(pVM);
1351	pVM->pgm.s.pInterPaePDPT64 = (PX86PDPT)MMR3PageAllocLow(pVM);
1352	pVM->pgm.s.pInterPaePML4 = (PX86PML4)MMR3PageAllocLow(pVM);
1353	if ( !pVM->pgm.s.pInterPD
1354	\|\| !pVM->pgm.s.apInterPTs[0]
1355	\|\| !pVM->pgm.s.apInterPTs[1]
1356	\|\| !pVM->pgm.s.apInterPaePTs[0]
1357	\|\| !pVM->pgm.s.apInterPaePTs[1]
1358	\|\| !pVM->pgm.s.apInterPaePDs[0]
1359	\|\| !pVM->pgm.s.apInterPaePDs[1]
1360	\|\| !pVM->pgm.s.apInterPaePDs[2]
1361	\|\| !pVM->pgm.s.apInterPaePDs[3]
1362	\|\| !pVM->pgm.s.pInterPaePDPT
1363	\|\| !pVM->pgm.s.pInterPaePDPT64
1364	\|\| !pVM->pgm.s.pInterPaePML4)
1365	{
1366	AssertMsgFailed(("Failed to allocate pages for the intermediate context!\n"));
1367	return VERR_NO_PAGE_MEMORY;
1368	}
1369
1370	pVM->pgm.s.HCPhysInterPD = MMPage2Phys(pVM, pVM->pgm.s.pInterPD);
1371	AssertRelease(pVM->pgm.s.HCPhysInterPD != NIL_RTHCPHYS && !(pVM->pgm.s.HCPhysInterPD & PAGE_OFFSET_MASK));
1372	pVM->pgm.s.HCPhysInterPaePDPT = MMPage2Phys(pVM, pVM->pgm.s.pInterPaePDPT);
1373	AssertRelease(pVM->pgm.s.HCPhysInterPaePDPT != NIL_RTHCPHYS && !(pVM->pgm.s.HCPhysInterPaePDPT & PAGE_OFFSET_MASK));
1374	pVM->pgm.s.HCPhysInterPaePML4 = MMPage2Phys(pVM, pVM->pgm.s.pInterPaePML4);
1375	AssertRelease(pVM->pgm.s.HCPhysInterPaePML4 != NIL_RTHCPHYS && !(pVM->pgm.s.HCPhysInterPaePML4 & PAGE_OFFSET_MASK));
1376
1377	/*
1378	* Initialize the pages, setting up the PML4 and PDPT for repetitive 4GB action.
1379	*/
1380	ASMMemZeroPage(pVM->pgm.s.pInterPD);
1381	ASMMemZeroPage(pVM->pgm.s.apInterPTs[0]);
1382	ASMMemZeroPage(pVM->pgm.s.apInterPTs[1]);
1383
1384	ASMMemZeroPage(pVM->pgm.s.apInterPaePTs[0]);
1385	ASMMemZeroPage(pVM->pgm.s.apInterPaePTs[1]);
1386
1387	ASMMemZeroPage(pVM->pgm.s.pInterPaePDPT);
1388	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.apInterPaePDs); i++)
1389	{
1390	ASMMemZeroPage(pVM->pgm.s.apInterPaePDs[i]);
1391	pVM->pgm.s.pInterPaePDPT->a[i].u = X86_PDPE_P \| PGM_PLXFLAGS_PERMANENT
1392	\| MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[i]);
1393	}
1394
1395	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.pInterPaePDPT64->a); i++)
1396	{
1397	const unsigned iPD = i % RT_ELEMENTS(pVM->pgm.s.apInterPaePDs);
1398	pVM->pgm.s.pInterPaePDPT64->a[i].u = X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_A \| PGM_PLXFLAGS_PERMANENT
1399	\| MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[iPD]);
1400	}
1401
1402	RTHCPHYS HCPhysInterPaePDPT64 = MMPage2Phys(pVM, pVM->pgm.s.pInterPaePDPT64);
1403	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.pInterPaePML4->a); i++)
1404	pVM->pgm.s.pInterPaePML4->a[i].u = X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_A \| PGM_PLXFLAGS_PERMANENT
1405	\| HCPhysInterPaePDPT64;
1406
1407	/*
1408	* Allocate pages for the three possible guest contexts (AMD64, PAE and plain 32-Bit).
1409	* We allocate pages for all three posibilities in order to simplify mappings and
1410	* avoid resource failure during mode switches. So, we need to cover all levels of the
1411	* of the first 4GB down to PD level.
1412	* As with the intermediate context, AMD64 uses the PAE PDPT and PDs.
1413	*/
1414	pVM->pgm.s.pShw32BitPdR3 = (PX86PD)MMR3PageAllocLow(pVM);
1415	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
1416	pVM->pgm.s.pShw32BitPdR0 = (uintptr_t)pVM->pgm.s.pShw32BitPdR3;
1417	#endif
1418	pVM->pgm.s.apShwPaePDsR3[0] = (PX86PDPAE)MMR3PageAlloc(pVM);
1419	pVM->pgm.s.apShwPaePDsR3[1] = (PX86PDPAE)MMR3PageAlloc(pVM);
1420	AssertRelease((uintptr_t)pVM->pgm.s.apShwPaePDsR3[0] + PAGE_SIZE == (uintptr_t)pVM->pgm.s.apShwPaePDsR3[1]);
1421	pVM->pgm.s.apShwPaePDsR3[2] = (PX86PDPAE)MMR3PageAlloc(pVM);
1422	AssertRelease((uintptr_t)pVM->pgm.s.apShwPaePDsR3[1] + PAGE_SIZE == (uintptr_t)pVM->pgm.s.apShwPaePDsR3[2]);
1423	pVM->pgm.s.apShwPaePDsR3[3] = (PX86PDPAE)MMR3PageAlloc(pVM);
1424	AssertRelease((uintptr_t)pVM->pgm.s.apShwPaePDsR3[2] + PAGE_SIZE == (uintptr_t)pVM->pgm.s.apShwPaePDsR3[3]);
1425	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
1426	pVM->pgm.s.apShwPaePDsR0[0] = (uintptr_t)pVM->pgm.s.apShwPaePDsR3[0];
1427	pVM->pgm.s.apShwPaePDsR0[1] = (uintptr_t)pVM->pgm.s.apShwPaePDsR3[1];
1428	pVM->pgm.s.apShwPaePDsR0[2] = (uintptr_t)pVM->pgm.s.apShwPaePDsR3[2];
1429	pVM->pgm.s.apShwPaePDsR0[3] = (uintptr_t)pVM->pgm.s.apShwPaePDsR3[3];
1430	#endif
1431	pVM->pgm.s.pShwPaePdptR3 = (PX86PDPT)MMR3PageAllocLow(pVM);
1432	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
1433	pVM->pgm.s.pShwPaePdptR0 = (uintptr_t)pVM->pgm.s.pShwPaePdptR3;
1434	#endif
1435	pVM->pgm.s.pShwNestedRootR3 = MMR3PageAllocLow(pVM);
1436	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
1437	pVM->pgm.s.pShwNestedRootR0 = (uintptr_t)pVM->pgm.s.pShwNestedRootR3;
1438	#endif
1439
1440	if ( !pVM->pgm.s.pShw32BitPdR3
1441	\|\| !pVM->pgm.s.apShwPaePDsR3[0]
1442	\|\| !pVM->pgm.s.apShwPaePDsR3[1]
1443	\|\| !pVM->pgm.s.apShwPaePDsR3[2]
1444	\|\| !pVM->pgm.s.apShwPaePDsR3[3]
1445	\|\| !pVM->pgm.s.pShwPaePdptR3
1446	\|\| !pVM->pgm.s.pShwNestedRootR3)
1447	{
1448	AssertMsgFailed(("Failed to allocate pages for the intermediate context!\n"));
1449	return VERR_NO_PAGE_MEMORY;
1450	}
1451
1452	/* get physical addresses. */
1453	pVM->pgm.s.HCPhysShw32BitPD = MMPage2Phys(pVM, pVM->pgm.s.pShw32BitPdR3);
1454	Assert(MMPagePhys2Page(pVM, pVM->pgm.s.HCPhysShw32BitPD) == pVM->pgm.s.pShw32BitPdR3);
1455	pVM->pgm.s.aHCPhysPaePDs[0] = MMPage2Phys(pVM, pVM->pgm.s.apShwPaePDsR3[0]);
1456	pVM->pgm.s.aHCPhysPaePDs[1] = MMPage2Phys(pVM, pVM->pgm.s.apShwPaePDsR3[1]);
1457	pVM->pgm.s.aHCPhysPaePDs[2] = MMPage2Phys(pVM, pVM->pgm.s.apShwPaePDsR3[2]);
1458	pVM->pgm.s.aHCPhysPaePDs[3] = MMPage2Phys(pVM, pVM->pgm.s.apShwPaePDsR3[3]);
1459	pVM->pgm.s.HCPhysShwPaePdpt = MMPage2Phys(pVM, pVM->pgm.s.pShwPaePdptR3);
1460	pVM->pgm.s.HCPhysShwNestedRoot = MMPage2Phys(pVM, pVM->pgm.s.pShwNestedRootR3);
1461
1462	/*
1463	* Initialize the pages, setting up the PML4 and PDPT for action below 4GB.
1464	*/
1465	ASMMemZero32(pVM->pgm.s.pShw32BitPdR3, PAGE_SIZE);
1466	ASMMemZero32(pVM->pgm.s.pShwPaePdptR3, PAGE_SIZE);
1467	ASMMemZero32(pVM->pgm.s.pShwNestedRootR3, PAGE_SIZE);
1468	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.apShwPaePDsR3); i++)
1469	{
1470	ASMMemZero32(pVM->pgm.s.apShwPaePDsR3[i], PAGE_SIZE);
1471	pVM->pgm.s.pShwPaePdptR3->a[i].u = X86_PDPE_P \| PGM_PLXFLAGS_PERMANENT \| pVM->pgm.s.aHCPhysPaePDs[i];
1472	/* The flags will be corrected when entering and leaving long mode. */
1473	}
1474
1475	CPUMSetHyperCR3(pVM, (uint32_t)pVM->pgm.s.HCPhysShw32BitPD);
1476
1477	/*
1478	* Initialize paging workers and mode from current host mode
1479	* and the guest running in real mode.
1480	*/
1481	pVM->pgm.s.enmHostMode = SUPGetPagingMode();
1482	switch (pVM->pgm.s.enmHostMode)
1483	{
1484	case SUPPAGINGMODE_32_BIT:
1485	case SUPPAGINGMODE_32_BIT_GLOBAL:
1486	case SUPPAGINGMODE_PAE:
1487	case SUPPAGINGMODE_PAE_GLOBAL:
1488	case SUPPAGINGMODE_PAE_NX:
1489	case SUPPAGINGMODE_PAE_GLOBAL_NX:
1490	break;
1491
1492	case SUPPAGINGMODE_AMD64:
1493	case SUPPAGINGMODE_AMD64_GLOBAL:
1494	case SUPPAGINGMODE_AMD64_NX:
1495	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
1496	#ifndef VBOX_WITH_HYBIRD_32BIT_KERNEL
1497	if (ARCH_BITS != 64)
1498	{
1499	AssertMsgFailed(("Host mode %d (64-bit) is not supported by non-64bit builds\n", pVM->pgm.s.enmHostMode));
1500	LogRel(("Host mode %d (64-bit) is not supported by non-64bit builds\n", pVM->pgm.s.enmHostMode));
1501	return VERR_PGM_UNSUPPORTED_HOST_PAGING_MODE;
1502	}
1503	#endif
1504	break;
1505	default:
1506	AssertMsgFailed(("Host mode %d is not supported\n", pVM->pgm.s.enmHostMode));
1507	return VERR_PGM_UNSUPPORTED_HOST_PAGING_MODE;
1508	}
1509	rc = pgmR3ModeDataInit(pVM, false /* don't resolve GC and R0 syms yet */);
1510	if (RT_SUCCESS(rc))
1511	rc = PGMR3ChangeMode(pVM, PGMMODE_REAL);
1512	if (RT_SUCCESS(rc))
1513	{
1514	LogFlow(("pgmR3InitPaging: returns successfully\n"));
1515	#if HC_ARCH_BITS == 64
1516	LogRel(("Debug: HCPhysShw32BitPD=%RHp aHCPhysPaePDs={%RHp,%RHp,%RHp,%RHp} HCPhysShwPaePdpt=%RHp HCPhysShwPaePml4=%RHp\n",
1517	pVM->pgm.s.HCPhysShw32BitPD,
1518	pVM->pgm.s.aHCPhysPaePDs[0], pVM->pgm.s.aHCPhysPaePDs[1], pVM->pgm.s.aHCPhysPaePDs[2], pVM->pgm.s.aHCPhysPaePDs[3],
1519	pVM->pgm.s.HCPhysShwPaePdpt,
1520	pVM->pgm.s.HCPhysShwPaePml4));
1521	LogRel(("Debug: HCPhysInterPD=%RHp HCPhysInterPaePDPT=%RHp HCPhysInterPaePML4=%RHp\n",
1522	pVM->pgm.s.HCPhysInterPD, pVM->pgm.s.HCPhysInterPaePDPT, pVM->pgm.s.HCPhysInterPaePML4));
1523	LogRel(("Debug: apInterPTs={%RHp,%RHp} apInterPaePTs={%RHp,%RHp} apInterPaePDs={%RHp,%RHp,%RHp,%RHp} pInterPaePDPT64=%RHp\n",
1524	MMPage2Phys(pVM, pVM->pgm.s.apInterPTs[0]), MMPage2Phys(pVM, pVM->pgm.s.apInterPTs[1]),
1525	MMPage2Phys(pVM, pVM->pgm.s.apInterPaePTs[0]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePTs[1]),
1526	MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[0]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[1]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[2]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[3]),
1527	MMPage2Phys(pVM, pVM->pgm.s.pInterPaePDPT64)));
1528	#endif
1529
1530	return VINF_SUCCESS;
1531	}
1532
1533	LogFlow(("pgmR3InitPaging: returns %Rrc\n", rc));
1534	return rc;
1535	}
1536
1537
1538	#ifdef VBOX_WITH_STATISTICS
1539	/**
1540	* Init statistics
1541	*/
1542	static void pgmR3InitStats(PVM pVM)
1543	{
1544	PPGM pPGM = &pVM->pgm.s;
1545	unsigned i;
1546
1547	/*
1548	* Note! The layout of this function matches the member layout exactly!
1549	*/
1550
1551	/* Common - misc variables */
1552	STAM_REG(pVM, &pPGM->cAllPages, STAMTYPE_U32, "/PGM/Page/cAllPages", STAMUNIT_OCCURENCES, "The total number of pages.");
1553	STAM_REG(pVM, &pPGM->cPrivatePages, STAMTYPE_U32, "/PGM/Page/cPrivatePages", STAMUNIT_OCCURENCES, "The number of private pages.");
1554	STAM_REG(pVM, &pPGM->cSharedPages, STAMTYPE_U32, "/PGM/Page/cSharedPages", STAMUNIT_OCCURENCES, "The number of shared pages.");
1555	STAM_REG(pVM, &pPGM->cZeroPages, STAMTYPE_U32, "/PGM/Page/cZeroPages", STAMUNIT_OCCURENCES, "The number of zero backed pages.");
1556	STAM_REG(pVM, &pPGM->ChunkR3Map.c, STAMTYPE_U32, "/PGM/ChunkR3Map/c", STAMUNIT_OCCURENCES, "Number of mapped chunks.");
1557	STAM_REG(pVM, &pPGM->ChunkR3Map.cMax, STAMTYPE_U32, "/PGM/ChunkR3Map/cMax", STAMUNIT_OCCURENCES, "Maximum number of mapped chunks.");
1558
1559	/* Common - stats */
1560	#ifdef PGMPOOL_WITH_GCPHYS_TRACKING
1561	STAM_REG(pVM, &pPGM->StatTrackVirgin, STAMTYPE_COUNTER, "/PGM/Track/Virgin", STAMUNIT_OCCURENCES, "The number of first time shadowings");
1562	STAM_REG(pVM, &pPGM->StatTrackAliased, STAMTYPE_COUNTER, "/PGM/Track/Aliased", STAMUNIT_OCCURENCES, "The number of times switching to cRef2, i.e. the page is being shadowed by two PTs.");
1563	STAM_REG(pVM, &pPGM->StatTrackAliasedMany, STAMTYPE_COUNTER, "/PGM/Track/AliasedMany", STAMUNIT_OCCURENCES, "The number of times we're tracking using cRef2.");
1564	STAM_REG(pVM, &pPGM->StatTrackAliasedLots, STAMTYPE_COUNTER, "/PGM/Track/AliasedLots", STAMUNIT_OCCURENCES, "The number of times we're hitting pages which has overflowed cRef2");
1565	STAM_REG(pVM, &pPGM->StatTrackOverflows, STAMTYPE_COUNTER, "/PGM/Track/Overflows", STAMUNIT_OCCURENCES, "The number of times the extent list grows to long.");
1566	STAM_REG(pVM, &pPGM->StatTrackDeref, STAMTYPE_PROFILE, "/PGM/Track/Deref", STAMUNIT_OCCURENCES, "Profiling of SyncPageWorkerTrackDeref (expensive).");
1567	#endif
1568	for (i = 0; i < RT_ELEMENTS(pPGM->StatSyncPtPD); i++)
1569	STAMR3RegisterF(pVM, &pPGM->StatSyncPtPD[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
1570	"The number of SyncPT per PD n.", "/PGM/PDSyncPT/%04X", i);
1571	for (i = 0; i < RT_ELEMENTS(pPGM->StatSyncPagePD); i++)
1572	STAMR3RegisterF(pVM, &pPGM->StatSyncPagePD[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
1573	"The number of SyncPage per PD n.", "/PGM/PDSyncPage/%04X", i);
1574
1575	/* R3 only: */
1576	STAM_REG(pVM, &pPGM->StatR3DetectedConflicts, STAMTYPE_COUNTER, "/PGM/R3/DetectedConflicts", STAMUNIT_OCCURENCES, "The number of times PGMR3CheckMappingConflicts() detected a conflict.");
1577	STAM_REG(pVM, &pPGM->StatR3ResolveConflict, STAMTYPE_PROFILE, "/PGM/R3/ResolveConflict", STAMUNIT_TICKS_PER_CALL, "pgmR3SyncPTResolveConflict() profiling (includes the entire relocation).");
1578	STAM_REG(pVM, &pPGM->StatR3GuestPDWrite, STAMTYPE_COUNTER, "/PGM/R3/PDWrite", STAMUNIT_OCCURENCES, "The total number of times pgmHCGuestPDWriteHandler() was called.");
1579	STAM_REG(pVM, &pPGM->StatR3GuestPDWriteConflict, STAMTYPE_COUNTER, "/PGM/R3/PDWriteConflict", STAMUNIT_OCCURENCES, "The number of times pgmHCGuestPDWriteHandler() detected a conflict.");
1580	STAM_REG(pVM, &pPGM->StatR3DynRamTotal, STAMTYPE_COUNTER, "/PGM/DynAlloc/TotalAlloc", STAMUNIT_MEGABYTES, "Allocated MBs of guest ram.");
1581	STAM_REG(pVM, &pPGM->StatR3DynRamGrow, STAMTYPE_COUNTER, "/PGM/DynAlloc/Grow", STAMUNIT_OCCURENCES, "Nr of pgmr3PhysGrowRange calls.");
1582
1583	/* GC only: */
1584	STAM_REG(pVM, &pPGM->StatRCDynMapCacheHits, STAMTYPE_COUNTER, "/PGM/RC/DynMapCache/Hits" , STAMUNIT_OCCURENCES, "Number of dynamic page mapping cache hits.");
1585	STAM_REG(pVM, &pPGM->StatRCDynMapCacheMisses, STAMTYPE_COUNTER, "/PGM/RC/DynMapCache/Misses" , STAMUNIT_OCCURENCES, "Number of dynamic page mapping cache misses.");
1586	STAM_REG(pVM, &pPGM->StatRCInvlPgConflict, STAMTYPE_COUNTER, "/PGM/RC/InvlPgConflict", STAMUNIT_OCCURENCES, "Number of times PGMInvalidatePage() detected a mapping conflict.");
1587	STAM_REG(pVM, &pPGM->StatRCInvlPgSyncMonCR3, STAMTYPE_COUNTER, "/PGM/RC/InvlPgSyncMonitorCR3", STAMUNIT_OCCURENCES, "Number of times PGMInvalidatePage() ran into PGM_SYNC_MONITOR_CR3.");
1588
1589	/* RZ only: */
1590	STAM_REG(pVM, &pPGM->StatRZTrap0e, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMTrap0eHandler() body.");
1591	STAM_REG(pVM, &pPGM->StatRZTrap0eTimeCheckPageFault, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time/CheckPageFault", STAMUNIT_TICKS_PER_CALL, "Profiling of checking for dirty/access emulation faults.");
1592	STAM_REG(pVM, &pPGM->StatRZTrap0eTimeSyncPT, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time/SyncPT", STAMUNIT_TICKS_PER_CALL, "Profiling of lazy page table syncing.");
1593	STAM_REG(pVM, &pPGM->StatRZTrap0eTimeMapping, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time/Mapping", STAMUNIT_TICKS_PER_CALL, "Profiling of checking virtual mappings.");
1594	STAM_REG(pVM, &pPGM->StatRZTrap0eTimeOutOfSync, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time/OutOfSync", STAMUNIT_TICKS_PER_CALL, "Profiling of out of sync page handling.");
1595	STAM_REG(pVM, &pPGM->StatRZTrap0eTimeHandlers, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time/Handlers", STAMUNIT_TICKS_PER_CALL, "Profiling of checking handlers.");
1596	STAM_REG(pVM, &pPGM->StatRZTrap0eTime2CSAM, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time2/CSAM", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is CSAM.");
1597	STAM_REG(pVM, &pPGM->StatRZTrap0eTime2DirtyAndAccessed, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time2/DirtyAndAccessedBits", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is dirty and/or accessed bit emulation.");
1598	STAM_REG(pVM, &pPGM->StatRZTrap0eTime2GuestTrap, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time2/GuestTrap", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is a guest trap.");
1599	STAM_REG(pVM, &pPGM->StatRZTrap0eTime2HndPhys, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time2/HandlerPhysical", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is a physical handler.");
1600	STAM_REG(pVM, &pPGM->StatRZTrap0eTime2HndVirt, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time2/HandlerVirtual", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is a virtual handler.");
1601	STAM_REG(pVM, &pPGM->StatRZTrap0eTime2HndUnhandled, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time2/HandlerUnhandled", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is access outside the monitored areas of a monitored page.");
1602	STAM_REG(pVM, &pPGM->StatRZTrap0eTime2Misc, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time2/Misc", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is not known.");
1603	STAM_REG(pVM, &pPGM->StatRZTrap0eTime2OutOfSync, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time2/OutOfSync", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is an out-of-sync page.");
1604	STAM_REG(pVM, &pPGM->StatRZTrap0eTime2OutOfSyncHndPhys, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time2/OutOfSyncHndPhys", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is an out-of-sync physical handler page.");
1605	STAM_REG(pVM, &pPGM->StatRZTrap0eTime2OutOfSyncHndVirt, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time2/OutOfSyncHndVirt", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is an out-of-sync virtual handler page.");
1606	STAM_REG(pVM, &pPGM->StatRZTrap0eTime2OutOfSyncHndObs, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time2/OutOfSyncObsHnd", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is an obsolete handler page.");
1607	STAM_REG(pVM, &pPGM->StatRZTrap0eTime2SyncPT, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time2/SyncPT", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is lazy syncing of a PT.");
1608	STAM_REG(pVM, &pPGM->StatRZTrap0eConflicts, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Conflicts", STAMUNIT_OCCURENCES, "The number of times #PF was caused by an undetected conflict.");
1609	STAM_REG(pVM, &pPGM->StatRZTrap0eHandlersMapping, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Handlers/Mapping", STAMUNIT_OCCURENCES, "Number of traps due to access handlers in mappings.");
1610	STAM_REG(pVM, &pPGM->StatRZTrap0eHandlersOutOfSync, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Handlers/OutOfSync", STAMUNIT_OCCURENCES, "Number of traps due to out-of-sync handled pages.");
1611	STAM_REG(pVM, &pPGM->StatRZTrap0eHandlersPhysical, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Handlers/Physical", STAMUNIT_OCCURENCES, "Number of traps due to physical access handlers.");
1612	STAM_REG(pVM, &pPGM->StatRZTrap0eHandlersVirtual, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Handlers/Virtual", STAMUNIT_OCCURENCES, "Number of traps due to virtual access handlers.");
1613	STAM_REG(pVM, &pPGM->StatRZTrap0eHandlersVirtualByPhys, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Handlers/VirtualByPhys", STAMUNIT_OCCURENCES, "Number of traps due to virtual access handlers by physical address.");
1614	STAM_REG(pVM, &pPGM->StatRZTrap0eHandlersVirtualUnmarked,STAMTYPE_COUNTER,"/PGM/RZ/Trap0e/Handlers/VirtualUnmarked",STAMUNIT_OCCURENCES, "Number of traps due to virtual access handlers by virtual address (without proper physical flags).");
1615	STAM_REG(pVM, &pPGM->StatRZTrap0eHandlersUnhandled, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Handlers/Unhandled", STAMUNIT_OCCURENCES, "Number of traps due to access outside range of monitored page(s).");
1616	STAM_REG(pVM, &pPGM->StatRZTrap0eHandlersInvalid, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Handlers/Invalid", STAMUNIT_OCCURENCES, "Number of traps due to access to invalid physical memory.");
1617	STAM_REG(pVM, &pPGM->StatRZTrap0eUSNotPresentRead, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Err/User/NPRead", STAMUNIT_OCCURENCES, "Number of user mode not present read page faults.");
1618	STAM_REG(pVM, &pPGM->StatRZTrap0eUSNotPresentWrite, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Err/User/NPWrite", STAMUNIT_OCCURENCES, "Number of user mode not present write page faults.");
1619	STAM_REG(pVM, &pPGM->StatRZTrap0eUSWrite, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Err/User/Write", STAMUNIT_OCCURENCES, "Number of user mode write page faults.");
1620	STAM_REG(pVM, &pPGM->StatRZTrap0eUSReserved, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Err/User/Reserved", STAMUNIT_OCCURENCES, "Number of user mode reserved bit page faults.");
1621	STAM_REG(pVM, &pPGM->StatRZTrap0eUSNXE, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Err/User/NXE", STAMUNIT_OCCURENCES, "Number of user mode NXE page faults.");
1622	STAM_REG(pVM, &pPGM->StatRZTrap0eUSRead, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Err/User/Read", STAMUNIT_OCCURENCES, "Number of user mode read page faults.");
1623	STAM_REG(pVM, &pPGM->StatRZTrap0eSVNotPresentRead, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Err/Supervisor/NPRead", STAMUNIT_OCCURENCES, "Number of supervisor mode not present read page faults.");
1624	STAM_REG(pVM, &pPGM->StatRZTrap0eSVNotPresentWrite, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Err/Supervisor/NPWrite", STAMUNIT_OCCURENCES, "Number of supervisor mode not present write page faults.");
1625	STAM_REG(pVM, &pPGM->StatRZTrap0eSVWrite, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Err/Supervisor/Write", STAMUNIT_OCCURENCES, "Number of supervisor mode write page faults.");
1626	STAM_REG(pVM, &pPGM->StatRZTrap0eSVReserved, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Err/Supervisor/Reserved", STAMUNIT_OCCURENCES, "Number of supervisor mode reserved bit page faults.");
1627	STAM_REG(pVM, &pPGM->StatRZTrap0eSNXE, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Err/Supervisor/NXE", STAMUNIT_OCCURENCES, "Number of supervisor mode NXE page faults.");
1628	STAM_REG(pVM, &pPGM->StatRZTrap0eGuestPF, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/GuestPF", STAMUNIT_OCCURENCES, "Number of real guest page faults.");
1629	STAM_REG(pVM, &pPGM->StatRZTrap0eGuestPFUnh, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/GuestPF/Unhandled", STAMUNIT_OCCURENCES, "Number of real guest page faults from the 'unhandled' case.");
1630	STAM_REG(pVM, &pPGM->StatRZTrap0eGuestPFMapping, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/GuestPF/InMapping", STAMUNIT_OCCURENCES, "Number of real guest page faults in a mapping.");
1631	STAM_REG(pVM, &pPGM->StatRZTrap0eWPEmulInRZ, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/WP/InRZ", STAMUNIT_OCCURENCES, "Number of guest page faults due to X86_CR0_WP emulation.");
1632	STAM_REG(pVM, &pPGM->StatRZTrap0eWPEmulToR3, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/WP/ToR3", STAMUNIT_OCCURENCES, "Number of guest page faults due to X86_CR0_WP emulation (forward to R3 for emulation).");
1633	for (i = 0; i < RT_ELEMENTS(pPGM->StatRZTrap0ePD); i++)
1634	STAMR3RegisterF(pVM, &pPGM->StatRZTrap0ePD[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
1635	"The number of traps in page directory n.", "/PGM/RZ/Trap0e/PD/%04X", i);
1636	STAM_REG(pVM, &pPGM->StatRZGuestCR3WriteHandled, STAMTYPE_COUNTER, "/PGM/RZ/CR3WriteHandled", STAMUNIT_OCCURENCES, "The number of times the Guest CR3 change was successfully handled.");
1637	STAM_REG(pVM, &pPGM->StatRZGuestCR3WriteUnhandled, STAMTYPE_COUNTER, "/PGM/RZ/CR3WriteUnhandled", STAMUNIT_OCCURENCES, "The number of times the Guest CR3 change was passed back to the recompiler.");
1638	STAM_REG(pVM, &pPGM->StatRZGuestCR3WriteConflict, STAMTYPE_COUNTER, "/PGM/RZ/CR3WriteConflict", STAMUNIT_OCCURENCES, "The number of times the Guest CR3 monitoring detected a conflict.");
1639	STAM_REG(pVM, &pPGM->StatRZGuestROMWriteHandled, STAMTYPE_COUNTER, "/PGM/RZ/ROMWriteHandled", STAMUNIT_OCCURENCES, "The number of times the Guest ROM change was successfully handled.");
1640	STAM_REG(pVM, &pPGM->StatRZGuestROMWriteUnhandled, STAMTYPE_COUNTER, "/PGM/RZ/ROMWriteUnhandled", STAMUNIT_OCCURENCES, "The number of times the Guest ROM change was passed back to the recompiler.");
1641
1642	/* HC only: */
1643
1644	/* RZ & R3: */
1645	STAM_REG(pVM, &pPGM->StatRZSyncCR3, STAMTYPE_PROFILE, "/PGM/RZ/SyncCR3", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMSyncCR3() body.");
1646	STAM_REG(pVM, &pPGM->StatRZSyncCR3Handlers, STAMTYPE_PROFILE, "/PGM/RZ/SyncCR3/Handlers", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMSyncCR3() update handler section.");
1647	STAM_REG(pVM, &pPGM->StatRZSyncCR3HandlerVirtualUpdate, STAMTYPE_PROFILE, "/PGM/RZ/SyncCR3/Handlers/VirtualUpdate", STAMUNIT_TICKS_PER_CALL, "Profiling of the virtual handler updates.");
1648	STAM_REG(pVM, &pPGM->StatRZSyncCR3HandlerVirtualReset, STAMTYPE_PROFILE, "/PGM/RZ/SyncCR3/Handlers/VirtualReset", STAMUNIT_TICKS_PER_CALL, "Profiling of the virtual handler resets.");
1649	STAM_REG(pVM, &pPGM->StatRZSyncCR3Global, STAMTYPE_COUNTER, "/PGM/RZ/SyncCR3/Global", STAMUNIT_OCCURENCES, "The number of global CR3 syncs.");
1650	STAM_REG(pVM, &pPGM->StatRZSyncCR3NotGlobal, STAMTYPE_COUNTER, "/PGM/RZ/SyncCR3/NotGlobal", STAMUNIT_OCCURENCES, "The number of non-global CR3 syncs.");
1651	STAM_REG(pVM, &pPGM->StatRZSyncCR3DstCacheHit, STAMTYPE_COUNTER, "/PGM/RZ/SyncCR3/DstChacheHit", STAMUNIT_OCCURENCES, "The number of times we got some kind of a cache hit.");
1652	STAM_REG(pVM, &pPGM->StatRZSyncCR3DstFreed, STAMTYPE_COUNTER, "/PGM/RZ/SyncCR3/DstFreed", STAMUNIT_OCCURENCES, "The number of times we've had to free a shadow entry.");
1653	STAM_REG(pVM, &pPGM->StatRZSyncCR3DstFreedSrcNP, STAMTYPE_COUNTER, "/PGM/RZ/SyncCR3/DstFreedSrcNP", STAMUNIT_OCCURENCES, "The number of times we've had to free a shadow entry for which the source entry was not present.");
1654	STAM_REG(pVM, &pPGM->StatRZSyncCR3DstNotPresent, STAMTYPE_COUNTER, "/PGM/RZ/SyncCR3/DstNotPresent", STAMUNIT_OCCURENCES, "The number of times we've encountered a not present shadow entry for a present guest entry.");
1655	STAM_REG(pVM, &pPGM->StatRZSyncCR3DstSkippedGlobalPD, STAMTYPE_COUNTER, "/PGM/RZ/SyncCR3/DstSkippedGlobalPD", STAMUNIT_OCCURENCES, "The number of times a global page directory wasn't flushed.");
1656	STAM_REG(pVM, &pPGM->StatRZSyncCR3DstSkippedGlobalPT, STAMTYPE_COUNTER, "/PGM/RZ/SyncCR3/DstSkippedGlobalPT", STAMUNIT_OCCURENCES, "The number of times a page table with only global entries wasn't flushed.");
1657	STAM_REG(pVM, &pPGM->StatRZSyncPT, STAMTYPE_PROFILE, "/PGM/RZ/SyncPT", STAMUNIT_TICKS_PER_CALL, "Profiling of the pfnSyncPT() body.");
1658	STAM_REG(pVM, &pPGM->StatRZSyncPTFailed, STAMTYPE_COUNTER, "/PGM/RZ/SyncPT/Failed", STAMUNIT_OCCURENCES, "The number of times pfnSyncPT() failed.");
1659	STAM_REG(pVM, &pPGM->StatRZSyncPT4K, STAMTYPE_COUNTER, "/PGM/RZ/SyncPT/4K", STAMUNIT_OCCURENCES, "Nr of 4K PT syncs");
1660	STAM_REG(pVM, &pPGM->StatRZSyncPT4M, STAMTYPE_COUNTER, "/PGM/RZ/SyncPT/4M", STAMUNIT_OCCURENCES, "Nr of 4M PT syncs");
1661	STAM_REG(pVM, &pPGM->StatRZSyncPagePDNAs, STAMTYPE_COUNTER, "/PGM/RZ/SyncPagePDNAs", STAMUNIT_OCCURENCES, "The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit.");
1662	STAM_REG(pVM, &pPGM->StatRZSyncPagePDOutOfSync, STAMTYPE_COUNTER, "/PGM/RZ/SyncPagePDOutOfSync", STAMUNIT_OCCURENCES, "The number of time we've encountered an out-of-sync PD in SyncPage.");
1663	STAM_REG(pVM, &pPGM->StatRZAccessedPage, STAMTYPE_COUNTER, "/PGM/RZ/AccessedPage", STAMUNIT_OCCURENCES, "The number of pages marked not present for accessed bit emulation.");
1664	STAM_REG(pVM, &pPGM->StatRZDirtyBitTracking, STAMTYPE_PROFILE, "/PGM/RZ/DirtyPage", STAMUNIT_TICKS_PER_CALL, "Profiling the dirty bit tracking in CheckPageFault().");
1665	STAM_REG(pVM, &pPGM->StatRZDirtyPage, STAMTYPE_COUNTER, "/PGM/RZ/DirtyPage/Mark", STAMUNIT_OCCURENCES, "The number of pages marked read-only for dirty bit tracking.");
1666	STAM_REG(pVM, &pPGM->StatRZDirtyPageBig, STAMTYPE_COUNTER, "/PGM/RZ/DirtyPage/MarkBig", STAMUNIT_OCCURENCES, "The number of 4MB pages marked read-only for dirty bit tracking.");
1667	STAM_REG(pVM, &pPGM->StatRZDirtyPageSkipped, STAMTYPE_COUNTER, "/PGM/RZ/DirtyPage/Skipped", STAMUNIT_OCCURENCES, "The number of pages already dirty or readonly.");
1668	STAM_REG(pVM, &pPGM->StatRZDirtyPageTrap, STAMTYPE_COUNTER, "/PGM/RZ/DirtyPage/Trap", STAMUNIT_OCCURENCES, "The number of traps generated for dirty bit tracking.");
1669	STAM_REG(pVM, &pPGM->StatRZDirtiedPage, STAMTYPE_COUNTER, "/PGM/RZ/DirtyPage/SetDirty", STAMUNIT_OCCURENCES, "The number of pages marked dirty because of write accesses.");
1670	STAM_REG(pVM, &pPGM->StatRZDirtyTrackRealPF, STAMTYPE_COUNTER, "/PGM/RZ/DirtyPage/RealPF", STAMUNIT_OCCURENCES, "The number of real pages faults during dirty bit tracking.");
1671	STAM_REG(pVM, &pPGM->StatRZPageAlreadyDirty, STAMTYPE_COUNTER, "/PGM/RZ/DirtyPage/AlreadySet", STAMUNIT_OCCURENCES, "The number of pages already marked dirty because of write accesses.");
1672	STAM_REG(pVM, &pPGM->StatRZInvalidatePage, STAMTYPE_PROFILE, "/PGM/RZ/InvalidatePage", STAMUNIT_TICKS_PER_CALL, "PGMInvalidatePage() profiling.");
1673	STAM_REG(pVM, &pPGM->StatRZInvalidatePage4KBPages, STAMTYPE_COUNTER, "/PGM/RZ/InvalidatePage/4KBPages", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was called for a 4KB page.");
1674	STAM_REG(pVM, &pPGM->StatRZInvalidatePage4MBPages, STAMTYPE_COUNTER, "/PGM/RZ/InvalidatePage/4MBPages", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was called for a 4MB page.");
1675	STAM_REG(pVM, &pPGM->StatRZInvalidatePage4MBPagesSkip, STAMTYPE_COUNTER, "/PGM/RZ/InvalidatePage/4MBPagesSkip",STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() skipped a 4MB page.");
1676	STAM_REG(pVM, &pPGM->StatRZInvalidatePagePDMappings, STAMTYPE_COUNTER, "/PGM/RZ/InvalidatePage/PDMappings", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict).");
1677	STAM_REG(pVM, &pPGM->StatRZInvalidatePagePDNAs, STAMTYPE_COUNTER, "/PGM/RZ/InvalidatePage/PDNAs", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was called for a not accessed page directory.");
1678	STAM_REG(pVM, &pPGM->StatRZInvalidatePagePDNPs, STAMTYPE_COUNTER, "/PGM/RZ/InvalidatePage/PDNPs", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was called for a not present page directory.");
1679	STAM_REG(pVM, &pPGM->StatRZInvalidatePagePDOutOfSync, STAMTYPE_COUNTER, "/PGM/RZ/InvalidatePage/PDOutOfSync", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was called for an out of sync page directory.");
1680	STAM_REG(pVM, &pPGM->StatRZInvalidatePageSkipped, STAMTYPE_COUNTER, "/PGM/RZ/InvalidatePage/Skipped", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3.");
1681	STAM_REG(pVM, &pPGM->StatRZVirtHandlerSearchByPhys, STAMTYPE_PROFILE, "/PGM/RZ/VirtHandlerSearchByPhys", STAMUNIT_TICKS_PER_CALL, "Profiling of pgmHandlerVirtualFindByPhysAddr.");
1682	STAM_REG(pVM, &pPGM->StatRZPhysHandlerReset, STAMTYPE_COUNTER, "/PGM/RZ/PhysHandlerReset", STAMUNIT_OCCURENCES, "The number of times PGMHandlerPhysicalReset is called.");
1683	STAM_REG(pVM, &pPGM->StatRZPageOutOfSyncSupervisor, STAMTYPE_COUNTER, "/PGM/RZ/OutOfSync/SuperVisor", STAMUNIT_OCCURENCES, "Number of traps due to pages out of sync and times VerifyAccessSyncPage calls SyncPage.");
1684	STAM_REG(pVM, &pPGM->StatRZPageOutOfSyncUser, STAMTYPE_COUNTER, "/PGM/RZ/OutOfSync/User", STAMUNIT_OCCURENCES, "Number of traps due to pages out of sync and times VerifyAccessSyncPage calls SyncPage.");
1685	STAM_REG(pVM, &pPGM->StatRZPrefetch, STAMTYPE_PROFILE, "/PGM/RZ/Prefetch", STAMUNIT_TICKS_PER_CALL, "PGMPrefetchPage profiling.");
1686	STAM_REG(pVM, &pPGM->StatRZChunkR3MapTlbHits, STAMTYPE_COUNTER, "/PGM/ChunkR3Map/TlbHitsRZ", STAMUNIT_OCCURENCES, "TLB hits.");
1687	STAM_REG(pVM, &pPGM->StatRZChunkR3MapTlbMisses, STAMTYPE_COUNTER, "/PGM/ChunkR3Map/TlbMissesRZ", STAMUNIT_OCCURENCES, "TLB misses.");
1688	STAM_REG(pVM, &pPGM->StatRZPageMapTlbHits, STAMTYPE_COUNTER, "/PGM/RZ/Page/MapTlbHits", STAMUNIT_OCCURENCES, "TLB hits.");
1689	STAM_REG(pVM, &pPGM->StatRZPageMapTlbMisses, STAMTYPE_COUNTER, "/PGM/RZ/Page/MapTlbMisses", STAMUNIT_OCCURENCES, "TLB misses.");
1690	STAM_REG(pVM, &pPGM->StatRZPageReplaceShared, STAMTYPE_COUNTER, "/PGM/RZ/Page/ReplacedShared", STAMUNIT_OCCURENCES, "Times a shared page was replaced.");
1691	STAM_REG(pVM, &pPGM->StatRZPageReplaceZero, STAMTYPE_COUNTER, "/PGM/RZ/Page/ReplacedZero", STAMUNIT_OCCURENCES, "Times the zero page was replaced.");
1692	/// @todo STAM_REG(pVM, &pPGM->StatRZPageHandyAllocs, STAMTYPE_COUNTER, "/PGM/RZ/Page/HandyAllocs", STAMUNIT_OCCURENCES, "Number of times we've allocated more handy pages.");
1693	STAM_REG(pVM, &pPGM->StatRZFlushTLB, STAMTYPE_PROFILE, "/PGM/RZ/FlushTLB", STAMUNIT_OCCURENCES, "Profiling of the PGMFlushTLB() body.");
1694	STAM_REG(pVM, &pPGM->StatRZFlushTLBNewCR3, STAMTYPE_COUNTER, "/PGM/RZ/FlushTLB/NewCR3", STAMUNIT_OCCURENCES, "The number of times PGMFlushTLB was called with a new CR3, non-global. (switch)");
1695	STAM_REG(pVM, &pPGM->StatRZFlushTLBNewCR3Global, STAMTYPE_COUNTER, "/PGM/RZ/FlushTLB/NewCR3Global", STAMUNIT_OCCURENCES, "The number of times PGMFlushTLB was called with a new CR3, global. (switch)");
1696	STAM_REG(pVM, &pPGM->StatRZFlushTLBSameCR3, STAMTYPE_COUNTER, "/PGM/RZ/FlushTLB/SameCR3", STAMUNIT_OCCURENCES, "The number of times PGMFlushTLB was called with the same CR3, non-global. (flush)");
1697	STAM_REG(pVM, &pPGM->StatRZFlushTLBSameCR3Global, STAMTYPE_COUNTER, "/PGM/RZ/FlushTLB/SameCR3Global", STAMUNIT_OCCURENCES, "The number of times PGMFlushTLB was called with the same CR3, global. (flush)");
1698	STAM_REG(pVM, &pPGM->StatRZGstModifyPage, STAMTYPE_PROFILE, "/PGM/RZ/GstModifyPage", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMGstModifyPage() body.");
1699
1700	STAM_REG(pVM, &pPGM->StatR3SyncCR3, STAMTYPE_PROFILE, "/PGM/R3/SyncCR3", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMSyncCR3() body.");
1701	STAM_REG(pVM, &pPGM->StatR3SyncCR3Handlers, STAMTYPE_PROFILE, "/PGM/R3/SyncCR3/Handlers", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMSyncCR3() update handler section.");
1702	STAM_REG(pVM, &pPGM->StatR3SyncCR3HandlerVirtualUpdate, STAMTYPE_PROFILE, "/PGM/R3/SyncCR3/Handlers/VirtualUpdate", STAMUNIT_TICKS_PER_CALL, "Profiling of the virtual handler updates.");
1703	STAM_REG(pVM, &pPGM->StatR3SyncCR3HandlerVirtualReset, STAMTYPE_PROFILE, "/PGM/R3/SyncCR3/Handlers/VirtualReset", STAMUNIT_TICKS_PER_CALL, "Profiling of the virtual handler resets.");
1704	STAM_REG(pVM, &pPGM->StatR3SyncCR3Global, STAMTYPE_COUNTER, "/PGM/R3/SyncCR3/Global", STAMUNIT_OCCURENCES, "The number of global CR3 syncs.");
1705	STAM_REG(pVM, &pPGM->StatR3SyncCR3NotGlobal, STAMTYPE_COUNTER, "/PGM/R3/SyncCR3/NotGlobal", STAMUNIT_OCCURENCES, "The number of non-global CR3 syncs.");
1706	STAM_REG(pVM, &pPGM->StatR3SyncCR3DstCacheHit, STAMTYPE_COUNTER, "/PGM/R3/SyncCR3/DstChacheHit", STAMUNIT_OCCURENCES, "The number of times we got some kind of a cache hit.");
1707	STAM_REG(pVM, &pPGM->StatR3SyncCR3DstFreed, STAMTYPE_COUNTER, "/PGM/R3/SyncCR3/DstFreed", STAMUNIT_OCCURENCES, "The number of times we've had to free a shadow entry.");
1708	STAM_REG(pVM, &pPGM->StatR3SyncCR3DstFreedSrcNP, STAMTYPE_COUNTER, "/PGM/R3/SyncCR3/DstFreedSrcNP", STAMUNIT_OCCURENCES, "The number of times we've had to free a shadow entry for which the source entry was not present.");
1709	STAM_REG(pVM, &pPGM->StatR3SyncCR3DstNotPresent, STAMTYPE_COUNTER, "/PGM/R3/SyncCR3/DstNotPresent", STAMUNIT_OCCURENCES, "The number of times we've encountered a not present shadow entry for a present guest entry.");
1710	STAM_REG(pVM, &pPGM->StatR3SyncCR3DstSkippedGlobalPD, STAMTYPE_COUNTER, "/PGM/R3/SyncCR3/DstSkippedGlobalPD", STAMUNIT_OCCURENCES, "The number of times a global page directory wasn't flushed.");
1711	STAM_REG(pVM, &pPGM->StatR3SyncCR3DstSkippedGlobalPT, STAMTYPE_COUNTER, "/PGM/R3/SyncCR3/DstSkippedGlobalPT", STAMUNIT_OCCURENCES, "The number of times a page table with only global entries wasn't flushed.");
1712	STAM_REG(pVM, &pPGM->StatR3SyncPT, STAMTYPE_PROFILE, "/PGM/R3/SyncPT", STAMUNIT_TICKS_PER_CALL, "Profiling of the pfnSyncPT() body.");
1713	STAM_REG(pVM, &pPGM->StatR3SyncPTFailed, STAMTYPE_COUNTER, "/PGM/R3/SyncPT/Failed", STAMUNIT_OCCURENCES, "The number of times pfnSyncPT() failed.");
1714	STAM_REG(pVM, &pPGM->StatR3SyncPT4K, STAMTYPE_COUNTER, "/PGM/R3/SyncPT/4K", STAMUNIT_OCCURENCES, "Nr of 4K PT syncs");
1715	STAM_REG(pVM, &pPGM->StatR3SyncPT4M, STAMTYPE_COUNTER, "/PGM/R3/SyncPT/4M", STAMUNIT_OCCURENCES, "Nr of 4M PT syncs");
1716	STAM_REG(pVM, &pPGM->StatR3SyncPagePDNAs, STAMTYPE_COUNTER, "/PGM/R3/SyncPagePDNAs", STAMUNIT_OCCURENCES, "The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit.");
1717	STAM_REG(pVM, &pPGM->StatR3SyncPagePDOutOfSync, STAMTYPE_COUNTER, "/PGM/R3/SyncPagePDOutOfSync", STAMUNIT_OCCURENCES, "The number of time we've encountered an out-of-sync PD in SyncPage.");
1718	STAM_REG(pVM, &pPGM->StatR3AccessedPage, STAMTYPE_COUNTER, "/PGM/R3/AccessedPage", STAMUNIT_OCCURENCES, "The number of pages marked not present for accessed bit emulation.");
1719	STAM_REG(pVM, &pPGM->StatR3DirtyBitTracking, STAMTYPE_PROFILE, "/PGM/R3/DirtyPage", STAMUNIT_TICKS_PER_CALL, "Profiling the dirty bit tracking in CheckPageFault().");
1720	STAM_REG(pVM, &pPGM->StatR3DirtyPage, STAMTYPE_COUNTER, "/PGM/R3/DirtyPage/Mark", STAMUNIT_OCCURENCES, "The number of pages marked read-only for dirty bit tracking.");
1721	STAM_REG(pVM, &pPGM->StatR3DirtyPageBig, STAMTYPE_COUNTER, "/PGM/R3/DirtyPage/MarkBig", STAMUNIT_OCCURENCES, "The number of 4MB pages marked read-only for dirty bit tracking.");
1722	STAM_REG(pVM, &pPGM->StatR3DirtyPageSkipped, STAMTYPE_COUNTER, "/PGM/R3/DirtyPage/Skipped", STAMUNIT_OCCURENCES, "The number of pages already dirty or readonly.");
1723	STAM_REG(pVM, &pPGM->StatR3DirtyPageTrap, STAMTYPE_COUNTER, "/PGM/R3/DirtyPage/Trap", STAMUNIT_OCCURENCES, "The number of traps generated for dirty bit tracking.");
1724	STAM_REG(pVM, &pPGM->StatR3DirtiedPage, STAMTYPE_COUNTER, "/PGM/R3/DirtyPage/SetDirty", STAMUNIT_OCCURENCES, "The number of pages marked dirty because of write accesses.");
1725	STAM_REG(pVM, &pPGM->StatR3DirtyTrackRealPF, STAMTYPE_COUNTER, "/PGM/R3/DirtyPage/RealPF", STAMUNIT_OCCURENCES, "The number of real pages faults during dirty bit tracking.");
1726	STAM_REG(pVM, &pPGM->StatR3PageAlreadyDirty, STAMTYPE_COUNTER, "/PGM/R3/DirtyPage/AlreadySet", STAMUNIT_OCCURENCES, "The number of pages already marked dirty because of write accesses.");
1727	STAM_REG(pVM, &pPGM->StatR3InvalidatePage, STAMTYPE_PROFILE, "/PGM/R3/InvalidatePage", STAMUNIT_TICKS_PER_CALL, "PGMInvalidatePage() profiling.");
1728	STAM_REG(pVM, &pPGM->StatR3InvalidatePage4KBPages, STAMTYPE_COUNTER, "/PGM/R3/InvalidatePage/4KBPages", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was called for a 4KB page.");
1729	STAM_REG(pVM, &pPGM->StatR3InvalidatePage4MBPages, STAMTYPE_COUNTER, "/PGM/R3/InvalidatePage/4MBPages", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was called for a 4MB page.");
1730	STAM_REG(pVM, &pPGM->StatR3InvalidatePage4MBPagesSkip, STAMTYPE_COUNTER, "/PGM/R3/InvalidatePage/4MBPagesSkip",STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() skipped a 4MB page.");
1731	STAM_REG(pVM, &pPGM->StatR3InvalidatePagePDMappings, STAMTYPE_COUNTER, "/PGM/R3/InvalidatePage/PDMappings", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict).");
1732	STAM_REG(pVM, &pPGM->StatR3InvalidatePagePDNAs, STAMTYPE_COUNTER, "/PGM/R3/InvalidatePage/PDNAs", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was called for a not accessed page directory.");
1733	STAM_REG(pVM, &pPGM->StatR3InvalidatePagePDNPs, STAMTYPE_COUNTER, "/PGM/R3/InvalidatePage/PDNPs", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was called for a not present page directory.");
1734	STAM_REG(pVM, &pPGM->StatR3InvalidatePagePDOutOfSync, STAMTYPE_COUNTER, "/PGM/R3/InvalidatePage/PDOutOfSync", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was called for an out of sync page directory.");
1735	STAM_REG(pVM, &pPGM->StatR3InvalidatePageSkipped, STAMTYPE_COUNTER, "/PGM/R3/InvalidatePage/Skipped", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3.");
1736	STAM_REG(pVM, &pPGM->StatR3VirtHandlerSearchByPhys, STAMTYPE_PROFILE, "/PGM/R3/VirtHandlerSearchByPhys", STAMUNIT_TICKS_PER_CALL, "Profiling of pgmHandlerVirtualFindByPhysAddr.");
1737	STAM_REG(pVM, &pPGM->StatR3PhysHandlerReset, STAMTYPE_COUNTER, "/PGM/R3/PhysHandlerReset", STAMUNIT_OCCURENCES, "The number of times PGMHandlerPhysicalReset is called.");
1738	STAM_REG(pVM, &pPGM->StatR3PageOutOfSyncSupervisor, STAMTYPE_COUNTER, "/PGM/R3/OutOfSync/SuperVisor", STAMUNIT_OCCURENCES, "Number of traps due to pages out of sync and times VerifyAccessSyncPage calls SyncPage.");
1739	STAM_REG(pVM, &pPGM->StatR3PageOutOfSyncUser, STAMTYPE_COUNTER, "/PGM/R3/OutOfSync/User", STAMUNIT_OCCURENCES, "Number of traps due to pages out of sync and times VerifyAccessSyncPage calls SyncPage.");
1740	STAM_REG(pVM, &pPGM->StatR3Prefetch, STAMTYPE_PROFILE, "/PGM/R3/Prefetch", STAMUNIT_TICKS_PER_CALL, "PGMPrefetchPage profiling.");
1741	STAM_REG(pVM, &pPGM->StatR3ChunkR3MapTlbHits, STAMTYPE_COUNTER, "/PGM/ChunkR3Map/TlbHitsR3", STAMUNIT_OCCURENCES, "TLB hits.");
1742	STAM_REG(pVM, &pPGM->StatR3ChunkR3MapTlbMisses, STAMTYPE_COUNTER, "/PGM/ChunkR3Map/TlbMissesR3", STAMUNIT_OCCURENCES, "TLB misses.");
1743	STAM_REG(pVM, &pPGM->StatR3PageMapTlbHits, STAMTYPE_COUNTER, "/PGM/R3/Page/MapTlbHits", STAMUNIT_OCCURENCES, "TLB hits.");
1744	STAM_REG(pVM, &pPGM->StatR3PageMapTlbMisses, STAMTYPE_COUNTER, "/PGM/R3/Page/MapTlbMisses", STAMUNIT_OCCURENCES, "TLB misses.");
1745	STAM_REG(pVM, &pPGM->StatR3PageReplaceShared, STAMTYPE_COUNTER, "/PGM/R3/Page/ReplacedShared", STAMUNIT_OCCURENCES, "Times a shared page was replaced.");
1746	STAM_REG(pVM, &pPGM->StatR3PageReplaceZero, STAMTYPE_COUNTER, "/PGM/R3/Page/ReplacedZero", STAMUNIT_OCCURENCES, "Times the zero page was replaced.");
1747	/// @todo STAM_REG(pVM, &pPGM->StatR3PageHandyAllocs, STAMTYPE_COUNTER, "/PGM/R3/Page/HandyAllocs", STAMUNIT_OCCURENCES, "Number of times we've allocated more handy pages.");
1748	STAM_REG(pVM, &pPGM->StatR3FlushTLB, STAMTYPE_PROFILE, "/PGM/R3/FlushTLB", STAMUNIT_OCCURENCES, "Profiling of the PGMFlushTLB() body.");
1749	STAM_REG(pVM, &pPGM->StatR3FlushTLBNewCR3, STAMTYPE_COUNTER, "/PGM/R3/FlushTLB/NewCR3", STAMUNIT_OCCURENCES, "The number of times PGMFlushTLB was called with a new CR3, non-global. (switch)");
1750	STAM_REG(pVM, &pPGM->StatR3FlushTLBNewCR3Global, STAMTYPE_COUNTER, "/PGM/R3/FlushTLB/NewCR3Global", STAMUNIT_OCCURENCES, "The number of times PGMFlushTLB was called with a new CR3, global. (switch)");
1751	STAM_REG(pVM, &pPGM->StatR3FlushTLBSameCR3, STAMTYPE_COUNTER, "/PGM/R3/FlushTLB/SameCR3", STAMUNIT_OCCURENCES, "The number of times PGMFlushTLB was called with the same CR3, non-global. (flush)");
1752	STAM_REG(pVM, &pPGM->StatR3FlushTLBSameCR3Global, STAMTYPE_COUNTER, "/PGM/R3/FlushTLB/SameCR3Global", STAMUNIT_OCCURENCES, "The number of times PGMFlushTLB was called with the same CR3, global. (flush)");
1753	STAM_REG(pVM, &pPGM->StatR3GstModifyPage, STAMTYPE_PROFILE, "/PGM/R3/GstModifyPage", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMGstModifyPage() body.");
1754
1755	}
1756	#endif /* VBOX_WITH_STATISTICS */
1757
1758
1759	/**
1760	* Init the PGM bits that rely on VMMR0 and MM to be fully initialized.
1761	*
1762	* The dynamic mapping area will also be allocated and initialized at this
1763	* time. We could allocate it during PGMR3Init of course, but the mapping
1764	* wouldn't be allocated at that time preventing us from setting up the
1765	* page table entries with the dummy page.
1766	*
1767	* @returns VBox status code.
1768	* @param pVM VM handle.
1769	*/
1770	VMMR3DECL(int) PGMR3InitDynMap(PVM pVM)
1771	{
1772	RTGCPTR GCPtr;
1773	/*
1774	* Reserve space for mapping the paging pages into guest context.
1775	*/
1776	int rc = MMR3HyperReserve(pVM, PAGE_SIZE * (2 + RT_ELEMENTS(pVM->pgm.s.apShwPaePDsR3) + 1 + 2 + 2), "Paging", &GCPtr);
1777	AssertRCReturn(rc, rc);
1778	pVM->pgm.s.pShw32BitPdRC = GCPtr;
1779	MMR3HyperReserve(pVM, PAGE_SIZE, "fence", NULL);
1780
1781	/*
1782	* Reserve space for the dynamic mappings.
1783	*/
1784	rc = MMR3HyperReserve(pVM, MM_HYPER_DYNAMIC_SIZE, "Dynamic mapping", &GCPtr);
1785	if (RT_SUCCESS(rc))
1786	pVM->pgm.s.pbDynPageMapBaseGC = GCPtr;
1787
1788	if ( RT_SUCCESS(rc)
1789	&& (pVM->pgm.s.pbDynPageMapBaseGC >> X86_PD_PAE_SHIFT) != ((pVM->pgm.s.pbDynPageMapBaseGC + MM_HYPER_DYNAMIC_SIZE - 1) >> X86_PD_PAE_SHIFT))
1790	{
1791	rc = MMR3HyperReserve(pVM, MM_HYPER_DYNAMIC_SIZE, "Dynamic mapping not crossing", &GCPtr);
1792	if (RT_SUCCESS(rc))
1793	pVM->pgm.s.pbDynPageMapBaseGC = GCPtr;
1794	}
1795	if (RT_SUCCESS(rc))
1796	{
1797	AssertRelease((pVM->pgm.s.pbDynPageMapBaseGC >> X86_PD_PAE_SHIFT) == ((pVM->pgm.s.pbDynPageMapBaseGC + MM_HYPER_DYNAMIC_SIZE - 1) >> X86_PD_PAE_SHIFT));
1798	MMR3HyperReserve(pVM, PAGE_SIZE, "fence", NULL);
1799	}
1800	return rc;
1801	}
1802
1803
1804	/**
1805	* Ring-3 init finalizing.
1806	*
1807	* @returns VBox status code.
1808	* @param pVM The VM handle.
1809	*/
1810	VMMR3DECL(int) PGMR3InitFinalize(PVM pVM)
1811	{
1812	/*
1813	* Map the paging pages into the guest context.
1814	*/
1815	RTGCPTR GCPtr = pVM->pgm.s.pShw32BitPdRC;
1816	AssertReleaseReturn(GCPtr, VERR_INTERNAL_ERROR);
1817
1818	int rc = PGMMap(pVM, GCPtr, pVM->pgm.s.HCPhysShw32BitPD, PAGE_SIZE, 0);
1819	AssertRCReturn(rc, rc);
1820	pVM->pgm.s.pShw32BitPdRC = GCPtr;
1821	GCPtr += PAGE_SIZE;
1822	GCPtr += PAGE_SIZE; /* reserved page */
1823
1824	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.apShwPaePDsR3); i++)
1825	{
1826	rc = PGMMap(pVM, GCPtr, pVM->pgm.s.aHCPhysPaePDs[i], PAGE_SIZE, 0);
1827	AssertRCReturn(rc, rc);
1828	pVM->pgm.s.apShwPaePDsRC[i] = GCPtr;
1829	GCPtr += PAGE_SIZE;
1830	}
1831	/* A bit of paranoia is justified. */
1832	AssertRelease(pVM->pgm.s.apShwPaePDsRC[0] + PAGE_SIZE == pVM->pgm.s.apShwPaePDsRC[1]);
1833	AssertRelease(pVM->pgm.s.apShwPaePDsRC[1] + PAGE_SIZE == pVM->pgm.s.apShwPaePDsRC[2]);
1834	AssertRelease(pVM->pgm.s.apShwPaePDsRC[2] + PAGE_SIZE == pVM->pgm.s.apShwPaePDsRC[3]);
1835	GCPtr += PAGE_SIZE; /* reserved page */
1836
1837	rc = PGMMap(pVM, GCPtr, pVM->pgm.s.HCPhysShwPaePdpt, PAGE_SIZE, 0);
1838	AssertRCReturn(rc, rc);
1839	pVM->pgm.s.pShwPaePdptRC = GCPtr;
1840	GCPtr += PAGE_SIZE;
1841	GCPtr += PAGE_SIZE; /* reserved page */
1842
1843
1844	/*
1845	* Reserve space for the dynamic mappings.
1846	* Initialize the dynamic mapping pages with dummy pages to simply the cache.
1847	*/
1848	/* get the pointer to the page table entries. */
1849	PPGMMAPPING pMapping = pgmGetMapping(pVM, pVM->pgm.s.pbDynPageMapBaseGC);
1850	AssertRelease(pMapping);
1851	const uintptr_t off = pVM->pgm.s.pbDynPageMapBaseGC - pMapping->GCPtr;
1852	const unsigned iPT = off >> X86_PD_SHIFT;
1853	const unsigned iPG = (off >> X86_PT_SHIFT) & X86_PT_MASK;
1854	pVM->pgm.s.paDynPageMap32BitPTEsGC = pMapping->aPTs[iPT].pPTRC + iPG * sizeof(pMapping->aPTs[0].pPTR3->a[0]);
1855	pVM->pgm.s.paDynPageMapPaePTEsGC = pMapping->aPTs[iPT].paPaePTsRC + iPG * sizeof(pMapping->aPTs[0].paPaePTsR3->a[0]);
1856
1857	/* init cache */
1858	RTHCPHYS HCPhysDummy = MMR3PageDummyHCPhys(pVM);
1859	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.aHCPhysDynPageMapCache); i++)
1860	pVM->pgm.s.aHCPhysDynPageMapCache[i] = HCPhysDummy;
1861
1862	for (unsigned i = 0; i < MM_HYPER_DYNAMIC_SIZE; i += PAGE_SIZE)
1863	{
1864	rc = PGMMap(pVM, pVM->pgm.s.pbDynPageMapBaseGC + i, HCPhysDummy, PAGE_SIZE, 0);
1865	AssertRCReturn(rc, rc);
1866	}
1867
1868	/*
1869	* Note that AMD uses all the 8 reserved bits for the address (so 40 bits in total);
1870	* Intel only goes up to 36 bits, so we stick to 36 as well.
1871	*/
1872	/** @todo How to test for the 40 bits support? Long mode seems to be the test criterium. */
1873	uint32_t u32Dummy, u32Features;
1874	CPUMGetGuestCpuId(pVM, 1, &u32Dummy, &u32Dummy, &u32Dummy, &u32Features);
1875
1876	if (u32Features & X86_CPUID_FEATURE_EDX_PSE36)
1877	pVM->pgm.s.GCPhys4MBPSEMask = RT_BIT_64(36) - 1;
1878	else
1879	pVM->pgm.s.GCPhys4MBPSEMask = RT_BIT_64(32) - 1;
1880
1881	LogRel(("PGMR3InitFinalize: 4 MB PSE mask %RGp\n", pVM->pgm.s.GCPhys4MBPSEMask));
1882
1883	return rc;
1884	}
1885
1886
1887	/**
1888	* Applies relocations to data and code managed by this component.
1889	*
1890	* This function will be called at init and whenever the VMM need to relocate it
1891	* self inside the GC.
1892	*
1893	* @param pVM The VM.
1894	* @param offDelta Relocation delta relative to old location.
1895	*/
1896	VMMR3DECL(void) PGMR3Relocate(PVM pVM, RTGCINTPTR offDelta)
1897	{
1898	LogFlow(("PGMR3Relocate\n"));
1899
1900	/*
1901	* Paging stuff.
1902	*/
1903	pVM->pgm.s.GCPtrCR3Mapping += offDelta;
1904	/** @todo move this into shadow and guest specific relocation functions. */
1905	AssertMsg(pVM->pgm.s.pShw32BitPdR3, ("Init order, no relocation before paging is initialized!\n"));
1906	pVM->pgm.s.pShw32BitPdRC += offDelta;
1907	pVM->pgm.s.pGst32BitPdRC += offDelta;
1908	AssertCompile(RT_ELEMENTS(pVM->pgm.s.apShwPaePDsRC) == RT_ELEMENTS(pVM->pgm.s.apGstPaePDsRC));
1909	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.apShwPaePDsRC); i++)
1910	{
1911	pVM->pgm.s.apShwPaePDsRC[i] += offDelta;
1912	pVM->pgm.s.apGstPaePDsRC[i] += offDelta;
1913	}
1914	pVM->pgm.s.pGstPaePdptRC += offDelta;
1915	pVM->pgm.s.pShwPaePdptRC += offDelta;
1916
1917	pgmR3ModeDataInit(pVM, true /* resolve GC/R0 symbols */);
1918	pgmR3ModeDataSwitch(pVM, pVM->pgm.s.enmShadowMode, pVM->pgm.s.enmGuestMode);
1919
1920	PGM_SHW_PFN(Relocate, pVM)(pVM, offDelta);
1921	PGM_GST_PFN(Relocate, pVM)(pVM, offDelta);
1922	PGM_BTH_PFN(Relocate, pVM)(pVM, offDelta);
1923
1924	/*
1925	* Trees.
1926	*/
1927	pVM->pgm.s.pTreesRC = MMHyperR3ToRC(pVM, pVM->pgm.s.pTreesR3);
1928
1929	/*
1930	* Ram ranges.
1931	*/
1932	if (pVM->pgm.s.pRamRangesR3)
1933	{
1934	pVM->pgm.s.pRamRangesRC = MMHyperR3ToRC(pVM, pVM->pgm.s.pRamRangesR3);
1935	for (PPGMRAMRANGE pCur = pVM->pgm.s.pRamRangesR3; pCur->pNextR3; pCur = pCur->pNextR3)
1936	pCur->pNextRC = MMHyperR3ToRC(pVM, pCur->pNextR3);
1937	}
1938
1939	/*
1940	* Update the two page directories with all page table mappings.
1941	* (One or more of them have changed, that's why we're here.)
1942	*/
1943	pVM->pgm.s.pMappingsRC = MMHyperR3ToRC(pVM, pVM->pgm.s.pMappingsR3);
1944	for (PPGMMAPPING pCur = pVM->pgm.s.pMappingsR3; pCur->pNextR3; pCur = pCur->pNextR3)
1945	pCur->pNextRC = MMHyperR3ToRC(pVM, pCur->pNextR3);
1946
1947	/* Relocate GC addresses of Page Tables. */
1948	for (PPGMMAPPING pCur = pVM->pgm.s.pMappingsR3; pCur; pCur = pCur->pNextR3)
1949	{
1950	for (RTHCUINT i = 0; i < pCur->cPTs; i++)
1951	{
1952	pCur->aPTs[i].pPTRC = MMHyperR3ToRC(pVM, pCur->aPTs[i].pPTR3);
1953	pCur->aPTs[i].paPaePTsRC = MMHyperR3ToRC(pVM, pCur->aPTs[i].paPaePTsR3);
1954	}
1955	}
1956
1957	/*
1958	* Dynamic page mapping area.
1959	*/
1960	pVM->pgm.s.paDynPageMap32BitPTEsGC += offDelta;
1961	pVM->pgm.s.paDynPageMapPaePTEsGC += offDelta;
1962	pVM->pgm.s.pbDynPageMapBaseGC += offDelta;
1963
1964	/*
1965	* The Zero page.
1966	*/
1967	pVM->pgm.s.pvZeroPgR0 = MMHyperR3ToR0(pVM, pVM->pgm.s.pvZeroPgR3);
1968	AssertRelease(pVM->pgm.s.pvZeroPgR0);
1969
1970	/*
1971	* Physical and virtual handlers.
1972	*/
1973	RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysHandlers, true, pgmR3RelocatePhysHandler, &offDelta);
1974	RTAvlroGCPtrDoWithAll(&pVM->pgm.s.pTreesR3->VirtHandlers, true, pgmR3RelocateVirtHandler, &offDelta);
1975	RTAvlroGCPtrDoWithAll(&pVM->pgm.s.pTreesR3->HyperVirtHandlers, true, pgmR3RelocateHyperVirtHandler, &offDelta);
1976
1977	/*
1978	* The page pool.
1979	*/
1980	pgmR3PoolRelocate(pVM);
1981	}
1982
1983
1984	/**
1985	* Callback function for relocating a physical access handler.
1986	*
1987	* @returns 0 (continue enum)
1988	* @param pNode Pointer to a PGMPHYSHANDLER node.
1989	* @param pvUser Pointer to the offDelta. This is a pointer to the delta since we're
1990	* not certain the delta will fit in a void pointer for all possible configs.
1991	*/
1992	static DECLCALLBACK(int) pgmR3RelocatePhysHandler(PAVLROGCPHYSNODECORE pNode, void *pvUser)
1993	{
1994	PPGMPHYSHANDLER pHandler = (PPGMPHYSHANDLER)pNode;
1995	RTGCINTPTR offDelta = *(PRTGCINTPTR)pvUser;
1996	if (pHandler->pfnHandlerRC)
1997	pHandler->pfnHandlerRC += offDelta;
1998	if (pHandler->pvUserRC >= 0x10000)
1999	pHandler->pvUserRC += offDelta;
2000	return 0;
2001	}
2002
2003
2004	/**
2005	* Callback function for relocating a virtual access handler.
2006	*
2007	* @returns 0 (continue enum)
2008	* @param pNode Pointer to a PGMVIRTHANDLER node.
2009	* @param pvUser Pointer to the offDelta. This is a pointer to the delta since we're
2010	* not certain the delta will fit in a void pointer for all possible configs.
2011	*/
2012	static DECLCALLBACK(int) pgmR3RelocateVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser)
2013	{
2014	PPGMVIRTHANDLER pHandler = (PPGMVIRTHANDLER)pNode;
2015	RTGCINTPTR offDelta = *(PRTGCINTPTR)pvUser;
2016	Assert( pHandler->enmType == PGMVIRTHANDLERTYPE_ALL
2017	\|\| pHandler->enmType == PGMVIRTHANDLERTYPE_WRITE);
2018	Assert(pHandler->pfnHandlerRC);
2019	pHandler->pfnHandlerRC += offDelta;
2020	return 0;
2021	}
2022
2023
2024	/**
2025	* Callback function for relocating a virtual access handler for the hypervisor mapping.
2026	*
2027	* @returns 0 (continue enum)
2028	* @param pNode Pointer to a PGMVIRTHANDLER node.
2029	* @param pvUser Pointer to the offDelta. This is a pointer to the delta since we're
2030	* not certain the delta will fit in a void pointer for all possible configs.
2031	*/
2032	static DECLCALLBACK(int) pgmR3RelocateHyperVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser)
2033	{
2034	PPGMVIRTHANDLER pHandler = (PPGMVIRTHANDLER)pNode;
2035	RTGCINTPTR offDelta = *(PRTGCINTPTR)pvUser;
2036	Assert(pHandler->enmType == PGMVIRTHANDLERTYPE_HYPERVISOR);
2037	Assert(pHandler->pfnHandlerRC);
2038	pHandler->pfnHandlerRC += offDelta;
2039	return 0;
2040	}
2041
2042
2043	/**
2044	* The VM is being reset.
2045	*
2046	* For the PGM component this means that any PD write monitors
2047	* needs to be removed.
2048	*
2049	* @param pVM VM handle.
2050	*/
2051	VMMR3DECL(void) PGMR3Reset(PVM pVM)
2052	{
2053	LogFlow(("PGMR3Reset:\n"));
2054	VM_ASSERT_EMT(pVM);
2055
2056	pgmLock(pVM);
2057
2058	/*
2059	* Unfix any fixed mappings and disable CR3 monitoring.
2060	*/
2061	pVM->pgm.s.fMappingsFixed = false;
2062	pVM->pgm.s.GCPtrMappingFixed = 0;
2063	pVM->pgm.s.cbMappingFixed = 0;
2064
2065	/* Exit the guest paging mode before the pgm pool gets reset.
2066	* Important to clean up the amd64 case.
2067	*/
2068	int rc = PGM_GST_PFN(Exit, pVM)(pVM);
2069	AssertRC(rc);
2070	#ifdef DEBUG
2071	DBGFR3InfoLog(pVM, "mappings", NULL);
2072	DBGFR3InfoLog(pVM, "handlers", "all nostat");
2073	#endif
2074
2075	/*
2076	* Reset the shadow page pool.
2077	*/
2078	pgmR3PoolReset(pVM);
2079
2080	/*
2081	* Re-init other members.
2082	*/
2083	pVM->pgm.s.fA20Enabled = true;
2084
2085	/*
2086	* Clear the FFs PGM owns.
2087	*/
2088	VM_FF_CLEAR(pVM, VM_FF_PGM_SYNC_CR3);
2089	VM_FF_CLEAR(pVM, VM_FF_PGM_SYNC_CR3_NON_GLOBAL);
2090
2091	/*
2092	* Reset (zero) RAM pages.
2093	*/
2094	rc = pgmR3PhysRamReset(pVM);
2095	if (RT_SUCCESS(rc))
2096	{
2097	#ifdef VBOX_WITH_NEW_PHYS_CODE
2098	/*
2099	* Reset (zero) shadow ROM pages.
2100	*/
2101	rc = pgmR3PhysRomReset(pVM);
2102	#endif
2103	if (RT_SUCCESS(rc))
2104	{
2105	/*
2106	* Switch mode back to real mode.
2107	*/
2108	rc = PGMR3ChangeMode(pVM, PGMMODE_REAL);
2109	STAM_REL_COUNTER_RESET(&pVM->pgm.s.cGuestModeChanges);
2110	}
2111	}
2112
2113	pgmUnlock(pVM);
2114	//return rc;
2115	AssertReleaseRC(rc);
2116	}
2117
2118
2119	#ifdef VBOX_STRICT
2120	/**
2121	* VM state change callback for clearing fNoMorePhysWrites after
2122	* a snapshot has been created.
2123	*/
2124	static DECLCALLBACK(void) pgmR3ResetNoMorePhysWritesFlag(PVM pVM, VMSTATE enmState, VMSTATE enmOldState, void *pvUser)
2125	{
2126	if (enmState == VMSTATE_RUNNING)
2127	pVM->pgm.s.fNoMorePhysWrites = false;
2128	}
2129	#endif
2130
2131
2132	/**
2133	* Terminates the PGM.
2134	*
2135	* @returns VBox status code.
2136	* @param pVM Pointer to VM structure.
2137	*/
2138	VMMR3DECL(int) PGMR3Term(PVM pVM)
2139	{
2140	return PDMR3CritSectDelete(&pVM->pgm.s.CritSect);
2141	}
2142
2143
2144	/**
2145	* Terminates the per-VCPU PGM.
2146	*
2147	* Termination means cleaning up and freeing all resources,
2148	* the VM it self is at this point powered off or suspended.
2149	*
2150	* @returns VBox status code.
2151	* @param pVM The VM to operate on.
2152	*/
2153	VMMR3DECL(int) PGMR3TermCPU(PVM pVM)
2154	{
2155	return 0;
2156	}
2157
2158
2159	/**
2160	* Execute state save operation.
2161	*
2162	* @returns VBox status code.
2163	* @param pVM VM Handle.
2164	* @param pSSM SSM operation handle.
2165	*/
2166	static DECLCALLBACK(int) pgmR3Save(PVM pVM, PSSMHANDLE pSSM)
2167	{
2168	PPGM pPGM = &pVM->pgm.s;
2169
2170	/* No more writes to physical memory after this point! */
2171	pVM->pgm.s.fNoMorePhysWrites = true;
2172
2173	/*
2174	* Save basic data (required / unaffected by relocation).
2175	*/
2176	#if 1
2177	SSMR3PutBool(pSSM, pPGM->fMappingsFixed);
2178	#else
2179	SSMR3PutUInt(pSSM, pPGM->fMappingsFixed);
2180	#endif
2181	SSMR3PutGCPtr(pSSM, pPGM->GCPtrMappingFixed);
2182	SSMR3PutU32(pSSM, pPGM->cbMappingFixed);
2183	SSMR3PutUInt(pSSM, pPGM->cbRamSize);
2184	SSMR3PutGCPhys(pSSM, pPGM->GCPhysA20Mask);
2185	SSMR3PutUInt(pSSM, pPGM->fA20Enabled);
2186	SSMR3PutUInt(pSSM, pPGM->fSyncFlags);
2187	SSMR3PutUInt(pSSM, pPGM->enmGuestMode);
2188	SSMR3PutU32(pSSM, ~0); /* Separator. */
2189
2190	/*
2191	* The guest mappings.
2192	*/
2193	uint32_t i = 0;
2194	for (PPGMMAPPING pMapping = pPGM->pMappingsR3; pMapping; pMapping = pMapping->pNextR3, i++)
2195	{
2196	SSMR3PutU32(pSSM, i);
2197	SSMR3PutStrZ(pSSM, pMapping->pszDesc); /* This is the best unique id we have... */
2198	SSMR3PutGCPtr(pSSM, pMapping->GCPtr);
2199	SSMR3PutGCUIntPtr(pSSM, pMapping->cPTs);
2200	/* flags are done by the mapping owners! */
2201	}
2202	SSMR3PutU32(pSSM, ~0); /* terminator. */
2203
2204	/*
2205	* Ram range flags and bits.
2206	*/
2207	i = 0;
2208	for (PPGMRAMRANGE pRam = pPGM->pRamRangesR3; pRam; pRam = pRam->pNextR3, i++)
2209	{
2210	/** @todo MMIO ranges may move (PCI reconfig), we currently assume they don't. */
2211
2212	SSMR3PutU32(pSSM, i);
2213	SSMR3PutGCPhys(pSSM, pRam->GCPhys);
2214	SSMR3PutGCPhys(pSSM, pRam->GCPhysLast);
2215	SSMR3PutGCPhys(pSSM, pRam->cb);
2216	SSMR3PutU8(pSSM, !!pRam->pvR3); /* boolean indicating memory or not. */
2217
2218	/* Flags. */
2219	const unsigned cPages = pRam->cb >> PAGE_SHIFT;
2220	for (unsigned iPage = 0; iPage < cPages; iPage++)
2221	SSMR3PutU16(pSSM, (uint16_t)(pRam->aPages[iPage].HCPhys & ~X86_PTE_PAE_PG_MASK)); /** @todo PAGE FLAGS */
2222
2223	/* any memory associated with the range. */
2224	if (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)
2225	{
2226	for (unsigned iChunk = 0; iChunk < (pRam->cb >> PGM_DYNAMIC_CHUNK_SHIFT); iChunk++)
2227	{
2228	if (pRam->paChunkR3Ptrs[iChunk])
2229	{
2230	SSMR3PutU8(pSSM, 1); /* chunk present */
2231	SSMR3PutMem(pSSM, (void *)pRam->paChunkR3Ptrs[iChunk], PGM_DYNAMIC_CHUNK_SIZE);
2232	}
2233	else
2234	SSMR3PutU8(pSSM, 0); /* no chunk present */
2235	}
2236	}
2237	else if (pRam->pvR3)
2238	{
2239	int rc = SSMR3PutMem(pSSM, pRam->pvR3, pRam->cb);
2240	if (RT_FAILURE(rc))
2241	{
2242	Log(("pgmR3Save: SSMR3PutMem(, %p, %#x) -> %Rrc\n", pRam->pvR3, pRam->cb, rc));
2243	return rc;
2244	}
2245	}
2246	}
2247	return SSMR3PutU32(pSSM, ~0); /* terminator. */
2248	}
2249
2250
2251	/**
2252	* Execute state load operation.
2253	*
2254	* @returns VBox status code.
2255	* @param pVM VM Handle.
2256	* @param pSSM SSM operation handle.
2257	* @param u32Version Data layout version.
2258	*/
2259	static DECLCALLBACK(int) pgmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version)
2260	{
2261	/*
2262	* Validate version.
2263	*/
2264	if (u32Version != PGM_SAVED_STATE_VERSION)
2265	{
2266	AssertMsgFailed(("pgmR3Load: Invalid version u32Version=%d (current %d)!\n", u32Version, PGM_SAVED_STATE_VERSION));
2267	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
2268	}
2269
2270	/*
2271	* Call the reset function to make sure all the memory is cleared.
2272	*/
2273	PGMR3Reset(pVM);
2274
2275	/*
2276	* Load basic data (required / unaffected by relocation).
2277	*/
2278	PPGM pPGM = &pVM->pgm.s;
2279	#if 1
2280	SSMR3GetBool(pSSM, &pPGM->fMappingsFixed);
2281	#else
2282	uint32_t u;
2283	SSMR3GetU32(pSSM, &u);
2284	pPGM->fMappingsFixed = u;
2285	#endif
2286	SSMR3GetGCPtr(pSSM, &pPGM->GCPtrMappingFixed);
2287	SSMR3GetU32(pSSM, &pPGM->cbMappingFixed);
2288
2289	RTUINT cbRamSize;
2290	int rc = SSMR3GetU32(pSSM, &cbRamSize);
2291	if (RT_FAILURE(rc))
2292	return rc;
2293	if (cbRamSize != pPGM->cbRamSize)
2294	return VERR_SSM_LOAD_MEMORY_SIZE_MISMATCH;
2295	SSMR3GetGCPhys(pSSM, &pPGM->GCPhysA20Mask);
2296	SSMR3GetUInt(pSSM, &pPGM->fA20Enabled);
2297	SSMR3GetUInt(pSSM, &pPGM->fSyncFlags);
2298	RTUINT uGuestMode;
2299	SSMR3GetUInt(pSSM, &uGuestMode);
2300	pPGM->enmGuestMode = (PGMMODE)uGuestMode;
2301
2302	/* check separator. */
2303	uint32_t u32Sep;
2304	SSMR3GetU32(pSSM, &u32Sep);
2305	if (RT_FAILURE(rc))
2306	return rc;
2307	if (u32Sep != (uint32_t)~0)
2308	{
2309	AssertMsgFailed(("u32Sep=%#x (first)\n", u32Sep));
2310	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2311	}
2312
2313	/*
2314	* The guest mappings.
2315	*/
2316	uint32_t i = 0;
2317	for (;; i++)
2318	{
2319	/* Check the seqence number / separator. */
2320	rc = SSMR3GetU32(pSSM, &u32Sep);
2321	if (RT_FAILURE(rc))
2322	return rc;
2323	if (u32Sep == ~0U)
2324	break;
2325	if (u32Sep != i)
2326	{
2327	AssertMsgFailed(("u32Sep=%#x (last)\n", u32Sep));
2328	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2329	}
2330
2331	/* get the mapping details. */
2332	char szDesc[256];
2333	szDesc[0] = '\0';
2334	rc = SSMR3GetStrZ(pSSM, szDesc, sizeof(szDesc));
2335	if (RT_FAILURE(rc))
2336	return rc;
2337	RTGCPTR GCPtr;
2338	SSMR3GetGCPtr(pSSM, &GCPtr);
2339	RTGCPTR cPTs;
2340	rc = SSMR3GetGCUIntPtr(pSSM, &cPTs);
2341	if (RT_FAILURE(rc))
2342	return rc;
2343
2344	/* find matching range. */
2345	PPGMMAPPING pMapping;
2346	for (pMapping = pPGM->pMappingsR3; pMapping; pMapping = pMapping->pNextR3)
2347	if ( pMapping->cPTs == cPTs
2348	&& !strcmp(pMapping->pszDesc, szDesc))
2349	break;
2350	if (!pMapping)
2351	{
2352	LogRel(("Couldn't find mapping: cPTs=%#x szDesc=%s (GCPtr=%RGv)\n",
2353	cPTs, szDesc, GCPtr));
2354	AssertFailed();
2355	return VERR_SSM_LOAD_CONFIG_MISMATCH;
2356	}
2357
2358	/* relocate it. */
2359	if (pMapping->GCPtr != GCPtr)
2360	{
2361	AssertMsg((GCPtr >> X86_PD_SHIFT << X86_PD_SHIFT) == GCPtr, ("GCPtr=%RGv\n", GCPtr));
2362	pgmR3MapRelocate(pVM, pMapping, pMapping->GCPtr, GCPtr);
2363	}
2364	else
2365	Log(("pgmR3Load: '%s' needed no relocation (%RGv)\n", szDesc, GCPtr));
2366	}
2367
2368	/*
2369	* Ram range flags and bits.
2370	*/
2371	i = 0;
2372	for (PPGMRAMRANGE pRam = pPGM->pRamRangesR3; pRam; pRam = pRam->pNextR3, i++)
2373	{
2374	/** @todo MMIO ranges may move (PCI reconfig), we currently assume they don't. */
2375	/* Check the seqence number / separator. */
2376	rc = SSMR3GetU32(pSSM, &u32Sep);
2377	if (RT_FAILURE(rc))
2378	return rc;
2379	if (u32Sep == ~0U)
2380	break;
2381	if (u32Sep != i)
2382	{
2383	AssertMsgFailed(("u32Sep=%#x (last)\n", u32Sep));
2384	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2385	}
2386
2387	/* Get the range details. */
2388	RTGCPHYS GCPhys;
2389	SSMR3GetGCPhys(pSSM, &GCPhys);
2390	RTGCPHYS GCPhysLast;
2391	SSMR3GetGCPhys(pSSM, &GCPhysLast);
2392	RTGCPHYS cb;
2393	SSMR3GetGCPhys(pSSM, &cb);
2394	uint8_t fHaveBits;
2395	rc = SSMR3GetU8(pSSM, &fHaveBits);
2396	if (RT_FAILURE(rc))
2397	return rc;
2398	if (fHaveBits & ~1)
2399	{
2400	AssertMsgFailed(("u32Sep=%#x (last)\n", u32Sep));
2401	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2402	}
2403
2404	/* Match it up with the current range. */
2405	if ( GCPhys != pRam->GCPhys
2406	\|\| GCPhysLast != pRam->GCPhysLast
2407	\|\| cb != pRam->cb
2408	\|\| fHaveBits != !!pRam->pvR3)
2409	{
2410	LogRel(("Ram range: %RGp-%RGp %RGp bytes %s\n"
2411	"State : %RGp-%RGp %RGp bytes %s\n",
2412	pRam->GCPhys, pRam->GCPhysLast, pRam->cb, pRam->pvR3 ? "bits" : "nobits",
2413	GCPhys, GCPhysLast, cb, fHaveBits ? "bits" : "nobits"));
2414	/*
2415	* If we're loading a state for debugging purpose, don't make a fuss if
2416	* the MMIO[2] and ROM stuff isn't 100% right, just skip the mismatches.
2417	*/
2418	if ( SSMR3HandleGetAfter(pSSM) != SSMAFTER_DEBUG_IT
2419	\|\| GCPhys < 8 * _1M)
2420	AssertFailedReturn(VERR_SSM_LOAD_CONFIG_MISMATCH);
2421
2422	RTGCPHYS cPages = ((GCPhysLast - GCPhys) + 1) >> PAGE_SHIFT;
2423	while (cPages-- > 0)
2424	{
2425	uint16_t u16Ignore;
2426	SSMR3GetU16(pSSM, &u16Ignore);
2427	}
2428	continue;
2429	}
2430
2431	/* Flags. */
2432	const unsigned cPages = pRam->cb >> PAGE_SHIFT;
2433	for (unsigned iPage = 0; iPage < cPages; iPage++)
2434	{
2435	uint16_t u16 = 0;
2436	SSMR3GetU16(pSSM, &u16);
2437	u16 &= PAGE_OFFSET_MASK & ~( RT_BIT(4) \| RT_BIT(5) \| RT_BIT(6)
2438	\| RT_BIT(7) \| RT_BIT(8) \| RT_BIT(9) \| RT_BIT(10) );
2439	// &= MM_RAM_FLAGS_DYNAMIC_ALLOC \| MM_RAM_FLAGS_RESERVED \| MM_RAM_FLAGS_ROM \| MM_RAM_FLAGS_MMIO \| MM_RAM_FLAGS_MMIO2
2440	pRam->aPages[iPage].HCPhys = PGM_PAGE_GET_HCPHYS(&pRam->aPages[iPage]) \| (RTHCPHYS)u16; /** @todo PAGE FLAGS */
2441	}
2442
2443	/* any memory associated with the range. */
2444	if (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)
2445	{
2446	for (unsigned iChunk = 0; iChunk < (pRam->cb >> PGM_DYNAMIC_CHUNK_SHIFT); iChunk++)
2447	{
2448	uint8_t fValidChunk;
2449
2450	rc = SSMR3GetU8(pSSM, &fValidChunk);
2451	if (RT_FAILURE(rc))
2452	return rc;
2453	if (fValidChunk > 1)
2454	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2455
2456	if (fValidChunk)
2457	{
2458	if (!pRam->paChunkR3Ptrs[iChunk])
2459	{
2460	rc = pgmr3PhysGrowRange(pVM, pRam->GCPhys + iChunk * PGM_DYNAMIC_CHUNK_SIZE);
2461	if (RT_FAILURE(rc))
2462	return rc;
2463	}
2464	Assert(pRam->paChunkR3Ptrs[iChunk]);
2465
2466	SSMR3GetMem(pSSM, (void *)pRam->paChunkR3Ptrs[iChunk], PGM_DYNAMIC_CHUNK_SIZE);
2467	}
2468	/* else nothing to do */
2469	}
2470	}
2471	else if (pRam->pvR3)
2472	{
2473	int rc = SSMR3GetMem(pSSM, pRam->pvR3, pRam->cb);
2474	if (RT_FAILURE(rc))
2475	{
2476	Log(("pgmR3Save: SSMR3GetMem(, %p, %#x) -> %Rrc\n", pRam->pvR3, pRam->cb, rc));
2477	return rc;
2478	}
2479	}
2480	}
2481
2482	/*
2483	* We require a full resync now.
2484	*/
2485	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3_NON_GLOBAL);
2486	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
2487	pPGM->fSyncFlags \|= PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL;
2488	pPGM->fPhysCacheFlushPending = true;
2489	pgmR3HandlerPhysicalUpdateAll(pVM);
2490
2491	/*
2492	* Change the paging mode.
2493	*/
2494	rc = PGMR3ChangeMode(pVM, pPGM->enmGuestMode);
2495
2496	/* Restore pVM->pgm.s.GCPhysCR3. */
2497	Assert(pVM->pgm.s.GCPhysCR3 == NIL_RTGCPHYS);
2498	RTGCPHYS GCPhysCR3 = CPUMGetGuestCR3(pVM);
2499	if ( pVM->pgm.s.enmGuestMode == PGMMODE_PAE
2500	\|\| pVM->pgm.s.enmGuestMode == PGMMODE_PAE_NX
2501	\|\| pVM->pgm.s.enmGuestMode == PGMMODE_AMD64
2502	\|\| pVM->pgm.s.enmGuestMode == PGMMODE_AMD64_NX)
2503	GCPhysCR3 = (GCPhysCR3 & X86_CR3_PAE_PAGE_MASK);
2504	else
2505	GCPhysCR3 = (GCPhysCR3 & X86_CR3_PAGE_MASK);
2506	pVM->pgm.s.GCPhysCR3 = GCPhysCR3;
2507
2508	return rc;
2509	}
2510
2511
2512	/**
2513	* Show paging mode.
2514	*
2515	* @param pVM VM Handle.
2516	* @param pHlp The info helpers.
2517	* @param pszArgs "all" (default), "guest", "shadow" or "host".
2518	*/
2519	static DECLCALLBACK(void) pgmR3InfoMode(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2520	{
2521	/* digest argument. */
2522	bool fGuest, fShadow, fHost;
2523	if (pszArgs)
2524	pszArgs = RTStrStripL(pszArgs);
2525	if (!pszArgs \|\| !*pszArgs \|\| strstr(pszArgs, "all"))
2526	fShadow = fHost = fGuest = true;
2527	else
2528	{
2529	fShadow = fHost = fGuest = false;
2530	if (strstr(pszArgs, "guest"))
2531	fGuest = true;
2532	if (strstr(pszArgs, "shadow"))
2533	fShadow = true;
2534	if (strstr(pszArgs, "host"))
2535	fHost = true;
2536	}
2537
2538	/* print info. */
2539	if (fGuest)
2540	pHlp->pfnPrintf(pHlp, "Guest paging mode: %s, changed %RU64 times, A20 %s\n",
2541	PGMGetModeName(pVM->pgm.s.enmGuestMode), pVM->pgm.s.cGuestModeChanges.c,
2542	pVM->pgm.s.fA20Enabled ? "enabled" : "disabled");
2543	if (fShadow)
2544	pHlp->pfnPrintf(pHlp, "Shadow paging mode: %s\n", PGMGetModeName(pVM->pgm.s.enmShadowMode));
2545	if (fHost)
2546	{
2547	const char *psz;
2548	switch (pVM->pgm.s.enmHostMode)
2549	{
2550	case SUPPAGINGMODE_INVALID: psz = "invalid"; break;
2551	case SUPPAGINGMODE_32_BIT: psz = "32-bit"; break;
2552	case SUPPAGINGMODE_32_BIT_GLOBAL: psz = "32-bit+G"; break;
2553	case SUPPAGINGMODE_PAE: psz = "PAE"; break;
2554	case SUPPAGINGMODE_PAE_GLOBAL: psz = "PAE+G"; break;
2555	case SUPPAGINGMODE_PAE_NX: psz = "PAE+NX"; break;
2556	case SUPPAGINGMODE_PAE_GLOBAL_NX: psz = "PAE+G+NX"; break;
2557	case SUPPAGINGMODE_AMD64: psz = "AMD64"; break;
2558	case SUPPAGINGMODE_AMD64_GLOBAL: psz = "AMD64+G"; break;
2559	case SUPPAGINGMODE_AMD64_NX: psz = "AMD64+NX"; break;
2560	case SUPPAGINGMODE_AMD64_GLOBAL_NX: psz = "AMD64+G+NX"; break;
2561	default: psz = "unknown"; break;
2562	}
2563	pHlp->pfnPrintf(pHlp, "Host paging mode: %s\n", psz);
2564	}
2565	}
2566
2567
2568	/**
2569	* Dump registered MMIO ranges to the log.
2570	*
2571	* @param pVM VM Handle.
2572	* @param pHlp The info helpers.
2573	* @param pszArgs Arguments, ignored.
2574	*/
2575	static DECLCALLBACK(void) pgmR3PhysInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2576	{
2577	NOREF(pszArgs);
2578	pHlp->pfnPrintf(pHlp,
2579	"RAM ranges (pVM=%p)\n"
2580	"%.s %.s\n",
2581	pVM,
2582	sizeof(RTGCPHYS) * 4 + 1, "GC Phys Range ",
2583	sizeof(RTHCPTR) * 2, "pvHC ");
2584
2585	for (PPGMRAMRANGE pCur = pVM->pgm.s.pRamRangesR3; pCur; pCur = pCur->pNextR3)
2586	pHlp->pfnPrintf(pHlp,
2587	"%RGp-%RGp %RHv %s\n",
2588	pCur->GCPhys,
2589	pCur->GCPhysLast,
2590	pCur->pvR3,
2591	pCur->pszDesc);
2592	}
2593
2594	/**
2595	* Dump the page directory to the log.
2596	*
2597	* @param pVM VM Handle.
2598	* @param pHlp The info helpers.
2599	* @param pszArgs Arguments, ignored.
2600	*/
2601	static DECLCALLBACK(void) pgmR3InfoCr3(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2602	{
2603	/** @todo fix this! Convert the PGMR3DumpHierarchyHC functions to do guest stuff. */
2604	/* Big pages supported? */
2605	const bool fPSE = !!(CPUMGetGuestCR4(pVM) & X86_CR4_PSE);
2606
2607	/* Global pages supported? */
2608	const bool fPGE = !!(CPUMGetGuestCR4(pVM) & X86_CR4_PGE);
2609
2610	NOREF(pszArgs);
2611
2612	/*
2613	* Get page directory addresses.
2614	*/
2615	PX86PD pPDSrc = pVM->pgm.s.pGst32BitPdR3;
2616	Assert(pPDSrc);
2617	Assert(PGMPhysGCPhys2HCPtrAssert(pVM, (RTGCPHYS)(CPUMGetGuestCR3(pVM) & X86_CR3_PAGE_MASK), sizeof(*pPDSrc)) == pPDSrc);
2618
2619	/*
2620	* Iterate the page directory.
2621	*/
2622	for (unsigned iPD = 0; iPD < RT_ELEMENTS(pPDSrc->a); iPD++)
2623	{
2624	X86PDE PdeSrc = pPDSrc->a[iPD];
2625	if (PdeSrc.n.u1Present)
2626	{
2627	if (PdeSrc.b.u1Size && fPSE)
2628	pHlp->pfnPrintf(pHlp,
2629	"%04X - %RGp P=%d U=%d RW=%d G=%d - BIG\n",
2630	iPD,
2631	pgmGstGet4MBPhysPage(&pVM->pgm.s, PdeSrc),
2632	PdeSrc.b.u1Present, PdeSrc.b.u1User, PdeSrc.b.u1Write, PdeSrc.b.u1Global && fPGE);
2633	else
2634	pHlp->pfnPrintf(pHlp,
2635	"%04X - %RGp P=%d U=%d RW=%d [G=%d]\n",
2636	iPD,
2637	(RTGCPHYS)(PdeSrc.u & X86_PDE_PG_MASK),
2638	PdeSrc.n.u1Present, PdeSrc.n.u1User, PdeSrc.n.u1Write, PdeSrc.b.u1Global && fPGE);
2639	}
2640	}
2641	}
2642
2643
2644	/**
2645	* Serivce a VMMCALLHOST_PGM_LOCK call.
2646	*
2647	* @returns VBox status code.
2648	* @param pVM The VM handle.
2649	*/
2650	VMMR3DECL(int) PGMR3LockCall(PVM pVM)
2651	{
2652	int rc = PDMR3CritSectEnterEx(&pVM->pgm.s.CritSect, true /* fHostCall */);
2653	AssertRC(rc);
2654	return rc;
2655	}
2656
2657
2658	/**
2659	* Converts a PGMMODE value to a PGM_TYPE_* \#define.
2660	*
2661	* @returns PGM_TYPE_*.
2662	* @param pgmMode The mode value to convert.
2663	*/
2664	DECLINLINE(unsigned) pgmModeToType(PGMMODE pgmMode)
2665	{
2666	switch (pgmMode)
2667	{
2668	case PGMMODE_REAL: return PGM_TYPE_REAL;
2669	case PGMMODE_PROTECTED: return PGM_TYPE_PROT;
2670	case PGMMODE_32_BIT: return PGM_TYPE_32BIT;
2671	case PGMMODE_PAE:
2672	case PGMMODE_PAE_NX: return PGM_TYPE_PAE;
2673	case PGMMODE_AMD64:
2674	case PGMMODE_AMD64_NX: return PGM_TYPE_AMD64;
2675	case PGMMODE_NESTED: return PGM_TYPE_NESTED;
2676	case PGMMODE_EPT: return PGM_TYPE_EPT;
2677	default:
2678	AssertFatalMsgFailed(("pgmMode=%d\n", pgmMode));
2679	}
2680	}
2681
2682
2683	/**
2684	* Gets the index into the paging mode data array of a SHW+GST mode.
2685	*
2686	* @returns PGM::paPagingData index.
2687	* @param uShwType The shadow paging mode type.
2688	* @param uGstType The guest paging mode type.
2689	*/
2690	DECLINLINE(unsigned) pgmModeDataIndex(unsigned uShwType, unsigned uGstType)
2691	{
2692	Assert(uShwType >= PGM_TYPE_32BIT && uShwType <= PGM_TYPE_MAX);
2693	Assert(uGstType >= PGM_TYPE_REAL && uGstType <= PGM_TYPE_AMD64);
2694	return (uShwType - PGM_TYPE_32BIT) * (PGM_TYPE_AMD64 - PGM_TYPE_REAL + 1)
2695	+ (uGstType - PGM_TYPE_REAL);
2696	}
2697
2698
2699	/**
2700	* Gets the index into the paging mode data array of a SHW+GST mode.
2701	*
2702	* @returns PGM::paPagingData index.
2703	* @param enmShw The shadow paging mode.
2704	* @param enmGst The guest paging mode.
2705	*/
2706	DECLINLINE(unsigned) pgmModeDataIndexByMode(PGMMODE enmShw, PGMMODE enmGst)
2707	{
2708	Assert(enmShw >= PGMMODE_32_BIT && enmShw <= PGMMODE_MAX);
2709	Assert(enmGst > PGMMODE_INVALID && enmGst < PGMMODE_MAX);
2710	return pgmModeDataIndex(pgmModeToType(enmShw), pgmModeToType(enmGst));
2711	}
2712
2713
2714	/**
2715	* Calculates the max data index.
2716	* @returns The number of entries in the paging data array.
2717	*/
2718	DECLINLINE(unsigned) pgmModeDataMaxIndex(void)
2719	{
2720	return pgmModeDataIndex(PGM_TYPE_MAX, PGM_TYPE_AMD64) + 1;
2721	}
2722
2723
2724	/**
2725	* Initializes the paging mode data kept in PGM::paModeData.
2726	*
2727	* @param pVM The VM handle.
2728	* @param fResolveGCAndR0 Indicate whether or not GC and Ring-0 symbols can be resolved now.
2729	* This is used early in the init process to avoid trouble with PDM
2730	* not being initialized yet.
2731	*/
2732	static int pgmR3ModeDataInit(PVM pVM, bool fResolveGCAndR0)
2733	{
2734	PPGMMODEDATA pModeData;
2735	int rc;
2736
2737	/*
2738	* Allocate the array on the first call.
2739	*/
2740	if (!pVM->pgm.s.paModeData)
2741	{
2742	pVM->pgm.s.paModeData = (PPGMMODEDATA)MMR3HeapAllocZ(pVM, MM_TAG_PGM, sizeof(PGMMODEDATA) * pgmModeDataMaxIndex());
2743	AssertReturn(pVM->pgm.s.paModeData, VERR_NO_MEMORY);
2744	}
2745
2746	/*
2747	* Initialize the array entries.
2748	*/
2749	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_32BIT, PGM_TYPE_REAL)];
2750	pModeData->uShwType = PGM_TYPE_32BIT;
2751	pModeData->uGstType = PGM_TYPE_REAL;
2752	rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2753	rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2754	rc = PGM_BTH_NAME_32BIT_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2755
2756	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_32BIT, PGMMODE_PROTECTED)];
2757	pModeData->uShwType = PGM_TYPE_32BIT;
2758	pModeData->uGstType = PGM_TYPE_PROT;
2759	rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2760	rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2761	rc = PGM_BTH_NAME_32BIT_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2762
2763	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_32BIT, PGM_TYPE_32BIT)];
2764	pModeData->uShwType = PGM_TYPE_32BIT;
2765	pModeData->uGstType = PGM_TYPE_32BIT;
2766	rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2767	rc = PGM_GST_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2768	rc = PGM_BTH_NAME_32BIT_32BIT(InitData)(pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2769
2770	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_REAL)];
2771	pModeData->uShwType = PGM_TYPE_PAE;
2772	pModeData->uGstType = PGM_TYPE_REAL;
2773	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2774	rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2775	rc = PGM_BTH_NAME_PAE_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2776
2777	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_PROT)];
2778	pModeData->uShwType = PGM_TYPE_PAE;
2779	pModeData->uGstType = PGM_TYPE_PROT;
2780	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2781	rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2782	rc = PGM_BTH_NAME_PAE_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2783
2784	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_32BIT)];
2785	pModeData->uShwType = PGM_TYPE_PAE;
2786	pModeData->uGstType = PGM_TYPE_32BIT;
2787	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2788	rc = PGM_GST_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2789	rc = PGM_BTH_NAME_PAE_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2790
2791	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_PAE)];
2792	pModeData->uShwType = PGM_TYPE_PAE;
2793	pModeData->uGstType = PGM_TYPE_PAE;
2794	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2795	rc = PGM_GST_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2796	rc = PGM_BTH_NAME_PAE_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2797
2798	#ifdef VBOX_WITH_64_BITS_GUESTS
2799	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_AMD64, PGM_TYPE_AMD64)];
2800	pModeData->uShwType = PGM_TYPE_AMD64;
2801	pModeData->uGstType = PGM_TYPE_AMD64;
2802	rc = PGM_SHW_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2803	rc = PGM_GST_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2804	rc = PGM_BTH_NAME_AMD64_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2805	#endif
2806
2807	/* The nested paging mode. */
2808	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_REAL)];
2809	pModeData->uShwType = PGM_TYPE_NESTED;
2810	pModeData->uGstType = PGM_TYPE_REAL;
2811	rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2812	rc = PGM_BTH_NAME_NESTED_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2813
2814	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGMMODE_PROTECTED)];
2815	pModeData->uShwType = PGM_TYPE_NESTED;
2816	pModeData->uGstType = PGM_TYPE_PROT;
2817	rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2818	rc = PGM_BTH_NAME_NESTED_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2819
2820	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_32BIT)];
2821	pModeData->uShwType = PGM_TYPE_NESTED;
2822	pModeData->uGstType = PGM_TYPE_32BIT;
2823	rc = PGM_GST_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2824	rc = PGM_BTH_NAME_NESTED_32BIT(InitData)(pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2825
2826	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_PAE)];
2827	pModeData->uShwType = PGM_TYPE_NESTED;
2828	pModeData->uGstType = PGM_TYPE_PAE;
2829	rc = PGM_GST_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2830	rc = PGM_BTH_NAME_NESTED_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2831
2832	#ifdef VBOX_WITH_64_BITS_GUESTS
2833	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_AMD64)];
2834	pModeData->uShwType = PGM_TYPE_NESTED;
2835	pModeData->uGstType = PGM_TYPE_AMD64;
2836	rc = PGM_GST_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2837	rc = PGM_BTH_NAME_NESTED_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2838	#endif
2839
2840	/* The shadow part of the nested callback mode depends on the host paging mode (AMD-V only). */
2841	switch(pVM->pgm.s.enmHostMode)
2842	{
2843	case SUPPAGINGMODE_32_BIT:
2844	case SUPPAGINGMODE_32_BIT_GLOBAL:
2845	#ifdef VBOX_WITH_64_BITS_GUESTS
2846	for (unsigned i=PGM_TYPE_REAL;i<=PGM_TYPE_AMD64;i++)
2847	#else
2848	for (unsigned i=PGM_TYPE_REAL;i<=PGM_TYPE_PAE;i++)
2849	#endif
2850	{
2851	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, i)];
2852	rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2853	}
2854	break;
2855
2856	case SUPPAGINGMODE_PAE:
2857	case SUPPAGINGMODE_PAE_NX:
2858	case SUPPAGINGMODE_PAE_GLOBAL:
2859	case SUPPAGINGMODE_PAE_GLOBAL_NX:
2860	#ifdef VBOX_WITH_64_BITS_GUESTS
2861	for (unsigned i=PGM_TYPE_REAL;i<=PGM_TYPE_AMD64;i++)
2862	#else
2863	for (unsigned i=PGM_TYPE_REAL;i<=PGM_TYPE_PAE;i++)
2864	#endif
2865	{
2866	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, i)];
2867	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2868	}
2869	break;
2870
2871	case SUPPAGINGMODE_AMD64:
2872	case SUPPAGINGMODE_AMD64_GLOBAL:
2873	case SUPPAGINGMODE_AMD64_NX:
2874	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
2875	#ifdef VBOX_WITH_64_BITS_GUESTS
2876	for (unsigned i=PGM_TYPE_REAL;i<=PGM_TYPE_AMD64;i++)
2877	#else
2878	for (unsigned i=PGM_TYPE_REAL;i<=PGM_TYPE_PAE;i++)
2879	#endif
2880	{
2881	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, i)];
2882	rc = PGM_SHW_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2883	}
2884	break;
2885	default:
2886	AssertFailed();
2887	break;
2888	}
2889
2890	/* Extended paging (EPT) / Intel VT-x */
2891	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_REAL)];
2892	pModeData->uShwType = PGM_TYPE_EPT;
2893	pModeData->uGstType = PGM_TYPE_REAL;
2894	rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2895	rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2896	rc = PGM_BTH_NAME_EPT_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2897
2898	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_PROT)];
2899	pModeData->uShwType = PGM_TYPE_EPT;
2900	pModeData->uGstType = PGM_TYPE_PROT;
2901	rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2902	rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2903	rc = PGM_BTH_NAME_EPT_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2904
2905	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_32BIT)];
2906	pModeData->uShwType = PGM_TYPE_EPT;
2907	pModeData->uGstType = PGM_TYPE_32BIT;
2908	rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2909	rc = PGM_GST_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2910	rc = PGM_BTH_NAME_EPT_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2911
2912	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_PAE)];
2913	pModeData->uShwType = PGM_TYPE_EPT;
2914	pModeData->uGstType = PGM_TYPE_PAE;
2915	rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2916	rc = PGM_GST_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2917	rc = PGM_BTH_NAME_EPT_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2918
2919	#ifdef VBOX_WITH_64_BITS_GUESTS
2920	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_AMD64)];
2921	pModeData->uShwType = PGM_TYPE_EPT;
2922	pModeData->uGstType = PGM_TYPE_AMD64;
2923	rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2924	rc = PGM_GST_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2925	rc = PGM_BTH_NAME_EPT_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2926	#endif
2927	return VINF_SUCCESS;
2928	}
2929
2930
2931	/**
2932	* Switch to different (or relocated in the relocate case) mode data.
2933	*
2934	* @param pVM The VM handle.
2935	* @param enmShw The the shadow paging mode.
2936	* @param enmGst The the guest paging mode.
2937	*/
2938	static void pgmR3ModeDataSwitch(PVM pVM, PGMMODE enmShw, PGMMODE enmGst)
2939	{
2940	PPGMMODEDATA pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndexByMode(enmShw, enmGst)];
2941
2942	Assert(pModeData->uGstType == pgmModeToType(enmGst));
2943	Assert(pModeData->uShwType == pgmModeToType(enmShw));
2944
2945	/* shadow */
2946	pVM->pgm.s.pfnR3ShwRelocate = pModeData->pfnR3ShwRelocate;
2947	pVM->pgm.s.pfnR3ShwExit = pModeData->pfnR3ShwExit;
2948	pVM->pgm.s.pfnR3ShwGetPage = pModeData->pfnR3ShwGetPage;
2949	Assert(pVM->pgm.s.pfnR3ShwGetPage);
2950	pVM->pgm.s.pfnR3ShwModifyPage = pModeData->pfnR3ShwModifyPage;
2951
2952	pVM->pgm.s.pfnRCShwGetPage = pModeData->pfnRCShwGetPage;
2953	pVM->pgm.s.pfnRCShwModifyPage = pModeData->pfnRCShwModifyPage;
2954
2955	pVM->pgm.s.pfnR0ShwGetPage = pModeData->pfnR0ShwGetPage;
2956	pVM->pgm.s.pfnR0ShwModifyPage = pModeData->pfnR0ShwModifyPage;
2957
2958
2959	/* guest */
2960	pVM->pgm.s.pfnR3GstRelocate = pModeData->pfnR3GstRelocate;
2961	pVM->pgm.s.pfnR3GstExit = pModeData->pfnR3GstExit;
2962	pVM->pgm.s.pfnR3GstGetPage = pModeData->pfnR3GstGetPage;
2963	Assert(pVM->pgm.s.pfnR3GstGetPage);
2964	pVM->pgm.s.pfnR3GstModifyPage = pModeData->pfnR3GstModifyPage;
2965	pVM->pgm.s.pfnR3GstGetPDE = pModeData->pfnR3GstGetPDE;
2966	pVM->pgm.s.pfnR3GstMonitorCR3 = pModeData->pfnR3GstMonitorCR3;
2967	pVM->pgm.s.pfnR3GstUnmonitorCR3 = pModeData->pfnR3GstUnmonitorCR3;
2968	pVM->pgm.s.pfnR3GstMapCR3 = pModeData->pfnR3GstMapCR3;
2969	pVM->pgm.s.pfnR3GstUnmapCR3 = pModeData->pfnR3GstUnmapCR3;
2970	pVM->pgm.s.pfnR3GstWriteHandlerCR3 = pModeData->pfnR3GstWriteHandlerCR3;
2971	pVM->pgm.s.pszR3GstWriteHandlerCR3 = pModeData->pszR3GstWriteHandlerCR3;
2972	pVM->pgm.s.pfnR3GstPAEWriteHandlerCR3 = pModeData->pfnR3GstPAEWriteHandlerCR3;
2973	pVM->pgm.s.pszR3GstPAEWriteHandlerCR3 = pModeData->pszR3GstPAEWriteHandlerCR3;
2974
2975	pVM->pgm.s.pfnRCGstGetPage = pModeData->pfnRCGstGetPage;
2976	pVM->pgm.s.pfnRCGstModifyPage = pModeData->pfnRCGstModifyPage;
2977	pVM->pgm.s.pfnRCGstGetPDE = pModeData->pfnRCGstGetPDE;
2978	pVM->pgm.s.pfnRCGstMonitorCR3 = pModeData->pfnRCGstMonitorCR3;
2979	pVM->pgm.s.pfnRCGstUnmonitorCR3 = pModeData->pfnRCGstUnmonitorCR3;
2980	pVM->pgm.s.pfnRCGstMapCR3 = pModeData->pfnRCGstMapCR3;
2981	pVM->pgm.s.pfnRCGstUnmapCR3 = pModeData->pfnRCGstUnmapCR3;
2982	pVM->pgm.s.pfnRCGstWriteHandlerCR3 = pModeData->pfnRCGstWriteHandlerCR3;
2983	pVM->pgm.s.pfnRCGstPAEWriteHandlerCR3 = pModeData->pfnRCGstPAEWriteHandlerCR3;
2984
2985	pVM->pgm.s.pfnR0GstGetPage = pModeData->pfnR0GstGetPage;
2986	pVM->pgm.s.pfnR0GstModifyPage = pModeData->pfnR0GstModifyPage;
2987	pVM->pgm.s.pfnR0GstGetPDE = pModeData->pfnR0GstGetPDE;
2988	pVM->pgm.s.pfnR0GstMonitorCR3 = pModeData->pfnR0GstMonitorCR3;
2989	pVM->pgm.s.pfnR0GstUnmonitorCR3 = pModeData->pfnR0GstUnmonitorCR3;
2990	pVM->pgm.s.pfnR0GstMapCR3 = pModeData->pfnR0GstMapCR3;
2991	pVM->pgm.s.pfnR0GstUnmapCR3 = pModeData->pfnR0GstUnmapCR3;
2992	pVM->pgm.s.pfnR0GstWriteHandlerCR3 = pModeData->pfnR0GstWriteHandlerCR3;
2993	pVM->pgm.s.pfnR0GstPAEWriteHandlerCR3 = pModeData->pfnR0GstPAEWriteHandlerCR3;
2994
2995
2996	/* both */
2997	pVM->pgm.s.pfnR3BthRelocate = pModeData->pfnR3BthRelocate;
2998	pVM->pgm.s.pfnR3BthInvalidatePage = pModeData->pfnR3BthInvalidatePage;
2999	pVM->pgm.s.pfnR3BthSyncCR3 = pModeData->pfnR3BthSyncCR3;
3000	Assert(pVM->pgm.s.pfnR3BthSyncCR3);
3001	pVM->pgm.s.pfnR3BthSyncPage = pModeData->pfnR3BthSyncPage;
3002	pVM->pgm.s.pfnR3BthPrefetchPage = pModeData->pfnR3BthPrefetchPage;
3003	pVM->pgm.s.pfnR3BthVerifyAccessSyncPage = pModeData->pfnR3BthVerifyAccessSyncPage;
3004	#ifdef VBOX_STRICT
3005	pVM->pgm.s.pfnR3BthAssertCR3 = pModeData->pfnR3BthAssertCR3;
3006	#endif
3007
3008	pVM->pgm.s.pfnRCBthTrap0eHandler = pModeData->pfnRCBthTrap0eHandler;
3009	pVM->pgm.s.pfnRCBthInvalidatePage = pModeData->pfnRCBthInvalidatePage;
3010	pVM->pgm.s.pfnRCBthSyncCR3 = pModeData->pfnRCBthSyncCR3;
3011	pVM->pgm.s.pfnRCBthSyncPage = pModeData->pfnRCBthSyncPage;
3012	pVM->pgm.s.pfnRCBthPrefetchPage = pModeData->pfnRCBthPrefetchPage;
3013	pVM->pgm.s.pfnRCBthVerifyAccessSyncPage = pModeData->pfnRCBthVerifyAccessSyncPage;
3014	#ifdef VBOX_STRICT
3015	pVM->pgm.s.pfnRCBthAssertCR3 = pModeData->pfnRCBthAssertCR3;
3016	#endif
3017
3018	pVM->pgm.s.pfnR0BthTrap0eHandler = pModeData->pfnR0BthTrap0eHandler;
3019	pVM->pgm.s.pfnR0BthInvalidatePage = pModeData->pfnR0BthInvalidatePage;
3020	pVM->pgm.s.pfnR0BthSyncCR3 = pModeData->pfnR0BthSyncCR3;
3021	pVM->pgm.s.pfnR0BthSyncPage = pModeData->pfnR0BthSyncPage;
3022	pVM->pgm.s.pfnR0BthPrefetchPage = pModeData->pfnR0BthPrefetchPage;
3023	pVM->pgm.s.pfnR0BthVerifyAccessSyncPage = pModeData->pfnR0BthVerifyAccessSyncPage;
3024	#ifdef VBOX_STRICT
3025	pVM->pgm.s.pfnR0BthAssertCR3 = pModeData->pfnR0BthAssertCR3;
3026	#endif
3027	}
3028
3029
3030	/**
3031	* Calculates the shadow paging mode.
3032	*
3033	* @returns The shadow paging mode.
3034	* @param pVM VM handle.
3035	* @param enmGuestMode The guest mode.
3036	* @param enmHostMode The host mode.
3037	* @param enmShadowMode The current shadow mode.
3038	* @param penmSwitcher Where to store the switcher to use.
3039	* VMMSWITCHER_INVALID means no change.
3040	*/
3041	static PGMMODE pgmR3CalcShadowMode(PVM pVM, PGMMODE enmGuestMode, SUPPAGINGMODE enmHostMode, PGMMODE enmShadowMode, VMMSWITCHER *penmSwitcher)
3042	{
3043	VMMSWITCHER enmSwitcher = VMMSWITCHER_INVALID;
3044	switch (enmGuestMode)
3045	{
3046	/*
3047	* When switching to real or protected mode we don't change
3048	* anything since it's likely that we'll switch back pretty soon.
3049	*
3050	* During pgmR3InitPaging we'll end up here with PGMMODE_INVALID
3051	* and is supposed to determine which shadow paging and switcher to
3052	* use during init.
3053	*/
3054	case PGMMODE_REAL:
3055	case PGMMODE_PROTECTED:
3056	if ( enmShadowMode != PGMMODE_INVALID
3057	&& !HWACCMIsEnabled(pVM) /* always switch in hwaccm mode! */)
3058	break; /* (no change) */
3059
3060	switch (enmHostMode)
3061	{
3062	case SUPPAGINGMODE_32_BIT:
3063	case SUPPAGINGMODE_32_BIT_GLOBAL:
3064	enmShadowMode = PGMMODE_32_BIT;
3065	enmSwitcher = VMMSWITCHER_32_TO_32;
3066	break;
3067
3068	case SUPPAGINGMODE_PAE:
3069	case SUPPAGINGMODE_PAE_NX:
3070	case SUPPAGINGMODE_PAE_GLOBAL:
3071	case SUPPAGINGMODE_PAE_GLOBAL_NX:
3072	enmShadowMode = PGMMODE_PAE;
3073	enmSwitcher = VMMSWITCHER_PAE_TO_PAE;
3074	#ifdef DEBUG_bird
3075	if (RTEnvExist("VBOX_32BIT"))
3076	{
3077	enmShadowMode = PGMMODE_32_BIT;
3078	enmSwitcher = VMMSWITCHER_PAE_TO_32;
3079	}
3080	#endif
3081	break;
3082
3083	case SUPPAGINGMODE_AMD64:
3084	case SUPPAGINGMODE_AMD64_GLOBAL:
3085	case SUPPAGINGMODE_AMD64_NX:
3086	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
3087	enmShadowMode = PGMMODE_PAE;
3088	enmSwitcher = VMMSWITCHER_AMD64_TO_PAE;
3089	break;
3090
3091	default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
3092	}
3093	break;
3094
3095	case PGMMODE_32_BIT:
3096	switch (enmHostMode)
3097	{
3098	case SUPPAGINGMODE_32_BIT:
3099	case SUPPAGINGMODE_32_BIT_GLOBAL:
3100	enmShadowMode = PGMMODE_32_BIT;
3101	enmSwitcher = VMMSWITCHER_32_TO_32;
3102	break;
3103
3104	case SUPPAGINGMODE_PAE:
3105	case SUPPAGINGMODE_PAE_NX:
3106	case SUPPAGINGMODE_PAE_GLOBAL:
3107	case SUPPAGINGMODE_PAE_GLOBAL_NX:
3108	enmShadowMode = PGMMODE_PAE;
3109	enmSwitcher = VMMSWITCHER_PAE_TO_PAE;
3110	#ifdef DEBUG_bird
3111	if (RTEnvExist("VBOX_32BIT"))
3112	{
3113	enmShadowMode = PGMMODE_32_BIT;
3114	enmSwitcher = VMMSWITCHER_PAE_TO_32;
3115	}
3116	#endif
3117	break;
3118
3119	case SUPPAGINGMODE_AMD64:
3120	case SUPPAGINGMODE_AMD64_GLOBAL:
3121	case SUPPAGINGMODE_AMD64_NX:
3122	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
3123	enmShadowMode = PGMMODE_PAE;
3124	enmSwitcher = VMMSWITCHER_AMD64_TO_PAE;
3125	break;
3126
3127	default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
3128	}
3129	break;
3130
3131	case PGMMODE_PAE:
3132	case PGMMODE_PAE_NX: /** @todo This might require more switchers and guest+both modes. */
3133	switch (enmHostMode)
3134	{
3135	case SUPPAGINGMODE_32_BIT:
3136	case SUPPAGINGMODE_32_BIT_GLOBAL:
3137	enmShadowMode = PGMMODE_PAE;
3138	enmSwitcher = VMMSWITCHER_32_TO_PAE;
3139	break;
3140
3141	case SUPPAGINGMODE_PAE:
3142	case SUPPAGINGMODE_PAE_NX:
3143	case SUPPAGINGMODE_PAE_GLOBAL:
3144	case SUPPAGINGMODE_PAE_GLOBAL_NX:
3145	enmShadowMode = PGMMODE_PAE;
3146	enmSwitcher = VMMSWITCHER_PAE_TO_PAE;
3147	break;
3148
3149	case SUPPAGINGMODE_AMD64:
3150	case SUPPAGINGMODE_AMD64_GLOBAL:
3151	case SUPPAGINGMODE_AMD64_NX:
3152	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
3153	enmShadowMode = PGMMODE_PAE;
3154	enmSwitcher = VMMSWITCHER_AMD64_TO_PAE;
3155	break;
3156
3157	default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
3158	}
3159	break;
3160
3161	case PGMMODE_AMD64:
3162	case PGMMODE_AMD64_NX:
3163	switch (enmHostMode)
3164	{
3165	case SUPPAGINGMODE_32_BIT:
3166	case SUPPAGINGMODE_32_BIT_GLOBAL:
3167	enmShadowMode = PGMMODE_PAE;
3168	enmSwitcher = VMMSWITCHER_32_TO_AMD64;
3169	break;
3170
3171	case SUPPAGINGMODE_PAE:
3172	case SUPPAGINGMODE_PAE_NX:
3173	case SUPPAGINGMODE_PAE_GLOBAL:
3174	case SUPPAGINGMODE_PAE_GLOBAL_NX:
3175	enmShadowMode = PGMMODE_PAE;
3176	enmSwitcher = VMMSWITCHER_PAE_TO_AMD64;
3177	break;
3178
3179	case SUPPAGINGMODE_AMD64:
3180	case SUPPAGINGMODE_AMD64_GLOBAL:
3181	case SUPPAGINGMODE_AMD64_NX:
3182	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
3183	enmShadowMode = PGMMODE_AMD64;
3184	enmSwitcher = VMMSWITCHER_AMD64_TO_AMD64;
3185	break;
3186
3187	default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
3188	}
3189	break;
3190
3191
3192	default:
3193	AssertReleaseMsgFailed(("enmGuestMode=%d\n", enmGuestMode));
3194	return PGMMODE_INVALID;
3195	}
3196	/* Override the shadow mode is nested paging is active. */
3197	if (HWACCMIsNestedPagingActive(pVM))
3198	enmShadowMode = HWACCMGetPagingMode(pVM);
3199
3200	*penmSwitcher = enmSwitcher;
3201	return enmShadowMode;
3202	}
3203
3204
3205	/**
3206	* Performs the actual mode change.
3207	* This is called by PGMChangeMode and pgmR3InitPaging().
3208	*
3209	* @returns VBox status code.
3210	* @param pVM VM handle.
3211	* @param enmGuestMode The new guest mode. This is assumed to be different from
3212	* the current mode.
3213	*/
3214	VMMR3DECL(int) PGMR3ChangeMode(PVM pVM, PGMMODE enmGuestMode)
3215	{
3216	Log(("PGMR3ChangeMode: Guest mode: %s -> %s\n", PGMGetModeName(pVM->pgm.s.enmGuestMode), PGMGetModeName(enmGuestMode)));
3217	STAM_REL_COUNTER_INC(&pVM->pgm.s.cGuestModeChanges);
3218
3219	/*
3220	* Calc the shadow mode and switcher.
3221	*/
3222	VMMSWITCHER enmSwitcher;
3223	PGMMODE enmShadowMode = pgmR3CalcShadowMode(pVM, enmGuestMode, pVM->pgm.s.enmHostMode, pVM->pgm.s.enmShadowMode, &enmSwitcher);
3224	if (enmSwitcher != VMMSWITCHER_INVALID)
3225	{
3226	/*
3227	* Select new switcher.
3228	*/
3229	int rc = VMMR3SelectSwitcher(pVM, enmSwitcher);
3230	if (RT_FAILURE(rc))
3231	{
3232	AssertReleaseMsgFailed(("VMMR3SelectSwitcher(%d) -> %Rrc\n", enmSwitcher, rc));
3233	return rc;
3234	}
3235	}
3236
3237	/*
3238	* Exit old mode(s).
3239	*/
3240	/* shadow */
3241	if (enmShadowMode != pVM->pgm.s.enmShadowMode)
3242	{
3243	LogFlow(("PGMR3ChangeMode: Shadow mode: %s -> %s\n", PGMGetModeName(pVM->pgm.s.enmShadowMode), PGMGetModeName(enmShadowMode)));
3244	if (PGM_SHW_PFN(Exit, pVM))
3245	{
3246	int rc = PGM_SHW_PFN(Exit, pVM)(pVM);
3247	if (RT_FAILURE(rc))
3248	{
3249	AssertMsgFailed(("Exit failed for shadow mode %d: %Rrc\n", pVM->pgm.s.enmShadowMode, rc));
3250	return rc;
3251	}
3252	}
3253
3254	}
3255	else
3256	LogFlow(("PGMR3ChangeMode: Shadow mode remains: %s\n", PGMGetModeName(pVM->pgm.s.enmShadowMode)));
3257
3258	/* guest */
3259	if (PGM_GST_PFN(Exit, pVM))
3260	{
3261	int rc = PGM_GST_PFN(Exit, pVM)(pVM);
3262	if (RT_FAILURE(rc))
3263	{
3264	AssertMsgFailed(("Exit failed for guest mode %d: %Rrc\n", pVM->pgm.s.enmGuestMode, rc));
3265	return rc;
3266	}
3267	}
3268
3269	/*
3270	* Load new paging mode data.
3271	*/
3272	pgmR3ModeDataSwitch(pVM, enmShadowMode, enmGuestMode);
3273
3274	/*
3275	* Enter new shadow mode (if changed).
3276	*/
3277	if (enmShadowMode != pVM->pgm.s.enmShadowMode)
3278	{
3279	int rc;
3280	pVM->pgm.s.enmShadowMode = enmShadowMode;
3281	switch (enmShadowMode)
3282	{
3283	case PGMMODE_32_BIT:
3284	rc = PGM_SHW_NAME_32BIT(Enter)(pVM);
3285	break;
3286	case PGMMODE_PAE:
3287	case PGMMODE_PAE_NX:
3288	rc = PGM_SHW_NAME_PAE(Enter)(pVM);
3289	break;
3290	case PGMMODE_AMD64:
3291	case PGMMODE_AMD64_NX:
3292	rc = PGM_SHW_NAME_AMD64(Enter)(pVM);
3293	break;
3294	case PGMMODE_NESTED:
3295	rc = PGM_SHW_NAME_NESTED(Enter)(pVM);
3296	break;
3297	case PGMMODE_EPT:
3298	rc = PGM_SHW_NAME_EPT(Enter)(pVM);
3299	break;
3300	case PGMMODE_REAL:
3301	case PGMMODE_PROTECTED:
3302	default:
3303	AssertReleaseMsgFailed(("enmShadowMode=%d\n", enmShadowMode));
3304	return VERR_INTERNAL_ERROR;
3305	}
3306	if (RT_FAILURE(rc))
3307	{
3308	AssertReleaseMsgFailed(("Entering enmShadowMode=%d failed: %Rrc\n", enmShadowMode, rc));
3309	pVM->pgm.s.enmShadowMode = PGMMODE_INVALID;
3310	return rc;
3311	}
3312	}
3313
3314	/** @todo This is a bug!
3315	*
3316	* We must flush the PGM pool cache if the guest mode changes; we don't always
3317	* switch shadow paging mode (e.g. protected->32-bit) and shouldn't reuse
3318	* the shadow page tables.
3319	*
3320	* That only applies when switching between paging and non-paging modes.
3321	*/
3322	/** @todo A20 setting */
3323	if ( pVM->pgm.s.CTX_SUFF(pPool)
3324	&& !HWACCMIsNestedPagingActive(pVM)
3325	&& PGMMODE_WITH_PAGING(pVM->pgm.s.enmGuestMode) != PGMMODE_WITH_PAGING(enmGuestMode))
3326	{
3327	Log(("PGMR3ChangeMode: changing guest paging mode -> flush pgm pool cache!\n"));
3328	pgmPoolFlushAll(pVM);
3329	}
3330
3331	/*
3332	* Enter the new guest and shadow+guest modes.
3333	*/
3334	int rc = -1;
3335	int rc2 = -1;
3336	RTGCPHYS GCPhysCR3 = NIL_RTGCPHYS;
3337	pVM->pgm.s.enmGuestMode = enmGuestMode;
3338	switch (enmGuestMode)
3339	{
3340	case PGMMODE_REAL:
3341	rc = PGM_GST_NAME_REAL(Enter)(pVM, NIL_RTGCPHYS);
3342	switch (pVM->pgm.s.enmShadowMode)
3343	{
3344	case PGMMODE_32_BIT:
3345	rc2 = PGM_BTH_NAME_32BIT_REAL(Enter)(pVM, NIL_RTGCPHYS);
3346	break;
3347	case PGMMODE_PAE:
3348	case PGMMODE_PAE_NX:
3349	rc2 = PGM_BTH_NAME_PAE_REAL(Enter)(pVM, NIL_RTGCPHYS);
3350	break;
3351	case PGMMODE_NESTED:
3352	rc2 = PGM_BTH_NAME_NESTED_REAL(Enter)(pVM, NIL_RTGCPHYS);
3353	break;
3354	case PGMMODE_EPT:
3355	rc2 = PGM_BTH_NAME_EPT_REAL(Enter)(pVM, NIL_RTGCPHYS);
3356	break;
3357	case PGMMODE_AMD64:
3358	case PGMMODE_AMD64_NX:
3359	AssertMsgFailed(("Should use PAE shadow mode!\n"));
3360	default: AssertFailed(); break;
3361	}
3362	break;
3363
3364	case PGMMODE_PROTECTED:
3365	rc = PGM_GST_NAME_PROT(Enter)(pVM, NIL_RTGCPHYS);
3366	switch (pVM->pgm.s.enmShadowMode)
3367	{
3368	case PGMMODE_32_BIT:
3369	rc2 = PGM_BTH_NAME_32BIT_PROT(Enter)(pVM, NIL_RTGCPHYS);
3370	break;
3371	case PGMMODE_PAE:
3372	case PGMMODE_PAE_NX:
3373	rc2 = PGM_BTH_NAME_PAE_PROT(Enter)(pVM, NIL_RTGCPHYS);
3374	break;
3375	case PGMMODE_NESTED:
3376	rc2 = PGM_BTH_NAME_NESTED_PROT(Enter)(pVM, NIL_RTGCPHYS);
3377	break;
3378	case PGMMODE_EPT:
3379	rc2 = PGM_BTH_NAME_EPT_PROT(Enter)(pVM, NIL_RTGCPHYS);
3380	break;
3381	case PGMMODE_AMD64:
3382	case PGMMODE_AMD64_NX:
3383	AssertMsgFailed(("Should use PAE shadow mode!\n"));
3384	default: AssertFailed(); break;
3385	}
3386	break;
3387
3388	case PGMMODE_32_BIT:
3389	GCPhysCR3 = CPUMGetGuestCR3(pVM) & X86_CR3_PAGE_MASK;
3390	rc = PGM_GST_NAME_32BIT(Enter)(pVM, GCPhysCR3);
3391	switch (pVM->pgm.s.enmShadowMode)
3392	{
3393	case PGMMODE_32_BIT:
3394	rc2 = PGM_BTH_NAME_32BIT_32BIT(Enter)(pVM, GCPhysCR3);
3395	break;
3396	case PGMMODE_PAE:
3397	case PGMMODE_PAE_NX:
3398	rc2 = PGM_BTH_NAME_PAE_32BIT(Enter)(pVM, GCPhysCR3);
3399	break;
3400	case PGMMODE_NESTED:
3401	rc2 = PGM_BTH_NAME_NESTED_32BIT(Enter)(pVM, GCPhysCR3);
3402	break;
3403	case PGMMODE_EPT:
3404	rc2 = PGM_BTH_NAME_EPT_32BIT(Enter)(pVM, GCPhysCR3);
3405	break;
3406	case PGMMODE_AMD64:
3407	case PGMMODE_AMD64_NX:
3408	AssertMsgFailed(("Should use PAE shadow mode!\n"));
3409	default: AssertFailed(); break;
3410	}
3411	break;
3412
3413	case PGMMODE_PAE_NX:
3414	case PGMMODE_PAE:
3415	{
3416	uint32_t u32Dummy, u32Features;
3417
3418	CPUMGetGuestCpuId(pVM, 1, &u32Dummy, &u32Dummy, &u32Dummy, &u32Features);
3419	if (!(u32Features & X86_CPUID_FEATURE_EDX_PAE))
3420	{
3421	/* Pause first, then inform Main. */
3422	rc = VMR3SuspendNoSave(pVM);
3423	AssertRC(rc);
3424
3425	VMSetRuntimeError(pVM, true, "PAEmode",
3426	N_("The guest is trying to switch to the PAE mode which is currently disabled by default in VirtualBox. Experimental PAE support can be enabled using the -pae option with VBoxManage"));
3427	/* we must return VINF_SUCCESS here otherwise the recompiler will assert */
3428	return VINF_SUCCESS;
3429	}
3430	GCPhysCR3 = CPUMGetGuestCR3(pVM) & X86_CR3_PAE_PAGE_MASK;
3431	rc = PGM_GST_NAME_PAE(Enter)(pVM, GCPhysCR3);
3432	switch (pVM->pgm.s.enmShadowMode)
3433	{
3434	case PGMMODE_PAE:
3435	case PGMMODE_PAE_NX:
3436	rc2 = PGM_BTH_NAME_PAE_PAE(Enter)(pVM, GCPhysCR3);
3437	break;
3438	case PGMMODE_NESTED:
3439	rc2 = PGM_BTH_NAME_NESTED_PAE(Enter)(pVM, GCPhysCR3);
3440	break;
3441	case PGMMODE_EPT:
3442	rc2 = PGM_BTH_NAME_EPT_PAE(Enter)(pVM, GCPhysCR3);
3443	break;
3444	case PGMMODE_32_BIT:
3445	case PGMMODE_AMD64:
3446	case PGMMODE_AMD64_NX:
3447	AssertMsgFailed(("Should use PAE shadow mode!\n"));
3448	default: AssertFailed(); break;
3449	}
3450	break;
3451	}
3452
3453	#ifdef VBOX_WITH_64_BITS_GUESTS
3454	case PGMMODE_AMD64_NX:
3455	case PGMMODE_AMD64:
3456	GCPhysCR3 = CPUMGetGuestCR3(pVM) & 0xfffffffffffff000ULL; /** @todo define this mask! */
3457	rc = PGM_GST_NAME_AMD64(Enter)(pVM, GCPhysCR3);
3458	switch (pVM->pgm.s.enmShadowMode)
3459	{
3460	case PGMMODE_AMD64:
3461	case PGMMODE_AMD64_NX:
3462	rc2 = PGM_BTH_NAME_AMD64_AMD64(Enter)(pVM, GCPhysCR3);
3463	break;
3464	case PGMMODE_NESTED:
3465	rc2 = PGM_BTH_NAME_NESTED_AMD64(Enter)(pVM, GCPhysCR3);
3466	break;
3467	case PGMMODE_EPT:
3468	rc2 = PGM_BTH_NAME_EPT_AMD64(Enter)(pVM, GCPhysCR3);
3469	break;
3470	case PGMMODE_32_BIT:
3471	case PGMMODE_PAE:
3472	case PGMMODE_PAE_NX:
3473	AssertMsgFailed(("Should use AMD64 shadow mode!\n"));
3474	default: AssertFailed(); break;
3475	}
3476	break;
3477	#endif
3478
3479	default:
3480	AssertReleaseMsgFailed(("enmGuestMode=%d\n", enmGuestMode));
3481	rc = VERR_NOT_IMPLEMENTED;
3482	break;
3483	}
3484
3485	/* status codes. */
3486	AssertRC(rc);
3487	AssertRC(rc2);
3488	if (RT_SUCCESS(rc))
3489	{
3490	rc = rc2;
3491	if (RT_SUCCESS(rc)) /* no informational status codes. */
3492	rc = VINF_SUCCESS;
3493	}
3494
3495	/*
3496	* Notify SELM so it can update the TSSes with correct CR3s.
3497	*/
3498	SELMR3PagingModeChanged(pVM);
3499
3500	/* Notify HWACCM as well. */
3501	HWACCMR3PagingModeChanged(pVM, pVM->pgm.s.enmShadowMode, pVM->pgm.s.enmGuestMode);
3502	return rc;
3503	}
3504
3505
3506	/**
3507	* Dumps a PAE shadow page table.
3508	*
3509	* @returns VBox status code (VINF_SUCCESS).
3510	* @param pVM The VM handle.
3511	* @param pPT Pointer to the page table.
3512	* @param u64Address The virtual address of the page table starts.
3513	* @param fLongMode Set if this a long mode table; clear if it's a legacy mode table.
3514	* @param cMaxDepth The maxium depth.
3515	* @param pHlp Pointer to the output functions.
3516	*/
3517	static int pgmR3DumpHierarchyHCPaePT(PVM pVM, PX86PTPAE pPT, uint64_t u64Address, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
3518	{
3519	for (unsigned i = 0; i < RT_ELEMENTS(pPT->a); i++)
3520	{
3521	X86PTEPAE Pte = pPT->a[i];
3522	if (Pte.n.u1Present)
3523	{
3524	pHlp->pfnPrintf(pHlp,
3525	fLongMode /P R S A D G WT CD AT NX 4M a p ? /
3526	? "%016llx 3 \| P %c %c %c %c %c %s %s %s %s 4K %c%c%c %016llx\n"
3527	: "%08llx 2 \| P %c %c %c %c %c %s %s %s %s 4K %c%c%c %016llx\n",
3528	u64Address + ((uint64_t)i << X86_PT_PAE_SHIFT),
3529	Pte.n.u1Write ? 'W' : 'R',
3530	Pte.n.u1User ? 'U' : 'S',
3531	Pte.n.u1Accessed ? 'A' : '-',
3532	Pte.n.u1Dirty ? 'D' : '-',
3533	Pte.n.u1Global ? 'G' : '-',
3534	Pte.n.u1WriteThru ? "WT" : "--",
3535	Pte.n.u1CacheDisable? "CD" : "--",
3536	Pte.n.u1PAT ? "AT" : "--",
3537	Pte.n.u1NoExecute ? "NX" : "--",
3538	Pte.u & PGM_PTFLAGS_TRACK_DIRTY ? 'd' : '-',
3539	Pte.u & RT_BIT(10) ? '1' : '0',
3540	Pte.u & PGM_PTFLAGS_CSAM_VALIDATED? 'v' : '-',
3541	Pte.u & X86_PTE_PAE_PG_MASK);
3542	}
3543	}
3544	return VINF_SUCCESS;
3545	}
3546
3547
3548	/**
3549	* Dumps a PAE shadow page directory table.
3550	*
3551	* @returns VBox status code (VINF_SUCCESS).
3552	* @param pVM The VM handle.
3553	* @param HCPhys The physical address of the page directory table.
3554	* @param u64Address The virtual address of the page table starts.
3555	* @param cr4 The CR4, PSE is currently used.
3556	* @param fLongMode Set if this a long mode table; clear if it's a legacy mode table.
3557	* @param cMaxDepth The maxium depth.
3558	* @param pHlp Pointer to the output functions.
3559	*/
3560	static int pgmR3DumpHierarchyHCPaePD(PVM pVM, RTHCPHYS HCPhys, uint64_t u64Address, uint32_t cr4, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
3561	{
3562	PX86PDPAE pPD = (PX86PDPAE)MMPagePhys2Page(pVM, HCPhys);
3563	if (!pPD)
3564	{
3565	pHlp->pfnPrintf(pHlp, "%0*llx error! Page directory at HCPhys=%RHp was not found in the page pool!\n",
3566	fLongMode ? 16 : 8, u64Address, HCPhys);
3567	return VERR_INVALID_PARAMETER;
3568	}
3569	const bool fBigPagesSupported = fLongMode \|\| !!(cr4 & X86_CR4_PSE);
3570
3571	int rc = VINF_SUCCESS;
3572	for (unsigned i = 0; i < RT_ELEMENTS(pPD->a); i++)
3573	{
3574	X86PDEPAE Pde = pPD->a[i];
3575	if (Pde.n.u1Present)
3576	{
3577	if (fBigPagesSupported && Pde.b.u1Size)
3578	pHlp->pfnPrintf(pHlp,
3579	fLongMode /P R S A D G WT CD AT NX 4M a p ? /
3580	? "%016llx 2 \| P %c %c %c %c %c %s %s %s %s 4M %c%c%c %016llx\n"
3581	: "%08llx 1 \| P %c %c %c %c %c %s %s %s %s 4M %c%c%c %016llx\n",
3582	u64Address + ((uint64_t)i << X86_PD_PAE_SHIFT),
3583	Pde.b.u1Write ? 'W' : 'R',
3584	Pde.b.u1User ? 'U' : 'S',
3585	Pde.b.u1Accessed ? 'A' : '-',
3586	Pde.b.u1Dirty ? 'D' : '-',
3587	Pde.b.u1Global ? 'G' : '-',
3588	Pde.b.u1WriteThru ? "WT" : "--",
3589	Pde.b.u1CacheDisable? "CD" : "--",
3590	Pde.b.u1PAT ? "AT" : "--",
3591	Pde.b.u1NoExecute ? "NX" : "--",
3592	Pde.u & RT_BIT_64(9) ? '1' : '0',
3593	Pde.u & PGM_PDFLAGS_MAPPING ? 'm' : '-',
3594	Pde.u & PGM_PDFLAGS_TRACK_DIRTY ? 'd' : '-',
3595	Pde.u & X86_PDE_PAE_PG_MASK);
3596	else
3597	{
3598	pHlp->pfnPrintf(pHlp,
3599	fLongMode /P R S A D G WT CD AT NX 4M a p ? /
3600	? "%016llx 2 \| P %c %c %c %c %c %s %s .. %s 4K %c%c%c %016llx\n"
3601	: "%08llx 1 \| P %c %c %c %c %c %s %s .. %s 4K %c%c%c %016llx\n",
3602	u64Address + ((uint64_t)i << X86_PD_PAE_SHIFT),
3603	Pde.n.u1Write ? 'W' : 'R',
3604	Pde.n.u1User ? 'U' : 'S',
3605	Pde.n.u1Accessed ? 'A' : '-',
3606	Pde.n.u1Reserved0 ? '?' : '.', /* ignored */
3607	Pde.n.u1Reserved1 ? '?' : '.', /* ignored */
3608	Pde.n.u1WriteThru ? "WT" : "--",
3609	Pde.n.u1CacheDisable? "CD" : "--",
3610	Pde.n.u1NoExecute ? "NX" : "--",
3611	Pde.u & RT_BIT_64(9) ? '1' : '0',
3612	Pde.u & PGM_PDFLAGS_MAPPING ? 'm' : '-',
3613	Pde.u & PGM_PDFLAGS_TRACK_DIRTY ? 'd' : '-',
3614	Pde.u & X86_PDE_PAE_PG_MASK);
3615	if (cMaxDepth >= 1)
3616	{
3617	/** @todo what about using the page pool for mapping PTs? */
3618	uint64_t u64AddressPT = u64Address + ((uint64_t)i << X86_PD_PAE_SHIFT);
3619	RTHCPHYS HCPhysPT = Pde.u & X86_PDE_PAE_PG_MASK;
3620	PX86PTPAE pPT = NULL;
3621	if (!(Pde.u & PGM_PDFLAGS_MAPPING))
3622	pPT = (PX86PTPAE)MMPagePhys2Page(pVM, HCPhysPT);
3623	else
3624	{
3625	for (PPGMMAPPING pMap = pVM->pgm.s.pMappingsR3; pMap; pMap = pMap->pNextR3)
3626	{
3627	uint64_t off = u64AddressPT - pMap->GCPtr;
3628	if (off < pMap->cb)
3629	{
3630	const int iPDE = (uint32_t)(off >> X86_PD_SHIFT);
3631	const int iSub = (int)((off >> X86_PD_PAE_SHIFT) & 1); /* MSC is a pain sometimes */
3632	if ((iSub ? pMap->aPTs[iPDE].HCPhysPaePT1 : pMap->aPTs[iPDE].HCPhysPaePT0) != HCPhysPT)
3633	pHlp->pfnPrintf(pHlp, "%0*llx error! Mapping error! PT %d has HCPhysPT=%RHp not %RHp is in the PD.\n",
3634	fLongMode ? 16 : 8, u64AddressPT, iPDE,
3635	iSub ? pMap->aPTs[iPDE].HCPhysPaePT1 : pMap->aPTs[iPDE].HCPhysPaePT0, HCPhysPT);
3636	pPT = &pMap->aPTs[iPDE].paPaePTsR3[iSub];
3637	}
3638	}
3639	}
3640	int rc2 = VERR_INVALID_PARAMETER;
3641	if (pPT)
3642	rc2 = pgmR3DumpHierarchyHCPaePT(pVM, pPT, u64AddressPT, fLongMode, cMaxDepth - 1, pHlp);
3643	else
3644	pHlp->pfnPrintf(pHlp, "%0*llx error! Page table at HCPhys=%RHp was not found in the page pool!\n",
3645	fLongMode ? 16 : 8, u64AddressPT, HCPhysPT);
3646	if (rc2 < rc && RT_SUCCESS(rc))
3647	rc = rc2;
3648	}
3649	}
3650	}
3651	}
3652	return rc;
3653	}
3654
3655
3656	/**
3657	* Dumps a PAE shadow page directory pointer table.
3658	*
3659	* @returns VBox status code (VINF_SUCCESS).
3660	* @param pVM The VM handle.
3661	* @param HCPhys The physical address of the page directory pointer table.
3662	* @param u64Address The virtual address of the page table starts.
3663	* @param cr4 The CR4, PSE is currently used.
3664	* @param fLongMode Set if this a long mode table; clear if it's a legacy mode table.
3665	* @param cMaxDepth The maxium depth.
3666	* @param pHlp Pointer to the output functions.
3667	*/
3668	static int pgmR3DumpHierarchyHCPaePDPT(PVM pVM, RTHCPHYS HCPhys, uint64_t u64Address, uint32_t cr4, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
3669	{
3670	PX86PDPT pPDPT = (PX86PDPT)MMPagePhys2Page(pVM, HCPhys);
3671	if (!pPDPT)
3672	{
3673	pHlp->pfnPrintf(pHlp, "%0*llx error! Page directory pointer table at HCPhys=%RHp was not found in the page pool!\n",
3674	fLongMode ? 16 : 8, u64Address, HCPhys);
3675	return VERR_INVALID_PARAMETER;
3676	}
3677
3678	int rc = VINF_SUCCESS;
3679	const unsigned c = fLongMode ? RT_ELEMENTS(pPDPT->a) : X86_PG_PAE_PDPE_ENTRIES;
3680	for (unsigned i = 0; i < c; i++)
3681	{
3682	X86PDPE Pdpe = pPDPT->a[i];
3683	if (Pdpe.n.u1Present)
3684	{
3685	if (fLongMode)
3686	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a p ? /
3687	"%016llx 1 \| P %c %c %c %c %c %s %s %s %s .. %c%c%c %016llx\n",
3688	u64Address + ((uint64_t)i << X86_PDPT_SHIFT),
3689	Pdpe.lm.u1Write ? 'W' : 'R',
3690	Pdpe.lm.u1User ? 'U' : 'S',
3691	Pdpe.lm.u1Accessed ? 'A' : '-',
3692	Pdpe.lm.u3Reserved & 1? '?' : '.', /* ignored */
3693	Pdpe.lm.u3Reserved & 4? '!' : '.', /* mbz */
3694	Pdpe.lm.u1WriteThru ? "WT" : "--",
3695	Pdpe.lm.u1CacheDisable? "CD" : "--",
3696	Pdpe.lm.u3Reserved & 2? "!" : "..",/* mbz */
3697	Pdpe.lm.u1NoExecute ? "NX" : "--",
3698	Pdpe.u & RT_BIT(9) ? '1' : '0',
3699	Pdpe.u & PGM_PLXFLAGS_PERMANENT ? 'p' : '-',
3700	Pdpe.u & RT_BIT(11) ? '1' : '0',
3701	Pdpe.u & X86_PDPE_PG_MASK);
3702	else
3703	pHlp->pfnPrintf(pHlp, /P G WT CD AT NX 4M a p ? /
3704	"%08x 0 \| P %c %s %s %s %s .. %c%c%c %016llx\n",
3705	i << X86_PDPT_SHIFT,
3706	Pdpe.n.u4Reserved & 1? '!' : '.', /* mbz */
3707	Pdpe.n.u4Reserved & 4? '!' : '.', /* mbz */
3708	Pdpe.n.u1WriteThru ? "WT" : "--",
3709	Pdpe.n.u1CacheDisable? "CD" : "--",
3710	Pdpe.n.u4Reserved & 2? "!" : "..",/* mbz */
3711	Pdpe.u & RT_BIT(9) ? '1' : '0',
3712	Pdpe.u & PGM_PLXFLAGS_PERMANENT ? 'p' : '-',
3713	Pdpe.u & RT_BIT(11) ? '1' : '0',
3714	Pdpe.u & X86_PDPE_PG_MASK);
3715	if (cMaxDepth >= 1)
3716	{
3717	int rc2 = pgmR3DumpHierarchyHCPaePD(pVM, Pdpe.u & X86_PDPE_PG_MASK, u64Address + ((uint64_t)i << X86_PDPT_SHIFT),
3718	cr4, fLongMode, cMaxDepth - 1, pHlp);
3719	if (rc2 < rc && RT_SUCCESS(rc))
3720	rc = rc2;
3721	}
3722	}
3723	}
3724	return rc;
3725	}
3726
3727
3728	/**
3729	* Dumps a 32-bit shadow page table.
3730	*
3731	* @returns VBox status code (VINF_SUCCESS).
3732	* @param pVM The VM handle.
3733	* @param HCPhys The physical address of the table.
3734	* @param cr4 The CR4, PSE is currently used.
3735	* @param cMaxDepth The maxium depth.
3736	* @param pHlp Pointer to the output functions.
3737	*/
3738	static int pgmR3DumpHierarchyHcPaePML4(PVM pVM, RTHCPHYS HCPhys, uint32_t cr4, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
3739	{
3740	PX86PML4 pPML4 = (PX86PML4)MMPagePhys2Page(pVM, HCPhys);
3741	if (!pPML4)
3742	{
3743	pHlp->pfnPrintf(pHlp, "Page map level 4 at HCPhys=%RHp was not found in the page pool!\n", HCPhys);
3744	return VERR_INVALID_PARAMETER;
3745	}
3746
3747	int rc = VINF_SUCCESS;
3748	for (unsigned i = 0; i < RT_ELEMENTS(pPML4->a); i++)
3749	{
3750	X86PML4E Pml4e = pPML4->a[i];
3751	if (Pml4e.n.u1Present)
3752	{
3753	uint64_t u64Address = ((uint64_t)i << X86_PML4_SHIFT) \| (((uint64_t)i >> (X86_PML4_SHIFT - X86_PDPT_SHIFT - 1)) * 0xffff000000000000ULL);
3754	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a p ? /
3755	"%016llx 0 \| P %c %c %c %c %c %s %s %s %s .. %c%c%c %016llx\n",
3756	u64Address,
3757	Pml4e.n.u1Write ? 'W' : 'R',
3758	Pml4e.n.u1User ? 'U' : 'S',
3759	Pml4e.n.u1Accessed ? 'A' : '-',
3760	Pml4e.n.u3Reserved & 1? '?' : '.', /* ignored */
3761	Pml4e.n.u3Reserved & 4? '!' : '.', /* mbz */
3762	Pml4e.n.u1WriteThru ? "WT" : "--",
3763	Pml4e.n.u1CacheDisable? "CD" : "--",
3764	Pml4e.n.u3Reserved & 2? "!" : "..",/* mbz */
3765	Pml4e.n.u1NoExecute ? "NX" : "--",
3766	Pml4e.u & RT_BIT(9) ? '1' : '0',
3767	Pml4e.u & PGM_PLXFLAGS_PERMANENT ? 'p' : '-',
3768	Pml4e.u & RT_BIT(11) ? '1' : '0',
3769	Pml4e.u & X86_PML4E_PG_MASK);
3770
3771	if (cMaxDepth >= 1)
3772	{
3773	int rc2 = pgmR3DumpHierarchyHCPaePDPT(pVM, Pml4e.u & X86_PML4E_PG_MASK, u64Address, cr4, true, cMaxDepth - 1, pHlp);
3774	if (rc2 < rc && RT_SUCCESS(rc))
3775	rc = rc2;
3776	}
3777	}
3778	}
3779	return rc;
3780	}
3781
3782
3783	/**
3784	* Dumps a 32-bit shadow page table.
3785	*
3786	* @returns VBox status code (VINF_SUCCESS).
3787	* @param pVM The VM handle.
3788	* @param pPT Pointer to the page table.
3789	* @param u32Address The virtual address this table starts at.
3790	* @param pHlp Pointer to the output functions.
3791	*/
3792	int pgmR3DumpHierarchyHC32BitPT(PVM pVM, PX86PT pPT, uint32_t u32Address, PCDBGFINFOHLP pHlp)
3793	{
3794	for (unsigned i = 0; i < RT_ELEMENTS(pPT->a); i++)
3795	{
3796	X86PTE Pte = pPT->a[i];
3797	if (Pte.n.u1Present)
3798	{
3799	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a m d /
3800	"%08x 1 \| P %c %c %c %c %c %s %s %s .. 4K %c%c%c %08x\n",
3801	u32Address + (i << X86_PT_SHIFT),
3802	Pte.n.u1Write ? 'W' : 'R',
3803	Pte.n.u1User ? 'U' : 'S',
3804	Pte.n.u1Accessed ? 'A' : '-',
3805	Pte.n.u1Dirty ? 'D' : '-',
3806	Pte.n.u1Global ? 'G' : '-',
3807	Pte.n.u1WriteThru ? "WT" : "--",
3808	Pte.n.u1CacheDisable? "CD" : "--",
3809	Pte.n.u1PAT ? "AT" : "--",
3810	Pte.u & PGM_PTFLAGS_TRACK_DIRTY ? 'd' : '-',
3811	Pte.u & RT_BIT(10) ? '1' : '0',
3812	Pte.u & PGM_PTFLAGS_CSAM_VALIDATED ? 'v' : '-',
3813	Pte.u & X86_PDE_PG_MASK);
3814	}
3815	}
3816	return VINF_SUCCESS;
3817	}
3818
3819
3820	/**
3821	* Dumps a 32-bit shadow page directory and page tables.
3822	*
3823	* @returns VBox status code (VINF_SUCCESS).
3824	* @param pVM The VM handle.
3825	* @param cr3 The root of the hierarchy.
3826	* @param cr4 The CR4, PSE is currently used.
3827	* @param cMaxDepth How deep into the hierarchy the dumper should go.
3828	* @param pHlp Pointer to the output functions.
3829	*/
3830	int pgmR3DumpHierarchyHC32BitPD(PVM pVM, uint32_t cr3, uint32_t cr4, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
3831	{
3832	PX86PD pPD = (PX86PD)MMPagePhys2Page(pVM, cr3 & X86_CR3_PAGE_MASK);
3833	if (!pPD)
3834	{
3835	pHlp->pfnPrintf(pHlp, "Page directory at %#x was not found in the page pool!\n", cr3 & X86_CR3_PAGE_MASK);
3836	return VERR_INVALID_PARAMETER;
3837	}
3838
3839	int rc = VINF_SUCCESS;
3840	for (unsigned i = 0; i < RT_ELEMENTS(pPD->a); i++)
3841	{
3842	X86PDE Pde = pPD->a[i];
3843	if (Pde.n.u1Present)
3844	{
3845	const uint32_t u32Address = i << X86_PD_SHIFT;
3846	if ((cr4 & X86_CR4_PSE) && Pde.b.u1Size)
3847	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a m d /
3848	"%08x 0 \| P %c %c %c %c %c %s %s %s .. 4M %c%c%c %08x\n",
3849	u32Address,
3850	Pde.b.u1Write ? 'W' : 'R',
3851	Pde.b.u1User ? 'U' : 'S',
3852	Pde.b.u1Accessed ? 'A' : '-',
3853	Pde.b.u1Dirty ? 'D' : '-',
3854	Pde.b.u1Global ? 'G' : '-',
3855	Pde.b.u1WriteThru ? "WT" : "--",
3856	Pde.b.u1CacheDisable? "CD" : "--",
3857	Pde.b.u1PAT ? "AT" : "--",
3858	Pde.u & RT_BIT_64(9) ? '1' : '0',
3859	Pde.u & PGM_PDFLAGS_MAPPING ? 'm' : '-',
3860	Pde.u & PGM_PDFLAGS_TRACK_DIRTY ? 'd' : '-',
3861	Pde.u & X86_PDE4M_PG_MASK);
3862	else
3863	{
3864	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a m d /
3865	"%08x 0 \| P %c %c %c %c %c %s %s .. .. 4K %c%c%c %08x\n",
3866	u32Address,
3867	Pde.n.u1Write ? 'W' : 'R',
3868	Pde.n.u1User ? 'U' : 'S',
3869	Pde.n.u1Accessed ? 'A' : '-',
3870	Pde.n.u1Reserved0 ? '?' : '.', /* ignored */
3871	Pde.n.u1Reserved1 ? '?' : '.', /* ignored */
3872	Pde.n.u1WriteThru ? "WT" : "--",
3873	Pde.n.u1CacheDisable? "CD" : "--",
3874	Pde.u & RT_BIT_64(9) ? '1' : '0',
3875	Pde.u & PGM_PDFLAGS_MAPPING ? 'm' : '-',
3876	Pde.u & PGM_PDFLAGS_TRACK_DIRTY ? 'd' : '-',
3877	Pde.u & X86_PDE_PG_MASK);
3878	if (cMaxDepth >= 1)
3879	{
3880	/** @todo what about using the page pool for mapping PTs? */
3881	RTHCPHYS HCPhys = Pde.u & X86_PDE_PG_MASK;
3882	PX86PT pPT = NULL;
3883	if (!(Pde.u & PGM_PDFLAGS_MAPPING))
3884	pPT = (PX86PT)MMPagePhys2Page(pVM, HCPhys);
3885	else
3886	{
3887	for (PPGMMAPPING pMap = pVM->pgm.s.pMappingsR3; pMap; pMap = pMap->pNextR3)
3888	if (u32Address - pMap->GCPtr < pMap->cb)
3889	{
3890	int iPDE = (u32Address - pMap->GCPtr) >> X86_PD_SHIFT;
3891	if (pMap->aPTs[iPDE].HCPhysPT != HCPhys)
3892	pHlp->pfnPrintf(pHlp, "%08x error! Mapping error! PT %d has HCPhysPT=%RHp not %RHp is in the PD.\n",
3893	u32Address, iPDE, pMap->aPTs[iPDE].HCPhysPT, HCPhys);
3894	pPT = pMap->aPTs[iPDE].pPTR3;
3895	}
3896	}
3897	int rc2 = VERR_INVALID_PARAMETER;
3898	if (pPT)
3899	rc2 = pgmR3DumpHierarchyHC32BitPT(pVM, pPT, u32Address, pHlp);
3900	else
3901	pHlp->pfnPrintf(pHlp, "%08x error! Page table at %#x was not found in the page pool!\n", u32Address, HCPhys);
3902	if (rc2 < rc && RT_SUCCESS(rc))
3903	rc = rc2;
3904	}
3905	}
3906	}
3907	}
3908
3909	return rc;
3910	}
3911
3912
3913	/**
3914	* Dumps a 32-bit shadow page table.
3915	*
3916	* @returns VBox status code (VINF_SUCCESS).
3917	* @param pVM The VM handle.
3918	* @param pPT Pointer to the page table.
3919	* @param u32Address The virtual address this table starts at.
3920	* @param PhysSearch Address to search for.
3921	*/
3922	int pgmR3DumpHierarchyGC32BitPT(PVM pVM, PX86PT pPT, uint32_t u32Address, RTGCPHYS PhysSearch)
3923	{
3924	for (unsigned i = 0; i < RT_ELEMENTS(pPT->a); i++)
3925	{
3926	X86PTE Pte = pPT->a[i];
3927	if (Pte.n.u1Present)
3928	{
3929	Log(( /P R S A D G WT CD AT NX 4M a m d /
3930	"%08x 1 \| P %c %c %c %c %c %s %s %s .. 4K %c%c%c %08x\n",
3931	u32Address + (i << X86_PT_SHIFT),
3932	Pte.n.u1Write ? 'W' : 'R',
3933	Pte.n.u1User ? 'U' : 'S',
3934	Pte.n.u1Accessed ? 'A' : '-',
3935	Pte.n.u1Dirty ? 'D' : '-',
3936	Pte.n.u1Global ? 'G' : '-',
3937	Pte.n.u1WriteThru ? "WT" : "--",
3938	Pte.n.u1CacheDisable? "CD" : "--",
3939	Pte.n.u1PAT ? "AT" : "--",
3940	Pte.u & PGM_PTFLAGS_TRACK_DIRTY ? 'd' : '-',
3941	Pte.u & RT_BIT(10) ? '1' : '0',
3942	Pte.u & PGM_PTFLAGS_CSAM_VALIDATED ? 'v' : '-',
3943	Pte.u & X86_PDE_PG_MASK));
3944
3945	if ((Pte.u & X86_PDE_PG_MASK) == PhysSearch)
3946	{
3947	uint64_t fPageShw = 0;
3948	RTHCPHYS pPhysHC = 0;
3949
3950	PGMShwGetPage(pVM, (RTGCPTR)(u32Address + (i << X86_PT_SHIFT)), &fPageShw, &pPhysHC);
3951	Log(("Found %RGp at %RGv -> flags=%llx\n", PhysSearch, (RTGCPTR)(u32Address + (i << X86_PT_SHIFT)), fPageShw));
3952	}
3953	}
3954	}
3955	return VINF_SUCCESS;
3956	}
3957
3958
3959	/**
3960	* Dumps a 32-bit guest page directory and page tables.
3961	*
3962	* @returns VBox status code (VINF_SUCCESS).
3963	* @param pVM The VM handle.
3964	* @param cr3 The root of the hierarchy.
3965	* @param cr4 The CR4, PSE is currently used.
3966	* @param PhysSearch Address to search for.
3967	*/
3968	VMMR3DECL(int) PGMR3DumpHierarchyGC(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCPHYS PhysSearch)
3969	{
3970	bool fLongMode = false;
3971	const unsigned cch = fLongMode ? 16 : 8; NOREF(cch);
3972	PX86PD pPD = 0;
3973
3974	int rc = PGM_GCPHYS_2_PTR(pVM, cr3 & X86_CR3_PAGE_MASK, &pPD);
3975	if (RT_FAILURE(rc) \|\| !pPD)
3976	{
3977	Log(("Page directory at %#x was not found in the page pool!\n", cr3 & X86_CR3_PAGE_MASK));
3978	return VERR_INVALID_PARAMETER;
3979	}
3980
3981	Log(("cr3=%08x cr4=%08x%s\n"
3982	"%-*s P - Present\n"
3983	"%-*s \| R/W - Read (0) / Write (1)\n"
3984	"%-*s \| \| U/S - User (1) / Supervisor (0)\n"
3985	"%-*s \| \| \| A - Accessed\n"
3986	"%-*s \| \| \| \| D - Dirty\n"
3987	"%-*s \| \| \| \| \| G - Global\n"
3988	"%-*s \| \| \| \| \| \| WT - Write thru\n"
3989	"%-*s \| \| \| \| \| \| \| CD - Cache disable\n"
3990	"%-*s \| \| \| \| \| \| \| \| AT - Attribute table (PAT)\n"
3991	"%-*s \| \| \| \| \| \| \| \| \| NX - No execute (K8)\n"
3992	"%-*s \| \| \| \| \| \| \| \| \| \| 4K/4M/2M - Page size.\n"
3993	"%-*s \| \| \| \| \| \| \| \| \| \| \| AVL - a=allocated; m=mapping; d=track dirty;\n"
3994	"%-*s \| \| \| \| \| \| \| \| \| \| \| \| p=permanent; v=validated;\n"
3995	"%-*s Level \| \| \| \| \| \| \| \| \| \| \| \| Page\n"
3996	/* xxxx n **** P R S A D G WT CD AT NX 4M AVL xxxxxxxxxxxxx
3997	- W U - - - -- -- -- -- -- 010 */
3998	, cr3, cr4, fLongMode ? " Long Mode" : "",
3999	cch, "", cch, "", cch, "", cch, "", cch, "", cch, "", cch, "",
4000	cch, "", cch, "", cch, "", cch, "", cch, "", cch, "", cch, "Address"));
4001
4002	for (unsigned i = 0; i < RT_ELEMENTS(pPD->a); i++)
4003	{
4004	X86PDE Pde = pPD->a[i];
4005	if (Pde.n.u1Present)
4006	{
4007	const uint32_t u32Address = i << X86_PD_SHIFT;
4008
4009	if ((cr4 & X86_CR4_PSE) && Pde.b.u1Size)
4010	Log(( /P R S A D G WT CD AT NX 4M a m d /
4011	"%08x 0 \| P %c %c %c %c %c %s %s %s .. 4M %c%c%c %08x\n",
4012	u32Address,
4013	Pde.b.u1Write ? 'W' : 'R',
4014	Pde.b.u1User ? 'U' : 'S',
4015	Pde.b.u1Accessed ? 'A' : '-',
4016	Pde.b.u1Dirty ? 'D' : '-',
4017	Pde.b.u1Global ? 'G' : '-',
4018	Pde.b.u1WriteThru ? "WT" : "--",
4019	Pde.b.u1CacheDisable? "CD" : "--",
4020	Pde.b.u1PAT ? "AT" : "--",
4021	Pde.u & RT_BIT(9) ? '1' : '0',
4022	Pde.u & RT_BIT(10) ? '1' : '0',
4023	Pde.u & RT_BIT(11) ? '1' : '0',
4024	pgmGstGet4MBPhysPage(&pVM->pgm.s, Pde)));
4025	/** @todo PhysSearch */
4026	else
4027	{
4028	Log(( /P R S A D G WT CD AT NX 4M a m d /
4029	"%08x 0 \| P %c %c %c %c %c %s %s .. .. 4K %c%c%c %08x\n",
4030	u32Address,
4031	Pde.n.u1Write ? 'W' : 'R',
4032	Pde.n.u1User ? 'U' : 'S',
4033	Pde.n.u1Accessed ? 'A' : '-',
4034	Pde.n.u1Reserved0 ? '?' : '.', /* ignored */
4035	Pde.n.u1Reserved1 ? '?' : '.', /* ignored */
4036	Pde.n.u1WriteThru ? "WT" : "--",
4037	Pde.n.u1CacheDisable? "CD" : "--",
4038	Pde.u & RT_BIT(9) ? '1' : '0',
4039	Pde.u & RT_BIT(10) ? '1' : '0',
4040	Pde.u & RT_BIT(11) ? '1' : '0',
4041	Pde.u & X86_PDE_PG_MASK));
4042	////if (cMaxDepth >= 1)
4043	{
4044	/** @todo what about using the page pool for mapping PTs? */
4045	RTGCPHYS GCPhys = Pde.u & X86_PDE_PG_MASK;
4046	PX86PT pPT = NULL;
4047
4048	rc = PGM_GCPHYS_2_PTR(pVM, GCPhys, &pPT);
4049
4050	int rc2 = VERR_INVALID_PARAMETER;
4051	if (pPT)
4052	rc2 = pgmR3DumpHierarchyGC32BitPT(pVM, pPT, u32Address, PhysSearch);
4053	else
4054	Log(("%08x error! Page table at %#x was not found in the page pool!\n", u32Address, GCPhys));
4055	if (rc2 < rc && RT_SUCCESS(rc))
4056	rc = rc2;
4057	}
4058	}
4059	}
4060	}
4061
4062	return rc;
4063	}
4064
4065
4066	/**
4067	* Dumps a page table hierarchy use only physical addresses and cr4/lm flags.
4068	*
4069	* @returns VBox status code (VINF_SUCCESS).
4070	* @param pVM The VM handle.
4071	* @param cr3 The root of the hierarchy.
4072	* @param cr4 The cr4, only PAE and PSE is currently used.
4073	* @param fLongMode Set if long mode, false if not long mode.
4074	* @param cMaxDepth Number of levels to dump.
4075	* @param pHlp Pointer to the output functions.
4076	*/
4077	VMMR3DECL(int) PGMR3DumpHierarchyHC(PVM pVM, uint64_t cr3, uint64_t cr4, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
4078	{
4079	if (!pHlp)
4080	pHlp = DBGFR3InfoLogHlp();
4081	if (!cMaxDepth)
4082	return VINF_SUCCESS;
4083	const unsigned cch = fLongMode ? 16 : 8;
4084	pHlp->pfnPrintf(pHlp,
4085	"cr3=%08x cr4=%08x%s\n"
4086	"%-*s P - Present\n"
4087	"%-*s \| R/W - Read (0) / Write (1)\n"
4088	"%-*s \| \| U/S - User (1) / Supervisor (0)\n"
4089	"%-*s \| \| \| A - Accessed\n"
4090	"%-*s \| \| \| \| D - Dirty\n"
4091	"%-*s \| \| \| \| \| G - Global\n"
4092	"%-*s \| \| \| \| \| \| WT - Write thru\n"
4093	"%-*s \| \| \| \| \| \| \| CD - Cache disable\n"
4094	"%-*s \| \| \| \| \| \| \| \| AT - Attribute table (PAT)\n"
4095	"%-*s \| \| \| \| \| \| \| \| \| NX - No execute (K8)\n"
4096	"%-*s \| \| \| \| \| \| \| \| \| \| 4K/4M/2M - Page size.\n"
4097	"%-*s \| \| \| \| \| \| \| \| \| \| \| AVL - a=allocated; m=mapping; d=track dirty;\n"
4098	"%-*s \| \| \| \| \| \| \| \| \| \| \| \| p=permanent; v=validated;\n"
4099	"%-*s Level \| \| \| \| \| \| \| \| \| \| \| \| Page\n"
4100	/* xxxx n **** P R S A D G WT CD AT NX 4M AVL xxxxxxxxxxxxx
4101	- W U - - - -- -- -- -- -- 010 */
4102	, cr3, cr4, fLongMode ? " Long Mode" : "",
4103	cch, "", cch, "", cch, "", cch, "", cch, "", cch, "", cch, "",
4104	cch, "", cch, "", cch, "", cch, "", cch, "", cch, "", cch, "Address");
4105	if (cr4 & X86_CR4_PAE)
4106	{
4107	if (fLongMode)
4108	return pgmR3DumpHierarchyHcPaePML4(pVM, cr3 & X86_CR3_PAGE_MASK, cr4, cMaxDepth, pHlp);
4109	return pgmR3DumpHierarchyHCPaePDPT(pVM, cr3 & X86_CR3_PAE_PAGE_MASK, 0, cr4, false, cMaxDepth, pHlp);
4110	}
4111	return pgmR3DumpHierarchyHC32BitPD(pVM, cr3 & X86_CR3_PAGE_MASK, cr4, cMaxDepth, pHlp);
4112	}
4113
4114	#ifdef VBOX_WITH_DEBUGGER
4115
4116	/**
4117	* The '.pgmram' command.
4118	*
4119	* @returns VBox status.
4120	* @param pCmd Pointer to the command descriptor (as registered).
4121	* @param pCmdHlp Pointer to command helper functions.
4122	* @param pVM Pointer to the current VM (if any).
4123	* @param paArgs Pointer to (readonly) array of arguments.
4124	* @param cArgs Number of arguments in the array.
4125	*/
4126	static DECLCALLBACK(int) pgmR3CmdRam(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4127	{
4128	/*
4129	* Validate input.
4130	*/
4131	if (!pVM)
4132	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4133	if (!pVM->pgm.s.pRamRangesRC)
4134	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Sorry, no Ram is registered.\n");
4135
4136	/*
4137	* Dump the ranges.
4138	*/
4139	int rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL, "From - To (incl) pvHC\n");
4140	PPGMRAMRANGE pRam;
4141	for (pRam = pVM->pgm.s.pRamRangesR3; pRam; pRam = pRam->pNextR3)
4142	{
4143	rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL,
4144	"%RGp - %RGp %p\n",
4145	pRam->GCPhys, pRam->GCPhysLast, pRam->pvR3);
4146	if (RT_FAILURE(rc))
4147	return rc;
4148	}
4149
4150	return VINF_SUCCESS;
4151	}
4152
4153
4154	/**
4155	* The '.pgmmap' command.
4156	*
4157	* @returns VBox status.
4158	* @param pCmd Pointer to the command descriptor (as registered).
4159	* @param pCmdHlp Pointer to command helper functions.
4160	* @param pVM Pointer to the current VM (if any).
4161	* @param paArgs Pointer to (readonly) array of arguments.
4162	* @param cArgs Number of arguments in the array.
4163	*/
4164	static DECLCALLBACK(int) pgmR3CmdMap(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4165	{
4166	/*
4167	* Validate input.
4168	*/
4169	if (!pVM)
4170	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4171	if (!pVM->pgm.s.pMappingsR3)
4172	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Sorry, no mappings are registered.\n");
4173
4174	/*
4175	* Print message about the fixedness of the mappings.
4176	*/
4177	int rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL, pVM->pgm.s.fMappingsFixed ? "The mappings are FIXED.\n" : "The mappings are FLOATING.\n");
4178	if (RT_FAILURE(rc))
4179	return rc;
4180
4181	/*
4182	* Dump the ranges.
4183	*/
4184	PPGMMAPPING pCur;
4185	for (pCur = pVM->pgm.s.pMappingsR3; pCur; pCur = pCur->pNextR3)
4186	{
4187	rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL,
4188	"%08x - %08x %s\n",
4189	pCur->GCPtr, pCur->GCPtrLast, pCur->pszDesc);
4190	if (RT_FAILURE(rc))
4191	return rc;
4192	}
4193
4194	return VINF_SUCCESS;
4195	}
4196
4197
4198	/**
4199	* The '.pgmsync' command.
4200	*
4201	* @returns VBox status.
4202	* @param pCmd Pointer to the command descriptor (as registered).
4203	* @param pCmdHlp Pointer to command helper functions.
4204	* @param pVM Pointer to the current VM (if any).
4205	* @param paArgs Pointer to (readonly) array of arguments.
4206	* @param cArgs Number of arguments in the array.
4207	*/
4208	static DECLCALLBACK(int) pgmR3CmdSync(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4209	{
4210	/*
4211	* Validate input.
4212	*/
4213	if (!pVM)
4214	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4215
4216	/*
4217	* Force page directory sync.
4218	*/
4219	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
4220
4221	int rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Forcing page directory sync.\n");
4222	if (RT_FAILURE(rc))
4223	return rc;
4224
4225	return VINF_SUCCESS;
4226	}
4227
4228
4229	#ifdef VBOX_STRICT
4230	/**
4231	* The '.pgmassertcr3' command.
4232	*
4233	* @returns VBox status.
4234	* @param pCmd Pointer to the command descriptor (as registered).
4235	* @param pCmdHlp Pointer to command helper functions.
4236	* @param pVM Pointer to the current VM (if any).
4237	* @param paArgs Pointer to (readonly) array of arguments.
4238	* @param cArgs Number of arguments in the array.
4239	*/
4240	static DECLCALLBACK(int) pgmR3CmdAssertCR3(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4241	{
4242	/*
4243	* Validate input.
4244	*/
4245	if (!pVM)
4246	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4247
4248	int rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Checking shadow CR3 page tables for consistency.\n");
4249	if (RT_FAILURE(rc))
4250	return rc;
4251
4252	PGMAssertCR3(pVM, CPUMGetGuestCR3(pVM), CPUMGetGuestCR4(pVM));
4253
4254	return VINF_SUCCESS;
4255	}
4256	#endif /* VBOX_STRICT */
4257
4258
4259	/**
4260	* The '.pgmsyncalways' command.
4261	*
4262	* @returns VBox status.
4263	* @param pCmd Pointer to the command descriptor (as registered).
4264	* @param pCmdHlp Pointer to command helper functions.
4265	* @param pVM Pointer to the current VM (if any).
4266	* @param paArgs Pointer to (readonly) array of arguments.
4267	* @param cArgs Number of arguments in the array.
4268	*/
4269	static DECLCALLBACK(int) pgmR3CmdSyncAlways(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4270	{
4271	/*
4272	* Validate input.
4273	*/
4274	if (!pVM)
4275	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4276
4277	/*
4278	* Force page directory sync.
4279	*/
4280	if (pVM->pgm.s.fSyncFlags & PGM_SYNC_ALWAYS)
4281	{
4282	ASMAtomicAndU32(&pVM->pgm.s.fSyncFlags, ~PGM_SYNC_ALWAYS);
4283	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Disabled permanent forced page directory syncing.\n");
4284	}
4285	else
4286	{
4287	ASMAtomicOrU32(&pVM->pgm.s.fSyncFlags, PGM_SYNC_ALWAYS);
4288	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
4289	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Enabled permanent forced page directory syncing.\n");
4290	}
4291	}
4292
4293	#endif /* VBOX_WITH_DEBUGGER */
4294
4295	/**
4296	* pvUser argument of the pgmR3CheckIntegrity*Node callbacks.
4297	*/
4298	typedef struct PGMCHECKINTARGS
4299	{
4300	bool fLeftToRight; /*< true: left-to-right; false: right-to-left. /
4301	PPGMPHYSHANDLER pPrevPhys;
4302	PPGMVIRTHANDLER pPrevVirt;
4303	PPGMPHYS2VIRTHANDLER pPrevPhys2Virt;
4304	PVM pVM;
4305	} PGMCHECKINTARGS, *PPGMCHECKINTARGS;
4306
4307	/**
4308	* Validate a node in the physical handler tree.
4309	*
4310	* @returns 0 on if ok, other wise 1.
4311	* @param pNode The handler node.
4312	* @param pvUser pVM.
4313	*/
4314	static DECLCALLBACK(int) pgmR3CheckIntegrityPhysHandlerNode(PAVLROGCPHYSNODECORE pNode, void *pvUser)
4315	{
4316	PPGMCHECKINTARGS pArgs = (PPGMCHECKINTARGS)pvUser;
4317	PPGMPHYSHANDLER pCur = (PPGMPHYSHANDLER)pNode;
4318	AssertReleaseReturn(!((uintptr_t)pCur & 7), 1);
4319	AssertReleaseMsg(pCur->Core.Key <= pCur->Core.KeyLast,("pCur=%p %RGp-%RGp %s\n", pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
4320	AssertReleaseMsg( !pArgs->pPrevPhys
4321	\|\| (pArgs->fLeftToRight ? pArgs->pPrevPhys->Core.KeyLast < pCur->Core.Key : pArgs->pPrevPhys->Core.KeyLast > pCur->Core.Key),
4322	("pPrevPhys=%p %RGp-%RGp %s\n"
4323	" pCur=%p %RGp-%RGp %s\n",
4324	pArgs->pPrevPhys, pArgs->pPrevPhys->Core.Key, pArgs->pPrevPhys->Core.KeyLast, pArgs->pPrevPhys->pszDesc,
4325	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
4326	pArgs->pPrevPhys = pCur;
4327	return 0;
4328	}
4329
4330
4331	/**
4332	* Validate a node in the virtual handler tree.
4333	*
4334	* @returns 0 on if ok, other wise 1.
4335	* @param pNode The handler node.
4336	* @param pvUser pVM.
4337	*/
4338	static DECLCALLBACK(int) pgmR3CheckIntegrityVirtHandlerNode(PAVLROGCPTRNODECORE pNode, void *pvUser)
4339	{
4340	PPGMCHECKINTARGS pArgs = (PPGMCHECKINTARGS)pvUser;
4341	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)pNode;
4342	AssertReleaseReturn(!((uintptr_t)pCur & 7), 1);
4343	AssertReleaseMsg(pCur->Core.Key <= pCur->Core.KeyLast,("pCur=%p %RGv-%RGv %s\n", pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
4344	AssertReleaseMsg( !pArgs->pPrevVirt
4345	\|\| (pArgs->fLeftToRight ? pArgs->pPrevVirt->Core.KeyLast < pCur->Core.Key : pArgs->pPrevVirt->Core.KeyLast > pCur->Core.Key),
4346	("pPrevVirt=%p %RGv-%RGv %s\n"
4347	" pCur=%p %RGv-%RGv %s\n",
4348	pArgs->pPrevVirt, pArgs->pPrevVirt->Core.Key, pArgs->pPrevVirt->Core.KeyLast, pArgs->pPrevVirt->pszDesc,
4349	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
4350	for (unsigned iPage = 0; iPage < pCur->cPages; iPage++)
4351	{
4352	AssertReleaseMsg(pCur->aPhysToVirt[iPage].offVirtHandler == -RT_OFFSETOF(PGMVIRTHANDLER, aPhysToVirt[iPage]),
4353	("pCur=%p %RGv-%RGv %s\n"
4354	"iPage=%d offVirtHandle=%#x expected %#x\n",
4355	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc,
4356	iPage, pCur->aPhysToVirt[iPage].offVirtHandler, -RT_OFFSETOF(PGMVIRTHANDLER, aPhysToVirt[iPage])));
4357	}
4358	pArgs->pPrevVirt = pCur;
4359	return 0;
4360	}
4361
4362
4363	/**
4364	* Validate a node in the virtual handler tree.
4365	*
4366	* @returns 0 on if ok, other wise 1.
4367	* @param pNode The handler node.
4368	* @param pvUser pVM.
4369	*/
4370	static DECLCALLBACK(int) pgmR3CheckIntegrityPhysToVirtHandlerNode(PAVLROGCPHYSNODECORE pNode, void *pvUser)
4371	{
4372	PPGMCHECKINTARGS pArgs = (PPGMCHECKINTARGS)pvUser;
4373	PPGMPHYS2VIRTHANDLER pCur = (PPGMPHYS2VIRTHANDLER)pNode;
4374	AssertReleaseMsgReturn(!((uintptr_t)pCur & 3), ("\n"), 1);
4375	AssertReleaseMsgReturn(!(pCur->offVirtHandler & 3), ("\n"), 1);
4376	AssertReleaseMsg(pCur->Core.Key <= pCur->Core.KeyLast,("pCur=%p %RGp-%RGp\n", pCur, pCur->Core.Key, pCur->Core.KeyLast));
4377	AssertReleaseMsg( !pArgs->pPrevPhys2Virt
4378	\|\| (pArgs->fLeftToRight ? pArgs->pPrevPhys2Virt->Core.KeyLast < pCur->Core.Key : pArgs->pPrevPhys2Virt->Core.KeyLast > pCur->Core.Key),
4379	("pPrevPhys2Virt=%p %RGp-%RGp\n"
4380	" pCur=%p %RGp-%RGp\n",
4381	pArgs->pPrevPhys2Virt, pArgs->pPrevPhys2Virt->Core.Key, pArgs->pPrevPhys2Virt->Core.KeyLast,
4382	pCur, pCur->Core.Key, pCur->Core.KeyLast));
4383	AssertReleaseMsg( !pArgs->pPrevPhys2Virt
4384	\|\| (pArgs->fLeftToRight ? pArgs->pPrevPhys2Virt->Core.KeyLast < pCur->Core.Key : pArgs->pPrevPhys2Virt->Core.KeyLast > pCur->Core.Key),
4385	("pPrevPhys2Virt=%p %RGp-%RGp\n"
4386	" pCur=%p %RGp-%RGp\n",
4387	pArgs->pPrevPhys2Virt, pArgs->pPrevPhys2Virt->Core.Key, pArgs->pPrevPhys2Virt->Core.KeyLast,
4388	pCur, pCur->Core.Key, pCur->Core.KeyLast));
4389	AssertReleaseMsg((pCur->offNextAlias & (PGMPHYS2VIRTHANDLER_IN_TREE \| PGMPHYS2VIRTHANDLER_IS_HEAD)) == (PGMPHYS2VIRTHANDLER_IN_TREE \| PGMPHYS2VIRTHANDLER_IS_HEAD),
4390	("pCur=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4391	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias));
4392	if (pCur->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK)
4393	{
4394	PPGMPHYS2VIRTHANDLER pCur2 = pCur;
4395	for (;;)
4396	{
4397	pCur2 = (PPGMPHYS2VIRTHANDLER)((intptr_t)pCur + (pCur->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK));
4398	AssertReleaseMsg(pCur2 != pCur,
4399	(" pCur=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4400	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias));
4401	AssertReleaseMsg((pCur2->offNextAlias & (PGMPHYS2VIRTHANDLER_IN_TREE \| PGMPHYS2VIRTHANDLER_IS_HEAD)) == PGMPHYS2VIRTHANDLER_IN_TREE,
4402	(" pCur=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
4403	"pCur2=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4404	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias,
4405	pCur2, pCur2->Core.Key, pCur2->Core.KeyLast, pCur2->offVirtHandler, pCur2->offNextAlias));
4406	AssertReleaseMsg((pCur2->Core.Key ^ pCur->Core.Key) < PAGE_SIZE,
4407	(" pCur=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
4408	"pCur2=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4409	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias,
4410	pCur2, pCur2->Core.Key, pCur2->Core.KeyLast, pCur2->offVirtHandler, pCur2->offNextAlias));
4411	AssertReleaseMsg((pCur2->Core.KeyLast ^ pCur->Core.KeyLast) < PAGE_SIZE,
4412	(" pCur=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
4413	"pCur2=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4414	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias,
4415	pCur2, pCur2->Core.Key, pCur2->Core.KeyLast, pCur2->offVirtHandler, pCur2->offNextAlias));
4416	if (!(pCur2->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK))
4417	break;
4418	}
4419	}
4420
4421	pArgs->pPrevPhys2Virt = pCur;
4422	return 0;
4423	}
4424
4425
4426	/**
4427	* Perform an integrity check on the PGM component.
4428	*
4429	* @returns VINF_SUCCESS if everything is fine.
4430	* @returns VBox error status after asserting on integrity breach.
4431	* @param pVM The VM handle.
4432	*/
4433	VMMR3DECL(int) PGMR3CheckIntegrity(PVM pVM)
4434	{
4435	AssertReleaseReturn(pVM->pgm.s.offVM, VERR_INTERNAL_ERROR);
4436
4437	/*
4438	* Check the trees.
4439	*/
4440	int cErrors = 0;
4441	const static PGMCHECKINTARGS s_LeftToRight = { true, NULL, NULL, NULL, pVM };
4442	const static PGMCHECKINTARGS s_RightToLeft = { false, NULL, NULL, NULL, pVM };
4443	PGMCHECKINTARGS Args = s_LeftToRight;
4444	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysHandlers, true, pgmR3CheckIntegrityPhysHandlerNode, &Args);
4445	Args = s_RightToLeft;
4446	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysHandlers, false, pgmR3CheckIntegrityPhysHandlerNode, &Args);
4447	Args = s_LeftToRight;
4448	cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesR3->VirtHandlers, true, pgmR3CheckIntegrityVirtHandlerNode, &Args);
4449	Args = s_RightToLeft;
4450	cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesR3->VirtHandlers, false, pgmR3CheckIntegrityVirtHandlerNode, &Args);
4451	Args = s_LeftToRight;
4452	cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesR3->HyperVirtHandlers, true, pgmR3CheckIntegrityVirtHandlerNode, &Args);
4453	Args = s_RightToLeft;
4454	cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesR3->HyperVirtHandlers, false, pgmR3CheckIntegrityVirtHandlerNode, &Args);
4455	Args = s_LeftToRight;
4456	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysToVirtHandlers, true, pgmR3CheckIntegrityPhysToVirtHandlerNode, &Args);
4457	Args = s_RightToLeft;
4458	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysToVirtHandlers, false, pgmR3CheckIntegrityPhysToVirtHandlerNode, &Args);
4459
4460	return !cErrors ? VINF_SUCCESS : VERR_INTERNAL_ERROR;
4461	}
4462
4463
4464	/**
4465	* Inform PGM if we want all mappings to be put into the shadow page table. (necessary for e.g. VMX)
4466	*
4467	* @returns VBox status code.
4468	* @param pVM VM handle.
4469	* @param fEnable Enable or disable shadow mappings
4470	*/
4471	VMMR3DECL(int) PGMR3ChangeShwPDMappings(PVM pVM, bool fEnable)
4472	{
4473	pVM->pgm.s.fDisableMappings = !fEnable;
4474
4475	uint32_t cb;
4476	int rc = PGMR3MappingsSize(pVM, &cb);
4477	AssertRCReturn(rc, rc);
4478
4479	/* Pretend the mappings are now fixed; to force a refresh of the reserved PDEs. */
4480	rc = PGMR3MappingsFix(pVM, MM_HYPER_AREA_ADDRESS, cb);
4481	AssertRCReturn(rc, rc);
4482
4483	return VINF_SUCCESS;
4484	}
4485

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source: vbox/trunk/src/VBox/VMM/PGM.cpp@ 14157

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