PGM.cpp@ 14299

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1	/* $Id: PGM.cpp 14260 2008-11-17 17:11:22Z vboxsync $ */
2	/** @file
3	* PGM - Page Manager and Monitor. (Mixing stuff here, not good?)
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22
23	/** @page pg_pgm PGM - The Page Manager and Monitor
24	*
25	* @see grp_pgm,
26	* @ref pg_pgm_pool,
27	* @ref pg_pgm_phys.
28	*
29	*
30	* @section sec_pgm_modes Paging Modes
31	*
32	* There are three memory contexts: Host Context (HC), Guest Context (GC)
33	* and intermediate context. When talking about paging HC can also be refered to
34	* as "host paging", and GC refered to as "shadow paging".
35	*
36	* We define three basic paging modes: 32-bit, PAE and AMD64. The host paging mode
37	* is defined by the host operating system. The mode used in the shadow paging mode
38	* depends on the host paging mode and what the mode the guest is currently in. The
39	* following relation between the two is defined:
40	*
41	* @verbatim
42	Host > 32-bit \| PAE \| AMD64 \|
43	Guest \| \| \| \|
44	==v================================
45	32-bit 32-bit PAE PAE
46	-------\|--------\|--------\|--------\|
47	PAE PAE PAE PAE
48	-------\|--------\|--------\|--------\|
49	AMD64 AMD64 AMD64 AMD64
50	-------\|--------\|--------\|--------\| @endverbatim
51	*
52	* All configuration except those in the diagonal (upper left) are expected to
53	* require special effort from the switcher (i.e. a bit slower).
54	*
55	*
56	*
57	*
58	* @section sec_pgm_shw The Shadow Memory Context
59	*
60	*
61	* [..]
62	*
63	* Because of guest context mappings requires PDPT and PML4 entries to allow
64	* writing on AMD64, the two upper levels will have fixed flags whatever the
65	* guest is thinking of using there. So, when shadowing the PD level we will
66	* calculate the effective flags of PD and all the higher levels. In legacy
67	* PAE mode this only applies to the PWT and PCD bits (the rest are
68	* ignored/reserved/MBZ). We will ignore those bits for the present.
69	*
70	*
71	*
72	* @section sec_pgm_int The Intermediate Memory Context
73	*
74	* The world switch goes thru an intermediate memory context which purpose it is
75	* to provide different mappings of the switcher code. All guest mappings are also
76	* present in this context.
77	*
78	* The switcher code is mapped at the same location as on the host, at an
79	* identity mapped location (physical equals virtual address), and at the
80	* hypervisor location. The identity mapped location is for when the world
81	* switches that involves disabling paging.
82	*
83	* PGM maintain page tables for 32-bit, PAE and AMD64 paging modes. This
84	* simplifies switching guest CPU mode and consistency at the cost of more
85	* code to do the work. All memory use for those page tables is located below
86	* 4GB (this includes page tables for guest context mappings).
87	*
88	*
89	* @subsection subsec_pgm_int_gc Guest Context Mappings
90	*
91	* During assignment and relocation of a guest context mapping the intermediate
92	* memory context is used to verify the new location.
93	*
94	* Guest context mappings are currently restricted to below 4GB, for reasons
95	* of simplicity. This may change when we implement AMD64 support.
96	*
97	*
98	*
99	*
100	* @section sec_pgm_misc Misc
101	*
102	* @subsection subsec_pgm_misc_diff Differences Between Legacy PAE and Long Mode PAE
103	*
104	* The differences between legacy PAE and long mode PAE are:
105	* -# PDPE bits 1, 2, 5 and 6 are defined differently. In leagcy mode they are
106	* all marked down as must-be-zero, while in long mode 1, 2 and 5 have the
107	* usual meanings while 6 is ignored (AMD). This means that upon switching to
108	* legacy PAE mode we'll have to clear these bits and when going to long mode
109	* they must be set. This applies to both intermediate and shadow contexts,
110	* however we don't need to do it for the intermediate one since we're
111	* executing with CR0.WP at that time.
112	* -# CR3 allows a 32-byte aligned address in legacy mode, while in long mode
113	* a page aligned one is required.
114	*
115	*
116	* @section sec_pgm_handlers Access Handlers
117	*
118	* Placeholder.
119	*
120	*
121	* @subsection sec_pgm_handlers_virt Virtual Access Handlers
122	*
123	* Placeholder.
124	*
125	*
126	* @subsection sec_pgm_handlers_virt Virtual Access Handlers
127	*
128	* We currently implement three types of virtual access handlers: ALL, WRITE
129	* and HYPERVISOR (WRITE). See PGMVIRTHANDLERTYPE for some more details.
130	*
131	* The HYPERVISOR access handlers is kept in a separate tree since it doesn't apply
132	* to physical pages (PGMTREES::HyperVirtHandlers) and only needs to be consulted in
133	* a special \#PF case. The ALL and WRITE are in the PGMTREES::VirtHandlers tree, the
134	* rest of this section is going to be about these handlers.
135	*
136	* We'll go thru the life cycle of a handler and try make sense of it all, don't know
137	* how successfull this is gonna be...
138	*
139	* 1. A handler is registered thru the PGMR3HandlerVirtualRegister and
140	* PGMHandlerVirtualRegisterEx APIs. We check for conflicting virtual handlers
141	* and create a new node that is inserted into the AVL tree (range key). Then
142	* a full PGM resync is flagged (clear pool, sync cr3, update virtual bit of PGMPAGE).
143	*
144	* 2. The following PGMSyncCR3/SyncCR3 operation will first make invoke HandlerVirtualUpdate.
145	*
146	* 2a. HandlerVirtualUpdate will will lookup all the pages covered by virtual handlers
147	* via the current guest CR3 and update the physical page -> virtual handler
148	* translation. Needless to say, this doesn't exactly scale very well. If any changes
149	* are detected, it will flag a virtual bit update just like we did on registration.
150	* PGMPHYS pages with changes will have their virtual handler state reset to NONE.
151	*
152	* 2b. The virtual bit update process will iterate all the pages covered by all the
153	* virtual handlers and update the PGMPAGE virtual handler state to the max of all
154	* virtual handlers on that page.
155	*
156	* 2c. Back in SyncCR3 we will now flush the entire shadow page cache to make sure
157	* we don't miss any alias mappings of the monitored pages.
158	*
159	* 2d. SyncCR3 will then proceed with syncing the CR3 table.
160	*
161	* 3. \#PF(np,read) on a page in the range. This will cause it to be synced
162	* read-only and resumed if it's a WRITE handler. If it's an ALL handler we
163	* will call the handlers like in the next step. If the physical mapping has
164	* changed we will - some time in the future - perform a handler callback
165	* (optional) and update the physical -> virtual handler cache.
166	*
167	* 4. \#PF(,write) on a page in the range. This will cause the handler to
168	* be invoked.
169	*
170	* 5. The guest invalidates the page and changes the physical backing or
171	* unmaps it. This should cause the invalidation callback to be invoked
172	* (it might not yet be 100% perfect). Exactly what happens next... is
173	* this where we mess up and end up out of sync for a while?
174	*
175	* 6. The handler is deregistered by the client via PGMHandlerVirtualDeregister.
176	* We will then set all PGMPAGEs in the physical -> virtual handler cache for
177	* this handler to NONE and trigger a full PGM resync (basically the same
178	* as int step 1). Which means 2 is executed again.
179	*
180	*
181	* @subsubsection sub_sec_pgm_handler_virt_todo TODOs
182	*
183	* There is a bunch of things that needs to be done to make the virtual handlers
184	* work 100% correctly and work more efficiently.
185	*
186	* The first bit hasn't been implemented yet because it's going to slow the
187	* whole mess down even more, and besides it seems to be working reliably for
188	* our current uses. OTOH, some of the optimizations might end up more or less
189	* implementing the missing bits, so we'll see.
190	*
191	* On the optimization side, the first thing to do is to try avoid unnecessary
192	* cache flushing. Then try team up with the shadowing code to track changes
193	* in mappings by means of access to them (shadow in), updates to shadows pages,
194	* invlpg, and shadow PT discarding (perhaps).
195	*
196	* Some idea that have popped up for optimization for current and new features:
197	* - bitmap indicating where there are virtual handlers installed.
198	* (4KB => 220 pages, page 212 => covers 32-bit address space 1:1!)
199	* - Further optimize this by min/max (needs min/max avl getters).
200	* - Shadow page table entry bit (if any left)?
201	*
202	*/
203
204
205	/** @page pg_pgm_phys PGM Physical Guest Memory Management
206	*
207	*
208	* Objectives:
209	* - Guest RAM over-commitment using memory ballooning,
210	* zero pages and general page sharing.
211	* - Moving or mirroring a VM onto a different physical machine.
212	*
213	*
214	* @subsection subsec_pgmPhys_Definitions Definitions
215	*
216	* Allocation chunk - A RTR0MemObjAllocPhysNC object and the tracking
217	* machinery assoicated with it.
218	*
219	*
220	*
221	*
222	* @subsection subsec_pgmPhys_AllocPage Allocating a page.
223	*
224	* Initially we map all guest memory to the (per VM) zero page, which
225	* means that none of the read functions will cause pages to be allocated.
226	*
227	* Exception, access bit in page tables that have been shared. This must
228	* be handled, but we must also make sure PGMGst*Modify doesn't make
229	* unnecessary modifications.
230	*
231	* Allocation points:
232	* - PGMPhysSimpleWriteGCPhys and PGMPhysWrite.
233	* - Replacing a zero page mapping at \#PF.
234	* - Replacing a shared page mapping at \#PF.
235	* - ROM registration (currently MMR3RomRegister).
236	* - VM restore (pgmR3Load).
237	*
238	* For the first three it would make sense to keep a few pages handy
239	* until we've reached the max memory commitment for the VM.
240	*
241	* For the ROM registration, we know exactly how many pages we need
242	* and will request these from ring-0. For restore, we will save
243	* the number of non-zero pages in the saved state and allocate
244	* them up front. This would allow the ring-0 component to refuse
245	* the request if the isn't sufficient memory available for VM use.
246	*
247	* Btw. for both ROM and restore allocations we won't be requiring
248	* zeroed pages as they are going to be filled instantly.
249	*
250	*
251	* @subsection subsec_pgmPhys_FreePage Freeing a page
252	*
253	* There are a few points where a page can be freed:
254	* - After being replaced by the zero page.
255	* - After being replaced by a shared page.
256	* - After being ballooned by the guest additions.
257	* - At reset.
258	* - At restore.
259	*
260	* When freeing one or more pages they will be returned to the ring-0
261	* component and replaced by the zero page.
262	*
263	* The reasoning for clearing out all the pages on reset is that it will
264	* return us to the exact same state as on power on, and may thereby help
265	* us reduce the memory load on the system. Further it might have a
266	* (temporary) positive influence on memory fragmentation (@see subsec_pgmPhys_Fragmentation).
267	*
268	* On restore, as mention under the allocation topic, pages should be
269	* freed / allocated depending on how many is actually required by the
270	* new VM state. The simplest approach is to do like on reset, and free
271	* all non-ROM pages and then allocate what we need.
272	*
273	* A measure to prevent some fragmentation, would be to let each allocation
274	* chunk have some affinity towards the VM having allocated the most pages
275	* from it. Also, try make sure to allocate from allocation chunks that
276	* are almost full. Admittedly, both these measures might work counter to
277	* our intentions and its probably not worth putting a lot of effort,
278	* cpu time or memory into this.
279	*
280	*
281	* @subsection subsec_pgmPhys_SharePage Sharing a page
282	*
283	* The basic idea is that there there will be a idle priority kernel
284	* thread walking the non-shared VM pages hashing them and looking for
285	* pages with the same checksum. If such pages are found, it will compare
286	* them byte-by-byte to see if they actually are identical. If found to be
287	* identical it will allocate a shared page, copy the content, check that
288	* the page didn't change while doing this, and finally request both the
289	* VMs to use the shared page instead. If the page is all zeros (special
290	* checksum and byte-by-byte check) it will request the VM that owns it
291	* to replace it with the zero page.
292	*
293	* To make this efficient, we will have to make sure not to try share a page
294	* that will change its contents soon. This part requires the most work.
295	* A simple idea would be to request the VM to write monitor the page for
296	* a while to make sure it isn't modified any time soon. Also, it may
297	* make sense to skip pages that are being write monitored since this
298	* information is readily available to the thread if it works on the
299	* per-VM guest memory structures (presently called PGMRAMRANGE).
300	*
301	*
302	* @subsection subsec_pgmPhys_Fragmentation Fragmentation Concerns and Counter Measures
303	*
304	* The pages are organized in allocation chunks in ring-0, this is a necessity
305	* if we wish to have an OS agnostic approach to this whole thing. (On Linux we
306	* could easily work on a page-by-page basis if we liked. Whether this is possible
307	* or efficient on NT I don't quite know.) Fragmentation within these chunks may
308	* become a problem as part of the idea here is that we wish to return memory to
309	* the host system.
310	*
311	* For instance, starting two VMs at the same time, they will both allocate the
312	* guest memory on-demand and if permitted their page allocations will be
313	* intermixed. Shut down one of the two VMs and it will be difficult to return
314	* any memory to the host system because the page allocation for the two VMs are
315	* mixed up in the same allocation chunks.
316	*
317	* To further complicate matters, when pages are freed because they have been
318	* ballooned or become shared/zero the whole idea is that the page is supposed
319	* to be reused by another VM or returned to the host system. This will cause
320	* allocation chunks to contain pages belonging to different VMs and prevent
321	* returning memory to the host when one of those VM shuts down.
322	*
323	* The only way to really deal with this problem is to move pages. This can
324	* either be done at VM shutdown and or by the idle priority worker thread
325	* that will be responsible for finding sharable/zero pages. The mechanisms
326	* involved for coercing a VM to move a page (or to do it for it) will be
327	* the same as when telling it to share/zero a page.
328	*
329	*
330	* @subsection subsec_pgmPhys_Tracking Tracking Structures And Their Cost
331	*
332	* There's a difficult balance between keeping the per-page tracking structures
333	* (global and guest page) easy to use and keeping them from eating too much
334	* memory. We have limited virtual memory resources available when operating in
335	* 32-bit kernel space (on 64-bit there'll it's quite a different story). The
336	* tracking structures will be attemted designed such that we can deal with up
337	* to 32GB of memory on a 32-bit system and essentially unlimited on 64-bit ones.
338	*
339	*
340	* @subsubsection subsubsec_pgmPhys_Tracking_Kernel Kernel Space
341	*
342	* @see pg_GMM
343	*
344	* @subsubsection subsubsec_pgmPhys_Tracking_PerVM Per-VM
345	*
346	* Fixed info is the physical address of the page (HCPhys) and the page id
347	* (described above). Theoretically we'll need 48(-12) bits for the HCPhys part.
348	* Today we've restricting ourselves to 40(-12) bits because this is the current
349	* restrictions of all AMD64 implementations (I think Barcelona will up this
350	* to 48(-12) bits, not that it really matters) and I needed the bits for
351	* tracking mappings of a page. 48-12 = 36. That leaves 28 bits, which means a
352	* decent range for the page id: 2^(28+12) = 1024TB.
353	*
354	* In additions to these, we'll have to keep maintaining the page flags as we
355	* currently do. Although it wouldn't harm to optimize these quite a bit, like
356	* for instance the ROM shouldn't depend on having a write handler installed
357	* in order for it to become read-only. A RO/RW bit should be considered so
358	* that the page syncing code doesn't have to mess about checking multiple
359	* flag combinations (ROM \|\| RW handler \|\| write monitored) in order to
360	* figure out how to setup a shadow PTE. But this of course, is second
361	* priority at present. Current this requires 12 bits, but could probably
362	* be optimized to ~8.
363	*
364	* Then there's the 24 bits used to track which shadow page tables are
365	* currently mapping a page for the purpose of speeding up physical
366	* access handlers, and thereby the page pool cache. More bit for this
367	* purpose wouldn't hurt IIRC.
368	*
369	* Then there is a new bit in which we need to record what kind of page
370	* this is, shared, zero, normal or write-monitored-normal. This'll
371	* require 2 bits. One bit might be needed for indicating whether a
372	* write monitored page has been written to. And yet another one or
373	* two for tracking migration status. 3-4 bits total then.
374	*
375	* Whatever is left will can be used to record the sharabilitiy of a
376	* page. The page checksum will not be stored in the per-VM table as
377	* the idle thread will not be permitted to do modifications to it.
378	* It will instead have to keep its own working set of potentially
379	* shareable pages and their check sums and stuff.
380	*
381	* For the present we'll keep the current packing of the
382	* PGMRAMRANGE::aHCPhys to keep the changes simple, only of course,
383	* we'll have to change it to a struct with a total of 128-bits at
384	* our disposal.
385	*
386	* The initial layout will be like this:
387	* @verbatim
388	RTHCPHYS HCPhys; The current stuff.
389	63:40 Current shadow PT tracking stuff.
390	39:12 The physical page frame number.
391	11:0 The current flags.
392	uint32_t u28PageId : 28; The page id.
393	uint32_t u2State : 2; The page state { zero, shared, normal, write monitored }.
394	uint32_t fWrittenTo : 1; Whether a write monitored page was written to.
395	uint32_t u1Reserved : 1; Reserved for later.
396	uint32_t u32Reserved; Reserved for later, mostly sharing stats.
397	@endverbatim
398	*
399	* The final layout will be something like this:
400	* @verbatim
401	RTHCPHYS HCPhys; The current stuff.
402	63:48 High page id (12+).
403	47:12 The physical page frame number.
404	11:0 Low page id.
405	uint32_t fReadOnly : 1; Whether it's readonly page (rom or monitored in some way).
406	uint32_t u3Type : 3; The page type {RESERVED, MMIO, MMIO2, ROM, shadowed ROM, RAM}.
407	uint32_t u2PhysMon : 2; Physical access handler type {none, read, write, all}.
408	uint32_t u2VirtMon : 2; Virtual access handler type {none, read, write, all}..
409	uint32_t u2State : 2; The page state { zero, shared, normal, write monitored }.
410	uint32_t fWrittenTo : 1; Whether a write monitored page was written to.
411	uint32_t u20Reserved : 20; Reserved for later, mostly sharing stats.
412	uint32_t u32Tracking; The shadow PT tracking stuff, roughly.
413	@endverbatim
414	*
415	* Cost wise, this means we'll double the cost for guest memory. There isn't anyway
416	* around that I'm afraid. It means that the cost of dealing out 32GB of memory
417	* to one or more VMs is: (32GB >> PAGE_SHIFT) * 16 bytes, or 128MBs. Or another
418	* example, the VM heap cost when assigning 1GB to a VM will be: 4MB.
419	*
420	* A couple of cost examples for the total cost per-VM + kernel.
421	* 32-bit Windows and 32-bit linux:
422	* 1GB guest ram, 256K pages: 4MB + 2MB(+) = 6MB
423	* 4GB guest ram, 1M pages: 16MB + 8MB(+) = 24MB
424	* 32GB guest ram, 8M pages: 128MB + 64MB(+) = 192MB
425	* 64-bit Windows and 64-bit linux:
426	* 1GB guest ram, 256K pages: 4MB + 3MB(+) = 7MB
427	* 4GB guest ram, 1M pages: 16MB + 12MB(+) = 28MB
428	* 32GB guest ram, 8M pages: 128MB + 96MB(+) = 224MB
429	*
430	* UPDATE - 2007-09-27:
431	* Will need a ballooned flag/state too because we cannot
432	* trust the guest 100% and reporting the same page as ballooned more
433	* than once will put the GMM off balance.
434	*
435	*
436	* @subsection subsec_pgmPhys_Serializing Serializing Access
437	*
438	* Initially, we'll try a simple scheme:
439	*
440	* - The per-VM RAM tracking structures (PGMRAMRANGE) is only modified
441	* by the EMT thread of that VM while in the pgm critsect.
442	* - Other threads in the VM process that needs to make reliable use of
443	* the per-VM RAM tracking structures will enter the critsect.
444	* - No process external thread or kernel thread will ever try enter
445	* the pgm critical section, as that just won't work.
446	* - The idle thread (and similar threads) doesn't not need 100% reliable
447	* data when performing it tasks as the EMT thread will be the one to
448	* do the actual changes later anyway. So, as long as it only accesses
449	* the main ram range, it can do so by somehow preventing the VM from
450	* being destroyed while it works on it...
451	*
452	* - The over-commitment management, including the allocating/freeing
453	* chunks, is serialized by a ring-0 mutex lock (a fast one since the
454	* more mundane mutex implementation is broken on Linux).
455	* - A separeate mutex is protecting the set of allocation chunks so
456	* that pages can be shared or/and freed up while some other VM is
457	* allocating more chunks. This mutex can be take from under the other
458	* one, but not the otherway around.
459	*
460	*
461	* @subsection subsec_pgmPhys_Request VM Request interface
462	*
463	* When in ring-0 it will become necessary to send requests to a VM so it can
464	* for instance move a page while defragmenting during VM destroy. The idle
465	* thread will make use of this interface to request VMs to setup shared
466	* pages and to perform write monitoring of pages.
467	*
468	* I would propose an interface similar to the current VMReq interface, similar
469	* in that it doesn't require locking and that the one sending the request may
470	* wait for completion if it wishes to. This shouldn't be very difficult to
471	* realize.
472	*
473	* The requests themselves are also pretty simple. They are basically:
474	* -# Check that some precondition is still true.
475	* -# Do the update.
476	* -# Update all shadow page tables involved with the page.
477	*
478	* The 3rd step is identical to what we're already doing when updating a
479	* physical handler, see pgmHandlerPhysicalSetRamFlagsAndFlushShadowPTs.
480	*
481	*
482	*
483	* @section sec_pgmPhys_MappingCaches Mapping Caches
484	*
485	* In order to be able to map in and out memory and to be able to support
486	* guest with more RAM than we've got virtual address space, we'll employing
487	* a mapping cache. There is already a tiny one for GC (see PGMGCDynMapGCPageEx)
488	* and we'll create a similar one for ring-0 unless we decide to setup a dedicate
489	* memory context for the HWACCM execution.
490	*
491	*
492	* @subsection subsec_pgmPhys_MappingCaches_R3 Ring-3
493	*
494	* We've considered implementing the ring-3 mapping cache page based but found
495	* that this was bother some when one had to take into account TLBs+SMP and
496	* portability (missing the necessary APIs on several platforms). There were
497	* also some performance concerns with this approach which hadn't quite been
498	* worked out.
499	*
500	* Instead, we'll be mapping allocation chunks into the VM process. This simplifies
501	* matters greatly quite a bit since we don't need to invent any new ring-0 stuff,
502	* only some minor RTR0MEMOBJ mapping stuff. The main concern here is that mapping
503	* compared to the previous idea is that mapping or unmapping a 1MB chunk is more
504	* costly than a single page, although how much more costly is uncertain. We'll
505	* try address this by using a very big cache, preferably bigger than the actual
506	* VM RAM size if possible. The current VM RAM sizes should give some idea for
507	* 32-bit boxes, while on 64-bit we can probably get away with employing an
508	* unlimited cache.
509	*
510	* The cache have to parts, as already indicated, the ring-3 side and the
511	* ring-0 side.
512	*
513	* The ring-0 will be tied to the page allocator since it will operate on the
514	* memory objects it contains. It will therefore require the first ring-0 mutex
515	* discussed in @ref subsec_pgmPhys_Serializing. We
516	* some double house keeping wrt to who has mapped what I think, since both
517	* VMMR0.r0 and RTR0MemObj will keep track of mapping relataions
518	*
519	* The ring-3 part will be protected by the pgm critsect. For simplicity, we'll
520	* require anyone that desires to do changes to the mapping cache to do that
521	* from within this critsect. Alternatively, we could employ a separate critsect
522	* for serializing changes to the mapping cache as this would reduce potential
523	* contention with other threads accessing mappings unrelated to the changes
524	* that are in process. We can see about this later, contention will show
525	* up in the statistics anyway, so it'll be simple to tell.
526	*
527	* The organization of the ring-3 part will be very much like how the allocation
528	* chunks are organized in ring-0, that is in an AVL tree by chunk id. To avoid
529	* having to walk the tree all the time, we'll have a couple of lookaside entries
530	* like in we do for I/O ports and MMIO in IOM.
531	*
532	* The simplified flow of a PGMPhysRead/Write function:
533	* -# Enter the PGM critsect.
534	* -# Lookup GCPhys in the ram ranges and get the Page ID.
535	* -# Calc the Allocation Chunk ID from the Page ID.
536	* -# Check the lookaside entries and then the AVL tree for the Chunk ID.
537	* If not found in cache:
538	* -# Call ring-0 and request it to be mapped and supply
539	* a chunk to be unmapped if the cache is maxed out already.
540	* -# Insert the new mapping into the AVL tree (id + R3 address).
541	* -# Update the relevant lookaside entry and return the mapping address.
542	* -# Do the read/write according to monitoring flags and everything.
543	* -# Leave the critsect.
544	*
545	*
546	* @section sec_pgmPhys_Fallback Fallback
547	*
548	* Current all the "second tier" hosts will not support the RTR0MemObjAllocPhysNC
549	* API and thus require a fallback.
550	*
551	* So, when RTR0MemObjAllocPhysNC returns VERR_NOT_SUPPORTED the page allocator
552	* will return to the ring-3 caller (and later ring-0) and asking it to seed
553	* the page allocator with some fresh pages (VERR_GMM_SEED_ME). Ring-3 will
554	* then perform an SUPPageAlloc(cbChunk >> PAGE_SHIFT) call and make a
555	* "SeededAllocPages" call to ring-0.
556	*
557	* The first time ring-0 sees the VERR_NOT_SUPPORTED failure it will disable
558	* all page sharing (zero page detection will continue). It will also force
559	* all allocations to come from the VM which seeded the page. Both these
560	* measures are taken to make sure that there will never be any need for
561	* mapping anything into ring-3 - everything will be mapped already.
562	*
563	* Whether we'll continue to use the current MM locked memory management
564	* for this I don't quite know (I'd prefer not to and just ditch that all
565	* togther), we'll see what's simplest to do.
566	*
567	*
568	*
569	* @section sec_pgmPhys_Changes Changes
570	*
571	* Breakdown of the changes involved?
572	*/
573
574
575	/** Saved state data unit version. */
576	#define PGM_SAVED_STATE_VERSION 6
577
578	/*******************************************************************************
579	* Header Files *
580	*******************************************************************************/
581	#define LOG_GROUP LOG_GROUP_PGM
582	#include <VBox/dbgf.h>
583	#include <VBox/pgm.h>
584	#include <VBox/cpum.h>
585	#include <VBox/iom.h>
586	#include <VBox/sup.h>
587	#include <VBox/mm.h>
588	#include <VBox/em.h>
589	#include <VBox/stam.h>
590	#include <VBox/rem.h>
591	#include <VBox/dbgf.h>
592	#include <VBox/rem.h>
593	#include <VBox/selm.h>
594	#include <VBox/ssm.h>
595	#include "PGMInternal.h"
596	#include <VBox/vm.h>
597	#include <VBox/dbg.h>
598	#include <VBox/hwaccm.h>
599
600	#include <iprt/assert.h>
601	#include <iprt/alloc.h>
602	#include <iprt/asm.h>
603	#include <iprt/thread.h>
604	#include <iprt/string.h>
605	#ifdef DEBUG_bird
606	# include <iprt/env.h>
607	#endif
608	#include <VBox/param.h>
609	#include <VBox/err.h>
610
611
612
613	/*******************************************************************************
614	* Internal Functions *
615	*******************************************************************************/
616	static int pgmR3InitPaging(PVM pVM);
617	static DECLCALLBACK(void) pgmR3PhysInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
618	static DECLCALLBACK(void) pgmR3InfoMode(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
619	static DECLCALLBACK(void) pgmR3InfoCr3(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
620	static DECLCALLBACK(int) pgmR3RelocatePhysHandler(PAVLROGCPHYSNODECORE pNode, void *pvUser);
621	static DECLCALLBACK(int) pgmR3RelocateVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser);
622	static DECLCALLBACK(int) pgmR3RelocateHyperVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser);
623	#ifdef VBOX_STRICT
624	static DECLCALLBACK(void) pgmR3ResetNoMorePhysWritesFlag(PVM pVM, VMSTATE enmState, VMSTATE enmOldState, void *pvUser);
625	#endif
626	static DECLCALLBACK(int) pgmR3Save(PVM pVM, PSSMHANDLE pSSM);
627	static DECLCALLBACK(int) pgmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version);
628	static int pgmR3ModeDataInit(PVM pVM, bool fResolveGCAndR0);
629	static void pgmR3ModeDataSwitch(PVM pVM, PGMMODE enmShw, PGMMODE enmGst);
630	static PGMMODE pgmR3CalcShadowMode(PVM pVM, PGMMODE enmGuestMode, SUPPAGINGMODE enmHostMode, PGMMODE enmShadowMode, VMMSWITCHER *penmSwitcher);
631
632	#ifdef VBOX_WITH_STATISTICS
633	static void pgmR3InitStats(PVM pVM);
634	#endif
635
636	#ifdef VBOX_WITH_DEBUGGER
637	/** @todo all but the two last commands must be converted to 'info'. */
638	static DECLCALLBACK(int) pgmR3CmdRam(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
639	static DECLCALLBACK(int) pgmR3CmdMap(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
640	static DECLCALLBACK(int) pgmR3CmdSync(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
641	static DECLCALLBACK(int) pgmR3CmdSyncAlways(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
642	# ifdef VBOX_STRICT
643	static DECLCALLBACK(int) pgmR3CmdAssertCR3(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
644	# endif
645	#endif
646
647
648	/*******************************************************************************
649	* Global Variables *
650	*******************************************************************************/
651	#ifdef VBOX_WITH_DEBUGGER
652	/** Command descriptors. */
653	static const DBGCCMD g_aCmds[] =
654	{
655	/* pszCmd, cArgsMin, cArgsMax, paArgDesc, cArgDescs, pResultDesc, fFlags, pfnHandler pszSyntax, ....pszDescription */
656	{ "pgmram", 0, 0, NULL, 0, NULL, 0, pgmR3CmdRam, "", "Display the ram ranges." },
657	{ "pgmmap", 0, 0, NULL, 0, NULL, 0, pgmR3CmdMap, "", "Display the mapping ranges." },
658	{ "pgmsync", 0, 0, NULL, 0, NULL, 0, pgmR3CmdSync, "", "Sync the CR3 page." },
659	#ifdef VBOX_STRICT
660	{ "pgmassertcr3", 0, 0, NULL, 0, NULL, 0, pgmR3CmdAssertCR3, "", "Check the shadow CR3 mapping." },
661	#endif
662	{ "pgmsyncalways", 0, 0, NULL, 0, NULL, 0, pgmR3CmdSyncAlways, "", "Toggle permanent CR3 syncing." },
663	};
664	#endif
665
666
667
668
669	/*
670	* Shadow - 32-bit mode
671	*/
672	#define PGM_SHW_TYPE PGM_TYPE_32BIT
673	#define PGM_SHW_NAME(name) PGM_SHW_NAME_32BIT(name)
674	#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_32BIT_STR(name)
675	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_32BIT_STR(name)
676	#include "PGMShw.h"
677
678	/* Guest - real mode */
679	#define PGM_GST_TYPE PGM_TYPE_REAL
680	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
681	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_REAL_STR(name)
682	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
683	#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_REAL(name)
684	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_32BIT_REAL_STR(name)
685	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_32BIT_REAL_STR(name)
686	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_PHYS
687	#include "PGMGst.h"
688	#include "PGMBth.h"
689	#undef BTH_PGMPOOLKIND_PT_FOR_PT
690	#undef PGM_BTH_NAME
691	#undef PGM_BTH_NAME_RC_STR
692	#undef PGM_BTH_NAME_R0_STR
693	#undef PGM_GST_TYPE
694	#undef PGM_GST_NAME
695	#undef PGM_GST_NAME_RC_STR
696	#undef PGM_GST_NAME_R0_STR
697
698	/* Guest - protected mode */
699	#define PGM_GST_TYPE PGM_TYPE_PROT
700	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
701	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PROT_STR(name)
702	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
703	#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_PROT(name)
704	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_32BIT_PROT_STR(name)
705	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_32BIT_PROT_STR(name)
706	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_PHYS
707	#include "PGMGst.h"
708	#include "PGMBth.h"
709	#undef BTH_PGMPOOLKIND_PT_FOR_PT
710	#undef PGM_BTH_NAME
711	#undef PGM_BTH_NAME_RC_STR
712	#undef PGM_BTH_NAME_R0_STR
713	#undef PGM_GST_TYPE
714	#undef PGM_GST_NAME
715	#undef PGM_GST_NAME_RC_STR
716	#undef PGM_GST_NAME_R0_STR
717
718	/* Guest - 32-bit mode */
719	#define PGM_GST_TYPE PGM_TYPE_32BIT
720	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
721	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_32BIT_STR(name)
722	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
723	#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_32BIT(name)
724	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_32BIT_32BIT_STR(name)
725	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_32BIT_32BIT_STR(name)
726	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT
727	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB
728	#include "PGMGst.h"
729	#include "PGMBth.h"
730	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
731	#undef BTH_PGMPOOLKIND_PT_FOR_PT
732	#undef PGM_BTH_NAME
733	#undef PGM_BTH_NAME_RC_STR
734	#undef PGM_BTH_NAME_R0_STR
735	#undef PGM_GST_TYPE
736	#undef PGM_GST_NAME
737	#undef PGM_GST_NAME_RC_STR
738	#undef PGM_GST_NAME_R0_STR
739
740	#undef PGM_SHW_TYPE
741	#undef PGM_SHW_NAME
742	#undef PGM_SHW_NAME_RC_STR
743	#undef PGM_SHW_NAME_R0_STR
744
745
746	/*
747	* Shadow - PAE mode
748	*/
749	#define PGM_SHW_TYPE PGM_TYPE_PAE
750	#define PGM_SHW_NAME(name) PGM_SHW_NAME_PAE(name)
751	#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_PAE_STR(name)
752	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_PAE_STR(name)
753	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_REAL(name)
754	#include "PGMShw.h"
755
756	/* Guest - real mode */
757	#define PGM_GST_TYPE PGM_TYPE_REAL
758	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
759	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_REAL_STR(name)
760	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
761	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_REAL(name)
762	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_PAE_REAL_STR(name)
763	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_REAL_STR(name)
764	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
765	#include "PGMBth.h"
766	#undef BTH_PGMPOOLKIND_PT_FOR_PT
767	#undef PGM_BTH_NAME
768	#undef PGM_BTH_NAME_RC_STR
769	#undef PGM_BTH_NAME_R0_STR
770	#undef PGM_GST_TYPE
771	#undef PGM_GST_NAME
772	#undef PGM_GST_NAME_RC_STR
773	#undef PGM_GST_NAME_R0_STR
774
775	/* Guest - protected mode */
776	#define PGM_GST_TYPE PGM_TYPE_PROT
777	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
778	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PROT_STR(name)
779	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
780	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_PROT(name)
781	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_PAE_PROT_STR(name)
782	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_PROT_STR(name)
783	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
784	#include "PGMBth.h"
785	#undef BTH_PGMPOOLKIND_PT_FOR_PT
786	#undef PGM_BTH_NAME
787	#undef PGM_BTH_NAME_RC_STR
788	#undef PGM_BTH_NAME_R0_STR
789	#undef PGM_GST_TYPE
790	#undef PGM_GST_NAME
791	#undef PGM_GST_NAME_RC_STR
792	#undef PGM_GST_NAME_R0_STR
793
794	/* Guest - 32-bit mode */
795	#define PGM_GST_TYPE PGM_TYPE_32BIT
796	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
797	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_32BIT_STR(name)
798	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
799	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_32BIT(name)
800	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_PAE_32BIT_STR(name)
801	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_32BIT_STR(name)
802	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_32BIT_PT
803	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB
804	#include "PGMBth.h"
805	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
806	#undef BTH_PGMPOOLKIND_PT_FOR_PT
807	#undef PGM_BTH_NAME
808	#undef PGM_BTH_NAME_RC_STR
809	#undef PGM_BTH_NAME_R0_STR
810	#undef PGM_GST_TYPE
811	#undef PGM_GST_NAME
812	#undef PGM_GST_NAME_RC_STR
813	#undef PGM_GST_NAME_R0_STR
814
815	/* Guest - PAE mode */
816	#define PGM_GST_TYPE PGM_TYPE_PAE
817	#define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
818	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PAE_STR(name)
819	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PAE_STR(name)
820	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_PAE(name)
821	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_PAE_PAE_STR(name)
822	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_PAE_STR(name)
823	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
824	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
825	#include "PGMGst.h"
826	#include "PGMBth.h"
827	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
828	#undef BTH_PGMPOOLKIND_PT_FOR_PT
829	#undef PGM_BTH_NAME
830	#undef PGM_BTH_NAME_RC_STR
831	#undef PGM_BTH_NAME_R0_STR
832	#undef PGM_GST_TYPE
833	#undef PGM_GST_NAME
834	#undef PGM_GST_NAME_RC_STR
835	#undef PGM_GST_NAME_R0_STR
836
837	#undef PGM_SHW_TYPE
838	#undef PGM_SHW_NAME
839	#undef PGM_SHW_NAME_RC_STR
840	#undef PGM_SHW_NAME_R0_STR
841
842
843	/*
844	* Shadow - AMD64 mode
845	*/
846	#define PGM_SHW_TYPE PGM_TYPE_AMD64
847	#define PGM_SHW_NAME(name) PGM_SHW_NAME_AMD64(name)
848	#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_AMD64_STR(name)
849	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_AMD64_STR(name)
850	#include "PGMShw.h"
851
852	#ifdef VBOX_WITH_64_BITS_GUESTS
853	/* Guest - AMD64 mode */
854	# define PGM_GST_TYPE PGM_TYPE_AMD64
855	# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
856	# define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_AMD64_STR(name)
857	# define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_AMD64_STR(name)
858	# define PGM_BTH_NAME(name) PGM_BTH_NAME_AMD64_AMD64(name)
859	# define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_AMD64_AMD64_STR(name)
860	# define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_AMD64_AMD64_STR(name)
861	# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
862	# define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
863	# include "PGMGst.h"
864	# include "PGMBth.h"
865	# undef BTH_PGMPOOLKIND_PT_FOR_BIG
866	# undef BTH_PGMPOOLKIND_PT_FOR_PT
867	# undef PGM_BTH_NAME
868	# undef PGM_BTH_NAME_RC_STR
869	# undef PGM_BTH_NAME_R0_STR
870	# undef PGM_GST_TYPE
871	# undef PGM_GST_NAME
872	# undef PGM_GST_NAME_RC_STR
873	# undef PGM_GST_NAME_R0_STR
874	#endif /* VBOX_WITH_64_BITS_GUESTS */
875
876	#undef PGM_SHW_TYPE
877	#undef PGM_SHW_NAME
878	#undef PGM_SHW_NAME_RC_STR
879	#undef PGM_SHW_NAME_R0_STR
880
881
882	/*
883	* Shadow - Nested paging mode
884	*/
885	#define PGM_SHW_TYPE PGM_TYPE_NESTED
886	#define PGM_SHW_NAME(name) PGM_SHW_NAME_NESTED(name)
887	#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_NESTED_STR(name)
888	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_NESTED_STR(name)
889	#include "PGMShw.h"
890
891	/* Guest - real mode */
892	#define PGM_GST_TYPE PGM_TYPE_REAL
893	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
894	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_REAL_STR(name)
895	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
896	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_REAL(name)
897	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_REAL_STR(name)
898	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_REAL_STR(name)
899	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
900	#include "PGMBth.h"
901	#undef BTH_PGMPOOLKIND_PT_FOR_PT
902	#undef PGM_BTH_NAME
903	#undef PGM_BTH_NAME_RC_STR
904	#undef PGM_BTH_NAME_R0_STR
905	#undef PGM_GST_TYPE
906	#undef PGM_GST_NAME
907	#undef PGM_GST_NAME_RC_STR
908	#undef PGM_GST_NAME_R0_STR
909
910	/* Guest - protected mode */
911	#define PGM_GST_TYPE PGM_TYPE_PROT
912	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
913	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PROT_STR(name)
914	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
915	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_PROT(name)
916	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_PROT_STR(name)
917	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_PROT_STR(name)
918	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
919	#include "PGMBth.h"
920	#undef BTH_PGMPOOLKIND_PT_FOR_PT
921	#undef PGM_BTH_NAME
922	#undef PGM_BTH_NAME_RC_STR
923	#undef PGM_BTH_NAME_R0_STR
924	#undef PGM_GST_TYPE
925	#undef PGM_GST_NAME
926	#undef PGM_GST_NAME_RC_STR
927	#undef PGM_GST_NAME_R0_STR
928
929	/* Guest - 32-bit mode */
930	#define PGM_GST_TYPE PGM_TYPE_32BIT
931	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
932	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_32BIT_STR(name)
933	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
934	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_32BIT(name)
935	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_32BIT_STR(name)
936	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_32BIT_STR(name)
937	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_32BIT_PT
938	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB
939	#include "PGMBth.h"
940	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
941	#undef BTH_PGMPOOLKIND_PT_FOR_PT
942	#undef PGM_BTH_NAME
943	#undef PGM_BTH_NAME_RC_STR
944	#undef PGM_BTH_NAME_R0_STR
945	#undef PGM_GST_TYPE
946	#undef PGM_GST_NAME
947	#undef PGM_GST_NAME_RC_STR
948	#undef PGM_GST_NAME_R0_STR
949
950	/* Guest - PAE mode */
951	#define PGM_GST_TYPE PGM_TYPE_PAE
952	#define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
953	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PAE_STR(name)
954	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PAE_STR(name)
955	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_PAE(name)
956	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_PAE_STR(name)
957	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_PAE_STR(name)
958	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
959	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
960	#include "PGMBth.h"
961	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
962	#undef BTH_PGMPOOLKIND_PT_FOR_PT
963	#undef PGM_BTH_NAME
964	#undef PGM_BTH_NAME_RC_STR
965	#undef PGM_BTH_NAME_R0_STR
966	#undef PGM_GST_TYPE
967	#undef PGM_GST_NAME
968	#undef PGM_GST_NAME_RC_STR
969	#undef PGM_GST_NAME_R0_STR
970
971	#ifdef VBOX_WITH_64_BITS_GUESTS
972	/* Guest - AMD64 mode */
973	# define PGM_GST_TYPE PGM_TYPE_AMD64
974	# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
975	# define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_AMD64_STR(name)
976	# define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_AMD64_STR(name)
977	# define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_AMD64(name)
978	# define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_AMD64_STR(name)
979	# define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_AMD64_STR(name)
980	# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
981	# define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
982	# include "PGMBth.h"
983	# undef BTH_PGMPOOLKIND_PT_FOR_BIG
984	# undef BTH_PGMPOOLKIND_PT_FOR_PT
985	# undef PGM_BTH_NAME
986	# undef PGM_BTH_NAME_RC_STR
987	# undef PGM_BTH_NAME_R0_STR
988	# undef PGM_GST_TYPE
989	# undef PGM_GST_NAME
990	# undef PGM_GST_NAME_RC_STR
991	# undef PGM_GST_NAME_R0_STR
992	#endif /* VBOX_WITH_64_BITS_GUESTS */
993
994	#undef PGM_SHW_TYPE
995	#undef PGM_SHW_NAME
996	#undef PGM_SHW_NAME_RC_STR
997	#undef PGM_SHW_NAME_R0_STR
998
999
1000	/*
1001	* Shadow - EPT
1002	*/
1003	#define PGM_SHW_TYPE PGM_TYPE_EPT
1004	#define PGM_SHW_NAME(name) PGM_SHW_NAME_EPT(name)
1005	#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_EPT_STR(name)
1006	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_EPT_STR(name)
1007	#include "PGMShw.h"
1008
1009	/* Guest - real mode */
1010	#define PGM_GST_TYPE PGM_TYPE_REAL
1011	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
1012	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_REAL_STR(name)
1013	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
1014	#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_REAL(name)
1015	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_REAL_STR(name)
1016	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_REAL_STR(name)
1017	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
1018	#include "PGMBth.h"
1019	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1020	#undef PGM_BTH_NAME
1021	#undef PGM_BTH_NAME_RC_STR
1022	#undef PGM_BTH_NAME_R0_STR
1023	#undef PGM_GST_TYPE
1024	#undef PGM_GST_NAME
1025	#undef PGM_GST_NAME_RC_STR
1026	#undef PGM_GST_NAME_R0_STR
1027
1028	/* Guest - protected mode */
1029	#define PGM_GST_TYPE PGM_TYPE_PROT
1030	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
1031	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PROT_STR(name)
1032	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
1033	#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_PROT(name)
1034	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_PROT_STR(name)
1035	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_PROT_STR(name)
1036	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
1037	#include "PGMBth.h"
1038	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1039	#undef PGM_BTH_NAME
1040	#undef PGM_BTH_NAME_RC_STR
1041	#undef PGM_BTH_NAME_R0_STR
1042	#undef PGM_GST_TYPE
1043	#undef PGM_GST_NAME
1044	#undef PGM_GST_NAME_RC_STR
1045	#undef PGM_GST_NAME_R0_STR
1046
1047	/* Guest - 32-bit mode */
1048	#define PGM_GST_TYPE PGM_TYPE_32BIT
1049	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
1050	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_32BIT_STR(name)
1051	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
1052	#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_32BIT(name)
1053	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_32BIT_STR(name)
1054	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_32BIT_STR(name)
1055	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_32BIT_PT
1056	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB
1057	#include "PGMBth.h"
1058	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
1059	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1060	#undef PGM_BTH_NAME
1061	#undef PGM_BTH_NAME_RC_STR
1062	#undef PGM_BTH_NAME_R0_STR
1063	#undef PGM_GST_TYPE
1064	#undef PGM_GST_NAME
1065	#undef PGM_GST_NAME_RC_STR
1066	#undef PGM_GST_NAME_R0_STR
1067
1068	/* Guest - PAE mode */
1069	#define PGM_GST_TYPE PGM_TYPE_PAE
1070	#define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
1071	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PAE_STR(name)
1072	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PAE_STR(name)
1073	#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_PAE(name)
1074	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_PAE_STR(name)
1075	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_PAE_STR(name)
1076	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
1077	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
1078	#include "PGMBth.h"
1079	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
1080	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1081	#undef PGM_BTH_NAME
1082	#undef PGM_BTH_NAME_RC_STR
1083	#undef PGM_BTH_NAME_R0_STR
1084	#undef PGM_GST_TYPE
1085	#undef PGM_GST_NAME
1086	#undef PGM_GST_NAME_RC_STR
1087	#undef PGM_GST_NAME_R0_STR
1088
1089	#ifdef VBOX_WITH_64_BITS_GUESTS
1090	/* Guest - AMD64 mode */
1091	# define PGM_GST_TYPE PGM_TYPE_AMD64
1092	# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
1093	# define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_AMD64_STR(name)
1094	# define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_AMD64_STR(name)
1095	# define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_AMD64(name)
1096	# define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_AMD64_STR(name)
1097	# define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_AMD64_STR(name)
1098	# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
1099	# define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
1100	# include "PGMBth.h"
1101	# undef BTH_PGMPOOLKIND_PT_FOR_BIG
1102	# undef BTH_PGMPOOLKIND_PT_FOR_PT
1103	# undef PGM_BTH_NAME
1104	# undef PGM_BTH_NAME_RC_STR
1105	# undef PGM_BTH_NAME_R0_STR
1106	# undef PGM_GST_TYPE
1107	# undef PGM_GST_NAME
1108	# undef PGM_GST_NAME_RC_STR
1109	# undef PGM_GST_NAME_R0_STR
1110	#endif /* VBOX_WITH_64_BITS_GUESTS */
1111
1112	#undef PGM_SHW_TYPE
1113	#undef PGM_SHW_NAME
1114	#undef PGM_SHW_NAME_RC_STR
1115	#undef PGM_SHW_NAME_R0_STR
1116
1117
1118
1119	/**
1120	* Initiates the paging of VM.
1121	*
1122	* @returns VBox status code.
1123	* @param pVM Pointer to VM structure.
1124	*/
1125	VMMR3DECL(int) PGMR3Init(PVM pVM)
1126	{
1127	LogFlow(("PGMR3Init:\n"));
1128
1129	/*
1130	* Assert alignment and sizes.
1131	*/
1132	AssertRelease(sizeof(pVM->pgm.s) <= sizeof(pVM->pgm.padding));
1133
1134	/*
1135	* Init the structure.
1136	*/
1137	pVM->pgm.s.offVM = RT_OFFSETOF(VM, pgm.s);
1138	pVM->pgm.s.enmShadowMode = PGMMODE_INVALID;
1139	pVM->pgm.s.enmGuestMode = PGMMODE_INVALID;
1140	pVM->pgm.s.enmHostMode = SUPPAGINGMODE_INVALID;
1141	pVM->pgm.s.GCPhysCR3 = NIL_RTGCPHYS;
1142	pVM->pgm.s.GCPhysGstCR3Monitored = NIL_RTGCPHYS;
1143	pVM->pgm.s.fA20Enabled = true;
1144	pVM->pgm.s.GCPhys4MBPSEMask = RT_BIT_64(32) - 1; /* default; checked later */
1145	pVM->pgm.s.pGstPaePdptR3 = NULL;
1146	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
1147	pVM->pgm.s.pGstPaePdptR0 = NIL_RTR0PTR;
1148	#endif
1149	pVM->pgm.s.pGstPaePdptRC = NIL_RTRCPTR;
1150	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.apGstPaePDsR3); i++)
1151	{
1152	pVM->pgm.s.apGstPaePDsR3[i] = NULL;
1153	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
1154	pVM->pgm.s.apGstPaePDsR0[i] = NIL_RTR0PTR;
1155	#endif
1156	pVM->pgm.s.apGstPaePDsRC[i] = NIL_RTRCPTR;
1157	pVM->pgm.s.aGCPhysGstPaePDs[i] = NIL_RTGCPHYS;
1158	pVM->pgm.s.aGCPhysGstPaePDsMonitored[i] = NIL_RTGCPHYS;
1159	}
1160
1161	#ifdef VBOX_STRICT
1162	VMR3AtStateRegister(pVM, pgmR3ResetNoMorePhysWritesFlag, NULL);
1163	#endif
1164
1165	/*
1166	* Get the configured RAM size - to estimate saved state size.
1167	*/
1168	uint64_t cbRam;
1169	int rc = CFGMR3QueryU64(CFGMR3GetRoot(pVM), "RamSize", &cbRam);
1170	if (rc == VERR_CFGM_VALUE_NOT_FOUND)
1171	cbRam = pVM->pgm.s.cbRamSize = 0;
1172	else if (RT_SUCCESS(rc))
1173	{
1174	if (cbRam < PAGE_SIZE)
1175	cbRam = 0;
1176	cbRam = RT_ALIGN_64(cbRam, PAGE_SIZE);
1177	pVM->pgm.s.cbRamSize = (RTUINT)cbRam;
1178	}
1179	else
1180	{
1181	AssertMsgFailed(("Configuration error: Failed to query integer \"RamSize\", rc=%Rrc.\n", rc));
1182	return rc;
1183	}
1184
1185	/*
1186	* Register saved state data unit.
1187	*/
1188	rc = SSMR3RegisterInternal(pVM, "pgm", 1, PGM_SAVED_STATE_VERSION, (size_t)cbRam + sizeof(PGM),
1189	NULL, pgmR3Save, NULL,
1190	NULL, pgmR3Load, NULL);
1191	if (RT_FAILURE(rc))
1192	return rc;
1193
1194	/*
1195	* Initialize the PGM critical section and flush the phys TLBs
1196	*/
1197	rc = PDMR3CritSectInit(pVM, &pVM->pgm.s.CritSect, "PGM");
1198	AssertRCReturn(rc, rc);
1199
1200	PGMR3PhysChunkInvalidateTLB(pVM);
1201	PGMPhysInvalidatePageR3MapTLB(pVM);
1202	PGMPhysInvalidatePageR0MapTLB(pVM);
1203	PGMPhysInvalidatePageGCMapTLB(pVM);
1204
1205	/*
1206	* Trees
1207	*/
1208	rc = MMHyperAlloc(pVM, sizeof(PGMTREES), 0, MM_TAG_PGM, (void **)&pVM->pgm.s.pTreesR3);
1209	if (RT_SUCCESS(rc))
1210	{
1211	pVM->pgm.s.pTreesR0 = MMHyperR3ToR0(pVM, pVM->pgm.s.pTreesR3);
1212	pVM->pgm.s.pTreesRC = MMHyperR3ToRC(pVM, pVM->pgm.s.pTreesR3);
1213
1214	/*
1215	* Alocate the zero page.
1216	*/
1217	rc = MMHyperAlloc(pVM, PAGE_SIZE, PAGE_SIZE, MM_TAG_PGM, &pVM->pgm.s.pvZeroPgR3);
1218	}
1219	if (RT_SUCCESS(rc))
1220	{
1221	pVM->pgm.s.pvZeroPgGC = MMHyperR3ToRC(pVM, pVM->pgm.s.pvZeroPgR3);
1222	pVM->pgm.s.pvZeroPgR0 = MMHyperR3ToR0(pVM, pVM->pgm.s.pvZeroPgR3);
1223	AssertRelease(pVM->pgm.s.pvZeroPgR0 != NIL_RTHCPHYS);
1224	pVM->pgm.s.HCPhysZeroPg = MMR3HyperHCVirt2HCPhys(pVM, pVM->pgm.s.pvZeroPgR3);
1225	AssertRelease(pVM->pgm.s.HCPhysZeroPg != NIL_RTHCPHYS);
1226
1227	/*
1228	* Init the paging.
1229	*/
1230	rc = pgmR3InitPaging(pVM);
1231	}
1232	if (RT_SUCCESS(rc))
1233	{
1234	/*
1235	* Init the page pool.
1236	*/
1237	rc = pgmR3PoolInit(pVM);
1238	}
1239	if (RT_SUCCESS(rc))
1240	{
1241	/*
1242	* Info & statistics
1243	*/
1244	DBGFR3InfoRegisterInternal(pVM, "mode",
1245	"Shows the current paging mode. "
1246	"Recognizes 'all', 'guest', 'shadow' and 'host' as arguments, defaulting to 'all' if nothing's given.",
1247	pgmR3InfoMode);
1248	DBGFR3InfoRegisterInternal(pVM, "pgmcr3",
1249	"Dumps all the entries in the top level paging table. No arguments.",
1250	pgmR3InfoCr3);
1251	DBGFR3InfoRegisterInternal(pVM, "phys",
1252	"Dumps all the physical address ranges. No arguments.",
1253	pgmR3PhysInfo);
1254	DBGFR3InfoRegisterInternal(pVM, "handlers",
1255	"Dumps physical, virtual and hyper virtual handlers. "
1256	"Pass 'phys', 'virt', 'hyper' as argument if only one kind is wanted."
1257	"Add 'nost' if the statistics are unwanted, use together with 'all' or explicit selection.",
1258	pgmR3InfoHandlers);
1259	DBGFR3InfoRegisterInternal(pVM, "mappings",
1260	"Dumps guest mappings.",
1261	pgmR3MapInfo);
1262
1263	STAM_REL_REG(pVM, &pVM->pgm.s.cGuestModeChanges, STAMTYPE_COUNTER, "/PGM/cGuestModeChanges", STAMUNIT_OCCURENCES, "Number of guest mode changes.");
1264	#ifdef VBOX_WITH_STATISTICS
1265	pgmR3InitStats(pVM);
1266	#endif
1267	#ifdef VBOX_WITH_DEBUGGER
1268	/*
1269	* Debugger commands.
1270	*/
1271	static bool fRegisteredCmds = false;
1272	if (!fRegisteredCmds)
1273	{
1274	int rc = DBGCRegisterCommands(&g_aCmds[0], RT_ELEMENTS(g_aCmds));
1275	if (RT_SUCCESS(rc))
1276	fRegisteredCmds = true;
1277	}
1278	#endif
1279	return VINF_SUCCESS;
1280	}
1281
1282	/* Almost no cleanup necessary, MM frees all memory. */
1283	PDMR3CritSectDelete(&pVM->pgm.s.CritSect);
1284
1285	return rc;
1286	}
1287
1288
1289	/**
1290	* Initializes the per-VCPU PGM.
1291	*
1292	* @returns VBox status code.
1293	* @param pVM The VM to operate on.
1294	*/
1295	VMMR3DECL(int) PGMR3InitCPU(PVM pVM)
1296	{
1297	LogFlow(("PGMR3InitCPU\n"));
1298	return VINF_SUCCESS;
1299	}
1300
1301
1302	/**
1303	* Init paging.
1304	*
1305	* Since we need to check what mode the host is operating in before we can choose
1306	* the right paging functions for the host we have to delay this until R0 has
1307	* been initialized.
1308	*
1309	* @returns VBox status code.
1310	* @param pVM VM handle.
1311	*/
1312	static int pgmR3InitPaging(PVM pVM)
1313	{
1314	/*
1315	* Force a recalculation of modes and switcher so everyone gets notified.
1316	*/
1317	pVM->pgm.s.enmShadowMode = PGMMODE_INVALID;
1318	pVM->pgm.s.enmGuestMode = PGMMODE_INVALID;
1319	pVM->pgm.s.enmHostMode = SUPPAGINGMODE_INVALID;
1320
1321	/*
1322	* Allocate static mapping space for whatever the cr3 register
1323	* points to and in the case of PAE mode to the 4 PDs.
1324	*/
1325	int rc = MMR3HyperReserve(pVM, PAGE_SIZE * 5, "CR3 mapping", &pVM->pgm.s.GCPtrCR3Mapping);
1326	if (RT_FAILURE(rc))
1327	{
1328	AssertMsgFailed(("Failed to reserve two pages for cr mapping in HMA, rc=%Rrc\n", rc));
1329	return rc;
1330	}
1331	MMR3HyperReserve(pVM, PAGE_SIZE, "fence", NULL);
1332
1333	/*
1334	* Allocate pages for the three possible intermediate contexts
1335	* (AMD64, PAE and plain 32-Bit). We maintain all three contexts
1336	* for the sake of simplicity. The AMD64 uses the PAE for the
1337	* lower levels, making the total number of pages 11 (3 + 7 + 1).
1338	*
1339	* We assume that two page tables will be enought for the core code
1340	* mappings (HC virtual and identity).
1341	*/
1342	pVM->pgm.s.pInterPD = (PX86PD)MMR3PageAllocLow(pVM);
1343	pVM->pgm.s.apInterPTs[0] = (PX86PT)MMR3PageAllocLow(pVM);
1344	pVM->pgm.s.apInterPTs[1] = (PX86PT)MMR3PageAllocLow(pVM);
1345	pVM->pgm.s.apInterPaePTs[0] = (PX86PTPAE)MMR3PageAlloc(pVM);
1346	pVM->pgm.s.apInterPaePTs[1] = (PX86PTPAE)MMR3PageAlloc(pVM);
1347	pVM->pgm.s.apInterPaePDs[0] = (PX86PDPAE)MMR3PageAlloc(pVM);
1348	pVM->pgm.s.apInterPaePDs[1] = (PX86PDPAE)MMR3PageAlloc(pVM);
1349	pVM->pgm.s.apInterPaePDs[2] = (PX86PDPAE)MMR3PageAlloc(pVM);
1350	pVM->pgm.s.apInterPaePDs[3] = (PX86PDPAE)MMR3PageAlloc(pVM);
1351	pVM->pgm.s.pInterPaePDPT = (PX86PDPT)MMR3PageAllocLow(pVM);
1352	pVM->pgm.s.pInterPaePDPT64 = (PX86PDPT)MMR3PageAllocLow(pVM);
1353	pVM->pgm.s.pInterPaePML4 = (PX86PML4)MMR3PageAllocLow(pVM);
1354	if ( !pVM->pgm.s.pInterPD
1355	\|\| !pVM->pgm.s.apInterPTs[0]
1356	\|\| !pVM->pgm.s.apInterPTs[1]
1357	\|\| !pVM->pgm.s.apInterPaePTs[0]
1358	\|\| !pVM->pgm.s.apInterPaePTs[1]
1359	\|\| !pVM->pgm.s.apInterPaePDs[0]
1360	\|\| !pVM->pgm.s.apInterPaePDs[1]
1361	\|\| !pVM->pgm.s.apInterPaePDs[2]
1362	\|\| !pVM->pgm.s.apInterPaePDs[3]
1363	\|\| !pVM->pgm.s.pInterPaePDPT
1364	\|\| !pVM->pgm.s.pInterPaePDPT64
1365	\|\| !pVM->pgm.s.pInterPaePML4)
1366	{
1367	AssertMsgFailed(("Failed to allocate pages for the intermediate context!\n"));
1368	return VERR_NO_PAGE_MEMORY;
1369	}
1370
1371	pVM->pgm.s.HCPhysInterPD = MMPage2Phys(pVM, pVM->pgm.s.pInterPD);
1372	AssertRelease(pVM->pgm.s.HCPhysInterPD != NIL_RTHCPHYS && !(pVM->pgm.s.HCPhysInterPD & PAGE_OFFSET_MASK));
1373	pVM->pgm.s.HCPhysInterPaePDPT = MMPage2Phys(pVM, pVM->pgm.s.pInterPaePDPT);
1374	AssertRelease(pVM->pgm.s.HCPhysInterPaePDPT != NIL_RTHCPHYS && !(pVM->pgm.s.HCPhysInterPaePDPT & PAGE_OFFSET_MASK));
1375	pVM->pgm.s.HCPhysInterPaePML4 = MMPage2Phys(pVM, pVM->pgm.s.pInterPaePML4);
1376	AssertRelease(pVM->pgm.s.HCPhysInterPaePML4 != NIL_RTHCPHYS && !(pVM->pgm.s.HCPhysInterPaePML4 & PAGE_OFFSET_MASK));
1377
1378	/*
1379	* Initialize the pages, setting up the PML4 and PDPT for repetitive 4GB action.
1380	*/
1381	ASMMemZeroPage(pVM->pgm.s.pInterPD);
1382	ASMMemZeroPage(pVM->pgm.s.apInterPTs[0]);
1383	ASMMemZeroPage(pVM->pgm.s.apInterPTs[1]);
1384
1385	ASMMemZeroPage(pVM->pgm.s.apInterPaePTs[0]);
1386	ASMMemZeroPage(pVM->pgm.s.apInterPaePTs[1]);
1387
1388	ASMMemZeroPage(pVM->pgm.s.pInterPaePDPT);
1389	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.apInterPaePDs); i++)
1390	{
1391	ASMMemZeroPage(pVM->pgm.s.apInterPaePDs[i]);
1392	pVM->pgm.s.pInterPaePDPT->a[i].u = X86_PDPE_P \| PGM_PLXFLAGS_PERMANENT
1393	\| MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[i]);
1394	}
1395
1396	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.pInterPaePDPT64->a); i++)
1397	{
1398	const unsigned iPD = i % RT_ELEMENTS(pVM->pgm.s.apInterPaePDs);
1399	pVM->pgm.s.pInterPaePDPT64->a[i].u = X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_A \| PGM_PLXFLAGS_PERMANENT
1400	\| MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[iPD]);
1401	}
1402
1403	RTHCPHYS HCPhysInterPaePDPT64 = MMPage2Phys(pVM, pVM->pgm.s.pInterPaePDPT64);
1404	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.pInterPaePML4->a); i++)
1405	pVM->pgm.s.pInterPaePML4->a[i].u = X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_A \| PGM_PLXFLAGS_PERMANENT
1406	\| HCPhysInterPaePDPT64;
1407
1408	/*
1409	* Allocate pages for the three possible guest contexts (AMD64, PAE and plain 32-Bit).
1410	* We allocate pages for all three posibilities in order to simplify mappings and
1411	* avoid resource failure during mode switches. So, we need to cover all levels of the
1412	* of the first 4GB down to PD level.
1413	* As with the intermediate context, AMD64 uses the PAE PDPT and PDs.
1414	*/
1415	pVM->pgm.s.pShw32BitPdR3 = (PX86PD)MMR3PageAllocLow(pVM);
1416	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
1417	pVM->pgm.s.pShw32BitPdR0 = (uintptr_t)pVM->pgm.s.pShw32BitPdR3;
1418	#endif
1419	pVM->pgm.s.apShwPaePDsR3[0] = (PX86PDPAE)MMR3PageAlloc(pVM);
1420	pVM->pgm.s.apShwPaePDsR3[1] = (PX86PDPAE)MMR3PageAlloc(pVM);
1421	AssertRelease((uintptr_t)pVM->pgm.s.apShwPaePDsR3[0] + PAGE_SIZE == (uintptr_t)pVM->pgm.s.apShwPaePDsR3[1]);
1422	pVM->pgm.s.apShwPaePDsR3[2] = (PX86PDPAE)MMR3PageAlloc(pVM);
1423	AssertRelease((uintptr_t)pVM->pgm.s.apShwPaePDsR3[1] + PAGE_SIZE == (uintptr_t)pVM->pgm.s.apShwPaePDsR3[2]);
1424	pVM->pgm.s.apShwPaePDsR3[3] = (PX86PDPAE)MMR3PageAlloc(pVM);
1425	AssertRelease((uintptr_t)pVM->pgm.s.apShwPaePDsR3[2] + PAGE_SIZE == (uintptr_t)pVM->pgm.s.apShwPaePDsR3[3]);
1426	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
1427	pVM->pgm.s.apShwPaePDsR0[0] = (uintptr_t)pVM->pgm.s.apShwPaePDsR3[0];
1428	pVM->pgm.s.apShwPaePDsR0[1] = (uintptr_t)pVM->pgm.s.apShwPaePDsR3[1];
1429	pVM->pgm.s.apShwPaePDsR0[2] = (uintptr_t)pVM->pgm.s.apShwPaePDsR3[2];
1430	pVM->pgm.s.apShwPaePDsR0[3] = (uintptr_t)pVM->pgm.s.apShwPaePDsR3[3];
1431	#endif
1432	pVM->pgm.s.pShwPaePdptR3 = (PX86PDPT)MMR3PageAllocLow(pVM);
1433	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
1434	pVM->pgm.s.pShwPaePdptR0 = (uintptr_t)pVM->pgm.s.pShwPaePdptR3;
1435	#endif
1436	pVM->pgm.s.pShwNestedRootR3 = MMR3PageAllocLow(pVM);
1437	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
1438	pVM->pgm.s.pShwNestedRootR0 = (uintptr_t)pVM->pgm.s.pShwNestedRootR3;
1439	#endif
1440
1441	if ( !pVM->pgm.s.pShw32BitPdR3
1442	\|\| !pVM->pgm.s.apShwPaePDsR3[0]
1443	\|\| !pVM->pgm.s.apShwPaePDsR3[1]
1444	\|\| !pVM->pgm.s.apShwPaePDsR3[2]
1445	\|\| !pVM->pgm.s.apShwPaePDsR3[3]
1446	\|\| !pVM->pgm.s.pShwPaePdptR3
1447	\|\| !pVM->pgm.s.pShwNestedRootR3)
1448	{
1449	AssertMsgFailed(("Failed to allocate pages for the intermediate context!\n"));
1450	return VERR_NO_PAGE_MEMORY;
1451	}
1452
1453	/* get physical addresses. */
1454	pVM->pgm.s.HCPhysShw32BitPD = MMPage2Phys(pVM, pVM->pgm.s.pShw32BitPdR3);
1455	Assert(MMPagePhys2Page(pVM, pVM->pgm.s.HCPhysShw32BitPD) == pVM->pgm.s.pShw32BitPdR3);
1456	pVM->pgm.s.aHCPhysPaePDs[0] = MMPage2Phys(pVM, pVM->pgm.s.apShwPaePDsR3[0]);
1457	pVM->pgm.s.aHCPhysPaePDs[1] = MMPage2Phys(pVM, pVM->pgm.s.apShwPaePDsR3[1]);
1458	pVM->pgm.s.aHCPhysPaePDs[2] = MMPage2Phys(pVM, pVM->pgm.s.apShwPaePDsR3[2]);
1459	pVM->pgm.s.aHCPhysPaePDs[3] = MMPage2Phys(pVM, pVM->pgm.s.apShwPaePDsR3[3]);
1460	pVM->pgm.s.HCPhysShwPaePdpt = MMPage2Phys(pVM, pVM->pgm.s.pShwPaePdptR3);
1461	pVM->pgm.s.HCPhysShwNestedRoot = MMPage2Phys(pVM, pVM->pgm.s.pShwNestedRootR3);
1462
1463	/*
1464	* Initialize the pages, setting up the PML4 and PDPT for action below 4GB.
1465	*/
1466	ASMMemZero32(pVM->pgm.s.pShw32BitPdR3, PAGE_SIZE);
1467	ASMMemZero32(pVM->pgm.s.pShwPaePdptR3, PAGE_SIZE);
1468	ASMMemZero32(pVM->pgm.s.pShwNestedRootR3, PAGE_SIZE);
1469	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.apShwPaePDsR3); i++)
1470	{
1471	ASMMemZero32(pVM->pgm.s.apShwPaePDsR3[i], PAGE_SIZE);
1472	pVM->pgm.s.pShwPaePdptR3->a[i].u = X86_PDPE_P \| PGM_PLXFLAGS_PERMANENT \| pVM->pgm.s.aHCPhysPaePDs[i];
1473	/* The flags will be corrected when entering and leaving long mode. */
1474	}
1475
1476	CPUMSetHyperCR3(pVM, (uint32_t)pVM->pgm.s.HCPhysShw32BitPD);
1477
1478	/*
1479	* Initialize paging workers and mode from current host mode
1480	* and the guest running in real mode.
1481	*/
1482	pVM->pgm.s.enmHostMode = SUPGetPagingMode();
1483	switch (pVM->pgm.s.enmHostMode)
1484	{
1485	case SUPPAGINGMODE_32_BIT:
1486	case SUPPAGINGMODE_32_BIT_GLOBAL:
1487	case SUPPAGINGMODE_PAE:
1488	case SUPPAGINGMODE_PAE_GLOBAL:
1489	case SUPPAGINGMODE_PAE_NX:
1490	case SUPPAGINGMODE_PAE_GLOBAL_NX:
1491	break;
1492
1493	case SUPPAGINGMODE_AMD64:
1494	case SUPPAGINGMODE_AMD64_GLOBAL:
1495	case SUPPAGINGMODE_AMD64_NX:
1496	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
1497	#ifndef VBOX_WITH_HYBIRD_32BIT_KERNEL
1498	if (ARCH_BITS != 64)
1499	{
1500	AssertMsgFailed(("Host mode %d (64-bit) is not supported by non-64bit builds\n", pVM->pgm.s.enmHostMode));
1501	LogRel(("Host mode %d (64-bit) is not supported by non-64bit builds\n", pVM->pgm.s.enmHostMode));
1502	return VERR_PGM_UNSUPPORTED_HOST_PAGING_MODE;
1503	}
1504	#endif
1505	break;
1506	default:
1507	AssertMsgFailed(("Host mode %d is not supported\n", pVM->pgm.s.enmHostMode));
1508	return VERR_PGM_UNSUPPORTED_HOST_PAGING_MODE;
1509	}
1510	rc = pgmR3ModeDataInit(pVM, false /* don't resolve GC and R0 syms yet */);
1511	if (RT_SUCCESS(rc))
1512	rc = PGMR3ChangeMode(pVM, PGMMODE_REAL);
1513	if (RT_SUCCESS(rc))
1514	{
1515	LogFlow(("pgmR3InitPaging: returns successfully\n"));
1516	#if HC_ARCH_BITS == 64
1517	LogRel(("Debug: HCPhysShw32BitPD=%RHp aHCPhysPaePDs={%RHp,%RHp,%RHp,%RHp} HCPhysShwPaePdpt=%RHp HCPhysShwPaePml4=%RHp\n",
1518	pVM->pgm.s.HCPhysShw32BitPD,
1519	pVM->pgm.s.aHCPhysPaePDs[0], pVM->pgm.s.aHCPhysPaePDs[1], pVM->pgm.s.aHCPhysPaePDs[2], pVM->pgm.s.aHCPhysPaePDs[3],
1520	pVM->pgm.s.HCPhysShwPaePdpt,
1521	pVM->pgm.s.HCPhysShwPaePml4));
1522	LogRel(("Debug: HCPhysInterPD=%RHp HCPhysInterPaePDPT=%RHp HCPhysInterPaePML4=%RHp\n",
1523	pVM->pgm.s.HCPhysInterPD, pVM->pgm.s.HCPhysInterPaePDPT, pVM->pgm.s.HCPhysInterPaePML4));
1524	LogRel(("Debug: apInterPTs={%RHp,%RHp} apInterPaePTs={%RHp,%RHp} apInterPaePDs={%RHp,%RHp,%RHp,%RHp} pInterPaePDPT64=%RHp\n",
1525	MMPage2Phys(pVM, pVM->pgm.s.apInterPTs[0]), MMPage2Phys(pVM, pVM->pgm.s.apInterPTs[1]),
1526	MMPage2Phys(pVM, pVM->pgm.s.apInterPaePTs[0]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePTs[1]),
1527	MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[0]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[1]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[2]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[3]),
1528	MMPage2Phys(pVM, pVM->pgm.s.pInterPaePDPT64)));
1529	#endif
1530
1531	return VINF_SUCCESS;
1532	}
1533
1534	LogFlow(("pgmR3InitPaging: returns %Rrc\n", rc));
1535	return rc;
1536	}
1537
1538
1539	#ifdef VBOX_WITH_STATISTICS
1540	/**
1541	* Init statistics
1542	*/
1543	static void pgmR3InitStats(PVM pVM)
1544	{
1545	PPGM pPGM = &pVM->pgm.s;
1546	unsigned i;
1547
1548	/*
1549	* Note! The layout of this function matches the member layout exactly!
1550	*/
1551
1552	/* Common - misc variables */
1553	STAM_REG(pVM, &pPGM->cAllPages, STAMTYPE_U32, "/PGM/Page/cAllPages", STAMUNIT_OCCURENCES, "The total number of pages.");
1554	STAM_REG(pVM, &pPGM->cPrivatePages, STAMTYPE_U32, "/PGM/Page/cPrivatePages", STAMUNIT_OCCURENCES, "The number of private pages.");
1555	STAM_REG(pVM, &pPGM->cSharedPages, STAMTYPE_U32, "/PGM/Page/cSharedPages", STAMUNIT_OCCURENCES, "The number of shared pages.");
1556	STAM_REG(pVM, &pPGM->cZeroPages, STAMTYPE_U32, "/PGM/Page/cZeroPages", STAMUNIT_OCCURENCES, "The number of zero backed pages.");
1557	STAM_REG(pVM, &pPGM->ChunkR3Map.c, STAMTYPE_U32, "/PGM/ChunkR3Map/c", STAMUNIT_OCCURENCES, "Number of mapped chunks.");
1558	STAM_REG(pVM, &pPGM->ChunkR3Map.cMax, STAMTYPE_U32, "/PGM/ChunkR3Map/cMax", STAMUNIT_OCCURENCES, "Maximum number of mapped chunks.");
1559
1560	/* Common - stats */
1561	#ifdef PGMPOOL_WITH_GCPHYS_TRACKING
1562	STAM_REG(pVM, &pPGM->StatTrackVirgin, STAMTYPE_COUNTER, "/PGM/Track/Virgin", STAMUNIT_OCCURENCES, "The number of first time shadowings");
1563	STAM_REG(pVM, &pPGM->StatTrackAliased, STAMTYPE_COUNTER, "/PGM/Track/Aliased", STAMUNIT_OCCURENCES, "The number of times switching to cRef2, i.e. the page is being shadowed by two PTs.");
1564	STAM_REG(pVM, &pPGM->StatTrackAliasedMany, STAMTYPE_COUNTER, "/PGM/Track/AliasedMany", STAMUNIT_OCCURENCES, "The number of times we're tracking using cRef2.");
1565	STAM_REG(pVM, &pPGM->StatTrackAliasedLots, STAMTYPE_COUNTER, "/PGM/Track/AliasedLots", STAMUNIT_OCCURENCES, "The number of times we're hitting pages which has overflowed cRef2");
1566	STAM_REG(pVM, &pPGM->StatTrackOverflows, STAMTYPE_COUNTER, "/PGM/Track/Overflows", STAMUNIT_OCCURENCES, "The number of times the extent list grows to long.");
1567	STAM_REG(pVM, &pPGM->StatTrackDeref, STAMTYPE_PROFILE, "/PGM/Track/Deref", STAMUNIT_OCCURENCES, "Profiling of SyncPageWorkerTrackDeref (expensive).");
1568	#endif
1569	for (i = 0; i < RT_ELEMENTS(pPGM->StatSyncPtPD); i++)
1570	STAMR3RegisterF(pVM, &pPGM->StatSyncPtPD[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
1571	"The number of SyncPT per PD n.", "/PGM/PDSyncPT/%04X", i);
1572	for (i = 0; i < RT_ELEMENTS(pPGM->StatSyncPagePD); i++)
1573	STAMR3RegisterF(pVM, &pPGM->StatSyncPagePD[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
1574	"The number of SyncPage per PD n.", "/PGM/PDSyncPage/%04X", i);
1575
1576	/* R3 only: */
1577	STAM_REG(pVM, &pPGM->StatR3DetectedConflicts, STAMTYPE_COUNTER, "/PGM/R3/DetectedConflicts", STAMUNIT_OCCURENCES, "The number of times PGMR3CheckMappingConflicts() detected a conflict.");
1578	STAM_REG(pVM, &pPGM->StatR3ResolveConflict, STAMTYPE_PROFILE, "/PGM/R3/ResolveConflict", STAMUNIT_TICKS_PER_CALL, "pgmR3SyncPTResolveConflict() profiling (includes the entire relocation).");
1579	STAM_REG(pVM, &pPGM->StatR3GuestPDWrite, STAMTYPE_COUNTER, "/PGM/R3/PDWrite", STAMUNIT_OCCURENCES, "The total number of times pgmHCGuestPDWriteHandler() was called.");
1580	STAM_REG(pVM, &pPGM->StatR3GuestPDWriteConflict, STAMTYPE_COUNTER, "/PGM/R3/PDWriteConflict", STAMUNIT_OCCURENCES, "The number of times pgmHCGuestPDWriteHandler() detected a conflict.");
1581	STAM_REG(pVM, &pPGM->StatR3DynRamTotal, STAMTYPE_COUNTER, "/PGM/DynAlloc/TotalAlloc", STAMUNIT_MEGABYTES, "Allocated MBs of guest ram.");
1582	STAM_REG(pVM, &pPGM->StatR3DynRamGrow, STAMTYPE_COUNTER, "/PGM/DynAlloc/Grow", STAMUNIT_OCCURENCES, "Nr of pgmr3PhysGrowRange calls.");
1583
1584	/* GC only: */
1585	STAM_REG(pVM, &pPGM->StatRCDynMapCacheHits, STAMTYPE_COUNTER, "/PGM/RC/DynMapCache/Hits" , STAMUNIT_OCCURENCES, "Number of dynamic page mapping cache hits.");
1586	STAM_REG(pVM, &pPGM->StatRCDynMapCacheMisses, STAMTYPE_COUNTER, "/PGM/RC/DynMapCache/Misses" , STAMUNIT_OCCURENCES, "Number of dynamic page mapping cache misses.");
1587	STAM_REG(pVM, &pPGM->StatRCInvlPgConflict, STAMTYPE_COUNTER, "/PGM/RC/InvlPgConflict", STAMUNIT_OCCURENCES, "Number of times PGMInvalidatePage() detected a mapping conflict.");
1588	STAM_REG(pVM, &pPGM->StatRCInvlPgSyncMonCR3, STAMTYPE_COUNTER, "/PGM/RC/InvlPgSyncMonitorCR3", STAMUNIT_OCCURENCES, "Number of times PGMInvalidatePage() ran into PGM_SYNC_MONITOR_CR3.");
1589
1590	/* RZ only: */
1591	STAM_REG(pVM, &pPGM->StatRZTrap0e, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMTrap0eHandler() body.");
1592	STAM_REG(pVM, &pPGM->StatRZTrap0eTimeCheckPageFault, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time/CheckPageFault", STAMUNIT_TICKS_PER_CALL, "Profiling of checking for dirty/access emulation faults.");
1593	STAM_REG(pVM, &pPGM->StatRZTrap0eTimeSyncPT, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time/SyncPT", STAMUNIT_TICKS_PER_CALL, "Profiling of lazy page table syncing.");
1594	STAM_REG(pVM, &pPGM->StatRZTrap0eTimeMapping, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time/Mapping", STAMUNIT_TICKS_PER_CALL, "Profiling of checking virtual mappings.");
1595	STAM_REG(pVM, &pPGM->StatRZTrap0eTimeOutOfSync, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time/OutOfSync", STAMUNIT_TICKS_PER_CALL, "Profiling of out of sync page handling.");
1596	STAM_REG(pVM, &pPGM->StatRZTrap0eTimeHandlers, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time/Handlers", STAMUNIT_TICKS_PER_CALL, "Profiling of checking handlers.");
1597	STAM_REG(pVM, &pPGM->StatRZTrap0eTime2CSAM, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time2/CSAM", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is CSAM.");
1598	STAM_REG(pVM, &pPGM->StatRZTrap0eTime2DirtyAndAccessed, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time2/DirtyAndAccessedBits", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is dirty and/or accessed bit emulation.");
1599	STAM_REG(pVM, &pPGM->StatRZTrap0eTime2GuestTrap, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time2/GuestTrap", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is a guest trap.");
1600	STAM_REG(pVM, &pPGM->StatRZTrap0eTime2HndPhys, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time2/HandlerPhysical", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is a physical handler.");
1601	STAM_REG(pVM, &pPGM->StatRZTrap0eTime2HndVirt, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time2/HandlerVirtual", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is a virtual handler.");
1602	STAM_REG(pVM, &pPGM->StatRZTrap0eTime2HndUnhandled, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time2/HandlerUnhandled", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is access outside the monitored areas of a monitored page.");
1603	STAM_REG(pVM, &pPGM->StatRZTrap0eTime2Misc, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time2/Misc", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is not known.");
1604	STAM_REG(pVM, &pPGM->StatRZTrap0eTime2OutOfSync, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time2/OutOfSync", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is an out-of-sync page.");
1605	STAM_REG(pVM, &pPGM->StatRZTrap0eTime2OutOfSyncHndPhys, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time2/OutOfSyncHndPhys", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is an out-of-sync physical handler page.");
1606	STAM_REG(pVM, &pPGM->StatRZTrap0eTime2OutOfSyncHndVirt, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time2/OutOfSyncHndVirt", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is an out-of-sync virtual handler page.");
1607	STAM_REG(pVM, &pPGM->StatRZTrap0eTime2OutOfSyncHndObs, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time2/OutOfSyncObsHnd", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is an obsolete handler page.");
1608	STAM_REG(pVM, &pPGM->StatRZTrap0eTime2SyncPT, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time2/SyncPT", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is lazy syncing of a PT.");
1609	STAM_REG(pVM, &pPGM->StatRZTrap0eConflicts, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Conflicts", STAMUNIT_OCCURENCES, "The number of times #PF was caused by an undetected conflict.");
1610	STAM_REG(pVM, &pPGM->StatRZTrap0eHandlersMapping, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Handlers/Mapping", STAMUNIT_OCCURENCES, "Number of traps due to access handlers in mappings.");
1611	STAM_REG(pVM, &pPGM->StatRZTrap0eHandlersOutOfSync, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Handlers/OutOfSync", STAMUNIT_OCCURENCES, "Number of traps due to out-of-sync handled pages.");
1612	STAM_REG(pVM, &pPGM->StatRZTrap0eHandlersPhysical, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Handlers/Physical", STAMUNIT_OCCURENCES, "Number of traps due to physical access handlers.");
1613	STAM_REG(pVM, &pPGM->StatRZTrap0eHandlersVirtual, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Handlers/Virtual", STAMUNIT_OCCURENCES, "Number of traps due to virtual access handlers.");
1614	STAM_REG(pVM, &pPGM->StatRZTrap0eHandlersVirtualByPhys, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Handlers/VirtualByPhys", STAMUNIT_OCCURENCES, "Number of traps due to virtual access handlers by physical address.");
1615	STAM_REG(pVM, &pPGM->StatRZTrap0eHandlersVirtualUnmarked,STAMTYPE_COUNTER,"/PGM/RZ/Trap0e/Handlers/VirtualUnmarked",STAMUNIT_OCCURENCES, "Number of traps due to virtual access handlers by virtual address (without proper physical flags).");
1616	STAM_REG(pVM, &pPGM->StatRZTrap0eHandlersUnhandled, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Handlers/Unhandled", STAMUNIT_OCCURENCES, "Number of traps due to access outside range of monitored page(s).");
1617	STAM_REG(pVM, &pPGM->StatRZTrap0eHandlersInvalid, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Handlers/Invalid", STAMUNIT_OCCURENCES, "Number of traps due to access to invalid physical memory.");
1618	STAM_REG(pVM, &pPGM->StatRZTrap0eUSNotPresentRead, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Err/User/NPRead", STAMUNIT_OCCURENCES, "Number of user mode not present read page faults.");
1619	STAM_REG(pVM, &pPGM->StatRZTrap0eUSNotPresentWrite, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Err/User/NPWrite", STAMUNIT_OCCURENCES, "Number of user mode not present write page faults.");
1620	STAM_REG(pVM, &pPGM->StatRZTrap0eUSWrite, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Err/User/Write", STAMUNIT_OCCURENCES, "Number of user mode write page faults.");
1621	STAM_REG(pVM, &pPGM->StatRZTrap0eUSReserved, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Err/User/Reserved", STAMUNIT_OCCURENCES, "Number of user mode reserved bit page faults.");
1622	STAM_REG(pVM, &pPGM->StatRZTrap0eUSNXE, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Err/User/NXE", STAMUNIT_OCCURENCES, "Number of user mode NXE page faults.");
1623	STAM_REG(pVM, &pPGM->StatRZTrap0eUSRead, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Err/User/Read", STAMUNIT_OCCURENCES, "Number of user mode read page faults.");
1624	STAM_REG(pVM, &pPGM->StatRZTrap0eSVNotPresentRead, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Err/Supervisor/NPRead", STAMUNIT_OCCURENCES, "Number of supervisor mode not present read page faults.");
1625	STAM_REG(pVM, &pPGM->StatRZTrap0eSVNotPresentWrite, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Err/Supervisor/NPWrite", STAMUNIT_OCCURENCES, "Number of supervisor mode not present write page faults.");
1626	STAM_REG(pVM, &pPGM->StatRZTrap0eSVWrite, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Err/Supervisor/Write", STAMUNIT_OCCURENCES, "Number of supervisor mode write page faults.");
1627	STAM_REG(pVM, &pPGM->StatRZTrap0eSVReserved, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Err/Supervisor/Reserved", STAMUNIT_OCCURENCES, "Number of supervisor mode reserved bit page faults.");
1628	STAM_REG(pVM, &pPGM->StatRZTrap0eSNXE, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Err/Supervisor/NXE", STAMUNIT_OCCURENCES, "Number of supervisor mode NXE page faults.");
1629	STAM_REG(pVM, &pPGM->StatRZTrap0eGuestPF, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/GuestPF", STAMUNIT_OCCURENCES, "Number of real guest page faults.");
1630	STAM_REG(pVM, &pPGM->StatRZTrap0eGuestPFUnh, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/GuestPF/Unhandled", STAMUNIT_OCCURENCES, "Number of real guest page faults from the 'unhandled' case.");
1631	STAM_REG(pVM, &pPGM->StatRZTrap0eGuestPFMapping, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/GuestPF/InMapping", STAMUNIT_OCCURENCES, "Number of real guest page faults in a mapping.");
1632	STAM_REG(pVM, &pPGM->StatRZTrap0eWPEmulInRZ, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/WP/InRZ", STAMUNIT_OCCURENCES, "Number of guest page faults due to X86_CR0_WP emulation.");
1633	STAM_REG(pVM, &pPGM->StatRZTrap0eWPEmulToR3, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/WP/ToR3", STAMUNIT_OCCURENCES, "Number of guest page faults due to X86_CR0_WP emulation (forward to R3 for emulation).");
1634	for (i = 0; i < RT_ELEMENTS(pPGM->StatRZTrap0ePD); i++)
1635	STAMR3RegisterF(pVM, &pPGM->StatRZTrap0ePD[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
1636	"The number of traps in page directory n.", "/PGM/RZ/Trap0e/PD/%04X", i);
1637	STAM_REG(pVM, &pPGM->StatRZGuestCR3WriteHandled, STAMTYPE_COUNTER, "/PGM/RZ/CR3WriteHandled", STAMUNIT_OCCURENCES, "The number of times the Guest CR3 change was successfully handled.");
1638	STAM_REG(pVM, &pPGM->StatRZGuestCR3WriteUnhandled, STAMTYPE_COUNTER, "/PGM/RZ/CR3WriteUnhandled", STAMUNIT_OCCURENCES, "The number of times the Guest CR3 change was passed back to the recompiler.");
1639	STAM_REG(pVM, &pPGM->StatRZGuestCR3WriteConflict, STAMTYPE_COUNTER, "/PGM/RZ/CR3WriteConflict", STAMUNIT_OCCURENCES, "The number of times the Guest CR3 monitoring detected a conflict.");
1640	STAM_REG(pVM, &pPGM->StatRZGuestROMWriteHandled, STAMTYPE_COUNTER, "/PGM/RZ/ROMWriteHandled", STAMUNIT_OCCURENCES, "The number of times the Guest ROM change was successfully handled.");
1641	STAM_REG(pVM, &pPGM->StatRZGuestROMWriteUnhandled, STAMTYPE_COUNTER, "/PGM/RZ/ROMWriteUnhandled", STAMUNIT_OCCURENCES, "The number of times the Guest ROM change was passed back to the recompiler.");
1642
1643	/* HC only: */
1644
1645	/* RZ & R3: */
1646	STAM_REG(pVM, &pPGM->StatRZSyncCR3, STAMTYPE_PROFILE, "/PGM/RZ/SyncCR3", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMSyncCR3() body.");
1647	STAM_REG(pVM, &pPGM->StatRZSyncCR3Handlers, STAMTYPE_PROFILE, "/PGM/RZ/SyncCR3/Handlers", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMSyncCR3() update handler section.");
1648	STAM_REG(pVM, &pPGM->StatRZSyncCR3HandlerVirtualUpdate, STAMTYPE_PROFILE, "/PGM/RZ/SyncCR3/Handlers/VirtualUpdate", STAMUNIT_TICKS_PER_CALL, "Profiling of the virtual handler updates.");
1649	STAM_REG(pVM, &pPGM->StatRZSyncCR3HandlerVirtualReset, STAMTYPE_PROFILE, "/PGM/RZ/SyncCR3/Handlers/VirtualReset", STAMUNIT_TICKS_PER_CALL, "Profiling of the virtual handler resets.");
1650	STAM_REG(pVM, &pPGM->StatRZSyncCR3Global, STAMTYPE_COUNTER, "/PGM/RZ/SyncCR3/Global", STAMUNIT_OCCURENCES, "The number of global CR3 syncs.");
1651	STAM_REG(pVM, &pPGM->StatRZSyncCR3NotGlobal, STAMTYPE_COUNTER, "/PGM/RZ/SyncCR3/NotGlobal", STAMUNIT_OCCURENCES, "The number of non-global CR3 syncs.");
1652	STAM_REG(pVM, &pPGM->StatRZSyncCR3DstCacheHit, STAMTYPE_COUNTER, "/PGM/RZ/SyncCR3/DstChacheHit", STAMUNIT_OCCURENCES, "The number of times we got some kind of a cache hit.");
1653	STAM_REG(pVM, &pPGM->StatRZSyncCR3DstFreed, STAMTYPE_COUNTER, "/PGM/RZ/SyncCR3/DstFreed", STAMUNIT_OCCURENCES, "The number of times we've had to free a shadow entry.");
1654	STAM_REG(pVM, &pPGM->StatRZSyncCR3DstFreedSrcNP, STAMTYPE_COUNTER, "/PGM/RZ/SyncCR3/DstFreedSrcNP", STAMUNIT_OCCURENCES, "The number of times we've had to free a shadow entry for which the source entry was not present.");
1655	STAM_REG(pVM, &pPGM->StatRZSyncCR3DstNotPresent, STAMTYPE_COUNTER, "/PGM/RZ/SyncCR3/DstNotPresent", STAMUNIT_OCCURENCES, "The number of times we've encountered a not present shadow entry for a present guest entry.");
1656	STAM_REG(pVM, &pPGM->StatRZSyncCR3DstSkippedGlobalPD, STAMTYPE_COUNTER, "/PGM/RZ/SyncCR3/DstSkippedGlobalPD", STAMUNIT_OCCURENCES, "The number of times a global page directory wasn't flushed.");
1657	STAM_REG(pVM, &pPGM->StatRZSyncCR3DstSkippedGlobalPT, STAMTYPE_COUNTER, "/PGM/RZ/SyncCR3/DstSkippedGlobalPT", STAMUNIT_OCCURENCES, "The number of times a page table with only global entries wasn't flushed.");
1658	STAM_REG(pVM, &pPGM->StatRZSyncPT, STAMTYPE_PROFILE, "/PGM/RZ/SyncPT", STAMUNIT_TICKS_PER_CALL, "Profiling of the pfnSyncPT() body.");
1659	STAM_REG(pVM, &pPGM->StatRZSyncPTFailed, STAMTYPE_COUNTER, "/PGM/RZ/SyncPT/Failed", STAMUNIT_OCCURENCES, "The number of times pfnSyncPT() failed.");
1660	STAM_REG(pVM, &pPGM->StatRZSyncPT4K, STAMTYPE_COUNTER, "/PGM/RZ/SyncPT/4K", STAMUNIT_OCCURENCES, "Nr of 4K PT syncs");
1661	STAM_REG(pVM, &pPGM->StatRZSyncPT4M, STAMTYPE_COUNTER, "/PGM/RZ/SyncPT/4M", STAMUNIT_OCCURENCES, "Nr of 4M PT syncs");
1662	STAM_REG(pVM, &pPGM->StatRZSyncPagePDNAs, STAMTYPE_COUNTER, "/PGM/RZ/SyncPagePDNAs", STAMUNIT_OCCURENCES, "The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit.");
1663	STAM_REG(pVM, &pPGM->StatRZSyncPagePDOutOfSync, STAMTYPE_COUNTER, "/PGM/RZ/SyncPagePDOutOfSync", STAMUNIT_OCCURENCES, "The number of time we've encountered an out-of-sync PD in SyncPage.");
1664	STAM_REG(pVM, &pPGM->StatRZAccessedPage, STAMTYPE_COUNTER, "/PGM/RZ/AccessedPage", STAMUNIT_OCCURENCES, "The number of pages marked not present for accessed bit emulation.");
1665	STAM_REG(pVM, &pPGM->StatRZDirtyBitTracking, STAMTYPE_PROFILE, "/PGM/RZ/DirtyPage", STAMUNIT_TICKS_PER_CALL, "Profiling the dirty bit tracking in CheckPageFault().");
1666	STAM_REG(pVM, &pPGM->StatRZDirtyPage, STAMTYPE_COUNTER, "/PGM/RZ/DirtyPage/Mark", STAMUNIT_OCCURENCES, "The number of pages marked read-only for dirty bit tracking.");
1667	STAM_REG(pVM, &pPGM->StatRZDirtyPageBig, STAMTYPE_COUNTER, "/PGM/RZ/DirtyPage/MarkBig", STAMUNIT_OCCURENCES, "The number of 4MB pages marked read-only for dirty bit tracking.");
1668	STAM_REG(pVM, &pPGM->StatRZDirtyPageSkipped, STAMTYPE_COUNTER, "/PGM/RZ/DirtyPage/Skipped", STAMUNIT_OCCURENCES, "The number of pages already dirty or readonly.");
1669	STAM_REG(pVM, &pPGM->StatRZDirtyPageTrap, STAMTYPE_COUNTER, "/PGM/RZ/DirtyPage/Trap", STAMUNIT_OCCURENCES, "The number of traps generated for dirty bit tracking.");
1670	STAM_REG(pVM, &pPGM->StatRZDirtiedPage, STAMTYPE_COUNTER, "/PGM/RZ/DirtyPage/SetDirty", STAMUNIT_OCCURENCES, "The number of pages marked dirty because of write accesses.");
1671	STAM_REG(pVM, &pPGM->StatRZDirtyTrackRealPF, STAMTYPE_COUNTER, "/PGM/RZ/DirtyPage/RealPF", STAMUNIT_OCCURENCES, "The number of real pages faults during dirty bit tracking.");
1672	STAM_REG(pVM, &pPGM->StatRZPageAlreadyDirty, STAMTYPE_COUNTER, "/PGM/RZ/DirtyPage/AlreadySet", STAMUNIT_OCCURENCES, "The number of pages already marked dirty because of write accesses.");
1673	STAM_REG(pVM, &pPGM->StatRZInvalidatePage, STAMTYPE_PROFILE, "/PGM/RZ/InvalidatePage", STAMUNIT_TICKS_PER_CALL, "PGMInvalidatePage() profiling.");
1674	STAM_REG(pVM, &pPGM->StatRZInvalidatePage4KBPages, STAMTYPE_COUNTER, "/PGM/RZ/InvalidatePage/4KBPages", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was called for a 4KB page.");
1675	STAM_REG(pVM, &pPGM->StatRZInvalidatePage4MBPages, STAMTYPE_COUNTER, "/PGM/RZ/InvalidatePage/4MBPages", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was called for a 4MB page.");
1676	STAM_REG(pVM, &pPGM->StatRZInvalidatePage4MBPagesSkip, STAMTYPE_COUNTER, "/PGM/RZ/InvalidatePage/4MBPagesSkip",STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() skipped a 4MB page.");
1677	STAM_REG(pVM, &pPGM->StatRZInvalidatePagePDMappings, STAMTYPE_COUNTER, "/PGM/RZ/InvalidatePage/PDMappings", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict).");
1678	STAM_REG(pVM, &pPGM->StatRZInvalidatePagePDNAs, STAMTYPE_COUNTER, "/PGM/RZ/InvalidatePage/PDNAs", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was called for a not accessed page directory.");
1679	STAM_REG(pVM, &pPGM->StatRZInvalidatePagePDNPs, STAMTYPE_COUNTER, "/PGM/RZ/InvalidatePage/PDNPs", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was called for a not present page directory.");
1680	STAM_REG(pVM, &pPGM->StatRZInvalidatePagePDOutOfSync, STAMTYPE_COUNTER, "/PGM/RZ/InvalidatePage/PDOutOfSync", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was called for an out of sync page directory.");
1681	STAM_REG(pVM, &pPGM->StatRZInvalidatePageSkipped, STAMTYPE_COUNTER, "/PGM/RZ/InvalidatePage/Skipped", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3.");
1682	STAM_REG(pVM, &pPGM->StatRZVirtHandlerSearchByPhys, STAMTYPE_PROFILE, "/PGM/RZ/VirtHandlerSearchByPhys", STAMUNIT_TICKS_PER_CALL, "Profiling of pgmHandlerVirtualFindByPhysAddr.");
1683	STAM_REG(pVM, &pPGM->StatRZPhysHandlerReset, STAMTYPE_COUNTER, "/PGM/RZ/PhysHandlerReset", STAMUNIT_OCCURENCES, "The number of times PGMHandlerPhysicalReset is called.");
1684	STAM_REG(pVM, &pPGM->StatRZPageOutOfSyncSupervisor, STAMTYPE_COUNTER, "/PGM/RZ/OutOfSync/SuperVisor", STAMUNIT_OCCURENCES, "Number of traps due to pages out of sync and times VerifyAccessSyncPage calls SyncPage.");
1685	STAM_REG(pVM, &pPGM->StatRZPageOutOfSyncUser, STAMTYPE_COUNTER, "/PGM/RZ/OutOfSync/User", STAMUNIT_OCCURENCES, "Number of traps due to pages out of sync and times VerifyAccessSyncPage calls SyncPage.");
1686	STAM_REG(pVM, &pPGM->StatRZPrefetch, STAMTYPE_PROFILE, "/PGM/RZ/Prefetch", STAMUNIT_TICKS_PER_CALL, "PGMPrefetchPage profiling.");
1687	STAM_REG(pVM, &pPGM->StatRZChunkR3MapTlbHits, STAMTYPE_COUNTER, "/PGM/ChunkR3Map/TlbHitsRZ", STAMUNIT_OCCURENCES, "TLB hits.");
1688	STAM_REG(pVM, &pPGM->StatRZChunkR3MapTlbMisses, STAMTYPE_COUNTER, "/PGM/ChunkR3Map/TlbMissesRZ", STAMUNIT_OCCURENCES, "TLB misses.");
1689	STAM_REG(pVM, &pPGM->StatRZPageMapTlbHits, STAMTYPE_COUNTER, "/PGM/RZ/Page/MapTlbHits", STAMUNIT_OCCURENCES, "TLB hits.");
1690	STAM_REG(pVM, &pPGM->StatRZPageMapTlbMisses, STAMTYPE_COUNTER, "/PGM/RZ/Page/MapTlbMisses", STAMUNIT_OCCURENCES, "TLB misses.");
1691	STAM_REG(pVM, &pPGM->StatRZPageReplaceShared, STAMTYPE_COUNTER, "/PGM/RZ/Page/ReplacedShared", STAMUNIT_OCCURENCES, "Times a shared page was replaced.");
1692	STAM_REG(pVM, &pPGM->StatRZPageReplaceZero, STAMTYPE_COUNTER, "/PGM/RZ/Page/ReplacedZero", STAMUNIT_OCCURENCES, "Times the zero page was replaced.");
1693	/// @todo STAM_REG(pVM, &pPGM->StatRZPageHandyAllocs, STAMTYPE_COUNTER, "/PGM/RZ/Page/HandyAllocs", STAMUNIT_OCCURENCES, "Number of times we've allocated more handy pages.");
1694	STAM_REG(pVM, &pPGM->StatRZFlushTLB, STAMTYPE_PROFILE, "/PGM/RZ/FlushTLB", STAMUNIT_OCCURENCES, "Profiling of the PGMFlushTLB() body.");
1695	STAM_REG(pVM, &pPGM->StatRZFlushTLBNewCR3, STAMTYPE_COUNTER, "/PGM/RZ/FlushTLB/NewCR3", STAMUNIT_OCCURENCES, "The number of times PGMFlushTLB was called with a new CR3, non-global. (switch)");
1696	STAM_REG(pVM, &pPGM->StatRZFlushTLBNewCR3Global, STAMTYPE_COUNTER, "/PGM/RZ/FlushTLB/NewCR3Global", STAMUNIT_OCCURENCES, "The number of times PGMFlushTLB was called with a new CR3, global. (switch)");
1697	STAM_REG(pVM, &pPGM->StatRZFlushTLBSameCR3, STAMTYPE_COUNTER, "/PGM/RZ/FlushTLB/SameCR3", STAMUNIT_OCCURENCES, "The number of times PGMFlushTLB was called with the same CR3, non-global. (flush)");
1698	STAM_REG(pVM, &pPGM->StatRZFlushTLBSameCR3Global, STAMTYPE_COUNTER, "/PGM/RZ/FlushTLB/SameCR3Global", STAMUNIT_OCCURENCES, "The number of times PGMFlushTLB was called with the same CR3, global. (flush)");
1699	STAM_REG(pVM, &pPGM->StatRZGstModifyPage, STAMTYPE_PROFILE, "/PGM/RZ/GstModifyPage", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMGstModifyPage() body.");
1700
1701	STAM_REG(pVM, &pPGM->StatR3SyncCR3, STAMTYPE_PROFILE, "/PGM/R3/SyncCR3", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMSyncCR3() body.");
1702	STAM_REG(pVM, &pPGM->StatR3SyncCR3Handlers, STAMTYPE_PROFILE, "/PGM/R3/SyncCR3/Handlers", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMSyncCR3() update handler section.");
1703	STAM_REG(pVM, &pPGM->StatR3SyncCR3HandlerVirtualUpdate, STAMTYPE_PROFILE, "/PGM/R3/SyncCR3/Handlers/VirtualUpdate", STAMUNIT_TICKS_PER_CALL, "Profiling of the virtual handler updates.");
1704	STAM_REG(pVM, &pPGM->StatR3SyncCR3HandlerVirtualReset, STAMTYPE_PROFILE, "/PGM/R3/SyncCR3/Handlers/VirtualReset", STAMUNIT_TICKS_PER_CALL, "Profiling of the virtual handler resets.");
1705	STAM_REG(pVM, &pPGM->StatR3SyncCR3Global, STAMTYPE_COUNTER, "/PGM/R3/SyncCR3/Global", STAMUNIT_OCCURENCES, "The number of global CR3 syncs.");
1706	STAM_REG(pVM, &pPGM->StatR3SyncCR3NotGlobal, STAMTYPE_COUNTER, "/PGM/R3/SyncCR3/NotGlobal", STAMUNIT_OCCURENCES, "The number of non-global CR3 syncs.");
1707	STAM_REG(pVM, &pPGM->StatR3SyncCR3DstCacheHit, STAMTYPE_COUNTER, "/PGM/R3/SyncCR3/DstChacheHit", STAMUNIT_OCCURENCES, "The number of times we got some kind of a cache hit.");
1708	STAM_REG(pVM, &pPGM->StatR3SyncCR3DstFreed, STAMTYPE_COUNTER, "/PGM/R3/SyncCR3/DstFreed", STAMUNIT_OCCURENCES, "The number of times we've had to free a shadow entry.");
1709	STAM_REG(pVM, &pPGM->StatR3SyncCR3DstFreedSrcNP, STAMTYPE_COUNTER, "/PGM/R3/SyncCR3/DstFreedSrcNP", STAMUNIT_OCCURENCES, "The number of times we've had to free a shadow entry for which the source entry was not present.");
1710	STAM_REG(pVM, &pPGM->StatR3SyncCR3DstNotPresent, STAMTYPE_COUNTER, "/PGM/R3/SyncCR3/DstNotPresent", STAMUNIT_OCCURENCES, "The number of times we've encountered a not present shadow entry for a present guest entry.");
1711	STAM_REG(pVM, &pPGM->StatR3SyncCR3DstSkippedGlobalPD, STAMTYPE_COUNTER, "/PGM/R3/SyncCR3/DstSkippedGlobalPD", STAMUNIT_OCCURENCES, "The number of times a global page directory wasn't flushed.");
1712	STAM_REG(pVM, &pPGM->StatR3SyncCR3DstSkippedGlobalPT, STAMTYPE_COUNTER, "/PGM/R3/SyncCR3/DstSkippedGlobalPT", STAMUNIT_OCCURENCES, "The number of times a page table with only global entries wasn't flushed.");
1713	STAM_REG(pVM, &pPGM->StatR3SyncPT, STAMTYPE_PROFILE, "/PGM/R3/SyncPT", STAMUNIT_TICKS_PER_CALL, "Profiling of the pfnSyncPT() body.");
1714	STAM_REG(pVM, &pPGM->StatR3SyncPTFailed, STAMTYPE_COUNTER, "/PGM/R3/SyncPT/Failed", STAMUNIT_OCCURENCES, "The number of times pfnSyncPT() failed.");
1715	STAM_REG(pVM, &pPGM->StatR3SyncPT4K, STAMTYPE_COUNTER, "/PGM/R3/SyncPT/4K", STAMUNIT_OCCURENCES, "Nr of 4K PT syncs");
1716	STAM_REG(pVM, &pPGM->StatR3SyncPT4M, STAMTYPE_COUNTER, "/PGM/R3/SyncPT/4M", STAMUNIT_OCCURENCES, "Nr of 4M PT syncs");
1717	STAM_REG(pVM, &pPGM->StatR3SyncPagePDNAs, STAMTYPE_COUNTER, "/PGM/R3/SyncPagePDNAs", STAMUNIT_OCCURENCES, "The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit.");
1718	STAM_REG(pVM, &pPGM->StatR3SyncPagePDOutOfSync, STAMTYPE_COUNTER, "/PGM/R3/SyncPagePDOutOfSync", STAMUNIT_OCCURENCES, "The number of time we've encountered an out-of-sync PD in SyncPage.");
1719	STAM_REG(pVM, &pPGM->StatR3AccessedPage, STAMTYPE_COUNTER, "/PGM/R3/AccessedPage", STAMUNIT_OCCURENCES, "The number of pages marked not present for accessed bit emulation.");
1720	STAM_REG(pVM, &pPGM->StatR3DirtyBitTracking, STAMTYPE_PROFILE, "/PGM/R3/DirtyPage", STAMUNIT_TICKS_PER_CALL, "Profiling the dirty bit tracking in CheckPageFault().");
1721	STAM_REG(pVM, &pPGM->StatR3DirtyPage, STAMTYPE_COUNTER, "/PGM/R3/DirtyPage/Mark", STAMUNIT_OCCURENCES, "The number of pages marked read-only for dirty bit tracking.");
1722	STAM_REG(pVM, &pPGM->StatR3DirtyPageBig, STAMTYPE_COUNTER, "/PGM/R3/DirtyPage/MarkBig", STAMUNIT_OCCURENCES, "The number of 4MB pages marked read-only for dirty bit tracking.");
1723	STAM_REG(pVM, &pPGM->StatR3DirtyPageSkipped, STAMTYPE_COUNTER, "/PGM/R3/DirtyPage/Skipped", STAMUNIT_OCCURENCES, "The number of pages already dirty or readonly.");
1724	STAM_REG(pVM, &pPGM->StatR3DirtyPageTrap, STAMTYPE_COUNTER, "/PGM/R3/DirtyPage/Trap", STAMUNIT_OCCURENCES, "The number of traps generated for dirty bit tracking.");
1725	STAM_REG(pVM, &pPGM->StatR3DirtiedPage, STAMTYPE_COUNTER, "/PGM/R3/DirtyPage/SetDirty", STAMUNIT_OCCURENCES, "The number of pages marked dirty because of write accesses.");
1726	STAM_REG(pVM, &pPGM->StatR3DirtyTrackRealPF, STAMTYPE_COUNTER, "/PGM/R3/DirtyPage/RealPF", STAMUNIT_OCCURENCES, "The number of real pages faults during dirty bit tracking.");
1727	STAM_REG(pVM, &pPGM->StatR3PageAlreadyDirty, STAMTYPE_COUNTER, "/PGM/R3/DirtyPage/AlreadySet", STAMUNIT_OCCURENCES, "The number of pages already marked dirty because of write accesses.");
1728	STAM_REG(pVM, &pPGM->StatR3InvalidatePage, STAMTYPE_PROFILE, "/PGM/R3/InvalidatePage", STAMUNIT_TICKS_PER_CALL, "PGMInvalidatePage() profiling.");
1729	STAM_REG(pVM, &pPGM->StatR3InvalidatePage4KBPages, STAMTYPE_COUNTER, "/PGM/R3/InvalidatePage/4KBPages", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was called for a 4KB page.");
1730	STAM_REG(pVM, &pPGM->StatR3InvalidatePage4MBPages, STAMTYPE_COUNTER, "/PGM/R3/InvalidatePage/4MBPages", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was called for a 4MB page.");
1731	STAM_REG(pVM, &pPGM->StatR3InvalidatePage4MBPagesSkip, STAMTYPE_COUNTER, "/PGM/R3/InvalidatePage/4MBPagesSkip",STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() skipped a 4MB page.");
1732	STAM_REG(pVM, &pPGM->StatR3InvalidatePagePDMappings, STAMTYPE_COUNTER, "/PGM/R3/InvalidatePage/PDMappings", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict).");
1733	STAM_REG(pVM, &pPGM->StatR3InvalidatePagePDNAs, STAMTYPE_COUNTER, "/PGM/R3/InvalidatePage/PDNAs", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was called for a not accessed page directory.");
1734	STAM_REG(pVM, &pPGM->StatR3InvalidatePagePDNPs, STAMTYPE_COUNTER, "/PGM/R3/InvalidatePage/PDNPs", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was called for a not present page directory.");
1735	STAM_REG(pVM, &pPGM->StatR3InvalidatePagePDOutOfSync, STAMTYPE_COUNTER, "/PGM/R3/InvalidatePage/PDOutOfSync", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was called for an out of sync page directory.");
1736	STAM_REG(pVM, &pPGM->StatR3InvalidatePageSkipped, STAMTYPE_COUNTER, "/PGM/R3/InvalidatePage/Skipped", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3.");
1737	STAM_REG(pVM, &pPGM->StatR3VirtHandlerSearchByPhys, STAMTYPE_PROFILE, "/PGM/R3/VirtHandlerSearchByPhys", STAMUNIT_TICKS_PER_CALL, "Profiling of pgmHandlerVirtualFindByPhysAddr.");
1738	STAM_REG(pVM, &pPGM->StatR3PhysHandlerReset, STAMTYPE_COUNTER, "/PGM/R3/PhysHandlerReset", STAMUNIT_OCCURENCES, "The number of times PGMHandlerPhysicalReset is called.");
1739	STAM_REG(pVM, &pPGM->StatR3PageOutOfSyncSupervisor, STAMTYPE_COUNTER, "/PGM/R3/OutOfSync/SuperVisor", STAMUNIT_OCCURENCES, "Number of traps due to pages out of sync and times VerifyAccessSyncPage calls SyncPage.");
1740	STAM_REG(pVM, &pPGM->StatR3PageOutOfSyncUser, STAMTYPE_COUNTER, "/PGM/R3/OutOfSync/User", STAMUNIT_OCCURENCES, "Number of traps due to pages out of sync and times VerifyAccessSyncPage calls SyncPage.");
1741	STAM_REG(pVM, &pPGM->StatR3Prefetch, STAMTYPE_PROFILE, "/PGM/R3/Prefetch", STAMUNIT_TICKS_PER_CALL, "PGMPrefetchPage profiling.");
1742	STAM_REG(pVM, &pPGM->StatR3ChunkR3MapTlbHits, STAMTYPE_COUNTER, "/PGM/ChunkR3Map/TlbHitsR3", STAMUNIT_OCCURENCES, "TLB hits.");
1743	STAM_REG(pVM, &pPGM->StatR3ChunkR3MapTlbMisses, STAMTYPE_COUNTER, "/PGM/ChunkR3Map/TlbMissesR3", STAMUNIT_OCCURENCES, "TLB misses.");
1744	STAM_REG(pVM, &pPGM->StatR3PageMapTlbHits, STAMTYPE_COUNTER, "/PGM/R3/Page/MapTlbHits", STAMUNIT_OCCURENCES, "TLB hits.");
1745	STAM_REG(pVM, &pPGM->StatR3PageMapTlbMisses, STAMTYPE_COUNTER, "/PGM/R3/Page/MapTlbMisses", STAMUNIT_OCCURENCES, "TLB misses.");
1746	STAM_REG(pVM, &pPGM->StatR3PageReplaceShared, STAMTYPE_COUNTER, "/PGM/R3/Page/ReplacedShared", STAMUNIT_OCCURENCES, "Times a shared page was replaced.");
1747	STAM_REG(pVM, &pPGM->StatR3PageReplaceZero, STAMTYPE_COUNTER, "/PGM/R3/Page/ReplacedZero", STAMUNIT_OCCURENCES, "Times the zero page was replaced.");
1748	/// @todo STAM_REG(pVM, &pPGM->StatR3PageHandyAllocs, STAMTYPE_COUNTER, "/PGM/R3/Page/HandyAllocs", STAMUNIT_OCCURENCES, "Number of times we've allocated more handy pages.");
1749	STAM_REG(pVM, &pPGM->StatR3FlushTLB, STAMTYPE_PROFILE, "/PGM/R3/FlushTLB", STAMUNIT_OCCURENCES, "Profiling of the PGMFlushTLB() body.");
1750	STAM_REG(pVM, &pPGM->StatR3FlushTLBNewCR3, STAMTYPE_COUNTER, "/PGM/R3/FlushTLB/NewCR3", STAMUNIT_OCCURENCES, "The number of times PGMFlushTLB was called with a new CR3, non-global. (switch)");
1751	STAM_REG(pVM, &pPGM->StatR3FlushTLBNewCR3Global, STAMTYPE_COUNTER, "/PGM/R3/FlushTLB/NewCR3Global", STAMUNIT_OCCURENCES, "The number of times PGMFlushTLB was called with a new CR3, global. (switch)");
1752	STAM_REG(pVM, &pPGM->StatR3FlushTLBSameCR3, STAMTYPE_COUNTER, "/PGM/R3/FlushTLB/SameCR3", STAMUNIT_OCCURENCES, "The number of times PGMFlushTLB was called with the same CR3, non-global. (flush)");
1753	STAM_REG(pVM, &pPGM->StatR3FlushTLBSameCR3Global, STAMTYPE_COUNTER, "/PGM/R3/FlushTLB/SameCR3Global", STAMUNIT_OCCURENCES, "The number of times PGMFlushTLB was called with the same CR3, global. (flush)");
1754	STAM_REG(pVM, &pPGM->StatR3GstModifyPage, STAMTYPE_PROFILE, "/PGM/R3/GstModifyPage", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMGstModifyPage() body.");
1755
1756	}
1757	#endif /* VBOX_WITH_STATISTICS */
1758
1759
1760	/**
1761	* Init the PGM bits that rely on VMMR0 and MM to be fully initialized.
1762	*
1763	* The dynamic mapping area will also be allocated and initialized at this
1764	* time. We could allocate it during PGMR3Init of course, but the mapping
1765	* wouldn't be allocated at that time preventing us from setting up the
1766	* page table entries with the dummy page.
1767	*
1768	* @returns VBox status code.
1769	* @param pVM VM handle.
1770	*/
1771	VMMR3DECL(int) PGMR3InitDynMap(PVM pVM)
1772	{
1773	RTGCPTR GCPtr;
1774	/*
1775	* Reserve space for mapping the paging pages into guest context.
1776	*/
1777	int rc = MMR3HyperReserve(pVM, PAGE_SIZE * (2 + RT_ELEMENTS(pVM->pgm.s.apShwPaePDsR3) + 1 + 2 + 2), "Paging", &GCPtr);
1778	AssertRCReturn(rc, rc);
1779	pVM->pgm.s.pShw32BitPdRC = GCPtr;
1780	MMR3HyperReserve(pVM, PAGE_SIZE, "fence", NULL);
1781
1782	/*
1783	* Reserve space for the dynamic mappings.
1784	*/
1785	rc = MMR3HyperReserve(pVM, MM_HYPER_DYNAMIC_SIZE, "Dynamic mapping", &GCPtr);
1786	if (RT_SUCCESS(rc))
1787	pVM->pgm.s.pbDynPageMapBaseGC = GCPtr;
1788
1789	if ( RT_SUCCESS(rc)
1790	&& (pVM->pgm.s.pbDynPageMapBaseGC >> X86_PD_PAE_SHIFT) != ((pVM->pgm.s.pbDynPageMapBaseGC + MM_HYPER_DYNAMIC_SIZE - 1) >> X86_PD_PAE_SHIFT))
1791	{
1792	rc = MMR3HyperReserve(pVM, MM_HYPER_DYNAMIC_SIZE, "Dynamic mapping not crossing", &GCPtr);
1793	if (RT_SUCCESS(rc))
1794	pVM->pgm.s.pbDynPageMapBaseGC = GCPtr;
1795	}
1796	if (RT_SUCCESS(rc))
1797	{
1798	AssertRelease((pVM->pgm.s.pbDynPageMapBaseGC >> X86_PD_PAE_SHIFT) == ((pVM->pgm.s.pbDynPageMapBaseGC + MM_HYPER_DYNAMIC_SIZE - 1) >> X86_PD_PAE_SHIFT));
1799	MMR3HyperReserve(pVM, PAGE_SIZE, "fence", NULL);
1800	}
1801	return rc;
1802	}
1803
1804
1805	/**
1806	* Ring-3 init finalizing.
1807	*
1808	* @returns VBox status code.
1809	* @param pVM The VM handle.
1810	*/
1811	VMMR3DECL(int) PGMR3InitFinalize(PVM pVM)
1812	{
1813	/*
1814	* Map the paging pages into the guest context.
1815	*/
1816	RTGCPTR GCPtr = pVM->pgm.s.pShw32BitPdRC;
1817	AssertReleaseReturn(GCPtr, VERR_INTERNAL_ERROR);
1818
1819	int rc = PGMMap(pVM, GCPtr, pVM->pgm.s.HCPhysShw32BitPD, PAGE_SIZE, 0);
1820	AssertRCReturn(rc, rc);
1821	pVM->pgm.s.pShw32BitPdRC = GCPtr;
1822	GCPtr += PAGE_SIZE;
1823	GCPtr += PAGE_SIZE; /* reserved page */
1824
1825	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.apShwPaePDsR3); i++)
1826	{
1827	rc = PGMMap(pVM, GCPtr, pVM->pgm.s.aHCPhysPaePDs[i], PAGE_SIZE, 0);
1828	AssertRCReturn(rc, rc);
1829	pVM->pgm.s.apShwPaePDsRC[i] = GCPtr;
1830	GCPtr += PAGE_SIZE;
1831	}
1832	/* A bit of paranoia is justified. */
1833	AssertRelease(pVM->pgm.s.apShwPaePDsRC[0] + PAGE_SIZE == pVM->pgm.s.apShwPaePDsRC[1]);
1834	AssertRelease(pVM->pgm.s.apShwPaePDsRC[1] + PAGE_SIZE == pVM->pgm.s.apShwPaePDsRC[2]);
1835	AssertRelease(pVM->pgm.s.apShwPaePDsRC[2] + PAGE_SIZE == pVM->pgm.s.apShwPaePDsRC[3]);
1836	GCPtr += PAGE_SIZE; /* reserved page */
1837
1838	rc = PGMMap(pVM, GCPtr, pVM->pgm.s.HCPhysShwPaePdpt, PAGE_SIZE, 0);
1839	AssertRCReturn(rc, rc);
1840	pVM->pgm.s.pShwPaePdptRC = GCPtr;
1841	GCPtr += PAGE_SIZE;
1842	GCPtr += PAGE_SIZE; /* reserved page */
1843
1844
1845	/*
1846	* Reserve space for the dynamic mappings.
1847	* Initialize the dynamic mapping pages with dummy pages to simply the cache.
1848	*/
1849	/* get the pointer to the page table entries. */
1850	PPGMMAPPING pMapping = pgmGetMapping(pVM, pVM->pgm.s.pbDynPageMapBaseGC);
1851	AssertRelease(pMapping);
1852	const uintptr_t off = pVM->pgm.s.pbDynPageMapBaseGC - pMapping->GCPtr;
1853	const unsigned iPT = off >> X86_PD_SHIFT;
1854	const unsigned iPG = (off >> X86_PT_SHIFT) & X86_PT_MASK;
1855	pVM->pgm.s.paDynPageMap32BitPTEsGC = pMapping->aPTs[iPT].pPTRC + iPG * sizeof(pMapping->aPTs[0].pPTR3->a[0]);
1856	pVM->pgm.s.paDynPageMapPaePTEsGC = pMapping->aPTs[iPT].paPaePTsRC + iPG * sizeof(pMapping->aPTs[0].paPaePTsR3->a[0]);
1857
1858	/* init cache */
1859	RTHCPHYS HCPhysDummy = MMR3PageDummyHCPhys(pVM);
1860	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.aHCPhysDynPageMapCache); i++)
1861	pVM->pgm.s.aHCPhysDynPageMapCache[i] = HCPhysDummy;
1862
1863	for (unsigned i = 0; i < MM_HYPER_DYNAMIC_SIZE; i += PAGE_SIZE)
1864	{
1865	rc = PGMMap(pVM, pVM->pgm.s.pbDynPageMapBaseGC + i, HCPhysDummy, PAGE_SIZE, 0);
1866	AssertRCReturn(rc, rc);
1867	}
1868
1869	/*
1870	* Note that AMD uses all the 8 reserved bits for the address (so 40 bits in total);
1871	* Intel only goes up to 36 bits, so we stick to 36 as well.
1872	*/
1873	/** @todo How to test for the 40 bits support? Long mode seems to be the test criterium. */
1874	uint32_t u32Dummy, u32Features;
1875	CPUMGetGuestCpuId(pVM, 1, &u32Dummy, &u32Dummy, &u32Dummy, &u32Features);
1876
1877	if (u32Features & X86_CPUID_FEATURE_EDX_PSE36)
1878	pVM->pgm.s.GCPhys4MBPSEMask = RT_BIT_64(36) - 1;
1879	else
1880	pVM->pgm.s.GCPhys4MBPSEMask = RT_BIT_64(32) - 1;
1881
1882	LogRel(("PGMR3InitFinalize: 4 MB PSE mask %RGp\n", pVM->pgm.s.GCPhys4MBPSEMask));
1883
1884	return rc;
1885	}
1886
1887
1888	/**
1889	* Applies relocations to data and code managed by this component.
1890	*
1891	* This function will be called at init and whenever the VMM need to relocate it
1892	* self inside the GC.
1893	*
1894	* @param pVM The VM.
1895	* @param offDelta Relocation delta relative to old location.
1896	*/
1897	VMMR3DECL(void) PGMR3Relocate(PVM pVM, RTGCINTPTR offDelta)
1898	{
1899	LogFlow(("PGMR3Relocate\n"));
1900
1901	/*
1902	* Paging stuff.
1903	*/
1904	pVM->pgm.s.GCPtrCR3Mapping += offDelta;
1905	/** @todo move this into shadow and guest specific relocation functions. */
1906	AssertMsg(pVM->pgm.s.pShw32BitPdR3, ("Init order, no relocation before paging is initialized!\n"));
1907	pVM->pgm.s.pShw32BitPdRC += offDelta;
1908	pVM->pgm.s.pGst32BitPdRC += offDelta;
1909	AssertCompile(RT_ELEMENTS(pVM->pgm.s.apShwPaePDsRC) == RT_ELEMENTS(pVM->pgm.s.apGstPaePDsRC));
1910	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.apShwPaePDsRC); i++)
1911	{
1912	pVM->pgm.s.apShwPaePDsRC[i] += offDelta;
1913	pVM->pgm.s.apGstPaePDsRC[i] += offDelta;
1914	}
1915	pVM->pgm.s.pGstPaePdptRC += offDelta;
1916	pVM->pgm.s.pShwPaePdptRC += offDelta;
1917
1918	pgmR3ModeDataInit(pVM, true /* resolve GC/R0 symbols */);
1919	pgmR3ModeDataSwitch(pVM, pVM->pgm.s.enmShadowMode, pVM->pgm.s.enmGuestMode);
1920
1921	PGM_SHW_PFN(Relocate, pVM)(pVM, offDelta);
1922	PGM_GST_PFN(Relocate, pVM)(pVM, offDelta);
1923	PGM_BTH_PFN(Relocate, pVM)(pVM, offDelta);
1924
1925	/*
1926	* Trees.
1927	*/
1928	pVM->pgm.s.pTreesRC = MMHyperR3ToRC(pVM, pVM->pgm.s.pTreesR3);
1929
1930	/*
1931	* Ram ranges.
1932	*/
1933	if (pVM->pgm.s.pRamRangesR3)
1934	{
1935	pVM->pgm.s.pRamRangesRC = MMHyperR3ToRC(pVM, pVM->pgm.s.pRamRangesR3);
1936	for (PPGMRAMRANGE pCur = pVM->pgm.s.pRamRangesR3; pCur->pNextR3; pCur = pCur->pNextR3)
1937	pCur->pNextRC = MMHyperR3ToRC(pVM, pCur->pNextR3);
1938	}
1939
1940	/*
1941	* Update the two page directories with all page table mappings.
1942	* (One or more of them have changed, that's why we're here.)
1943	*/
1944	pVM->pgm.s.pMappingsRC = MMHyperR3ToRC(pVM, pVM->pgm.s.pMappingsR3);
1945	for (PPGMMAPPING pCur = pVM->pgm.s.pMappingsR3; pCur->pNextR3; pCur = pCur->pNextR3)
1946	pCur->pNextRC = MMHyperR3ToRC(pVM, pCur->pNextR3);
1947
1948	/* Relocate GC addresses of Page Tables. */
1949	for (PPGMMAPPING pCur = pVM->pgm.s.pMappingsR3; pCur; pCur = pCur->pNextR3)
1950	{
1951	for (RTHCUINT i = 0; i < pCur->cPTs; i++)
1952	{
1953	pCur->aPTs[i].pPTRC = MMHyperR3ToRC(pVM, pCur->aPTs[i].pPTR3);
1954	pCur->aPTs[i].paPaePTsRC = MMHyperR3ToRC(pVM, pCur->aPTs[i].paPaePTsR3);
1955	}
1956	}
1957
1958	/*
1959	* Dynamic page mapping area.
1960	*/
1961	pVM->pgm.s.paDynPageMap32BitPTEsGC += offDelta;
1962	pVM->pgm.s.paDynPageMapPaePTEsGC += offDelta;
1963	pVM->pgm.s.pbDynPageMapBaseGC += offDelta;
1964
1965	/*
1966	* The Zero page.
1967	*/
1968	pVM->pgm.s.pvZeroPgR0 = MMHyperR3ToR0(pVM, pVM->pgm.s.pvZeroPgR3);
1969	AssertRelease(pVM->pgm.s.pvZeroPgR0);
1970
1971	/*
1972	* Physical and virtual handlers.
1973	*/
1974	RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysHandlers, true, pgmR3RelocatePhysHandler, &offDelta);
1975	RTAvlroGCPtrDoWithAll(&pVM->pgm.s.pTreesR3->VirtHandlers, true, pgmR3RelocateVirtHandler, &offDelta);
1976	RTAvlroGCPtrDoWithAll(&pVM->pgm.s.pTreesR3->HyperVirtHandlers, true, pgmR3RelocateHyperVirtHandler, &offDelta);
1977
1978	/*
1979	* The page pool.
1980	*/
1981	pgmR3PoolRelocate(pVM);
1982	}
1983
1984
1985	/**
1986	* Callback function for relocating a physical access handler.
1987	*
1988	* @returns 0 (continue enum)
1989	* @param pNode Pointer to a PGMPHYSHANDLER node.
1990	* @param pvUser Pointer to the offDelta. This is a pointer to the delta since we're
1991	* not certain the delta will fit in a void pointer for all possible configs.
1992	*/
1993	static DECLCALLBACK(int) pgmR3RelocatePhysHandler(PAVLROGCPHYSNODECORE pNode, void *pvUser)
1994	{
1995	PPGMPHYSHANDLER pHandler = (PPGMPHYSHANDLER)pNode;
1996	RTGCINTPTR offDelta = *(PRTGCINTPTR)pvUser;
1997	if (pHandler->pfnHandlerRC)
1998	pHandler->pfnHandlerRC += offDelta;
1999	if (pHandler->pvUserRC >= 0x10000)
2000	pHandler->pvUserRC += offDelta;
2001	return 0;
2002	}
2003
2004
2005	/**
2006	* Callback function for relocating a virtual access handler.
2007	*
2008	* @returns 0 (continue enum)
2009	* @param pNode Pointer to a PGMVIRTHANDLER node.
2010	* @param pvUser Pointer to the offDelta. This is a pointer to the delta since we're
2011	* not certain the delta will fit in a void pointer for all possible configs.
2012	*/
2013	static DECLCALLBACK(int) pgmR3RelocateVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser)
2014	{
2015	PPGMVIRTHANDLER pHandler = (PPGMVIRTHANDLER)pNode;
2016	RTGCINTPTR offDelta = *(PRTGCINTPTR)pvUser;
2017	Assert( pHandler->enmType == PGMVIRTHANDLERTYPE_ALL
2018	\|\| pHandler->enmType == PGMVIRTHANDLERTYPE_WRITE);
2019	Assert(pHandler->pfnHandlerRC);
2020	pHandler->pfnHandlerRC += offDelta;
2021	return 0;
2022	}
2023
2024
2025	/**
2026	* Callback function for relocating a virtual access handler for the hypervisor mapping.
2027	*
2028	* @returns 0 (continue enum)
2029	* @param pNode Pointer to a PGMVIRTHANDLER node.
2030	* @param pvUser Pointer to the offDelta. This is a pointer to the delta since we're
2031	* not certain the delta will fit in a void pointer for all possible configs.
2032	*/
2033	static DECLCALLBACK(int) pgmR3RelocateHyperVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser)
2034	{
2035	PPGMVIRTHANDLER pHandler = (PPGMVIRTHANDLER)pNode;
2036	RTGCINTPTR offDelta = *(PRTGCINTPTR)pvUser;
2037	Assert(pHandler->enmType == PGMVIRTHANDLERTYPE_HYPERVISOR);
2038	Assert(pHandler->pfnHandlerRC);
2039	pHandler->pfnHandlerRC += offDelta;
2040	return 0;
2041	}
2042
2043
2044	/**
2045	* The VM is being reset.
2046	*
2047	* For the PGM component this means that any PD write monitors
2048	* needs to be removed.
2049	*
2050	* @param pVM VM handle.
2051	*/
2052	VMMR3DECL(void) PGMR3Reset(PVM pVM)
2053	{
2054	LogFlow(("PGMR3Reset:\n"));
2055	VM_ASSERT_EMT(pVM);
2056
2057	pgmLock(pVM);
2058
2059	/*
2060	* Unfix any fixed mappings and disable CR3 monitoring.
2061	*/
2062	pVM->pgm.s.fMappingsFixed = false;
2063	pVM->pgm.s.GCPtrMappingFixed = 0;
2064	pVM->pgm.s.cbMappingFixed = 0;
2065
2066	/* Exit the guest paging mode before the pgm pool gets reset.
2067	* Important to clean up the amd64 case.
2068	*/
2069	int rc = PGM_GST_PFN(Exit, pVM)(pVM);
2070	AssertRC(rc);
2071	#ifdef DEBUG
2072	DBGFR3InfoLog(pVM, "mappings", NULL);
2073	DBGFR3InfoLog(pVM, "handlers", "all nostat");
2074	#endif
2075
2076	/*
2077	* Reset the shadow page pool.
2078	*/
2079	pgmR3PoolReset(pVM);
2080
2081	/*
2082	* Re-init other members.
2083	*/
2084	pVM->pgm.s.fA20Enabled = true;
2085
2086	/*
2087	* Clear the FFs PGM owns.
2088	*/
2089	VM_FF_CLEAR(pVM, VM_FF_PGM_SYNC_CR3);
2090	VM_FF_CLEAR(pVM, VM_FF_PGM_SYNC_CR3_NON_GLOBAL);
2091
2092	/*
2093	* Reset (zero) RAM pages.
2094	*/
2095	rc = pgmR3PhysRamReset(pVM);
2096	if (RT_SUCCESS(rc))
2097	{
2098	#ifdef VBOX_WITH_NEW_PHYS_CODE
2099	/*
2100	* Reset (zero) shadow ROM pages.
2101	*/
2102	rc = pgmR3PhysRomReset(pVM);
2103	#endif
2104	if (RT_SUCCESS(rc))
2105	{
2106	/*
2107	* Switch mode back to real mode.
2108	*/
2109	rc = PGMR3ChangeMode(pVM, PGMMODE_REAL);
2110	STAM_REL_COUNTER_RESET(&pVM->pgm.s.cGuestModeChanges);
2111	}
2112	}
2113
2114	pgmUnlock(pVM);
2115	//return rc;
2116	AssertReleaseRC(rc);
2117	}
2118
2119
2120	#ifdef VBOX_STRICT
2121	/**
2122	* VM state change callback for clearing fNoMorePhysWrites after
2123	* a snapshot has been created.
2124	*/
2125	static DECLCALLBACK(void) pgmR3ResetNoMorePhysWritesFlag(PVM pVM, VMSTATE enmState, VMSTATE enmOldState, void *pvUser)
2126	{
2127	if (enmState == VMSTATE_RUNNING)
2128	pVM->pgm.s.fNoMorePhysWrites = false;
2129	}
2130	#endif
2131
2132
2133	/**
2134	* Terminates the PGM.
2135	*
2136	* @returns VBox status code.
2137	* @param pVM Pointer to VM structure.
2138	*/
2139	VMMR3DECL(int) PGMR3Term(PVM pVM)
2140	{
2141	return PDMR3CritSectDelete(&pVM->pgm.s.CritSect);
2142	}
2143
2144
2145	/**
2146	* Terminates the per-VCPU PGM.
2147	*
2148	* Termination means cleaning up and freeing all resources,
2149	* the VM it self is at this point powered off or suspended.
2150	*
2151	* @returns VBox status code.
2152	* @param pVM The VM to operate on.
2153	*/
2154	VMMR3DECL(int) PGMR3TermCPU(PVM pVM)
2155	{
2156	return 0;
2157	}
2158
2159
2160	/**
2161	* Execute state save operation.
2162	*
2163	* @returns VBox status code.
2164	* @param pVM VM Handle.
2165	* @param pSSM SSM operation handle.
2166	*/
2167	static DECLCALLBACK(int) pgmR3Save(PVM pVM, PSSMHANDLE pSSM)
2168	{
2169	PPGM pPGM = &pVM->pgm.s;
2170
2171	/* No more writes to physical memory after this point! */
2172	pVM->pgm.s.fNoMorePhysWrites = true;
2173
2174	/*
2175	* Save basic data (required / unaffected by relocation).
2176	*/
2177	#if 1
2178	SSMR3PutBool(pSSM, pPGM->fMappingsFixed);
2179	#else
2180	SSMR3PutUInt(pSSM, pPGM->fMappingsFixed);
2181	#endif
2182	SSMR3PutGCPtr(pSSM, pPGM->GCPtrMappingFixed);
2183	SSMR3PutU32(pSSM, pPGM->cbMappingFixed);
2184	SSMR3PutUInt(pSSM, pPGM->cbRamSize);
2185	SSMR3PutGCPhys(pSSM, pPGM->GCPhysA20Mask);
2186	SSMR3PutUInt(pSSM, pPGM->fA20Enabled);
2187	SSMR3PutUInt(pSSM, pPGM->fSyncFlags);
2188	SSMR3PutUInt(pSSM, pPGM->enmGuestMode);
2189	SSMR3PutU32(pSSM, ~0); /* Separator. */
2190
2191	/*
2192	* The guest mappings.
2193	*/
2194	uint32_t i = 0;
2195	for (PPGMMAPPING pMapping = pPGM->pMappingsR3; pMapping; pMapping = pMapping->pNextR3, i++)
2196	{
2197	SSMR3PutU32(pSSM, i);
2198	SSMR3PutStrZ(pSSM, pMapping->pszDesc); /* This is the best unique id we have... */
2199	SSMR3PutGCPtr(pSSM, pMapping->GCPtr);
2200	SSMR3PutGCUIntPtr(pSSM, pMapping->cPTs);
2201	/* flags are done by the mapping owners! */
2202	}
2203	SSMR3PutU32(pSSM, ~0); /* terminator. */
2204
2205	/*
2206	* Ram range flags and bits.
2207	*/
2208	i = 0;
2209	for (PPGMRAMRANGE pRam = pPGM->pRamRangesR3; pRam; pRam = pRam->pNextR3, i++)
2210	{
2211	/** @todo MMIO ranges may move (PCI reconfig), we currently assume they don't. */
2212
2213	SSMR3PutU32(pSSM, i);
2214	SSMR3PutGCPhys(pSSM, pRam->GCPhys);
2215	SSMR3PutGCPhys(pSSM, pRam->GCPhysLast);
2216	SSMR3PutGCPhys(pSSM, pRam->cb);
2217	SSMR3PutU8(pSSM, !!pRam->pvR3); /* boolean indicating memory or not. */
2218
2219	/* Flags. */
2220	const unsigned cPages = pRam->cb >> PAGE_SHIFT;
2221	for (unsigned iPage = 0; iPage < cPages; iPage++)
2222	SSMR3PutU16(pSSM, (uint16_t)(pRam->aPages[iPage].HCPhys & ~X86_PTE_PAE_PG_MASK)); /** @todo PAGE FLAGS */
2223
2224	/* any memory associated with the range. */
2225	if (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)
2226	{
2227	for (unsigned iChunk = 0; iChunk < (pRam->cb >> PGM_DYNAMIC_CHUNK_SHIFT); iChunk++)
2228	{
2229	if (pRam->paChunkR3Ptrs[iChunk])
2230	{
2231	SSMR3PutU8(pSSM, 1); /* chunk present */
2232	SSMR3PutMem(pSSM, (void *)pRam->paChunkR3Ptrs[iChunk], PGM_DYNAMIC_CHUNK_SIZE);
2233	}
2234	else
2235	SSMR3PutU8(pSSM, 0); /* no chunk present */
2236	}
2237	}
2238	else if (pRam->pvR3)
2239	{
2240	int rc = SSMR3PutMem(pSSM, pRam->pvR3, pRam->cb);
2241	if (RT_FAILURE(rc))
2242	{
2243	Log(("pgmR3Save: SSMR3PutMem(, %p, %#x) -> %Rrc\n", pRam->pvR3, pRam->cb, rc));
2244	return rc;
2245	}
2246	}
2247	}
2248	return SSMR3PutU32(pSSM, ~0); /* terminator. */
2249	}
2250
2251
2252	/**
2253	* Execute state load operation.
2254	*
2255	* @returns VBox status code.
2256	* @param pVM VM Handle.
2257	* @param pSSM SSM operation handle.
2258	* @param u32Version Data layout version.
2259	*/
2260	static DECLCALLBACK(int) pgmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version)
2261	{
2262	/*
2263	* Validate version.
2264	*/
2265	if (u32Version != PGM_SAVED_STATE_VERSION)
2266	{
2267	AssertMsgFailed(("pgmR3Load: Invalid version u32Version=%d (current %d)!\n", u32Version, PGM_SAVED_STATE_VERSION));
2268	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
2269	}
2270
2271	/*
2272	* Call the reset function to make sure all the memory is cleared.
2273	*/
2274	PGMR3Reset(pVM);
2275
2276	/*
2277	* Load basic data (required / unaffected by relocation).
2278	*/
2279	PPGM pPGM = &pVM->pgm.s;
2280	#if 1
2281	SSMR3GetBool(pSSM, &pPGM->fMappingsFixed);
2282	#else
2283	uint32_t u;
2284	SSMR3GetU32(pSSM, &u);
2285	pPGM->fMappingsFixed = u;
2286	#endif
2287	SSMR3GetGCPtr(pSSM, &pPGM->GCPtrMappingFixed);
2288	SSMR3GetU32(pSSM, &pPGM->cbMappingFixed);
2289
2290	RTUINT cbRamSize;
2291	int rc = SSMR3GetU32(pSSM, &cbRamSize);
2292	if (RT_FAILURE(rc))
2293	return rc;
2294	if (cbRamSize != pPGM->cbRamSize)
2295	return VERR_SSM_LOAD_MEMORY_SIZE_MISMATCH;
2296	SSMR3GetGCPhys(pSSM, &pPGM->GCPhysA20Mask);
2297	SSMR3GetUInt(pSSM, &pPGM->fA20Enabled);
2298	SSMR3GetUInt(pSSM, &pPGM->fSyncFlags);
2299	RTUINT uGuestMode;
2300	SSMR3GetUInt(pSSM, &uGuestMode);
2301	pPGM->enmGuestMode = (PGMMODE)uGuestMode;
2302
2303	/* check separator. */
2304	uint32_t u32Sep;
2305	SSMR3GetU32(pSSM, &u32Sep);
2306	if (RT_FAILURE(rc))
2307	return rc;
2308	if (u32Sep != (uint32_t)~0)
2309	{
2310	AssertMsgFailed(("u32Sep=%#x (first)\n", u32Sep));
2311	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2312	}
2313
2314	/*
2315	* The guest mappings.
2316	*/
2317	uint32_t i = 0;
2318	for (;; i++)
2319	{
2320	/* Check the seqence number / separator. */
2321	rc = SSMR3GetU32(pSSM, &u32Sep);
2322	if (RT_FAILURE(rc))
2323	return rc;
2324	if (u32Sep == ~0U)
2325	break;
2326	if (u32Sep != i)
2327	{
2328	AssertMsgFailed(("u32Sep=%#x (last)\n", u32Sep));
2329	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2330	}
2331
2332	/* get the mapping details. */
2333	char szDesc[256];
2334	szDesc[0] = '\0';
2335	rc = SSMR3GetStrZ(pSSM, szDesc, sizeof(szDesc));
2336	if (RT_FAILURE(rc))
2337	return rc;
2338	RTGCPTR GCPtr;
2339	SSMR3GetGCPtr(pSSM, &GCPtr);
2340	RTGCPTR cPTs;
2341	rc = SSMR3GetGCUIntPtr(pSSM, &cPTs);
2342	if (RT_FAILURE(rc))
2343	return rc;
2344
2345	/* find matching range. */
2346	PPGMMAPPING pMapping;
2347	for (pMapping = pPGM->pMappingsR3; pMapping; pMapping = pMapping->pNextR3)
2348	if ( pMapping->cPTs == cPTs
2349	&& !strcmp(pMapping->pszDesc, szDesc))
2350	break;
2351	if (!pMapping)
2352	{
2353	LogRel(("Couldn't find mapping: cPTs=%#x szDesc=%s (GCPtr=%RGv)\n",
2354	cPTs, szDesc, GCPtr));
2355	AssertFailed();
2356	return VERR_SSM_LOAD_CONFIG_MISMATCH;
2357	}
2358
2359	/* relocate it. */
2360	if (pMapping->GCPtr != GCPtr)
2361	{
2362	AssertMsg((GCPtr >> X86_PD_SHIFT << X86_PD_SHIFT) == GCPtr, ("GCPtr=%RGv\n", GCPtr));
2363	pgmR3MapRelocate(pVM, pMapping, pMapping->GCPtr, GCPtr);
2364	}
2365	else
2366	Log(("pgmR3Load: '%s' needed no relocation (%RGv)\n", szDesc, GCPtr));
2367	}
2368
2369	/*
2370	* Ram range flags and bits.
2371	*/
2372	i = 0;
2373	for (PPGMRAMRANGE pRam = pPGM->pRamRangesR3; pRam; pRam = pRam->pNextR3, i++)
2374	{
2375	/** @todo MMIO ranges may move (PCI reconfig), we currently assume they don't. */
2376	/* Check the seqence number / separator. */
2377	rc = SSMR3GetU32(pSSM, &u32Sep);
2378	if (RT_FAILURE(rc))
2379	return rc;
2380	if (u32Sep == ~0U)
2381	break;
2382	if (u32Sep != i)
2383	{
2384	AssertMsgFailed(("u32Sep=%#x (last)\n", u32Sep));
2385	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2386	}
2387
2388	/* Get the range details. */
2389	RTGCPHYS GCPhys;
2390	SSMR3GetGCPhys(pSSM, &GCPhys);
2391	RTGCPHYS GCPhysLast;
2392	SSMR3GetGCPhys(pSSM, &GCPhysLast);
2393	RTGCPHYS cb;
2394	SSMR3GetGCPhys(pSSM, &cb);
2395	uint8_t fHaveBits;
2396	rc = SSMR3GetU8(pSSM, &fHaveBits);
2397	if (RT_FAILURE(rc))
2398	return rc;
2399	if (fHaveBits & ~1)
2400	{
2401	AssertMsgFailed(("u32Sep=%#x (last)\n", u32Sep));
2402	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2403	}
2404
2405	/* Match it up with the current range. */
2406	if ( GCPhys != pRam->GCPhys
2407	\|\| GCPhysLast != pRam->GCPhysLast
2408	\|\| cb != pRam->cb
2409	\|\| fHaveBits != !!pRam->pvR3)
2410	{
2411	LogRel(("Ram range: %RGp-%RGp %RGp bytes %s\n"
2412	"State : %RGp-%RGp %RGp bytes %s\n",
2413	pRam->GCPhys, pRam->GCPhysLast, pRam->cb, pRam->pvR3 ? "bits" : "nobits",
2414	GCPhys, GCPhysLast, cb, fHaveBits ? "bits" : "nobits"));
2415	/*
2416	* If we're loading a state for debugging purpose, don't make a fuss if
2417	* the MMIO[2] and ROM stuff isn't 100% right, just skip the mismatches.
2418	*/
2419	if ( SSMR3HandleGetAfter(pSSM) != SSMAFTER_DEBUG_IT
2420	\|\| GCPhys < 8 * _1M)
2421	AssertFailedReturn(VERR_SSM_LOAD_CONFIG_MISMATCH);
2422
2423	RTGCPHYS cPages = ((GCPhysLast - GCPhys) + 1) >> PAGE_SHIFT;
2424	while (cPages-- > 0)
2425	{
2426	uint16_t u16Ignore;
2427	SSMR3GetU16(pSSM, &u16Ignore);
2428	}
2429	continue;
2430	}
2431
2432	/* Flags. */
2433	const unsigned cPages = pRam->cb >> PAGE_SHIFT;
2434	for (unsigned iPage = 0; iPage < cPages; iPage++)
2435	{
2436	uint16_t u16 = 0;
2437	SSMR3GetU16(pSSM, &u16);
2438	u16 &= PAGE_OFFSET_MASK & ~( RT_BIT(4) \| RT_BIT(5) \| RT_BIT(6)
2439	\| RT_BIT(7) \| RT_BIT(8) \| RT_BIT(9) \| RT_BIT(10) );
2440	// &= MM_RAM_FLAGS_DYNAMIC_ALLOC \| MM_RAM_FLAGS_RESERVED \| MM_RAM_FLAGS_ROM \| MM_RAM_FLAGS_MMIO \| MM_RAM_FLAGS_MMIO2
2441	pRam->aPages[iPage].HCPhys = PGM_PAGE_GET_HCPHYS(&pRam->aPages[iPage]) \| (RTHCPHYS)u16; /** @todo PAGE FLAGS */
2442	}
2443
2444	/* any memory associated with the range. */
2445	if (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)
2446	{
2447	for (unsigned iChunk = 0; iChunk < (pRam->cb >> PGM_DYNAMIC_CHUNK_SHIFT); iChunk++)
2448	{
2449	uint8_t fValidChunk;
2450
2451	rc = SSMR3GetU8(pSSM, &fValidChunk);
2452	if (RT_FAILURE(rc))
2453	return rc;
2454	if (fValidChunk > 1)
2455	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2456
2457	if (fValidChunk)
2458	{
2459	if (!pRam->paChunkR3Ptrs[iChunk])
2460	{
2461	rc = pgmr3PhysGrowRange(pVM, pRam->GCPhys + iChunk * PGM_DYNAMIC_CHUNK_SIZE);
2462	if (RT_FAILURE(rc))
2463	return rc;
2464	}
2465	Assert(pRam->paChunkR3Ptrs[iChunk]);
2466
2467	SSMR3GetMem(pSSM, (void *)pRam->paChunkR3Ptrs[iChunk], PGM_DYNAMIC_CHUNK_SIZE);
2468	}
2469	/* else nothing to do */
2470	}
2471	}
2472	else if (pRam->pvR3)
2473	{
2474	int rc = SSMR3GetMem(pSSM, pRam->pvR3, pRam->cb);
2475	if (RT_FAILURE(rc))
2476	{
2477	Log(("pgmR3Save: SSMR3GetMem(, %p, %#x) -> %Rrc\n", pRam->pvR3, pRam->cb, rc));
2478	return rc;
2479	}
2480	}
2481	}
2482
2483	/*
2484	* We require a full resync now.
2485	*/
2486	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3_NON_GLOBAL);
2487	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
2488	pPGM->fSyncFlags \|= PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL;
2489	pPGM->fPhysCacheFlushPending = true;
2490	pgmR3HandlerPhysicalUpdateAll(pVM);
2491
2492	/*
2493	* Change the paging mode.
2494	*/
2495	rc = PGMR3ChangeMode(pVM, pPGM->enmGuestMode);
2496
2497	/* Restore pVM->pgm.s.GCPhysCR3. */
2498	Assert(pVM->pgm.s.GCPhysCR3 == NIL_RTGCPHYS);
2499	RTGCPHYS GCPhysCR3 = CPUMGetGuestCR3(pVM);
2500	if ( pVM->pgm.s.enmGuestMode == PGMMODE_PAE
2501	\|\| pVM->pgm.s.enmGuestMode == PGMMODE_PAE_NX
2502	\|\| pVM->pgm.s.enmGuestMode == PGMMODE_AMD64
2503	\|\| pVM->pgm.s.enmGuestMode == PGMMODE_AMD64_NX)
2504	GCPhysCR3 = (GCPhysCR3 & X86_CR3_PAE_PAGE_MASK);
2505	else
2506	GCPhysCR3 = (GCPhysCR3 & X86_CR3_PAGE_MASK);
2507	pVM->pgm.s.GCPhysCR3 = GCPhysCR3;
2508
2509	return rc;
2510	}
2511
2512
2513	/**
2514	* Show paging mode.
2515	*
2516	* @param pVM VM Handle.
2517	* @param pHlp The info helpers.
2518	* @param pszArgs "all" (default), "guest", "shadow" or "host".
2519	*/
2520	static DECLCALLBACK(void) pgmR3InfoMode(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2521	{
2522	/* digest argument. */
2523	bool fGuest, fShadow, fHost;
2524	if (pszArgs)
2525	pszArgs = RTStrStripL(pszArgs);
2526	if (!pszArgs \|\| !*pszArgs \|\| strstr(pszArgs, "all"))
2527	fShadow = fHost = fGuest = true;
2528	else
2529	{
2530	fShadow = fHost = fGuest = false;
2531	if (strstr(pszArgs, "guest"))
2532	fGuest = true;
2533	if (strstr(pszArgs, "shadow"))
2534	fShadow = true;
2535	if (strstr(pszArgs, "host"))
2536	fHost = true;
2537	}
2538
2539	/* print info. */
2540	if (fGuest)
2541	pHlp->pfnPrintf(pHlp, "Guest paging mode: %s, changed %RU64 times, A20 %s\n",
2542	PGMGetModeName(pVM->pgm.s.enmGuestMode), pVM->pgm.s.cGuestModeChanges.c,
2543	pVM->pgm.s.fA20Enabled ? "enabled" : "disabled");
2544	if (fShadow)
2545	pHlp->pfnPrintf(pHlp, "Shadow paging mode: %s\n", PGMGetModeName(pVM->pgm.s.enmShadowMode));
2546	if (fHost)
2547	{
2548	const char *psz;
2549	switch (pVM->pgm.s.enmHostMode)
2550	{
2551	case SUPPAGINGMODE_INVALID: psz = "invalid"; break;
2552	case SUPPAGINGMODE_32_BIT: psz = "32-bit"; break;
2553	case SUPPAGINGMODE_32_BIT_GLOBAL: psz = "32-bit+G"; break;
2554	case SUPPAGINGMODE_PAE: psz = "PAE"; break;
2555	case SUPPAGINGMODE_PAE_GLOBAL: psz = "PAE+G"; break;
2556	case SUPPAGINGMODE_PAE_NX: psz = "PAE+NX"; break;
2557	case SUPPAGINGMODE_PAE_GLOBAL_NX: psz = "PAE+G+NX"; break;
2558	case SUPPAGINGMODE_AMD64: psz = "AMD64"; break;
2559	case SUPPAGINGMODE_AMD64_GLOBAL: psz = "AMD64+G"; break;
2560	case SUPPAGINGMODE_AMD64_NX: psz = "AMD64+NX"; break;
2561	case SUPPAGINGMODE_AMD64_GLOBAL_NX: psz = "AMD64+G+NX"; break;
2562	default: psz = "unknown"; break;
2563	}
2564	pHlp->pfnPrintf(pHlp, "Host paging mode: %s\n", psz);
2565	}
2566	}
2567
2568
2569	/**
2570	* Dump registered MMIO ranges to the log.
2571	*
2572	* @param pVM VM Handle.
2573	* @param pHlp The info helpers.
2574	* @param pszArgs Arguments, ignored.
2575	*/
2576	static DECLCALLBACK(void) pgmR3PhysInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2577	{
2578	NOREF(pszArgs);
2579	pHlp->pfnPrintf(pHlp,
2580	"RAM ranges (pVM=%p)\n"
2581	"%.s %.s\n",
2582	pVM,
2583	sizeof(RTGCPHYS) * 4 + 1, "GC Phys Range ",
2584	sizeof(RTHCPTR) * 2, "pvHC ");
2585
2586	for (PPGMRAMRANGE pCur = pVM->pgm.s.pRamRangesR3; pCur; pCur = pCur->pNextR3)
2587	pHlp->pfnPrintf(pHlp,
2588	"%RGp-%RGp %RHv %s\n",
2589	pCur->GCPhys,
2590	pCur->GCPhysLast,
2591	pCur->pvR3,
2592	pCur->pszDesc);
2593	}
2594
2595	/**
2596	* Dump the page directory to the log.
2597	*
2598	* @param pVM VM Handle.
2599	* @param pHlp The info helpers.
2600	* @param pszArgs Arguments, ignored.
2601	*/
2602	static DECLCALLBACK(void) pgmR3InfoCr3(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2603	{
2604	/** @todo fix this! Convert the PGMR3DumpHierarchyHC functions to do guest stuff. */
2605	/* Big pages supported? */
2606	const bool fPSE = !!(CPUMGetGuestCR4(pVM) & X86_CR4_PSE);
2607
2608	/* Global pages supported? */
2609	const bool fPGE = !!(CPUMGetGuestCR4(pVM) & X86_CR4_PGE);
2610
2611	NOREF(pszArgs);
2612
2613	/*
2614	* Get page directory addresses.
2615	*/
2616	PX86PD pPDSrc = pVM->pgm.s.pGst32BitPdR3;
2617	Assert(pPDSrc);
2618	Assert(PGMPhysGCPhys2HCPtrAssert(pVM, (RTGCPHYS)(CPUMGetGuestCR3(pVM) & X86_CR3_PAGE_MASK), sizeof(*pPDSrc)) == pPDSrc);
2619
2620	/*
2621	* Iterate the page directory.
2622	*/
2623	for (unsigned iPD = 0; iPD < RT_ELEMENTS(pPDSrc->a); iPD++)
2624	{
2625	X86PDE PdeSrc = pPDSrc->a[iPD];
2626	if (PdeSrc.n.u1Present)
2627	{
2628	if (PdeSrc.b.u1Size && fPSE)
2629	pHlp->pfnPrintf(pHlp,
2630	"%04X - %RGp P=%d U=%d RW=%d G=%d - BIG\n",
2631	iPD,
2632	pgmGstGet4MBPhysPage(&pVM->pgm.s, PdeSrc),
2633	PdeSrc.b.u1Present, PdeSrc.b.u1User, PdeSrc.b.u1Write, PdeSrc.b.u1Global && fPGE);
2634	else
2635	pHlp->pfnPrintf(pHlp,
2636	"%04X - %RGp P=%d U=%d RW=%d [G=%d]\n",
2637	iPD,
2638	(RTGCPHYS)(PdeSrc.u & X86_PDE_PG_MASK),
2639	PdeSrc.n.u1Present, PdeSrc.n.u1User, PdeSrc.n.u1Write, PdeSrc.b.u1Global && fPGE);
2640	}
2641	}
2642	}
2643
2644
2645	/**
2646	* Serivce a VMMCALLHOST_PGM_LOCK call.
2647	*
2648	* @returns VBox status code.
2649	* @param pVM The VM handle.
2650	*/
2651	VMMR3DECL(int) PGMR3LockCall(PVM pVM)
2652	{
2653	int rc = PDMR3CritSectEnterEx(&pVM->pgm.s.CritSect, true /* fHostCall */);
2654	AssertRC(rc);
2655	return rc;
2656	}
2657
2658
2659	/**
2660	* Converts a PGMMODE value to a PGM_TYPE_* \#define.
2661	*
2662	* @returns PGM_TYPE_*.
2663	* @param pgmMode The mode value to convert.
2664	*/
2665	DECLINLINE(unsigned) pgmModeToType(PGMMODE pgmMode)
2666	{
2667	switch (pgmMode)
2668	{
2669	case PGMMODE_REAL: return PGM_TYPE_REAL;
2670	case PGMMODE_PROTECTED: return PGM_TYPE_PROT;
2671	case PGMMODE_32_BIT: return PGM_TYPE_32BIT;
2672	case PGMMODE_PAE:
2673	case PGMMODE_PAE_NX: return PGM_TYPE_PAE;
2674	case PGMMODE_AMD64:
2675	case PGMMODE_AMD64_NX: return PGM_TYPE_AMD64;
2676	case PGMMODE_NESTED: return PGM_TYPE_NESTED;
2677	case PGMMODE_EPT: return PGM_TYPE_EPT;
2678	default:
2679	AssertFatalMsgFailed(("pgmMode=%d\n", pgmMode));
2680	}
2681	}
2682
2683
2684	/**
2685	* Gets the index into the paging mode data array of a SHW+GST mode.
2686	*
2687	* @returns PGM::paPagingData index.
2688	* @param uShwType The shadow paging mode type.
2689	* @param uGstType The guest paging mode type.
2690	*/
2691	DECLINLINE(unsigned) pgmModeDataIndex(unsigned uShwType, unsigned uGstType)
2692	{
2693	Assert(uShwType >= PGM_TYPE_32BIT && uShwType <= PGM_TYPE_MAX);
2694	Assert(uGstType >= PGM_TYPE_REAL && uGstType <= PGM_TYPE_AMD64);
2695	return (uShwType - PGM_TYPE_32BIT) * (PGM_TYPE_AMD64 - PGM_TYPE_REAL + 1)
2696	+ (uGstType - PGM_TYPE_REAL);
2697	}
2698
2699
2700	/**
2701	* Gets the index into the paging mode data array of a SHW+GST mode.
2702	*
2703	* @returns PGM::paPagingData index.
2704	* @param enmShw The shadow paging mode.
2705	* @param enmGst The guest paging mode.
2706	*/
2707	DECLINLINE(unsigned) pgmModeDataIndexByMode(PGMMODE enmShw, PGMMODE enmGst)
2708	{
2709	Assert(enmShw >= PGMMODE_32_BIT && enmShw <= PGMMODE_MAX);
2710	Assert(enmGst > PGMMODE_INVALID && enmGst < PGMMODE_MAX);
2711	return pgmModeDataIndex(pgmModeToType(enmShw), pgmModeToType(enmGst));
2712	}
2713
2714
2715	/**
2716	* Calculates the max data index.
2717	* @returns The number of entries in the paging data array.
2718	*/
2719	DECLINLINE(unsigned) pgmModeDataMaxIndex(void)
2720	{
2721	return pgmModeDataIndex(PGM_TYPE_MAX, PGM_TYPE_AMD64) + 1;
2722	}
2723
2724
2725	/**
2726	* Initializes the paging mode data kept in PGM::paModeData.
2727	*
2728	* @param pVM The VM handle.
2729	* @param fResolveGCAndR0 Indicate whether or not GC and Ring-0 symbols can be resolved now.
2730	* This is used early in the init process to avoid trouble with PDM
2731	* not being initialized yet.
2732	*/
2733	static int pgmR3ModeDataInit(PVM pVM, bool fResolveGCAndR0)
2734	{
2735	PPGMMODEDATA pModeData;
2736	int rc;
2737
2738	/*
2739	* Allocate the array on the first call.
2740	*/
2741	if (!pVM->pgm.s.paModeData)
2742	{
2743	pVM->pgm.s.paModeData = (PPGMMODEDATA)MMR3HeapAllocZ(pVM, MM_TAG_PGM, sizeof(PGMMODEDATA) * pgmModeDataMaxIndex());
2744	AssertReturn(pVM->pgm.s.paModeData, VERR_NO_MEMORY);
2745	}
2746
2747	/*
2748	* Initialize the array entries.
2749	*/
2750	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_32BIT, PGM_TYPE_REAL)];
2751	pModeData->uShwType = PGM_TYPE_32BIT;
2752	pModeData->uGstType = PGM_TYPE_REAL;
2753	rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2754	rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2755	rc = PGM_BTH_NAME_32BIT_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2756
2757	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_32BIT, PGMMODE_PROTECTED)];
2758	pModeData->uShwType = PGM_TYPE_32BIT;
2759	pModeData->uGstType = PGM_TYPE_PROT;
2760	rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2761	rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2762	rc = PGM_BTH_NAME_32BIT_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2763
2764	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_32BIT, PGM_TYPE_32BIT)];
2765	pModeData->uShwType = PGM_TYPE_32BIT;
2766	pModeData->uGstType = PGM_TYPE_32BIT;
2767	rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2768	rc = PGM_GST_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2769	rc = PGM_BTH_NAME_32BIT_32BIT(InitData)(pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2770
2771	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_REAL)];
2772	pModeData->uShwType = PGM_TYPE_PAE;
2773	pModeData->uGstType = PGM_TYPE_REAL;
2774	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2775	rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2776	rc = PGM_BTH_NAME_PAE_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2777
2778	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_PROT)];
2779	pModeData->uShwType = PGM_TYPE_PAE;
2780	pModeData->uGstType = PGM_TYPE_PROT;
2781	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2782	rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2783	rc = PGM_BTH_NAME_PAE_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2784
2785	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_32BIT)];
2786	pModeData->uShwType = PGM_TYPE_PAE;
2787	pModeData->uGstType = PGM_TYPE_32BIT;
2788	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2789	rc = PGM_GST_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2790	rc = PGM_BTH_NAME_PAE_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2791
2792	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_PAE)];
2793	pModeData->uShwType = PGM_TYPE_PAE;
2794	pModeData->uGstType = PGM_TYPE_PAE;
2795	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2796	rc = PGM_GST_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2797	rc = PGM_BTH_NAME_PAE_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2798
2799	#ifdef VBOX_WITH_64_BITS_GUESTS
2800	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_AMD64, PGM_TYPE_AMD64)];
2801	pModeData->uShwType = PGM_TYPE_AMD64;
2802	pModeData->uGstType = PGM_TYPE_AMD64;
2803	rc = PGM_SHW_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2804	rc = PGM_GST_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2805	rc = PGM_BTH_NAME_AMD64_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2806	#endif
2807
2808	/* The nested paging mode. */
2809	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_REAL)];
2810	pModeData->uShwType = PGM_TYPE_NESTED;
2811	pModeData->uGstType = PGM_TYPE_REAL;
2812	rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2813	rc = PGM_BTH_NAME_NESTED_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2814
2815	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGMMODE_PROTECTED)];
2816	pModeData->uShwType = PGM_TYPE_NESTED;
2817	pModeData->uGstType = PGM_TYPE_PROT;
2818	rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2819	rc = PGM_BTH_NAME_NESTED_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2820
2821	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_32BIT)];
2822	pModeData->uShwType = PGM_TYPE_NESTED;
2823	pModeData->uGstType = PGM_TYPE_32BIT;
2824	rc = PGM_GST_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2825	rc = PGM_BTH_NAME_NESTED_32BIT(InitData)(pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2826
2827	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_PAE)];
2828	pModeData->uShwType = PGM_TYPE_NESTED;
2829	pModeData->uGstType = PGM_TYPE_PAE;
2830	rc = PGM_GST_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2831	rc = PGM_BTH_NAME_NESTED_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2832
2833	#ifdef VBOX_WITH_64_BITS_GUESTS
2834	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_AMD64)];
2835	pModeData->uShwType = PGM_TYPE_NESTED;
2836	pModeData->uGstType = PGM_TYPE_AMD64;
2837	rc = PGM_GST_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2838	rc = PGM_BTH_NAME_NESTED_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2839	#endif
2840
2841	/* The shadow part of the nested callback mode depends on the host paging mode (AMD-V only). */
2842	switch(pVM->pgm.s.enmHostMode)
2843	{
2844	case SUPPAGINGMODE_32_BIT:
2845	case SUPPAGINGMODE_32_BIT_GLOBAL:
2846	#ifdef VBOX_WITH_64_BITS_GUESTS
2847	for (unsigned i=PGM_TYPE_REAL;i<=PGM_TYPE_AMD64;i++)
2848	#else
2849	for (unsigned i=PGM_TYPE_REAL;i<=PGM_TYPE_PAE;i++)
2850	#endif
2851	{
2852	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, i)];
2853	rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2854	}
2855	break;
2856
2857	case SUPPAGINGMODE_PAE:
2858	case SUPPAGINGMODE_PAE_NX:
2859	case SUPPAGINGMODE_PAE_GLOBAL:
2860	case SUPPAGINGMODE_PAE_GLOBAL_NX:
2861	#ifdef VBOX_WITH_64_BITS_GUESTS
2862	for (unsigned i=PGM_TYPE_REAL;i<=PGM_TYPE_AMD64;i++)
2863	#else
2864	for (unsigned i=PGM_TYPE_REAL;i<=PGM_TYPE_PAE;i++)
2865	#endif
2866	{
2867	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, i)];
2868	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2869	}
2870	break;
2871
2872	case SUPPAGINGMODE_AMD64:
2873	case SUPPAGINGMODE_AMD64_GLOBAL:
2874	case SUPPAGINGMODE_AMD64_NX:
2875	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
2876	#ifdef VBOX_WITH_64_BITS_GUESTS
2877	for (unsigned i=PGM_TYPE_REAL;i<=PGM_TYPE_AMD64;i++)
2878	#else
2879	for (unsigned i=PGM_TYPE_REAL;i<=PGM_TYPE_PAE;i++)
2880	#endif
2881	{
2882	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, i)];
2883	rc = PGM_SHW_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2884	}
2885	break;
2886	default:
2887	AssertFailed();
2888	break;
2889	}
2890
2891	/* Extended paging (EPT) / Intel VT-x */
2892	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_REAL)];
2893	pModeData->uShwType = PGM_TYPE_EPT;
2894	pModeData->uGstType = PGM_TYPE_REAL;
2895	rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2896	rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2897	rc = PGM_BTH_NAME_EPT_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2898
2899	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_PROT)];
2900	pModeData->uShwType = PGM_TYPE_EPT;
2901	pModeData->uGstType = PGM_TYPE_PROT;
2902	rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2903	rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2904	rc = PGM_BTH_NAME_EPT_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2905
2906	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_32BIT)];
2907	pModeData->uShwType = PGM_TYPE_EPT;
2908	pModeData->uGstType = PGM_TYPE_32BIT;
2909	rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2910	rc = PGM_GST_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2911	rc = PGM_BTH_NAME_EPT_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2912
2913	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_PAE)];
2914	pModeData->uShwType = PGM_TYPE_EPT;
2915	pModeData->uGstType = PGM_TYPE_PAE;
2916	rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2917	rc = PGM_GST_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2918	rc = PGM_BTH_NAME_EPT_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2919
2920	#ifdef VBOX_WITH_64_BITS_GUESTS
2921	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_AMD64)];
2922	pModeData->uShwType = PGM_TYPE_EPT;
2923	pModeData->uGstType = PGM_TYPE_AMD64;
2924	rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2925	rc = PGM_GST_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2926	rc = PGM_BTH_NAME_EPT_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2927	#endif
2928	return VINF_SUCCESS;
2929	}
2930
2931
2932	/**
2933	* Switch to different (or relocated in the relocate case) mode data.
2934	*
2935	* @param pVM The VM handle.
2936	* @param enmShw The the shadow paging mode.
2937	* @param enmGst The the guest paging mode.
2938	*/
2939	static void pgmR3ModeDataSwitch(PVM pVM, PGMMODE enmShw, PGMMODE enmGst)
2940	{
2941	PPGMMODEDATA pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndexByMode(enmShw, enmGst)];
2942
2943	Assert(pModeData->uGstType == pgmModeToType(enmGst));
2944	Assert(pModeData->uShwType == pgmModeToType(enmShw));
2945
2946	/* shadow */
2947	pVM->pgm.s.pfnR3ShwRelocate = pModeData->pfnR3ShwRelocate;
2948	pVM->pgm.s.pfnR3ShwExit = pModeData->pfnR3ShwExit;
2949	pVM->pgm.s.pfnR3ShwGetPage = pModeData->pfnR3ShwGetPage;
2950	Assert(pVM->pgm.s.pfnR3ShwGetPage);
2951	pVM->pgm.s.pfnR3ShwModifyPage = pModeData->pfnR3ShwModifyPage;
2952
2953	pVM->pgm.s.pfnRCShwGetPage = pModeData->pfnRCShwGetPage;
2954	pVM->pgm.s.pfnRCShwModifyPage = pModeData->pfnRCShwModifyPage;
2955
2956	pVM->pgm.s.pfnR0ShwGetPage = pModeData->pfnR0ShwGetPage;
2957	pVM->pgm.s.pfnR0ShwModifyPage = pModeData->pfnR0ShwModifyPage;
2958
2959
2960	/* guest */
2961	pVM->pgm.s.pfnR3GstRelocate = pModeData->pfnR3GstRelocate;
2962	pVM->pgm.s.pfnR3GstExit = pModeData->pfnR3GstExit;
2963	pVM->pgm.s.pfnR3GstGetPage = pModeData->pfnR3GstGetPage;
2964	Assert(pVM->pgm.s.pfnR3GstGetPage);
2965	pVM->pgm.s.pfnR3GstModifyPage = pModeData->pfnR3GstModifyPage;
2966	pVM->pgm.s.pfnR3GstGetPDE = pModeData->pfnR3GstGetPDE;
2967	pVM->pgm.s.pfnR3GstMonitorCR3 = pModeData->pfnR3GstMonitorCR3;
2968	pVM->pgm.s.pfnR3GstUnmonitorCR3 = pModeData->pfnR3GstUnmonitorCR3;
2969	pVM->pgm.s.pfnR3GstMapCR3 = pModeData->pfnR3GstMapCR3;
2970	pVM->pgm.s.pfnR3GstUnmapCR3 = pModeData->pfnR3GstUnmapCR3;
2971	pVM->pgm.s.pfnR3GstWriteHandlerCR3 = pModeData->pfnR3GstWriteHandlerCR3;
2972	pVM->pgm.s.pszR3GstWriteHandlerCR3 = pModeData->pszR3GstWriteHandlerCR3;
2973	pVM->pgm.s.pfnR3GstPAEWriteHandlerCR3 = pModeData->pfnR3GstPAEWriteHandlerCR3;
2974	pVM->pgm.s.pszR3GstPAEWriteHandlerCR3 = pModeData->pszR3GstPAEWriteHandlerCR3;
2975
2976	pVM->pgm.s.pfnRCGstGetPage = pModeData->pfnRCGstGetPage;
2977	pVM->pgm.s.pfnRCGstModifyPage = pModeData->pfnRCGstModifyPage;
2978	pVM->pgm.s.pfnRCGstGetPDE = pModeData->pfnRCGstGetPDE;
2979	pVM->pgm.s.pfnRCGstMonitorCR3 = pModeData->pfnRCGstMonitorCR3;
2980	pVM->pgm.s.pfnRCGstUnmonitorCR3 = pModeData->pfnRCGstUnmonitorCR3;
2981	pVM->pgm.s.pfnRCGstMapCR3 = pModeData->pfnRCGstMapCR3;
2982	pVM->pgm.s.pfnRCGstUnmapCR3 = pModeData->pfnRCGstUnmapCR3;
2983	pVM->pgm.s.pfnRCGstWriteHandlerCR3 = pModeData->pfnRCGstWriteHandlerCR3;
2984	pVM->pgm.s.pfnRCGstPAEWriteHandlerCR3 = pModeData->pfnRCGstPAEWriteHandlerCR3;
2985
2986	pVM->pgm.s.pfnR0GstGetPage = pModeData->pfnR0GstGetPage;
2987	pVM->pgm.s.pfnR0GstModifyPage = pModeData->pfnR0GstModifyPage;
2988	pVM->pgm.s.pfnR0GstGetPDE = pModeData->pfnR0GstGetPDE;
2989	pVM->pgm.s.pfnR0GstMonitorCR3 = pModeData->pfnR0GstMonitorCR3;
2990	pVM->pgm.s.pfnR0GstUnmonitorCR3 = pModeData->pfnR0GstUnmonitorCR3;
2991	pVM->pgm.s.pfnR0GstMapCR3 = pModeData->pfnR0GstMapCR3;
2992	pVM->pgm.s.pfnR0GstUnmapCR3 = pModeData->pfnR0GstUnmapCR3;
2993	pVM->pgm.s.pfnR0GstWriteHandlerCR3 = pModeData->pfnR0GstWriteHandlerCR3;
2994	pVM->pgm.s.pfnR0GstPAEWriteHandlerCR3 = pModeData->pfnR0GstPAEWriteHandlerCR3;
2995
2996
2997	/* both */
2998	pVM->pgm.s.pfnR3BthRelocate = pModeData->pfnR3BthRelocate;
2999	pVM->pgm.s.pfnR3BthInvalidatePage = pModeData->pfnR3BthInvalidatePage;
3000	pVM->pgm.s.pfnR3BthSyncCR3 = pModeData->pfnR3BthSyncCR3;
3001	Assert(pVM->pgm.s.pfnR3BthSyncCR3);
3002	pVM->pgm.s.pfnR3BthSyncPage = pModeData->pfnR3BthSyncPage;
3003	pVM->pgm.s.pfnR3BthPrefetchPage = pModeData->pfnR3BthPrefetchPage;
3004	pVM->pgm.s.pfnR3BthVerifyAccessSyncPage = pModeData->pfnR3BthVerifyAccessSyncPage;
3005	#ifdef VBOX_STRICT
3006	pVM->pgm.s.pfnR3BthAssertCR3 = pModeData->pfnR3BthAssertCR3;
3007	#endif
3008
3009	pVM->pgm.s.pfnRCBthTrap0eHandler = pModeData->pfnRCBthTrap0eHandler;
3010	pVM->pgm.s.pfnRCBthInvalidatePage = pModeData->pfnRCBthInvalidatePage;
3011	pVM->pgm.s.pfnRCBthSyncCR3 = pModeData->pfnRCBthSyncCR3;
3012	pVM->pgm.s.pfnRCBthSyncPage = pModeData->pfnRCBthSyncPage;
3013	pVM->pgm.s.pfnRCBthPrefetchPage = pModeData->pfnRCBthPrefetchPage;
3014	pVM->pgm.s.pfnRCBthVerifyAccessSyncPage = pModeData->pfnRCBthVerifyAccessSyncPage;
3015	#ifdef VBOX_STRICT
3016	pVM->pgm.s.pfnRCBthAssertCR3 = pModeData->pfnRCBthAssertCR3;
3017	#endif
3018
3019	pVM->pgm.s.pfnR0BthTrap0eHandler = pModeData->pfnR0BthTrap0eHandler;
3020	pVM->pgm.s.pfnR0BthInvalidatePage = pModeData->pfnR0BthInvalidatePage;
3021	pVM->pgm.s.pfnR0BthSyncCR3 = pModeData->pfnR0BthSyncCR3;
3022	pVM->pgm.s.pfnR0BthSyncPage = pModeData->pfnR0BthSyncPage;
3023	pVM->pgm.s.pfnR0BthPrefetchPage = pModeData->pfnR0BthPrefetchPage;
3024	pVM->pgm.s.pfnR0BthVerifyAccessSyncPage = pModeData->pfnR0BthVerifyAccessSyncPage;
3025	#ifdef VBOX_STRICT
3026	pVM->pgm.s.pfnR0BthAssertCR3 = pModeData->pfnR0BthAssertCR3;
3027	#endif
3028	}
3029
3030
3031	/**
3032	* Calculates the shadow paging mode.
3033	*
3034	* @returns The shadow paging mode.
3035	* @param pVM VM handle.
3036	* @param enmGuestMode The guest mode.
3037	* @param enmHostMode The host mode.
3038	* @param enmShadowMode The current shadow mode.
3039	* @param penmSwitcher Where to store the switcher to use.
3040	* VMMSWITCHER_INVALID means no change.
3041	*/
3042	static PGMMODE pgmR3CalcShadowMode(PVM pVM, PGMMODE enmGuestMode, SUPPAGINGMODE enmHostMode, PGMMODE enmShadowMode, VMMSWITCHER *penmSwitcher)
3043	{
3044	VMMSWITCHER enmSwitcher = VMMSWITCHER_INVALID;
3045	switch (enmGuestMode)
3046	{
3047	/*
3048	* When switching to real or protected mode we don't change
3049	* anything since it's likely that we'll switch back pretty soon.
3050	*
3051	* During pgmR3InitPaging we'll end up here with PGMMODE_INVALID
3052	* and is supposed to determine which shadow paging and switcher to
3053	* use during init.
3054	*/
3055	case PGMMODE_REAL:
3056	case PGMMODE_PROTECTED:
3057	if ( enmShadowMode != PGMMODE_INVALID
3058	&& !HWACCMIsEnabled(pVM) /* always switch in hwaccm mode! */)
3059	break; /* (no change) */
3060
3061	switch (enmHostMode)
3062	{
3063	case SUPPAGINGMODE_32_BIT:
3064	case SUPPAGINGMODE_32_BIT_GLOBAL:
3065	enmShadowMode = PGMMODE_32_BIT;
3066	enmSwitcher = VMMSWITCHER_32_TO_32;
3067	break;
3068
3069	case SUPPAGINGMODE_PAE:
3070	case SUPPAGINGMODE_PAE_NX:
3071	case SUPPAGINGMODE_PAE_GLOBAL:
3072	case SUPPAGINGMODE_PAE_GLOBAL_NX:
3073	enmShadowMode = PGMMODE_PAE;
3074	enmSwitcher = VMMSWITCHER_PAE_TO_PAE;
3075	#ifdef DEBUG_bird
3076	if (RTEnvExist("VBOX_32BIT"))
3077	{
3078	enmShadowMode = PGMMODE_32_BIT;
3079	enmSwitcher = VMMSWITCHER_PAE_TO_32;
3080	}
3081	#endif
3082	break;
3083
3084	case SUPPAGINGMODE_AMD64:
3085	case SUPPAGINGMODE_AMD64_GLOBAL:
3086	case SUPPAGINGMODE_AMD64_NX:
3087	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
3088	enmShadowMode = PGMMODE_PAE;
3089	enmSwitcher = VMMSWITCHER_AMD64_TO_PAE;
3090	#ifdef DEBUG_bird
3091	if (RTEnvExist("VBOX_32BIT"))
3092	{
3093	enmShadowMode = PGMMODE_32_BIT;
3094	enmSwitcher = VMMSWITCHER_AMD64_TO_32;
3095	}
3096	#endif
3097	break;
3098
3099	default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
3100	}
3101	break;
3102
3103	case PGMMODE_32_BIT:
3104	switch (enmHostMode)
3105	{
3106	case SUPPAGINGMODE_32_BIT:
3107	case SUPPAGINGMODE_32_BIT_GLOBAL:
3108	enmShadowMode = PGMMODE_32_BIT;
3109	enmSwitcher = VMMSWITCHER_32_TO_32;
3110	break;
3111
3112	case SUPPAGINGMODE_PAE:
3113	case SUPPAGINGMODE_PAE_NX:
3114	case SUPPAGINGMODE_PAE_GLOBAL:
3115	case SUPPAGINGMODE_PAE_GLOBAL_NX:
3116	enmShadowMode = PGMMODE_PAE;
3117	enmSwitcher = VMMSWITCHER_PAE_TO_PAE;
3118	#ifdef DEBUG_bird
3119	if (RTEnvExist("VBOX_32BIT"))
3120	{
3121	enmShadowMode = PGMMODE_32_BIT;
3122	enmSwitcher = VMMSWITCHER_PAE_TO_32;
3123	}
3124	#endif
3125	break;
3126
3127	case SUPPAGINGMODE_AMD64:
3128	case SUPPAGINGMODE_AMD64_GLOBAL:
3129	case SUPPAGINGMODE_AMD64_NX:
3130	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
3131	enmShadowMode = PGMMODE_PAE;
3132	enmSwitcher = VMMSWITCHER_AMD64_TO_PAE;
3133	#ifdef DEBUG_bird
3134	if (RTEnvExist("VBOX_32BIT"))
3135	{
3136	enmShadowMode = PGMMODE_32_BIT;
3137	enmSwitcher = VMMSWITCHER_AMD64_TO_32;
3138	}
3139	#endif
3140	break;
3141
3142	default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
3143	}
3144	break;
3145
3146	case PGMMODE_PAE:
3147	case PGMMODE_PAE_NX: /** @todo This might require more switchers and guest+both modes. */
3148	switch (enmHostMode)
3149	{
3150	case SUPPAGINGMODE_32_BIT:
3151	case SUPPAGINGMODE_32_BIT_GLOBAL:
3152	enmShadowMode = PGMMODE_PAE;
3153	enmSwitcher = VMMSWITCHER_32_TO_PAE;
3154	break;
3155
3156	case SUPPAGINGMODE_PAE:
3157	case SUPPAGINGMODE_PAE_NX:
3158	case SUPPAGINGMODE_PAE_GLOBAL:
3159	case SUPPAGINGMODE_PAE_GLOBAL_NX:
3160	enmShadowMode = PGMMODE_PAE;
3161	enmSwitcher = VMMSWITCHER_PAE_TO_PAE;
3162	break;
3163
3164	case SUPPAGINGMODE_AMD64:
3165	case SUPPAGINGMODE_AMD64_GLOBAL:
3166	case SUPPAGINGMODE_AMD64_NX:
3167	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
3168	enmShadowMode = PGMMODE_PAE;
3169	enmSwitcher = VMMSWITCHER_AMD64_TO_PAE;
3170	break;
3171
3172	default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
3173	}
3174	break;
3175
3176	case PGMMODE_AMD64:
3177	case PGMMODE_AMD64_NX:
3178	switch (enmHostMode)
3179	{
3180	case SUPPAGINGMODE_32_BIT:
3181	case SUPPAGINGMODE_32_BIT_GLOBAL:
3182	enmShadowMode = PGMMODE_PAE;
3183	enmSwitcher = VMMSWITCHER_32_TO_AMD64;
3184	break;
3185
3186	case SUPPAGINGMODE_PAE:
3187	case SUPPAGINGMODE_PAE_NX:
3188	case SUPPAGINGMODE_PAE_GLOBAL:
3189	case SUPPAGINGMODE_PAE_GLOBAL_NX:
3190	enmShadowMode = PGMMODE_PAE;
3191	enmSwitcher = VMMSWITCHER_PAE_TO_AMD64;
3192	break;
3193
3194	case SUPPAGINGMODE_AMD64:
3195	case SUPPAGINGMODE_AMD64_GLOBAL:
3196	case SUPPAGINGMODE_AMD64_NX:
3197	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
3198	enmShadowMode = PGMMODE_AMD64;
3199	enmSwitcher = VMMSWITCHER_AMD64_TO_AMD64;
3200	break;
3201
3202	default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
3203	}
3204	break;
3205
3206
3207	default:
3208	AssertReleaseMsgFailed(("enmGuestMode=%d\n", enmGuestMode));
3209	return PGMMODE_INVALID;
3210	}
3211	/* Override the shadow mode is nested paging is active. */
3212	if (HWACCMIsNestedPagingActive(pVM))
3213	enmShadowMode = HWACCMGetPagingMode(pVM);
3214
3215	*penmSwitcher = enmSwitcher;
3216	return enmShadowMode;
3217	}
3218
3219
3220	/**
3221	* Performs the actual mode change.
3222	* This is called by PGMChangeMode and pgmR3InitPaging().
3223	*
3224	* @returns VBox status code.
3225	* @param pVM VM handle.
3226	* @param enmGuestMode The new guest mode. This is assumed to be different from
3227	* the current mode.
3228	*/
3229	VMMR3DECL(int) PGMR3ChangeMode(PVM pVM, PGMMODE enmGuestMode)
3230	{
3231	Log(("PGMR3ChangeMode: Guest mode: %s -> %s\n", PGMGetModeName(pVM->pgm.s.enmGuestMode), PGMGetModeName(enmGuestMode)));
3232	STAM_REL_COUNTER_INC(&pVM->pgm.s.cGuestModeChanges);
3233
3234	/*
3235	* Calc the shadow mode and switcher.
3236	*/
3237	VMMSWITCHER enmSwitcher;
3238	PGMMODE enmShadowMode = pgmR3CalcShadowMode(pVM, enmGuestMode, pVM->pgm.s.enmHostMode, pVM->pgm.s.enmShadowMode, &enmSwitcher);
3239	if (enmSwitcher != VMMSWITCHER_INVALID)
3240	{
3241	/*
3242	* Select new switcher.
3243	*/
3244	int rc = VMMR3SelectSwitcher(pVM, enmSwitcher);
3245	if (RT_FAILURE(rc))
3246	{
3247	AssertReleaseMsgFailed(("VMMR3SelectSwitcher(%d) -> %Rrc\n", enmSwitcher, rc));
3248	return rc;
3249	}
3250	}
3251
3252	/*
3253	* Exit old mode(s).
3254	*/
3255	/* shadow */
3256	if (enmShadowMode != pVM->pgm.s.enmShadowMode)
3257	{
3258	LogFlow(("PGMR3ChangeMode: Shadow mode: %s -> %s\n", PGMGetModeName(pVM->pgm.s.enmShadowMode), PGMGetModeName(enmShadowMode)));
3259	if (PGM_SHW_PFN(Exit, pVM))
3260	{
3261	int rc = PGM_SHW_PFN(Exit, pVM)(pVM);
3262	if (RT_FAILURE(rc))
3263	{
3264	AssertMsgFailed(("Exit failed for shadow mode %d: %Rrc\n", pVM->pgm.s.enmShadowMode, rc));
3265	return rc;
3266	}
3267	}
3268
3269	}
3270	else
3271	LogFlow(("PGMR3ChangeMode: Shadow mode remains: %s\n", PGMGetModeName(pVM->pgm.s.enmShadowMode)));
3272
3273	/* guest */
3274	if (PGM_GST_PFN(Exit, pVM))
3275	{
3276	int rc = PGM_GST_PFN(Exit, pVM)(pVM);
3277	if (RT_FAILURE(rc))
3278	{
3279	AssertMsgFailed(("Exit failed for guest mode %d: %Rrc\n", pVM->pgm.s.enmGuestMode, rc));
3280	return rc;
3281	}
3282	}
3283
3284	/*
3285	* Load new paging mode data.
3286	*/
3287	pgmR3ModeDataSwitch(pVM, enmShadowMode, enmGuestMode);
3288
3289	/*
3290	* Enter new shadow mode (if changed).
3291	*/
3292	if (enmShadowMode != pVM->pgm.s.enmShadowMode)
3293	{
3294	int rc;
3295	pVM->pgm.s.enmShadowMode = enmShadowMode;
3296	switch (enmShadowMode)
3297	{
3298	case PGMMODE_32_BIT:
3299	rc = PGM_SHW_NAME_32BIT(Enter)(pVM);
3300	break;
3301	case PGMMODE_PAE:
3302	case PGMMODE_PAE_NX:
3303	rc = PGM_SHW_NAME_PAE(Enter)(pVM);
3304	break;
3305	case PGMMODE_AMD64:
3306	case PGMMODE_AMD64_NX:
3307	rc = PGM_SHW_NAME_AMD64(Enter)(pVM);
3308	break;
3309	case PGMMODE_NESTED:
3310	rc = PGM_SHW_NAME_NESTED(Enter)(pVM);
3311	break;
3312	case PGMMODE_EPT:
3313	rc = PGM_SHW_NAME_EPT(Enter)(pVM);
3314	break;
3315	case PGMMODE_REAL:
3316	case PGMMODE_PROTECTED:
3317	default:
3318	AssertReleaseMsgFailed(("enmShadowMode=%d\n", enmShadowMode));
3319	return VERR_INTERNAL_ERROR;
3320	}
3321	if (RT_FAILURE(rc))
3322	{
3323	AssertReleaseMsgFailed(("Entering enmShadowMode=%d failed: %Rrc\n", enmShadowMode, rc));
3324	pVM->pgm.s.enmShadowMode = PGMMODE_INVALID;
3325	return rc;
3326	}
3327	}
3328
3329	/** @todo This is a bug!
3330	*
3331	* We must flush the PGM pool cache if the guest mode changes; we don't always
3332	* switch shadow paging mode (e.g. protected->32-bit) and shouldn't reuse
3333	* the shadow page tables.
3334	*
3335	* That only applies when switching between paging and non-paging modes.
3336	*/
3337	/** @todo A20 setting */
3338	if ( pVM->pgm.s.CTX_SUFF(pPool)
3339	&& !HWACCMIsNestedPagingActive(pVM)
3340	&& PGMMODE_WITH_PAGING(pVM->pgm.s.enmGuestMode) != PGMMODE_WITH_PAGING(enmGuestMode))
3341	{
3342	Log(("PGMR3ChangeMode: changing guest paging mode -> flush pgm pool cache!\n"));
3343	pgmPoolFlushAll(pVM);
3344	}
3345
3346	/*
3347	* Enter the new guest and shadow+guest modes.
3348	*/
3349	int rc = -1;
3350	int rc2 = -1;
3351	RTGCPHYS GCPhysCR3 = NIL_RTGCPHYS;
3352	pVM->pgm.s.enmGuestMode = enmGuestMode;
3353	switch (enmGuestMode)
3354	{
3355	case PGMMODE_REAL:
3356	rc = PGM_GST_NAME_REAL(Enter)(pVM, NIL_RTGCPHYS);
3357	switch (pVM->pgm.s.enmShadowMode)
3358	{
3359	case PGMMODE_32_BIT:
3360	rc2 = PGM_BTH_NAME_32BIT_REAL(Enter)(pVM, NIL_RTGCPHYS);
3361	break;
3362	case PGMMODE_PAE:
3363	case PGMMODE_PAE_NX:
3364	rc2 = PGM_BTH_NAME_PAE_REAL(Enter)(pVM, NIL_RTGCPHYS);
3365	break;
3366	case PGMMODE_NESTED:
3367	rc2 = PGM_BTH_NAME_NESTED_REAL(Enter)(pVM, NIL_RTGCPHYS);
3368	break;
3369	case PGMMODE_EPT:
3370	rc2 = PGM_BTH_NAME_EPT_REAL(Enter)(pVM, NIL_RTGCPHYS);
3371	break;
3372	case PGMMODE_AMD64:
3373	case PGMMODE_AMD64_NX:
3374	AssertMsgFailed(("Should use PAE shadow mode!\n"));
3375	default: AssertFailed(); break;
3376	}
3377	break;
3378
3379	case PGMMODE_PROTECTED:
3380	rc = PGM_GST_NAME_PROT(Enter)(pVM, NIL_RTGCPHYS);
3381	switch (pVM->pgm.s.enmShadowMode)
3382	{
3383	case PGMMODE_32_BIT:
3384	rc2 = PGM_BTH_NAME_32BIT_PROT(Enter)(pVM, NIL_RTGCPHYS);
3385	break;
3386	case PGMMODE_PAE:
3387	case PGMMODE_PAE_NX:
3388	rc2 = PGM_BTH_NAME_PAE_PROT(Enter)(pVM, NIL_RTGCPHYS);
3389	break;
3390	case PGMMODE_NESTED:
3391	rc2 = PGM_BTH_NAME_NESTED_PROT(Enter)(pVM, NIL_RTGCPHYS);
3392	break;
3393	case PGMMODE_EPT:
3394	rc2 = PGM_BTH_NAME_EPT_PROT(Enter)(pVM, NIL_RTGCPHYS);
3395	break;
3396	case PGMMODE_AMD64:
3397	case PGMMODE_AMD64_NX:
3398	AssertMsgFailed(("Should use PAE shadow mode!\n"));
3399	default: AssertFailed(); break;
3400	}
3401	break;
3402
3403	case PGMMODE_32_BIT:
3404	GCPhysCR3 = CPUMGetGuestCR3(pVM) & X86_CR3_PAGE_MASK;
3405	rc = PGM_GST_NAME_32BIT(Enter)(pVM, GCPhysCR3);
3406	switch (pVM->pgm.s.enmShadowMode)
3407	{
3408	case PGMMODE_32_BIT:
3409	rc2 = PGM_BTH_NAME_32BIT_32BIT(Enter)(pVM, GCPhysCR3);
3410	break;
3411	case PGMMODE_PAE:
3412	case PGMMODE_PAE_NX:
3413	rc2 = PGM_BTH_NAME_PAE_32BIT(Enter)(pVM, GCPhysCR3);
3414	break;
3415	case PGMMODE_NESTED:
3416	rc2 = PGM_BTH_NAME_NESTED_32BIT(Enter)(pVM, GCPhysCR3);
3417	break;
3418	case PGMMODE_EPT:
3419	rc2 = PGM_BTH_NAME_EPT_32BIT(Enter)(pVM, GCPhysCR3);
3420	break;
3421	case PGMMODE_AMD64:
3422	case PGMMODE_AMD64_NX:
3423	AssertMsgFailed(("Should use PAE shadow mode!\n"));
3424	default: AssertFailed(); break;
3425	}
3426	break;
3427
3428	case PGMMODE_PAE_NX:
3429	case PGMMODE_PAE:
3430	{
3431	uint32_t u32Dummy, u32Features;
3432
3433	CPUMGetGuestCpuId(pVM, 1, &u32Dummy, &u32Dummy, &u32Dummy, &u32Features);
3434	if (!(u32Features & X86_CPUID_FEATURE_EDX_PAE))
3435	{
3436	/* Pause first, then inform Main. */
3437	rc = VMR3SuspendNoSave(pVM);
3438	AssertRC(rc);
3439
3440	VMSetRuntimeError(pVM, true, "PAEmode",
3441	N_("The guest is trying to switch to the PAE mode which is currently disabled by default in VirtualBox. PAE support can be enabled using the VM settings (General/Advanced)"));
3442	/* we must return VINF_SUCCESS here otherwise the recompiler will assert */
3443	return VINF_SUCCESS;
3444	}
3445	GCPhysCR3 = CPUMGetGuestCR3(pVM) & X86_CR3_PAE_PAGE_MASK;
3446	rc = PGM_GST_NAME_PAE(Enter)(pVM, GCPhysCR3);
3447	switch (pVM->pgm.s.enmShadowMode)
3448	{
3449	case PGMMODE_PAE:
3450	case PGMMODE_PAE_NX:
3451	rc2 = PGM_BTH_NAME_PAE_PAE(Enter)(pVM, GCPhysCR3);
3452	break;
3453	case PGMMODE_NESTED:
3454	rc2 = PGM_BTH_NAME_NESTED_PAE(Enter)(pVM, GCPhysCR3);
3455	break;
3456	case PGMMODE_EPT:
3457	rc2 = PGM_BTH_NAME_EPT_PAE(Enter)(pVM, GCPhysCR3);
3458	break;
3459	case PGMMODE_32_BIT:
3460	case PGMMODE_AMD64:
3461	case PGMMODE_AMD64_NX:
3462	AssertMsgFailed(("Should use PAE shadow mode!\n"));
3463	default: AssertFailed(); break;
3464	}
3465	break;
3466	}
3467
3468	#ifdef VBOX_WITH_64_BITS_GUESTS
3469	case PGMMODE_AMD64_NX:
3470	case PGMMODE_AMD64:
3471	GCPhysCR3 = CPUMGetGuestCR3(pVM) & 0xfffffffffffff000ULL; /** @todo define this mask! */
3472	rc = PGM_GST_NAME_AMD64(Enter)(pVM, GCPhysCR3);
3473	switch (pVM->pgm.s.enmShadowMode)
3474	{
3475	case PGMMODE_AMD64:
3476	case PGMMODE_AMD64_NX:
3477	rc2 = PGM_BTH_NAME_AMD64_AMD64(Enter)(pVM, GCPhysCR3);
3478	break;
3479	case PGMMODE_NESTED:
3480	rc2 = PGM_BTH_NAME_NESTED_AMD64(Enter)(pVM, GCPhysCR3);
3481	break;
3482	case PGMMODE_EPT:
3483	rc2 = PGM_BTH_NAME_EPT_AMD64(Enter)(pVM, GCPhysCR3);
3484	break;
3485	case PGMMODE_32_BIT:
3486	case PGMMODE_PAE:
3487	case PGMMODE_PAE_NX:
3488	AssertMsgFailed(("Should use AMD64 shadow mode!\n"));
3489	default: AssertFailed(); break;
3490	}
3491	break;
3492	#endif
3493
3494	default:
3495	AssertReleaseMsgFailed(("enmGuestMode=%d\n", enmGuestMode));
3496	rc = VERR_NOT_IMPLEMENTED;
3497	break;
3498	}
3499
3500	/* status codes. */
3501	AssertRC(rc);
3502	AssertRC(rc2);
3503	if (RT_SUCCESS(rc))
3504	{
3505	rc = rc2;
3506	if (RT_SUCCESS(rc)) /* no informational status codes. */
3507	rc = VINF_SUCCESS;
3508	}
3509
3510	/*
3511	* Notify SELM so it can update the TSSes with correct CR3s.
3512	*/
3513	SELMR3PagingModeChanged(pVM);
3514
3515	/* Notify HWACCM as well. */
3516	HWACCMR3PagingModeChanged(pVM, pVM->pgm.s.enmShadowMode, pVM->pgm.s.enmGuestMode);
3517	return rc;
3518	}
3519
3520
3521	/**
3522	* Dumps a PAE shadow page table.
3523	*
3524	* @returns VBox status code (VINF_SUCCESS).
3525	* @param pVM The VM handle.
3526	* @param pPT Pointer to the page table.
3527	* @param u64Address The virtual address of the page table starts.
3528	* @param fLongMode Set if this a long mode table; clear if it's a legacy mode table.
3529	* @param cMaxDepth The maxium depth.
3530	* @param pHlp Pointer to the output functions.
3531	*/
3532	static int pgmR3DumpHierarchyHCPaePT(PVM pVM, PX86PTPAE pPT, uint64_t u64Address, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
3533	{
3534	for (unsigned i = 0; i < RT_ELEMENTS(pPT->a); i++)
3535	{
3536	X86PTEPAE Pte = pPT->a[i];
3537	if (Pte.n.u1Present)
3538	{
3539	pHlp->pfnPrintf(pHlp,
3540	fLongMode /P R S A D G WT CD AT NX 4M a p ? /
3541	? "%016llx 3 \| P %c %c %c %c %c %s %s %s %s 4K %c%c%c %016llx\n"
3542	: "%08llx 2 \| P %c %c %c %c %c %s %s %s %s 4K %c%c%c %016llx\n",
3543	u64Address + ((uint64_t)i << X86_PT_PAE_SHIFT),
3544	Pte.n.u1Write ? 'W' : 'R',
3545	Pte.n.u1User ? 'U' : 'S',
3546	Pte.n.u1Accessed ? 'A' : '-',
3547	Pte.n.u1Dirty ? 'D' : '-',
3548	Pte.n.u1Global ? 'G' : '-',
3549	Pte.n.u1WriteThru ? "WT" : "--",
3550	Pte.n.u1CacheDisable? "CD" : "--",
3551	Pte.n.u1PAT ? "AT" : "--",
3552	Pte.n.u1NoExecute ? "NX" : "--",
3553	Pte.u & PGM_PTFLAGS_TRACK_DIRTY ? 'd' : '-',
3554	Pte.u & RT_BIT(10) ? '1' : '0',
3555	Pte.u & PGM_PTFLAGS_CSAM_VALIDATED? 'v' : '-',
3556	Pte.u & X86_PTE_PAE_PG_MASK);
3557	}
3558	}
3559	return VINF_SUCCESS;
3560	}
3561
3562
3563	/**
3564	* Dumps a PAE shadow page directory table.
3565	*
3566	* @returns VBox status code (VINF_SUCCESS).
3567	* @param pVM The VM handle.
3568	* @param HCPhys The physical address of the page directory table.
3569	* @param u64Address The virtual address of the page table starts.
3570	* @param cr4 The CR4, PSE is currently used.
3571	* @param fLongMode Set if this a long mode table; clear if it's a legacy mode table.
3572	* @param cMaxDepth The maxium depth.
3573	* @param pHlp Pointer to the output functions.
3574	*/
3575	static int pgmR3DumpHierarchyHCPaePD(PVM pVM, RTHCPHYS HCPhys, uint64_t u64Address, uint32_t cr4, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
3576	{
3577	PX86PDPAE pPD = (PX86PDPAE)MMPagePhys2Page(pVM, HCPhys);
3578	if (!pPD)
3579	{
3580	pHlp->pfnPrintf(pHlp, "%0*llx error! Page directory at HCPhys=%RHp was not found in the page pool!\n",
3581	fLongMode ? 16 : 8, u64Address, HCPhys);
3582	return VERR_INVALID_PARAMETER;
3583	}
3584	const bool fBigPagesSupported = fLongMode \|\| !!(cr4 & X86_CR4_PSE);
3585
3586	int rc = VINF_SUCCESS;
3587	for (unsigned i = 0; i < RT_ELEMENTS(pPD->a); i++)
3588	{
3589	X86PDEPAE Pde = pPD->a[i];
3590	if (Pde.n.u1Present)
3591	{
3592	if (fBigPagesSupported && Pde.b.u1Size)
3593	pHlp->pfnPrintf(pHlp,
3594	fLongMode /P R S A D G WT CD AT NX 4M a p ? /
3595	? "%016llx 2 \| P %c %c %c %c %c %s %s %s %s 4M %c%c%c %016llx\n"
3596	: "%08llx 1 \| P %c %c %c %c %c %s %s %s %s 4M %c%c%c %016llx\n",
3597	u64Address + ((uint64_t)i << X86_PD_PAE_SHIFT),
3598	Pde.b.u1Write ? 'W' : 'R',
3599	Pde.b.u1User ? 'U' : 'S',
3600	Pde.b.u1Accessed ? 'A' : '-',
3601	Pde.b.u1Dirty ? 'D' : '-',
3602	Pde.b.u1Global ? 'G' : '-',
3603	Pde.b.u1WriteThru ? "WT" : "--",
3604	Pde.b.u1CacheDisable? "CD" : "--",
3605	Pde.b.u1PAT ? "AT" : "--",
3606	Pde.b.u1NoExecute ? "NX" : "--",
3607	Pde.u & RT_BIT_64(9) ? '1' : '0',
3608	Pde.u & PGM_PDFLAGS_MAPPING ? 'm' : '-',
3609	Pde.u & PGM_PDFLAGS_TRACK_DIRTY ? 'd' : '-',
3610	Pde.u & X86_PDE_PAE_PG_MASK);
3611	else
3612	{
3613	pHlp->pfnPrintf(pHlp,
3614	fLongMode /P R S A D G WT CD AT NX 4M a p ? /
3615	? "%016llx 2 \| P %c %c %c %c %c %s %s .. %s 4K %c%c%c %016llx\n"
3616	: "%08llx 1 \| P %c %c %c %c %c %s %s .. %s 4K %c%c%c %016llx\n",
3617	u64Address + ((uint64_t)i << X86_PD_PAE_SHIFT),
3618	Pde.n.u1Write ? 'W' : 'R',
3619	Pde.n.u1User ? 'U' : 'S',
3620	Pde.n.u1Accessed ? 'A' : '-',
3621	Pde.n.u1Reserved0 ? '?' : '.', /* ignored */
3622	Pde.n.u1Reserved1 ? '?' : '.', /* ignored */
3623	Pde.n.u1WriteThru ? "WT" : "--",
3624	Pde.n.u1CacheDisable? "CD" : "--",
3625	Pde.n.u1NoExecute ? "NX" : "--",
3626	Pde.u & RT_BIT_64(9) ? '1' : '0',
3627	Pde.u & PGM_PDFLAGS_MAPPING ? 'm' : '-',
3628	Pde.u & PGM_PDFLAGS_TRACK_DIRTY ? 'd' : '-',
3629	Pde.u & X86_PDE_PAE_PG_MASK);
3630	if (cMaxDepth >= 1)
3631	{
3632	/** @todo what about using the page pool for mapping PTs? */
3633	uint64_t u64AddressPT = u64Address + ((uint64_t)i << X86_PD_PAE_SHIFT);
3634	RTHCPHYS HCPhysPT = Pde.u & X86_PDE_PAE_PG_MASK;
3635	PX86PTPAE pPT = NULL;
3636	if (!(Pde.u & PGM_PDFLAGS_MAPPING))
3637	pPT = (PX86PTPAE)MMPagePhys2Page(pVM, HCPhysPT);
3638	else
3639	{
3640	for (PPGMMAPPING pMap = pVM->pgm.s.pMappingsR3; pMap; pMap = pMap->pNextR3)
3641	{
3642	uint64_t off = u64AddressPT - pMap->GCPtr;
3643	if (off < pMap->cb)
3644	{
3645	const int iPDE = (uint32_t)(off >> X86_PD_SHIFT);
3646	const int iSub = (int)((off >> X86_PD_PAE_SHIFT) & 1); /* MSC is a pain sometimes */
3647	if ((iSub ? pMap->aPTs[iPDE].HCPhysPaePT1 : pMap->aPTs[iPDE].HCPhysPaePT0) != HCPhysPT)
3648	pHlp->pfnPrintf(pHlp, "%0*llx error! Mapping error! PT %d has HCPhysPT=%RHp not %RHp is in the PD.\n",
3649	fLongMode ? 16 : 8, u64AddressPT, iPDE,
3650	iSub ? pMap->aPTs[iPDE].HCPhysPaePT1 : pMap->aPTs[iPDE].HCPhysPaePT0, HCPhysPT);
3651	pPT = &pMap->aPTs[iPDE].paPaePTsR3[iSub];
3652	}
3653	}
3654	}
3655	int rc2 = VERR_INVALID_PARAMETER;
3656	if (pPT)
3657	rc2 = pgmR3DumpHierarchyHCPaePT(pVM, pPT, u64AddressPT, fLongMode, cMaxDepth - 1, pHlp);
3658	else
3659	pHlp->pfnPrintf(pHlp, "%0*llx error! Page table at HCPhys=%RHp was not found in the page pool!\n",
3660	fLongMode ? 16 : 8, u64AddressPT, HCPhysPT);
3661	if (rc2 < rc && RT_SUCCESS(rc))
3662	rc = rc2;
3663	}
3664	}
3665	}
3666	}
3667	return rc;
3668	}
3669
3670
3671	/**
3672	* Dumps a PAE shadow page directory pointer table.
3673	*
3674	* @returns VBox status code (VINF_SUCCESS).
3675	* @param pVM The VM handle.
3676	* @param HCPhys The physical address of the page directory pointer table.
3677	* @param u64Address The virtual address of the page table starts.
3678	* @param cr4 The CR4, PSE is currently used.
3679	* @param fLongMode Set if this a long mode table; clear if it's a legacy mode table.
3680	* @param cMaxDepth The maxium depth.
3681	* @param pHlp Pointer to the output functions.
3682	*/
3683	static int pgmR3DumpHierarchyHCPaePDPT(PVM pVM, RTHCPHYS HCPhys, uint64_t u64Address, uint32_t cr4, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
3684	{
3685	PX86PDPT pPDPT = (PX86PDPT)MMPagePhys2Page(pVM, HCPhys);
3686	if (!pPDPT)
3687	{
3688	pHlp->pfnPrintf(pHlp, "%0*llx error! Page directory pointer table at HCPhys=%RHp was not found in the page pool!\n",
3689	fLongMode ? 16 : 8, u64Address, HCPhys);
3690	return VERR_INVALID_PARAMETER;
3691	}
3692
3693	int rc = VINF_SUCCESS;
3694	const unsigned c = fLongMode ? RT_ELEMENTS(pPDPT->a) : X86_PG_PAE_PDPE_ENTRIES;
3695	for (unsigned i = 0; i < c; i++)
3696	{
3697	X86PDPE Pdpe = pPDPT->a[i];
3698	if (Pdpe.n.u1Present)
3699	{
3700	if (fLongMode)
3701	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a p ? /
3702	"%016llx 1 \| P %c %c %c %c %c %s %s %s %s .. %c%c%c %016llx\n",
3703	u64Address + ((uint64_t)i << X86_PDPT_SHIFT),
3704	Pdpe.lm.u1Write ? 'W' : 'R',
3705	Pdpe.lm.u1User ? 'U' : 'S',
3706	Pdpe.lm.u1Accessed ? 'A' : '-',
3707	Pdpe.lm.u3Reserved & 1? '?' : '.', /* ignored */
3708	Pdpe.lm.u3Reserved & 4? '!' : '.', /* mbz */
3709	Pdpe.lm.u1WriteThru ? "WT" : "--",
3710	Pdpe.lm.u1CacheDisable? "CD" : "--",
3711	Pdpe.lm.u3Reserved & 2? "!" : "..",/* mbz */
3712	Pdpe.lm.u1NoExecute ? "NX" : "--",
3713	Pdpe.u & RT_BIT(9) ? '1' : '0',
3714	Pdpe.u & PGM_PLXFLAGS_PERMANENT ? 'p' : '-',
3715	Pdpe.u & RT_BIT(11) ? '1' : '0',
3716	Pdpe.u & X86_PDPE_PG_MASK);
3717	else
3718	pHlp->pfnPrintf(pHlp, /P G WT CD AT NX 4M a p ? /
3719	"%08x 0 \| P %c %s %s %s %s .. %c%c%c %016llx\n",
3720	i << X86_PDPT_SHIFT,
3721	Pdpe.n.u4Reserved & 1? '!' : '.', /* mbz */
3722	Pdpe.n.u4Reserved & 4? '!' : '.', /* mbz */
3723	Pdpe.n.u1WriteThru ? "WT" : "--",
3724	Pdpe.n.u1CacheDisable? "CD" : "--",
3725	Pdpe.n.u4Reserved & 2? "!" : "..",/* mbz */
3726	Pdpe.u & RT_BIT(9) ? '1' : '0',
3727	Pdpe.u & PGM_PLXFLAGS_PERMANENT ? 'p' : '-',
3728	Pdpe.u & RT_BIT(11) ? '1' : '0',
3729	Pdpe.u & X86_PDPE_PG_MASK);
3730	if (cMaxDepth >= 1)
3731	{
3732	int rc2 = pgmR3DumpHierarchyHCPaePD(pVM, Pdpe.u & X86_PDPE_PG_MASK, u64Address + ((uint64_t)i << X86_PDPT_SHIFT),
3733	cr4, fLongMode, cMaxDepth - 1, pHlp);
3734	if (rc2 < rc && RT_SUCCESS(rc))
3735	rc = rc2;
3736	}
3737	}
3738	}
3739	return rc;
3740	}
3741
3742
3743	/**
3744	* Dumps a 32-bit shadow page table.
3745	*
3746	* @returns VBox status code (VINF_SUCCESS).
3747	* @param pVM The VM handle.
3748	* @param HCPhys The physical address of the table.
3749	* @param cr4 The CR4, PSE is currently used.
3750	* @param cMaxDepth The maxium depth.
3751	* @param pHlp Pointer to the output functions.
3752	*/
3753	static int pgmR3DumpHierarchyHcPaePML4(PVM pVM, RTHCPHYS HCPhys, uint32_t cr4, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
3754	{
3755	PX86PML4 pPML4 = (PX86PML4)MMPagePhys2Page(pVM, HCPhys);
3756	if (!pPML4)
3757	{
3758	pHlp->pfnPrintf(pHlp, "Page map level 4 at HCPhys=%RHp was not found in the page pool!\n", HCPhys);
3759	return VERR_INVALID_PARAMETER;
3760	}
3761
3762	int rc = VINF_SUCCESS;
3763	for (unsigned i = 0; i < RT_ELEMENTS(pPML4->a); i++)
3764	{
3765	X86PML4E Pml4e = pPML4->a[i];
3766	if (Pml4e.n.u1Present)
3767	{
3768	uint64_t u64Address = ((uint64_t)i << X86_PML4_SHIFT) \| (((uint64_t)i >> (X86_PML4_SHIFT - X86_PDPT_SHIFT - 1)) * 0xffff000000000000ULL);
3769	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a p ? /
3770	"%016llx 0 \| P %c %c %c %c %c %s %s %s %s .. %c%c%c %016llx\n",
3771	u64Address,
3772	Pml4e.n.u1Write ? 'W' : 'R',
3773	Pml4e.n.u1User ? 'U' : 'S',
3774	Pml4e.n.u1Accessed ? 'A' : '-',
3775	Pml4e.n.u3Reserved & 1? '?' : '.', /* ignored */
3776	Pml4e.n.u3Reserved & 4? '!' : '.', /* mbz */
3777	Pml4e.n.u1WriteThru ? "WT" : "--",
3778	Pml4e.n.u1CacheDisable? "CD" : "--",
3779	Pml4e.n.u3Reserved & 2? "!" : "..",/* mbz */
3780	Pml4e.n.u1NoExecute ? "NX" : "--",
3781	Pml4e.u & RT_BIT(9) ? '1' : '0',
3782	Pml4e.u & PGM_PLXFLAGS_PERMANENT ? 'p' : '-',
3783	Pml4e.u & RT_BIT(11) ? '1' : '0',
3784	Pml4e.u & X86_PML4E_PG_MASK);
3785
3786	if (cMaxDepth >= 1)
3787	{
3788	int rc2 = pgmR3DumpHierarchyHCPaePDPT(pVM, Pml4e.u & X86_PML4E_PG_MASK, u64Address, cr4, true, cMaxDepth - 1, pHlp);
3789	if (rc2 < rc && RT_SUCCESS(rc))
3790	rc = rc2;
3791	}
3792	}
3793	}
3794	return rc;
3795	}
3796
3797
3798	/**
3799	* Dumps a 32-bit shadow page table.
3800	*
3801	* @returns VBox status code (VINF_SUCCESS).
3802	* @param pVM The VM handle.
3803	* @param pPT Pointer to the page table.
3804	* @param u32Address The virtual address this table starts at.
3805	* @param pHlp Pointer to the output functions.
3806	*/
3807	int pgmR3DumpHierarchyHC32BitPT(PVM pVM, PX86PT pPT, uint32_t u32Address, PCDBGFINFOHLP pHlp)
3808	{
3809	for (unsigned i = 0; i < RT_ELEMENTS(pPT->a); i++)
3810	{
3811	X86PTE Pte = pPT->a[i];
3812	if (Pte.n.u1Present)
3813	{
3814	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a m d /
3815	"%08x 1 \| P %c %c %c %c %c %s %s %s .. 4K %c%c%c %08x\n",
3816	u32Address + (i << X86_PT_SHIFT),
3817	Pte.n.u1Write ? 'W' : 'R',
3818	Pte.n.u1User ? 'U' : 'S',
3819	Pte.n.u1Accessed ? 'A' : '-',
3820	Pte.n.u1Dirty ? 'D' : '-',
3821	Pte.n.u1Global ? 'G' : '-',
3822	Pte.n.u1WriteThru ? "WT" : "--",
3823	Pte.n.u1CacheDisable? "CD" : "--",
3824	Pte.n.u1PAT ? "AT" : "--",
3825	Pte.u & PGM_PTFLAGS_TRACK_DIRTY ? 'd' : '-',
3826	Pte.u & RT_BIT(10) ? '1' : '0',
3827	Pte.u & PGM_PTFLAGS_CSAM_VALIDATED ? 'v' : '-',
3828	Pte.u & X86_PDE_PG_MASK);
3829	}
3830	}
3831	return VINF_SUCCESS;
3832	}
3833
3834
3835	/**
3836	* Dumps a 32-bit shadow page directory and page tables.
3837	*
3838	* @returns VBox status code (VINF_SUCCESS).
3839	* @param pVM The VM handle.
3840	* @param cr3 The root of the hierarchy.
3841	* @param cr4 The CR4, PSE is currently used.
3842	* @param cMaxDepth How deep into the hierarchy the dumper should go.
3843	* @param pHlp Pointer to the output functions.
3844	*/
3845	int pgmR3DumpHierarchyHC32BitPD(PVM pVM, uint32_t cr3, uint32_t cr4, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
3846	{
3847	PX86PD pPD = (PX86PD)MMPagePhys2Page(pVM, cr3 & X86_CR3_PAGE_MASK);
3848	if (!pPD)
3849	{
3850	pHlp->pfnPrintf(pHlp, "Page directory at %#x was not found in the page pool!\n", cr3 & X86_CR3_PAGE_MASK);
3851	return VERR_INVALID_PARAMETER;
3852	}
3853
3854	int rc = VINF_SUCCESS;
3855	for (unsigned i = 0; i < RT_ELEMENTS(pPD->a); i++)
3856	{
3857	X86PDE Pde = pPD->a[i];
3858	if (Pde.n.u1Present)
3859	{
3860	const uint32_t u32Address = i << X86_PD_SHIFT;
3861	if ((cr4 & X86_CR4_PSE) && Pde.b.u1Size)
3862	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a m d /
3863	"%08x 0 \| P %c %c %c %c %c %s %s %s .. 4M %c%c%c %08x\n",
3864	u32Address,
3865	Pde.b.u1Write ? 'W' : 'R',
3866	Pde.b.u1User ? 'U' : 'S',
3867	Pde.b.u1Accessed ? 'A' : '-',
3868	Pde.b.u1Dirty ? 'D' : '-',
3869	Pde.b.u1Global ? 'G' : '-',
3870	Pde.b.u1WriteThru ? "WT" : "--",
3871	Pde.b.u1CacheDisable? "CD" : "--",
3872	Pde.b.u1PAT ? "AT" : "--",
3873	Pde.u & RT_BIT_64(9) ? '1' : '0',
3874	Pde.u & PGM_PDFLAGS_MAPPING ? 'm' : '-',
3875	Pde.u & PGM_PDFLAGS_TRACK_DIRTY ? 'd' : '-',
3876	Pde.u & X86_PDE4M_PG_MASK);
3877	else
3878	{
3879	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a m d /
3880	"%08x 0 \| P %c %c %c %c %c %s %s .. .. 4K %c%c%c %08x\n",
3881	u32Address,
3882	Pde.n.u1Write ? 'W' : 'R',
3883	Pde.n.u1User ? 'U' : 'S',
3884	Pde.n.u1Accessed ? 'A' : '-',
3885	Pde.n.u1Reserved0 ? '?' : '.', /* ignored */
3886	Pde.n.u1Reserved1 ? '?' : '.', /* ignored */
3887	Pde.n.u1WriteThru ? "WT" : "--",
3888	Pde.n.u1CacheDisable? "CD" : "--",
3889	Pde.u & RT_BIT_64(9) ? '1' : '0',
3890	Pde.u & PGM_PDFLAGS_MAPPING ? 'm' : '-',
3891	Pde.u & PGM_PDFLAGS_TRACK_DIRTY ? 'd' : '-',
3892	Pde.u & X86_PDE_PG_MASK);
3893	if (cMaxDepth >= 1)
3894	{
3895	/** @todo what about using the page pool for mapping PTs? */
3896	RTHCPHYS HCPhys = Pde.u & X86_PDE_PG_MASK;
3897	PX86PT pPT = NULL;
3898	if (!(Pde.u & PGM_PDFLAGS_MAPPING))
3899	pPT = (PX86PT)MMPagePhys2Page(pVM, HCPhys);
3900	else
3901	{
3902	for (PPGMMAPPING pMap = pVM->pgm.s.pMappingsR3; pMap; pMap = pMap->pNextR3)
3903	if (u32Address - pMap->GCPtr < pMap->cb)
3904	{
3905	int iPDE = (u32Address - pMap->GCPtr) >> X86_PD_SHIFT;
3906	if (pMap->aPTs[iPDE].HCPhysPT != HCPhys)
3907	pHlp->pfnPrintf(pHlp, "%08x error! Mapping error! PT %d has HCPhysPT=%RHp not %RHp is in the PD.\n",
3908	u32Address, iPDE, pMap->aPTs[iPDE].HCPhysPT, HCPhys);
3909	pPT = pMap->aPTs[iPDE].pPTR3;
3910	}
3911	}
3912	int rc2 = VERR_INVALID_PARAMETER;
3913	if (pPT)
3914	rc2 = pgmR3DumpHierarchyHC32BitPT(pVM, pPT, u32Address, pHlp);
3915	else
3916	pHlp->pfnPrintf(pHlp, "%08x error! Page table at %#x was not found in the page pool!\n", u32Address, HCPhys);
3917	if (rc2 < rc && RT_SUCCESS(rc))
3918	rc = rc2;
3919	}
3920	}
3921	}
3922	}
3923
3924	return rc;
3925	}
3926
3927
3928	/**
3929	* Dumps a 32-bit shadow page table.
3930	*
3931	* @returns VBox status code (VINF_SUCCESS).
3932	* @param pVM The VM handle.
3933	* @param pPT Pointer to the page table.
3934	* @param u32Address The virtual address this table starts at.
3935	* @param PhysSearch Address to search for.
3936	*/
3937	int pgmR3DumpHierarchyGC32BitPT(PVM pVM, PX86PT pPT, uint32_t u32Address, RTGCPHYS PhysSearch)
3938	{
3939	for (unsigned i = 0; i < RT_ELEMENTS(pPT->a); i++)
3940	{
3941	X86PTE Pte = pPT->a[i];
3942	if (Pte.n.u1Present)
3943	{
3944	Log(( /P R S A D G WT CD AT NX 4M a m d /
3945	"%08x 1 \| P %c %c %c %c %c %s %s %s .. 4K %c%c%c %08x\n",
3946	u32Address + (i << X86_PT_SHIFT),
3947	Pte.n.u1Write ? 'W' : 'R',
3948	Pte.n.u1User ? 'U' : 'S',
3949	Pte.n.u1Accessed ? 'A' : '-',
3950	Pte.n.u1Dirty ? 'D' : '-',
3951	Pte.n.u1Global ? 'G' : '-',
3952	Pte.n.u1WriteThru ? "WT" : "--",
3953	Pte.n.u1CacheDisable? "CD" : "--",
3954	Pte.n.u1PAT ? "AT" : "--",
3955	Pte.u & PGM_PTFLAGS_TRACK_DIRTY ? 'd' : '-',
3956	Pte.u & RT_BIT(10) ? '1' : '0',
3957	Pte.u & PGM_PTFLAGS_CSAM_VALIDATED ? 'v' : '-',
3958	Pte.u & X86_PDE_PG_MASK));
3959
3960	if ((Pte.u & X86_PDE_PG_MASK) == PhysSearch)
3961	{
3962	uint64_t fPageShw = 0;
3963	RTHCPHYS pPhysHC = 0;
3964
3965	PGMShwGetPage(pVM, (RTGCPTR)(u32Address + (i << X86_PT_SHIFT)), &fPageShw, &pPhysHC);
3966	Log(("Found %RGp at %RGv -> flags=%llx\n", PhysSearch, (RTGCPTR)(u32Address + (i << X86_PT_SHIFT)), fPageShw));
3967	}
3968	}
3969	}
3970	return VINF_SUCCESS;
3971	}
3972
3973
3974	/**
3975	* Dumps a 32-bit guest page directory and page tables.
3976	*
3977	* @returns VBox status code (VINF_SUCCESS).
3978	* @param pVM The VM handle.
3979	* @param cr3 The root of the hierarchy.
3980	* @param cr4 The CR4, PSE is currently used.
3981	* @param PhysSearch Address to search for.
3982	*/
3983	VMMR3DECL(int) PGMR3DumpHierarchyGC(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCPHYS PhysSearch)
3984	{
3985	bool fLongMode = false;
3986	const unsigned cch = fLongMode ? 16 : 8; NOREF(cch);
3987	PX86PD pPD = 0;
3988
3989	int rc = PGM_GCPHYS_2_PTR(pVM, cr3 & X86_CR3_PAGE_MASK, &pPD);
3990	if (RT_FAILURE(rc) \|\| !pPD)
3991	{
3992	Log(("Page directory at %#x was not found in the page pool!\n", cr3 & X86_CR3_PAGE_MASK));
3993	return VERR_INVALID_PARAMETER;
3994	}
3995
3996	Log(("cr3=%08x cr4=%08x%s\n"
3997	"%-*s P - Present\n"
3998	"%-*s \| R/W - Read (0) / Write (1)\n"
3999	"%-*s \| \| U/S - User (1) / Supervisor (0)\n"
4000	"%-*s \| \| \| A - Accessed\n"
4001	"%-*s \| \| \| \| D - Dirty\n"
4002	"%-*s \| \| \| \| \| G - Global\n"
4003	"%-*s \| \| \| \| \| \| WT - Write thru\n"
4004	"%-*s \| \| \| \| \| \| \| CD - Cache disable\n"
4005	"%-*s \| \| \| \| \| \| \| \| AT - Attribute table (PAT)\n"
4006	"%-*s \| \| \| \| \| \| \| \| \| NX - No execute (K8)\n"
4007	"%-*s \| \| \| \| \| \| \| \| \| \| 4K/4M/2M - Page size.\n"
4008	"%-*s \| \| \| \| \| \| \| \| \| \| \| AVL - a=allocated; m=mapping; d=track dirty;\n"
4009	"%-*s \| \| \| \| \| \| \| \| \| \| \| \| p=permanent; v=validated;\n"
4010	"%-*s Level \| \| \| \| \| \| \| \| \| \| \| \| Page\n"
4011	/* xxxx n **** P R S A D G WT CD AT NX 4M AVL xxxxxxxxxxxxx
4012	- W U - - - -- -- -- -- -- 010 */
4013	, cr3, cr4, fLongMode ? " Long Mode" : "",
4014	cch, "", cch, "", cch, "", cch, "", cch, "", cch, "", cch, "",
4015	cch, "", cch, "", cch, "", cch, "", cch, "", cch, "", cch, "Address"));
4016
4017	for (unsigned i = 0; i < RT_ELEMENTS(pPD->a); i++)
4018	{
4019	X86PDE Pde = pPD->a[i];
4020	if (Pde.n.u1Present)
4021	{
4022	const uint32_t u32Address = i << X86_PD_SHIFT;
4023
4024	if ((cr4 & X86_CR4_PSE) && Pde.b.u1Size)
4025	Log(( /P R S A D G WT CD AT NX 4M a m d /
4026	"%08x 0 \| P %c %c %c %c %c %s %s %s .. 4M %c%c%c %08x\n",
4027	u32Address,
4028	Pde.b.u1Write ? 'W' : 'R',
4029	Pde.b.u1User ? 'U' : 'S',
4030	Pde.b.u1Accessed ? 'A' : '-',
4031	Pde.b.u1Dirty ? 'D' : '-',
4032	Pde.b.u1Global ? 'G' : '-',
4033	Pde.b.u1WriteThru ? "WT" : "--",
4034	Pde.b.u1CacheDisable? "CD" : "--",
4035	Pde.b.u1PAT ? "AT" : "--",
4036	Pde.u & RT_BIT(9) ? '1' : '0',
4037	Pde.u & RT_BIT(10) ? '1' : '0',
4038	Pde.u & RT_BIT(11) ? '1' : '0',
4039	pgmGstGet4MBPhysPage(&pVM->pgm.s, Pde)));
4040	/** @todo PhysSearch */
4041	else
4042	{
4043	Log(( /P R S A D G WT CD AT NX 4M a m d /
4044	"%08x 0 \| P %c %c %c %c %c %s %s .. .. 4K %c%c%c %08x\n",
4045	u32Address,
4046	Pde.n.u1Write ? 'W' : 'R',
4047	Pde.n.u1User ? 'U' : 'S',
4048	Pde.n.u1Accessed ? 'A' : '-',
4049	Pde.n.u1Reserved0 ? '?' : '.', /* ignored */
4050	Pde.n.u1Reserved1 ? '?' : '.', /* ignored */
4051	Pde.n.u1WriteThru ? "WT" : "--",
4052	Pde.n.u1CacheDisable? "CD" : "--",
4053	Pde.u & RT_BIT(9) ? '1' : '0',
4054	Pde.u & RT_BIT(10) ? '1' : '0',
4055	Pde.u & RT_BIT(11) ? '1' : '0',
4056	Pde.u & X86_PDE_PG_MASK));
4057	////if (cMaxDepth >= 1)
4058	{
4059	/** @todo what about using the page pool for mapping PTs? */
4060	RTGCPHYS GCPhys = Pde.u & X86_PDE_PG_MASK;
4061	PX86PT pPT = NULL;
4062
4063	rc = PGM_GCPHYS_2_PTR(pVM, GCPhys, &pPT);
4064
4065	int rc2 = VERR_INVALID_PARAMETER;
4066	if (pPT)
4067	rc2 = pgmR3DumpHierarchyGC32BitPT(pVM, pPT, u32Address, PhysSearch);
4068	else
4069	Log(("%08x error! Page table at %#x was not found in the page pool!\n", u32Address, GCPhys));
4070	if (rc2 < rc && RT_SUCCESS(rc))
4071	rc = rc2;
4072	}
4073	}
4074	}
4075	}
4076
4077	return rc;
4078	}
4079
4080
4081	/**
4082	* Dumps a page table hierarchy use only physical addresses and cr4/lm flags.
4083	*
4084	* @returns VBox status code (VINF_SUCCESS).
4085	* @param pVM The VM handle.
4086	* @param cr3 The root of the hierarchy.
4087	* @param cr4 The cr4, only PAE and PSE is currently used.
4088	* @param fLongMode Set if long mode, false if not long mode.
4089	* @param cMaxDepth Number of levels to dump.
4090	* @param pHlp Pointer to the output functions.
4091	*/
4092	VMMR3DECL(int) PGMR3DumpHierarchyHC(PVM pVM, uint64_t cr3, uint64_t cr4, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
4093	{
4094	if (!pHlp)
4095	pHlp = DBGFR3InfoLogHlp();
4096	if (!cMaxDepth)
4097	return VINF_SUCCESS;
4098	const unsigned cch = fLongMode ? 16 : 8;
4099	pHlp->pfnPrintf(pHlp,
4100	"cr3=%08x cr4=%08x%s\n"
4101	"%-*s P - Present\n"
4102	"%-*s \| R/W - Read (0) / Write (1)\n"
4103	"%-*s \| \| U/S - User (1) / Supervisor (0)\n"
4104	"%-*s \| \| \| A - Accessed\n"
4105	"%-*s \| \| \| \| D - Dirty\n"
4106	"%-*s \| \| \| \| \| G - Global\n"
4107	"%-*s \| \| \| \| \| \| WT - Write thru\n"
4108	"%-*s \| \| \| \| \| \| \| CD - Cache disable\n"
4109	"%-*s \| \| \| \| \| \| \| \| AT - Attribute table (PAT)\n"
4110	"%-*s \| \| \| \| \| \| \| \| \| NX - No execute (K8)\n"
4111	"%-*s \| \| \| \| \| \| \| \| \| \| 4K/4M/2M - Page size.\n"
4112	"%-*s \| \| \| \| \| \| \| \| \| \| \| AVL - a=allocated; m=mapping; d=track dirty;\n"
4113	"%-*s \| \| \| \| \| \| \| \| \| \| \| \| p=permanent; v=validated;\n"
4114	"%-*s Level \| \| \| \| \| \| \| \| \| \| \| \| Page\n"
4115	/* xxxx n **** P R S A D G WT CD AT NX 4M AVL xxxxxxxxxxxxx
4116	- W U - - - -- -- -- -- -- 010 */
4117	, cr3, cr4, fLongMode ? " Long Mode" : "",
4118	cch, "", cch, "", cch, "", cch, "", cch, "", cch, "", cch, "",
4119	cch, "", cch, "", cch, "", cch, "", cch, "", cch, "", cch, "Address");
4120	if (cr4 & X86_CR4_PAE)
4121	{
4122	if (fLongMode)
4123	return pgmR3DumpHierarchyHcPaePML4(pVM, cr3 & X86_CR3_PAGE_MASK, cr4, cMaxDepth, pHlp);
4124	return pgmR3DumpHierarchyHCPaePDPT(pVM, cr3 & X86_CR3_PAE_PAGE_MASK, 0, cr4, false, cMaxDepth, pHlp);
4125	}
4126	return pgmR3DumpHierarchyHC32BitPD(pVM, cr3 & X86_CR3_PAGE_MASK, cr4, cMaxDepth, pHlp);
4127	}
4128
4129	#ifdef VBOX_WITH_DEBUGGER
4130
4131	/**
4132	* The '.pgmram' command.
4133	*
4134	* @returns VBox status.
4135	* @param pCmd Pointer to the command descriptor (as registered).
4136	* @param pCmdHlp Pointer to command helper functions.
4137	* @param pVM Pointer to the current VM (if any).
4138	* @param paArgs Pointer to (readonly) array of arguments.
4139	* @param cArgs Number of arguments in the array.
4140	*/
4141	static DECLCALLBACK(int) pgmR3CmdRam(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4142	{
4143	/*
4144	* Validate input.
4145	*/
4146	if (!pVM)
4147	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4148	if (!pVM->pgm.s.pRamRangesRC)
4149	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Sorry, no Ram is registered.\n");
4150
4151	/*
4152	* Dump the ranges.
4153	*/
4154	int rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL, "From - To (incl) pvHC\n");
4155	PPGMRAMRANGE pRam;
4156	for (pRam = pVM->pgm.s.pRamRangesR3; pRam; pRam = pRam->pNextR3)
4157	{
4158	rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL,
4159	"%RGp - %RGp %p\n",
4160	pRam->GCPhys, pRam->GCPhysLast, pRam->pvR3);
4161	if (RT_FAILURE(rc))
4162	return rc;
4163	}
4164
4165	return VINF_SUCCESS;
4166	}
4167
4168
4169	/**
4170	* The '.pgmmap' command.
4171	*
4172	* @returns VBox status.
4173	* @param pCmd Pointer to the command descriptor (as registered).
4174	* @param pCmdHlp Pointer to command helper functions.
4175	* @param pVM Pointer to the current VM (if any).
4176	* @param paArgs Pointer to (readonly) array of arguments.
4177	* @param cArgs Number of arguments in the array.
4178	*/
4179	static DECLCALLBACK(int) pgmR3CmdMap(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4180	{
4181	/*
4182	* Validate input.
4183	*/
4184	if (!pVM)
4185	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4186	if (!pVM->pgm.s.pMappingsR3)
4187	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Sorry, no mappings are registered.\n");
4188
4189	/*
4190	* Print message about the fixedness of the mappings.
4191	*/
4192	int rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL, pVM->pgm.s.fMappingsFixed ? "The mappings are FIXED.\n" : "The mappings are FLOATING.\n");
4193	if (RT_FAILURE(rc))
4194	return rc;
4195
4196	/*
4197	* Dump the ranges.
4198	*/
4199	PPGMMAPPING pCur;
4200	for (pCur = pVM->pgm.s.pMappingsR3; pCur; pCur = pCur->pNextR3)
4201	{
4202	rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL,
4203	"%08x - %08x %s\n",
4204	pCur->GCPtr, pCur->GCPtrLast, pCur->pszDesc);
4205	if (RT_FAILURE(rc))
4206	return rc;
4207	}
4208
4209	return VINF_SUCCESS;
4210	}
4211
4212
4213	/**
4214	* The '.pgmsync' command.
4215	*
4216	* @returns VBox status.
4217	* @param pCmd Pointer to the command descriptor (as registered).
4218	* @param pCmdHlp Pointer to command helper functions.
4219	* @param pVM Pointer to the current VM (if any).
4220	* @param paArgs Pointer to (readonly) array of arguments.
4221	* @param cArgs Number of arguments in the array.
4222	*/
4223	static DECLCALLBACK(int) pgmR3CmdSync(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4224	{
4225	/*
4226	* Validate input.
4227	*/
4228	if (!pVM)
4229	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4230
4231	/*
4232	* Force page directory sync.
4233	*/
4234	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
4235
4236	int rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Forcing page directory sync.\n");
4237	if (RT_FAILURE(rc))
4238	return rc;
4239
4240	return VINF_SUCCESS;
4241	}
4242
4243
4244	#ifdef VBOX_STRICT
4245	/**
4246	* The '.pgmassertcr3' command.
4247	*
4248	* @returns VBox status.
4249	* @param pCmd Pointer to the command descriptor (as registered).
4250	* @param pCmdHlp Pointer to command helper functions.
4251	* @param pVM Pointer to the current VM (if any).
4252	* @param paArgs Pointer to (readonly) array of arguments.
4253	* @param cArgs Number of arguments in the array.
4254	*/
4255	static DECLCALLBACK(int) pgmR3CmdAssertCR3(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4256	{
4257	/*
4258	* Validate input.
4259	*/
4260	if (!pVM)
4261	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4262
4263	int rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Checking shadow CR3 page tables for consistency.\n");
4264	if (RT_FAILURE(rc))
4265	return rc;
4266
4267	PGMAssertCR3(pVM, CPUMGetGuestCR3(pVM), CPUMGetGuestCR4(pVM));
4268
4269	return VINF_SUCCESS;
4270	}
4271	#endif /* VBOX_STRICT */
4272
4273
4274	/**
4275	* The '.pgmsyncalways' command.
4276	*
4277	* @returns VBox status.
4278	* @param pCmd Pointer to the command descriptor (as registered).
4279	* @param pCmdHlp Pointer to command helper functions.
4280	* @param pVM Pointer to the current VM (if any).
4281	* @param paArgs Pointer to (readonly) array of arguments.
4282	* @param cArgs Number of arguments in the array.
4283	*/
4284	static DECLCALLBACK(int) pgmR3CmdSyncAlways(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4285	{
4286	/*
4287	* Validate input.
4288	*/
4289	if (!pVM)
4290	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4291
4292	/*
4293	* Force page directory sync.
4294	*/
4295	if (pVM->pgm.s.fSyncFlags & PGM_SYNC_ALWAYS)
4296	{
4297	ASMAtomicAndU32(&pVM->pgm.s.fSyncFlags, ~PGM_SYNC_ALWAYS);
4298	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Disabled permanent forced page directory syncing.\n");
4299	}
4300	else
4301	{
4302	ASMAtomicOrU32(&pVM->pgm.s.fSyncFlags, PGM_SYNC_ALWAYS);
4303	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
4304	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Enabled permanent forced page directory syncing.\n");
4305	}
4306	}
4307
4308	#endif /* VBOX_WITH_DEBUGGER */
4309
4310	/**
4311	* pvUser argument of the pgmR3CheckIntegrity*Node callbacks.
4312	*/
4313	typedef struct PGMCHECKINTARGS
4314	{
4315	bool fLeftToRight; /*< true: left-to-right; false: right-to-left. /
4316	PPGMPHYSHANDLER pPrevPhys;
4317	PPGMVIRTHANDLER pPrevVirt;
4318	PPGMPHYS2VIRTHANDLER pPrevPhys2Virt;
4319	PVM pVM;
4320	} PGMCHECKINTARGS, *PPGMCHECKINTARGS;
4321
4322	/**
4323	* Validate a node in the physical handler tree.
4324	*
4325	* @returns 0 on if ok, other wise 1.
4326	* @param pNode The handler node.
4327	* @param pvUser pVM.
4328	*/
4329	static DECLCALLBACK(int) pgmR3CheckIntegrityPhysHandlerNode(PAVLROGCPHYSNODECORE pNode, void *pvUser)
4330	{
4331	PPGMCHECKINTARGS pArgs = (PPGMCHECKINTARGS)pvUser;
4332	PPGMPHYSHANDLER pCur = (PPGMPHYSHANDLER)pNode;
4333	AssertReleaseReturn(!((uintptr_t)pCur & 7), 1);
4334	AssertReleaseMsg(pCur->Core.Key <= pCur->Core.KeyLast,("pCur=%p %RGp-%RGp %s\n", pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
4335	AssertReleaseMsg( !pArgs->pPrevPhys
4336	\|\| (pArgs->fLeftToRight ? pArgs->pPrevPhys->Core.KeyLast < pCur->Core.Key : pArgs->pPrevPhys->Core.KeyLast > pCur->Core.Key),
4337	("pPrevPhys=%p %RGp-%RGp %s\n"
4338	" pCur=%p %RGp-%RGp %s\n",
4339	pArgs->pPrevPhys, pArgs->pPrevPhys->Core.Key, pArgs->pPrevPhys->Core.KeyLast, pArgs->pPrevPhys->pszDesc,
4340	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
4341	pArgs->pPrevPhys = pCur;
4342	return 0;
4343	}
4344
4345
4346	/**
4347	* Validate a node in the virtual handler tree.
4348	*
4349	* @returns 0 on if ok, other wise 1.
4350	* @param pNode The handler node.
4351	* @param pvUser pVM.
4352	*/
4353	static DECLCALLBACK(int) pgmR3CheckIntegrityVirtHandlerNode(PAVLROGCPTRNODECORE pNode, void *pvUser)
4354	{
4355	PPGMCHECKINTARGS pArgs = (PPGMCHECKINTARGS)pvUser;
4356	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)pNode;
4357	AssertReleaseReturn(!((uintptr_t)pCur & 7), 1);
4358	AssertReleaseMsg(pCur->Core.Key <= pCur->Core.KeyLast,("pCur=%p %RGv-%RGv %s\n", pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
4359	AssertReleaseMsg( !pArgs->pPrevVirt
4360	\|\| (pArgs->fLeftToRight ? pArgs->pPrevVirt->Core.KeyLast < pCur->Core.Key : pArgs->pPrevVirt->Core.KeyLast > pCur->Core.Key),
4361	("pPrevVirt=%p %RGv-%RGv %s\n"
4362	" pCur=%p %RGv-%RGv %s\n",
4363	pArgs->pPrevVirt, pArgs->pPrevVirt->Core.Key, pArgs->pPrevVirt->Core.KeyLast, pArgs->pPrevVirt->pszDesc,
4364	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
4365	for (unsigned iPage = 0; iPage < pCur->cPages; iPage++)
4366	{
4367	AssertReleaseMsg(pCur->aPhysToVirt[iPage].offVirtHandler == -RT_OFFSETOF(PGMVIRTHANDLER, aPhysToVirt[iPage]),
4368	("pCur=%p %RGv-%RGv %s\n"
4369	"iPage=%d offVirtHandle=%#x expected %#x\n",
4370	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc,
4371	iPage, pCur->aPhysToVirt[iPage].offVirtHandler, -RT_OFFSETOF(PGMVIRTHANDLER, aPhysToVirt[iPage])));
4372	}
4373	pArgs->pPrevVirt = pCur;
4374	return 0;
4375	}
4376
4377
4378	/**
4379	* Validate a node in the virtual handler tree.
4380	*
4381	* @returns 0 on if ok, other wise 1.
4382	* @param pNode The handler node.
4383	* @param pvUser pVM.
4384	*/
4385	static DECLCALLBACK(int) pgmR3CheckIntegrityPhysToVirtHandlerNode(PAVLROGCPHYSNODECORE pNode, void *pvUser)
4386	{
4387	PPGMCHECKINTARGS pArgs = (PPGMCHECKINTARGS)pvUser;
4388	PPGMPHYS2VIRTHANDLER pCur = (PPGMPHYS2VIRTHANDLER)pNode;
4389	AssertReleaseMsgReturn(!((uintptr_t)pCur & 3), ("\n"), 1);
4390	AssertReleaseMsgReturn(!(pCur->offVirtHandler & 3), ("\n"), 1);
4391	AssertReleaseMsg(pCur->Core.Key <= pCur->Core.KeyLast,("pCur=%p %RGp-%RGp\n", pCur, pCur->Core.Key, pCur->Core.KeyLast));
4392	AssertReleaseMsg( !pArgs->pPrevPhys2Virt
4393	\|\| (pArgs->fLeftToRight ? pArgs->pPrevPhys2Virt->Core.KeyLast < pCur->Core.Key : pArgs->pPrevPhys2Virt->Core.KeyLast > pCur->Core.Key),
4394	("pPrevPhys2Virt=%p %RGp-%RGp\n"
4395	" pCur=%p %RGp-%RGp\n",
4396	pArgs->pPrevPhys2Virt, pArgs->pPrevPhys2Virt->Core.Key, pArgs->pPrevPhys2Virt->Core.KeyLast,
4397	pCur, pCur->Core.Key, pCur->Core.KeyLast));
4398	AssertReleaseMsg( !pArgs->pPrevPhys2Virt
4399	\|\| (pArgs->fLeftToRight ? pArgs->pPrevPhys2Virt->Core.KeyLast < pCur->Core.Key : pArgs->pPrevPhys2Virt->Core.KeyLast > pCur->Core.Key),
4400	("pPrevPhys2Virt=%p %RGp-%RGp\n"
4401	" pCur=%p %RGp-%RGp\n",
4402	pArgs->pPrevPhys2Virt, pArgs->pPrevPhys2Virt->Core.Key, pArgs->pPrevPhys2Virt->Core.KeyLast,
4403	pCur, pCur->Core.Key, pCur->Core.KeyLast));
4404	AssertReleaseMsg((pCur->offNextAlias & (PGMPHYS2VIRTHANDLER_IN_TREE \| PGMPHYS2VIRTHANDLER_IS_HEAD)) == (PGMPHYS2VIRTHANDLER_IN_TREE \| PGMPHYS2VIRTHANDLER_IS_HEAD),
4405	("pCur=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4406	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias));
4407	if (pCur->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK)
4408	{
4409	PPGMPHYS2VIRTHANDLER pCur2 = pCur;
4410	for (;;)
4411	{
4412	pCur2 = (PPGMPHYS2VIRTHANDLER)((intptr_t)pCur + (pCur->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK));
4413	AssertReleaseMsg(pCur2 != pCur,
4414	(" pCur=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4415	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias));
4416	AssertReleaseMsg((pCur2->offNextAlias & (PGMPHYS2VIRTHANDLER_IN_TREE \| PGMPHYS2VIRTHANDLER_IS_HEAD)) == PGMPHYS2VIRTHANDLER_IN_TREE,
4417	(" pCur=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
4418	"pCur2=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4419	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias,
4420	pCur2, pCur2->Core.Key, pCur2->Core.KeyLast, pCur2->offVirtHandler, pCur2->offNextAlias));
4421	AssertReleaseMsg((pCur2->Core.Key ^ pCur->Core.Key) < PAGE_SIZE,
4422	(" pCur=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
4423	"pCur2=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4424	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias,
4425	pCur2, pCur2->Core.Key, pCur2->Core.KeyLast, pCur2->offVirtHandler, pCur2->offNextAlias));
4426	AssertReleaseMsg((pCur2->Core.KeyLast ^ pCur->Core.KeyLast) < PAGE_SIZE,
4427	(" pCur=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
4428	"pCur2=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4429	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias,
4430	pCur2, pCur2->Core.Key, pCur2->Core.KeyLast, pCur2->offVirtHandler, pCur2->offNextAlias));
4431	if (!(pCur2->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK))
4432	break;
4433	}
4434	}
4435
4436	pArgs->pPrevPhys2Virt = pCur;
4437	return 0;
4438	}
4439
4440
4441	/**
4442	* Perform an integrity check on the PGM component.
4443	*
4444	* @returns VINF_SUCCESS if everything is fine.
4445	* @returns VBox error status after asserting on integrity breach.
4446	* @param pVM The VM handle.
4447	*/
4448	VMMR3DECL(int) PGMR3CheckIntegrity(PVM pVM)
4449	{
4450	AssertReleaseReturn(pVM->pgm.s.offVM, VERR_INTERNAL_ERROR);
4451
4452	/*
4453	* Check the trees.
4454	*/
4455	int cErrors = 0;
4456	const static PGMCHECKINTARGS s_LeftToRight = { true, NULL, NULL, NULL, pVM };
4457	const static PGMCHECKINTARGS s_RightToLeft = { false, NULL, NULL, NULL, pVM };
4458	PGMCHECKINTARGS Args = s_LeftToRight;
4459	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysHandlers, true, pgmR3CheckIntegrityPhysHandlerNode, &Args);
4460	Args = s_RightToLeft;
4461	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysHandlers, false, pgmR3CheckIntegrityPhysHandlerNode, &Args);
4462	Args = s_LeftToRight;
4463	cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesR3->VirtHandlers, true, pgmR3CheckIntegrityVirtHandlerNode, &Args);
4464	Args = s_RightToLeft;
4465	cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesR3->VirtHandlers, false, pgmR3CheckIntegrityVirtHandlerNode, &Args);
4466	Args = s_LeftToRight;
4467	cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesR3->HyperVirtHandlers, true, pgmR3CheckIntegrityVirtHandlerNode, &Args);
4468	Args = s_RightToLeft;
4469	cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesR3->HyperVirtHandlers, false, pgmR3CheckIntegrityVirtHandlerNode, &Args);
4470	Args = s_LeftToRight;
4471	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysToVirtHandlers, true, pgmR3CheckIntegrityPhysToVirtHandlerNode, &Args);
4472	Args = s_RightToLeft;
4473	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysToVirtHandlers, false, pgmR3CheckIntegrityPhysToVirtHandlerNode, &Args);
4474
4475	return !cErrors ? VINF_SUCCESS : VERR_INTERNAL_ERROR;
4476	}
4477
4478
4479	/**
4480	* Inform PGM if we want all mappings to be put into the shadow page table. (necessary for e.g. VMX)
4481	*
4482	* @returns VBox status code.
4483	* @param pVM VM handle.
4484	* @param fEnable Enable or disable shadow mappings
4485	*/
4486	VMMR3DECL(int) PGMR3ChangeShwPDMappings(PVM pVM, bool fEnable)
4487	{
4488	pVM->pgm.s.fDisableMappings = !fEnable;
4489
4490	uint32_t cb;
4491	int rc = PGMR3MappingsSize(pVM, &cb);
4492	AssertRCReturn(rc, rc);
4493
4494	/* Pretend the mappings are now fixed; to force a refresh of the reserved PDEs. */
4495	rc = PGMR3MappingsFix(pVM, MM_HYPER_AREA_ADDRESS, cb);
4496	AssertRCReturn(rc, rc);
4497
4498	return VINF_SUCCESS;
4499	}
4500

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source: vbox/trunk/src/VBox/VMM/PGM.cpp@ 14299

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