PGM.cpp@ 15404

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1	/* $Id: PGM.cpp 15404 2008-12-12 22:43:42Z vboxsync $ */
2	/** @file
3	* PGM - Page Manager and Monitor. (Mixing stuff here, not good?)
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22
23	/** @page pg_pgm PGM - The Page Manager and Monitor
24	*
25	* @see grp_pgm,
26	* @ref pg_pgm_pool,
27	* @ref pg_pgm_phys.
28	*
29	*
30	* @section sec_pgm_modes Paging Modes
31	*
32	* There are three memory contexts: Host Context (HC), Guest Context (GC)
33	* and intermediate context. When talking about paging HC can also be refered to
34	* as "host paging", and GC refered to as "shadow paging".
35	*
36	* We define three basic paging modes: 32-bit, PAE and AMD64. The host paging mode
37	* is defined by the host operating system. The mode used in the shadow paging mode
38	* depends on the host paging mode and what the mode the guest is currently in. The
39	* following relation between the two is defined:
40	*
41	* @verbatim
42	Host > 32-bit \| PAE \| AMD64 \|
43	Guest \| \| \| \|
44	==v================================
45	32-bit 32-bit PAE PAE
46	-------\|--------\|--------\|--------\|
47	PAE PAE PAE PAE
48	-------\|--------\|--------\|--------\|
49	AMD64 AMD64 AMD64 AMD64
50	-------\|--------\|--------\|--------\| @endverbatim
51	*
52	* All configuration except those in the diagonal (upper left) are expected to
53	* require special effort from the switcher (i.e. a bit slower).
54	*
55	*
56	*
57	*
58	* @section sec_pgm_shw The Shadow Memory Context
59	*
60	*
61	* [..]
62	*
63	* Because of guest context mappings requires PDPT and PML4 entries to allow
64	* writing on AMD64, the two upper levels will have fixed flags whatever the
65	* guest is thinking of using there. So, when shadowing the PD level we will
66	* calculate the effective flags of PD and all the higher levels. In legacy
67	* PAE mode this only applies to the PWT and PCD bits (the rest are
68	* ignored/reserved/MBZ). We will ignore those bits for the present.
69	*
70	*
71	*
72	* @section sec_pgm_int The Intermediate Memory Context
73	*
74	* The world switch goes thru an intermediate memory context which purpose it is
75	* to provide different mappings of the switcher code. All guest mappings are also
76	* present in this context.
77	*
78	* The switcher code is mapped at the same location as on the host, at an
79	* identity mapped location (physical equals virtual address), and at the
80	* hypervisor location. The identity mapped location is for when the world
81	* switches that involves disabling paging.
82	*
83	* PGM maintain page tables for 32-bit, PAE and AMD64 paging modes. This
84	* simplifies switching guest CPU mode and consistency at the cost of more
85	* code to do the work. All memory use for those page tables is located below
86	* 4GB (this includes page tables for guest context mappings).
87	*
88	*
89	* @subsection subsec_pgm_int_gc Guest Context Mappings
90	*
91	* During assignment and relocation of a guest context mapping the intermediate
92	* memory context is used to verify the new location.
93	*
94	* Guest context mappings are currently restricted to below 4GB, for reasons
95	* of simplicity. This may change when we implement AMD64 support.
96	*
97	*
98	*
99	*
100	* @section sec_pgm_misc Misc
101	*
102	* @subsection subsec_pgm_misc_diff Differences Between Legacy PAE and Long Mode PAE
103	*
104	* The differences between legacy PAE and long mode PAE are:
105	* -# PDPE bits 1, 2, 5 and 6 are defined differently. In leagcy mode they are
106	* all marked down as must-be-zero, while in long mode 1, 2 and 5 have the
107	* usual meanings while 6 is ignored (AMD). This means that upon switching to
108	* legacy PAE mode we'll have to clear these bits and when going to long mode
109	* they must be set. This applies to both intermediate and shadow contexts,
110	* however we don't need to do it for the intermediate one since we're
111	* executing with CR0.WP at that time.
112	* -# CR3 allows a 32-byte aligned address in legacy mode, while in long mode
113	* a page aligned one is required.
114	*
115	*
116	* @section sec_pgm_handlers Access Handlers
117	*
118	* Placeholder.
119	*
120	*
121	* @subsection sec_pgm_handlers_virt Virtual Access Handlers
122	*
123	* Placeholder.
124	*
125	*
126	* @subsection sec_pgm_handlers_virt Virtual Access Handlers
127	*
128	* We currently implement three types of virtual access handlers: ALL, WRITE
129	* and HYPERVISOR (WRITE). See PGMVIRTHANDLERTYPE for some more details.
130	*
131	* The HYPERVISOR access handlers is kept in a separate tree since it doesn't apply
132	* to physical pages (PGMTREES::HyperVirtHandlers) and only needs to be consulted in
133	* a special \#PF case. The ALL and WRITE are in the PGMTREES::VirtHandlers tree, the
134	* rest of this section is going to be about these handlers.
135	*
136	* We'll go thru the life cycle of a handler and try make sense of it all, don't know
137	* how successfull this is gonna be...
138	*
139	* 1. A handler is registered thru the PGMR3HandlerVirtualRegister and
140	* PGMHandlerVirtualRegisterEx APIs. We check for conflicting virtual handlers
141	* and create a new node that is inserted into the AVL tree (range key). Then
142	* a full PGM resync is flagged (clear pool, sync cr3, update virtual bit of PGMPAGE).
143	*
144	* 2. The following PGMSyncCR3/SyncCR3 operation will first make invoke HandlerVirtualUpdate.
145	*
146	* 2a. HandlerVirtualUpdate will will lookup all the pages covered by virtual handlers
147	* via the current guest CR3 and update the physical page -> virtual handler
148	* translation. Needless to say, this doesn't exactly scale very well. If any changes
149	* are detected, it will flag a virtual bit update just like we did on registration.
150	* PGMPHYS pages with changes will have their virtual handler state reset to NONE.
151	*
152	* 2b. The virtual bit update process will iterate all the pages covered by all the
153	* virtual handlers and update the PGMPAGE virtual handler state to the max of all
154	* virtual handlers on that page.
155	*
156	* 2c. Back in SyncCR3 we will now flush the entire shadow page cache to make sure
157	* we don't miss any alias mappings of the monitored pages.
158	*
159	* 2d. SyncCR3 will then proceed with syncing the CR3 table.
160	*
161	* 3. \#PF(np,read) on a page in the range. This will cause it to be synced
162	* read-only and resumed if it's a WRITE handler. If it's an ALL handler we
163	* will call the handlers like in the next step. If the physical mapping has
164	* changed we will - some time in the future - perform a handler callback
165	* (optional) and update the physical -> virtual handler cache.
166	*
167	* 4. \#PF(,write) on a page in the range. This will cause the handler to
168	* be invoked.
169	*
170	* 5. The guest invalidates the page and changes the physical backing or
171	* unmaps it. This should cause the invalidation callback to be invoked
172	* (it might not yet be 100% perfect). Exactly what happens next... is
173	* this where we mess up and end up out of sync for a while?
174	*
175	* 6. The handler is deregistered by the client via PGMHandlerVirtualDeregister.
176	* We will then set all PGMPAGEs in the physical -> virtual handler cache for
177	* this handler to NONE and trigger a full PGM resync (basically the same
178	* as int step 1). Which means 2 is executed again.
179	*
180	*
181	* @subsubsection sub_sec_pgm_handler_virt_todo TODOs
182	*
183	* There is a bunch of things that needs to be done to make the virtual handlers
184	* work 100% correctly and work more efficiently.
185	*
186	* The first bit hasn't been implemented yet because it's going to slow the
187	* whole mess down even more, and besides it seems to be working reliably for
188	* our current uses. OTOH, some of the optimizations might end up more or less
189	* implementing the missing bits, so we'll see.
190	*
191	* On the optimization side, the first thing to do is to try avoid unnecessary
192	* cache flushing. Then try team up with the shadowing code to track changes
193	* in mappings by means of access to them (shadow in), updates to shadows pages,
194	* invlpg, and shadow PT discarding (perhaps).
195	*
196	* Some idea that have popped up for optimization for current and new features:
197	* - bitmap indicating where there are virtual handlers installed.
198	* (4KB => 220 pages, page 212 => covers 32-bit address space 1:1!)
199	* - Further optimize this by min/max (needs min/max avl getters).
200	* - Shadow page table entry bit (if any left)?
201	*
202	*/
203
204
205	/** @page pg_pgm_phys PGM Physical Guest Memory Management
206	*
207	*
208	* Objectives:
209	* - Guest RAM over-commitment using memory ballooning,
210	* zero pages and general page sharing.
211	* - Moving or mirroring a VM onto a different physical machine.
212	*
213	*
214	* @subsection subsec_pgmPhys_Definitions Definitions
215	*
216	* Allocation chunk - A RTR0MemObjAllocPhysNC object and the tracking
217	* machinery assoicated with it.
218	*
219	*
220	*
221	*
222	* @subsection subsec_pgmPhys_AllocPage Allocating a page.
223	*
224	* Initially we map all guest memory to the (per VM) zero page, which
225	* means that none of the read functions will cause pages to be allocated.
226	*
227	* Exception, access bit in page tables that have been shared. This must
228	* be handled, but we must also make sure PGMGst*Modify doesn't make
229	* unnecessary modifications.
230	*
231	* Allocation points:
232	* - PGMPhysSimpleWriteGCPhys and PGMPhysWrite.
233	* - Replacing a zero page mapping at \#PF.
234	* - Replacing a shared page mapping at \#PF.
235	* - ROM registration (currently MMR3RomRegister).
236	* - VM restore (pgmR3Load).
237	*
238	* For the first three it would make sense to keep a few pages handy
239	* until we've reached the max memory commitment for the VM.
240	*
241	* For the ROM registration, we know exactly how many pages we need
242	* and will request these from ring-0. For restore, we will save
243	* the number of non-zero pages in the saved state and allocate
244	* them up front. This would allow the ring-0 component to refuse
245	* the request if the isn't sufficient memory available for VM use.
246	*
247	* Btw. for both ROM and restore allocations we won't be requiring
248	* zeroed pages as they are going to be filled instantly.
249	*
250	*
251	* @subsection subsec_pgmPhys_FreePage Freeing a page
252	*
253	* There are a few points where a page can be freed:
254	* - After being replaced by the zero page.
255	* - After being replaced by a shared page.
256	* - After being ballooned by the guest additions.
257	* - At reset.
258	* - At restore.
259	*
260	* When freeing one or more pages they will be returned to the ring-0
261	* component and replaced by the zero page.
262	*
263	* The reasoning for clearing out all the pages on reset is that it will
264	* return us to the exact same state as on power on, and may thereby help
265	* us reduce the memory load on the system. Further it might have a
266	* (temporary) positive influence on memory fragmentation (@see subsec_pgmPhys_Fragmentation).
267	*
268	* On restore, as mention under the allocation topic, pages should be
269	* freed / allocated depending on how many is actually required by the
270	* new VM state. The simplest approach is to do like on reset, and free
271	* all non-ROM pages and then allocate what we need.
272	*
273	* A measure to prevent some fragmentation, would be to let each allocation
274	* chunk have some affinity towards the VM having allocated the most pages
275	* from it. Also, try make sure to allocate from allocation chunks that
276	* are almost full. Admittedly, both these measures might work counter to
277	* our intentions and its probably not worth putting a lot of effort,
278	* cpu time or memory into this.
279	*
280	*
281	* @subsection subsec_pgmPhys_SharePage Sharing a page
282	*
283	* The basic idea is that there there will be a idle priority kernel
284	* thread walking the non-shared VM pages hashing them and looking for
285	* pages with the same checksum. If such pages are found, it will compare
286	* them byte-by-byte to see if they actually are identical. If found to be
287	* identical it will allocate a shared page, copy the content, check that
288	* the page didn't change while doing this, and finally request both the
289	* VMs to use the shared page instead. If the page is all zeros (special
290	* checksum and byte-by-byte check) it will request the VM that owns it
291	* to replace it with the zero page.
292	*
293	* To make this efficient, we will have to make sure not to try share a page
294	* that will change its contents soon. This part requires the most work.
295	* A simple idea would be to request the VM to write monitor the page for
296	* a while to make sure it isn't modified any time soon. Also, it may
297	* make sense to skip pages that are being write monitored since this
298	* information is readily available to the thread if it works on the
299	* per-VM guest memory structures (presently called PGMRAMRANGE).
300	*
301	*
302	* @subsection subsec_pgmPhys_Fragmentation Fragmentation Concerns and Counter Measures
303	*
304	* The pages are organized in allocation chunks in ring-0, this is a necessity
305	* if we wish to have an OS agnostic approach to this whole thing. (On Linux we
306	* could easily work on a page-by-page basis if we liked. Whether this is possible
307	* or efficient on NT I don't quite know.) Fragmentation within these chunks may
308	* become a problem as part of the idea here is that we wish to return memory to
309	* the host system.
310	*
311	* For instance, starting two VMs at the same time, they will both allocate the
312	* guest memory on-demand and if permitted their page allocations will be
313	* intermixed. Shut down one of the two VMs and it will be difficult to return
314	* any memory to the host system because the page allocation for the two VMs are
315	* mixed up in the same allocation chunks.
316	*
317	* To further complicate matters, when pages are freed because they have been
318	* ballooned or become shared/zero the whole idea is that the page is supposed
319	* to be reused by another VM or returned to the host system. This will cause
320	* allocation chunks to contain pages belonging to different VMs and prevent
321	* returning memory to the host when one of those VM shuts down.
322	*
323	* The only way to really deal with this problem is to move pages. This can
324	* either be done at VM shutdown and or by the idle priority worker thread
325	* that will be responsible for finding sharable/zero pages. The mechanisms
326	* involved for coercing a VM to move a page (or to do it for it) will be
327	* the same as when telling it to share/zero a page.
328	*
329	*
330	* @subsection subsec_pgmPhys_Tracking Tracking Structures And Their Cost
331	*
332	* There's a difficult balance between keeping the per-page tracking structures
333	* (global and guest page) easy to use and keeping them from eating too much
334	* memory. We have limited virtual memory resources available when operating in
335	* 32-bit kernel space (on 64-bit there'll it's quite a different story). The
336	* tracking structures will be attemted designed such that we can deal with up
337	* to 32GB of memory on a 32-bit system and essentially unlimited on 64-bit ones.
338	*
339	*
340	* @subsubsection subsubsec_pgmPhys_Tracking_Kernel Kernel Space
341	*
342	* @see pg_GMM
343	*
344	* @subsubsection subsubsec_pgmPhys_Tracking_PerVM Per-VM
345	*
346	* Fixed info is the physical address of the page (HCPhys) and the page id
347	* (described above). Theoretically we'll need 48(-12) bits for the HCPhys part.
348	* Today we've restricting ourselves to 40(-12) bits because this is the current
349	* restrictions of all AMD64 implementations (I think Barcelona will up this
350	* to 48(-12) bits, not that it really matters) and I needed the bits for
351	* tracking mappings of a page. 48-12 = 36. That leaves 28 bits, which means a
352	* decent range for the page id: 2^(28+12) = 1024TB.
353	*
354	* In additions to these, we'll have to keep maintaining the page flags as we
355	* currently do. Although it wouldn't harm to optimize these quite a bit, like
356	* for instance the ROM shouldn't depend on having a write handler installed
357	* in order for it to become read-only. A RO/RW bit should be considered so
358	* that the page syncing code doesn't have to mess about checking multiple
359	* flag combinations (ROM \|\| RW handler \|\| write monitored) in order to
360	* figure out how to setup a shadow PTE. But this of course, is second
361	* priority at present. Current this requires 12 bits, but could probably
362	* be optimized to ~8.
363	*
364	* Then there's the 24 bits used to track which shadow page tables are
365	* currently mapping a page for the purpose of speeding up physical
366	* access handlers, and thereby the page pool cache. More bit for this
367	* purpose wouldn't hurt IIRC.
368	*
369	* Then there is a new bit in which we need to record what kind of page
370	* this is, shared, zero, normal or write-monitored-normal. This'll
371	* require 2 bits. One bit might be needed for indicating whether a
372	* write monitored page has been written to. And yet another one or
373	* two for tracking migration status. 3-4 bits total then.
374	*
375	* Whatever is left will can be used to record the sharabilitiy of a
376	* page. The page checksum will not be stored in the per-VM table as
377	* the idle thread will not be permitted to do modifications to it.
378	* It will instead have to keep its own working set of potentially
379	* shareable pages and their check sums and stuff.
380	*
381	* For the present we'll keep the current packing of the
382	* PGMRAMRANGE::aHCPhys to keep the changes simple, only of course,
383	* we'll have to change it to a struct with a total of 128-bits at
384	* our disposal.
385	*
386	* The initial layout will be like this:
387	* @verbatim
388	RTHCPHYS HCPhys; The current stuff.
389	63:40 Current shadow PT tracking stuff.
390	39:12 The physical page frame number.
391	11:0 The current flags.
392	uint32_t u28PageId : 28; The page id.
393	uint32_t u2State : 2; The page state { zero, shared, normal, write monitored }.
394	uint32_t fWrittenTo : 1; Whether a write monitored page was written to.
395	uint32_t u1Reserved : 1; Reserved for later.
396	uint32_t u32Reserved; Reserved for later, mostly sharing stats.
397	@endverbatim
398	*
399	* The final layout will be something like this:
400	* @verbatim
401	RTHCPHYS HCPhys; The current stuff.
402	63:48 High page id (12+).
403	47:12 The physical page frame number.
404	11:0 Low page id.
405	uint32_t fReadOnly : 1; Whether it's readonly page (rom or monitored in some way).
406	uint32_t u3Type : 3; The page type {RESERVED, MMIO, MMIO2, ROM, shadowed ROM, RAM}.
407	uint32_t u2PhysMon : 2; Physical access handler type {none, read, write, all}.
408	uint32_t u2VirtMon : 2; Virtual access handler type {none, read, write, all}..
409	uint32_t u2State : 2; The page state { zero, shared, normal, write monitored }.
410	uint32_t fWrittenTo : 1; Whether a write monitored page was written to.
411	uint32_t u20Reserved : 20; Reserved for later, mostly sharing stats.
412	uint32_t u32Tracking; The shadow PT tracking stuff, roughly.
413	@endverbatim
414	*
415	* Cost wise, this means we'll double the cost for guest memory. There isn't anyway
416	* around that I'm afraid. It means that the cost of dealing out 32GB of memory
417	* to one or more VMs is: (32GB >> PAGE_SHIFT) * 16 bytes, or 128MBs. Or another
418	* example, the VM heap cost when assigning 1GB to a VM will be: 4MB.
419	*
420	* A couple of cost examples for the total cost per-VM + kernel.
421	* 32-bit Windows and 32-bit linux:
422	* 1GB guest ram, 256K pages: 4MB + 2MB(+) = 6MB
423	* 4GB guest ram, 1M pages: 16MB + 8MB(+) = 24MB
424	* 32GB guest ram, 8M pages: 128MB + 64MB(+) = 192MB
425	* 64-bit Windows and 64-bit linux:
426	* 1GB guest ram, 256K pages: 4MB + 3MB(+) = 7MB
427	* 4GB guest ram, 1M pages: 16MB + 12MB(+) = 28MB
428	* 32GB guest ram, 8M pages: 128MB + 96MB(+) = 224MB
429	*
430	* UPDATE - 2007-09-27:
431	* Will need a ballooned flag/state too because we cannot
432	* trust the guest 100% and reporting the same page as ballooned more
433	* than once will put the GMM off balance.
434	*
435	*
436	* @subsection subsec_pgmPhys_Serializing Serializing Access
437	*
438	* Initially, we'll try a simple scheme:
439	*
440	* - The per-VM RAM tracking structures (PGMRAMRANGE) is only modified
441	* by the EMT thread of that VM while in the pgm critsect.
442	* - Other threads in the VM process that needs to make reliable use of
443	* the per-VM RAM tracking structures will enter the critsect.
444	* - No process external thread or kernel thread will ever try enter
445	* the pgm critical section, as that just won't work.
446	* - The idle thread (and similar threads) doesn't not need 100% reliable
447	* data when performing it tasks as the EMT thread will be the one to
448	* do the actual changes later anyway. So, as long as it only accesses
449	* the main ram range, it can do so by somehow preventing the VM from
450	* being destroyed while it works on it...
451	*
452	* - The over-commitment management, including the allocating/freeing
453	* chunks, is serialized by a ring-0 mutex lock (a fast one since the
454	* more mundane mutex implementation is broken on Linux).
455	* - A separeate mutex is protecting the set of allocation chunks so
456	* that pages can be shared or/and freed up while some other VM is
457	* allocating more chunks. This mutex can be take from under the other
458	* one, but not the otherway around.
459	*
460	*
461	* @subsection subsec_pgmPhys_Request VM Request interface
462	*
463	* When in ring-0 it will become necessary to send requests to a VM so it can
464	* for instance move a page while defragmenting during VM destroy. The idle
465	* thread will make use of this interface to request VMs to setup shared
466	* pages and to perform write monitoring of pages.
467	*
468	* I would propose an interface similar to the current VMReq interface, similar
469	* in that it doesn't require locking and that the one sending the request may
470	* wait for completion if it wishes to. This shouldn't be very difficult to
471	* realize.
472	*
473	* The requests themselves are also pretty simple. They are basically:
474	* -# Check that some precondition is still true.
475	* -# Do the update.
476	* -# Update all shadow page tables involved with the page.
477	*
478	* The 3rd step is identical to what we're already doing when updating a
479	* physical handler, see pgmHandlerPhysicalSetRamFlagsAndFlushShadowPTs.
480	*
481	*
482	*
483	* @section sec_pgmPhys_MappingCaches Mapping Caches
484	*
485	* In order to be able to map in and out memory and to be able to support
486	* guest with more RAM than we've got virtual address space, we'll employing
487	* a mapping cache. There is already a tiny one for GC (see PGMGCDynMapGCPageEx)
488	* and we'll create a similar one for ring-0 unless we decide to setup a dedicate
489	* memory context for the HWACCM execution.
490	*
491	*
492	* @subsection subsec_pgmPhys_MappingCaches_R3 Ring-3
493	*
494	* We've considered implementing the ring-3 mapping cache page based but found
495	* that this was bother some when one had to take into account TLBs+SMP and
496	* portability (missing the necessary APIs on several platforms). There were
497	* also some performance concerns with this approach which hadn't quite been
498	* worked out.
499	*
500	* Instead, we'll be mapping allocation chunks into the VM process. This simplifies
501	* matters greatly quite a bit since we don't need to invent any new ring-0 stuff,
502	* only some minor RTR0MEMOBJ mapping stuff. The main concern here is that mapping
503	* compared to the previous idea is that mapping or unmapping a 1MB chunk is more
504	* costly than a single page, although how much more costly is uncertain. We'll
505	* try address this by using a very big cache, preferably bigger than the actual
506	* VM RAM size if possible. The current VM RAM sizes should give some idea for
507	* 32-bit boxes, while on 64-bit we can probably get away with employing an
508	* unlimited cache.
509	*
510	* The cache have to parts, as already indicated, the ring-3 side and the
511	* ring-0 side.
512	*
513	* The ring-0 will be tied to the page allocator since it will operate on the
514	* memory objects it contains. It will therefore require the first ring-0 mutex
515	* discussed in @ref subsec_pgmPhys_Serializing. We
516	* some double house keeping wrt to who has mapped what I think, since both
517	* VMMR0.r0 and RTR0MemObj will keep track of mapping relataions
518	*
519	* The ring-3 part will be protected by the pgm critsect. For simplicity, we'll
520	* require anyone that desires to do changes to the mapping cache to do that
521	* from within this critsect. Alternatively, we could employ a separate critsect
522	* for serializing changes to the mapping cache as this would reduce potential
523	* contention with other threads accessing mappings unrelated to the changes
524	* that are in process. We can see about this later, contention will show
525	* up in the statistics anyway, so it'll be simple to tell.
526	*
527	* The organization of the ring-3 part will be very much like how the allocation
528	* chunks are organized in ring-0, that is in an AVL tree by chunk id. To avoid
529	* having to walk the tree all the time, we'll have a couple of lookaside entries
530	* like in we do for I/O ports and MMIO in IOM.
531	*
532	* The simplified flow of a PGMPhysRead/Write function:
533	* -# Enter the PGM critsect.
534	* -# Lookup GCPhys in the ram ranges and get the Page ID.
535	* -# Calc the Allocation Chunk ID from the Page ID.
536	* -# Check the lookaside entries and then the AVL tree for the Chunk ID.
537	* If not found in cache:
538	* -# Call ring-0 and request it to be mapped and supply
539	* a chunk to be unmapped if the cache is maxed out already.
540	* -# Insert the new mapping into the AVL tree (id + R3 address).
541	* -# Update the relevant lookaside entry and return the mapping address.
542	* -# Do the read/write according to monitoring flags and everything.
543	* -# Leave the critsect.
544	*
545	*
546	* @section sec_pgmPhys_Fallback Fallback
547	*
548	* Current all the "second tier" hosts will not support the RTR0MemObjAllocPhysNC
549	* API and thus require a fallback.
550	*
551	* So, when RTR0MemObjAllocPhysNC returns VERR_NOT_SUPPORTED the page allocator
552	* will return to the ring-3 caller (and later ring-0) and asking it to seed
553	* the page allocator with some fresh pages (VERR_GMM_SEED_ME). Ring-3 will
554	* then perform an SUPPageAlloc(cbChunk >> PAGE_SHIFT) call and make a
555	* "SeededAllocPages" call to ring-0.
556	*
557	* The first time ring-0 sees the VERR_NOT_SUPPORTED failure it will disable
558	* all page sharing (zero page detection will continue). It will also force
559	* all allocations to come from the VM which seeded the page. Both these
560	* measures are taken to make sure that there will never be any need for
561	* mapping anything into ring-3 - everything will be mapped already.
562	*
563	* Whether we'll continue to use the current MM locked memory management
564	* for this I don't quite know (I'd prefer not to and just ditch that all
565	* togther), we'll see what's simplest to do.
566	*
567	*
568	*
569	* @section sec_pgmPhys_Changes Changes
570	*
571	* Breakdown of the changes involved?
572	*/
573
574
575	/** Saved state data unit version. */
576	#define PGM_SAVED_STATE_VERSION 6
577
578	/*******************************************************************************
579	* Header Files *
580	*******************************************************************************/
581	#define LOG_GROUP LOG_GROUP_PGM
582	#include <VBox/dbgf.h>
583	#include <VBox/pgm.h>
584	#include <VBox/cpum.h>
585	#include <VBox/iom.h>
586	#include <VBox/sup.h>
587	#include <VBox/mm.h>
588	#include <VBox/em.h>
589	#include <VBox/stam.h>
590	#include <VBox/rem.h>
591	#include <VBox/dbgf.h>
592	#include <VBox/rem.h>
593	#include <VBox/selm.h>
594	#include <VBox/ssm.h>
595	#include "PGMInternal.h"
596	#include <VBox/vm.h>
597	#include <VBox/dbg.h>
598	#include <VBox/hwaccm.h>
599
600	#include <iprt/assert.h>
601	#include <iprt/alloc.h>
602	#include <iprt/asm.h>
603	#include <iprt/thread.h>
604	#include <iprt/string.h>
605	#ifdef DEBUG_bird
606	# include <iprt/env.h>
607	#endif
608	#include <VBox/param.h>
609	#include <VBox/err.h>
610
611
612
613	/*******************************************************************************
614	* Internal Functions *
615	*******************************************************************************/
616	static int pgmR3InitPaging(PVM pVM);
617	static DECLCALLBACK(void) pgmR3PhysInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
618	static DECLCALLBACK(void) pgmR3InfoMode(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
619	static DECLCALLBACK(void) pgmR3InfoCr3(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
620	static DECLCALLBACK(int) pgmR3RelocatePhysHandler(PAVLROGCPHYSNODECORE pNode, void *pvUser);
621	static DECLCALLBACK(int) pgmR3RelocateVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser);
622	static DECLCALLBACK(int) pgmR3RelocateHyperVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser);
623	#ifdef VBOX_STRICT
624	static DECLCALLBACK(void) pgmR3ResetNoMorePhysWritesFlag(PVM pVM, VMSTATE enmState, VMSTATE enmOldState, void *pvUser);
625	#endif
626	static DECLCALLBACK(int) pgmR3Save(PVM pVM, PSSMHANDLE pSSM);
627	static DECLCALLBACK(int) pgmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version);
628	static int pgmR3ModeDataInit(PVM pVM, bool fResolveGCAndR0);
629	static void pgmR3ModeDataSwitch(PVM pVM, PGMMODE enmShw, PGMMODE enmGst);
630	static PGMMODE pgmR3CalcShadowMode(PVM pVM, PGMMODE enmGuestMode, SUPPAGINGMODE enmHostMode, PGMMODE enmShadowMode, VMMSWITCHER *penmSwitcher);
631
632	#ifdef VBOX_WITH_STATISTICS
633	static void pgmR3InitStats(PVM pVM);
634	#endif
635
636	#ifdef VBOX_WITH_DEBUGGER
637	/** @todo all but the two last commands must be converted to 'info'. */
638	static DECLCALLBACK(int) pgmR3CmdRam(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
639	static DECLCALLBACK(int) pgmR3CmdMap(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
640	static DECLCALLBACK(int) pgmR3CmdSync(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
641	static DECLCALLBACK(int) pgmR3CmdSyncAlways(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
642	# ifdef VBOX_STRICT
643	static DECLCALLBACK(int) pgmR3CmdAssertCR3(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
644	# endif
645	#endif
646
647
648	/*******************************************************************************
649	* Global Variables *
650	*******************************************************************************/
651	#ifdef VBOX_WITH_DEBUGGER
652	/** Command descriptors. */
653	static const DBGCCMD g_aCmds[] =
654	{
655	/* pszCmd, cArgsMin, cArgsMax, paArgDesc, cArgDescs, pResultDesc, fFlags, pfnHandler pszSyntax, ....pszDescription */
656	{ "pgmram", 0, 0, NULL, 0, NULL, 0, pgmR3CmdRam, "", "Display the ram ranges." },
657	{ "pgmmap", 0, 0, NULL, 0, NULL, 0, pgmR3CmdMap, "", "Display the mapping ranges." },
658	{ "pgmsync", 0, 0, NULL, 0, NULL, 0, pgmR3CmdSync, "", "Sync the CR3 page." },
659	#ifdef VBOX_STRICT
660	{ "pgmassertcr3", 0, 0, NULL, 0, NULL, 0, pgmR3CmdAssertCR3, "", "Check the shadow CR3 mapping." },
661	#endif
662	{ "pgmsyncalways", 0, 0, NULL, 0, NULL, 0, pgmR3CmdSyncAlways, "", "Toggle permanent CR3 syncing." },
663	};
664	#endif
665
666
667
668
669	/*
670	* Shadow - 32-bit mode
671	*/
672	#define PGM_SHW_TYPE PGM_TYPE_32BIT
673	#define PGM_SHW_NAME(name) PGM_SHW_NAME_32BIT(name)
674	#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_32BIT_STR(name)
675	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_32BIT_STR(name)
676	#include "PGMShw.h"
677
678	/* Guest - real mode */
679	#define PGM_GST_TYPE PGM_TYPE_REAL
680	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
681	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_REAL_STR(name)
682	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
683	#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_REAL(name)
684	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_32BIT_REAL_STR(name)
685	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_32BIT_REAL_STR(name)
686	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_PHYS
687	#include "PGMGst.h"
688	#include "PGMBth.h"
689	#undef BTH_PGMPOOLKIND_PT_FOR_PT
690	#undef PGM_BTH_NAME
691	#undef PGM_BTH_NAME_RC_STR
692	#undef PGM_BTH_NAME_R0_STR
693	#undef PGM_GST_TYPE
694	#undef PGM_GST_NAME
695	#undef PGM_GST_NAME_RC_STR
696	#undef PGM_GST_NAME_R0_STR
697
698	/* Guest - protected mode */
699	#define PGM_GST_TYPE PGM_TYPE_PROT
700	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
701	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PROT_STR(name)
702	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
703	#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_PROT(name)
704	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_32BIT_PROT_STR(name)
705	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_32BIT_PROT_STR(name)
706	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_PHYS
707	#include "PGMGst.h"
708	#include "PGMBth.h"
709	#undef BTH_PGMPOOLKIND_PT_FOR_PT
710	#undef PGM_BTH_NAME
711	#undef PGM_BTH_NAME_RC_STR
712	#undef PGM_BTH_NAME_R0_STR
713	#undef PGM_GST_TYPE
714	#undef PGM_GST_NAME
715	#undef PGM_GST_NAME_RC_STR
716	#undef PGM_GST_NAME_R0_STR
717
718	/* Guest - 32-bit mode */
719	#define PGM_GST_TYPE PGM_TYPE_32BIT
720	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
721	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_32BIT_STR(name)
722	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
723	#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_32BIT(name)
724	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_32BIT_32BIT_STR(name)
725	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_32BIT_32BIT_STR(name)
726	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT
727	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB
728	#include "PGMGst.h"
729	#include "PGMBth.h"
730	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
731	#undef BTH_PGMPOOLKIND_PT_FOR_PT
732	#undef PGM_BTH_NAME
733	#undef PGM_BTH_NAME_RC_STR
734	#undef PGM_BTH_NAME_R0_STR
735	#undef PGM_GST_TYPE
736	#undef PGM_GST_NAME
737	#undef PGM_GST_NAME_RC_STR
738	#undef PGM_GST_NAME_R0_STR
739
740	#undef PGM_SHW_TYPE
741	#undef PGM_SHW_NAME
742	#undef PGM_SHW_NAME_RC_STR
743	#undef PGM_SHW_NAME_R0_STR
744
745
746	/*
747	* Shadow - PAE mode
748	*/
749	#define PGM_SHW_TYPE PGM_TYPE_PAE
750	#define PGM_SHW_NAME(name) PGM_SHW_NAME_PAE(name)
751	#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_PAE_STR(name)
752	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_PAE_STR(name)
753	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_REAL(name)
754	#include "PGMShw.h"
755
756	/* Guest - real mode */
757	#define PGM_GST_TYPE PGM_TYPE_REAL
758	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
759	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_REAL_STR(name)
760	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
761	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_REAL(name)
762	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_PAE_REAL_STR(name)
763	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_REAL_STR(name)
764	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
765	#include "PGMBth.h"
766	#undef BTH_PGMPOOLKIND_PT_FOR_PT
767	#undef PGM_BTH_NAME
768	#undef PGM_BTH_NAME_RC_STR
769	#undef PGM_BTH_NAME_R0_STR
770	#undef PGM_GST_TYPE
771	#undef PGM_GST_NAME
772	#undef PGM_GST_NAME_RC_STR
773	#undef PGM_GST_NAME_R0_STR
774
775	/* Guest - protected mode */
776	#define PGM_GST_TYPE PGM_TYPE_PROT
777	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
778	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PROT_STR(name)
779	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
780	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_PROT(name)
781	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_PAE_PROT_STR(name)
782	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_PROT_STR(name)
783	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
784	#include "PGMBth.h"
785	#undef BTH_PGMPOOLKIND_PT_FOR_PT
786	#undef PGM_BTH_NAME
787	#undef PGM_BTH_NAME_RC_STR
788	#undef PGM_BTH_NAME_R0_STR
789	#undef PGM_GST_TYPE
790	#undef PGM_GST_NAME
791	#undef PGM_GST_NAME_RC_STR
792	#undef PGM_GST_NAME_R0_STR
793
794	/* Guest - 32-bit mode */
795	#define PGM_GST_TYPE PGM_TYPE_32BIT
796	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
797	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_32BIT_STR(name)
798	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
799	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_32BIT(name)
800	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_PAE_32BIT_STR(name)
801	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_32BIT_STR(name)
802	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_32BIT_PT
803	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB
804	#include "PGMBth.h"
805	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
806	#undef BTH_PGMPOOLKIND_PT_FOR_PT
807	#undef PGM_BTH_NAME
808	#undef PGM_BTH_NAME_RC_STR
809	#undef PGM_BTH_NAME_R0_STR
810	#undef PGM_GST_TYPE
811	#undef PGM_GST_NAME
812	#undef PGM_GST_NAME_RC_STR
813	#undef PGM_GST_NAME_R0_STR
814
815	/* Guest - PAE mode */
816	#define PGM_GST_TYPE PGM_TYPE_PAE
817	#define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
818	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PAE_STR(name)
819	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PAE_STR(name)
820	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_PAE(name)
821	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_PAE_PAE_STR(name)
822	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_PAE_STR(name)
823	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
824	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
825	#include "PGMGst.h"
826	#include "PGMBth.h"
827	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
828	#undef BTH_PGMPOOLKIND_PT_FOR_PT
829	#undef PGM_BTH_NAME
830	#undef PGM_BTH_NAME_RC_STR
831	#undef PGM_BTH_NAME_R0_STR
832	#undef PGM_GST_TYPE
833	#undef PGM_GST_NAME
834	#undef PGM_GST_NAME_RC_STR
835	#undef PGM_GST_NAME_R0_STR
836
837	#undef PGM_SHW_TYPE
838	#undef PGM_SHW_NAME
839	#undef PGM_SHW_NAME_RC_STR
840	#undef PGM_SHW_NAME_R0_STR
841
842
843	/*
844	* Shadow - AMD64 mode
845	*/
846	#define PGM_SHW_TYPE PGM_TYPE_AMD64
847	#define PGM_SHW_NAME(name) PGM_SHW_NAME_AMD64(name)
848	#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_AMD64_STR(name)
849	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_AMD64_STR(name)
850	#include "PGMShw.h"
851
852	#ifdef VBOX_WITH_64_BITS_GUESTS
853	/* Guest - AMD64 mode */
854	# define PGM_GST_TYPE PGM_TYPE_AMD64
855	# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
856	# define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_AMD64_STR(name)
857	# define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_AMD64_STR(name)
858	# define PGM_BTH_NAME(name) PGM_BTH_NAME_AMD64_AMD64(name)
859	# define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_AMD64_AMD64_STR(name)
860	# define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_AMD64_AMD64_STR(name)
861	# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
862	# define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
863	# include "PGMGst.h"
864	# include "PGMBth.h"
865	# undef BTH_PGMPOOLKIND_PT_FOR_BIG
866	# undef BTH_PGMPOOLKIND_PT_FOR_PT
867	# undef PGM_BTH_NAME
868	# undef PGM_BTH_NAME_RC_STR
869	# undef PGM_BTH_NAME_R0_STR
870	# undef PGM_GST_TYPE
871	# undef PGM_GST_NAME
872	# undef PGM_GST_NAME_RC_STR
873	# undef PGM_GST_NAME_R0_STR
874	#endif /* VBOX_WITH_64_BITS_GUESTS */
875
876	#undef PGM_SHW_TYPE
877	#undef PGM_SHW_NAME
878	#undef PGM_SHW_NAME_RC_STR
879	#undef PGM_SHW_NAME_R0_STR
880
881
882	/*
883	* Shadow - Nested paging mode
884	*/
885	#define PGM_SHW_TYPE PGM_TYPE_NESTED
886	#define PGM_SHW_NAME(name) PGM_SHW_NAME_NESTED(name)
887	#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_NESTED_STR(name)
888	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_NESTED_STR(name)
889	#include "PGMShw.h"
890
891	/* Guest - real mode */
892	#define PGM_GST_TYPE PGM_TYPE_REAL
893	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
894	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_REAL_STR(name)
895	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
896	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_REAL(name)
897	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_REAL_STR(name)
898	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_REAL_STR(name)
899	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
900	#include "PGMBth.h"
901	#undef BTH_PGMPOOLKIND_PT_FOR_PT
902	#undef PGM_BTH_NAME
903	#undef PGM_BTH_NAME_RC_STR
904	#undef PGM_BTH_NAME_R0_STR
905	#undef PGM_GST_TYPE
906	#undef PGM_GST_NAME
907	#undef PGM_GST_NAME_RC_STR
908	#undef PGM_GST_NAME_R0_STR
909
910	/* Guest - protected mode */
911	#define PGM_GST_TYPE PGM_TYPE_PROT
912	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
913	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PROT_STR(name)
914	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
915	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_PROT(name)
916	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_PROT_STR(name)
917	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_PROT_STR(name)
918	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
919	#include "PGMBth.h"
920	#undef BTH_PGMPOOLKIND_PT_FOR_PT
921	#undef PGM_BTH_NAME
922	#undef PGM_BTH_NAME_RC_STR
923	#undef PGM_BTH_NAME_R0_STR
924	#undef PGM_GST_TYPE
925	#undef PGM_GST_NAME
926	#undef PGM_GST_NAME_RC_STR
927	#undef PGM_GST_NAME_R0_STR
928
929	/* Guest - 32-bit mode */
930	#define PGM_GST_TYPE PGM_TYPE_32BIT
931	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
932	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_32BIT_STR(name)
933	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
934	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_32BIT(name)
935	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_32BIT_STR(name)
936	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_32BIT_STR(name)
937	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_32BIT_PT
938	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB
939	#include "PGMBth.h"
940	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
941	#undef BTH_PGMPOOLKIND_PT_FOR_PT
942	#undef PGM_BTH_NAME
943	#undef PGM_BTH_NAME_RC_STR
944	#undef PGM_BTH_NAME_R0_STR
945	#undef PGM_GST_TYPE
946	#undef PGM_GST_NAME
947	#undef PGM_GST_NAME_RC_STR
948	#undef PGM_GST_NAME_R0_STR
949
950	/* Guest - PAE mode */
951	#define PGM_GST_TYPE PGM_TYPE_PAE
952	#define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
953	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PAE_STR(name)
954	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PAE_STR(name)
955	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_PAE(name)
956	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_PAE_STR(name)
957	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_PAE_STR(name)
958	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
959	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
960	#include "PGMBth.h"
961	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
962	#undef BTH_PGMPOOLKIND_PT_FOR_PT
963	#undef PGM_BTH_NAME
964	#undef PGM_BTH_NAME_RC_STR
965	#undef PGM_BTH_NAME_R0_STR
966	#undef PGM_GST_TYPE
967	#undef PGM_GST_NAME
968	#undef PGM_GST_NAME_RC_STR
969	#undef PGM_GST_NAME_R0_STR
970
971	#ifdef VBOX_WITH_64_BITS_GUESTS
972	/* Guest - AMD64 mode */
973	# define PGM_GST_TYPE PGM_TYPE_AMD64
974	# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
975	# define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_AMD64_STR(name)
976	# define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_AMD64_STR(name)
977	# define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_AMD64(name)
978	# define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_AMD64_STR(name)
979	# define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_AMD64_STR(name)
980	# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
981	# define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
982	# include "PGMBth.h"
983	# undef BTH_PGMPOOLKIND_PT_FOR_BIG
984	# undef BTH_PGMPOOLKIND_PT_FOR_PT
985	# undef PGM_BTH_NAME
986	# undef PGM_BTH_NAME_RC_STR
987	# undef PGM_BTH_NAME_R0_STR
988	# undef PGM_GST_TYPE
989	# undef PGM_GST_NAME
990	# undef PGM_GST_NAME_RC_STR
991	# undef PGM_GST_NAME_R0_STR
992	#endif /* VBOX_WITH_64_BITS_GUESTS */
993
994	#undef PGM_SHW_TYPE
995	#undef PGM_SHW_NAME
996	#undef PGM_SHW_NAME_RC_STR
997	#undef PGM_SHW_NAME_R0_STR
998
999
1000	/*
1001	* Shadow - EPT
1002	*/
1003	#define PGM_SHW_TYPE PGM_TYPE_EPT
1004	#define PGM_SHW_NAME(name) PGM_SHW_NAME_EPT(name)
1005	#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_EPT_STR(name)
1006	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_EPT_STR(name)
1007	#include "PGMShw.h"
1008
1009	/* Guest - real mode */
1010	#define PGM_GST_TYPE PGM_TYPE_REAL
1011	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
1012	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_REAL_STR(name)
1013	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
1014	#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_REAL(name)
1015	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_REAL_STR(name)
1016	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_REAL_STR(name)
1017	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
1018	#include "PGMBth.h"
1019	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1020	#undef PGM_BTH_NAME
1021	#undef PGM_BTH_NAME_RC_STR
1022	#undef PGM_BTH_NAME_R0_STR
1023	#undef PGM_GST_TYPE
1024	#undef PGM_GST_NAME
1025	#undef PGM_GST_NAME_RC_STR
1026	#undef PGM_GST_NAME_R0_STR
1027
1028	/* Guest - protected mode */
1029	#define PGM_GST_TYPE PGM_TYPE_PROT
1030	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
1031	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PROT_STR(name)
1032	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
1033	#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_PROT(name)
1034	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_PROT_STR(name)
1035	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_PROT_STR(name)
1036	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
1037	#include "PGMBth.h"
1038	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1039	#undef PGM_BTH_NAME
1040	#undef PGM_BTH_NAME_RC_STR
1041	#undef PGM_BTH_NAME_R0_STR
1042	#undef PGM_GST_TYPE
1043	#undef PGM_GST_NAME
1044	#undef PGM_GST_NAME_RC_STR
1045	#undef PGM_GST_NAME_R0_STR
1046
1047	/* Guest - 32-bit mode */
1048	#define PGM_GST_TYPE PGM_TYPE_32BIT
1049	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
1050	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_32BIT_STR(name)
1051	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
1052	#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_32BIT(name)
1053	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_32BIT_STR(name)
1054	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_32BIT_STR(name)
1055	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_32BIT_PT
1056	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB
1057	#include "PGMBth.h"
1058	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
1059	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1060	#undef PGM_BTH_NAME
1061	#undef PGM_BTH_NAME_RC_STR
1062	#undef PGM_BTH_NAME_R0_STR
1063	#undef PGM_GST_TYPE
1064	#undef PGM_GST_NAME
1065	#undef PGM_GST_NAME_RC_STR
1066	#undef PGM_GST_NAME_R0_STR
1067
1068	/* Guest - PAE mode */
1069	#define PGM_GST_TYPE PGM_TYPE_PAE
1070	#define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
1071	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PAE_STR(name)
1072	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PAE_STR(name)
1073	#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_PAE(name)
1074	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_PAE_STR(name)
1075	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_PAE_STR(name)
1076	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
1077	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
1078	#include "PGMBth.h"
1079	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
1080	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1081	#undef PGM_BTH_NAME
1082	#undef PGM_BTH_NAME_RC_STR
1083	#undef PGM_BTH_NAME_R0_STR
1084	#undef PGM_GST_TYPE
1085	#undef PGM_GST_NAME
1086	#undef PGM_GST_NAME_RC_STR
1087	#undef PGM_GST_NAME_R0_STR
1088
1089	#ifdef VBOX_WITH_64_BITS_GUESTS
1090	/* Guest - AMD64 mode */
1091	# define PGM_GST_TYPE PGM_TYPE_AMD64
1092	# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
1093	# define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_AMD64_STR(name)
1094	# define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_AMD64_STR(name)
1095	# define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_AMD64(name)
1096	# define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_AMD64_STR(name)
1097	# define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_AMD64_STR(name)
1098	# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
1099	# define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
1100	# include "PGMBth.h"
1101	# undef BTH_PGMPOOLKIND_PT_FOR_BIG
1102	# undef BTH_PGMPOOLKIND_PT_FOR_PT
1103	# undef PGM_BTH_NAME
1104	# undef PGM_BTH_NAME_RC_STR
1105	# undef PGM_BTH_NAME_R0_STR
1106	# undef PGM_GST_TYPE
1107	# undef PGM_GST_NAME
1108	# undef PGM_GST_NAME_RC_STR
1109	# undef PGM_GST_NAME_R0_STR
1110	#endif /* VBOX_WITH_64_BITS_GUESTS */
1111
1112	#undef PGM_SHW_TYPE
1113	#undef PGM_SHW_NAME
1114	#undef PGM_SHW_NAME_RC_STR
1115	#undef PGM_SHW_NAME_R0_STR
1116
1117
1118
1119	/**
1120	* Initiates the paging of VM.
1121	*
1122	* @returns VBox status code.
1123	* @param pVM Pointer to VM structure.
1124	*/
1125	VMMR3DECL(int) PGMR3Init(PVM pVM)
1126	{
1127	LogFlow(("PGMR3Init:\n"));
1128
1129	/*
1130	* Assert alignment and sizes.
1131	*/
1132	AssertRelease(sizeof(pVM->pgm.s) <= sizeof(pVM->pgm.padding));
1133
1134	/*
1135	* Init the structure.
1136	*/
1137	pVM->pgm.s.offVM = RT_OFFSETOF(VM, pgm.s);
1138	pVM->pgm.s.offVCpu = RT_OFFSETOF(VMCPU, pgm.s);
1139	pVM->pgm.s.enmShadowMode = PGMMODE_INVALID;
1140	pVM->pgm.s.enmGuestMode = PGMMODE_INVALID;
1141	pVM->pgm.s.enmHostMode = SUPPAGINGMODE_INVALID;
1142	pVM->pgm.s.GCPhysCR3 = NIL_RTGCPHYS;
1143	pVM->pgm.s.GCPhysGstCR3Monitored = NIL_RTGCPHYS;
1144	pVM->pgm.s.fA20Enabled = true;
1145	pVM->pgm.s.GCPhys4MBPSEMask = RT_BIT_64(32) - 1; /* default; checked later */
1146	pVM->pgm.s.pGstPaePdptR3 = NULL;
1147	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
1148	pVM->pgm.s.pGstPaePdptR0 = NIL_RTR0PTR;
1149	#endif
1150	pVM->pgm.s.pGstPaePdptRC = NIL_RTRCPTR;
1151	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.apGstPaePDsR3); i++)
1152	{
1153	pVM->pgm.s.apGstPaePDsR3[i] = NULL;
1154	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
1155	pVM->pgm.s.apGstPaePDsR0[i] = NIL_RTR0PTR;
1156	#endif
1157	pVM->pgm.s.apGstPaePDsRC[i] = NIL_RTRCPTR;
1158	pVM->pgm.s.aGCPhysGstPaePDs[i] = NIL_RTGCPHYS;
1159	pVM->pgm.s.aGCPhysGstPaePDsMonitored[i] = NIL_RTGCPHYS;
1160	}
1161
1162	#ifdef VBOX_STRICT
1163	VMR3AtStateRegister(pVM, pgmR3ResetNoMorePhysWritesFlag, NULL);
1164	#endif
1165
1166	/*
1167	* Get the configured RAM size - to estimate saved state size.
1168	*/
1169	uint64_t cbRam;
1170	int rc = CFGMR3QueryU64(CFGMR3GetRoot(pVM), "RamSize", &cbRam);
1171	if (rc == VERR_CFGM_VALUE_NOT_FOUND)
1172	cbRam = pVM->pgm.s.cbRamSize = 0;
1173	else if (RT_SUCCESS(rc))
1174	{
1175	if (cbRam < PAGE_SIZE)
1176	cbRam = 0;
1177	cbRam = RT_ALIGN_64(cbRam, PAGE_SIZE);
1178	pVM->pgm.s.cbRamSize = (RTUINT)cbRam;
1179	}
1180	else
1181	{
1182	AssertMsgFailed(("Configuration error: Failed to query integer \"RamSize\", rc=%Rrc.\n", rc));
1183	return rc;
1184	}
1185
1186	/*
1187	* Register saved state data unit.
1188	*/
1189	rc = SSMR3RegisterInternal(pVM, "pgm", 1, PGM_SAVED_STATE_VERSION, (size_t)cbRam + sizeof(PGM),
1190	NULL, pgmR3Save, NULL,
1191	NULL, pgmR3Load, NULL);
1192	if (RT_FAILURE(rc))
1193	return rc;
1194
1195	/*
1196	* Initialize the PGM critical section and flush the phys TLBs
1197	*/
1198	rc = PDMR3CritSectInit(pVM, &pVM->pgm.s.CritSect, "PGM");
1199	AssertRCReturn(rc, rc);
1200
1201	PGMR3PhysChunkInvalidateTLB(pVM);
1202	PGMPhysInvalidatePageR3MapTLB(pVM);
1203	PGMPhysInvalidatePageR0MapTLB(pVM);
1204	PGMPhysInvalidatePageGCMapTLB(pVM);
1205
1206	/*
1207	* Trees
1208	*/
1209	rc = MMHyperAlloc(pVM, sizeof(PGMTREES), 0, MM_TAG_PGM, (void **)&pVM->pgm.s.pTreesR3);
1210	if (RT_SUCCESS(rc))
1211	{
1212	pVM->pgm.s.pTreesR0 = MMHyperR3ToR0(pVM, pVM->pgm.s.pTreesR3);
1213	pVM->pgm.s.pTreesRC = MMHyperR3ToRC(pVM, pVM->pgm.s.pTreesR3);
1214
1215	/*
1216	* Alocate the zero page.
1217	*/
1218	rc = MMHyperAlloc(pVM, PAGE_SIZE, PAGE_SIZE, MM_TAG_PGM, &pVM->pgm.s.pvZeroPgR3);
1219	}
1220	if (RT_SUCCESS(rc))
1221	{
1222	pVM->pgm.s.pvZeroPgGC = MMHyperR3ToRC(pVM, pVM->pgm.s.pvZeroPgR3);
1223	pVM->pgm.s.pvZeroPgR0 = MMHyperR3ToR0(pVM, pVM->pgm.s.pvZeroPgR3);
1224	AssertRelease(pVM->pgm.s.pvZeroPgR0 != NIL_RTHCPHYS);
1225	pVM->pgm.s.HCPhysZeroPg = MMR3HyperHCVirt2HCPhys(pVM, pVM->pgm.s.pvZeroPgR3);
1226	AssertRelease(pVM->pgm.s.HCPhysZeroPg != NIL_RTHCPHYS);
1227
1228	/*
1229	* Init the paging.
1230	*/
1231	rc = pgmR3InitPaging(pVM);
1232	}
1233	if (RT_SUCCESS(rc))
1234	{
1235	/*
1236	* Init the page pool.
1237	*/
1238	rc = pgmR3PoolInit(pVM);
1239	}
1240	if (RT_SUCCESS(rc))
1241	{
1242	/*
1243	* Info & statistics
1244	*/
1245	DBGFR3InfoRegisterInternal(pVM, "mode",
1246	"Shows the current paging mode. "
1247	"Recognizes 'all', 'guest', 'shadow' and 'host' as arguments, defaulting to 'all' if nothing's given.",
1248	pgmR3InfoMode);
1249	DBGFR3InfoRegisterInternal(pVM, "pgmcr3",
1250	"Dumps all the entries in the top level paging table. No arguments.",
1251	pgmR3InfoCr3);
1252	DBGFR3InfoRegisterInternal(pVM, "phys",
1253	"Dumps all the physical address ranges. No arguments.",
1254	pgmR3PhysInfo);
1255	DBGFR3InfoRegisterInternal(pVM, "handlers",
1256	"Dumps physical, virtual and hyper virtual handlers. "
1257	"Pass 'phys', 'virt', 'hyper' as argument if only one kind is wanted."
1258	"Add 'nost' if the statistics are unwanted, use together with 'all' or explicit selection.",
1259	pgmR3InfoHandlers);
1260	DBGFR3InfoRegisterInternal(pVM, "mappings",
1261	"Dumps guest mappings.",
1262	pgmR3MapInfo);
1263
1264	STAM_REL_REG(pVM, &pVM->pgm.s.cGuestModeChanges, STAMTYPE_COUNTER, "/PGM/cGuestModeChanges", STAMUNIT_OCCURENCES, "Number of guest mode changes.");
1265	#ifdef VBOX_WITH_STATISTICS
1266	pgmR3InitStats(pVM);
1267	#endif
1268	#ifdef VBOX_WITH_DEBUGGER
1269	/*
1270	* Debugger commands.
1271	*/
1272	static bool fRegisteredCmds = false;
1273	if (!fRegisteredCmds)
1274	{
1275	int rc = DBGCRegisterCommands(&g_aCmds[0], RT_ELEMENTS(g_aCmds));
1276	if (RT_SUCCESS(rc))
1277	fRegisteredCmds = true;
1278	}
1279	#endif
1280	return VINF_SUCCESS;
1281	}
1282
1283	/* Almost no cleanup necessary, MM frees all memory. */
1284	PDMR3CritSectDelete(&pVM->pgm.s.CritSect);
1285
1286	return rc;
1287	}
1288
1289
1290	/**
1291	* Initializes the per-VCPU PGM.
1292	*
1293	* @returns VBox status code.
1294	* @param pVM The VM to operate on.
1295	*/
1296	VMMR3DECL(int) PGMR3InitCPU(PVM pVM)
1297	{
1298	LogFlow(("PGMR3InitCPU\n"));
1299	return VINF_SUCCESS;
1300	}
1301
1302
1303	/**
1304	* Init paging.
1305	*
1306	* Since we need to check what mode the host is operating in before we can choose
1307	* the right paging functions for the host we have to delay this until R0 has
1308	* been initialized.
1309	*
1310	* @returns VBox status code.
1311	* @param pVM VM handle.
1312	*/
1313	static int pgmR3InitPaging(PVM pVM)
1314	{
1315	/*
1316	* Force a recalculation of modes and switcher so everyone gets notified.
1317	*/
1318	pVM->pgm.s.enmShadowMode = PGMMODE_INVALID;
1319	pVM->pgm.s.enmGuestMode = PGMMODE_INVALID;
1320	pVM->pgm.s.enmHostMode = SUPPAGINGMODE_INVALID;
1321
1322	/*
1323	* Allocate static mapping space for whatever the cr3 register
1324	* points to and in the case of PAE mode to the 4 PDs.
1325	*/
1326	int rc = MMR3HyperReserve(pVM, PAGE_SIZE * 5, "CR3 mapping", &pVM->pgm.s.GCPtrCR3Mapping);
1327	if (RT_FAILURE(rc))
1328	{
1329	AssertMsgFailed(("Failed to reserve two pages for cr mapping in HMA, rc=%Rrc\n", rc));
1330	return rc;
1331	}
1332	MMR3HyperReserve(pVM, PAGE_SIZE, "fence", NULL);
1333
1334	/*
1335	* Allocate pages for the three possible intermediate contexts
1336	* (AMD64, PAE and plain 32-Bit). We maintain all three contexts
1337	* for the sake of simplicity. The AMD64 uses the PAE for the
1338	* lower levels, making the total number of pages 11 (3 + 7 + 1).
1339	*
1340	* We assume that two page tables will be enought for the core code
1341	* mappings (HC virtual and identity).
1342	*/
1343	pVM->pgm.s.pInterPD = (PX86PD)MMR3PageAllocLow(pVM);
1344	pVM->pgm.s.apInterPTs[0] = (PX86PT)MMR3PageAllocLow(pVM);
1345	pVM->pgm.s.apInterPTs[1] = (PX86PT)MMR3PageAllocLow(pVM);
1346	pVM->pgm.s.apInterPaePTs[0] = (PX86PTPAE)MMR3PageAlloc(pVM);
1347	pVM->pgm.s.apInterPaePTs[1] = (PX86PTPAE)MMR3PageAlloc(pVM);
1348	pVM->pgm.s.apInterPaePDs[0] = (PX86PDPAE)MMR3PageAlloc(pVM);
1349	pVM->pgm.s.apInterPaePDs[1] = (PX86PDPAE)MMR3PageAlloc(pVM);
1350	pVM->pgm.s.apInterPaePDs[2] = (PX86PDPAE)MMR3PageAlloc(pVM);
1351	pVM->pgm.s.apInterPaePDs[3] = (PX86PDPAE)MMR3PageAlloc(pVM);
1352	pVM->pgm.s.pInterPaePDPT = (PX86PDPT)MMR3PageAllocLow(pVM);
1353	pVM->pgm.s.pInterPaePDPT64 = (PX86PDPT)MMR3PageAllocLow(pVM);
1354	pVM->pgm.s.pInterPaePML4 = (PX86PML4)MMR3PageAllocLow(pVM);
1355	if ( !pVM->pgm.s.pInterPD
1356	\|\| !pVM->pgm.s.apInterPTs[0]
1357	\|\| !pVM->pgm.s.apInterPTs[1]
1358	\|\| !pVM->pgm.s.apInterPaePTs[0]
1359	\|\| !pVM->pgm.s.apInterPaePTs[1]
1360	\|\| !pVM->pgm.s.apInterPaePDs[0]
1361	\|\| !pVM->pgm.s.apInterPaePDs[1]
1362	\|\| !pVM->pgm.s.apInterPaePDs[2]
1363	\|\| !pVM->pgm.s.apInterPaePDs[3]
1364	\|\| !pVM->pgm.s.pInterPaePDPT
1365	\|\| !pVM->pgm.s.pInterPaePDPT64
1366	\|\| !pVM->pgm.s.pInterPaePML4)
1367	{
1368	AssertMsgFailed(("Failed to allocate pages for the intermediate context!\n"));
1369	return VERR_NO_PAGE_MEMORY;
1370	}
1371
1372	pVM->pgm.s.HCPhysInterPD = MMPage2Phys(pVM, pVM->pgm.s.pInterPD);
1373	AssertRelease(pVM->pgm.s.HCPhysInterPD != NIL_RTHCPHYS && !(pVM->pgm.s.HCPhysInterPD & PAGE_OFFSET_MASK));
1374	pVM->pgm.s.HCPhysInterPaePDPT = MMPage2Phys(pVM, pVM->pgm.s.pInterPaePDPT);
1375	AssertRelease(pVM->pgm.s.HCPhysInterPaePDPT != NIL_RTHCPHYS && !(pVM->pgm.s.HCPhysInterPaePDPT & PAGE_OFFSET_MASK));
1376	pVM->pgm.s.HCPhysInterPaePML4 = MMPage2Phys(pVM, pVM->pgm.s.pInterPaePML4);
1377	AssertRelease(pVM->pgm.s.HCPhysInterPaePML4 != NIL_RTHCPHYS && !(pVM->pgm.s.HCPhysInterPaePML4 & PAGE_OFFSET_MASK));
1378
1379	/*
1380	* Initialize the pages, setting up the PML4 and PDPT for repetitive 4GB action.
1381	*/
1382	ASMMemZeroPage(pVM->pgm.s.pInterPD);
1383	ASMMemZeroPage(pVM->pgm.s.apInterPTs[0]);
1384	ASMMemZeroPage(pVM->pgm.s.apInterPTs[1]);
1385
1386	ASMMemZeroPage(pVM->pgm.s.apInterPaePTs[0]);
1387	ASMMemZeroPage(pVM->pgm.s.apInterPaePTs[1]);
1388
1389	ASMMemZeroPage(pVM->pgm.s.pInterPaePDPT);
1390	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.apInterPaePDs); i++)
1391	{
1392	ASMMemZeroPage(pVM->pgm.s.apInterPaePDs[i]);
1393	pVM->pgm.s.pInterPaePDPT->a[i].u = X86_PDPE_P \| PGM_PLXFLAGS_PERMANENT
1394	\| MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[i]);
1395	}
1396
1397	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.pInterPaePDPT64->a); i++)
1398	{
1399	const unsigned iPD = i % RT_ELEMENTS(pVM->pgm.s.apInterPaePDs);
1400	pVM->pgm.s.pInterPaePDPT64->a[i].u = X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_A \| PGM_PLXFLAGS_PERMANENT
1401	\| MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[iPD]);
1402	}
1403
1404	RTHCPHYS HCPhysInterPaePDPT64 = MMPage2Phys(pVM, pVM->pgm.s.pInterPaePDPT64);
1405	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.pInterPaePML4->a); i++)
1406	pVM->pgm.s.pInterPaePML4->a[i].u = X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_A \| PGM_PLXFLAGS_PERMANENT
1407	\| HCPhysInterPaePDPT64;
1408
1409	/*
1410	* Allocate pages for the three possible guest contexts (AMD64, PAE and plain 32-Bit).
1411	* We allocate pages for all three posibilities in order to simplify mappings and
1412	* avoid resource failure during mode switches. So, we need to cover all levels of the
1413	* of the first 4GB down to PD level.
1414	* As with the intermediate context, AMD64 uses the PAE PDPT and PDs.
1415	*/
1416	#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
1417	pVM->pgm.s.pShw32BitPdR3 = (PX86PD)MMR3PageAllocLow(pVM);
1418	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
1419	pVM->pgm.s.pShw32BitPdR0 = (uintptr_t)pVM->pgm.s.pShw32BitPdR3;
1420	# endif
1421	pVM->pgm.s.apShwPaePDsR3[0] = (PX86PDPAE)MMR3PageAlloc(pVM);
1422	pVM->pgm.s.apShwPaePDsR3[1] = (PX86PDPAE)MMR3PageAlloc(pVM);
1423	AssertRelease((uintptr_t)pVM->pgm.s.apShwPaePDsR3[0] + PAGE_SIZE == (uintptr_t)pVM->pgm.s.apShwPaePDsR3[1]);
1424	pVM->pgm.s.apShwPaePDsR3[2] = (PX86PDPAE)MMR3PageAlloc(pVM);
1425	AssertRelease((uintptr_t)pVM->pgm.s.apShwPaePDsR3[1] + PAGE_SIZE == (uintptr_t)pVM->pgm.s.apShwPaePDsR3[2]);
1426	pVM->pgm.s.apShwPaePDsR3[3] = (PX86PDPAE)MMR3PageAlloc(pVM);
1427	AssertRelease((uintptr_t)pVM->pgm.s.apShwPaePDsR3[2] + PAGE_SIZE == (uintptr_t)pVM->pgm.s.apShwPaePDsR3[3]);
1428	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
1429	pVM->pgm.s.apShwPaePDsR0[0] = (uintptr_t)pVM->pgm.s.apShwPaePDsR3[0];
1430	pVM->pgm.s.apShwPaePDsR0[1] = (uintptr_t)pVM->pgm.s.apShwPaePDsR3[1];
1431	pVM->pgm.s.apShwPaePDsR0[2] = (uintptr_t)pVM->pgm.s.apShwPaePDsR3[2];
1432	pVM->pgm.s.apShwPaePDsR0[3] = (uintptr_t)pVM->pgm.s.apShwPaePDsR3[3];
1433	# endif
1434	pVM->pgm.s.pShwPaePdptR3 = (PX86PDPT)MMR3PageAllocLow(pVM);
1435	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
1436	pVM->pgm.s.pShwPaePdptR0 = (uintptr_t)pVM->pgm.s.pShwPaePdptR3;
1437	# endif
1438	#endif /* VBOX_WITH_PGMPOOL_PAGING_ONLY */
1439	pVM->pgm.s.pShwNestedRootR3 = MMR3PageAllocLow(pVM);
1440	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
1441	pVM->pgm.s.pShwNestedRootR0 = (uintptr_t)pVM->pgm.s.pShwNestedRootR3;
1442	#endif
1443
1444	#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
1445	if (!pVM->pgm.s.pShwNestedRootR3)
1446	#else
1447	if ( !pVM->pgm.s.pShw32BitPdR3
1448	\|\| !pVM->pgm.s.apShwPaePDsR3[0]
1449	\|\| !pVM->pgm.s.apShwPaePDsR3[1]
1450	\|\| !pVM->pgm.s.apShwPaePDsR3[2]
1451	\|\| !pVM->pgm.s.apShwPaePDsR3[3]
1452	\|\| !pVM->pgm.s.pShwPaePdptR3
1453	\|\| !pVM->pgm.s.pShwNestedRootR3)
1454	#endif
1455	{
1456	AssertMsgFailed(("Failed to allocate pages for the intermediate context!\n"));
1457	return VERR_NO_PAGE_MEMORY;
1458	}
1459
1460	/* get physical addresses. */
1461	#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
1462	pVM->pgm.s.HCPhysShw32BitPD = MMPage2Phys(pVM, pVM->pgm.s.pShw32BitPdR3);
1463	Assert(MMPagePhys2Page(pVM, pVM->pgm.s.HCPhysShw32BitPD) == pVM->pgm.s.pShw32BitPdR3);
1464	pVM->pgm.s.aHCPhysPaePDs[0] = MMPage2Phys(pVM, pVM->pgm.s.apShwPaePDsR3[0]);
1465	pVM->pgm.s.aHCPhysPaePDs[1] = MMPage2Phys(pVM, pVM->pgm.s.apShwPaePDsR3[1]);
1466	pVM->pgm.s.aHCPhysPaePDs[2] = MMPage2Phys(pVM, pVM->pgm.s.apShwPaePDsR3[2]);
1467	pVM->pgm.s.aHCPhysPaePDs[3] = MMPage2Phys(pVM, pVM->pgm.s.apShwPaePDsR3[3]);
1468	pVM->pgm.s.HCPhysShwPaePdpt = MMPage2Phys(pVM, pVM->pgm.s.pShwPaePdptR3);
1469	#endif
1470	pVM->pgm.s.HCPhysShwNestedRoot = MMPage2Phys(pVM, pVM->pgm.s.pShwNestedRootR3);
1471
1472	/*
1473	* Initialize the pages, setting up the PML4 and PDPT for action below 4GB.
1474	*/
1475	#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
1476	ASMMemZero32(pVM->pgm.s.pShw32BitPdR3, PAGE_SIZE);
1477	ASMMemZero32(pVM->pgm.s.pShwPaePdptR3, PAGE_SIZE);
1478	#endif
1479	ASMMemZero32(pVM->pgm.s.pShwNestedRootR3, PAGE_SIZE);
1480	#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
1481	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.apShwPaePDsR3); i++)
1482	{
1483	ASMMemZero32(pVM->pgm.s.apShwPaePDsR3[i], PAGE_SIZE);
1484	pVM->pgm.s.pShwPaePdptR3->a[i].u = X86_PDPE_P \| PGM_PLXFLAGS_PERMANENT \| pVM->pgm.s.aHCPhysPaePDs[i];
1485	/* The flags will be corrected when entering and leaving long mode. */
1486	}
1487
1488	CPUMSetHyperCR3(pVM, (uint32_t)pVM->pgm.s.HCPhysShw32BitPD);
1489	#endif
1490
1491	/*
1492	* Initialize paging workers and mode from current host mode
1493	* and the guest running in real mode.
1494	*/
1495	pVM->pgm.s.enmHostMode = SUPGetPagingMode();
1496	switch (pVM->pgm.s.enmHostMode)
1497	{
1498	case SUPPAGINGMODE_32_BIT:
1499	case SUPPAGINGMODE_32_BIT_GLOBAL:
1500	case SUPPAGINGMODE_PAE:
1501	case SUPPAGINGMODE_PAE_GLOBAL:
1502	case SUPPAGINGMODE_PAE_NX:
1503	case SUPPAGINGMODE_PAE_GLOBAL_NX:
1504	break;
1505
1506	case SUPPAGINGMODE_AMD64:
1507	case SUPPAGINGMODE_AMD64_GLOBAL:
1508	case SUPPAGINGMODE_AMD64_NX:
1509	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
1510	#ifndef VBOX_WITH_HYBIRD_32BIT_KERNEL
1511	if (ARCH_BITS != 64)
1512	{
1513	AssertMsgFailed(("Host mode %d (64-bit) is not supported by non-64bit builds\n", pVM->pgm.s.enmHostMode));
1514	LogRel(("Host mode %d (64-bit) is not supported by non-64bit builds\n", pVM->pgm.s.enmHostMode));
1515	return VERR_PGM_UNSUPPORTED_HOST_PAGING_MODE;
1516	}
1517	#endif
1518	break;
1519	default:
1520	AssertMsgFailed(("Host mode %d is not supported\n", pVM->pgm.s.enmHostMode));
1521	return VERR_PGM_UNSUPPORTED_HOST_PAGING_MODE;
1522	}
1523	rc = pgmR3ModeDataInit(pVM, false /* don't resolve GC and R0 syms yet */);
1524	if (RT_SUCCESS(rc))
1525	rc = PGMR3ChangeMode(pVM, PGMMODE_REAL);
1526	if (RT_SUCCESS(rc))
1527	{
1528	LogFlow(("pgmR3InitPaging: returns successfully\n"));
1529	#if HC_ARCH_BITS == 64
1530	# ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
1531	LogRel(("Debug: HCPhysShw32BitPD=%RHp aHCPhysPaePDs={%RHp,%RHp,%RHp,%RHp} HCPhysShwPaePdpt=%RHp HCPhysShwPaePml4=%RHp\n",
1532	pVM->pgm.s.HCPhysShw32BitPD,
1533	pVM->pgm.s.aHCPhysPaePDs[0], pVM->pgm.s.aHCPhysPaePDs[1], pVM->pgm.s.aHCPhysPaePDs[2], pVM->pgm.s.aHCPhysPaePDs[3],
1534	pVM->pgm.s.HCPhysShwPaePdpt,
1535	pVM->pgm.s.HCPhysShwPaePml4));
1536	# endif
1537	LogRel(("Debug: HCPhysInterPD=%RHp HCPhysInterPaePDPT=%RHp HCPhysInterPaePML4=%RHp\n",
1538	pVM->pgm.s.HCPhysInterPD, pVM->pgm.s.HCPhysInterPaePDPT, pVM->pgm.s.HCPhysInterPaePML4));
1539	LogRel(("Debug: apInterPTs={%RHp,%RHp} apInterPaePTs={%RHp,%RHp} apInterPaePDs={%RHp,%RHp,%RHp,%RHp} pInterPaePDPT64=%RHp\n",
1540	MMPage2Phys(pVM, pVM->pgm.s.apInterPTs[0]), MMPage2Phys(pVM, pVM->pgm.s.apInterPTs[1]),
1541	MMPage2Phys(pVM, pVM->pgm.s.apInterPaePTs[0]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePTs[1]),
1542	MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[0]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[1]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[2]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[3]),
1543	MMPage2Phys(pVM, pVM->pgm.s.pInterPaePDPT64)));
1544	#endif
1545
1546	return VINF_SUCCESS;
1547	}
1548
1549	LogFlow(("pgmR3InitPaging: returns %Rrc\n", rc));
1550	return rc;
1551	}
1552
1553
1554	#ifdef VBOX_WITH_STATISTICS
1555	/**
1556	* Init statistics
1557	*/
1558	static void pgmR3InitStats(PVM pVM)
1559	{
1560	PPGM pPGM = &pVM->pgm.s;
1561	unsigned i;
1562
1563	/*
1564	* Note! The layout of this function matches the member layout exactly!
1565	*/
1566
1567	/* Common - misc variables */
1568	STAM_REG(pVM, &pPGM->cAllPages, STAMTYPE_U32, "/PGM/Page/cAllPages", STAMUNIT_OCCURENCES, "The total number of pages.");
1569	STAM_REG(pVM, &pPGM->cPrivatePages, STAMTYPE_U32, "/PGM/Page/cPrivatePages", STAMUNIT_OCCURENCES, "The number of private pages.");
1570	STAM_REG(pVM, &pPGM->cSharedPages, STAMTYPE_U32, "/PGM/Page/cSharedPages", STAMUNIT_OCCURENCES, "The number of shared pages.");
1571	STAM_REG(pVM, &pPGM->cZeroPages, STAMTYPE_U32, "/PGM/Page/cZeroPages", STAMUNIT_OCCURENCES, "The number of zero backed pages.");
1572	STAM_REG(pVM, &pPGM->ChunkR3Map.c, STAMTYPE_U32, "/PGM/ChunkR3Map/c", STAMUNIT_OCCURENCES, "Number of mapped chunks.");
1573	STAM_REG(pVM, &pPGM->ChunkR3Map.cMax, STAMTYPE_U32, "/PGM/ChunkR3Map/cMax", STAMUNIT_OCCURENCES, "Maximum number of mapped chunks.");
1574
1575	/* Common - stats */
1576	#ifdef PGMPOOL_WITH_GCPHYS_TRACKING
1577	STAM_REG(pVM, &pPGM->StatTrackVirgin, STAMTYPE_COUNTER, "/PGM/Track/Virgin", STAMUNIT_OCCURENCES, "The number of first time shadowings");
1578	STAM_REG(pVM, &pPGM->StatTrackAliased, STAMTYPE_COUNTER, "/PGM/Track/Aliased", STAMUNIT_OCCURENCES, "The number of times switching to cRef2, i.e. the page is being shadowed by two PTs.");
1579	STAM_REG(pVM, &pPGM->StatTrackAliasedMany, STAMTYPE_COUNTER, "/PGM/Track/AliasedMany", STAMUNIT_OCCURENCES, "The number of times we're tracking using cRef2.");
1580	STAM_REG(pVM, &pPGM->StatTrackAliasedLots, STAMTYPE_COUNTER, "/PGM/Track/AliasedLots", STAMUNIT_OCCURENCES, "The number of times we're hitting pages which has overflowed cRef2");
1581	STAM_REG(pVM, &pPGM->StatTrackOverflows, STAMTYPE_COUNTER, "/PGM/Track/Overflows", STAMUNIT_OCCURENCES, "The number of times the extent list grows to long.");
1582	STAM_REG(pVM, &pPGM->StatTrackDeref, STAMTYPE_PROFILE, "/PGM/Track/Deref", STAMUNIT_OCCURENCES, "Profiling of SyncPageWorkerTrackDeref (expensive).");
1583	#endif
1584	for (i = 0; i < RT_ELEMENTS(pPGM->StatSyncPtPD); i++)
1585	STAMR3RegisterF(pVM, &pPGM->StatSyncPtPD[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
1586	"The number of SyncPT per PD n.", "/PGM/PDSyncPT/%04X", i);
1587	for (i = 0; i < RT_ELEMENTS(pPGM->StatSyncPagePD); i++)
1588	STAMR3RegisterF(pVM, &pPGM->StatSyncPagePD[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
1589	"The number of SyncPage per PD n.", "/PGM/PDSyncPage/%04X", i);
1590
1591	/* R3 only: */
1592	STAM_REG(pVM, &pPGM->StatR3DetectedConflicts, STAMTYPE_COUNTER, "/PGM/R3/DetectedConflicts", STAMUNIT_OCCURENCES, "The number of times PGMR3CheckMappingConflicts() detected a conflict.");
1593	STAM_REG(pVM, &pPGM->StatR3ResolveConflict, STAMTYPE_PROFILE, "/PGM/R3/ResolveConflict", STAMUNIT_TICKS_PER_CALL, "pgmR3SyncPTResolveConflict() profiling (includes the entire relocation).");
1594	STAM_REG(pVM, &pPGM->StatR3GuestPDWrite, STAMTYPE_COUNTER, "/PGM/R3/PDWrite", STAMUNIT_OCCURENCES, "The total number of times pgmHCGuestPDWriteHandler() was called.");
1595	STAM_REG(pVM, &pPGM->StatR3GuestPDWriteConflict, STAMTYPE_COUNTER, "/PGM/R3/PDWriteConflict", STAMUNIT_OCCURENCES, "The number of times pgmHCGuestPDWriteHandler() detected a conflict.");
1596	STAM_REG(pVM, &pPGM->StatR3DynRamTotal, STAMTYPE_COUNTER, "/PGM/DynAlloc/TotalAlloc", STAMUNIT_MEGABYTES, "Allocated MBs of guest ram.");
1597	STAM_REG(pVM, &pPGM->StatR3DynRamGrow, STAMTYPE_COUNTER, "/PGM/DynAlloc/Grow", STAMUNIT_OCCURENCES, "Nr of pgmr3PhysGrowRange calls.");
1598
1599	/* R0 only: */
1600	STAM_REG(pVM, &pPGM->StatR0DynMapMigrateInvlPg, STAMTYPE_COUNTER, "/PGM/R0/DynMapMigrateInvlPg", STAMUNIT_OCCURENCES, "invlpg count in PGMDynMapMigrateAutoSet.");
1601	STAM_REG(pVM, &pPGM->StatR0DynMapGCPageInl, STAMTYPE_PROFILE, "/PGM/R0/DynMapPageGCPageInl", STAMUNIT_TICKS_PER_CALL, "Calls to pgmR0DynMapGCPageInlined.");
1602	STAM_REG(pVM, &pPGM->StatR0DynMapGCPageInlHits, STAMTYPE_COUNTER, "/PGM/R0/DynMapPageGCPageInl/Hits", STAMUNIT_OCCURENCES, "Hash table lookup hits.");
1603	STAM_REG(pVM, &pPGM->StatR0DynMapGCPageInlMisses, STAMTYPE_COUNTER, "/PGM/R0/DynMapPageGCPageInl/Misses", STAMUNIT_OCCURENCES, "Misses that falls back to code common with PGMDynMapHCPage.");
1604	STAM_REG(pVM, &pPGM->StatR0DynMapGCPageInlRamHits, STAMTYPE_COUNTER, "/PGM/R0/DynMapPageGCPageInl/RamHits", STAMUNIT_OCCURENCES, "1st ram range hits.");
1605	STAM_REG(pVM, &pPGM->StatR0DynMapGCPageInlRamMisses, STAMTYPE_COUNTER, "/PGM/R0/DynMapPageGCPageInl/RamMisses", STAMUNIT_OCCURENCES, "1st ram range misses, takes slow path.");
1606	STAM_REG(pVM, &pPGM->StatR0DynMapHCPageInl, STAMTYPE_PROFILE, "/PGM/R0/DynMapPageHCPageInl", STAMUNIT_TICKS_PER_CALL, "Calls to pgmR0DynMapHCPageInlined.");
1607	STAM_REG(pVM, &pPGM->StatR0DynMapHCPageInlHits, STAMTYPE_COUNTER, "/PGM/R0/DynMapPageHCPageInl/Hits", STAMUNIT_OCCURENCES, "Hash table lookup hits.");
1608	STAM_REG(pVM, &pPGM->StatR0DynMapHCPageInlMisses, STAMTYPE_COUNTER, "/PGM/R0/DynMapPageHCPageInl/Misses", STAMUNIT_OCCURENCES, "Misses that falls back to code common with PGMDynMapHCPage.");
1609	STAM_REG(pVM, &pPGM->StatR0DynMapPage, STAMTYPE_COUNTER, "/PGM/R0/DynMapPage", STAMUNIT_OCCURENCES, "Calls to pgmR0DynMapPage");
1610	STAM_REG(pVM, &pPGM->StatR0DynMapSetOptimize, STAMTYPE_COUNTER, "/PGM/R0/DynMapPage/SetOptimize", STAMUNIT_OCCURENCES, "Calls to pgmDynMapOptimizeAutoSet.");
1611	STAM_REG(pVM, &pPGM->StatR0DynMapSetSearchHits, STAMTYPE_COUNTER, "/PGM/R0/DynMapPage/SetSearchHits", STAMUNIT_OCCURENCES, "Set search hits.");
1612	STAM_REG(pVM, &pPGM->StatR0DynMapSetSearchMisses, STAMTYPE_COUNTER, "/PGM/R0/DynMapPage/SetSearchMisses", STAMUNIT_OCCURENCES, "Set search misses.");
1613	STAM_REG(pVM, &pPGM->StatR0DynMapHCPage, STAMTYPE_PROFILE, "/PGM/R0/DynMapPage/HCPage", STAMUNIT_TICKS_PER_CALL, "Calls to PGMDynMapHCPage (ring-0).");
1614	STAM_REG(pVM, &pPGM->StatR0DynMapPageHits0, STAMTYPE_COUNTER, "/PGM/R0/DynMapPage/Hits0", STAMUNIT_OCCURENCES, "Hits at iPage+0");
1615	STAM_REG(pVM, &pPGM->StatR0DynMapPageHits1, STAMTYPE_COUNTER, "/PGM/R0/DynMapPage/Hits1", STAMUNIT_OCCURENCES, "Hits at iPage+1");
1616	STAM_REG(pVM, &pPGM->StatR0DynMapPageHits2, STAMTYPE_COUNTER, "/PGM/R0/DynMapPage/Hits2", STAMUNIT_OCCURENCES, "Hits at iPage+2");
1617	STAM_REG(pVM, &pPGM->StatR0DynMapPageInvlPg, STAMTYPE_COUNTER, "/PGM/R0/DynMapPage/InvlPg", STAMUNIT_OCCURENCES, "invlpg count in pgmR0DynMapPageSlow.");
1618	STAM_REG(pVM, &pPGM->StatR0DynMapPageSlow, STAMTYPE_COUNTER, "/PGM/R0/DynMapPage/Slow", STAMUNIT_OCCURENCES, "Calls to pgmR0DynMapPageSlow - subtract this from pgmR0DynMapPage to get 1st level hits.");
1619	STAM_REG(pVM, &pPGM->StatR0DynMapPageSlowLoopHits, STAMTYPE_COUNTER, "/PGM/R0/DynMapPage/SlowLoopHits" , STAMUNIT_OCCURENCES, "Hits in the loop path.");
1620	STAM_REG(pVM, &pPGM->StatR0DynMapPageSlowLoopMisses, STAMTYPE_COUNTER, "/PGM/R0/DynMapPage/SlowLoopMisses", STAMUNIT_OCCURENCES, "Misses in the loop path. NonLoopMisses = Slow - SlowLoopHit - SlowLoopMisses");
1621	//STAM_REG(pVM, &pPGM->StatR0DynMapPageSlowLostHits, STAMTYPE_COUNTER, "/PGM/R0/DynMapPage/SlowLostHits", STAMUNIT_OCCURENCES, "Lost hits.");
1622
1623	/* GC only: */
1624	STAM_REG(pVM, &pPGM->StatRCDynMapCacheHits, STAMTYPE_COUNTER, "/PGM/RC/DynMapCache/Hits" , STAMUNIT_OCCURENCES, "Number of dynamic page mapping cache hits.");
1625	STAM_REG(pVM, &pPGM->StatRCDynMapCacheMisses, STAMTYPE_COUNTER, "/PGM/RC/DynMapCache/Misses" , STAMUNIT_OCCURENCES, "Number of dynamic page mapping cache misses.");
1626	STAM_REG(pVM, &pPGM->StatRCInvlPgConflict, STAMTYPE_COUNTER, "/PGM/RC/InvlPgConflict", STAMUNIT_OCCURENCES, "Number of times PGMInvalidatePage() detected a mapping conflict.");
1627	STAM_REG(pVM, &pPGM->StatRCInvlPgSyncMonCR3, STAMTYPE_COUNTER, "/PGM/RC/InvlPgSyncMonitorCR3", STAMUNIT_OCCURENCES, "Number of times PGMInvalidatePage() ran into PGM_SYNC_MONITOR_CR3.");
1628
1629	/* RZ only: */
1630	STAM_REG(pVM, &pPGM->StatRZTrap0e, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMTrap0eHandler() body.");
1631	STAM_REG(pVM, &pPGM->StatRZTrap0eTimeCheckPageFault, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time/CheckPageFault", STAMUNIT_TICKS_PER_CALL, "Profiling of checking for dirty/access emulation faults.");
1632	STAM_REG(pVM, &pPGM->StatRZTrap0eTimeSyncPT, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time/SyncPT", STAMUNIT_TICKS_PER_CALL, "Profiling of lazy page table syncing.");
1633	STAM_REG(pVM, &pPGM->StatRZTrap0eTimeMapping, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time/Mapping", STAMUNIT_TICKS_PER_CALL, "Profiling of checking virtual mappings.");
1634	STAM_REG(pVM, &pPGM->StatRZTrap0eTimeOutOfSync, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time/OutOfSync", STAMUNIT_TICKS_PER_CALL, "Profiling of out of sync page handling.");
1635	STAM_REG(pVM, &pPGM->StatRZTrap0eTimeHandlers, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time/Handlers", STAMUNIT_TICKS_PER_CALL, "Profiling of checking handlers.");
1636	STAM_REG(pVM, &pPGM->StatRZTrap0eTime2CSAM, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time2/CSAM", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is CSAM.");
1637	STAM_REG(pVM, &pPGM->StatRZTrap0eTime2DirtyAndAccessed, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time2/DirtyAndAccessedBits", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is dirty and/or accessed bit emulation.");
1638	STAM_REG(pVM, &pPGM->StatRZTrap0eTime2GuestTrap, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time2/GuestTrap", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is a guest trap.");
1639	STAM_REG(pVM, &pPGM->StatRZTrap0eTime2HndPhys, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time2/HandlerPhysical", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is a physical handler.");
1640	STAM_REG(pVM, &pPGM->StatRZTrap0eTime2HndVirt, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time2/HandlerVirtual", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is a virtual handler.");
1641	STAM_REG(pVM, &pPGM->StatRZTrap0eTime2HndUnhandled, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time2/HandlerUnhandled", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is access outside the monitored areas of a monitored page.");
1642	STAM_REG(pVM, &pPGM->StatRZTrap0eTime2Misc, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time2/Misc", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is not known.");
1643	STAM_REG(pVM, &pPGM->StatRZTrap0eTime2OutOfSync, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time2/OutOfSync", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is an out-of-sync page.");
1644	STAM_REG(pVM, &pPGM->StatRZTrap0eTime2OutOfSyncHndPhys, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time2/OutOfSyncHndPhys", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is an out-of-sync physical handler page.");
1645	STAM_REG(pVM, &pPGM->StatRZTrap0eTime2OutOfSyncHndVirt, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time2/OutOfSyncHndVirt", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is an out-of-sync virtual handler page.");
1646	STAM_REG(pVM, &pPGM->StatRZTrap0eTime2OutOfSyncHndObs, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time2/OutOfSyncObsHnd", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is an obsolete handler page.");
1647	STAM_REG(pVM, &pPGM->StatRZTrap0eTime2SyncPT, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time2/SyncPT", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is lazy syncing of a PT.");
1648	STAM_REG(pVM, &pPGM->StatRZTrap0eConflicts, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Conflicts", STAMUNIT_OCCURENCES, "The number of times #PF was caused by an undetected conflict.");
1649	STAM_REG(pVM, &pPGM->StatRZTrap0eHandlersMapping, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Handlers/Mapping", STAMUNIT_OCCURENCES, "Number of traps due to access handlers in mappings.");
1650	STAM_REG(pVM, &pPGM->StatRZTrap0eHandlersOutOfSync, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Handlers/OutOfSync", STAMUNIT_OCCURENCES, "Number of traps due to out-of-sync handled pages.");
1651	STAM_REG(pVM, &pPGM->StatRZTrap0eHandlersPhysical, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Handlers/Physical", STAMUNIT_OCCURENCES, "Number of traps due to physical access handlers.");
1652	STAM_REG(pVM, &pPGM->StatRZTrap0eHandlersVirtual, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Handlers/Virtual", STAMUNIT_OCCURENCES, "Number of traps due to virtual access handlers.");
1653	STAM_REG(pVM, &pPGM->StatRZTrap0eHandlersVirtualByPhys, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Handlers/VirtualByPhys", STAMUNIT_OCCURENCES, "Number of traps due to virtual access handlers by physical address.");
1654	STAM_REG(pVM, &pPGM->StatRZTrap0eHandlersVirtualUnmarked,STAMTYPE_COUNTER,"/PGM/RZ/Trap0e/Handlers/VirtualUnmarked",STAMUNIT_OCCURENCES, "Number of traps due to virtual access handlers by virtual address (without proper physical flags).");
1655	STAM_REG(pVM, &pPGM->StatRZTrap0eHandlersUnhandled, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Handlers/Unhandled", STAMUNIT_OCCURENCES, "Number of traps due to access outside range of monitored page(s).");
1656	STAM_REG(pVM, &pPGM->StatRZTrap0eHandlersInvalid, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Handlers/Invalid", STAMUNIT_OCCURENCES, "Number of traps due to access to invalid physical memory.");
1657	STAM_REG(pVM, &pPGM->StatRZTrap0eUSNotPresentRead, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Err/User/NPRead", STAMUNIT_OCCURENCES, "Number of user mode not present read page faults.");
1658	STAM_REG(pVM, &pPGM->StatRZTrap0eUSNotPresentWrite, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Err/User/NPWrite", STAMUNIT_OCCURENCES, "Number of user mode not present write page faults.");
1659	STAM_REG(pVM, &pPGM->StatRZTrap0eUSWrite, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Err/User/Write", STAMUNIT_OCCURENCES, "Number of user mode write page faults.");
1660	STAM_REG(pVM, &pPGM->StatRZTrap0eUSReserved, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Err/User/Reserved", STAMUNIT_OCCURENCES, "Number of user mode reserved bit page faults.");
1661	STAM_REG(pVM, &pPGM->StatRZTrap0eUSNXE, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Err/User/NXE", STAMUNIT_OCCURENCES, "Number of user mode NXE page faults.");
1662	STAM_REG(pVM, &pPGM->StatRZTrap0eUSRead, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Err/User/Read", STAMUNIT_OCCURENCES, "Number of user mode read page faults.");
1663	STAM_REG(pVM, &pPGM->StatRZTrap0eSVNotPresentRead, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Err/Supervisor/NPRead", STAMUNIT_OCCURENCES, "Number of supervisor mode not present read page faults.");
1664	STAM_REG(pVM, &pPGM->StatRZTrap0eSVNotPresentWrite, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Err/Supervisor/NPWrite", STAMUNIT_OCCURENCES, "Number of supervisor mode not present write page faults.");
1665	STAM_REG(pVM, &pPGM->StatRZTrap0eSVWrite, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Err/Supervisor/Write", STAMUNIT_OCCURENCES, "Number of supervisor mode write page faults.");
1666	STAM_REG(pVM, &pPGM->StatRZTrap0eSVReserved, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Err/Supervisor/Reserved", STAMUNIT_OCCURENCES, "Number of supervisor mode reserved bit page faults.");
1667	STAM_REG(pVM, &pPGM->StatRZTrap0eSNXE, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Err/Supervisor/NXE", STAMUNIT_OCCURENCES, "Number of supervisor mode NXE page faults.");
1668	STAM_REG(pVM, &pPGM->StatRZTrap0eGuestPF, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/GuestPF", STAMUNIT_OCCURENCES, "Number of real guest page faults.");
1669	STAM_REG(pVM, &pPGM->StatRZTrap0eGuestPFUnh, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/GuestPF/Unhandled", STAMUNIT_OCCURENCES, "Number of real guest page faults from the 'unhandled' case.");
1670	STAM_REG(pVM, &pPGM->StatRZTrap0eGuestPFMapping, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/GuestPF/InMapping", STAMUNIT_OCCURENCES, "Number of real guest page faults in a mapping.");
1671	STAM_REG(pVM, &pPGM->StatRZTrap0eWPEmulInRZ, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/WP/InRZ", STAMUNIT_OCCURENCES, "Number of guest page faults due to X86_CR0_WP emulation.");
1672	STAM_REG(pVM, &pPGM->StatRZTrap0eWPEmulToR3, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/WP/ToR3", STAMUNIT_OCCURENCES, "Number of guest page faults due to X86_CR0_WP emulation (forward to R3 for emulation).");
1673	for (i = 0; i < RT_ELEMENTS(pPGM->StatRZTrap0ePD); i++)
1674	STAMR3RegisterF(pVM, &pPGM->StatRZTrap0ePD[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
1675	"The number of traps in page directory n.", "/PGM/RZ/Trap0e/PD/%04X", i);
1676	STAM_REG(pVM, &pPGM->StatRZGuestCR3WriteHandled, STAMTYPE_COUNTER, "/PGM/RZ/CR3WriteHandled", STAMUNIT_OCCURENCES, "The number of times the Guest CR3 change was successfully handled.");
1677	STAM_REG(pVM, &pPGM->StatRZGuestCR3WriteUnhandled, STAMTYPE_COUNTER, "/PGM/RZ/CR3WriteUnhandled", STAMUNIT_OCCURENCES, "The number of times the Guest CR3 change was passed back to the recompiler.");
1678	STAM_REG(pVM, &pPGM->StatRZGuestCR3WriteConflict, STAMTYPE_COUNTER, "/PGM/RZ/CR3WriteConflict", STAMUNIT_OCCURENCES, "The number of times the Guest CR3 monitoring detected a conflict.");
1679	STAM_REG(pVM, &pPGM->StatRZGuestROMWriteHandled, STAMTYPE_COUNTER, "/PGM/RZ/ROMWriteHandled", STAMUNIT_OCCURENCES, "The number of times the Guest ROM change was successfully handled.");
1680	STAM_REG(pVM, &pPGM->StatRZGuestROMWriteUnhandled, STAMTYPE_COUNTER, "/PGM/RZ/ROMWriteUnhandled", STAMUNIT_OCCURENCES, "The number of times the Guest ROM change was passed back to the recompiler.");
1681
1682	/* HC only: */
1683
1684	/* RZ & R3: */
1685	STAM_REG(pVM, &pPGM->StatRZSyncCR3, STAMTYPE_PROFILE, "/PGM/RZ/SyncCR3", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMSyncCR3() body.");
1686	STAM_REG(pVM, &pPGM->StatRZSyncCR3Handlers, STAMTYPE_PROFILE, "/PGM/RZ/SyncCR3/Handlers", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMSyncCR3() update handler section.");
1687	STAM_REG(pVM, &pPGM->StatRZSyncCR3HandlerVirtualUpdate, STAMTYPE_PROFILE, "/PGM/RZ/SyncCR3/Handlers/VirtualUpdate", STAMUNIT_TICKS_PER_CALL, "Profiling of the virtual handler updates.");
1688	STAM_REG(pVM, &pPGM->StatRZSyncCR3HandlerVirtualReset, STAMTYPE_PROFILE, "/PGM/RZ/SyncCR3/Handlers/VirtualReset", STAMUNIT_TICKS_PER_CALL, "Profiling of the virtual handler resets.");
1689	STAM_REG(pVM, &pPGM->StatRZSyncCR3Global, STAMTYPE_COUNTER, "/PGM/RZ/SyncCR3/Global", STAMUNIT_OCCURENCES, "The number of global CR3 syncs.");
1690	STAM_REG(pVM, &pPGM->StatRZSyncCR3NotGlobal, STAMTYPE_COUNTER, "/PGM/RZ/SyncCR3/NotGlobal", STAMUNIT_OCCURENCES, "The number of non-global CR3 syncs.");
1691	STAM_REG(pVM, &pPGM->StatRZSyncCR3DstCacheHit, STAMTYPE_COUNTER, "/PGM/RZ/SyncCR3/DstChacheHit", STAMUNIT_OCCURENCES, "The number of times we got some kind of a cache hit.");
1692	STAM_REG(pVM, &pPGM->StatRZSyncCR3DstFreed, STAMTYPE_COUNTER, "/PGM/RZ/SyncCR3/DstFreed", STAMUNIT_OCCURENCES, "The number of times we've had to free a shadow entry.");
1693	STAM_REG(pVM, &pPGM->StatRZSyncCR3DstFreedSrcNP, STAMTYPE_COUNTER, "/PGM/RZ/SyncCR3/DstFreedSrcNP", STAMUNIT_OCCURENCES, "The number of times we've had to free a shadow entry for which the source entry was not present.");
1694	STAM_REG(pVM, &pPGM->StatRZSyncCR3DstNotPresent, STAMTYPE_COUNTER, "/PGM/RZ/SyncCR3/DstNotPresent", STAMUNIT_OCCURENCES, "The number of times we've encountered a not present shadow entry for a present guest entry.");
1695	STAM_REG(pVM, &pPGM->StatRZSyncCR3DstSkippedGlobalPD, STAMTYPE_COUNTER, "/PGM/RZ/SyncCR3/DstSkippedGlobalPD", STAMUNIT_OCCURENCES, "The number of times a global page directory wasn't flushed.");
1696	STAM_REG(pVM, &pPGM->StatRZSyncCR3DstSkippedGlobalPT, STAMTYPE_COUNTER, "/PGM/RZ/SyncCR3/DstSkippedGlobalPT", STAMUNIT_OCCURENCES, "The number of times a page table with only global entries wasn't flushed.");
1697	STAM_REG(pVM, &pPGM->StatRZSyncPT, STAMTYPE_PROFILE, "/PGM/RZ/SyncPT", STAMUNIT_TICKS_PER_CALL, "Profiling of the pfnSyncPT() body.");
1698	STAM_REG(pVM, &pPGM->StatRZSyncPTFailed, STAMTYPE_COUNTER, "/PGM/RZ/SyncPT/Failed", STAMUNIT_OCCURENCES, "The number of times pfnSyncPT() failed.");
1699	STAM_REG(pVM, &pPGM->StatRZSyncPT4K, STAMTYPE_COUNTER, "/PGM/RZ/SyncPT/4K", STAMUNIT_OCCURENCES, "Nr of 4K PT syncs");
1700	STAM_REG(pVM, &pPGM->StatRZSyncPT4M, STAMTYPE_COUNTER, "/PGM/RZ/SyncPT/4M", STAMUNIT_OCCURENCES, "Nr of 4M PT syncs");
1701	STAM_REG(pVM, &pPGM->StatRZSyncPagePDNAs, STAMTYPE_COUNTER, "/PGM/RZ/SyncPagePDNAs", STAMUNIT_OCCURENCES, "The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit.");
1702	STAM_REG(pVM, &pPGM->StatRZSyncPagePDOutOfSync, STAMTYPE_COUNTER, "/PGM/RZ/SyncPagePDOutOfSync", STAMUNIT_OCCURENCES, "The number of time we've encountered an out-of-sync PD in SyncPage.");
1703	STAM_REG(pVM, &pPGM->StatRZAccessedPage, STAMTYPE_COUNTER, "/PGM/RZ/AccessedPage", STAMUNIT_OCCURENCES, "The number of pages marked not present for accessed bit emulation.");
1704	STAM_REG(pVM, &pPGM->StatRZDirtyBitTracking, STAMTYPE_PROFILE, "/PGM/RZ/DirtyPage", STAMUNIT_TICKS_PER_CALL, "Profiling the dirty bit tracking in CheckPageFault().");
1705	STAM_REG(pVM, &pPGM->StatRZDirtyPage, STAMTYPE_COUNTER, "/PGM/RZ/DirtyPage/Mark", STAMUNIT_OCCURENCES, "The number of pages marked read-only for dirty bit tracking.");
1706	STAM_REG(pVM, &pPGM->StatRZDirtyPageBig, STAMTYPE_COUNTER, "/PGM/RZ/DirtyPage/MarkBig", STAMUNIT_OCCURENCES, "The number of 4MB pages marked read-only for dirty bit tracking.");
1707	STAM_REG(pVM, &pPGM->StatRZDirtyPageSkipped, STAMTYPE_COUNTER, "/PGM/RZ/DirtyPage/Skipped", STAMUNIT_OCCURENCES, "The number of pages already dirty or readonly.");
1708	STAM_REG(pVM, &pPGM->StatRZDirtyPageTrap, STAMTYPE_COUNTER, "/PGM/RZ/DirtyPage/Trap", STAMUNIT_OCCURENCES, "The number of traps generated for dirty bit tracking.");
1709	STAM_REG(pVM, &pPGM->StatRZDirtiedPage, STAMTYPE_COUNTER, "/PGM/RZ/DirtyPage/SetDirty", STAMUNIT_OCCURENCES, "The number of pages marked dirty because of write accesses.");
1710	STAM_REG(pVM, &pPGM->StatRZDirtyTrackRealPF, STAMTYPE_COUNTER, "/PGM/RZ/DirtyPage/RealPF", STAMUNIT_OCCURENCES, "The number of real pages faults during dirty bit tracking.");
1711	STAM_REG(pVM, &pPGM->StatRZPageAlreadyDirty, STAMTYPE_COUNTER, "/PGM/RZ/DirtyPage/AlreadySet", STAMUNIT_OCCURENCES, "The number of pages already marked dirty because of write accesses.");
1712	STAM_REG(pVM, &pPGM->StatRZInvalidatePage, STAMTYPE_PROFILE, "/PGM/RZ/InvalidatePage", STAMUNIT_TICKS_PER_CALL, "PGMInvalidatePage() profiling.");
1713	STAM_REG(pVM, &pPGM->StatRZInvalidatePage4KBPages, STAMTYPE_COUNTER, "/PGM/RZ/InvalidatePage/4KBPages", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was called for a 4KB page.");
1714	STAM_REG(pVM, &pPGM->StatRZInvalidatePage4MBPages, STAMTYPE_COUNTER, "/PGM/RZ/InvalidatePage/4MBPages", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was called for a 4MB page.");
1715	STAM_REG(pVM, &pPGM->StatRZInvalidatePage4MBPagesSkip, STAMTYPE_COUNTER, "/PGM/RZ/InvalidatePage/4MBPagesSkip",STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() skipped a 4MB page.");
1716	STAM_REG(pVM, &pPGM->StatRZInvalidatePagePDMappings, STAMTYPE_COUNTER, "/PGM/RZ/InvalidatePage/PDMappings", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict).");
1717	STAM_REG(pVM, &pPGM->StatRZInvalidatePagePDNAs, STAMTYPE_COUNTER, "/PGM/RZ/InvalidatePage/PDNAs", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was called for a not accessed page directory.");
1718	STAM_REG(pVM, &pPGM->StatRZInvalidatePagePDNPs, STAMTYPE_COUNTER, "/PGM/RZ/InvalidatePage/PDNPs", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was called for a not present page directory.");
1719	STAM_REG(pVM, &pPGM->StatRZInvalidatePagePDOutOfSync, STAMTYPE_COUNTER, "/PGM/RZ/InvalidatePage/PDOutOfSync", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was called for an out of sync page directory.");
1720	STAM_REG(pVM, &pPGM->StatRZInvalidatePageSkipped, STAMTYPE_COUNTER, "/PGM/RZ/InvalidatePage/Skipped", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3.");
1721	STAM_REG(pVM, &pPGM->StatRZVirtHandlerSearchByPhys, STAMTYPE_PROFILE, "/PGM/RZ/VirtHandlerSearchByPhys", STAMUNIT_TICKS_PER_CALL, "Profiling of pgmHandlerVirtualFindByPhysAddr.");
1722	STAM_REG(pVM, &pPGM->StatRZPhysHandlerReset, STAMTYPE_COUNTER, "/PGM/RZ/PhysHandlerReset", STAMUNIT_OCCURENCES, "The number of times PGMHandlerPhysicalReset is called.");
1723	STAM_REG(pVM, &pPGM->StatRZPageOutOfSyncSupervisor, STAMTYPE_COUNTER, "/PGM/RZ/OutOfSync/SuperVisor", STAMUNIT_OCCURENCES, "Number of traps due to pages out of sync and times VerifyAccessSyncPage calls SyncPage.");
1724	STAM_REG(pVM, &pPGM->StatRZPageOutOfSyncUser, STAMTYPE_COUNTER, "/PGM/RZ/OutOfSync/User", STAMUNIT_OCCURENCES, "Number of traps due to pages out of sync and times VerifyAccessSyncPage calls SyncPage.");
1725	STAM_REG(pVM, &pPGM->StatRZPrefetch, STAMTYPE_PROFILE, "/PGM/RZ/Prefetch", STAMUNIT_TICKS_PER_CALL, "PGMPrefetchPage profiling.");
1726	STAM_REG(pVM, &pPGM->StatRZChunkR3MapTlbHits, STAMTYPE_COUNTER, "/PGM/ChunkR3Map/TlbHitsRZ", STAMUNIT_OCCURENCES, "TLB hits.");
1727	STAM_REG(pVM, &pPGM->StatRZChunkR3MapTlbMisses, STAMTYPE_COUNTER, "/PGM/ChunkR3Map/TlbMissesRZ", STAMUNIT_OCCURENCES, "TLB misses.");
1728	STAM_REG(pVM, &pPGM->StatRZPageMapTlbHits, STAMTYPE_COUNTER, "/PGM/RZ/Page/MapTlbHits", STAMUNIT_OCCURENCES, "TLB hits.");
1729	STAM_REG(pVM, &pPGM->StatRZPageMapTlbMisses, STAMTYPE_COUNTER, "/PGM/RZ/Page/MapTlbMisses", STAMUNIT_OCCURENCES, "TLB misses.");
1730	STAM_REG(pVM, &pPGM->StatRZPageReplaceShared, STAMTYPE_COUNTER, "/PGM/RZ/Page/ReplacedShared", STAMUNIT_OCCURENCES, "Times a shared page was replaced.");
1731	STAM_REG(pVM, &pPGM->StatRZPageReplaceZero, STAMTYPE_COUNTER, "/PGM/RZ/Page/ReplacedZero", STAMUNIT_OCCURENCES, "Times the zero page was replaced.");
1732	/// @todo STAM_REG(pVM, &pPGM->StatRZPageHandyAllocs, STAMTYPE_COUNTER, "/PGM/RZ/Page/HandyAllocs", STAMUNIT_OCCURENCES, "Number of times we've allocated more handy pages.");
1733	STAM_REG(pVM, &pPGM->StatRZFlushTLB, STAMTYPE_PROFILE, "/PGM/RZ/FlushTLB", STAMUNIT_OCCURENCES, "Profiling of the PGMFlushTLB() body.");
1734	STAM_REG(pVM, &pPGM->StatRZFlushTLBNewCR3, STAMTYPE_COUNTER, "/PGM/RZ/FlushTLB/NewCR3", STAMUNIT_OCCURENCES, "The number of times PGMFlushTLB was called with a new CR3, non-global. (switch)");
1735	STAM_REG(pVM, &pPGM->StatRZFlushTLBNewCR3Global, STAMTYPE_COUNTER, "/PGM/RZ/FlushTLB/NewCR3Global", STAMUNIT_OCCURENCES, "The number of times PGMFlushTLB was called with a new CR3, global. (switch)");
1736	STAM_REG(pVM, &pPGM->StatRZFlushTLBSameCR3, STAMTYPE_COUNTER, "/PGM/RZ/FlushTLB/SameCR3", STAMUNIT_OCCURENCES, "The number of times PGMFlushTLB was called with the same CR3, non-global. (flush)");
1737	STAM_REG(pVM, &pPGM->StatRZFlushTLBSameCR3Global, STAMTYPE_COUNTER, "/PGM/RZ/FlushTLB/SameCR3Global", STAMUNIT_OCCURENCES, "The number of times PGMFlushTLB was called with the same CR3, global. (flush)");
1738	STAM_REG(pVM, &pPGM->StatRZGstModifyPage, STAMTYPE_PROFILE, "/PGM/RZ/GstModifyPage", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMGstModifyPage() body.");
1739
1740	STAM_REG(pVM, &pPGM->StatR3SyncCR3, STAMTYPE_PROFILE, "/PGM/R3/SyncCR3", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMSyncCR3() body.");
1741	STAM_REG(pVM, &pPGM->StatR3SyncCR3Handlers, STAMTYPE_PROFILE, "/PGM/R3/SyncCR3/Handlers", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMSyncCR3() update handler section.");
1742	STAM_REG(pVM, &pPGM->StatR3SyncCR3HandlerVirtualUpdate, STAMTYPE_PROFILE, "/PGM/R3/SyncCR3/Handlers/VirtualUpdate", STAMUNIT_TICKS_PER_CALL, "Profiling of the virtual handler updates.");
1743	STAM_REG(pVM, &pPGM->StatR3SyncCR3HandlerVirtualReset, STAMTYPE_PROFILE, "/PGM/R3/SyncCR3/Handlers/VirtualReset", STAMUNIT_TICKS_PER_CALL, "Profiling of the virtual handler resets.");
1744	STAM_REG(pVM, &pPGM->StatR3SyncCR3Global, STAMTYPE_COUNTER, "/PGM/R3/SyncCR3/Global", STAMUNIT_OCCURENCES, "The number of global CR3 syncs.");
1745	STAM_REG(pVM, &pPGM->StatR3SyncCR3NotGlobal, STAMTYPE_COUNTER, "/PGM/R3/SyncCR3/NotGlobal", STAMUNIT_OCCURENCES, "The number of non-global CR3 syncs.");
1746	STAM_REG(pVM, &pPGM->StatR3SyncCR3DstCacheHit, STAMTYPE_COUNTER, "/PGM/R3/SyncCR3/DstChacheHit", STAMUNIT_OCCURENCES, "The number of times we got some kind of a cache hit.");
1747	STAM_REG(pVM, &pPGM->StatR3SyncCR3DstFreed, STAMTYPE_COUNTER, "/PGM/R3/SyncCR3/DstFreed", STAMUNIT_OCCURENCES, "The number of times we've had to free a shadow entry.");
1748	STAM_REG(pVM, &pPGM->StatR3SyncCR3DstFreedSrcNP, STAMTYPE_COUNTER, "/PGM/R3/SyncCR3/DstFreedSrcNP", STAMUNIT_OCCURENCES, "The number of times we've had to free a shadow entry for which the source entry was not present.");
1749	STAM_REG(pVM, &pPGM->StatR3SyncCR3DstNotPresent, STAMTYPE_COUNTER, "/PGM/R3/SyncCR3/DstNotPresent", STAMUNIT_OCCURENCES, "The number of times we've encountered a not present shadow entry for a present guest entry.");
1750	STAM_REG(pVM, &pPGM->StatR3SyncCR3DstSkippedGlobalPD, STAMTYPE_COUNTER, "/PGM/R3/SyncCR3/DstSkippedGlobalPD", STAMUNIT_OCCURENCES, "The number of times a global page directory wasn't flushed.");
1751	STAM_REG(pVM, &pPGM->StatR3SyncCR3DstSkippedGlobalPT, STAMTYPE_COUNTER, "/PGM/R3/SyncCR3/DstSkippedGlobalPT", STAMUNIT_OCCURENCES, "The number of times a page table with only global entries wasn't flushed.");
1752	STAM_REG(pVM, &pPGM->StatR3SyncPT, STAMTYPE_PROFILE, "/PGM/R3/SyncPT", STAMUNIT_TICKS_PER_CALL, "Profiling of the pfnSyncPT() body.");
1753	STAM_REG(pVM, &pPGM->StatR3SyncPTFailed, STAMTYPE_COUNTER, "/PGM/R3/SyncPT/Failed", STAMUNIT_OCCURENCES, "The number of times pfnSyncPT() failed.");
1754	STAM_REG(pVM, &pPGM->StatR3SyncPT4K, STAMTYPE_COUNTER, "/PGM/R3/SyncPT/4K", STAMUNIT_OCCURENCES, "Nr of 4K PT syncs");
1755	STAM_REG(pVM, &pPGM->StatR3SyncPT4M, STAMTYPE_COUNTER, "/PGM/R3/SyncPT/4M", STAMUNIT_OCCURENCES, "Nr of 4M PT syncs");
1756	STAM_REG(pVM, &pPGM->StatR3SyncPagePDNAs, STAMTYPE_COUNTER, "/PGM/R3/SyncPagePDNAs", STAMUNIT_OCCURENCES, "The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit.");
1757	STAM_REG(pVM, &pPGM->StatR3SyncPagePDOutOfSync, STAMTYPE_COUNTER, "/PGM/R3/SyncPagePDOutOfSync", STAMUNIT_OCCURENCES, "The number of time we've encountered an out-of-sync PD in SyncPage.");
1758	STAM_REG(pVM, &pPGM->StatR3AccessedPage, STAMTYPE_COUNTER, "/PGM/R3/AccessedPage", STAMUNIT_OCCURENCES, "The number of pages marked not present for accessed bit emulation.");
1759	STAM_REG(pVM, &pPGM->StatR3DirtyBitTracking, STAMTYPE_PROFILE, "/PGM/R3/DirtyPage", STAMUNIT_TICKS_PER_CALL, "Profiling the dirty bit tracking in CheckPageFault().");
1760	STAM_REG(pVM, &pPGM->StatR3DirtyPage, STAMTYPE_COUNTER, "/PGM/R3/DirtyPage/Mark", STAMUNIT_OCCURENCES, "The number of pages marked read-only for dirty bit tracking.");
1761	STAM_REG(pVM, &pPGM->StatR3DirtyPageBig, STAMTYPE_COUNTER, "/PGM/R3/DirtyPage/MarkBig", STAMUNIT_OCCURENCES, "The number of 4MB pages marked read-only for dirty bit tracking.");
1762	STAM_REG(pVM, &pPGM->StatR3DirtyPageSkipped, STAMTYPE_COUNTER, "/PGM/R3/DirtyPage/Skipped", STAMUNIT_OCCURENCES, "The number of pages already dirty or readonly.");
1763	STAM_REG(pVM, &pPGM->StatR3DirtyPageTrap, STAMTYPE_COUNTER, "/PGM/R3/DirtyPage/Trap", STAMUNIT_OCCURENCES, "The number of traps generated for dirty bit tracking.");
1764	STAM_REG(pVM, &pPGM->StatR3DirtiedPage, STAMTYPE_COUNTER, "/PGM/R3/DirtyPage/SetDirty", STAMUNIT_OCCURENCES, "The number of pages marked dirty because of write accesses.");
1765	STAM_REG(pVM, &pPGM->StatR3DirtyTrackRealPF, STAMTYPE_COUNTER, "/PGM/R3/DirtyPage/RealPF", STAMUNIT_OCCURENCES, "The number of real pages faults during dirty bit tracking.");
1766	STAM_REG(pVM, &pPGM->StatR3PageAlreadyDirty, STAMTYPE_COUNTER, "/PGM/R3/DirtyPage/AlreadySet", STAMUNIT_OCCURENCES, "The number of pages already marked dirty because of write accesses.");
1767	STAM_REG(pVM, &pPGM->StatR3InvalidatePage, STAMTYPE_PROFILE, "/PGM/R3/InvalidatePage", STAMUNIT_TICKS_PER_CALL, "PGMInvalidatePage() profiling.");
1768	STAM_REG(pVM, &pPGM->StatR3InvalidatePage4KBPages, STAMTYPE_COUNTER, "/PGM/R3/InvalidatePage/4KBPages", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was called for a 4KB page.");
1769	STAM_REG(pVM, &pPGM->StatR3InvalidatePage4MBPages, STAMTYPE_COUNTER, "/PGM/R3/InvalidatePage/4MBPages", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was called for a 4MB page.");
1770	STAM_REG(pVM, &pPGM->StatR3InvalidatePage4MBPagesSkip, STAMTYPE_COUNTER, "/PGM/R3/InvalidatePage/4MBPagesSkip",STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() skipped a 4MB page.");
1771	STAM_REG(pVM, &pPGM->StatR3InvalidatePagePDMappings, STAMTYPE_COUNTER, "/PGM/R3/InvalidatePage/PDMappings", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict).");
1772	STAM_REG(pVM, &pPGM->StatR3InvalidatePagePDNAs, STAMTYPE_COUNTER, "/PGM/R3/InvalidatePage/PDNAs", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was called for a not accessed page directory.");
1773	STAM_REG(pVM, &pPGM->StatR3InvalidatePagePDNPs, STAMTYPE_COUNTER, "/PGM/R3/InvalidatePage/PDNPs", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was called for a not present page directory.");
1774	STAM_REG(pVM, &pPGM->StatR3InvalidatePagePDOutOfSync, STAMTYPE_COUNTER, "/PGM/R3/InvalidatePage/PDOutOfSync", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was called for an out of sync page directory.");
1775	STAM_REG(pVM, &pPGM->StatR3InvalidatePageSkipped, STAMTYPE_COUNTER, "/PGM/R3/InvalidatePage/Skipped", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3.");
1776	STAM_REG(pVM, &pPGM->StatR3VirtHandlerSearchByPhys, STAMTYPE_PROFILE, "/PGM/R3/VirtHandlerSearchByPhys", STAMUNIT_TICKS_PER_CALL, "Profiling of pgmHandlerVirtualFindByPhysAddr.");
1777	STAM_REG(pVM, &pPGM->StatR3PhysHandlerReset, STAMTYPE_COUNTER, "/PGM/R3/PhysHandlerReset", STAMUNIT_OCCURENCES, "The number of times PGMHandlerPhysicalReset is called.");
1778	STAM_REG(pVM, &pPGM->StatR3PageOutOfSyncSupervisor, STAMTYPE_COUNTER, "/PGM/R3/OutOfSync/SuperVisor", STAMUNIT_OCCURENCES, "Number of traps due to pages out of sync and times VerifyAccessSyncPage calls SyncPage.");
1779	STAM_REG(pVM, &pPGM->StatR3PageOutOfSyncUser, STAMTYPE_COUNTER, "/PGM/R3/OutOfSync/User", STAMUNIT_OCCURENCES, "Number of traps due to pages out of sync and times VerifyAccessSyncPage calls SyncPage.");
1780	STAM_REG(pVM, &pPGM->StatR3Prefetch, STAMTYPE_PROFILE, "/PGM/R3/Prefetch", STAMUNIT_TICKS_PER_CALL, "PGMPrefetchPage profiling.");
1781	STAM_REG(pVM, &pPGM->StatR3ChunkR3MapTlbHits, STAMTYPE_COUNTER, "/PGM/ChunkR3Map/TlbHitsR3", STAMUNIT_OCCURENCES, "TLB hits.");
1782	STAM_REG(pVM, &pPGM->StatR3ChunkR3MapTlbMisses, STAMTYPE_COUNTER, "/PGM/ChunkR3Map/TlbMissesR3", STAMUNIT_OCCURENCES, "TLB misses.");
1783	STAM_REG(pVM, &pPGM->StatR3PageMapTlbHits, STAMTYPE_COUNTER, "/PGM/R3/Page/MapTlbHits", STAMUNIT_OCCURENCES, "TLB hits.");
1784	STAM_REG(pVM, &pPGM->StatR3PageMapTlbMisses, STAMTYPE_COUNTER, "/PGM/R3/Page/MapTlbMisses", STAMUNIT_OCCURENCES, "TLB misses.");
1785	STAM_REG(pVM, &pPGM->StatR3PageReplaceShared, STAMTYPE_COUNTER, "/PGM/R3/Page/ReplacedShared", STAMUNIT_OCCURENCES, "Times a shared page was replaced.");
1786	STAM_REG(pVM, &pPGM->StatR3PageReplaceZero, STAMTYPE_COUNTER, "/PGM/R3/Page/ReplacedZero", STAMUNIT_OCCURENCES, "Times the zero page was replaced.");
1787	/// @todo STAM_REG(pVM, &pPGM->StatR3PageHandyAllocs, STAMTYPE_COUNTER, "/PGM/R3/Page/HandyAllocs", STAMUNIT_OCCURENCES, "Number of times we've allocated more handy pages.");
1788	STAM_REG(pVM, &pPGM->StatR3FlushTLB, STAMTYPE_PROFILE, "/PGM/R3/FlushTLB", STAMUNIT_OCCURENCES, "Profiling of the PGMFlushTLB() body.");
1789	STAM_REG(pVM, &pPGM->StatR3FlushTLBNewCR3, STAMTYPE_COUNTER, "/PGM/R3/FlushTLB/NewCR3", STAMUNIT_OCCURENCES, "The number of times PGMFlushTLB was called with a new CR3, non-global. (switch)");
1790	STAM_REG(pVM, &pPGM->StatR3FlushTLBNewCR3Global, STAMTYPE_COUNTER, "/PGM/R3/FlushTLB/NewCR3Global", STAMUNIT_OCCURENCES, "The number of times PGMFlushTLB was called with a new CR3, global. (switch)");
1791	STAM_REG(pVM, &pPGM->StatR3FlushTLBSameCR3, STAMTYPE_COUNTER, "/PGM/R3/FlushTLB/SameCR3", STAMUNIT_OCCURENCES, "The number of times PGMFlushTLB was called with the same CR3, non-global. (flush)");
1792	STAM_REG(pVM, &pPGM->StatR3FlushTLBSameCR3Global, STAMTYPE_COUNTER, "/PGM/R3/FlushTLB/SameCR3Global", STAMUNIT_OCCURENCES, "The number of times PGMFlushTLB was called with the same CR3, global. (flush)");
1793	STAM_REG(pVM, &pPGM->StatR3GstModifyPage, STAMTYPE_PROFILE, "/PGM/R3/GstModifyPage", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMGstModifyPage() body.");
1794
1795	}
1796	#endif /* VBOX_WITH_STATISTICS */
1797
1798
1799	/**
1800	* Init the PGM bits that rely on VMMR0 and MM to be fully initialized.
1801	*
1802	* The dynamic mapping area will also be allocated and initialized at this
1803	* time. We could allocate it during PGMR3Init of course, but the mapping
1804	* wouldn't be allocated at that time preventing us from setting up the
1805	* page table entries with the dummy page.
1806	*
1807	* @returns VBox status code.
1808	* @param pVM VM handle.
1809	*/
1810	VMMR3DECL(int) PGMR3InitDynMap(PVM pVM)
1811	{
1812	RTGCPTR GCPtr;
1813	int rc;
1814
1815	#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
1816	/*
1817	* Reserve space for mapping the paging pages into guest context.
1818	*/
1819	rc = MMR3HyperReserve(pVM, PAGE_SIZE * (2 + RT_ELEMENTS(pVM->pgm.s.apShwPaePDsR3) + 1 + 2 + 2), "Paging", &GCPtr);
1820	AssertRCReturn(rc, rc);
1821	pVM->pgm.s.pShw32BitPdRC = GCPtr;
1822	MMR3HyperReserve(pVM, PAGE_SIZE, "fence", NULL);
1823	#endif
1824
1825	/*
1826	* Reserve space for the dynamic mappings.
1827	*/
1828	rc = MMR3HyperReserve(pVM, MM_HYPER_DYNAMIC_SIZE, "Dynamic mapping", &GCPtr);
1829	if (RT_SUCCESS(rc))
1830	pVM->pgm.s.pbDynPageMapBaseGC = GCPtr;
1831
1832	if ( RT_SUCCESS(rc)
1833	&& (pVM->pgm.s.pbDynPageMapBaseGC >> X86_PD_PAE_SHIFT) != ((pVM->pgm.s.pbDynPageMapBaseGC + MM_HYPER_DYNAMIC_SIZE - 1) >> X86_PD_PAE_SHIFT))
1834	{
1835	rc = MMR3HyperReserve(pVM, MM_HYPER_DYNAMIC_SIZE, "Dynamic mapping not crossing", &GCPtr);
1836	if (RT_SUCCESS(rc))
1837	pVM->pgm.s.pbDynPageMapBaseGC = GCPtr;
1838	}
1839	if (RT_SUCCESS(rc))
1840	{
1841	AssertRelease((pVM->pgm.s.pbDynPageMapBaseGC >> X86_PD_PAE_SHIFT) == ((pVM->pgm.s.pbDynPageMapBaseGC + MM_HYPER_DYNAMIC_SIZE - 1) >> X86_PD_PAE_SHIFT));
1842	MMR3HyperReserve(pVM, PAGE_SIZE, "fence", NULL);
1843	}
1844	return rc;
1845	}
1846
1847
1848	/**
1849	* Ring-3 init finalizing.
1850	*
1851	* @returns VBox status code.
1852	* @param pVM The VM handle.
1853	*/
1854	VMMR3DECL(int) PGMR3InitFinalize(PVM pVM)
1855	{
1856	int rc;
1857
1858	#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
1859	/*
1860	* Map the paging pages into the guest context.
1861	*/
1862	RTGCPTR GCPtr = pVM->pgm.s.pShw32BitPdRC;
1863	AssertReleaseReturn(GCPtr, VERR_INTERNAL_ERROR);
1864
1865	rc = PGMMap(pVM, GCPtr, pVM->pgm.s.HCPhysShw32BitPD, PAGE_SIZE, 0);
1866	AssertRCReturn(rc, rc);
1867	pVM->pgm.s.pShw32BitPdRC = GCPtr;
1868	GCPtr += PAGE_SIZE;
1869	GCPtr += PAGE_SIZE; /* reserved page */
1870
1871	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.apShwPaePDsR3); i++)
1872	{
1873	rc = PGMMap(pVM, GCPtr, pVM->pgm.s.aHCPhysPaePDs[i], PAGE_SIZE, 0);
1874	AssertRCReturn(rc, rc);
1875	pVM->pgm.s.apShwPaePDsRC[i] = GCPtr;
1876	GCPtr += PAGE_SIZE;
1877	}
1878	/* A bit of paranoia is justified. */
1879	AssertRelease(pVM->pgm.s.apShwPaePDsRC[0] + PAGE_SIZE == pVM->pgm.s.apShwPaePDsRC[1]);
1880	AssertRelease(pVM->pgm.s.apShwPaePDsRC[1] + PAGE_SIZE == pVM->pgm.s.apShwPaePDsRC[2]);
1881	AssertRelease(pVM->pgm.s.apShwPaePDsRC[2] + PAGE_SIZE == pVM->pgm.s.apShwPaePDsRC[3]);
1882	GCPtr += PAGE_SIZE; /* reserved page */
1883
1884	rc = PGMMap(pVM, GCPtr, pVM->pgm.s.HCPhysShwPaePdpt, PAGE_SIZE, 0);
1885	AssertRCReturn(rc, rc);
1886	pVM->pgm.s.pShwPaePdptRC = GCPtr;
1887	GCPtr += PAGE_SIZE;
1888	GCPtr += PAGE_SIZE; /* reserved page */
1889	#endif
1890
1891	/*
1892	* Reserve space for the dynamic mappings.
1893	* Initialize the dynamic mapping pages with dummy pages to simply the cache.
1894	*/
1895	/* get the pointer to the page table entries. */
1896	PPGMMAPPING pMapping = pgmGetMapping(pVM, pVM->pgm.s.pbDynPageMapBaseGC);
1897	AssertRelease(pMapping);
1898	const uintptr_t off = pVM->pgm.s.pbDynPageMapBaseGC - pMapping->GCPtr;
1899	const unsigned iPT = off >> X86_PD_SHIFT;
1900	const unsigned iPG = (off >> X86_PT_SHIFT) & X86_PT_MASK;
1901	pVM->pgm.s.paDynPageMap32BitPTEsGC = pMapping->aPTs[iPT].pPTRC + iPG * sizeof(pMapping->aPTs[0].pPTR3->a[0]);
1902	pVM->pgm.s.paDynPageMapPaePTEsGC = pMapping->aPTs[iPT].paPaePTsRC + iPG * sizeof(pMapping->aPTs[0].paPaePTsR3->a[0]);
1903
1904	/* init cache */
1905	RTHCPHYS HCPhysDummy = MMR3PageDummyHCPhys(pVM);
1906	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.aHCPhysDynPageMapCache); i++)
1907	pVM->pgm.s.aHCPhysDynPageMapCache[i] = HCPhysDummy;
1908
1909	for (unsigned i = 0; i < MM_HYPER_DYNAMIC_SIZE; i += PAGE_SIZE)
1910	{
1911	rc = PGMMap(pVM, pVM->pgm.s.pbDynPageMapBaseGC + i, HCPhysDummy, PAGE_SIZE, 0);
1912	AssertRCReturn(rc, rc);
1913	}
1914
1915	/*
1916	* Note that AMD uses all the 8 reserved bits for the address (so 40 bits in total);
1917	* Intel only goes up to 36 bits, so we stick to 36 as well.
1918	*/
1919	/** @todo How to test for the 40 bits support? Long mode seems to be the test criterium. */
1920	uint32_t u32Dummy, u32Features;
1921	CPUMGetGuestCpuId(pVM, 1, &u32Dummy, &u32Dummy, &u32Dummy, &u32Features);
1922
1923	if (u32Features & X86_CPUID_FEATURE_EDX_PSE36)
1924	pVM->pgm.s.GCPhys4MBPSEMask = RT_BIT_64(36) - 1;
1925	else
1926	pVM->pgm.s.GCPhys4MBPSEMask = RT_BIT_64(32) - 1;
1927
1928	LogRel(("PGMR3InitFinalize: 4 MB PSE mask %RGp\n", pVM->pgm.s.GCPhys4MBPSEMask));
1929
1930	return rc;
1931	}
1932
1933
1934	/**
1935	* Applies relocations to data and code managed by this component.
1936	*
1937	* This function will be called at init and whenever the VMM need to relocate it
1938	* self inside the GC.
1939	*
1940	* @param pVM The VM.
1941	* @param offDelta Relocation delta relative to old location.
1942	*/
1943	VMMR3DECL(void) PGMR3Relocate(PVM pVM, RTGCINTPTR offDelta)
1944	{
1945	LogFlow(("PGMR3Relocate\n"));
1946
1947	/*
1948	* Paging stuff.
1949	*/
1950	pVM->pgm.s.GCPtrCR3Mapping += offDelta;
1951	/** @todo move this into shadow and guest specific relocation functions. */
1952	AssertMsg(pVM->pgm.s.pShw32BitPdR3, ("Init order, no relocation before paging is initialized!\n"));
1953	#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
1954	pVM->pgm.s.pShw32BitPdRC += offDelta;
1955	#endif
1956	pVM->pgm.s.pGst32BitPdRC += offDelta;
1957	AssertCompile(RT_ELEMENTS(pVM->pgm.s.apShwPaePDsRC) == RT_ELEMENTS(pVM->pgm.s.apGstPaePDsRC));
1958	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.apShwPaePDsRC); i++)
1959	{
1960	#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
1961	pVM->pgm.s.apShwPaePDsRC[i] += offDelta;
1962	#endif
1963	pVM->pgm.s.apGstPaePDsRC[i] += offDelta;
1964	}
1965	pVM->pgm.s.pGstPaePdptRC += offDelta;
1966	#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
1967	pVM->pgm.s.pShwPaePdptRC += offDelta;
1968	#endif
1969
1970	pgmR3ModeDataInit(pVM, true /* resolve GC/R0 symbols */);
1971	pgmR3ModeDataSwitch(pVM, pVM->pgm.s.enmShadowMode, pVM->pgm.s.enmGuestMode);
1972
1973	PGM_SHW_PFN(Relocate, pVM)(pVM, offDelta);
1974	PGM_GST_PFN(Relocate, pVM)(pVM, offDelta);
1975	PGM_BTH_PFN(Relocate, pVM)(pVM, offDelta);
1976
1977	/*
1978	* Trees.
1979	*/
1980	pVM->pgm.s.pTreesRC = MMHyperR3ToRC(pVM, pVM->pgm.s.pTreesR3);
1981
1982	/*
1983	* Ram ranges.
1984	*/
1985	if (pVM->pgm.s.pRamRangesR3)
1986	{
1987	pVM->pgm.s.pRamRangesRC = MMHyperR3ToRC(pVM, pVM->pgm.s.pRamRangesR3);
1988	for (PPGMRAMRANGE pCur = pVM->pgm.s.pRamRangesR3; pCur->pNextR3; pCur = pCur->pNextR3)
1989	pCur->pNextRC = MMHyperR3ToRC(pVM, pCur->pNextR3);
1990	}
1991
1992	/*
1993	* Update the two page directories with all page table mappings.
1994	* (One or more of them have changed, that's why we're here.)
1995	*/
1996	pVM->pgm.s.pMappingsRC = MMHyperR3ToRC(pVM, pVM->pgm.s.pMappingsR3);
1997	for (PPGMMAPPING pCur = pVM->pgm.s.pMappingsR3; pCur->pNextR3; pCur = pCur->pNextR3)
1998	pCur->pNextRC = MMHyperR3ToRC(pVM, pCur->pNextR3);
1999
2000	/* Relocate GC addresses of Page Tables. */
2001	for (PPGMMAPPING pCur = pVM->pgm.s.pMappingsR3; pCur; pCur = pCur->pNextR3)
2002	{
2003	for (RTHCUINT i = 0; i < pCur->cPTs; i++)
2004	{
2005	pCur->aPTs[i].pPTRC = MMHyperR3ToRC(pVM, pCur->aPTs[i].pPTR3);
2006	pCur->aPTs[i].paPaePTsRC = MMHyperR3ToRC(pVM, pCur->aPTs[i].paPaePTsR3);
2007	}
2008	}
2009
2010	/*
2011	* Dynamic page mapping area.
2012	*/
2013	pVM->pgm.s.paDynPageMap32BitPTEsGC += offDelta;
2014	pVM->pgm.s.paDynPageMapPaePTEsGC += offDelta;
2015	pVM->pgm.s.pbDynPageMapBaseGC += offDelta;
2016
2017	/*
2018	* The Zero page.
2019	*/
2020	pVM->pgm.s.pvZeroPgR0 = MMHyperR3ToR0(pVM, pVM->pgm.s.pvZeroPgR3);
2021	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
2022	AssertRelease(pVM->pgm.s.pvZeroPgR0 != NIL_RTR0PTR \|\| !VMMIsHwVirtExtForced(pVM));
2023	#else
2024	AssertRelease(pVM->pgm.s.pvZeroPgR0 != NIL_RTR0PTR);
2025	#endif
2026
2027	/*
2028	* Physical and virtual handlers.
2029	*/
2030	RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysHandlers, true, pgmR3RelocatePhysHandler, &offDelta);
2031	RTAvlroGCPtrDoWithAll(&pVM->pgm.s.pTreesR3->VirtHandlers, true, pgmR3RelocateVirtHandler, &offDelta);
2032	RTAvlroGCPtrDoWithAll(&pVM->pgm.s.pTreesR3->HyperVirtHandlers, true, pgmR3RelocateHyperVirtHandler, &offDelta);
2033
2034	/*
2035	* The page pool.
2036	*/
2037	pgmR3PoolRelocate(pVM);
2038	}
2039
2040
2041	/**
2042	* Callback function for relocating a physical access handler.
2043	*
2044	* @returns 0 (continue enum)
2045	* @param pNode Pointer to a PGMPHYSHANDLER node.
2046	* @param pvUser Pointer to the offDelta. This is a pointer to the delta since we're
2047	* not certain the delta will fit in a void pointer for all possible configs.
2048	*/
2049	static DECLCALLBACK(int) pgmR3RelocatePhysHandler(PAVLROGCPHYSNODECORE pNode, void *pvUser)
2050	{
2051	PPGMPHYSHANDLER pHandler = (PPGMPHYSHANDLER)pNode;
2052	RTGCINTPTR offDelta = *(PRTGCINTPTR)pvUser;
2053	if (pHandler->pfnHandlerRC)
2054	pHandler->pfnHandlerRC += offDelta;
2055	if (pHandler->pvUserRC >= 0x10000)
2056	pHandler->pvUserRC += offDelta;
2057	return 0;
2058	}
2059
2060
2061	/**
2062	* Callback function for relocating a virtual access handler.
2063	*
2064	* @returns 0 (continue enum)
2065	* @param pNode Pointer to a PGMVIRTHANDLER node.
2066	* @param pvUser Pointer to the offDelta. This is a pointer to the delta since we're
2067	* not certain the delta will fit in a void pointer for all possible configs.
2068	*/
2069	static DECLCALLBACK(int) pgmR3RelocateVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser)
2070	{
2071	PPGMVIRTHANDLER pHandler = (PPGMVIRTHANDLER)pNode;
2072	RTGCINTPTR offDelta = *(PRTGCINTPTR)pvUser;
2073	Assert( pHandler->enmType == PGMVIRTHANDLERTYPE_ALL
2074	\|\| pHandler->enmType == PGMVIRTHANDLERTYPE_WRITE);
2075	Assert(pHandler->pfnHandlerRC);
2076	pHandler->pfnHandlerRC += offDelta;
2077	return 0;
2078	}
2079
2080
2081	/**
2082	* Callback function for relocating a virtual access handler for the hypervisor mapping.
2083	*
2084	* @returns 0 (continue enum)
2085	* @param pNode Pointer to a PGMVIRTHANDLER node.
2086	* @param pvUser Pointer to the offDelta. This is a pointer to the delta since we're
2087	* not certain the delta will fit in a void pointer for all possible configs.
2088	*/
2089	static DECLCALLBACK(int) pgmR3RelocateHyperVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser)
2090	{
2091	PPGMVIRTHANDLER pHandler = (PPGMVIRTHANDLER)pNode;
2092	RTGCINTPTR offDelta = *(PRTGCINTPTR)pvUser;
2093	Assert(pHandler->enmType == PGMVIRTHANDLERTYPE_HYPERVISOR);
2094	Assert(pHandler->pfnHandlerRC);
2095	pHandler->pfnHandlerRC += offDelta;
2096	return 0;
2097	}
2098
2099
2100	/**
2101	* The VM is being reset.
2102	*
2103	* For the PGM component this means that any PD write monitors
2104	* needs to be removed.
2105	*
2106	* @param pVM VM handle.
2107	*/
2108	VMMR3DECL(void) PGMR3Reset(PVM pVM)
2109	{
2110	LogFlow(("PGMR3Reset:\n"));
2111	VM_ASSERT_EMT(pVM);
2112
2113	pgmLock(pVM);
2114
2115	/*
2116	* Unfix any fixed mappings and disable CR3 monitoring.
2117	*/
2118	pVM->pgm.s.fMappingsFixed = false;
2119	pVM->pgm.s.GCPtrMappingFixed = 0;
2120	pVM->pgm.s.cbMappingFixed = 0;
2121
2122	/* Exit the guest paging mode before the pgm pool gets reset.
2123	* Important to clean up the amd64 case.
2124	*/
2125	int rc = PGM_GST_PFN(Exit, pVM)(pVM);
2126	AssertRC(rc);
2127	#ifdef DEBUG
2128	DBGFR3InfoLog(pVM, "mappings", NULL);
2129	DBGFR3InfoLog(pVM, "handlers", "all nostat");
2130	#endif
2131
2132	/*
2133	* Reset the shadow page pool.
2134	*/
2135	pgmR3PoolReset(pVM);
2136
2137	/*
2138	* Re-init other members.
2139	*/
2140	pVM->pgm.s.fA20Enabled = true;
2141
2142	/*
2143	* Clear the FFs PGM owns.
2144	*/
2145	VM_FF_CLEAR(pVM, VM_FF_PGM_SYNC_CR3);
2146	VM_FF_CLEAR(pVM, VM_FF_PGM_SYNC_CR3_NON_GLOBAL);
2147
2148	/*
2149	* Reset (zero) RAM pages.
2150	*/
2151	rc = pgmR3PhysRamReset(pVM);
2152	if (RT_SUCCESS(rc))
2153	{
2154	#ifdef VBOX_WITH_NEW_PHYS_CODE
2155	/*
2156	* Reset (zero) shadow ROM pages.
2157	*/
2158	rc = pgmR3PhysRomReset(pVM);
2159	#endif
2160	if (RT_SUCCESS(rc))
2161	{
2162	/*
2163	* Switch mode back to real mode.
2164	*/
2165	rc = PGMR3ChangeMode(pVM, PGMMODE_REAL);
2166	STAM_REL_COUNTER_RESET(&pVM->pgm.s.cGuestModeChanges);
2167	}
2168	}
2169
2170	pgmUnlock(pVM);
2171	//return rc;
2172	AssertReleaseRC(rc);
2173	}
2174
2175
2176	#ifdef VBOX_STRICT
2177	/**
2178	* VM state change callback for clearing fNoMorePhysWrites after
2179	* a snapshot has been created.
2180	*/
2181	static DECLCALLBACK(void) pgmR3ResetNoMorePhysWritesFlag(PVM pVM, VMSTATE enmState, VMSTATE enmOldState, void *pvUser)
2182	{
2183	if (enmState == VMSTATE_RUNNING)
2184	pVM->pgm.s.fNoMorePhysWrites = false;
2185	}
2186	#endif
2187
2188
2189	/**
2190	* Terminates the PGM.
2191	*
2192	* @returns VBox status code.
2193	* @param pVM Pointer to VM structure.
2194	*/
2195	VMMR3DECL(int) PGMR3Term(PVM pVM)
2196	{
2197	return PDMR3CritSectDelete(&pVM->pgm.s.CritSect);
2198	}
2199
2200
2201	/**
2202	* Terminates the per-VCPU PGM.
2203	*
2204	* Termination means cleaning up and freeing all resources,
2205	* the VM it self is at this point powered off or suspended.
2206	*
2207	* @returns VBox status code.
2208	* @param pVM The VM to operate on.
2209	*/
2210	VMMR3DECL(int) PGMR3TermCPU(PVM pVM)
2211	{
2212	return 0;
2213	}
2214
2215
2216	/**
2217	* Execute state save operation.
2218	*
2219	* @returns VBox status code.
2220	* @param pVM VM Handle.
2221	* @param pSSM SSM operation handle.
2222	*/
2223	static DECLCALLBACK(int) pgmR3Save(PVM pVM, PSSMHANDLE pSSM)
2224	{
2225	PPGM pPGM = &pVM->pgm.s;
2226
2227	/* No more writes to physical memory after this point! */
2228	pVM->pgm.s.fNoMorePhysWrites = true;
2229
2230	/*
2231	* Save basic data (required / unaffected by relocation).
2232	*/
2233	#if 1
2234	SSMR3PutBool(pSSM, pPGM->fMappingsFixed);
2235	#else
2236	SSMR3PutUInt(pSSM, pPGM->fMappingsFixed);
2237	#endif
2238	SSMR3PutGCPtr(pSSM, pPGM->GCPtrMappingFixed);
2239	SSMR3PutU32(pSSM, pPGM->cbMappingFixed);
2240	SSMR3PutUInt(pSSM, pPGM->cbRamSize);
2241	SSMR3PutGCPhys(pSSM, pPGM->GCPhysA20Mask);
2242	SSMR3PutUInt(pSSM, pPGM->fA20Enabled);
2243	SSMR3PutUInt(pSSM, pPGM->fSyncFlags);
2244	SSMR3PutUInt(pSSM, pPGM->enmGuestMode);
2245	SSMR3PutU32(pSSM, ~0); /* Separator. */
2246
2247	/*
2248	* The guest mappings.
2249	*/
2250	uint32_t i = 0;
2251	for (PPGMMAPPING pMapping = pPGM->pMappingsR3; pMapping; pMapping = pMapping->pNextR3, i++)
2252	{
2253	SSMR3PutU32(pSSM, i);
2254	SSMR3PutStrZ(pSSM, pMapping->pszDesc); /* This is the best unique id we have... */
2255	SSMR3PutGCPtr(pSSM, pMapping->GCPtr);
2256	SSMR3PutGCUIntPtr(pSSM, pMapping->cPTs);
2257	/* flags are done by the mapping owners! */
2258	}
2259	SSMR3PutU32(pSSM, ~0); /* terminator. */
2260
2261	/*
2262	* Ram range flags and bits.
2263	*/
2264	i = 0;
2265	for (PPGMRAMRANGE pRam = pPGM->pRamRangesR3; pRam; pRam = pRam->pNextR3, i++)
2266	{
2267	/** @todo MMIO ranges may move (PCI reconfig), we currently assume they don't. */
2268
2269	SSMR3PutU32(pSSM, i);
2270	SSMR3PutGCPhys(pSSM, pRam->GCPhys);
2271	SSMR3PutGCPhys(pSSM, pRam->GCPhysLast);
2272	SSMR3PutGCPhys(pSSM, pRam->cb);
2273	SSMR3PutU8(pSSM, !!pRam->pvR3); /* boolean indicating memory or not. */
2274
2275	/* Flags. */
2276	const unsigned cPages = pRam->cb >> PAGE_SHIFT;
2277	for (unsigned iPage = 0; iPage < cPages; iPage++)
2278	SSMR3PutU16(pSSM, (uint16_t)(pRam->aPages[iPage].HCPhys & ~X86_PTE_PAE_PG_MASK)); /** @todo PAGE FLAGS */
2279
2280	/* any memory associated with the range. */
2281	if (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)
2282	{
2283	for (unsigned iChunk = 0; iChunk < (pRam->cb >> PGM_DYNAMIC_CHUNK_SHIFT); iChunk++)
2284	{
2285	if (pRam->paChunkR3Ptrs[iChunk])
2286	{
2287	SSMR3PutU8(pSSM, 1); /* chunk present */
2288	SSMR3PutMem(pSSM, (void *)pRam->paChunkR3Ptrs[iChunk], PGM_DYNAMIC_CHUNK_SIZE);
2289	}
2290	else
2291	SSMR3PutU8(pSSM, 0); /* no chunk present */
2292	}
2293	}
2294	else if (pRam->pvR3)
2295	{
2296	int rc = SSMR3PutMem(pSSM, pRam->pvR3, pRam->cb);
2297	if (RT_FAILURE(rc))
2298	{
2299	Log(("pgmR3Save: SSMR3PutMem(, %p, %#x) -> %Rrc\n", pRam->pvR3, pRam->cb, rc));
2300	return rc;
2301	}
2302	}
2303	}
2304	return SSMR3PutU32(pSSM, ~0); /* terminator. */
2305	}
2306
2307
2308	/**
2309	* Execute state load operation.
2310	*
2311	* @returns VBox status code.
2312	* @param pVM VM Handle.
2313	* @param pSSM SSM operation handle.
2314	* @param u32Version Data layout version.
2315	*/
2316	static DECLCALLBACK(int) pgmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version)
2317	{
2318	/*
2319	* Validate version.
2320	*/
2321	if (u32Version != PGM_SAVED_STATE_VERSION)
2322	{
2323	AssertMsgFailed(("pgmR3Load: Invalid version u32Version=%d (current %d)!\n", u32Version, PGM_SAVED_STATE_VERSION));
2324	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
2325	}
2326
2327	/*
2328	* Call the reset function to make sure all the memory is cleared.
2329	*/
2330	PGMR3Reset(pVM);
2331
2332	/*
2333	* Load basic data (required / unaffected by relocation).
2334	*/
2335	PPGM pPGM = &pVM->pgm.s;
2336	#if 1
2337	SSMR3GetBool(pSSM, &pPGM->fMappingsFixed);
2338	#else
2339	uint32_t u;
2340	SSMR3GetU32(pSSM, &u);
2341	pPGM->fMappingsFixed = u;
2342	#endif
2343	SSMR3GetGCPtr(pSSM, &pPGM->GCPtrMappingFixed);
2344	SSMR3GetU32(pSSM, &pPGM->cbMappingFixed);
2345
2346	RTUINT cbRamSize;
2347	int rc = SSMR3GetU32(pSSM, &cbRamSize);
2348	if (RT_FAILURE(rc))
2349	return rc;
2350	if (cbRamSize != pPGM->cbRamSize)
2351	return VERR_SSM_LOAD_MEMORY_SIZE_MISMATCH;
2352	SSMR3GetGCPhys(pSSM, &pPGM->GCPhysA20Mask);
2353	SSMR3GetUInt(pSSM, &pPGM->fA20Enabled);
2354	SSMR3GetUInt(pSSM, &pPGM->fSyncFlags);
2355	RTUINT uGuestMode;
2356	SSMR3GetUInt(pSSM, &uGuestMode);
2357	pPGM->enmGuestMode = (PGMMODE)uGuestMode;
2358
2359	/* check separator. */
2360	uint32_t u32Sep;
2361	SSMR3GetU32(pSSM, &u32Sep);
2362	if (RT_FAILURE(rc))
2363	return rc;
2364	if (u32Sep != (uint32_t)~0)
2365	{
2366	AssertMsgFailed(("u32Sep=%#x (first)\n", u32Sep));
2367	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2368	}
2369
2370	/*
2371	* The guest mappings.
2372	*/
2373	uint32_t i = 0;
2374	for (;; i++)
2375	{
2376	/* Check the seqence number / separator. */
2377	rc = SSMR3GetU32(pSSM, &u32Sep);
2378	if (RT_FAILURE(rc))
2379	return rc;
2380	if (u32Sep == ~0U)
2381	break;
2382	if (u32Sep != i)
2383	{
2384	AssertMsgFailed(("u32Sep=%#x (last)\n", u32Sep));
2385	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2386	}
2387
2388	/* get the mapping details. */
2389	char szDesc[256];
2390	szDesc[0] = '\0';
2391	rc = SSMR3GetStrZ(pSSM, szDesc, sizeof(szDesc));
2392	if (RT_FAILURE(rc))
2393	return rc;
2394	RTGCPTR GCPtr;
2395	SSMR3GetGCPtr(pSSM, &GCPtr);
2396	RTGCPTR cPTs;
2397	rc = SSMR3GetGCUIntPtr(pSSM, &cPTs);
2398	if (RT_FAILURE(rc))
2399	return rc;
2400
2401	/* find matching range. */
2402	PPGMMAPPING pMapping;
2403	for (pMapping = pPGM->pMappingsR3; pMapping; pMapping = pMapping->pNextR3)
2404	if ( pMapping->cPTs == cPTs
2405	&& !strcmp(pMapping->pszDesc, szDesc))
2406	break;
2407	if (!pMapping)
2408	{
2409	LogRel(("Couldn't find mapping: cPTs=%#x szDesc=%s (GCPtr=%RGv)\n",
2410	cPTs, szDesc, GCPtr));
2411	AssertFailed();
2412	return VERR_SSM_LOAD_CONFIG_MISMATCH;
2413	}
2414
2415	/* relocate it. */
2416	if (pMapping->GCPtr != GCPtr)
2417	{
2418	AssertMsg((GCPtr >> X86_PD_SHIFT << X86_PD_SHIFT) == GCPtr, ("GCPtr=%RGv\n", GCPtr));
2419	pgmR3MapRelocate(pVM, pMapping, pMapping->GCPtr, GCPtr);
2420	}
2421	else
2422	Log(("pgmR3Load: '%s' needed no relocation (%RGv)\n", szDesc, GCPtr));
2423	}
2424
2425	/*
2426	* Ram range flags and bits.
2427	*/
2428	i = 0;
2429	for (PPGMRAMRANGE pRam = pPGM->pRamRangesR3; pRam; pRam = pRam->pNextR3, i++)
2430	{
2431	/** @todo MMIO ranges may move (PCI reconfig), we currently assume they don't. */
2432	/* Check the seqence number / separator. */
2433	rc = SSMR3GetU32(pSSM, &u32Sep);
2434	if (RT_FAILURE(rc))
2435	return rc;
2436	if (u32Sep == ~0U)
2437	break;
2438	if (u32Sep != i)
2439	{
2440	AssertMsgFailed(("u32Sep=%#x (last)\n", u32Sep));
2441	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2442	}
2443
2444	/* Get the range details. */
2445	RTGCPHYS GCPhys;
2446	SSMR3GetGCPhys(pSSM, &GCPhys);
2447	RTGCPHYS GCPhysLast;
2448	SSMR3GetGCPhys(pSSM, &GCPhysLast);
2449	RTGCPHYS cb;
2450	SSMR3GetGCPhys(pSSM, &cb);
2451	uint8_t fHaveBits;
2452	rc = SSMR3GetU8(pSSM, &fHaveBits);
2453	if (RT_FAILURE(rc))
2454	return rc;
2455	if (fHaveBits & ~1)
2456	{
2457	AssertMsgFailed(("u32Sep=%#x (last)\n", u32Sep));
2458	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2459	}
2460
2461	/* Match it up with the current range. */
2462	if ( GCPhys != pRam->GCPhys
2463	\|\| GCPhysLast != pRam->GCPhysLast
2464	\|\| cb != pRam->cb
2465	\|\| fHaveBits != !!pRam->pvR3)
2466	{
2467	LogRel(("Ram range: %RGp-%RGp %RGp bytes %s\n"
2468	"State : %RGp-%RGp %RGp bytes %s\n",
2469	pRam->GCPhys, pRam->GCPhysLast, pRam->cb, pRam->pvR3 ? "bits" : "nobits",
2470	GCPhys, GCPhysLast, cb, fHaveBits ? "bits" : "nobits"));
2471	/*
2472	* If we're loading a state for debugging purpose, don't make a fuss if
2473	* the MMIO[2] and ROM stuff isn't 100% right, just skip the mismatches.
2474	*/
2475	if ( SSMR3HandleGetAfter(pSSM) != SSMAFTER_DEBUG_IT
2476	\|\| GCPhys < 8 * _1M)
2477	AssertFailedReturn(VERR_SSM_LOAD_CONFIG_MISMATCH);
2478
2479	RTGCPHYS cPages = ((GCPhysLast - GCPhys) + 1) >> PAGE_SHIFT;
2480	while (cPages-- > 0)
2481	{
2482	uint16_t u16Ignore;
2483	SSMR3GetU16(pSSM, &u16Ignore);
2484	}
2485	continue;
2486	}
2487
2488	/* Flags. */
2489	const unsigned cPages = pRam->cb >> PAGE_SHIFT;
2490	for (unsigned iPage = 0; iPage < cPages; iPage++)
2491	{
2492	uint16_t u16 = 0;
2493	SSMR3GetU16(pSSM, &u16);
2494	u16 &= PAGE_OFFSET_MASK & ~( RT_BIT(4) \| RT_BIT(5) \| RT_BIT(6)
2495	\| RT_BIT(7) \| RT_BIT(8) \| RT_BIT(9) \| RT_BIT(10) );
2496	// &= MM_RAM_FLAGS_DYNAMIC_ALLOC \| MM_RAM_FLAGS_RESERVED \| MM_RAM_FLAGS_ROM \| MM_RAM_FLAGS_MMIO \| MM_RAM_FLAGS_MMIO2
2497	pRam->aPages[iPage].HCPhys = PGM_PAGE_GET_HCPHYS(&pRam->aPages[iPage]) \| (RTHCPHYS)u16; /** @todo PAGE FLAGS */
2498	}
2499
2500	/* any memory associated with the range. */
2501	if (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)
2502	{
2503	for (unsigned iChunk = 0; iChunk < (pRam->cb >> PGM_DYNAMIC_CHUNK_SHIFT); iChunk++)
2504	{
2505	uint8_t fValidChunk;
2506
2507	rc = SSMR3GetU8(pSSM, &fValidChunk);
2508	if (RT_FAILURE(rc))
2509	return rc;
2510	if (fValidChunk > 1)
2511	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2512
2513	if (fValidChunk)
2514	{
2515	if (!pRam->paChunkR3Ptrs[iChunk])
2516	{
2517	rc = pgmr3PhysGrowRange(pVM, pRam->GCPhys + iChunk * PGM_DYNAMIC_CHUNK_SIZE);
2518	if (RT_FAILURE(rc))
2519	return rc;
2520	}
2521	Assert(pRam->paChunkR3Ptrs[iChunk]);
2522
2523	SSMR3GetMem(pSSM, (void *)pRam->paChunkR3Ptrs[iChunk], PGM_DYNAMIC_CHUNK_SIZE);
2524	}
2525	/* else nothing to do */
2526	}
2527	}
2528	else if (pRam->pvR3)
2529	{
2530	int rc = SSMR3GetMem(pSSM, pRam->pvR3, pRam->cb);
2531	if (RT_FAILURE(rc))
2532	{
2533	Log(("pgmR3Save: SSMR3GetMem(, %p, %#x) -> %Rrc\n", pRam->pvR3, pRam->cb, rc));
2534	return rc;
2535	}
2536	}
2537	}
2538
2539	/*
2540	* We require a full resync now.
2541	*/
2542	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3_NON_GLOBAL);
2543	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
2544	pPGM->fSyncFlags \|= PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL;
2545	pPGM->fPhysCacheFlushPending = true;
2546	pgmR3HandlerPhysicalUpdateAll(pVM);
2547
2548	/*
2549	* Change the paging mode.
2550	*/
2551	rc = PGMR3ChangeMode(pVM, pPGM->enmGuestMode);
2552
2553	/* Restore pVM->pgm.s.GCPhysCR3. */
2554	Assert(pVM->pgm.s.GCPhysCR3 == NIL_RTGCPHYS);
2555	RTGCPHYS GCPhysCR3 = CPUMGetGuestCR3(pVM);
2556	if ( pVM->pgm.s.enmGuestMode == PGMMODE_PAE
2557	\|\| pVM->pgm.s.enmGuestMode == PGMMODE_PAE_NX
2558	\|\| pVM->pgm.s.enmGuestMode == PGMMODE_AMD64
2559	\|\| pVM->pgm.s.enmGuestMode == PGMMODE_AMD64_NX)
2560	GCPhysCR3 = (GCPhysCR3 & X86_CR3_PAE_PAGE_MASK);
2561	else
2562	GCPhysCR3 = (GCPhysCR3 & X86_CR3_PAGE_MASK);
2563	pVM->pgm.s.GCPhysCR3 = GCPhysCR3;
2564
2565	return rc;
2566	}
2567
2568
2569	/**
2570	* Show paging mode.
2571	*
2572	* @param pVM VM Handle.
2573	* @param pHlp The info helpers.
2574	* @param pszArgs "all" (default), "guest", "shadow" or "host".
2575	*/
2576	static DECLCALLBACK(void) pgmR3InfoMode(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2577	{
2578	/* digest argument. */
2579	bool fGuest, fShadow, fHost;
2580	if (pszArgs)
2581	pszArgs = RTStrStripL(pszArgs);
2582	if (!pszArgs \|\| !*pszArgs \|\| strstr(pszArgs, "all"))
2583	fShadow = fHost = fGuest = true;
2584	else
2585	{
2586	fShadow = fHost = fGuest = false;
2587	if (strstr(pszArgs, "guest"))
2588	fGuest = true;
2589	if (strstr(pszArgs, "shadow"))
2590	fShadow = true;
2591	if (strstr(pszArgs, "host"))
2592	fHost = true;
2593	}
2594
2595	/* print info. */
2596	if (fGuest)
2597	pHlp->pfnPrintf(pHlp, "Guest paging mode: %s, changed %RU64 times, A20 %s\n",
2598	PGMGetModeName(pVM->pgm.s.enmGuestMode), pVM->pgm.s.cGuestModeChanges.c,
2599	pVM->pgm.s.fA20Enabled ? "enabled" : "disabled");
2600	if (fShadow)
2601	pHlp->pfnPrintf(pHlp, "Shadow paging mode: %s\n", PGMGetModeName(pVM->pgm.s.enmShadowMode));
2602	if (fHost)
2603	{
2604	const char *psz;
2605	switch (pVM->pgm.s.enmHostMode)
2606	{
2607	case SUPPAGINGMODE_INVALID: psz = "invalid"; break;
2608	case SUPPAGINGMODE_32_BIT: psz = "32-bit"; break;
2609	case SUPPAGINGMODE_32_BIT_GLOBAL: psz = "32-bit+G"; break;
2610	case SUPPAGINGMODE_PAE: psz = "PAE"; break;
2611	case SUPPAGINGMODE_PAE_GLOBAL: psz = "PAE+G"; break;
2612	case SUPPAGINGMODE_PAE_NX: psz = "PAE+NX"; break;
2613	case SUPPAGINGMODE_PAE_GLOBAL_NX: psz = "PAE+G+NX"; break;
2614	case SUPPAGINGMODE_AMD64: psz = "AMD64"; break;
2615	case SUPPAGINGMODE_AMD64_GLOBAL: psz = "AMD64+G"; break;
2616	case SUPPAGINGMODE_AMD64_NX: psz = "AMD64+NX"; break;
2617	case SUPPAGINGMODE_AMD64_GLOBAL_NX: psz = "AMD64+G+NX"; break;
2618	default: psz = "unknown"; break;
2619	}
2620	pHlp->pfnPrintf(pHlp, "Host paging mode: %s\n", psz);
2621	}
2622	}
2623
2624
2625	/**
2626	* Dump registered MMIO ranges to the log.
2627	*
2628	* @param pVM VM Handle.
2629	* @param pHlp The info helpers.
2630	* @param pszArgs Arguments, ignored.
2631	*/
2632	static DECLCALLBACK(void) pgmR3PhysInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2633	{
2634	NOREF(pszArgs);
2635	pHlp->pfnPrintf(pHlp,
2636	"RAM ranges (pVM=%p)\n"
2637	"%.s %.s\n",
2638	pVM,
2639	sizeof(RTGCPHYS) * 4 + 1, "GC Phys Range ",
2640	sizeof(RTHCPTR) * 2, "pvHC ");
2641
2642	for (PPGMRAMRANGE pCur = pVM->pgm.s.pRamRangesR3; pCur; pCur = pCur->pNextR3)
2643	pHlp->pfnPrintf(pHlp,
2644	"%RGp-%RGp %RHv %s\n",
2645	pCur->GCPhys,
2646	pCur->GCPhysLast,
2647	pCur->pvR3,
2648	pCur->pszDesc);
2649	}
2650
2651	/**
2652	* Dump the page directory to the log.
2653	*
2654	* @param pVM VM Handle.
2655	* @param pHlp The info helpers.
2656	* @param pszArgs Arguments, ignored.
2657	*/
2658	static DECLCALLBACK(void) pgmR3InfoCr3(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2659	{
2660	/** @todo fix this! Convert the PGMR3DumpHierarchyHC functions to do guest stuff. */
2661	/* Big pages supported? */
2662	const bool fPSE = !!(CPUMGetGuestCR4(pVM) & X86_CR4_PSE);
2663
2664	/* Global pages supported? */
2665	const bool fPGE = !!(CPUMGetGuestCR4(pVM) & X86_CR4_PGE);
2666
2667	NOREF(pszArgs);
2668
2669	/*
2670	* Get page directory addresses.
2671	*/
2672	PX86PD pPDSrc = pVM->pgm.s.pGst32BitPdR3;
2673	Assert(pPDSrc);
2674	Assert(PGMPhysGCPhys2R3PtrAssert(pVM, (RTGCPHYS)(CPUMGetGuestCR3(pVM) & X86_CR3_PAGE_MASK), sizeof(*pPDSrc)) == pPDSrc);
2675
2676	/*
2677	* Iterate the page directory.
2678	*/
2679	for (unsigned iPD = 0; iPD < RT_ELEMENTS(pPDSrc->a); iPD++)
2680	{
2681	X86PDE PdeSrc = pPDSrc->a[iPD];
2682	if (PdeSrc.n.u1Present)
2683	{
2684	if (PdeSrc.b.u1Size && fPSE)
2685	pHlp->pfnPrintf(pHlp,
2686	"%04X - %RGp P=%d U=%d RW=%d G=%d - BIG\n",
2687	iPD,
2688	pgmGstGet4MBPhysPage(&pVM->pgm.s, PdeSrc),
2689	PdeSrc.b.u1Present, PdeSrc.b.u1User, PdeSrc.b.u1Write, PdeSrc.b.u1Global && fPGE);
2690	else
2691	pHlp->pfnPrintf(pHlp,
2692	"%04X - %RGp P=%d U=%d RW=%d [G=%d]\n",
2693	iPD,
2694	(RTGCPHYS)(PdeSrc.u & X86_PDE_PG_MASK),
2695	PdeSrc.n.u1Present, PdeSrc.n.u1User, PdeSrc.n.u1Write, PdeSrc.b.u1Global && fPGE);
2696	}
2697	}
2698	}
2699
2700
2701	/**
2702	* Serivce a VMMCALLHOST_PGM_LOCK call.
2703	*
2704	* @returns VBox status code.
2705	* @param pVM The VM handle.
2706	*/
2707	VMMR3DECL(int) PGMR3LockCall(PVM pVM)
2708	{
2709	int rc = PDMR3CritSectEnterEx(&pVM->pgm.s.CritSect, true /* fHostCall */);
2710	AssertRC(rc);
2711	return rc;
2712	}
2713
2714
2715	/**
2716	* Converts a PGMMODE value to a PGM_TYPE_* \#define.
2717	*
2718	* @returns PGM_TYPE_*.
2719	* @param pgmMode The mode value to convert.
2720	*/
2721	DECLINLINE(unsigned) pgmModeToType(PGMMODE pgmMode)
2722	{
2723	switch (pgmMode)
2724	{
2725	case PGMMODE_REAL: return PGM_TYPE_REAL;
2726	case PGMMODE_PROTECTED: return PGM_TYPE_PROT;
2727	case PGMMODE_32_BIT: return PGM_TYPE_32BIT;
2728	case PGMMODE_PAE:
2729	case PGMMODE_PAE_NX: return PGM_TYPE_PAE;
2730	case PGMMODE_AMD64:
2731	case PGMMODE_AMD64_NX: return PGM_TYPE_AMD64;
2732	case PGMMODE_NESTED: return PGM_TYPE_NESTED;
2733	case PGMMODE_EPT: return PGM_TYPE_EPT;
2734	default:
2735	AssertFatalMsgFailed(("pgmMode=%d\n", pgmMode));
2736	}
2737	}
2738
2739
2740	/**
2741	* Gets the index into the paging mode data array of a SHW+GST mode.
2742	*
2743	* @returns PGM::paPagingData index.
2744	* @param uShwType The shadow paging mode type.
2745	* @param uGstType The guest paging mode type.
2746	*/
2747	DECLINLINE(unsigned) pgmModeDataIndex(unsigned uShwType, unsigned uGstType)
2748	{
2749	Assert(uShwType >= PGM_TYPE_32BIT && uShwType <= PGM_TYPE_MAX);
2750	Assert(uGstType >= PGM_TYPE_REAL && uGstType <= PGM_TYPE_AMD64);
2751	return (uShwType - PGM_TYPE_32BIT) * (PGM_TYPE_AMD64 - PGM_TYPE_REAL + 1)
2752	+ (uGstType - PGM_TYPE_REAL);
2753	}
2754
2755
2756	/**
2757	* Gets the index into the paging mode data array of a SHW+GST mode.
2758	*
2759	* @returns PGM::paPagingData index.
2760	* @param enmShw The shadow paging mode.
2761	* @param enmGst The guest paging mode.
2762	*/
2763	DECLINLINE(unsigned) pgmModeDataIndexByMode(PGMMODE enmShw, PGMMODE enmGst)
2764	{
2765	Assert(enmShw >= PGMMODE_32_BIT && enmShw <= PGMMODE_MAX);
2766	Assert(enmGst > PGMMODE_INVALID && enmGst < PGMMODE_MAX);
2767	return pgmModeDataIndex(pgmModeToType(enmShw), pgmModeToType(enmGst));
2768	}
2769
2770
2771	/**
2772	* Calculates the max data index.
2773	* @returns The number of entries in the paging data array.
2774	*/
2775	DECLINLINE(unsigned) pgmModeDataMaxIndex(void)
2776	{
2777	return pgmModeDataIndex(PGM_TYPE_MAX, PGM_TYPE_AMD64) + 1;
2778	}
2779
2780
2781	/**
2782	* Initializes the paging mode data kept in PGM::paModeData.
2783	*
2784	* @param pVM The VM handle.
2785	* @param fResolveGCAndR0 Indicate whether or not GC and Ring-0 symbols can be resolved now.
2786	* This is used early in the init process to avoid trouble with PDM
2787	* not being initialized yet.
2788	*/
2789	static int pgmR3ModeDataInit(PVM pVM, bool fResolveGCAndR0)
2790	{
2791	PPGMMODEDATA pModeData;
2792	int rc;
2793
2794	/*
2795	* Allocate the array on the first call.
2796	*/
2797	if (!pVM->pgm.s.paModeData)
2798	{
2799	pVM->pgm.s.paModeData = (PPGMMODEDATA)MMR3HeapAllocZ(pVM, MM_TAG_PGM, sizeof(PGMMODEDATA) * pgmModeDataMaxIndex());
2800	AssertReturn(pVM->pgm.s.paModeData, VERR_NO_MEMORY);
2801	}
2802
2803	/*
2804	* Initialize the array entries.
2805	*/
2806	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_32BIT, PGM_TYPE_REAL)];
2807	pModeData->uShwType = PGM_TYPE_32BIT;
2808	pModeData->uGstType = PGM_TYPE_REAL;
2809	rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2810	rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2811	rc = PGM_BTH_NAME_32BIT_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2812
2813	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_32BIT, PGMMODE_PROTECTED)];
2814	pModeData->uShwType = PGM_TYPE_32BIT;
2815	pModeData->uGstType = PGM_TYPE_PROT;
2816	rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2817	rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2818	rc = PGM_BTH_NAME_32BIT_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2819
2820	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_32BIT, PGM_TYPE_32BIT)];
2821	pModeData->uShwType = PGM_TYPE_32BIT;
2822	pModeData->uGstType = PGM_TYPE_32BIT;
2823	rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2824	rc = PGM_GST_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2825	rc = PGM_BTH_NAME_32BIT_32BIT(InitData)(pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2826
2827	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_REAL)];
2828	pModeData->uShwType = PGM_TYPE_PAE;
2829	pModeData->uGstType = PGM_TYPE_REAL;
2830	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2831	rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2832	rc = PGM_BTH_NAME_PAE_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2833
2834	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_PROT)];
2835	pModeData->uShwType = PGM_TYPE_PAE;
2836	pModeData->uGstType = PGM_TYPE_PROT;
2837	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2838	rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2839	rc = PGM_BTH_NAME_PAE_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2840
2841	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_32BIT)];
2842	pModeData->uShwType = PGM_TYPE_PAE;
2843	pModeData->uGstType = PGM_TYPE_32BIT;
2844	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2845	rc = PGM_GST_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2846	rc = PGM_BTH_NAME_PAE_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2847
2848	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_PAE)];
2849	pModeData->uShwType = PGM_TYPE_PAE;
2850	pModeData->uGstType = PGM_TYPE_PAE;
2851	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2852	rc = PGM_GST_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2853	rc = PGM_BTH_NAME_PAE_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2854
2855	#ifdef VBOX_WITH_64_BITS_GUESTS
2856	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_AMD64, PGM_TYPE_AMD64)];
2857	pModeData->uShwType = PGM_TYPE_AMD64;
2858	pModeData->uGstType = PGM_TYPE_AMD64;
2859	rc = PGM_SHW_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2860	rc = PGM_GST_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2861	rc = PGM_BTH_NAME_AMD64_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2862	#endif
2863
2864	/* The nested paging mode. */
2865	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_REAL)];
2866	pModeData->uShwType = PGM_TYPE_NESTED;
2867	pModeData->uGstType = PGM_TYPE_REAL;
2868	rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2869	rc = PGM_BTH_NAME_NESTED_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2870
2871	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGMMODE_PROTECTED)];
2872	pModeData->uShwType = PGM_TYPE_NESTED;
2873	pModeData->uGstType = PGM_TYPE_PROT;
2874	rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2875	rc = PGM_BTH_NAME_NESTED_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2876
2877	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_32BIT)];
2878	pModeData->uShwType = PGM_TYPE_NESTED;
2879	pModeData->uGstType = PGM_TYPE_32BIT;
2880	rc = PGM_GST_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2881	rc = PGM_BTH_NAME_NESTED_32BIT(InitData)(pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2882
2883	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_PAE)];
2884	pModeData->uShwType = PGM_TYPE_NESTED;
2885	pModeData->uGstType = PGM_TYPE_PAE;
2886	rc = PGM_GST_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2887	rc = PGM_BTH_NAME_NESTED_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2888
2889	#ifdef VBOX_WITH_64_BITS_GUESTS
2890	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_AMD64)];
2891	pModeData->uShwType = PGM_TYPE_NESTED;
2892	pModeData->uGstType = PGM_TYPE_AMD64;
2893	rc = PGM_GST_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2894	rc = PGM_BTH_NAME_NESTED_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2895	#endif
2896
2897	/* The shadow part of the nested callback mode depends on the host paging mode (AMD-V only). */
2898	switch (pVM->pgm.s.enmHostMode)
2899	{
2900	#if HC_ARCH_BITS == 32
2901	case SUPPAGINGMODE_32_BIT:
2902	case SUPPAGINGMODE_32_BIT_GLOBAL:
2903	for (unsigned i = PGM_TYPE_REAL; i <= PGM_TYPE_PAE; i++)
2904	{
2905	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, i)];
2906	rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2907	}
2908	# ifdef VBOX_WITH_64_BITS_GUESTS
2909	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_AMD64)];
2910	rc = PGM_SHW_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2911	# endif
2912	break;
2913
2914	case SUPPAGINGMODE_PAE:
2915	case SUPPAGINGMODE_PAE_NX:
2916	case SUPPAGINGMODE_PAE_GLOBAL:
2917	case SUPPAGINGMODE_PAE_GLOBAL_NX:
2918	for (unsigned i = PGM_TYPE_REAL; i <= PGM_TYPE_PAE; i++)
2919	{
2920	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, i)];
2921	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2922	}
2923	# ifdef VBOX_WITH_64_BITS_GUESTS
2924	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_AMD64)];
2925	rc = PGM_SHW_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2926	# endif
2927	break;
2928	#endif /* HC_ARCH_BITS == 32 */
2929
2930	#if HC_ARCH_BITS == 64 \|\| defined(RT_OS_DARWIN)
2931	case SUPPAGINGMODE_AMD64:
2932	case SUPPAGINGMODE_AMD64_GLOBAL:
2933	case SUPPAGINGMODE_AMD64_NX:
2934	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
2935	# ifdef VBOX_WITH_64_BITS_GUESTS
2936	for (unsigned i = PGM_TYPE_REAL; i <= PGM_TYPE_AMD64; i++)
2937	# else
2938	for (unsigned i = PGM_TYPE_REAL; i <= PGM_TYPE_PAE; i++)
2939	# endif
2940	{
2941	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, i)];
2942	rc = PGM_SHW_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2943	}
2944	break;
2945	#endif /* HC_ARCH_BITS == 64 \|\| RT_OS_DARWIN */
2946
2947	default:
2948	AssertFailed();
2949	break;
2950	}
2951
2952	/* Extended paging (EPT) / Intel VT-x */
2953	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_REAL)];
2954	pModeData->uShwType = PGM_TYPE_EPT;
2955	pModeData->uGstType = PGM_TYPE_REAL;
2956	rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2957	rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2958	rc = PGM_BTH_NAME_EPT_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2959
2960	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_PROT)];
2961	pModeData->uShwType = PGM_TYPE_EPT;
2962	pModeData->uGstType = PGM_TYPE_PROT;
2963	rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2964	rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2965	rc = PGM_BTH_NAME_EPT_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2966
2967	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_32BIT)];
2968	pModeData->uShwType = PGM_TYPE_EPT;
2969	pModeData->uGstType = PGM_TYPE_32BIT;
2970	rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2971	rc = PGM_GST_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2972	rc = PGM_BTH_NAME_EPT_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2973
2974	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_PAE)];
2975	pModeData->uShwType = PGM_TYPE_EPT;
2976	pModeData->uGstType = PGM_TYPE_PAE;
2977	rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2978	rc = PGM_GST_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2979	rc = PGM_BTH_NAME_EPT_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2980
2981	#ifdef VBOX_WITH_64_BITS_GUESTS
2982	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_AMD64)];
2983	pModeData->uShwType = PGM_TYPE_EPT;
2984	pModeData->uGstType = PGM_TYPE_AMD64;
2985	rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2986	rc = PGM_GST_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2987	rc = PGM_BTH_NAME_EPT_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2988	#endif
2989	return VINF_SUCCESS;
2990	}
2991
2992
2993	/**
2994	* Switch to different (or relocated in the relocate case) mode data.
2995	*
2996	* @param pVM The VM handle.
2997	* @param enmShw The the shadow paging mode.
2998	* @param enmGst The the guest paging mode.
2999	*/
3000	static void pgmR3ModeDataSwitch(PVM pVM, PGMMODE enmShw, PGMMODE enmGst)
3001	{
3002	PPGMMODEDATA pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndexByMode(enmShw, enmGst)];
3003
3004	Assert(pModeData->uGstType == pgmModeToType(enmGst));
3005	Assert(pModeData->uShwType == pgmModeToType(enmShw));
3006
3007	/* shadow */
3008	pVM->pgm.s.pfnR3ShwRelocate = pModeData->pfnR3ShwRelocate;
3009	pVM->pgm.s.pfnR3ShwExit = pModeData->pfnR3ShwExit;
3010	pVM->pgm.s.pfnR3ShwGetPage = pModeData->pfnR3ShwGetPage;
3011	Assert(pVM->pgm.s.pfnR3ShwGetPage);
3012	pVM->pgm.s.pfnR3ShwModifyPage = pModeData->pfnR3ShwModifyPage;
3013
3014	pVM->pgm.s.pfnRCShwGetPage = pModeData->pfnRCShwGetPage;
3015	pVM->pgm.s.pfnRCShwModifyPage = pModeData->pfnRCShwModifyPage;
3016
3017	pVM->pgm.s.pfnR0ShwGetPage = pModeData->pfnR0ShwGetPage;
3018	pVM->pgm.s.pfnR0ShwModifyPage = pModeData->pfnR0ShwModifyPage;
3019
3020
3021	/* guest */
3022	pVM->pgm.s.pfnR3GstRelocate = pModeData->pfnR3GstRelocate;
3023	pVM->pgm.s.pfnR3GstExit = pModeData->pfnR3GstExit;
3024	pVM->pgm.s.pfnR3GstGetPage = pModeData->pfnR3GstGetPage;
3025	Assert(pVM->pgm.s.pfnR3GstGetPage);
3026	pVM->pgm.s.pfnR3GstModifyPage = pModeData->pfnR3GstModifyPage;
3027	pVM->pgm.s.pfnR3GstGetPDE = pModeData->pfnR3GstGetPDE;
3028	#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
3029	pVM->pgm.s.pfnR3GstMonitorCR3 = pModeData->pfnR3GstMonitorCR3;
3030	pVM->pgm.s.pfnR3GstUnmonitorCR3 = pModeData->pfnR3GstUnmonitorCR3;
3031	#endif
3032	pVM->pgm.s.pfnR3GstMapCR3 = pModeData->pfnR3GstMapCR3;
3033	pVM->pgm.s.pfnR3GstUnmapCR3 = pModeData->pfnR3GstUnmapCR3;
3034	#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
3035	pVM->pgm.s.pfnR3GstWriteHandlerCR3 = pModeData->pfnR3GstWriteHandlerCR3;
3036	pVM->pgm.s.pszR3GstWriteHandlerCR3 = pModeData->pszR3GstWriteHandlerCR3;
3037	pVM->pgm.s.pfnR3GstPAEWriteHandlerCR3 = pModeData->pfnR3GstPAEWriteHandlerCR3;
3038	pVM->pgm.s.pszR3GstPAEWriteHandlerCR3 = pModeData->pszR3GstPAEWriteHandlerCR3;
3039	#endif
3040	pVM->pgm.s.pfnRCGstGetPage = pModeData->pfnRCGstGetPage;
3041	pVM->pgm.s.pfnRCGstModifyPage = pModeData->pfnRCGstModifyPage;
3042	pVM->pgm.s.pfnRCGstGetPDE = pModeData->pfnRCGstGetPDE;
3043	#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
3044	pVM->pgm.s.pfnRCGstMonitorCR3 = pModeData->pfnRCGstMonitorCR3;
3045	pVM->pgm.s.pfnRCGstUnmonitorCR3 = pModeData->pfnRCGstUnmonitorCR3;
3046	#endif
3047	pVM->pgm.s.pfnRCGstMapCR3 = pModeData->pfnRCGstMapCR3;
3048	pVM->pgm.s.pfnRCGstUnmapCR3 = pModeData->pfnRCGstUnmapCR3;
3049	#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
3050	pVM->pgm.s.pfnRCGstWriteHandlerCR3 = pModeData->pfnRCGstWriteHandlerCR3;
3051	pVM->pgm.s.pfnRCGstPAEWriteHandlerCR3 = pModeData->pfnRCGstPAEWriteHandlerCR3;
3052	#endif
3053	pVM->pgm.s.pfnR0GstGetPage = pModeData->pfnR0GstGetPage;
3054	pVM->pgm.s.pfnR0GstModifyPage = pModeData->pfnR0GstModifyPage;
3055	pVM->pgm.s.pfnR0GstGetPDE = pModeData->pfnR0GstGetPDE;
3056	#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
3057	pVM->pgm.s.pfnR0GstMonitorCR3 = pModeData->pfnR0GstMonitorCR3;
3058	pVM->pgm.s.pfnR0GstUnmonitorCR3 = pModeData->pfnR0GstUnmonitorCR3;
3059	#endif
3060	pVM->pgm.s.pfnR0GstMapCR3 = pModeData->pfnR0GstMapCR3;
3061	pVM->pgm.s.pfnR0GstUnmapCR3 = pModeData->pfnR0GstUnmapCR3;
3062	#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
3063	pVM->pgm.s.pfnR0GstWriteHandlerCR3 = pModeData->pfnR0GstWriteHandlerCR3;
3064	pVM->pgm.s.pfnR0GstPAEWriteHandlerCR3 = pModeData->pfnR0GstPAEWriteHandlerCR3;
3065	#endif
3066
3067	/* both */
3068	pVM->pgm.s.pfnR3BthRelocate = pModeData->pfnR3BthRelocate;
3069	pVM->pgm.s.pfnR3BthInvalidatePage = pModeData->pfnR3BthInvalidatePage;
3070	pVM->pgm.s.pfnR3BthSyncCR3 = pModeData->pfnR3BthSyncCR3;
3071	Assert(pVM->pgm.s.pfnR3BthSyncCR3);
3072	pVM->pgm.s.pfnR3BthSyncPage = pModeData->pfnR3BthSyncPage;
3073	pVM->pgm.s.pfnR3BthPrefetchPage = pModeData->pfnR3BthPrefetchPage;
3074	pVM->pgm.s.pfnR3BthVerifyAccessSyncPage = pModeData->pfnR3BthVerifyAccessSyncPage;
3075	#ifdef VBOX_STRICT
3076	pVM->pgm.s.pfnR3BthAssertCR3 = pModeData->pfnR3BthAssertCR3;
3077	#endif
3078
3079	pVM->pgm.s.pfnRCBthTrap0eHandler = pModeData->pfnRCBthTrap0eHandler;
3080	pVM->pgm.s.pfnRCBthInvalidatePage = pModeData->pfnRCBthInvalidatePage;
3081	pVM->pgm.s.pfnRCBthSyncCR3 = pModeData->pfnRCBthSyncCR3;
3082	pVM->pgm.s.pfnRCBthSyncPage = pModeData->pfnRCBthSyncPage;
3083	pVM->pgm.s.pfnRCBthPrefetchPage = pModeData->pfnRCBthPrefetchPage;
3084	pVM->pgm.s.pfnRCBthVerifyAccessSyncPage = pModeData->pfnRCBthVerifyAccessSyncPage;
3085	#ifdef VBOX_STRICT
3086	pVM->pgm.s.pfnRCBthAssertCR3 = pModeData->pfnRCBthAssertCR3;
3087	#endif
3088
3089	pVM->pgm.s.pfnR0BthTrap0eHandler = pModeData->pfnR0BthTrap0eHandler;
3090	pVM->pgm.s.pfnR0BthInvalidatePage = pModeData->pfnR0BthInvalidatePage;
3091	pVM->pgm.s.pfnR0BthSyncCR3 = pModeData->pfnR0BthSyncCR3;
3092	pVM->pgm.s.pfnR0BthSyncPage = pModeData->pfnR0BthSyncPage;
3093	pVM->pgm.s.pfnR0BthPrefetchPage = pModeData->pfnR0BthPrefetchPage;
3094	pVM->pgm.s.pfnR0BthVerifyAccessSyncPage = pModeData->pfnR0BthVerifyAccessSyncPage;
3095	#ifdef VBOX_STRICT
3096	pVM->pgm.s.pfnR0BthAssertCR3 = pModeData->pfnR0BthAssertCR3;
3097	#endif
3098	}
3099
3100
3101	/**
3102	* Calculates the shadow paging mode.
3103	*
3104	* @returns The shadow paging mode.
3105	* @param pVM VM handle.
3106	* @param enmGuestMode The guest mode.
3107	* @param enmHostMode The host mode.
3108	* @param enmShadowMode The current shadow mode.
3109	* @param penmSwitcher Where to store the switcher to use.
3110	* VMMSWITCHER_INVALID means no change.
3111	*/
3112	static PGMMODE pgmR3CalcShadowMode(PVM pVM, PGMMODE enmGuestMode, SUPPAGINGMODE enmHostMode, PGMMODE enmShadowMode, VMMSWITCHER *penmSwitcher)
3113	{
3114	VMMSWITCHER enmSwitcher = VMMSWITCHER_INVALID;
3115	switch (enmGuestMode)
3116	{
3117	/*
3118	* When switching to real or protected mode we don't change
3119	* anything since it's likely that we'll switch back pretty soon.
3120	*
3121	* During pgmR3InitPaging we'll end up here with PGMMODE_INVALID
3122	* and is supposed to determine which shadow paging and switcher to
3123	* use during init.
3124	*/
3125	case PGMMODE_REAL:
3126	case PGMMODE_PROTECTED:
3127	if ( enmShadowMode != PGMMODE_INVALID
3128	&& !HWACCMIsEnabled(pVM) /* always switch in hwaccm mode! */)
3129	break; /* (no change) */
3130
3131	switch (enmHostMode)
3132	{
3133	case SUPPAGINGMODE_32_BIT:
3134	case SUPPAGINGMODE_32_BIT_GLOBAL:
3135	enmShadowMode = PGMMODE_32_BIT;
3136	enmSwitcher = VMMSWITCHER_32_TO_32;
3137	break;
3138
3139	case SUPPAGINGMODE_PAE:
3140	case SUPPAGINGMODE_PAE_NX:
3141	case SUPPAGINGMODE_PAE_GLOBAL:
3142	case SUPPAGINGMODE_PAE_GLOBAL_NX:
3143	enmShadowMode = PGMMODE_PAE;
3144	enmSwitcher = VMMSWITCHER_PAE_TO_PAE;
3145	#ifdef DEBUG_bird
3146	if (RTEnvExist("VBOX_32BIT"))
3147	{
3148	enmShadowMode = PGMMODE_32_BIT;
3149	enmSwitcher = VMMSWITCHER_PAE_TO_32;
3150	}
3151	#endif
3152	break;
3153
3154	case SUPPAGINGMODE_AMD64:
3155	case SUPPAGINGMODE_AMD64_GLOBAL:
3156	case SUPPAGINGMODE_AMD64_NX:
3157	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
3158	enmShadowMode = PGMMODE_PAE;
3159	enmSwitcher = VMMSWITCHER_AMD64_TO_PAE;
3160	#ifdef DEBUG_bird
3161	if (RTEnvExist("VBOX_32BIT"))
3162	{
3163	enmShadowMode = PGMMODE_32_BIT;
3164	enmSwitcher = VMMSWITCHER_AMD64_TO_32;
3165	}
3166	#endif
3167	break;
3168
3169	default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
3170	}
3171	break;
3172
3173	case PGMMODE_32_BIT:
3174	switch (enmHostMode)
3175	{
3176	case SUPPAGINGMODE_32_BIT:
3177	case SUPPAGINGMODE_32_BIT_GLOBAL:
3178	enmShadowMode = PGMMODE_32_BIT;
3179	enmSwitcher = VMMSWITCHER_32_TO_32;
3180	break;
3181
3182	case SUPPAGINGMODE_PAE:
3183	case SUPPAGINGMODE_PAE_NX:
3184	case SUPPAGINGMODE_PAE_GLOBAL:
3185	case SUPPAGINGMODE_PAE_GLOBAL_NX:
3186	enmShadowMode = PGMMODE_PAE;
3187	enmSwitcher = VMMSWITCHER_PAE_TO_PAE;
3188	#ifdef DEBUG_bird
3189	if (RTEnvExist("VBOX_32BIT"))
3190	{
3191	enmShadowMode = PGMMODE_32_BIT;
3192	enmSwitcher = VMMSWITCHER_PAE_TO_32;
3193	}
3194	#endif
3195	break;
3196
3197	case SUPPAGINGMODE_AMD64:
3198	case SUPPAGINGMODE_AMD64_GLOBAL:
3199	case SUPPAGINGMODE_AMD64_NX:
3200	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
3201	enmShadowMode = PGMMODE_PAE;
3202	enmSwitcher = VMMSWITCHER_AMD64_TO_PAE;
3203	#ifdef DEBUG_bird
3204	if (RTEnvExist("VBOX_32BIT"))
3205	{
3206	enmShadowMode = PGMMODE_32_BIT;
3207	enmSwitcher = VMMSWITCHER_AMD64_TO_32;
3208	}
3209	#endif
3210	break;
3211
3212	default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
3213	}
3214	break;
3215
3216	case PGMMODE_PAE:
3217	case PGMMODE_PAE_NX: /** @todo This might require more switchers and guest+both modes. */
3218	switch (enmHostMode)
3219	{
3220	case SUPPAGINGMODE_32_BIT:
3221	case SUPPAGINGMODE_32_BIT_GLOBAL:
3222	enmShadowMode = PGMMODE_PAE;
3223	enmSwitcher = VMMSWITCHER_32_TO_PAE;
3224	break;
3225
3226	case SUPPAGINGMODE_PAE:
3227	case SUPPAGINGMODE_PAE_NX:
3228	case SUPPAGINGMODE_PAE_GLOBAL:
3229	case SUPPAGINGMODE_PAE_GLOBAL_NX:
3230	enmShadowMode = PGMMODE_PAE;
3231	enmSwitcher = VMMSWITCHER_PAE_TO_PAE;
3232	break;
3233
3234	case SUPPAGINGMODE_AMD64:
3235	case SUPPAGINGMODE_AMD64_GLOBAL:
3236	case SUPPAGINGMODE_AMD64_NX:
3237	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
3238	enmShadowMode = PGMMODE_PAE;
3239	enmSwitcher = VMMSWITCHER_AMD64_TO_PAE;
3240	break;
3241
3242	default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
3243	}
3244	break;
3245
3246	case PGMMODE_AMD64:
3247	case PGMMODE_AMD64_NX:
3248	switch (enmHostMode)
3249	{
3250	case SUPPAGINGMODE_32_BIT:
3251	case SUPPAGINGMODE_32_BIT_GLOBAL:
3252	enmShadowMode = PGMMODE_AMD64;
3253	enmSwitcher = VMMSWITCHER_32_TO_AMD64;
3254	break;
3255
3256	case SUPPAGINGMODE_PAE:
3257	case SUPPAGINGMODE_PAE_NX:
3258	case SUPPAGINGMODE_PAE_GLOBAL:
3259	case SUPPAGINGMODE_PAE_GLOBAL_NX:
3260	enmShadowMode = PGMMODE_AMD64;
3261	enmSwitcher = VMMSWITCHER_PAE_TO_AMD64;
3262	break;
3263
3264	case SUPPAGINGMODE_AMD64:
3265	case SUPPAGINGMODE_AMD64_GLOBAL:
3266	case SUPPAGINGMODE_AMD64_NX:
3267	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
3268	enmShadowMode = PGMMODE_AMD64;
3269	enmSwitcher = VMMSWITCHER_AMD64_TO_AMD64;
3270	break;
3271
3272	default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
3273	}
3274	break;
3275
3276
3277	default:
3278	AssertReleaseMsgFailed(("enmGuestMode=%d\n", enmGuestMode));
3279	return PGMMODE_INVALID;
3280	}
3281	/* Override the shadow mode is nested paging is active. */
3282	if (HWACCMIsNestedPagingActive(pVM))
3283	enmShadowMode = HWACCMGetShwPagingMode(pVM);
3284
3285	*penmSwitcher = enmSwitcher;
3286	return enmShadowMode;
3287	}
3288
3289
3290	/**
3291	* Performs the actual mode change.
3292	* This is called by PGMChangeMode and pgmR3InitPaging().
3293	*
3294	* @returns VBox status code.
3295	* @param pVM VM handle.
3296	* @param enmGuestMode The new guest mode. This is assumed to be different from
3297	* the current mode.
3298	*/
3299	VMMR3DECL(int) PGMR3ChangeMode(PVM pVM, PGMMODE enmGuestMode)
3300	{
3301	Log(("PGMR3ChangeMode: Guest mode: %s -> %s\n", PGMGetModeName(pVM->pgm.s.enmGuestMode), PGMGetModeName(enmGuestMode)));
3302	STAM_REL_COUNTER_INC(&pVM->pgm.s.cGuestModeChanges);
3303
3304	/*
3305	* Calc the shadow mode and switcher.
3306	*/
3307	VMMSWITCHER enmSwitcher;
3308	PGMMODE enmShadowMode = pgmR3CalcShadowMode(pVM, enmGuestMode, pVM->pgm.s.enmHostMode, pVM->pgm.s.enmShadowMode, &enmSwitcher);
3309	if (enmSwitcher != VMMSWITCHER_INVALID)
3310	{
3311	/*
3312	* Select new switcher.
3313	*/
3314	int rc = VMMR3SelectSwitcher(pVM, enmSwitcher);
3315	if (RT_FAILURE(rc))
3316	{
3317	AssertReleaseMsgFailed(("VMMR3SelectSwitcher(%d) -> %Rrc\n", enmSwitcher, rc));
3318	return rc;
3319	}
3320	}
3321
3322	/*
3323	* Exit old mode(s).
3324	*/
3325	/* shadow */
3326	if (enmShadowMode != pVM->pgm.s.enmShadowMode)
3327	{
3328	LogFlow(("PGMR3ChangeMode: Shadow mode: %s -> %s\n", PGMGetModeName(pVM->pgm.s.enmShadowMode), PGMGetModeName(enmShadowMode)));
3329	if (PGM_SHW_PFN(Exit, pVM))
3330	{
3331	int rc = PGM_SHW_PFN(Exit, pVM)(pVM);
3332	if (RT_FAILURE(rc))
3333	{
3334	AssertMsgFailed(("Exit failed for shadow mode %d: %Rrc\n", pVM->pgm.s.enmShadowMode, rc));
3335	return rc;
3336	}
3337	}
3338
3339	}
3340	else
3341	LogFlow(("PGMR3ChangeMode: Shadow mode remains: %s\n", PGMGetModeName(pVM->pgm.s.enmShadowMode)));
3342
3343	/* guest */
3344	if (PGM_GST_PFN(Exit, pVM))
3345	{
3346	int rc = PGM_GST_PFN(Exit, pVM)(pVM);
3347	if (RT_FAILURE(rc))
3348	{
3349	AssertMsgFailed(("Exit failed for guest mode %d: %Rrc\n", pVM->pgm.s.enmGuestMode, rc));
3350	return rc;
3351	}
3352	}
3353
3354	/*
3355	* Load new paging mode data.
3356	*/
3357	pgmR3ModeDataSwitch(pVM, enmShadowMode, enmGuestMode);
3358
3359	/*
3360	* Enter new shadow mode (if changed).
3361	*/
3362	if (enmShadowMode != pVM->pgm.s.enmShadowMode)
3363	{
3364	int rc;
3365	pVM->pgm.s.enmShadowMode = enmShadowMode;
3366	switch (enmShadowMode)
3367	{
3368	case PGMMODE_32_BIT:
3369	rc = PGM_SHW_NAME_32BIT(Enter)(pVM);
3370	break;
3371	case PGMMODE_PAE:
3372	case PGMMODE_PAE_NX:
3373	rc = PGM_SHW_NAME_PAE(Enter)(pVM);
3374	break;
3375	case PGMMODE_AMD64:
3376	case PGMMODE_AMD64_NX:
3377	rc = PGM_SHW_NAME_AMD64(Enter)(pVM);
3378	break;
3379	case PGMMODE_NESTED:
3380	rc = PGM_SHW_NAME_NESTED(Enter)(pVM);
3381	break;
3382	case PGMMODE_EPT:
3383	rc = PGM_SHW_NAME_EPT(Enter)(pVM);
3384	break;
3385	case PGMMODE_REAL:
3386	case PGMMODE_PROTECTED:
3387	default:
3388	AssertReleaseMsgFailed(("enmShadowMode=%d\n", enmShadowMode));
3389	return VERR_INTERNAL_ERROR;
3390	}
3391	if (RT_FAILURE(rc))
3392	{
3393	AssertReleaseMsgFailed(("Entering enmShadowMode=%d failed: %Rrc\n", enmShadowMode, rc));
3394	pVM->pgm.s.enmShadowMode = PGMMODE_INVALID;
3395	return rc;
3396	}
3397	}
3398
3399	/** @todo This is a bug!
3400	*
3401	* We must flush the PGM pool cache if the guest mode changes; we don't always
3402	* switch shadow paging mode (e.g. protected->32-bit) and shouldn't reuse
3403	* the shadow page tables.
3404	*
3405	* That only applies when switching between paging and non-paging modes.
3406	*/
3407	/** @todo A20 setting */
3408	if ( pVM->pgm.s.CTX_SUFF(pPool)
3409	&& !HWACCMIsNestedPagingActive(pVM)
3410	&& PGMMODE_WITH_PAGING(pVM->pgm.s.enmGuestMode) != PGMMODE_WITH_PAGING(enmGuestMode))
3411	{
3412	Log(("PGMR3ChangeMode: changing guest paging mode -> flush pgm pool cache!\n"));
3413	pgmPoolFlushAll(pVM);
3414	}
3415
3416	/*
3417	* Enter the new guest and shadow+guest modes.
3418	*/
3419	int rc = -1;
3420	int rc2 = -1;
3421	RTGCPHYS GCPhysCR3 = NIL_RTGCPHYS;
3422	pVM->pgm.s.enmGuestMode = enmGuestMode;
3423	switch (enmGuestMode)
3424	{
3425	case PGMMODE_REAL:
3426	rc = PGM_GST_NAME_REAL(Enter)(pVM, NIL_RTGCPHYS);
3427	switch (pVM->pgm.s.enmShadowMode)
3428	{
3429	case PGMMODE_32_BIT:
3430	rc2 = PGM_BTH_NAME_32BIT_REAL(Enter)(pVM, NIL_RTGCPHYS);
3431	break;
3432	case PGMMODE_PAE:
3433	case PGMMODE_PAE_NX:
3434	rc2 = PGM_BTH_NAME_PAE_REAL(Enter)(pVM, NIL_RTGCPHYS);
3435	break;
3436	case PGMMODE_NESTED:
3437	rc2 = PGM_BTH_NAME_NESTED_REAL(Enter)(pVM, NIL_RTGCPHYS);
3438	break;
3439	case PGMMODE_EPT:
3440	rc2 = PGM_BTH_NAME_EPT_REAL(Enter)(pVM, NIL_RTGCPHYS);
3441	break;
3442	case PGMMODE_AMD64:
3443	case PGMMODE_AMD64_NX:
3444	AssertMsgFailed(("Should use PAE shadow mode!\n"));
3445	default: AssertFailed(); break;
3446	}
3447	break;
3448
3449	case PGMMODE_PROTECTED:
3450	rc = PGM_GST_NAME_PROT(Enter)(pVM, NIL_RTGCPHYS);
3451	switch (pVM->pgm.s.enmShadowMode)
3452	{
3453	case PGMMODE_32_BIT:
3454	rc2 = PGM_BTH_NAME_32BIT_PROT(Enter)(pVM, NIL_RTGCPHYS);
3455	break;
3456	case PGMMODE_PAE:
3457	case PGMMODE_PAE_NX:
3458	rc2 = PGM_BTH_NAME_PAE_PROT(Enter)(pVM, NIL_RTGCPHYS);
3459	break;
3460	case PGMMODE_NESTED:
3461	rc2 = PGM_BTH_NAME_NESTED_PROT(Enter)(pVM, NIL_RTGCPHYS);
3462	break;
3463	case PGMMODE_EPT:
3464	rc2 = PGM_BTH_NAME_EPT_PROT(Enter)(pVM, NIL_RTGCPHYS);
3465	break;
3466	case PGMMODE_AMD64:
3467	case PGMMODE_AMD64_NX:
3468	AssertMsgFailed(("Should use PAE shadow mode!\n"));
3469	default: AssertFailed(); break;
3470	}
3471	break;
3472
3473	case PGMMODE_32_BIT:
3474	GCPhysCR3 = CPUMGetGuestCR3(pVM) & X86_CR3_PAGE_MASK;
3475	rc = PGM_GST_NAME_32BIT(Enter)(pVM, GCPhysCR3);
3476	switch (pVM->pgm.s.enmShadowMode)
3477	{
3478	case PGMMODE_32_BIT:
3479	rc2 = PGM_BTH_NAME_32BIT_32BIT(Enter)(pVM, GCPhysCR3);
3480	break;
3481	case PGMMODE_PAE:
3482	case PGMMODE_PAE_NX:
3483	rc2 = PGM_BTH_NAME_PAE_32BIT(Enter)(pVM, GCPhysCR3);
3484	break;
3485	case PGMMODE_NESTED:
3486	rc2 = PGM_BTH_NAME_NESTED_32BIT(Enter)(pVM, GCPhysCR3);
3487	break;
3488	case PGMMODE_EPT:
3489	rc2 = PGM_BTH_NAME_EPT_32BIT(Enter)(pVM, GCPhysCR3);
3490	break;
3491	case PGMMODE_AMD64:
3492	case PGMMODE_AMD64_NX:
3493	AssertMsgFailed(("Should use PAE shadow mode!\n"));
3494	default: AssertFailed(); break;
3495	}
3496	break;
3497
3498	case PGMMODE_PAE_NX:
3499	case PGMMODE_PAE:
3500	{
3501	uint32_t u32Dummy, u32Features;
3502
3503	CPUMGetGuestCpuId(pVM, 1, &u32Dummy, &u32Dummy, &u32Dummy, &u32Features);
3504	if (!(u32Features & X86_CPUID_FEATURE_EDX_PAE))
3505	{
3506	/* Pause first, then inform Main. */
3507	rc = VMR3SuspendNoSave(pVM);
3508	AssertRC(rc);
3509
3510	VMSetRuntimeError(pVM, true, "PAEmode",
3511	N_("The guest is trying to switch to the PAE mode which is currently disabled by default in VirtualBox. PAE support can be enabled using the VM settings (General/Advanced)"));
3512	/* we must return VINF_SUCCESS here otherwise the recompiler will assert */
3513	return VINF_SUCCESS;
3514	}
3515	GCPhysCR3 = CPUMGetGuestCR3(pVM) & X86_CR3_PAE_PAGE_MASK;
3516	rc = PGM_GST_NAME_PAE(Enter)(pVM, GCPhysCR3);
3517	switch (pVM->pgm.s.enmShadowMode)
3518	{
3519	case PGMMODE_PAE:
3520	case PGMMODE_PAE_NX:
3521	rc2 = PGM_BTH_NAME_PAE_PAE(Enter)(pVM, GCPhysCR3);
3522	break;
3523	case PGMMODE_NESTED:
3524	rc2 = PGM_BTH_NAME_NESTED_PAE(Enter)(pVM, GCPhysCR3);
3525	break;
3526	case PGMMODE_EPT:
3527	rc2 = PGM_BTH_NAME_EPT_PAE(Enter)(pVM, GCPhysCR3);
3528	break;
3529	case PGMMODE_32_BIT:
3530	case PGMMODE_AMD64:
3531	case PGMMODE_AMD64_NX:
3532	AssertMsgFailed(("Should use PAE shadow mode!\n"));
3533	default: AssertFailed(); break;
3534	}
3535	break;
3536	}
3537
3538	#ifdef VBOX_WITH_64_BITS_GUESTS
3539	case PGMMODE_AMD64_NX:
3540	case PGMMODE_AMD64:
3541	GCPhysCR3 = CPUMGetGuestCR3(pVM) & UINT64_C(0xfffffffffffff000); /** @todo define this mask! */
3542	rc = PGM_GST_NAME_AMD64(Enter)(pVM, GCPhysCR3);
3543	switch (pVM->pgm.s.enmShadowMode)
3544	{
3545	case PGMMODE_AMD64:
3546	case PGMMODE_AMD64_NX:
3547	rc2 = PGM_BTH_NAME_AMD64_AMD64(Enter)(pVM, GCPhysCR3);
3548	break;
3549	case PGMMODE_NESTED:
3550	rc2 = PGM_BTH_NAME_NESTED_AMD64(Enter)(pVM, GCPhysCR3);
3551	break;
3552	case PGMMODE_EPT:
3553	rc2 = PGM_BTH_NAME_EPT_AMD64(Enter)(pVM, GCPhysCR3);
3554	break;
3555	case PGMMODE_32_BIT:
3556	case PGMMODE_PAE:
3557	case PGMMODE_PAE_NX:
3558	AssertMsgFailed(("Should use AMD64 shadow mode!\n"));
3559	default: AssertFailed(); break;
3560	}
3561	break;
3562	#endif
3563
3564	default:
3565	AssertReleaseMsgFailed(("enmGuestMode=%d\n", enmGuestMode));
3566	rc = VERR_NOT_IMPLEMENTED;
3567	break;
3568	}
3569
3570	/* status codes. */
3571	AssertRC(rc);
3572	AssertRC(rc2);
3573	if (RT_SUCCESS(rc))
3574	{
3575	rc = rc2;
3576	if (RT_SUCCESS(rc)) /* no informational status codes. */
3577	rc = VINF_SUCCESS;
3578	}
3579
3580	/*
3581	* Notify SELM so it can update the TSSes with correct CR3s.
3582	*/
3583	SELMR3PagingModeChanged(pVM);
3584
3585	/* Notify HWACCM as well. */
3586	HWACCMR3PagingModeChanged(pVM, pVM->pgm.s.enmShadowMode, pVM->pgm.s.enmGuestMode);
3587	return rc;
3588	}
3589
3590
3591	/**
3592	* Dumps a PAE shadow page table.
3593	*
3594	* @returns VBox status code (VINF_SUCCESS).
3595	* @param pVM The VM handle.
3596	* @param pPT Pointer to the page table.
3597	* @param u64Address The virtual address of the page table starts.
3598	* @param fLongMode Set if this a long mode table; clear if it's a legacy mode table.
3599	* @param cMaxDepth The maxium depth.
3600	* @param pHlp Pointer to the output functions.
3601	*/
3602	static int pgmR3DumpHierarchyHCPaePT(PVM pVM, PX86PTPAE pPT, uint64_t u64Address, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
3603	{
3604	for (unsigned i = 0; i < RT_ELEMENTS(pPT->a); i++)
3605	{
3606	X86PTEPAE Pte = pPT->a[i];
3607	if (Pte.n.u1Present)
3608	{
3609	pHlp->pfnPrintf(pHlp,
3610	fLongMode /P R S A D G WT CD AT NX 4M a p ? /
3611	? "%016llx 3 \| P %c %c %c %c %c %s %s %s %s 4K %c%c%c %016llx\n"
3612	: "%08llx 2 \| P %c %c %c %c %c %s %s %s %s 4K %c%c%c %016llx\n",
3613	u64Address + ((uint64_t)i << X86_PT_PAE_SHIFT),
3614	Pte.n.u1Write ? 'W' : 'R',
3615	Pte.n.u1User ? 'U' : 'S',
3616	Pte.n.u1Accessed ? 'A' : '-',
3617	Pte.n.u1Dirty ? 'D' : '-',
3618	Pte.n.u1Global ? 'G' : '-',
3619	Pte.n.u1WriteThru ? "WT" : "--",
3620	Pte.n.u1CacheDisable? "CD" : "--",
3621	Pte.n.u1PAT ? "AT" : "--",
3622	Pte.n.u1NoExecute ? "NX" : "--",
3623	Pte.u & PGM_PTFLAGS_TRACK_DIRTY ? 'd' : '-',
3624	Pte.u & RT_BIT(10) ? '1' : '0',
3625	Pte.u & PGM_PTFLAGS_CSAM_VALIDATED? 'v' : '-',
3626	Pte.u & X86_PTE_PAE_PG_MASK);
3627	}
3628	}
3629	return VINF_SUCCESS;
3630	}
3631
3632
3633	/**
3634	* Dumps a PAE shadow page directory table.
3635	*
3636	* @returns VBox status code (VINF_SUCCESS).
3637	* @param pVM The VM handle.
3638	* @param HCPhys The physical address of the page directory table.
3639	* @param u64Address The virtual address of the page table starts.
3640	* @param cr4 The CR4, PSE is currently used.
3641	* @param fLongMode Set if this a long mode table; clear if it's a legacy mode table.
3642	* @param cMaxDepth The maxium depth.
3643	* @param pHlp Pointer to the output functions.
3644	*/
3645	static int pgmR3DumpHierarchyHCPaePD(PVM pVM, RTHCPHYS HCPhys, uint64_t u64Address, uint32_t cr4, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
3646	{
3647	PX86PDPAE pPD = (PX86PDPAE)MMPagePhys2Page(pVM, HCPhys);
3648	if (!pPD)
3649	{
3650	pHlp->pfnPrintf(pHlp, "%0*llx error! Page directory at HCPhys=%RHp was not found in the page pool!\n",
3651	fLongMode ? 16 : 8, u64Address, HCPhys);
3652	return VERR_INVALID_PARAMETER;
3653	}
3654	const bool fBigPagesSupported = fLongMode \|\| !!(cr4 & X86_CR4_PSE);
3655
3656	int rc = VINF_SUCCESS;
3657	for (unsigned i = 0; i < RT_ELEMENTS(pPD->a); i++)
3658	{
3659	X86PDEPAE Pde = pPD->a[i];
3660	if (Pde.n.u1Present)
3661	{
3662	if (fBigPagesSupported && Pde.b.u1Size)
3663	pHlp->pfnPrintf(pHlp,
3664	fLongMode /P R S A D G WT CD AT NX 4M a p ? /
3665	? "%016llx 2 \| P %c %c %c %c %c %s %s %s %s 4M %c%c%c %016llx\n"
3666	: "%08llx 1 \| P %c %c %c %c %c %s %s %s %s 4M %c%c%c %016llx\n",
3667	u64Address + ((uint64_t)i << X86_PD_PAE_SHIFT),
3668	Pde.b.u1Write ? 'W' : 'R',
3669	Pde.b.u1User ? 'U' : 'S',
3670	Pde.b.u1Accessed ? 'A' : '-',
3671	Pde.b.u1Dirty ? 'D' : '-',
3672	Pde.b.u1Global ? 'G' : '-',
3673	Pde.b.u1WriteThru ? "WT" : "--",
3674	Pde.b.u1CacheDisable? "CD" : "--",
3675	Pde.b.u1PAT ? "AT" : "--",
3676	Pde.b.u1NoExecute ? "NX" : "--",
3677	Pde.u & RT_BIT_64(9) ? '1' : '0',
3678	Pde.u & PGM_PDFLAGS_MAPPING ? 'm' : '-',
3679	Pde.u & PGM_PDFLAGS_TRACK_DIRTY ? 'd' : '-',
3680	Pde.u & X86_PDE_PAE_PG_MASK);
3681	else
3682	{
3683	pHlp->pfnPrintf(pHlp,
3684	fLongMode /P R S A D G WT CD AT NX 4M a p ? /
3685	? "%016llx 2 \| P %c %c %c %c %c %s %s .. %s 4K %c%c%c %016llx\n"
3686	: "%08llx 1 \| P %c %c %c %c %c %s %s .. %s 4K %c%c%c %016llx\n",
3687	u64Address + ((uint64_t)i << X86_PD_PAE_SHIFT),
3688	Pde.n.u1Write ? 'W' : 'R',
3689	Pde.n.u1User ? 'U' : 'S',
3690	Pde.n.u1Accessed ? 'A' : '-',
3691	Pde.n.u1Reserved0 ? '?' : '.', /* ignored */
3692	Pde.n.u1Reserved1 ? '?' : '.', /* ignored */
3693	Pde.n.u1WriteThru ? "WT" : "--",
3694	Pde.n.u1CacheDisable? "CD" : "--",
3695	Pde.n.u1NoExecute ? "NX" : "--",
3696	Pde.u & RT_BIT_64(9) ? '1' : '0',
3697	Pde.u & PGM_PDFLAGS_MAPPING ? 'm' : '-',
3698	Pde.u & PGM_PDFLAGS_TRACK_DIRTY ? 'd' : '-',
3699	Pde.u & X86_PDE_PAE_PG_MASK);
3700	if (cMaxDepth >= 1)
3701	{
3702	/** @todo what about using the page pool for mapping PTs? */
3703	uint64_t u64AddressPT = u64Address + ((uint64_t)i << X86_PD_PAE_SHIFT);
3704	RTHCPHYS HCPhysPT = Pde.u & X86_PDE_PAE_PG_MASK;
3705	PX86PTPAE pPT = NULL;
3706	if (!(Pde.u & PGM_PDFLAGS_MAPPING))
3707	pPT = (PX86PTPAE)MMPagePhys2Page(pVM, HCPhysPT);
3708	else
3709	{
3710	for (PPGMMAPPING pMap = pVM->pgm.s.pMappingsR3; pMap; pMap = pMap->pNextR3)
3711	{
3712	uint64_t off = u64AddressPT - pMap->GCPtr;
3713	if (off < pMap->cb)
3714	{
3715	const int iPDE = (uint32_t)(off >> X86_PD_SHIFT);
3716	const int iSub = (int)((off >> X86_PD_PAE_SHIFT) & 1); /* MSC is a pain sometimes */
3717	if ((iSub ? pMap->aPTs[iPDE].HCPhysPaePT1 : pMap->aPTs[iPDE].HCPhysPaePT0) != HCPhysPT)
3718	pHlp->pfnPrintf(pHlp, "%0*llx error! Mapping error! PT %d has HCPhysPT=%RHp not %RHp is in the PD.\n",
3719	fLongMode ? 16 : 8, u64AddressPT, iPDE,
3720	iSub ? pMap->aPTs[iPDE].HCPhysPaePT1 : pMap->aPTs[iPDE].HCPhysPaePT0, HCPhysPT);
3721	pPT = &pMap->aPTs[iPDE].paPaePTsR3[iSub];
3722	}
3723	}
3724	}
3725	int rc2 = VERR_INVALID_PARAMETER;
3726	if (pPT)
3727	rc2 = pgmR3DumpHierarchyHCPaePT(pVM, pPT, u64AddressPT, fLongMode, cMaxDepth - 1, pHlp);
3728	else
3729	pHlp->pfnPrintf(pHlp, "%0*llx error! Page table at HCPhys=%RHp was not found in the page pool!\n",
3730	fLongMode ? 16 : 8, u64AddressPT, HCPhysPT);
3731	if (rc2 < rc && RT_SUCCESS(rc))
3732	rc = rc2;
3733	}
3734	}
3735	}
3736	}
3737	return rc;
3738	}
3739
3740
3741	/**
3742	* Dumps a PAE shadow page directory pointer table.
3743	*
3744	* @returns VBox status code (VINF_SUCCESS).
3745	* @param pVM The VM handle.
3746	* @param HCPhys The physical address of the page directory pointer table.
3747	* @param u64Address The virtual address of the page table starts.
3748	* @param cr4 The CR4, PSE is currently used.
3749	* @param fLongMode Set if this a long mode table; clear if it's a legacy mode table.
3750	* @param cMaxDepth The maxium depth.
3751	* @param pHlp Pointer to the output functions.
3752	*/
3753	static int pgmR3DumpHierarchyHCPaePDPT(PVM pVM, RTHCPHYS HCPhys, uint64_t u64Address, uint32_t cr4, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
3754	{
3755	PX86PDPT pPDPT = (PX86PDPT)MMPagePhys2Page(pVM, HCPhys);
3756	if (!pPDPT)
3757	{
3758	pHlp->pfnPrintf(pHlp, "%0*llx error! Page directory pointer table at HCPhys=%RHp was not found in the page pool!\n",
3759	fLongMode ? 16 : 8, u64Address, HCPhys);
3760	return VERR_INVALID_PARAMETER;
3761	}
3762
3763	int rc = VINF_SUCCESS;
3764	const unsigned c = fLongMode ? RT_ELEMENTS(pPDPT->a) : X86_PG_PAE_PDPE_ENTRIES;
3765	for (unsigned i = 0; i < c; i++)
3766	{
3767	X86PDPE Pdpe = pPDPT->a[i];
3768	if (Pdpe.n.u1Present)
3769	{
3770	if (fLongMode)
3771	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a p ? /
3772	"%016llx 1 \| P %c %c %c %c %c %s %s %s %s .. %c%c%c %016llx\n",
3773	u64Address + ((uint64_t)i << X86_PDPT_SHIFT),
3774	Pdpe.lm.u1Write ? 'W' : 'R',
3775	Pdpe.lm.u1User ? 'U' : 'S',
3776	Pdpe.lm.u1Accessed ? 'A' : '-',
3777	Pdpe.lm.u3Reserved & 1? '?' : '.', /* ignored */
3778	Pdpe.lm.u3Reserved & 4? '!' : '.', /* mbz */
3779	Pdpe.lm.u1WriteThru ? "WT" : "--",
3780	Pdpe.lm.u1CacheDisable? "CD" : "--",
3781	Pdpe.lm.u3Reserved & 2? "!" : "..",/* mbz */
3782	Pdpe.lm.u1NoExecute ? "NX" : "--",
3783	Pdpe.u & RT_BIT(9) ? '1' : '0',
3784	Pdpe.u & PGM_PLXFLAGS_PERMANENT ? 'p' : '-',
3785	Pdpe.u & RT_BIT(11) ? '1' : '0',
3786	Pdpe.u & X86_PDPE_PG_MASK);
3787	else
3788	pHlp->pfnPrintf(pHlp, /P G WT CD AT NX 4M a p ? /
3789	"%08x 0 \| P %c %s %s %s %s .. %c%c%c %016llx\n",
3790	i << X86_PDPT_SHIFT,
3791	Pdpe.n.u4Reserved & 1? '!' : '.', /* mbz */
3792	Pdpe.n.u4Reserved & 4? '!' : '.', /* mbz */
3793	Pdpe.n.u1WriteThru ? "WT" : "--",
3794	Pdpe.n.u1CacheDisable? "CD" : "--",
3795	Pdpe.n.u4Reserved & 2? "!" : "..",/* mbz */
3796	Pdpe.u & RT_BIT(9) ? '1' : '0',
3797	Pdpe.u & PGM_PLXFLAGS_PERMANENT ? 'p' : '-',
3798	Pdpe.u & RT_BIT(11) ? '1' : '0',
3799	Pdpe.u & X86_PDPE_PG_MASK);
3800	if (cMaxDepth >= 1)
3801	{
3802	int rc2 = pgmR3DumpHierarchyHCPaePD(pVM, Pdpe.u & X86_PDPE_PG_MASK, u64Address + ((uint64_t)i << X86_PDPT_SHIFT),
3803	cr4, fLongMode, cMaxDepth - 1, pHlp);
3804	if (rc2 < rc && RT_SUCCESS(rc))
3805	rc = rc2;
3806	}
3807	}
3808	}
3809	return rc;
3810	}
3811
3812
3813	/**
3814	* Dumps a 32-bit shadow page table.
3815	*
3816	* @returns VBox status code (VINF_SUCCESS).
3817	* @param pVM The VM handle.
3818	* @param HCPhys The physical address of the table.
3819	* @param cr4 The CR4, PSE is currently used.
3820	* @param cMaxDepth The maxium depth.
3821	* @param pHlp Pointer to the output functions.
3822	*/
3823	static int pgmR3DumpHierarchyHcPaePML4(PVM pVM, RTHCPHYS HCPhys, uint32_t cr4, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
3824	{
3825	PX86PML4 pPML4 = (PX86PML4)MMPagePhys2Page(pVM, HCPhys);
3826	if (!pPML4)
3827	{
3828	pHlp->pfnPrintf(pHlp, "Page map level 4 at HCPhys=%RHp was not found in the page pool!\n", HCPhys);
3829	return VERR_INVALID_PARAMETER;
3830	}
3831
3832	int rc = VINF_SUCCESS;
3833	for (unsigned i = 0; i < RT_ELEMENTS(pPML4->a); i++)
3834	{
3835	X86PML4E Pml4e = pPML4->a[i];
3836	if (Pml4e.n.u1Present)
3837	{
3838	uint64_t u64Address = ((uint64_t)i << X86_PML4_SHIFT) \| (((uint64_t)i >> (X86_PML4_SHIFT - X86_PDPT_SHIFT - 1)) * 0xffff000000000000ULL);
3839	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a p ? /
3840	"%016llx 0 \| P %c %c %c %c %c %s %s %s %s .. %c%c%c %016llx\n",
3841	u64Address,
3842	Pml4e.n.u1Write ? 'W' : 'R',
3843	Pml4e.n.u1User ? 'U' : 'S',
3844	Pml4e.n.u1Accessed ? 'A' : '-',
3845	Pml4e.n.u3Reserved & 1? '?' : '.', /* ignored */
3846	Pml4e.n.u3Reserved & 4? '!' : '.', /* mbz */
3847	Pml4e.n.u1WriteThru ? "WT" : "--",
3848	Pml4e.n.u1CacheDisable? "CD" : "--",
3849	Pml4e.n.u3Reserved & 2? "!" : "..",/* mbz */
3850	Pml4e.n.u1NoExecute ? "NX" : "--",
3851	Pml4e.u & RT_BIT(9) ? '1' : '0',
3852	Pml4e.u & PGM_PLXFLAGS_PERMANENT ? 'p' : '-',
3853	Pml4e.u & RT_BIT(11) ? '1' : '0',
3854	Pml4e.u & X86_PML4E_PG_MASK);
3855
3856	if (cMaxDepth >= 1)
3857	{
3858	int rc2 = pgmR3DumpHierarchyHCPaePDPT(pVM, Pml4e.u & X86_PML4E_PG_MASK, u64Address, cr4, true, cMaxDepth - 1, pHlp);
3859	if (rc2 < rc && RT_SUCCESS(rc))
3860	rc = rc2;
3861	}
3862	}
3863	}
3864	return rc;
3865	}
3866
3867
3868	/**
3869	* Dumps a 32-bit shadow page table.
3870	*
3871	* @returns VBox status code (VINF_SUCCESS).
3872	* @param pVM The VM handle.
3873	* @param pPT Pointer to the page table.
3874	* @param u32Address The virtual address this table starts at.
3875	* @param pHlp Pointer to the output functions.
3876	*/
3877	int pgmR3DumpHierarchyHC32BitPT(PVM pVM, PX86PT pPT, uint32_t u32Address, PCDBGFINFOHLP pHlp)
3878	{
3879	for (unsigned i = 0; i < RT_ELEMENTS(pPT->a); i++)
3880	{
3881	X86PTE Pte = pPT->a[i];
3882	if (Pte.n.u1Present)
3883	{
3884	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a m d /
3885	"%08x 1 \| P %c %c %c %c %c %s %s %s .. 4K %c%c%c %08x\n",
3886	u32Address + (i << X86_PT_SHIFT),
3887	Pte.n.u1Write ? 'W' : 'R',
3888	Pte.n.u1User ? 'U' : 'S',
3889	Pte.n.u1Accessed ? 'A' : '-',
3890	Pte.n.u1Dirty ? 'D' : '-',
3891	Pte.n.u1Global ? 'G' : '-',
3892	Pte.n.u1WriteThru ? "WT" : "--",
3893	Pte.n.u1CacheDisable? "CD" : "--",
3894	Pte.n.u1PAT ? "AT" : "--",
3895	Pte.u & PGM_PTFLAGS_TRACK_DIRTY ? 'd' : '-',
3896	Pte.u & RT_BIT(10) ? '1' : '0',
3897	Pte.u & PGM_PTFLAGS_CSAM_VALIDATED ? 'v' : '-',
3898	Pte.u & X86_PDE_PG_MASK);
3899	}
3900	}
3901	return VINF_SUCCESS;
3902	}
3903
3904
3905	/**
3906	* Dumps a 32-bit shadow page directory and page tables.
3907	*
3908	* @returns VBox status code (VINF_SUCCESS).
3909	* @param pVM The VM handle.
3910	* @param cr3 The root of the hierarchy.
3911	* @param cr4 The CR4, PSE is currently used.
3912	* @param cMaxDepth How deep into the hierarchy the dumper should go.
3913	* @param pHlp Pointer to the output functions.
3914	*/
3915	int pgmR3DumpHierarchyHC32BitPD(PVM pVM, uint32_t cr3, uint32_t cr4, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
3916	{
3917	PX86PD pPD = (PX86PD)MMPagePhys2Page(pVM, cr3 & X86_CR3_PAGE_MASK);
3918	if (!pPD)
3919	{
3920	pHlp->pfnPrintf(pHlp, "Page directory at %#x was not found in the page pool!\n", cr3 & X86_CR3_PAGE_MASK);
3921	return VERR_INVALID_PARAMETER;
3922	}
3923
3924	int rc = VINF_SUCCESS;
3925	for (unsigned i = 0; i < RT_ELEMENTS(pPD->a); i++)
3926	{
3927	X86PDE Pde = pPD->a[i];
3928	if (Pde.n.u1Present)
3929	{
3930	const uint32_t u32Address = i << X86_PD_SHIFT;
3931	if ((cr4 & X86_CR4_PSE) && Pde.b.u1Size)
3932	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a m d /
3933	"%08x 0 \| P %c %c %c %c %c %s %s %s .. 4M %c%c%c %08x\n",
3934	u32Address,
3935	Pde.b.u1Write ? 'W' : 'R',
3936	Pde.b.u1User ? 'U' : 'S',
3937	Pde.b.u1Accessed ? 'A' : '-',
3938	Pde.b.u1Dirty ? 'D' : '-',
3939	Pde.b.u1Global ? 'G' : '-',
3940	Pde.b.u1WriteThru ? "WT" : "--",
3941	Pde.b.u1CacheDisable? "CD" : "--",
3942	Pde.b.u1PAT ? "AT" : "--",
3943	Pde.u & RT_BIT_64(9) ? '1' : '0',
3944	Pde.u & PGM_PDFLAGS_MAPPING ? 'm' : '-',
3945	Pde.u & PGM_PDFLAGS_TRACK_DIRTY ? 'd' : '-',
3946	Pde.u & X86_PDE4M_PG_MASK);
3947	else
3948	{
3949	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a m d /
3950	"%08x 0 \| P %c %c %c %c %c %s %s .. .. 4K %c%c%c %08x\n",
3951	u32Address,
3952	Pde.n.u1Write ? 'W' : 'R',
3953	Pde.n.u1User ? 'U' : 'S',
3954	Pde.n.u1Accessed ? 'A' : '-',
3955	Pde.n.u1Reserved0 ? '?' : '.', /* ignored */
3956	Pde.n.u1Reserved1 ? '?' : '.', /* ignored */
3957	Pde.n.u1WriteThru ? "WT" : "--",
3958	Pde.n.u1CacheDisable? "CD" : "--",
3959	Pde.u & RT_BIT_64(9) ? '1' : '0',
3960	Pde.u & PGM_PDFLAGS_MAPPING ? 'm' : '-',
3961	Pde.u & PGM_PDFLAGS_TRACK_DIRTY ? 'd' : '-',
3962	Pde.u & X86_PDE_PG_MASK);
3963	if (cMaxDepth >= 1)
3964	{
3965	/** @todo what about using the page pool for mapping PTs? */
3966	RTHCPHYS HCPhys = Pde.u & X86_PDE_PG_MASK;
3967	PX86PT pPT = NULL;
3968	if (!(Pde.u & PGM_PDFLAGS_MAPPING))
3969	pPT = (PX86PT)MMPagePhys2Page(pVM, HCPhys);
3970	else
3971	{
3972	for (PPGMMAPPING pMap = pVM->pgm.s.pMappingsR3; pMap; pMap = pMap->pNextR3)
3973	if (u32Address - pMap->GCPtr < pMap->cb)
3974	{
3975	int iPDE = (u32Address - pMap->GCPtr) >> X86_PD_SHIFT;
3976	if (pMap->aPTs[iPDE].HCPhysPT != HCPhys)
3977	pHlp->pfnPrintf(pHlp, "%08x error! Mapping error! PT %d has HCPhysPT=%RHp not %RHp is in the PD.\n",
3978	u32Address, iPDE, pMap->aPTs[iPDE].HCPhysPT, HCPhys);
3979	pPT = pMap->aPTs[iPDE].pPTR3;
3980	}
3981	}
3982	int rc2 = VERR_INVALID_PARAMETER;
3983	if (pPT)
3984	rc2 = pgmR3DumpHierarchyHC32BitPT(pVM, pPT, u32Address, pHlp);
3985	else
3986	pHlp->pfnPrintf(pHlp, "%08x error! Page table at %#x was not found in the page pool!\n", u32Address, HCPhys);
3987	if (rc2 < rc && RT_SUCCESS(rc))
3988	rc = rc2;
3989	}
3990	}
3991	}
3992	}
3993
3994	return rc;
3995	}
3996
3997
3998	/**
3999	* Dumps a 32-bit shadow page table.
4000	*
4001	* @returns VBox status code (VINF_SUCCESS).
4002	* @param pVM The VM handle.
4003	* @param pPT Pointer to the page table.
4004	* @param u32Address The virtual address this table starts at.
4005	* @param PhysSearch Address to search for.
4006	*/
4007	int pgmR3DumpHierarchyGC32BitPT(PVM pVM, PX86PT pPT, uint32_t u32Address, RTGCPHYS PhysSearch)
4008	{
4009	for (unsigned i = 0; i < RT_ELEMENTS(pPT->a); i++)
4010	{
4011	X86PTE Pte = pPT->a[i];
4012	if (Pte.n.u1Present)
4013	{
4014	Log(( /P R S A D G WT CD AT NX 4M a m d /
4015	"%08x 1 \| P %c %c %c %c %c %s %s %s .. 4K %c%c%c %08x\n",
4016	u32Address + (i << X86_PT_SHIFT),
4017	Pte.n.u1Write ? 'W' : 'R',
4018	Pte.n.u1User ? 'U' : 'S',
4019	Pte.n.u1Accessed ? 'A' : '-',
4020	Pte.n.u1Dirty ? 'D' : '-',
4021	Pte.n.u1Global ? 'G' : '-',
4022	Pte.n.u1WriteThru ? "WT" : "--",
4023	Pte.n.u1CacheDisable? "CD" : "--",
4024	Pte.n.u1PAT ? "AT" : "--",
4025	Pte.u & PGM_PTFLAGS_TRACK_DIRTY ? 'd' : '-',
4026	Pte.u & RT_BIT(10) ? '1' : '0',
4027	Pte.u & PGM_PTFLAGS_CSAM_VALIDATED ? 'v' : '-',
4028	Pte.u & X86_PDE_PG_MASK));
4029
4030	if ((Pte.u & X86_PDE_PG_MASK) == PhysSearch)
4031	{
4032	uint64_t fPageShw = 0;
4033	RTHCPHYS pPhysHC = 0;
4034
4035	PGMShwGetPage(pVM, (RTGCPTR)(u32Address + (i << X86_PT_SHIFT)), &fPageShw, &pPhysHC);
4036	Log(("Found %RGp at %RGv -> flags=%llx\n", PhysSearch, (RTGCPTR)(u32Address + (i << X86_PT_SHIFT)), fPageShw));
4037	}
4038	}
4039	}
4040	return VINF_SUCCESS;
4041	}
4042
4043
4044	/**
4045	* Dumps a 32-bit guest page directory and page tables.
4046	*
4047	* @returns VBox status code (VINF_SUCCESS).
4048	* @param pVM The VM handle.
4049	* @param cr3 The root of the hierarchy.
4050	* @param cr4 The CR4, PSE is currently used.
4051	* @param PhysSearch Address to search for.
4052	*/
4053	VMMR3DECL(int) PGMR3DumpHierarchyGC(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCPHYS PhysSearch)
4054	{
4055	bool fLongMode = false;
4056	const unsigned cch = fLongMode ? 16 : 8; NOREF(cch);
4057	PX86PD pPD = 0;
4058
4059	int rc = PGM_GCPHYS_2_PTR(pVM, cr3 & X86_CR3_PAGE_MASK, &pPD);
4060	if (RT_FAILURE(rc) \|\| !pPD)
4061	{
4062	Log(("Page directory at %#x was not found in the page pool!\n", cr3 & X86_CR3_PAGE_MASK));
4063	return VERR_INVALID_PARAMETER;
4064	}
4065
4066	Log(("cr3=%08x cr4=%08x%s\n"
4067	"%-*s P - Present\n"
4068	"%-*s \| R/W - Read (0) / Write (1)\n"
4069	"%-*s \| \| U/S - User (1) / Supervisor (0)\n"
4070	"%-*s \| \| \| A - Accessed\n"
4071	"%-*s \| \| \| \| D - Dirty\n"
4072	"%-*s \| \| \| \| \| G - Global\n"
4073	"%-*s \| \| \| \| \| \| WT - Write thru\n"
4074	"%-*s \| \| \| \| \| \| \| CD - Cache disable\n"
4075	"%-*s \| \| \| \| \| \| \| \| AT - Attribute table (PAT)\n"
4076	"%-*s \| \| \| \| \| \| \| \| \| NX - No execute (K8)\n"
4077	"%-*s \| \| \| \| \| \| \| \| \| \| 4K/4M/2M - Page size.\n"
4078	"%-*s \| \| \| \| \| \| \| \| \| \| \| AVL - a=allocated; m=mapping; d=track dirty;\n"
4079	"%-*s \| \| \| \| \| \| \| \| \| \| \| \| p=permanent; v=validated;\n"
4080	"%-*s Level \| \| \| \| \| \| \| \| \| \| \| \| Page\n"
4081	/* xxxx n **** P R S A D G WT CD AT NX 4M AVL xxxxxxxxxxxxx
4082	- W U - - - -- -- -- -- -- 010 */
4083	, cr3, cr4, fLongMode ? " Long Mode" : "",
4084	cch, "", cch, "", cch, "", cch, "", cch, "", cch, "", cch, "",
4085	cch, "", cch, "", cch, "", cch, "", cch, "", cch, "", cch, "Address"));
4086
4087	for (unsigned i = 0; i < RT_ELEMENTS(pPD->a); i++)
4088	{
4089	X86PDE Pde = pPD->a[i];
4090	if (Pde.n.u1Present)
4091	{
4092	const uint32_t u32Address = i << X86_PD_SHIFT;
4093
4094	if ((cr4 & X86_CR4_PSE) && Pde.b.u1Size)
4095	Log(( /P R S A D G WT CD AT NX 4M a m d /
4096	"%08x 0 \| P %c %c %c %c %c %s %s %s .. 4M %c%c%c %08x\n",
4097	u32Address,
4098	Pde.b.u1Write ? 'W' : 'R',
4099	Pde.b.u1User ? 'U' : 'S',
4100	Pde.b.u1Accessed ? 'A' : '-',
4101	Pde.b.u1Dirty ? 'D' : '-',
4102	Pde.b.u1Global ? 'G' : '-',
4103	Pde.b.u1WriteThru ? "WT" : "--",
4104	Pde.b.u1CacheDisable? "CD" : "--",
4105	Pde.b.u1PAT ? "AT" : "--",
4106	Pde.u & RT_BIT(9) ? '1' : '0',
4107	Pde.u & RT_BIT(10) ? '1' : '0',
4108	Pde.u & RT_BIT(11) ? '1' : '0',
4109	pgmGstGet4MBPhysPage(&pVM->pgm.s, Pde)));
4110	/** @todo PhysSearch */
4111	else
4112	{
4113	Log(( /P R S A D G WT CD AT NX 4M a m d /
4114	"%08x 0 \| P %c %c %c %c %c %s %s .. .. 4K %c%c%c %08x\n",
4115	u32Address,
4116	Pde.n.u1Write ? 'W' : 'R',
4117	Pde.n.u1User ? 'U' : 'S',
4118	Pde.n.u1Accessed ? 'A' : '-',
4119	Pde.n.u1Reserved0 ? '?' : '.', /* ignored */
4120	Pde.n.u1Reserved1 ? '?' : '.', /* ignored */
4121	Pde.n.u1WriteThru ? "WT" : "--",
4122	Pde.n.u1CacheDisable? "CD" : "--",
4123	Pde.u & RT_BIT(9) ? '1' : '0',
4124	Pde.u & RT_BIT(10) ? '1' : '0',
4125	Pde.u & RT_BIT(11) ? '1' : '0',
4126	Pde.u & X86_PDE_PG_MASK));
4127	////if (cMaxDepth >= 1)
4128	{
4129	/** @todo what about using the page pool for mapping PTs? */
4130	RTGCPHYS GCPhys = Pde.u & X86_PDE_PG_MASK;
4131	PX86PT pPT = NULL;
4132
4133	rc = PGM_GCPHYS_2_PTR(pVM, GCPhys, &pPT);
4134
4135	int rc2 = VERR_INVALID_PARAMETER;
4136	if (pPT)
4137	rc2 = pgmR3DumpHierarchyGC32BitPT(pVM, pPT, u32Address, PhysSearch);
4138	else
4139	Log(("%08x error! Page table at %#x was not found in the page pool!\n", u32Address, GCPhys));
4140	if (rc2 < rc && RT_SUCCESS(rc))
4141	rc = rc2;
4142	}
4143	}
4144	}
4145	}
4146
4147	return rc;
4148	}
4149
4150
4151	/**
4152	* Dumps a page table hierarchy use only physical addresses and cr4/lm flags.
4153	*
4154	* @returns VBox status code (VINF_SUCCESS).
4155	* @param pVM The VM handle.
4156	* @param cr3 The root of the hierarchy.
4157	* @param cr4 The cr4, only PAE and PSE is currently used.
4158	* @param fLongMode Set if long mode, false if not long mode.
4159	* @param cMaxDepth Number of levels to dump.
4160	* @param pHlp Pointer to the output functions.
4161	*/
4162	VMMR3DECL(int) PGMR3DumpHierarchyHC(PVM pVM, uint64_t cr3, uint64_t cr4, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
4163	{
4164	if (!pHlp)
4165	pHlp = DBGFR3InfoLogHlp();
4166	if (!cMaxDepth)
4167	return VINF_SUCCESS;
4168	const unsigned cch = fLongMode ? 16 : 8;
4169	pHlp->pfnPrintf(pHlp,
4170	"cr3=%08x cr4=%08x%s\n"
4171	"%-*s P - Present\n"
4172	"%-*s \| R/W - Read (0) / Write (1)\n"
4173	"%-*s \| \| U/S - User (1) / Supervisor (0)\n"
4174	"%-*s \| \| \| A - Accessed\n"
4175	"%-*s \| \| \| \| D - Dirty\n"
4176	"%-*s \| \| \| \| \| G - Global\n"
4177	"%-*s \| \| \| \| \| \| WT - Write thru\n"
4178	"%-*s \| \| \| \| \| \| \| CD - Cache disable\n"
4179	"%-*s \| \| \| \| \| \| \| \| AT - Attribute table (PAT)\n"
4180	"%-*s \| \| \| \| \| \| \| \| \| NX - No execute (K8)\n"
4181	"%-*s \| \| \| \| \| \| \| \| \| \| 4K/4M/2M - Page size.\n"
4182	"%-*s \| \| \| \| \| \| \| \| \| \| \| AVL - a=allocated; m=mapping; d=track dirty;\n"
4183	"%-*s \| \| \| \| \| \| \| \| \| \| \| \| p=permanent; v=validated;\n"
4184	"%-*s Level \| \| \| \| \| \| \| \| \| \| \| \| Page\n"
4185	/* xxxx n **** P R S A D G WT CD AT NX 4M AVL xxxxxxxxxxxxx
4186	- W U - - - -- -- -- -- -- 010 */
4187	, cr3, cr4, fLongMode ? " Long Mode" : "",
4188	cch, "", cch, "", cch, "", cch, "", cch, "", cch, "", cch, "",
4189	cch, "", cch, "", cch, "", cch, "", cch, "", cch, "", cch, "Address");
4190	if (cr4 & X86_CR4_PAE)
4191	{
4192	if (fLongMode)
4193	return pgmR3DumpHierarchyHcPaePML4(pVM, cr3 & X86_CR3_PAGE_MASK, cr4, cMaxDepth, pHlp);
4194	return pgmR3DumpHierarchyHCPaePDPT(pVM, cr3 & X86_CR3_PAE_PAGE_MASK, 0, cr4, false, cMaxDepth, pHlp);
4195	}
4196	return pgmR3DumpHierarchyHC32BitPD(pVM, cr3 & X86_CR3_PAGE_MASK, cr4, cMaxDepth, pHlp);
4197	}
4198
4199	#ifdef VBOX_WITH_DEBUGGER
4200
4201	/**
4202	* The '.pgmram' command.
4203	*
4204	* @returns VBox status.
4205	* @param pCmd Pointer to the command descriptor (as registered).
4206	* @param pCmdHlp Pointer to command helper functions.
4207	* @param pVM Pointer to the current VM (if any).
4208	* @param paArgs Pointer to (readonly) array of arguments.
4209	* @param cArgs Number of arguments in the array.
4210	*/
4211	static DECLCALLBACK(int) pgmR3CmdRam(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4212	{
4213	/*
4214	* Validate input.
4215	*/
4216	if (!pVM)
4217	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4218	if (!pVM->pgm.s.pRamRangesRC)
4219	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Sorry, no Ram is registered.\n");
4220
4221	/*
4222	* Dump the ranges.
4223	*/
4224	int rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL, "From - To (incl) pvHC\n");
4225	PPGMRAMRANGE pRam;
4226	for (pRam = pVM->pgm.s.pRamRangesR3; pRam; pRam = pRam->pNextR3)
4227	{
4228	rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL,
4229	"%RGp - %RGp %p\n",
4230	pRam->GCPhys, pRam->GCPhysLast, pRam->pvR3);
4231	if (RT_FAILURE(rc))
4232	return rc;
4233	}
4234
4235	return VINF_SUCCESS;
4236	}
4237
4238
4239	/**
4240	* The '.pgmmap' command.
4241	*
4242	* @returns VBox status.
4243	* @param pCmd Pointer to the command descriptor (as registered).
4244	* @param pCmdHlp Pointer to command helper functions.
4245	* @param pVM Pointer to the current VM (if any).
4246	* @param paArgs Pointer to (readonly) array of arguments.
4247	* @param cArgs Number of arguments in the array.
4248	*/
4249	static DECLCALLBACK(int) pgmR3CmdMap(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4250	{
4251	/*
4252	* Validate input.
4253	*/
4254	if (!pVM)
4255	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4256	if (!pVM->pgm.s.pMappingsR3)
4257	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Sorry, no mappings are registered.\n");
4258
4259	/*
4260	* Print message about the fixedness of the mappings.
4261	*/
4262	int rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL, pVM->pgm.s.fMappingsFixed ? "The mappings are FIXED.\n" : "The mappings are FLOATING.\n");
4263	if (RT_FAILURE(rc))
4264	return rc;
4265
4266	/*
4267	* Dump the ranges.
4268	*/
4269	PPGMMAPPING pCur;
4270	for (pCur = pVM->pgm.s.pMappingsR3; pCur; pCur = pCur->pNextR3)
4271	{
4272	rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL,
4273	"%08x - %08x %s\n",
4274	pCur->GCPtr, pCur->GCPtrLast, pCur->pszDesc);
4275	if (RT_FAILURE(rc))
4276	return rc;
4277	}
4278
4279	return VINF_SUCCESS;
4280	}
4281
4282
4283	/**
4284	* The '.pgmsync' command.
4285	*
4286	* @returns VBox status.
4287	* @param pCmd Pointer to the command descriptor (as registered).
4288	* @param pCmdHlp Pointer to command helper functions.
4289	* @param pVM Pointer to the current VM (if any).
4290	* @param paArgs Pointer to (readonly) array of arguments.
4291	* @param cArgs Number of arguments in the array.
4292	*/
4293	static DECLCALLBACK(int) pgmR3CmdSync(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4294	{
4295	/*
4296	* Validate input.
4297	*/
4298	if (!pVM)
4299	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4300
4301	/*
4302	* Force page directory sync.
4303	*/
4304	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
4305
4306	int rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Forcing page directory sync.\n");
4307	if (RT_FAILURE(rc))
4308	return rc;
4309
4310	return VINF_SUCCESS;
4311	}
4312
4313
4314	#ifdef VBOX_STRICT
4315	/**
4316	* The '.pgmassertcr3' command.
4317	*
4318	* @returns VBox status.
4319	* @param pCmd Pointer to the command descriptor (as registered).
4320	* @param pCmdHlp Pointer to command helper functions.
4321	* @param pVM Pointer to the current VM (if any).
4322	* @param paArgs Pointer to (readonly) array of arguments.
4323	* @param cArgs Number of arguments in the array.
4324	*/
4325	static DECLCALLBACK(int) pgmR3CmdAssertCR3(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4326	{
4327	/*
4328	* Validate input.
4329	*/
4330	if (!pVM)
4331	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4332
4333	int rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Checking shadow CR3 page tables for consistency.\n");
4334	if (RT_FAILURE(rc))
4335	return rc;
4336
4337	PGMAssertCR3(pVM, CPUMGetGuestCR3(pVM), CPUMGetGuestCR4(pVM));
4338
4339	return VINF_SUCCESS;
4340	}
4341	#endif /* VBOX_STRICT */
4342
4343
4344	/**
4345	* The '.pgmsyncalways' command.
4346	*
4347	* @returns VBox status.
4348	* @param pCmd Pointer to the command descriptor (as registered).
4349	* @param pCmdHlp Pointer to command helper functions.
4350	* @param pVM Pointer to the current VM (if any).
4351	* @param paArgs Pointer to (readonly) array of arguments.
4352	* @param cArgs Number of arguments in the array.
4353	*/
4354	static DECLCALLBACK(int) pgmR3CmdSyncAlways(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4355	{
4356	/*
4357	* Validate input.
4358	*/
4359	if (!pVM)
4360	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4361
4362	/*
4363	* Force page directory sync.
4364	*/
4365	if (pVM->pgm.s.fSyncFlags & PGM_SYNC_ALWAYS)
4366	{
4367	ASMAtomicAndU32(&pVM->pgm.s.fSyncFlags, ~PGM_SYNC_ALWAYS);
4368	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Disabled permanent forced page directory syncing.\n");
4369	}
4370	else
4371	{
4372	ASMAtomicOrU32(&pVM->pgm.s.fSyncFlags, PGM_SYNC_ALWAYS);
4373	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
4374	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Enabled permanent forced page directory syncing.\n");
4375	}
4376	}
4377
4378	#endif /* VBOX_WITH_DEBUGGER */
4379
4380	/**
4381	* pvUser argument of the pgmR3CheckIntegrity*Node callbacks.
4382	*/
4383	typedef struct PGMCHECKINTARGS
4384	{
4385	bool fLeftToRight; /*< true: left-to-right; false: right-to-left. /
4386	PPGMPHYSHANDLER pPrevPhys;
4387	PPGMVIRTHANDLER pPrevVirt;
4388	PPGMPHYS2VIRTHANDLER pPrevPhys2Virt;
4389	PVM pVM;
4390	} PGMCHECKINTARGS, *PPGMCHECKINTARGS;
4391
4392	/**
4393	* Validate a node in the physical handler tree.
4394	*
4395	* @returns 0 on if ok, other wise 1.
4396	* @param pNode The handler node.
4397	* @param pvUser pVM.
4398	*/
4399	static DECLCALLBACK(int) pgmR3CheckIntegrityPhysHandlerNode(PAVLROGCPHYSNODECORE pNode, void *pvUser)
4400	{
4401	PPGMCHECKINTARGS pArgs = (PPGMCHECKINTARGS)pvUser;
4402	PPGMPHYSHANDLER pCur = (PPGMPHYSHANDLER)pNode;
4403	AssertReleaseReturn(!((uintptr_t)pCur & 7), 1);
4404	AssertReleaseMsg(pCur->Core.Key <= pCur->Core.KeyLast,("pCur=%p %RGp-%RGp %s\n", pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
4405	AssertReleaseMsg( !pArgs->pPrevPhys
4406	\|\| (pArgs->fLeftToRight ? pArgs->pPrevPhys->Core.KeyLast < pCur->Core.Key : pArgs->pPrevPhys->Core.KeyLast > pCur->Core.Key),
4407	("pPrevPhys=%p %RGp-%RGp %s\n"
4408	" pCur=%p %RGp-%RGp %s\n",
4409	pArgs->pPrevPhys, pArgs->pPrevPhys->Core.Key, pArgs->pPrevPhys->Core.KeyLast, pArgs->pPrevPhys->pszDesc,
4410	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
4411	pArgs->pPrevPhys = pCur;
4412	return 0;
4413	}
4414
4415
4416	/**
4417	* Validate a node in the virtual handler tree.
4418	*
4419	* @returns 0 on if ok, other wise 1.
4420	* @param pNode The handler node.
4421	* @param pvUser pVM.
4422	*/
4423	static DECLCALLBACK(int) pgmR3CheckIntegrityVirtHandlerNode(PAVLROGCPTRNODECORE pNode, void *pvUser)
4424	{
4425	PPGMCHECKINTARGS pArgs = (PPGMCHECKINTARGS)pvUser;
4426	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)pNode;
4427	AssertReleaseReturn(!((uintptr_t)pCur & 7), 1);
4428	AssertReleaseMsg(pCur->Core.Key <= pCur->Core.KeyLast,("pCur=%p %RGv-%RGv %s\n", pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
4429	AssertReleaseMsg( !pArgs->pPrevVirt
4430	\|\| (pArgs->fLeftToRight ? pArgs->pPrevVirt->Core.KeyLast < pCur->Core.Key : pArgs->pPrevVirt->Core.KeyLast > pCur->Core.Key),
4431	("pPrevVirt=%p %RGv-%RGv %s\n"
4432	" pCur=%p %RGv-%RGv %s\n",
4433	pArgs->pPrevVirt, pArgs->pPrevVirt->Core.Key, pArgs->pPrevVirt->Core.KeyLast, pArgs->pPrevVirt->pszDesc,
4434	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
4435	for (unsigned iPage = 0; iPage < pCur->cPages; iPage++)
4436	{
4437	AssertReleaseMsg(pCur->aPhysToVirt[iPage].offVirtHandler == -RT_OFFSETOF(PGMVIRTHANDLER, aPhysToVirt[iPage]),
4438	("pCur=%p %RGv-%RGv %s\n"
4439	"iPage=%d offVirtHandle=%#x expected %#x\n",
4440	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc,
4441	iPage, pCur->aPhysToVirt[iPage].offVirtHandler, -RT_OFFSETOF(PGMVIRTHANDLER, aPhysToVirt[iPage])));
4442	}
4443	pArgs->pPrevVirt = pCur;
4444	return 0;
4445	}
4446
4447
4448	/**
4449	* Validate a node in the virtual handler tree.
4450	*
4451	* @returns 0 on if ok, other wise 1.
4452	* @param pNode The handler node.
4453	* @param pvUser pVM.
4454	*/
4455	static DECLCALLBACK(int) pgmR3CheckIntegrityPhysToVirtHandlerNode(PAVLROGCPHYSNODECORE pNode, void *pvUser)
4456	{
4457	PPGMCHECKINTARGS pArgs = (PPGMCHECKINTARGS)pvUser;
4458	PPGMPHYS2VIRTHANDLER pCur = (PPGMPHYS2VIRTHANDLER)pNode;
4459	AssertReleaseMsgReturn(!((uintptr_t)pCur & 3), ("\n"), 1);
4460	AssertReleaseMsgReturn(!(pCur->offVirtHandler & 3), ("\n"), 1);
4461	AssertReleaseMsg(pCur->Core.Key <= pCur->Core.KeyLast,("pCur=%p %RGp-%RGp\n", pCur, pCur->Core.Key, pCur->Core.KeyLast));
4462	AssertReleaseMsg( !pArgs->pPrevPhys2Virt
4463	\|\| (pArgs->fLeftToRight ? pArgs->pPrevPhys2Virt->Core.KeyLast < pCur->Core.Key : pArgs->pPrevPhys2Virt->Core.KeyLast > pCur->Core.Key),
4464	("pPrevPhys2Virt=%p %RGp-%RGp\n"
4465	" pCur=%p %RGp-%RGp\n",
4466	pArgs->pPrevPhys2Virt, pArgs->pPrevPhys2Virt->Core.Key, pArgs->pPrevPhys2Virt->Core.KeyLast,
4467	pCur, pCur->Core.Key, pCur->Core.KeyLast));
4468	AssertReleaseMsg( !pArgs->pPrevPhys2Virt
4469	\|\| (pArgs->fLeftToRight ? pArgs->pPrevPhys2Virt->Core.KeyLast < pCur->Core.Key : pArgs->pPrevPhys2Virt->Core.KeyLast > pCur->Core.Key),
4470	("pPrevPhys2Virt=%p %RGp-%RGp\n"
4471	" pCur=%p %RGp-%RGp\n",
4472	pArgs->pPrevPhys2Virt, pArgs->pPrevPhys2Virt->Core.Key, pArgs->pPrevPhys2Virt->Core.KeyLast,
4473	pCur, pCur->Core.Key, pCur->Core.KeyLast));
4474	AssertReleaseMsg((pCur->offNextAlias & (PGMPHYS2VIRTHANDLER_IN_TREE \| PGMPHYS2VIRTHANDLER_IS_HEAD)) == (PGMPHYS2VIRTHANDLER_IN_TREE \| PGMPHYS2VIRTHANDLER_IS_HEAD),
4475	("pCur=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4476	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias));
4477	if (pCur->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK)
4478	{
4479	PPGMPHYS2VIRTHANDLER pCur2 = pCur;
4480	for (;;)
4481	{
4482	pCur2 = (PPGMPHYS2VIRTHANDLER)((intptr_t)pCur + (pCur->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK));
4483	AssertReleaseMsg(pCur2 != pCur,
4484	(" pCur=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4485	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias));
4486	AssertReleaseMsg((pCur2->offNextAlias & (PGMPHYS2VIRTHANDLER_IN_TREE \| PGMPHYS2VIRTHANDLER_IS_HEAD)) == PGMPHYS2VIRTHANDLER_IN_TREE,
4487	(" pCur=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
4488	"pCur2=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4489	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias,
4490	pCur2, pCur2->Core.Key, pCur2->Core.KeyLast, pCur2->offVirtHandler, pCur2->offNextAlias));
4491	AssertReleaseMsg((pCur2->Core.Key ^ pCur->Core.Key) < PAGE_SIZE,
4492	(" pCur=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
4493	"pCur2=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4494	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias,
4495	pCur2, pCur2->Core.Key, pCur2->Core.KeyLast, pCur2->offVirtHandler, pCur2->offNextAlias));
4496	AssertReleaseMsg((pCur2->Core.KeyLast ^ pCur->Core.KeyLast) < PAGE_SIZE,
4497	(" pCur=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
4498	"pCur2=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4499	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias,
4500	pCur2, pCur2->Core.Key, pCur2->Core.KeyLast, pCur2->offVirtHandler, pCur2->offNextAlias));
4501	if (!(pCur2->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK))
4502	break;
4503	}
4504	}
4505
4506	pArgs->pPrevPhys2Virt = pCur;
4507	return 0;
4508	}
4509
4510
4511	/**
4512	* Perform an integrity check on the PGM component.
4513	*
4514	* @returns VINF_SUCCESS if everything is fine.
4515	* @returns VBox error status after asserting on integrity breach.
4516	* @param pVM The VM handle.
4517	*/
4518	VMMR3DECL(int) PGMR3CheckIntegrity(PVM pVM)
4519	{
4520	AssertReleaseReturn(pVM->pgm.s.offVM, VERR_INTERNAL_ERROR);
4521
4522	/*
4523	* Check the trees.
4524	*/
4525	int cErrors = 0;
4526	const static PGMCHECKINTARGS s_LeftToRight = { true, NULL, NULL, NULL, pVM };
4527	const static PGMCHECKINTARGS s_RightToLeft = { false, NULL, NULL, NULL, pVM };
4528	PGMCHECKINTARGS Args = s_LeftToRight;
4529	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysHandlers, true, pgmR3CheckIntegrityPhysHandlerNode, &Args);
4530	Args = s_RightToLeft;
4531	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysHandlers, false, pgmR3CheckIntegrityPhysHandlerNode, &Args);
4532	Args = s_LeftToRight;
4533	cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesR3->VirtHandlers, true, pgmR3CheckIntegrityVirtHandlerNode, &Args);
4534	Args = s_RightToLeft;
4535	cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesR3->VirtHandlers, false, pgmR3CheckIntegrityVirtHandlerNode, &Args);
4536	Args = s_LeftToRight;
4537	cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesR3->HyperVirtHandlers, true, pgmR3CheckIntegrityVirtHandlerNode, &Args);
4538	Args = s_RightToLeft;
4539	cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesR3->HyperVirtHandlers, false, pgmR3CheckIntegrityVirtHandlerNode, &Args);
4540	Args = s_LeftToRight;
4541	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysToVirtHandlers, true, pgmR3CheckIntegrityPhysToVirtHandlerNode, &Args);
4542	Args = s_RightToLeft;
4543	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysToVirtHandlers, false, pgmR3CheckIntegrityPhysToVirtHandlerNode, &Args);
4544
4545	return !cErrors ? VINF_SUCCESS : VERR_INTERNAL_ERROR;
4546	}
4547
4548
4549	/**
4550	* Inform PGM if we want all mappings to be put into the shadow page table. (necessary for e.g. VMX)
4551	*
4552	* @returns VBox status code.
4553	* @param pVM VM handle.
4554	* @param fEnable Enable or disable shadow mappings
4555	*/
4556	VMMR3DECL(int) PGMR3ChangeShwPDMappings(PVM pVM, bool fEnable)
4557	{
4558	pVM->pgm.s.fDisableMappings = !fEnable;
4559
4560	uint32_t cb;
4561	int rc = PGMR3MappingsSize(pVM, &cb);
4562	AssertRCReturn(rc, rc);
4563
4564	/* Pretend the mappings are now fixed; to force a refresh of the reserved PDEs. */
4565	rc = PGMR3MappingsFix(pVM, MM_HYPER_AREA_ADDRESS, cb);
4566	AssertRCReturn(rc, rc);
4567
4568	return VINF_SUCCESS;
4569	}
4570

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source: vbox/trunk/src/VBox/VMM/PGM.cpp@ 15404

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