PGM.cpp@ 15411

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1	/* $Id: PGM.cpp 15411 2008-12-13 03:30:58Z vboxsync $ */
2	/** @file
3	* PGM - Page Manager and Monitor. (Mixing stuff here, not good?)
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22
23	/** @page pg_pgm PGM - The Page Manager and Monitor
24	*
25	* @see grp_pgm,
26	* @ref pg_pgm_pool,
27	* @ref pg_pgm_phys.
28	*
29	*
30	* @section sec_pgm_modes Paging Modes
31	*
32	* There are three memory contexts: Host Context (HC), Guest Context (GC)
33	* and intermediate context. When talking about paging HC can also be refered to
34	* as "host paging", and GC refered to as "shadow paging".
35	*
36	* We define three basic paging modes: 32-bit, PAE and AMD64. The host paging mode
37	* is defined by the host operating system. The mode used in the shadow paging mode
38	* depends on the host paging mode and what the mode the guest is currently in. The
39	* following relation between the two is defined:
40	*
41	* @verbatim
42	Host > 32-bit \| PAE \| AMD64 \|
43	Guest \| \| \| \|
44	==v================================
45	32-bit 32-bit PAE PAE
46	-------\|--------\|--------\|--------\|
47	PAE PAE PAE PAE
48	-------\|--------\|--------\|--------\|
49	AMD64 AMD64 AMD64 AMD64
50	-------\|--------\|--------\|--------\| @endverbatim
51	*
52	* All configuration except those in the diagonal (upper left) are expected to
53	* require special effort from the switcher (i.e. a bit slower).
54	*
55	*
56	*
57	*
58	* @section sec_pgm_shw The Shadow Memory Context
59	*
60	*
61	* [..]
62	*
63	* Because of guest context mappings requires PDPT and PML4 entries to allow
64	* writing on AMD64, the two upper levels will have fixed flags whatever the
65	* guest is thinking of using there. So, when shadowing the PD level we will
66	* calculate the effective flags of PD and all the higher levels. In legacy
67	* PAE mode this only applies to the PWT and PCD bits (the rest are
68	* ignored/reserved/MBZ). We will ignore those bits for the present.
69	*
70	*
71	*
72	* @section sec_pgm_int The Intermediate Memory Context
73	*
74	* The world switch goes thru an intermediate memory context which purpose it is
75	* to provide different mappings of the switcher code. All guest mappings are also
76	* present in this context.
77	*
78	* The switcher code is mapped at the same location as on the host, at an
79	* identity mapped location (physical equals virtual address), and at the
80	* hypervisor location. The identity mapped location is for when the world
81	* switches that involves disabling paging.
82	*
83	* PGM maintain page tables for 32-bit, PAE and AMD64 paging modes. This
84	* simplifies switching guest CPU mode and consistency at the cost of more
85	* code to do the work. All memory use for those page tables is located below
86	* 4GB (this includes page tables for guest context mappings).
87	*
88	*
89	* @subsection subsec_pgm_int_gc Guest Context Mappings
90	*
91	* During assignment and relocation of a guest context mapping the intermediate
92	* memory context is used to verify the new location.
93	*
94	* Guest context mappings are currently restricted to below 4GB, for reasons
95	* of simplicity. This may change when we implement AMD64 support.
96	*
97	*
98	*
99	*
100	* @section sec_pgm_misc Misc
101	*
102	* @subsection subsec_pgm_misc_diff Differences Between Legacy PAE and Long Mode PAE
103	*
104	* The differences between legacy PAE and long mode PAE are:
105	* -# PDPE bits 1, 2, 5 and 6 are defined differently. In leagcy mode they are
106	* all marked down as must-be-zero, while in long mode 1, 2 and 5 have the
107	* usual meanings while 6 is ignored (AMD). This means that upon switching to
108	* legacy PAE mode we'll have to clear these bits and when going to long mode
109	* they must be set. This applies to both intermediate and shadow contexts,
110	* however we don't need to do it for the intermediate one since we're
111	* executing with CR0.WP at that time.
112	* -# CR3 allows a 32-byte aligned address in legacy mode, while in long mode
113	* a page aligned one is required.
114	*
115	*
116	* @section sec_pgm_handlers Access Handlers
117	*
118	* Placeholder.
119	*
120	*
121	* @subsection sec_pgm_handlers_virt Virtual Access Handlers
122	*
123	* Placeholder.
124	*
125	*
126	* @subsection sec_pgm_handlers_virt Virtual Access Handlers
127	*
128	* We currently implement three types of virtual access handlers: ALL, WRITE
129	* and HYPERVISOR (WRITE). See PGMVIRTHANDLERTYPE for some more details.
130	*
131	* The HYPERVISOR access handlers is kept in a separate tree since it doesn't apply
132	* to physical pages (PGMTREES::HyperVirtHandlers) and only needs to be consulted in
133	* a special \#PF case. The ALL and WRITE are in the PGMTREES::VirtHandlers tree, the
134	* rest of this section is going to be about these handlers.
135	*
136	* We'll go thru the life cycle of a handler and try make sense of it all, don't know
137	* how successfull this is gonna be...
138	*
139	* 1. A handler is registered thru the PGMR3HandlerVirtualRegister and
140	* PGMHandlerVirtualRegisterEx APIs. We check for conflicting virtual handlers
141	* and create a new node that is inserted into the AVL tree (range key). Then
142	* a full PGM resync is flagged (clear pool, sync cr3, update virtual bit of PGMPAGE).
143	*
144	* 2. The following PGMSyncCR3/SyncCR3 operation will first make invoke HandlerVirtualUpdate.
145	*
146	* 2a. HandlerVirtualUpdate will will lookup all the pages covered by virtual handlers
147	* via the current guest CR3 and update the physical page -> virtual handler
148	* translation. Needless to say, this doesn't exactly scale very well. If any changes
149	* are detected, it will flag a virtual bit update just like we did on registration.
150	* PGMPHYS pages with changes will have their virtual handler state reset to NONE.
151	*
152	* 2b. The virtual bit update process will iterate all the pages covered by all the
153	* virtual handlers and update the PGMPAGE virtual handler state to the max of all
154	* virtual handlers on that page.
155	*
156	* 2c. Back in SyncCR3 we will now flush the entire shadow page cache to make sure
157	* we don't miss any alias mappings of the monitored pages.
158	*
159	* 2d. SyncCR3 will then proceed with syncing the CR3 table.
160	*
161	* 3. \#PF(np,read) on a page in the range. This will cause it to be synced
162	* read-only and resumed if it's a WRITE handler. If it's an ALL handler we
163	* will call the handlers like in the next step. If the physical mapping has
164	* changed we will - some time in the future - perform a handler callback
165	* (optional) and update the physical -> virtual handler cache.
166	*
167	* 4. \#PF(,write) on a page in the range. This will cause the handler to
168	* be invoked.
169	*
170	* 5. The guest invalidates the page and changes the physical backing or
171	* unmaps it. This should cause the invalidation callback to be invoked
172	* (it might not yet be 100% perfect). Exactly what happens next... is
173	* this where we mess up and end up out of sync for a while?
174	*
175	* 6. The handler is deregistered by the client via PGMHandlerVirtualDeregister.
176	* We will then set all PGMPAGEs in the physical -> virtual handler cache for
177	* this handler to NONE and trigger a full PGM resync (basically the same
178	* as int step 1). Which means 2 is executed again.
179	*
180	*
181	* @subsubsection sub_sec_pgm_handler_virt_todo TODOs
182	*
183	* There is a bunch of things that needs to be done to make the virtual handlers
184	* work 100% correctly and work more efficiently.
185	*
186	* The first bit hasn't been implemented yet because it's going to slow the
187	* whole mess down even more, and besides it seems to be working reliably for
188	* our current uses. OTOH, some of the optimizations might end up more or less
189	* implementing the missing bits, so we'll see.
190	*
191	* On the optimization side, the first thing to do is to try avoid unnecessary
192	* cache flushing. Then try team up with the shadowing code to track changes
193	* in mappings by means of access to them (shadow in), updates to shadows pages,
194	* invlpg, and shadow PT discarding (perhaps).
195	*
196	* Some idea that have popped up for optimization for current and new features:
197	* - bitmap indicating where there are virtual handlers installed.
198	* (4KB => 220 pages, page 212 => covers 32-bit address space 1:1!)
199	* - Further optimize this by min/max (needs min/max avl getters).
200	* - Shadow page table entry bit (if any left)?
201	*
202	*/
203
204
205	/** @page pg_pgm_phys PGM Physical Guest Memory Management
206	*
207	*
208	* Objectives:
209	* - Guest RAM over-commitment using memory ballooning,
210	* zero pages and general page sharing.
211	* - Moving or mirroring a VM onto a different physical machine.
212	*
213	*
214	* @subsection subsec_pgmPhys_Definitions Definitions
215	*
216	* Allocation chunk - A RTR0MemObjAllocPhysNC object and the tracking
217	* machinery assoicated with it.
218	*
219	*
220	*
221	*
222	* @subsection subsec_pgmPhys_AllocPage Allocating a page.
223	*
224	* Initially we map all guest memory to the (per VM) zero page, which
225	* means that none of the read functions will cause pages to be allocated.
226	*
227	* Exception, access bit in page tables that have been shared. This must
228	* be handled, but we must also make sure PGMGst*Modify doesn't make
229	* unnecessary modifications.
230	*
231	* Allocation points:
232	* - PGMPhysSimpleWriteGCPhys and PGMPhysWrite.
233	* - Replacing a zero page mapping at \#PF.
234	* - Replacing a shared page mapping at \#PF.
235	* - ROM registration (currently MMR3RomRegister).
236	* - VM restore (pgmR3Load).
237	*
238	* For the first three it would make sense to keep a few pages handy
239	* until we've reached the max memory commitment for the VM.
240	*
241	* For the ROM registration, we know exactly how many pages we need
242	* and will request these from ring-0. For restore, we will save
243	* the number of non-zero pages in the saved state and allocate
244	* them up front. This would allow the ring-0 component to refuse
245	* the request if the isn't sufficient memory available for VM use.
246	*
247	* Btw. for both ROM and restore allocations we won't be requiring
248	* zeroed pages as they are going to be filled instantly.
249	*
250	*
251	* @subsection subsec_pgmPhys_FreePage Freeing a page
252	*
253	* There are a few points where a page can be freed:
254	* - After being replaced by the zero page.
255	* - After being replaced by a shared page.
256	* - After being ballooned by the guest additions.
257	* - At reset.
258	* - At restore.
259	*
260	* When freeing one or more pages they will be returned to the ring-0
261	* component and replaced by the zero page.
262	*
263	* The reasoning for clearing out all the pages on reset is that it will
264	* return us to the exact same state as on power on, and may thereby help
265	* us reduce the memory load on the system. Further it might have a
266	* (temporary) positive influence on memory fragmentation (@see subsec_pgmPhys_Fragmentation).
267	*
268	* On restore, as mention under the allocation topic, pages should be
269	* freed / allocated depending on how many is actually required by the
270	* new VM state. The simplest approach is to do like on reset, and free
271	* all non-ROM pages and then allocate what we need.
272	*
273	* A measure to prevent some fragmentation, would be to let each allocation
274	* chunk have some affinity towards the VM having allocated the most pages
275	* from it. Also, try make sure to allocate from allocation chunks that
276	* are almost full. Admittedly, both these measures might work counter to
277	* our intentions and its probably not worth putting a lot of effort,
278	* cpu time or memory into this.
279	*
280	*
281	* @subsection subsec_pgmPhys_SharePage Sharing a page
282	*
283	* The basic idea is that there there will be a idle priority kernel
284	* thread walking the non-shared VM pages hashing them and looking for
285	* pages with the same checksum. If such pages are found, it will compare
286	* them byte-by-byte to see if they actually are identical. If found to be
287	* identical it will allocate a shared page, copy the content, check that
288	* the page didn't change while doing this, and finally request both the
289	* VMs to use the shared page instead. If the page is all zeros (special
290	* checksum and byte-by-byte check) it will request the VM that owns it
291	* to replace it with the zero page.
292	*
293	* To make this efficient, we will have to make sure not to try share a page
294	* that will change its contents soon. This part requires the most work.
295	* A simple idea would be to request the VM to write monitor the page for
296	* a while to make sure it isn't modified any time soon. Also, it may
297	* make sense to skip pages that are being write monitored since this
298	* information is readily available to the thread if it works on the
299	* per-VM guest memory structures (presently called PGMRAMRANGE).
300	*
301	*
302	* @subsection subsec_pgmPhys_Fragmentation Fragmentation Concerns and Counter Measures
303	*
304	* The pages are organized in allocation chunks in ring-0, this is a necessity
305	* if we wish to have an OS agnostic approach to this whole thing. (On Linux we
306	* could easily work on a page-by-page basis if we liked. Whether this is possible
307	* or efficient on NT I don't quite know.) Fragmentation within these chunks may
308	* become a problem as part of the idea here is that we wish to return memory to
309	* the host system.
310	*
311	* For instance, starting two VMs at the same time, they will both allocate the
312	* guest memory on-demand and if permitted their page allocations will be
313	* intermixed. Shut down one of the two VMs and it will be difficult to return
314	* any memory to the host system because the page allocation for the two VMs are
315	* mixed up in the same allocation chunks.
316	*
317	* To further complicate matters, when pages are freed because they have been
318	* ballooned or become shared/zero the whole idea is that the page is supposed
319	* to be reused by another VM or returned to the host system. This will cause
320	* allocation chunks to contain pages belonging to different VMs and prevent
321	* returning memory to the host when one of those VM shuts down.
322	*
323	* The only way to really deal with this problem is to move pages. This can
324	* either be done at VM shutdown and or by the idle priority worker thread
325	* that will be responsible for finding sharable/zero pages. The mechanisms
326	* involved for coercing a VM to move a page (or to do it for it) will be
327	* the same as when telling it to share/zero a page.
328	*
329	*
330	* @subsection subsec_pgmPhys_Tracking Tracking Structures And Their Cost
331	*
332	* There's a difficult balance between keeping the per-page tracking structures
333	* (global and guest page) easy to use and keeping them from eating too much
334	* memory. We have limited virtual memory resources available when operating in
335	* 32-bit kernel space (on 64-bit there'll it's quite a different story). The
336	* tracking structures will be attemted designed such that we can deal with up
337	* to 32GB of memory on a 32-bit system and essentially unlimited on 64-bit ones.
338	*
339	*
340	* @subsubsection subsubsec_pgmPhys_Tracking_Kernel Kernel Space
341	*
342	* @see pg_GMM
343	*
344	* @subsubsection subsubsec_pgmPhys_Tracking_PerVM Per-VM
345	*
346	* Fixed info is the physical address of the page (HCPhys) and the page id
347	* (described above). Theoretically we'll need 48(-12) bits for the HCPhys part.
348	* Today we've restricting ourselves to 40(-12) bits because this is the current
349	* restrictions of all AMD64 implementations (I think Barcelona will up this
350	* to 48(-12) bits, not that it really matters) and I needed the bits for
351	* tracking mappings of a page. 48-12 = 36. That leaves 28 bits, which means a
352	* decent range for the page id: 2^(28+12) = 1024TB.
353	*
354	* In additions to these, we'll have to keep maintaining the page flags as we
355	* currently do. Although it wouldn't harm to optimize these quite a bit, like
356	* for instance the ROM shouldn't depend on having a write handler installed
357	* in order for it to become read-only. A RO/RW bit should be considered so
358	* that the page syncing code doesn't have to mess about checking multiple
359	* flag combinations (ROM \|\| RW handler \|\| write monitored) in order to
360	* figure out how to setup a shadow PTE. But this of course, is second
361	* priority at present. Current this requires 12 bits, but could probably
362	* be optimized to ~8.
363	*
364	* Then there's the 24 bits used to track which shadow page tables are
365	* currently mapping a page for the purpose of speeding up physical
366	* access handlers, and thereby the page pool cache. More bit for this
367	* purpose wouldn't hurt IIRC.
368	*
369	* Then there is a new bit in which we need to record what kind of page
370	* this is, shared, zero, normal or write-monitored-normal. This'll
371	* require 2 bits. One bit might be needed for indicating whether a
372	* write monitored page has been written to. And yet another one or
373	* two for tracking migration status. 3-4 bits total then.
374	*
375	* Whatever is left will can be used to record the sharabilitiy of a
376	* page. The page checksum will not be stored in the per-VM table as
377	* the idle thread will not be permitted to do modifications to it.
378	* It will instead have to keep its own working set of potentially
379	* shareable pages and their check sums and stuff.
380	*
381	* For the present we'll keep the current packing of the
382	* PGMRAMRANGE::aHCPhys to keep the changes simple, only of course,
383	* we'll have to change it to a struct with a total of 128-bits at
384	* our disposal.
385	*
386	* The initial layout will be like this:
387	* @verbatim
388	RTHCPHYS HCPhys; The current stuff.
389	63:40 Current shadow PT tracking stuff.
390	39:12 The physical page frame number.
391	11:0 The current flags.
392	uint32_t u28PageId : 28; The page id.
393	uint32_t u2State : 2; The page state { zero, shared, normal, write monitored }.
394	uint32_t fWrittenTo : 1; Whether a write monitored page was written to.
395	uint32_t u1Reserved : 1; Reserved for later.
396	uint32_t u32Reserved; Reserved for later, mostly sharing stats.
397	@endverbatim
398	*
399	* The final layout will be something like this:
400	* @verbatim
401	RTHCPHYS HCPhys; The current stuff.
402	63:48 High page id (12+).
403	47:12 The physical page frame number.
404	11:0 Low page id.
405	uint32_t fReadOnly : 1; Whether it's readonly page (rom or monitored in some way).
406	uint32_t u3Type : 3; The page type {RESERVED, MMIO, MMIO2, ROM, shadowed ROM, RAM}.
407	uint32_t u2PhysMon : 2; Physical access handler type {none, read, write, all}.
408	uint32_t u2VirtMon : 2; Virtual access handler type {none, read, write, all}..
409	uint32_t u2State : 2; The page state { zero, shared, normal, write monitored }.
410	uint32_t fWrittenTo : 1; Whether a write monitored page was written to.
411	uint32_t u20Reserved : 20; Reserved for later, mostly sharing stats.
412	uint32_t u32Tracking; The shadow PT tracking stuff, roughly.
413	@endverbatim
414	*
415	* Cost wise, this means we'll double the cost for guest memory. There isn't anyway
416	* around that I'm afraid. It means that the cost of dealing out 32GB of memory
417	* to one or more VMs is: (32GB >> PAGE_SHIFT) * 16 bytes, or 128MBs. Or another
418	* example, the VM heap cost when assigning 1GB to a VM will be: 4MB.
419	*
420	* A couple of cost examples for the total cost per-VM + kernel.
421	* 32-bit Windows and 32-bit linux:
422	* 1GB guest ram, 256K pages: 4MB + 2MB(+) = 6MB
423	* 4GB guest ram, 1M pages: 16MB + 8MB(+) = 24MB
424	* 32GB guest ram, 8M pages: 128MB + 64MB(+) = 192MB
425	* 64-bit Windows and 64-bit linux:
426	* 1GB guest ram, 256K pages: 4MB + 3MB(+) = 7MB
427	* 4GB guest ram, 1M pages: 16MB + 12MB(+) = 28MB
428	* 32GB guest ram, 8M pages: 128MB + 96MB(+) = 224MB
429	*
430	* UPDATE - 2007-09-27:
431	* Will need a ballooned flag/state too because we cannot
432	* trust the guest 100% and reporting the same page as ballooned more
433	* than once will put the GMM off balance.
434	*
435	*
436	* @subsection subsec_pgmPhys_Serializing Serializing Access
437	*
438	* Initially, we'll try a simple scheme:
439	*
440	* - The per-VM RAM tracking structures (PGMRAMRANGE) is only modified
441	* by the EMT thread of that VM while in the pgm critsect.
442	* - Other threads in the VM process that needs to make reliable use of
443	* the per-VM RAM tracking structures will enter the critsect.
444	* - No process external thread or kernel thread will ever try enter
445	* the pgm critical section, as that just won't work.
446	* - The idle thread (and similar threads) doesn't not need 100% reliable
447	* data when performing it tasks as the EMT thread will be the one to
448	* do the actual changes later anyway. So, as long as it only accesses
449	* the main ram range, it can do so by somehow preventing the VM from
450	* being destroyed while it works on it...
451	*
452	* - The over-commitment management, including the allocating/freeing
453	* chunks, is serialized by a ring-0 mutex lock (a fast one since the
454	* more mundane mutex implementation is broken on Linux).
455	* - A separeate mutex is protecting the set of allocation chunks so
456	* that pages can be shared or/and freed up while some other VM is
457	* allocating more chunks. This mutex can be take from under the other
458	* one, but not the otherway around.
459	*
460	*
461	* @subsection subsec_pgmPhys_Request VM Request interface
462	*
463	* When in ring-0 it will become necessary to send requests to a VM so it can
464	* for instance move a page while defragmenting during VM destroy. The idle
465	* thread will make use of this interface to request VMs to setup shared
466	* pages and to perform write monitoring of pages.
467	*
468	* I would propose an interface similar to the current VMReq interface, similar
469	* in that it doesn't require locking and that the one sending the request may
470	* wait for completion if it wishes to. This shouldn't be very difficult to
471	* realize.
472	*
473	* The requests themselves are also pretty simple. They are basically:
474	* -# Check that some precondition is still true.
475	* -# Do the update.
476	* -# Update all shadow page tables involved with the page.
477	*
478	* The 3rd step is identical to what we're already doing when updating a
479	* physical handler, see pgmHandlerPhysicalSetRamFlagsAndFlushShadowPTs.
480	*
481	*
482	*
483	* @section sec_pgmPhys_MappingCaches Mapping Caches
484	*
485	* In order to be able to map in and out memory and to be able to support
486	* guest with more RAM than we've got virtual address space, we'll employing
487	* a mapping cache. There is already a tiny one for GC (see PGMGCDynMapGCPageEx)
488	* and we'll create a similar one for ring-0 unless we decide to setup a dedicate
489	* memory context for the HWACCM execution.
490	*
491	*
492	* @subsection subsec_pgmPhys_MappingCaches_R3 Ring-3
493	*
494	* We've considered implementing the ring-3 mapping cache page based but found
495	* that this was bother some when one had to take into account TLBs+SMP and
496	* portability (missing the necessary APIs on several platforms). There were
497	* also some performance concerns with this approach which hadn't quite been
498	* worked out.
499	*
500	* Instead, we'll be mapping allocation chunks into the VM process. This simplifies
501	* matters greatly quite a bit since we don't need to invent any new ring-0 stuff,
502	* only some minor RTR0MEMOBJ mapping stuff. The main concern here is that mapping
503	* compared to the previous idea is that mapping or unmapping a 1MB chunk is more
504	* costly than a single page, although how much more costly is uncertain. We'll
505	* try address this by using a very big cache, preferably bigger than the actual
506	* VM RAM size if possible. The current VM RAM sizes should give some idea for
507	* 32-bit boxes, while on 64-bit we can probably get away with employing an
508	* unlimited cache.
509	*
510	* The cache have to parts, as already indicated, the ring-3 side and the
511	* ring-0 side.
512	*
513	* The ring-0 will be tied to the page allocator since it will operate on the
514	* memory objects it contains. It will therefore require the first ring-0 mutex
515	* discussed in @ref subsec_pgmPhys_Serializing. We
516	* some double house keeping wrt to who has mapped what I think, since both
517	* VMMR0.r0 and RTR0MemObj will keep track of mapping relataions
518	*
519	* The ring-3 part will be protected by the pgm critsect. For simplicity, we'll
520	* require anyone that desires to do changes to the mapping cache to do that
521	* from within this critsect. Alternatively, we could employ a separate critsect
522	* for serializing changes to the mapping cache as this would reduce potential
523	* contention with other threads accessing mappings unrelated to the changes
524	* that are in process. We can see about this later, contention will show
525	* up in the statistics anyway, so it'll be simple to tell.
526	*
527	* The organization of the ring-3 part will be very much like how the allocation
528	* chunks are organized in ring-0, that is in an AVL tree by chunk id. To avoid
529	* having to walk the tree all the time, we'll have a couple of lookaside entries
530	* like in we do for I/O ports and MMIO in IOM.
531	*
532	* The simplified flow of a PGMPhysRead/Write function:
533	* -# Enter the PGM critsect.
534	* -# Lookup GCPhys in the ram ranges and get the Page ID.
535	* -# Calc the Allocation Chunk ID from the Page ID.
536	* -# Check the lookaside entries and then the AVL tree for the Chunk ID.
537	* If not found in cache:
538	* -# Call ring-0 and request it to be mapped and supply
539	* a chunk to be unmapped if the cache is maxed out already.
540	* -# Insert the new mapping into the AVL tree (id + R3 address).
541	* -# Update the relevant lookaside entry and return the mapping address.
542	* -# Do the read/write according to monitoring flags and everything.
543	* -# Leave the critsect.
544	*
545	*
546	* @section sec_pgmPhys_Fallback Fallback
547	*
548	* Current all the "second tier" hosts will not support the RTR0MemObjAllocPhysNC
549	* API and thus require a fallback.
550	*
551	* So, when RTR0MemObjAllocPhysNC returns VERR_NOT_SUPPORTED the page allocator
552	* will return to the ring-3 caller (and later ring-0) and asking it to seed
553	* the page allocator with some fresh pages (VERR_GMM_SEED_ME). Ring-3 will
554	* then perform an SUPPageAlloc(cbChunk >> PAGE_SHIFT) call and make a
555	* "SeededAllocPages" call to ring-0.
556	*
557	* The first time ring-0 sees the VERR_NOT_SUPPORTED failure it will disable
558	* all page sharing (zero page detection will continue). It will also force
559	* all allocations to come from the VM which seeded the page. Both these
560	* measures are taken to make sure that there will never be any need for
561	* mapping anything into ring-3 - everything will be mapped already.
562	*
563	* Whether we'll continue to use the current MM locked memory management
564	* for this I don't quite know (I'd prefer not to and just ditch that all
565	* togther), we'll see what's simplest to do.
566	*
567	*
568	*
569	* @section sec_pgmPhys_Changes Changes
570	*
571	* Breakdown of the changes involved?
572	*/
573
574
575	/** Saved state data unit version. */
576	#define PGM_SAVED_STATE_VERSION 6
577
578	/*******************************************************************************
579	* Header Files *
580	*******************************************************************************/
581	#define LOG_GROUP LOG_GROUP_PGM
582	#include <VBox/dbgf.h>
583	#include <VBox/pgm.h>
584	#include <VBox/cpum.h>
585	#include <VBox/iom.h>
586	#include <VBox/sup.h>
587	#include <VBox/mm.h>
588	#include <VBox/em.h>
589	#include <VBox/stam.h>
590	#include <VBox/rem.h>
591	#include <VBox/dbgf.h>
592	#include <VBox/rem.h>
593	#include <VBox/selm.h>
594	#include <VBox/ssm.h>
595	#include "PGMInternal.h"
596	#include <VBox/vm.h>
597	#include <VBox/dbg.h>
598	#include <VBox/hwaccm.h>
599
600	#include <iprt/assert.h>
601	#include <iprt/alloc.h>
602	#include <iprt/asm.h>
603	#include <iprt/thread.h>
604	#include <iprt/string.h>
605	#ifdef DEBUG_bird
606	# include <iprt/env.h>
607	#endif
608	#include <VBox/param.h>
609	#include <VBox/err.h>
610
611
612
613	/*******************************************************************************
614	* Internal Functions *
615	*******************************************************************************/
616	static int pgmR3InitPaging(PVM pVM);
617	static DECLCALLBACK(void) pgmR3PhysInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
618	static DECLCALLBACK(void) pgmR3InfoMode(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
619	static DECLCALLBACK(void) pgmR3InfoCr3(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
620	static DECLCALLBACK(int) pgmR3RelocatePhysHandler(PAVLROGCPHYSNODECORE pNode, void *pvUser);
621	static DECLCALLBACK(int) pgmR3RelocateVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser);
622	static DECLCALLBACK(int) pgmR3RelocateHyperVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser);
623	#ifdef VBOX_STRICT
624	static DECLCALLBACK(void) pgmR3ResetNoMorePhysWritesFlag(PVM pVM, VMSTATE enmState, VMSTATE enmOldState, void *pvUser);
625	#endif
626	static DECLCALLBACK(int) pgmR3Save(PVM pVM, PSSMHANDLE pSSM);
627	static DECLCALLBACK(int) pgmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version);
628	static int pgmR3ModeDataInit(PVM pVM, bool fResolveGCAndR0);
629	static void pgmR3ModeDataSwitch(PVM pVM, PGMMODE enmShw, PGMMODE enmGst);
630	static PGMMODE pgmR3CalcShadowMode(PVM pVM, PGMMODE enmGuestMode, SUPPAGINGMODE enmHostMode, PGMMODE enmShadowMode, VMMSWITCHER *penmSwitcher);
631
632	#ifdef VBOX_WITH_STATISTICS
633	static void pgmR3InitStats(PVM pVM);
634	#endif
635
636	#ifdef VBOX_WITH_DEBUGGER
637	/** @todo all but the two last commands must be converted to 'info'. */
638	static DECLCALLBACK(int) pgmR3CmdRam(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
639	static DECLCALLBACK(int) pgmR3CmdMap(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
640	static DECLCALLBACK(int) pgmR3CmdSync(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
641	static DECLCALLBACK(int) pgmR3CmdSyncAlways(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
642	# ifdef VBOX_STRICT
643	static DECLCALLBACK(int) pgmR3CmdAssertCR3(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
644	# endif
645	#endif
646
647
648	/*******************************************************************************
649	* Global Variables *
650	*******************************************************************************/
651	#ifdef VBOX_WITH_DEBUGGER
652	/** Command descriptors. */
653	static const DBGCCMD g_aCmds[] =
654	{
655	/* pszCmd, cArgsMin, cArgsMax, paArgDesc, cArgDescs, pResultDesc, fFlags, pfnHandler pszSyntax, ....pszDescription */
656	{ "pgmram", 0, 0, NULL, 0, NULL, 0, pgmR3CmdRam, "", "Display the ram ranges." },
657	{ "pgmmap", 0, 0, NULL, 0, NULL, 0, pgmR3CmdMap, "", "Display the mapping ranges." },
658	{ "pgmsync", 0, 0, NULL, 0, NULL, 0, pgmR3CmdSync, "", "Sync the CR3 page." },
659	#ifdef VBOX_STRICT
660	{ "pgmassertcr3", 0, 0, NULL, 0, NULL, 0, pgmR3CmdAssertCR3, "", "Check the shadow CR3 mapping." },
661	#endif
662	{ "pgmsyncalways", 0, 0, NULL, 0, NULL, 0, pgmR3CmdSyncAlways, "", "Toggle permanent CR3 syncing." },
663	};
664	#endif
665
666
667
668
669	/*
670	* Shadow - 32-bit mode
671	*/
672	#define PGM_SHW_TYPE PGM_TYPE_32BIT
673	#define PGM_SHW_NAME(name) PGM_SHW_NAME_32BIT(name)
674	#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_32BIT_STR(name)
675	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_32BIT_STR(name)
676	#include "PGMShw.h"
677
678	/* Guest - real mode */
679	#define PGM_GST_TYPE PGM_TYPE_REAL
680	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
681	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_REAL_STR(name)
682	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
683	#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_REAL(name)
684	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_32BIT_REAL_STR(name)
685	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_32BIT_REAL_STR(name)
686	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_PHYS
687	#include "PGMGst.h"
688	#include "PGMBth.h"
689	#undef BTH_PGMPOOLKIND_PT_FOR_PT
690	#undef PGM_BTH_NAME
691	#undef PGM_BTH_NAME_RC_STR
692	#undef PGM_BTH_NAME_R0_STR
693	#undef PGM_GST_TYPE
694	#undef PGM_GST_NAME
695	#undef PGM_GST_NAME_RC_STR
696	#undef PGM_GST_NAME_R0_STR
697
698	/* Guest - protected mode */
699	#define PGM_GST_TYPE PGM_TYPE_PROT
700	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
701	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PROT_STR(name)
702	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
703	#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_PROT(name)
704	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_32BIT_PROT_STR(name)
705	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_32BIT_PROT_STR(name)
706	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_PHYS
707	#include "PGMGst.h"
708	#include "PGMBth.h"
709	#undef BTH_PGMPOOLKIND_PT_FOR_PT
710	#undef PGM_BTH_NAME
711	#undef PGM_BTH_NAME_RC_STR
712	#undef PGM_BTH_NAME_R0_STR
713	#undef PGM_GST_TYPE
714	#undef PGM_GST_NAME
715	#undef PGM_GST_NAME_RC_STR
716	#undef PGM_GST_NAME_R0_STR
717
718	/* Guest - 32-bit mode */
719	#define PGM_GST_TYPE PGM_TYPE_32BIT
720	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
721	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_32BIT_STR(name)
722	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
723	#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_32BIT(name)
724	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_32BIT_32BIT_STR(name)
725	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_32BIT_32BIT_STR(name)
726	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT
727	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB
728	#include "PGMGst.h"
729	#include "PGMBth.h"
730	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
731	#undef BTH_PGMPOOLKIND_PT_FOR_PT
732	#undef PGM_BTH_NAME
733	#undef PGM_BTH_NAME_RC_STR
734	#undef PGM_BTH_NAME_R0_STR
735	#undef PGM_GST_TYPE
736	#undef PGM_GST_NAME
737	#undef PGM_GST_NAME_RC_STR
738	#undef PGM_GST_NAME_R0_STR
739
740	#undef PGM_SHW_TYPE
741	#undef PGM_SHW_NAME
742	#undef PGM_SHW_NAME_RC_STR
743	#undef PGM_SHW_NAME_R0_STR
744
745
746	/*
747	* Shadow - PAE mode
748	*/
749	#define PGM_SHW_TYPE PGM_TYPE_PAE
750	#define PGM_SHW_NAME(name) PGM_SHW_NAME_PAE(name)
751	#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_PAE_STR(name)
752	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_PAE_STR(name)
753	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_REAL(name)
754	#include "PGMShw.h"
755
756	/* Guest - real mode */
757	#define PGM_GST_TYPE PGM_TYPE_REAL
758	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
759	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_REAL_STR(name)
760	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
761	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_REAL(name)
762	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_PAE_REAL_STR(name)
763	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_REAL_STR(name)
764	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
765	#include "PGMBth.h"
766	#undef BTH_PGMPOOLKIND_PT_FOR_PT
767	#undef PGM_BTH_NAME
768	#undef PGM_BTH_NAME_RC_STR
769	#undef PGM_BTH_NAME_R0_STR
770	#undef PGM_GST_TYPE
771	#undef PGM_GST_NAME
772	#undef PGM_GST_NAME_RC_STR
773	#undef PGM_GST_NAME_R0_STR
774
775	/* Guest - protected mode */
776	#define PGM_GST_TYPE PGM_TYPE_PROT
777	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
778	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PROT_STR(name)
779	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
780	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_PROT(name)
781	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_PAE_PROT_STR(name)
782	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_PROT_STR(name)
783	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
784	#include "PGMBth.h"
785	#undef BTH_PGMPOOLKIND_PT_FOR_PT
786	#undef PGM_BTH_NAME
787	#undef PGM_BTH_NAME_RC_STR
788	#undef PGM_BTH_NAME_R0_STR
789	#undef PGM_GST_TYPE
790	#undef PGM_GST_NAME
791	#undef PGM_GST_NAME_RC_STR
792	#undef PGM_GST_NAME_R0_STR
793
794	/* Guest - 32-bit mode */
795	#define PGM_GST_TYPE PGM_TYPE_32BIT
796	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
797	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_32BIT_STR(name)
798	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
799	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_32BIT(name)
800	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_PAE_32BIT_STR(name)
801	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_32BIT_STR(name)
802	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_32BIT_PT
803	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB
804	#include "PGMBth.h"
805	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
806	#undef BTH_PGMPOOLKIND_PT_FOR_PT
807	#undef PGM_BTH_NAME
808	#undef PGM_BTH_NAME_RC_STR
809	#undef PGM_BTH_NAME_R0_STR
810	#undef PGM_GST_TYPE
811	#undef PGM_GST_NAME
812	#undef PGM_GST_NAME_RC_STR
813	#undef PGM_GST_NAME_R0_STR
814
815	/* Guest - PAE mode */
816	#define PGM_GST_TYPE PGM_TYPE_PAE
817	#define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
818	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PAE_STR(name)
819	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PAE_STR(name)
820	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_PAE(name)
821	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_PAE_PAE_STR(name)
822	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_PAE_STR(name)
823	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
824	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
825	#include "PGMGst.h"
826	#include "PGMBth.h"
827	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
828	#undef BTH_PGMPOOLKIND_PT_FOR_PT
829	#undef PGM_BTH_NAME
830	#undef PGM_BTH_NAME_RC_STR
831	#undef PGM_BTH_NAME_R0_STR
832	#undef PGM_GST_TYPE
833	#undef PGM_GST_NAME
834	#undef PGM_GST_NAME_RC_STR
835	#undef PGM_GST_NAME_R0_STR
836
837	#undef PGM_SHW_TYPE
838	#undef PGM_SHW_NAME
839	#undef PGM_SHW_NAME_RC_STR
840	#undef PGM_SHW_NAME_R0_STR
841
842
843	/*
844	* Shadow - AMD64 mode
845	*/
846	#define PGM_SHW_TYPE PGM_TYPE_AMD64
847	#define PGM_SHW_NAME(name) PGM_SHW_NAME_AMD64(name)
848	#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_AMD64_STR(name)
849	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_AMD64_STR(name)
850	#include "PGMShw.h"
851
852	#ifdef VBOX_WITH_64_BITS_GUESTS
853	/* Guest - AMD64 mode */
854	# define PGM_GST_TYPE PGM_TYPE_AMD64
855	# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
856	# define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_AMD64_STR(name)
857	# define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_AMD64_STR(name)
858	# define PGM_BTH_NAME(name) PGM_BTH_NAME_AMD64_AMD64(name)
859	# define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_AMD64_AMD64_STR(name)
860	# define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_AMD64_AMD64_STR(name)
861	# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
862	# define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
863	# include "PGMGst.h"
864	# include "PGMBth.h"
865	# undef BTH_PGMPOOLKIND_PT_FOR_BIG
866	# undef BTH_PGMPOOLKIND_PT_FOR_PT
867	# undef PGM_BTH_NAME
868	# undef PGM_BTH_NAME_RC_STR
869	# undef PGM_BTH_NAME_R0_STR
870	# undef PGM_GST_TYPE
871	# undef PGM_GST_NAME
872	# undef PGM_GST_NAME_RC_STR
873	# undef PGM_GST_NAME_R0_STR
874	#endif /* VBOX_WITH_64_BITS_GUESTS */
875
876	#undef PGM_SHW_TYPE
877	#undef PGM_SHW_NAME
878	#undef PGM_SHW_NAME_RC_STR
879	#undef PGM_SHW_NAME_R0_STR
880
881
882	/*
883	* Shadow - Nested paging mode
884	*/
885	#define PGM_SHW_TYPE PGM_TYPE_NESTED
886	#define PGM_SHW_NAME(name) PGM_SHW_NAME_NESTED(name)
887	#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_NESTED_STR(name)
888	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_NESTED_STR(name)
889	#include "PGMShw.h"
890
891	/* Guest - real mode */
892	#define PGM_GST_TYPE PGM_TYPE_REAL
893	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
894	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_REAL_STR(name)
895	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
896	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_REAL(name)
897	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_REAL_STR(name)
898	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_REAL_STR(name)
899	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
900	#include "PGMBth.h"
901	#undef BTH_PGMPOOLKIND_PT_FOR_PT
902	#undef PGM_BTH_NAME
903	#undef PGM_BTH_NAME_RC_STR
904	#undef PGM_BTH_NAME_R0_STR
905	#undef PGM_GST_TYPE
906	#undef PGM_GST_NAME
907	#undef PGM_GST_NAME_RC_STR
908	#undef PGM_GST_NAME_R0_STR
909
910	/* Guest - protected mode */
911	#define PGM_GST_TYPE PGM_TYPE_PROT
912	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
913	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PROT_STR(name)
914	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
915	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_PROT(name)
916	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_PROT_STR(name)
917	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_PROT_STR(name)
918	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
919	#include "PGMBth.h"
920	#undef BTH_PGMPOOLKIND_PT_FOR_PT
921	#undef PGM_BTH_NAME
922	#undef PGM_BTH_NAME_RC_STR
923	#undef PGM_BTH_NAME_R0_STR
924	#undef PGM_GST_TYPE
925	#undef PGM_GST_NAME
926	#undef PGM_GST_NAME_RC_STR
927	#undef PGM_GST_NAME_R0_STR
928
929	/* Guest - 32-bit mode */
930	#define PGM_GST_TYPE PGM_TYPE_32BIT
931	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
932	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_32BIT_STR(name)
933	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
934	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_32BIT(name)
935	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_32BIT_STR(name)
936	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_32BIT_STR(name)
937	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_32BIT_PT
938	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB
939	#include "PGMBth.h"
940	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
941	#undef BTH_PGMPOOLKIND_PT_FOR_PT
942	#undef PGM_BTH_NAME
943	#undef PGM_BTH_NAME_RC_STR
944	#undef PGM_BTH_NAME_R0_STR
945	#undef PGM_GST_TYPE
946	#undef PGM_GST_NAME
947	#undef PGM_GST_NAME_RC_STR
948	#undef PGM_GST_NAME_R0_STR
949
950	/* Guest - PAE mode */
951	#define PGM_GST_TYPE PGM_TYPE_PAE
952	#define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
953	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PAE_STR(name)
954	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PAE_STR(name)
955	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_PAE(name)
956	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_PAE_STR(name)
957	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_PAE_STR(name)
958	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
959	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
960	#include "PGMBth.h"
961	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
962	#undef BTH_PGMPOOLKIND_PT_FOR_PT
963	#undef PGM_BTH_NAME
964	#undef PGM_BTH_NAME_RC_STR
965	#undef PGM_BTH_NAME_R0_STR
966	#undef PGM_GST_TYPE
967	#undef PGM_GST_NAME
968	#undef PGM_GST_NAME_RC_STR
969	#undef PGM_GST_NAME_R0_STR
970
971	#ifdef VBOX_WITH_64_BITS_GUESTS
972	/* Guest - AMD64 mode */
973	# define PGM_GST_TYPE PGM_TYPE_AMD64
974	# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
975	# define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_AMD64_STR(name)
976	# define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_AMD64_STR(name)
977	# define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_AMD64(name)
978	# define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_AMD64_STR(name)
979	# define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_AMD64_STR(name)
980	# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
981	# define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
982	# include "PGMBth.h"
983	# undef BTH_PGMPOOLKIND_PT_FOR_BIG
984	# undef BTH_PGMPOOLKIND_PT_FOR_PT
985	# undef PGM_BTH_NAME
986	# undef PGM_BTH_NAME_RC_STR
987	# undef PGM_BTH_NAME_R0_STR
988	# undef PGM_GST_TYPE
989	# undef PGM_GST_NAME
990	# undef PGM_GST_NAME_RC_STR
991	# undef PGM_GST_NAME_R0_STR
992	#endif /* VBOX_WITH_64_BITS_GUESTS */
993
994	#undef PGM_SHW_TYPE
995	#undef PGM_SHW_NAME
996	#undef PGM_SHW_NAME_RC_STR
997	#undef PGM_SHW_NAME_R0_STR
998
999
1000	/*
1001	* Shadow - EPT
1002	*/
1003	#define PGM_SHW_TYPE PGM_TYPE_EPT
1004	#define PGM_SHW_NAME(name) PGM_SHW_NAME_EPT(name)
1005	#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_EPT_STR(name)
1006	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_EPT_STR(name)
1007	#include "PGMShw.h"
1008
1009	/* Guest - real mode */
1010	#define PGM_GST_TYPE PGM_TYPE_REAL
1011	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
1012	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_REAL_STR(name)
1013	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
1014	#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_REAL(name)
1015	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_REAL_STR(name)
1016	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_REAL_STR(name)
1017	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
1018	#include "PGMBth.h"
1019	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1020	#undef PGM_BTH_NAME
1021	#undef PGM_BTH_NAME_RC_STR
1022	#undef PGM_BTH_NAME_R0_STR
1023	#undef PGM_GST_TYPE
1024	#undef PGM_GST_NAME
1025	#undef PGM_GST_NAME_RC_STR
1026	#undef PGM_GST_NAME_R0_STR
1027
1028	/* Guest - protected mode */
1029	#define PGM_GST_TYPE PGM_TYPE_PROT
1030	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
1031	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PROT_STR(name)
1032	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
1033	#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_PROT(name)
1034	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_PROT_STR(name)
1035	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_PROT_STR(name)
1036	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
1037	#include "PGMBth.h"
1038	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1039	#undef PGM_BTH_NAME
1040	#undef PGM_BTH_NAME_RC_STR
1041	#undef PGM_BTH_NAME_R0_STR
1042	#undef PGM_GST_TYPE
1043	#undef PGM_GST_NAME
1044	#undef PGM_GST_NAME_RC_STR
1045	#undef PGM_GST_NAME_R0_STR
1046
1047	/* Guest - 32-bit mode */
1048	#define PGM_GST_TYPE PGM_TYPE_32BIT
1049	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
1050	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_32BIT_STR(name)
1051	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
1052	#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_32BIT(name)
1053	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_32BIT_STR(name)
1054	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_32BIT_STR(name)
1055	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_32BIT_PT
1056	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB
1057	#include "PGMBth.h"
1058	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
1059	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1060	#undef PGM_BTH_NAME
1061	#undef PGM_BTH_NAME_RC_STR
1062	#undef PGM_BTH_NAME_R0_STR
1063	#undef PGM_GST_TYPE
1064	#undef PGM_GST_NAME
1065	#undef PGM_GST_NAME_RC_STR
1066	#undef PGM_GST_NAME_R0_STR
1067
1068	/* Guest - PAE mode */
1069	#define PGM_GST_TYPE PGM_TYPE_PAE
1070	#define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
1071	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PAE_STR(name)
1072	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PAE_STR(name)
1073	#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_PAE(name)
1074	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_PAE_STR(name)
1075	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_PAE_STR(name)
1076	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
1077	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
1078	#include "PGMBth.h"
1079	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
1080	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1081	#undef PGM_BTH_NAME
1082	#undef PGM_BTH_NAME_RC_STR
1083	#undef PGM_BTH_NAME_R0_STR
1084	#undef PGM_GST_TYPE
1085	#undef PGM_GST_NAME
1086	#undef PGM_GST_NAME_RC_STR
1087	#undef PGM_GST_NAME_R0_STR
1088
1089	#ifdef VBOX_WITH_64_BITS_GUESTS
1090	/* Guest - AMD64 mode */
1091	# define PGM_GST_TYPE PGM_TYPE_AMD64
1092	# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
1093	# define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_AMD64_STR(name)
1094	# define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_AMD64_STR(name)
1095	# define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_AMD64(name)
1096	# define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_AMD64_STR(name)
1097	# define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_AMD64_STR(name)
1098	# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
1099	# define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
1100	# include "PGMBth.h"
1101	# undef BTH_PGMPOOLKIND_PT_FOR_BIG
1102	# undef BTH_PGMPOOLKIND_PT_FOR_PT
1103	# undef PGM_BTH_NAME
1104	# undef PGM_BTH_NAME_RC_STR
1105	# undef PGM_BTH_NAME_R0_STR
1106	# undef PGM_GST_TYPE
1107	# undef PGM_GST_NAME
1108	# undef PGM_GST_NAME_RC_STR
1109	# undef PGM_GST_NAME_R0_STR
1110	#endif /* VBOX_WITH_64_BITS_GUESTS */
1111
1112	#undef PGM_SHW_TYPE
1113	#undef PGM_SHW_NAME
1114	#undef PGM_SHW_NAME_RC_STR
1115	#undef PGM_SHW_NAME_R0_STR
1116
1117
1118
1119	/**
1120	* Initiates the paging of VM.
1121	*
1122	* @returns VBox status code.
1123	* @param pVM Pointer to VM structure.
1124	*/
1125	VMMR3DECL(int) PGMR3Init(PVM pVM)
1126	{
1127	LogFlow(("PGMR3Init:\n"));
1128
1129	/*
1130	* Assert alignment and sizes.
1131	*/
1132	AssertRelease(sizeof(pVM->pgm.s) <= sizeof(pVM->pgm.padding));
1133
1134	/*
1135	* Init the structure.
1136	*/
1137	pVM->pgm.s.offVM = RT_OFFSETOF(VM, pgm.s);
1138	pVM->pgm.s.offVCpu = RT_OFFSETOF(VMCPU, pgm.s);
1139	pVM->pgm.s.enmShadowMode = PGMMODE_INVALID;
1140	pVM->pgm.s.enmGuestMode = PGMMODE_INVALID;
1141	pVM->pgm.s.enmHostMode = SUPPAGINGMODE_INVALID;
1142	pVM->pgm.s.GCPhysCR3 = NIL_RTGCPHYS;
1143	pVM->pgm.s.GCPhysGstCR3Monitored = NIL_RTGCPHYS;
1144	pVM->pgm.s.fA20Enabled = true;
1145	pVM->pgm.s.GCPhys4MBPSEMask = RT_BIT_64(32) - 1; /* default; checked later */
1146	pVM->pgm.s.pGstPaePdptR3 = NULL;
1147	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
1148	pVM->pgm.s.pGstPaePdptR0 = NIL_RTR0PTR;
1149	#endif
1150	pVM->pgm.s.pGstPaePdptRC = NIL_RTRCPTR;
1151	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.apGstPaePDsR3); i++)
1152	{
1153	pVM->pgm.s.apGstPaePDsR3[i] = NULL;
1154	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
1155	pVM->pgm.s.apGstPaePDsR0[i] = NIL_RTR0PTR;
1156	#endif
1157	pVM->pgm.s.apGstPaePDsRC[i] = NIL_RTRCPTR;
1158	pVM->pgm.s.aGCPhysGstPaePDs[i] = NIL_RTGCPHYS;
1159	pVM->pgm.s.aGCPhysGstPaePDsMonitored[i] = NIL_RTGCPHYS;
1160	}
1161
1162	#ifdef VBOX_STRICT
1163	VMR3AtStateRegister(pVM, pgmR3ResetNoMorePhysWritesFlag, NULL);
1164	#endif
1165
1166	/*
1167	* Get the configured RAM size - to estimate saved state size.
1168	*/
1169	uint64_t cbRam;
1170	int rc = CFGMR3QueryU64(CFGMR3GetRoot(pVM), "RamSize", &cbRam);
1171	if (rc == VERR_CFGM_VALUE_NOT_FOUND)
1172	cbRam = pVM->pgm.s.cbRamSize = 0;
1173	else if (RT_SUCCESS(rc))
1174	{
1175	if (cbRam < PAGE_SIZE)
1176	cbRam = 0;
1177	cbRam = RT_ALIGN_64(cbRam, PAGE_SIZE);
1178	pVM->pgm.s.cbRamSize = (RTUINT)cbRam;
1179	}
1180	else
1181	{
1182	AssertMsgFailed(("Configuration error: Failed to query integer \"RamSize\", rc=%Rrc.\n", rc));
1183	return rc;
1184	}
1185
1186	/*
1187	* Register saved state data unit.
1188	*/
1189	rc = SSMR3RegisterInternal(pVM, "pgm", 1, PGM_SAVED_STATE_VERSION, (size_t)cbRam + sizeof(PGM),
1190	NULL, pgmR3Save, NULL,
1191	NULL, pgmR3Load, NULL);
1192	if (RT_FAILURE(rc))
1193	return rc;
1194
1195	/*
1196	* Initialize the PGM critical section and flush the phys TLBs
1197	*/
1198	rc = PDMR3CritSectInit(pVM, &pVM->pgm.s.CritSect, "PGM");
1199	AssertRCReturn(rc, rc);
1200
1201	PGMR3PhysChunkInvalidateTLB(pVM);
1202	PGMPhysInvalidatePageR3MapTLB(pVM);
1203	PGMPhysInvalidatePageR0MapTLB(pVM);
1204	PGMPhysInvalidatePageGCMapTLB(pVM);
1205
1206	/*
1207	* Trees
1208	*/
1209	rc = MMHyperAlloc(pVM, sizeof(PGMTREES), 0, MM_TAG_PGM, (void **)&pVM->pgm.s.pTreesR3);
1210	if (RT_SUCCESS(rc))
1211	{
1212	pVM->pgm.s.pTreesR0 = MMHyperR3ToR0(pVM, pVM->pgm.s.pTreesR3);
1213	pVM->pgm.s.pTreesRC = MMHyperR3ToRC(pVM, pVM->pgm.s.pTreesR3);
1214
1215	/*
1216	* Alocate the zero page.
1217	*/
1218	rc = MMHyperAlloc(pVM, PAGE_SIZE, PAGE_SIZE, MM_TAG_PGM, &pVM->pgm.s.pvZeroPgR3);
1219	}
1220	if (RT_SUCCESS(rc))
1221	{
1222	pVM->pgm.s.pvZeroPgGC = MMHyperR3ToRC(pVM, pVM->pgm.s.pvZeroPgR3);
1223	pVM->pgm.s.pvZeroPgR0 = MMHyperR3ToR0(pVM, pVM->pgm.s.pvZeroPgR3);
1224	AssertRelease(pVM->pgm.s.pvZeroPgR0 != NIL_RTHCPHYS);
1225	pVM->pgm.s.HCPhysZeroPg = MMR3HyperHCVirt2HCPhys(pVM, pVM->pgm.s.pvZeroPgR3);
1226	AssertRelease(pVM->pgm.s.HCPhysZeroPg != NIL_RTHCPHYS);
1227
1228	/*
1229	* Init the paging.
1230	*/
1231	rc = pgmR3InitPaging(pVM);
1232	}
1233	if (RT_SUCCESS(rc))
1234	{
1235	/*
1236	* Init the page pool.
1237	*/
1238	rc = pgmR3PoolInit(pVM);
1239	}
1240	if (RT_SUCCESS(rc))
1241	{
1242	/*
1243	* Info & statistics
1244	*/
1245	DBGFR3InfoRegisterInternal(pVM, "mode",
1246	"Shows the current paging mode. "
1247	"Recognizes 'all', 'guest', 'shadow' and 'host' as arguments, defaulting to 'all' if nothing's given.",
1248	pgmR3InfoMode);
1249	DBGFR3InfoRegisterInternal(pVM, "pgmcr3",
1250	"Dumps all the entries in the top level paging table. No arguments.",
1251	pgmR3InfoCr3);
1252	DBGFR3InfoRegisterInternal(pVM, "phys",
1253	"Dumps all the physical address ranges. No arguments.",
1254	pgmR3PhysInfo);
1255	DBGFR3InfoRegisterInternal(pVM, "handlers",
1256	"Dumps physical, virtual and hyper virtual handlers. "
1257	"Pass 'phys', 'virt', 'hyper' as argument if only one kind is wanted."
1258	"Add 'nost' if the statistics are unwanted, use together with 'all' or explicit selection.",
1259	pgmR3InfoHandlers);
1260	DBGFR3InfoRegisterInternal(pVM, "mappings",
1261	"Dumps guest mappings.",
1262	pgmR3MapInfo);
1263
1264	STAM_REL_REG(pVM, &pVM->pgm.s.cGuestModeChanges, STAMTYPE_COUNTER, "/PGM/cGuestModeChanges", STAMUNIT_OCCURENCES, "Number of guest mode changes.");
1265	#ifdef VBOX_WITH_STATISTICS
1266	pgmR3InitStats(pVM);
1267	#endif
1268	#ifdef VBOX_WITH_DEBUGGER
1269	/*
1270	* Debugger commands.
1271	*/
1272	static bool fRegisteredCmds = false;
1273	if (!fRegisteredCmds)
1274	{
1275	int rc = DBGCRegisterCommands(&g_aCmds[0], RT_ELEMENTS(g_aCmds));
1276	if (RT_SUCCESS(rc))
1277	fRegisteredCmds = true;
1278	}
1279	#endif
1280	return VINF_SUCCESS;
1281	}
1282
1283	/* Almost no cleanup necessary, MM frees all memory. */
1284	PDMR3CritSectDelete(&pVM->pgm.s.CritSect);
1285
1286	return rc;
1287	}
1288
1289
1290	/**
1291	* Initializes the per-VCPU PGM.
1292	*
1293	* @returns VBox status code.
1294	* @param pVM The VM to operate on.
1295	*/
1296	VMMR3DECL(int) PGMR3InitCPU(PVM pVM)
1297	{
1298	LogFlow(("PGMR3InitCPU\n"));
1299	return VINF_SUCCESS;
1300	}
1301
1302
1303	/**
1304	* Init paging.
1305	*
1306	* Since we need to check what mode the host is operating in before we can choose
1307	* the right paging functions for the host we have to delay this until R0 has
1308	* been initialized.
1309	*
1310	* @returns VBox status code.
1311	* @param pVM VM handle.
1312	*/
1313	static int pgmR3InitPaging(PVM pVM)
1314	{
1315	/*
1316	* Force a recalculation of modes and switcher so everyone gets notified.
1317	*/
1318	pVM->pgm.s.enmShadowMode = PGMMODE_INVALID;
1319	pVM->pgm.s.enmGuestMode = PGMMODE_INVALID;
1320	pVM->pgm.s.enmHostMode = SUPPAGINGMODE_INVALID;
1321
1322	/*
1323	* Allocate static mapping space for whatever the cr3 register
1324	* points to and in the case of PAE mode to the 4 PDs.
1325	*/
1326	int rc = MMR3HyperReserve(pVM, PAGE_SIZE * 5, "CR3 mapping", &pVM->pgm.s.GCPtrCR3Mapping);
1327	if (RT_FAILURE(rc))
1328	{
1329	AssertMsgFailed(("Failed to reserve two pages for cr mapping in HMA, rc=%Rrc\n", rc));
1330	return rc;
1331	}
1332	MMR3HyperReserve(pVM, PAGE_SIZE, "fence", NULL);
1333
1334	/*
1335	* Allocate pages for the three possible intermediate contexts
1336	* (AMD64, PAE and plain 32-Bit). We maintain all three contexts
1337	* for the sake of simplicity. The AMD64 uses the PAE for the
1338	* lower levels, making the total number of pages 11 (3 + 7 + 1).
1339	*
1340	* We assume that two page tables will be enought for the core code
1341	* mappings (HC virtual and identity).
1342	*/
1343	pVM->pgm.s.pInterPD = (PX86PD)MMR3PageAllocLow(pVM);
1344	pVM->pgm.s.apInterPTs[0] = (PX86PT)MMR3PageAllocLow(pVM);
1345	pVM->pgm.s.apInterPTs[1] = (PX86PT)MMR3PageAllocLow(pVM);
1346	pVM->pgm.s.apInterPaePTs[0] = (PX86PTPAE)MMR3PageAlloc(pVM);
1347	pVM->pgm.s.apInterPaePTs[1] = (PX86PTPAE)MMR3PageAlloc(pVM);
1348	pVM->pgm.s.apInterPaePDs[0] = (PX86PDPAE)MMR3PageAlloc(pVM);
1349	pVM->pgm.s.apInterPaePDs[1] = (PX86PDPAE)MMR3PageAlloc(pVM);
1350	pVM->pgm.s.apInterPaePDs[2] = (PX86PDPAE)MMR3PageAlloc(pVM);
1351	pVM->pgm.s.apInterPaePDs[3] = (PX86PDPAE)MMR3PageAlloc(pVM);
1352	pVM->pgm.s.pInterPaePDPT = (PX86PDPT)MMR3PageAllocLow(pVM);
1353	pVM->pgm.s.pInterPaePDPT64 = (PX86PDPT)MMR3PageAllocLow(pVM);
1354	pVM->pgm.s.pInterPaePML4 = (PX86PML4)MMR3PageAllocLow(pVM);
1355	if ( !pVM->pgm.s.pInterPD
1356	\|\| !pVM->pgm.s.apInterPTs[0]
1357	\|\| !pVM->pgm.s.apInterPTs[1]
1358	\|\| !pVM->pgm.s.apInterPaePTs[0]
1359	\|\| !pVM->pgm.s.apInterPaePTs[1]
1360	\|\| !pVM->pgm.s.apInterPaePDs[0]
1361	\|\| !pVM->pgm.s.apInterPaePDs[1]
1362	\|\| !pVM->pgm.s.apInterPaePDs[2]
1363	\|\| !pVM->pgm.s.apInterPaePDs[3]
1364	\|\| !pVM->pgm.s.pInterPaePDPT
1365	\|\| !pVM->pgm.s.pInterPaePDPT64
1366	\|\| !pVM->pgm.s.pInterPaePML4)
1367	{
1368	AssertMsgFailed(("Failed to allocate pages for the intermediate context!\n"));
1369	return VERR_NO_PAGE_MEMORY;
1370	}
1371
1372	pVM->pgm.s.HCPhysInterPD = MMPage2Phys(pVM, pVM->pgm.s.pInterPD);
1373	AssertRelease(pVM->pgm.s.HCPhysInterPD != NIL_RTHCPHYS && !(pVM->pgm.s.HCPhysInterPD & PAGE_OFFSET_MASK));
1374	pVM->pgm.s.HCPhysInterPaePDPT = MMPage2Phys(pVM, pVM->pgm.s.pInterPaePDPT);
1375	AssertRelease(pVM->pgm.s.HCPhysInterPaePDPT != NIL_RTHCPHYS && !(pVM->pgm.s.HCPhysInterPaePDPT & PAGE_OFFSET_MASK));
1376	pVM->pgm.s.HCPhysInterPaePML4 = MMPage2Phys(pVM, pVM->pgm.s.pInterPaePML4);
1377	AssertRelease(pVM->pgm.s.HCPhysInterPaePML4 != NIL_RTHCPHYS && !(pVM->pgm.s.HCPhysInterPaePML4 & PAGE_OFFSET_MASK));
1378
1379	/*
1380	* Initialize the pages, setting up the PML4 and PDPT for repetitive 4GB action.
1381	*/
1382	ASMMemZeroPage(pVM->pgm.s.pInterPD);
1383	ASMMemZeroPage(pVM->pgm.s.apInterPTs[0]);
1384	ASMMemZeroPage(pVM->pgm.s.apInterPTs[1]);
1385
1386	ASMMemZeroPage(pVM->pgm.s.apInterPaePTs[0]);
1387	ASMMemZeroPage(pVM->pgm.s.apInterPaePTs[1]);
1388
1389	ASMMemZeroPage(pVM->pgm.s.pInterPaePDPT);
1390	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.apInterPaePDs); i++)
1391	{
1392	ASMMemZeroPage(pVM->pgm.s.apInterPaePDs[i]);
1393	pVM->pgm.s.pInterPaePDPT->a[i].u = X86_PDPE_P \| PGM_PLXFLAGS_PERMANENT
1394	\| MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[i]);
1395	}
1396
1397	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.pInterPaePDPT64->a); i++)
1398	{
1399	const unsigned iPD = i % RT_ELEMENTS(pVM->pgm.s.apInterPaePDs);
1400	pVM->pgm.s.pInterPaePDPT64->a[i].u = X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_A \| PGM_PLXFLAGS_PERMANENT
1401	\| MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[iPD]);
1402	}
1403
1404	RTHCPHYS HCPhysInterPaePDPT64 = MMPage2Phys(pVM, pVM->pgm.s.pInterPaePDPT64);
1405	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.pInterPaePML4->a); i++)
1406	pVM->pgm.s.pInterPaePML4->a[i].u = X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_A \| PGM_PLXFLAGS_PERMANENT
1407	\| HCPhysInterPaePDPT64;
1408
1409	/*
1410	* Allocate pages for the three possible guest contexts (AMD64, PAE and plain 32-Bit).
1411	* We allocate pages for all three posibilities in order to simplify mappings and
1412	* avoid resource failure during mode switches. So, we need to cover all levels of the
1413	* of the first 4GB down to PD level.
1414	* As with the intermediate context, AMD64 uses the PAE PDPT and PDs.
1415	*/
1416	#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
1417	pVM->pgm.s.pShw32BitPdR3 = (PX86PD)MMR3PageAllocLow(pVM);
1418	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
1419	pVM->pgm.s.pShw32BitPdR0 = (uintptr_t)pVM->pgm.s.pShw32BitPdR3;
1420	# endif
1421	pVM->pgm.s.apShwPaePDsR3[0] = (PX86PDPAE)MMR3PageAlloc(pVM);
1422	pVM->pgm.s.apShwPaePDsR3[1] = (PX86PDPAE)MMR3PageAlloc(pVM);
1423	AssertRelease((uintptr_t)pVM->pgm.s.apShwPaePDsR3[0] + PAGE_SIZE == (uintptr_t)pVM->pgm.s.apShwPaePDsR3[1]);
1424	pVM->pgm.s.apShwPaePDsR3[2] = (PX86PDPAE)MMR3PageAlloc(pVM);
1425	AssertRelease((uintptr_t)pVM->pgm.s.apShwPaePDsR3[1] + PAGE_SIZE == (uintptr_t)pVM->pgm.s.apShwPaePDsR3[2]);
1426	pVM->pgm.s.apShwPaePDsR3[3] = (PX86PDPAE)MMR3PageAlloc(pVM);
1427	AssertRelease((uintptr_t)pVM->pgm.s.apShwPaePDsR3[2] + PAGE_SIZE == (uintptr_t)pVM->pgm.s.apShwPaePDsR3[3]);
1428	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
1429	pVM->pgm.s.apShwPaePDsR0[0] = (uintptr_t)pVM->pgm.s.apShwPaePDsR3[0];
1430	pVM->pgm.s.apShwPaePDsR0[1] = (uintptr_t)pVM->pgm.s.apShwPaePDsR3[1];
1431	pVM->pgm.s.apShwPaePDsR0[2] = (uintptr_t)pVM->pgm.s.apShwPaePDsR3[2];
1432	pVM->pgm.s.apShwPaePDsR0[3] = (uintptr_t)pVM->pgm.s.apShwPaePDsR3[3];
1433	# endif
1434	pVM->pgm.s.pShwPaePdptR3 = (PX86PDPT)MMR3PageAllocLow(pVM);
1435	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
1436	pVM->pgm.s.pShwPaePdptR0 = (uintptr_t)pVM->pgm.s.pShwPaePdptR3;
1437	# endif
1438	#endif /* VBOX_WITH_PGMPOOL_PAGING_ONLY */
1439	pVM->pgm.s.pShwNestedRootR3 = MMR3PageAllocLow(pVM);
1440	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
1441	pVM->pgm.s.pShwNestedRootR0 = (uintptr_t)pVM->pgm.s.pShwNestedRootR3;
1442	#endif
1443
1444	#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
1445	if (!pVM->pgm.s.pShwNestedRootR3)
1446	#else
1447	if ( !pVM->pgm.s.pShw32BitPdR3
1448	\|\| !pVM->pgm.s.apShwPaePDsR3[0]
1449	\|\| !pVM->pgm.s.apShwPaePDsR3[1]
1450	\|\| !pVM->pgm.s.apShwPaePDsR3[2]
1451	\|\| !pVM->pgm.s.apShwPaePDsR3[3]
1452	\|\| !pVM->pgm.s.pShwPaePdptR3
1453	\|\| !pVM->pgm.s.pShwNestedRootR3)
1454	#endif
1455	{
1456	AssertMsgFailed(("Failed to allocate pages for the intermediate context!\n"));
1457	return VERR_NO_PAGE_MEMORY;
1458	}
1459
1460	/* get physical addresses. */
1461	#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
1462	pVM->pgm.s.HCPhysShw32BitPD = MMPage2Phys(pVM, pVM->pgm.s.pShw32BitPdR3);
1463	Assert(MMPagePhys2Page(pVM, pVM->pgm.s.HCPhysShw32BitPD) == pVM->pgm.s.pShw32BitPdR3);
1464	pVM->pgm.s.aHCPhysPaePDs[0] = MMPage2Phys(pVM, pVM->pgm.s.apShwPaePDsR3[0]);
1465	pVM->pgm.s.aHCPhysPaePDs[1] = MMPage2Phys(pVM, pVM->pgm.s.apShwPaePDsR3[1]);
1466	pVM->pgm.s.aHCPhysPaePDs[2] = MMPage2Phys(pVM, pVM->pgm.s.apShwPaePDsR3[2]);
1467	pVM->pgm.s.aHCPhysPaePDs[3] = MMPage2Phys(pVM, pVM->pgm.s.apShwPaePDsR3[3]);
1468	pVM->pgm.s.HCPhysShwPaePdpt = MMPage2Phys(pVM, pVM->pgm.s.pShwPaePdptR3);
1469	#endif
1470	pVM->pgm.s.HCPhysShwNestedRoot = MMPage2Phys(pVM, pVM->pgm.s.pShwNestedRootR3);
1471
1472	/*
1473	* Initialize the pages, setting up the PML4 and PDPT for action below 4GB.
1474	*/
1475	#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
1476	ASMMemZero32(pVM->pgm.s.pShw32BitPdR3, PAGE_SIZE);
1477	ASMMemZero32(pVM->pgm.s.pShwPaePdptR3, PAGE_SIZE);
1478	#endif
1479	ASMMemZero32(pVM->pgm.s.pShwNestedRootR3, PAGE_SIZE);
1480	#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
1481	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.apShwPaePDsR3); i++)
1482	{
1483	ASMMemZero32(pVM->pgm.s.apShwPaePDsR3[i], PAGE_SIZE);
1484	pVM->pgm.s.pShwPaePdptR3->a[i].u = X86_PDPE_P \| PGM_PLXFLAGS_PERMANENT \| pVM->pgm.s.aHCPhysPaePDs[i];
1485	/* The flags will be corrected when entering and leaving long mode. */
1486	}
1487
1488	CPUMSetHyperCR3(pVM, (uint32_t)pVM->pgm.s.HCPhysShw32BitPD);
1489	#endif
1490
1491	/*
1492	* Initialize paging workers and mode from current host mode
1493	* and the guest running in real mode.
1494	*/
1495	pVM->pgm.s.enmHostMode = SUPGetPagingMode();
1496	switch (pVM->pgm.s.enmHostMode)
1497	{
1498	case SUPPAGINGMODE_32_BIT:
1499	case SUPPAGINGMODE_32_BIT_GLOBAL:
1500	case SUPPAGINGMODE_PAE:
1501	case SUPPAGINGMODE_PAE_GLOBAL:
1502	case SUPPAGINGMODE_PAE_NX:
1503	case SUPPAGINGMODE_PAE_GLOBAL_NX:
1504	break;
1505
1506	case SUPPAGINGMODE_AMD64:
1507	case SUPPAGINGMODE_AMD64_GLOBAL:
1508	case SUPPAGINGMODE_AMD64_NX:
1509	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
1510	#ifndef VBOX_WITH_HYBIRD_32BIT_KERNEL
1511	if (ARCH_BITS != 64)
1512	{
1513	AssertMsgFailed(("Host mode %d (64-bit) is not supported by non-64bit builds\n", pVM->pgm.s.enmHostMode));
1514	LogRel(("Host mode %d (64-bit) is not supported by non-64bit builds\n", pVM->pgm.s.enmHostMode));
1515	return VERR_PGM_UNSUPPORTED_HOST_PAGING_MODE;
1516	}
1517	#endif
1518	break;
1519	default:
1520	AssertMsgFailed(("Host mode %d is not supported\n", pVM->pgm.s.enmHostMode));
1521	return VERR_PGM_UNSUPPORTED_HOST_PAGING_MODE;
1522	}
1523	rc = pgmR3ModeDataInit(pVM, false /* don't resolve GC and R0 syms yet */);
1524	if (RT_SUCCESS(rc))
1525	rc = PGMR3ChangeMode(pVM, PGMMODE_REAL);
1526	if (RT_SUCCESS(rc))
1527	{
1528	LogFlow(("pgmR3InitPaging: returns successfully\n"));
1529	#if HC_ARCH_BITS == 64
1530	# ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
1531	LogRel(("Debug: HCPhysShw32BitPD=%RHp aHCPhysPaePDs={%RHp,%RHp,%RHp,%RHp} HCPhysShwPaePdpt=%RHp HCPhysShwPaePml4=%RHp\n",
1532	pVM->pgm.s.HCPhysShw32BitPD,
1533	pVM->pgm.s.aHCPhysPaePDs[0], pVM->pgm.s.aHCPhysPaePDs[1], pVM->pgm.s.aHCPhysPaePDs[2], pVM->pgm.s.aHCPhysPaePDs[3],
1534	pVM->pgm.s.HCPhysShwPaePdpt,
1535	pVM->pgm.s.HCPhysShwPaePml4));
1536	# endif
1537	LogRel(("Debug: HCPhysInterPD=%RHp HCPhysInterPaePDPT=%RHp HCPhysInterPaePML4=%RHp\n",
1538	pVM->pgm.s.HCPhysInterPD, pVM->pgm.s.HCPhysInterPaePDPT, pVM->pgm.s.HCPhysInterPaePML4));
1539	LogRel(("Debug: apInterPTs={%RHp,%RHp} apInterPaePTs={%RHp,%RHp} apInterPaePDs={%RHp,%RHp,%RHp,%RHp} pInterPaePDPT64=%RHp\n",
1540	MMPage2Phys(pVM, pVM->pgm.s.apInterPTs[0]), MMPage2Phys(pVM, pVM->pgm.s.apInterPTs[1]),
1541	MMPage2Phys(pVM, pVM->pgm.s.apInterPaePTs[0]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePTs[1]),
1542	MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[0]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[1]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[2]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[3]),
1543	MMPage2Phys(pVM, pVM->pgm.s.pInterPaePDPT64)));
1544	#endif
1545
1546	return VINF_SUCCESS;
1547	}
1548
1549	LogFlow(("pgmR3InitPaging: returns %Rrc\n", rc));
1550	return rc;
1551	}
1552
1553
1554	#ifdef VBOX_WITH_STATISTICS
1555	/**
1556	* Init statistics
1557	*/
1558	static void pgmR3InitStats(PVM pVM)
1559	{
1560	PPGM pPGM = &pVM->pgm.s;
1561	unsigned i;
1562
1563	/*
1564	* Note! The layout of this function matches the member layout exactly!
1565	*/
1566
1567	/* Common - misc variables */
1568	STAM_REG(pVM, &pPGM->cAllPages, STAMTYPE_U32, "/PGM/Page/cAllPages", STAMUNIT_OCCURENCES, "The total number of pages.");
1569	STAM_REG(pVM, &pPGM->cPrivatePages, STAMTYPE_U32, "/PGM/Page/cPrivatePages", STAMUNIT_OCCURENCES, "The number of private pages.");
1570	STAM_REG(pVM, &pPGM->cSharedPages, STAMTYPE_U32, "/PGM/Page/cSharedPages", STAMUNIT_OCCURENCES, "The number of shared pages.");
1571	STAM_REG(pVM, &pPGM->cZeroPages, STAMTYPE_U32, "/PGM/Page/cZeroPages", STAMUNIT_OCCURENCES, "The number of zero backed pages.");
1572	STAM_REG(pVM, &pPGM->ChunkR3Map.c, STAMTYPE_U32, "/PGM/ChunkR3Map/c", STAMUNIT_OCCURENCES, "Number of mapped chunks.");
1573	STAM_REG(pVM, &pPGM->ChunkR3Map.cMax, STAMTYPE_U32, "/PGM/ChunkR3Map/cMax", STAMUNIT_OCCURENCES, "Maximum number of mapped chunks.");
1574
1575	/* Common - stats */
1576	#ifdef PGMPOOL_WITH_GCPHYS_TRACKING
1577	STAM_REG(pVM, &pPGM->StatTrackVirgin, STAMTYPE_COUNTER, "/PGM/Track/Virgin", STAMUNIT_OCCURENCES, "The number of first time shadowings");
1578	STAM_REG(pVM, &pPGM->StatTrackAliased, STAMTYPE_COUNTER, "/PGM/Track/Aliased", STAMUNIT_OCCURENCES, "The number of times switching to cRef2, i.e. the page is being shadowed by two PTs.");
1579	STAM_REG(pVM, &pPGM->StatTrackAliasedMany, STAMTYPE_COUNTER, "/PGM/Track/AliasedMany", STAMUNIT_OCCURENCES, "The number of times we're tracking using cRef2.");
1580	STAM_REG(pVM, &pPGM->StatTrackAliasedLots, STAMTYPE_COUNTER, "/PGM/Track/AliasedLots", STAMUNIT_OCCURENCES, "The number of times we're hitting pages which has overflowed cRef2");
1581	STAM_REG(pVM, &pPGM->StatTrackOverflows, STAMTYPE_COUNTER, "/PGM/Track/Overflows", STAMUNIT_OCCURENCES, "The number of times the extent list grows to long.");
1582	STAM_REG(pVM, &pPGM->StatTrackDeref, STAMTYPE_PROFILE, "/PGM/Track/Deref", STAMUNIT_OCCURENCES, "Profiling of SyncPageWorkerTrackDeref (expensive).");
1583	#endif
1584	for (i = 0; i < RT_ELEMENTS(pPGM->StatSyncPtPD); i++)
1585	STAMR3RegisterF(pVM, &pPGM->StatSyncPtPD[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
1586	"The number of SyncPT per PD n.", "/PGM/PDSyncPT/%04X", i);
1587	for (i = 0; i < RT_ELEMENTS(pPGM->StatSyncPagePD); i++)
1588	STAMR3RegisterF(pVM, &pPGM->StatSyncPagePD[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
1589	"The number of SyncPage per PD n.", "/PGM/PDSyncPage/%04X", i);
1590
1591	/* R3 only: */
1592	STAM_REG(pVM, &pPGM->StatR3DetectedConflicts, STAMTYPE_COUNTER, "/PGM/R3/DetectedConflicts", STAMUNIT_OCCURENCES, "The number of times PGMR3CheckMappingConflicts() detected a conflict.");
1593	STAM_REG(pVM, &pPGM->StatR3ResolveConflict, STAMTYPE_PROFILE, "/PGM/R3/ResolveConflict", STAMUNIT_TICKS_PER_CALL, "pgmR3SyncPTResolveConflict() profiling (includes the entire relocation).");
1594	STAM_REG(pVM, &pPGM->StatR3GuestPDWrite, STAMTYPE_COUNTER, "/PGM/R3/PDWrite", STAMUNIT_OCCURENCES, "The total number of times pgmHCGuestPDWriteHandler() was called.");
1595	STAM_REG(pVM, &pPGM->StatR3GuestPDWriteConflict, STAMTYPE_COUNTER, "/PGM/R3/PDWriteConflict", STAMUNIT_OCCURENCES, "The number of times pgmHCGuestPDWriteHandler() detected a conflict.");
1596	STAM_REG(pVM, &pPGM->StatR3DynRamTotal, STAMTYPE_COUNTER, "/PGM/DynAlloc/TotalAlloc", STAMUNIT_MEGABYTES, "Allocated MBs of guest ram.");
1597	STAM_REG(pVM, &pPGM->StatR3DynRamGrow, STAMTYPE_COUNTER, "/PGM/DynAlloc/Grow", STAMUNIT_OCCURENCES, "Nr of pgmr3PhysGrowRange calls.");
1598
1599	/* R0 only: */
1600	STAM_REG(pVM, &pPGM->StatR0DynMapMigrateInvlPg, STAMTYPE_COUNTER, "/PGM/R0/DynMapMigrateInvlPg", STAMUNIT_OCCURENCES, "invlpg count in PGMDynMapMigrateAutoSet.");
1601	STAM_REG(pVM, &pPGM->StatR0DynMapGCPageInl, STAMTYPE_PROFILE, "/PGM/R0/DynMapPageGCPageInl", STAMUNIT_TICKS_PER_CALL, "Calls to pgmR0DynMapGCPageInlined.");
1602	STAM_REG(pVM, &pPGM->StatR0DynMapGCPageInlHits, STAMTYPE_COUNTER, "/PGM/R0/DynMapPageGCPageInl/Hits", STAMUNIT_OCCURENCES, "Hash table lookup hits.");
1603	STAM_REG(pVM, &pPGM->StatR0DynMapGCPageInlMisses, STAMTYPE_COUNTER, "/PGM/R0/DynMapPageGCPageInl/Misses", STAMUNIT_OCCURENCES, "Misses that falls back to code common with PGMDynMapHCPage.");
1604	STAM_REG(pVM, &pPGM->StatR0DynMapGCPageInlRamHits, STAMTYPE_COUNTER, "/PGM/R0/DynMapPageGCPageInl/RamHits", STAMUNIT_OCCURENCES, "1st ram range hits.");
1605	STAM_REG(pVM, &pPGM->StatR0DynMapGCPageInlRamMisses, STAMTYPE_COUNTER, "/PGM/R0/DynMapPageGCPageInl/RamMisses", STAMUNIT_OCCURENCES, "1st ram range misses, takes slow path.");
1606	STAM_REG(pVM, &pPGM->StatR0DynMapHCPageInl, STAMTYPE_PROFILE, "/PGM/R0/DynMapPageHCPageInl", STAMUNIT_TICKS_PER_CALL, "Calls to pgmR0DynMapHCPageInlined.");
1607	STAM_REG(pVM, &pPGM->StatR0DynMapHCPageInlHits, STAMTYPE_COUNTER, "/PGM/R0/DynMapPageHCPageInl/Hits", STAMUNIT_OCCURENCES, "Hash table lookup hits.");
1608	STAM_REG(pVM, &pPGM->StatR0DynMapHCPageInlMisses, STAMTYPE_COUNTER, "/PGM/R0/DynMapPageHCPageInl/Misses", STAMUNIT_OCCURENCES, "Misses that falls back to code common with PGMDynMapHCPage.");
1609	STAM_REG(pVM, &pPGM->StatR0DynMapPage, STAMTYPE_COUNTER, "/PGM/R0/DynMapPage", STAMUNIT_OCCURENCES, "Calls to pgmR0DynMapPage");
1610	STAM_REG(pVM, &pPGM->StatR0DynMapSetOptimize, STAMTYPE_COUNTER, "/PGM/R0/DynMapPage/SetOptimize", STAMUNIT_OCCURENCES, "Calls to pgmDynMapOptimizeAutoSet.");
1611	STAM_REG(pVM, &pPGM->StatR0DynMapSetSearchFlushes, STAMTYPE_COUNTER, "/PGM/R0/DynMapPage/SetSearchFlushes",STAMUNIT_OCCURENCES, "Set search restorting to subset flushes.");
1612	STAM_REG(pVM, &pPGM->StatR0DynMapSetSearchHits, STAMTYPE_COUNTER, "/PGM/R0/DynMapPage/SetSearchHits", STAMUNIT_OCCURENCES, "Set search hits.");
1613	STAM_REG(pVM, &pPGM->StatR0DynMapSetSearchMisses, STAMTYPE_COUNTER, "/PGM/R0/DynMapPage/SetSearchMisses", STAMUNIT_OCCURENCES, "Set search misses.");
1614	STAM_REG(pVM, &pPGM->StatR0DynMapHCPage, STAMTYPE_PROFILE, "/PGM/R0/DynMapPage/HCPage", STAMUNIT_TICKS_PER_CALL, "Calls to PGMDynMapHCPage (ring-0).");
1615	STAM_REG(pVM, &pPGM->StatR0DynMapPageHits0, STAMTYPE_COUNTER, "/PGM/R0/DynMapPage/Hits0", STAMUNIT_OCCURENCES, "Hits at iPage+0");
1616	STAM_REG(pVM, &pPGM->StatR0DynMapPageHits1, STAMTYPE_COUNTER, "/PGM/R0/DynMapPage/Hits1", STAMUNIT_OCCURENCES, "Hits at iPage+1");
1617	STAM_REG(pVM, &pPGM->StatR0DynMapPageHits2, STAMTYPE_COUNTER, "/PGM/R0/DynMapPage/Hits2", STAMUNIT_OCCURENCES, "Hits at iPage+2");
1618	STAM_REG(pVM, &pPGM->StatR0DynMapPageInvlPg, STAMTYPE_COUNTER, "/PGM/R0/DynMapPage/InvlPg", STAMUNIT_OCCURENCES, "invlpg count in pgmR0DynMapPageSlow.");
1619	STAM_REG(pVM, &pPGM->StatR0DynMapPageSlow, STAMTYPE_COUNTER, "/PGM/R0/DynMapPage/Slow", STAMUNIT_OCCURENCES, "Calls to pgmR0DynMapPageSlow - subtract this from pgmR0DynMapPage to get 1st level hits.");
1620	STAM_REG(pVM, &pPGM->StatR0DynMapPageSlowLoopHits, STAMTYPE_COUNTER, "/PGM/R0/DynMapPage/SlowLoopHits" , STAMUNIT_OCCURENCES, "Hits in the loop path.");
1621	STAM_REG(pVM, &pPGM->StatR0DynMapPageSlowLoopMisses, STAMTYPE_COUNTER, "/PGM/R0/DynMapPage/SlowLoopMisses", STAMUNIT_OCCURENCES, "Misses in the loop path. NonLoopMisses = Slow - SlowLoopHit - SlowLoopMisses");
1622	//STAM_REG(pVM, &pPGM->StatR0DynMapPageSlowLostHits, STAMTYPE_COUNTER, "/PGM/R0/DynMapPage/SlowLostHits", STAMUNIT_OCCURENCES, "Lost hits.");
1623	STAM_REG(pVM, &pPGM->StatR0DynMapSubsets, STAMTYPE_COUNTER, "/PGM/R0/Subsets", STAMUNIT_OCCURENCES, "Times PGMDynMapPushAutoSubset was called.");
1624	STAM_REG(pVM, &pPGM->StatR0DynMapPopFlushes, STAMTYPE_COUNTER, "/PGM/R0/SubsetPopFlushes", STAMUNIT_OCCURENCES, "Times PGMDynMapPopAutoSubset flushes the subset.");
1625
1626	/* GC only: */
1627	STAM_REG(pVM, &pPGM->StatRCDynMapCacheHits, STAMTYPE_COUNTER, "/PGM/RC/DynMapCache/Hits" , STAMUNIT_OCCURENCES, "Number of dynamic page mapping cache hits.");
1628	STAM_REG(pVM, &pPGM->StatRCDynMapCacheMisses, STAMTYPE_COUNTER, "/PGM/RC/DynMapCache/Misses" , STAMUNIT_OCCURENCES, "Number of dynamic page mapping cache misses.");
1629	STAM_REG(pVM, &pPGM->StatRCInvlPgConflict, STAMTYPE_COUNTER, "/PGM/RC/InvlPgConflict", STAMUNIT_OCCURENCES, "Number of times PGMInvalidatePage() detected a mapping conflict.");
1630	STAM_REG(pVM, &pPGM->StatRCInvlPgSyncMonCR3, STAMTYPE_COUNTER, "/PGM/RC/InvlPgSyncMonitorCR3", STAMUNIT_OCCURENCES, "Number of times PGMInvalidatePage() ran into PGM_SYNC_MONITOR_CR3.");
1631
1632	/* RZ only: */
1633	STAM_REG(pVM, &pPGM->StatRZTrap0e, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMTrap0eHandler() body.");
1634	STAM_REG(pVM, &pPGM->StatRZTrap0eTimeCheckPageFault, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time/CheckPageFault", STAMUNIT_TICKS_PER_CALL, "Profiling of checking for dirty/access emulation faults.");
1635	STAM_REG(pVM, &pPGM->StatRZTrap0eTimeSyncPT, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time/SyncPT", STAMUNIT_TICKS_PER_CALL, "Profiling of lazy page table syncing.");
1636	STAM_REG(pVM, &pPGM->StatRZTrap0eTimeMapping, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time/Mapping", STAMUNIT_TICKS_PER_CALL, "Profiling of checking virtual mappings.");
1637	STAM_REG(pVM, &pPGM->StatRZTrap0eTimeOutOfSync, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time/OutOfSync", STAMUNIT_TICKS_PER_CALL, "Profiling of out of sync page handling.");
1638	STAM_REG(pVM, &pPGM->StatRZTrap0eTimeHandlers, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time/Handlers", STAMUNIT_TICKS_PER_CALL, "Profiling of checking handlers.");
1639	STAM_REG(pVM, &pPGM->StatRZTrap0eTime2CSAM, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time2/CSAM", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is CSAM.");
1640	STAM_REG(pVM, &pPGM->StatRZTrap0eTime2DirtyAndAccessed, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time2/DirtyAndAccessedBits", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is dirty and/or accessed bit emulation.");
1641	STAM_REG(pVM, &pPGM->StatRZTrap0eTime2GuestTrap, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time2/GuestTrap", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is a guest trap.");
1642	STAM_REG(pVM, &pPGM->StatRZTrap0eTime2HndPhys, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time2/HandlerPhysical", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is a physical handler.");
1643	STAM_REG(pVM, &pPGM->StatRZTrap0eTime2HndVirt, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time2/HandlerVirtual", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is a virtual handler.");
1644	STAM_REG(pVM, &pPGM->StatRZTrap0eTime2HndUnhandled, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time2/HandlerUnhandled", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is access outside the monitored areas of a monitored page.");
1645	STAM_REG(pVM, &pPGM->StatRZTrap0eTime2Misc, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time2/Misc", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is not known.");
1646	STAM_REG(pVM, &pPGM->StatRZTrap0eTime2OutOfSync, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time2/OutOfSync", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is an out-of-sync page.");
1647	STAM_REG(pVM, &pPGM->StatRZTrap0eTime2OutOfSyncHndPhys, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time2/OutOfSyncHndPhys", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is an out-of-sync physical handler page.");
1648	STAM_REG(pVM, &pPGM->StatRZTrap0eTime2OutOfSyncHndVirt, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time2/OutOfSyncHndVirt", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is an out-of-sync virtual handler page.");
1649	STAM_REG(pVM, &pPGM->StatRZTrap0eTime2OutOfSyncHndObs, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time2/OutOfSyncObsHnd", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is an obsolete handler page.");
1650	STAM_REG(pVM, &pPGM->StatRZTrap0eTime2SyncPT, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time2/SyncPT", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is lazy syncing of a PT.");
1651	STAM_REG(pVM, &pPGM->StatRZTrap0eConflicts, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Conflicts", STAMUNIT_OCCURENCES, "The number of times #PF was caused by an undetected conflict.");
1652	STAM_REG(pVM, &pPGM->StatRZTrap0eHandlersMapping, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Handlers/Mapping", STAMUNIT_OCCURENCES, "Number of traps due to access handlers in mappings.");
1653	STAM_REG(pVM, &pPGM->StatRZTrap0eHandlersOutOfSync, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Handlers/OutOfSync", STAMUNIT_OCCURENCES, "Number of traps due to out-of-sync handled pages.");
1654	STAM_REG(pVM, &pPGM->StatRZTrap0eHandlersPhysical, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Handlers/Physical", STAMUNIT_OCCURENCES, "Number of traps due to physical access handlers.");
1655	STAM_REG(pVM, &pPGM->StatRZTrap0eHandlersVirtual, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Handlers/Virtual", STAMUNIT_OCCURENCES, "Number of traps due to virtual access handlers.");
1656	STAM_REG(pVM, &pPGM->StatRZTrap0eHandlersVirtualByPhys, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Handlers/VirtualByPhys", STAMUNIT_OCCURENCES, "Number of traps due to virtual access handlers by physical address.");
1657	STAM_REG(pVM, &pPGM->StatRZTrap0eHandlersVirtualUnmarked,STAMTYPE_COUNTER,"/PGM/RZ/Trap0e/Handlers/VirtualUnmarked",STAMUNIT_OCCURENCES, "Number of traps due to virtual access handlers by virtual address (without proper physical flags).");
1658	STAM_REG(pVM, &pPGM->StatRZTrap0eHandlersUnhandled, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Handlers/Unhandled", STAMUNIT_OCCURENCES, "Number of traps due to access outside range of monitored page(s).");
1659	STAM_REG(pVM, &pPGM->StatRZTrap0eHandlersInvalid, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Handlers/Invalid", STAMUNIT_OCCURENCES, "Number of traps due to access to invalid physical memory.");
1660	STAM_REG(pVM, &pPGM->StatRZTrap0eUSNotPresentRead, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Err/User/NPRead", STAMUNIT_OCCURENCES, "Number of user mode not present read page faults.");
1661	STAM_REG(pVM, &pPGM->StatRZTrap0eUSNotPresentWrite, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Err/User/NPWrite", STAMUNIT_OCCURENCES, "Number of user mode not present write page faults.");
1662	STAM_REG(pVM, &pPGM->StatRZTrap0eUSWrite, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Err/User/Write", STAMUNIT_OCCURENCES, "Number of user mode write page faults.");
1663	STAM_REG(pVM, &pPGM->StatRZTrap0eUSReserved, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Err/User/Reserved", STAMUNIT_OCCURENCES, "Number of user mode reserved bit page faults.");
1664	STAM_REG(pVM, &pPGM->StatRZTrap0eUSNXE, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Err/User/NXE", STAMUNIT_OCCURENCES, "Number of user mode NXE page faults.");
1665	STAM_REG(pVM, &pPGM->StatRZTrap0eUSRead, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Err/User/Read", STAMUNIT_OCCURENCES, "Number of user mode read page faults.");
1666	STAM_REG(pVM, &pPGM->StatRZTrap0eSVNotPresentRead, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Err/Supervisor/NPRead", STAMUNIT_OCCURENCES, "Number of supervisor mode not present read page faults.");
1667	STAM_REG(pVM, &pPGM->StatRZTrap0eSVNotPresentWrite, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Err/Supervisor/NPWrite", STAMUNIT_OCCURENCES, "Number of supervisor mode not present write page faults.");
1668	STAM_REG(pVM, &pPGM->StatRZTrap0eSVWrite, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Err/Supervisor/Write", STAMUNIT_OCCURENCES, "Number of supervisor mode write page faults.");
1669	STAM_REG(pVM, &pPGM->StatRZTrap0eSVReserved, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Err/Supervisor/Reserved", STAMUNIT_OCCURENCES, "Number of supervisor mode reserved bit page faults.");
1670	STAM_REG(pVM, &pPGM->StatRZTrap0eSNXE, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Err/Supervisor/NXE", STAMUNIT_OCCURENCES, "Number of supervisor mode NXE page faults.");
1671	STAM_REG(pVM, &pPGM->StatRZTrap0eGuestPF, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/GuestPF", STAMUNIT_OCCURENCES, "Number of real guest page faults.");
1672	STAM_REG(pVM, &pPGM->StatRZTrap0eGuestPFUnh, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/GuestPF/Unhandled", STAMUNIT_OCCURENCES, "Number of real guest page faults from the 'unhandled' case.");
1673	STAM_REG(pVM, &pPGM->StatRZTrap0eGuestPFMapping, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/GuestPF/InMapping", STAMUNIT_OCCURENCES, "Number of real guest page faults in a mapping.");
1674	STAM_REG(pVM, &pPGM->StatRZTrap0eWPEmulInRZ, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/WP/InRZ", STAMUNIT_OCCURENCES, "Number of guest page faults due to X86_CR0_WP emulation.");
1675	STAM_REG(pVM, &pPGM->StatRZTrap0eWPEmulToR3, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/WP/ToR3", STAMUNIT_OCCURENCES, "Number of guest page faults due to X86_CR0_WP emulation (forward to R3 for emulation).");
1676	for (i = 0; i < RT_ELEMENTS(pPGM->StatRZTrap0ePD); i++)
1677	STAMR3RegisterF(pVM, &pPGM->StatRZTrap0ePD[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
1678	"The number of traps in page directory n.", "/PGM/RZ/Trap0e/PD/%04X", i);
1679	STAM_REG(pVM, &pPGM->StatRZGuestCR3WriteHandled, STAMTYPE_COUNTER, "/PGM/RZ/CR3WriteHandled", STAMUNIT_OCCURENCES, "The number of times the Guest CR3 change was successfully handled.");
1680	STAM_REG(pVM, &pPGM->StatRZGuestCR3WriteUnhandled, STAMTYPE_COUNTER, "/PGM/RZ/CR3WriteUnhandled", STAMUNIT_OCCURENCES, "The number of times the Guest CR3 change was passed back to the recompiler.");
1681	STAM_REG(pVM, &pPGM->StatRZGuestCR3WriteConflict, STAMTYPE_COUNTER, "/PGM/RZ/CR3WriteConflict", STAMUNIT_OCCURENCES, "The number of times the Guest CR3 monitoring detected a conflict.");
1682	STAM_REG(pVM, &pPGM->StatRZGuestROMWriteHandled, STAMTYPE_COUNTER, "/PGM/RZ/ROMWriteHandled", STAMUNIT_OCCURENCES, "The number of times the Guest ROM change was successfully handled.");
1683	STAM_REG(pVM, &pPGM->StatRZGuestROMWriteUnhandled, STAMTYPE_COUNTER, "/PGM/RZ/ROMWriteUnhandled", STAMUNIT_OCCURENCES, "The number of times the Guest ROM change was passed back to the recompiler.");
1684
1685	/* HC only: */
1686
1687	/* RZ & R3: */
1688	STAM_REG(pVM, &pPGM->StatRZSyncCR3, STAMTYPE_PROFILE, "/PGM/RZ/SyncCR3", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMSyncCR3() body.");
1689	STAM_REG(pVM, &pPGM->StatRZSyncCR3Handlers, STAMTYPE_PROFILE, "/PGM/RZ/SyncCR3/Handlers", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMSyncCR3() update handler section.");
1690	STAM_REG(pVM, &pPGM->StatRZSyncCR3HandlerVirtualUpdate, STAMTYPE_PROFILE, "/PGM/RZ/SyncCR3/Handlers/VirtualUpdate", STAMUNIT_TICKS_PER_CALL, "Profiling of the virtual handler updates.");
1691	STAM_REG(pVM, &pPGM->StatRZSyncCR3HandlerVirtualReset, STAMTYPE_PROFILE, "/PGM/RZ/SyncCR3/Handlers/VirtualReset", STAMUNIT_TICKS_PER_CALL, "Profiling of the virtual handler resets.");
1692	STAM_REG(pVM, &pPGM->StatRZSyncCR3Global, STAMTYPE_COUNTER, "/PGM/RZ/SyncCR3/Global", STAMUNIT_OCCURENCES, "The number of global CR3 syncs.");
1693	STAM_REG(pVM, &pPGM->StatRZSyncCR3NotGlobal, STAMTYPE_COUNTER, "/PGM/RZ/SyncCR3/NotGlobal", STAMUNIT_OCCURENCES, "The number of non-global CR3 syncs.");
1694	STAM_REG(pVM, &pPGM->StatRZSyncCR3DstCacheHit, STAMTYPE_COUNTER, "/PGM/RZ/SyncCR3/DstChacheHit", STAMUNIT_OCCURENCES, "The number of times we got some kind of a cache hit.");
1695	STAM_REG(pVM, &pPGM->StatRZSyncCR3DstFreed, STAMTYPE_COUNTER, "/PGM/RZ/SyncCR3/DstFreed", STAMUNIT_OCCURENCES, "The number of times we've had to free a shadow entry.");
1696	STAM_REG(pVM, &pPGM->StatRZSyncCR3DstFreedSrcNP, STAMTYPE_COUNTER, "/PGM/RZ/SyncCR3/DstFreedSrcNP", STAMUNIT_OCCURENCES, "The number of times we've had to free a shadow entry for which the source entry was not present.");
1697	STAM_REG(pVM, &pPGM->StatRZSyncCR3DstNotPresent, STAMTYPE_COUNTER, "/PGM/RZ/SyncCR3/DstNotPresent", STAMUNIT_OCCURENCES, "The number of times we've encountered a not present shadow entry for a present guest entry.");
1698	STAM_REG(pVM, &pPGM->StatRZSyncCR3DstSkippedGlobalPD, STAMTYPE_COUNTER, "/PGM/RZ/SyncCR3/DstSkippedGlobalPD", STAMUNIT_OCCURENCES, "The number of times a global page directory wasn't flushed.");
1699	STAM_REG(pVM, &pPGM->StatRZSyncCR3DstSkippedGlobalPT, STAMTYPE_COUNTER, "/PGM/RZ/SyncCR3/DstSkippedGlobalPT", STAMUNIT_OCCURENCES, "The number of times a page table with only global entries wasn't flushed.");
1700	STAM_REG(pVM, &pPGM->StatRZSyncPT, STAMTYPE_PROFILE, "/PGM/RZ/SyncPT", STAMUNIT_TICKS_PER_CALL, "Profiling of the pfnSyncPT() body.");
1701	STAM_REG(pVM, &pPGM->StatRZSyncPTFailed, STAMTYPE_COUNTER, "/PGM/RZ/SyncPT/Failed", STAMUNIT_OCCURENCES, "The number of times pfnSyncPT() failed.");
1702	STAM_REG(pVM, &pPGM->StatRZSyncPT4K, STAMTYPE_COUNTER, "/PGM/RZ/SyncPT/4K", STAMUNIT_OCCURENCES, "Nr of 4K PT syncs");
1703	STAM_REG(pVM, &pPGM->StatRZSyncPT4M, STAMTYPE_COUNTER, "/PGM/RZ/SyncPT/4M", STAMUNIT_OCCURENCES, "Nr of 4M PT syncs");
1704	STAM_REG(pVM, &pPGM->StatRZSyncPagePDNAs, STAMTYPE_COUNTER, "/PGM/RZ/SyncPagePDNAs", STAMUNIT_OCCURENCES, "The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit.");
1705	STAM_REG(pVM, &pPGM->StatRZSyncPagePDOutOfSync, STAMTYPE_COUNTER, "/PGM/RZ/SyncPagePDOutOfSync", STAMUNIT_OCCURENCES, "The number of time we've encountered an out-of-sync PD in SyncPage.");
1706	STAM_REG(pVM, &pPGM->StatRZAccessedPage, STAMTYPE_COUNTER, "/PGM/RZ/AccessedPage", STAMUNIT_OCCURENCES, "The number of pages marked not present for accessed bit emulation.");
1707	STAM_REG(pVM, &pPGM->StatRZDirtyBitTracking, STAMTYPE_PROFILE, "/PGM/RZ/DirtyPage", STAMUNIT_TICKS_PER_CALL, "Profiling the dirty bit tracking in CheckPageFault().");
1708	STAM_REG(pVM, &pPGM->StatRZDirtyPage, STAMTYPE_COUNTER, "/PGM/RZ/DirtyPage/Mark", STAMUNIT_OCCURENCES, "The number of pages marked read-only for dirty bit tracking.");
1709	STAM_REG(pVM, &pPGM->StatRZDirtyPageBig, STAMTYPE_COUNTER, "/PGM/RZ/DirtyPage/MarkBig", STAMUNIT_OCCURENCES, "The number of 4MB pages marked read-only for dirty bit tracking.");
1710	STAM_REG(pVM, &pPGM->StatRZDirtyPageSkipped, STAMTYPE_COUNTER, "/PGM/RZ/DirtyPage/Skipped", STAMUNIT_OCCURENCES, "The number of pages already dirty or readonly.");
1711	STAM_REG(pVM, &pPGM->StatRZDirtyPageTrap, STAMTYPE_COUNTER, "/PGM/RZ/DirtyPage/Trap", STAMUNIT_OCCURENCES, "The number of traps generated for dirty bit tracking.");
1712	STAM_REG(pVM, &pPGM->StatRZDirtiedPage, STAMTYPE_COUNTER, "/PGM/RZ/DirtyPage/SetDirty", STAMUNIT_OCCURENCES, "The number of pages marked dirty because of write accesses.");
1713	STAM_REG(pVM, &pPGM->StatRZDirtyTrackRealPF, STAMTYPE_COUNTER, "/PGM/RZ/DirtyPage/RealPF", STAMUNIT_OCCURENCES, "The number of real pages faults during dirty bit tracking.");
1714	STAM_REG(pVM, &pPGM->StatRZPageAlreadyDirty, STAMTYPE_COUNTER, "/PGM/RZ/DirtyPage/AlreadySet", STAMUNIT_OCCURENCES, "The number of pages already marked dirty because of write accesses.");
1715	STAM_REG(pVM, &pPGM->StatRZInvalidatePage, STAMTYPE_PROFILE, "/PGM/RZ/InvalidatePage", STAMUNIT_TICKS_PER_CALL, "PGMInvalidatePage() profiling.");
1716	STAM_REG(pVM, &pPGM->StatRZInvalidatePage4KBPages, STAMTYPE_COUNTER, "/PGM/RZ/InvalidatePage/4KBPages", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was called for a 4KB page.");
1717	STAM_REG(pVM, &pPGM->StatRZInvalidatePage4MBPages, STAMTYPE_COUNTER, "/PGM/RZ/InvalidatePage/4MBPages", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was called for a 4MB page.");
1718	STAM_REG(pVM, &pPGM->StatRZInvalidatePage4MBPagesSkip, STAMTYPE_COUNTER, "/PGM/RZ/InvalidatePage/4MBPagesSkip",STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() skipped a 4MB page.");
1719	STAM_REG(pVM, &pPGM->StatRZInvalidatePagePDMappings, STAMTYPE_COUNTER, "/PGM/RZ/InvalidatePage/PDMappings", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict).");
1720	STAM_REG(pVM, &pPGM->StatRZInvalidatePagePDNAs, STAMTYPE_COUNTER, "/PGM/RZ/InvalidatePage/PDNAs", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was called for a not accessed page directory.");
1721	STAM_REG(pVM, &pPGM->StatRZInvalidatePagePDNPs, STAMTYPE_COUNTER, "/PGM/RZ/InvalidatePage/PDNPs", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was called for a not present page directory.");
1722	STAM_REG(pVM, &pPGM->StatRZInvalidatePagePDOutOfSync, STAMTYPE_COUNTER, "/PGM/RZ/InvalidatePage/PDOutOfSync", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was called for an out of sync page directory.");
1723	STAM_REG(pVM, &pPGM->StatRZInvalidatePageSkipped, STAMTYPE_COUNTER, "/PGM/RZ/InvalidatePage/Skipped", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3.");
1724	STAM_REG(pVM, &pPGM->StatRZVirtHandlerSearchByPhys, STAMTYPE_PROFILE, "/PGM/RZ/VirtHandlerSearchByPhys", STAMUNIT_TICKS_PER_CALL, "Profiling of pgmHandlerVirtualFindByPhysAddr.");
1725	STAM_REG(pVM, &pPGM->StatRZPhysHandlerReset, STAMTYPE_COUNTER, "/PGM/RZ/PhysHandlerReset", STAMUNIT_OCCURENCES, "The number of times PGMHandlerPhysicalReset is called.");
1726	STAM_REG(pVM, &pPGM->StatRZPageOutOfSyncSupervisor, STAMTYPE_COUNTER, "/PGM/RZ/OutOfSync/SuperVisor", STAMUNIT_OCCURENCES, "Number of traps due to pages out of sync and times VerifyAccessSyncPage calls SyncPage.");
1727	STAM_REG(pVM, &pPGM->StatRZPageOutOfSyncUser, STAMTYPE_COUNTER, "/PGM/RZ/OutOfSync/User", STAMUNIT_OCCURENCES, "Number of traps due to pages out of sync and times VerifyAccessSyncPage calls SyncPage.");
1728	STAM_REG(pVM, &pPGM->StatRZPrefetch, STAMTYPE_PROFILE, "/PGM/RZ/Prefetch", STAMUNIT_TICKS_PER_CALL, "PGMPrefetchPage profiling.");
1729	STAM_REG(pVM, &pPGM->StatRZChunkR3MapTlbHits, STAMTYPE_COUNTER, "/PGM/ChunkR3Map/TlbHitsRZ", STAMUNIT_OCCURENCES, "TLB hits.");
1730	STAM_REG(pVM, &pPGM->StatRZChunkR3MapTlbMisses, STAMTYPE_COUNTER, "/PGM/ChunkR3Map/TlbMissesRZ", STAMUNIT_OCCURENCES, "TLB misses.");
1731	STAM_REG(pVM, &pPGM->StatRZPageMapTlbHits, STAMTYPE_COUNTER, "/PGM/RZ/Page/MapTlbHits", STAMUNIT_OCCURENCES, "TLB hits.");
1732	STAM_REG(pVM, &pPGM->StatRZPageMapTlbMisses, STAMTYPE_COUNTER, "/PGM/RZ/Page/MapTlbMisses", STAMUNIT_OCCURENCES, "TLB misses.");
1733	STAM_REG(pVM, &pPGM->StatRZPageReplaceShared, STAMTYPE_COUNTER, "/PGM/RZ/Page/ReplacedShared", STAMUNIT_OCCURENCES, "Times a shared page was replaced.");
1734	STAM_REG(pVM, &pPGM->StatRZPageReplaceZero, STAMTYPE_COUNTER, "/PGM/RZ/Page/ReplacedZero", STAMUNIT_OCCURENCES, "Times the zero page was replaced.");
1735	/// @todo STAM_REG(pVM, &pPGM->StatRZPageHandyAllocs, STAMTYPE_COUNTER, "/PGM/RZ/Page/HandyAllocs", STAMUNIT_OCCURENCES, "Number of times we've allocated more handy pages.");
1736	STAM_REG(pVM, &pPGM->StatRZFlushTLB, STAMTYPE_PROFILE, "/PGM/RZ/FlushTLB", STAMUNIT_OCCURENCES, "Profiling of the PGMFlushTLB() body.");
1737	STAM_REG(pVM, &pPGM->StatRZFlushTLBNewCR3, STAMTYPE_COUNTER, "/PGM/RZ/FlushTLB/NewCR3", STAMUNIT_OCCURENCES, "The number of times PGMFlushTLB was called with a new CR3, non-global. (switch)");
1738	STAM_REG(pVM, &pPGM->StatRZFlushTLBNewCR3Global, STAMTYPE_COUNTER, "/PGM/RZ/FlushTLB/NewCR3Global", STAMUNIT_OCCURENCES, "The number of times PGMFlushTLB was called with a new CR3, global. (switch)");
1739	STAM_REG(pVM, &pPGM->StatRZFlushTLBSameCR3, STAMTYPE_COUNTER, "/PGM/RZ/FlushTLB/SameCR3", STAMUNIT_OCCURENCES, "The number of times PGMFlushTLB was called with the same CR3, non-global. (flush)");
1740	STAM_REG(pVM, &pPGM->StatRZFlushTLBSameCR3Global, STAMTYPE_COUNTER, "/PGM/RZ/FlushTLB/SameCR3Global", STAMUNIT_OCCURENCES, "The number of times PGMFlushTLB was called with the same CR3, global. (flush)");
1741	STAM_REG(pVM, &pPGM->StatRZGstModifyPage, STAMTYPE_PROFILE, "/PGM/RZ/GstModifyPage", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMGstModifyPage() body.");
1742
1743	STAM_REG(pVM, &pPGM->StatR3SyncCR3, STAMTYPE_PROFILE, "/PGM/R3/SyncCR3", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMSyncCR3() body.");
1744	STAM_REG(pVM, &pPGM->StatR3SyncCR3Handlers, STAMTYPE_PROFILE, "/PGM/R3/SyncCR3/Handlers", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMSyncCR3() update handler section.");
1745	STAM_REG(pVM, &pPGM->StatR3SyncCR3HandlerVirtualUpdate, STAMTYPE_PROFILE, "/PGM/R3/SyncCR3/Handlers/VirtualUpdate", STAMUNIT_TICKS_PER_CALL, "Profiling of the virtual handler updates.");
1746	STAM_REG(pVM, &pPGM->StatR3SyncCR3HandlerVirtualReset, STAMTYPE_PROFILE, "/PGM/R3/SyncCR3/Handlers/VirtualReset", STAMUNIT_TICKS_PER_CALL, "Profiling of the virtual handler resets.");
1747	STAM_REG(pVM, &pPGM->StatR3SyncCR3Global, STAMTYPE_COUNTER, "/PGM/R3/SyncCR3/Global", STAMUNIT_OCCURENCES, "The number of global CR3 syncs.");
1748	STAM_REG(pVM, &pPGM->StatR3SyncCR3NotGlobal, STAMTYPE_COUNTER, "/PGM/R3/SyncCR3/NotGlobal", STAMUNIT_OCCURENCES, "The number of non-global CR3 syncs.");
1749	STAM_REG(pVM, &pPGM->StatR3SyncCR3DstCacheHit, STAMTYPE_COUNTER, "/PGM/R3/SyncCR3/DstChacheHit", STAMUNIT_OCCURENCES, "The number of times we got some kind of a cache hit.");
1750	STAM_REG(pVM, &pPGM->StatR3SyncCR3DstFreed, STAMTYPE_COUNTER, "/PGM/R3/SyncCR3/DstFreed", STAMUNIT_OCCURENCES, "The number of times we've had to free a shadow entry.");
1751	STAM_REG(pVM, &pPGM->StatR3SyncCR3DstFreedSrcNP, STAMTYPE_COUNTER, "/PGM/R3/SyncCR3/DstFreedSrcNP", STAMUNIT_OCCURENCES, "The number of times we've had to free a shadow entry for which the source entry was not present.");
1752	STAM_REG(pVM, &pPGM->StatR3SyncCR3DstNotPresent, STAMTYPE_COUNTER, "/PGM/R3/SyncCR3/DstNotPresent", STAMUNIT_OCCURENCES, "The number of times we've encountered a not present shadow entry for a present guest entry.");
1753	STAM_REG(pVM, &pPGM->StatR3SyncCR3DstSkippedGlobalPD, STAMTYPE_COUNTER, "/PGM/R3/SyncCR3/DstSkippedGlobalPD", STAMUNIT_OCCURENCES, "The number of times a global page directory wasn't flushed.");
1754	STAM_REG(pVM, &pPGM->StatR3SyncCR3DstSkippedGlobalPT, STAMTYPE_COUNTER, "/PGM/R3/SyncCR3/DstSkippedGlobalPT", STAMUNIT_OCCURENCES, "The number of times a page table with only global entries wasn't flushed.");
1755	STAM_REG(pVM, &pPGM->StatR3SyncPT, STAMTYPE_PROFILE, "/PGM/R3/SyncPT", STAMUNIT_TICKS_PER_CALL, "Profiling of the pfnSyncPT() body.");
1756	STAM_REG(pVM, &pPGM->StatR3SyncPTFailed, STAMTYPE_COUNTER, "/PGM/R3/SyncPT/Failed", STAMUNIT_OCCURENCES, "The number of times pfnSyncPT() failed.");
1757	STAM_REG(pVM, &pPGM->StatR3SyncPT4K, STAMTYPE_COUNTER, "/PGM/R3/SyncPT/4K", STAMUNIT_OCCURENCES, "Nr of 4K PT syncs");
1758	STAM_REG(pVM, &pPGM->StatR3SyncPT4M, STAMTYPE_COUNTER, "/PGM/R3/SyncPT/4M", STAMUNIT_OCCURENCES, "Nr of 4M PT syncs");
1759	STAM_REG(pVM, &pPGM->StatR3SyncPagePDNAs, STAMTYPE_COUNTER, "/PGM/R3/SyncPagePDNAs", STAMUNIT_OCCURENCES, "The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit.");
1760	STAM_REG(pVM, &pPGM->StatR3SyncPagePDOutOfSync, STAMTYPE_COUNTER, "/PGM/R3/SyncPagePDOutOfSync", STAMUNIT_OCCURENCES, "The number of time we've encountered an out-of-sync PD in SyncPage.");
1761	STAM_REG(pVM, &pPGM->StatR3AccessedPage, STAMTYPE_COUNTER, "/PGM/R3/AccessedPage", STAMUNIT_OCCURENCES, "The number of pages marked not present for accessed bit emulation.");
1762	STAM_REG(pVM, &pPGM->StatR3DirtyBitTracking, STAMTYPE_PROFILE, "/PGM/R3/DirtyPage", STAMUNIT_TICKS_PER_CALL, "Profiling the dirty bit tracking in CheckPageFault().");
1763	STAM_REG(pVM, &pPGM->StatR3DirtyPage, STAMTYPE_COUNTER, "/PGM/R3/DirtyPage/Mark", STAMUNIT_OCCURENCES, "The number of pages marked read-only for dirty bit tracking.");
1764	STAM_REG(pVM, &pPGM->StatR3DirtyPageBig, STAMTYPE_COUNTER, "/PGM/R3/DirtyPage/MarkBig", STAMUNIT_OCCURENCES, "The number of 4MB pages marked read-only for dirty bit tracking.");
1765	STAM_REG(pVM, &pPGM->StatR3DirtyPageSkipped, STAMTYPE_COUNTER, "/PGM/R3/DirtyPage/Skipped", STAMUNIT_OCCURENCES, "The number of pages already dirty or readonly.");
1766	STAM_REG(pVM, &pPGM->StatR3DirtyPageTrap, STAMTYPE_COUNTER, "/PGM/R3/DirtyPage/Trap", STAMUNIT_OCCURENCES, "The number of traps generated for dirty bit tracking.");
1767	STAM_REG(pVM, &pPGM->StatR3DirtiedPage, STAMTYPE_COUNTER, "/PGM/R3/DirtyPage/SetDirty", STAMUNIT_OCCURENCES, "The number of pages marked dirty because of write accesses.");
1768	STAM_REG(pVM, &pPGM->StatR3DirtyTrackRealPF, STAMTYPE_COUNTER, "/PGM/R3/DirtyPage/RealPF", STAMUNIT_OCCURENCES, "The number of real pages faults during dirty bit tracking.");
1769	STAM_REG(pVM, &pPGM->StatR3PageAlreadyDirty, STAMTYPE_COUNTER, "/PGM/R3/DirtyPage/AlreadySet", STAMUNIT_OCCURENCES, "The number of pages already marked dirty because of write accesses.");
1770	STAM_REG(pVM, &pPGM->StatR3InvalidatePage, STAMTYPE_PROFILE, "/PGM/R3/InvalidatePage", STAMUNIT_TICKS_PER_CALL, "PGMInvalidatePage() profiling.");
1771	STAM_REG(pVM, &pPGM->StatR3InvalidatePage4KBPages, STAMTYPE_COUNTER, "/PGM/R3/InvalidatePage/4KBPages", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was called for a 4KB page.");
1772	STAM_REG(pVM, &pPGM->StatR3InvalidatePage4MBPages, STAMTYPE_COUNTER, "/PGM/R3/InvalidatePage/4MBPages", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was called for a 4MB page.");
1773	STAM_REG(pVM, &pPGM->StatR3InvalidatePage4MBPagesSkip, STAMTYPE_COUNTER, "/PGM/R3/InvalidatePage/4MBPagesSkip",STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() skipped a 4MB page.");
1774	STAM_REG(pVM, &pPGM->StatR3InvalidatePagePDMappings, STAMTYPE_COUNTER, "/PGM/R3/InvalidatePage/PDMappings", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict).");
1775	STAM_REG(pVM, &pPGM->StatR3InvalidatePagePDNAs, STAMTYPE_COUNTER, "/PGM/R3/InvalidatePage/PDNAs", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was called for a not accessed page directory.");
1776	STAM_REG(pVM, &pPGM->StatR3InvalidatePagePDNPs, STAMTYPE_COUNTER, "/PGM/R3/InvalidatePage/PDNPs", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was called for a not present page directory.");
1777	STAM_REG(pVM, &pPGM->StatR3InvalidatePagePDOutOfSync, STAMTYPE_COUNTER, "/PGM/R3/InvalidatePage/PDOutOfSync", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was called for an out of sync page directory.");
1778	STAM_REG(pVM, &pPGM->StatR3InvalidatePageSkipped, STAMTYPE_COUNTER, "/PGM/R3/InvalidatePage/Skipped", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3.");
1779	STAM_REG(pVM, &pPGM->StatR3VirtHandlerSearchByPhys, STAMTYPE_PROFILE, "/PGM/R3/VirtHandlerSearchByPhys", STAMUNIT_TICKS_PER_CALL, "Profiling of pgmHandlerVirtualFindByPhysAddr.");
1780	STAM_REG(pVM, &pPGM->StatR3PhysHandlerReset, STAMTYPE_COUNTER, "/PGM/R3/PhysHandlerReset", STAMUNIT_OCCURENCES, "The number of times PGMHandlerPhysicalReset is called.");
1781	STAM_REG(pVM, &pPGM->StatR3PageOutOfSyncSupervisor, STAMTYPE_COUNTER, "/PGM/R3/OutOfSync/SuperVisor", STAMUNIT_OCCURENCES, "Number of traps due to pages out of sync and times VerifyAccessSyncPage calls SyncPage.");
1782	STAM_REG(pVM, &pPGM->StatR3PageOutOfSyncUser, STAMTYPE_COUNTER, "/PGM/R3/OutOfSync/User", STAMUNIT_OCCURENCES, "Number of traps due to pages out of sync and times VerifyAccessSyncPage calls SyncPage.");
1783	STAM_REG(pVM, &pPGM->StatR3Prefetch, STAMTYPE_PROFILE, "/PGM/R3/Prefetch", STAMUNIT_TICKS_PER_CALL, "PGMPrefetchPage profiling.");
1784	STAM_REG(pVM, &pPGM->StatR3ChunkR3MapTlbHits, STAMTYPE_COUNTER, "/PGM/ChunkR3Map/TlbHitsR3", STAMUNIT_OCCURENCES, "TLB hits.");
1785	STAM_REG(pVM, &pPGM->StatR3ChunkR3MapTlbMisses, STAMTYPE_COUNTER, "/PGM/ChunkR3Map/TlbMissesR3", STAMUNIT_OCCURENCES, "TLB misses.");
1786	STAM_REG(pVM, &pPGM->StatR3PageMapTlbHits, STAMTYPE_COUNTER, "/PGM/R3/Page/MapTlbHits", STAMUNIT_OCCURENCES, "TLB hits.");
1787	STAM_REG(pVM, &pPGM->StatR3PageMapTlbMisses, STAMTYPE_COUNTER, "/PGM/R3/Page/MapTlbMisses", STAMUNIT_OCCURENCES, "TLB misses.");
1788	STAM_REG(pVM, &pPGM->StatR3PageReplaceShared, STAMTYPE_COUNTER, "/PGM/R3/Page/ReplacedShared", STAMUNIT_OCCURENCES, "Times a shared page was replaced.");
1789	STAM_REG(pVM, &pPGM->StatR3PageReplaceZero, STAMTYPE_COUNTER, "/PGM/R3/Page/ReplacedZero", STAMUNIT_OCCURENCES, "Times the zero page was replaced.");
1790	/// @todo STAM_REG(pVM, &pPGM->StatR3PageHandyAllocs, STAMTYPE_COUNTER, "/PGM/R3/Page/HandyAllocs", STAMUNIT_OCCURENCES, "Number of times we've allocated more handy pages.");
1791	STAM_REG(pVM, &pPGM->StatR3FlushTLB, STAMTYPE_PROFILE, "/PGM/R3/FlushTLB", STAMUNIT_OCCURENCES, "Profiling of the PGMFlushTLB() body.");
1792	STAM_REG(pVM, &pPGM->StatR3FlushTLBNewCR3, STAMTYPE_COUNTER, "/PGM/R3/FlushTLB/NewCR3", STAMUNIT_OCCURENCES, "The number of times PGMFlushTLB was called with a new CR3, non-global. (switch)");
1793	STAM_REG(pVM, &pPGM->StatR3FlushTLBNewCR3Global, STAMTYPE_COUNTER, "/PGM/R3/FlushTLB/NewCR3Global", STAMUNIT_OCCURENCES, "The number of times PGMFlushTLB was called with a new CR3, global. (switch)");
1794	STAM_REG(pVM, &pPGM->StatR3FlushTLBSameCR3, STAMTYPE_COUNTER, "/PGM/R3/FlushTLB/SameCR3", STAMUNIT_OCCURENCES, "The number of times PGMFlushTLB was called with the same CR3, non-global. (flush)");
1795	STAM_REG(pVM, &pPGM->StatR3FlushTLBSameCR3Global, STAMTYPE_COUNTER, "/PGM/R3/FlushTLB/SameCR3Global", STAMUNIT_OCCURENCES, "The number of times PGMFlushTLB was called with the same CR3, global. (flush)");
1796	STAM_REG(pVM, &pPGM->StatR3GstModifyPage, STAMTYPE_PROFILE, "/PGM/R3/GstModifyPage", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMGstModifyPage() body.");
1797
1798	}
1799	#endif /* VBOX_WITH_STATISTICS */
1800
1801
1802	/**
1803	* Init the PGM bits that rely on VMMR0 and MM to be fully initialized.
1804	*
1805	* The dynamic mapping area will also be allocated and initialized at this
1806	* time. We could allocate it during PGMR3Init of course, but the mapping
1807	* wouldn't be allocated at that time preventing us from setting up the
1808	* page table entries with the dummy page.
1809	*
1810	* @returns VBox status code.
1811	* @param pVM VM handle.
1812	*/
1813	VMMR3DECL(int) PGMR3InitDynMap(PVM pVM)
1814	{
1815	RTGCPTR GCPtr;
1816	int rc;
1817
1818	#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
1819	/*
1820	* Reserve space for mapping the paging pages into guest context.
1821	*/
1822	rc = MMR3HyperReserve(pVM, PAGE_SIZE * (2 + RT_ELEMENTS(pVM->pgm.s.apShwPaePDsR3) + 1 + 2 + 2), "Paging", &GCPtr);
1823	AssertRCReturn(rc, rc);
1824	pVM->pgm.s.pShw32BitPdRC = GCPtr;
1825	MMR3HyperReserve(pVM, PAGE_SIZE, "fence", NULL);
1826	#endif
1827
1828	/*
1829	* Reserve space for the dynamic mappings.
1830	*/
1831	rc = MMR3HyperReserve(pVM, MM_HYPER_DYNAMIC_SIZE, "Dynamic mapping", &GCPtr);
1832	if (RT_SUCCESS(rc))
1833	pVM->pgm.s.pbDynPageMapBaseGC = GCPtr;
1834
1835	if ( RT_SUCCESS(rc)
1836	&& (pVM->pgm.s.pbDynPageMapBaseGC >> X86_PD_PAE_SHIFT) != ((pVM->pgm.s.pbDynPageMapBaseGC + MM_HYPER_DYNAMIC_SIZE - 1) >> X86_PD_PAE_SHIFT))
1837	{
1838	rc = MMR3HyperReserve(pVM, MM_HYPER_DYNAMIC_SIZE, "Dynamic mapping not crossing", &GCPtr);
1839	if (RT_SUCCESS(rc))
1840	pVM->pgm.s.pbDynPageMapBaseGC = GCPtr;
1841	}
1842	if (RT_SUCCESS(rc))
1843	{
1844	AssertRelease((pVM->pgm.s.pbDynPageMapBaseGC >> X86_PD_PAE_SHIFT) == ((pVM->pgm.s.pbDynPageMapBaseGC + MM_HYPER_DYNAMIC_SIZE - 1) >> X86_PD_PAE_SHIFT));
1845	MMR3HyperReserve(pVM, PAGE_SIZE, "fence", NULL);
1846	}
1847	return rc;
1848	}
1849
1850
1851	/**
1852	* Ring-3 init finalizing.
1853	*
1854	* @returns VBox status code.
1855	* @param pVM The VM handle.
1856	*/
1857	VMMR3DECL(int) PGMR3InitFinalize(PVM pVM)
1858	{
1859	int rc;
1860
1861	#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
1862	/*
1863	* Map the paging pages into the guest context.
1864	*/
1865	RTGCPTR GCPtr = pVM->pgm.s.pShw32BitPdRC;
1866	AssertReleaseReturn(GCPtr, VERR_INTERNAL_ERROR);
1867
1868	rc = PGMMap(pVM, GCPtr, pVM->pgm.s.HCPhysShw32BitPD, PAGE_SIZE, 0);
1869	AssertRCReturn(rc, rc);
1870	pVM->pgm.s.pShw32BitPdRC = GCPtr;
1871	GCPtr += PAGE_SIZE;
1872	GCPtr += PAGE_SIZE; /* reserved page */
1873
1874	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.apShwPaePDsR3); i++)
1875	{
1876	rc = PGMMap(pVM, GCPtr, pVM->pgm.s.aHCPhysPaePDs[i], PAGE_SIZE, 0);
1877	AssertRCReturn(rc, rc);
1878	pVM->pgm.s.apShwPaePDsRC[i] = GCPtr;
1879	GCPtr += PAGE_SIZE;
1880	}
1881	/* A bit of paranoia is justified. */
1882	AssertRelease(pVM->pgm.s.apShwPaePDsRC[0] + PAGE_SIZE == pVM->pgm.s.apShwPaePDsRC[1]);
1883	AssertRelease(pVM->pgm.s.apShwPaePDsRC[1] + PAGE_SIZE == pVM->pgm.s.apShwPaePDsRC[2]);
1884	AssertRelease(pVM->pgm.s.apShwPaePDsRC[2] + PAGE_SIZE == pVM->pgm.s.apShwPaePDsRC[3]);
1885	GCPtr += PAGE_SIZE; /* reserved page */
1886
1887	rc = PGMMap(pVM, GCPtr, pVM->pgm.s.HCPhysShwPaePdpt, PAGE_SIZE, 0);
1888	AssertRCReturn(rc, rc);
1889	pVM->pgm.s.pShwPaePdptRC = GCPtr;
1890	GCPtr += PAGE_SIZE;
1891	GCPtr += PAGE_SIZE; /* reserved page */
1892	#endif
1893
1894	/*
1895	* Reserve space for the dynamic mappings.
1896	* Initialize the dynamic mapping pages with dummy pages to simply the cache.
1897	*/
1898	/* get the pointer to the page table entries. */
1899	PPGMMAPPING pMapping = pgmGetMapping(pVM, pVM->pgm.s.pbDynPageMapBaseGC);
1900	AssertRelease(pMapping);
1901	const uintptr_t off = pVM->pgm.s.pbDynPageMapBaseGC - pMapping->GCPtr;
1902	const unsigned iPT = off >> X86_PD_SHIFT;
1903	const unsigned iPG = (off >> X86_PT_SHIFT) & X86_PT_MASK;
1904	pVM->pgm.s.paDynPageMap32BitPTEsGC = pMapping->aPTs[iPT].pPTRC + iPG * sizeof(pMapping->aPTs[0].pPTR3->a[0]);
1905	pVM->pgm.s.paDynPageMapPaePTEsGC = pMapping->aPTs[iPT].paPaePTsRC + iPG * sizeof(pMapping->aPTs[0].paPaePTsR3->a[0]);
1906
1907	/* init cache */
1908	RTHCPHYS HCPhysDummy = MMR3PageDummyHCPhys(pVM);
1909	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.aHCPhysDynPageMapCache); i++)
1910	pVM->pgm.s.aHCPhysDynPageMapCache[i] = HCPhysDummy;
1911
1912	for (unsigned i = 0; i < MM_HYPER_DYNAMIC_SIZE; i += PAGE_SIZE)
1913	{
1914	rc = PGMMap(pVM, pVM->pgm.s.pbDynPageMapBaseGC + i, HCPhysDummy, PAGE_SIZE, 0);
1915	AssertRCReturn(rc, rc);
1916	}
1917
1918	/*
1919	* Note that AMD uses all the 8 reserved bits for the address (so 40 bits in total);
1920	* Intel only goes up to 36 bits, so we stick to 36 as well.
1921	*/
1922	/** @todo How to test for the 40 bits support? Long mode seems to be the test criterium. */
1923	uint32_t u32Dummy, u32Features;
1924	CPUMGetGuestCpuId(pVM, 1, &u32Dummy, &u32Dummy, &u32Dummy, &u32Features);
1925
1926	if (u32Features & X86_CPUID_FEATURE_EDX_PSE36)
1927	pVM->pgm.s.GCPhys4MBPSEMask = RT_BIT_64(36) - 1;
1928	else
1929	pVM->pgm.s.GCPhys4MBPSEMask = RT_BIT_64(32) - 1;
1930
1931	LogRel(("PGMR3InitFinalize: 4 MB PSE mask %RGp\n", pVM->pgm.s.GCPhys4MBPSEMask));
1932
1933	return rc;
1934	}
1935
1936
1937	/**
1938	* Applies relocations to data and code managed by this component.
1939	*
1940	* This function will be called at init and whenever the VMM need to relocate it
1941	* self inside the GC.
1942	*
1943	* @param pVM The VM.
1944	* @param offDelta Relocation delta relative to old location.
1945	*/
1946	VMMR3DECL(void) PGMR3Relocate(PVM pVM, RTGCINTPTR offDelta)
1947	{
1948	LogFlow(("PGMR3Relocate\n"));
1949
1950	/*
1951	* Paging stuff.
1952	*/
1953	pVM->pgm.s.GCPtrCR3Mapping += offDelta;
1954	/** @todo move this into shadow and guest specific relocation functions. */
1955	AssertMsg(pVM->pgm.s.pShw32BitPdR3, ("Init order, no relocation before paging is initialized!\n"));
1956	#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
1957	pVM->pgm.s.pShw32BitPdRC += offDelta;
1958	#endif
1959	pVM->pgm.s.pGst32BitPdRC += offDelta;
1960	AssertCompile(RT_ELEMENTS(pVM->pgm.s.apShwPaePDsRC) == RT_ELEMENTS(pVM->pgm.s.apGstPaePDsRC));
1961	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.apShwPaePDsRC); i++)
1962	{
1963	#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
1964	pVM->pgm.s.apShwPaePDsRC[i] += offDelta;
1965	#endif
1966	pVM->pgm.s.apGstPaePDsRC[i] += offDelta;
1967	}
1968	pVM->pgm.s.pGstPaePdptRC += offDelta;
1969	#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
1970	pVM->pgm.s.pShwPaePdptRC += offDelta;
1971	#endif
1972
1973	pgmR3ModeDataInit(pVM, true /* resolve GC/R0 symbols */);
1974	pgmR3ModeDataSwitch(pVM, pVM->pgm.s.enmShadowMode, pVM->pgm.s.enmGuestMode);
1975
1976	PGM_SHW_PFN(Relocate, pVM)(pVM, offDelta);
1977	PGM_GST_PFN(Relocate, pVM)(pVM, offDelta);
1978	PGM_BTH_PFN(Relocate, pVM)(pVM, offDelta);
1979
1980	/*
1981	* Trees.
1982	*/
1983	pVM->pgm.s.pTreesRC = MMHyperR3ToRC(pVM, pVM->pgm.s.pTreesR3);
1984
1985	/*
1986	* Ram ranges.
1987	*/
1988	if (pVM->pgm.s.pRamRangesR3)
1989	{
1990	pVM->pgm.s.pRamRangesRC = MMHyperR3ToRC(pVM, pVM->pgm.s.pRamRangesR3);
1991	for (PPGMRAMRANGE pCur = pVM->pgm.s.pRamRangesR3; pCur->pNextR3; pCur = pCur->pNextR3)
1992	pCur->pNextRC = MMHyperR3ToRC(pVM, pCur->pNextR3);
1993	}
1994
1995	/*
1996	* Update the two page directories with all page table mappings.
1997	* (One or more of them have changed, that's why we're here.)
1998	*/
1999	pVM->pgm.s.pMappingsRC = MMHyperR3ToRC(pVM, pVM->pgm.s.pMappingsR3);
2000	for (PPGMMAPPING pCur = pVM->pgm.s.pMappingsR3; pCur->pNextR3; pCur = pCur->pNextR3)
2001	pCur->pNextRC = MMHyperR3ToRC(pVM, pCur->pNextR3);
2002
2003	/* Relocate GC addresses of Page Tables. */
2004	for (PPGMMAPPING pCur = pVM->pgm.s.pMappingsR3; pCur; pCur = pCur->pNextR3)
2005	{
2006	for (RTHCUINT i = 0; i < pCur->cPTs; i++)
2007	{
2008	pCur->aPTs[i].pPTRC = MMHyperR3ToRC(pVM, pCur->aPTs[i].pPTR3);
2009	pCur->aPTs[i].paPaePTsRC = MMHyperR3ToRC(pVM, pCur->aPTs[i].paPaePTsR3);
2010	}
2011	}
2012
2013	/*
2014	* Dynamic page mapping area.
2015	*/
2016	pVM->pgm.s.paDynPageMap32BitPTEsGC += offDelta;
2017	pVM->pgm.s.paDynPageMapPaePTEsGC += offDelta;
2018	pVM->pgm.s.pbDynPageMapBaseGC += offDelta;
2019
2020	/*
2021	* The Zero page.
2022	*/
2023	pVM->pgm.s.pvZeroPgR0 = MMHyperR3ToR0(pVM, pVM->pgm.s.pvZeroPgR3);
2024	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
2025	AssertRelease(pVM->pgm.s.pvZeroPgR0 != NIL_RTR0PTR \|\| !VMMIsHwVirtExtForced(pVM));
2026	#else
2027	AssertRelease(pVM->pgm.s.pvZeroPgR0 != NIL_RTR0PTR);
2028	#endif
2029
2030	/*
2031	* Physical and virtual handlers.
2032	*/
2033	RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysHandlers, true, pgmR3RelocatePhysHandler, &offDelta);
2034	RTAvlroGCPtrDoWithAll(&pVM->pgm.s.pTreesR3->VirtHandlers, true, pgmR3RelocateVirtHandler, &offDelta);
2035	RTAvlroGCPtrDoWithAll(&pVM->pgm.s.pTreesR3->HyperVirtHandlers, true, pgmR3RelocateHyperVirtHandler, &offDelta);
2036
2037	/*
2038	* The page pool.
2039	*/
2040	pgmR3PoolRelocate(pVM);
2041	}
2042
2043
2044	/**
2045	* Callback function for relocating a physical access handler.
2046	*
2047	* @returns 0 (continue enum)
2048	* @param pNode Pointer to a PGMPHYSHANDLER node.
2049	* @param pvUser Pointer to the offDelta. This is a pointer to the delta since we're
2050	* not certain the delta will fit in a void pointer for all possible configs.
2051	*/
2052	static DECLCALLBACK(int) pgmR3RelocatePhysHandler(PAVLROGCPHYSNODECORE pNode, void *pvUser)
2053	{
2054	PPGMPHYSHANDLER pHandler = (PPGMPHYSHANDLER)pNode;
2055	RTGCINTPTR offDelta = *(PRTGCINTPTR)pvUser;
2056	if (pHandler->pfnHandlerRC)
2057	pHandler->pfnHandlerRC += offDelta;
2058	if (pHandler->pvUserRC >= 0x10000)
2059	pHandler->pvUserRC += offDelta;
2060	return 0;
2061	}
2062
2063
2064	/**
2065	* Callback function for relocating a virtual access handler.
2066	*
2067	* @returns 0 (continue enum)
2068	* @param pNode Pointer to a PGMVIRTHANDLER node.
2069	* @param pvUser Pointer to the offDelta. This is a pointer to the delta since we're
2070	* not certain the delta will fit in a void pointer for all possible configs.
2071	*/
2072	static DECLCALLBACK(int) pgmR3RelocateVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser)
2073	{
2074	PPGMVIRTHANDLER pHandler = (PPGMVIRTHANDLER)pNode;
2075	RTGCINTPTR offDelta = *(PRTGCINTPTR)pvUser;
2076	Assert( pHandler->enmType == PGMVIRTHANDLERTYPE_ALL
2077	\|\| pHandler->enmType == PGMVIRTHANDLERTYPE_WRITE);
2078	Assert(pHandler->pfnHandlerRC);
2079	pHandler->pfnHandlerRC += offDelta;
2080	return 0;
2081	}
2082
2083
2084	/**
2085	* Callback function for relocating a virtual access handler for the hypervisor mapping.
2086	*
2087	* @returns 0 (continue enum)
2088	* @param pNode Pointer to a PGMVIRTHANDLER node.
2089	* @param pvUser Pointer to the offDelta. This is a pointer to the delta since we're
2090	* not certain the delta will fit in a void pointer for all possible configs.
2091	*/
2092	static DECLCALLBACK(int) pgmR3RelocateHyperVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser)
2093	{
2094	PPGMVIRTHANDLER pHandler = (PPGMVIRTHANDLER)pNode;
2095	RTGCINTPTR offDelta = *(PRTGCINTPTR)pvUser;
2096	Assert(pHandler->enmType == PGMVIRTHANDLERTYPE_HYPERVISOR);
2097	Assert(pHandler->pfnHandlerRC);
2098	pHandler->pfnHandlerRC += offDelta;
2099	return 0;
2100	}
2101
2102
2103	/**
2104	* The VM is being reset.
2105	*
2106	* For the PGM component this means that any PD write monitors
2107	* needs to be removed.
2108	*
2109	* @param pVM VM handle.
2110	*/
2111	VMMR3DECL(void) PGMR3Reset(PVM pVM)
2112	{
2113	LogFlow(("PGMR3Reset:\n"));
2114	VM_ASSERT_EMT(pVM);
2115
2116	pgmLock(pVM);
2117
2118	/*
2119	* Unfix any fixed mappings and disable CR3 monitoring.
2120	*/
2121	pVM->pgm.s.fMappingsFixed = false;
2122	pVM->pgm.s.GCPtrMappingFixed = 0;
2123	pVM->pgm.s.cbMappingFixed = 0;
2124
2125	/* Exit the guest paging mode before the pgm pool gets reset.
2126	* Important to clean up the amd64 case.
2127	*/
2128	int rc = PGM_GST_PFN(Exit, pVM)(pVM);
2129	AssertRC(rc);
2130	#ifdef DEBUG
2131	DBGFR3InfoLog(pVM, "mappings", NULL);
2132	DBGFR3InfoLog(pVM, "handlers", "all nostat");
2133	#endif
2134
2135	/*
2136	* Reset the shadow page pool.
2137	*/
2138	pgmR3PoolReset(pVM);
2139
2140	/*
2141	* Re-init other members.
2142	*/
2143	pVM->pgm.s.fA20Enabled = true;
2144
2145	/*
2146	* Clear the FFs PGM owns.
2147	*/
2148	VM_FF_CLEAR(pVM, VM_FF_PGM_SYNC_CR3);
2149	VM_FF_CLEAR(pVM, VM_FF_PGM_SYNC_CR3_NON_GLOBAL);
2150
2151	/*
2152	* Reset (zero) RAM pages.
2153	*/
2154	rc = pgmR3PhysRamReset(pVM);
2155	if (RT_SUCCESS(rc))
2156	{
2157	#ifdef VBOX_WITH_NEW_PHYS_CODE
2158	/*
2159	* Reset (zero) shadow ROM pages.
2160	*/
2161	rc = pgmR3PhysRomReset(pVM);
2162	#endif
2163	if (RT_SUCCESS(rc))
2164	{
2165	/*
2166	* Switch mode back to real mode.
2167	*/
2168	rc = PGMR3ChangeMode(pVM, PGMMODE_REAL);
2169	STAM_REL_COUNTER_RESET(&pVM->pgm.s.cGuestModeChanges);
2170	}
2171	}
2172
2173	pgmUnlock(pVM);
2174	//return rc;
2175	AssertReleaseRC(rc);
2176	}
2177
2178
2179	#ifdef VBOX_STRICT
2180	/**
2181	* VM state change callback for clearing fNoMorePhysWrites after
2182	* a snapshot has been created.
2183	*/
2184	static DECLCALLBACK(void) pgmR3ResetNoMorePhysWritesFlag(PVM pVM, VMSTATE enmState, VMSTATE enmOldState, void *pvUser)
2185	{
2186	if (enmState == VMSTATE_RUNNING)
2187	pVM->pgm.s.fNoMorePhysWrites = false;
2188	}
2189	#endif
2190
2191
2192	/**
2193	* Terminates the PGM.
2194	*
2195	* @returns VBox status code.
2196	* @param pVM Pointer to VM structure.
2197	*/
2198	VMMR3DECL(int) PGMR3Term(PVM pVM)
2199	{
2200	return PDMR3CritSectDelete(&pVM->pgm.s.CritSect);
2201	}
2202
2203
2204	/**
2205	* Terminates the per-VCPU PGM.
2206	*
2207	* Termination means cleaning up and freeing all resources,
2208	* the VM it self is at this point powered off or suspended.
2209	*
2210	* @returns VBox status code.
2211	* @param pVM The VM to operate on.
2212	*/
2213	VMMR3DECL(int) PGMR3TermCPU(PVM pVM)
2214	{
2215	return 0;
2216	}
2217
2218
2219	/**
2220	* Execute state save operation.
2221	*
2222	* @returns VBox status code.
2223	* @param pVM VM Handle.
2224	* @param pSSM SSM operation handle.
2225	*/
2226	static DECLCALLBACK(int) pgmR3Save(PVM pVM, PSSMHANDLE pSSM)
2227	{
2228	PPGM pPGM = &pVM->pgm.s;
2229
2230	/* No more writes to physical memory after this point! */
2231	pVM->pgm.s.fNoMorePhysWrites = true;
2232
2233	/*
2234	* Save basic data (required / unaffected by relocation).
2235	*/
2236	#if 1
2237	SSMR3PutBool(pSSM, pPGM->fMappingsFixed);
2238	#else
2239	SSMR3PutUInt(pSSM, pPGM->fMappingsFixed);
2240	#endif
2241	SSMR3PutGCPtr(pSSM, pPGM->GCPtrMappingFixed);
2242	SSMR3PutU32(pSSM, pPGM->cbMappingFixed);
2243	SSMR3PutUInt(pSSM, pPGM->cbRamSize);
2244	SSMR3PutGCPhys(pSSM, pPGM->GCPhysA20Mask);
2245	SSMR3PutUInt(pSSM, pPGM->fA20Enabled);
2246	SSMR3PutUInt(pSSM, pPGM->fSyncFlags);
2247	SSMR3PutUInt(pSSM, pPGM->enmGuestMode);
2248	SSMR3PutU32(pSSM, ~0); /* Separator. */
2249
2250	/*
2251	* The guest mappings.
2252	*/
2253	uint32_t i = 0;
2254	for (PPGMMAPPING pMapping = pPGM->pMappingsR3; pMapping; pMapping = pMapping->pNextR3, i++)
2255	{
2256	SSMR3PutU32(pSSM, i);
2257	SSMR3PutStrZ(pSSM, pMapping->pszDesc); /* This is the best unique id we have... */
2258	SSMR3PutGCPtr(pSSM, pMapping->GCPtr);
2259	SSMR3PutGCUIntPtr(pSSM, pMapping->cPTs);
2260	/* flags are done by the mapping owners! */
2261	}
2262	SSMR3PutU32(pSSM, ~0); /* terminator. */
2263
2264	/*
2265	* Ram range flags and bits.
2266	*/
2267	i = 0;
2268	for (PPGMRAMRANGE pRam = pPGM->pRamRangesR3; pRam; pRam = pRam->pNextR3, i++)
2269	{
2270	/** @todo MMIO ranges may move (PCI reconfig), we currently assume they don't. */
2271
2272	SSMR3PutU32(pSSM, i);
2273	SSMR3PutGCPhys(pSSM, pRam->GCPhys);
2274	SSMR3PutGCPhys(pSSM, pRam->GCPhysLast);
2275	SSMR3PutGCPhys(pSSM, pRam->cb);
2276	SSMR3PutU8(pSSM, !!pRam->pvR3); /* boolean indicating memory or not. */
2277
2278	/* Flags. */
2279	const unsigned cPages = pRam->cb >> PAGE_SHIFT;
2280	for (unsigned iPage = 0; iPage < cPages; iPage++)
2281	SSMR3PutU16(pSSM, (uint16_t)(pRam->aPages[iPage].HCPhys & ~X86_PTE_PAE_PG_MASK)); /** @todo PAGE FLAGS */
2282
2283	/* any memory associated with the range. */
2284	if (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)
2285	{
2286	for (unsigned iChunk = 0; iChunk < (pRam->cb >> PGM_DYNAMIC_CHUNK_SHIFT); iChunk++)
2287	{
2288	if (pRam->paChunkR3Ptrs[iChunk])
2289	{
2290	SSMR3PutU8(pSSM, 1); /* chunk present */
2291	SSMR3PutMem(pSSM, (void *)pRam->paChunkR3Ptrs[iChunk], PGM_DYNAMIC_CHUNK_SIZE);
2292	}
2293	else
2294	SSMR3PutU8(pSSM, 0); /* no chunk present */
2295	}
2296	}
2297	else if (pRam->pvR3)
2298	{
2299	int rc = SSMR3PutMem(pSSM, pRam->pvR3, pRam->cb);
2300	if (RT_FAILURE(rc))
2301	{
2302	Log(("pgmR3Save: SSMR3PutMem(, %p, %#x) -> %Rrc\n", pRam->pvR3, pRam->cb, rc));
2303	return rc;
2304	}
2305	}
2306	}
2307	return SSMR3PutU32(pSSM, ~0); /* terminator. */
2308	}
2309
2310
2311	/**
2312	* Execute state load operation.
2313	*
2314	* @returns VBox status code.
2315	* @param pVM VM Handle.
2316	* @param pSSM SSM operation handle.
2317	* @param u32Version Data layout version.
2318	*/
2319	static DECLCALLBACK(int) pgmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version)
2320	{
2321	/*
2322	* Validate version.
2323	*/
2324	if (u32Version != PGM_SAVED_STATE_VERSION)
2325	{
2326	AssertMsgFailed(("pgmR3Load: Invalid version u32Version=%d (current %d)!\n", u32Version, PGM_SAVED_STATE_VERSION));
2327	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
2328	}
2329
2330	/*
2331	* Call the reset function to make sure all the memory is cleared.
2332	*/
2333	PGMR3Reset(pVM);
2334
2335	/*
2336	* Load basic data (required / unaffected by relocation).
2337	*/
2338	PPGM pPGM = &pVM->pgm.s;
2339	#if 1
2340	SSMR3GetBool(pSSM, &pPGM->fMappingsFixed);
2341	#else
2342	uint32_t u;
2343	SSMR3GetU32(pSSM, &u);
2344	pPGM->fMappingsFixed = u;
2345	#endif
2346	SSMR3GetGCPtr(pSSM, &pPGM->GCPtrMappingFixed);
2347	SSMR3GetU32(pSSM, &pPGM->cbMappingFixed);
2348
2349	RTUINT cbRamSize;
2350	int rc = SSMR3GetU32(pSSM, &cbRamSize);
2351	if (RT_FAILURE(rc))
2352	return rc;
2353	if (cbRamSize != pPGM->cbRamSize)
2354	return VERR_SSM_LOAD_MEMORY_SIZE_MISMATCH;
2355	SSMR3GetGCPhys(pSSM, &pPGM->GCPhysA20Mask);
2356	SSMR3GetUInt(pSSM, &pPGM->fA20Enabled);
2357	SSMR3GetUInt(pSSM, &pPGM->fSyncFlags);
2358	RTUINT uGuestMode;
2359	SSMR3GetUInt(pSSM, &uGuestMode);
2360	pPGM->enmGuestMode = (PGMMODE)uGuestMode;
2361
2362	/* check separator. */
2363	uint32_t u32Sep;
2364	SSMR3GetU32(pSSM, &u32Sep);
2365	if (RT_FAILURE(rc))
2366	return rc;
2367	if (u32Sep != (uint32_t)~0)
2368	{
2369	AssertMsgFailed(("u32Sep=%#x (first)\n", u32Sep));
2370	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2371	}
2372
2373	/*
2374	* The guest mappings.
2375	*/
2376	uint32_t i = 0;
2377	for (;; i++)
2378	{
2379	/* Check the seqence number / separator. */
2380	rc = SSMR3GetU32(pSSM, &u32Sep);
2381	if (RT_FAILURE(rc))
2382	return rc;
2383	if (u32Sep == ~0U)
2384	break;
2385	if (u32Sep != i)
2386	{
2387	AssertMsgFailed(("u32Sep=%#x (last)\n", u32Sep));
2388	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2389	}
2390
2391	/* get the mapping details. */
2392	char szDesc[256];
2393	szDesc[0] = '\0';
2394	rc = SSMR3GetStrZ(pSSM, szDesc, sizeof(szDesc));
2395	if (RT_FAILURE(rc))
2396	return rc;
2397	RTGCPTR GCPtr;
2398	SSMR3GetGCPtr(pSSM, &GCPtr);
2399	RTGCPTR cPTs;
2400	rc = SSMR3GetGCUIntPtr(pSSM, &cPTs);
2401	if (RT_FAILURE(rc))
2402	return rc;
2403
2404	/* find matching range. */
2405	PPGMMAPPING pMapping;
2406	for (pMapping = pPGM->pMappingsR3; pMapping; pMapping = pMapping->pNextR3)
2407	if ( pMapping->cPTs == cPTs
2408	&& !strcmp(pMapping->pszDesc, szDesc))
2409	break;
2410	if (!pMapping)
2411	{
2412	LogRel(("Couldn't find mapping: cPTs=%#x szDesc=%s (GCPtr=%RGv)\n",
2413	cPTs, szDesc, GCPtr));
2414	AssertFailed();
2415	return VERR_SSM_LOAD_CONFIG_MISMATCH;
2416	}
2417
2418	/* relocate it. */
2419	if (pMapping->GCPtr != GCPtr)
2420	{
2421	AssertMsg((GCPtr >> X86_PD_SHIFT << X86_PD_SHIFT) == GCPtr, ("GCPtr=%RGv\n", GCPtr));
2422	pgmR3MapRelocate(pVM, pMapping, pMapping->GCPtr, GCPtr);
2423	}
2424	else
2425	Log(("pgmR3Load: '%s' needed no relocation (%RGv)\n", szDesc, GCPtr));
2426	}
2427
2428	/*
2429	* Ram range flags and bits.
2430	*/
2431	i = 0;
2432	for (PPGMRAMRANGE pRam = pPGM->pRamRangesR3; pRam; pRam = pRam->pNextR3, i++)
2433	{
2434	/** @todo MMIO ranges may move (PCI reconfig), we currently assume they don't. */
2435	/* Check the seqence number / separator. */
2436	rc = SSMR3GetU32(pSSM, &u32Sep);
2437	if (RT_FAILURE(rc))
2438	return rc;
2439	if (u32Sep == ~0U)
2440	break;
2441	if (u32Sep != i)
2442	{
2443	AssertMsgFailed(("u32Sep=%#x (last)\n", u32Sep));
2444	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2445	}
2446
2447	/* Get the range details. */
2448	RTGCPHYS GCPhys;
2449	SSMR3GetGCPhys(pSSM, &GCPhys);
2450	RTGCPHYS GCPhysLast;
2451	SSMR3GetGCPhys(pSSM, &GCPhysLast);
2452	RTGCPHYS cb;
2453	SSMR3GetGCPhys(pSSM, &cb);
2454	uint8_t fHaveBits;
2455	rc = SSMR3GetU8(pSSM, &fHaveBits);
2456	if (RT_FAILURE(rc))
2457	return rc;
2458	if (fHaveBits & ~1)
2459	{
2460	AssertMsgFailed(("u32Sep=%#x (last)\n", u32Sep));
2461	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2462	}
2463
2464	/* Match it up with the current range. */
2465	if ( GCPhys != pRam->GCPhys
2466	\|\| GCPhysLast != pRam->GCPhysLast
2467	\|\| cb != pRam->cb
2468	\|\| fHaveBits != !!pRam->pvR3)
2469	{
2470	LogRel(("Ram range: %RGp-%RGp %RGp bytes %s\n"
2471	"State : %RGp-%RGp %RGp bytes %s\n",
2472	pRam->GCPhys, pRam->GCPhysLast, pRam->cb, pRam->pvR3 ? "bits" : "nobits",
2473	GCPhys, GCPhysLast, cb, fHaveBits ? "bits" : "nobits"));
2474	/*
2475	* If we're loading a state for debugging purpose, don't make a fuss if
2476	* the MMIO[2] and ROM stuff isn't 100% right, just skip the mismatches.
2477	*/
2478	if ( SSMR3HandleGetAfter(pSSM) != SSMAFTER_DEBUG_IT
2479	\|\| GCPhys < 8 * _1M)
2480	AssertFailedReturn(VERR_SSM_LOAD_CONFIG_MISMATCH);
2481
2482	RTGCPHYS cPages = ((GCPhysLast - GCPhys) + 1) >> PAGE_SHIFT;
2483	while (cPages-- > 0)
2484	{
2485	uint16_t u16Ignore;
2486	SSMR3GetU16(pSSM, &u16Ignore);
2487	}
2488	continue;
2489	}
2490
2491	/* Flags. */
2492	const unsigned cPages = pRam->cb >> PAGE_SHIFT;
2493	for (unsigned iPage = 0; iPage < cPages; iPage++)
2494	{
2495	uint16_t u16 = 0;
2496	SSMR3GetU16(pSSM, &u16);
2497	u16 &= PAGE_OFFSET_MASK & ~( RT_BIT(4) \| RT_BIT(5) \| RT_BIT(6)
2498	\| RT_BIT(7) \| RT_BIT(8) \| RT_BIT(9) \| RT_BIT(10) );
2499	// &= MM_RAM_FLAGS_DYNAMIC_ALLOC \| MM_RAM_FLAGS_RESERVED \| MM_RAM_FLAGS_ROM \| MM_RAM_FLAGS_MMIO \| MM_RAM_FLAGS_MMIO2
2500	pRam->aPages[iPage].HCPhys = PGM_PAGE_GET_HCPHYS(&pRam->aPages[iPage]) \| (RTHCPHYS)u16; /** @todo PAGE FLAGS */
2501	}
2502
2503	/* any memory associated with the range. */
2504	if (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)
2505	{
2506	for (unsigned iChunk = 0; iChunk < (pRam->cb >> PGM_DYNAMIC_CHUNK_SHIFT); iChunk++)
2507	{
2508	uint8_t fValidChunk;
2509
2510	rc = SSMR3GetU8(pSSM, &fValidChunk);
2511	if (RT_FAILURE(rc))
2512	return rc;
2513	if (fValidChunk > 1)
2514	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2515
2516	if (fValidChunk)
2517	{
2518	if (!pRam->paChunkR3Ptrs[iChunk])
2519	{
2520	rc = pgmr3PhysGrowRange(pVM, pRam->GCPhys + iChunk * PGM_DYNAMIC_CHUNK_SIZE);
2521	if (RT_FAILURE(rc))
2522	return rc;
2523	}
2524	Assert(pRam->paChunkR3Ptrs[iChunk]);
2525
2526	SSMR3GetMem(pSSM, (void *)pRam->paChunkR3Ptrs[iChunk], PGM_DYNAMIC_CHUNK_SIZE);
2527	}
2528	/* else nothing to do */
2529	}
2530	}
2531	else if (pRam->pvR3)
2532	{
2533	int rc = SSMR3GetMem(pSSM, pRam->pvR3, pRam->cb);
2534	if (RT_FAILURE(rc))
2535	{
2536	Log(("pgmR3Save: SSMR3GetMem(, %p, %#x) -> %Rrc\n", pRam->pvR3, pRam->cb, rc));
2537	return rc;
2538	}
2539	}
2540	}
2541
2542	/*
2543	* We require a full resync now.
2544	*/
2545	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3_NON_GLOBAL);
2546	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
2547	pPGM->fSyncFlags \|= PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL;
2548	pPGM->fPhysCacheFlushPending = true;
2549	pgmR3HandlerPhysicalUpdateAll(pVM);
2550
2551	/*
2552	* Change the paging mode.
2553	*/
2554	rc = PGMR3ChangeMode(pVM, pPGM->enmGuestMode);
2555
2556	/* Restore pVM->pgm.s.GCPhysCR3. */
2557	Assert(pVM->pgm.s.GCPhysCR3 == NIL_RTGCPHYS);
2558	RTGCPHYS GCPhysCR3 = CPUMGetGuestCR3(pVM);
2559	if ( pVM->pgm.s.enmGuestMode == PGMMODE_PAE
2560	\|\| pVM->pgm.s.enmGuestMode == PGMMODE_PAE_NX
2561	\|\| pVM->pgm.s.enmGuestMode == PGMMODE_AMD64
2562	\|\| pVM->pgm.s.enmGuestMode == PGMMODE_AMD64_NX)
2563	GCPhysCR3 = (GCPhysCR3 & X86_CR3_PAE_PAGE_MASK);
2564	else
2565	GCPhysCR3 = (GCPhysCR3 & X86_CR3_PAGE_MASK);
2566	pVM->pgm.s.GCPhysCR3 = GCPhysCR3;
2567
2568	return rc;
2569	}
2570
2571
2572	/**
2573	* Show paging mode.
2574	*
2575	* @param pVM VM Handle.
2576	* @param pHlp The info helpers.
2577	* @param pszArgs "all" (default), "guest", "shadow" or "host".
2578	*/
2579	static DECLCALLBACK(void) pgmR3InfoMode(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2580	{
2581	/* digest argument. */
2582	bool fGuest, fShadow, fHost;
2583	if (pszArgs)
2584	pszArgs = RTStrStripL(pszArgs);
2585	if (!pszArgs \|\| !*pszArgs \|\| strstr(pszArgs, "all"))
2586	fShadow = fHost = fGuest = true;
2587	else
2588	{
2589	fShadow = fHost = fGuest = false;
2590	if (strstr(pszArgs, "guest"))
2591	fGuest = true;
2592	if (strstr(pszArgs, "shadow"))
2593	fShadow = true;
2594	if (strstr(pszArgs, "host"))
2595	fHost = true;
2596	}
2597
2598	/* print info. */
2599	if (fGuest)
2600	pHlp->pfnPrintf(pHlp, "Guest paging mode: %s, changed %RU64 times, A20 %s\n",
2601	PGMGetModeName(pVM->pgm.s.enmGuestMode), pVM->pgm.s.cGuestModeChanges.c,
2602	pVM->pgm.s.fA20Enabled ? "enabled" : "disabled");
2603	if (fShadow)
2604	pHlp->pfnPrintf(pHlp, "Shadow paging mode: %s\n", PGMGetModeName(pVM->pgm.s.enmShadowMode));
2605	if (fHost)
2606	{
2607	const char *psz;
2608	switch (pVM->pgm.s.enmHostMode)
2609	{
2610	case SUPPAGINGMODE_INVALID: psz = "invalid"; break;
2611	case SUPPAGINGMODE_32_BIT: psz = "32-bit"; break;
2612	case SUPPAGINGMODE_32_BIT_GLOBAL: psz = "32-bit+G"; break;
2613	case SUPPAGINGMODE_PAE: psz = "PAE"; break;
2614	case SUPPAGINGMODE_PAE_GLOBAL: psz = "PAE+G"; break;
2615	case SUPPAGINGMODE_PAE_NX: psz = "PAE+NX"; break;
2616	case SUPPAGINGMODE_PAE_GLOBAL_NX: psz = "PAE+G+NX"; break;
2617	case SUPPAGINGMODE_AMD64: psz = "AMD64"; break;
2618	case SUPPAGINGMODE_AMD64_GLOBAL: psz = "AMD64+G"; break;
2619	case SUPPAGINGMODE_AMD64_NX: psz = "AMD64+NX"; break;
2620	case SUPPAGINGMODE_AMD64_GLOBAL_NX: psz = "AMD64+G+NX"; break;
2621	default: psz = "unknown"; break;
2622	}
2623	pHlp->pfnPrintf(pHlp, "Host paging mode: %s\n", psz);
2624	}
2625	}
2626
2627
2628	/**
2629	* Dump registered MMIO ranges to the log.
2630	*
2631	* @param pVM VM Handle.
2632	* @param pHlp The info helpers.
2633	* @param pszArgs Arguments, ignored.
2634	*/
2635	static DECLCALLBACK(void) pgmR3PhysInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2636	{
2637	NOREF(pszArgs);
2638	pHlp->pfnPrintf(pHlp,
2639	"RAM ranges (pVM=%p)\n"
2640	"%.s %.s\n",
2641	pVM,
2642	sizeof(RTGCPHYS) * 4 + 1, "GC Phys Range ",
2643	sizeof(RTHCPTR) * 2, "pvHC ");
2644
2645	for (PPGMRAMRANGE pCur = pVM->pgm.s.pRamRangesR3; pCur; pCur = pCur->pNextR3)
2646	pHlp->pfnPrintf(pHlp,
2647	"%RGp-%RGp %RHv %s\n",
2648	pCur->GCPhys,
2649	pCur->GCPhysLast,
2650	pCur->pvR3,
2651	pCur->pszDesc);
2652	}
2653
2654	/**
2655	* Dump the page directory to the log.
2656	*
2657	* @param pVM VM Handle.
2658	* @param pHlp The info helpers.
2659	* @param pszArgs Arguments, ignored.
2660	*/
2661	static DECLCALLBACK(void) pgmR3InfoCr3(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2662	{
2663	/** @todo fix this! Convert the PGMR3DumpHierarchyHC functions to do guest stuff. */
2664	/* Big pages supported? */
2665	const bool fPSE = !!(CPUMGetGuestCR4(pVM) & X86_CR4_PSE);
2666
2667	/* Global pages supported? */
2668	const bool fPGE = !!(CPUMGetGuestCR4(pVM) & X86_CR4_PGE);
2669
2670	NOREF(pszArgs);
2671
2672	/*
2673	* Get page directory addresses.
2674	*/
2675	PX86PD pPDSrc = pVM->pgm.s.pGst32BitPdR3;
2676	Assert(pPDSrc);
2677	Assert(PGMPhysGCPhys2R3PtrAssert(pVM, (RTGCPHYS)(CPUMGetGuestCR3(pVM) & X86_CR3_PAGE_MASK), sizeof(*pPDSrc)) == pPDSrc);
2678
2679	/*
2680	* Iterate the page directory.
2681	*/
2682	for (unsigned iPD = 0; iPD < RT_ELEMENTS(pPDSrc->a); iPD++)
2683	{
2684	X86PDE PdeSrc = pPDSrc->a[iPD];
2685	if (PdeSrc.n.u1Present)
2686	{
2687	if (PdeSrc.b.u1Size && fPSE)
2688	pHlp->pfnPrintf(pHlp,
2689	"%04X - %RGp P=%d U=%d RW=%d G=%d - BIG\n",
2690	iPD,
2691	pgmGstGet4MBPhysPage(&pVM->pgm.s, PdeSrc),
2692	PdeSrc.b.u1Present, PdeSrc.b.u1User, PdeSrc.b.u1Write, PdeSrc.b.u1Global && fPGE);
2693	else
2694	pHlp->pfnPrintf(pHlp,
2695	"%04X - %RGp P=%d U=%d RW=%d [G=%d]\n",
2696	iPD,
2697	(RTGCPHYS)(PdeSrc.u & X86_PDE_PG_MASK),
2698	PdeSrc.n.u1Present, PdeSrc.n.u1User, PdeSrc.n.u1Write, PdeSrc.b.u1Global && fPGE);
2699	}
2700	}
2701	}
2702
2703
2704	/**
2705	* Serivce a VMMCALLHOST_PGM_LOCK call.
2706	*
2707	* @returns VBox status code.
2708	* @param pVM The VM handle.
2709	*/
2710	VMMR3DECL(int) PGMR3LockCall(PVM pVM)
2711	{
2712	int rc = PDMR3CritSectEnterEx(&pVM->pgm.s.CritSect, true /* fHostCall */);
2713	AssertRC(rc);
2714	return rc;
2715	}
2716
2717
2718	/**
2719	* Converts a PGMMODE value to a PGM_TYPE_* \#define.
2720	*
2721	* @returns PGM_TYPE_*.
2722	* @param pgmMode The mode value to convert.
2723	*/
2724	DECLINLINE(unsigned) pgmModeToType(PGMMODE pgmMode)
2725	{
2726	switch (pgmMode)
2727	{
2728	case PGMMODE_REAL: return PGM_TYPE_REAL;
2729	case PGMMODE_PROTECTED: return PGM_TYPE_PROT;
2730	case PGMMODE_32_BIT: return PGM_TYPE_32BIT;
2731	case PGMMODE_PAE:
2732	case PGMMODE_PAE_NX: return PGM_TYPE_PAE;
2733	case PGMMODE_AMD64:
2734	case PGMMODE_AMD64_NX: return PGM_TYPE_AMD64;
2735	case PGMMODE_NESTED: return PGM_TYPE_NESTED;
2736	case PGMMODE_EPT: return PGM_TYPE_EPT;
2737	default:
2738	AssertFatalMsgFailed(("pgmMode=%d\n", pgmMode));
2739	}
2740	}
2741
2742
2743	/**
2744	* Gets the index into the paging mode data array of a SHW+GST mode.
2745	*
2746	* @returns PGM::paPagingData index.
2747	* @param uShwType The shadow paging mode type.
2748	* @param uGstType The guest paging mode type.
2749	*/
2750	DECLINLINE(unsigned) pgmModeDataIndex(unsigned uShwType, unsigned uGstType)
2751	{
2752	Assert(uShwType >= PGM_TYPE_32BIT && uShwType <= PGM_TYPE_MAX);
2753	Assert(uGstType >= PGM_TYPE_REAL && uGstType <= PGM_TYPE_AMD64);
2754	return (uShwType - PGM_TYPE_32BIT) * (PGM_TYPE_AMD64 - PGM_TYPE_REAL + 1)
2755	+ (uGstType - PGM_TYPE_REAL);
2756	}
2757
2758
2759	/**
2760	* Gets the index into the paging mode data array of a SHW+GST mode.
2761	*
2762	* @returns PGM::paPagingData index.
2763	* @param enmShw The shadow paging mode.
2764	* @param enmGst The guest paging mode.
2765	*/
2766	DECLINLINE(unsigned) pgmModeDataIndexByMode(PGMMODE enmShw, PGMMODE enmGst)
2767	{
2768	Assert(enmShw >= PGMMODE_32_BIT && enmShw <= PGMMODE_MAX);
2769	Assert(enmGst > PGMMODE_INVALID && enmGst < PGMMODE_MAX);
2770	return pgmModeDataIndex(pgmModeToType(enmShw), pgmModeToType(enmGst));
2771	}
2772
2773
2774	/**
2775	* Calculates the max data index.
2776	* @returns The number of entries in the paging data array.
2777	*/
2778	DECLINLINE(unsigned) pgmModeDataMaxIndex(void)
2779	{
2780	return pgmModeDataIndex(PGM_TYPE_MAX, PGM_TYPE_AMD64) + 1;
2781	}
2782
2783
2784	/**
2785	* Initializes the paging mode data kept in PGM::paModeData.
2786	*
2787	* @param pVM The VM handle.
2788	* @param fResolveGCAndR0 Indicate whether or not GC and Ring-0 symbols can be resolved now.
2789	* This is used early in the init process to avoid trouble with PDM
2790	* not being initialized yet.
2791	*/
2792	static int pgmR3ModeDataInit(PVM pVM, bool fResolveGCAndR0)
2793	{
2794	PPGMMODEDATA pModeData;
2795	int rc;
2796
2797	/*
2798	* Allocate the array on the first call.
2799	*/
2800	if (!pVM->pgm.s.paModeData)
2801	{
2802	pVM->pgm.s.paModeData = (PPGMMODEDATA)MMR3HeapAllocZ(pVM, MM_TAG_PGM, sizeof(PGMMODEDATA) * pgmModeDataMaxIndex());
2803	AssertReturn(pVM->pgm.s.paModeData, VERR_NO_MEMORY);
2804	}
2805
2806	/*
2807	* Initialize the array entries.
2808	*/
2809	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_32BIT, PGM_TYPE_REAL)];
2810	pModeData->uShwType = PGM_TYPE_32BIT;
2811	pModeData->uGstType = PGM_TYPE_REAL;
2812	rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2813	rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2814	rc = PGM_BTH_NAME_32BIT_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2815
2816	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_32BIT, PGMMODE_PROTECTED)];
2817	pModeData->uShwType = PGM_TYPE_32BIT;
2818	pModeData->uGstType = PGM_TYPE_PROT;
2819	rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2820	rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2821	rc = PGM_BTH_NAME_32BIT_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2822
2823	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_32BIT, PGM_TYPE_32BIT)];
2824	pModeData->uShwType = PGM_TYPE_32BIT;
2825	pModeData->uGstType = PGM_TYPE_32BIT;
2826	rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2827	rc = PGM_GST_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2828	rc = PGM_BTH_NAME_32BIT_32BIT(InitData)(pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2829
2830	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_REAL)];
2831	pModeData->uShwType = PGM_TYPE_PAE;
2832	pModeData->uGstType = PGM_TYPE_REAL;
2833	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2834	rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2835	rc = PGM_BTH_NAME_PAE_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2836
2837	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_PROT)];
2838	pModeData->uShwType = PGM_TYPE_PAE;
2839	pModeData->uGstType = PGM_TYPE_PROT;
2840	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2841	rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2842	rc = PGM_BTH_NAME_PAE_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2843
2844	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_32BIT)];
2845	pModeData->uShwType = PGM_TYPE_PAE;
2846	pModeData->uGstType = PGM_TYPE_32BIT;
2847	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2848	rc = PGM_GST_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2849	rc = PGM_BTH_NAME_PAE_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2850
2851	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_PAE)];
2852	pModeData->uShwType = PGM_TYPE_PAE;
2853	pModeData->uGstType = PGM_TYPE_PAE;
2854	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2855	rc = PGM_GST_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2856	rc = PGM_BTH_NAME_PAE_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2857
2858	#ifdef VBOX_WITH_64_BITS_GUESTS
2859	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_AMD64, PGM_TYPE_AMD64)];
2860	pModeData->uShwType = PGM_TYPE_AMD64;
2861	pModeData->uGstType = PGM_TYPE_AMD64;
2862	rc = PGM_SHW_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2863	rc = PGM_GST_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2864	rc = PGM_BTH_NAME_AMD64_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2865	#endif
2866
2867	/* The nested paging mode. */
2868	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_REAL)];
2869	pModeData->uShwType = PGM_TYPE_NESTED;
2870	pModeData->uGstType = PGM_TYPE_REAL;
2871	rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2872	rc = PGM_BTH_NAME_NESTED_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2873
2874	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGMMODE_PROTECTED)];
2875	pModeData->uShwType = PGM_TYPE_NESTED;
2876	pModeData->uGstType = PGM_TYPE_PROT;
2877	rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2878	rc = PGM_BTH_NAME_NESTED_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2879
2880	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_32BIT)];
2881	pModeData->uShwType = PGM_TYPE_NESTED;
2882	pModeData->uGstType = PGM_TYPE_32BIT;
2883	rc = PGM_GST_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2884	rc = PGM_BTH_NAME_NESTED_32BIT(InitData)(pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2885
2886	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_PAE)];
2887	pModeData->uShwType = PGM_TYPE_NESTED;
2888	pModeData->uGstType = PGM_TYPE_PAE;
2889	rc = PGM_GST_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2890	rc = PGM_BTH_NAME_NESTED_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2891
2892	#ifdef VBOX_WITH_64_BITS_GUESTS
2893	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_AMD64)];
2894	pModeData->uShwType = PGM_TYPE_NESTED;
2895	pModeData->uGstType = PGM_TYPE_AMD64;
2896	rc = PGM_GST_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2897	rc = PGM_BTH_NAME_NESTED_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2898	#endif
2899
2900	/* The shadow part of the nested callback mode depends on the host paging mode (AMD-V only). */
2901	switch (pVM->pgm.s.enmHostMode)
2902	{
2903	#if HC_ARCH_BITS == 32
2904	case SUPPAGINGMODE_32_BIT:
2905	case SUPPAGINGMODE_32_BIT_GLOBAL:
2906	for (unsigned i = PGM_TYPE_REAL; i <= PGM_TYPE_PAE; i++)
2907	{
2908	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, i)];
2909	rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2910	}
2911	# ifdef VBOX_WITH_64_BITS_GUESTS
2912	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_AMD64)];
2913	rc = PGM_SHW_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2914	# endif
2915	break;
2916
2917	case SUPPAGINGMODE_PAE:
2918	case SUPPAGINGMODE_PAE_NX:
2919	case SUPPAGINGMODE_PAE_GLOBAL:
2920	case SUPPAGINGMODE_PAE_GLOBAL_NX:
2921	for (unsigned i = PGM_TYPE_REAL; i <= PGM_TYPE_PAE; i++)
2922	{
2923	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, i)];
2924	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2925	}
2926	# ifdef VBOX_WITH_64_BITS_GUESTS
2927	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_AMD64)];
2928	rc = PGM_SHW_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2929	# endif
2930	break;
2931	#endif /* HC_ARCH_BITS == 32 */
2932
2933	#if HC_ARCH_BITS == 64 \|\| defined(RT_OS_DARWIN)
2934	case SUPPAGINGMODE_AMD64:
2935	case SUPPAGINGMODE_AMD64_GLOBAL:
2936	case SUPPAGINGMODE_AMD64_NX:
2937	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
2938	# ifdef VBOX_WITH_64_BITS_GUESTS
2939	for (unsigned i = PGM_TYPE_REAL; i <= PGM_TYPE_AMD64; i++)
2940	# else
2941	for (unsigned i = PGM_TYPE_REAL; i <= PGM_TYPE_PAE; i++)
2942	# endif
2943	{
2944	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, i)];
2945	rc = PGM_SHW_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2946	}
2947	break;
2948	#endif /* HC_ARCH_BITS == 64 \|\| RT_OS_DARWIN */
2949
2950	default:
2951	AssertFailed();
2952	break;
2953	}
2954
2955	/* Extended paging (EPT) / Intel VT-x */
2956	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_REAL)];
2957	pModeData->uShwType = PGM_TYPE_EPT;
2958	pModeData->uGstType = PGM_TYPE_REAL;
2959	rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2960	rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2961	rc = PGM_BTH_NAME_EPT_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2962
2963	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_PROT)];
2964	pModeData->uShwType = PGM_TYPE_EPT;
2965	pModeData->uGstType = PGM_TYPE_PROT;
2966	rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2967	rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2968	rc = PGM_BTH_NAME_EPT_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2969
2970	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_32BIT)];
2971	pModeData->uShwType = PGM_TYPE_EPT;
2972	pModeData->uGstType = PGM_TYPE_32BIT;
2973	rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2974	rc = PGM_GST_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2975	rc = PGM_BTH_NAME_EPT_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2976
2977	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_PAE)];
2978	pModeData->uShwType = PGM_TYPE_EPT;
2979	pModeData->uGstType = PGM_TYPE_PAE;
2980	rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2981	rc = PGM_GST_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2982	rc = PGM_BTH_NAME_EPT_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2983
2984	#ifdef VBOX_WITH_64_BITS_GUESTS
2985	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_AMD64)];
2986	pModeData->uShwType = PGM_TYPE_EPT;
2987	pModeData->uGstType = PGM_TYPE_AMD64;
2988	rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2989	rc = PGM_GST_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2990	rc = PGM_BTH_NAME_EPT_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2991	#endif
2992	return VINF_SUCCESS;
2993	}
2994
2995
2996	/**
2997	* Switch to different (or relocated in the relocate case) mode data.
2998	*
2999	* @param pVM The VM handle.
3000	* @param enmShw The the shadow paging mode.
3001	* @param enmGst The the guest paging mode.
3002	*/
3003	static void pgmR3ModeDataSwitch(PVM pVM, PGMMODE enmShw, PGMMODE enmGst)
3004	{
3005	PPGMMODEDATA pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndexByMode(enmShw, enmGst)];
3006
3007	Assert(pModeData->uGstType == pgmModeToType(enmGst));
3008	Assert(pModeData->uShwType == pgmModeToType(enmShw));
3009
3010	/* shadow */
3011	pVM->pgm.s.pfnR3ShwRelocate = pModeData->pfnR3ShwRelocate;
3012	pVM->pgm.s.pfnR3ShwExit = pModeData->pfnR3ShwExit;
3013	pVM->pgm.s.pfnR3ShwGetPage = pModeData->pfnR3ShwGetPage;
3014	Assert(pVM->pgm.s.pfnR3ShwGetPage);
3015	pVM->pgm.s.pfnR3ShwModifyPage = pModeData->pfnR3ShwModifyPage;
3016
3017	pVM->pgm.s.pfnRCShwGetPage = pModeData->pfnRCShwGetPage;
3018	pVM->pgm.s.pfnRCShwModifyPage = pModeData->pfnRCShwModifyPage;
3019
3020	pVM->pgm.s.pfnR0ShwGetPage = pModeData->pfnR0ShwGetPage;
3021	pVM->pgm.s.pfnR0ShwModifyPage = pModeData->pfnR0ShwModifyPage;
3022
3023
3024	/* guest */
3025	pVM->pgm.s.pfnR3GstRelocate = pModeData->pfnR3GstRelocate;
3026	pVM->pgm.s.pfnR3GstExit = pModeData->pfnR3GstExit;
3027	pVM->pgm.s.pfnR3GstGetPage = pModeData->pfnR3GstGetPage;
3028	Assert(pVM->pgm.s.pfnR3GstGetPage);
3029	pVM->pgm.s.pfnR3GstModifyPage = pModeData->pfnR3GstModifyPage;
3030	pVM->pgm.s.pfnR3GstGetPDE = pModeData->pfnR3GstGetPDE;
3031	#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
3032	pVM->pgm.s.pfnR3GstMonitorCR3 = pModeData->pfnR3GstMonitorCR3;
3033	pVM->pgm.s.pfnR3GstUnmonitorCR3 = pModeData->pfnR3GstUnmonitorCR3;
3034	#endif
3035	pVM->pgm.s.pfnR3GstMapCR3 = pModeData->pfnR3GstMapCR3;
3036	pVM->pgm.s.pfnR3GstUnmapCR3 = pModeData->pfnR3GstUnmapCR3;
3037	#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
3038	pVM->pgm.s.pfnR3GstWriteHandlerCR3 = pModeData->pfnR3GstWriteHandlerCR3;
3039	pVM->pgm.s.pszR3GstWriteHandlerCR3 = pModeData->pszR3GstWriteHandlerCR3;
3040	pVM->pgm.s.pfnR3GstPAEWriteHandlerCR3 = pModeData->pfnR3GstPAEWriteHandlerCR3;
3041	pVM->pgm.s.pszR3GstPAEWriteHandlerCR3 = pModeData->pszR3GstPAEWriteHandlerCR3;
3042	#endif
3043	pVM->pgm.s.pfnRCGstGetPage = pModeData->pfnRCGstGetPage;
3044	pVM->pgm.s.pfnRCGstModifyPage = pModeData->pfnRCGstModifyPage;
3045	pVM->pgm.s.pfnRCGstGetPDE = pModeData->pfnRCGstGetPDE;
3046	#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
3047	pVM->pgm.s.pfnRCGstMonitorCR3 = pModeData->pfnRCGstMonitorCR3;
3048	pVM->pgm.s.pfnRCGstUnmonitorCR3 = pModeData->pfnRCGstUnmonitorCR3;
3049	#endif
3050	pVM->pgm.s.pfnRCGstMapCR3 = pModeData->pfnRCGstMapCR3;
3051	pVM->pgm.s.pfnRCGstUnmapCR3 = pModeData->pfnRCGstUnmapCR3;
3052	#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
3053	pVM->pgm.s.pfnRCGstWriteHandlerCR3 = pModeData->pfnRCGstWriteHandlerCR3;
3054	pVM->pgm.s.pfnRCGstPAEWriteHandlerCR3 = pModeData->pfnRCGstPAEWriteHandlerCR3;
3055	#endif
3056	pVM->pgm.s.pfnR0GstGetPage = pModeData->pfnR0GstGetPage;
3057	pVM->pgm.s.pfnR0GstModifyPage = pModeData->pfnR0GstModifyPage;
3058	pVM->pgm.s.pfnR0GstGetPDE = pModeData->pfnR0GstGetPDE;
3059	#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
3060	pVM->pgm.s.pfnR0GstMonitorCR3 = pModeData->pfnR0GstMonitorCR3;
3061	pVM->pgm.s.pfnR0GstUnmonitorCR3 = pModeData->pfnR0GstUnmonitorCR3;
3062	#endif
3063	pVM->pgm.s.pfnR0GstMapCR3 = pModeData->pfnR0GstMapCR3;
3064	pVM->pgm.s.pfnR0GstUnmapCR3 = pModeData->pfnR0GstUnmapCR3;
3065	#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
3066	pVM->pgm.s.pfnR0GstWriteHandlerCR3 = pModeData->pfnR0GstWriteHandlerCR3;
3067	pVM->pgm.s.pfnR0GstPAEWriteHandlerCR3 = pModeData->pfnR0GstPAEWriteHandlerCR3;
3068	#endif
3069
3070	/* both */
3071	pVM->pgm.s.pfnR3BthRelocate = pModeData->pfnR3BthRelocate;
3072	pVM->pgm.s.pfnR3BthInvalidatePage = pModeData->pfnR3BthInvalidatePage;
3073	pVM->pgm.s.pfnR3BthSyncCR3 = pModeData->pfnR3BthSyncCR3;
3074	Assert(pVM->pgm.s.pfnR3BthSyncCR3);
3075	pVM->pgm.s.pfnR3BthSyncPage = pModeData->pfnR3BthSyncPage;
3076	pVM->pgm.s.pfnR3BthPrefetchPage = pModeData->pfnR3BthPrefetchPage;
3077	pVM->pgm.s.pfnR3BthVerifyAccessSyncPage = pModeData->pfnR3BthVerifyAccessSyncPage;
3078	#ifdef VBOX_STRICT
3079	pVM->pgm.s.pfnR3BthAssertCR3 = pModeData->pfnR3BthAssertCR3;
3080	#endif
3081
3082	pVM->pgm.s.pfnRCBthTrap0eHandler = pModeData->pfnRCBthTrap0eHandler;
3083	pVM->pgm.s.pfnRCBthInvalidatePage = pModeData->pfnRCBthInvalidatePage;
3084	pVM->pgm.s.pfnRCBthSyncCR3 = pModeData->pfnRCBthSyncCR3;
3085	pVM->pgm.s.pfnRCBthSyncPage = pModeData->pfnRCBthSyncPage;
3086	pVM->pgm.s.pfnRCBthPrefetchPage = pModeData->pfnRCBthPrefetchPage;
3087	pVM->pgm.s.pfnRCBthVerifyAccessSyncPage = pModeData->pfnRCBthVerifyAccessSyncPage;
3088	#ifdef VBOX_STRICT
3089	pVM->pgm.s.pfnRCBthAssertCR3 = pModeData->pfnRCBthAssertCR3;
3090	#endif
3091
3092	pVM->pgm.s.pfnR0BthTrap0eHandler = pModeData->pfnR0BthTrap0eHandler;
3093	pVM->pgm.s.pfnR0BthInvalidatePage = pModeData->pfnR0BthInvalidatePage;
3094	pVM->pgm.s.pfnR0BthSyncCR3 = pModeData->pfnR0BthSyncCR3;
3095	pVM->pgm.s.pfnR0BthSyncPage = pModeData->pfnR0BthSyncPage;
3096	pVM->pgm.s.pfnR0BthPrefetchPage = pModeData->pfnR0BthPrefetchPage;
3097	pVM->pgm.s.pfnR0BthVerifyAccessSyncPage = pModeData->pfnR0BthVerifyAccessSyncPage;
3098	#ifdef VBOX_STRICT
3099	pVM->pgm.s.pfnR0BthAssertCR3 = pModeData->pfnR0BthAssertCR3;
3100	#endif
3101	}
3102
3103
3104	/**
3105	* Calculates the shadow paging mode.
3106	*
3107	* @returns The shadow paging mode.
3108	* @param pVM VM handle.
3109	* @param enmGuestMode The guest mode.
3110	* @param enmHostMode The host mode.
3111	* @param enmShadowMode The current shadow mode.
3112	* @param penmSwitcher Where to store the switcher to use.
3113	* VMMSWITCHER_INVALID means no change.
3114	*/
3115	static PGMMODE pgmR3CalcShadowMode(PVM pVM, PGMMODE enmGuestMode, SUPPAGINGMODE enmHostMode, PGMMODE enmShadowMode, VMMSWITCHER *penmSwitcher)
3116	{
3117	VMMSWITCHER enmSwitcher = VMMSWITCHER_INVALID;
3118	switch (enmGuestMode)
3119	{
3120	/*
3121	* When switching to real or protected mode we don't change
3122	* anything since it's likely that we'll switch back pretty soon.
3123	*
3124	* During pgmR3InitPaging we'll end up here with PGMMODE_INVALID
3125	* and is supposed to determine which shadow paging and switcher to
3126	* use during init.
3127	*/
3128	case PGMMODE_REAL:
3129	case PGMMODE_PROTECTED:
3130	if ( enmShadowMode != PGMMODE_INVALID
3131	&& !HWACCMIsEnabled(pVM) /* always switch in hwaccm mode! */)
3132	break; /* (no change) */
3133
3134	switch (enmHostMode)
3135	{
3136	case SUPPAGINGMODE_32_BIT:
3137	case SUPPAGINGMODE_32_BIT_GLOBAL:
3138	enmShadowMode = PGMMODE_32_BIT;
3139	enmSwitcher = VMMSWITCHER_32_TO_32;
3140	break;
3141
3142	case SUPPAGINGMODE_PAE:
3143	case SUPPAGINGMODE_PAE_NX:
3144	case SUPPAGINGMODE_PAE_GLOBAL:
3145	case SUPPAGINGMODE_PAE_GLOBAL_NX:
3146	enmShadowMode = PGMMODE_PAE;
3147	enmSwitcher = VMMSWITCHER_PAE_TO_PAE;
3148	#ifdef DEBUG_bird
3149	if (RTEnvExist("VBOX_32BIT"))
3150	{
3151	enmShadowMode = PGMMODE_32_BIT;
3152	enmSwitcher = VMMSWITCHER_PAE_TO_32;
3153	}
3154	#endif
3155	break;
3156
3157	case SUPPAGINGMODE_AMD64:
3158	case SUPPAGINGMODE_AMD64_GLOBAL:
3159	case SUPPAGINGMODE_AMD64_NX:
3160	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
3161	enmShadowMode = PGMMODE_PAE;
3162	enmSwitcher = VMMSWITCHER_AMD64_TO_PAE;
3163	#ifdef DEBUG_bird
3164	if (RTEnvExist("VBOX_32BIT"))
3165	{
3166	enmShadowMode = PGMMODE_32_BIT;
3167	enmSwitcher = VMMSWITCHER_AMD64_TO_32;
3168	}
3169	#endif
3170	break;
3171
3172	default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
3173	}
3174	break;
3175
3176	case PGMMODE_32_BIT:
3177	switch (enmHostMode)
3178	{
3179	case SUPPAGINGMODE_32_BIT:
3180	case SUPPAGINGMODE_32_BIT_GLOBAL:
3181	enmShadowMode = PGMMODE_32_BIT;
3182	enmSwitcher = VMMSWITCHER_32_TO_32;
3183	break;
3184
3185	case SUPPAGINGMODE_PAE:
3186	case SUPPAGINGMODE_PAE_NX:
3187	case SUPPAGINGMODE_PAE_GLOBAL:
3188	case SUPPAGINGMODE_PAE_GLOBAL_NX:
3189	enmShadowMode = PGMMODE_PAE;
3190	enmSwitcher = VMMSWITCHER_PAE_TO_PAE;
3191	#ifdef DEBUG_bird
3192	if (RTEnvExist("VBOX_32BIT"))
3193	{
3194	enmShadowMode = PGMMODE_32_BIT;
3195	enmSwitcher = VMMSWITCHER_PAE_TO_32;
3196	}
3197	#endif
3198	break;
3199
3200	case SUPPAGINGMODE_AMD64:
3201	case SUPPAGINGMODE_AMD64_GLOBAL:
3202	case SUPPAGINGMODE_AMD64_NX:
3203	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
3204	enmShadowMode = PGMMODE_PAE;
3205	enmSwitcher = VMMSWITCHER_AMD64_TO_PAE;
3206	#ifdef DEBUG_bird
3207	if (RTEnvExist("VBOX_32BIT"))
3208	{
3209	enmShadowMode = PGMMODE_32_BIT;
3210	enmSwitcher = VMMSWITCHER_AMD64_TO_32;
3211	}
3212	#endif
3213	break;
3214
3215	default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
3216	}
3217	break;
3218
3219	case PGMMODE_PAE:
3220	case PGMMODE_PAE_NX: /** @todo This might require more switchers and guest+both modes. */
3221	switch (enmHostMode)
3222	{
3223	case SUPPAGINGMODE_32_BIT:
3224	case SUPPAGINGMODE_32_BIT_GLOBAL:
3225	enmShadowMode = PGMMODE_PAE;
3226	enmSwitcher = VMMSWITCHER_32_TO_PAE;
3227	break;
3228
3229	case SUPPAGINGMODE_PAE:
3230	case SUPPAGINGMODE_PAE_NX:
3231	case SUPPAGINGMODE_PAE_GLOBAL:
3232	case SUPPAGINGMODE_PAE_GLOBAL_NX:
3233	enmShadowMode = PGMMODE_PAE;
3234	enmSwitcher = VMMSWITCHER_PAE_TO_PAE;
3235	break;
3236
3237	case SUPPAGINGMODE_AMD64:
3238	case SUPPAGINGMODE_AMD64_GLOBAL:
3239	case SUPPAGINGMODE_AMD64_NX:
3240	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
3241	enmShadowMode = PGMMODE_PAE;
3242	enmSwitcher = VMMSWITCHER_AMD64_TO_PAE;
3243	break;
3244
3245	default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
3246	}
3247	break;
3248
3249	case PGMMODE_AMD64:
3250	case PGMMODE_AMD64_NX:
3251	switch (enmHostMode)
3252	{
3253	case SUPPAGINGMODE_32_BIT:
3254	case SUPPAGINGMODE_32_BIT_GLOBAL:
3255	enmShadowMode = PGMMODE_AMD64;
3256	enmSwitcher = VMMSWITCHER_32_TO_AMD64;
3257	break;
3258
3259	case SUPPAGINGMODE_PAE:
3260	case SUPPAGINGMODE_PAE_NX:
3261	case SUPPAGINGMODE_PAE_GLOBAL:
3262	case SUPPAGINGMODE_PAE_GLOBAL_NX:
3263	enmShadowMode = PGMMODE_AMD64;
3264	enmSwitcher = VMMSWITCHER_PAE_TO_AMD64;
3265	break;
3266
3267	case SUPPAGINGMODE_AMD64:
3268	case SUPPAGINGMODE_AMD64_GLOBAL:
3269	case SUPPAGINGMODE_AMD64_NX:
3270	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
3271	enmShadowMode = PGMMODE_AMD64;
3272	enmSwitcher = VMMSWITCHER_AMD64_TO_AMD64;
3273	break;
3274
3275	default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
3276	}
3277	break;
3278
3279
3280	default:
3281	AssertReleaseMsgFailed(("enmGuestMode=%d\n", enmGuestMode));
3282	return PGMMODE_INVALID;
3283	}
3284	/* Override the shadow mode is nested paging is active. */
3285	if (HWACCMIsNestedPagingActive(pVM))
3286	enmShadowMode = HWACCMGetShwPagingMode(pVM);
3287
3288	*penmSwitcher = enmSwitcher;
3289	return enmShadowMode;
3290	}
3291
3292
3293	/**
3294	* Performs the actual mode change.
3295	* This is called by PGMChangeMode and pgmR3InitPaging().
3296	*
3297	* @returns VBox status code.
3298	* @param pVM VM handle.
3299	* @param enmGuestMode The new guest mode. This is assumed to be different from
3300	* the current mode.
3301	*/
3302	VMMR3DECL(int) PGMR3ChangeMode(PVM pVM, PGMMODE enmGuestMode)
3303	{
3304	Log(("PGMR3ChangeMode: Guest mode: %s -> %s\n", PGMGetModeName(pVM->pgm.s.enmGuestMode), PGMGetModeName(enmGuestMode)));
3305	STAM_REL_COUNTER_INC(&pVM->pgm.s.cGuestModeChanges);
3306
3307	/*
3308	* Calc the shadow mode and switcher.
3309	*/
3310	VMMSWITCHER enmSwitcher;
3311	PGMMODE enmShadowMode = pgmR3CalcShadowMode(pVM, enmGuestMode, pVM->pgm.s.enmHostMode, pVM->pgm.s.enmShadowMode, &enmSwitcher);
3312	if (enmSwitcher != VMMSWITCHER_INVALID)
3313	{
3314	/*
3315	* Select new switcher.
3316	*/
3317	int rc = VMMR3SelectSwitcher(pVM, enmSwitcher);
3318	if (RT_FAILURE(rc))
3319	{
3320	AssertReleaseMsgFailed(("VMMR3SelectSwitcher(%d) -> %Rrc\n", enmSwitcher, rc));
3321	return rc;
3322	}
3323	}
3324
3325	/*
3326	* Exit old mode(s).
3327	*/
3328	/* shadow */
3329	if (enmShadowMode != pVM->pgm.s.enmShadowMode)
3330	{
3331	LogFlow(("PGMR3ChangeMode: Shadow mode: %s -> %s\n", PGMGetModeName(pVM->pgm.s.enmShadowMode), PGMGetModeName(enmShadowMode)));
3332	if (PGM_SHW_PFN(Exit, pVM))
3333	{
3334	int rc = PGM_SHW_PFN(Exit, pVM)(pVM);
3335	if (RT_FAILURE(rc))
3336	{
3337	AssertMsgFailed(("Exit failed for shadow mode %d: %Rrc\n", pVM->pgm.s.enmShadowMode, rc));
3338	return rc;
3339	}
3340	}
3341
3342	}
3343	else
3344	LogFlow(("PGMR3ChangeMode: Shadow mode remains: %s\n", PGMGetModeName(pVM->pgm.s.enmShadowMode)));
3345
3346	/* guest */
3347	if (PGM_GST_PFN(Exit, pVM))
3348	{
3349	int rc = PGM_GST_PFN(Exit, pVM)(pVM);
3350	if (RT_FAILURE(rc))
3351	{
3352	AssertMsgFailed(("Exit failed for guest mode %d: %Rrc\n", pVM->pgm.s.enmGuestMode, rc));
3353	return rc;
3354	}
3355	}
3356
3357	/*
3358	* Load new paging mode data.
3359	*/
3360	pgmR3ModeDataSwitch(pVM, enmShadowMode, enmGuestMode);
3361
3362	/*
3363	* Enter new shadow mode (if changed).
3364	*/
3365	if (enmShadowMode != pVM->pgm.s.enmShadowMode)
3366	{
3367	int rc;
3368	pVM->pgm.s.enmShadowMode = enmShadowMode;
3369	switch (enmShadowMode)
3370	{
3371	case PGMMODE_32_BIT:
3372	rc = PGM_SHW_NAME_32BIT(Enter)(pVM);
3373	break;
3374	case PGMMODE_PAE:
3375	case PGMMODE_PAE_NX:
3376	rc = PGM_SHW_NAME_PAE(Enter)(pVM);
3377	break;
3378	case PGMMODE_AMD64:
3379	case PGMMODE_AMD64_NX:
3380	rc = PGM_SHW_NAME_AMD64(Enter)(pVM);
3381	break;
3382	case PGMMODE_NESTED:
3383	rc = PGM_SHW_NAME_NESTED(Enter)(pVM);
3384	break;
3385	case PGMMODE_EPT:
3386	rc = PGM_SHW_NAME_EPT(Enter)(pVM);
3387	break;
3388	case PGMMODE_REAL:
3389	case PGMMODE_PROTECTED:
3390	default:
3391	AssertReleaseMsgFailed(("enmShadowMode=%d\n", enmShadowMode));
3392	return VERR_INTERNAL_ERROR;
3393	}
3394	if (RT_FAILURE(rc))
3395	{
3396	AssertReleaseMsgFailed(("Entering enmShadowMode=%d failed: %Rrc\n", enmShadowMode, rc));
3397	pVM->pgm.s.enmShadowMode = PGMMODE_INVALID;
3398	return rc;
3399	}
3400	}
3401
3402	/** @todo This is a bug!
3403	*
3404	* We must flush the PGM pool cache if the guest mode changes; we don't always
3405	* switch shadow paging mode (e.g. protected->32-bit) and shouldn't reuse
3406	* the shadow page tables.
3407	*
3408	* That only applies when switching between paging and non-paging modes.
3409	*/
3410	/** @todo A20 setting */
3411	if ( pVM->pgm.s.CTX_SUFF(pPool)
3412	&& !HWACCMIsNestedPagingActive(pVM)
3413	&& PGMMODE_WITH_PAGING(pVM->pgm.s.enmGuestMode) != PGMMODE_WITH_PAGING(enmGuestMode))
3414	{
3415	Log(("PGMR3ChangeMode: changing guest paging mode -> flush pgm pool cache!\n"));
3416	pgmPoolFlushAll(pVM);
3417	}
3418
3419	/*
3420	* Enter the new guest and shadow+guest modes.
3421	*/
3422	int rc = -1;
3423	int rc2 = -1;
3424	RTGCPHYS GCPhysCR3 = NIL_RTGCPHYS;
3425	pVM->pgm.s.enmGuestMode = enmGuestMode;
3426	switch (enmGuestMode)
3427	{
3428	case PGMMODE_REAL:
3429	rc = PGM_GST_NAME_REAL(Enter)(pVM, NIL_RTGCPHYS);
3430	switch (pVM->pgm.s.enmShadowMode)
3431	{
3432	case PGMMODE_32_BIT:
3433	rc2 = PGM_BTH_NAME_32BIT_REAL(Enter)(pVM, NIL_RTGCPHYS);
3434	break;
3435	case PGMMODE_PAE:
3436	case PGMMODE_PAE_NX:
3437	rc2 = PGM_BTH_NAME_PAE_REAL(Enter)(pVM, NIL_RTGCPHYS);
3438	break;
3439	case PGMMODE_NESTED:
3440	rc2 = PGM_BTH_NAME_NESTED_REAL(Enter)(pVM, NIL_RTGCPHYS);
3441	break;
3442	case PGMMODE_EPT:
3443	rc2 = PGM_BTH_NAME_EPT_REAL(Enter)(pVM, NIL_RTGCPHYS);
3444	break;
3445	case PGMMODE_AMD64:
3446	case PGMMODE_AMD64_NX:
3447	AssertMsgFailed(("Should use PAE shadow mode!\n"));
3448	default: AssertFailed(); break;
3449	}
3450	break;
3451
3452	case PGMMODE_PROTECTED:
3453	rc = PGM_GST_NAME_PROT(Enter)(pVM, NIL_RTGCPHYS);
3454	switch (pVM->pgm.s.enmShadowMode)
3455	{
3456	case PGMMODE_32_BIT:
3457	rc2 = PGM_BTH_NAME_32BIT_PROT(Enter)(pVM, NIL_RTGCPHYS);
3458	break;
3459	case PGMMODE_PAE:
3460	case PGMMODE_PAE_NX:
3461	rc2 = PGM_BTH_NAME_PAE_PROT(Enter)(pVM, NIL_RTGCPHYS);
3462	break;
3463	case PGMMODE_NESTED:
3464	rc2 = PGM_BTH_NAME_NESTED_PROT(Enter)(pVM, NIL_RTGCPHYS);
3465	break;
3466	case PGMMODE_EPT:
3467	rc2 = PGM_BTH_NAME_EPT_PROT(Enter)(pVM, NIL_RTGCPHYS);
3468	break;
3469	case PGMMODE_AMD64:
3470	case PGMMODE_AMD64_NX:
3471	AssertMsgFailed(("Should use PAE shadow mode!\n"));
3472	default: AssertFailed(); break;
3473	}
3474	break;
3475
3476	case PGMMODE_32_BIT:
3477	GCPhysCR3 = CPUMGetGuestCR3(pVM) & X86_CR3_PAGE_MASK;
3478	rc = PGM_GST_NAME_32BIT(Enter)(pVM, GCPhysCR3);
3479	switch (pVM->pgm.s.enmShadowMode)
3480	{
3481	case PGMMODE_32_BIT:
3482	rc2 = PGM_BTH_NAME_32BIT_32BIT(Enter)(pVM, GCPhysCR3);
3483	break;
3484	case PGMMODE_PAE:
3485	case PGMMODE_PAE_NX:
3486	rc2 = PGM_BTH_NAME_PAE_32BIT(Enter)(pVM, GCPhysCR3);
3487	break;
3488	case PGMMODE_NESTED:
3489	rc2 = PGM_BTH_NAME_NESTED_32BIT(Enter)(pVM, GCPhysCR3);
3490	break;
3491	case PGMMODE_EPT:
3492	rc2 = PGM_BTH_NAME_EPT_32BIT(Enter)(pVM, GCPhysCR3);
3493	break;
3494	case PGMMODE_AMD64:
3495	case PGMMODE_AMD64_NX:
3496	AssertMsgFailed(("Should use PAE shadow mode!\n"));
3497	default: AssertFailed(); break;
3498	}
3499	break;
3500
3501	case PGMMODE_PAE_NX:
3502	case PGMMODE_PAE:
3503	{
3504	uint32_t u32Dummy, u32Features;
3505
3506	CPUMGetGuestCpuId(pVM, 1, &u32Dummy, &u32Dummy, &u32Dummy, &u32Features);
3507	if (!(u32Features & X86_CPUID_FEATURE_EDX_PAE))
3508	{
3509	/* Pause first, then inform Main. */
3510	rc = VMR3SuspendNoSave(pVM);
3511	AssertRC(rc);
3512
3513	VMSetRuntimeError(pVM, true, "PAEmode",
3514	N_("The guest is trying to switch to the PAE mode which is currently disabled by default in VirtualBox. PAE support can be enabled using the VM settings (General/Advanced)"));
3515	/* we must return VINF_SUCCESS here otherwise the recompiler will assert */
3516	return VINF_SUCCESS;
3517	}
3518	GCPhysCR3 = CPUMGetGuestCR3(pVM) & X86_CR3_PAE_PAGE_MASK;
3519	rc = PGM_GST_NAME_PAE(Enter)(pVM, GCPhysCR3);
3520	switch (pVM->pgm.s.enmShadowMode)
3521	{
3522	case PGMMODE_PAE:
3523	case PGMMODE_PAE_NX:
3524	rc2 = PGM_BTH_NAME_PAE_PAE(Enter)(pVM, GCPhysCR3);
3525	break;
3526	case PGMMODE_NESTED:
3527	rc2 = PGM_BTH_NAME_NESTED_PAE(Enter)(pVM, GCPhysCR3);
3528	break;
3529	case PGMMODE_EPT:
3530	rc2 = PGM_BTH_NAME_EPT_PAE(Enter)(pVM, GCPhysCR3);
3531	break;
3532	case PGMMODE_32_BIT:
3533	case PGMMODE_AMD64:
3534	case PGMMODE_AMD64_NX:
3535	AssertMsgFailed(("Should use PAE shadow mode!\n"));
3536	default: AssertFailed(); break;
3537	}
3538	break;
3539	}
3540
3541	#ifdef VBOX_WITH_64_BITS_GUESTS
3542	case PGMMODE_AMD64_NX:
3543	case PGMMODE_AMD64:
3544	GCPhysCR3 = CPUMGetGuestCR3(pVM) & UINT64_C(0xfffffffffffff000); /** @todo define this mask! */
3545	rc = PGM_GST_NAME_AMD64(Enter)(pVM, GCPhysCR3);
3546	switch (pVM->pgm.s.enmShadowMode)
3547	{
3548	case PGMMODE_AMD64:
3549	case PGMMODE_AMD64_NX:
3550	rc2 = PGM_BTH_NAME_AMD64_AMD64(Enter)(pVM, GCPhysCR3);
3551	break;
3552	case PGMMODE_NESTED:
3553	rc2 = PGM_BTH_NAME_NESTED_AMD64(Enter)(pVM, GCPhysCR3);
3554	break;
3555	case PGMMODE_EPT:
3556	rc2 = PGM_BTH_NAME_EPT_AMD64(Enter)(pVM, GCPhysCR3);
3557	break;
3558	case PGMMODE_32_BIT:
3559	case PGMMODE_PAE:
3560	case PGMMODE_PAE_NX:
3561	AssertMsgFailed(("Should use AMD64 shadow mode!\n"));
3562	default: AssertFailed(); break;
3563	}
3564	break;
3565	#endif
3566
3567	default:
3568	AssertReleaseMsgFailed(("enmGuestMode=%d\n", enmGuestMode));
3569	rc = VERR_NOT_IMPLEMENTED;
3570	break;
3571	}
3572
3573	/* status codes. */
3574	AssertRC(rc);
3575	AssertRC(rc2);
3576	if (RT_SUCCESS(rc))
3577	{
3578	rc = rc2;
3579	if (RT_SUCCESS(rc)) /* no informational status codes. */
3580	rc = VINF_SUCCESS;
3581	}
3582
3583	/*
3584	* Notify SELM so it can update the TSSes with correct CR3s.
3585	*/
3586	SELMR3PagingModeChanged(pVM);
3587
3588	/* Notify HWACCM as well. */
3589	HWACCMR3PagingModeChanged(pVM, pVM->pgm.s.enmShadowMode, pVM->pgm.s.enmGuestMode);
3590	return rc;
3591	}
3592
3593
3594	/**
3595	* Dumps a PAE shadow page table.
3596	*
3597	* @returns VBox status code (VINF_SUCCESS).
3598	* @param pVM The VM handle.
3599	* @param pPT Pointer to the page table.
3600	* @param u64Address The virtual address of the page table starts.
3601	* @param fLongMode Set if this a long mode table; clear if it's a legacy mode table.
3602	* @param cMaxDepth The maxium depth.
3603	* @param pHlp Pointer to the output functions.
3604	*/
3605	static int pgmR3DumpHierarchyHCPaePT(PVM pVM, PX86PTPAE pPT, uint64_t u64Address, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
3606	{
3607	for (unsigned i = 0; i < RT_ELEMENTS(pPT->a); i++)
3608	{
3609	X86PTEPAE Pte = pPT->a[i];
3610	if (Pte.n.u1Present)
3611	{
3612	pHlp->pfnPrintf(pHlp,
3613	fLongMode /P R S A D G WT CD AT NX 4M a p ? /
3614	? "%016llx 3 \| P %c %c %c %c %c %s %s %s %s 4K %c%c%c %016llx\n"
3615	: "%08llx 2 \| P %c %c %c %c %c %s %s %s %s 4K %c%c%c %016llx\n",
3616	u64Address + ((uint64_t)i << X86_PT_PAE_SHIFT),
3617	Pte.n.u1Write ? 'W' : 'R',
3618	Pte.n.u1User ? 'U' : 'S',
3619	Pte.n.u1Accessed ? 'A' : '-',
3620	Pte.n.u1Dirty ? 'D' : '-',
3621	Pte.n.u1Global ? 'G' : '-',
3622	Pte.n.u1WriteThru ? "WT" : "--",
3623	Pte.n.u1CacheDisable? "CD" : "--",
3624	Pte.n.u1PAT ? "AT" : "--",
3625	Pte.n.u1NoExecute ? "NX" : "--",
3626	Pte.u & PGM_PTFLAGS_TRACK_DIRTY ? 'd' : '-',
3627	Pte.u & RT_BIT(10) ? '1' : '0',
3628	Pte.u & PGM_PTFLAGS_CSAM_VALIDATED? 'v' : '-',
3629	Pte.u & X86_PTE_PAE_PG_MASK);
3630	}
3631	}
3632	return VINF_SUCCESS;
3633	}
3634
3635
3636	/**
3637	* Dumps a PAE shadow page directory table.
3638	*
3639	* @returns VBox status code (VINF_SUCCESS).
3640	* @param pVM The VM handle.
3641	* @param HCPhys The physical address of the page directory table.
3642	* @param u64Address The virtual address of the page table starts.
3643	* @param cr4 The CR4, PSE is currently used.
3644	* @param fLongMode Set if this a long mode table; clear if it's a legacy mode table.
3645	* @param cMaxDepth The maxium depth.
3646	* @param pHlp Pointer to the output functions.
3647	*/
3648	static int pgmR3DumpHierarchyHCPaePD(PVM pVM, RTHCPHYS HCPhys, uint64_t u64Address, uint32_t cr4, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
3649	{
3650	PX86PDPAE pPD = (PX86PDPAE)MMPagePhys2Page(pVM, HCPhys);
3651	if (!pPD)
3652	{
3653	pHlp->pfnPrintf(pHlp, "%0*llx error! Page directory at HCPhys=%RHp was not found in the page pool!\n",
3654	fLongMode ? 16 : 8, u64Address, HCPhys);
3655	return VERR_INVALID_PARAMETER;
3656	}
3657	const bool fBigPagesSupported = fLongMode \|\| !!(cr4 & X86_CR4_PSE);
3658
3659	int rc = VINF_SUCCESS;
3660	for (unsigned i = 0; i < RT_ELEMENTS(pPD->a); i++)
3661	{
3662	X86PDEPAE Pde = pPD->a[i];
3663	if (Pde.n.u1Present)
3664	{
3665	if (fBigPagesSupported && Pde.b.u1Size)
3666	pHlp->pfnPrintf(pHlp,
3667	fLongMode /P R S A D G WT CD AT NX 4M a p ? /
3668	? "%016llx 2 \| P %c %c %c %c %c %s %s %s %s 4M %c%c%c %016llx\n"
3669	: "%08llx 1 \| P %c %c %c %c %c %s %s %s %s 4M %c%c%c %016llx\n",
3670	u64Address + ((uint64_t)i << X86_PD_PAE_SHIFT),
3671	Pde.b.u1Write ? 'W' : 'R',
3672	Pde.b.u1User ? 'U' : 'S',
3673	Pde.b.u1Accessed ? 'A' : '-',
3674	Pde.b.u1Dirty ? 'D' : '-',
3675	Pde.b.u1Global ? 'G' : '-',
3676	Pde.b.u1WriteThru ? "WT" : "--",
3677	Pde.b.u1CacheDisable? "CD" : "--",
3678	Pde.b.u1PAT ? "AT" : "--",
3679	Pde.b.u1NoExecute ? "NX" : "--",
3680	Pde.u & RT_BIT_64(9) ? '1' : '0',
3681	Pde.u & PGM_PDFLAGS_MAPPING ? 'm' : '-',
3682	Pde.u & PGM_PDFLAGS_TRACK_DIRTY ? 'd' : '-',
3683	Pde.u & X86_PDE_PAE_PG_MASK);
3684	else
3685	{
3686	pHlp->pfnPrintf(pHlp,
3687	fLongMode /P R S A D G WT CD AT NX 4M a p ? /
3688	? "%016llx 2 \| P %c %c %c %c %c %s %s .. %s 4K %c%c%c %016llx\n"
3689	: "%08llx 1 \| P %c %c %c %c %c %s %s .. %s 4K %c%c%c %016llx\n",
3690	u64Address + ((uint64_t)i << X86_PD_PAE_SHIFT),
3691	Pde.n.u1Write ? 'W' : 'R',
3692	Pde.n.u1User ? 'U' : 'S',
3693	Pde.n.u1Accessed ? 'A' : '-',
3694	Pde.n.u1Reserved0 ? '?' : '.', /* ignored */
3695	Pde.n.u1Reserved1 ? '?' : '.', /* ignored */
3696	Pde.n.u1WriteThru ? "WT" : "--",
3697	Pde.n.u1CacheDisable? "CD" : "--",
3698	Pde.n.u1NoExecute ? "NX" : "--",
3699	Pde.u & RT_BIT_64(9) ? '1' : '0',
3700	Pde.u & PGM_PDFLAGS_MAPPING ? 'm' : '-',
3701	Pde.u & PGM_PDFLAGS_TRACK_DIRTY ? 'd' : '-',
3702	Pde.u & X86_PDE_PAE_PG_MASK);
3703	if (cMaxDepth >= 1)
3704	{
3705	/** @todo what about using the page pool for mapping PTs? */
3706	uint64_t u64AddressPT = u64Address + ((uint64_t)i << X86_PD_PAE_SHIFT);
3707	RTHCPHYS HCPhysPT = Pde.u & X86_PDE_PAE_PG_MASK;
3708	PX86PTPAE pPT = NULL;
3709	if (!(Pde.u & PGM_PDFLAGS_MAPPING))
3710	pPT = (PX86PTPAE)MMPagePhys2Page(pVM, HCPhysPT);
3711	else
3712	{
3713	for (PPGMMAPPING pMap = pVM->pgm.s.pMappingsR3; pMap; pMap = pMap->pNextR3)
3714	{
3715	uint64_t off = u64AddressPT - pMap->GCPtr;
3716	if (off < pMap->cb)
3717	{
3718	const int iPDE = (uint32_t)(off >> X86_PD_SHIFT);
3719	const int iSub = (int)((off >> X86_PD_PAE_SHIFT) & 1); /* MSC is a pain sometimes */
3720	if ((iSub ? pMap->aPTs[iPDE].HCPhysPaePT1 : pMap->aPTs[iPDE].HCPhysPaePT0) != HCPhysPT)
3721	pHlp->pfnPrintf(pHlp, "%0*llx error! Mapping error! PT %d has HCPhysPT=%RHp not %RHp is in the PD.\n",
3722	fLongMode ? 16 : 8, u64AddressPT, iPDE,
3723	iSub ? pMap->aPTs[iPDE].HCPhysPaePT1 : pMap->aPTs[iPDE].HCPhysPaePT0, HCPhysPT);
3724	pPT = &pMap->aPTs[iPDE].paPaePTsR3[iSub];
3725	}
3726	}
3727	}
3728	int rc2 = VERR_INVALID_PARAMETER;
3729	if (pPT)
3730	rc2 = pgmR3DumpHierarchyHCPaePT(pVM, pPT, u64AddressPT, fLongMode, cMaxDepth - 1, pHlp);
3731	else
3732	pHlp->pfnPrintf(pHlp, "%0*llx error! Page table at HCPhys=%RHp was not found in the page pool!\n",
3733	fLongMode ? 16 : 8, u64AddressPT, HCPhysPT);
3734	if (rc2 < rc && RT_SUCCESS(rc))
3735	rc = rc2;
3736	}
3737	}
3738	}
3739	}
3740	return rc;
3741	}
3742
3743
3744	/**
3745	* Dumps a PAE shadow page directory pointer table.
3746	*
3747	* @returns VBox status code (VINF_SUCCESS).
3748	* @param pVM The VM handle.
3749	* @param HCPhys The physical address of the page directory pointer table.
3750	* @param u64Address The virtual address of the page table starts.
3751	* @param cr4 The CR4, PSE is currently used.
3752	* @param fLongMode Set if this a long mode table; clear if it's a legacy mode table.
3753	* @param cMaxDepth The maxium depth.
3754	* @param pHlp Pointer to the output functions.
3755	*/
3756	static int pgmR3DumpHierarchyHCPaePDPT(PVM pVM, RTHCPHYS HCPhys, uint64_t u64Address, uint32_t cr4, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
3757	{
3758	PX86PDPT pPDPT = (PX86PDPT)MMPagePhys2Page(pVM, HCPhys);
3759	if (!pPDPT)
3760	{
3761	pHlp->pfnPrintf(pHlp, "%0*llx error! Page directory pointer table at HCPhys=%RHp was not found in the page pool!\n",
3762	fLongMode ? 16 : 8, u64Address, HCPhys);
3763	return VERR_INVALID_PARAMETER;
3764	}
3765
3766	int rc = VINF_SUCCESS;
3767	const unsigned c = fLongMode ? RT_ELEMENTS(pPDPT->a) : X86_PG_PAE_PDPE_ENTRIES;
3768	for (unsigned i = 0; i < c; i++)
3769	{
3770	X86PDPE Pdpe = pPDPT->a[i];
3771	if (Pdpe.n.u1Present)
3772	{
3773	if (fLongMode)
3774	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a p ? /
3775	"%016llx 1 \| P %c %c %c %c %c %s %s %s %s .. %c%c%c %016llx\n",
3776	u64Address + ((uint64_t)i << X86_PDPT_SHIFT),
3777	Pdpe.lm.u1Write ? 'W' : 'R',
3778	Pdpe.lm.u1User ? 'U' : 'S',
3779	Pdpe.lm.u1Accessed ? 'A' : '-',
3780	Pdpe.lm.u3Reserved & 1? '?' : '.', /* ignored */
3781	Pdpe.lm.u3Reserved & 4? '!' : '.', /* mbz */
3782	Pdpe.lm.u1WriteThru ? "WT" : "--",
3783	Pdpe.lm.u1CacheDisable? "CD" : "--",
3784	Pdpe.lm.u3Reserved & 2? "!" : "..",/* mbz */
3785	Pdpe.lm.u1NoExecute ? "NX" : "--",
3786	Pdpe.u & RT_BIT(9) ? '1' : '0',
3787	Pdpe.u & PGM_PLXFLAGS_PERMANENT ? 'p' : '-',
3788	Pdpe.u & RT_BIT(11) ? '1' : '0',
3789	Pdpe.u & X86_PDPE_PG_MASK);
3790	else
3791	pHlp->pfnPrintf(pHlp, /P G WT CD AT NX 4M a p ? /
3792	"%08x 0 \| P %c %s %s %s %s .. %c%c%c %016llx\n",
3793	i << X86_PDPT_SHIFT,
3794	Pdpe.n.u4Reserved & 1? '!' : '.', /* mbz */
3795	Pdpe.n.u4Reserved & 4? '!' : '.', /* mbz */
3796	Pdpe.n.u1WriteThru ? "WT" : "--",
3797	Pdpe.n.u1CacheDisable? "CD" : "--",
3798	Pdpe.n.u4Reserved & 2? "!" : "..",/* mbz */
3799	Pdpe.u & RT_BIT(9) ? '1' : '0',
3800	Pdpe.u & PGM_PLXFLAGS_PERMANENT ? 'p' : '-',
3801	Pdpe.u & RT_BIT(11) ? '1' : '0',
3802	Pdpe.u & X86_PDPE_PG_MASK);
3803	if (cMaxDepth >= 1)
3804	{
3805	int rc2 = pgmR3DumpHierarchyHCPaePD(pVM, Pdpe.u & X86_PDPE_PG_MASK, u64Address + ((uint64_t)i << X86_PDPT_SHIFT),
3806	cr4, fLongMode, cMaxDepth - 1, pHlp);
3807	if (rc2 < rc && RT_SUCCESS(rc))
3808	rc = rc2;
3809	}
3810	}
3811	}
3812	return rc;
3813	}
3814
3815
3816	/**
3817	* Dumps a 32-bit shadow page table.
3818	*
3819	* @returns VBox status code (VINF_SUCCESS).
3820	* @param pVM The VM handle.
3821	* @param HCPhys The physical address of the table.
3822	* @param cr4 The CR4, PSE is currently used.
3823	* @param cMaxDepth The maxium depth.
3824	* @param pHlp Pointer to the output functions.
3825	*/
3826	static int pgmR3DumpHierarchyHcPaePML4(PVM pVM, RTHCPHYS HCPhys, uint32_t cr4, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
3827	{
3828	PX86PML4 pPML4 = (PX86PML4)MMPagePhys2Page(pVM, HCPhys);
3829	if (!pPML4)
3830	{
3831	pHlp->pfnPrintf(pHlp, "Page map level 4 at HCPhys=%RHp was not found in the page pool!\n", HCPhys);
3832	return VERR_INVALID_PARAMETER;
3833	}
3834
3835	int rc = VINF_SUCCESS;
3836	for (unsigned i = 0; i < RT_ELEMENTS(pPML4->a); i++)
3837	{
3838	X86PML4E Pml4e = pPML4->a[i];
3839	if (Pml4e.n.u1Present)
3840	{
3841	uint64_t u64Address = ((uint64_t)i << X86_PML4_SHIFT) \| (((uint64_t)i >> (X86_PML4_SHIFT - X86_PDPT_SHIFT - 1)) * 0xffff000000000000ULL);
3842	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a p ? /
3843	"%016llx 0 \| P %c %c %c %c %c %s %s %s %s .. %c%c%c %016llx\n",
3844	u64Address,
3845	Pml4e.n.u1Write ? 'W' : 'R',
3846	Pml4e.n.u1User ? 'U' : 'S',
3847	Pml4e.n.u1Accessed ? 'A' : '-',
3848	Pml4e.n.u3Reserved & 1? '?' : '.', /* ignored */
3849	Pml4e.n.u3Reserved & 4? '!' : '.', /* mbz */
3850	Pml4e.n.u1WriteThru ? "WT" : "--",
3851	Pml4e.n.u1CacheDisable? "CD" : "--",
3852	Pml4e.n.u3Reserved & 2? "!" : "..",/* mbz */
3853	Pml4e.n.u1NoExecute ? "NX" : "--",
3854	Pml4e.u & RT_BIT(9) ? '1' : '0',
3855	Pml4e.u & PGM_PLXFLAGS_PERMANENT ? 'p' : '-',
3856	Pml4e.u & RT_BIT(11) ? '1' : '0',
3857	Pml4e.u & X86_PML4E_PG_MASK);
3858
3859	if (cMaxDepth >= 1)
3860	{
3861	int rc2 = pgmR3DumpHierarchyHCPaePDPT(pVM, Pml4e.u & X86_PML4E_PG_MASK, u64Address, cr4, true, cMaxDepth - 1, pHlp);
3862	if (rc2 < rc && RT_SUCCESS(rc))
3863	rc = rc2;
3864	}
3865	}
3866	}
3867	return rc;
3868	}
3869
3870
3871	/**
3872	* Dumps a 32-bit shadow page table.
3873	*
3874	* @returns VBox status code (VINF_SUCCESS).
3875	* @param pVM The VM handle.
3876	* @param pPT Pointer to the page table.
3877	* @param u32Address The virtual address this table starts at.
3878	* @param pHlp Pointer to the output functions.
3879	*/
3880	int pgmR3DumpHierarchyHC32BitPT(PVM pVM, PX86PT pPT, uint32_t u32Address, PCDBGFINFOHLP pHlp)
3881	{
3882	for (unsigned i = 0; i < RT_ELEMENTS(pPT->a); i++)
3883	{
3884	X86PTE Pte = pPT->a[i];
3885	if (Pte.n.u1Present)
3886	{
3887	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a m d /
3888	"%08x 1 \| P %c %c %c %c %c %s %s %s .. 4K %c%c%c %08x\n",
3889	u32Address + (i << X86_PT_SHIFT),
3890	Pte.n.u1Write ? 'W' : 'R',
3891	Pte.n.u1User ? 'U' : 'S',
3892	Pte.n.u1Accessed ? 'A' : '-',
3893	Pte.n.u1Dirty ? 'D' : '-',
3894	Pte.n.u1Global ? 'G' : '-',
3895	Pte.n.u1WriteThru ? "WT" : "--",
3896	Pte.n.u1CacheDisable? "CD" : "--",
3897	Pte.n.u1PAT ? "AT" : "--",
3898	Pte.u & PGM_PTFLAGS_TRACK_DIRTY ? 'd' : '-',
3899	Pte.u & RT_BIT(10) ? '1' : '0',
3900	Pte.u & PGM_PTFLAGS_CSAM_VALIDATED ? 'v' : '-',
3901	Pte.u & X86_PDE_PG_MASK);
3902	}
3903	}
3904	return VINF_SUCCESS;
3905	}
3906
3907
3908	/**
3909	* Dumps a 32-bit shadow page directory and page tables.
3910	*
3911	* @returns VBox status code (VINF_SUCCESS).
3912	* @param pVM The VM handle.
3913	* @param cr3 The root of the hierarchy.
3914	* @param cr4 The CR4, PSE is currently used.
3915	* @param cMaxDepth How deep into the hierarchy the dumper should go.
3916	* @param pHlp Pointer to the output functions.
3917	*/
3918	int pgmR3DumpHierarchyHC32BitPD(PVM pVM, uint32_t cr3, uint32_t cr4, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
3919	{
3920	PX86PD pPD = (PX86PD)MMPagePhys2Page(pVM, cr3 & X86_CR3_PAGE_MASK);
3921	if (!pPD)
3922	{
3923	pHlp->pfnPrintf(pHlp, "Page directory at %#x was not found in the page pool!\n", cr3 & X86_CR3_PAGE_MASK);
3924	return VERR_INVALID_PARAMETER;
3925	}
3926
3927	int rc = VINF_SUCCESS;
3928	for (unsigned i = 0; i < RT_ELEMENTS(pPD->a); i++)
3929	{
3930	X86PDE Pde = pPD->a[i];
3931	if (Pde.n.u1Present)
3932	{
3933	const uint32_t u32Address = i << X86_PD_SHIFT;
3934	if ((cr4 & X86_CR4_PSE) && Pde.b.u1Size)
3935	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a m d /
3936	"%08x 0 \| P %c %c %c %c %c %s %s %s .. 4M %c%c%c %08x\n",
3937	u32Address,
3938	Pde.b.u1Write ? 'W' : 'R',
3939	Pde.b.u1User ? 'U' : 'S',
3940	Pde.b.u1Accessed ? 'A' : '-',
3941	Pde.b.u1Dirty ? 'D' : '-',
3942	Pde.b.u1Global ? 'G' : '-',
3943	Pde.b.u1WriteThru ? "WT" : "--",
3944	Pde.b.u1CacheDisable? "CD" : "--",
3945	Pde.b.u1PAT ? "AT" : "--",
3946	Pde.u & RT_BIT_64(9) ? '1' : '0',
3947	Pde.u & PGM_PDFLAGS_MAPPING ? 'm' : '-',
3948	Pde.u & PGM_PDFLAGS_TRACK_DIRTY ? 'd' : '-',
3949	Pde.u & X86_PDE4M_PG_MASK);
3950	else
3951	{
3952	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a m d /
3953	"%08x 0 \| P %c %c %c %c %c %s %s .. .. 4K %c%c%c %08x\n",
3954	u32Address,
3955	Pde.n.u1Write ? 'W' : 'R',
3956	Pde.n.u1User ? 'U' : 'S',
3957	Pde.n.u1Accessed ? 'A' : '-',
3958	Pde.n.u1Reserved0 ? '?' : '.', /* ignored */
3959	Pde.n.u1Reserved1 ? '?' : '.', /* ignored */
3960	Pde.n.u1WriteThru ? "WT" : "--",
3961	Pde.n.u1CacheDisable? "CD" : "--",
3962	Pde.u & RT_BIT_64(9) ? '1' : '0',
3963	Pde.u & PGM_PDFLAGS_MAPPING ? 'm' : '-',
3964	Pde.u & PGM_PDFLAGS_TRACK_DIRTY ? 'd' : '-',
3965	Pde.u & X86_PDE_PG_MASK);
3966	if (cMaxDepth >= 1)
3967	{
3968	/** @todo what about using the page pool for mapping PTs? */
3969	RTHCPHYS HCPhys = Pde.u & X86_PDE_PG_MASK;
3970	PX86PT pPT = NULL;
3971	if (!(Pde.u & PGM_PDFLAGS_MAPPING))
3972	pPT = (PX86PT)MMPagePhys2Page(pVM, HCPhys);
3973	else
3974	{
3975	for (PPGMMAPPING pMap = pVM->pgm.s.pMappingsR3; pMap; pMap = pMap->pNextR3)
3976	if (u32Address - pMap->GCPtr < pMap->cb)
3977	{
3978	int iPDE = (u32Address - pMap->GCPtr) >> X86_PD_SHIFT;
3979	if (pMap->aPTs[iPDE].HCPhysPT != HCPhys)
3980	pHlp->pfnPrintf(pHlp, "%08x error! Mapping error! PT %d has HCPhysPT=%RHp not %RHp is in the PD.\n",
3981	u32Address, iPDE, pMap->aPTs[iPDE].HCPhysPT, HCPhys);
3982	pPT = pMap->aPTs[iPDE].pPTR3;
3983	}
3984	}
3985	int rc2 = VERR_INVALID_PARAMETER;
3986	if (pPT)
3987	rc2 = pgmR3DumpHierarchyHC32BitPT(pVM, pPT, u32Address, pHlp);
3988	else
3989	pHlp->pfnPrintf(pHlp, "%08x error! Page table at %#x was not found in the page pool!\n", u32Address, HCPhys);
3990	if (rc2 < rc && RT_SUCCESS(rc))
3991	rc = rc2;
3992	}
3993	}
3994	}
3995	}
3996
3997	return rc;
3998	}
3999
4000
4001	/**
4002	* Dumps a 32-bit shadow page table.
4003	*
4004	* @returns VBox status code (VINF_SUCCESS).
4005	* @param pVM The VM handle.
4006	* @param pPT Pointer to the page table.
4007	* @param u32Address The virtual address this table starts at.
4008	* @param PhysSearch Address to search for.
4009	*/
4010	int pgmR3DumpHierarchyGC32BitPT(PVM pVM, PX86PT pPT, uint32_t u32Address, RTGCPHYS PhysSearch)
4011	{
4012	for (unsigned i = 0; i < RT_ELEMENTS(pPT->a); i++)
4013	{
4014	X86PTE Pte = pPT->a[i];
4015	if (Pte.n.u1Present)
4016	{
4017	Log(( /P R S A D G WT CD AT NX 4M a m d /
4018	"%08x 1 \| P %c %c %c %c %c %s %s %s .. 4K %c%c%c %08x\n",
4019	u32Address + (i << X86_PT_SHIFT),
4020	Pte.n.u1Write ? 'W' : 'R',
4021	Pte.n.u1User ? 'U' : 'S',
4022	Pte.n.u1Accessed ? 'A' : '-',
4023	Pte.n.u1Dirty ? 'D' : '-',
4024	Pte.n.u1Global ? 'G' : '-',
4025	Pte.n.u1WriteThru ? "WT" : "--",
4026	Pte.n.u1CacheDisable? "CD" : "--",
4027	Pte.n.u1PAT ? "AT" : "--",
4028	Pte.u & PGM_PTFLAGS_TRACK_DIRTY ? 'd' : '-',
4029	Pte.u & RT_BIT(10) ? '1' : '0',
4030	Pte.u & PGM_PTFLAGS_CSAM_VALIDATED ? 'v' : '-',
4031	Pte.u & X86_PDE_PG_MASK));
4032
4033	if ((Pte.u & X86_PDE_PG_MASK) == PhysSearch)
4034	{
4035	uint64_t fPageShw = 0;
4036	RTHCPHYS pPhysHC = 0;
4037
4038	PGMShwGetPage(pVM, (RTGCPTR)(u32Address + (i << X86_PT_SHIFT)), &fPageShw, &pPhysHC);
4039	Log(("Found %RGp at %RGv -> flags=%llx\n", PhysSearch, (RTGCPTR)(u32Address + (i << X86_PT_SHIFT)), fPageShw));
4040	}
4041	}
4042	}
4043	return VINF_SUCCESS;
4044	}
4045
4046
4047	/**
4048	* Dumps a 32-bit guest page directory and page tables.
4049	*
4050	* @returns VBox status code (VINF_SUCCESS).
4051	* @param pVM The VM handle.
4052	* @param cr3 The root of the hierarchy.
4053	* @param cr4 The CR4, PSE is currently used.
4054	* @param PhysSearch Address to search for.
4055	*/
4056	VMMR3DECL(int) PGMR3DumpHierarchyGC(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCPHYS PhysSearch)
4057	{
4058	bool fLongMode = false;
4059	const unsigned cch = fLongMode ? 16 : 8; NOREF(cch);
4060	PX86PD pPD = 0;
4061
4062	int rc = PGM_GCPHYS_2_PTR(pVM, cr3 & X86_CR3_PAGE_MASK, &pPD);
4063	if (RT_FAILURE(rc) \|\| !pPD)
4064	{
4065	Log(("Page directory at %#x was not found in the page pool!\n", cr3 & X86_CR3_PAGE_MASK));
4066	return VERR_INVALID_PARAMETER;
4067	}
4068
4069	Log(("cr3=%08x cr4=%08x%s\n"
4070	"%-*s P - Present\n"
4071	"%-*s \| R/W - Read (0) / Write (1)\n"
4072	"%-*s \| \| U/S - User (1) / Supervisor (0)\n"
4073	"%-*s \| \| \| A - Accessed\n"
4074	"%-*s \| \| \| \| D - Dirty\n"
4075	"%-*s \| \| \| \| \| G - Global\n"
4076	"%-*s \| \| \| \| \| \| WT - Write thru\n"
4077	"%-*s \| \| \| \| \| \| \| CD - Cache disable\n"
4078	"%-*s \| \| \| \| \| \| \| \| AT - Attribute table (PAT)\n"
4079	"%-*s \| \| \| \| \| \| \| \| \| NX - No execute (K8)\n"
4080	"%-*s \| \| \| \| \| \| \| \| \| \| 4K/4M/2M - Page size.\n"
4081	"%-*s \| \| \| \| \| \| \| \| \| \| \| AVL - a=allocated; m=mapping; d=track dirty;\n"
4082	"%-*s \| \| \| \| \| \| \| \| \| \| \| \| p=permanent; v=validated;\n"
4083	"%-*s Level \| \| \| \| \| \| \| \| \| \| \| \| Page\n"
4084	/* xxxx n **** P R S A D G WT CD AT NX 4M AVL xxxxxxxxxxxxx
4085	- W U - - - -- -- -- -- -- 010 */
4086	, cr3, cr4, fLongMode ? " Long Mode" : "",
4087	cch, "", cch, "", cch, "", cch, "", cch, "", cch, "", cch, "",
4088	cch, "", cch, "", cch, "", cch, "", cch, "", cch, "", cch, "Address"));
4089
4090	for (unsigned i = 0; i < RT_ELEMENTS(pPD->a); i++)
4091	{
4092	X86PDE Pde = pPD->a[i];
4093	if (Pde.n.u1Present)
4094	{
4095	const uint32_t u32Address = i << X86_PD_SHIFT;
4096
4097	if ((cr4 & X86_CR4_PSE) && Pde.b.u1Size)
4098	Log(( /P R S A D G WT CD AT NX 4M a m d /
4099	"%08x 0 \| P %c %c %c %c %c %s %s %s .. 4M %c%c%c %08x\n",
4100	u32Address,
4101	Pde.b.u1Write ? 'W' : 'R',
4102	Pde.b.u1User ? 'U' : 'S',
4103	Pde.b.u1Accessed ? 'A' : '-',
4104	Pde.b.u1Dirty ? 'D' : '-',
4105	Pde.b.u1Global ? 'G' : '-',
4106	Pde.b.u1WriteThru ? "WT" : "--",
4107	Pde.b.u1CacheDisable? "CD" : "--",
4108	Pde.b.u1PAT ? "AT" : "--",
4109	Pde.u & RT_BIT(9) ? '1' : '0',
4110	Pde.u & RT_BIT(10) ? '1' : '0',
4111	Pde.u & RT_BIT(11) ? '1' : '0',
4112	pgmGstGet4MBPhysPage(&pVM->pgm.s, Pde)));
4113	/** @todo PhysSearch */
4114	else
4115	{
4116	Log(( /P R S A D G WT CD AT NX 4M a m d /
4117	"%08x 0 \| P %c %c %c %c %c %s %s .. .. 4K %c%c%c %08x\n",
4118	u32Address,
4119	Pde.n.u1Write ? 'W' : 'R',
4120	Pde.n.u1User ? 'U' : 'S',
4121	Pde.n.u1Accessed ? 'A' : '-',
4122	Pde.n.u1Reserved0 ? '?' : '.', /* ignored */
4123	Pde.n.u1Reserved1 ? '?' : '.', /* ignored */
4124	Pde.n.u1WriteThru ? "WT" : "--",
4125	Pde.n.u1CacheDisable? "CD" : "--",
4126	Pde.u & RT_BIT(9) ? '1' : '0',
4127	Pde.u & RT_BIT(10) ? '1' : '0',
4128	Pde.u & RT_BIT(11) ? '1' : '0',
4129	Pde.u & X86_PDE_PG_MASK));
4130	////if (cMaxDepth >= 1)
4131	{
4132	/** @todo what about using the page pool for mapping PTs? */
4133	RTGCPHYS GCPhys = Pde.u & X86_PDE_PG_MASK;
4134	PX86PT pPT = NULL;
4135
4136	rc = PGM_GCPHYS_2_PTR(pVM, GCPhys, &pPT);
4137
4138	int rc2 = VERR_INVALID_PARAMETER;
4139	if (pPT)
4140	rc2 = pgmR3DumpHierarchyGC32BitPT(pVM, pPT, u32Address, PhysSearch);
4141	else
4142	Log(("%08x error! Page table at %#x was not found in the page pool!\n", u32Address, GCPhys));
4143	if (rc2 < rc && RT_SUCCESS(rc))
4144	rc = rc2;
4145	}
4146	}
4147	}
4148	}
4149
4150	return rc;
4151	}
4152
4153
4154	/**
4155	* Dumps a page table hierarchy use only physical addresses and cr4/lm flags.
4156	*
4157	* @returns VBox status code (VINF_SUCCESS).
4158	* @param pVM The VM handle.
4159	* @param cr3 The root of the hierarchy.
4160	* @param cr4 The cr4, only PAE and PSE is currently used.
4161	* @param fLongMode Set if long mode, false if not long mode.
4162	* @param cMaxDepth Number of levels to dump.
4163	* @param pHlp Pointer to the output functions.
4164	*/
4165	VMMR3DECL(int) PGMR3DumpHierarchyHC(PVM pVM, uint64_t cr3, uint64_t cr4, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
4166	{
4167	if (!pHlp)
4168	pHlp = DBGFR3InfoLogHlp();
4169	if (!cMaxDepth)
4170	return VINF_SUCCESS;
4171	const unsigned cch = fLongMode ? 16 : 8;
4172	pHlp->pfnPrintf(pHlp,
4173	"cr3=%08x cr4=%08x%s\n"
4174	"%-*s P - Present\n"
4175	"%-*s \| R/W - Read (0) / Write (1)\n"
4176	"%-*s \| \| U/S - User (1) / Supervisor (0)\n"
4177	"%-*s \| \| \| A - Accessed\n"
4178	"%-*s \| \| \| \| D - Dirty\n"
4179	"%-*s \| \| \| \| \| G - Global\n"
4180	"%-*s \| \| \| \| \| \| WT - Write thru\n"
4181	"%-*s \| \| \| \| \| \| \| CD - Cache disable\n"
4182	"%-*s \| \| \| \| \| \| \| \| AT - Attribute table (PAT)\n"
4183	"%-*s \| \| \| \| \| \| \| \| \| NX - No execute (K8)\n"
4184	"%-*s \| \| \| \| \| \| \| \| \| \| 4K/4M/2M - Page size.\n"
4185	"%-*s \| \| \| \| \| \| \| \| \| \| \| AVL - a=allocated; m=mapping; d=track dirty;\n"
4186	"%-*s \| \| \| \| \| \| \| \| \| \| \| \| p=permanent; v=validated;\n"
4187	"%-*s Level \| \| \| \| \| \| \| \| \| \| \| \| Page\n"
4188	/* xxxx n **** P R S A D G WT CD AT NX 4M AVL xxxxxxxxxxxxx
4189	- W U - - - -- -- -- -- -- 010 */
4190	, cr3, cr4, fLongMode ? " Long Mode" : "",
4191	cch, "", cch, "", cch, "", cch, "", cch, "", cch, "", cch, "",
4192	cch, "", cch, "", cch, "", cch, "", cch, "", cch, "", cch, "Address");
4193	if (cr4 & X86_CR4_PAE)
4194	{
4195	if (fLongMode)
4196	return pgmR3DumpHierarchyHcPaePML4(pVM, cr3 & X86_CR3_PAGE_MASK, cr4, cMaxDepth, pHlp);
4197	return pgmR3DumpHierarchyHCPaePDPT(pVM, cr3 & X86_CR3_PAE_PAGE_MASK, 0, cr4, false, cMaxDepth, pHlp);
4198	}
4199	return pgmR3DumpHierarchyHC32BitPD(pVM, cr3 & X86_CR3_PAGE_MASK, cr4, cMaxDepth, pHlp);
4200	}
4201
4202	#ifdef VBOX_WITH_DEBUGGER
4203
4204	/**
4205	* The '.pgmram' command.
4206	*
4207	* @returns VBox status.
4208	* @param pCmd Pointer to the command descriptor (as registered).
4209	* @param pCmdHlp Pointer to command helper functions.
4210	* @param pVM Pointer to the current VM (if any).
4211	* @param paArgs Pointer to (readonly) array of arguments.
4212	* @param cArgs Number of arguments in the array.
4213	*/
4214	static DECLCALLBACK(int) pgmR3CmdRam(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4215	{
4216	/*
4217	* Validate input.
4218	*/
4219	if (!pVM)
4220	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4221	if (!pVM->pgm.s.pRamRangesRC)
4222	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Sorry, no Ram is registered.\n");
4223
4224	/*
4225	* Dump the ranges.
4226	*/
4227	int rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL, "From - To (incl) pvHC\n");
4228	PPGMRAMRANGE pRam;
4229	for (pRam = pVM->pgm.s.pRamRangesR3; pRam; pRam = pRam->pNextR3)
4230	{
4231	rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL,
4232	"%RGp - %RGp %p\n",
4233	pRam->GCPhys, pRam->GCPhysLast, pRam->pvR3);
4234	if (RT_FAILURE(rc))
4235	return rc;
4236	}
4237
4238	return VINF_SUCCESS;
4239	}
4240
4241
4242	/**
4243	* The '.pgmmap' command.
4244	*
4245	* @returns VBox status.
4246	* @param pCmd Pointer to the command descriptor (as registered).
4247	* @param pCmdHlp Pointer to command helper functions.
4248	* @param pVM Pointer to the current VM (if any).
4249	* @param paArgs Pointer to (readonly) array of arguments.
4250	* @param cArgs Number of arguments in the array.
4251	*/
4252	static DECLCALLBACK(int) pgmR3CmdMap(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4253	{
4254	/*
4255	* Validate input.
4256	*/
4257	if (!pVM)
4258	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4259	if (!pVM->pgm.s.pMappingsR3)
4260	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Sorry, no mappings are registered.\n");
4261
4262	/*
4263	* Print message about the fixedness of the mappings.
4264	*/
4265	int rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL, pVM->pgm.s.fMappingsFixed ? "The mappings are FIXED.\n" : "The mappings are FLOATING.\n");
4266	if (RT_FAILURE(rc))
4267	return rc;
4268
4269	/*
4270	* Dump the ranges.
4271	*/
4272	PPGMMAPPING pCur;
4273	for (pCur = pVM->pgm.s.pMappingsR3; pCur; pCur = pCur->pNextR3)
4274	{
4275	rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL,
4276	"%08x - %08x %s\n",
4277	pCur->GCPtr, pCur->GCPtrLast, pCur->pszDesc);
4278	if (RT_FAILURE(rc))
4279	return rc;
4280	}
4281
4282	return VINF_SUCCESS;
4283	}
4284
4285
4286	/**
4287	* The '.pgmsync' command.
4288	*
4289	* @returns VBox status.
4290	* @param pCmd Pointer to the command descriptor (as registered).
4291	* @param pCmdHlp Pointer to command helper functions.
4292	* @param pVM Pointer to the current VM (if any).
4293	* @param paArgs Pointer to (readonly) array of arguments.
4294	* @param cArgs Number of arguments in the array.
4295	*/
4296	static DECLCALLBACK(int) pgmR3CmdSync(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4297	{
4298	/*
4299	* Validate input.
4300	*/
4301	if (!pVM)
4302	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4303
4304	/*
4305	* Force page directory sync.
4306	*/
4307	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
4308
4309	int rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Forcing page directory sync.\n");
4310	if (RT_FAILURE(rc))
4311	return rc;
4312
4313	return VINF_SUCCESS;
4314	}
4315
4316
4317	#ifdef VBOX_STRICT
4318	/**
4319	* The '.pgmassertcr3' command.
4320	*
4321	* @returns VBox status.
4322	* @param pCmd Pointer to the command descriptor (as registered).
4323	* @param pCmdHlp Pointer to command helper functions.
4324	* @param pVM Pointer to the current VM (if any).
4325	* @param paArgs Pointer to (readonly) array of arguments.
4326	* @param cArgs Number of arguments in the array.
4327	*/
4328	static DECLCALLBACK(int) pgmR3CmdAssertCR3(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4329	{
4330	/*
4331	* Validate input.
4332	*/
4333	if (!pVM)
4334	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4335
4336	int rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Checking shadow CR3 page tables for consistency.\n");
4337	if (RT_FAILURE(rc))
4338	return rc;
4339
4340	PGMAssertCR3(pVM, CPUMGetGuestCR3(pVM), CPUMGetGuestCR4(pVM));
4341
4342	return VINF_SUCCESS;
4343	}
4344	#endif /* VBOX_STRICT */
4345
4346
4347	/**
4348	* The '.pgmsyncalways' command.
4349	*
4350	* @returns VBox status.
4351	* @param pCmd Pointer to the command descriptor (as registered).
4352	* @param pCmdHlp Pointer to command helper functions.
4353	* @param pVM Pointer to the current VM (if any).
4354	* @param paArgs Pointer to (readonly) array of arguments.
4355	* @param cArgs Number of arguments in the array.
4356	*/
4357	static DECLCALLBACK(int) pgmR3CmdSyncAlways(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4358	{
4359	/*
4360	* Validate input.
4361	*/
4362	if (!pVM)
4363	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4364
4365	/*
4366	* Force page directory sync.
4367	*/
4368	if (pVM->pgm.s.fSyncFlags & PGM_SYNC_ALWAYS)
4369	{
4370	ASMAtomicAndU32(&pVM->pgm.s.fSyncFlags, ~PGM_SYNC_ALWAYS);
4371	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Disabled permanent forced page directory syncing.\n");
4372	}
4373	else
4374	{
4375	ASMAtomicOrU32(&pVM->pgm.s.fSyncFlags, PGM_SYNC_ALWAYS);
4376	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
4377	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Enabled permanent forced page directory syncing.\n");
4378	}
4379	}
4380
4381	#endif /* VBOX_WITH_DEBUGGER */
4382
4383	/**
4384	* pvUser argument of the pgmR3CheckIntegrity*Node callbacks.
4385	*/
4386	typedef struct PGMCHECKINTARGS
4387	{
4388	bool fLeftToRight; /*< true: left-to-right; false: right-to-left. /
4389	PPGMPHYSHANDLER pPrevPhys;
4390	PPGMVIRTHANDLER pPrevVirt;
4391	PPGMPHYS2VIRTHANDLER pPrevPhys2Virt;
4392	PVM pVM;
4393	} PGMCHECKINTARGS, *PPGMCHECKINTARGS;
4394
4395	/**
4396	* Validate a node in the physical handler tree.
4397	*
4398	* @returns 0 on if ok, other wise 1.
4399	* @param pNode The handler node.
4400	* @param pvUser pVM.
4401	*/
4402	static DECLCALLBACK(int) pgmR3CheckIntegrityPhysHandlerNode(PAVLROGCPHYSNODECORE pNode, void *pvUser)
4403	{
4404	PPGMCHECKINTARGS pArgs = (PPGMCHECKINTARGS)pvUser;
4405	PPGMPHYSHANDLER pCur = (PPGMPHYSHANDLER)pNode;
4406	AssertReleaseReturn(!((uintptr_t)pCur & 7), 1);
4407	AssertReleaseMsg(pCur->Core.Key <= pCur->Core.KeyLast,("pCur=%p %RGp-%RGp %s\n", pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
4408	AssertReleaseMsg( !pArgs->pPrevPhys
4409	\|\| (pArgs->fLeftToRight ? pArgs->pPrevPhys->Core.KeyLast < pCur->Core.Key : pArgs->pPrevPhys->Core.KeyLast > pCur->Core.Key),
4410	("pPrevPhys=%p %RGp-%RGp %s\n"
4411	" pCur=%p %RGp-%RGp %s\n",
4412	pArgs->pPrevPhys, pArgs->pPrevPhys->Core.Key, pArgs->pPrevPhys->Core.KeyLast, pArgs->pPrevPhys->pszDesc,
4413	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
4414	pArgs->pPrevPhys = pCur;
4415	return 0;
4416	}
4417
4418
4419	/**
4420	* Validate a node in the virtual handler tree.
4421	*
4422	* @returns 0 on if ok, other wise 1.
4423	* @param pNode The handler node.
4424	* @param pvUser pVM.
4425	*/
4426	static DECLCALLBACK(int) pgmR3CheckIntegrityVirtHandlerNode(PAVLROGCPTRNODECORE pNode, void *pvUser)
4427	{
4428	PPGMCHECKINTARGS pArgs = (PPGMCHECKINTARGS)pvUser;
4429	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)pNode;
4430	AssertReleaseReturn(!((uintptr_t)pCur & 7), 1);
4431	AssertReleaseMsg(pCur->Core.Key <= pCur->Core.KeyLast,("pCur=%p %RGv-%RGv %s\n", pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
4432	AssertReleaseMsg( !pArgs->pPrevVirt
4433	\|\| (pArgs->fLeftToRight ? pArgs->pPrevVirt->Core.KeyLast < pCur->Core.Key : pArgs->pPrevVirt->Core.KeyLast > pCur->Core.Key),
4434	("pPrevVirt=%p %RGv-%RGv %s\n"
4435	" pCur=%p %RGv-%RGv %s\n",
4436	pArgs->pPrevVirt, pArgs->pPrevVirt->Core.Key, pArgs->pPrevVirt->Core.KeyLast, pArgs->pPrevVirt->pszDesc,
4437	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
4438	for (unsigned iPage = 0; iPage < pCur->cPages; iPage++)
4439	{
4440	AssertReleaseMsg(pCur->aPhysToVirt[iPage].offVirtHandler == -RT_OFFSETOF(PGMVIRTHANDLER, aPhysToVirt[iPage]),
4441	("pCur=%p %RGv-%RGv %s\n"
4442	"iPage=%d offVirtHandle=%#x expected %#x\n",
4443	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc,
4444	iPage, pCur->aPhysToVirt[iPage].offVirtHandler, -RT_OFFSETOF(PGMVIRTHANDLER, aPhysToVirt[iPage])));
4445	}
4446	pArgs->pPrevVirt = pCur;
4447	return 0;
4448	}
4449
4450
4451	/**
4452	* Validate a node in the virtual handler tree.
4453	*
4454	* @returns 0 on if ok, other wise 1.
4455	* @param pNode The handler node.
4456	* @param pvUser pVM.
4457	*/
4458	static DECLCALLBACK(int) pgmR3CheckIntegrityPhysToVirtHandlerNode(PAVLROGCPHYSNODECORE pNode, void *pvUser)
4459	{
4460	PPGMCHECKINTARGS pArgs = (PPGMCHECKINTARGS)pvUser;
4461	PPGMPHYS2VIRTHANDLER pCur = (PPGMPHYS2VIRTHANDLER)pNode;
4462	AssertReleaseMsgReturn(!((uintptr_t)pCur & 3), ("\n"), 1);
4463	AssertReleaseMsgReturn(!(pCur->offVirtHandler & 3), ("\n"), 1);
4464	AssertReleaseMsg(pCur->Core.Key <= pCur->Core.KeyLast,("pCur=%p %RGp-%RGp\n", pCur, pCur->Core.Key, pCur->Core.KeyLast));
4465	AssertReleaseMsg( !pArgs->pPrevPhys2Virt
4466	\|\| (pArgs->fLeftToRight ? pArgs->pPrevPhys2Virt->Core.KeyLast < pCur->Core.Key : pArgs->pPrevPhys2Virt->Core.KeyLast > pCur->Core.Key),
4467	("pPrevPhys2Virt=%p %RGp-%RGp\n"
4468	" pCur=%p %RGp-%RGp\n",
4469	pArgs->pPrevPhys2Virt, pArgs->pPrevPhys2Virt->Core.Key, pArgs->pPrevPhys2Virt->Core.KeyLast,
4470	pCur, pCur->Core.Key, pCur->Core.KeyLast));
4471	AssertReleaseMsg( !pArgs->pPrevPhys2Virt
4472	\|\| (pArgs->fLeftToRight ? pArgs->pPrevPhys2Virt->Core.KeyLast < pCur->Core.Key : pArgs->pPrevPhys2Virt->Core.KeyLast > pCur->Core.Key),
4473	("pPrevPhys2Virt=%p %RGp-%RGp\n"
4474	" pCur=%p %RGp-%RGp\n",
4475	pArgs->pPrevPhys2Virt, pArgs->pPrevPhys2Virt->Core.Key, pArgs->pPrevPhys2Virt->Core.KeyLast,
4476	pCur, pCur->Core.Key, pCur->Core.KeyLast));
4477	AssertReleaseMsg((pCur->offNextAlias & (PGMPHYS2VIRTHANDLER_IN_TREE \| PGMPHYS2VIRTHANDLER_IS_HEAD)) == (PGMPHYS2VIRTHANDLER_IN_TREE \| PGMPHYS2VIRTHANDLER_IS_HEAD),
4478	("pCur=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4479	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias));
4480	if (pCur->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK)
4481	{
4482	PPGMPHYS2VIRTHANDLER pCur2 = pCur;
4483	for (;;)
4484	{
4485	pCur2 = (PPGMPHYS2VIRTHANDLER)((intptr_t)pCur + (pCur->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK));
4486	AssertReleaseMsg(pCur2 != pCur,
4487	(" pCur=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4488	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias));
4489	AssertReleaseMsg((pCur2->offNextAlias & (PGMPHYS2VIRTHANDLER_IN_TREE \| PGMPHYS2VIRTHANDLER_IS_HEAD)) == PGMPHYS2VIRTHANDLER_IN_TREE,
4490	(" pCur=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
4491	"pCur2=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4492	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias,
4493	pCur2, pCur2->Core.Key, pCur2->Core.KeyLast, pCur2->offVirtHandler, pCur2->offNextAlias));
4494	AssertReleaseMsg((pCur2->Core.Key ^ pCur->Core.Key) < PAGE_SIZE,
4495	(" pCur=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
4496	"pCur2=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4497	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias,
4498	pCur2, pCur2->Core.Key, pCur2->Core.KeyLast, pCur2->offVirtHandler, pCur2->offNextAlias));
4499	AssertReleaseMsg((pCur2->Core.KeyLast ^ pCur->Core.KeyLast) < PAGE_SIZE,
4500	(" pCur=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
4501	"pCur2=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4502	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias,
4503	pCur2, pCur2->Core.Key, pCur2->Core.KeyLast, pCur2->offVirtHandler, pCur2->offNextAlias));
4504	if (!(pCur2->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK))
4505	break;
4506	}
4507	}
4508
4509	pArgs->pPrevPhys2Virt = pCur;
4510	return 0;
4511	}
4512
4513
4514	/**
4515	* Perform an integrity check on the PGM component.
4516	*
4517	* @returns VINF_SUCCESS if everything is fine.
4518	* @returns VBox error status after asserting on integrity breach.
4519	* @param pVM The VM handle.
4520	*/
4521	VMMR3DECL(int) PGMR3CheckIntegrity(PVM pVM)
4522	{
4523	AssertReleaseReturn(pVM->pgm.s.offVM, VERR_INTERNAL_ERROR);
4524
4525	/*
4526	* Check the trees.
4527	*/
4528	int cErrors = 0;
4529	const static PGMCHECKINTARGS s_LeftToRight = { true, NULL, NULL, NULL, pVM };
4530	const static PGMCHECKINTARGS s_RightToLeft = { false, NULL, NULL, NULL, pVM };
4531	PGMCHECKINTARGS Args = s_LeftToRight;
4532	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysHandlers, true, pgmR3CheckIntegrityPhysHandlerNode, &Args);
4533	Args = s_RightToLeft;
4534	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysHandlers, false, pgmR3CheckIntegrityPhysHandlerNode, &Args);
4535	Args = s_LeftToRight;
4536	cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesR3->VirtHandlers, true, pgmR3CheckIntegrityVirtHandlerNode, &Args);
4537	Args = s_RightToLeft;
4538	cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesR3->VirtHandlers, false, pgmR3CheckIntegrityVirtHandlerNode, &Args);
4539	Args = s_LeftToRight;
4540	cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesR3->HyperVirtHandlers, true, pgmR3CheckIntegrityVirtHandlerNode, &Args);
4541	Args = s_RightToLeft;
4542	cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesR3->HyperVirtHandlers, false, pgmR3CheckIntegrityVirtHandlerNode, &Args);
4543	Args = s_LeftToRight;
4544	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysToVirtHandlers, true, pgmR3CheckIntegrityPhysToVirtHandlerNode, &Args);
4545	Args = s_RightToLeft;
4546	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysToVirtHandlers, false, pgmR3CheckIntegrityPhysToVirtHandlerNode, &Args);
4547
4548	return !cErrors ? VINF_SUCCESS : VERR_INTERNAL_ERROR;
4549	}
4550
4551
4552	/**
4553	* Inform PGM if we want all mappings to be put into the shadow page table. (necessary for e.g. VMX)
4554	*
4555	* @returns VBox status code.
4556	* @param pVM VM handle.
4557	* @param fEnable Enable or disable shadow mappings
4558	*/
4559	VMMR3DECL(int) PGMR3ChangeShwPDMappings(PVM pVM, bool fEnable)
4560	{
4561	pVM->pgm.s.fDisableMappings = !fEnable;
4562
4563	uint32_t cb;
4564	int rc = PGMR3MappingsSize(pVM, &cb);
4565	AssertRCReturn(rc, rc);
4566
4567	/* Pretend the mappings are now fixed; to force a refresh of the reserved PDEs. */
4568	rc = PGMR3MappingsFix(pVM, MM_HYPER_AREA_ADDRESS, cb);
4569	AssertRCReturn(rc, rc);
4570
4571	return VINF_SUCCESS;
4572	}
4573

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source: vbox/trunk/src/VBox/VMM/PGM.cpp@ 15411

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