PGM.cpp@ 15491

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PGM: Fixed saved state hack (VMMDev Heap).
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1	/* $Id: PGM.cpp 15491 2008-12-15 10:28:56Z vboxsync $ */
2	/** @file
3	* PGM - Page Manager and Monitor. (Mixing stuff here, not good?)
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22
23	/** @page pg_pgm PGM - The Page Manager and Monitor
24	*
25	* @see grp_pgm,
26	* @ref pg_pgm_pool,
27	* @ref pg_pgm_phys.
28	*
29	*
30	* @section sec_pgm_modes Paging Modes
31	*
32	* There are three memory contexts: Host Context (HC), Guest Context (GC)
33	* and intermediate context. When talking about paging HC can also be refered to
34	* as "host paging", and GC refered to as "shadow paging".
35	*
36	* We define three basic paging modes: 32-bit, PAE and AMD64. The host paging mode
37	* is defined by the host operating system. The mode used in the shadow paging mode
38	* depends on the host paging mode and what the mode the guest is currently in. The
39	* following relation between the two is defined:
40	*
41	* @verbatim
42	Host > 32-bit \| PAE \| AMD64 \|
43	Guest \| \| \| \|
44	==v================================
45	32-bit 32-bit PAE PAE
46	-------\|--------\|--------\|--------\|
47	PAE PAE PAE PAE
48	-------\|--------\|--------\|--------\|
49	AMD64 AMD64 AMD64 AMD64
50	-------\|--------\|--------\|--------\| @endverbatim
51	*
52	* All configuration except those in the diagonal (upper left) are expected to
53	* require special effort from the switcher (i.e. a bit slower).
54	*
55	*
56	*
57	*
58	* @section sec_pgm_shw The Shadow Memory Context
59	*
60	*
61	* [..]
62	*
63	* Because of guest context mappings requires PDPT and PML4 entries to allow
64	* writing on AMD64, the two upper levels will have fixed flags whatever the
65	* guest is thinking of using there. So, when shadowing the PD level we will
66	* calculate the effective flags of PD and all the higher levels. In legacy
67	* PAE mode this only applies to the PWT and PCD bits (the rest are
68	* ignored/reserved/MBZ). We will ignore those bits for the present.
69	*
70	*
71	*
72	* @section sec_pgm_int The Intermediate Memory Context
73	*
74	* The world switch goes thru an intermediate memory context which purpose it is
75	* to provide different mappings of the switcher code. All guest mappings are also
76	* present in this context.
77	*
78	* The switcher code is mapped at the same location as on the host, at an
79	* identity mapped location (physical equals virtual address), and at the
80	* hypervisor location. The identity mapped location is for when the world
81	* switches that involves disabling paging.
82	*
83	* PGM maintain page tables for 32-bit, PAE and AMD64 paging modes. This
84	* simplifies switching guest CPU mode and consistency at the cost of more
85	* code to do the work. All memory use for those page tables is located below
86	* 4GB (this includes page tables for guest context mappings).
87	*
88	*
89	* @subsection subsec_pgm_int_gc Guest Context Mappings
90	*
91	* During assignment and relocation of a guest context mapping the intermediate
92	* memory context is used to verify the new location.
93	*
94	* Guest context mappings are currently restricted to below 4GB, for reasons
95	* of simplicity. This may change when we implement AMD64 support.
96	*
97	*
98	*
99	*
100	* @section sec_pgm_misc Misc
101	*
102	* @subsection subsec_pgm_misc_diff Differences Between Legacy PAE and Long Mode PAE
103	*
104	* The differences between legacy PAE and long mode PAE are:
105	* -# PDPE bits 1, 2, 5 and 6 are defined differently. In leagcy mode they are
106	* all marked down as must-be-zero, while in long mode 1, 2 and 5 have the
107	* usual meanings while 6 is ignored (AMD). This means that upon switching to
108	* legacy PAE mode we'll have to clear these bits and when going to long mode
109	* they must be set. This applies to both intermediate and shadow contexts,
110	* however we don't need to do it for the intermediate one since we're
111	* executing with CR0.WP at that time.
112	* -# CR3 allows a 32-byte aligned address in legacy mode, while in long mode
113	* a page aligned one is required.
114	*
115	*
116	* @section sec_pgm_handlers Access Handlers
117	*
118	* Placeholder.
119	*
120	*
121	* @subsection sec_pgm_handlers_virt Virtual Access Handlers
122	*
123	* Placeholder.
124	*
125	*
126	* @subsection sec_pgm_handlers_virt Virtual Access Handlers
127	*
128	* We currently implement three types of virtual access handlers: ALL, WRITE
129	* and HYPERVISOR (WRITE). See PGMVIRTHANDLERTYPE for some more details.
130	*
131	* The HYPERVISOR access handlers is kept in a separate tree since it doesn't apply
132	* to physical pages (PGMTREES::HyperVirtHandlers) and only needs to be consulted in
133	* a special \#PF case. The ALL and WRITE are in the PGMTREES::VirtHandlers tree, the
134	* rest of this section is going to be about these handlers.
135	*
136	* We'll go thru the life cycle of a handler and try make sense of it all, don't know
137	* how successfull this is gonna be...
138	*
139	* 1. A handler is registered thru the PGMR3HandlerVirtualRegister and
140	* PGMHandlerVirtualRegisterEx APIs. We check for conflicting virtual handlers
141	* and create a new node that is inserted into the AVL tree (range key). Then
142	* a full PGM resync is flagged (clear pool, sync cr3, update virtual bit of PGMPAGE).
143	*
144	* 2. The following PGMSyncCR3/SyncCR3 operation will first make invoke HandlerVirtualUpdate.
145	*
146	* 2a. HandlerVirtualUpdate will will lookup all the pages covered by virtual handlers
147	* via the current guest CR3 and update the physical page -> virtual handler
148	* translation. Needless to say, this doesn't exactly scale very well. If any changes
149	* are detected, it will flag a virtual bit update just like we did on registration.
150	* PGMPHYS pages with changes will have their virtual handler state reset to NONE.
151	*
152	* 2b. The virtual bit update process will iterate all the pages covered by all the
153	* virtual handlers and update the PGMPAGE virtual handler state to the max of all
154	* virtual handlers on that page.
155	*
156	* 2c. Back in SyncCR3 we will now flush the entire shadow page cache to make sure
157	* we don't miss any alias mappings of the monitored pages.
158	*
159	* 2d. SyncCR3 will then proceed with syncing the CR3 table.
160	*
161	* 3. \#PF(np,read) on a page in the range. This will cause it to be synced
162	* read-only and resumed if it's a WRITE handler. If it's an ALL handler we
163	* will call the handlers like in the next step. If the physical mapping has
164	* changed we will - some time in the future - perform a handler callback
165	* (optional) and update the physical -> virtual handler cache.
166	*
167	* 4. \#PF(,write) on a page in the range. This will cause the handler to
168	* be invoked.
169	*
170	* 5. The guest invalidates the page and changes the physical backing or
171	* unmaps it. This should cause the invalidation callback to be invoked
172	* (it might not yet be 100% perfect). Exactly what happens next... is
173	* this where we mess up and end up out of sync for a while?
174	*
175	* 6. The handler is deregistered by the client via PGMHandlerVirtualDeregister.
176	* We will then set all PGMPAGEs in the physical -> virtual handler cache for
177	* this handler to NONE and trigger a full PGM resync (basically the same
178	* as int step 1). Which means 2 is executed again.
179	*
180	*
181	* @subsubsection sub_sec_pgm_handler_virt_todo TODOs
182	*
183	* There is a bunch of things that needs to be done to make the virtual handlers
184	* work 100% correctly and work more efficiently.
185	*
186	* The first bit hasn't been implemented yet because it's going to slow the
187	* whole mess down even more, and besides it seems to be working reliably for
188	* our current uses. OTOH, some of the optimizations might end up more or less
189	* implementing the missing bits, so we'll see.
190	*
191	* On the optimization side, the first thing to do is to try avoid unnecessary
192	* cache flushing. Then try team up with the shadowing code to track changes
193	* in mappings by means of access to them (shadow in), updates to shadows pages,
194	* invlpg, and shadow PT discarding (perhaps).
195	*
196	* Some idea that have popped up for optimization for current and new features:
197	* - bitmap indicating where there are virtual handlers installed.
198	* (4KB => 220 pages, page 212 => covers 32-bit address space 1:1!)
199	* - Further optimize this by min/max (needs min/max avl getters).
200	* - Shadow page table entry bit (if any left)?
201	*
202	*/
203
204
205	/** @page pg_pgm_phys PGM Physical Guest Memory Management
206	*
207	*
208	* Objectives:
209	* - Guest RAM over-commitment using memory ballooning,
210	* zero pages and general page sharing.
211	* - Moving or mirroring a VM onto a different physical machine.
212	*
213	*
214	* @subsection subsec_pgmPhys_Definitions Definitions
215	*
216	* Allocation chunk - A RTR0MemObjAllocPhysNC object and the tracking
217	* machinery assoicated with it.
218	*
219	*
220	*
221	*
222	* @subsection subsec_pgmPhys_AllocPage Allocating a page.
223	*
224	* Initially we map all guest memory to the (per VM) zero page, which
225	* means that none of the read functions will cause pages to be allocated.
226	*
227	* Exception, access bit in page tables that have been shared. This must
228	* be handled, but we must also make sure PGMGst*Modify doesn't make
229	* unnecessary modifications.
230	*
231	* Allocation points:
232	* - PGMPhysSimpleWriteGCPhys and PGMPhysWrite.
233	* - Replacing a zero page mapping at \#PF.
234	* - Replacing a shared page mapping at \#PF.
235	* - ROM registration (currently MMR3RomRegister).
236	* - VM restore (pgmR3Load).
237	*
238	* For the first three it would make sense to keep a few pages handy
239	* until we've reached the max memory commitment for the VM.
240	*
241	* For the ROM registration, we know exactly how many pages we need
242	* and will request these from ring-0. For restore, we will save
243	* the number of non-zero pages in the saved state and allocate
244	* them up front. This would allow the ring-0 component to refuse
245	* the request if the isn't sufficient memory available for VM use.
246	*
247	* Btw. for both ROM and restore allocations we won't be requiring
248	* zeroed pages as they are going to be filled instantly.
249	*
250	*
251	* @subsection subsec_pgmPhys_FreePage Freeing a page
252	*
253	* There are a few points where a page can be freed:
254	* - After being replaced by the zero page.
255	* - After being replaced by a shared page.
256	* - After being ballooned by the guest additions.
257	* - At reset.
258	* - At restore.
259	*
260	* When freeing one or more pages they will be returned to the ring-0
261	* component and replaced by the zero page.
262	*
263	* The reasoning for clearing out all the pages on reset is that it will
264	* return us to the exact same state as on power on, and may thereby help
265	* us reduce the memory load on the system. Further it might have a
266	* (temporary) positive influence on memory fragmentation (@see subsec_pgmPhys_Fragmentation).
267	*
268	* On restore, as mention under the allocation topic, pages should be
269	* freed / allocated depending on how many is actually required by the
270	* new VM state. The simplest approach is to do like on reset, and free
271	* all non-ROM pages and then allocate what we need.
272	*
273	* A measure to prevent some fragmentation, would be to let each allocation
274	* chunk have some affinity towards the VM having allocated the most pages
275	* from it. Also, try make sure to allocate from allocation chunks that
276	* are almost full. Admittedly, both these measures might work counter to
277	* our intentions and its probably not worth putting a lot of effort,
278	* cpu time or memory into this.
279	*
280	*
281	* @subsection subsec_pgmPhys_SharePage Sharing a page
282	*
283	* The basic idea is that there there will be a idle priority kernel
284	* thread walking the non-shared VM pages hashing them and looking for
285	* pages with the same checksum. If such pages are found, it will compare
286	* them byte-by-byte to see if they actually are identical. If found to be
287	* identical it will allocate a shared page, copy the content, check that
288	* the page didn't change while doing this, and finally request both the
289	* VMs to use the shared page instead. If the page is all zeros (special
290	* checksum and byte-by-byte check) it will request the VM that owns it
291	* to replace it with the zero page.
292	*
293	* To make this efficient, we will have to make sure not to try share a page
294	* that will change its contents soon. This part requires the most work.
295	* A simple idea would be to request the VM to write monitor the page for
296	* a while to make sure it isn't modified any time soon. Also, it may
297	* make sense to skip pages that are being write monitored since this
298	* information is readily available to the thread if it works on the
299	* per-VM guest memory structures (presently called PGMRAMRANGE).
300	*
301	*
302	* @subsection subsec_pgmPhys_Fragmentation Fragmentation Concerns and Counter Measures
303	*
304	* The pages are organized in allocation chunks in ring-0, this is a necessity
305	* if we wish to have an OS agnostic approach to this whole thing. (On Linux we
306	* could easily work on a page-by-page basis if we liked. Whether this is possible
307	* or efficient on NT I don't quite know.) Fragmentation within these chunks may
308	* become a problem as part of the idea here is that we wish to return memory to
309	* the host system.
310	*
311	* For instance, starting two VMs at the same time, they will both allocate the
312	* guest memory on-demand and if permitted their page allocations will be
313	* intermixed. Shut down one of the two VMs and it will be difficult to return
314	* any memory to the host system because the page allocation for the two VMs are
315	* mixed up in the same allocation chunks.
316	*
317	* To further complicate matters, when pages are freed because they have been
318	* ballooned or become shared/zero the whole idea is that the page is supposed
319	* to be reused by another VM or returned to the host system. This will cause
320	* allocation chunks to contain pages belonging to different VMs and prevent
321	* returning memory to the host when one of those VM shuts down.
322	*
323	* The only way to really deal with this problem is to move pages. This can
324	* either be done at VM shutdown and or by the idle priority worker thread
325	* that will be responsible for finding sharable/zero pages. The mechanisms
326	* involved for coercing a VM to move a page (or to do it for it) will be
327	* the same as when telling it to share/zero a page.
328	*
329	*
330	* @subsection subsec_pgmPhys_Tracking Tracking Structures And Their Cost
331	*
332	* There's a difficult balance between keeping the per-page tracking structures
333	* (global and guest page) easy to use and keeping them from eating too much
334	* memory. We have limited virtual memory resources available when operating in
335	* 32-bit kernel space (on 64-bit there'll it's quite a different story). The
336	* tracking structures will be attemted designed such that we can deal with up
337	* to 32GB of memory on a 32-bit system and essentially unlimited on 64-bit ones.
338	*
339	*
340	* @subsubsection subsubsec_pgmPhys_Tracking_Kernel Kernel Space
341	*
342	* @see pg_GMM
343	*
344	* @subsubsection subsubsec_pgmPhys_Tracking_PerVM Per-VM
345	*
346	* Fixed info is the physical address of the page (HCPhys) and the page id
347	* (described above). Theoretically we'll need 48(-12) bits for the HCPhys part.
348	* Today we've restricting ourselves to 40(-12) bits because this is the current
349	* restrictions of all AMD64 implementations (I think Barcelona will up this
350	* to 48(-12) bits, not that it really matters) and I needed the bits for
351	* tracking mappings of a page. 48-12 = 36. That leaves 28 bits, which means a
352	* decent range for the page id: 2^(28+12) = 1024TB.
353	*
354	* In additions to these, we'll have to keep maintaining the page flags as we
355	* currently do. Although it wouldn't harm to optimize these quite a bit, like
356	* for instance the ROM shouldn't depend on having a write handler installed
357	* in order for it to become read-only. A RO/RW bit should be considered so
358	* that the page syncing code doesn't have to mess about checking multiple
359	* flag combinations (ROM \|\| RW handler \|\| write monitored) in order to
360	* figure out how to setup a shadow PTE. But this of course, is second
361	* priority at present. Current this requires 12 bits, but could probably
362	* be optimized to ~8.
363	*
364	* Then there's the 24 bits used to track which shadow page tables are
365	* currently mapping a page for the purpose of speeding up physical
366	* access handlers, and thereby the page pool cache. More bit for this
367	* purpose wouldn't hurt IIRC.
368	*
369	* Then there is a new bit in which we need to record what kind of page
370	* this is, shared, zero, normal or write-monitored-normal. This'll
371	* require 2 bits. One bit might be needed for indicating whether a
372	* write monitored page has been written to. And yet another one or
373	* two for tracking migration status. 3-4 bits total then.
374	*
375	* Whatever is left will can be used to record the sharabilitiy of a
376	* page. The page checksum will not be stored in the per-VM table as
377	* the idle thread will not be permitted to do modifications to it.
378	* It will instead have to keep its own working set of potentially
379	* shareable pages and their check sums and stuff.
380	*
381	* For the present we'll keep the current packing of the
382	* PGMRAMRANGE::aHCPhys to keep the changes simple, only of course,
383	* we'll have to change it to a struct with a total of 128-bits at
384	* our disposal.
385	*
386	* The initial layout will be like this:
387	* @verbatim
388	RTHCPHYS HCPhys; The current stuff.
389	63:40 Current shadow PT tracking stuff.
390	39:12 The physical page frame number.
391	11:0 The current flags.
392	uint32_t u28PageId : 28; The page id.
393	uint32_t u2State : 2; The page state { zero, shared, normal, write monitored }.
394	uint32_t fWrittenTo : 1; Whether a write monitored page was written to.
395	uint32_t u1Reserved : 1; Reserved for later.
396	uint32_t u32Reserved; Reserved for later, mostly sharing stats.
397	@endverbatim
398	*
399	* The final layout will be something like this:
400	* @verbatim
401	RTHCPHYS HCPhys; The current stuff.
402	63:48 High page id (12+).
403	47:12 The physical page frame number.
404	11:0 Low page id.
405	uint32_t fReadOnly : 1; Whether it's readonly page (rom or monitored in some way).
406	uint32_t u3Type : 3; The page type {RESERVED, MMIO, MMIO2, ROM, shadowed ROM, RAM}.
407	uint32_t u2PhysMon : 2; Physical access handler type {none, read, write, all}.
408	uint32_t u2VirtMon : 2; Virtual access handler type {none, read, write, all}..
409	uint32_t u2State : 2; The page state { zero, shared, normal, write monitored }.
410	uint32_t fWrittenTo : 1; Whether a write monitored page was written to.
411	uint32_t u20Reserved : 20; Reserved for later, mostly sharing stats.
412	uint32_t u32Tracking; The shadow PT tracking stuff, roughly.
413	@endverbatim
414	*
415	* Cost wise, this means we'll double the cost for guest memory. There isn't anyway
416	* around that I'm afraid. It means that the cost of dealing out 32GB of memory
417	* to one or more VMs is: (32GB >> PAGE_SHIFT) * 16 bytes, or 128MBs. Or another
418	* example, the VM heap cost when assigning 1GB to a VM will be: 4MB.
419	*
420	* A couple of cost examples for the total cost per-VM + kernel.
421	* 32-bit Windows and 32-bit linux:
422	* 1GB guest ram, 256K pages: 4MB + 2MB(+) = 6MB
423	* 4GB guest ram, 1M pages: 16MB + 8MB(+) = 24MB
424	* 32GB guest ram, 8M pages: 128MB + 64MB(+) = 192MB
425	* 64-bit Windows and 64-bit linux:
426	* 1GB guest ram, 256K pages: 4MB + 3MB(+) = 7MB
427	* 4GB guest ram, 1M pages: 16MB + 12MB(+) = 28MB
428	* 32GB guest ram, 8M pages: 128MB + 96MB(+) = 224MB
429	*
430	* UPDATE - 2007-09-27:
431	* Will need a ballooned flag/state too because we cannot
432	* trust the guest 100% and reporting the same page as ballooned more
433	* than once will put the GMM off balance.
434	*
435	*
436	* @subsection subsec_pgmPhys_Serializing Serializing Access
437	*
438	* Initially, we'll try a simple scheme:
439	*
440	* - The per-VM RAM tracking structures (PGMRAMRANGE) is only modified
441	* by the EMT thread of that VM while in the pgm critsect.
442	* - Other threads in the VM process that needs to make reliable use of
443	* the per-VM RAM tracking structures will enter the critsect.
444	* - No process external thread or kernel thread will ever try enter
445	* the pgm critical section, as that just won't work.
446	* - The idle thread (and similar threads) doesn't not need 100% reliable
447	* data when performing it tasks as the EMT thread will be the one to
448	* do the actual changes later anyway. So, as long as it only accesses
449	* the main ram range, it can do so by somehow preventing the VM from
450	* being destroyed while it works on it...
451	*
452	* - The over-commitment management, including the allocating/freeing
453	* chunks, is serialized by a ring-0 mutex lock (a fast one since the
454	* more mundane mutex implementation is broken on Linux).
455	* - A separeate mutex is protecting the set of allocation chunks so
456	* that pages can be shared or/and freed up while some other VM is
457	* allocating more chunks. This mutex can be take from under the other
458	* one, but not the otherway around.
459	*
460	*
461	* @subsection subsec_pgmPhys_Request VM Request interface
462	*
463	* When in ring-0 it will become necessary to send requests to a VM so it can
464	* for instance move a page while defragmenting during VM destroy. The idle
465	* thread will make use of this interface to request VMs to setup shared
466	* pages and to perform write monitoring of pages.
467	*
468	* I would propose an interface similar to the current VMReq interface, similar
469	* in that it doesn't require locking and that the one sending the request may
470	* wait for completion if it wishes to. This shouldn't be very difficult to
471	* realize.
472	*
473	* The requests themselves are also pretty simple. They are basically:
474	* -# Check that some precondition is still true.
475	* -# Do the update.
476	* -# Update all shadow page tables involved with the page.
477	*
478	* The 3rd step is identical to what we're already doing when updating a
479	* physical handler, see pgmHandlerPhysicalSetRamFlagsAndFlushShadowPTs.
480	*
481	*
482	*
483	* @section sec_pgmPhys_MappingCaches Mapping Caches
484	*
485	* In order to be able to map in and out memory and to be able to support
486	* guest with more RAM than we've got virtual address space, we'll employing
487	* a mapping cache. There is already a tiny one for GC (see PGMGCDynMapGCPageEx)
488	* and we'll create a similar one for ring-0 unless we decide to setup a dedicate
489	* memory context for the HWACCM execution.
490	*
491	*
492	* @subsection subsec_pgmPhys_MappingCaches_R3 Ring-3
493	*
494	* We've considered implementing the ring-3 mapping cache page based but found
495	* that this was bother some when one had to take into account TLBs+SMP and
496	* portability (missing the necessary APIs on several platforms). There were
497	* also some performance concerns with this approach which hadn't quite been
498	* worked out.
499	*
500	* Instead, we'll be mapping allocation chunks into the VM process. This simplifies
501	* matters greatly quite a bit since we don't need to invent any new ring-0 stuff,
502	* only some minor RTR0MEMOBJ mapping stuff. The main concern here is that mapping
503	* compared to the previous idea is that mapping or unmapping a 1MB chunk is more
504	* costly than a single page, although how much more costly is uncertain. We'll
505	* try address this by using a very big cache, preferably bigger than the actual
506	* VM RAM size if possible. The current VM RAM sizes should give some idea for
507	* 32-bit boxes, while on 64-bit we can probably get away with employing an
508	* unlimited cache.
509	*
510	* The cache have to parts, as already indicated, the ring-3 side and the
511	* ring-0 side.
512	*
513	* The ring-0 will be tied to the page allocator since it will operate on the
514	* memory objects it contains. It will therefore require the first ring-0 mutex
515	* discussed in @ref subsec_pgmPhys_Serializing. We
516	* some double house keeping wrt to who has mapped what I think, since both
517	* VMMR0.r0 and RTR0MemObj will keep track of mapping relataions
518	*
519	* The ring-3 part will be protected by the pgm critsect. For simplicity, we'll
520	* require anyone that desires to do changes to the mapping cache to do that
521	* from within this critsect. Alternatively, we could employ a separate critsect
522	* for serializing changes to the mapping cache as this would reduce potential
523	* contention with other threads accessing mappings unrelated to the changes
524	* that are in process. We can see about this later, contention will show
525	* up in the statistics anyway, so it'll be simple to tell.
526	*
527	* The organization of the ring-3 part will be very much like how the allocation
528	* chunks are organized in ring-0, that is in an AVL tree by chunk id. To avoid
529	* having to walk the tree all the time, we'll have a couple of lookaside entries
530	* like in we do for I/O ports and MMIO in IOM.
531	*
532	* The simplified flow of a PGMPhysRead/Write function:
533	* -# Enter the PGM critsect.
534	* -# Lookup GCPhys in the ram ranges and get the Page ID.
535	* -# Calc the Allocation Chunk ID from the Page ID.
536	* -# Check the lookaside entries and then the AVL tree for the Chunk ID.
537	* If not found in cache:
538	* -# Call ring-0 and request it to be mapped and supply
539	* a chunk to be unmapped if the cache is maxed out already.
540	* -# Insert the new mapping into the AVL tree (id + R3 address).
541	* -# Update the relevant lookaside entry and return the mapping address.
542	* -# Do the read/write according to monitoring flags and everything.
543	* -# Leave the critsect.
544	*
545	*
546	* @section sec_pgmPhys_Fallback Fallback
547	*
548	* Current all the "second tier" hosts will not support the RTR0MemObjAllocPhysNC
549	* API and thus require a fallback.
550	*
551	* So, when RTR0MemObjAllocPhysNC returns VERR_NOT_SUPPORTED the page allocator
552	* will return to the ring-3 caller (and later ring-0) and asking it to seed
553	* the page allocator with some fresh pages (VERR_GMM_SEED_ME). Ring-3 will
554	* then perform an SUPPageAlloc(cbChunk >> PAGE_SHIFT) call and make a
555	* "SeededAllocPages" call to ring-0.
556	*
557	* The first time ring-0 sees the VERR_NOT_SUPPORTED failure it will disable
558	* all page sharing (zero page detection will continue). It will also force
559	* all allocations to come from the VM which seeded the page. Both these
560	* measures are taken to make sure that there will never be any need for
561	* mapping anything into ring-3 - everything will be mapped already.
562	*
563	* Whether we'll continue to use the current MM locked memory management
564	* for this I don't quite know (I'd prefer not to and just ditch that all
565	* togther), we'll see what's simplest to do.
566	*
567	*
568	*
569	* @section sec_pgmPhys_Changes Changes
570	*
571	* Breakdown of the changes involved?
572	*/
573
574
575	/** Saved state data unit version. */
576	#define PGM_SAVED_STATE_VERSION 6
577
578	/*******************************************************************************
579	* Header Files *
580	*******************************************************************************/
581	#define LOG_GROUP LOG_GROUP_PGM
582	#include <VBox/dbgf.h>
583	#include <VBox/pgm.h>
584	#include <VBox/cpum.h>
585	#include <VBox/iom.h>
586	#include <VBox/sup.h>
587	#include <VBox/mm.h>
588	#include <VBox/em.h>
589	#include <VBox/stam.h>
590	#include <VBox/rem.h>
591	#include <VBox/dbgf.h>
592	#include <VBox/rem.h>
593	#include <VBox/selm.h>
594	#include <VBox/ssm.h>
595	#include "PGMInternal.h"
596	#include <VBox/vm.h>
597	#include <VBox/dbg.h>
598	#include <VBox/hwaccm.h>
599
600	#include <iprt/assert.h>
601	#include <iprt/alloc.h>
602	#include <iprt/asm.h>
603	#include <iprt/thread.h>
604	#include <iprt/string.h>
605	#ifdef DEBUG_bird
606	# include <iprt/env.h>
607	#endif
608	#include <VBox/param.h>
609	#include <VBox/err.h>
610
611
612
613	/*******************************************************************************
614	* Internal Functions *
615	*******************************************************************************/
616	static int pgmR3InitPaging(PVM pVM);
617	static DECLCALLBACK(void) pgmR3PhysInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
618	static DECLCALLBACK(void) pgmR3InfoMode(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
619	static DECLCALLBACK(void) pgmR3InfoCr3(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
620	static DECLCALLBACK(int) pgmR3RelocatePhysHandler(PAVLROGCPHYSNODECORE pNode, void *pvUser);
621	static DECLCALLBACK(int) pgmR3RelocateVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser);
622	static DECLCALLBACK(int) pgmR3RelocateHyperVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser);
623	#ifdef VBOX_STRICT
624	static DECLCALLBACK(void) pgmR3ResetNoMorePhysWritesFlag(PVM pVM, VMSTATE enmState, VMSTATE enmOldState, void *pvUser);
625	#endif
626	static DECLCALLBACK(int) pgmR3Save(PVM pVM, PSSMHANDLE pSSM);
627	static DECLCALLBACK(int) pgmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version);
628	static int pgmR3ModeDataInit(PVM pVM, bool fResolveGCAndR0);
629	static void pgmR3ModeDataSwitch(PVM pVM, PGMMODE enmShw, PGMMODE enmGst);
630	static PGMMODE pgmR3CalcShadowMode(PVM pVM, PGMMODE enmGuestMode, SUPPAGINGMODE enmHostMode, PGMMODE enmShadowMode, VMMSWITCHER *penmSwitcher);
631
632	#ifdef VBOX_WITH_STATISTICS
633	static void pgmR3InitStats(PVM pVM);
634	#endif
635
636	#ifdef VBOX_WITH_DEBUGGER
637	/** @todo all but the two last commands must be converted to 'info'. */
638	static DECLCALLBACK(int) pgmR3CmdRam(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
639	static DECLCALLBACK(int) pgmR3CmdMap(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
640	static DECLCALLBACK(int) pgmR3CmdSync(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
641	static DECLCALLBACK(int) pgmR3CmdSyncAlways(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
642	# ifdef VBOX_STRICT
643	static DECLCALLBACK(int) pgmR3CmdAssertCR3(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
644	# endif
645	#endif
646
647
648	/*******************************************************************************
649	* Global Variables *
650	*******************************************************************************/
651	#ifdef VBOX_WITH_DEBUGGER
652	/** Command descriptors. */
653	static const DBGCCMD g_aCmds[] =
654	{
655	/* pszCmd, cArgsMin, cArgsMax, paArgDesc, cArgDescs, pResultDesc, fFlags, pfnHandler pszSyntax, ....pszDescription */
656	{ "pgmram", 0, 0, NULL, 0, NULL, 0, pgmR3CmdRam, "", "Display the ram ranges." },
657	{ "pgmmap", 0, 0, NULL, 0, NULL, 0, pgmR3CmdMap, "", "Display the mapping ranges." },
658	{ "pgmsync", 0, 0, NULL, 0, NULL, 0, pgmR3CmdSync, "", "Sync the CR3 page." },
659	#ifdef VBOX_STRICT
660	{ "pgmassertcr3", 0, 0, NULL, 0, NULL, 0, pgmR3CmdAssertCR3, "", "Check the shadow CR3 mapping." },
661	#endif
662	{ "pgmsyncalways", 0, 0, NULL, 0, NULL, 0, pgmR3CmdSyncAlways, "", "Toggle permanent CR3 syncing." },
663	};
664	#endif
665
666
667
668
669	/*
670	* Shadow - 32-bit mode
671	*/
672	#define PGM_SHW_TYPE PGM_TYPE_32BIT
673	#define PGM_SHW_NAME(name) PGM_SHW_NAME_32BIT(name)
674	#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_32BIT_STR(name)
675	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_32BIT_STR(name)
676	#include "PGMShw.h"
677
678	/* Guest - real mode */
679	#define PGM_GST_TYPE PGM_TYPE_REAL
680	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
681	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_REAL_STR(name)
682	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
683	#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_REAL(name)
684	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_32BIT_REAL_STR(name)
685	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_32BIT_REAL_STR(name)
686	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_PHYS
687	#include "PGMGst.h"
688	#include "PGMBth.h"
689	#undef BTH_PGMPOOLKIND_PT_FOR_PT
690	#undef PGM_BTH_NAME
691	#undef PGM_BTH_NAME_RC_STR
692	#undef PGM_BTH_NAME_R0_STR
693	#undef PGM_GST_TYPE
694	#undef PGM_GST_NAME
695	#undef PGM_GST_NAME_RC_STR
696	#undef PGM_GST_NAME_R0_STR
697
698	/* Guest - protected mode */
699	#define PGM_GST_TYPE PGM_TYPE_PROT
700	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
701	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PROT_STR(name)
702	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
703	#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_PROT(name)
704	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_32BIT_PROT_STR(name)
705	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_32BIT_PROT_STR(name)
706	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_PHYS
707	#include "PGMGst.h"
708	#include "PGMBth.h"
709	#undef BTH_PGMPOOLKIND_PT_FOR_PT
710	#undef PGM_BTH_NAME
711	#undef PGM_BTH_NAME_RC_STR
712	#undef PGM_BTH_NAME_R0_STR
713	#undef PGM_GST_TYPE
714	#undef PGM_GST_NAME
715	#undef PGM_GST_NAME_RC_STR
716	#undef PGM_GST_NAME_R0_STR
717
718	/* Guest - 32-bit mode */
719	#define PGM_GST_TYPE PGM_TYPE_32BIT
720	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
721	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_32BIT_STR(name)
722	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
723	#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_32BIT(name)
724	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_32BIT_32BIT_STR(name)
725	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_32BIT_32BIT_STR(name)
726	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT
727	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB
728	#include "PGMGst.h"
729	#include "PGMBth.h"
730	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
731	#undef BTH_PGMPOOLKIND_PT_FOR_PT
732	#undef PGM_BTH_NAME
733	#undef PGM_BTH_NAME_RC_STR
734	#undef PGM_BTH_NAME_R0_STR
735	#undef PGM_GST_TYPE
736	#undef PGM_GST_NAME
737	#undef PGM_GST_NAME_RC_STR
738	#undef PGM_GST_NAME_R0_STR
739
740	#undef PGM_SHW_TYPE
741	#undef PGM_SHW_NAME
742	#undef PGM_SHW_NAME_RC_STR
743	#undef PGM_SHW_NAME_R0_STR
744
745
746	/*
747	* Shadow - PAE mode
748	*/
749	#define PGM_SHW_TYPE PGM_TYPE_PAE
750	#define PGM_SHW_NAME(name) PGM_SHW_NAME_PAE(name)
751	#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_PAE_STR(name)
752	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_PAE_STR(name)
753	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_REAL(name)
754	#include "PGMShw.h"
755
756	/* Guest - real mode */
757	#define PGM_GST_TYPE PGM_TYPE_REAL
758	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
759	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_REAL_STR(name)
760	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
761	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_REAL(name)
762	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_PAE_REAL_STR(name)
763	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_REAL_STR(name)
764	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
765	#include "PGMBth.h"
766	#undef BTH_PGMPOOLKIND_PT_FOR_PT
767	#undef PGM_BTH_NAME
768	#undef PGM_BTH_NAME_RC_STR
769	#undef PGM_BTH_NAME_R0_STR
770	#undef PGM_GST_TYPE
771	#undef PGM_GST_NAME
772	#undef PGM_GST_NAME_RC_STR
773	#undef PGM_GST_NAME_R0_STR
774
775	/* Guest - protected mode */
776	#define PGM_GST_TYPE PGM_TYPE_PROT
777	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
778	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PROT_STR(name)
779	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
780	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_PROT(name)
781	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_PAE_PROT_STR(name)
782	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_PROT_STR(name)
783	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
784	#include "PGMBth.h"
785	#undef BTH_PGMPOOLKIND_PT_FOR_PT
786	#undef PGM_BTH_NAME
787	#undef PGM_BTH_NAME_RC_STR
788	#undef PGM_BTH_NAME_R0_STR
789	#undef PGM_GST_TYPE
790	#undef PGM_GST_NAME
791	#undef PGM_GST_NAME_RC_STR
792	#undef PGM_GST_NAME_R0_STR
793
794	/* Guest - 32-bit mode */
795	#define PGM_GST_TYPE PGM_TYPE_32BIT
796	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
797	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_32BIT_STR(name)
798	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
799	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_32BIT(name)
800	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_PAE_32BIT_STR(name)
801	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_32BIT_STR(name)
802	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_32BIT_PT
803	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB
804	#include "PGMBth.h"
805	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
806	#undef BTH_PGMPOOLKIND_PT_FOR_PT
807	#undef PGM_BTH_NAME
808	#undef PGM_BTH_NAME_RC_STR
809	#undef PGM_BTH_NAME_R0_STR
810	#undef PGM_GST_TYPE
811	#undef PGM_GST_NAME
812	#undef PGM_GST_NAME_RC_STR
813	#undef PGM_GST_NAME_R0_STR
814
815	/* Guest - PAE mode */
816	#define PGM_GST_TYPE PGM_TYPE_PAE
817	#define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
818	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PAE_STR(name)
819	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PAE_STR(name)
820	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_PAE(name)
821	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_PAE_PAE_STR(name)
822	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_PAE_STR(name)
823	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
824	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
825	#include "PGMGst.h"
826	#include "PGMBth.h"
827	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
828	#undef BTH_PGMPOOLKIND_PT_FOR_PT
829	#undef PGM_BTH_NAME
830	#undef PGM_BTH_NAME_RC_STR
831	#undef PGM_BTH_NAME_R0_STR
832	#undef PGM_GST_TYPE
833	#undef PGM_GST_NAME
834	#undef PGM_GST_NAME_RC_STR
835	#undef PGM_GST_NAME_R0_STR
836
837	#undef PGM_SHW_TYPE
838	#undef PGM_SHW_NAME
839	#undef PGM_SHW_NAME_RC_STR
840	#undef PGM_SHW_NAME_R0_STR
841
842
843	/*
844	* Shadow - AMD64 mode
845	*/
846	#define PGM_SHW_TYPE PGM_TYPE_AMD64
847	#define PGM_SHW_NAME(name) PGM_SHW_NAME_AMD64(name)
848	#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_AMD64_STR(name)
849	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_AMD64_STR(name)
850	#include "PGMShw.h"
851
852	#ifdef VBOX_WITH_64_BITS_GUESTS
853	/* Guest - AMD64 mode */
854	# define PGM_GST_TYPE PGM_TYPE_AMD64
855	# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
856	# define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_AMD64_STR(name)
857	# define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_AMD64_STR(name)
858	# define PGM_BTH_NAME(name) PGM_BTH_NAME_AMD64_AMD64(name)
859	# define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_AMD64_AMD64_STR(name)
860	# define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_AMD64_AMD64_STR(name)
861	# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
862	# define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
863	# include "PGMGst.h"
864	# include "PGMBth.h"
865	# undef BTH_PGMPOOLKIND_PT_FOR_BIG
866	# undef BTH_PGMPOOLKIND_PT_FOR_PT
867	# undef PGM_BTH_NAME
868	# undef PGM_BTH_NAME_RC_STR
869	# undef PGM_BTH_NAME_R0_STR
870	# undef PGM_GST_TYPE
871	# undef PGM_GST_NAME
872	# undef PGM_GST_NAME_RC_STR
873	# undef PGM_GST_NAME_R0_STR
874	#endif /* VBOX_WITH_64_BITS_GUESTS */
875
876	#undef PGM_SHW_TYPE
877	#undef PGM_SHW_NAME
878	#undef PGM_SHW_NAME_RC_STR
879	#undef PGM_SHW_NAME_R0_STR
880
881
882	/*
883	* Shadow - Nested paging mode
884	*/
885	#define PGM_SHW_TYPE PGM_TYPE_NESTED
886	#define PGM_SHW_NAME(name) PGM_SHW_NAME_NESTED(name)
887	#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_NESTED_STR(name)
888	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_NESTED_STR(name)
889	#include "PGMShw.h"
890
891	/* Guest - real mode */
892	#define PGM_GST_TYPE PGM_TYPE_REAL
893	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
894	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_REAL_STR(name)
895	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
896	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_REAL(name)
897	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_REAL_STR(name)
898	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_REAL_STR(name)
899	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
900	#include "PGMBth.h"
901	#undef BTH_PGMPOOLKIND_PT_FOR_PT
902	#undef PGM_BTH_NAME
903	#undef PGM_BTH_NAME_RC_STR
904	#undef PGM_BTH_NAME_R0_STR
905	#undef PGM_GST_TYPE
906	#undef PGM_GST_NAME
907	#undef PGM_GST_NAME_RC_STR
908	#undef PGM_GST_NAME_R0_STR
909
910	/* Guest - protected mode */
911	#define PGM_GST_TYPE PGM_TYPE_PROT
912	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
913	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PROT_STR(name)
914	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
915	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_PROT(name)
916	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_PROT_STR(name)
917	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_PROT_STR(name)
918	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
919	#include "PGMBth.h"
920	#undef BTH_PGMPOOLKIND_PT_FOR_PT
921	#undef PGM_BTH_NAME
922	#undef PGM_BTH_NAME_RC_STR
923	#undef PGM_BTH_NAME_R0_STR
924	#undef PGM_GST_TYPE
925	#undef PGM_GST_NAME
926	#undef PGM_GST_NAME_RC_STR
927	#undef PGM_GST_NAME_R0_STR
928
929	/* Guest - 32-bit mode */
930	#define PGM_GST_TYPE PGM_TYPE_32BIT
931	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
932	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_32BIT_STR(name)
933	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
934	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_32BIT(name)
935	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_32BIT_STR(name)
936	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_32BIT_STR(name)
937	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_32BIT_PT
938	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB
939	#include "PGMBth.h"
940	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
941	#undef BTH_PGMPOOLKIND_PT_FOR_PT
942	#undef PGM_BTH_NAME
943	#undef PGM_BTH_NAME_RC_STR
944	#undef PGM_BTH_NAME_R0_STR
945	#undef PGM_GST_TYPE
946	#undef PGM_GST_NAME
947	#undef PGM_GST_NAME_RC_STR
948	#undef PGM_GST_NAME_R0_STR
949
950	/* Guest - PAE mode */
951	#define PGM_GST_TYPE PGM_TYPE_PAE
952	#define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
953	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PAE_STR(name)
954	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PAE_STR(name)
955	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_PAE(name)
956	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_PAE_STR(name)
957	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_PAE_STR(name)
958	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
959	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
960	#include "PGMBth.h"
961	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
962	#undef BTH_PGMPOOLKIND_PT_FOR_PT
963	#undef PGM_BTH_NAME
964	#undef PGM_BTH_NAME_RC_STR
965	#undef PGM_BTH_NAME_R0_STR
966	#undef PGM_GST_TYPE
967	#undef PGM_GST_NAME
968	#undef PGM_GST_NAME_RC_STR
969	#undef PGM_GST_NAME_R0_STR
970
971	#ifdef VBOX_WITH_64_BITS_GUESTS
972	/* Guest - AMD64 mode */
973	# define PGM_GST_TYPE PGM_TYPE_AMD64
974	# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
975	# define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_AMD64_STR(name)
976	# define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_AMD64_STR(name)
977	# define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_AMD64(name)
978	# define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_AMD64_STR(name)
979	# define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_AMD64_STR(name)
980	# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
981	# define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
982	# include "PGMBth.h"
983	# undef BTH_PGMPOOLKIND_PT_FOR_BIG
984	# undef BTH_PGMPOOLKIND_PT_FOR_PT
985	# undef PGM_BTH_NAME
986	# undef PGM_BTH_NAME_RC_STR
987	# undef PGM_BTH_NAME_R0_STR
988	# undef PGM_GST_TYPE
989	# undef PGM_GST_NAME
990	# undef PGM_GST_NAME_RC_STR
991	# undef PGM_GST_NAME_R0_STR
992	#endif /* VBOX_WITH_64_BITS_GUESTS */
993
994	#undef PGM_SHW_TYPE
995	#undef PGM_SHW_NAME
996	#undef PGM_SHW_NAME_RC_STR
997	#undef PGM_SHW_NAME_R0_STR
998
999
1000	/*
1001	* Shadow - EPT
1002	*/
1003	#define PGM_SHW_TYPE PGM_TYPE_EPT
1004	#define PGM_SHW_NAME(name) PGM_SHW_NAME_EPT(name)
1005	#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_EPT_STR(name)
1006	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_EPT_STR(name)
1007	#include "PGMShw.h"
1008
1009	/* Guest - real mode */
1010	#define PGM_GST_TYPE PGM_TYPE_REAL
1011	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
1012	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_REAL_STR(name)
1013	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
1014	#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_REAL(name)
1015	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_REAL_STR(name)
1016	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_REAL_STR(name)
1017	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
1018	#include "PGMBth.h"
1019	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1020	#undef PGM_BTH_NAME
1021	#undef PGM_BTH_NAME_RC_STR
1022	#undef PGM_BTH_NAME_R0_STR
1023	#undef PGM_GST_TYPE
1024	#undef PGM_GST_NAME
1025	#undef PGM_GST_NAME_RC_STR
1026	#undef PGM_GST_NAME_R0_STR
1027
1028	/* Guest - protected mode */
1029	#define PGM_GST_TYPE PGM_TYPE_PROT
1030	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
1031	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PROT_STR(name)
1032	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
1033	#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_PROT(name)
1034	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_PROT_STR(name)
1035	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_PROT_STR(name)
1036	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
1037	#include "PGMBth.h"
1038	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1039	#undef PGM_BTH_NAME
1040	#undef PGM_BTH_NAME_RC_STR
1041	#undef PGM_BTH_NAME_R0_STR
1042	#undef PGM_GST_TYPE
1043	#undef PGM_GST_NAME
1044	#undef PGM_GST_NAME_RC_STR
1045	#undef PGM_GST_NAME_R0_STR
1046
1047	/* Guest - 32-bit mode */
1048	#define PGM_GST_TYPE PGM_TYPE_32BIT
1049	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
1050	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_32BIT_STR(name)
1051	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
1052	#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_32BIT(name)
1053	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_32BIT_STR(name)
1054	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_32BIT_STR(name)
1055	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_32BIT_PT
1056	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB
1057	#include "PGMBth.h"
1058	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
1059	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1060	#undef PGM_BTH_NAME
1061	#undef PGM_BTH_NAME_RC_STR
1062	#undef PGM_BTH_NAME_R0_STR
1063	#undef PGM_GST_TYPE
1064	#undef PGM_GST_NAME
1065	#undef PGM_GST_NAME_RC_STR
1066	#undef PGM_GST_NAME_R0_STR
1067
1068	/* Guest - PAE mode */
1069	#define PGM_GST_TYPE PGM_TYPE_PAE
1070	#define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
1071	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PAE_STR(name)
1072	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PAE_STR(name)
1073	#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_PAE(name)
1074	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_PAE_STR(name)
1075	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_PAE_STR(name)
1076	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
1077	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
1078	#include "PGMBth.h"
1079	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
1080	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1081	#undef PGM_BTH_NAME
1082	#undef PGM_BTH_NAME_RC_STR
1083	#undef PGM_BTH_NAME_R0_STR
1084	#undef PGM_GST_TYPE
1085	#undef PGM_GST_NAME
1086	#undef PGM_GST_NAME_RC_STR
1087	#undef PGM_GST_NAME_R0_STR
1088
1089	#ifdef VBOX_WITH_64_BITS_GUESTS
1090	/* Guest - AMD64 mode */
1091	# define PGM_GST_TYPE PGM_TYPE_AMD64
1092	# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
1093	# define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_AMD64_STR(name)
1094	# define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_AMD64_STR(name)
1095	# define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_AMD64(name)
1096	# define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_AMD64_STR(name)
1097	# define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_AMD64_STR(name)
1098	# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
1099	# define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
1100	# include "PGMBth.h"
1101	# undef BTH_PGMPOOLKIND_PT_FOR_BIG
1102	# undef BTH_PGMPOOLKIND_PT_FOR_PT
1103	# undef PGM_BTH_NAME
1104	# undef PGM_BTH_NAME_RC_STR
1105	# undef PGM_BTH_NAME_R0_STR
1106	# undef PGM_GST_TYPE
1107	# undef PGM_GST_NAME
1108	# undef PGM_GST_NAME_RC_STR
1109	# undef PGM_GST_NAME_R0_STR
1110	#endif /* VBOX_WITH_64_BITS_GUESTS */
1111
1112	#undef PGM_SHW_TYPE
1113	#undef PGM_SHW_NAME
1114	#undef PGM_SHW_NAME_RC_STR
1115	#undef PGM_SHW_NAME_R0_STR
1116
1117
1118
1119	/**
1120	* Initiates the paging of VM.
1121	*
1122	* @returns VBox status code.
1123	* @param pVM Pointer to VM structure.
1124	*/
1125	VMMR3DECL(int) PGMR3Init(PVM pVM)
1126	{
1127	LogFlow(("PGMR3Init:\n"));
1128
1129	/*
1130	* Assert alignment and sizes.
1131	*/
1132	AssertRelease(sizeof(pVM->pgm.s) <= sizeof(pVM->pgm.padding));
1133
1134	/*
1135	* Init the structure.
1136	*/
1137	pVM->pgm.s.offVM = RT_OFFSETOF(VM, pgm.s);
1138	pVM->pgm.s.offVCpu = RT_OFFSETOF(VMCPU, pgm.s);
1139	pVM->pgm.s.enmShadowMode = PGMMODE_INVALID;
1140	pVM->pgm.s.enmGuestMode = PGMMODE_INVALID;
1141	pVM->pgm.s.enmHostMode = SUPPAGINGMODE_INVALID;
1142	pVM->pgm.s.GCPhysCR3 = NIL_RTGCPHYS;
1143	pVM->pgm.s.GCPhysGstCR3Monitored = NIL_RTGCPHYS;
1144	pVM->pgm.s.fA20Enabled = true;
1145	pVM->pgm.s.GCPhys4MBPSEMask = RT_BIT_64(32) - 1; /* default; checked later */
1146	pVM->pgm.s.pGstPaePdptR3 = NULL;
1147	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
1148	pVM->pgm.s.pGstPaePdptR0 = NIL_RTR0PTR;
1149	#endif
1150	pVM->pgm.s.pGstPaePdptRC = NIL_RTRCPTR;
1151	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.apGstPaePDsR3); i++)
1152	{
1153	pVM->pgm.s.apGstPaePDsR3[i] = NULL;
1154	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
1155	pVM->pgm.s.apGstPaePDsR0[i] = NIL_RTR0PTR;
1156	#endif
1157	pVM->pgm.s.apGstPaePDsRC[i] = NIL_RTRCPTR;
1158	pVM->pgm.s.aGCPhysGstPaePDs[i] = NIL_RTGCPHYS;
1159	pVM->pgm.s.aGCPhysGstPaePDsMonitored[i] = NIL_RTGCPHYS;
1160	}
1161
1162	#ifdef VBOX_STRICT
1163	VMR3AtStateRegister(pVM, pgmR3ResetNoMorePhysWritesFlag, NULL);
1164	#endif
1165
1166	/*
1167	* Get the configured RAM size - to estimate saved state size.
1168	*/
1169	uint64_t cbRam;
1170	int rc = CFGMR3QueryU64(CFGMR3GetRoot(pVM), "RamSize", &cbRam);
1171	if (rc == VERR_CFGM_VALUE_NOT_FOUND)
1172	cbRam = pVM->pgm.s.cbRamSize = 0;
1173	else if (RT_SUCCESS(rc))
1174	{
1175	if (cbRam < PAGE_SIZE)
1176	cbRam = 0;
1177	cbRam = RT_ALIGN_64(cbRam, PAGE_SIZE);
1178	pVM->pgm.s.cbRamSize = (RTUINT)cbRam;
1179	}
1180	else
1181	{
1182	AssertMsgFailed(("Configuration error: Failed to query integer \"RamSize\", rc=%Rrc.\n", rc));
1183	return rc;
1184	}
1185
1186	/*
1187	* Register saved state data unit.
1188	*/
1189	rc = SSMR3RegisterInternal(pVM, "pgm", 1, PGM_SAVED_STATE_VERSION, (size_t)cbRam + sizeof(PGM),
1190	NULL, pgmR3Save, NULL,
1191	NULL, pgmR3Load, NULL);
1192	if (RT_FAILURE(rc))
1193	return rc;
1194
1195	/*
1196	* Initialize the PGM critical section and flush the phys TLBs
1197	*/
1198	rc = PDMR3CritSectInit(pVM, &pVM->pgm.s.CritSect, "PGM");
1199	AssertRCReturn(rc, rc);
1200
1201	PGMR3PhysChunkInvalidateTLB(pVM);
1202	PGMPhysInvalidatePageR3MapTLB(pVM);
1203	PGMPhysInvalidatePageR0MapTLB(pVM);
1204	PGMPhysInvalidatePageGCMapTLB(pVM);
1205
1206	/*
1207	* Trees
1208	*/
1209	rc = MMHyperAlloc(pVM, sizeof(PGMTREES), 0, MM_TAG_PGM, (void **)&pVM->pgm.s.pTreesR3);
1210	if (RT_SUCCESS(rc))
1211	{
1212	pVM->pgm.s.pTreesR0 = MMHyperR3ToR0(pVM, pVM->pgm.s.pTreesR3);
1213	pVM->pgm.s.pTreesRC = MMHyperR3ToRC(pVM, pVM->pgm.s.pTreesR3);
1214
1215	/*
1216	* Alocate the zero page.
1217	*/
1218	rc = MMHyperAlloc(pVM, PAGE_SIZE, PAGE_SIZE, MM_TAG_PGM, &pVM->pgm.s.pvZeroPgR3);
1219	}
1220	if (RT_SUCCESS(rc))
1221	{
1222	pVM->pgm.s.pvZeroPgGC = MMHyperR3ToRC(pVM, pVM->pgm.s.pvZeroPgR3);
1223	pVM->pgm.s.pvZeroPgR0 = MMHyperR3ToR0(pVM, pVM->pgm.s.pvZeroPgR3);
1224	AssertRelease(pVM->pgm.s.pvZeroPgR0 != NIL_RTHCPHYS);
1225	pVM->pgm.s.HCPhysZeroPg = MMR3HyperHCVirt2HCPhys(pVM, pVM->pgm.s.pvZeroPgR3);
1226	AssertRelease(pVM->pgm.s.HCPhysZeroPg != NIL_RTHCPHYS);
1227
1228	/*
1229	* Init the paging.
1230	*/
1231	rc = pgmR3InitPaging(pVM);
1232	}
1233	if (RT_SUCCESS(rc))
1234	{
1235	/*
1236	* Init the page pool.
1237	*/
1238	rc = pgmR3PoolInit(pVM);
1239	}
1240	if (RT_SUCCESS(rc))
1241	{
1242	/*
1243	* Info & statistics
1244	*/
1245	DBGFR3InfoRegisterInternal(pVM, "mode",
1246	"Shows the current paging mode. "
1247	"Recognizes 'all', 'guest', 'shadow' and 'host' as arguments, defaulting to 'all' if nothing's given.",
1248	pgmR3InfoMode);
1249	DBGFR3InfoRegisterInternal(pVM, "pgmcr3",
1250	"Dumps all the entries in the top level paging table. No arguments.",
1251	pgmR3InfoCr3);
1252	DBGFR3InfoRegisterInternal(pVM, "phys",
1253	"Dumps all the physical address ranges. No arguments.",
1254	pgmR3PhysInfo);
1255	DBGFR3InfoRegisterInternal(pVM, "handlers",
1256	"Dumps physical, virtual and hyper virtual handlers. "
1257	"Pass 'phys', 'virt', 'hyper' as argument if only one kind is wanted."
1258	"Add 'nost' if the statistics are unwanted, use together with 'all' or explicit selection.",
1259	pgmR3InfoHandlers);
1260	DBGFR3InfoRegisterInternal(pVM, "mappings",
1261	"Dumps guest mappings.",
1262	pgmR3MapInfo);
1263
1264	STAM_REL_REG(pVM, &pVM->pgm.s.cGuestModeChanges, STAMTYPE_COUNTER, "/PGM/cGuestModeChanges", STAMUNIT_OCCURENCES, "Number of guest mode changes.");
1265	#ifdef VBOX_WITH_STATISTICS
1266	pgmR3InitStats(pVM);
1267	#endif
1268	#ifdef VBOX_WITH_DEBUGGER
1269	/*
1270	* Debugger commands.
1271	*/
1272	static bool fRegisteredCmds = false;
1273	if (!fRegisteredCmds)
1274	{
1275	int rc = DBGCRegisterCommands(&g_aCmds[0], RT_ELEMENTS(g_aCmds));
1276	if (RT_SUCCESS(rc))
1277	fRegisteredCmds = true;
1278	}
1279	#endif
1280	return VINF_SUCCESS;
1281	}
1282
1283	/* Almost no cleanup necessary, MM frees all memory. */
1284	PDMR3CritSectDelete(&pVM->pgm.s.CritSect);
1285
1286	return rc;
1287	}
1288
1289
1290	/**
1291	* Initializes the per-VCPU PGM.
1292	*
1293	* @returns VBox status code.
1294	* @param pVM The VM to operate on.
1295	*/
1296	VMMR3DECL(int) PGMR3InitCPU(PVM pVM)
1297	{
1298	LogFlow(("PGMR3InitCPU\n"));
1299	return VINF_SUCCESS;
1300	}
1301
1302
1303	/**
1304	* Init paging.
1305	*
1306	* Since we need to check what mode the host is operating in before we can choose
1307	* the right paging functions for the host we have to delay this until R0 has
1308	* been initialized.
1309	*
1310	* @returns VBox status code.
1311	* @param pVM VM handle.
1312	*/
1313	static int pgmR3InitPaging(PVM pVM)
1314	{
1315	/*
1316	* Force a recalculation of modes and switcher so everyone gets notified.
1317	*/
1318	pVM->pgm.s.enmShadowMode = PGMMODE_INVALID;
1319	pVM->pgm.s.enmGuestMode = PGMMODE_INVALID;
1320	pVM->pgm.s.enmHostMode = SUPPAGINGMODE_INVALID;
1321
1322	/*
1323	* Allocate static mapping space for whatever the cr3 register
1324	* points to and in the case of PAE mode to the 4 PDs.
1325	*/
1326	int rc = MMR3HyperReserve(pVM, PAGE_SIZE * 5, "CR3 mapping", &pVM->pgm.s.GCPtrCR3Mapping);
1327	if (RT_FAILURE(rc))
1328	{
1329	AssertMsgFailed(("Failed to reserve two pages for cr mapping in HMA, rc=%Rrc\n", rc));
1330	return rc;
1331	}
1332	MMR3HyperReserve(pVM, PAGE_SIZE, "fence", NULL);
1333
1334	/*
1335	* Allocate pages for the three possible intermediate contexts
1336	* (AMD64, PAE and plain 32-Bit). We maintain all three contexts
1337	* for the sake of simplicity. The AMD64 uses the PAE for the
1338	* lower levels, making the total number of pages 11 (3 + 7 + 1).
1339	*
1340	* We assume that two page tables will be enought for the core code
1341	* mappings (HC virtual and identity).
1342	*/
1343	pVM->pgm.s.pInterPD = (PX86PD)MMR3PageAllocLow(pVM);
1344	pVM->pgm.s.apInterPTs[0] = (PX86PT)MMR3PageAllocLow(pVM);
1345	pVM->pgm.s.apInterPTs[1] = (PX86PT)MMR3PageAllocLow(pVM);
1346	pVM->pgm.s.apInterPaePTs[0] = (PX86PTPAE)MMR3PageAlloc(pVM);
1347	pVM->pgm.s.apInterPaePTs[1] = (PX86PTPAE)MMR3PageAlloc(pVM);
1348	pVM->pgm.s.apInterPaePDs[0] = (PX86PDPAE)MMR3PageAlloc(pVM);
1349	pVM->pgm.s.apInterPaePDs[1] = (PX86PDPAE)MMR3PageAlloc(pVM);
1350	pVM->pgm.s.apInterPaePDs[2] = (PX86PDPAE)MMR3PageAlloc(pVM);
1351	pVM->pgm.s.apInterPaePDs[3] = (PX86PDPAE)MMR3PageAlloc(pVM);
1352	pVM->pgm.s.pInterPaePDPT = (PX86PDPT)MMR3PageAllocLow(pVM);
1353	pVM->pgm.s.pInterPaePDPT64 = (PX86PDPT)MMR3PageAllocLow(pVM);
1354	pVM->pgm.s.pInterPaePML4 = (PX86PML4)MMR3PageAllocLow(pVM);
1355	if ( !pVM->pgm.s.pInterPD
1356	\|\| !pVM->pgm.s.apInterPTs[0]
1357	\|\| !pVM->pgm.s.apInterPTs[1]
1358	\|\| !pVM->pgm.s.apInterPaePTs[0]
1359	\|\| !pVM->pgm.s.apInterPaePTs[1]
1360	\|\| !pVM->pgm.s.apInterPaePDs[0]
1361	\|\| !pVM->pgm.s.apInterPaePDs[1]
1362	\|\| !pVM->pgm.s.apInterPaePDs[2]
1363	\|\| !pVM->pgm.s.apInterPaePDs[3]
1364	\|\| !pVM->pgm.s.pInterPaePDPT
1365	\|\| !pVM->pgm.s.pInterPaePDPT64
1366	\|\| !pVM->pgm.s.pInterPaePML4)
1367	{
1368	AssertMsgFailed(("Failed to allocate pages for the intermediate context!\n"));
1369	return VERR_NO_PAGE_MEMORY;
1370	}
1371
1372	pVM->pgm.s.HCPhysInterPD = MMPage2Phys(pVM, pVM->pgm.s.pInterPD);
1373	AssertRelease(pVM->pgm.s.HCPhysInterPD != NIL_RTHCPHYS && !(pVM->pgm.s.HCPhysInterPD & PAGE_OFFSET_MASK));
1374	pVM->pgm.s.HCPhysInterPaePDPT = MMPage2Phys(pVM, pVM->pgm.s.pInterPaePDPT);
1375	AssertRelease(pVM->pgm.s.HCPhysInterPaePDPT != NIL_RTHCPHYS && !(pVM->pgm.s.HCPhysInterPaePDPT & PAGE_OFFSET_MASK));
1376	pVM->pgm.s.HCPhysInterPaePML4 = MMPage2Phys(pVM, pVM->pgm.s.pInterPaePML4);
1377	AssertRelease(pVM->pgm.s.HCPhysInterPaePML4 != NIL_RTHCPHYS && !(pVM->pgm.s.HCPhysInterPaePML4 & PAGE_OFFSET_MASK));
1378
1379	/*
1380	* Initialize the pages, setting up the PML4 and PDPT for repetitive 4GB action.
1381	*/
1382	ASMMemZeroPage(pVM->pgm.s.pInterPD);
1383	ASMMemZeroPage(pVM->pgm.s.apInterPTs[0]);
1384	ASMMemZeroPage(pVM->pgm.s.apInterPTs[1]);
1385
1386	ASMMemZeroPage(pVM->pgm.s.apInterPaePTs[0]);
1387	ASMMemZeroPage(pVM->pgm.s.apInterPaePTs[1]);
1388
1389	ASMMemZeroPage(pVM->pgm.s.pInterPaePDPT);
1390	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.apInterPaePDs); i++)
1391	{
1392	ASMMemZeroPage(pVM->pgm.s.apInterPaePDs[i]);
1393	pVM->pgm.s.pInterPaePDPT->a[i].u = X86_PDPE_P \| PGM_PLXFLAGS_PERMANENT
1394	\| MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[i]);
1395	}
1396
1397	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.pInterPaePDPT64->a); i++)
1398	{
1399	const unsigned iPD = i % RT_ELEMENTS(pVM->pgm.s.apInterPaePDs);
1400	pVM->pgm.s.pInterPaePDPT64->a[i].u = X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_A \| PGM_PLXFLAGS_PERMANENT
1401	\| MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[iPD]);
1402	}
1403
1404	RTHCPHYS HCPhysInterPaePDPT64 = MMPage2Phys(pVM, pVM->pgm.s.pInterPaePDPT64);
1405	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.pInterPaePML4->a); i++)
1406	pVM->pgm.s.pInterPaePML4->a[i].u = X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_A \| PGM_PLXFLAGS_PERMANENT
1407	\| HCPhysInterPaePDPT64;
1408
1409	/*
1410	* Allocate pages for the three possible guest contexts (AMD64, PAE and plain 32-Bit).
1411	* We allocate pages for all three posibilities in order to simplify mappings and
1412	* avoid resource failure during mode switches. So, we need to cover all levels of the
1413	* of the first 4GB down to PD level.
1414	* As with the intermediate context, AMD64 uses the PAE PDPT and PDs.
1415	*/
1416	#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
1417	pVM->pgm.s.pShw32BitPdR3 = (PX86PD)MMR3PageAllocLow(pVM);
1418	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
1419	pVM->pgm.s.pShw32BitPdR0 = (uintptr_t)pVM->pgm.s.pShw32BitPdR3;
1420	# endif
1421	pVM->pgm.s.apShwPaePDsR3[0] = (PX86PDPAE)MMR3PageAlloc(pVM);
1422	pVM->pgm.s.apShwPaePDsR3[1] = (PX86PDPAE)MMR3PageAlloc(pVM);
1423	AssertRelease((uintptr_t)pVM->pgm.s.apShwPaePDsR3[0] + PAGE_SIZE == (uintptr_t)pVM->pgm.s.apShwPaePDsR3[1]);
1424	pVM->pgm.s.apShwPaePDsR3[2] = (PX86PDPAE)MMR3PageAlloc(pVM);
1425	AssertRelease((uintptr_t)pVM->pgm.s.apShwPaePDsR3[1] + PAGE_SIZE == (uintptr_t)pVM->pgm.s.apShwPaePDsR3[2]);
1426	pVM->pgm.s.apShwPaePDsR3[3] = (PX86PDPAE)MMR3PageAlloc(pVM);
1427	AssertRelease((uintptr_t)pVM->pgm.s.apShwPaePDsR3[2] + PAGE_SIZE == (uintptr_t)pVM->pgm.s.apShwPaePDsR3[3]);
1428	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
1429	pVM->pgm.s.apShwPaePDsR0[0] = (uintptr_t)pVM->pgm.s.apShwPaePDsR3[0];
1430	pVM->pgm.s.apShwPaePDsR0[1] = (uintptr_t)pVM->pgm.s.apShwPaePDsR3[1];
1431	pVM->pgm.s.apShwPaePDsR0[2] = (uintptr_t)pVM->pgm.s.apShwPaePDsR3[2];
1432	pVM->pgm.s.apShwPaePDsR0[3] = (uintptr_t)pVM->pgm.s.apShwPaePDsR3[3];
1433	# endif
1434	pVM->pgm.s.pShwPaePdptR3 = (PX86PDPT)MMR3PageAllocLow(pVM);
1435	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
1436	pVM->pgm.s.pShwPaePdptR0 = (uintptr_t)pVM->pgm.s.pShwPaePdptR3;
1437	# endif
1438	#endif /* VBOX_WITH_PGMPOOL_PAGING_ONLY */
1439	pVM->pgm.s.pShwNestedRootR3 = MMR3PageAllocLow(pVM);
1440	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
1441	pVM->pgm.s.pShwNestedRootR0 = (uintptr_t)pVM->pgm.s.pShwNestedRootR3;
1442	#endif
1443
1444	#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
1445	if (!pVM->pgm.s.pShwNestedRootR3)
1446	#else
1447	if ( !pVM->pgm.s.pShw32BitPdR3
1448	\|\| !pVM->pgm.s.apShwPaePDsR3[0]
1449	\|\| !pVM->pgm.s.apShwPaePDsR3[1]
1450	\|\| !pVM->pgm.s.apShwPaePDsR3[2]
1451	\|\| !pVM->pgm.s.apShwPaePDsR3[3]
1452	\|\| !pVM->pgm.s.pShwPaePdptR3
1453	\|\| !pVM->pgm.s.pShwNestedRootR3)
1454	#endif
1455	{
1456	AssertMsgFailed(("Failed to allocate pages for the intermediate context!\n"));
1457	return VERR_NO_PAGE_MEMORY;
1458	}
1459
1460	/* get physical addresses. */
1461	#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
1462	pVM->pgm.s.HCPhysShw32BitPD = MMPage2Phys(pVM, pVM->pgm.s.pShw32BitPdR3);
1463	Assert(MMPagePhys2Page(pVM, pVM->pgm.s.HCPhysShw32BitPD) == pVM->pgm.s.pShw32BitPdR3);
1464	pVM->pgm.s.aHCPhysPaePDs[0] = MMPage2Phys(pVM, pVM->pgm.s.apShwPaePDsR3[0]);
1465	pVM->pgm.s.aHCPhysPaePDs[1] = MMPage2Phys(pVM, pVM->pgm.s.apShwPaePDsR3[1]);
1466	pVM->pgm.s.aHCPhysPaePDs[2] = MMPage2Phys(pVM, pVM->pgm.s.apShwPaePDsR3[2]);
1467	pVM->pgm.s.aHCPhysPaePDs[3] = MMPage2Phys(pVM, pVM->pgm.s.apShwPaePDsR3[3]);
1468	pVM->pgm.s.HCPhysShwPaePdpt = MMPage2Phys(pVM, pVM->pgm.s.pShwPaePdptR3);
1469	#endif
1470	pVM->pgm.s.HCPhysShwNestedRoot = MMPage2Phys(pVM, pVM->pgm.s.pShwNestedRootR3);
1471
1472	/*
1473	* Initialize the pages, setting up the PML4 and PDPT for action below 4GB.
1474	*/
1475	#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
1476	ASMMemZero32(pVM->pgm.s.pShw32BitPdR3, PAGE_SIZE);
1477	ASMMemZero32(pVM->pgm.s.pShwPaePdptR3, PAGE_SIZE);
1478	#endif
1479	ASMMemZero32(pVM->pgm.s.pShwNestedRootR3, PAGE_SIZE);
1480	#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
1481	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.apShwPaePDsR3); i++)
1482	{
1483	ASMMemZero32(pVM->pgm.s.apShwPaePDsR3[i], PAGE_SIZE);
1484	pVM->pgm.s.pShwPaePdptR3->a[i].u = X86_PDPE_P \| PGM_PLXFLAGS_PERMANENT \| pVM->pgm.s.aHCPhysPaePDs[i];
1485	/* The flags will be corrected when entering and leaving long mode. */
1486	}
1487
1488	CPUMSetHyperCR3(pVM, (uint32_t)pVM->pgm.s.HCPhysShw32BitPD);
1489	#endif
1490
1491	/*
1492	* Initialize paging workers and mode from current host mode
1493	* and the guest running in real mode.
1494	*/
1495	pVM->pgm.s.enmHostMode = SUPGetPagingMode();
1496	switch (pVM->pgm.s.enmHostMode)
1497	{
1498	case SUPPAGINGMODE_32_BIT:
1499	case SUPPAGINGMODE_32_BIT_GLOBAL:
1500	case SUPPAGINGMODE_PAE:
1501	case SUPPAGINGMODE_PAE_GLOBAL:
1502	case SUPPAGINGMODE_PAE_NX:
1503	case SUPPAGINGMODE_PAE_GLOBAL_NX:
1504	break;
1505
1506	case SUPPAGINGMODE_AMD64:
1507	case SUPPAGINGMODE_AMD64_GLOBAL:
1508	case SUPPAGINGMODE_AMD64_NX:
1509	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
1510	#ifndef VBOX_WITH_HYBRID_32BIT_KERNEL
1511	if (ARCH_BITS != 64)
1512	{
1513	AssertMsgFailed(("Host mode %d (64-bit) is not supported by non-64bit builds\n", pVM->pgm.s.enmHostMode));
1514	LogRel(("Host mode %d (64-bit) is not supported by non-64bit builds\n", pVM->pgm.s.enmHostMode));
1515	return VERR_PGM_UNSUPPORTED_HOST_PAGING_MODE;
1516	}
1517	#endif
1518	break;
1519	default:
1520	AssertMsgFailed(("Host mode %d is not supported\n", pVM->pgm.s.enmHostMode));
1521	return VERR_PGM_UNSUPPORTED_HOST_PAGING_MODE;
1522	}
1523	rc = pgmR3ModeDataInit(pVM, false /* don't resolve GC and R0 syms yet */);
1524	if (RT_SUCCESS(rc))
1525	rc = PGMR3ChangeMode(pVM, PGMMODE_REAL);
1526	if (RT_SUCCESS(rc))
1527	{
1528	LogFlow(("pgmR3InitPaging: returns successfully\n"));
1529	#if HC_ARCH_BITS == 64
1530	# ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
1531	LogRel(("Debug: HCPhysShw32BitPD=%RHp aHCPhysPaePDs={%RHp,%RHp,%RHp,%RHp} HCPhysShwPaePdpt=%RHp HCPhysShwPaePml4=%RHp\n",
1532	pVM->pgm.s.HCPhysShw32BitPD,
1533	pVM->pgm.s.aHCPhysPaePDs[0], pVM->pgm.s.aHCPhysPaePDs[1], pVM->pgm.s.aHCPhysPaePDs[2], pVM->pgm.s.aHCPhysPaePDs[3],
1534	pVM->pgm.s.HCPhysShwPaePdpt,
1535	pVM->pgm.s.HCPhysShwPaePml4));
1536	# endif
1537	LogRel(("Debug: HCPhysInterPD=%RHp HCPhysInterPaePDPT=%RHp HCPhysInterPaePML4=%RHp\n",
1538	pVM->pgm.s.HCPhysInterPD, pVM->pgm.s.HCPhysInterPaePDPT, pVM->pgm.s.HCPhysInterPaePML4));
1539	LogRel(("Debug: apInterPTs={%RHp,%RHp} apInterPaePTs={%RHp,%RHp} apInterPaePDs={%RHp,%RHp,%RHp,%RHp} pInterPaePDPT64=%RHp\n",
1540	MMPage2Phys(pVM, pVM->pgm.s.apInterPTs[0]), MMPage2Phys(pVM, pVM->pgm.s.apInterPTs[1]),
1541	MMPage2Phys(pVM, pVM->pgm.s.apInterPaePTs[0]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePTs[1]),
1542	MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[0]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[1]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[2]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[3]),
1543	MMPage2Phys(pVM, pVM->pgm.s.pInterPaePDPT64)));
1544	#endif
1545
1546	return VINF_SUCCESS;
1547	}
1548
1549	LogFlow(("pgmR3InitPaging: returns %Rrc\n", rc));
1550	return rc;
1551	}
1552
1553
1554	#ifdef VBOX_WITH_STATISTICS
1555	/**
1556	* Init statistics
1557	*/
1558	static void pgmR3InitStats(PVM pVM)
1559	{
1560	PPGM pPGM = &pVM->pgm.s;
1561	unsigned i;
1562
1563	/*
1564	* Note! The layout of this function matches the member layout exactly!
1565	*/
1566
1567	/* Common - misc variables */
1568	STAM_REG(pVM, &pPGM->cAllPages, STAMTYPE_U32, "/PGM/Page/cAllPages", STAMUNIT_OCCURENCES, "The total number of pages.");
1569	STAM_REG(pVM, &pPGM->cPrivatePages, STAMTYPE_U32, "/PGM/Page/cPrivatePages", STAMUNIT_OCCURENCES, "The number of private pages.");
1570	STAM_REG(pVM, &pPGM->cSharedPages, STAMTYPE_U32, "/PGM/Page/cSharedPages", STAMUNIT_OCCURENCES, "The number of shared pages.");
1571	STAM_REG(pVM, &pPGM->cZeroPages, STAMTYPE_U32, "/PGM/Page/cZeroPages", STAMUNIT_OCCURENCES, "The number of zero backed pages.");
1572	STAM_REG(pVM, &pPGM->ChunkR3Map.c, STAMTYPE_U32, "/PGM/ChunkR3Map/c", STAMUNIT_OCCURENCES, "Number of mapped chunks.");
1573	STAM_REG(pVM, &pPGM->ChunkR3Map.cMax, STAMTYPE_U32, "/PGM/ChunkR3Map/cMax", STAMUNIT_OCCURENCES, "Maximum number of mapped chunks.");
1574
1575	/* Common - stats */
1576	#ifdef PGMPOOL_WITH_GCPHYS_TRACKING
1577	STAM_REG(pVM, &pPGM->StatTrackVirgin, STAMTYPE_COUNTER, "/PGM/Track/Virgin", STAMUNIT_OCCURENCES, "The number of first time shadowings");
1578	STAM_REG(pVM, &pPGM->StatTrackAliased, STAMTYPE_COUNTER, "/PGM/Track/Aliased", STAMUNIT_OCCURENCES, "The number of times switching to cRef2, i.e. the page is being shadowed by two PTs.");
1579	STAM_REG(pVM, &pPGM->StatTrackAliasedMany, STAMTYPE_COUNTER, "/PGM/Track/AliasedMany", STAMUNIT_OCCURENCES, "The number of times we're tracking using cRef2.");
1580	STAM_REG(pVM, &pPGM->StatTrackAliasedLots, STAMTYPE_COUNTER, "/PGM/Track/AliasedLots", STAMUNIT_OCCURENCES, "The number of times we're hitting pages which has overflowed cRef2");
1581	STAM_REG(pVM, &pPGM->StatTrackOverflows, STAMTYPE_COUNTER, "/PGM/Track/Overflows", STAMUNIT_OCCURENCES, "The number of times the extent list grows to long.");
1582	STAM_REG(pVM, &pPGM->StatTrackDeref, STAMTYPE_PROFILE, "/PGM/Track/Deref", STAMUNIT_OCCURENCES, "Profiling of SyncPageWorkerTrackDeref (expensive).");
1583	#endif
1584	for (i = 0; i < RT_ELEMENTS(pPGM->StatSyncPtPD); i++)
1585	STAMR3RegisterF(pVM, &pPGM->StatSyncPtPD[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
1586	"The number of SyncPT per PD n.", "/PGM/PDSyncPT/%04X", i);
1587	for (i = 0; i < RT_ELEMENTS(pPGM->StatSyncPagePD); i++)
1588	STAMR3RegisterF(pVM, &pPGM->StatSyncPagePD[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
1589	"The number of SyncPage per PD n.", "/PGM/PDSyncPage/%04X", i);
1590
1591	/* R3 only: */
1592	STAM_REG(pVM, &pPGM->StatR3DetectedConflicts, STAMTYPE_COUNTER, "/PGM/R3/DetectedConflicts", STAMUNIT_OCCURENCES, "The number of times PGMR3CheckMappingConflicts() detected a conflict.");
1593	STAM_REG(pVM, &pPGM->StatR3ResolveConflict, STAMTYPE_PROFILE, "/PGM/R3/ResolveConflict", STAMUNIT_TICKS_PER_CALL, "pgmR3SyncPTResolveConflict() profiling (includes the entire relocation).");
1594	STAM_REG(pVM, &pPGM->StatR3GuestPDWrite, STAMTYPE_COUNTER, "/PGM/R3/PDWrite", STAMUNIT_OCCURENCES, "The total number of times pgmHCGuestPDWriteHandler() was called.");
1595	STAM_REG(pVM, &pPGM->StatR3GuestPDWriteConflict, STAMTYPE_COUNTER, "/PGM/R3/PDWriteConflict", STAMUNIT_OCCURENCES, "The number of times pgmHCGuestPDWriteHandler() detected a conflict.");
1596	STAM_REG(pVM, &pPGM->StatR3DynRamTotal, STAMTYPE_COUNTER, "/PGM/DynAlloc/TotalAlloc", STAMUNIT_MEGABYTES, "Allocated MBs of guest ram.");
1597	STAM_REG(pVM, &pPGM->StatR3DynRamGrow, STAMTYPE_COUNTER, "/PGM/DynAlloc/Grow", STAMUNIT_OCCURENCES, "Nr of pgmr3PhysGrowRange calls.");
1598
1599	/* R0 only: */
1600	STAM_REG(pVM, &pPGM->StatR0DynMapMigrateInvlPg, STAMTYPE_COUNTER, "/PGM/R0/DynMapMigrateInvlPg", STAMUNIT_OCCURENCES, "invlpg count in PGMDynMapMigrateAutoSet.");
1601	STAM_REG(pVM, &pPGM->StatR0DynMapGCPageInl, STAMTYPE_PROFILE, "/PGM/R0/DynMapPageGCPageInl", STAMUNIT_TICKS_PER_CALL, "Calls to pgmR0DynMapGCPageInlined.");
1602	STAM_REG(pVM, &pPGM->StatR0DynMapGCPageInlHits, STAMTYPE_COUNTER, "/PGM/R0/DynMapPageGCPageInl/Hits", STAMUNIT_OCCURENCES, "Hash table lookup hits.");
1603	STAM_REG(pVM, &pPGM->StatR0DynMapGCPageInlMisses, STAMTYPE_COUNTER, "/PGM/R0/DynMapPageGCPageInl/Misses", STAMUNIT_OCCURENCES, "Misses that falls back to code common with PGMDynMapHCPage.");
1604	STAM_REG(pVM, &pPGM->StatR0DynMapGCPageInlRamHits, STAMTYPE_COUNTER, "/PGM/R0/DynMapPageGCPageInl/RamHits", STAMUNIT_OCCURENCES, "1st ram range hits.");
1605	STAM_REG(pVM, &pPGM->StatR0DynMapGCPageInlRamMisses, STAMTYPE_COUNTER, "/PGM/R0/DynMapPageGCPageInl/RamMisses", STAMUNIT_OCCURENCES, "1st ram range misses, takes slow path.");
1606	STAM_REG(pVM, &pPGM->StatR0DynMapHCPageInl, STAMTYPE_PROFILE, "/PGM/R0/DynMapPageHCPageInl", STAMUNIT_TICKS_PER_CALL, "Calls to pgmR0DynMapHCPageInlined.");
1607	STAM_REG(pVM, &pPGM->StatR0DynMapHCPageInlHits, STAMTYPE_COUNTER, "/PGM/R0/DynMapPageHCPageInl/Hits", STAMUNIT_OCCURENCES, "Hash table lookup hits.");
1608	STAM_REG(pVM, &pPGM->StatR0DynMapHCPageInlMisses, STAMTYPE_COUNTER, "/PGM/R0/DynMapPageHCPageInl/Misses", STAMUNIT_OCCURENCES, "Misses that falls back to code common with PGMDynMapHCPage.");
1609	STAM_REG(pVM, &pPGM->StatR0DynMapPage, STAMTYPE_COUNTER, "/PGM/R0/DynMapPage", STAMUNIT_OCCURENCES, "Calls to pgmR0DynMapPage");
1610	STAM_REG(pVM, &pPGM->StatR0DynMapSetOptimize, STAMTYPE_COUNTER, "/PGM/R0/DynMapPage/SetOptimize", STAMUNIT_OCCURENCES, "Calls to pgmDynMapOptimizeAutoSet.");
1611	STAM_REG(pVM, &pPGM->StatR0DynMapSetSearchFlushes, STAMTYPE_COUNTER, "/PGM/R0/DynMapPage/SetSearchFlushes",STAMUNIT_OCCURENCES, "Set search restorting to subset flushes.");
1612	STAM_REG(pVM, &pPGM->StatR0DynMapSetSearchHits, STAMTYPE_COUNTER, "/PGM/R0/DynMapPage/SetSearchHits", STAMUNIT_OCCURENCES, "Set search hits.");
1613	STAM_REG(pVM, &pPGM->StatR0DynMapSetSearchMisses, STAMTYPE_COUNTER, "/PGM/R0/DynMapPage/SetSearchMisses", STAMUNIT_OCCURENCES, "Set search misses.");
1614	STAM_REG(pVM, &pPGM->StatR0DynMapHCPage, STAMTYPE_PROFILE, "/PGM/R0/DynMapPage/HCPage", STAMUNIT_TICKS_PER_CALL, "Calls to PGMDynMapHCPage (ring-0).");
1615	STAM_REG(pVM, &pPGM->StatR0DynMapPageHits0, STAMTYPE_COUNTER, "/PGM/R0/DynMapPage/Hits0", STAMUNIT_OCCURENCES, "Hits at iPage+0");
1616	STAM_REG(pVM, &pPGM->StatR0DynMapPageHits1, STAMTYPE_COUNTER, "/PGM/R0/DynMapPage/Hits1", STAMUNIT_OCCURENCES, "Hits at iPage+1");
1617	STAM_REG(pVM, &pPGM->StatR0DynMapPageHits2, STAMTYPE_COUNTER, "/PGM/R0/DynMapPage/Hits2", STAMUNIT_OCCURENCES, "Hits at iPage+2");
1618	STAM_REG(pVM, &pPGM->StatR0DynMapPageInvlPg, STAMTYPE_COUNTER, "/PGM/R0/DynMapPage/InvlPg", STAMUNIT_OCCURENCES, "invlpg count in pgmR0DynMapPageSlow.");
1619	STAM_REG(pVM, &pPGM->StatR0DynMapPageSlow, STAMTYPE_COUNTER, "/PGM/R0/DynMapPage/Slow", STAMUNIT_OCCURENCES, "Calls to pgmR0DynMapPageSlow - subtract this from pgmR0DynMapPage to get 1st level hits.");
1620	STAM_REG(pVM, &pPGM->StatR0DynMapPageSlowLoopHits, STAMTYPE_COUNTER, "/PGM/R0/DynMapPage/SlowLoopHits" , STAMUNIT_OCCURENCES, "Hits in the loop path.");
1621	STAM_REG(pVM, &pPGM->StatR0DynMapPageSlowLoopMisses, STAMTYPE_COUNTER, "/PGM/R0/DynMapPage/SlowLoopMisses", STAMUNIT_OCCURENCES, "Misses in the loop path. NonLoopMisses = Slow - SlowLoopHit - SlowLoopMisses");
1622	//STAM_REG(pVM, &pPGM->StatR0DynMapPageSlowLostHits, STAMTYPE_COUNTER, "/PGM/R0/DynMapPage/SlowLostHits", STAMUNIT_OCCURENCES, "Lost hits.");
1623	STAM_REG(pVM, &pPGM->StatR0DynMapSubsets, STAMTYPE_COUNTER, "/PGM/R0/Subsets", STAMUNIT_OCCURENCES, "Times PGMDynMapPushAutoSubset was called.");
1624	STAM_REG(pVM, &pPGM->StatR0DynMapPopFlushes, STAMTYPE_COUNTER, "/PGM/R0/SubsetPopFlushes", STAMUNIT_OCCURENCES, "Times PGMDynMapPopAutoSubset flushes the subset.");
1625	STAM_REG(pVM, &pPGM->aStatR0DynMapSetSize[0], STAMTYPE_COUNTER, "/PGM/R0/SetSize000..09", STAMUNIT_OCCURENCES, "00-09% filled");
1626	STAM_REG(pVM, &pPGM->aStatR0DynMapSetSize[1], STAMTYPE_COUNTER, "/PGM/R0/SetSize010..19", STAMUNIT_OCCURENCES, "10-19% filled");
1627	STAM_REG(pVM, &pPGM->aStatR0DynMapSetSize[2], STAMTYPE_COUNTER, "/PGM/R0/SetSize020..29", STAMUNIT_OCCURENCES, "20-29% filled");
1628	STAM_REG(pVM, &pPGM->aStatR0DynMapSetSize[3], STAMTYPE_COUNTER, "/PGM/R0/SetSize030..39", STAMUNIT_OCCURENCES, "30-39% filled");
1629	STAM_REG(pVM, &pPGM->aStatR0DynMapSetSize[4], STAMTYPE_COUNTER, "/PGM/R0/SetSize040..49", STAMUNIT_OCCURENCES, "40-49% filled");
1630	STAM_REG(pVM, &pPGM->aStatR0DynMapSetSize[5], STAMTYPE_COUNTER, "/PGM/R0/SetSize050..59", STAMUNIT_OCCURENCES, "50-59% filled");
1631	STAM_REG(pVM, &pPGM->aStatR0DynMapSetSize[6], STAMTYPE_COUNTER, "/PGM/R0/SetSize060..69", STAMUNIT_OCCURENCES, "60-69% filled");
1632	STAM_REG(pVM, &pPGM->aStatR0DynMapSetSize[7], STAMTYPE_COUNTER, "/PGM/R0/SetSize070..79", STAMUNIT_OCCURENCES, "70-79% filled");
1633	STAM_REG(pVM, &pPGM->aStatR0DynMapSetSize[8], STAMTYPE_COUNTER, "/PGM/R0/SetSize080..89", STAMUNIT_OCCURENCES, "80-89% filled");
1634	STAM_REG(pVM, &pPGM->aStatR0DynMapSetSize[9], STAMTYPE_COUNTER, "/PGM/R0/SetSize090..99", STAMUNIT_OCCURENCES, "90-99% filled");
1635	STAM_REG(pVM, &pPGM->aStatR0DynMapSetSize[10], STAMTYPE_COUNTER, "/PGM/R0/SetSize100", STAMUNIT_OCCURENCES, "100% filled");
1636
1637	/* GC only: */
1638	STAM_REG(pVM, &pPGM->StatRCDynMapCacheHits, STAMTYPE_COUNTER, "/PGM/RC/DynMapCache/Hits" , STAMUNIT_OCCURENCES, "Number of dynamic page mapping cache hits.");
1639	STAM_REG(pVM, &pPGM->StatRCDynMapCacheMisses, STAMTYPE_COUNTER, "/PGM/RC/DynMapCache/Misses" , STAMUNIT_OCCURENCES, "Number of dynamic page mapping cache misses.");
1640	STAM_REG(pVM, &pPGM->StatRCInvlPgConflict, STAMTYPE_COUNTER, "/PGM/RC/InvlPgConflict", STAMUNIT_OCCURENCES, "Number of times PGMInvalidatePage() detected a mapping conflict.");
1641	STAM_REG(pVM, &pPGM->StatRCInvlPgSyncMonCR3, STAMTYPE_COUNTER, "/PGM/RC/InvlPgSyncMonitorCR3", STAMUNIT_OCCURENCES, "Number of times PGMInvalidatePage() ran into PGM_SYNC_MONITOR_CR3.");
1642
1643	/* RZ only: */
1644	STAM_REG(pVM, &pPGM->StatRZTrap0e, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMTrap0eHandler() body.");
1645	STAM_REG(pVM, &pPGM->StatRZTrap0eTimeCheckPageFault, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time/CheckPageFault", STAMUNIT_TICKS_PER_CALL, "Profiling of checking for dirty/access emulation faults.");
1646	STAM_REG(pVM, &pPGM->StatRZTrap0eTimeSyncPT, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time/SyncPT", STAMUNIT_TICKS_PER_CALL, "Profiling of lazy page table syncing.");
1647	STAM_REG(pVM, &pPGM->StatRZTrap0eTimeMapping, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time/Mapping", STAMUNIT_TICKS_PER_CALL, "Profiling of checking virtual mappings.");
1648	STAM_REG(pVM, &pPGM->StatRZTrap0eTimeOutOfSync, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time/OutOfSync", STAMUNIT_TICKS_PER_CALL, "Profiling of out of sync page handling.");
1649	STAM_REG(pVM, &pPGM->StatRZTrap0eTimeHandlers, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time/Handlers", STAMUNIT_TICKS_PER_CALL, "Profiling of checking handlers.");
1650	STAM_REG(pVM, &pPGM->StatRZTrap0eTime2CSAM, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time2/CSAM", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is CSAM.");
1651	STAM_REG(pVM, &pPGM->StatRZTrap0eTime2DirtyAndAccessed, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time2/DirtyAndAccessedBits", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is dirty and/or accessed bit emulation.");
1652	STAM_REG(pVM, &pPGM->StatRZTrap0eTime2GuestTrap, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time2/GuestTrap", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is a guest trap.");
1653	STAM_REG(pVM, &pPGM->StatRZTrap0eTime2HndPhys, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time2/HandlerPhysical", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is a physical handler.");
1654	STAM_REG(pVM, &pPGM->StatRZTrap0eTime2HndVirt, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time2/HandlerVirtual", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is a virtual handler.");
1655	STAM_REG(pVM, &pPGM->StatRZTrap0eTime2HndUnhandled, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time2/HandlerUnhandled", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is access outside the monitored areas of a monitored page.");
1656	STAM_REG(pVM, &pPGM->StatRZTrap0eTime2Misc, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time2/Misc", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is not known.");
1657	STAM_REG(pVM, &pPGM->StatRZTrap0eTime2OutOfSync, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time2/OutOfSync", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is an out-of-sync page.");
1658	STAM_REG(pVM, &pPGM->StatRZTrap0eTime2OutOfSyncHndPhys, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time2/OutOfSyncHndPhys", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is an out-of-sync physical handler page.");
1659	STAM_REG(pVM, &pPGM->StatRZTrap0eTime2OutOfSyncHndVirt, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time2/OutOfSyncHndVirt", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is an out-of-sync virtual handler page.");
1660	STAM_REG(pVM, &pPGM->StatRZTrap0eTime2OutOfSyncHndObs, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time2/OutOfSyncObsHnd", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is an obsolete handler page.");
1661	STAM_REG(pVM, &pPGM->StatRZTrap0eTime2SyncPT, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time2/SyncPT", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is lazy syncing of a PT.");
1662	STAM_REG(pVM, &pPGM->StatRZTrap0eConflicts, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Conflicts", STAMUNIT_OCCURENCES, "The number of times #PF was caused by an undetected conflict.");
1663	STAM_REG(pVM, &pPGM->StatRZTrap0eHandlersMapping, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Handlers/Mapping", STAMUNIT_OCCURENCES, "Number of traps due to access handlers in mappings.");
1664	STAM_REG(pVM, &pPGM->StatRZTrap0eHandlersOutOfSync, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Handlers/OutOfSync", STAMUNIT_OCCURENCES, "Number of traps due to out-of-sync handled pages.");
1665	STAM_REG(pVM, &pPGM->StatRZTrap0eHandlersPhysical, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Handlers/Physical", STAMUNIT_OCCURENCES, "Number of traps due to physical access handlers.");
1666	STAM_REG(pVM, &pPGM->StatRZTrap0eHandlersVirtual, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Handlers/Virtual", STAMUNIT_OCCURENCES, "Number of traps due to virtual access handlers.");
1667	STAM_REG(pVM, &pPGM->StatRZTrap0eHandlersVirtualByPhys, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Handlers/VirtualByPhys", STAMUNIT_OCCURENCES, "Number of traps due to virtual access handlers by physical address.");
1668	STAM_REG(pVM, &pPGM->StatRZTrap0eHandlersVirtualUnmarked,STAMTYPE_COUNTER,"/PGM/RZ/Trap0e/Handlers/VirtualUnmarked",STAMUNIT_OCCURENCES, "Number of traps due to virtual access handlers by virtual address (without proper physical flags).");
1669	STAM_REG(pVM, &pPGM->StatRZTrap0eHandlersUnhandled, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Handlers/Unhandled", STAMUNIT_OCCURENCES, "Number of traps due to access outside range of monitored page(s).");
1670	STAM_REG(pVM, &pPGM->StatRZTrap0eHandlersInvalid, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Handlers/Invalid", STAMUNIT_OCCURENCES, "Number of traps due to access to invalid physical memory.");
1671	STAM_REG(pVM, &pPGM->StatRZTrap0eUSNotPresentRead, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Err/User/NPRead", STAMUNIT_OCCURENCES, "Number of user mode not present read page faults.");
1672	STAM_REG(pVM, &pPGM->StatRZTrap0eUSNotPresentWrite, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Err/User/NPWrite", STAMUNIT_OCCURENCES, "Number of user mode not present write page faults.");
1673	STAM_REG(pVM, &pPGM->StatRZTrap0eUSWrite, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Err/User/Write", STAMUNIT_OCCURENCES, "Number of user mode write page faults.");
1674	STAM_REG(pVM, &pPGM->StatRZTrap0eUSReserved, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Err/User/Reserved", STAMUNIT_OCCURENCES, "Number of user mode reserved bit page faults.");
1675	STAM_REG(pVM, &pPGM->StatRZTrap0eUSNXE, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Err/User/NXE", STAMUNIT_OCCURENCES, "Number of user mode NXE page faults.");
1676	STAM_REG(pVM, &pPGM->StatRZTrap0eUSRead, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Err/User/Read", STAMUNIT_OCCURENCES, "Number of user mode read page faults.");
1677	STAM_REG(pVM, &pPGM->StatRZTrap0eSVNotPresentRead, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Err/Supervisor/NPRead", STAMUNIT_OCCURENCES, "Number of supervisor mode not present read page faults.");
1678	STAM_REG(pVM, &pPGM->StatRZTrap0eSVNotPresentWrite, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Err/Supervisor/NPWrite", STAMUNIT_OCCURENCES, "Number of supervisor mode not present write page faults.");
1679	STAM_REG(pVM, &pPGM->StatRZTrap0eSVWrite, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Err/Supervisor/Write", STAMUNIT_OCCURENCES, "Number of supervisor mode write page faults.");
1680	STAM_REG(pVM, &pPGM->StatRZTrap0eSVReserved, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Err/Supervisor/Reserved", STAMUNIT_OCCURENCES, "Number of supervisor mode reserved bit page faults.");
1681	STAM_REG(pVM, &pPGM->StatRZTrap0eSNXE, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Err/Supervisor/NXE", STAMUNIT_OCCURENCES, "Number of supervisor mode NXE page faults.");
1682	STAM_REG(pVM, &pPGM->StatRZTrap0eGuestPF, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/GuestPF", STAMUNIT_OCCURENCES, "Number of real guest page faults.");
1683	STAM_REG(pVM, &pPGM->StatRZTrap0eGuestPFUnh, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/GuestPF/Unhandled", STAMUNIT_OCCURENCES, "Number of real guest page faults from the 'unhandled' case.");
1684	STAM_REG(pVM, &pPGM->StatRZTrap0eGuestPFMapping, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/GuestPF/InMapping", STAMUNIT_OCCURENCES, "Number of real guest page faults in a mapping.");
1685	STAM_REG(pVM, &pPGM->StatRZTrap0eWPEmulInRZ, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/WP/InRZ", STAMUNIT_OCCURENCES, "Number of guest page faults due to X86_CR0_WP emulation.");
1686	STAM_REG(pVM, &pPGM->StatRZTrap0eWPEmulToR3, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/WP/ToR3", STAMUNIT_OCCURENCES, "Number of guest page faults due to X86_CR0_WP emulation (forward to R3 for emulation).");
1687	for (i = 0; i < RT_ELEMENTS(pPGM->StatRZTrap0ePD); i++)
1688	STAMR3RegisterF(pVM, &pPGM->StatRZTrap0ePD[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
1689	"The number of traps in page directory n.", "/PGM/RZ/Trap0e/PD/%04X", i);
1690	STAM_REG(pVM, &pPGM->StatRZGuestCR3WriteHandled, STAMTYPE_COUNTER, "/PGM/RZ/CR3WriteHandled", STAMUNIT_OCCURENCES, "The number of times the Guest CR3 change was successfully handled.");
1691	STAM_REG(pVM, &pPGM->StatRZGuestCR3WriteUnhandled, STAMTYPE_COUNTER, "/PGM/RZ/CR3WriteUnhandled", STAMUNIT_OCCURENCES, "The number of times the Guest CR3 change was passed back to the recompiler.");
1692	STAM_REG(pVM, &pPGM->StatRZGuestCR3WriteConflict, STAMTYPE_COUNTER, "/PGM/RZ/CR3WriteConflict", STAMUNIT_OCCURENCES, "The number of times the Guest CR3 monitoring detected a conflict.");
1693	STAM_REG(pVM, &pPGM->StatRZGuestROMWriteHandled, STAMTYPE_COUNTER, "/PGM/RZ/ROMWriteHandled", STAMUNIT_OCCURENCES, "The number of times the Guest ROM change was successfully handled.");
1694	STAM_REG(pVM, &pPGM->StatRZGuestROMWriteUnhandled, STAMTYPE_COUNTER, "/PGM/RZ/ROMWriteUnhandled", STAMUNIT_OCCURENCES, "The number of times the Guest ROM change was passed back to the recompiler.");
1695
1696	/* HC only: */
1697
1698	/* RZ & R3: */
1699	STAM_REG(pVM, &pPGM->StatRZSyncCR3, STAMTYPE_PROFILE, "/PGM/RZ/SyncCR3", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMSyncCR3() body.");
1700	STAM_REG(pVM, &pPGM->StatRZSyncCR3Handlers, STAMTYPE_PROFILE, "/PGM/RZ/SyncCR3/Handlers", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMSyncCR3() update handler section.");
1701	STAM_REG(pVM, &pPGM->StatRZSyncCR3HandlerVirtualUpdate, STAMTYPE_PROFILE, "/PGM/RZ/SyncCR3/Handlers/VirtualUpdate", STAMUNIT_TICKS_PER_CALL, "Profiling of the virtual handler updates.");
1702	STAM_REG(pVM, &pPGM->StatRZSyncCR3HandlerVirtualReset, STAMTYPE_PROFILE, "/PGM/RZ/SyncCR3/Handlers/VirtualReset", STAMUNIT_TICKS_PER_CALL, "Profiling of the virtual handler resets.");
1703	STAM_REG(pVM, &pPGM->StatRZSyncCR3Global, STAMTYPE_COUNTER, "/PGM/RZ/SyncCR3/Global", STAMUNIT_OCCURENCES, "The number of global CR3 syncs.");
1704	STAM_REG(pVM, &pPGM->StatRZSyncCR3NotGlobal, STAMTYPE_COUNTER, "/PGM/RZ/SyncCR3/NotGlobal", STAMUNIT_OCCURENCES, "The number of non-global CR3 syncs.");
1705	STAM_REG(pVM, &pPGM->StatRZSyncCR3DstCacheHit, STAMTYPE_COUNTER, "/PGM/RZ/SyncCR3/DstChacheHit", STAMUNIT_OCCURENCES, "The number of times we got some kind of a cache hit.");
1706	STAM_REG(pVM, &pPGM->StatRZSyncCR3DstFreed, STAMTYPE_COUNTER, "/PGM/RZ/SyncCR3/DstFreed", STAMUNIT_OCCURENCES, "The number of times we've had to free a shadow entry.");
1707	STAM_REG(pVM, &pPGM->StatRZSyncCR3DstFreedSrcNP, STAMTYPE_COUNTER, "/PGM/RZ/SyncCR3/DstFreedSrcNP", STAMUNIT_OCCURENCES, "The number of times we've had to free a shadow entry for which the source entry was not present.");
1708	STAM_REG(pVM, &pPGM->StatRZSyncCR3DstNotPresent, STAMTYPE_COUNTER, "/PGM/RZ/SyncCR3/DstNotPresent", STAMUNIT_OCCURENCES, "The number of times we've encountered a not present shadow entry for a present guest entry.");
1709	STAM_REG(pVM, &pPGM->StatRZSyncCR3DstSkippedGlobalPD, STAMTYPE_COUNTER, "/PGM/RZ/SyncCR3/DstSkippedGlobalPD", STAMUNIT_OCCURENCES, "The number of times a global page directory wasn't flushed.");
1710	STAM_REG(pVM, &pPGM->StatRZSyncCR3DstSkippedGlobalPT, STAMTYPE_COUNTER, "/PGM/RZ/SyncCR3/DstSkippedGlobalPT", STAMUNIT_OCCURENCES, "The number of times a page table with only global entries wasn't flushed.");
1711	STAM_REG(pVM, &pPGM->StatRZSyncPT, STAMTYPE_PROFILE, "/PGM/RZ/SyncPT", STAMUNIT_TICKS_PER_CALL, "Profiling of the pfnSyncPT() body.");
1712	STAM_REG(pVM, &pPGM->StatRZSyncPTFailed, STAMTYPE_COUNTER, "/PGM/RZ/SyncPT/Failed", STAMUNIT_OCCURENCES, "The number of times pfnSyncPT() failed.");
1713	STAM_REG(pVM, &pPGM->StatRZSyncPT4K, STAMTYPE_COUNTER, "/PGM/RZ/SyncPT/4K", STAMUNIT_OCCURENCES, "Nr of 4K PT syncs");
1714	STAM_REG(pVM, &pPGM->StatRZSyncPT4M, STAMTYPE_COUNTER, "/PGM/RZ/SyncPT/4M", STAMUNIT_OCCURENCES, "Nr of 4M PT syncs");
1715	STAM_REG(pVM, &pPGM->StatRZSyncPagePDNAs, STAMTYPE_COUNTER, "/PGM/RZ/SyncPagePDNAs", STAMUNIT_OCCURENCES, "The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit.");
1716	STAM_REG(pVM, &pPGM->StatRZSyncPagePDOutOfSync, STAMTYPE_COUNTER, "/PGM/RZ/SyncPagePDOutOfSync", STAMUNIT_OCCURENCES, "The number of time we've encountered an out-of-sync PD in SyncPage.");
1717	STAM_REG(pVM, &pPGM->StatRZAccessedPage, STAMTYPE_COUNTER, "/PGM/RZ/AccessedPage", STAMUNIT_OCCURENCES, "The number of pages marked not present for accessed bit emulation.");
1718	STAM_REG(pVM, &pPGM->StatRZDirtyBitTracking, STAMTYPE_PROFILE, "/PGM/RZ/DirtyPage", STAMUNIT_TICKS_PER_CALL, "Profiling the dirty bit tracking in CheckPageFault().");
1719	STAM_REG(pVM, &pPGM->StatRZDirtyPage, STAMTYPE_COUNTER, "/PGM/RZ/DirtyPage/Mark", STAMUNIT_OCCURENCES, "The number of pages marked read-only for dirty bit tracking.");
1720	STAM_REG(pVM, &pPGM->StatRZDirtyPageBig, STAMTYPE_COUNTER, "/PGM/RZ/DirtyPage/MarkBig", STAMUNIT_OCCURENCES, "The number of 4MB pages marked read-only for dirty bit tracking.");
1721	STAM_REG(pVM, &pPGM->StatRZDirtyPageSkipped, STAMTYPE_COUNTER, "/PGM/RZ/DirtyPage/Skipped", STAMUNIT_OCCURENCES, "The number of pages already dirty or readonly.");
1722	STAM_REG(pVM, &pPGM->StatRZDirtyPageTrap, STAMTYPE_COUNTER, "/PGM/RZ/DirtyPage/Trap", STAMUNIT_OCCURENCES, "The number of traps generated for dirty bit tracking.");
1723	STAM_REG(pVM, &pPGM->StatRZDirtiedPage, STAMTYPE_COUNTER, "/PGM/RZ/DirtyPage/SetDirty", STAMUNIT_OCCURENCES, "The number of pages marked dirty because of write accesses.");
1724	STAM_REG(pVM, &pPGM->StatRZDirtyTrackRealPF, STAMTYPE_COUNTER, "/PGM/RZ/DirtyPage/RealPF", STAMUNIT_OCCURENCES, "The number of real pages faults during dirty bit tracking.");
1725	STAM_REG(pVM, &pPGM->StatRZPageAlreadyDirty, STAMTYPE_COUNTER, "/PGM/RZ/DirtyPage/AlreadySet", STAMUNIT_OCCURENCES, "The number of pages already marked dirty because of write accesses.");
1726	STAM_REG(pVM, &pPGM->StatRZInvalidatePage, STAMTYPE_PROFILE, "/PGM/RZ/InvalidatePage", STAMUNIT_TICKS_PER_CALL, "PGMInvalidatePage() profiling.");
1727	STAM_REG(pVM, &pPGM->StatRZInvalidatePage4KBPages, STAMTYPE_COUNTER, "/PGM/RZ/InvalidatePage/4KBPages", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was called for a 4KB page.");
1728	STAM_REG(pVM, &pPGM->StatRZInvalidatePage4MBPages, STAMTYPE_COUNTER, "/PGM/RZ/InvalidatePage/4MBPages", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was called for a 4MB page.");
1729	STAM_REG(pVM, &pPGM->StatRZInvalidatePage4MBPagesSkip, STAMTYPE_COUNTER, "/PGM/RZ/InvalidatePage/4MBPagesSkip",STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() skipped a 4MB page.");
1730	STAM_REG(pVM, &pPGM->StatRZInvalidatePagePDMappings, STAMTYPE_COUNTER, "/PGM/RZ/InvalidatePage/PDMappings", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict).");
1731	STAM_REG(pVM, &pPGM->StatRZInvalidatePagePDNAs, STAMTYPE_COUNTER, "/PGM/RZ/InvalidatePage/PDNAs", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was called for a not accessed page directory.");
1732	STAM_REG(pVM, &pPGM->StatRZInvalidatePagePDNPs, STAMTYPE_COUNTER, "/PGM/RZ/InvalidatePage/PDNPs", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was called for a not present page directory.");
1733	STAM_REG(pVM, &pPGM->StatRZInvalidatePagePDOutOfSync, STAMTYPE_COUNTER, "/PGM/RZ/InvalidatePage/PDOutOfSync", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was called for an out of sync page directory.");
1734	STAM_REG(pVM, &pPGM->StatRZInvalidatePageSkipped, STAMTYPE_COUNTER, "/PGM/RZ/InvalidatePage/Skipped", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3.");
1735	STAM_REG(pVM, &pPGM->StatRZVirtHandlerSearchByPhys, STAMTYPE_PROFILE, "/PGM/RZ/VirtHandlerSearchByPhys", STAMUNIT_TICKS_PER_CALL, "Profiling of pgmHandlerVirtualFindByPhysAddr.");
1736	STAM_REG(pVM, &pPGM->StatRZPhysHandlerReset, STAMTYPE_COUNTER, "/PGM/RZ/PhysHandlerReset", STAMUNIT_OCCURENCES, "The number of times PGMHandlerPhysicalReset is called.");
1737	STAM_REG(pVM, &pPGM->StatRZPageOutOfSyncSupervisor, STAMTYPE_COUNTER, "/PGM/RZ/OutOfSync/SuperVisor", STAMUNIT_OCCURENCES, "Number of traps due to pages out of sync and times VerifyAccessSyncPage calls SyncPage.");
1738	STAM_REG(pVM, &pPGM->StatRZPageOutOfSyncUser, STAMTYPE_COUNTER, "/PGM/RZ/OutOfSync/User", STAMUNIT_OCCURENCES, "Number of traps due to pages out of sync and times VerifyAccessSyncPage calls SyncPage.");
1739	STAM_REG(pVM, &pPGM->StatRZPrefetch, STAMTYPE_PROFILE, "/PGM/RZ/Prefetch", STAMUNIT_TICKS_PER_CALL, "PGMPrefetchPage profiling.");
1740	STAM_REG(pVM, &pPGM->StatRZChunkR3MapTlbHits, STAMTYPE_COUNTER, "/PGM/ChunkR3Map/TlbHitsRZ", STAMUNIT_OCCURENCES, "TLB hits.");
1741	STAM_REG(pVM, &pPGM->StatRZChunkR3MapTlbMisses, STAMTYPE_COUNTER, "/PGM/ChunkR3Map/TlbMissesRZ", STAMUNIT_OCCURENCES, "TLB misses.");
1742	STAM_REG(pVM, &pPGM->StatRZPageMapTlbHits, STAMTYPE_COUNTER, "/PGM/RZ/Page/MapTlbHits", STAMUNIT_OCCURENCES, "TLB hits.");
1743	STAM_REG(pVM, &pPGM->StatRZPageMapTlbMisses, STAMTYPE_COUNTER, "/PGM/RZ/Page/MapTlbMisses", STAMUNIT_OCCURENCES, "TLB misses.");
1744	STAM_REG(pVM, &pPGM->StatRZPageReplaceShared, STAMTYPE_COUNTER, "/PGM/RZ/Page/ReplacedShared", STAMUNIT_OCCURENCES, "Times a shared page was replaced.");
1745	STAM_REG(pVM, &pPGM->StatRZPageReplaceZero, STAMTYPE_COUNTER, "/PGM/RZ/Page/ReplacedZero", STAMUNIT_OCCURENCES, "Times the zero page was replaced.");
1746	/// @todo STAM_REG(pVM, &pPGM->StatRZPageHandyAllocs, STAMTYPE_COUNTER, "/PGM/RZ/Page/HandyAllocs", STAMUNIT_OCCURENCES, "Number of times we've allocated more handy pages.");
1747	STAM_REG(pVM, &pPGM->StatRZFlushTLB, STAMTYPE_PROFILE, "/PGM/RZ/FlushTLB", STAMUNIT_OCCURENCES, "Profiling of the PGMFlushTLB() body.");
1748	STAM_REG(pVM, &pPGM->StatRZFlushTLBNewCR3, STAMTYPE_COUNTER, "/PGM/RZ/FlushTLB/NewCR3", STAMUNIT_OCCURENCES, "The number of times PGMFlushTLB was called with a new CR3, non-global. (switch)");
1749	STAM_REG(pVM, &pPGM->StatRZFlushTLBNewCR3Global, STAMTYPE_COUNTER, "/PGM/RZ/FlushTLB/NewCR3Global", STAMUNIT_OCCURENCES, "The number of times PGMFlushTLB was called with a new CR3, global. (switch)");
1750	STAM_REG(pVM, &pPGM->StatRZFlushTLBSameCR3, STAMTYPE_COUNTER, "/PGM/RZ/FlushTLB/SameCR3", STAMUNIT_OCCURENCES, "The number of times PGMFlushTLB was called with the same CR3, non-global. (flush)");
1751	STAM_REG(pVM, &pPGM->StatRZFlushTLBSameCR3Global, STAMTYPE_COUNTER, "/PGM/RZ/FlushTLB/SameCR3Global", STAMUNIT_OCCURENCES, "The number of times PGMFlushTLB was called with the same CR3, global. (flush)");
1752	STAM_REG(pVM, &pPGM->StatRZGstModifyPage, STAMTYPE_PROFILE, "/PGM/RZ/GstModifyPage", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMGstModifyPage() body.");
1753
1754	STAM_REG(pVM, &pPGM->StatR3SyncCR3, STAMTYPE_PROFILE, "/PGM/R3/SyncCR3", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMSyncCR3() body.");
1755	STAM_REG(pVM, &pPGM->StatR3SyncCR3Handlers, STAMTYPE_PROFILE, "/PGM/R3/SyncCR3/Handlers", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMSyncCR3() update handler section.");
1756	STAM_REG(pVM, &pPGM->StatR3SyncCR3HandlerVirtualUpdate, STAMTYPE_PROFILE, "/PGM/R3/SyncCR3/Handlers/VirtualUpdate", STAMUNIT_TICKS_PER_CALL, "Profiling of the virtual handler updates.");
1757	STAM_REG(pVM, &pPGM->StatR3SyncCR3HandlerVirtualReset, STAMTYPE_PROFILE, "/PGM/R3/SyncCR3/Handlers/VirtualReset", STAMUNIT_TICKS_PER_CALL, "Profiling of the virtual handler resets.");
1758	STAM_REG(pVM, &pPGM->StatR3SyncCR3Global, STAMTYPE_COUNTER, "/PGM/R3/SyncCR3/Global", STAMUNIT_OCCURENCES, "The number of global CR3 syncs.");
1759	STAM_REG(pVM, &pPGM->StatR3SyncCR3NotGlobal, STAMTYPE_COUNTER, "/PGM/R3/SyncCR3/NotGlobal", STAMUNIT_OCCURENCES, "The number of non-global CR3 syncs.");
1760	STAM_REG(pVM, &pPGM->StatR3SyncCR3DstCacheHit, STAMTYPE_COUNTER, "/PGM/R3/SyncCR3/DstChacheHit", STAMUNIT_OCCURENCES, "The number of times we got some kind of a cache hit.");
1761	STAM_REG(pVM, &pPGM->StatR3SyncCR3DstFreed, STAMTYPE_COUNTER, "/PGM/R3/SyncCR3/DstFreed", STAMUNIT_OCCURENCES, "The number of times we've had to free a shadow entry.");
1762	STAM_REG(pVM, &pPGM->StatR3SyncCR3DstFreedSrcNP, STAMTYPE_COUNTER, "/PGM/R3/SyncCR3/DstFreedSrcNP", STAMUNIT_OCCURENCES, "The number of times we've had to free a shadow entry for which the source entry was not present.");
1763	STAM_REG(pVM, &pPGM->StatR3SyncCR3DstNotPresent, STAMTYPE_COUNTER, "/PGM/R3/SyncCR3/DstNotPresent", STAMUNIT_OCCURENCES, "The number of times we've encountered a not present shadow entry for a present guest entry.");
1764	STAM_REG(pVM, &pPGM->StatR3SyncCR3DstSkippedGlobalPD, STAMTYPE_COUNTER, "/PGM/R3/SyncCR3/DstSkippedGlobalPD", STAMUNIT_OCCURENCES, "The number of times a global page directory wasn't flushed.");
1765	STAM_REG(pVM, &pPGM->StatR3SyncCR3DstSkippedGlobalPT, STAMTYPE_COUNTER, "/PGM/R3/SyncCR3/DstSkippedGlobalPT", STAMUNIT_OCCURENCES, "The number of times a page table with only global entries wasn't flushed.");
1766	STAM_REG(pVM, &pPGM->StatR3SyncPT, STAMTYPE_PROFILE, "/PGM/R3/SyncPT", STAMUNIT_TICKS_PER_CALL, "Profiling of the pfnSyncPT() body.");
1767	STAM_REG(pVM, &pPGM->StatR3SyncPTFailed, STAMTYPE_COUNTER, "/PGM/R3/SyncPT/Failed", STAMUNIT_OCCURENCES, "The number of times pfnSyncPT() failed.");
1768	STAM_REG(pVM, &pPGM->StatR3SyncPT4K, STAMTYPE_COUNTER, "/PGM/R3/SyncPT/4K", STAMUNIT_OCCURENCES, "Nr of 4K PT syncs");
1769	STAM_REG(pVM, &pPGM->StatR3SyncPT4M, STAMTYPE_COUNTER, "/PGM/R3/SyncPT/4M", STAMUNIT_OCCURENCES, "Nr of 4M PT syncs");
1770	STAM_REG(pVM, &pPGM->StatR3SyncPagePDNAs, STAMTYPE_COUNTER, "/PGM/R3/SyncPagePDNAs", STAMUNIT_OCCURENCES, "The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit.");
1771	STAM_REG(pVM, &pPGM->StatR3SyncPagePDOutOfSync, STAMTYPE_COUNTER, "/PGM/R3/SyncPagePDOutOfSync", STAMUNIT_OCCURENCES, "The number of time we've encountered an out-of-sync PD in SyncPage.");
1772	STAM_REG(pVM, &pPGM->StatR3AccessedPage, STAMTYPE_COUNTER, "/PGM/R3/AccessedPage", STAMUNIT_OCCURENCES, "The number of pages marked not present for accessed bit emulation.");
1773	STAM_REG(pVM, &pPGM->StatR3DirtyBitTracking, STAMTYPE_PROFILE, "/PGM/R3/DirtyPage", STAMUNIT_TICKS_PER_CALL, "Profiling the dirty bit tracking in CheckPageFault().");
1774	STAM_REG(pVM, &pPGM->StatR3DirtyPage, STAMTYPE_COUNTER, "/PGM/R3/DirtyPage/Mark", STAMUNIT_OCCURENCES, "The number of pages marked read-only for dirty bit tracking.");
1775	STAM_REG(pVM, &pPGM->StatR3DirtyPageBig, STAMTYPE_COUNTER, "/PGM/R3/DirtyPage/MarkBig", STAMUNIT_OCCURENCES, "The number of 4MB pages marked read-only for dirty bit tracking.");
1776	STAM_REG(pVM, &pPGM->StatR3DirtyPageSkipped, STAMTYPE_COUNTER, "/PGM/R3/DirtyPage/Skipped", STAMUNIT_OCCURENCES, "The number of pages already dirty or readonly.");
1777	STAM_REG(pVM, &pPGM->StatR3DirtyPageTrap, STAMTYPE_COUNTER, "/PGM/R3/DirtyPage/Trap", STAMUNIT_OCCURENCES, "The number of traps generated for dirty bit tracking.");
1778	STAM_REG(pVM, &pPGM->StatR3DirtiedPage, STAMTYPE_COUNTER, "/PGM/R3/DirtyPage/SetDirty", STAMUNIT_OCCURENCES, "The number of pages marked dirty because of write accesses.");
1779	STAM_REG(pVM, &pPGM->StatR3DirtyTrackRealPF, STAMTYPE_COUNTER, "/PGM/R3/DirtyPage/RealPF", STAMUNIT_OCCURENCES, "The number of real pages faults during dirty bit tracking.");
1780	STAM_REG(pVM, &pPGM->StatR3PageAlreadyDirty, STAMTYPE_COUNTER, "/PGM/R3/DirtyPage/AlreadySet", STAMUNIT_OCCURENCES, "The number of pages already marked dirty because of write accesses.");
1781	STAM_REG(pVM, &pPGM->StatR3InvalidatePage, STAMTYPE_PROFILE, "/PGM/R3/InvalidatePage", STAMUNIT_TICKS_PER_CALL, "PGMInvalidatePage() profiling.");
1782	STAM_REG(pVM, &pPGM->StatR3InvalidatePage4KBPages, STAMTYPE_COUNTER, "/PGM/R3/InvalidatePage/4KBPages", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was called for a 4KB page.");
1783	STAM_REG(pVM, &pPGM->StatR3InvalidatePage4MBPages, STAMTYPE_COUNTER, "/PGM/R3/InvalidatePage/4MBPages", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was called for a 4MB page.");
1784	STAM_REG(pVM, &pPGM->StatR3InvalidatePage4MBPagesSkip, STAMTYPE_COUNTER, "/PGM/R3/InvalidatePage/4MBPagesSkip",STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() skipped a 4MB page.");
1785	STAM_REG(pVM, &pPGM->StatR3InvalidatePagePDMappings, STAMTYPE_COUNTER, "/PGM/R3/InvalidatePage/PDMappings", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict).");
1786	STAM_REG(pVM, &pPGM->StatR3InvalidatePagePDNAs, STAMTYPE_COUNTER, "/PGM/R3/InvalidatePage/PDNAs", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was called for a not accessed page directory.");
1787	STAM_REG(pVM, &pPGM->StatR3InvalidatePagePDNPs, STAMTYPE_COUNTER, "/PGM/R3/InvalidatePage/PDNPs", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was called for a not present page directory.");
1788	STAM_REG(pVM, &pPGM->StatR3InvalidatePagePDOutOfSync, STAMTYPE_COUNTER, "/PGM/R3/InvalidatePage/PDOutOfSync", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was called for an out of sync page directory.");
1789	STAM_REG(pVM, &pPGM->StatR3InvalidatePageSkipped, STAMTYPE_COUNTER, "/PGM/R3/InvalidatePage/Skipped", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3.");
1790	STAM_REG(pVM, &pPGM->StatR3VirtHandlerSearchByPhys, STAMTYPE_PROFILE, "/PGM/R3/VirtHandlerSearchByPhys", STAMUNIT_TICKS_PER_CALL, "Profiling of pgmHandlerVirtualFindByPhysAddr.");
1791	STAM_REG(pVM, &pPGM->StatR3PhysHandlerReset, STAMTYPE_COUNTER, "/PGM/R3/PhysHandlerReset", STAMUNIT_OCCURENCES, "The number of times PGMHandlerPhysicalReset is called.");
1792	STAM_REG(pVM, &pPGM->StatR3PageOutOfSyncSupervisor, STAMTYPE_COUNTER, "/PGM/R3/OutOfSync/SuperVisor", STAMUNIT_OCCURENCES, "Number of traps due to pages out of sync and times VerifyAccessSyncPage calls SyncPage.");
1793	STAM_REG(pVM, &pPGM->StatR3PageOutOfSyncUser, STAMTYPE_COUNTER, "/PGM/R3/OutOfSync/User", STAMUNIT_OCCURENCES, "Number of traps due to pages out of sync and times VerifyAccessSyncPage calls SyncPage.");
1794	STAM_REG(pVM, &pPGM->StatR3Prefetch, STAMTYPE_PROFILE, "/PGM/R3/Prefetch", STAMUNIT_TICKS_PER_CALL, "PGMPrefetchPage profiling.");
1795	STAM_REG(pVM, &pPGM->StatR3ChunkR3MapTlbHits, STAMTYPE_COUNTER, "/PGM/ChunkR3Map/TlbHitsR3", STAMUNIT_OCCURENCES, "TLB hits.");
1796	STAM_REG(pVM, &pPGM->StatR3ChunkR3MapTlbMisses, STAMTYPE_COUNTER, "/PGM/ChunkR3Map/TlbMissesR3", STAMUNIT_OCCURENCES, "TLB misses.");
1797	STAM_REG(pVM, &pPGM->StatR3PageMapTlbHits, STAMTYPE_COUNTER, "/PGM/R3/Page/MapTlbHits", STAMUNIT_OCCURENCES, "TLB hits.");
1798	STAM_REG(pVM, &pPGM->StatR3PageMapTlbMisses, STAMTYPE_COUNTER, "/PGM/R3/Page/MapTlbMisses", STAMUNIT_OCCURENCES, "TLB misses.");
1799	STAM_REG(pVM, &pPGM->StatR3PageReplaceShared, STAMTYPE_COUNTER, "/PGM/R3/Page/ReplacedShared", STAMUNIT_OCCURENCES, "Times a shared page was replaced.");
1800	STAM_REG(pVM, &pPGM->StatR3PageReplaceZero, STAMTYPE_COUNTER, "/PGM/R3/Page/ReplacedZero", STAMUNIT_OCCURENCES, "Times the zero page was replaced.");
1801	/// @todo STAM_REG(pVM, &pPGM->StatR3PageHandyAllocs, STAMTYPE_COUNTER, "/PGM/R3/Page/HandyAllocs", STAMUNIT_OCCURENCES, "Number of times we've allocated more handy pages.");
1802	STAM_REG(pVM, &pPGM->StatR3FlushTLB, STAMTYPE_PROFILE, "/PGM/R3/FlushTLB", STAMUNIT_OCCURENCES, "Profiling of the PGMFlushTLB() body.");
1803	STAM_REG(pVM, &pPGM->StatR3FlushTLBNewCR3, STAMTYPE_COUNTER, "/PGM/R3/FlushTLB/NewCR3", STAMUNIT_OCCURENCES, "The number of times PGMFlushTLB was called with a new CR3, non-global. (switch)");
1804	STAM_REG(pVM, &pPGM->StatR3FlushTLBNewCR3Global, STAMTYPE_COUNTER, "/PGM/R3/FlushTLB/NewCR3Global", STAMUNIT_OCCURENCES, "The number of times PGMFlushTLB was called with a new CR3, global. (switch)");
1805	STAM_REG(pVM, &pPGM->StatR3FlushTLBSameCR3, STAMTYPE_COUNTER, "/PGM/R3/FlushTLB/SameCR3", STAMUNIT_OCCURENCES, "The number of times PGMFlushTLB was called with the same CR3, non-global. (flush)");
1806	STAM_REG(pVM, &pPGM->StatR3FlushTLBSameCR3Global, STAMTYPE_COUNTER, "/PGM/R3/FlushTLB/SameCR3Global", STAMUNIT_OCCURENCES, "The number of times PGMFlushTLB was called with the same CR3, global. (flush)");
1807	STAM_REG(pVM, &pPGM->StatR3GstModifyPage, STAMTYPE_PROFILE, "/PGM/R3/GstModifyPage", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMGstModifyPage() body.");
1808
1809	}
1810	#endif /* VBOX_WITH_STATISTICS */
1811
1812
1813	/**
1814	* Init the PGM bits that rely on VMMR0 and MM to be fully initialized.
1815	*
1816	* The dynamic mapping area will also be allocated and initialized at this
1817	* time. We could allocate it during PGMR3Init of course, but the mapping
1818	* wouldn't be allocated at that time preventing us from setting up the
1819	* page table entries with the dummy page.
1820	*
1821	* @returns VBox status code.
1822	* @param pVM VM handle.
1823	*/
1824	VMMR3DECL(int) PGMR3InitDynMap(PVM pVM)
1825	{
1826	RTGCPTR GCPtr;
1827	int rc;
1828
1829	#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
1830	/*
1831	* Reserve space for mapping the paging pages into guest context.
1832	*/
1833	rc = MMR3HyperReserve(pVM, PAGE_SIZE * (2 + RT_ELEMENTS(pVM->pgm.s.apShwPaePDsR3) + 1 + 2 + 2), "Paging", &GCPtr);
1834	AssertRCReturn(rc, rc);
1835	pVM->pgm.s.pShw32BitPdRC = GCPtr;
1836	MMR3HyperReserve(pVM, PAGE_SIZE, "fence", NULL);
1837	#endif
1838
1839	/*
1840	* Reserve space for the dynamic mappings.
1841	*/
1842	rc = MMR3HyperReserve(pVM, MM_HYPER_DYNAMIC_SIZE, "Dynamic mapping", &GCPtr);
1843	if (RT_SUCCESS(rc))
1844	pVM->pgm.s.pbDynPageMapBaseGC = GCPtr;
1845
1846	if ( RT_SUCCESS(rc)
1847	&& (pVM->pgm.s.pbDynPageMapBaseGC >> X86_PD_PAE_SHIFT) != ((pVM->pgm.s.pbDynPageMapBaseGC + MM_HYPER_DYNAMIC_SIZE - 1) >> X86_PD_PAE_SHIFT))
1848	{
1849	rc = MMR3HyperReserve(pVM, MM_HYPER_DYNAMIC_SIZE, "Dynamic mapping not crossing", &GCPtr);
1850	if (RT_SUCCESS(rc))
1851	pVM->pgm.s.pbDynPageMapBaseGC = GCPtr;
1852	}
1853	if (RT_SUCCESS(rc))
1854	{
1855	AssertRelease((pVM->pgm.s.pbDynPageMapBaseGC >> X86_PD_PAE_SHIFT) == ((pVM->pgm.s.pbDynPageMapBaseGC + MM_HYPER_DYNAMIC_SIZE - 1) >> X86_PD_PAE_SHIFT));
1856	MMR3HyperReserve(pVM, PAGE_SIZE, "fence", NULL);
1857	}
1858	return rc;
1859	}
1860
1861
1862	/**
1863	* Ring-3 init finalizing.
1864	*
1865	* @returns VBox status code.
1866	* @param pVM The VM handle.
1867	*/
1868	VMMR3DECL(int) PGMR3InitFinalize(PVM pVM)
1869	{
1870	int rc;
1871
1872	#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
1873	/*
1874	* Map the paging pages into the guest context.
1875	*/
1876	RTGCPTR GCPtr = pVM->pgm.s.pShw32BitPdRC;
1877	AssertReleaseReturn(GCPtr, VERR_INTERNAL_ERROR);
1878
1879	rc = PGMMap(pVM, GCPtr, pVM->pgm.s.HCPhysShw32BitPD, PAGE_SIZE, 0);
1880	AssertRCReturn(rc, rc);
1881	pVM->pgm.s.pShw32BitPdRC = GCPtr;
1882	GCPtr += PAGE_SIZE;
1883	GCPtr += PAGE_SIZE; /* reserved page */
1884
1885	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.apShwPaePDsR3); i++)
1886	{
1887	rc = PGMMap(pVM, GCPtr, pVM->pgm.s.aHCPhysPaePDs[i], PAGE_SIZE, 0);
1888	AssertRCReturn(rc, rc);
1889	pVM->pgm.s.apShwPaePDsRC[i] = GCPtr;
1890	GCPtr += PAGE_SIZE;
1891	}
1892	/* A bit of paranoia is justified. */
1893	AssertRelease(pVM->pgm.s.apShwPaePDsRC[0] + PAGE_SIZE == pVM->pgm.s.apShwPaePDsRC[1]);
1894	AssertRelease(pVM->pgm.s.apShwPaePDsRC[1] + PAGE_SIZE == pVM->pgm.s.apShwPaePDsRC[2]);
1895	AssertRelease(pVM->pgm.s.apShwPaePDsRC[2] + PAGE_SIZE == pVM->pgm.s.apShwPaePDsRC[3]);
1896	GCPtr += PAGE_SIZE; /* reserved page */
1897
1898	rc = PGMMap(pVM, GCPtr, pVM->pgm.s.HCPhysShwPaePdpt, PAGE_SIZE, 0);
1899	AssertRCReturn(rc, rc);
1900	pVM->pgm.s.pShwPaePdptRC = GCPtr;
1901	GCPtr += PAGE_SIZE;
1902	GCPtr += PAGE_SIZE; /* reserved page */
1903	#endif
1904
1905	/*
1906	* Reserve space for the dynamic mappings.
1907	* Initialize the dynamic mapping pages with dummy pages to simply the cache.
1908	*/
1909	/* get the pointer to the page table entries. */
1910	PPGMMAPPING pMapping = pgmGetMapping(pVM, pVM->pgm.s.pbDynPageMapBaseGC);
1911	AssertRelease(pMapping);
1912	const uintptr_t off = pVM->pgm.s.pbDynPageMapBaseGC - pMapping->GCPtr;
1913	const unsigned iPT = off >> X86_PD_SHIFT;
1914	const unsigned iPG = (off >> X86_PT_SHIFT) & X86_PT_MASK;
1915	pVM->pgm.s.paDynPageMap32BitPTEsGC = pMapping->aPTs[iPT].pPTRC + iPG * sizeof(pMapping->aPTs[0].pPTR3->a[0]);
1916	pVM->pgm.s.paDynPageMapPaePTEsGC = pMapping->aPTs[iPT].paPaePTsRC + iPG * sizeof(pMapping->aPTs[0].paPaePTsR3->a[0]);
1917
1918	/* init cache */
1919	RTHCPHYS HCPhysDummy = MMR3PageDummyHCPhys(pVM);
1920	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.aHCPhysDynPageMapCache); i++)
1921	pVM->pgm.s.aHCPhysDynPageMapCache[i] = HCPhysDummy;
1922
1923	for (unsigned i = 0; i < MM_HYPER_DYNAMIC_SIZE; i += PAGE_SIZE)
1924	{
1925	rc = PGMMap(pVM, pVM->pgm.s.pbDynPageMapBaseGC + i, HCPhysDummy, PAGE_SIZE, 0);
1926	AssertRCReturn(rc, rc);
1927	}
1928
1929	/*
1930	* Note that AMD uses all the 8 reserved bits for the address (so 40 bits in total);
1931	* Intel only goes up to 36 bits, so we stick to 36 as well.
1932	*/
1933	/** @todo How to test for the 40 bits support? Long mode seems to be the test criterium. */
1934	uint32_t u32Dummy, u32Features;
1935	CPUMGetGuestCpuId(pVM, 1, &u32Dummy, &u32Dummy, &u32Dummy, &u32Features);
1936
1937	if (u32Features & X86_CPUID_FEATURE_EDX_PSE36)
1938	pVM->pgm.s.GCPhys4MBPSEMask = RT_BIT_64(36) - 1;
1939	else
1940	pVM->pgm.s.GCPhys4MBPSEMask = RT_BIT_64(32) - 1;
1941
1942	LogRel(("PGMR3InitFinalize: 4 MB PSE mask %RGp\n", pVM->pgm.s.GCPhys4MBPSEMask));
1943
1944	return rc;
1945	}
1946
1947
1948	/**
1949	* Applies relocations to data and code managed by this component.
1950	*
1951	* This function will be called at init and whenever the VMM need to relocate it
1952	* self inside the GC.
1953	*
1954	* @param pVM The VM.
1955	* @param offDelta Relocation delta relative to old location.
1956	*/
1957	VMMR3DECL(void) PGMR3Relocate(PVM pVM, RTGCINTPTR offDelta)
1958	{
1959	LogFlow(("PGMR3Relocate\n"));
1960
1961	/*
1962	* Paging stuff.
1963	*/
1964	pVM->pgm.s.GCPtrCR3Mapping += offDelta;
1965	/** @todo move this into shadow and guest specific relocation functions. */
1966	AssertMsg(pVM->pgm.s.pShw32BitPdR3, ("Init order, no relocation before paging is initialized!\n"));
1967	#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
1968	pVM->pgm.s.pShw32BitPdRC += offDelta;
1969	#endif
1970	pVM->pgm.s.pGst32BitPdRC += offDelta;
1971	AssertCompile(RT_ELEMENTS(pVM->pgm.s.apShwPaePDsRC) == RT_ELEMENTS(pVM->pgm.s.apGstPaePDsRC));
1972	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.apShwPaePDsRC); i++)
1973	{
1974	#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
1975	pVM->pgm.s.apShwPaePDsRC[i] += offDelta;
1976	#endif
1977	pVM->pgm.s.apGstPaePDsRC[i] += offDelta;
1978	}
1979	pVM->pgm.s.pGstPaePdptRC += offDelta;
1980	#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
1981	pVM->pgm.s.pShwPaePdptRC += offDelta;
1982	#endif
1983
1984	pgmR3ModeDataInit(pVM, true /* resolve GC/R0 symbols */);
1985	pgmR3ModeDataSwitch(pVM, pVM->pgm.s.enmShadowMode, pVM->pgm.s.enmGuestMode);
1986
1987	PGM_SHW_PFN(Relocate, pVM)(pVM, offDelta);
1988	PGM_GST_PFN(Relocate, pVM)(pVM, offDelta);
1989	PGM_BTH_PFN(Relocate, pVM)(pVM, offDelta);
1990
1991	/*
1992	* Trees.
1993	*/
1994	pVM->pgm.s.pTreesRC = MMHyperR3ToRC(pVM, pVM->pgm.s.pTreesR3);
1995
1996	/*
1997	* Ram ranges.
1998	*/
1999	if (pVM->pgm.s.pRamRangesR3)
2000	{
2001	pVM->pgm.s.pRamRangesRC = MMHyperR3ToRC(pVM, pVM->pgm.s.pRamRangesR3);
2002	for (PPGMRAMRANGE pCur = pVM->pgm.s.pRamRangesR3; pCur->pNextR3; pCur = pCur->pNextR3)
2003	pCur->pNextRC = MMHyperR3ToRC(pVM, pCur->pNextR3);
2004	}
2005
2006	/*
2007	* Update the two page directories with all page table mappings.
2008	* (One or more of them have changed, that's why we're here.)
2009	*/
2010	pVM->pgm.s.pMappingsRC = MMHyperR3ToRC(pVM, pVM->pgm.s.pMappingsR3);
2011	for (PPGMMAPPING pCur = pVM->pgm.s.pMappingsR3; pCur->pNextR3; pCur = pCur->pNextR3)
2012	pCur->pNextRC = MMHyperR3ToRC(pVM, pCur->pNextR3);
2013
2014	/* Relocate GC addresses of Page Tables. */
2015	for (PPGMMAPPING pCur = pVM->pgm.s.pMappingsR3; pCur; pCur = pCur->pNextR3)
2016	{
2017	for (RTHCUINT i = 0; i < pCur->cPTs; i++)
2018	{
2019	pCur->aPTs[i].pPTRC = MMHyperR3ToRC(pVM, pCur->aPTs[i].pPTR3);
2020	pCur->aPTs[i].paPaePTsRC = MMHyperR3ToRC(pVM, pCur->aPTs[i].paPaePTsR3);
2021	}
2022	}
2023
2024	/*
2025	* Dynamic page mapping area.
2026	*/
2027	pVM->pgm.s.paDynPageMap32BitPTEsGC += offDelta;
2028	pVM->pgm.s.paDynPageMapPaePTEsGC += offDelta;
2029	pVM->pgm.s.pbDynPageMapBaseGC += offDelta;
2030
2031	/*
2032	* The Zero page.
2033	*/
2034	pVM->pgm.s.pvZeroPgR0 = MMHyperR3ToR0(pVM, pVM->pgm.s.pvZeroPgR3);
2035	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
2036	AssertRelease(pVM->pgm.s.pvZeroPgR0 != NIL_RTR0PTR \|\| !VMMIsHwVirtExtForced(pVM));
2037	#else
2038	AssertRelease(pVM->pgm.s.pvZeroPgR0 != NIL_RTR0PTR);
2039	#endif
2040
2041	/*
2042	* Physical and virtual handlers.
2043	*/
2044	RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysHandlers, true, pgmR3RelocatePhysHandler, &offDelta);
2045	RTAvlroGCPtrDoWithAll(&pVM->pgm.s.pTreesR3->VirtHandlers, true, pgmR3RelocateVirtHandler, &offDelta);
2046	RTAvlroGCPtrDoWithAll(&pVM->pgm.s.pTreesR3->HyperVirtHandlers, true, pgmR3RelocateHyperVirtHandler, &offDelta);
2047
2048	/*
2049	* The page pool.
2050	*/
2051	pgmR3PoolRelocate(pVM);
2052	}
2053
2054
2055	/**
2056	* Callback function for relocating a physical access handler.
2057	*
2058	* @returns 0 (continue enum)
2059	* @param pNode Pointer to a PGMPHYSHANDLER node.
2060	* @param pvUser Pointer to the offDelta. This is a pointer to the delta since we're
2061	* not certain the delta will fit in a void pointer for all possible configs.
2062	*/
2063	static DECLCALLBACK(int) pgmR3RelocatePhysHandler(PAVLROGCPHYSNODECORE pNode, void *pvUser)
2064	{
2065	PPGMPHYSHANDLER pHandler = (PPGMPHYSHANDLER)pNode;
2066	RTGCINTPTR offDelta = *(PRTGCINTPTR)pvUser;
2067	if (pHandler->pfnHandlerRC)
2068	pHandler->pfnHandlerRC += offDelta;
2069	if (pHandler->pvUserRC >= 0x10000)
2070	pHandler->pvUserRC += offDelta;
2071	return 0;
2072	}
2073
2074
2075	/**
2076	* Callback function for relocating a virtual access handler.
2077	*
2078	* @returns 0 (continue enum)
2079	* @param pNode Pointer to a PGMVIRTHANDLER node.
2080	* @param pvUser Pointer to the offDelta. This is a pointer to the delta since we're
2081	* not certain the delta will fit in a void pointer for all possible configs.
2082	*/
2083	static DECLCALLBACK(int) pgmR3RelocateVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser)
2084	{
2085	PPGMVIRTHANDLER pHandler = (PPGMVIRTHANDLER)pNode;
2086	RTGCINTPTR offDelta = *(PRTGCINTPTR)pvUser;
2087	Assert( pHandler->enmType == PGMVIRTHANDLERTYPE_ALL
2088	\|\| pHandler->enmType == PGMVIRTHANDLERTYPE_WRITE);
2089	Assert(pHandler->pfnHandlerRC);
2090	pHandler->pfnHandlerRC += offDelta;
2091	return 0;
2092	}
2093
2094
2095	/**
2096	* Callback function for relocating a virtual access handler for the hypervisor mapping.
2097	*
2098	* @returns 0 (continue enum)
2099	* @param pNode Pointer to a PGMVIRTHANDLER node.
2100	* @param pvUser Pointer to the offDelta. This is a pointer to the delta since we're
2101	* not certain the delta will fit in a void pointer for all possible configs.
2102	*/
2103	static DECLCALLBACK(int) pgmR3RelocateHyperVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser)
2104	{
2105	PPGMVIRTHANDLER pHandler = (PPGMVIRTHANDLER)pNode;
2106	RTGCINTPTR offDelta = *(PRTGCINTPTR)pvUser;
2107	Assert(pHandler->enmType == PGMVIRTHANDLERTYPE_HYPERVISOR);
2108	Assert(pHandler->pfnHandlerRC);
2109	pHandler->pfnHandlerRC += offDelta;
2110	return 0;
2111	}
2112
2113
2114	/**
2115	* The VM is being reset.
2116	*
2117	* For the PGM component this means that any PD write monitors
2118	* needs to be removed.
2119	*
2120	* @param pVM VM handle.
2121	*/
2122	VMMR3DECL(void) PGMR3Reset(PVM pVM)
2123	{
2124	LogFlow(("PGMR3Reset:\n"));
2125	VM_ASSERT_EMT(pVM);
2126
2127	pgmLock(pVM);
2128
2129	/*
2130	* Unfix any fixed mappings and disable CR3 monitoring.
2131	*/
2132	pVM->pgm.s.fMappingsFixed = false;
2133	pVM->pgm.s.GCPtrMappingFixed = 0;
2134	pVM->pgm.s.cbMappingFixed = 0;
2135
2136	/* Exit the guest paging mode before the pgm pool gets reset.
2137	* Important to clean up the amd64 case.
2138	*/
2139	int rc = PGM_GST_PFN(Exit, pVM)(pVM);
2140	AssertRC(rc);
2141	#ifdef DEBUG
2142	DBGFR3InfoLog(pVM, "mappings", NULL);
2143	DBGFR3InfoLog(pVM, "handlers", "all nostat");
2144	#endif
2145
2146	/*
2147	* Reset the shadow page pool.
2148	*/
2149	pgmR3PoolReset(pVM);
2150
2151	/*
2152	* Re-init other members.
2153	*/
2154	pVM->pgm.s.fA20Enabled = true;
2155
2156	/*
2157	* Clear the FFs PGM owns.
2158	*/
2159	VM_FF_CLEAR(pVM, VM_FF_PGM_SYNC_CR3);
2160	VM_FF_CLEAR(pVM, VM_FF_PGM_SYNC_CR3_NON_GLOBAL);
2161
2162	/*
2163	* Reset (zero) RAM pages.
2164	*/
2165	rc = pgmR3PhysRamReset(pVM);
2166	if (RT_SUCCESS(rc))
2167	{
2168	#ifdef VBOX_WITH_NEW_PHYS_CODE
2169	/*
2170	* Reset (zero) shadow ROM pages.
2171	*/
2172	rc = pgmR3PhysRomReset(pVM);
2173	#endif
2174	if (RT_SUCCESS(rc))
2175	{
2176	/*
2177	* Switch mode back to real mode.
2178	*/
2179	rc = PGMR3ChangeMode(pVM, PGMMODE_REAL);
2180	STAM_REL_COUNTER_RESET(&pVM->pgm.s.cGuestModeChanges);
2181	}
2182	}
2183
2184	pgmUnlock(pVM);
2185	//return rc;
2186	AssertReleaseRC(rc);
2187	}
2188
2189
2190	#ifdef VBOX_STRICT
2191	/**
2192	* VM state change callback for clearing fNoMorePhysWrites after
2193	* a snapshot has been created.
2194	*/
2195	static DECLCALLBACK(void) pgmR3ResetNoMorePhysWritesFlag(PVM pVM, VMSTATE enmState, VMSTATE enmOldState, void *pvUser)
2196	{
2197	if (enmState == VMSTATE_RUNNING)
2198	pVM->pgm.s.fNoMorePhysWrites = false;
2199	}
2200	#endif
2201
2202
2203	/**
2204	* Terminates the PGM.
2205	*
2206	* @returns VBox status code.
2207	* @param pVM Pointer to VM structure.
2208	*/
2209	VMMR3DECL(int) PGMR3Term(PVM pVM)
2210	{
2211	return PDMR3CritSectDelete(&pVM->pgm.s.CritSect);
2212	}
2213
2214
2215	/**
2216	* Terminates the per-VCPU PGM.
2217	*
2218	* Termination means cleaning up and freeing all resources,
2219	* the VM it self is at this point powered off or suspended.
2220	*
2221	* @returns VBox status code.
2222	* @param pVM The VM to operate on.
2223	*/
2224	VMMR3DECL(int) PGMR3TermCPU(PVM pVM)
2225	{
2226	return 0;
2227	}
2228
2229
2230	/**
2231	* Execute state save operation.
2232	*
2233	* @returns VBox status code.
2234	* @param pVM VM Handle.
2235	* @param pSSM SSM operation handle.
2236	*/
2237	static DECLCALLBACK(int) pgmR3Save(PVM pVM, PSSMHANDLE pSSM)
2238	{
2239	PPGM pPGM = &pVM->pgm.s;
2240
2241	/* No more writes to physical memory after this point! */
2242	pVM->pgm.s.fNoMorePhysWrites = true;
2243
2244	/*
2245	* Save basic data (required / unaffected by relocation).
2246	*/
2247	#if 1
2248	SSMR3PutBool(pSSM, pPGM->fMappingsFixed);
2249	#else
2250	SSMR3PutUInt(pSSM, pPGM->fMappingsFixed);
2251	#endif
2252	SSMR3PutGCPtr(pSSM, pPGM->GCPtrMappingFixed);
2253	SSMR3PutU32(pSSM, pPGM->cbMappingFixed);
2254	SSMR3PutUInt(pSSM, pPGM->cbRamSize);
2255	SSMR3PutGCPhys(pSSM, pPGM->GCPhysA20Mask);
2256	SSMR3PutUInt(pSSM, pPGM->fA20Enabled);
2257	SSMR3PutUInt(pSSM, pPGM->fSyncFlags);
2258	SSMR3PutUInt(pSSM, pPGM->enmGuestMode);
2259	SSMR3PutU32(pSSM, ~0); /* Separator. */
2260
2261	/*
2262	* The guest mappings.
2263	*/
2264	uint32_t i = 0;
2265	for (PPGMMAPPING pMapping = pPGM->pMappingsR3; pMapping; pMapping = pMapping->pNextR3, i++)
2266	{
2267	SSMR3PutU32(pSSM, i);
2268	SSMR3PutStrZ(pSSM, pMapping->pszDesc); /* This is the best unique id we have... */
2269	SSMR3PutGCPtr(pSSM, pMapping->GCPtr);
2270	SSMR3PutGCUIntPtr(pSSM, pMapping->cPTs);
2271	/* flags are done by the mapping owners! */
2272	}
2273	SSMR3PutU32(pSSM, ~0); /* terminator. */
2274
2275	/*
2276	* Ram range flags and bits.
2277	*/
2278	i = 0;
2279	for (PPGMRAMRANGE pRam = pPGM->pRamRangesR3; pRam; pRam = pRam->pNextR3, i++)
2280	{
2281	/** @todo MMIO ranges may move (PCI reconfig), we currently assume they don't. */
2282
2283	SSMR3PutU32(pSSM, i);
2284	SSMR3PutGCPhys(pSSM, pRam->GCPhys);
2285	SSMR3PutGCPhys(pSSM, pRam->GCPhysLast);
2286	SSMR3PutGCPhys(pSSM, pRam->cb);
2287	SSMR3PutU8(pSSM, !!pRam->pvR3); /* boolean indicating memory or not. */
2288
2289	/* Flags. */
2290	const unsigned cPages = pRam->cb >> PAGE_SHIFT;
2291	for (unsigned iPage = 0; iPage < cPages; iPage++)
2292	SSMR3PutU16(pSSM, (uint16_t)(pRam->aPages[iPage].HCPhys & ~X86_PTE_PAE_PG_MASK)); /** @todo PAGE FLAGS */
2293
2294	/* any memory associated with the range. */
2295	if (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)
2296	{
2297	for (unsigned iChunk = 0; iChunk < (pRam->cb >> PGM_DYNAMIC_CHUNK_SHIFT); iChunk++)
2298	{
2299	if (pRam->paChunkR3Ptrs[iChunk])
2300	{
2301	SSMR3PutU8(pSSM, 1); /* chunk present */
2302	SSMR3PutMem(pSSM, (void *)pRam->paChunkR3Ptrs[iChunk], PGM_DYNAMIC_CHUNK_SIZE);
2303	}
2304	else
2305	SSMR3PutU8(pSSM, 0); /* no chunk present */
2306	}
2307	}
2308	else if (pRam->pvR3)
2309	{
2310	int rc = SSMR3PutMem(pSSM, pRam->pvR3, pRam->cb);
2311	if (RT_FAILURE(rc))
2312	{
2313	Log(("pgmR3Save: SSMR3PutMem(, %p, %#x) -> %Rrc\n", pRam->pvR3, pRam->cb, rc));
2314	return rc;
2315	}
2316	}
2317	}
2318	return SSMR3PutU32(pSSM, ~0); /* terminator. */
2319	}
2320
2321
2322	/**
2323	* Execute state load operation.
2324	*
2325	* @returns VBox status code.
2326	* @param pVM VM Handle.
2327	* @param pSSM SSM operation handle.
2328	* @param u32Version Data layout version.
2329	*/
2330	static DECLCALLBACK(int) pgmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version)
2331	{
2332	/*
2333	* Validate version.
2334	*/
2335	if (u32Version != PGM_SAVED_STATE_VERSION)
2336	{
2337	AssertMsgFailed(("pgmR3Load: Invalid version u32Version=%d (current %d)!\n", u32Version, PGM_SAVED_STATE_VERSION));
2338	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
2339	}
2340
2341	/*
2342	* Call the reset function to make sure all the memory is cleared.
2343	*/
2344	PGMR3Reset(pVM);
2345
2346	/*
2347	* Load basic data (required / unaffected by relocation).
2348	*/
2349	PPGM pPGM = &pVM->pgm.s;
2350	#if 1
2351	SSMR3GetBool(pSSM, &pPGM->fMappingsFixed);
2352	#else
2353	uint32_t u;
2354	SSMR3GetU32(pSSM, &u);
2355	pPGM->fMappingsFixed = u;
2356	#endif
2357	SSMR3GetGCPtr(pSSM, &pPGM->GCPtrMappingFixed);
2358	SSMR3GetU32(pSSM, &pPGM->cbMappingFixed);
2359
2360	RTUINT cbRamSize;
2361	int rc = SSMR3GetU32(pSSM, &cbRamSize);
2362	if (RT_FAILURE(rc))
2363	return rc;
2364	if (cbRamSize != pPGM->cbRamSize)
2365	return VERR_SSM_LOAD_MEMORY_SIZE_MISMATCH;
2366	SSMR3GetGCPhys(pSSM, &pPGM->GCPhysA20Mask);
2367	SSMR3GetUInt(pSSM, &pPGM->fA20Enabled);
2368	SSMR3GetUInt(pSSM, &pPGM->fSyncFlags);
2369	RTUINT uGuestMode;
2370	SSMR3GetUInt(pSSM, &uGuestMode);
2371	pPGM->enmGuestMode = (PGMMODE)uGuestMode;
2372
2373	/* check separator. */
2374	uint32_t u32Sep;
2375	SSMR3GetU32(pSSM, &u32Sep);
2376	if (RT_FAILURE(rc))
2377	return rc;
2378	if (u32Sep != (uint32_t)~0)
2379	{
2380	AssertMsgFailed(("u32Sep=%#x (first)\n", u32Sep));
2381	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2382	}
2383
2384	/*
2385	* The guest mappings.
2386	*/
2387	uint32_t i = 0;
2388	for (;; i++)
2389	{
2390	/* Check the seqence number / separator. */
2391	rc = SSMR3GetU32(pSSM, &u32Sep);
2392	if (RT_FAILURE(rc))
2393	return rc;
2394	if (u32Sep == ~0U)
2395	break;
2396	if (u32Sep != i)
2397	{
2398	AssertMsgFailed(("u32Sep=%#x (last)\n", u32Sep));
2399	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2400	}
2401
2402	/* get the mapping details. */
2403	char szDesc[256];
2404	szDesc[0] = '\0';
2405	rc = SSMR3GetStrZ(pSSM, szDesc, sizeof(szDesc));
2406	if (RT_FAILURE(rc))
2407	return rc;
2408	RTGCPTR GCPtr;
2409	SSMR3GetGCPtr(pSSM, &GCPtr);
2410	RTGCPTR cPTs;
2411	rc = SSMR3GetGCUIntPtr(pSSM, &cPTs);
2412	if (RT_FAILURE(rc))
2413	return rc;
2414
2415	/* find matching range. */
2416	PPGMMAPPING pMapping;
2417	for (pMapping = pPGM->pMappingsR3; pMapping; pMapping = pMapping->pNextR3)
2418	if ( pMapping->cPTs == cPTs
2419	&& !strcmp(pMapping->pszDesc, szDesc))
2420	break;
2421	if (!pMapping)
2422	{
2423	LogRel(("Couldn't find mapping: cPTs=%#x szDesc=%s (GCPtr=%RGv)\n",
2424	cPTs, szDesc, GCPtr));
2425	AssertFailed();
2426	return VERR_SSM_LOAD_CONFIG_MISMATCH;
2427	}
2428
2429	/* relocate it. */
2430	if (pMapping->GCPtr != GCPtr)
2431	{
2432	AssertMsg((GCPtr >> X86_PD_SHIFT << X86_PD_SHIFT) == GCPtr, ("GCPtr=%RGv\n", GCPtr));
2433	pgmR3MapRelocate(pVM, pMapping, pMapping->GCPtr, GCPtr);
2434	}
2435	else
2436	Log(("pgmR3Load: '%s' needed no relocation (%RGv)\n", szDesc, GCPtr));
2437	}
2438
2439	/*
2440	* Ram range flags and bits.
2441	*/
2442	i = 0;
2443	for (PPGMRAMRANGE pRam = pPGM->pRamRangesR3; pRam; pRam = pRam->pNextR3, i++)
2444	{
2445	/** @todo MMIO ranges may move (PCI reconfig), we currently assume they don't. */
2446	/* Check the seqence number / separator. */
2447	rc = SSMR3GetU32(pSSM, &u32Sep);
2448	if (RT_FAILURE(rc))
2449	return rc;
2450	if (u32Sep == ~0U)
2451	break;
2452	if (u32Sep != i)
2453	{
2454	AssertMsgFailed(("u32Sep=%#x (last)\n", u32Sep));
2455	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2456	}
2457
2458	/* Get the range details. */
2459	RTGCPHYS GCPhys;
2460	SSMR3GetGCPhys(pSSM, &GCPhys);
2461	RTGCPHYS GCPhysLast;
2462	SSMR3GetGCPhys(pSSM, &GCPhysLast);
2463	RTGCPHYS cb;
2464	SSMR3GetGCPhys(pSSM, &cb);
2465	uint8_t fHaveBits;
2466	rc = SSMR3GetU8(pSSM, &fHaveBits);
2467	if (RT_FAILURE(rc))
2468	return rc;
2469	if (fHaveBits & ~1)
2470	{
2471	AssertMsgFailed(("u32Sep=%#x (last)\n", u32Sep));
2472	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2473	}
2474
2475	/* This is a horribly ugly hack for an 2.0 -> 2.1 incompatibility
2476	in the VMMDev PCI regions. VMMDev Heap was added in 2.1 and we
2477	simply skip it here if it's not in the saved state. */
2478	if ( ( GCPhys != pRam->GCPhys
2479	\|\| GCPhysLast != pRam->GCPhysLast
2480	\|\| cb != pRam->cb
2481	\|\| fHaveBits != !!pRam->pvR3)
2482	&& !strcmp(pRam->pszDesc, "VMMDev Heap")
2483	&& pRam->pNextR3)
2484	pRam = pRam->pNextR3; /* don't increment i. */
2485
2486	/* Match it up with the current range. */
2487	if ( GCPhys != pRam->GCPhys
2488	\|\| GCPhysLast != pRam->GCPhysLast
2489	\|\| cb != pRam->cb
2490	\|\| fHaveBits != !!pRam->pvR3)
2491	{
2492	LogRel(("Ram range: %RGp-%RGp %RGp bytes %s\n"
2493	"State : %RGp-%RGp %RGp bytes %s\n",
2494	pRam->GCPhys, pRam->GCPhysLast, pRam->cb, pRam->pvR3 ? "bits" : "nobits",
2495	GCPhys, GCPhysLast, cb, fHaveBits ? "bits" : "nobits"));
2496	/*
2497	* If we're loading a state for debugging purpose, don't make a fuss if
2498	* the MMIO[2] and ROM stuff isn't 100% right, just skip the mismatches.
2499	*/
2500	if ( SSMR3HandleGetAfter(pSSM) != SSMAFTER_DEBUG_IT
2501	\|\| GCPhys < 8 * _1M)
2502	AssertFailedReturn(VERR_SSM_LOAD_CONFIG_MISMATCH);
2503
2504	RTGCPHYS cPages = ((GCPhysLast - GCPhys) + 1) >> PAGE_SHIFT;
2505	while (cPages-- > 0)
2506	{
2507	uint16_t u16Ignore;
2508	SSMR3GetU16(pSSM, &u16Ignore);
2509	}
2510	continue;
2511	}
2512
2513	/* Flags. */
2514	const unsigned cPages = pRam->cb >> PAGE_SHIFT;
2515	for (unsigned iPage = 0; iPage < cPages; iPage++)
2516	{
2517	uint16_t u16 = 0;
2518	SSMR3GetU16(pSSM, &u16);
2519	u16 &= PAGE_OFFSET_MASK & ~( RT_BIT(4) \| RT_BIT(5) \| RT_BIT(6)
2520	\| RT_BIT(7) \| RT_BIT(8) \| RT_BIT(9) \| RT_BIT(10) );
2521	// &= MM_RAM_FLAGS_DYNAMIC_ALLOC \| MM_RAM_FLAGS_RESERVED \| MM_RAM_FLAGS_ROM \| MM_RAM_FLAGS_MMIO \| MM_RAM_FLAGS_MMIO2
2522	pRam->aPages[iPage].HCPhys = PGM_PAGE_GET_HCPHYS(&pRam->aPages[iPage]) \| (RTHCPHYS)u16; /** @todo PAGE FLAGS */
2523	}
2524
2525	/* any memory associated with the range. */
2526	if (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)
2527	{
2528	for (unsigned iChunk = 0; iChunk < (pRam->cb >> PGM_DYNAMIC_CHUNK_SHIFT); iChunk++)
2529	{
2530	uint8_t fValidChunk;
2531
2532	rc = SSMR3GetU8(pSSM, &fValidChunk);
2533	if (RT_FAILURE(rc))
2534	return rc;
2535	if (fValidChunk > 1)
2536	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2537
2538	if (fValidChunk)
2539	{
2540	if (!pRam->paChunkR3Ptrs[iChunk])
2541	{
2542	rc = pgmr3PhysGrowRange(pVM, pRam->GCPhys + iChunk * PGM_DYNAMIC_CHUNK_SIZE);
2543	if (RT_FAILURE(rc))
2544	return rc;
2545	}
2546	Assert(pRam->paChunkR3Ptrs[iChunk]);
2547
2548	SSMR3GetMem(pSSM, (void *)pRam->paChunkR3Ptrs[iChunk], PGM_DYNAMIC_CHUNK_SIZE);
2549	}
2550	/* else nothing to do */
2551	}
2552	}
2553	else if (pRam->pvR3)
2554	{
2555	int rc = SSMR3GetMem(pSSM, pRam->pvR3, pRam->cb);
2556	if (RT_FAILURE(rc))
2557	{
2558	Log(("pgmR3Save: SSMR3GetMem(, %p, %#x) -> %Rrc\n", pRam->pvR3, pRam->cb, rc));
2559	return rc;
2560	}
2561	}
2562	}
2563
2564	/*
2565	* We require a full resync now.
2566	*/
2567	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3_NON_GLOBAL);
2568	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
2569	pPGM->fSyncFlags \|= PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL;
2570	pPGM->fPhysCacheFlushPending = true;
2571	pgmR3HandlerPhysicalUpdateAll(pVM);
2572
2573	/*
2574	* Change the paging mode.
2575	*/
2576	rc = PGMR3ChangeMode(pVM, pPGM->enmGuestMode);
2577
2578	/* Restore pVM->pgm.s.GCPhysCR3. */
2579	Assert(pVM->pgm.s.GCPhysCR3 == NIL_RTGCPHYS);
2580	RTGCPHYS GCPhysCR3 = CPUMGetGuestCR3(pVM);
2581	if ( pVM->pgm.s.enmGuestMode == PGMMODE_PAE
2582	\|\| pVM->pgm.s.enmGuestMode == PGMMODE_PAE_NX
2583	\|\| pVM->pgm.s.enmGuestMode == PGMMODE_AMD64
2584	\|\| pVM->pgm.s.enmGuestMode == PGMMODE_AMD64_NX)
2585	GCPhysCR3 = (GCPhysCR3 & X86_CR3_PAE_PAGE_MASK);
2586	else
2587	GCPhysCR3 = (GCPhysCR3 & X86_CR3_PAGE_MASK);
2588	pVM->pgm.s.GCPhysCR3 = GCPhysCR3;
2589
2590	return rc;
2591	}
2592
2593
2594	/**
2595	* Show paging mode.
2596	*
2597	* @param pVM VM Handle.
2598	* @param pHlp The info helpers.
2599	* @param pszArgs "all" (default), "guest", "shadow" or "host".
2600	*/
2601	static DECLCALLBACK(void) pgmR3InfoMode(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2602	{
2603	/* digest argument. */
2604	bool fGuest, fShadow, fHost;
2605	if (pszArgs)
2606	pszArgs = RTStrStripL(pszArgs);
2607	if (!pszArgs \|\| !*pszArgs \|\| strstr(pszArgs, "all"))
2608	fShadow = fHost = fGuest = true;
2609	else
2610	{
2611	fShadow = fHost = fGuest = false;
2612	if (strstr(pszArgs, "guest"))
2613	fGuest = true;
2614	if (strstr(pszArgs, "shadow"))
2615	fShadow = true;
2616	if (strstr(pszArgs, "host"))
2617	fHost = true;
2618	}
2619
2620	/* print info. */
2621	if (fGuest)
2622	pHlp->pfnPrintf(pHlp, "Guest paging mode: %s, changed %RU64 times, A20 %s\n",
2623	PGMGetModeName(pVM->pgm.s.enmGuestMode), pVM->pgm.s.cGuestModeChanges.c,
2624	pVM->pgm.s.fA20Enabled ? "enabled" : "disabled");
2625	if (fShadow)
2626	pHlp->pfnPrintf(pHlp, "Shadow paging mode: %s\n", PGMGetModeName(pVM->pgm.s.enmShadowMode));
2627	if (fHost)
2628	{
2629	const char *psz;
2630	switch (pVM->pgm.s.enmHostMode)
2631	{
2632	case SUPPAGINGMODE_INVALID: psz = "invalid"; break;
2633	case SUPPAGINGMODE_32_BIT: psz = "32-bit"; break;
2634	case SUPPAGINGMODE_32_BIT_GLOBAL: psz = "32-bit+G"; break;
2635	case SUPPAGINGMODE_PAE: psz = "PAE"; break;
2636	case SUPPAGINGMODE_PAE_GLOBAL: psz = "PAE+G"; break;
2637	case SUPPAGINGMODE_PAE_NX: psz = "PAE+NX"; break;
2638	case SUPPAGINGMODE_PAE_GLOBAL_NX: psz = "PAE+G+NX"; break;
2639	case SUPPAGINGMODE_AMD64: psz = "AMD64"; break;
2640	case SUPPAGINGMODE_AMD64_GLOBAL: psz = "AMD64+G"; break;
2641	case SUPPAGINGMODE_AMD64_NX: psz = "AMD64+NX"; break;
2642	case SUPPAGINGMODE_AMD64_GLOBAL_NX: psz = "AMD64+G+NX"; break;
2643	default: psz = "unknown"; break;
2644	}
2645	pHlp->pfnPrintf(pHlp, "Host paging mode: %s\n", psz);
2646	}
2647	}
2648
2649
2650	/**
2651	* Dump registered MMIO ranges to the log.
2652	*
2653	* @param pVM VM Handle.
2654	* @param pHlp The info helpers.
2655	* @param pszArgs Arguments, ignored.
2656	*/
2657	static DECLCALLBACK(void) pgmR3PhysInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2658	{
2659	NOREF(pszArgs);
2660	pHlp->pfnPrintf(pHlp,
2661	"RAM ranges (pVM=%p)\n"
2662	"%.s %.s\n",
2663	pVM,
2664	sizeof(RTGCPHYS) * 4 + 1, "GC Phys Range ",
2665	sizeof(RTHCPTR) * 2, "pvHC ");
2666
2667	for (PPGMRAMRANGE pCur = pVM->pgm.s.pRamRangesR3; pCur; pCur = pCur->pNextR3)
2668	pHlp->pfnPrintf(pHlp,
2669	"%RGp-%RGp %RHv %s\n",
2670	pCur->GCPhys,
2671	pCur->GCPhysLast,
2672	pCur->pvR3,
2673	pCur->pszDesc);
2674	}
2675
2676	/**
2677	* Dump the page directory to the log.
2678	*
2679	* @param pVM VM Handle.
2680	* @param pHlp The info helpers.
2681	* @param pszArgs Arguments, ignored.
2682	*/
2683	static DECLCALLBACK(void) pgmR3InfoCr3(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2684	{
2685	/** @todo fix this! Convert the PGMR3DumpHierarchyHC functions to do guest stuff. */
2686	/* Big pages supported? */
2687	const bool fPSE = !!(CPUMGetGuestCR4(pVM) & X86_CR4_PSE);
2688
2689	/* Global pages supported? */
2690	const bool fPGE = !!(CPUMGetGuestCR4(pVM) & X86_CR4_PGE);
2691
2692	NOREF(pszArgs);
2693
2694	/*
2695	* Get page directory addresses.
2696	*/
2697	PX86PD pPDSrc = pVM->pgm.s.pGst32BitPdR3;
2698	Assert(pPDSrc);
2699	Assert(PGMPhysGCPhys2R3PtrAssert(pVM, (RTGCPHYS)(CPUMGetGuestCR3(pVM) & X86_CR3_PAGE_MASK), sizeof(*pPDSrc)) == pPDSrc);
2700
2701	/*
2702	* Iterate the page directory.
2703	*/
2704	for (unsigned iPD = 0; iPD < RT_ELEMENTS(pPDSrc->a); iPD++)
2705	{
2706	X86PDE PdeSrc = pPDSrc->a[iPD];
2707	if (PdeSrc.n.u1Present)
2708	{
2709	if (PdeSrc.b.u1Size && fPSE)
2710	pHlp->pfnPrintf(pHlp,
2711	"%04X - %RGp P=%d U=%d RW=%d G=%d - BIG\n",
2712	iPD,
2713	pgmGstGet4MBPhysPage(&pVM->pgm.s, PdeSrc),
2714	PdeSrc.b.u1Present, PdeSrc.b.u1User, PdeSrc.b.u1Write, PdeSrc.b.u1Global && fPGE);
2715	else
2716	pHlp->pfnPrintf(pHlp,
2717	"%04X - %RGp P=%d U=%d RW=%d [G=%d]\n",
2718	iPD,
2719	(RTGCPHYS)(PdeSrc.u & X86_PDE_PG_MASK),
2720	PdeSrc.n.u1Present, PdeSrc.n.u1User, PdeSrc.n.u1Write, PdeSrc.b.u1Global && fPGE);
2721	}
2722	}
2723	}
2724
2725
2726	/**
2727	* Serivce a VMMCALLHOST_PGM_LOCK call.
2728	*
2729	* @returns VBox status code.
2730	* @param pVM The VM handle.
2731	*/
2732	VMMR3DECL(int) PGMR3LockCall(PVM pVM)
2733	{
2734	int rc = PDMR3CritSectEnterEx(&pVM->pgm.s.CritSect, true /* fHostCall */);
2735	AssertRC(rc);
2736	return rc;
2737	}
2738
2739
2740	/**
2741	* Converts a PGMMODE value to a PGM_TYPE_* \#define.
2742	*
2743	* @returns PGM_TYPE_*.
2744	* @param pgmMode The mode value to convert.
2745	*/
2746	DECLINLINE(unsigned) pgmModeToType(PGMMODE pgmMode)
2747	{
2748	switch (pgmMode)
2749	{
2750	case PGMMODE_REAL: return PGM_TYPE_REAL;
2751	case PGMMODE_PROTECTED: return PGM_TYPE_PROT;
2752	case PGMMODE_32_BIT: return PGM_TYPE_32BIT;
2753	case PGMMODE_PAE:
2754	case PGMMODE_PAE_NX: return PGM_TYPE_PAE;
2755	case PGMMODE_AMD64:
2756	case PGMMODE_AMD64_NX: return PGM_TYPE_AMD64;
2757	case PGMMODE_NESTED: return PGM_TYPE_NESTED;
2758	case PGMMODE_EPT: return PGM_TYPE_EPT;
2759	default:
2760	AssertFatalMsgFailed(("pgmMode=%d\n", pgmMode));
2761	}
2762	}
2763
2764
2765	/**
2766	* Gets the index into the paging mode data array of a SHW+GST mode.
2767	*
2768	* @returns PGM::paPagingData index.
2769	* @param uShwType The shadow paging mode type.
2770	* @param uGstType The guest paging mode type.
2771	*/
2772	DECLINLINE(unsigned) pgmModeDataIndex(unsigned uShwType, unsigned uGstType)
2773	{
2774	Assert(uShwType >= PGM_TYPE_32BIT && uShwType <= PGM_TYPE_MAX);
2775	Assert(uGstType >= PGM_TYPE_REAL && uGstType <= PGM_TYPE_AMD64);
2776	return (uShwType - PGM_TYPE_32BIT) * (PGM_TYPE_AMD64 - PGM_TYPE_REAL + 1)
2777	+ (uGstType - PGM_TYPE_REAL);
2778	}
2779
2780
2781	/**
2782	* Gets the index into the paging mode data array of a SHW+GST mode.
2783	*
2784	* @returns PGM::paPagingData index.
2785	* @param enmShw The shadow paging mode.
2786	* @param enmGst The guest paging mode.
2787	*/
2788	DECLINLINE(unsigned) pgmModeDataIndexByMode(PGMMODE enmShw, PGMMODE enmGst)
2789	{
2790	Assert(enmShw >= PGMMODE_32_BIT && enmShw <= PGMMODE_MAX);
2791	Assert(enmGst > PGMMODE_INVALID && enmGst < PGMMODE_MAX);
2792	return pgmModeDataIndex(pgmModeToType(enmShw), pgmModeToType(enmGst));
2793	}
2794
2795
2796	/**
2797	* Calculates the max data index.
2798	* @returns The number of entries in the paging data array.
2799	*/
2800	DECLINLINE(unsigned) pgmModeDataMaxIndex(void)
2801	{
2802	return pgmModeDataIndex(PGM_TYPE_MAX, PGM_TYPE_AMD64) + 1;
2803	}
2804
2805
2806	/**
2807	* Initializes the paging mode data kept in PGM::paModeData.
2808	*
2809	* @param pVM The VM handle.
2810	* @param fResolveGCAndR0 Indicate whether or not GC and Ring-0 symbols can be resolved now.
2811	* This is used early in the init process to avoid trouble with PDM
2812	* not being initialized yet.
2813	*/
2814	static int pgmR3ModeDataInit(PVM pVM, bool fResolveGCAndR0)
2815	{
2816	PPGMMODEDATA pModeData;
2817	int rc;
2818
2819	/*
2820	* Allocate the array on the first call.
2821	*/
2822	if (!pVM->pgm.s.paModeData)
2823	{
2824	pVM->pgm.s.paModeData = (PPGMMODEDATA)MMR3HeapAllocZ(pVM, MM_TAG_PGM, sizeof(PGMMODEDATA) * pgmModeDataMaxIndex());
2825	AssertReturn(pVM->pgm.s.paModeData, VERR_NO_MEMORY);
2826	}
2827
2828	/*
2829	* Initialize the array entries.
2830	*/
2831	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_32BIT, PGM_TYPE_REAL)];
2832	pModeData->uShwType = PGM_TYPE_32BIT;
2833	pModeData->uGstType = PGM_TYPE_REAL;
2834	rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2835	rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2836	rc = PGM_BTH_NAME_32BIT_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2837
2838	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_32BIT, PGMMODE_PROTECTED)];
2839	pModeData->uShwType = PGM_TYPE_32BIT;
2840	pModeData->uGstType = PGM_TYPE_PROT;
2841	rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2842	rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2843	rc = PGM_BTH_NAME_32BIT_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2844
2845	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_32BIT, PGM_TYPE_32BIT)];
2846	pModeData->uShwType = PGM_TYPE_32BIT;
2847	pModeData->uGstType = PGM_TYPE_32BIT;
2848	rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2849	rc = PGM_GST_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2850	rc = PGM_BTH_NAME_32BIT_32BIT(InitData)(pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2851
2852	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_REAL)];
2853	pModeData->uShwType = PGM_TYPE_PAE;
2854	pModeData->uGstType = PGM_TYPE_REAL;
2855	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2856	rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2857	rc = PGM_BTH_NAME_PAE_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2858
2859	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_PROT)];
2860	pModeData->uShwType = PGM_TYPE_PAE;
2861	pModeData->uGstType = PGM_TYPE_PROT;
2862	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2863	rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2864	rc = PGM_BTH_NAME_PAE_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2865
2866	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_32BIT)];
2867	pModeData->uShwType = PGM_TYPE_PAE;
2868	pModeData->uGstType = PGM_TYPE_32BIT;
2869	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2870	rc = PGM_GST_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2871	rc = PGM_BTH_NAME_PAE_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2872
2873	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_PAE)];
2874	pModeData->uShwType = PGM_TYPE_PAE;
2875	pModeData->uGstType = PGM_TYPE_PAE;
2876	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2877	rc = PGM_GST_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2878	rc = PGM_BTH_NAME_PAE_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2879
2880	#ifdef VBOX_WITH_64_BITS_GUESTS
2881	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_AMD64, PGM_TYPE_AMD64)];
2882	pModeData->uShwType = PGM_TYPE_AMD64;
2883	pModeData->uGstType = PGM_TYPE_AMD64;
2884	rc = PGM_SHW_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2885	rc = PGM_GST_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2886	rc = PGM_BTH_NAME_AMD64_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2887	#endif
2888
2889	/* The nested paging mode. */
2890	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_REAL)];
2891	pModeData->uShwType = PGM_TYPE_NESTED;
2892	pModeData->uGstType = PGM_TYPE_REAL;
2893	rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2894	rc = PGM_BTH_NAME_NESTED_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2895
2896	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGMMODE_PROTECTED)];
2897	pModeData->uShwType = PGM_TYPE_NESTED;
2898	pModeData->uGstType = PGM_TYPE_PROT;
2899	rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2900	rc = PGM_BTH_NAME_NESTED_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2901
2902	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_32BIT)];
2903	pModeData->uShwType = PGM_TYPE_NESTED;
2904	pModeData->uGstType = PGM_TYPE_32BIT;
2905	rc = PGM_GST_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2906	rc = PGM_BTH_NAME_NESTED_32BIT(InitData)(pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2907
2908	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_PAE)];
2909	pModeData->uShwType = PGM_TYPE_NESTED;
2910	pModeData->uGstType = PGM_TYPE_PAE;
2911	rc = PGM_GST_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2912	rc = PGM_BTH_NAME_NESTED_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2913
2914	#ifdef VBOX_WITH_64_BITS_GUESTS
2915	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_AMD64)];
2916	pModeData->uShwType = PGM_TYPE_NESTED;
2917	pModeData->uGstType = PGM_TYPE_AMD64;
2918	rc = PGM_GST_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2919	rc = PGM_BTH_NAME_NESTED_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2920	#endif
2921
2922	/* The shadow part of the nested callback mode depends on the host paging mode (AMD-V only). */
2923	switch (pVM->pgm.s.enmHostMode)
2924	{
2925	#if HC_ARCH_BITS == 32
2926	case SUPPAGINGMODE_32_BIT:
2927	case SUPPAGINGMODE_32_BIT_GLOBAL:
2928	for (unsigned i = PGM_TYPE_REAL; i <= PGM_TYPE_PAE; i++)
2929	{
2930	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, i)];
2931	rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2932	}
2933	# ifdef VBOX_WITH_64_BITS_GUESTS
2934	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_AMD64)];
2935	rc = PGM_SHW_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2936	# endif
2937	break;
2938
2939	case SUPPAGINGMODE_PAE:
2940	case SUPPAGINGMODE_PAE_NX:
2941	case SUPPAGINGMODE_PAE_GLOBAL:
2942	case SUPPAGINGMODE_PAE_GLOBAL_NX:
2943	for (unsigned i = PGM_TYPE_REAL; i <= PGM_TYPE_PAE; i++)
2944	{
2945	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, i)];
2946	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2947	}
2948	# ifdef VBOX_WITH_64_BITS_GUESTS
2949	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_AMD64)];
2950	rc = PGM_SHW_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2951	# endif
2952	break;
2953	#endif /* HC_ARCH_BITS == 32 */
2954
2955	#if HC_ARCH_BITS == 64 \|\| defined(RT_OS_DARWIN)
2956	case SUPPAGINGMODE_AMD64:
2957	case SUPPAGINGMODE_AMD64_GLOBAL:
2958	case SUPPAGINGMODE_AMD64_NX:
2959	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
2960	# ifdef VBOX_WITH_64_BITS_GUESTS
2961	for (unsigned i = PGM_TYPE_REAL; i <= PGM_TYPE_AMD64; i++)
2962	# else
2963	for (unsigned i = PGM_TYPE_REAL; i <= PGM_TYPE_PAE; i++)
2964	# endif
2965	{
2966	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, i)];
2967	rc = PGM_SHW_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2968	}
2969	break;
2970	#endif /* HC_ARCH_BITS == 64 \|\| RT_OS_DARWIN */
2971
2972	default:
2973	AssertFailed();
2974	break;
2975	}
2976
2977	/* Extended paging (EPT) / Intel VT-x */
2978	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_REAL)];
2979	pModeData->uShwType = PGM_TYPE_EPT;
2980	pModeData->uGstType = PGM_TYPE_REAL;
2981	rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2982	rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2983	rc = PGM_BTH_NAME_EPT_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2984
2985	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_PROT)];
2986	pModeData->uShwType = PGM_TYPE_EPT;
2987	pModeData->uGstType = PGM_TYPE_PROT;
2988	rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2989	rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2990	rc = PGM_BTH_NAME_EPT_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2991
2992	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_32BIT)];
2993	pModeData->uShwType = PGM_TYPE_EPT;
2994	pModeData->uGstType = PGM_TYPE_32BIT;
2995	rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2996	rc = PGM_GST_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2997	rc = PGM_BTH_NAME_EPT_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2998
2999	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_PAE)];
3000	pModeData->uShwType = PGM_TYPE_EPT;
3001	pModeData->uGstType = PGM_TYPE_PAE;
3002	rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3003	rc = PGM_GST_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3004	rc = PGM_BTH_NAME_EPT_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3005
3006	#ifdef VBOX_WITH_64_BITS_GUESTS
3007	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_AMD64)];
3008	pModeData->uShwType = PGM_TYPE_EPT;
3009	pModeData->uGstType = PGM_TYPE_AMD64;
3010	rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3011	rc = PGM_GST_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3012	rc = PGM_BTH_NAME_EPT_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3013	#endif
3014	return VINF_SUCCESS;
3015	}
3016
3017
3018	/**
3019	* Switch to different (or relocated in the relocate case) mode data.
3020	*
3021	* @param pVM The VM handle.
3022	* @param enmShw The the shadow paging mode.
3023	* @param enmGst The the guest paging mode.
3024	*/
3025	static void pgmR3ModeDataSwitch(PVM pVM, PGMMODE enmShw, PGMMODE enmGst)
3026	{
3027	PPGMMODEDATA pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndexByMode(enmShw, enmGst)];
3028
3029	Assert(pModeData->uGstType == pgmModeToType(enmGst));
3030	Assert(pModeData->uShwType == pgmModeToType(enmShw));
3031
3032	/* shadow */
3033	pVM->pgm.s.pfnR3ShwRelocate = pModeData->pfnR3ShwRelocate;
3034	pVM->pgm.s.pfnR3ShwExit = pModeData->pfnR3ShwExit;
3035	pVM->pgm.s.pfnR3ShwGetPage = pModeData->pfnR3ShwGetPage;
3036	Assert(pVM->pgm.s.pfnR3ShwGetPage);
3037	pVM->pgm.s.pfnR3ShwModifyPage = pModeData->pfnR3ShwModifyPage;
3038
3039	pVM->pgm.s.pfnRCShwGetPage = pModeData->pfnRCShwGetPage;
3040	pVM->pgm.s.pfnRCShwModifyPage = pModeData->pfnRCShwModifyPage;
3041
3042	pVM->pgm.s.pfnR0ShwGetPage = pModeData->pfnR0ShwGetPage;
3043	pVM->pgm.s.pfnR0ShwModifyPage = pModeData->pfnR0ShwModifyPage;
3044
3045
3046	/* guest */
3047	pVM->pgm.s.pfnR3GstRelocate = pModeData->pfnR3GstRelocate;
3048	pVM->pgm.s.pfnR3GstExit = pModeData->pfnR3GstExit;
3049	pVM->pgm.s.pfnR3GstGetPage = pModeData->pfnR3GstGetPage;
3050	Assert(pVM->pgm.s.pfnR3GstGetPage);
3051	pVM->pgm.s.pfnR3GstModifyPage = pModeData->pfnR3GstModifyPage;
3052	pVM->pgm.s.pfnR3GstGetPDE = pModeData->pfnR3GstGetPDE;
3053	#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
3054	pVM->pgm.s.pfnR3GstMonitorCR3 = pModeData->pfnR3GstMonitorCR3;
3055	pVM->pgm.s.pfnR3GstUnmonitorCR3 = pModeData->pfnR3GstUnmonitorCR3;
3056	#endif
3057	pVM->pgm.s.pfnR3GstMapCR3 = pModeData->pfnR3GstMapCR3;
3058	pVM->pgm.s.pfnR3GstUnmapCR3 = pModeData->pfnR3GstUnmapCR3;
3059	#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
3060	pVM->pgm.s.pfnR3GstWriteHandlerCR3 = pModeData->pfnR3GstWriteHandlerCR3;
3061	pVM->pgm.s.pszR3GstWriteHandlerCR3 = pModeData->pszR3GstWriteHandlerCR3;
3062	pVM->pgm.s.pfnR3GstPAEWriteHandlerCR3 = pModeData->pfnR3GstPAEWriteHandlerCR3;
3063	pVM->pgm.s.pszR3GstPAEWriteHandlerCR3 = pModeData->pszR3GstPAEWriteHandlerCR3;
3064	#endif
3065	pVM->pgm.s.pfnRCGstGetPage = pModeData->pfnRCGstGetPage;
3066	pVM->pgm.s.pfnRCGstModifyPage = pModeData->pfnRCGstModifyPage;
3067	pVM->pgm.s.pfnRCGstGetPDE = pModeData->pfnRCGstGetPDE;
3068	#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
3069	pVM->pgm.s.pfnRCGstMonitorCR3 = pModeData->pfnRCGstMonitorCR3;
3070	pVM->pgm.s.pfnRCGstUnmonitorCR3 = pModeData->pfnRCGstUnmonitorCR3;
3071	#endif
3072	pVM->pgm.s.pfnRCGstMapCR3 = pModeData->pfnRCGstMapCR3;
3073	pVM->pgm.s.pfnRCGstUnmapCR3 = pModeData->pfnRCGstUnmapCR3;
3074	#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
3075	pVM->pgm.s.pfnRCGstWriteHandlerCR3 = pModeData->pfnRCGstWriteHandlerCR3;
3076	pVM->pgm.s.pfnRCGstPAEWriteHandlerCR3 = pModeData->pfnRCGstPAEWriteHandlerCR3;
3077	#endif
3078	pVM->pgm.s.pfnR0GstGetPage = pModeData->pfnR0GstGetPage;
3079	pVM->pgm.s.pfnR0GstModifyPage = pModeData->pfnR0GstModifyPage;
3080	pVM->pgm.s.pfnR0GstGetPDE = pModeData->pfnR0GstGetPDE;
3081	#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
3082	pVM->pgm.s.pfnR0GstMonitorCR3 = pModeData->pfnR0GstMonitorCR3;
3083	pVM->pgm.s.pfnR0GstUnmonitorCR3 = pModeData->pfnR0GstUnmonitorCR3;
3084	#endif
3085	pVM->pgm.s.pfnR0GstMapCR3 = pModeData->pfnR0GstMapCR3;
3086	pVM->pgm.s.pfnR0GstUnmapCR3 = pModeData->pfnR0GstUnmapCR3;
3087	#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
3088	pVM->pgm.s.pfnR0GstWriteHandlerCR3 = pModeData->pfnR0GstWriteHandlerCR3;
3089	pVM->pgm.s.pfnR0GstPAEWriteHandlerCR3 = pModeData->pfnR0GstPAEWriteHandlerCR3;
3090	#endif
3091
3092	/* both */
3093	pVM->pgm.s.pfnR3BthRelocate = pModeData->pfnR3BthRelocate;
3094	pVM->pgm.s.pfnR3BthInvalidatePage = pModeData->pfnR3BthInvalidatePage;
3095	pVM->pgm.s.pfnR3BthSyncCR3 = pModeData->pfnR3BthSyncCR3;
3096	Assert(pVM->pgm.s.pfnR3BthSyncCR3);
3097	pVM->pgm.s.pfnR3BthSyncPage = pModeData->pfnR3BthSyncPage;
3098	pVM->pgm.s.pfnR3BthPrefetchPage = pModeData->pfnR3BthPrefetchPage;
3099	pVM->pgm.s.pfnR3BthVerifyAccessSyncPage = pModeData->pfnR3BthVerifyAccessSyncPage;
3100	#ifdef VBOX_STRICT
3101	pVM->pgm.s.pfnR3BthAssertCR3 = pModeData->pfnR3BthAssertCR3;
3102	#endif
3103
3104	pVM->pgm.s.pfnRCBthTrap0eHandler = pModeData->pfnRCBthTrap0eHandler;
3105	pVM->pgm.s.pfnRCBthInvalidatePage = pModeData->pfnRCBthInvalidatePage;
3106	pVM->pgm.s.pfnRCBthSyncCR3 = pModeData->pfnRCBthSyncCR3;
3107	pVM->pgm.s.pfnRCBthSyncPage = pModeData->pfnRCBthSyncPage;
3108	pVM->pgm.s.pfnRCBthPrefetchPage = pModeData->pfnRCBthPrefetchPage;
3109	pVM->pgm.s.pfnRCBthVerifyAccessSyncPage = pModeData->pfnRCBthVerifyAccessSyncPage;
3110	#ifdef VBOX_STRICT
3111	pVM->pgm.s.pfnRCBthAssertCR3 = pModeData->pfnRCBthAssertCR3;
3112	#endif
3113
3114	pVM->pgm.s.pfnR0BthTrap0eHandler = pModeData->pfnR0BthTrap0eHandler;
3115	pVM->pgm.s.pfnR0BthInvalidatePage = pModeData->pfnR0BthInvalidatePage;
3116	pVM->pgm.s.pfnR0BthSyncCR3 = pModeData->pfnR0BthSyncCR3;
3117	pVM->pgm.s.pfnR0BthSyncPage = pModeData->pfnR0BthSyncPage;
3118	pVM->pgm.s.pfnR0BthPrefetchPage = pModeData->pfnR0BthPrefetchPage;
3119	pVM->pgm.s.pfnR0BthVerifyAccessSyncPage = pModeData->pfnR0BthVerifyAccessSyncPage;
3120	#ifdef VBOX_STRICT
3121	pVM->pgm.s.pfnR0BthAssertCR3 = pModeData->pfnR0BthAssertCR3;
3122	#endif
3123	}
3124
3125
3126	/**
3127	* Calculates the shadow paging mode.
3128	*
3129	* @returns The shadow paging mode.
3130	* @param pVM VM handle.
3131	* @param enmGuestMode The guest mode.
3132	* @param enmHostMode The host mode.
3133	* @param enmShadowMode The current shadow mode.
3134	* @param penmSwitcher Where to store the switcher to use.
3135	* VMMSWITCHER_INVALID means no change.
3136	*/
3137	static PGMMODE pgmR3CalcShadowMode(PVM pVM, PGMMODE enmGuestMode, SUPPAGINGMODE enmHostMode, PGMMODE enmShadowMode, VMMSWITCHER *penmSwitcher)
3138	{
3139	VMMSWITCHER enmSwitcher = VMMSWITCHER_INVALID;
3140	switch (enmGuestMode)
3141	{
3142	/*
3143	* When switching to real or protected mode we don't change
3144	* anything since it's likely that we'll switch back pretty soon.
3145	*
3146	* During pgmR3InitPaging we'll end up here with PGMMODE_INVALID
3147	* and is supposed to determine which shadow paging and switcher to
3148	* use during init.
3149	*/
3150	case PGMMODE_REAL:
3151	case PGMMODE_PROTECTED:
3152	if ( enmShadowMode != PGMMODE_INVALID
3153	&& !HWACCMIsEnabled(pVM) /* always switch in hwaccm mode! */)
3154	break; /* (no change) */
3155
3156	switch (enmHostMode)
3157	{
3158	case SUPPAGINGMODE_32_BIT:
3159	case SUPPAGINGMODE_32_BIT_GLOBAL:
3160	enmShadowMode = PGMMODE_32_BIT;
3161	enmSwitcher = VMMSWITCHER_32_TO_32;
3162	break;
3163
3164	case SUPPAGINGMODE_PAE:
3165	case SUPPAGINGMODE_PAE_NX:
3166	case SUPPAGINGMODE_PAE_GLOBAL:
3167	case SUPPAGINGMODE_PAE_GLOBAL_NX:
3168	enmShadowMode = PGMMODE_PAE;
3169	enmSwitcher = VMMSWITCHER_PAE_TO_PAE;
3170	#ifdef DEBUG_bird
3171	if (RTEnvExist("VBOX_32BIT"))
3172	{
3173	enmShadowMode = PGMMODE_32_BIT;
3174	enmSwitcher = VMMSWITCHER_PAE_TO_32;
3175	}
3176	#endif
3177	break;
3178
3179	case SUPPAGINGMODE_AMD64:
3180	case SUPPAGINGMODE_AMD64_GLOBAL:
3181	case SUPPAGINGMODE_AMD64_NX:
3182	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
3183	enmShadowMode = PGMMODE_PAE;
3184	enmSwitcher = VMMSWITCHER_AMD64_TO_PAE;
3185	#ifdef DEBUG_bird
3186	if (RTEnvExist("VBOX_32BIT"))
3187	{
3188	enmShadowMode = PGMMODE_32_BIT;
3189	enmSwitcher = VMMSWITCHER_AMD64_TO_32;
3190	}
3191	#endif
3192	break;
3193
3194	default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
3195	}
3196	break;
3197
3198	case PGMMODE_32_BIT:
3199	switch (enmHostMode)
3200	{
3201	case SUPPAGINGMODE_32_BIT:
3202	case SUPPAGINGMODE_32_BIT_GLOBAL:
3203	enmShadowMode = PGMMODE_32_BIT;
3204	enmSwitcher = VMMSWITCHER_32_TO_32;
3205	break;
3206
3207	case SUPPAGINGMODE_PAE:
3208	case SUPPAGINGMODE_PAE_NX:
3209	case SUPPAGINGMODE_PAE_GLOBAL:
3210	case SUPPAGINGMODE_PAE_GLOBAL_NX:
3211	enmShadowMode = PGMMODE_PAE;
3212	enmSwitcher = VMMSWITCHER_PAE_TO_PAE;
3213	#ifdef DEBUG_bird
3214	if (RTEnvExist("VBOX_32BIT"))
3215	{
3216	enmShadowMode = PGMMODE_32_BIT;
3217	enmSwitcher = VMMSWITCHER_PAE_TO_32;
3218	}
3219	#endif
3220	break;
3221
3222	case SUPPAGINGMODE_AMD64:
3223	case SUPPAGINGMODE_AMD64_GLOBAL:
3224	case SUPPAGINGMODE_AMD64_NX:
3225	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
3226	enmShadowMode = PGMMODE_PAE;
3227	enmSwitcher = VMMSWITCHER_AMD64_TO_PAE;
3228	#ifdef DEBUG_bird
3229	if (RTEnvExist("VBOX_32BIT"))
3230	{
3231	enmShadowMode = PGMMODE_32_BIT;
3232	enmSwitcher = VMMSWITCHER_AMD64_TO_32;
3233	}
3234	#endif
3235	break;
3236
3237	default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
3238	}
3239	break;
3240
3241	case PGMMODE_PAE:
3242	case PGMMODE_PAE_NX: /** @todo This might require more switchers and guest+both modes. */
3243	switch (enmHostMode)
3244	{
3245	case SUPPAGINGMODE_32_BIT:
3246	case SUPPAGINGMODE_32_BIT_GLOBAL:
3247	enmShadowMode = PGMMODE_PAE;
3248	enmSwitcher = VMMSWITCHER_32_TO_PAE;
3249	break;
3250
3251	case SUPPAGINGMODE_PAE:
3252	case SUPPAGINGMODE_PAE_NX:
3253	case SUPPAGINGMODE_PAE_GLOBAL:
3254	case SUPPAGINGMODE_PAE_GLOBAL_NX:
3255	enmShadowMode = PGMMODE_PAE;
3256	enmSwitcher = VMMSWITCHER_PAE_TO_PAE;
3257	break;
3258
3259	case SUPPAGINGMODE_AMD64:
3260	case SUPPAGINGMODE_AMD64_GLOBAL:
3261	case SUPPAGINGMODE_AMD64_NX:
3262	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
3263	enmShadowMode = PGMMODE_PAE;
3264	enmSwitcher = VMMSWITCHER_AMD64_TO_PAE;
3265	break;
3266
3267	default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
3268	}
3269	break;
3270
3271	case PGMMODE_AMD64:
3272	case PGMMODE_AMD64_NX:
3273	switch (enmHostMode)
3274	{
3275	case SUPPAGINGMODE_32_BIT:
3276	case SUPPAGINGMODE_32_BIT_GLOBAL:
3277	enmShadowMode = PGMMODE_AMD64;
3278	enmSwitcher = VMMSWITCHER_32_TO_AMD64;
3279	break;
3280
3281	case SUPPAGINGMODE_PAE:
3282	case SUPPAGINGMODE_PAE_NX:
3283	case SUPPAGINGMODE_PAE_GLOBAL:
3284	case SUPPAGINGMODE_PAE_GLOBAL_NX:
3285	enmShadowMode = PGMMODE_AMD64;
3286	enmSwitcher = VMMSWITCHER_PAE_TO_AMD64;
3287	break;
3288
3289	case SUPPAGINGMODE_AMD64:
3290	case SUPPAGINGMODE_AMD64_GLOBAL:
3291	case SUPPAGINGMODE_AMD64_NX:
3292	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
3293	enmShadowMode = PGMMODE_AMD64;
3294	enmSwitcher = VMMSWITCHER_AMD64_TO_AMD64;
3295	break;
3296
3297	default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
3298	}
3299	break;
3300
3301
3302	default:
3303	AssertReleaseMsgFailed(("enmGuestMode=%d\n", enmGuestMode));
3304	return PGMMODE_INVALID;
3305	}
3306	/* Override the shadow mode is nested paging is active. */
3307	if (HWACCMIsNestedPagingActive(pVM))
3308	enmShadowMode = HWACCMGetShwPagingMode(pVM);
3309
3310	*penmSwitcher = enmSwitcher;
3311	return enmShadowMode;
3312	}
3313
3314
3315	/**
3316	* Performs the actual mode change.
3317	* This is called by PGMChangeMode and pgmR3InitPaging().
3318	*
3319	* @returns VBox status code.
3320	* @param pVM VM handle.
3321	* @param enmGuestMode The new guest mode. This is assumed to be different from
3322	* the current mode.
3323	*/
3324	VMMR3DECL(int) PGMR3ChangeMode(PVM pVM, PGMMODE enmGuestMode)
3325	{
3326	Log(("PGMR3ChangeMode: Guest mode: %s -> %s\n", PGMGetModeName(pVM->pgm.s.enmGuestMode), PGMGetModeName(enmGuestMode)));
3327	STAM_REL_COUNTER_INC(&pVM->pgm.s.cGuestModeChanges);
3328
3329	/*
3330	* Calc the shadow mode and switcher.
3331	*/
3332	VMMSWITCHER enmSwitcher;
3333	PGMMODE enmShadowMode = pgmR3CalcShadowMode(pVM, enmGuestMode, pVM->pgm.s.enmHostMode, pVM->pgm.s.enmShadowMode, &enmSwitcher);
3334	if (enmSwitcher != VMMSWITCHER_INVALID)
3335	{
3336	/*
3337	* Select new switcher.
3338	*/
3339	int rc = VMMR3SelectSwitcher(pVM, enmSwitcher);
3340	if (RT_FAILURE(rc))
3341	{
3342	AssertReleaseMsgFailed(("VMMR3SelectSwitcher(%d) -> %Rrc\n", enmSwitcher, rc));
3343	return rc;
3344	}
3345	}
3346
3347	/*
3348	* Exit old mode(s).
3349	*/
3350	/* shadow */
3351	if (enmShadowMode != pVM->pgm.s.enmShadowMode)
3352	{
3353	LogFlow(("PGMR3ChangeMode: Shadow mode: %s -> %s\n", PGMGetModeName(pVM->pgm.s.enmShadowMode), PGMGetModeName(enmShadowMode)));
3354	if (PGM_SHW_PFN(Exit, pVM))
3355	{
3356	int rc = PGM_SHW_PFN(Exit, pVM)(pVM);
3357	if (RT_FAILURE(rc))
3358	{
3359	AssertMsgFailed(("Exit failed for shadow mode %d: %Rrc\n", pVM->pgm.s.enmShadowMode, rc));
3360	return rc;
3361	}
3362	}
3363
3364	}
3365	else
3366	LogFlow(("PGMR3ChangeMode: Shadow mode remains: %s\n", PGMGetModeName(pVM->pgm.s.enmShadowMode)));
3367
3368	/* guest */
3369	if (PGM_GST_PFN(Exit, pVM))
3370	{
3371	int rc = PGM_GST_PFN(Exit, pVM)(pVM);
3372	if (RT_FAILURE(rc))
3373	{
3374	AssertMsgFailed(("Exit failed for guest mode %d: %Rrc\n", pVM->pgm.s.enmGuestMode, rc));
3375	return rc;
3376	}
3377	}
3378
3379	/*
3380	* Load new paging mode data.
3381	*/
3382	pgmR3ModeDataSwitch(pVM, enmShadowMode, enmGuestMode);
3383
3384	/*
3385	* Enter new shadow mode (if changed).
3386	*/
3387	if (enmShadowMode != pVM->pgm.s.enmShadowMode)
3388	{
3389	int rc;
3390	pVM->pgm.s.enmShadowMode = enmShadowMode;
3391	switch (enmShadowMode)
3392	{
3393	case PGMMODE_32_BIT:
3394	rc = PGM_SHW_NAME_32BIT(Enter)(pVM);
3395	break;
3396	case PGMMODE_PAE:
3397	case PGMMODE_PAE_NX:
3398	rc = PGM_SHW_NAME_PAE(Enter)(pVM);
3399	break;
3400	case PGMMODE_AMD64:
3401	case PGMMODE_AMD64_NX:
3402	rc = PGM_SHW_NAME_AMD64(Enter)(pVM);
3403	break;
3404	case PGMMODE_NESTED:
3405	rc = PGM_SHW_NAME_NESTED(Enter)(pVM);
3406	break;
3407	case PGMMODE_EPT:
3408	rc = PGM_SHW_NAME_EPT(Enter)(pVM);
3409	break;
3410	case PGMMODE_REAL:
3411	case PGMMODE_PROTECTED:
3412	default:
3413	AssertReleaseMsgFailed(("enmShadowMode=%d\n", enmShadowMode));
3414	return VERR_INTERNAL_ERROR;
3415	}
3416	if (RT_FAILURE(rc))
3417	{
3418	AssertReleaseMsgFailed(("Entering enmShadowMode=%d failed: %Rrc\n", enmShadowMode, rc));
3419	pVM->pgm.s.enmShadowMode = PGMMODE_INVALID;
3420	return rc;
3421	}
3422	}
3423
3424	/** @todo This is a bug!
3425	*
3426	* We must flush the PGM pool cache if the guest mode changes; we don't always
3427	* switch shadow paging mode (e.g. protected->32-bit) and shouldn't reuse
3428	* the shadow page tables.
3429	*
3430	* That only applies when switching between paging and non-paging modes.
3431	*/
3432	/** @todo A20 setting */
3433	if ( pVM->pgm.s.CTX_SUFF(pPool)
3434	&& !HWACCMIsNestedPagingActive(pVM)
3435	&& PGMMODE_WITH_PAGING(pVM->pgm.s.enmGuestMode) != PGMMODE_WITH_PAGING(enmGuestMode))
3436	{
3437	Log(("PGMR3ChangeMode: changing guest paging mode -> flush pgm pool cache!\n"));
3438	pgmPoolFlushAll(pVM);
3439	}
3440
3441	/*
3442	* Enter the new guest and shadow+guest modes.
3443	*/
3444	int rc = -1;
3445	int rc2 = -1;
3446	RTGCPHYS GCPhysCR3 = NIL_RTGCPHYS;
3447	pVM->pgm.s.enmGuestMode = enmGuestMode;
3448	switch (enmGuestMode)
3449	{
3450	case PGMMODE_REAL:
3451	rc = PGM_GST_NAME_REAL(Enter)(pVM, NIL_RTGCPHYS);
3452	switch (pVM->pgm.s.enmShadowMode)
3453	{
3454	case PGMMODE_32_BIT:
3455	rc2 = PGM_BTH_NAME_32BIT_REAL(Enter)(pVM, NIL_RTGCPHYS);
3456	break;
3457	case PGMMODE_PAE:
3458	case PGMMODE_PAE_NX:
3459	rc2 = PGM_BTH_NAME_PAE_REAL(Enter)(pVM, NIL_RTGCPHYS);
3460	break;
3461	case PGMMODE_NESTED:
3462	rc2 = PGM_BTH_NAME_NESTED_REAL(Enter)(pVM, NIL_RTGCPHYS);
3463	break;
3464	case PGMMODE_EPT:
3465	rc2 = PGM_BTH_NAME_EPT_REAL(Enter)(pVM, NIL_RTGCPHYS);
3466	break;
3467	case PGMMODE_AMD64:
3468	case PGMMODE_AMD64_NX:
3469	AssertMsgFailed(("Should use PAE shadow mode!\n"));
3470	default: AssertFailed(); break;
3471	}
3472	break;
3473
3474	case PGMMODE_PROTECTED:
3475	rc = PGM_GST_NAME_PROT(Enter)(pVM, NIL_RTGCPHYS);
3476	switch (pVM->pgm.s.enmShadowMode)
3477	{
3478	case PGMMODE_32_BIT:
3479	rc2 = PGM_BTH_NAME_32BIT_PROT(Enter)(pVM, NIL_RTGCPHYS);
3480	break;
3481	case PGMMODE_PAE:
3482	case PGMMODE_PAE_NX:
3483	rc2 = PGM_BTH_NAME_PAE_PROT(Enter)(pVM, NIL_RTGCPHYS);
3484	break;
3485	case PGMMODE_NESTED:
3486	rc2 = PGM_BTH_NAME_NESTED_PROT(Enter)(pVM, NIL_RTGCPHYS);
3487	break;
3488	case PGMMODE_EPT:
3489	rc2 = PGM_BTH_NAME_EPT_PROT(Enter)(pVM, NIL_RTGCPHYS);
3490	break;
3491	case PGMMODE_AMD64:
3492	case PGMMODE_AMD64_NX:
3493	AssertMsgFailed(("Should use PAE shadow mode!\n"));
3494	default: AssertFailed(); break;
3495	}
3496	break;
3497
3498	case PGMMODE_32_BIT:
3499	GCPhysCR3 = CPUMGetGuestCR3(pVM) & X86_CR3_PAGE_MASK;
3500	rc = PGM_GST_NAME_32BIT(Enter)(pVM, GCPhysCR3);
3501	switch (pVM->pgm.s.enmShadowMode)
3502	{
3503	case PGMMODE_32_BIT:
3504	rc2 = PGM_BTH_NAME_32BIT_32BIT(Enter)(pVM, GCPhysCR3);
3505	break;
3506	case PGMMODE_PAE:
3507	case PGMMODE_PAE_NX:
3508	rc2 = PGM_BTH_NAME_PAE_32BIT(Enter)(pVM, GCPhysCR3);
3509	break;
3510	case PGMMODE_NESTED:
3511	rc2 = PGM_BTH_NAME_NESTED_32BIT(Enter)(pVM, GCPhysCR3);
3512	break;
3513	case PGMMODE_EPT:
3514	rc2 = PGM_BTH_NAME_EPT_32BIT(Enter)(pVM, GCPhysCR3);
3515	break;
3516	case PGMMODE_AMD64:
3517	case PGMMODE_AMD64_NX:
3518	AssertMsgFailed(("Should use PAE shadow mode!\n"));
3519	default: AssertFailed(); break;
3520	}
3521	break;
3522
3523	case PGMMODE_PAE_NX:
3524	case PGMMODE_PAE:
3525	{
3526	uint32_t u32Dummy, u32Features;
3527
3528	CPUMGetGuestCpuId(pVM, 1, &u32Dummy, &u32Dummy, &u32Dummy, &u32Features);
3529	if (!(u32Features & X86_CPUID_FEATURE_EDX_PAE))
3530	{
3531	/* Pause first, then inform Main. */
3532	rc = VMR3SuspendNoSave(pVM);
3533	AssertRC(rc);
3534
3535	VMSetRuntimeError(pVM, true, "PAEmode",
3536	N_("The guest is trying to switch to the PAE mode which is currently disabled by default in VirtualBox. PAE support can be enabled using the VM settings (General/Advanced)"));
3537	/* we must return VINF_SUCCESS here otherwise the recompiler will assert */
3538	return VINF_SUCCESS;
3539	}
3540	GCPhysCR3 = CPUMGetGuestCR3(pVM) & X86_CR3_PAE_PAGE_MASK;
3541	rc = PGM_GST_NAME_PAE(Enter)(pVM, GCPhysCR3);
3542	switch (pVM->pgm.s.enmShadowMode)
3543	{
3544	case PGMMODE_PAE:
3545	case PGMMODE_PAE_NX:
3546	rc2 = PGM_BTH_NAME_PAE_PAE(Enter)(pVM, GCPhysCR3);
3547	break;
3548	case PGMMODE_NESTED:
3549	rc2 = PGM_BTH_NAME_NESTED_PAE(Enter)(pVM, GCPhysCR3);
3550	break;
3551	case PGMMODE_EPT:
3552	rc2 = PGM_BTH_NAME_EPT_PAE(Enter)(pVM, GCPhysCR3);
3553	break;
3554	case PGMMODE_32_BIT:
3555	case PGMMODE_AMD64:
3556	case PGMMODE_AMD64_NX:
3557	AssertMsgFailed(("Should use PAE shadow mode!\n"));
3558	default: AssertFailed(); break;
3559	}
3560	break;
3561	}
3562
3563	#ifdef VBOX_WITH_64_BITS_GUESTS
3564	case PGMMODE_AMD64_NX:
3565	case PGMMODE_AMD64:
3566	GCPhysCR3 = CPUMGetGuestCR3(pVM) & UINT64_C(0xfffffffffffff000); /** @todo define this mask! */
3567	rc = PGM_GST_NAME_AMD64(Enter)(pVM, GCPhysCR3);
3568	switch (pVM->pgm.s.enmShadowMode)
3569	{
3570	case PGMMODE_AMD64:
3571	case PGMMODE_AMD64_NX:
3572	rc2 = PGM_BTH_NAME_AMD64_AMD64(Enter)(pVM, GCPhysCR3);
3573	break;
3574	case PGMMODE_NESTED:
3575	rc2 = PGM_BTH_NAME_NESTED_AMD64(Enter)(pVM, GCPhysCR3);
3576	break;
3577	case PGMMODE_EPT:
3578	rc2 = PGM_BTH_NAME_EPT_AMD64(Enter)(pVM, GCPhysCR3);
3579	break;
3580	case PGMMODE_32_BIT:
3581	case PGMMODE_PAE:
3582	case PGMMODE_PAE_NX:
3583	AssertMsgFailed(("Should use AMD64 shadow mode!\n"));
3584	default: AssertFailed(); break;
3585	}
3586	break;
3587	#endif
3588
3589	default:
3590	AssertReleaseMsgFailed(("enmGuestMode=%d\n", enmGuestMode));
3591	rc = VERR_NOT_IMPLEMENTED;
3592	break;
3593	}
3594
3595	/* status codes. */
3596	AssertRC(rc);
3597	AssertRC(rc2);
3598	if (RT_SUCCESS(rc))
3599	{
3600	rc = rc2;
3601	if (RT_SUCCESS(rc)) /* no informational status codes. */
3602	rc = VINF_SUCCESS;
3603	}
3604
3605	/*
3606	* Notify SELM so it can update the TSSes with correct CR3s.
3607	*/
3608	SELMR3PagingModeChanged(pVM);
3609
3610	/* Notify HWACCM as well. */
3611	HWACCMR3PagingModeChanged(pVM, pVM->pgm.s.enmShadowMode, pVM->pgm.s.enmGuestMode);
3612	return rc;
3613	}
3614
3615
3616	/**
3617	* Dumps a PAE shadow page table.
3618	*
3619	* @returns VBox status code (VINF_SUCCESS).
3620	* @param pVM The VM handle.
3621	* @param pPT Pointer to the page table.
3622	* @param u64Address The virtual address of the page table starts.
3623	* @param fLongMode Set if this a long mode table; clear if it's a legacy mode table.
3624	* @param cMaxDepth The maxium depth.
3625	* @param pHlp Pointer to the output functions.
3626	*/
3627	static int pgmR3DumpHierarchyHCPaePT(PVM pVM, PX86PTPAE pPT, uint64_t u64Address, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
3628	{
3629	for (unsigned i = 0; i < RT_ELEMENTS(pPT->a); i++)
3630	{
3631	X86PTEPAE Pte = pPT->a[i];
3632	if (Pte.n.u1Present)
3633	{
3634	pHlp->pfnPrintf(pHlp,
3635	fLongMode /P R S A D G WT CD AT NX 4M a p ? /
3636	? "%016llx 3 \| P %c %c %c %c %c %s %s %s %s 4K %c%c%c %016llx\n"
3637	: "%08llx 2 \| P %c %c %c %c %c %s %s %s %s 4K %c%c%c %016llx\n",
3638	u64Address + ((uint64_t)i << X86_PT_PAE_SHIFT),
3639	Pte.n.u1Write ? 'W' : 'R',
3640	Pte.n.u1User ? 'U' : 'S',
3641	Pte.n.u1Accessed ? 'A' : '-',
3642	Pte.n.u1Dirty ? 'D' : '-',
3643	Pte.n.u1Global ? 'G' : '-',
3644	Pte.n.u1WriteThru ? "WT" : "--",
3645	Pte.n.u1CacheDisable? "CD" : "--",
3646	Pte.n.u1PAT ? "AT" : "--",
3647	Pte.n.u1NoExecute ? "NX" : "--",
3648	Pte.u & PGM_PTFLAGS_TRACK_DIRTY ? 'd' : '-',
3649	Pte.u & RT_BIT(10) ? '1' : '0',
3650	Pte.u & PGM_PTFLAGS_CSAM_VALIDATED? 'v' : '-',
3651	Pte.u & X86_PTE_PAE_PG_MASK);
3652	}
3653	}
3654	return VINF_SUCCESS;
3655	}
3656
3657
3658	/**
3659	* Dumps a PAE shadow page directory table.
3660	*
3661	* @returns VBox status code (VINF_SUCCESS).
3662	* @param pVM The VM handle.
3663	* @param HCPhys The physical address of the page directory table.
3664	* @param u64Address The virtual address of the page table starts.
3665	* @param cr4 The CR4, PSE is currently used.
3666	* @param fLongMode Set if this a long mode table; clear if it's a legacy mode table.
3667	* @param cMaxDepth The maxium depth.
3668	* @param pHlp Pointer to the output functions.
3669	*/
3670	static int pgmR3DumpHierarchyHCPaePD(PVM pVM, RTHCPHYS HCPhys, uint64_t u64Address, uint32_t cr4, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
3671	{
3672	PX86PDPAE pPD = (PX86PDPAE)MMPagePhys2Page(pVM, HCPhys);
3673	if (!pPD)
3674	{
3675	pHlp->pfnPrintf(pHlp, "%0*llx error! Page directory at HCPhys=%RHp was not found in the page pool!\n",
3676	fLongMode ? 16 : 8, u64Address, HCPhys);
3677	return VERR_INVALID_PARAMETER;
3678	}
3679	const bool fBigPagesSupported = fLongMode \|\| !!(cr4 & X86_CR4_PSE);
3680
3681	int rc = VINF_SUCCESS;
3682	for (unsigned i = 0; i < RT_ELEMENTS(pPD->a); i++)
3683	{
3684	X86PDEPAE Pde = pPD->a[i];
3685	if (Pde.n.u1Present)
3686	{
3687	if (fBigPagesSupported && Pde.b.u1Size)
3688	pHlp->pfnPrintf(pHlp,
3689	fLongMode /P R S A D G WT CD AT NX 4M a p ? /
3690	? "%016llx 2 \| P %c %c %c %c %c %s %s %s %s 4M %c%c%c %016llx\n"
3691	: "%08llx 1 \| P %c %c %c %c %c %s %s %s %s 4M %c%c%c %016llx\n",
3692	u64Address + ((uint64_t)i << X86_PD_PAE_SHIFT),
3693	Pde.b.u1Write ? 'W' : 'R',
3694	Pde.b.u1User ? 'U' : 'S',
3695	Pde.b.u1Accessed ? 'A' : '-',
3696	Pde.b.u1Dirty ? 'D' : '-',
3697	Pde.b.u1Global ? 'G' : '-',
3698	Pde.b.u1WriteThru ? "WT" : "--",
3699	Pde.b.u1CacheDisable? "CD" : "--",
3700	Pde.b.u1PAT ? "AT" : "--",
3701	Pde.b.u1NoExecute ? "NX" : "--",
3702	Pde.u & RT_BIT_64(9) ? '1' : '0',
3703	Pde.u & PGM_PDFLAGS_MAPPING ? 'm' : '-',
3704	Pde.u & PGM_PDFLAGS_TRACK_DIRTY ? 'd' : '-',
3705	Pde.u & X86_PDE_PAE_PG_MASK);
3706	else
3707	{
3708	pHlp->pfnPrintf(pHlp,
3709	fLongMode /P R S A D G WT CD AT NX 4M a p ? /
3710	? "%016llx 2 \| P %c %c %c %c %c %s %s .. %s 4K %c%c%c %016llx\n"
3711	: "%08llx 1 \| P %c %c %c %c %c %s %s .. %s 4K %c%c%c %016llx\n",
3712	u64Address + ((uint64_t)i << X86_PD_PAE_SHIFT),
3713	Pde.n.u1Write ? 'W' : 'R',
3714	Pde.n.u1User ? 'U' : 'S',
3715	Pde.n.u1Accessed ? 'A' : '-',
3716	Pde.n.u1Reserved0 ? '?' : '.', /* ignored */
3717	Pde.n.u1Reserved1 ? '?' : '.', /* ignored */
3718	Pde.n.u1WriteThru ? "WT" : "--",
3719	Pde.n.u1CacheDisable? "CD" : "--",
3720	Pde.n.u1NoExecute ? "NX" : "--",
3721	Pde.u & RT_BIT_64(9) ? '1' : '0',
3722	Pde.u & PGM_PDFLAGS_MAPPING ? 'm' : '-',
3723	Pde.u & PGM_PDFLAGS_TRACK_DIRTY ? 'd' : '-',
3724	Pde.u & X86_PDE_PAE_PG_MASK);
3725	if (cMaxDepth >= 1)
3726	{
3727	/** @todo what about using the page pool for mapping PTs? */
3728	uint64_t u64AddressPT = u64Address + ((uint64_t)i << X86_PD_PAE_SHIFT);
3729	RTHCPHYS HCPhysPT = Pde.u & X86_PDE_PAE_PG_MASK;
3730	PX86PTPAE pPT = NULL;
3731	if (!(Pde.u & PGM_PDFLAGS_MAPPING))
3732	pPT = (PX86PTPAE)MMPagePhys2Page(pVM, HCPhysPT);
3733	else
3734	{
3735	for (PPGMMAPPING pMap = pVM->pgm.s.pMappingsR3; pMap; pMap = pMap->pNextR3)
3736	{
3737	uint64_t off = u64AddressPT - pMap->GCPtr;
3738	if (off < pMap->cb)
3739	{
3740	const int iPDE = (uint32_t)(off >> X86_PD_SHIFT);
3741	const int iSub = (int)((off >> X86_PD_PAE_SHIFT) & 1); /* MSC is a pain sometimes */
3742	if ((iSub ? pMap->aPTs[iPDE].HCPhysPaePT1 : pMap->aPTs[iPDE].HCPhysPaePT0) != HCPhysPT)
3743	pHlp->pfnPrintf(pHlp, "%0*llx error! Mapping error! PT %d has HCPhysPT=%RHp not %RHp is in the PD.\n",
3744	fLongMode ? 16 : 8, u64AddressPT, iPDE,
3745	iSub ? pMap->aPTs[iPDE].HCPhysPaePT1 : pMap->aPTs[iPDE].HCPhysPaePT0, HCPhysPT);
3746	pPT = &pMap->aPTs[iPDE].paPaePTsR3[iSub];
3747	}
3748	}
3749	}
3750	int rc2 = VERR_INVALID_PARAMETER;
3751	if (pPT)
3752	rc2 = pgmR3DumpHierarchyHCPaePT(pVM, pPT, u64AddressPT, fLongMode, cMaxDepth - 1, pHlp);
3753	else
3754	pHlp->pfnPrintf(pHlp, "%0*llx error! Page table at HCPhys=%RHp was not found in the page pool!\n",
3755	fLongMode ? 16 : 8, u64AddressPT, HCPhysPT);
3756	if (rc2 < rc && RT_SUCCESS(rc))
3757	rc = rc2;
3758	}
3759	}
3760	}
3761	}
3762	return rc;
3763	}
3764
3765
3766	/**
3767	* Dumps a PAE shadow page directory pointer table.
3768	*
3769	* @returns VBox status code (VINF_SUCCESS).
3770	* @param pVM The VM handle.
3771	* @param HCPhys The physical address of the page directory pointer table.
3772	* @param u64Address The virtual address of the page table starts.
3773	* @param cr4 The CR4, PSE is currently used.
3774	* @param fLongMode Set if this a long mode table; clear if it's a legacy mode table.
3775	* @param cMaxDepth The maxium depth.
3776	* @param pHlp Pointer to the output functions.
3777	*/
3778	static int pgmR3DumpHierarchyHCPaePDPT(PVM pVM, RTHCPHYS HCPhys, uint64_t u64Address, uint32_t cr4, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
3779	{
3780	PX86PDPT pPDPT = (PX86PDPT)MMPagePhys2Page(pVM, HCPhys);
3781	if (!pPDPT)
3782	{
3783	pHlp->pfnPrintf(pHlp, "%0*llx error! Page directory pointer table at HCPhys=%RHp was not found in the page pool!\n",
3784	fLongMode ? 16 : 8, u64Address, HCPhys);
3785	return VERR_INVALID_PARAMETER;
3786	}
3787
3788	int rc = VINF_SUCCESS;
3789	const unsigned c = fLongMode ? RT_ELEMENTS(pPDPT->a) : X86_PG_PAE_PDPE_ENTRIES;
3790	for (unsigned i = 0; i < c; i++)
3791	{
3792	X86PDPE Pdpe = pPDPT->a[i];
3793	if (Pdpe.n.u1Present)
3794	{
3795	if (fLongMode)
3796	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a p ? /
3797	"%016llx 1 \| P %c %c %c %c %c %s %s %s %s .. %c%c%c %016llx\n",
3798	u64Address + ((uint64_t)i << X86_PDPT_SHIFT),
3799	Pdpe.lm.u1Write ? 'W' : 'R',
3800	Pdpe.lm.u1User ? 'U' : 'S',
3801	Pdpe.lm.u1Accessed ? 'A' : '-',
3802	Pdpe.lm.u3Reserved & 1? '?' : '.', /* ignored */
3803	Pdpe.lm.u3Reserved & 4? '!' : '.', /* mbz */
3804	Pdpe.lm.u1WriteThru ? "WT" : "--",
3805	Pdpe.lm.u1CacheDisable? "CD" : "--",
3806	Pdpe.lm.u3Reserved & 2? "!" : "..",/* mbz */
3807	Pdpe.lm.u1NoExecute ? "NX" : "--",
3808	Pdpe.u & RT_BIT(9) ? '1' : '0',
3809	Pdpe.u & PGM_PLXFLAGS_PERMANENT ? 'p' : '-',
3810	Pdpe.u & RT_BIT(11) ? '1' : '0',
3811	Pdpe.u & X86_PDPE_PG_MASK);
3812	else
3813	pHlp->pfnPrintf(pHlp, /P G WT CD AT NX 4M a p ? /
3814	"%08x 0 \| P %c %s %s %s %s .. %c%c%c %016llx\n",
3815	i << X86_PDPT_SHIFT,
3816	Pdpe.n.u4Reserved & 1? '!' : '.', /* mbz */
3817	Pdpe.n.u4Reserved & 4? '!' : '.', /* mbz */
3818	Pdpe.n.u1WriteThru ? "WT" : "--",
3819	Pdpe.n.u1CacheDisable? "CD" : "--",
3820	Pdpe.n.u4Reserved & 2? "!" : "..",/* mbz */
3821	Pdpe.u & RT_BIT(9) ? '1' : '0',
3822	Pdpe.u & PGM_PLXFLAGS_PERMANENT ? 'p' : '-',
3823	Pdpe.u & RT_BIT(11) ? '1' : '0',
3824	Pdpe.u & X86_PDPE_PG_MASK);
3825	if (cMaxDepth >= 1)
3826	{
3827	int rc2 = pgmR3DumpHierarchyHCPaePD(pVM, Pdpe.u & X86_PDPE_PG_MASK, u64Address + ((uint64_t)i << X86_PDPT_SHIFT),
3828	cr4, fLongMode, cMaxDepth - 1, pHlp);
3829	if (rc2 < rc && RT_SUCCESS(rc))
3830	rc = rc2;
3831	}
3832	}
3833	}
3834	return rc;
3835	}
3836
3837
3838	/**
3839	* Dumps a 32-bit shadow page table.
3840	*
3841	* @returns VBox status code (VINF_SUCCESS).
3842	* @param pVM The VM handle.
3843	* @param HCPhys The physical address of the table.
3844	* @param cr4 The CR4, PSE is currently used.
3845	* @param cMaxDepth The maxium depth.
3846	* @param pHlp Pointer to the output functions.
3847	*/
3848	static int pgmR3DumpHierarchyHcPaePML4(PVM pVM, RTHCPHYS HCPhys, uint32_t cr4, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
3849	{
3850	PX86PML4 pPML4 = (PX86PML4)MMPagePhys2Page(pVM, HCPhys);
3851	if (!pPML4)
3852	{
3853	pHlp->pfnPrintf(pHlp, "Page map level 4 at HCPhys=%RHp was not found in the page pool!\n", HCPhys);
3854	return VERR_INVALID_PARAMETER;
3855	}
3856
3857	int rc = VINF_SUCCESS;
3858	for (unsigned i = 0; i < RT_ELEMENTS(pPML4->a); i++)
3859	{
3860	X86PML4E Pml4e = pPML4->a[i];
3861	if (Pml4e.n.u1Present)
3862	{
3863	uint64_t u64Address = ((uint64_t)i << X86_PML4_SHIFT) \| (((uint64_t)i >> (X86_PML4_SHIFT - X86_PDPT_SHIFT - 1)) * 0xffff000000000000ULL);
3864	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a p ? /
3865	"%016llx 0 \| P %c %c %c %c %c %s %s %s %s .. %c%c%c %016llx\n",
3866	u64Address,
3867	Pml4e.n.u1Write ? 'W' : 'R',
3868	Pml4e.n.u1User ? 'U' : 'S',
3869	Pml4e.n.u1Accessed ? 'A' : '-',
3870	Pml4e.n.u3Reserved & 1? '?' : '.', /* ignored */
3871	Pml4e.n.u3Reserved & 4? '!' : '.', /* mbz */
3872	Pml4e.n.u1WriteThru ? "WT" : "--",
3873	Pml4e.n.u1CacheDisable? "CD" : "--",
3874	Pml4e.n.u3Reserved & 2? "!" : "..",/* mbz */
3875	Pml4e.n.u1NoExecute ? "NX" : "--",
3876	Pml4e.u & RT_BIT(9) ? '1' : '0',
3877	Pml4e.u & PGM_PLXFLAGS_PERMANENT ? 'p' : '-',
3878	Pml4e.u & RT_BIT(11) ? '1' : '0',
3879	Pml4e.u & X86_PML4E_PG_MASK);
3880
3881	if (cMaxDepth >= 1)
3882	{
3883	int rc2 = pgmR3DumpHierarchyHCPaePDPT(pVM, Pml4e.u & X86_PML4E_PG_MASK, u64Address, cr4, true, cMaxDepth - 1, pHlp);
3884	if (rc2 < rc && RT_SUCCESS(rc))
3885	rc = rc2;
3886	}
3887	}
3888	}
3889	return rc;
3890	}
3891
3892
3893	/**
3894	* Dumps a 32-bit shadow page table.
3895	*
3896	* @returns VBox status code (VINF_SUCCESS).
3897	* @param pVM The VM handle.
3898	* @param pPT Pointer to the page table.
3899	* @param u32Address The virtual address this table starts at.
3900	* @param pHlp Pointer to the output functions.
3901	*/
3902	int pgmR3DumpHierarchyHC32BitPT(PVM pVM, PX86PT pPT, uint32_t u32Address, PCDBGFINFOHLP pHlp)
3903	{
3904	for (unsigned i = 0; i < RT_ELEMENTS(pPT->a); i++)
3905	{
3906	X86PTE Pte = pPT->a[i];
3907	if (Pte.n.u1Present)
3908	{
3909	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a m d /
3910	"%08x 1 \| P %c %c %c %c %c %s %s %s .. 4K %c%c%c %08x\n",
3911	u32Address + (i << X86_PT_SHIFT),
3912	Pte.n.u1Write ? 'W' : 'R',
3913	Pte.n.u1User ? 'U' : 'S',
3914	Pte.n.u1Accessed ? 'A' : '-',
3915	Pte.n.u1Dirty ? 'D' : '-',
3916	Pte.n.u1Global ? 'G' : '-',
3917	Pte.n.u1WriteThru ? "WT" : "--",
3918	Pte.n.u1CacheDisable? "CD" : "--",
3919	Pte.n.u1PAT ? "AT" : "--",
3920	Pte.u & PGM_PTFLAGS_TRACK_DIRTY ? 'd' : '-',
3921	Pte.u & RT_BIT(10) ? '1' : '0',
3922	Pte.u & PGM_PTFLAGS_CSAM_VALIDATED ? 'v' : '-',
3923	Pte.u & X86_PDE_PG_MASK);
3924	}
3925	}
3926	return VINF_SUCCESS;
3927	}
3928
3929
3930	/**
3931	* Dumps a 32-bit shadow page directory and page tables.
3932	*
3933	* @returns VBox status code (VINF_SUCCESS).
3934	* @param pVM The VM handle.
3935	* @param cr3 The root of the hierarchy.
3936	* @param cr4 The CR4, PSE is currently used.
3937	* @param cMaxDepth How deep into the hierarchy the dumper should go.
3938	* @param pHlp Pointer to the output functions.
3939	*/
3940	int pgmR3DumpHierarchyHC32BitPD(PVM pVM, uint32_t cr3, uint32_t cr4, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
3941	{
3942	PX86PD pPD = (PX86PD)MMPagePhys2Page(pVM, cr3 & X86_CR3_PAGE_MASK);
3943	if (!pPD)
3944	{
3945	pHlp->pfnPrintf(pHlp, "Page directory at %#x was not found in the page pool!\n", cr3 & X86_CR3_PAGE_MASK);
3946	return VERR_INVALID_PARAMETER;
3947	}
3948
3949	int rc = VINF_SUCCESS;
3950	for (unsigned i = 0; i < RT_ELEMENTS(pPD->a); i++)
3951	{
3952	X86PDE Pde = pPD->a[i];
3953	if (Pde.n.u1Present)
3954	{
3955	const uint32_t u32Address = i << X86_PD_SHIFT;
3956	if ((cr4 & X86_CR4_PSE) && Pde.b.u1Size)
3957	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a m d /
3958	"%08x 0 \| P %c %c %c %c %c %s %s %s .. 4M %c%c%c %08x\n",
3959	u32Address,
3960	Pde.b.u1Write ? 'W' : 'R',
3961	Pde.b.u1User ? 'U' : 'S',
3962	Pde.b.u1Accessed ? 'A' : '-',
3963	Pde.b.u1Dirty ? 'D' : '-',
3964	Pde.b.u1Global ? 'G' : '-',
3965	Pde.b.u1WriteThru ? "WT" : "--",
3966	Pde.b.u1CacheDisable? "CD" : "--",
3967	Pde.b.u1PAT ? "AT" : "--",
3968	Pde.u & RT_BIT_64(9) ? '1' : '0',
3969	Pde.u & PGM_PDFLAGS_MAPPING ? 'm' : '-',
3970	Pde.u & PGM_PDFLAGS_TRACK_DIRTY ? 'd' : '-',
3971	Pde.u & X86_PDE4M_PG_MASK);
3972	else
3973	{
3974	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a m d /
3975	"%08x 0 \| P %c %c %c %c %c %s %s .. .. 4K %c%c%c %08x\n",
3976	u32Address,
3977	Pde.n.u1Write ? 'W' : 'R',
3978	Pde.n.u1User ? 'U' : 'S',
3979	Pde.n.u1Accessed ? 'A' : '-',
3980	Pde.n.u1Reserved0 ? '?' : '.', /* ignored */
3981	Pde.n.u1Reserved1 ? '?' : '.', /* ignored */
3982	Pde.n.u1WriteThru ? "WT" : "--",
3983	Pde.n.u1CacheDisable? "CD" : "--",
3984	Pde.u & RT_BIT_64(9) ? '1' : '0',
3985	Pde.u & PGM_PDFLAGS_MAPPING ? 'm' : '-',
3986	Pde.u & PGM_PDFLAGS_TRACK_DIRTY ? 'd' : '-',
3987	Pde.u & X86_PDE_PG_MASK);
3988	if (cMaxDepth >= 1)
3989	{
3990	/** @todo what about using the page pool for mapping PTs? */
3991	RTHCPHYS HCPhys = Pde.u & X86_PDE_PG_MASK;
3992	PX86PT pPT = NULL;
3993	if (!(Pde.u & PGM_PDFLAGS_MAPPING))
3994	pPT = (PX86PT)MMPagePhys2Page(pVM, HCPhys);
3995	else
3996	{
3997	for (PPGMMAPPING pMap = pVM->pgm.s.pMappingsR3; pMap; pMap = pMap->pNextR3)
3998	if (u32Address - pMap->GCPtr < pMap->cb)
3999	{
4000	int iPDE = (u32Address - pMap->GCPtr) >> X86_PD_SHIFT;
4001	if (pMap->aPTs[iPDE].HCPhysPT != HCPhys)
4002	pHlp->pfnPrintf(pHlp, "%08x error! Mapping error! PT %d has HCPhysPT=%RHp not %RHp is in the PD.\n",
4003	u32Address, iPDE, pMap->aPTs[iPDE].HCPhysPT, HCPhys);
4004	pPT = pMap->aPTs[iPDE].pPTR3;
4005	}
4006	}
4007	int rc2 = VERR_INVALID_PARAMETER;
4008	if (pPT)
4009	rc2 = pgmR3DumpHierarchyHC32BitPT(pVM, pPT, u32Address, pHlp);
4010	else
4011	pHlp->pfnPrintf(pHlp, "%08x error! Page table at %#x was not found in the page pool!\n", u32Address, HCPhys);
4012	if (rc2 < rc && RT_SUCCESS(rc))
4013	rc = rc2;
4014	}
4015	}
4016	}
4017	}
4018
4019	return rc;
4020	}
4021
4022
4023	/**
4024	* Dumps a 32-bit shadow page table.
4025	*
4026	* @returns VBox status code (VINF_SUCCESS).
4027	* @param pVM The VM handle.
4028	* @param pPT Pointer to the page table.
4029	* @param u32Address The virtual address this table starts at.
4030	* @param PhysSearch Address to search for.
4031	*/
4032	int pgmR3DumpHierarchyGC32BitPT(PVM pVM, PX86PT pPT, uint32_t u32Address, RTGCPHYS PhysSearch)
4033	{
4034	for (unsigned i = 0; i < RT_ELEMENTS(pPT->a); i++)
4035	{
4036	X86PTE Pte = pPT->a[i];
4037	if (Pte.n.u1Present)
4038	{
4039	Log(( /P R S A D G WT CD AT NX 4M a m d /
4040	"%08x 1 \| P %c %c %c %c %c %s %s %s .. 4K %c%c%c %08x\n",
4041	u32Address + (i << X86_PT_SHIFT),
4042	Pte.n.u1Write ? 'W' : 'R',
4043	Pte.n.u1User ? 'U' : 'S',
4044	Pte.n.u1Accessed ? 'A' : '-',
4045	Pte.n.u1Dirty ? 'D' : '-',
4046	Pte.n.u1Global ? 'G' : '-',
4047	Pte.n.u1WriteThru ? "WT" : "--",
4048	Pte.n.u1CacheDisable? "CD" : "--",
4049	Pte.n.u1PAT ? "AT" : "--",
4050	Pte.u & PGM_PTFLAGS_TRACK_DIRTY ? 'd' : '-',
4051	Pte.u & RT_BIT(10) ? '1' : '0',
4052	Pte.u & PGM_PTFLAGS_CSAM_VALIDATED ? 'v' : '-',
4053	Pte.u & X86_PDE_PG_MASK));
4054
4055	if ((Pte.u & X86_PDE_PG_MASK) == PhysSearch)
4056	{
4057	uint64_t fPageShw = 0;
4058	RTHCPHYS pPhysHC = 0;
4059
4060	PGMShwGetPage(pVM, (RTGCPTR)(u32Address + (i << X86_PT_SHIFT)), &fPageShw, &pPhysHC);
4061	Log(("Found %RGp at %RGv -> flags=%llx\n", PhysSearch, (RTGCPTR)(u32Address + (i << X86_PT_SHIFT)), fPageShw));
4062	}
4063	}
4064	}
4065	return VINF_SUCCESS;
4066	}
4067
4068
4069	/**
4070	* Dumps a 32-bit guest page directory and page tables.
4071	*
4072	* @returns VBox status code (VINF_SUCCESS).
4073	* @param pVM The VM handle.
4074	* @param cr3 The root of the hierarchy.
4075	* @param cr4 The CR4, PSE is currently used.
4076	* @param PhysSearch Address to search for.
4077	*/
4078	VMMR3DECL(int) PGMR3DumpHierarchyGC(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCPHYS PhysSearch)
4079	{
4080	bool fLongMode = false;
4081	const unsigned cch = fLongMode ? 16 : 8; NOREF(cch);
4082	PX86PD pPD = 0;
4083
4084	int rc = PGM_GCPHYS_2_PTR(pVM, cr3 & X86_CR3_PAGE_MASK, &pPD);
4085	if (RT_FAILURE(rc) \|\| !pPD)
4086	{
4087	Log(("Page directory at %#x was not found in the page pool!\n", cr3 & X86_CR3_PAGE_MASK));
4088	return VERR_INVALID_PARAMETER;
4089	}
4090
4091	Log(("cr3=%08x cr4=%08x%s\n"
4092	"%-*s P - Present\n"
4093	"%-*s \| R/W - Read (0) / Write (1)\n"
4094	"%-*s \| \| U/S - User (1) / Supervisor (0)\n"
4095	"%-*s \| \| \| A - Accessed\n"
4096	"%-*s \| \| \| \| D - Dirty\n"
4097	"%-*s \| \| \| \| \| G - Global\n"
4098	"%-*s \| \| \| \| \| \| WT - Write thru\n"
4099	"%-*s \| \| \| \| \| \| \| CD - Cache disable\n"
4100	"%-*s \| \| \| \| \| \| \| \| AT - Attribute table (PAT)\n"
4101	"%-*s \| \| \| \| \| \| \| \| \| NX - No execute (K8)\n"
4102	"%-*s \| \| \| \| \| \| \| \| \| \| 4K/4M/2M - Page size.\n"
4103	"%-*s \| \| \| \| \| \| \| \| \| \| \| AVL - a=allocated; m=mapping; d=track dirty;\n"
4104	"%-*s \| \| \| \| \| \| \| \| \| \| \| \| p=permanent; v=validated;\n"
4105	"%-*s Level \| \| \| \| \| \| \| \| \| \| \| \| Page\n"
4106	/* xxxx n **** P R S A D G WT CD AT NX 4M AVL xxxxxxxxxxxxx
4107	- W U - - - -- -- -- -- -- 010 */
4108	, cr3, cr4, fLongMode ? " Long Mode" : "",
4109	cch, "", cch, "", cch, "", cch, "", cch, "", cch, "", cch, "",
4110	cch, "", cch, "", cch, "", cch, "", cch, "", cch, "", cch, "Address"));
4111
4112	for (unsigned i = 0; i < RT_ELEMENTS(pPD->a); i++)
4113	{
4114	X86PDE Pde = pPD->a[i];
4115	if (Pde.n.u1Present)
4116	{
4117	const uint32_t u32Address = i << X86_PD_SHIFT;
4118
4119	if ((cr4 & X86_CR4_PSE) && Pde.b.u1Size)
4120	Log(( /P R S A D G WT CD AT NX 4M a m d /
4121	"%08x 0 \| P %c %c %c %c %c %s %s %s .. 4M %c%c%c %08x\n",
4122	u32Address,
4123	Pde.b.u1Write ? 'W' : 'R',
4124	Pde.b.u1User ? 'U' : 'S',
4125	Pde.b.u1Accessed ? 'A' : '-',
4126	Pde.b.u1Dirty ? 'D' : '-',
4127	Pde.b.u1Global ? 'G' : '-',
4128	Pde.b.u1WriteThru ? "WT" : "--",
4129	Pde.b.u1CacheDisable? "CD" : "--",
4130	Pde.b.u1PAT ? "AT" : "--",
4131	Pde.u & RT_BIT(9) ? '1' : '0',
4132	Pde.u & RT_BIT(10) ? '1' : '0',
4133	Pde.u & RT_BIT(11) ? '1' : '0',
4134	pgmGstGet4MBPhysPage(&pVM->pgm.s, Pde)));
4135	/** @todo PhysSearch */
4136	else
4137	{
4138	Log(( /P R S A D G WT CD AT NX 4M a m d /
4139	"%08x 0 \| P %c %c %c %c %c %s %s .. .. 4K %c%c%c %08x\n",
4140	u32Address,
4141	Pde.n.u1Write ? 'W' : 'R',
4142	Pde.n.u1User ? 'U' : 'S',
4143	Pde.n.u1Accessed ? 'A' : '-',
4144	Pde.n.u1Reserved0 ? '?' : '.', /* ignored */
4145	Pde.n.u1Reserved1 ? '?' : '.', /* ignored */
4146	Pde.n.u1WriteThru ? "WT" : "--",
4147	Pde.n.u1CacheDisable? "CD" : "--",
4148	Pde.u & RT_BIT(9) ? '1' : '0',
4149	Pde.u & RT_BIT(10) ? '1' : '0',
4150	Pde.u & RT_BIT(11) ? '1' : '0',
4151	Pde.u & X86_PDE_PG_MASK));
4152	////if (cMaxDepth >= 1)
4153	{
4154	/** @todo what about using the page pool for mapping PTs? */
4155	RTGCPHYS GCPhys = Pde.u & X86_PDE_PG_MASK;
4156	PX86PT pPT = NULL;
4157
4158	rc = PGM_GCPHYS_2_PTR(pVM, GCPhys, &pPT);
4159
4160	int rc2 = VERR_INVALID_PARAMETER;
4161	if (pPT)
4162	rc2 = pgmR3DumpHierarchyGC32BitPT(pVM, pPT, u32Address, PhysSearch);
4163	else
4164	Log(("%08x error! Page table at %#x was not found in the page pool!\n", u32Address, GCPhys));
4165	if (rc2 < rc && RT_SUCCESS(rc))
4166	rc = rc2;
4167	}
4168	}
4169	}
4170	}
4171
4172	return rc;
4173	}
4174
4175
4176	/**
4177	* Dumps a page table hierarchy use only physical addresses and cr4/lm flags.
4178	*
4179	* @returns VBox status code (VINF_SUCCESS).
4180	* @param pVM The VM handle.
4181	* @param cr3 The root of the hierarchy.
4182	* @param cr4 The cr4, only PAE and PSE is currently used.
4183	* @param fLongMode Set if long mode, false if not long mode.
4184	* @param cMaxDepth Number of levels to dump.
4185	* @param pHlp Pointer to the output functions.
4186	*/
4187	VMMR3DECL(int) PGMR3DumpHierarchyHC(PVM pVM, uint64_t cr3, uint64_t cr4, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
4188	{
4189	if (!pHlp)
4190	pHlp = DBGFR3InfoLogHlp();
4191	if (!cMaxDepth)
4192	return VINF_SUCCESS;
4193	const unsigned cch = fLongMode ? 16 : 8;
4194	pHlp->pfnPrintf(pHlp,
4195	"cr3=%08x cr4=%08x%s\n"
4196	"%-*s P - Present\n"
4197	"%-*s \| R/W - Read (0) / Write (1)\n"
4198	"%-*s \| \| U/S - User (1) / Supervisor (0)\n"
4199	"%-*s \| \| \| A - Accessed\n"
4200	"%-*s \| \| \| \| D - Dirty\n"
4201	"%-*s \| \| \| \| \| G - Global\n"
4202	"%-*s \| \| \| \| \| \| WT - Write thru\n"
4203	"%-*s \| \| \| \| \| \| \| CD - Cache disable\n"
4204	"%-*s \| \| \| \| \| \| \| \| AT - Attribute table (PAT)\n"
4205	"%-*s \| \| \| \| \| \| \| \| \| NX - No execute (K8)\n"
4206	"%-*s \| \| \| \| \| \| \| \| \| \| 4K/4M/2M - Page size.\n"
4207	"%-*s \| \| \| \| \| \| \| \| \| \| \| AVL - a=allocated; m=mapping; d=track dirty;\n"
4208	"%-*s \| \| \| \| \| \| \| \| \| \| \| \| p=permanent; v=validated;\n"
4209	"%-*s Level \| \| \| \| \| \| \| \| \| \| \| \| Page\n"
4210	/* xxxx n **** P R S A D G WT CD AT NX 4M AVL xxxxxxxxxxxxx
4211	- W U - - - -- -- -- -- -- 010 */
4212	, cr3, cr4, fLongMode ? " Long Mode" : "",
4213	cch, "", cch, "", cch, "", cch, "", cch, "", cch, "", cch, "",
4214	cch, "", cch, "", cch, "", cch, "", cch, "", cch, "", cch, "Address");
4215	if (cr4 & X86_CR4_PAE)
4216	{
4217	if (fLongMode)
4218	return pgmR3DumpHierarchyHcPaePML4(pVM, cr3 & X86_CR3_PAGE_MASK, cr4, cMaxDepth, pHlp);
4219	return pgmR3DumpHierarchyHCPaePDPT(pVM, cr3 & X86_CR3_PAE_PAGE_MASK, 0, cr4, false, cMaxDepth, pHlp);
4220	}
4221	return pgmR3DumpHierarchyHC32BitPD(pVM, cr3 & X86_CR3_PAGE_MASK, cr4, cMaxDepth, pHlp);
4222	}
4223
4224	#ifdef VBOX_WITH_DEBUGGER
4225
4226	/**
4227	* The '.pgmram' command.
4228	*
4229	* @returns VBox status.
4230	* @param pCmd Pointer to the command descriptor (as registered).
4231	* @param pCmdHlp Pointer to command helper functions.
4232	* @param pVM Pointer to the current VM (if any).
4233	* @param paArgs Pointer to (readonly) array of arguments.
4234	* @param cArgs Number of arguments in the array.
4235	*/
4236	static DECLCALLBACK(int) pgmR3CmdRam(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4237	{
4238	/*
4239	* Validate input.
4240	*/
4241	if (!pVM)
4242	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4243	if (!pVM->pgm.s.pRamRangesRC)
4244	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Sorry, no Ram is registered.\n");
4245
4246	/*
4247	* Dump the ranges.
4248	*/
4249	int rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL, "From - To (incl) pvHC\n");
4250	PPGMRAMRANGE pRam;
4251	for (pRam = pVM->pgm.s.pRamRangesR3; pRam; pRam = pRam->pNextR3)
4252	{
4253	rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL,
4254	"%RGp - %RGp %p\n",
4255	pRam->GCPhys, pRam->GCPhysLast, pRam->pvR3);
4256	if (RT_FAILURE(rc))
4257	return rc;
4258	}
4259
4260	return VINF_SUCCESS;
4261	}
4262
4263
4264	/**
4265	* The '.pgmmap' command.
4266	*
4267	* @returns VBox status.
4268	* @param pCmd Pointer to the command descriptor (as registered).
4269	* @param pCmdHlp Pointer to command helper functions.
4270	* @param pVM Pointer to the current VM (if any).
4271	* @param paArgs Pointer to (readonly) array of arguments.
4272	* @param cArgs Number of arguments in the array.
4273	*/
4274	static DECLCALLBACK(int) pgmR3CmdMap(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4275	{
4276	/*
4277	* Validate input.
4278	*/
4279	if (!pVM)
4280	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4281	if (!pVM->pgm.s.pMappingsR3)
4282	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Sorry, no mappings are registered.\n");
4283
4284	/*
4285	* Print message about the fixedness of the mappings.
4286	*/
4287	int rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL, pVM->pgm.s.fMappingsFixed ? "The mappings are FIXED.\n" : "The mappings are FLOATING.\n");
4288	if (RT_FAILURE(rc))
4289	return rc;
4290
4291	/*
4292	* Dump the ranges.
4293	*/
4294	PPGMMAPPING pCur;
4295	for (pCur = pVM->pgm.s.pMappingsR3; pCur; pCur = pCur->pNextR3)
4296	{
4297	rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL,
4298	"%08x - %08x %s\n",
4299	pCur->GCPtr, pCur->GCPtrLast, pCur->pszDesc);
4300	if (RT_FAILURE(rc))
4301	return rc;
4302	}
4303
4304	return VINF_SUCCESS;
4305	}
4306
4307
4308	/**
4309	* The '.pgmsync' command.
4310	*
4311	* @returns VBox status.
4312	* @param pCmd Pointer to the command descriptor (as registered).
4313	* @param pCmdHlp Pointer to command helper functions.
4314	* @param pVM Pointer to the current VM (if any).
4315	* @param paArgs Pointer to (readonly) array of arguments.
4316	* @param cArgs Number of arguments in the array.
4317	*/
4318	static DECLCALLBACK(int) pgmR3CmdSync(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4319	{
4320	/*
4321	* Validate input.
4322	*/
4323	if (!pVM)
4324	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4325
4326	/*
4327	* Force page directory sync.
4328	*/
4329	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
4330
4331	int rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Forcing page directory sync.\n");
4332	if (RT_FAILURE(rc))
4333	return rc;
4334
4335	return VINF_SUCCESS;
4336	}
4337
4338
4339	#ifdef VBOX_STRICT
4340	/**
4341	* The '.pgmassertcr3' command.
4342	*
4343	* @returns VBox status.
4344	* @param pCmd Pointer to the command descriptor (as registered).
4345	* @param pCmdHlp Pointer to command helper functions.
4346	* @param pVM Pointer to the current VM (if any).
4347	* @param paArgs Pointer to (readonly) array of arguments.
4348	* @param cArgs Number of arguments in the array.
4349	*/
4350	static DECLCALLBACK(int) pgmR3CmdAssertCR3(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4351	{
4352	/*
4353	* Validate input.
4354	*/
4355	if (!pVM)
4356	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4357
4358	int rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Checking shadow CR3 page tables for consistency.\n");
4359	if (RT_FAILURE(rc))
4360	return rc;
4361
4362	PGMAssertCR3(pVM, CPUMGetGuestCR3(pVM), CPUMGetGuestCR4(pVM));
4363
4364	return VINF_SUCCESS;
4365	}
4366	#endif /* VBOX_STRICT */
4367
4368
4369	/**
4370	* The '.pgmsyncalways' command.
4371	*
4372	* @returns VBox status.
4373	* @param pCmd Pointer to the command descriptor (as registered).
4374	* @param pCmdHlp Pointer to command helper functions.
4375	* @param pVM Pointer to the current VM (if any).
4376	* @param paArgs Pointer to (readonly) array of arguments.
4377	* @param cArgs Number of arguments in the array.
4378	*/
4379	static DECLCALLBACK(int) pgmR3CmdSyncAlways(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4380	{
4381	/*
4382	* Validate input.
4383	*/
4384	if (!pVM)
4385	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4386
4387	/*
4388	* Force page directory sync.
4389	*/
4390	if (pVM->pgm.s.fSyncFlags & PGM_SYNC_ALWAYS)
4391	{
4392	ASMAtomicAndU32(&pVM->pgm.s.fSyncFlags, ~PGM_SYNC_ALWAYS);
4393	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Disabled permanent forced page directory syncing.\n");
4394	}
4395	else
4396	{
4397	ASMAtomicOrU32(&pVM->pgm.s.fSyncFlags, PGM_SYNC_ALWAYS);
4398	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
4399	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Enabled permanent forced page directory syncing.\n");
4400	}
4401	}
4402
4403	#endif /* VBOX_WITH_DEBUGGER */
4404
4405	/**
4406	* pvUser argument of the pgmR3CheckIntegrity*Node callbacks.
4407	*/
4408	typedef struct PGMCHECKINTARGS
4409	{
4410	bool fLeftToRight; /*< true: left-to-right; false: right-to-left. /
4411	PPGMPHYSHANDLER pPrevPhys;
4412	PPGMVIRTHANDLER pPrevVirt;
4413	PPGMPHYS2VIRTHANDLER pPrevPhys2Virt;
4414	PVM pVM;
4415	} PGMCHECKINTARGS, *PPGMCHECKINTARGS;
4416
4417	/**
4418	* Validate a node in the physical handler tree.
4419	*
4420	* @returns 0 on if ok, other wise 1.
4421	* @param pNode The handler node.
4422	* @param pvUser pVM.
4423	*/
4424	static DECLCALLBACK(int) pgmR3CheckIntegrityPhysHandlerNode(PAVLROGCPHYSNODECORE pNode, void *pvUser)
4425	{
4426	PPGMCHECKINTARGS pArgs = (PPGMCHECKINTARGS)pvUser;
4427	PPGMPHYSHANDLER pCur = (PPGMPHYSHANDLER)pNode;
4428	AssertReleaseReturn(!((uintptr_t)pCur & 7), 1);
4429	AssertReleaseMsg(pCur->Core.Key <= pCur->Core.KeyLast,("pCur=%p %RGp-%RGp %s\n", pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
4430	AssertReleaseMsg( !pArgs->pPrevPhys
4431	\|\| (pArgs->fLeftToRight ? pArgs->pPrevPhys->Core.KeyLast < pCur->Core.Key : pArgs->pPrevPhys->Core.KeyLast > pCur->Core.Key),
4432	("pPrevPhys=%p %RGp-%RGp %s\n"
4433	" pCur=%p %RGp-%RGp %s\n",
4434	pArgs->pPrevPhys, pArgs->pPrevPhys->Core.Key, pArgs->pPrevPhys->Core.KeyLast, pArgs->pPrevPhys->pszDesc,
4435	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
4436	pArgs->pPrevPhys = pCur;
4437	return 0;
4438	}
4439
4440
4441	/**
4442	* Validate a node in the virtual handler tree.
4443	*
4444	* @returns 0 on if ok, other wise 1.
4445	* @param pNode The handler node.
4446	* @param pvUser pVM.
4447	*/
4448	static DECLCALLBACK(int) pgmR3CheckIntegrityVirtHandlerNode(PAVLROGCPTRNODECORE pNode, void *pvUser)
4449	{
4450	PPGMCHECKINTARGS pArgs = (PPGMCHECKINTARGS)pvUser;
4451	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)pNode;
4452	AssertReleaseReturn(!((uintptr_t)pCur & 7), 1);
4453	AssertReleaseMsg(pCur->Core.Key <= pCur->Core.KeyLast,("pCur=%p %RGv-%RGv %s\n", pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
4454	AssertReleaseMsg( !pArgs->pPrevVirt
4455	\|\| (pArgs->fLeftToRight ? pArgs->pPrevVirt->Core.KeyLast < pCur->Core.Key : pArgs->pPrevVirt->Core.KeyLast > pCur->Core.Key),
4456	("pPrevVirt=%p %RGv-%RGv %s\n"
4457	" pCur=%p %RGv-%RGv %s\n",
4458	pArgs->pPrevVirt, pArgs->pPrevVirt->Core.Key, pArgs->pPrevVirt->Core.KeyLast, pArgs->pPrevVirt->pszDesc,
4459	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
4460	for (unsigned iPage = 0; iPage < pCur->cPages; iPage++)
4461	{
4462	AssertReleaseMsg(pCur->aPhysToVirt[iPage].offVirtHandler == -RT_OFFSETOF(PGMVIRTHANDLER, aPhysToVirt[iPage]),
4463	("pCur=%p %RGv-%RGv %s\n"
4464	"iPage=%d offVirtHandle=%#x expected %#x\n",
4465	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc,
4466	iPage, pCur->aPhysToVirt[iPage].offVirtHandler, -RT_OFFSETOF(PGMVIRTHANDLER, aPhysToVirt[iPage])));
4467	}
4468	pArgs->pPrevVirt = pCur;
4469	return 0;
4470	}
4471
4472
4473	/**
4474	* Validate a node in the virtual handler tree.
4475	*
4476	* @returns 0 on if ok, other wise 1.
4477	* @param pNode The handler node.
4478	* @param pvUser pVM.
4479	*/
4480	static DECLCALLBACK(int) pgmR3CheckIntegrityPhysToVirtHandlerNode(PAVLROGCPHYSNODECORE pNode, void *pvUser)
4481	{
4482	PPGMCHECKINTARGS pArgs = (PPGMCHECKINTARGS)pvUser;
4483	PPGMPHYS2VIRTHANDLER pCur = (PPGMPHYS2VIRTHANDLER)pNode;
4484	AssertReleaseMsgReturn(!((uintptr_t)pCur & 3), ("\n"), 1);
4485	AssertReleaseMsgReturn(!(pCur->offVirtHandler & 3), ("\n"), 1);
4486	AssertReleaseMsg(pCur->Core.Key <= pCur->Core.KeyLast,("pCur=%p %RGp-%RGp\n", pCur, pCur->Core.Key, pCur->Core.KeyLast));
4487	AssertReleaseMsg( !pArgs->pPrevPhys2Virt
4488	\|\| (pArgs->fLeftToRight ? pArgs->pPrevPhys2Virt->Core.KeyLast < pCur->Core.Key : pArgs->pPrevPhys2Virt->Core.KeyLast > pCur->Core.Key),
4489	("pPrevPhys2Virt=%p %RGp-%RGp\n"
4490	" pCur=%p %RGp-%RGp\n",
4491	pArgs->pPrevPhys2Virt, pArgs->pPrevPhys2Virt->Core.Key, pArgs->pPrevPhys2Virt->Core.KeyLast,
4492	pCur, pCur->Core.Key, pCur->Core.KeyLast));
4493	AssertReleaseMsg( !pArgs->pPrevPhys2Virt
4494	\|\| (pArgs->fLeftToRight ? pArgs->pPrevPhys2Virt->Core.KeyLast < pCur->Core.Key : pArgs->pPrevPhys2Virt->Core.KeyLast > pCur->Core.Key),
4495	("pPrevPhys2Virt=%p %RGp-%RGp\n"
4496	" pCur=%p %RGp-%RGp\n",
4497	pArgs->pPrevPhys2Virt, pArgs->pPrevPhys2Virt->Core.Key, pArgs->pPrevPhys2Virt->Core.KeyLast,
4498	pCur, pCur->Core.Key, pCur->Core.KeyLast));
4499	AssertReleaseMsg((pCur->offNextAlias & (PGMPHYS2VIRTHANDLER_IN_TREE \| PGMPHYS2VIRTHANDLER_IS_HEAD)) == (PGMPHYS2VIRTHANDLER_IN_TREE \| PGMPHYS2VIRTHANDLER_IS_HEAD),
4500	("pCur=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4501	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias));
4502	if (pCur->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK)
4503	{
4504	PPGMPHYS2VIRTHANDLER pCur2 = pCur;
4505	for (;;)
4506	{
4507	pCur2 = (PPGMPHYS2VIRTHANDLER)((intptr_t)pCur + (pCur->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK));
4508	AssertReleaseMsg(pCur2 != pCur,
4509	(" pCur=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4510	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias));
4511	AssertReleaseMsg((pCur2->offNextAlias & (PGMPHYS2VIRTHANDLER_IN_TREE \| PGMPHYS2VIRTHANDLER_IS_HEAD)) == PGMPHYS2VIRTHANDLER_IN_TREE,
4512	(" pCur=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
4513	"pCur2=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4514	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias,
4515	pCur2, pCur2->Core.Key, pCur2->Core.KeyLast, pCur2->offVirtHandler, pCur2->offNextAlias));
4516	AssertReleaseMsg((pCur2->Core.Key ^ pCur->Core.Key) < PAGE_SIZE,
4517	(" pCur=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
4518	"pCur2=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4519	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias,
4520	pCur2, pCur2->Core.Key, pCur2->Core.KeyLast, pCur2->offVirtHandler, pCur2->offNextAlias));
4521	AssertReleaseMsg((pCur2->Core.KeyLast ^ pCur->Core.KeyLast) < PAGE_SIZE,
4522	(" pCur=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
4523	"pCur2=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4524	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias,
4525	pCur2, pCur2->Core.Key, pCur2->Core.KeyLast, pCur2->offVirtHandler, pCur2->offNextAlias));
4526	if (!(pCur2->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK))
4527	break;
4528	}
4529	}
4530
4531	pArgs->pPrevPhys2Virt = pCur;
4532	return 0;
4533	}
4534
4535
4536	/**
4537	* Perform an integrity check on the PGM component.
4538	*
4539	* @returns VINF_SUCCESS if everything is fine.
4540	* @returns VBox error status after asserting on integrity breach.
4541	* @param pVM The VM handle.
4542	*/
4543	VMMR3DECL(int) PGMR3CheckIntegrity(PVM pVM)
4544	{
4545	AssertReleaseReturn(pVM->pgm.s.offVM, VERR_INTERNAL_ERROR);
4546
4547	/*
4548	* Check the trees.
4549	*/
4550	int cErrors = 0;
4551	const static PGMCHECKINTARGS s_LeftToRight = { true, NULL, NULL, NULL, pVM };
4552	const static PGMCHECKINTARGS s_RightToLeft = { false, NULL, NULL, NULL, pVM };
4553	PGMCHECKINTARGS Args = s_LeftToRight;
4554	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysHandlers, true, pgmR3CheckIntegrityPhysHandlerNode, &Args);
4555	Args = s_RightToLeft;
4556	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysHandlers, false, pgmR3CheckIntegrityPhysHandlerNode, &Args);
4557	Args = s_LeftToRight;
4558	cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesR3->VirtHandlers, true, pgmR3CheckIntegrityVirtHandlerNode, &Args);
4559	Args = s_RightToLeft;
4560	cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesR3->VirtHandlers, false, pgmR3CheckIntegrityVirtHandlerNode, &Args);
4561	Args = s_LeftToRight;
4562	cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesR3->HyperVirtHandlers, true, pgmR3CheckIntegrityVirtHandlerNode, &Args);
4563	Args = s_RightToLeft;
4564	cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesR3->HyperVirtHandlers, false, pgmR3CheckIntegrityVirtHandlerNode, &Args);
4565	Args = s_LeftToRight;
4566	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysToVirtHandlers, true, pgmR3CheckIntegrityPhysToVirtHandlerNode, &Args);
4567	Args = s_RightToLeft;
4568	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysToVirtHandlers, false, pgmR3CheckIntegrityPhysToVirtHandlerNode, &Args);
4569
4570	return !cErrors ? VINF_SUCCESS : VERR_INTERNAL_ERROR;
4571	}
4572
4573
4574	/**
4575	* Inform PGM if we want all mappings to be put into the shadow page table. (necessary for e.g. VMX)
4576	*
4577	* @returns VBox status code.
4578	* @param pVM VM handle.
4579	* @param fEnable Enable or disable shadow mappings
4580	*/
4581	VMMR3DECL(int) PGMR3ChangeShwPDMappings(PVM pVM, bool fEnable)
4582	{
4583	pVM->pgm.s.fDisableMappings = !fEnable;
4584
4585	uint32_t cb;
4586	int rc = PGMR3MappingsSize(pVM, &cb);
4587	AssertRCReturn(rc, rc);
4588
4589	/* Pretend the mappings are now fixed; to force a refresh of the reserved PDEs. */
4590	rc = PGMR3MappingsFix(pVM, MM_HYPER_AREA_ADDRESS, cb);
4591	AssertRCReturn(rc, rc);
4592
4593	return VINF_SUCCESS;
4594	}
4595

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source: vbox/trunk/src/VBox/VMM/PGM.cpp@ 15491

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