PGM.cpp@ 16416

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1	/* $Id: PGM.cpp 16412 2009-01-30 13:23:20Z vboxsync $ */
2	/** @file
3	* PGM - Page Manager and Monitor. (Mixing stuff here, not good?)
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22
23	/** @page pg_pgm PGM - The Page Manager and Monitor
24	*
25	* @see grp_pgm,
26	* @ref pg_pgm_pool,
27	* @ref pg_pgm_phys.
28	*
29	*
30	* @section sec_pgm_modes Paging Modes
31	*
32	* There are three memory contexts: Host Context (HC), Guest Context (GC)
33	* and intermediate context. When talking about paging HC can also be refered to
34	* as "host paging", and GC refered to as "shadow paging".
35	*
36	* We define three basic paging modes: 32-bit, PAE and AMD64. The host paging mode
37	* is defined by the host operating system. The mode used in the shadow paging mode
38	* depends on the host paging mode and what the mode the guest is currently in. The
39	* following relation between the two is defined:
40	*
41	* @verbatim
42	Host > 32-bit \| PAE \| AMD64 \|
43	Guest \| \| \| \|
44	==v================================
45	32-bit 32-bit PAE PAE
46	-------\|--------\|--------\|--------\|
47	PAE PAE PAE PAE
48	-------\|--------\|--------\|--------\|
49	AMD64 AMD64 AMD64 AMD64
50	-------\|--------\|--------\|--------\| @endverbatim
51	*
52	* All configuration except those in the diagonal (upper left) are expected to
53	* require special effort from the switcher (i.e. a bit slower).
54	*
55	*
56	*
57	*
58	* @section sec_pgm_shw The Shadow Memory Context
59	*
60	*
61	* [..]
62	*
63	* Because of guest context mappings requires PDPT and PML4 entries to allow
64	* writing on AMD64, the two upper levels will have fixed flags whatever the
65	* guest is thinking of using there. So, when shadowing the PD level we will
66	* calculate the effective flags of PD and all the higher levels. In legacy
67	* PAE mode this only applies to the PWT and PCD bits (the rest are
68	* ignored/reserved/MBZ). We will ignore those bits for the present.
69	*
70	*
71	*
72	* @section sec_pgm_int The Intermediate Memory Context
73	*
74	* The world switch goes thru an intermediate memory context which purpose it is
75	* to provide different mappings of the switcher code. All guest mappings are also
76	* present in this context.
77	*
78	* The switcher code is mapped at the same location as on the host, at an
79	* identity mapped location (physical equals virtual address), and at the
80	* hypervisor location. The identity mapped location is for when the world
81	* switches that involves disabling paging.
82	*
83	* PGM maintain page tables for 32-bit, PAE and AMD64 paging modes. This
84	* simplifies switching guest CPU mode and consistency at the cost of more
85	* code to do the work. All memory use for those page tables is located below
86	* 4GB (this includes page tables for guest context mappings).
87	*
88	*
89	* @subsection subsec_pgm_int_gc Guest Context Mappings
90	*
91	* During assignment and relocation of a guest context mapping the intermediate
92	* memory context is used to verify the new location.
93	*
94	* Guest context mappings are currently restricted to below 4GB, for reasons
95	* of simplicity. This may change when we implement AMD64 support.
96	*
97	*
98	*
99	*
100	* @section sec_pgm_misc Misc
101	*
102	* @subsection subsec_pgm_misc_diff Differences Between Legacy PAE and Long Mode PAE
103	*
104	* The differences between legacy PAE and long mode PAE are:
105	* -# PDPE bits 1, 2, 5 and 6 are defined differently. In leagcy mode they are
106	* all marked down as must-be-zero, while in long mode 1, 2 and 5 have the
107	* usual meanings while 6 is ignored (AMD). This means that upon switching to
108	* legacy PAE mode we'll have to clear these bits and when going to long mode
109	* they must be set. This applies to both intermediate and shadow contexts,
110	* however we don't need to do it for the intermediate one since we're
111	* executing with CR0.WP at that time.
112	* -# CR3 allows a 32-byte aligned address in legacy mode, while in long mode
113	* a page aligned one is required.
114	*
115	*
116	* @section sec_pgm_handlers Access Handlers
117	*
118	* Placeholder.
119	*
120	*
121	* @subsection sec_pgm_handlers_virt Virtual Access Handlers
122	*
123	* Placeholder.
124	*
125	*
126	* @subsection sec_pgm_handlers_virt Virtual Access Handlers
127	*
128	* We currently implement three types of virtual access handlers: ALL, WRITE
129	* and HYPERVISOR (WRITE). See PGMVIRTHANDLERTYPE for some more details.
130	*
131	* The HYPERVISOR access handlers is kept in a separate tree since it doesn't apply
132	* to physical pages (PGMTREES::HyperVirtHandlers) and only needs to be consulted in
133	* a special \#PF case. The ALL and WRITE are in the PGMTREES::VirtHandlers tree, the
134	* rest of this section is going to be about these handlers.
135	*
136	* We'll go thru the life cycle of a handler and try make sense of it all, don't know
137	* how successfull this is gonna be...
138	*
139	* 1. A handler is registered thru the PGMR3HandlerVirtualRegister and
140	* PGMHandlerVirtualRegisterEx APIs. We check for conflicting virtual handlers
141	* and create a new node that is inserted into the AVL tree (range key). Then
142	* a full PGM resync is flagged (clear pool, sync cr3, update virtual bit of PGMPAGE).
143	*
144	* 2. The following PGMSyncCR3/SyncCR3 operation will first make invoke HandlerVirtualUpdate.
145	*
146	* 2a. HandlerVirtualUpdate will will lookup all the pages covered by virtual handlers
147	* via the current guest CR3 and update the physical page -> virtual handler
148	* translation. Needless to say, this doesn't exactly scale very well. If any changes
149	* are detected, it will flag a virtual bit update just like we did on registration.
150	* PGMPHYS pages with changes will have their virtual handler state reset to NONE.
151	*
152	* 2b. The virtual bit update process will iterate all the pages covered by all the
153	* virtual handlers and update the PGMPAGE virtual handler state to the max of all
154	* virtual handlers on that page.
155	*
156	* 2c. Back in SyncCR3 we will now flush the entire shadow page cache to make sure
157	* we don't miss any alias mappings of the monitored pages.
158	*
159	* 2d. SyncCR3 will then proceed with syncing the CR3 table.
160	*
161	* 3. \#PF(np,read) on a page in the range. This will cause it to be synced
162	* read-only and resumed if it's a WRITE handler. If it's an ALL handler we
163	* will call the handlers like in the next step. If the physical mapping has
164	* changed we will - some time in the future - perform a handler callback
165	* (optional) and update the physical -> virtual handler cache.
166	*
167	* 4. \#PF(,write) on a page in the range. This will cause the handler to
168	* be invoked.
169	*
170	* 5. The guest invalidates the page and changes the physical backing or
171	* unmaps it. This should cause the invalidation callback to be invoked
172	* (it might not yet be 100% perfect). Exactly what happens next... is
173	* this where we mess up and end up out of sync for a while?
174	*
175	* 6. The handler is deregistered by the client via PGMHandlerVirtualDeregister.
176	* We will then set all PGMPAGEs in the physical -> virtual handler cache for
177	* this handler to NONE and trigger a full PGM resync (basically the same
178	* as int step 1). Which means 2 is executed again.
179	*
180	*
181	* @subsubsection sub_sec_pgm_handler_virt_todo TODOs
182	*
183	* There is a bunch of things that needs to be done to make the virtual handlers
184	* work 100% correctly and work more efficiently.
185	*
186	* The first bit hasn't been implemented yet because it's going to slow the
187	* whole mess down even more, and besides it seems to be working reliably for
188	* our current uses. OTOH, some of the optimizations might end up more or less
189	* implementing the missing bits, so we'll see.
190	*
191	* On the optimization side, the first thing to do is to try avoid unnecessary
192	* cache flushing. Then try team up with the shadowing code to track changes
193	* in mappings by means of access to them (shadow in), updates to shadows pages,
194	* invlpg, and shadow PT discarding (perhaps).
195	*
196	* Some idea that have popped up for optimization for current and new features:
197	* - bitmap indicating where there are virtual handlers installed.
198	* (4KB => 220 pages, page 212 => covers 32-bit address space 1:1!)
199	* - Further optimize this by min/max (needs min/max avl getters).
200	* - Shadow page table entry bit (if any left)?
201	*
202	*/
203
204
205	/** @page pg_pgm_phys PGM Physical Guest Memory Management
206	*
207	*
208	* Objectives:
209	* - Guest RAM over-commitment using memory ballooning,
210	* zero pages and general page sharing.
211	* - Moving or mirroring a VM onto a different physical machine.
212	*
213	*
214	* @subsection subsec_pgmPhys_Definitions Definitions
215	*
216	* Allocation chunk - A RTR0MemObjAllocPhysNC object and the tracking
217	* machinery assoicated with it.
218	*
219	*
220	*
221	*
222	* @subsection subsec_pgmPhys_AllocPage Allocating a page.
223	*
224	* Initially we map all guest memory to the (per VM) zero page, which
225	* means that none of the read functions will cause pages to be allocated.
226	*
227	* Exception, access bit in page tables that have been shared. This must
228	* be handled, but we must also make sure PGMGst*Modify doesn't make
229	* unnecessary modifications.
230	*
231	* Allocation points:
232	* - PGMPhysSimpleWriteGCPhys and PGMPhysWrite.
233	* - Replacing a zero page mapping at \#PF.
234	* - Replacing a shared page mapping at \#PF.
235	* - ROM registration (currently MMR3RomRegister).
236	* - VM restore (pgmR3Load).
237	*
238	* For the first three it would make sense to keep a few pages handy
239	* until we've reached the max memory commitment for the VM.
240	*
241	* For the ROM registration, we know exactly how many pages we need
242	* and will request these from ring-0. For restore, we will save
243	* the number of non-zero pages in the saved state and allocate
244	* them up front. This would allow the ring-0 component to refuse
245	* the request if the isn't sufficient memory available for VM use.
246	*
247	* Btw. for both ROM and restore allocations we won't be requiring
248	* zeroed pages as they are going to be filled instantly.
249	*
250	*
251	* @subsection subsec_pgmPhys_FreePage Freeing a page
252	*
253	* There are a few points where a page can be freed:
254	* - After being replaced by the zero page.
255	* - After being replaced by a shared page.
256	* - After being ballooned by the guest additions.
257	* - At reset.
258	* - At restore.
259	*
260	* When freeing one or more pages they will be returned to the ring-0
261	* component and replaced by the zero page.
262	*
263	* The reasoning for clearing out all the pages on reset is that it will
264	* return us to the exact same state as on power on, and may thereby help
265	* us reduce the memory load on the system. Further it might have a
266	* (temporary) positive influence on memory fragmentation (@see subsec_pgmPhys_Fragmentation).
267	*
268	* On restore, as mention under the allocation topic, pages should be
269	* freed / allocated depending on how many is actually required by the
270	* new VM state. The simplest approach is to do like on reset, and free
271	* all non-ROM pages and then allocate what we need.
272	*
273	* A measure to prevent some fragmentation, would be to let each allocation
274	* chunk have some affinity towards the VM having allocated the most pages
275	* from it. Also, try make sure to allocate from allocation chunks that
276	* are almost full. Admittedly, both these measures might work counter to
277	* our intentions and its probably not worth putting a lot of effort,
278	* cpu time or memory into this.
279	*
280	*
281	* @subsection subsec_pgmPhys_SharePage Sharing a page
282	*
283	* The basic idea is that there there will be a idle priority kernel
284	* thread walking the non-shared VM pages hashing them and looking for
285	* pages with the same checksum. If such pages are found, it will compare
286	* them byte-by-byte to see if they actually are identical. If found to be
287	* identical it will allocate a shared page, copy the content, check that
288	* the page didn't change while doing this, and finally request both the
289	* VMs to use the shared page instead. If the page is all zeros (special
290	* checksum and byte-by-byte check) it will request the VM that owns it
291	* to replace it with the zero page.
292	*
293	* To make this efficient, we will have to make sure not to try share a page
294	* that will change its contents soon. This part requires the most work.
295	* A simple idea would be to request the VM to write monitor the page for
296	* a while to make sure it isn't modified any time soon. Also, it may
297	* make sense to skip pages that are being write monitored since this
298	* information is readily available to the thread if it works on the
299	* per-VM guest memory structures (presently called PGMRAMRANGE).
300	*
301	*
302	* @subsection subsec_pgmPhys_Fragmentation Fragmentation Concerns and Counter Measures
303	*
304	* The pages are organized in allocation chunks in ring-0, this is a necessity
305	* if we wish to have an OS agnostic approach to this whole thing. (On Linux we
306	* could easily work on a page-by-page basis if we liked. Whether this is possible
307	* or efficient on NT I don't quite know.) Fragmentation within these chunks may
308	* become a problem as part of the idea here is that we wish to return memory to
309	* the host system.
310	*
311	* For instance, starting two VMs at the same time, they will both allocate the
312	* guest memory on-demand and if permitted their page allocations will be
313	* intermixed. Shut down one of the two VMs and it will be difficult to return
314	* any memory to the host system because the page allocation for the two VMs are
315	* mixed up in the same allocation chunks.
316	*
317	* To further complicate matters, when pages are freed because they have been
318	* ballooned or become shared/zero the whole idea is that the page is supposed
319	* to be reused by another VM or returned to the host system. This will cause
320	* allocation chunks to contain pages belonging to different VMs and prevent
321	* returning memory to the host when one of those VM shuts down.
322	*
323	* The only way to really deal with this problem is to move pages. This can
324	* either be done at VM shutdown and or by the idle priority worker thread
325	* that will be responsible for finding sharable/zero pages. The mechanisms
326	* involved for coercing a VM to move a page (or to do it for it) will be
327	* the same as when telling it to share/zero a page.
328	*
329	*
330	* @subsection subsec_pgmPhys_Tracking Tracking Structures And Their Cost
331	*
332	* There's a difficult balance between keeping the per-page tracking structures
333	* (global and guest page) easy to use and keeping them from eating too much
334	* memory. We have limited virtual memory resources available when operating in
335	* 32-bit kernel space (on 64-bit there'll it's quite a different story). The
336	* tracking structures will be attemted designed such that we can deal with up
337	* to 32GB of memory on a 32-bit system and essentially unlimited on 64-bit ones.
338	*
339	*
340	* @subsubsection subsubsec_pgmPhys_Tracking_Kernel Kernel Space
341	*
342	* @see pg_GMM
343	*
344	* @subsubsection subsubsec_pgmPhys_Tracking_PerVM Per-VM
345	*
346	* Fixed info is the physical address of the page (HCPhys) and the page id
347	* (described above). Theoretically we'll need 48(-12) bits for the HCPhys part.
348	* Today we've restricting ourselves to 40(-12) bits because this is the current
349	* restrictions of all AMD64 implementations (I think Barcelona will up this
350	* to 48(-12) bits, not that it really matters) and I needed the bits for
351	* tracking mappings of a page. 48-12 = 36. That leaves 28 bits, which means a
352	* decent range for the page id: 2^(28+12) = 1024TB.
353	*
354	* In additions to these, we'll have to keep maintaining the page flags as we
355	* currently do. Although it wouldn't harm to optimize these quite a bit, like
356	* for instance the ROM shouldn't depend on having a write handler installed
357	* in order for it to become read-only. A RO/RW bit should be considered so
358	* that the page syncing code doesn't have to mess about checking multiple
359	* flag combinations (ROM \|\| RW handler \|\| write monitored) in order to
360	* figure out how to setup a shadow PTE. But this of course, is second
361	* priority at present. Current this requires 12 bits, but could probably
362	* be optimized to ~8.
363	*
364	* Then there's the 24 bits used to track which shadow page tables are
365	* currently mapping a page for the purpose of speeding up physical
366	* access handlers, and thereby the page pool cache. More bit for this
367	* purpose wouldn't hurt IIRC.
368	*
369	* Then there is a new bit in which we need to record what kind of page
370	* this is, shared, zero, normal or write-monitored-normal. This'll
371	* require 2 bits. One bit might be needed for indicating whether a
372	* write monitored page has been written to. And yet another one or
373	* two for tracking migration status. 3-4 bits total then.
374	*
375	* Whatever is left will can be used to record the sharabilitiy of a
376	* page. The page checksum will not be stored in the per-VM table as
377	* the idle thread will not be permitted to do modifications to it.
378	* It will instead have to keep its own working set of potentially
379	* shareable pages and their check sums and stuff.
380	*
381	* For the present we'll keep the current packing of the
382	* PGMRAMRANGE::aHCPhys to keep the changes simple, only of course,
383	* we'll have to change it to a struct with a total of 128-bits at
384	* our disposal.
385	*
386	* The initial layout will be like this:
387	* @verbatim
388	RTHCPHYS HCPhys; The current stuff.
389	63:40 Current shadow PT tracking stuff.
390	39:12 The physical page frame number.
391	11:0 The current flags.
392	uint32_t u28PageId : 28; The page id.
393	uint32_t u2State : 2; The page state { zero, shared, normal, write monitored }.
394	uint32_t fWrittenTo : 1; Whether a write monitored page was written to.
395	uint32_t u1Reserved : 1; Reserved for later.
396	uint32_t u32Reserved; Reserved for later, mostly sharing stats.
397	@endverbatim
398	*
399	* The final layout will be something like this:
400	* @verbatim
401	RTHCPHYS HCPhys; The current stuff.
402	63:48 High page id (12+).
403	47:12 The physical page frame number.
404	11:0 Low page id.
405	uint32_t fReadOnly : 1; Whether it's readonly page (rom or monitored in some way).
406	uint32_t u3Type : 3; The page type {RESERVED, MMIO, MMIO2, ROM, shadowed ROM, RAM}.
407	uint32_t u2PhysMon : 2; Physical access handler type {none, read, write, all}.
408	uint32_t u2VirtMon : 2; Virtual access handler type {none, read, write, all}..
409	uint32_t u2State : 2; The page state { zero, shared, normal, write monitored }.
410	uint32_t fWrittenTo : 1; Whether a write monitored page was written to.
411	uint32_t u20Reserved : 20; Reserved for later, mostly sharing stats.
412	uint32_t u32Tracking; The shadow PT tracking stuff, roughly.
413	@endverbatim
414	*
415	* Cost wise, this means we'll double the cost for guest memory. There isn't anyway
416	* around that I'm afraid. It means that the cost of dealing out 32GB of memory
417	* to one or more VMs is: (32GB >> PAGE_SHIFT) * 16 bytes, or 128MBs. Or another
418	* example, the VM heap cost when assigning 1GB to a VM will be: 4MB.
419	*
420	* A couple of cost examples for the total cost per-VM + kernel.
421	* 32-bit Windows and 32-bit linux:
422	* 1GB guest ram, 256K pages: 4MB + 2MB(+) = 6MB
423	* 4GB guest ram, 1M pages: 16MB + 8MB(+) = 24MB
424	* 32GB guest ram, 8M pages: 128MB + 64MB(+) = 192MB
425	* 64-bit Windows and 64-bit linux:
426	* 1GB guest ram, 256K pages: 4MB + 3MB(+) = 7MB
427	* 4GB guest ram, 1M pages: 16MB + 12MB(+) = 28MB
428	* 32GB guest ram, 8M pages: 128MB + 96MB(+) = 224MB
429	*
430	* UPDATE - 2007-09-27:
431	* Will need a ballooned flag/state too because we cannot
432	* trust the guest 100% and reporting the same page as ballooned more
433	* than once will put the GMM off balance.
434	*
435	*
436	* @subsection subsec_pgmPhys_Serializing Serializing Access
437	*
438	* Initially, we'll try a simple scheme:
439	*
440	* - The per-VM RAM tracking structures (PGMRAMRANGE) is only modified
441	* by the EMT thread of that VM while in the pgm critsect.
442	* - Other threads in the VM process that needs to make reliable use of
443	* the per-VM RAM tracking structures will enter the critsect.
444	* - No process external thread or kernel thread will ever try enter
445	* the pgm critical section, as that just won't work.
446	* - The idle thread (and similar threads) doesn't not need 100% reliable
447	* data when performing it tasks as the EMT thread will be the one to
448	* do the actual changes later anyway. So, as long as it only accesses
449	* the main ram range, it can do so by somehow preventing the VM from
450	* being destroyed while it works on it...
451	*
452	* - The over-commitment management, including the allocating/freeing
453	* chunks, is serialized by a ring-0 mutex lock (a fast one since the
454	* more mundane mutex implementation is broken on Linux).
455	* - A separeate mutex is protecting the set of allocation chunks so
456	* that pages can be shared or/and freed up while some other VM is
457	* allocating more chunks. This mutex can be take from under the other
458	* one, but not the otherway around.
459	*
460	*
461	* @subsection subsec_pgmPhys_Request VM Request interface
462	*
463	* When in ring-0 it will become necessary to send requests to a VM so it can
464	* for instance move a page while defragmenting during VM destroy. The idle
465	* thread will make use of this interface to request VMs to setup shared
466	* pages and to perform write monitoring of pages.
467	*
468	* I would propose an interface similar to the current VMReq interface, similar
469	* in that it doesn't require locking and that the one sending the request may
470	* wait for completion if it wishes to. This shouldn't be very difficult to
471	* realize.
472	*
473	* The requests themselves are also pretty simple. They are basically:
474	* -# Check that some precondition is still true.
475	* -# Do the update.
476	* -# Update all shadow page tables involved with the page.
477	*
478	* The 3rd step is identical to what we're already doing when updating a
479	* physical handler, see pgmHandlerPhysicalSetRamFlagsAndFlushShadowPTs.
480	*
481	*
482	*
483	* @section sec_pgmPhys_MappingCaches Mapping Caches
484	*
485	* In order to be able to map in and out memory and to be able to support
486	* guest with more RAM than we've got virtual address space, we'll employing
487	* a mapping cache. There is already a tiny one for GC (see PGMGCDynMapGCPageEx)
488	* and we'll create a similar one for ring-0 unless we decide to setup a dedicate
489	* memory context for the HWACCM execution.
490	*
491	*
492	* @subsection subsec_pgmPhys_MappingCaches_R3 Ring-3
493	*
494	* We've considered implementing the ring-3 mapping cache page based but found
495	* that this was bother some when one had to take into account TLBs+SMP and
496	* portability (missing the necessary APIs on several platforms). There were
497	* also some performance concerns with this approach which hadn't quite been
498	* worked out.
499	*
500	* Instead, we'll be mapping allocation chunks into the VM process. This simplifies
501	* matters greatly quite a bit since we don't need to invent any new ring-0 stuff,
502	* only some minor RTR0MEMOBJ mapping stuff. The main concern here is that mapping
503	* compared to the previous idea is that mapping or unmapping a 1MB chunk is more
504	* costly than a single page, although how much more costly is uncertain. We'll
505	* try address this by using a very big cache, preferably bigger than the actual
506	* VM RAM size if possible. The current VM RAM sizes should give some idea for
507	* 32-bit boxes, while on 64-bit we can probably get away with employing an
508	* unlimited cache.
509	*
510	* The cache have to parts, as already indicated, the ring-3 side and the
511	* ring-0 side.
512	*
513	* The ring-0 will be tied to the page allocator since it will operate on the
514	* memory objects it contains. It will therefore require the first ring-0 mutex
515	* discussed in @ref subsec_pgmPhys_Serializing. We
516	* some double house keeping wrt to who has mapped what I think, since both
517	* VMMR0.r0 and RTR0MemObj will keep track of mapping relataions
518	*
519	* The ring-3 part will be protected by the pgm critsect. For simplicity, we'll
520	* require anyone that desires to do changes to the mapping cache to do that
521	* from within this critsect. Alternatively, we could employ a separate critsect
522	* for serializing changes to the mapping cache as this would reduce potential
523	* contention with other threads accessing mappings unrelated to the changes
524	* that are in process. We can see about this later, contention will show
525	* up in the statistics anyway, so it'll be simple to tell.
526	*
527	* The organization of the ring-3 part will be very much like how the allocation
528	* chunks are organized in ring-0, that is in an AVL tree by chunk id. To avoid
529	* having to walk the tree all the time, we'll have a couple of lookaside entries
530	* like in we do for I/O ports and MMIO in IOM.
531	*
532	* The simplified flow of a PGMPhysRead/Write function:
533	* -# Enter the PGM critsect.
534	* -# Lookup GCPhys in the ram ranges and get the Page ID.
535	* -# Calc the Allocation Chunk ID from the Page ID.
536	* -# Check the lookaside entries and then the AVL tree for the Chunk ID.
537	* If not found in cache:
538	* -# Call ring-0 and request it to be mapped and supply
539	* a chunk to be unmapped if the cache is maxed out already.
540	* -# Insert the new mapping into the AVL tree (id + R3 address).
541	* -# Update the relevant lookaside entry and return the mapping address.
542	* -# Do the read/write according to monitoring flags and everything.
543	* -# Leave the critsect.
544	*
545	*
546	* @section sec_pgmPhys_Fallback Fallback
547	*
548	* Current all the "second tier" hosts will not support the RTR0MemObjAllocPhysNC
549	* API and thus require a fallback.
550	*
551	* So, when RTR0MemObjAllocPhysNC returns VERR_NOT_SUPPORTED the page allocator
552	* will return to the ring-3 caller (and later ring-0) and asking it to seed
553	* the page allocator with some fresh pages (VERR_GMM_SEED_ME). Ring-3 will
554	* then perform an SUPPageAlloc(cbChunk >> PAGE_SHIFT) call and make a
555	* "SeededAllocPages" call to ring-0.
556	*
557	* The first time ring-0 sees the VERR_NOT_SUPPORTED failure it will disable
558	* all page sharing (zero page detection will continue). It will also force
559	* all allocations to come from the VM which seeded the page. Both these
560	* measures are taken to make sure that there will never be any need for
561	* mapping anything into ring-3 - everything will be mapped already.
562	*
563	* Whether we'll continue to use the current MM locked memory management
564	* for this I don't quite know (I'd prefer not to and just ditch that all
565	* togther), we'll see what's simplest to do.
566	*
567	*
568	*
569	* @section sec_pgmPhys_Changes Changes
570	*
571	* Breakdown of the changes involved?
572	*/
573
574
575	/** Saved state data unit version. */
576	#define PGM_SAVED_STATE_VERSION 6
577
578	/*******************************************************************************
579	* Header Files *
580	*******************************************************************************/
581	#define LOG_GROUP LOG_GROUP_PGM
582	#include <VBox/dbgf.h>
583	#include <VBox/pgm.h>
584	#include <VBox/cpum.h>
585	#include <VBox/iom.h>
586	#include <VBox/sup.h>
587	#include <VBox/mm.h>
588	#include <VBox/em.h>
589	#include <VBox/stam.h>
590	#include <VBox/rem.h>
591	#include <VBox/dbgf.h>
592	#include <VBox/rem.h>
593	#include <VBox/selm.h>
594	#include <VBox/ssm.h>
595	#include "PGMInternal.h"
596	#include <VBox/vm.h>
597	#include <VBox/dbg.h>
598	#include <VBox/hwaccm.h>
599
600	#include <iprt/assert.h>
601	#include <iprt/alloc.h>
602	#include <iprt/asm.h>
603	#include <iprt/thread.h>
604	#include <iprt/string.h>
605	#ifdef DEBUG_bird
606	# include <iprt/env.h>
607	#endif
608	#include <VBox/param.h>
609	#include <VBox/err.h>
610
611
612
613	/*******************************************************************************
614	* Internal Functions *
615	*******************************************************************************/
616	static int pgmR3InitPaging(PVM pVM);
617	static DECLCALLBACK(void) pgmR3PhysInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
618	static DECLCALLBACK(void) pgmR3InfoMode(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
619	static DECLCALLBACK(void) pgmR3InfoCr3(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
620	static DECLCALLBACK(int) pgmR3RelocatePhysHandler(PAVLROGCPHYSNODECORE pNode, void *pvUser);
621	static DECLCALLBACK(int) pgmR3RelocateVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser);
622	static DECLCALLBACK(int) pgmR3RelocateHyperVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser);
623	#ifdef VBOX_STRICT
624	static DECLCALLBACK(void) pgmR3ResetNoMorePhysWritesFlag(PVM pVM, VMSTATE enmState, VMSTATE enmOldState, void *pvUser);
625	#endif
626	static DECLCALLBACK(int) pgmR3Save(PVM pVM, PSSMHANDLE pSSM);
627	static DECLCALLBACK(int) pgmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version);
628	static int pgmR3ModeDataInit(PVM pVM, bool fResolveGCAndR0);
629	static void pgmR3ModeDataSwitch(PVM pVM, PGMMODE enmShw, PGMMODE enmGst);
630	static PGMMODE pgmR3CalcShadowMode(PVM pVM, PGMMODE enmGuestMode, SUPPAGINGMODE enmHostMode, PGMMODE enmShadowMode, VMMSWITCHER *penmSwitcher);
631
632	#ifdef VBOX_WITH_STATISTICS
633	static void pgmR3InitStats(PVM pVM);
634	#endif
635
636	#ifdef VBOX_WITH_DEBUGGER
637	/** @todo all but the two last commands must be converted to 'info'. */
638	static DECLCALLBACK(int) pgmR3CmdRam(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
639	static DECLCALLBACK(int) pgmR3CmdMap(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
640	static DECLCALLBACK(int) pgmR3CmdSync(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
641	static DECLCALLBACK(int) pgmR3CmdSyncAlways(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
642	# ifdef VBOX_STRICT
643	static DECLCALLBACK(int) pgmR3CmdAssertCR3(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
644	# endif
645	#endif
646
647
648	/*******************************************************************************
649	* Global Variables *
650	*******************************************************************************/
651	#ifdef VBOX_WITH_DEBUGGER
652	/** Command descriptors. */
653	static const DBGCCMD g_aCmds[] =
654	{
655	/* pszCmd, cArgsMin, cArgsMax, paArgDesc, cArgDescs, pResultDesc, fFlags, pfnHandler pszSyntax, ....pszDescription */
656	{ "pgmram", 0, 0, NULL, 0, NULL, 0, pgmR3CmdRam, "", "Display the ram ranges." },
657	{ "pgmmap", 0, 0, NULL, 0, NULL, 0, pgmR3CmdMap, "", "Display the mapping ranges." },
658	{ "pgmsync", 0, 0, NULL, 0, NULL, 0, pgmR3CmdSync, "", "Sync the CR3 page." },
659	#ifdef VBOX_STRICT
660	{ "pgmassertcr3", 0, 0, NULL, 0, NULL, 0, pgmR3CmdAssertCR3, "", "Check the shadow CR3 mapping." },
661	#endif
662	{ "pgmsyncalways", 0, 0, NULL, 0, NULL, 0, pgmR3CmdSyncAlways, "", "Toggle permanent CR3 syncing." },
663	};
664	#endif
665
666
667
668
669	/*
670	* Shadow - 32-bit mode
671	*/
672	#define PGM_SHW_TYPE PGM_TYPE_32BIT
673	#define PGM_SHW_NAME(name) PGM_SHW_NAME_32BIT(name)
674	#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_32BIT_STR(name)
675	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_32BIT_STR(name)
676	#include "PGMShw.h"
677
678	/* Guest - real mode */
679	#define PGM_GST_TYPE PGM_TYPE_REAL
680	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
681	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_REAL_STR(name)
682	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
683	#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_REAL(name)
684	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_32BIT_REAL_STR(name)
685	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_32BIT_REAL_STR(name)
686	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_PHYS
687	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_32BIT_PD_PHYS_REAL
688	#include "PGMBth.h"
689	#include "PGMGst.h"
690	#undef BTH_PGMPOOLKIND_PT_FOR_PT
691	#undef BTH_PGMPOOLKIND_ROOT
692	#undef PGM_BTH_NAME
693	#undef PGM_BTH_NAME_RC_STR
694	#undef PGM_BTH_NAME_R0_STR
695	#undef PGM_GST_TYPE
696	#undef PGM_GST_NAME
697	#undef PGM_GST_NAME_RC_STR
698	#undef PGM_GST_NAME_R0_STR
699
700	/* Guest - protected mode */
701	#define PGM_GST_TYPE PGM_TYPE_PROT
702	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
703	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PROT_STR(name)
704	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
705	#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_PROT(name)
706	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_32BIT_PROT_STR(name)
707	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_32BIT_PROT_STR(name)
708	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_PHYS
709	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_32BIT_PD_PHYS_PROT
710	#include "PGMBth.h"
711	#include "PGMGst.h"
712	#undef BTH_PGMPOOLKIND_PT_FOR_PT
713	#undef BTH_PGMPOOLKIND_ROOT
714	#undef PGM_BTH_NAME
715	#undef PGM_BTH_NAME_RC_STR
716	#undef PGM_BTH_NAME_R0_STR
717	#undef PGM_GST_TYPE
718	#undef PGM_GST_NAME
719	#undef PGM_GST_NAME_RC_STR
720	#undef PGM_GST_NAME_R0_STR
721
722	/* Guest - 32-bit mode */
723	#define PGM_GST_TYPE PGM_TYPE_32BIT
724	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
725	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_32BIT_STR(name)
726	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
727	#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_32BIT(name)
728	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_32BIT_32BIT_STR(name)
729	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_32BIT_32BIT_STR(name)
730	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT
731	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB
732	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_32BIT_PD
733	#include "PGMBth.h"
734	#include "PGMGst.h"
735	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
736	#undef BTH_PGMPOOLKIND_PT_FOR_PT
737	#undef BTH_PGMPOOLKIND_ROOT
738	#undef PGM_BTH_NAME
739	#undef PGM_BTH_NAME_RC_STR
740	#undef PGM_BTH_NAME_R0_STR
741	#undef PGM_GST_TYPE
742	#undef PGM_GST_NAME
743	#undef PGM_GST_NAME_RC_STR
744	#undef PGM_GST_NAME_R0_STR
745
746	#undef PGM_SHW_TYPE
747	#undef PGM_SHW_NAME
748	#undef PGM_SHW_NAME_RC_STR
749	#undef PGM_SHW_NAME_R0_STR
750
751
752	/*
753	* Shadow - PAE mode
754	*/
755	#define PGM_SHW_TYPE PGM_TYPE_PAE
756	#define PGM_SHW_NAME(name) PGM_SHW_NAME_PAE(name)
757	#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_PAE_STR(name)
758	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_PAE_STR(name)
759	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_REAL(name)
760	#include "PGMShw.h"
761
762	/* Guest - real mode */
763	#define PGM_GST_TYPE PGM_TYPE_REAL
764	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
765	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_REAL_STR(name)
766	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
767	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_REAL(name)
768	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_PAE_REAL_STR(name)
769	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_REAL_STR(name)
770	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
771	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT_PHYS_REAL
772	#include "PGMBth.h"
773	#undef BTH_PGMPOOLKIND_PT_FOR_PT
774	#undef BTH_PGMPOOLKIND_ROOT
775	#undef PGM_BTH_NAME
776	#undef PGM_BTH_NAME_RC_STR
777	#undef PGM_BTH_NAME_R0_STR
778	#undef PGM_GST_TYPE
779	#undef PGM_GST_NAME
780	#undef PGM_GST_NAME_RC_STR
781	#undef PGM_GST_NAME_R0_STR
782
783	/* Guest - protected mode */
784	#define PGM_GST_TYPE PGM_TYPE_PROT
785	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
786	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PROT_STR(name)
787	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
788	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_PROT(name)
789	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_PAE_PROT_STR(name)
790	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_PROT_STR(name)
791	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
792	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT_PHYS_PROT
793	#include "PGMBth.h"
794	#undef BTH_PGMPOOLKIND_PT_FOR_PT
795	#undef BTH_PGMPOOLKIND_ROOT
796	#undef PGM_BTH_NAME
797	#undef PGM_BTH_NAME_RC_STR
798	#undef PGM_BTH_NAME_R0_STR
799	#undef PGM_GST_TYPE
800	#undef PGM_GST_NAME
801	#undef PGM_GST_NAME_RC_STR
802	#undef PGM_GST_NAME_R0_STR
803
804	/* Guest - 32-bit mode */
805	#define PGM_GST_TYPE PGM_TYPE_32BIT
806	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
807	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_32BIT_STR(name)
808	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
809	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_32BIT(name)
810	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_PAE_32BIT_STR(name)
811	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_32BIT_STR(name)
812	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_32BIT_PT
813	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB
814	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT_FOR_32BIT
815	#include "PGMBth.h"
816	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
817	#undef BTH_PGMPOOLKIND_PT_FOR_PT
818	#undef BTH_PGMPOOLKIND_ROOT
819	#undef PGM_BTH_NAME
820	#undef PGM_BTH_NAME_RC_STR
821	#undef PGM_BTH_NAME_R0_STR
822	#undef PGM_GST_TYPE
823	#undef PGM_GST_NAME
824	#undef PGM_GST_NAME_RC_STR
825	#undef PGM_GST_NAME_R0_STR
826
827	/* Guest - PAE mode */
828	#define PGM_GST_TYPE PGM_TYPE_PAE
829	#define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
830	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PAE_STR(name)
831	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PAE_STR(name)
832	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_PAE(name)
833	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_PAE_PAE_STR(name)
834	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_PAE_STR(name)
835	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
836	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
837	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT
838	#include "PGMBth.h"
839	#include "PGMGst.h"
840	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
841	#undef BTH_PGMPOOLKIND_PT_FOR_PT
842	#undef BTH_PGMPOOLKIND_ROOT
843	#undef PGM_BTH_NAME
844	#undef PGM_BTH_NAME_RC_STR
845	#undef PGM_BTH_NAME_R0_STR
846	#undef PGM_GST_TYPE
847	#undef PGM_GST_NAME
848	#undef PGM_GST_NAME_RC_STR
849	#undef PGM_GST_NAME_R0_STR
850
851	#undef PGM_SHW_TYPE
852	#undef PGM_SHW_NAME
853	#undef PGM_SHW_NAME_RC_STR
854	#undef PGM_SHW_NAME_R0_STR
855
856
857	/*
858	* Shadow - AMD64 mode
859	*/
860	#define PGM_SHW_TYPE PGM_TYPE_AMD64
861	#define PGM_SHW_NAME(name) PGM_SHW_NAME_AMD64(name)
862	#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_AMD64_STR(name)
863	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_AMD64_STR(name)
864	#include "PGMShw.h"
865
866	#ifdef VBOX_WITH_64_BITS_GUESTS
867	/* Guest - AMD64 mode */
868	# define PGM_GST_TYPE PGM_TYPE_AMD64
869	# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
870	# define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_AMD64_STR(name)
871	# define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_AMD64_STR(name)
872	# define PGM_BTH_NAME(name) PGM_BTH_NAME_AMD64_AMD64(name)
873	# define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_AMD64_AMD64_STR(name)
874	# define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_AMD64_AMD64_STR(name)
875	# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
876	# define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
877	# define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_64BIT_PML4
878	# include "PGMBth.h"
879	# include "PGMGst.h"
880	# undef BTH_PGMPOOLKIND_PT_FOR_BIG
881	# undef BTH_PGMPOOLKIND_PT_FOR_PT
882	# undef BTH_PGMPOOLKIND_ROOT
883	# undef PGM_BTH_NAME
884	# undef PGM_BTH_NAME_RC_STR
885	# undef PGM_BTH_NAME_R0_STR
886	# undef PGM_GST_TYPE
887	# undef PGM_GST_NAME
888	# undef PGM_GST_NAME_RC_STR
889	# undef PGM_GST_NAME_R0_STR
890	#endif /* VBOX_WITH_64_BITS_GUESTS */
891
892	#undef PGM_SHW_TYPE
893	#undef PGM_SHW_NAME
894	#undef PGM_SHW_NAME_RC_STR
895	#undef PGM_SHW_NAME_R0_STR
896
897
898	/*
899	* Shadow - Nested paging mode
900	*/
901	#define PGM_SHW_TYPE PGM_TYPE_NESTED
902	#define PGM_SHW_NAME(name) PGM_SHW_NAME_NESTED(name)
903	#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_NESTED_STR(name)
904	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_NESTED_STR(name)
905	#include "PGMShw.h"
906
907	/* Guest - real mode */
908	#define PGM_GST_TYPE PGM_TYPE_REAL
909	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
910	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_REAL_STR(name)
911	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
912	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_REAL(name)
913	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_REAL_STR(name)
914	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_REAL_STR(name)
915	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
916	#include "PGMBth.h"
917	#undef BTH_PGMPOOLKIND_PT_FOR_PT
918	#undef PGM_BTH_NAME
919	#undef PGM_BTH_NAME_RC_STR
920	#undef PGM_BTH_NAME_R0_STR
921	#undef PGM_GST_TYPE
922	#undef PGM_GST_NAME
923	#undef PGM_GST_NAME_RC_STR
924	#undef PGM_GST_NAME_R0_STR
925
926	/* Guest - protected mode */
927	#define PGM_GST_TYPE PGM_TYPE_PROT
928	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
929	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PROT_STR(name)
930	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
931	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_PROT(name)
932	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_PROT_STR(name)
933	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_PROT_STR(name)
934	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
935	#include "PGMBth.h"
936	#undef BTH_PGMPOOLKIND_PT_FOR_PT
937	#undef PGM_BTH_NAME
938	#undef PGM_BTH_NAME_RC_STR
939	#undef PGM_BTH_NAME_R0_STR
940	#undef PGM_GST_TYPE
941	#undef PGM_GST_NAME
942	#undef PGM_GST_NAME_RC_STR
943	#undef PGM_GST_NAME_R0_STR
944
945	/* Guest - 32-bit mode */
946	#define PGM_GST_TYPE PGM_TYPE_32BIT
947	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
948	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_32BIT_STR(name)
949	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
950	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_32BIT(name)
951	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_32BIT_STR(name)
952	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_32BIT_STR(name)
953	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_32BIT_PT
954	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB
955	#include "PGMBth.h"
956	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
957	#undef BTH_PGMPOOLKIND_PT_FOR_PT
958	#undef PGM_BTH_NAME
959	#undef PGM_BTH_NAME_RC_STR
960	#undef PGM_BTH_NAME_R0_STR
961	#undef PGM_GST_TYPE
962	#undef PGM_GST_NAME
963	#undef PGM_GST_NAME_RC_STR
964	#undef PGM_GST_NAME_R0_STR
965
966	/* Guest - PAE mode */
967	#define PGM_GST_TYPE PGM_TYPE_PAE
968	#define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
969	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PAE_STR(name)
970	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PAE_STR(name)
971	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_PAE(name)
972	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_PAE_STR(name)
973	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_PAE_STR(name)
974	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
975	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
976	#include "PGMBth.h"
977	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
978	#undef BTH_PGMPOOLKIND_PT_FOR_PT
979	#undef PGM_BTH_NAME
980	#undef PGM_BTH_NAME_RC_STR
981	#undef PGM_BTH_NAME_R0_STR
982	#undef PGM_GST_TYPE
983	#undef PGM_GST_NAME
984	#undef PGM_GST_NAME_RC_STR
985	#undef PGM_GST_NAME_R0_STR
986
987	#ifdef VBOX_WITH_64_BITS_GUESTS
988	/* Guest - AMD64 mode */
989	# define PGM_GST_TYPE PGM_TYPE_AMD64
990	# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
991	# define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_AMD64_STR(name)
992	# define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_AMD64_STR(name)
993	# define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_AMD64(name)
994	# define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_AMD64_STR(name)
995	# define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_AMD64_STR(name)
996	# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
997	# define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
998	# include "PGMBth.h"
999	# undef BTH_PGMPOOLKIND_PT_FOR_BIG
1000	# undef BTH_PGMPOOLKIND_PT_FOR_PT
1001	# undef PGM_BTH_NAME
1002	# undef PGM_BTH_NAME_RC_STR
1003	# undef PGM_BTH_NAME_R0_STR
1004	# undef PGM_GST_TYPE
1005	# undef PGM_GST_NAME
1006	# undef PGM_GST_NAME_RC_STR
1007	# undef PGM_GST_NAME_R0_STR
1008	#endif /* VBOX_WITH_64_BITS_GUESTS */
1009
1010	#undef PGM_SHW_TYPE
1011	#undef PGM_SHW_NAME
1012	#undef PGM_SHW_NAME_RC_STR
1013	#undef PGM_SHW_NAME_R0_STR
1014
1015
1016	/*
1017	* Shadow - EPT
1018	*/
1019	#define PGM_SHW_TYPE PGM_TYPE_EPT
1020	#define PGM_SHW_NAME(name) PGM_SHW_NAME_EPT(name)
1021	#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_EPT_STR(name)
1022	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_EPT_STR(name)
1023	#include "PGMShw.h"
1024
1025	/* Guest - real mode */
1026	#define PGM_GST_TYPE PGM_TYPE_REAL
1027	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
1028	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_REAL_STR(name)
1029	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
1030	#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_REAL(name)
1031	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_REAL_STR(name)
1032	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_REAL_STR(name)
1033	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
1034	#include "PGMBth.h"
1035	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1036	#undef PGM_BTH_NAME
1037	#undef PGM_BTH_NAME_RC_STR
1038	#undef PGM_BTH_NAME_R0_STR
1039	#undef PGM_GST_TYPE
1040	#undef PGM_GST_NAME
1041	#undef PGM_GST_NAME_RC_STR
1042	#undef PGM_GST_NAME_R0_STR
1043
1044	/* Guest - protected mode */
1045	#define PGM_GST_TYPE PGM_TYPE_PROT
1046	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
1047	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PROT_STR(name)
1048	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
1049	#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_PROT(name)
1050	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_PROT_STR(name)
1051	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_PROT_STR(name)
1052	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
1053	#include "PGMBth.h"
1054	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1055	#undef PGM_BTH_NAME
1056	#undef PGM_BTH_NAME_RC_STR
1057	#undef PGM_BTH_NAME_R0_STR
1058	#undef PGM_GST_TYPE
1059	#undef PGM_GST_NAME
1060	#undef PGM_GST_NAME_RC_STR
1061	#undef PGM_GST_NAME_R0_STR
1062
1063	/* Guest - 32-bit mode */
1064	#define PGM_GST_TYPE PGM_TYPE_32BIT
1065	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
1066	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_32BIT_STR(name)
1067	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
1068	#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_32BIT(name)
1069	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_32BIT_STR(name)
1070	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_32BIT_STR(name)
1071	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_32BIT_PT
1072	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB
1073	#include "PGMBth.h"
1074	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
1075	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1076	#undef PGM_BTH_NAME
1077	#undef PGM_BTH_NAME_RC_STR
1078	#undef PGM_BTH_NAME_R0_STR
1079	#undef PGM_GST_TYPE
1080	#undef PGM_GST_NAME
1081	#undef PGM_GST_NAME_RC_STR
1082	#undef PGM_GST_NAME_R0_STR
1083
1084	/* Guest - PAE mode */
1085	#define PGM_GST_TYPE PGM_TYPE_PAE
1086	#define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
1087	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PAE_STR(name)
1088	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PAE_STR(name)
1089	#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_PAE(name)
1090	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_PAE_STR(name)
1091	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_PAE_STR(name)
1092	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
1093	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
1094	#include "PGMBth.h"
1095	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
1096	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1097	#undef PGM_BTH_NAME
1098	#undef PGM_BTH_NAME_RC_STR
1099	#undef PGM_BTH_NAME_R0_STR
1100	#undef PGM_GST_TYPE
1101	#undef PGM_GST_NAME
1102	#undef PGM_GST_NAME_RC_STR
1103	#undef PGM_GST_NAME_R0_STR
1104
1105	#ifdef VBOX_WITH_64_BITS_GUESTS
1106	/* Guest - AMD64 mode */
1107	# define PGM_GST_TYPE PGM_TYPE_AMD64
1108	# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
1109	# define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_AMD64_STR(name)
1110	# define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_AMD64_STR(name)
1111	# define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_AMD64(name)
1112	# define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_AMD64_STR(name)
1113	# define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_AMD64_STR(name)
1114	# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
1115	# define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
1116	# include "PGMBth.h"
1117	# undef BTH_PGMPOOLKIND_PT_FOR_BIG
1118	# undef BTH_PGMPOOLKIND_PT_FOR_PT
1119	# undef PGM_BTH_NAME
1120	# undef PGM_BTH_NAME_RC_STR
1121	# undef PGM_BTH_NAME_R0_STR
1122	# undef PGM_GST_TYPE
1123	# undef PGM_GST_NAME
1124	# undef PGM_GST_NAME_RC_STR
1125	# undef PGM_GST_NAME_R0_STR
1126	#endif /* VBOX_WITH_64_BITS_GUESTS */
1127
1128	#undef PGM_SHW_TYPE
1129	#undef PGM_SHW_NAME
1130	#undef PGM_SHW_NAME_RC_STR
1131	#undef PGM_SHW_NAME_R0_STR
1132
1133
1134
1135	/**
1136	* Initiates the paging of VM.
1137	*
1138	* @returns VBox status code.
1139	* @param pVM Pointer to VM structure.
1140	*/
1141	VMMR3DECL(int) PGMR3Init(PVM pVM)
1142	{
1143	LogFlow(("PGMR3Init:\n"));
1144
1145	/*
1146	* Assert alignment and sizes.
1147	*/
1148	AssertRelease(sizeof(pVM->pgm.s) <= sizeof(pVM->pgm.padding));
1149
1150	/*
1151	* Init the structure.
1152	*/
1153	pVM->pgm.s.offVM = RT_OFFSETOF(VM, pgm.s);
1154	pVM->pgm.s.offVCpu = RT_OFFSETOF(VMCPU, pgm.s);
1155	pVM->pgm.s.enmShadowMode = PGMMODE_INVALID;
1156	pVM->pgm.s.enmGuestMode = PGMMODE_INVALID;
1157	pVM->pgm.s.enmHostMode = SUPPAGINGMODE_INVALID;
1158	pVM->pgm.s.GCPhysCR3 = NIL_RTGCPHYS;
1159	pVM->pgm.s.GCPhysGstCR3Monitored = NIL_RTGCPHYS;
1160	pVM->pgm.s.fA20Enabled = true;
1161	pVM->pgm.s.GCPhys4MBPSEMask = RT_BIT_64(32) - 1; /* default; checked later */
1162	pVM->pgm.s.pGstPaePdptR3 = NULL;
1163	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
1164	pVM->pgm.s.pGstPaePdptR0 = NIL_RTR0PTR;
1165	#endif
1166	pVM->pgm.s.pGstPaePdptRC = NIL_RTRCPTR;
1167	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.apGstPaePDsR3); i++)
1168	{
1169	pVM->pgm.s.apGstPaePDsR3[i] = NULL;
1170	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
1171	pVM->pgm.s.apGstPaePDsR0[i] = NIL_RTR0PTR;
1172	#endif
1173	pVM->pgm.s.apGstPaePDsRC[i] = NIL_RTRCPTR;
1174	pVM->pgm.s.aGCPhysGstPaePDs[i] = NIL_RTGCPHYS;
1175	pVM->pgm.s.aGCPhysGstPaePDsMonitored[i] = NIL_RTGCPHYS;
1176	}
1177
1178	#ifdef VBOX_STRICT
1179	VMR3AtStateRegister(pVM, pgmR3ResetNoMorePhysWritesFlag, NULL);
1180	#endif
1181
1182	/*
1183	* Get the configured RAM size - to estimate saved state size.
1184	*/
1185	uint64_t cbRam;
1186	int rc = CFGMR3QueryU64(CFGMR3GetRoot(pVM), "RamSize", &cbRam);
1187	if (rc == VERR_CFGM_VALUE_NOT_FOUND)
1188	cbRam = pVM->pgm.s.cbRamSize = 0;
1189	else if (RT_SUCCESS(rc))
1190	{
1191	if (cbRam < PAGE_SIZE)
1192	cbRam = 0;
1193	cbRam = RT_ALIGN_64(cbRam, PAGE_SIZE);
1194	pVM->pgm.s.cbRamSize = (RTUINT)cbRam;
1195	}
1196	else
1197	{
1198	AssertMsgFailed(("Configuration error: Failed to query integer \"RamSize\", rc=%Rrc.\n", rc));
1199	return rc;
1200	}
1201
1202	/*
1203	* Register saved state data unit.
1204	*/
1205	rc = SSMR3RegisterInternal(pVM, "pgm", 1, PGM_SAVED_STATE_VERSION, (size_t)cbRam + sizeof(PGM),
1206	NULL, pgmR3Save, NULL,
1207	NULL, pgmR3Load, NULL);
1208	if (RT_FAILURE(rc))
1209	return rc;
1210
1211	/*
1212	* Initialize the PGM critical section and flush the phys TLBs
1213	*/
1214	rc = PDMR3CritSectInit(pVM, &pVM->pgm.s.CritSect, "PGM");
1215	AssertRCReturn(rc, rc);
1216
1217	PGMR3PhysChunkInvalidateTLB(pVM);
1218	PGMPhysInvalidatePageR3MapTLB(pVM);
1219	PGMPhysInvalidatePageR0MapTLB(pVM);
1220	PGMPhysInvalidatePageGCMapTLB(pVM);
1221
1222	/*
1223	* Trees
1224	*/
1225	rc = MMHyperAlloc(pVM, sizeof(PGMTREES), 0, MM_TAG_PGM, (void **)&pVM->pgm.s.pTreesR3);
1226	if (RT_SUCCESS(rc))
1227	{
1228	pVM->pgm.s.pTreesR0 = MMHyperR3ToR0(pVM, pVM->pgm.s.pTreesR3);
1229	pVM->pgm.s.pTreesRC = MMHyperR3ToRC(pVM, pVM->pgm.s.pTreesR3);
1230
1231	/*
1232	* Alocate the zero page.
1233	*/
1234	rc = MMHyperAlloc(pVM, PAGE_SIZE, PAGE_SIZE, MM_TAG_PGM, &pVM->pgm.s.pvZeroPgR3);
1235	}
1236	if (RT_SUCCESS(rc))
1237	{
1238	pVM->pgm.s.pvZeroPgGC = MMHyperR3ToRC(pVM, pVM->pgm.s.pvZeroPgR3);
1239	pVM->pgm.s.pvZeroPgR0 = MMHyperR3ToR0(pVM, pVM->pgm.s.pvZeroPgR3);
1240	AssertRelease(pVM->pgm.s.pvZeroPgR0 != NIL_RTHCPHYS);
1241	pVM->pgm.s.HCPhysZeroPg = MMR3HyperHCVirt2HCPhys(pVM, pVM->pgm.s.pvZeroPgR3);
1242	AssertRelease(pVM->pgm.s.HCPhysZeroPg != NIL_RTHCPHYS);
1243
1244	/*
1245	* Init the paging.
1246	*/
1247	rc = pgmR3InitPaging(pVM);
1248	}
1249	if (RT_SUCCESS(rc))
1250	{
1251	/*
1252	* Init the page pool.
1253	*/
1254	rc = pgmR3PoolInit(pVM);
1255	}
1256	if (RT_SUCCESS(rc))
1257	{
1258	/*
1259	* Info & statistics
1260	*/
1261	DBGFR3InfoRegisterInternal(pVM, "mode",
1262	"Shows the current paging mode. "
1263	"Recognizes 'all', 'guest', 'shadow' and 'host' as arguments, defaulting to 'all' if nothing's given.",
1264	pgmR3InfoMode);
1265	DBGFR3InfoRegisterInternal(pVM, "pgmcr3",
1266	"Dumps all the entries in the top level paging table. No arguments.",
1267	pgmR3InfoCr3);
1268	DBGFR3InfoRegisterInternal(pVM, "phys",
1269	"Dumps all the physical address ranges. No arguments.",
1270	pgmR3PhysInfo);
1271	DBGFR3InfoRegisterInternal(pVM, "handlers",
1272	"Dumps physical, virtual and hyper virtual handlers. "
1273	"Pass 'phys', 'virt', 'hyper' as argument if only one kind is wanted."
1274	"Add 'nost' if the statistics are unwanted, use together with 'all' or explicit selection.",
1275	pgmR3InfoHandlers);
1276	DBGFR3InfoRegisterInternal(pVM, "mappings",
1277	"Dumps guest mappings.",
1278	pgmR3MapInfo);
1279
1280	STAM_REL_REG(pVM, &pVM->pgm.s.cGuestModeChanges, STAMTYPE_COUNTER, "/PGM/cGuestModeChanges", STAMUNIT_OCCURENCES, "Number of guest mode changes.");
1281	STAM_REL_REG(pVM, &pVM->pgm.s.cRelocations, STAMTYPE_COUNTER, "/PGM/cRelocations", STAMUNIT_OCCURENCES, "Number of hypervisor relocations.");
1282	#ifdef VBOX_WITH_STATISTICS
1283	pgmR3InitStats(pVM);
1284	#endif
1285	#ifdef VBOX_WITH_DEBUGGER
1286	/*
1287	* Debugger commands.
1288	*/
1289	static bool fRegisteredCmds = false;
1290	if (!fRegisteredCmds)
1291	{
1292	int rc = DBGCRegisterCommands(&g_aCmds[0], RT_ELEMENTS(g_aCmds));
1293	if (RT_SUCCESS(rc))
1294	fRegisteredCmds = true;
1295	}
1296	#endif
1297	return VINF_SUCCESS;
1298	}
1299
1300	/* Almost no cleanup necessary, MM frees all memory. */
1301	PDMR3CritSectDelete(&pVM->pgm.s.CritSect);
1302
1303	return rc;
1304	}
1305
1306
1307	/**
1308	* Initializes the per-VCPU PGM.
1309	*
1310	* @returns VBox status code.
1311	* @param pVM The VM to operate on.
1312	*/
1313	VMMR3DECL(int) PGMR3InitCPU(PVM pVM)
1314	{
1315	LogFlow(("PGMR3InitCPU\n"));
1316	return VINF_SUCCESS;
1317	}
1318
1319
1320	/**
1321	* Init paging.
1322	*
1323	* Since we need to check what mode the host is operating in before we can choose
1324	* the right paging functions for the host we have to delay this until R0 has
1325	* been initialized.
1326	*
1327	* @returns VBox status code.
1328	* @param pVM VM handle.
1329	*/
1330	static int pgmR3InitPaging(PVM pVM)
1331	{
1332	/*
1333	* Force a recalculation of modes and switcher so everyone gets notified.
1334	*/
1335	pVM->pgm.s.enmShadowMode = PGMMODE_INVALID;
1336	pVM->pgm.s.enmGuestMode = PGMMODE_INVALID;
1337	pVM->pgm.s.enmHostMode = SUPPAGINGMODE_INVALID;
1338
1339	/*
1340	* Allocate static mapping space for whatever the cr3 register
1341	* points to and in the case of PAE mode to the 4 PDs.
1342	*/
1343	int rc = MMR3HyperReserve(pVM, PAGE_SIZE * 5, "CR3 mapping", &pVM->pgm.s.GCPtrCR3Mapping);
1344	if (RT_FAILURE(rc))
1345	{
1346	AssertMsgFailed(("Failed to reserve two pages for cr mapping in HMA, rc=%Rrc\n", rc));
1347	return rc;
1348	}
1349	MMR3HyperReserve(pVM, PAGE_SIZE, "fence", NULL);
1350
1351	/*
1352	* Allocate pages for the three possible intermediate contexts
1353	* (AMD64, PAE and plain 32-Bit). We maintain all three contexts
1354	* for the sake of simplicity. The AMD64 uses the PAE for the
1355	* lower levels, making the total number of pages 11 (3 + 7 + 1).
1356	*
1357	* We assume that two page tables will be enought for the core code
1358	* mappings (HC virtual and identity).
1359	*/
1360	pVM->pgm.s.pInterPD = (PX86PD)MMR3PageAllocLow(pVM);
1361	pVM->pgm.s.apInterPTs[0] = (PX86PT)MMR3PageAllocLow(pVM);
1362	pVM->pgm.s.apInterPTs[1] = (PX86PT)MMR3PageAllocLow(pVM);
1363	pVM->pgm.s.apInterPaePTs[0] = (PX86PTPAE)MMR3PageAlloc(pVM);
1364	pVM->pgm.s.apInterPaePTs[1] = (PX86PTPAE)MMR3PageAlloc(pVM);
1365	pVM->pgm.s.apInterPaePDs[0] = (PX86PDPAE)MMR3PageAlloc(pVM);
1366	pVM->pgm.s.apInterPaePDs[1] = (PX86PDPAE)MMR3PageAlloc(pVM);
1367	pVM->pgm.s.apInterPaePDs[2] = (PX86PDPAE)MMR3PageAlloc(pVM);
1368	pVM->pgm.s.apInterPaePDs[3] = (PX86PDPAE)MMR3PageAlloc(pVM);
1369	pVM->pgm.s.pInterPaePDPT = (PX86PDPT)MMR3PageAllocLow(pVM);
1370	pVM->pgm.s.pInterPaePDPT64 = (PX86PDPT)MMR3PageAllocLow(pVM);
1371	pVM->pgm.s.pInterPaePML4 = (PX86PML4)MMR3PageAllocLow(pVM);
1372	if ( !pVM->pgm.s.pInterPD
1373	\|\| !pVM->pgm.s.apInterPTs[0]
1374	\|\| !pVM->pgm.s.apInterPTs[1]
1375	\|\| !pVM->pgm.s.apInterPaePTs[0]
1376	\|\| !pVM->pgm.s.apInterPaePTs[1]
1377	\|\| !pVM->pgm.s.apInterPaePDs[0]
1378	\|\| !pVM->pgm.s.apInterPaePDs[1]
1379	\|\| !pVM->pgm.s.apInterPaePDs[2]
1380	\|\| !pVM->pgm.s.apInterPaePDs[3]
1381	\|\| !pVM->pgm.s.pInterPaePDPT
1382	\|\| !pVM->pgm.s.pInterPaePDPT64
1383	\|\| !pVM->pgm.s.pInterPaePML4)
1384	{
1385	AssertMsgFailed(("Failed to allocate pages for the intermediate context!\n"));
1386	return VERR_NO_PAGE_MEMORY;
1387	}
1388
1389	pVM->pgm.s.HCPhysInterPD = MMPage2Phys(pVM, pVM->pgm.s.pInterPD);
1390	AssertRelease(pVM->pgm.s.HCPhysInterPD != NIL_RTHCPHYS && !(pVM->pgm.s.HCPhysInterPD & PAGE_OFFSET_MASK));
1391	pVM->pgm.s.HCPhysInterPaePDPT = MMPage2Phys(pVM, pVM->pgm.s.pInterPaePDPT);
1392	AssertRelease(pVM->pgm.s.HCPhysInterPaePDPT != NIL_RTHCPHYS && !(pVM->pgm.s.HCPhysInterPaePDPT & PAGE_OFFSET_MASK));
1393	pVM->pgm.s.HCPhysInterPaePML4 = MMPage2Phys(pVM, pVM->pgm.s.pInterPaePML4);
1394	AssertRelease(pVM->pgm.s.HCPhysInterPaePML4 != NIL_RTHCPHYS && !(pVM->pgm.s.HCPhysInterPaePML4 & PAGE_OFFSET_MASK) && pVM->pgm.s.HCPhysInterPaePML4 < 0xffffffff);
1395
1396	/*
1397	* Initialize the pages, setting up the PML4 and PDPT for repetitive 4GB action.
1398	*/
1399	ASMMemZeroPage(pVM->pgm.s.pInterPD);
1400	ASMMemZeroPage(pVM->pgm.s.apInterPTs[0]);
1401	ASMMemZeroPage(pVM->pgm.s.apInterPTs[1]);
1402
1403	ASMMemZeroPage(pVM->pgm.s.apInterPaePTs[0]);
1404	ASMMemZeroPage(pVM->pgm.s.apInterPaePTs[1]);
1405
1406	ASMMemZeroPage(pVM->pgm.s.pInterPaePDPT);
1407	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.apInterPaePDs); i++)
1408	{
1409	ASMMemZeroPage(pVM->pgm.s.apInterPaePDs[i]);
1410	pVM->pgm.s.pInterPaePDPT->a[i].u = X86_PDPE_P \| PGM_PLXFLAGS_PERMANENT
1411	\| MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[i]);
1412	}
1413
1414	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.pInterPaePDPT64->a); i++)
1415	{
1416	const unsigned iPD = i % RT_ELEMENTS(pVM->pgm.s.apInterPaePDs);
1417	pVM->pgm.s.pInterPaePDPT64->a[i].u = X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_A \| PGM_PLXFLAGS_PERMANENT
1418	\| MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[iPD]);
1419	}
1420
1421	RTHCPHYS HCPhysInterPaePDPT64 = MMPage2Phys(pVM, pVM->pgm.s.pInterPaePDPT64);
1422	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.pInterPaePML4->a); i++)
1423	pVM->pgm.s.pInterPaePML4->a[i].u = X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_A \| PGM_PLXFLAGS_PERMANENT
1424	\| HCPhysInterPaePDPT64;
1425
1426	/*
1427	* Allocate pages for the three possible guest contexts (AMD64, PAE and plain 32-Bit).
1428	* We allocate pages for all three posibilities in order to simplify mappings and
1429	* avoid resource failure during mode switches. So, we need to cover all levels of the
1430	* of the first 4GB down to PD level.
1431	* As with the intermediate context, AMD64 uses the PAE PDPT and PDs.
1432	*/
1433	#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
1434	pVM->pgm.s.pShw32BitPdR3 = (PX86PD)MMR3PageAllocLow(pVM);
1435	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
1436	pVM->pgm.s.pShw32BitPdR0 = (uintptr_t)pVM->pgm.s.pShw32BitPdR3;
1437	# endif
1438	pVM->pgm.s.apShwPaePDsR3[0] = (PX86PDPAE)MMR3PageAlloc(pVM);
1439	pVM->pgm.s.apShwPaePDsR3[1] = (PX86PDPAE)MMR3PageAlloc(pVM);
1440	AssertRelease((uintptr_t)pVM->pgm.s.apShwPaePDsR3[0] + PAGE_SIZE == (uintptr_t)pVM->pgm.s.apShwPaePDsR3[1]);
1441	pVM->pgm.s.apShwPaePDsR3[2] = (PX86PDPAE)MMR3PageAlloc(pVM);
1442	AssertRelease((uintptr_t)pVM->pgm.s.apShwPaePDsR3[1] + PAGE_SIZE == (uintptr_t)pVM->pgm.s.apShwPaePDsR3[2]);
1443	pVM->pgm.s.apShwPaePDsR3[3] = (PX86PDPAE)MMR3PageAlloc(pVM);
1444	AssertRelease((uintptr_t)pVM->pgm.s.apShwPaePDsR3[2] + PAGE_SIZE == (uintptr_t)pVM->pgm.s.apShwPaePDsR3[3]);
1445	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
1446	pVM->pgm.s.apShwPaePDsR0[0] = (uintptr_t)pVM->pgm.s.apShwPaePDsR3[0];
1447	pVM->pgm.s.apShwPaePDsR0[1] = (uintptr_t)pVM->pgm.s.apShwPaePDsR3[1];
1448	pVM->pgm.s.apShwPaePDsR0[2] = (uintptr_t)pVM->pgm.s.apShwPaePDsR3[2];
1449	pVM->pgm.s.apShwPaePDsR0[3] = (uintptr_t)pVM->pgm.s.apShwPaePDsR3[3];
1450	# endif
1451	pVM->pgm.s.pShwPaePdptR3 = (PX86PDPT)MMR3PageAllocLow(pVM);
1452	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
1453	pVM->pgm.s.pShwPaePdptR0 = (uintptr_t)pVM->pgm.s.pShwPaePdptR3;
1454	# endif
1455	#endif /* VBOX_WITH_PGMPOOL_PAGING_ONLY */
1456	pVM->pgm.s.pShwNestedRootR3 = MMR3PageAllocLow(pVM);
1457	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
1458	pVM->pgm.s.pShwNestedRootR0 = (uintptr_t)pVM->pgm.s.pShwNestedRootR3;
1459	#endif
1460
1461	#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
1462	if (!pVM->pgm.s.pShwNestedRootR3)
1463	#else
1464	if ( !pVM->pgm.s.pShw32BitPdR3
1465	\|\| !pVM->pgm.s.apShwPaePDsR3[0]
1466	\|\| !pVM->pgm.s.apShwPaePDsR3[1]
1467	\|\| !pVM->pgm.s.apShwPaePDsR3[2]
1468	\|\| !pVM->pgm.s.apShwPaePDsR3[3]
1469	\|\| !pVM->pgm.s.pShwPaePdptR3
1470	\|\| !pVM->pgm.s.pShwNestedRootR3)
1471	#endif
1472	{
1473	AssertMsgFailed(("Failed to allocate pages for the intermediate context!\n"));
1474	return VERR_NO_PAGE_MEMORY;
1475	}
1476
1477	/* get physical addresses. */
1478	#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
1479	pVM->pgm.s.HCPhysShw32BitPD = MMPage2Phys(pVM, pVM->pgm.s.pShw32BitPdR3);
1480	Assert(MMPagePhys2Page(pVM, pVM->pgm.s.HCPhysShw32BitPD) == pVM->pgm.s.pShw32BitPdR3);
1481	pVM->pgm.s.aHCPhysPaePDs[0] = MMPage2Phys(pVM, pVM->pgm.s.apShwPaePDsR3[0]);
1482	pVM->pgm.s.aHCPhysPaePDs[1] = MMPage2Phys(pVM, pVM->pgm.s.apShwPaePDsR3[1]);
1483	pVM->pgm.s.aHCPhysPaePDs[2] = MMPage2Phys(pVM, pVM->pgm.s.apShwPaePDsR3[2]);
1484	pVM->pgm.s.aHCPhysPaePDs[3] = MMPage2Phys(pVM, pVM->pgm.s.apShwPaePDsR3[3]);
1485	pVM->pgm.s.HCPhysShwPaePdpt = MMPage2Phys(pVM, pVM->pgm.s.pShwPaePdptR3);
1486	#endif
1487	pVM->pgm.s.HCPhysShwNestedRoot = MMPage2Phys(pVM, pVM->pgm.s.pShwNestedRootR3);
1488
1489	/*
1490	* Initialize the pages, setting up the PML4 and PDPT for action below 4GB.
1491	*/
1492	#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
1493	ASMMemZero32(pVM->pgm.s.pShw32BitPdR3, PAGE_SIZE);
1494	ASMMemZero32(pVM->pgm.s.pShwPaePdptR3, PAGE_SIZE);
1495	#endif
1496	ASMMemZero32(pVM->pgm.s.pShwNestedRootR3, PAGE_SIZE);
1497	#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
1498	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.apShwPaePDsR3); i++)
1499	{
1500	ASMMemZero32(pVM->pgm.s.apShwPaePDsR3[i], PAGE_SIZE);
1501	pVM->pgm.s.pShwPaePdptR3->a[i].u = X86_PDPE_P \| PGM_PLXFLAGS_PERMANENT \| pVM->pgm.s.aHCPhysPaePDs[i];
1502	/* The flags will be corrected when entering and leaving long mode. */
1503	}
1504
1505	CPUMSetHyperCR3(pVM, (uint32_t)pVM->pgm.s.HCPhysShw32BitPD);
1506	#endif
1507
1508	/*
1509	* Initialize paging workers and mode from current host mode
1510	* and the guest running in real mode.
1511	*/
1512	pVM->pgm.s.enmHostMode = SUPGetPagingMode();
1513	switch (pVM->pgm.s.enmHostMode)
1514	{
1515	case SUPPAGINGMODE_32_BIT:
1516	case SUPPAGINGMODE_32_BIT_GLOBAL:
1517	case SUPPAGINGMODE_PAE:
1518	case SUPPAGINGMODE_PAE_GLOBAL:
1519	case SUPPAGINGMODE_PAE_NX:
1520	case SUPPAGINGMODE_PAE_GLOBAL_NX:
1521	break;
1522
1523	case SUPPAGINGMODE_AMD64:
1524	case SUPPAGINGMODE_AMD64_GLOBAL:
1525	case SUPPAGINGMODE_AMD64_NX:
1526	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
1527	#ifndef VBOX_WITH_HYBRID_32BIT_KERNEL
1528	if (ARCH_BITS != 64)
1529	{
1530	AssertMsgFailed(("Host mode %d (64-bit) is not supported by non-64bit builds\n", pVM->pgm.s.enmHostMode));
1531	LogRel(("Host mode %d (64-bit) is not supported by non-64bit builds\n", pVM->pgm.s.enmHostMode));
1532	return VERR_PGM_UNSUPPORTED_HOST_PAGING_MODE;
1533	}
1534	#endif
1535	break;
1536	default:
1537	AssertMsgFailed(("Host mode %d is not supported\n", pVM->pgm.s.enmHostMode));
1538	return VERR_PGM_UNSUPPORTED_HOST_PAGING_MODE;
1539	}
1540	rc = pgmR3ModeDataInit(pVM, false /* don't resolve GC and R0 syms yet */);
1541	if (RT_SUCCESS(rc))
1542	rc = PGMR3ChangeMode(pVM, PGMMODE_REAL);
1543	if (RT_SUCCESS(rc))
1544	{
1545	LogFlow(("pgmR3InitPaging: returns successfully\n"));
1546	#if HC_ARCH_BITS == 64
1547	# ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
1548	LogRel(("Debug: HCPhysShw32BitPD=%RHp aHCPhysPaePDs={%RHp,%RHp,%RHp,%RHp} HCPhysShwPaePdpt=%RHp\n",
1549	pVM->pgm.s.HCPhysShw32BitPD,
1550	pVM->pgm.s.aHCPhysPaePDs[0], pVM->pgm.s.aHCPhysPaePDs[1], pVM->pgm.s.aHCPhysPaePDs[2], pVM->pgm.s.aHCPhysPaePDs[3],
1551	pVM->pgm.s.HCPhysShwPaePdpt));
1552	# endif
1553	LogRel(("Debug: HCPhysInterPD=%RHp HCPhysInterPaePDPT=%RHp HCPhysInterPaePML4=%RHp\n",
1554	pVM->pgm.s.HCPhysInterPD, pVM->pgm.s.HCPhysInterPaePDPT, pVM->pgm.s.HCPhysInterPaePML4));
1555	LogRel(("Debug: apInterPTs={%RHp,%RHp} apInterPaePTs={%RHp,%RHp} apInterPaePDs={%RHp,%RHp,%RHp,%RHp} pInterPaePDPT64=%RHp\n",
1556	MMPage2Phys(pVM, pVM->pgm.s.apInterPTs[0]), MMPage2Phys(pVM, pVM->pgm.s.apInterPTs[1]),
1557	MMPage2Phys(pVM, pVM->pgm.s.apInterPaePTs[0]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePTs[1]),
1558	MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[0]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[1]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[2]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[3]),
1559	MMPage2Phys(pVM, pVM->pgm.s.pInterPaePDPT64)));
1560	#endif
1561
1562	return VINF_SUCCESS;
1563	}
1564
1565	LogFlow(("pgmR3InitPaging: returns %Rrc\n", rc));
1566	return rc;
1567	}
1568
1569
1570	#ifdef VBOX_WITH_STATISTICS
1571	/**
1572	* Init statistics
1573	*/
1574	static void pgmR3InitStats(PVM pVM)
1575	{
1576	PPGM pPGM = &pVM->pgm.s;
1577	unsigned i;
1578
1579	/*
1580	* Note! The layout of this function matches the member layout exactly!
1581	*/
1582
1583	/* Common - misc variables */
1584	STAM_REG(pVM, &pPGM->cAllPages, STAMTYPE_U32, "/PGM/Page/cAllPages", STAMUNIT_OCCURENCES, "The total number of pages.");
1585	STAM_REG(pVM, &pPGM->cPrivatePages, STAMTYPE_U32, "/PGM/Page/cPrivatePages", STAMUNIT_OCCURENCES, "The number of private pages.");
1586	STAM_REG(pVM, &pPGM->cSharedPages, STAMTYPE_U32, "/PGM/Page/cSharedPages", STAMUNIT_OCCURENCES, "The number of shared pages.");
1587	STAM_REG(pVM, &pPGM->cZeroPages, STAMTYPE_U32, "/PGM/Page/cZeroPages", STAMUNIT_OCCURENCES, "The number of zero backed pages.");
1588	STAM_REG(pVM, &pPGM->ChunkR3Map.c, STAMTYPE_U32, "/PGM/ChunkR3Map/c", STAMUNIT_OCCURENCES, "Number of mapped chunks.");
1589	STAM_REG(pVM, &pPGM->ChunkR3Map.cMax, STAMTYPE_U32, "/PGM/ChunkR3Map/cMax", STAMUNIT_OCCURENCES, "Maximum number of mapped chunks.");
1590
1591	/* Common - stats */
1592	#ifdef PGMPOOL_WITH_GCPHYS_TRACKING
1593	STAM_REG(pVM, &pPGM->StatTrackVirgin, STAMTYPE_COUNTER, "/PGM/Track/Virgin", STAMUNIT_OCCURENCES, "The number of first time shadowings");
1594	STAM_REG(pVM, &pPGM->StatTrackAliased, STAMTYPE_COUNTER, "/PGM/Track/Aliased", STAMUNIT_OCCURENCES, "The number of times switching to cRef2, i.e. the page is being shadowed by two PTs.");
1595	STAM_REG(pVM, &pPGM->StatTrackAliasedMany, STAMTYPE_COUNTER, "/PGM/Track/AliasedMany", STAMUNIT_OCCURENCES, "The number of times we're tracking using cRef2.");
1596	STAM_REG(pVM, &pPGM->StatTrackAliasedLots, STAMTYPE_COUNTER, "/PGM/Track/AliasedLots", STAMUNIT_OCCURENCES, "The number of times we're hitting pages which has overflowed cRef2");
1597	STAM_REG(pVM, &pPGM->StatTrackOverflows, STAMTYPE_COUNTER, "/PGM/Track/Overflows", STAMUNIT_OCCURENCES, "The number of times the extent list grows to long.");
1598	STAM_REG(pVM, &pPGM->StatTrackDeref, STAMTYPE_PROFILE, "/PGM/Track/Deref", STAMUNIT_OCCURENCES, "Profiling of SyncPageWorkerTrackDeref (expensive).");
1599	#endif
1600	for (i = 0; i < RT_ELEMENTS(pPGM->StatSyncPtPD); i++)
1601	STAMR3RegisterF(pVM, &pPGM->StatSyncPtPD[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
1602	"The number of SyncPT per PD n.", "/PGM/PDSyncPT/%04X", i);
1603	for (i = 0; i < RT_ELEMENTS(pPGM->StatSyncPagePD); i++)
1604	STAMR3RegisterF(pVM, &pPGM->StatSyncPagePD[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
1605	"The number of SyncPage per PD n.", "/PGM/PDSyncPage/%04X", i);
1606
1607	/* R3 only: */
1608	STAM_REG(pVM, &pPGM->StatR3DetectedConflicts, STAMTYPE_COUNTER, "/PGM/R3/DetectedConflicts", STAMUNIT_OCCURENCES, "The number of times PGMR3CheckMappingConflicts() detected a conflict.");
1609	STAM_REG(pVM, &pPGM->StatR3ResolveConflict, STAMTYPE_PROFILE, "/PGM/R3/ResolveConflict", STAMUNIT_TICKS_PER_CALL, "pgmR3SyncPTResolveConflict() profiling (includes the entire relocation).");
1610	STAM_REG(pVM, &pPGM->StatR3GuestPDWrite, STAMTYPE_COUNTER, "/PGM/R3/PDWrite", STAMUNIT_OCCURENCES, "The total number of times pgmHCGuestPDWriteHandler() was called.");
1611	STAM_REG(pVM, &pPGM->StatR3GuestPDWriteConflict, STAMTYPE_COUNTER, "/PGM/R3/PDWriteConflict", STAMUNIT_OCCURENCES, "The number of times pgmHCGuestPDWriteHandler() detected a conflict.");
1612	STAM_REG(pVM, &pPGM->StatR3DynRamTotal, STAMTYPE_COUNTER, "/PGM/DynAlloc/TotalAlloc", STAMUNIT_MEGABYTES, "Allocated MBs of guest ram.");
1613	STAM_REG(pVM, &pPGM->StatR3DynRamGrow, STAMTYPE_COUNTER, "/PGM/DynAlloc/Grow", STAMUNIT_OCCURENCES, "Nr of pgmr3PhysGrowRange calls.");
1614
1615	/* R0 only: */
1616	STAM_REG(pVM, &pPGM->StatR0DynMapMigrateInvlPg, STAMTYPE_COUNTER, "/PGM/R0/DynMapMigrateInvlPg", STAMUNIT_OCCURENCES, "invlpg count in PGMDynMapMigrateAutoSet.");
1617	STAM_REG(pVM, &pPGM->StatR0DynMapGCPageInl, STAMTYPE_PROFILE, "/PGM/R0/DynMapPageGCPageInl", STAMUNIT_TICKS_PER_CALL, "Calls to pgmR0DynMapGCPageInlined.");
1618	STAM_REG(pVM, &pPGM->StatR0DynMapGCPageInlHits, STAMTYPE_COUNTER, "/PGM/R0/DynMapPageGCPageInl/Hits", STAMUNIT_OCCURENCES, "Hash table lookup hits.");
1619	STAM_REG(pVM, &pPGM->StatR0DynMapGCPageInlMisses, STAMTYPE_COUNTER, "/PGM/R0/DynMapPageGCPageInl/Misses", STAMUNIT_OCCURENCES, "Misses that falls back to code common with PGMDynMapHCPage.");
1620	STAM_REG(pVM, &pPGM->StatR0DynMapGCPageInlRamHits, STAMTYPE_COUNTER, "/PGM/R0/DynMapPageGCPageInl/RamHits", STAMUNIT_OCCURENCES, "1st ram range hits.");
1621	STAM_REG(pVM, &pPGM->StatR0DynMapGCPageInlRamMisses, STAMTYPE_COUNTER, "/PGM/R0/DynMapPageGCPageInl/RamMisses", STAMUNIT_OCCURENCES, "1st ram range misses, takes slow path.");
1622	STAM_REG(pVM, &pPGM->StatR0DynMapHCPageInl, STAMTYPE_PROFILE, "/PGM/R0/DynMapPageHCPageInl", STAMUNIT_TICKS_PER_CALL, "Calls to pgmR0DynMapHCPageInlined.");
1623	STAM_REG(pVM, &pPGM->StatR0DynMapHCPageInlHits, STAMTYPE_COUNTER, "/PGM/R0/DynMapPageHCPageInl/Hits", STAMUNIT_OCCURENCES, "Hash table lookup hits.");
1624	STAM_REG(pVM, &pPGM->StatR0DynMapHCPageInlMisses, STAMTYPE_COUNTER, "/PGM/R0/DynMapPageHCPageInl/Misses", STAMUNIT_OCCURENCES, "Misses that falls back to code common with PGMDynMapHCPage.");
1625	STAM_REG(pVM, &pPGM->StatR0DynMapPage, STAMTYPE_COUNTER, "/PGM/R0/DynMapPage", STAMUNIT_OCCURENCES, "Calls to pgmR0DynMapPage");
1626	STAM_REG(pVM, &pPGM->StatR0DynMapSetOptimize, STAMTYPE_COUNTER, "/PGM/R0/DynMapPage/SetOptimize", STAMUNIT_OCCURENCES, "Calls to pgmDynMapOptimizeAutoSet.");
1627	STAM_REG(pVM, &pPGM->StatR0DynMapSetSearchFlushes, STAMTYPE_COUNTER, "/PGM/R0/DynMapPage/SetSearchFlushes",STAMUNIT_OCCURENCES, "Set search restorting to subset flushes.");
1628	STAM_REG(pVM, &pPGM->StatR0DynMapSetSearchHits, STAMTYPE_COUNTER, "/PGM/R0/DynMapPage/SetSearchHits", STAMUNIT_OCCURENCES, "Set search hits.");
1629	STAM_REG(pVM, &pPGM->StatR0DynMapSetSearchMisses, STAMTYPE_COUNTER, "/PGM/R0/DynMapPage/SetSearchMisses", STAMUNIT_OCCURENCES, "Set search misses.");
1630	STAM_REG(pVM, &pPGM->StatR0DynMapHCPage, STAMTYPE_PROFILE, "/PGM/R0/DynMapPage/HCPage", STAMUNIT_TICKS_PER_CALL, "Calls to PGMDynMapHCPage (ring-0).");
1631	STAM_REG(pVM, &pPGM->StatR0DynMapPageHits0, STAMTYPE_COUNTER, "/PGM/R0/DynMapPage/Hits0", STAMUNIT_OCCURENCES, "Hits at iPage+0");
1632	STAM_REG(pVM, &pPGM->StatR0DynMapPageHits1, STAMTYPE_COUNTER, "/PGM/R0/DynMapPage/Hits1", STAMUNIT_OCCURENCES, "Hits at iPage+1");
1633	STAM_REG(pVM, &pPGM->StatR0DynMapPageHits2, STAMTYPE_COUNTER, "/PGM/R0/DynMapPage/Hits2", STAMUNIT_OCCURENCES, "Hits at iPage+2");
1634	STAM_REG(pVM, &pPGM->StatR0DynMapPageInvlPg, STAMTYPE_COUNTER, "/PGM/R0/DynMapPage/InvlPg", STAMUNIT_OCCURENCES, "invlpg count in pgmR0DynMapPageSlow.");
1635	STAM_REG(pVM, &pPGM->StatR0DynMapPageSlow, STAMTYPE_COUNTER, "/PGM/R0/DynMapPage/Slow", STAMUNIT_OCCURENCES, "Calls to pgmR0DynMapPageSlow - subtract this from pgmR0DynMapPage to get 1st level hits.");
1636	STAM_REG(pVM, &pPGM->StatR0DynMapPageSlowLoopHits, STAMTYPE_COUNTER, "/PGM/R0/DynMapPage/SlowLoopHits" , STAMUNIT_OCCURENCES, "Hits in the loop path.");
1637	STAM_REG(pVM, &pPGM->StatR0DynMapPageSlowLoopMisses, STAMTYPE_COUNTER, "/PGM/R0/DynMapPage/SlowLoopMisses", STAMUNIT_OCCURENCES, "Misses in the loop path. NonLoopMisses = Slow - SlowLoopHit - SlowLoopMisses");
1638	//STAM_REG(pVM, &pPGM->StatR0DynMapPageSlowLostHits, STAMTYPE_COUNTER, "/PGM/R0/DynMapPage/SlowLostHits", STAMUNIT_OCCURENCES, "Lost hits.");
1639	STAM_REG(pVM, &pPGM->StatR0DynMapSubsets, STAMTYPE_COUNTER, "/PGM/R0/Subsets", STAMUNIT_OCCURENCES, "Times PGMDynMapPushAutoSubset was called.");
1640	STAM_REG(pVM, &pPGM->StatR0DynMapPopFlushes, STAMTYPE_COUNTER, "/PGM/R0/SubsetPopFlushes", STAMUNIT_OCCURENCES, "Times PGMDynMapPopAutoSubset flushes the subset.");
1641	STAM_REG(pVM, &pPGM->aStatR0DynMapSetSize[0], STAMTYPE_COUNTER, "/PGM/R0/SetSize000..09", STAMUNIT_OCCURENCES, "00-09% filled");
1642	STAM_REG(pVM, &pPGM->aStatR0DynMapSetSize[1], STAMTYPE_COUNTER, "/PGM/R0/SetSize010..19", STAMUNIT_OCCURENCES, "10-19% filled");
1643	STAM_REG(pVM, &pPGM->aStatR0DynMapSetSize[2], STAMTYPE_COUNTER, "/PGM/R0/SetSize020..29", STAMUNIT_OCCURENCES, "20-29% filled");
1644	STAM_REG(pVM, &pPGM->aStatR0DynMapSetSize[3], STAMTYPE_COUNTER, "/PGM/R0/SetSize030..39", STAMUNIT_OCCURENCES, "30-39% filled");
1645	STAM_REG(pVM, &pPGM->aStatR0DynMapSetSize[4], STAMTYPE_COUNTER, "/PGM/R0/SetSize040..49", STAMUNIT_OCCURENCES, "40-49% filled");
1646	STAM_REG(pVM, &pPGM->aStatR0DynMapSetSize[5], STAMTYPE_COUNTER, "/PGM/R0/SetSize050..59", STAMUNIT_OCCURENCES, "50-59% filled");
1647	STAM_REG(pVM, &pPGM->aStatR0DynMapSetSize[6], STAMTYPE_COUNTER, "/PGM/R0/SetSize060..69", STAMUNIT_OCCURENCES, "60-69% filled");
1648	STAM_REG(pVM, &pPGM->aStatR0DynMapSetSize[7], STAMTYPE_COUNTER, "/PGM/R0/SetSize070..79", STAMUNIT_OCCURENCES, "70-79% filled");
1649	STAM_REG(pVM, &pPGM->aStatR0DynMapSetSize[8], STAMTYPE_COUNTER, "/PGM/R0/SetSize080..89", STAMUNIT_OCCURENCES, "80-89% filled");
1650	STAM_REG(pVM, &pPGM->aStatR0DynMapSetSize[9], STAMTYPE_COUNTER, "/PGM/R0/SetSize090..99", STAMUNIT_OCCURENCES, "90-99% filled");
1651	STAM_REG(pVM, &pPGM->aStatR0DynMapSetSize[10], STAMTYPE_COUNTER, "/PGM/R0/SetSize100", STAMUNIT_OCCURENCES, "100% filled");
1652
1653	/* GC only: */
1654	STAM_REG(pVM, &pPGM->StatRCDynMapCacheHits, STAMTYPE_COUNTER, "/PGM/RC/DynMapCache/Hits" , STAMUNIT_OCCURENCES, "Number of dynamic page mapping cache hits.");
1655	STAM_REG(pVM, &pPGM->StatRCDynMapCacheMisses, STAMTYPE_COUNTER, "/PGM/RC/DynMapCache/Misses" , STAMUNIT_OCCURENCES, "Number of dynamic page mapping cache misses.");
1656	STAM_REG(pVM, &pPGM->StatRCInvlPgConflict, STAMTYPE_COUNTER, "/PGM/RC/InvlPgConflict", STAMUNIT_OCCURENCES, "Number of times PGMInvalidatePage() detected a mapping conflict.");
1657	STAM_REG(pVM, &pPGM->StatRCInvlPgSyncMonCR3, STAMTYPE_COUNTER, "/PGM/RC/InvlPgSyncMonitorCR3", STAMUNIT_OCCURENCES, "Number of times PGMInvalidatePage() ran into PGM_SYNC_MONITOR_CR3.");
1658
1659	/* RZ only: */
1660	STAM_REG(pVM, &pPGM->StatRZTrap0e, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMTrap0eHandler() body.");
1661	STAM_REG(pVM, &pPGM->StatRZTrap0eTimeCheckPageFault, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time/CheckPageFault", STAMUNIT_TICKS_PER_CALL, "Profiling of checking for dirty/access emulation faults.");
1662	STAM_REG(pVM, &pPGM->StatRZTrap0eTimeSyncPT, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time/SyncPT", STAMUNIT_TICKS_PER_CALL, "Profiling of lazy page table syncing.");
1663	STAM_REG(pVM, &pPGM->StatRZTrap0eTimeMapping, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time/Mapping", STAMUNIT_TICKS_PER_CALL, "Profiling of checking virtual mappings.");
1664	STAM_REG(pVM, &pPGM->StatRZTrap0eTimeOutOfSync, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time/OutOfSync", STAMUNIT_TICKS_PER_CALL, "Profiling of out of sync page handling.");
1665	STAM_REG(pVM, &pPGM->StatRZTrap0eTimeHandlers, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time/Handlers", STAMUNIT_TICKS_PER_CALL, "Profiling of checking handlers.");
1666	STAM_REG(pVM, &pPGM->StatRZTrap0eTime2CSAM, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time2/CSAM", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is CSAM.");
1667	STAM_REG(pVM, &pPGM->StatRZTrap0eTime2DirtyAndAccessed, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time2/DirtyAndAccessedBits", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is dirty and/or accessed bit emulation.");
1668	STAM_REG(pVM, &pPGM->StatRZTrap0eTime2GuestTrap, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time2/GuestTrap", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is a guest trap.");
1669	STAM_REG(pVM, &pPGM->StatRZTrap0eTime2HndPhys, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time2/HandlerPhysical", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is a physical handler.");
1670	STAM_REG(pVM, &pPGM->StatRZTrap0eTime2HndVirt, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time2/HandlerVirtual", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is a virtual handler.");
1671	STAM_REG(pVM, &pPGM->StatRZTrap0eTime2HndUnhandled, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time2/HandlerUnhandled", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is access outside the monitored areas of a monitored page.");
1672	STAM_REG(pVM, &pPGM->StatRZTrap0eTime2Misc, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time2/Misc", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is not known.");
1673	STAM_REG(pVM, &pPGM->StatRZTrap0eTime2OutOfSync, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time2/OutOfSync", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is an out-of-sync page.");
1674	STAM_REG(pVM, &pPGM->StatRZTrap0eTime2OutOfSyncHndPhys, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time2/OutOfSyncHndPhys", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is an out-of-sync physical handler page.");
1675	STAM_REG(pVM, &pPGM->StatRZTrap0eTime2OutOfSyncHndVirt, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time2/OutOfSyncHndVirt", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is an out-of-sync virtual handler page.");
1676	STAM_REG(pVM, &pPGM->StatRZTrap0eTime2OutOfSyncHndObs, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time2/OutOfSyncObsHnd", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is an obsolete handler page.");
1677	STAM_REG(pVM, &pPGM->StatRZTrap0eTime2SyncPT, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time2/SyncPT", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is lazy syncing of a PT.");
1678	STAM_REG(pVM, &pPGM->StatRZTrap0eConflicts, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Conflicts", STAMUNIT_OCCURENCES, "The number of times #PF was caused by an undetected conflict.");
1679	STAM_REG(pVM, &pPGM->StatRZTrap0eHandlersMapping, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Handlers/Mapping", STAMUNIT_OCCURENCES, "Number of traps due to access handlers in mappings.");
1680	STAM_REG(pVM, &pPGM->StatRZTrap0eHandlersOutOfSync, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Handlers/OutOfSync", STAMUNIT_OCCURENCES, "Number of traps due to out-of-sync handled pages.");
1681	STAM_REG(pVM, &pPGM->StatRZTrap0eHandlersPhysical, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Handlers/Physical", STAMUNIT_OCCURENCES, "Number of traps due to physical access handlers.");
1682	STAM_REG(pVM, &pPGM->StatRZTrap0eHandlersVirtual, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Handlers/Virtual", STAMUNIT_OCCURENCES, "Number of traps due to virtual access handlers.");
1683	STAM_REG(pVM, &pPGM->StatRZTrap0eHandlersVirtualByPhys, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Handlers/VirtualByPhys", STAMUNIT_OCCURENCES, "Number of traps due to virtual access handlers by physical address.");
1684	STAM_REG(pVM, &pPGM->StatRZTrap0eHandlersVirtualUnmarked,STAMTYPE_COUNTER,"/PGM/RZ/Trap0e/Handlers/VirtualUnmarked",STAMUNIT_OCCURENCES, "Number of traps due to virtual access handlers by virtual address (without proper physical flags).");
1685	STAM_REG(pVM, &pPGM->StatRZTrap0eHandlersUnhandled, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Handlers/Unhandled", STAMUNIT_OCCURENCES, "Number of traps due to access outside range of monitored page(s).");
1686	STAM_REG(pVM, &pPGM->StatRZTrap0eHandlersInvalid, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Handlers/Invalid", STAMUNIT_OCCURENCES, "Number of traps due to access to invalid physical memory.");
1687	STAM_REG(pVM, &pPGM->StatRZTrap0eUSNotPresentRead, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Err/User/NPRead", STAMUNIT_OCCURENCES, "Number of user mode not present read page faults.");
1688	STAM_REG(pVM, &pPGM->StatRZTrap0eUSNotPresentWrite, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Err/User/NPWrite", STAMUNIT_OCCURENCES, "Number of user mode not present write page faults.");
1689	STAM_REG(pVM, &pPGM->StatRZTrap0eUSWrite, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Err/User/Write", STAMUNIT_OCCURENCES, "Number of user mode write page faults.");
1690	STAM_REG(pVM, &pPGM->StatRZTrap0eUSReserved, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Err/User/Reserved", STAMUNIT_OCCURENCES, "Number of user mode reserved bit page faults.");
1691	STAM_REG(pVM, &pPGM->StatRZTrap0eUSNXE, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Err/User/NXE", STAMUNIT_OCCURENCES, "Number of user mode NXE page faults.");
1692	STAM_REG(pVM, &pPGM->StatRZTrap0eUSRead, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Err/User/Read", STAMUNIT_OCCURENCES, "Number of user mode read page faults.");
1693	STAM_REG(pVM, &pPGM->StatRZTrap0eSVNotPresentRead, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Err/Supervisor/NPRead", STAMUNIT_OCCURENCES, "Number of supervisor mode not present read page faults.");
1694	STAM_REG(pVM, &pPGM->StatRZTrap0eSVNotPresentWrite, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Err/Supervisor/NPWrite", STAMUNIT_OCCURENCES, "Number of supervisor mode not present write page faults.");
1695	STAM_REG(pVM, &pPGM->StatRZTrap0eSVWrite, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Err/Supervisor/Write", STAMUNIT_OCCURENCES, "Number of supervisor mode write page faults.");
1696	STAM_REG(pVM, &pPGM->StatRZTrap0eSVReserved, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Err/Supervisor/Reserved", STAMUNIT_OCCURENCES, "Number of supervisor mode reserved bit page faults.");
1697	STAM_REG(pVM, &pPGM->StatRZTrap0eSNXE, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Err/Supervisor/NXE", STAMUNIT_OCCURENCES, "Number of supervisor mode NXE page faults.");
1698	STAM_REG(pVM, &pPGM->StatRZTrap0eGuestPF, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/GuestPF", STAMUNIT_OCCURENCES, "Number of real guest page faults.");
1699	STAM_REG(pVM, &pPGM->StatRZTrap0eGuestPFUnh, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/GuestPF/Unhandled", STAMUNIT_OCCURENCES, "Number of real guest page faults from the 'unhandled' case.");
1700	STAM_REG(pVM, &pPGM->StatRZTrap0eGuestPFMapping, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/GuestPF/InMapping", STAMUNIT_OCCURENCES, "Number of real guest page faults in a mapping.");
1701	STAM_REG(pVM, &pPGM->StatRZTrap0eWPEmulInRZ, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/WP/InRZ", STAMUNIT_OCCURENCES, "Number of guest page faults due to X86_CR0_WP emulation.");
1702	STAM_REG(pVM, &pPGM->StatRZTrap0eWPEmulToR3, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/WP/ToR3", STAMUNIT_OCCURENCES, "Number of guest page faults due to X86_CR0_WP emulation (forward to R3 for emulation).");
1703	for (i = 0; i < RT_ELEMENTS(pPGM->StatRZTrap0ePD); i++)
1704	STAMR3RegisterF(pVM, &pPGM->StatRZTrap0ePD[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
1705	"The number of traps in page directory n.", "/PGM/RZ/Trap0e/PD/%04X", i);
1706	STAM_REG(pVM, &pPGM->StatRZGuestCR3WriteHandled, STAMTYPE_COUNTER, "/PGM/RZ/CR3WriteHandled", STAMUNIT_OCCURENCES, "The number of times the Guest CR3 change was successfully handled.");
1707	STAM_REG(pVM, &pPGM->StatRZGuestCR3WriteUnhandled, STAMTYPE_COUNTER, "/PGM/RZ/CR3WriteUnhandled", STAMUNIT_OCCURENCES, "The number of times the Guest CR3 change was passed back to the recompiler.");
1708	STAM_REG(pVM, &pPGM->StatRZGuestCR3WriteConflict, STAMTYPE_COUNTER, "/PGM/RZ/CR3WriteConflict", STAMUNIT_OCCURENCES, "The number of times the Guest CR3 monitoring detected a conflict.");
1709	STAM_REG(pVM, &pPGM->StatRZGuestROMWriteHandled, STAMTYPE_COUNTER, "/PGM/RZ/ROMWriteHandled", STAMUNIT_OCCURENCES, "The number of times the Guest ROM change was successfully handled.");
1710	STAM_REG(pVM, &pPGM->StatRZGuestROMWriteUnhandled, STAMTYPE_COUNTER, "/PGM/RZ/ROMWriteUnhandled", STAMUNIT_OCCURENCES, "The number of times the Guest ROM change was passed back to the recompiler.");
1711
1712	/* HC only: */
1713
1714	/* RZ & R3: */
1715	STAM_REG(pVM, &pPGM->StatRZSyncCR3, STAMTYPE_PROFILE, "/PGM/RZ/SyncCR3", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMSyncCR3() body.");
1716	STAM_REG(pVM, &pPGM->StatRZSyncCR3Handlers, STAMTYPE_PROFILE, "/PGM/RZ/SyncCR3/Handlers", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMSyncCR3() update handler section.");
1717	STAM_REG(pVM, &pPGM->StatRZSyncCR3HandlerVirtualUpdate, STAMTYPE_PROFILE, "/PGM/RZ/SyncCR3/Handlers/VirtualUpdate", STAMUNIT_TICKS_PER_CALL, "Profiling of the virtual handler updates.");
1718	STAM_REG(pVM, &pPGM->StatRZSyncCR3HandlerVirtualReset, STAMTYPE_PROFILE, "/PGM/RZ/SyncCR3/Handlers/VirtualReset", STAMUNIT_TICKS_PER_CALL, "Profiling of the virtual handler resets.");
1719	STAM_REG(pVM, &pPGM->StatRZSyncCR3Global, STAMTYPE_COUNTER, "/PGM/RZ/SyncCR3/Global", STAMUNIT_OCCURENCES, "The number of global CR3 syncs.");
1720	STAM_REG(pVM, &pPGM->StatRZSyncCR3NotGlobal, STAMTYPE_COUNTER, "/PGM/RZ/SyncCR3/NotGlobal", STAMUNIT_OCCURENCES, "The number of non-global CR3 syncs.");
1721	STAM_REG(pVM, &pPGM->StatRZSyncCR3DstCacheHit, STAMTYPE_COUNTER, "/PGM/RZ/SyncCR3/DstChacheHit", STAMUNIT_OCCURENCES, "The number of times we got some kind of a cache hit.");
1722	STAM_REG(pVM, &pPGM->StatRZSyncCR3DstFreed, STAMTYPE_COUNTER, "/PGM/RZ/SyncCR3/DstFreed", STAMUNIT_OCCURENCES, "The number of times we've had to free a shadow entry.");
1723	STAM_REG(pVM, &pPGM->StatRZSyncCR3DstFreedSrcNP, STAMTYPE_COUNTER, "/PGM/RZ/SyncCR3/DstFreedSrcNP", STAMUNIT_OCCURENCES, "The number of times we've had to free a shadow entry for which the source entry was not present.");
1724	STAM_REG(pVM, &pPGM->StatRZSyncCR3DstNotPresent, STAMTYPE_COUNTER, "/PGM/RZ/SyncCR3/DstNotPresent", STAMUNIT_OCCURENCES, "The number of times we've encountered a not present shadow entry for a present guest entry.");
1725	STAM_REG(pVM, &pPGM->StatRZSyncCR3DstSkippedGlobalPD, STAMTYPE_COUNTER, "/PGM/RZ/SyncCR3/DstSkippedGlobalPD", STAMUNIT_OCCURENCES, "The number of times a global page directory wasn't flushed.");
1726	STAM_REG(pVM, &pPGM->StatRZSyncCR3DstSkippedGlobalPT, STAMTYPE_COUNTER, "/PGM/RZ/SyncCR3/DstSkippedGlobalPT", STAMUNIT_OCCURENCES, "The number of times a page table with only global entries wasn't flushed.");
1727	STAM_REG(pVM, &pPGM->StatRZSyncPT, STAMTYPE_PROFILE, "/PGM/RZ/SyncPT", STAMUNIT_TICKS_PER_CALL, "Profiling of the pfnSyncPT() body.");
1728	STAM_REG(pVM, &pPGM->StatRZSyncPTFailed, STAMTYPE_COUNTER, "/PGM/RZ/SyncPT/Failed", STAMUNIT_OCCURENCES, "The number of times pfnSyncPT() failed.");
1729	STAM_REG(pVM, &pPGM->StatRZSyncPT4K, STAMTYPE_COUNTER, "/PGM/RZ/SyncPT/4K", STAMUNIT_OCCURENCES, "Nr of 4K PT syncs");
1730	STAM_REG(pVM, &pPGM->StatRZSyncPT4M, STAMTYPE_COUNTER, "/PGM/RZ/SyncPT/4M", STAMUNIT_OCCURENCES, "Nr of 4M PT syncs");
1731	STAM_REG(pVM, &pPGM->StatRZSyncPagePDNAs, STAMTYPE_COUNTER, "/PGM/RZ/SyncPagePDNAs", STAMUNIT_OCCURENCES, "The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit.");
1732	STAM_REG(pVM, &pPGM->StatRZSyncPagePDOutOfSync, STAMTYPE_COUNTER, "/PGM/RZ/SyncPagePDOutOfSync", STAMUNIT_OCCURENCES, "The number of time we've encountered an out-of-sync PD in SyncPage.");
1733	STAM_REG(pVM, &pPGM->StatRZAccessedPage, STAMTYPE_COUNTER, "/PGM/RZ/AccessedPage", STAMUNIT_OCCURENCES, "The number of pages marked not present for accessed bit emulation.");
1734	STAM_REG(pVM, &pPGM->StatRZDirtyBitTracking, STAMTYPE_PROFILE, "/PGM/RZ/DirtyPage", STAMUNIT_TICKS_PER_CALL, "Profiling the dirty bit tracking in CheckPageFault().");
1735	STAM_REG(pVM, &pPGM->StatRZDirtyPage, STAMTYPE_COUNTER, "/PGM/RZ/DirtyPage/Mark", STAMUNIT_OCCURENCES, "The number of pages marked read-only for dirty bit tracking.");
1736	STAM_REG(pVM, &pPGM->StatRZDirtyPageBig, STAMTYPE_COUNTER, "/PGM/RZ/DirtyPage/MarkBig", STAMUNIT_OCCURENCES, "The number of 4MB pages marked read-only for dirty bit tracking.");
1737	STAM_REG(pVM, &pPGM->StatRZDirtyPageSkipped, STAMTYPE_COUNTER, "/PGM/RZ/DirtyPage/Skipped", STAMUNIT_OCCURENCES, "The number of pages already dirty or readonly.");
1738	STAM_REG(pVM, &pPGM->StatRZDirtyPageTrap, STAMTYPE_COUNTER, "/PGM/RZ/DirtyPage/Trap", STAMUNIT_OCCURENCES, "The number of traps generated for dirty bit tracking.");
1739	STAM_REG(pVM, &pPGM->StatRZDirtiedPage, STAMTYPE_COUNTER, "/PGM/RZ/DirtyPage/SetDirty", STAMUNIT_OCCURENCES, "The number of pages marked dirty because of write accesses.");
1740	STAM_REG(pVM, &pPGM->StatRZDirtyTrackRealPF, STAMTYPE_COUNTER, "/PGM/RZ/DirtyPage/RealPF", STAMUNIT_OCCURENCES, "The number of real pages faults during dirty bit tracking.");
1741	STAM_REG(pVM, &pPGM->StatRZPageAlreadyDirty, STAMTYPE_COUNTER, "/PGM/RZ/DirtyPage/AlreadySet", STAMUNIT_OCCURENCES, "The number of pages already marked dirty because of write accesses.");
1742	STAM_REG(pVM, &pPGM->StatRZInvalidatePage, STAMTYPE_PROFILE, "/PGM/RZ/InvalidatePage", STAMUNIT_TICKS_PER_CALL, "PGMInvalidatePage() profiling.");
1743	STAM_REG(pVM, &pPGM->StatRZInvalidatePage4KBPages, STAMTYPE_COUNTER, "/PGM/RZ/InvalidatePage/4KBPages", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was called for a 4KB page.");
1744	STAM_REG(pVM, &pPGM->StatRZInvalidatePage4MBPages, STAMTYPE_COUNTER, "/PGM/RZ/InvalidatePage/4MBPages", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was called for a 4MB page.");
1745	STAM_REG(pVM, &pPGM->StatRZInvalidatePage4MBPagesSkip, STAMTYPE_COUNTER, "/PGM/RZ/InvalidatePage/4MBPagesSkip",STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() skipped a 4MB page.");
1746	STAM_REG(pVM, &pPGM->StatRZInvalidatePagePDMappings, STAMTYPE_COUNTER, "/PGM/RZ/InvalidatePage/PDMappings", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict).");
1747	STAM_REG(pVM, &pPGM->StatRZInvalidatePagePDNAs, STAMTYPE_COUNTER, "/PGM/RZ/InvalidatePage/PDNAs", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was called for a not accessed page directory.");
1748	STAM_REG(pVM, &pPGM->StatRZInvalidatePagePDNPs, STAMTYPE_COUNTER, "/PGM/RZ/InvalidatePage/PDNPs", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was called for a not present page directory.");
1749	STAM_REG(pVM, &pPGM->StatRZInvalidatePagePDOutOfSync, STAMTYPE_COUNTER, "/PGM/RZ/InvalidatePage/PDOutOfSync", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was called for an out of sync page directory.");
1750	STAM_REG(pVM, &pPGM->StatRZInvalidatePageSkipped, STAMTYPE_COUNTER, "/PGM/RZ/InvalidatePage/Skipped", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3.");
1751	STAM_REG(pVM, &pPGM->StatRZVirtHandlerSearchByPhys, STAMTYPE_PROFILE, "/PGM/RZ/VirtHandlerSearchByPhys", STAMUNIT_TICKS_PER_CALL, "Profiling of pgmHandlerVirtualFindByPhysAddr.");
1752	STAM_REG(pVM, &pPGM->StatRZPhysHandlerReset, STAMTYPE_COUNTER, "/PGM/RZ/PhysHandlerReset", STAMUNIT_OCCURENCES, "The number of times PGMHandlerPhysicalReset is called.");
1753	STAM_REG(pVM, &pPGM->StatRZPageOutOfSyncSupervisor, STAMTYPE_COUNTER, "/PGM/RZ/OutOfSync/SuperVisor", STAMUNIT_OCCURENCES, "Number of traps due to pages out of sync and times VerifyAccessSyncPage calls SyncPage.");
1754	STAM_REG(pVM, &pPGM->StatRZPageOutOfSyncUser, STAMTYPE_COUNTER, "/PGM/RZ/OutOfSync/User", STAMUNIT_OCCURENCES, "Number of traps due to pages out of sync and times VerifyAccessSyncPage calls SyncPage.");
1755	STAM_REG(pVM, &pPGM->StatRZPrefetch, STAMTYPE_PROFILE, "/PGM/RZ/Prefetch", STAMUNIT_TICKS_PER_CALL, "PGMPrefetchPage profiling.");
1756	STAM_REG(pVM, &pPGM->StatRZChunkR3MapTlbHits, STAMTYPE_COUNTER, "/PGM/ChunkR3Map/TlbHitsRZ", STAMUNIT_OCCURENCES, "TLB hits.");
1757	STAM_REG(pVM, &pPGM->StatRZChunkR3MapTlbMisses, STAMTYPE_COUNTER, "/PGM/ChunkR3Map/TlbMissesRZ", STAMUNIT_OCCURENCES, "TLB misses.");
1758	STAM_REG(pVM, &pPGM->StatRZPageMapTlbHits, STAMTYPE_COUNTER, "/PGM/RZ/Page/MapTlbHits", STAMUNIT_OCCURENCES, "TLB hits.");
1759	STAM_REG(pVM, &pPGM->StatRZPageMapTlbMisses, STAMTYPE_COUNTER, "/PGM/RZ/Page/MapTlbMisses", STAMUNIT_OCCURENCES, "TLB misses.");
1760	STAM_REG(pVM, &pPGM->StatRZPageReplaceShared, STAMTYPE_COUNTER, "/PGM/RZ/Page/ReplacedShared", STAMUNIT_OCCURENCES, "Times a shared page was replaced.");
1761	STAM_REG(pVM, &pPGM->StatRZPageReplaceZero, STAMTYPE_COUNTER, "/PGM/RZ/Page/ReplacedZero", STAMUNIT_OCCURENCES, "Times the zero page was replaced.");
1762	/// @todo STAM_REG(pVM, &pPGM->StatRZPageHandyAllocs, STAMTYPE_COUNTER, "/PGM/RZ/Page/HandyAllocs", STAMUNIT_OCCURENCES, "Number of times we've allocated more handy pages.");
1763	STAM_REG(pVM, &pPGM->StatRZFlushTLB, STAMTYPE_PROFILE, "/PGM/RZ/FlushTLB", STAMUNIT_OCCURENCES, "Profiling of the PGMFlushTLB() body.");
1764	STAM_REG(pVM, &pPGM->StatRZFlushTLBNewCR3, STAMTYPE_COUNTER, "/PGM/RZ/FlushTLB/NewCR3", STAMUNIT_OCCURENCES, "The number of times PGMFlushTLB was called with a new CR3, non-global. (switch)");
1765	STAM_REG(pVM, &pPGM->StatRZFlushTLBNewCR3Global, STAMTYPE_COUNTER, "/PGM/RZ/FlushTLB/NewCR3Global", STAMUNIT_OCCURENCES, "The number of times PGMFlushTLB was called with a new CR3, global. (switch)");
1766	STAM_REG(pVM, &pPGM->StatRZFlushTLBSameCR3, STAMTYPE_COUNTER, "/PGM/RZ/FlushTLB/SameCR3", STAMUNIT_OCCURENCES, "The number of times PGMFlushTLB was called with the same CR3, non-global. (flush)");
1767	STAM_REG(pVM, &pPGM->StatRZFlushTLBSameCR3Global, STAMTYPE_COUNTER, "/PGM/RZ/FlushTLB/SameCR3Global", STAMUNIT_OCCURENCES, "The number of times PGMFlushTLB was called with the same CR3, global. (flush)");
1768	STAM_REG(pVM, &pPGM->StatRZGstModifyPage, STAMTYPE_PROFILE, "/PGM/RZ/GstModifyPage", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMGstModifyPage() body.");
1769
1770	STAM_REG(pVM, &pPGM->StatR3SyncCR3, STAMTYPE_PROFILE, "/PGM/R3/SyncCR3", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMSyncCR3() body.");
1771	STAM_REG(pVM, &pPGM->StatR3SyncCR3Handlers, STAMTYPE_PROFILE, "/PGM/R3/SyncCR3/Handlers", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMSyncCR3() update handler section.");
1772	STAM_REG(pVM, &pPGM->StatR3SyncCR3HandlerVirtualUpdate, STAMTYPE_PROFILE, "/PGM/R3/SyncCR3/Handlers/VirtualUpdate", STAMUNIT_TICKS_PER_CALL, "Profiling of the virtual handler updates.");
1773	STAM_REG(pVM, &pPGM->StatR3SyncCR3HandlerVirtualReset, STAMTYPE_PROFILE, "/PGM/R3/SyncCR3/Handlers/VirtualReset", STAMUNIT_TICKS_PER_CALL, "Profiling of the virtual handler resets.");
1774	STAM_REG(pVM, &pPGM->StatR3SyncCR3Global, STAMTYPE_COUNTER, "/PGM/R3/SyncCR3/Global", STAMUNIT_OCCURENCES, "The number of global CR3 syncs.");
1775	STAM_REG(pVM, &pPGM->StatR3SyncCR3NotGlobal, STAMTYPE_COUNTER, "/PGM/R3/SyncCR3/NotGlobal", STAMUNIT_OCCURENCES, "The number of non-global CR3 syncs.");
1776	STAM_REG(pVM, &pPGM->StatR3SyncCR3DstCacheHit, STAMTYPE_COUNTER, "/PGM/R3/SyncCR3/DstChacheHit", STAMUNIT_OCCURENCES, "The number of times we got some kind of a cache hit.");
1777	STAM_REG(pVM, &pPGM->StatR3SyncCR3DstFreed, STAMTYPE_COUNTER, "/PGM/R3/SyncCR3/DstFreed", STAMUNIT_OCCURENCES, "The number of times we've had to free a shadow entry.");
1778	STAM_REG(pVM, &pPGM->StatR3SyncCR3DstFreedSrcNP, STAMTYPE_COUNTER, "/PGM/R3/SyncCR3/DstFreedSrcNP", STAMUNIT_OCCURENCES, "The number of times we've had to free a shadow entry for which the source entry was not present.");
1779	STAM_REG(pVM, &pPGM->StatR3SyncCR3DstNotPresent, STAMTYPE_COUNTER, "/PGM/R3/SyncCR3/DstNotPresent", STAMUNIT_OCCURENCES, "The number of times we've encountered a not present shadow entry for a present guest entry.");
1780	STAM_REG(pVM, &pPGM->StatR3SyncCR3DstSkippedGlobalPD, STAMTYPE_COUNTER, "/PGM/R3/SyncCR3/DstSkippedGlobalPD", STAMUNIT_OCCURENCES, "The number of times a global page directory wasn't flushed.");
1781	STAM_REG(pVM, &pPGM->StatR3SyncCR3DstSkippedGlobalPT, STAMTYPE_COUNTER, "/PGM/R3/SyncCR3/DstSkippedGlobalPT", STAMUNIT_OCCURENCES, "The number of times a page table with only global entries wasn't flushed.");
1782	STAM_REG(pVM, &pPGM->StatR3SyncPT, STAMTYPE_PROFILE, "/PGM/R3/SyncPT", STAMUNIT_TICKS_PER_CALL, "Profiling of the pfnSyncPT() body.");
1783	STAM_REG(pVM, &pPGM->StatR3SyncPTFailed, STAMTYPE_COUNTER, "/PGM/R3/SyncPT/Failed", STAMUNIT_OCCURENCES, "The number of times pfnSyncPT() failed.");
1784	STAM_REG(pVM, &pPGM->StatR3SyncPT4K, STAMTYPE_COUNTER, "/PGM/R3/SyncPT/4K", STAMUNIT_OCCURENCES, "Nr of 4K PT syncs");
1785	STAM_REG(pVM, &pPGM->StatR3SyncPT4M, STAMTYPE_COUNTER, "/PGM/R3/SyncPT/4M", STAMUNIT_OCCURENCES, "Nr of 4M PT syncs");
1786	STAM_REG(pVM, &pPGM->StatR3SyncPagePDNAs, STAMTYPE_COUNTER, "/PGM/R3/SyncPagePDNAs", STAMUNIT_OCCURENCES, "The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit.");
1787	STAM_REG(pVM, &pPGM->StatR3SyncPagePDOutOfSync, STAMTYPE_COUNTER, "/PGM/R3/SyncPagePDOutOfSync", STAMUNIT_OCCURENCES, "The number of time we've encountered an out-of-sync PD in SyncPage.");
1788	STAM_REG(pVM, &pPGM->StatR3AccessedPage, STAMTYPE_COUNTER, "/PGM/R3/AccessedPage", STAMUNIT_OCCURENCES, "The number of pages marked not present for accessed bit emulation.");
1789	STAM_REG(pVM, &pPGM->StatR3DirtyBitTracking, STAMTYPE_PROFILE, "/PGM/R3/DirtyPage", STAMUNIT_TICKS_PER_CALL, "Profiling the dirty bit tracking in CheckPageFault().");
1790	STAM_REG(pVM, &pPGM->StatR3DirtyPage, STAMTYPE_COUNTER, "/PGM/R3/DirtyPage/Mark", STAMUNIT_OCCURENCES, "The number of pages marked read-only for dirty bit tracking.");
1791	STAM_REG(pVM, &pPGM->StatR3DirtyPageBig, STAMTYPE_COUNTER, "/PGM/R3/DirtyPage/MarkBig", STAMUNIT_OCCURENCES, "The number of 4MB pages marked read-only for dirty bit tracking.");
1792	STAM_REG(pVM, &pPGM->StatR3DirtyPageSkipped, STAMTYPE_COUNTER, "/PGM/R3/DirtyPage/Skipped", STAMUNIT_OCCURENCES, "The number of pages already dirty or readonly.");
1793	STAM_REG(pVM, &pPGM->StatR3DirtyPageTrap, STAMTYPE_COUNTER, "/PGM/R3/DirtyPage/Trap", STAMUNIT_OCCURENCES, "The number of traps generated for dirty bit tracking.");
1794	STAM_REG(pVM, &pPGM->StatR3DirtiedPage, STAMTYPE_COUNTER, "/PGM/R3/DirtyPage/SetDirty", STAMUNIT_OCCURENCES, "The number of pages marked dirty because of write accesses.");
1795	STAM_REG(pVM, &pPGM->StatR3DirtyTrackRealPF, STAMTYPE_COUNTER, "/PGM/R3/DirtyPage/RealPF", STAMUNIT_OCCURENCES, "The number of real pages faults during dirty bit tracking.");
1796	STAM_REG(pVM, &pPGM->StatR3PageAlreadyDirty, STAMTYPE_COUNTER, "/PGM/R3/DirtyPage/AlreadySet", STAMUNIT_OCCURENCES, "The number of pages already marked dirty because of write accesses.");
1797	STAM_REG(pVM, &pPGM->StatR3InvalidatePage, STAMTYPE_PROFILE, "/PGM/R3/InvalidatePage", STAMUNIT_TICKS_PER_CALL, "PGMInvalidatePage() profiling.");
1798	STAM_REG(pVM, &pPGM->StatR3InvalidatePage4KBPages, STAMTYPE_COUNTER, "/PGM/R3/InvalidatePage/4KBPages", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was called for a 4KB page.");
1799	STAM_REG(pVM, &pPGM->StatR3InvalidatePage4MBPages, STAMTYPE_COUNTER, "/PGM/R3/InvalidatePage/4MBPages", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was called for a 4MB page.");
1800	STAM_REG(pVM, &pPGM->StatR3InvalidatePage4MBPagesSkip, STAMTYPE_COUNTER, "/PGM/R3/InvalidatePage/4MBPagesSkip",STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() skipped a 4MB page.");
1801	STAM_REG(pVM, &pPGM->StatR3InvalidatePagePDMappings, STAMTYPE_COUNTER, "/PGM/R3/InvalidatePage/PDMappings", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict).");
1802	STAM_REG(pVM, &pPGM->StatR3InvalidatePagePDNAs, STAMTYPE_COUNTER, "/PGM/R3/InvalidatePage/PDNAs", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was called for a not accessed page directory.");
1803	STAM_REG(pVM, &pPGM->StatR3InvalidatePagePDNPs, STAMTYPE_COUNTER, "/PGM/R3/InvalidatePage/PDNPs", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was called for a not present page directory.");
1804	STAM_REG(pVM, &pPGM->StatR3InvalidatePagePDOutOfSync, STAMTYPE_COUNTER, "/PGM/R3/InvalidatePage/PDOutOfSync", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was called for an out of sync page directory.");
1805	STAM_REG(pVM, &pPGM->StatR3InvalidatePageSkipped, STAMTYPE_COUNTER, "/PGM/R3/InvalidatePage/Skipped", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3.");
1806	STAM_REG(pVM, &pPGM->StatR3VirtHandlerSearchByPhys, STAMTYPE_PROFILE, "/PGM/R3/VirtHandlerSearchByPhys", STAMUNIT_TICKS_PER_CALL, "Profiling of pgmHandlerVirtualFindByPhysAddr.");
1807	STAM_REG(pVM, &pPGM->StatR3PhysHandlerReset, STAMTYPE_COUNTER, "/PGM/R3/PhysHandlerReset", STAMUNIT_OCCURENCES, "The number of times PGMHandlerPhysicalReset is called.");
1808	STAM_REG(pVM, &pPGM->StatR3PageOutOfSyncSupervisor, STAMTYPE_COUNTER, "/PGM/R3/OutOfSync/SuperVisor", STAMUNIT_OCCURENCES, "Number of traps due to pages out of sync and times VerifyAccessSyncPage calls SyncPage.");
1809	STAM_REG(pVM, &pPGM->StatR3PageOutOfSyncUser, STAMTYPE_COUNTER, "/PGM/R3/OutOfSync/User", STAMUNIT_OCCURENCES, "Number of traps due to pages out of sync and times VerifyAccessSyncPage calls SyncPage.");
1810	STAM_REG(pVM, &pPGM->StatR3Prefetch, STAMTYPE_PROFILE, "/PGM/R3/Prefetch", STAMUNIT_TICKS_PER_CALL, "PGMPrefetchPage profiling.");
1811	STAM_REG(pVM, &pPGM->StatR3ChunkR3MapTlbHits, STAMTYPE_COUNTER, "/PGM/ChunkR3Map/TlbHitsR3", STAMUNIT_OCCURENCES, "TLB hits.");
1812	STAM_REG(pVM, &pPGM->StatR3ChunkR3MapTlbMisses, STAMTYPE_COUNTER, "/PGM/ChunkR3Map/TlbMissesR3", STAMUNIT_OCCURENCES, "TLB misses.");
1813	STAM_REG(pVM, &pPGM->StatR3PageMapTlbHits, STAMTYPE_COUNTER, "/PGM/R3/Page/MapTlbHits", STAMUNIT_OCCURENCES, "TLB hits.");
1814	STAM_REG(pVM, &pPGM->StatR3PageMapTlbMisses, STAMTYPE_COUNTER, "/PGM/R3/Page/MapTlbMisses", STAMUNIT_OCCURENCES, "TLB misses.");
1815	STAM_REG(pVM, &pPGM->StatR3PageReplaceShared, STAMTYPE_COUNTER, "/PGM/R3/Page/ReplacedShared", STAMUNIT_OCCURENCES, "Times a shared page was replaced.");
1816	STAM_REG(pVM, &pPGM->StatR3PageReplaceZero, STAMTYPE_COUNTER, "/PGM/R3/Page/ReplacedZero", STAMUNIT_OCCURENCES, "Times the zero page was replaced.");
1817	/// @todo STAM_REG(pVM, &pPGM->StatR3PageHandyAllocs, STAMTYPE_COUNTER, "/PGM/R3/Page/HandyAllocs", STAMUNIT_OCCURENCES, "Number of times we've allocated more handy pages.");
1818	STAM_REG(pVM, &pPGM->StatR3FlushTLB, STAMTYPE_PROFILE, "/PGM/R3/FlushTLB", STAMUNIT_OCCURENCES, "Profiling of the PGMFlushTLB() body.");
1819	STAM_REG(pVM, &pPGM->StatR3FlushTLBNewCR3, STAMTYPE_COUNTER, "/PGM/R3/FlushTLB/NewCR3", STAMUNIT_OCCURENCES, "The number of times PGMFlushTLB was called with a new CR3, non-global. (switch)");
1820	STAM_REG(pVM, &pPGM->StatR3FlushTLBNewCR3Global, STAMTYPE_COUNTER, "/PGM/R3/FlushTLB/NewCR3Global", STAMUNIT_OCCURENCES, "The number of times PGMFlushTLB was called with a new CR3, global. (switch)");
1821	STAM_REG(pVM, &pPGM->StatR3FlushTLBSameCR3, STAMTYPE_COUNTER, "/PGM/R3/FlushTLB/SameCR3", STAMUNIT_OCCURENCES, "The number of times PGMFlushTLB was called with the same CR3, non-global. (flush)");
1822	STAM_REG(pVM, &pPGM->StatR3FlushTLBSameCR3Global, STAMTYPE_COUNTER, "/PGM/R3/FlushTLB/SameCR3Global", STAMUNIT_OCCURENCES, "The number of times PGMFlushTLB was called with the same CR3, global. (flush)");
1823	STAM_REG(pVM, &pPGM->StatR3GstModifyPage, STAMTYPE_PROFILE, "/PGM/R3/GstModifyPage", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMGstModifyPage() body.");
1824
1825	}
1826	#endif /* VBOX_WITH_STATISTICS */
1827
1828
1829	/**
1830	* Init the PGM bits that rely on VMMR0 and MM to be fully initialized.
1831	*
1832	* The dynamic mapping area will also be allocated and initialized at this
1833	* time. We could allocate it during PGMR3Init of course, but the mapping
1834	* wouldn't be allocated at that time preventing us from setting up the
1835	* page table entries with the dummy page.
1836	*
1837	* @returns VBox status code.
1838	* @param pVM VM handle.
1839	*/
1840	VMMR3DECL(int) PGMR3InitDynMap(PVM pVM)
1841	{
1842	RTGCPTR GCPtr;
1843	int rc;
1844
1845	#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
1846	/*
1847	* Reserve space for mapping the paging pages into guest context.
1848	*/
1849	rc = MMR3HyperReserve(pVM, PAGE_SIZE * (2 + RT_ELEMENTS(pVM->pgm.s.apShwPaePDsR3) + 1 + 2 + 2), "Paging", &GCPtr);
1850	AssertRCReturn(rc, rc);
1851	pVM->pgm.s.pShw32BitPdRC = GCPtr;
1852	MMR3HyperReserve(pVM, PAGE_SIZE, "fence", NULL);
1853	#endif
1854
1855	/*
1856	* Reserve space for the dynamic mappings.
1857	*/
1858	rc = MMR3HyperReserve(pVM, MM_HYPER_DYNAMIC_SIZE, "Dynamic mapping", &GCPtr);
1859	if (RT_SUCCESS(rc))
1860	pVM->pgm.s.pbDynPageMapBaseGC = GCPtr;
1861
1862	if ( RT_SUCCESS(rc)
1863	&& (pVM->pgm.s.pbDynPageMapBaseGC >> X86_PD_PAE_SHIFT) != ((pVM->pgm.s.pbDynPageMapBaseGC + MM_HYPER_DYNAMIC_SIZE - 1) >> X86_PD_PAE_SHIFT))
1864	{
1865	rc = MMR3HyperReserve(pVM, MM_HYPER_DYNAMIC_SIZE, "Dynamic mapping not crossing", &GCPtr);
1866	if (RT_SUCCESS(rc))
1867	pVM->pgm.s.pbDynPageMapBaseGC = GCPtr;
1868	}
1869	if (RT_SUCCESS(rc))
1870	{
1871	AssertRelease((pVM->pgm.s.pbDynPageMapBaseGC >> X86_PD_PAE_SHIFT) == ((pVM->pgm.s.pbDynPageMapBaseGC + MM_HYPER_DYNAMIC_SIZE - 1) >> X86_PD_PAE_SHIFT));
1872	MMR3HyperReserve(pVM, PAGE_SIZE, "fence", NULL);
1873	}
1874	return rc;
1875	}
1876
1877
1878	/**
1879	* Ring-3 init finalizing.
1880	*
1881	* @returns VBox status code.
1882	* @param pVM The VM handle.
1883	*/
1884	VMMR3DECL(int) PGMR3InitFinalize(PVM pVM)
1885	{
1886	int rc;
1887
1888	#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
1889	/*
1890	* Map the paging pages into the guest context.
1891	*/
1892	RTGCPTR GCPtr = pVM->pgm.s.pShw32BitPdRC;
1893	AssertReleaseReturn(GCPtr, VERR_INTERNAL_ERROR);
1894
1895	rc = PGMMap(pVM, GCPtr, pVM->pgm.s.HCPhysShw32BitPD, PAGE_SIZE, 0);
1896	AssertRCReturn(rc, rc);
1897	pVM->pgm.s.pShw32BitPdRC = GCPtr;
1898	GCPtr += PAGE_SIZE;
1899	GCPtr += PAGE_SIZE; /* reserved page */
1900
1901	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.apShwPaePDsR3); i++)
1902	{
1903	rc = PGMMap(pVM, GCPtr, pVM->pgm.s.aHCPhysPaePDs[i], PAGE_SIZE, 0);
1904	AssertRCReturn(rc, rc);
1905	pVM->pgm.s.apShwPaePDsRC[i] = GCPtr;
1906	GCPtr += PAGE_SIZE;
1907	}
1908	/* A bit of paranoia is justified. */
1909	AssertRelease(pVM->pgm.s.apShwPaePDsRC[0] + PAGE_SIZE == pVM->pgm.s.apShwPaePDsRC[1]);
1910	AssertRelease(pVM->pgm.s.apShwPaePDsRC[1] + PAGE_SIZE == pVM->pgm.s.apShwPaePDsRC[2]);
1911	AssertRelease(pVM->pgm.s.apShwPaePDsRC[2] + PAGE_SIZE == pVM->pgm.s.apShwPaePDsRC[3]);
1912	GCPtr += PAGE_SIZE; /* reserved page */
1913
1914	rc = PGMMap(pVM, GCPtr, pVM->pgm.s.HCPhysShwPaePdpt, PAGE_SIZE, 0);
1915	AssertRCReturn(rc, rc);
1916	pVM->pgm.s.pShwPaePdptRC = GCPtr;
1917	GCPtr += PAGE_SIZE;
1918	GCPtr += PAGE_SIZE; /* reserved page */
1919	#endif
1920
1921	/*
1922	* Reserve space for the dynamic mappings.
1923	* Initialize the dynamic mapping pages with dummy pages to simply the cache.
1924	*/
1925	/* get the pointer to the page table entries. */
1926	PPGMMAPPING pMapping = pgmGetMapping(pVM, pVM->pgm.s.pbDynPageMapBaseGC);
1927	AssertRelease(pMapping);
1928	const uintptr_t off = pVM->pgm.s.pbDynPageMapBaseGC - pMapping->GCPtr;
1929	const unsigned iPT = off >> X86_PD_SHIFT;
1930	const unsigned iPG = (off >> X86_PT_SHIFT) & X86_PT_MASK;
1931	pVM->pgm.s.paDynPageMap32BitPTEsGC = pMapping->aPTs[iPT].pPTRC + iPG * sizeof(pMapping->aPTs[0].pPTR3->a[0]);
1932	pVM->pgm.s.paDynPageMapPaePTEsGC = pMapping->aPTs[iPT].paPaePTsRC + iPG * sizeof(pMapping->aPTs[0].paPaePTsR3->a[0]);
1933
1934	/* init cache */
1935	RTHCPHYS HCPhysDummy = MMR3PageDummyHCPhys(pVM);
1936	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.aHCPhysDynPageMapCache); i++)
1937	pVM->pgm.s.aHCPhysDynPageMapCache[i] = HCPhysDummy;
1938
1939	for (unsigned i = 0; i < MM_HYPER_DYNAMIC_SIZE; i += PAGE_SIZE)
1940	{
1941	rc = PGMMap(pVM, pVM->pgm.s.pbDynPageMapBaseGC + i, HCPhysDummy, PAGE_SIZE, 0);
1942	AssertRCReturn(rc, rc);
1943	}
1944
1945	/*
1946	* Note that AMD uses all the 8 reserved bits for the address (so 40 bits in total);
1947	* Intel only goes up to 36 bits, so we stick to 36 as well.
1948	*/
1949	/** @todo How to test for the 40 bits support? Long mode seems to be the test criterium. */
1950	uint32_t u32Dummy, u32Features;
1951	CPUMGetGuestCpuId(pVM, 1, &u32Dummy, &u32Dummy, &u32Dummy, &u32Features);
1952
1953	if (u32Features & X86_CPUID_FEATURE_EDX_PSE36)
1954	pVM->pgm.s.GCPhys4MBPSEMask = RT_BIT_64(36) - 1;
1955	else
1956	pVM->pgm.s.GCPhys4MBPSEMask = RT_BIT_64(32) - 1;
1957
1958	LogRel(("PGMR3InitFinalize: 4 MB PSE mask %RGp\n", pVM->pgm.s.GCPhys4MBPSEMask));
1959
1960	return rc;
1961	}
1962
1963
1964	/**
1965	* Applies relocations to data and code managed by this component.
1966	*
1967	* This function will be called at init and whenever the VMM need to relocate it
1968	* self inside the GC.
1969	*
1970	* @param pVM The VM.
1971	* @param offDelta Relocation delta relative to old location.
1972	*/
1973	VMMR3DECL(void) PGMR3Relocate(PVM pVM, RTGCINTPTR offDelta)
1974	{
1975	LogFlow(("PGMR3Relocate\n"));
1976
1977	/*
1978	* Paging stuff.
1979	*/
1980	pVM->pgm.s.GCPtrCR3Mapping += offDelta;
1981	/** @todo move this into shadow and guest specific relocation functions. */
1982	#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
1983	AssertMsg(pVM->pgm.s.pShwNestedRootR3, ("Init order, no relocation before paging is initialized!\n"));
1984	#else
1985	AssertMsg(pVM->pgm.s.pShw32BitPdR3, ("Init order, no relocation before paging is initialized!\n"));
1986	pVM->pgm.s.pShw32BitPdRC += offDelta;
1987	#endif
1988	pVM->pgm.s.pGst32BitPdRC += offDelta;
1989	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.apGstPaePDsRC); i++)
1990	{
1991	#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
1992	AssertCompile(RT_ELEMENTS(pVM->pgm.s.apShwPaePDsRC) == RT_ELEMENTS(pVM->pgm.s.apGstPaePDsRC));
1993	pVM->pgm.s.apShwPaePDsRC[i] += offDelta;
1994	#endif
1995	pVM->pgm.s.apGstPaePDsRC[i] += offDelta;
1996	}
1997	pVM->pgm.s.pGstPaePdptRC += offDelta;
1998	#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
1999	pVM->pgm.s.pShwPaePdptRC += offDelta;
2000	#endif
2001
2002	pgmR3ModeDataInit(pVM, true /* resolve GC/R0 symbols */);
2003	pgmR3ModeDataSwitch(pVM, pVM->pgm.s.enmShadowMode, pVM->pgm.s.enmGuestMode);
2004
2005	PGM_SHW_PFN(Relocate, pVM)(pVM, offDelta);
2006	PGM_GST_PFN(Relocate, pVM)(pVM, offDelta);
2007	PGM_BTH_PFN(Relocate, pVM)(pVM, offDelta);
2008
2009	/*
2010	* Trees.
2011	*/
2012	pVM->pgm.s.pTreesRC = MMHyperR3ToRC(pVM, pVM->pgm.s.pTreesR3);
2013
2014	/*
2015	* Ram ranges.
2016	*/
2017	if (pVM->pgm.s.pRamRangesR3)
2018	{
2019	pVM->pgm.s.pRamRangesRC = MMHyperR3ToRC(pVM, pVM->pgm.s.pRamRangesR3);
2020	for (PPGMRAMRANGE pCur = pVM->pgm.s.pRamRangesR3; pCur->pNextR3; pCur = pCur->pNextR3)
2021	pCur->pNextRC = MMHyperR3ToRC(pVM, pCur->pNextR3);
2022	}
2023
2024	/*
2025	* Update the two page directories with all page table mappings.
2026	* (One or more of them have changed, that's why we're here.)
2027	*/
2028	pVM->pgm.s.pMappingsRC = MMHyperR3ToRC(pVM, pVM->pgm.s.pMappingsR3);
2029	for (PPGMMAPPING pCur = pVM->pgm.s.pMappingsR3; pCur->pNextR3; pCur = pCur->pNextR3)
2030	pCur->pNextRC = MMHyperR3ToRC(pVM, pCur->pNextR3);
2031
2032	/* Relocate GC addresses of Page Tables. */
2033	for (PPGMMAPPING pCur = pVM->pgm.s.pMappingsR3; pCur; pCur = pCur->pNextR3)
2034	{
2035	for (RTHCUINT i = 0; i < pCur->cPTs; i++)
2036	{
2037	pCur->aPTs[i].pPTRC = MMHyperR3ToRC(pVM, pCur->aPTs[i].pPTR3);
2038	pCur->aPTs[i].paPaePTsRC = MMHyperR3ToRC(pVM, pCur->aPTs[i].paPaePTsR3);
2039	}
2040	}
2041
2042	/*
2043	* Dynamic page mapping area.
2044	*/
2045	pVM->pgm.s.paDynPageMap32BitPTEsGC += offDelta;
2046	pVM->pgm.s.paDynPageMapPaePTEsGC += offDelta;
2047	pVM->pgm.s.pbDynPageMapBaseGC += offDelta;
2048
2049	/*
2050	* The Zero page.
2051	*/
2052	pVM->pgm.s.pvZeroPgR0 = MMHyperR3ToR0(pVM, pVM->pgm.s.pvZeroPgR3);
2053	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
2054	AssertRelease(pVM->pgm.s.pvZeroPgR0 != NIL_RTR0PTR \|\| !VMMIsHwVirtExtForced(pVM));
2055	#else
2056	AssertRelease(pVM->pgm.s.pvZeroPgR0 != NIL_RTR0PTR);
2057	#endif
2058
2059	/*
2060	* Physical and virtual handlers.
2061	*/
2062	RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysHandlers, true, pgmR3RelocatePhysHandler, &offDelta);
2063	RTAvlroGCPtrDoWithAll(&pVM->pgm.s.pTreesR3->VirtHandlers, true, pgmR3RelocateVirtHandler, &offDelta);
2064	RTAvlroGCPtrDoWithAll(&pVM->pgm.s.pTreesR3->HyperVirtHandlers, true, pgmR3RelocateHyperVirtHandler, &offDelta);
2065
2066	/*
2067	* The page pool.
2068	*/
2069	pgmR3PoolRelocate(pVM);
2070	}
2071
2072
2073	/**
2074	* Callback function for relocating a physical access handler.
2075	*
2076	* @returns 0 (continue enum)
2077	* @param pNode Pointer to a PGMPHYSHANDLER node.
2078	* @param pvUser Pointer to the offDelta. This is a pointer to the delta since we're
2079	* not certain the delta will fit in a void pointer for all possible configs.
2080	*/
2081	static DECLCALLBACK(int) pgmR3RelocatePhysHandler(PAVLROGCPHYSNODECORE pNode, void *pvUser)
2082	{
2083	PPGMPHYSHANDLER pHandler = (PPGMPHYSHANDLER)pNode;
2084	RTGCINTPTR offDelta = *(PRTGCINTPTR)pvUser;
2085	if (pHandler->pfnHandlerRC)
2086	pHandler->pfnHandlerRC += offDelta;
2087	if (pHandler->pvUserRC >= 0x10000)
2088	pHandler->pvUserRC += offDelta;
2089	return 0;
2090	}
2091
2092
2093	/**
2094	* Callback function for relocating a virtual access handler.
2095	*
2096	* @returns 0 (continue enum)
2097	* @param pNode Pointer to a PGMVIRTHANDLER node.
2098	* @param pvUser Pointer to the offDelta. This is a pointer to the delta since we're
2099	* not certain the delta will fit in a void pointer for all possible configs.
2100	*/
2101	static DECLCALLBACK(int) pgmR3RelocateVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser)
2102	{
2103	PPGMVIRTHANDLER pHandler = (PPGMVIRTHANDLER)pNode;
2104	RTGCINTPTR offDelta = *(PRTGCINTPTR)pvUser;
2105	Assert( pHandler->enmType == PGMVIRTHANDLERTYPE_ALL
2106	\|\| pHandler->enmType == PGMVIRTHANDLERTYPE_WRITE);
2107	Assert(pHandler->pfnHandlerRC);
2108	pHandler->pfnHandlerRC += offDelta;
2109	return 0;
2110	}
2111
2112
2113	/**
2114	* Callback function for relocating a virtual access handler for the hypervisor mapping.
2115	*
2116	* @returns 0 (continue enum)
2117	* @param pNode Pointer to a PGMVIRTHANDLER node.
2118	* @param pvUser Pointer to the offDelta. This is a pointer to the delta since we're
2119	* not certain the delta will fit in a void pointer for all possible configs.
2120	*/
2121	static DECLCALLBACK(int) pgmR3RelocateHyperVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser)
2122	{
2123	PPGMVIRTHANDLER pHandler = (PPGMVIRTHANDLER)pNode;
2124	RTGCINTPTR offDelta = *(PRTGCINTPTR)pvUser;
2125	Assert(pHandler->enmType == PGMVIRTHANDLERTYPE_HYPERVISOR);
2126	Assert(pHandler->pfnHandlerRC);
2127	pHandler->pfnHandlerRC += offDelta;
2128	return 0;
2129	}
2130
2131
2132	/**
2133	* The VM is being reset.
2134	*
2135	* For the PGM component this means that any PD write monitors
2136	* needs to be removed.
2137	*
2138	* @param pVM VM handle.
2139	*/
2140	VMMR3DECL(void) PGMR3Reset(PVM pVM)
2141	{
2142	LogFlow(("PGMR3Reset:\n"));
2143	VM_ASSERT_EMT(pVM);
2144
2145	pgmLock(pVM);
2146
2147	/*
2148	* Unfix any fixed mappings and disable CR3 monitoring.
2149	*/
2150	pVM->pgm.s.fMappingsFixed = false;
2151	pVM->pgm.s.GCPtrMappingFixed = 0;
2152	pVM->pgm.s.cbMappingFixed = 0;
2153
2154	/* Exit the guest paging mode before the pgm pool gets reset.
2155	* Important to clean up the amd64 case.
2156	*/
2157	int rc = PGM_GST_PFN(Exit, pVM)(pVM);
2158	AssertRC(rc);
2159	#ifdef DEBUG
2160	DBGFR3InfoLog(pVM, "mappings", NULL);
2161	DBGFR3InfoLog(pVM, "handlers", "all nostat");
2162	#endif
2163
2164	/*
2165	* Reset the shadow page pool.
2166	*/
2167	pgmR3PoolReset(pVM);
2168
2169	/*
2170	* Re-init other members.
2171	*/
2172	pVM->pgm.s.fA20Enabled = true;
2173
2174	/*
2175	* Clear the FFs PGM owns.
2176	*/
2177	VM_FF_CLEAR(pVM, VM_FF_PGM_SYNC_CR3);
2178	VM_FF_CLEAR(pVM, VM_FF_PGM_SYNC_CR3_NON_GLOBAL);
2179
2180	/*
2181	* Reset (zero) RAM pages.
2182	*/
2183	rc = pgmR3PhysRamReset(pVM);
2184	if (RT_SUCCESS(rc))
2185	{
2186	#ifdef VBOX_WITH_NEW_PHYS_CODE
2187	/*
2188	* Reset (zero) shadow ROM pages.
2189	*/
2190	rc = pgmR3PhysRomReset(pVM);
2191	#endif
2192	if (RT_SUCCESS(rc))
2193	{
2194	/*
2195	* Switch mode back to real mode.
2196	*/
2197	rc = PGMR3ChangeMode(pVM, PGMMODE_REAL);
2198	STAM_REL_COUNTER_RESET(&pVM->pgm.s.cGuestModeChanges);
2199	}
2200	}
2201
2202	pgmUnlock(pVM);
2203	//return rc;
2204	AssertReleaseRC(rc);
2205	}
2206
2207
2208	#ifdef VBOX_STRICT
2209	/**
2210	* VM state change callback for clearing fNoMorePhysWrites after
2211	* a snapshot has been created.
2212	*/
2213	static DECLCALLBACK(void) pgmR3ResetNoMorePhysWritesFlag(PVM pVM, VMSTATE enmState, VMSTATE enmOldState, void *pvUser)
2214	{
2215	if (enmState == VMSTATE_RUNNING)
2216	pVM->pgm.s.fNoMorePhysWrites = false;
2217	}
2218	#endif
2219
2220
2221	/**
2222	* Terminates the PGM.
2223	*
2224	* @returns VBox status code.
2225	* @param pVM Pointer to VM structure.
2226	*/
2227	VMMR3DECL(int) PGMR3Term(PVM pVM)
2228	{
2229	return PDMR3CritSectDelete(&pVM->pgm.s.CritSect);
2230	}
2231
2232
2233	/**
2234	* Terminates the per-VCPU PGM.
2235	*
2236	* Termination means cleaning up and freeing all resources,
2237	* the VM it self is at this point powered off or suspended.
2238	*
2239	* @returns VBox status code.
2240	* @param pVM The VM to operate on.
2241	*/
2242	VMMR3DECL(int) PGMR3TermCPU(PVM pVM)
2243	{
2244	return 0;
2245	}
2246
2247
2248	/**
2249	* Execute state save operation.
2250	*
2251	* @returns VBox status code.
2252	* @param pVM VM Handle.
2253	* @param pSSM SSM operation handle.
2254	*/
2255	static DECLCALLBACK(int) pgmR3Save(PVM pVM, PSSMHANDLE pSSM)
2256	{
2257	PPGM pPGM = &pVM->pgm.s;
2258
2259	/* No more writes to physical memory after this point! */
2260	pVM->pgm.s.fNoMorePhysWrites = true;
2261
2262	/*
2263	* Save basic data (required / unaffected by relocation).
2264	*/
2265	#if 1
2266	SSMR3PutBool(pSSM, pPGM->fMappingsFixed);
2267	#else
2268	SSMR3PutUInt(pSSM, pPGM->fMappingsFixed);
2269	#endif
2270	SSMR3PutGCPtr(pSSM, pPGM->GCPtrMappingFixed);
2271	SSMR3PutU32(pSSM, pPGM->cbMappingFixed);
2272	SSMR3PutUInt(pSSM, pPGM->cbRamSize);
2273	SSMR3PutGCPhys(pSSM, pPGM->GCPhysA20Mask);
2274	SSMR3PutUInt(pSSM, pPGM->fA20Enabled);
2275	SSMR3PutUInt(pSSM, pPGM->fSyncFlags);
2276	SSMR3PutUInt(pSSM, pPGM->enmGuestMode);
2277	SSMR3PutU32(pSSM, ~0); /* Separator. */
2278
2279	/*
2280	* The guest mappings.
2281	*/
2282	uint32_t i = 0;
2283	for (PPGMMAPPING pMapping = pPGM->pMappingsR3; pMapping; pMapping = pMapping->pNextR3, i++)
2284	{
2285	SSMR3PutU32(pSSM, i);
2286	SSMR3PutStrZ(pSSM, pMapping->pszDesc); /* This is the best unique id we have... */
2287	SSMR3PutGCPtr(pSSM, pMapping->GCPtr);
2288	SSMR3PutGCUIntPtr(pSSM, pMapping->cPTs);
2289	/* flags are done by the mapping owners! */
2290	}
2291	SSMR3PutU32(pSSM, ~0); /* terminator. */
2292
2293	/*
2294	* Ram range flags and bits.
2295	*/
2296	i = 0;
2297	for (PPGMRAMRANGE pRam = pPGM->pRamRangesR3; pRam; pRam = pRam->pNextR3, i++)
2298	{
2299	/** @todo MMIO ranges may move (PCI reconfig), we currently assume they don't. */
2300
2301	SSMR3PutU32(pSSM, i);
2302	SSMR3PutGCPhys(pSSM, pRam->GCPhys);
2303	SSMR3PutGCPhys(pSSM, pRam->GCPhysLast);
2304	SSMR3PutGCPhys(pSSM, pRam->cb);
2305	SSMR3PutU8(pSSM, !!pRam->pvR3); /* boolean indicating memory or not. */
2306
2307	/* Flags. */
2308	const unsigned cPages = pRam->cb >> PAGE_SHIFT;
2309	for (unsigned iPage = 0; iPage < cPages; iPage++)
2310	SSMR3PutU16(pSSM, (uint16_t)(pRam->aPages[iPage].HCPhys & ~X86_PTE_PAE_PG_MASK)); /** @todo PAGE FLAGS */
2311
2312	/* any memory associated with the range. */
2313	if (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)
2314	{
2315	for (unsigned iChunk = 0; iChunk < (pRam->cb >> PGM_DYNAMIC_CHUNK_SHIFT); iChunk++)
2316	{
2317	if (pRam->paChunkR3Ptrs[iChunk])
2318	{
2319	SSMR3PutU8(pSSM, 1); /* chunk present */
2320	SSMR3PutMem(pSSM, (void *)pRam->paChunkR3Ptrs[iChunk], PGM_DYNAMIC_CHUNK_SIZE);
2321	}
2322	else
2323	SSMR3PutU8(pSSM, 0); /* no chunk present */
2324	}
2325	}
2326	else if (pRam->pvR3)
2327	{
2328	int rc = SSMR3PutMem(pSSM, pRam->pvR3, pRam->cb);
2329	if (RT_FAILURE(rc))
2330	{
2331	Log(("pgmR3Save: SSMR3PutMem(, %p, %#x) -> %Rrc\n", pRam->pvR3, pRam->cb, rc));
2332	return rc;
2333	}
2334	}
2335	}
2336	return SSMR3PutU32(pSSM, ~0); /* terminator. */
2337	}
2338
2339
2340	/**
2341	* Execute state load operation.
2342	*
2343	* @returns VBox status code.
2344	* @param pVM VM Handle.
2345	* @param pSSM SSM operation handle.
2346	* @param u32Version Data layout version.
2347	*/
2348	static DECLCALLBACK(int) pgmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version)
2349	{
2350	/*
2351	* Validate version.
2352	*/
2353	if (u32Version != PGM_SAVED_STATE_VERSION)
2354	{
2355	AssertMsgFailed(("pgmR3Load: Invalid version u32Version=%d (current %d)!\n", u32Version, PGM_SAVED_STATE_VERSION));
2356	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
2357	}
2358
2359	/*
2360	* Call the reset function to make sure all the memory is cleared.
2361	*/
2362	PGMR3Reset(pVM);
2363
2364	/*
2365	* Load basic data (required / unaffected by relocation).
2366	*/
2367	PPGM pPGM = &pVM->pgm.s;
2368	#if 1
2369	SSMR3GetBool(pSSM, &pPGM->fMappingsFixed);
2370	#else
2371	uint32_t u;
2372	SSMR3GetU32(pSSM, &u);
2373	pPGM->fMappingsFixed = u;
2374	#endif
2375	SSMR3GetGCPtr(pSSM, &pPGM->GCPtrMappingFixed);
2376	SSMR3GetU32(pSSM, &pPGM->cbMappingFixed);
2377
2378	RTUINT cbRamSize;
2379	int rc = SSMR3GetU32(pSSM, &cbRamSize);
2380	if (RT_FAILURE(rc))
2381	return rc;
2382	if (cbRamSize != pPGM->cbRamSize)
2383	return VERR_SSM_LOAD_MEMORY_SIZE_MISMATCH;
2384	SSMR3GetGCPhys(pSSM, &pPGM->GCPhysA20Mask);
2385	SSMR3GetUInt(pSSM, &pPGM->fA20Enabled);
2386	SSMR3GetUInt(pSSM, &pPGM->fSyncFlags);
2387	RTUINT uGuestMode;
2388	SSMR3GetUInt(pSSM, &uGuestMode);
2389	pPGM->enmGuestMode = (PGMMODE)uGuestMode;
2390
2391	/* check separator. */
2392	uint32_t u32Sep;
2393	SSMR3GetU32(pSSM, &u32Sep);
2394	if (RT_FAILURE(rc))
2395	return rc;
2396	if (u32Sep != (uint32_t)~0)
2397	{
2398	AssertMsgFailed(("u32Sep=%#x (first)\n", u32Sep));
2399	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2400	}
2401
2402	/*
2403	* The guest mappings.
2404	*/
2405	uint32_t i = 0;
2406	for (;; i++)
2407	{
2408	/* Check the seqence number / separator. */
2409	rc = SSMR3GetU32(pSSM, &u32Sep);
2410	if (RT_FAILURE(rc))
2411	return rc;
2412	if (u32Sep == ~0U)
2413	break;
2414	if (u32Sep != i)
2415	{
2416	AssertMsgFailed(("u32Sep=%#x (last)\n", u32Sep));
2417	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2418	}
2419
2420	/* get the mapping details. */
2421	char szDesc[256];
2422	szDesc[0] = '\0';
2423	rc = SSMR3GetStrZ(pSSM, szDesc, sizeof(szDesc));
2424	if (RT_FAILURE(rc))
2425	return rc;
2426	RTGCPTR GCPtr;
2427	SSMR3GetGCPtr(pSSM, &GCPtr);
2428	RTGCPTR cPTs;
2429	rc = SSMR3GetGCUIntPtr(pSSM, &cPTs);
2430	if (RT_FAILURE(rc))
2431	return rc;
2432
2433	/* find matching range. */
2434	PPGMMAPPING pMapping;
2435	for (pMapping = pPGM->pMappingsR3; pMapping; pMapping = pMapping->pNextR3)
2436	if ( pMapping->cPTs == cPTs
2437	&& !strcmp(pMapping->pszDesc, szDesc))
2438	break;
2439	if (!pMapping)
2440	{
2441	LogRel(("Couldn't find mapping: cPTs=%#x szDesc=%s (GCPtr=%RGv)\n",
2442	cPTs, szDesc, GCPtr));
2443	AssertFailed();
2444	return VERR_SSM_LOAD_CONFIG_MISMATCH;
2445	}
2446
2447	/* relocate it. */
2448	if (pMapping->GCPtr != GCPtr)
2449	{
2450	AssertMsg((GCPtr >> X86_PD_SHIFT << X86_PD_SHIFT) == GCPtr, ("GCPtr=%RGv\n", GCPtr));
2451	pgmR3MapRelocate(pVM, pMapping, pMapping->GCPtr, GCPtr);
2452	}
2453	else
2454	Log(("pgmR3Load: '%s' needed no relocation (%RGv)\n", szDesc, GCPtr));
2455	}
2456
2457	/*
2458	* Ram range flags and bits.
2459	*/
2460	i = 0;
2461	for (PPGMRAMRANGE pRam = pPGM->pRamRangesR3; pRam; pRam = pRam->pNextR3, i++)
2462	{
2463	/** @todo MMIO ranges may move (PCI reconfig), we currently assume they don't. */
2464	/* Check the seqence number / separator. */
2465	rc = SSMR3GetU32(pSSM, &u32Sep);
2466	if (RT_FAILURE(rc))
2467	return rc;
2468	if (u32Sep == ~0U)
2469	break;
2470	if (u32Sep != i)
2471	{
2472	AssertMsgFailed(("u32Sep=%#x (last)\n", u32Sep));
2473	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2474	}
2475
2476	/* Get the range details. */
2477	RTGCPHYS GCPhys;
2478	SSMR3GetGCPhys(pSSM, &GCPhys);
2479	RTGCPHYS GCPhysLast;
2480	SSMR3GetGCPhys(pSSM, &GCPhysLast);
2481	RTGCPHYS cb;
2482	SSMR3GetGCPhys(pSSM, &cb);
2483	uint8_t fHaveBits;
2484	rc = SSMR3GetU8(pSSM, &fHaveBits);
2485	if (RT_FAILURE(rc))
2486	return rc;
2487	if (fHaveBits & ~1)
2488	{
2489	AssertMsgFailed(("u32Sep=%#x (last)\n", u32Sep));
2490	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2491	}
2492
2493	/* Match it up with the current range. */
2494	if ( GCPhys != pRam->GCPhys
2495	\|\| GCPhysLast != pRam->GCPhysLast
2496	\|\| cb != pRam->cb
2497	\|\| fHaveBits != !!pRam->pvR3)
2498	{
2499	LogRel(("Ram range: %RGp-%RGp %RGp bytes %s\n"
2500	"State : %RGp-%RGp %RGp bytes %s\n",
2501	pRam->GCPhys, pRam->GCPhysLast, pRam->cb, pRam->pvR3 ? "bits" : "nobits",
2502	GCPhys, GCPhysLast, cb, fHaveBits ? "bits" : "nobits"));
2503	/*
2504	* If we're loading a state for debugging purpose, don't make a fuss if
2505	* the MMIO[2] and ROM stuff isn't 100% right, just skip the mismatches.
2506	*/
2507	if ( SSMR3HandleGetAfter(pSSM) != SSMAFTER_DEBUG_IT
2508	\|\| GCPhys < 8 * _1M)
2509	AssertFailedReturn(VERR_SSM_LOAD_CONFIG_MISMATCH);
2510
2511	RTGCPHYS cPages = ((GCPhysLast - GCPhys) + 1) >> PAGE_SHIFT;
2512	while (cPages-- > 0)
2513	{
2514	uint16_t u16Ignore;
2515	SSMR3GetU16(pSSM, &u16Ignore);
2516	}
2517	continue;
2518	}
2519
2520	/* Flags. */
2521	const unsigned cPages = pRam->cb >> PAGE_SHIFT;
2522	for (unsigned iPage = 0; iPage < cPages; iPage++)
2523	{
2524	uint16_t u16 = 0;
2525	SSMR3GetU16(pSSM, &u16);
2526	u16 &= PAGE_OFFSET_MASK & ~( RT_BIT(4) \| RT_BIT(5) \| RT_BIT(6)
2527	\| RT_BIT(7) \| RT_BIT(8) \| RT_BIT(9) \| RT_BIT(10) );
2528	// &= MM_RAM_FLAGS_DYNAMIC_ALLOC \| MM_RAM_FLAGS_RESERVED \| MM_RAM_FLAGS_ROM \| MM_RAM_FLAGS_MMIO \| MM_RAM_FLAGS_MMIO2
2529	pRam->aPages[iPage].HCPhys = PGM_PAGE_GET_HCPHYS(&pRam->aPages[iPage]) \| (RTHCPHYS)u16; /** @todo PAGE FLAGS */
2530	}
2531
2532	/* any memory associated with the range. */
2533	if (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)
2534	{
2535	for (unsigned iChunk = 0; iChunk < (pRam->cb >> PGM_DYNAMIC_CHUNK_SHIFT); iChunk++)
2536	{
2537	uint8_t fValidChunk;
2538
2539	rc = SSMR3GetU8(pSSM, &fValidChunk);
2540	if (RT_FAILURE(rc))
2541	return rc;
2542	if (fValidChunk > 1)
2543	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2544
2545	if (fValidChunk)
2546	{
2547	if (!pRam->paChunkR3Ptrs[iChunk])
2548	{
2549	rc = pgmr3PhysGrowRange(pVM, pRam->GCPhys + iChunk * PGM_DYNAMIC_CHUNK_SIZE);
2550	if (RT_FAILURE(rc))
2551	return rc;
2552	}
2553	Assert(pRam->paChunkR3Ptrs[iChunk]);
2554
2555	SSMR3GetMem(pSSM, (void *)pRam->paChunkR3Ptrs[iChunk], PGM_DYNAMIC_CHUNK_SIZE);
2556	}
2557	/* else nothing to do */
2558	}
2559	}
2560	else if (pRam->pvR3)
2561	{
2562	int rc = SSMR3GetMem(pSSM, pRam->pvR3, pRam->cb);
2563	if (RT_FAILURE(rc))
2564	{
2565	Log(("pgmR3Save: SSMR3GetMem(, %p, %#x) -> %Rrc\n", pRam->pvR3, pRam->cb, rc));
2566	return rc;
2567	}
2568	}
2569	}
2570
2571	/*
2572	* We require a full resync now.
2573	*/
2574	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3_NON_GLOBAL);
2575	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
2576	pPGM->fSyncFlags \|= PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL;
2577	pPGM->fPhysCacheFlushPending = true;
2578	pgmR3HandlerPhysicalUpdateAll(pVM);
2579
2580	/*
2581	* Change the paging mode.
2582	*/
2583	rc = PGMR3ChangeMode(pVM, pPGM->enmGuestMode);
2584
2585	/* Restore pVM->pgm.s.GCPhysCR3. */
2586	Assert(pVM->pgm.s.GCPhysCR3 == NIL_RTGCPHYS);
2587	RTGCPHYS GCPhysCR3 = CPUMGetGuestCR3(pVM);
2588	if ( pVM->pgm.s.enmGuestMode == PGMMODE_PAE
2589	\|\| pVM->pgm.s.enmGuestMode == PGMMODE_PAE_NX
2590	\|\| pVM->pgm.s.enmGuestMode == PGMMODE_AMD64
2591	\|\| pVM->pgm.s.enmGuestMode == PGMMODE_AMD64_NX)
2592	GCPhysCR3 = (GCPhysCR3 & X86_CR3_PAE_PAGE_MASK);
2593	else
2594	GCPhysCR3 = (GCPhysCR3 & X86_CR3_PAGE_MASK);
2595	pVM->pgm.s.GCPhysCR3 = GCPhysCR3;
2596
2597	return rc;
2598	}
2599
2600
2601	/**
2602	* Show paging mode.
2603	*
2604	* @param pVM VM Handle.
2605	* @param pHlp The info helpers.
2606	* @param pszArgs "all" (default), "guest", "shadow" or "host".
2607	*/
2608	static DECLCALLBACK(void) pgmR3InfoMode(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2609	{
2610	/* digest argument. */
2611	bool fGuest, fShadow, fHost;
2612	if (pszArgs)
2613	pszArgs = RTStrStripL(pszArgs);
2614	if (!pszArgs \|\| !*pszArgs \|\| strstr(pszArgs, "all"))
2615	fShadow = fHost = fGuest = true;
2616	else
2617	{
2618	fShadow = fHost = fGuest = false;
2619	if (strstr(pszArgs, "guest"))
2620	fGuest = true;
2621	if (strstr(pszArgs, "shadow"))
2622	fShadow = true;
2623	if (strstr(pszArgs, "host"))
2624	fHost = true;
2625	}
2626
2627	/* print info. */
2628	if (fGuest)
2629	pHlp->pfnPrintf(pHlp, "Guest paging mode: %s, changed %RU64 times, A20 %s\n",
2630	PGMGetModeName(pVM->pgm.s.enmGuestMode), pVM->pgm.s.cGuestModeChanges.c,
2631	pVM->pgm.s.fA20Enabled ? "enabled" : "disabled");
2632	if (fShadow)
2633	pHlp->pfnPrintf(pHlp, "Shadow paging mode: %s\n", PGMGetModeName(pVM->pgm.s.enmShadowMode));
2634	if (fHost)
2635	{
2636	const char *psz;
2637	switch (pVM->pgm.s.enmHostMode)
2638	{
2639	case SUPPAGINGMODE_INVALID: psz = "invalid"; break;
2640	case SUPPAGINGMODE_32_BIT: psz = "32-bit"; break;
2641	case SUPPAGINGMODE_32_BIT_GLOBAL: psz = "32-bit+G"; break;
2642	case SUPPAGINGMODE_PAE: psz = "PAE"; break;
2643	case SUPPAGINGMODE_PAE_GLOBAL: psz = "PAE+G"; break;
2644	case SUPPAGINGMODE_PAE_NX: psz = "PAE+NX"; break;
2645	case SUPPAGINGMODE_PAE_GLOBAL_NX: psz = "PAE+G+NX"; break;
2646	case SUPPAGINGMODE_AMD64: psz = "AMD64"; break;
2647	case SUPPAGINGMODE_AMD64_GLOBAL: psz = "AMD64+G"; break;
2648	case SUPPAGINGMODE_AMD64_NX: psz = "AMD64+NX"; break;
2649	case SUPPAGINGMODE_AMD64_GLOBAL_NX: psz = "AMD64+G+NX"; break;
2650	default: psz = "unknown"; break;
2651	}
2652	pHlp->pfnPrintf(pHlp, "Host paging mode: %s\n", psz);
2653	}
2654	}
2655
2656
2657	/**
2658	* Dump registered MMIO ranges to the log.
2659	*
2660	* @param pVM VM Handle.
2661	* @param pHlp The info helpers.
2662	* @param pszArgs Arguments, ignored.
2663	*/
2664	static DECLCALLBACK(void) pgmR3PhysInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2665	{
2666	NOREF(pszArgs);
2667	pHlp->pfnPrintf(pHlp,
2668	"RAM ranges (pVM=%p)\n"
2669	"%.s %.s\n",
2670	pVM,
2671	sizeof(RTGCPHYS) * 4 + 1, "GC Phys Range ",
2672	sizeof(RTHCPTR) * 2, "pvHC ");
2673
2674	for (PPGMRAMRANGE pCur = pVM->pgm.s.pRamRangesR3; pCur; pCur = pCur->pNextR3)
2675	pHlp->pfnPrintf(pHlp,
2676	"%RGp-%RGp %RHv %s\n",
2677	pCur->GCPhys,
2678	pCur->GCPhysLast,
2679	pCur->pvR3,
2680	pCur->pszDesc);
2681	}
2682
2683	/**
2684	* Dump the page directory to the log.
2685	*
2686	* @param pVM VM Handle.
2687	* @param pHlp The info helpers.
2688	* @param pszArgs Arguments, ignored.
2689	*/
2690	static DECLCALLBACK(void) pgmR3InfoCr3(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2691	{
2692	/** @todo fix this! Convert the PGMR3DumpHierarchyHC functions to do guest stuff. */
2693	/* Big pages supported? */
2694	const bool fPSE = !!(CPUMGetGuestCR4(pVM) & X86_CR4_PSE);
2695
2696	/* Global pages supported? */
2697	const bool fPGE = !!(CPUMGetGuestCR4(pVM) & X86_CR4_PGE);
2698
2699	NOREF(pszArgs);
2700
2701	/*
2702	* Get page directory addresses.
2703	*/
2704	PX86PD pPDSrc = pVM->pgm.s.pGst32BitPdR3;
2705	Assert(pPDSrc);
2706	Assert(PGMPhysGCPhys2R3PtrAssert(pVM, (RTGCPHYS)(CPUMGetGuestCR3(pVM) & X86_CR3_PAGE_MASK), sizeof(*pPDSrc)) == pPDSrc);
2707
2708	/*
2709	* Iterate the page directory.
2710	*/
2711	for (unsigned iPD = 0; iPD < RT_ELEMENTS(pPDSrc->a); iPD++)
2712	{
2713	X86PDE PdeSrc = pPDSrc->a[iPD];
2714	if (PdeSrc.n.u1Present)
2715	{
2716	if (PdeSrc.b.u1Size && fPSE)
2717	pHlp->pfnPrintf(pHlp,
2718	"%04X - %RGp P=%d U=%d RW=%d G=%d - BIG\n",
2719	iPD,
2720	pgmGstGet4MBPhysPage(&pVM->pgm.s, PdeSrc),
2721	PdeSrc.b.u1Present, PdeSrc.b.u1User, PdeSrc.b.u1Write, PdeSrc.b.u1Global && fPGE);
2722	else
2723	pHlp->pfnPrintf(pHlp,
2724	"%04X - %RGp P=%d U=%d RW=%d [G=%d]\n",
2725	iPD,
2726	(RTGCPHYS)(PdeSrc.u & X86_PDE_PG_MASK),
2727	PdeSrc.n.u1Present, PdeSrc.n.u1User, PdeSrc.n.u1Write, PdeSrc.b.u1Global && fPGE);
2728	}
2729	}
2730	}
2731
2732
2733	/**
2734	* Serivce a VMMCALLHOST_PGM_LOCK call.
2735	*
2736	* @returns VBox status code.
2737	* @param pVM The VM handle.
2738	*/
2739	VMMR3DECL(int) PGMR3LockCall(PVM pVM)
2740	{
2741	int rc = PDMR3CritSectEnterEx(&pVM->pgm.s.CritSect, true /* fHostCall */);
2742	AssertRC(rc);
2743	return rc;
2744	}
2745
2746
2747	/**
2748	* Converts a PGMMODE value to a PGM_TYPE_* \#define.
2749	*
2750	* @returns PGM_TYPE_*.
2751	* @param pgmMode The mode value to convert.
2752	*/
2753	DECLINLINE(unsigned) pgmModeToType(PGMMODE pgmMode)
2754	{
2755	switch (pgmMode)
2756	{
2757	case PGMMODE_REAL: return PGM_TYPE_REAL;
2758	case PGMMODE_PROTECTED: return PGM_TYPE_PROT;
2759	case PGMMODE_32_BIT: return PGM_TYPE_32BIT;
2760	case PGMMODE_PAE:
2761	case PGMMODE_PAE_NX: return PGM_TYPE_PAE;
2762	case PGMMODE_AMD64:
2763	case PGMMODE_AMD64_NX: return PGM_TYPE_AMD64;
2764	case PGMMODE_NESTED: return PGM_TYPE_NESTED;
2765	case PGMMODE_EPT: return PGM_TYPE_EPT;
2766	default:
2767	AssertFatalMsgFailed(("pgmMode=%d\n", pgmMode));
2768	}
2769	}
2770
2771
2772	/**
2773	* Gets the index into the paging mode data array of a SHW+GST mode.
2774	*
2775	* @returns PGM::paPagingData index.
2776	* @param uShwType The shadow paging mode type.
2777	* @param uGstType The guest paging mode type.
2778	*/
2779	DECLINLINE(unsigned) pgmModeDataIndex(unsigned uShwType, unsigned uGstType)
2780	{
2781	Assert(uShwType >= PGM_TYPE_32BIT && uShwType <= PGM_TYPE_MAX);
2782	Assert(uGstType >= PGM_TYPE_REAL && uGstType <= PGM_TYPE_AMD64);
2783	return (uShwType - PGM_TYPE_32BIT) * (PGM_TYPE_AMD64 - PGM_TYPE_REAL + 1)
2784	+ (uGstType - PGM_TYPE_REAL);
2785	}
2786
2787
2788	/**
2789	* Gets the index into the paging mode data array of a SHW+GST mode.
2790	*
2791	* @returns PGM::paPagingData index.
2792	* @param enmShw The shadow paging mode.
2793	* @param enmGst The guest paging mode.
2794	*/
2795	DECLINLINE(unsigned) pgmModeDataIndexByMode(PGMMODE enmShw, PGMMODE enmGst)
2796	{
2797	Assert(enmShw >= PGMMODE_32_BIT && enmShw <= PGMMODE_MAX);
2798	Assert(enmGst > PGMMODE_INVALID && enmGst < PGMMODE_MAX);
2799	return pgmModeDataIndex(pgmModeToType(enmShw), pgmModeToType(enmGst));
2800	}
2801
2802
2803	/**
2804	* Calculates the max data index.
2805	* @returns The number of entries in the paging data array.
2806	*/
2807	DECLINLINE(unsigned) pgmModeDataMaxIndex(void)
2808	{
2809	return pgmModeDataIndex(PGM_TYPE_MAX, PGM_TYPE_AMD64) + 1;
2810	}
2811
2812
2813	/**
2814	* Initializes the paging mode data kept in PGM::paModeData.
2815	*
2816	* @param pVM The VM handle.
2817	* @param fResolveGCAndR0 Indicate whether or not GC and Ring-0 symbols can be resolved now.
2818	* This is used early in the init process to avoid trouble with PDM
2819	* not being initialized yet.
2820	*/
2821	static int pgmR3ModeDataInit(PVM pVM, bool fResolveGCAndR0)
2822	{
2823	PPGMMODEDATA pModeData;
2824	int rc;
2825
2826	/*
2827	* Allocate the array on the first call.
2828	*/
2829	if (!pVM->pgm.s.paModeData)
2830	{
2831	pVM->pgm.s.paModeData = (PPGMMODEDATA)MMR3HeapAllocZ(pVM, MM_TAG_PGM, sizeof(PGMMODEDATA) * pgmModeDataMaxIndex());
2832	AssertReturn(pVM->pgm.s.paModeData, VERR_NO_MEMORY);
2833	}
2834
2835	/*
2836	* Initialize the array entries.
2837	*/
2838	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_32BIT, PGM_TYPE_REAL)];
2839	pModeData->uShwType = PGM_TYPE_32BIT;
2840	pModeData->uGstType = PGM_TYPE_REAL;
2841	rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2842	rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2843	rc = PGM_BTH_NAME_32BIT_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2844
2845	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_32BIT, PGMMODE_PROTECTED)];
2846	pModeData->uShwType = PGM_TYPE_32BIT;
2847	pModeData->uGstType = PGM_TYPE_PROT;
2848	rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2849	rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2850	rc = PGM_BTH_NAME_32BIT_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2851
2852	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_32BIT, PGM_TYPE_32BIT)];
2853	pModeData->uShwType = PGM_TYPE_32BIT;
2854	pModeData->uGstType = PGM_TYPE_32BIT;
2855	rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2856	rc = PGM_GST_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2857	rc = PGM_BTH_NAME_32BIT_32BIT(InitData)(pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2858
2859	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_REAL)];
2860	pModeData->uShwType = PGM_TYPE_PAE;
2861	pModeData->uGstType = PGM_TYPE_REAL;
2862	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2863	rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2864	rc = PGM_BTH_NAME_PAE_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2865
2866	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_PROT)];
2867	pModeData->uShwType = PGM_TYPE_PAE;
2868	pModeData->uGstType = PGM_TYPE_PROT;
2869	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2870	rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2871	rc = PGM_BTH_NAME_PAE_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2872
2873	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_32BIT)];
2874	pModeData->uShwType = PGM_TYPE_PAE;
2875	pModeData->uGstType = PGM_TYPE_32BIT;
2876	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2877	rc = PGM_GST_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2878	rc = PGM_BTH_NAME_PAE_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2879
2880	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_PAE)];
2881	pModeData->uShwType = PGM_TYPE_PAE;
2882	pModeData->uGstType = PGM_TYPE_PAE;
2883	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2884	rc = PGM_GST_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2885	rc = PGM_BTH_NAME_PAE_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2886
2887	#ifdef VBOX_WITH_64_BITS_GUESTS
2888	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_AMD64, PGM_TYPE_AMD64)];
2889	pModeData->uShwType = PGM_TYPE_AMD64;
2890	pModeData->uGstType = PGM_TYPE_AMD64;
2891	rc = PGM_SHW_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2892	rc = PGM_GST_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2893	rc = PGM_BTH_NAME_AMD64_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2894	#endif
2895
2896	/* The nested paging mode. */
2897	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_REAL)];
2898	pModeData->uShwType = PGM_TYPE_NESTED;
2899	pModeData->uGstType = PGM_TYPE_REAL;
2900	rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2901	rc = PGM_BTH_NAME_NESTED_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2902
2903	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGMMODE_PROTECTED)];
2904	pModeData->uShwType = PGM_TYPE_NESTED;
2905	pModeData->uGstType = PGM_TYPE_PROT;
2906	rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2907	rc = PGM_BTH_NAME_NESTED_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2908
2909	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_32BIT)];
2910	pModeData->uShwType = PGM_TYPE_NESTED;
2911	pModeData->uGstType = PGM_TYPE_32BIT;
2912	rc = PGM_GST_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2913	rc = PGM_BTH_NAME_NESTED_32BIT(InitData)(pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2914
2915	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_PAE)];
2916	pModeData->uShwType = PGM_TYPE_NESTED;
2917	pModeData->uGstType = PGM_TYPE_PAE;
2918	rc = PGM_GST_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2919	rc = PGM_BTH_NAME_NESTED_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2920
2921	#ifdef VBOX_WITH_64_BITS_GUESTS
2922	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_AMD64)];
2923	pModeData->uShwType = PGM_TYPE_NESTED;
2924	pModeData->uGstType = PGM_TYPE_AMD64;
2925	rc = PGM_GST_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2926	rc = PGM_BTH_NAME_NESTED_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2927	#endif
2928
2929	/* The shadow part of the nested callback mode depends on the host paging mode (AMD-V only). */
2930	switch (pVM->pgm.s.enmHostMode)
2931	{
2932	#if HC_ARCH_BITS == 32
2933	case SUPPAGINGMODE_32_BIT:
2934	case SUPPAGINGMODE_32_BIT_GLOBAL:
2935	for (unsigned i = PGM_TYPE_REAL; i <= PGM_TYPE_PAE; i++)
2936	{
2937	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, i)];
2938	rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2939	}
2940	# ifdef VBOX_WITH_64_BITS_GUESTS
2941	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_AMD64)];
2942	rc = PGM_SHW_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2943	# endif
2944	break;
2945
2946	case SUPPAGINGMODE_PAE:
2947	case SUPPAGINGMODE_PAE_NX:
2948	case SUPPAGINGMODE_PAE_GLOBAL:
2949	case SUPPAGINGMODE_PAE_GLOBAL_NX:
2950	for (unsigned i = PGM_TYPE_REAL; i <= PGM_TYPE_PAE; i++)
2951	{
2952	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, i)];
2953	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2954	}
2955	# ifdef VBOX_WITH_64_BITS_GUESTS
2956	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_AMD64)];
2957	rc = PGM_SHW_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2958	# endif
2959	break;
2960	#endif /* HC_ARCH_BITS == 32 */
2961
2962	#if HC_ARCH_BITS == 64 \|\| defined(RT_OS_DARWIN)
2963	case SUPPAGINGMODE_AMD64:
2964	case SUPPAGINGMODE_AMD64_GLOBAL:
2965	case SUPPAGINGMODE_AMD64_NX:
2966	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
2967	# ifdef VBOX_WITH_64_BITS_GUESTS
2968	for (unsigned i = PGM_TYPE_REAL; i <= PGM_TYPE_AMD64; i++)
2969	# else
2970	for (unsigned i = PGM_TYPE_REAL; i <= PGM_TYPE_PAE; i++)
2971	# endif
2972	{
2973	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, i)];
2974	rc = PGM_SHW_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2975	}
2976	break;
2977	#endif /* HC_ARCH_BITS == 64 \|\| RT_OS_DARWIN */
2978
2979	default:
2980	AssertFailed();
2981	break;
2982	}
2983
2984	/* Extended paging (EPT) / Intel VT-x */
2985	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_REAL)];
2986	pModeData->uShwType = PGM_TYPE_EPT;
2987	pModeData->uGstType = PGM_TYPE_REAL;
2988	rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2989	rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2990	rc = PGM_BTH_NAME_EPT_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2991
2992	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_PROT)];
2993	pModeData->uShwType = PGM_TYPE_EPT;
2994	pModeData->uGstType = PGM_TYPE_PROT;
2995	rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2996	rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2997	rc = PGM_BTH_NAME_EPT_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2998
2999	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_32BIT)];
3000	pModeData->uShwType = PGM_TYPE_EPT;
3001	pModeData->uGstType = PGM_TYPE_32BIT;
3002	rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3003	rc = PGM_GST_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3004	rc = PGM_BTH_NAME_EPT_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3005
3006	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_PAE)];
3007	pModeData->uShwType = PGM_TYPE_EPT;
3008	pModeData->uGstType = PGM_TYPE_PAE;
3009	rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3010	rc = PGM_GST_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3011	rc = PGM_BTH_NAME_EPT_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3012
3013	#ifdef VBOX_WITH_64_BITS_GUESTS
3014	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_AMD64)];
3015	pModeData->uShwType = PGM_TYPE_EPT;
3016	pModeData->uGstType = PGM_TYPE_AMD64;
3017	rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3018	rc = PGM_GST_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3019	rc = PGM_BTH_NAME_EPT_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3020	#endif
3021	return VINF_SUCCESS;
3022	}
3023
3024
3025	/**
3026	* Switch to different (or relocated in the relocate case) mode data.
3027	*
3028	* @param pVM The VM handle.
3029	* @param enmShw The the shadow paging mode.
3030	* @param enmGst The the guest paging mode.
3031	*/
3032	static void pgmR3ModeDataSwitch(PVM pVM, PGMMODE enmShw, PGMMODE enmGst)
3033	{
3034	PPGMMODEDATA pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndexByMode(enmShw, enmGst)];
3035
3036	Assert(pModeData->uGstType == pgmModeToType(enmGst));
3037	Assert(pModeData->uShwType == pgmModeToType(enmShw));
3038
3039	/* shadow */
3040	pVM->pgm.s.pfnR3ShwRelocate = pModeData->pfnR3ShwRelocate;
3041	pVM->pgm.s.pfnR3ShwExit = pModeData->pfnR3ShwExit;
3042	pVM->pgm.s.pfnR3ShwGetPage = pModeData->pfnR3ShwGetPage;
3043	Assert(pVM->pgm.s.pfnR3ShwGetPage);
3044	pVM->pgm.s.pfnR3ShwModifyPage = pModeData->pfnR3ShwModifyPage;
3045
3046	pVM->pgm.s.pfnRCShwGetPage = pModeData->pfnRCShwGetPage;
3047	pVM->pgm.s.pfnRCShwModifyPage = pModeData->pfnRCShwModifyPage;
3048
3049	pVM->pgm.s.pfnR0ShwGetPage = pModeData->pfnR0ShwGetPage;
3050	pVM->pgm.s.pfnR0ShwModifyPage = pModeData->pfnR0ShwModifyPage;
3051
3052
3053	/* guest */
3054	pVM->pgm.s.pfnR3GstRelocate = pModeData->pfnR3GstRelocate;
3055	pVM->pgm.s.pfnR3GstExit = pModeData->pfnR3GstExit;
3056	pVM->pgm.s.pfnR3GstGetPage = pModeData->pfnR3GstGetPage;
3057	Assert(pVM->pgm.s.pfnR3GstGetPage);
3058	pVM->pgm.s.pfnR3GstModifyPage = pModeData->pfnR3GstModifyPage;
3059	pVM->pgm.s.pfnR3GstGetPDE = pModeData->pfnR3GstGetPDE;
3060	#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
3061	pVM->pgm.s.pfnR3GstMonitorCR3 = pModeData->pfnR3GstMonitorCR3;
3062	pVM->pgm.s.pfnR3GstUnmonitorCR3 = pModeData->pfnR3GstUnmonitorCR3;
3063	#endif
3064	#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
3065	pVM->pgm.s.pfnR3GstWriteHandlerCR3 = pModeData->pfnR3GstWriteHandlerCR3;
3066	pVM->pgm.s.pszR3GstWriteHandlerCR3 = pModeData->pszR3GstWriteHandlerCR3;
3067	pVM->pgm.s.pfnR3GstPAEWriteHandlerCR3 = pModeData->pfnR3GstPAEWriteHandlerCR3;
3068	pVM->pgm.s.pszR3GstPAEWriteHandlerCR3 = pModeData->pszR3GstPAEWriteHandlerCR3;
3069	#endif
3070	pVM->pgm.s.pfnRCGstGetPage = pModeData->pfnRCGstGetPage;
3071	pVM->pgm.s.pfnRCGstModifyPage = pModeData->pfnRCGstModifyPage;
3072	pVM->pgm.s.pfnRCGstGetPDE = pModeData->pfnRCGstGetPDE;
3073	#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
3074	pVM->pgm.s.pfnRCGstMonitorCR3 = pModeData->pfnRCGstMonitorCR3;
3075	pVM->pgm.s.pfnRCGstUnmonitorCR3 = pModeData->pfnRCGstUnmonitorCR3;
3076	#endif
3077	#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
3078	pVM->pgm.s.pfnRCGstWriteHandlerCR3 = pModeData->pfnRCGstWriteHandlerCR3;
3079	pVM->pgm.s.pfnRCGstPAEWriteHandlerCR3 = pModeData->pfnRCGstPAEWriteHandlerCR3;
3080	#endif
3081	pVM->pgm.s.pfnR0GstGetPage = pModeData->pfnR0GstGetPage;
3082	pVM->pgm.s.pfnR0GstModifyPage = pModeData->pfnR0GstModifyPage;
3083	pVM->pgm.s.pfnR0GstGetPDE = pModeData->pfnR0GstGetPDE;
3084	#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
3085	pVM->pgm.s.pfnR0GstMonitorCR3 = pModeData->pfnR0GstMonitorCR3;
3086	pVM->pgm.s.pfnR0GstUnmonitorCR3 = pModeData->pfnR0GstUnmonitorCR3;
3087	#endif
3088	#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
3089	pVM->pgm.s.pfnR0GstWriteHandlerCR3 = pModeData->pfnR0GstWriteHandlerCR3;
3090	pVM->pgm.s.pfnR0GstPAEWriteHandlerCR3 = pModeData->pfnR0GstPAEWriteHandlerCR3;
3091	#endif
3092
3093	/* both */
3094	pVM->pgm.s.pfnR3BthRelocate = pModeData->pfnR3BthRelocate;
3095	pVM->pgm.s.pfnR3BthInvalidatePage = pModeData->pfnR3BthInvalidatePage;
3096	pVM->pgm.s.pfnR3BthSyncCR3 = pModeData->pfnR3BthSyncCR3;
3097	Assert(pVM->pgm.s.pfnR3BthSyncCR3);
3098	pVM->pgm.s.pfnR3BthSyncPage = pModeData->pfnR3BthSyncPage;
3099	pVM->pgm.s.pfnR3BthPrefetchPage = pModeData->pfnR3BthPrefetchPage;
3100	pVM->pgm.s.pfnR3BthVerifyAccessSyncPage = pModeData->pfnR3BthVerifyAccessSyncPage;
3101	#ifdef VBOX_STRICT
3102	pVM->pgm.s.pfnR3BthAssertCR3 = pModeData->pfnR3BthAssertCR3;
3103	#endif
3104	pVM->pgm.s.pfnR3BthMapCR3 = pModeData->pfnR3BthMapCR3;
3105	pVM->pgm.s.pfnR3BthUnmapCR3 = pModeData->pfnR3BthUnmapCR3;
3106
3107	pVM->pgm.s.pfnRCBthTrap0eHandler = pModeData->pfnRCBthTrap0eHandler;
3108	pVM->pgm.s.pfnRCBthInvalidatePage = pModeData->pfnRCBthInvalidatePage;
3109	pVM->pgm.s.pfnRCBthSyncCR3 = pModeData->pfnRCBthSyncCR3;
3110	pVM->pgm.s.pfnRCBthSyncPage = pModeData->pfnRCBthSyncPage;
3111	pVM->pgm.s.pfnRCBthPrefetchPage = pModeData->pfnRCBthPrefetchPage;
3112	pVM->pgm.s.pfnRCBthVerifyAccessSyncPage = pModeData->pfnRCBthVerifyAccessSyncPage;
3113	#ifdef VBOX_STRICT
3114	pVM->pgm.s.pfnRCBthAssertCR3 = pModeData->pfnRCBthAssertCR3;
3115	#endif
3116	pVM->pgm.s.pfnRCBthMapCR3 = pModeData->pfnRCBthMapCR3;
3117	pVM->pgm.s.pfnRCBthUnmapCR3 = pModeData->pfnRCBthUnmapCR3;
3118
3119	pVM->pgm.s.pfnR0BthTrap0eHandler = pModeData->pfnR0BthTrap0eHandler;
3120	pVM->pgm.s.pfnR0BthInvalidatePage = pModeData->pfnR0BthInvalidatePage;
3121	pVM->pgm.s.pfnR0BthSyncCR3 = pModeData->pfnR0BthSyncCR3;
3122	pVM->pgm.s.pfnR0BthSyncPage = pModeData->pfnR0BthSyncPage;
3123	pVM->pgm.s.pfnR0BthPrefetchPage = pModeData->pfnR0BthPrefetchPage;
3124	pVM->pgm.s.pfnR0BthVerifyAccessSyncPage = pModeData->pfnR0BthVerifyAccessSyncPage;
3125	#ifdef VBOX_STRICT
3126	pVM->pgm.s.pfnR0BthAssertCR3 = pModeData->pfnR0BthAssertCR3;
3127	#endif
3128	pVM->pgm.s.pfnR0BthMapCR3 = pModeData->pfnR0BthMapCR3;
3129	pVM->pgm.s.pfnR0BthUnmapCR3 = pModeData->pfnR0BthUnmapCR3;
3130	}
3131
3132
3133	/**
3134	* Calculates the shadow paging mode.
3135	*
3136	* @returns The shadow paging mode.
3137	* @param pVM VM handle.
3138	* @param enmGuestMode The guest mode.
3139	* @param enmHostMode The host mode.
3140	* @param enmShadowMode The current shadow mode.
3141	* @param penmSwitcher Where to store the switcher to use.
3142	* VMMSWITCHER_INVALID means no change.
3143	*/
3144	static PGMMODE pgmR3CalcShadowMode(PVM pVM, PGMMODE enmGuestMode, SUPPAGINGMODE enmHostMode, PGMMODE enmShadowMode, VMMSWITCHER *penmSwitcher)
3145	{
3146	VMMSWITCHER enmSwitcher = VMMSWITCHER_INVALID;
3147	switch (enmGuestMode)
3148	{
3149	/*
3150	* When switching to real or protected mode we don't change
3151	* anything since it's likely that we'll switch back pretty soon.
3152	*
3153	* During pgmR3InitPaging we'll end up here with PGMMODE_INVALID
3154	* and is supposed to determine which shadow paging and switcher to
3155	* use during init.
3156	*/
3157	case PGMMODE_REAL:
3158	case PGMMODE_PROTECTED:
3159	if ( enmShadowMode != PGMMODE_INVALID
3160	&& !HWACCMIsEnabled(pVM) /* always switch in hwaccm mode! */)
3161	break; /* (no change) */
3162
3163	switch (enmHostMode)
3164	{
3165	case SUPPAGINGMODE_32_BIT:
3166	case SUPPAGINGMODE_32_BIT_GLOBAL:
3167	enmShadowMode = PGMMODE_32_BIT;
3168	enmSwitcher = VMMSWITCHER_32_TO_32;
3169	break;
3170
3171	case SUPPAGINGMODE_PAE:
3172	case SUPPAGINGMODE_PAE_NX:
3173	case SUPPAGINGMODE_PAE_GLOBAL:
3174	case SUPPAGINGMODE_PAE_GLOBAL_NX:
3175	enmShadowMode = PGMMODE_PAE;
3176	enmSwitcher = VMMSWITCHER_PAE_TO_PAE;
3177	#ifdef DEBUG_bird
3178	if (RTEnvExist("VBOX_32BIT"))
3179	{
3180	enmShadowMode = PGMMODE_32_BIT;
3181	enmSwitcher = VMMSWITCHER_PAE_TO_32;
3182	}
3183	#endif
3184	break;
3185
3186	case SUPPAGINGMODE_AMD64:
3187	case SUPPAGINGMODE_AMD64_GLOBAL:
3188	case SUPPAGINGMODE_AMD64_NX:
3189	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
3190	enmShadowMode = PGMMODE_PAE;
3191	enmSwitcher = VMMSWITCHER_AMD64_TO_PAE;
3192	#ifdef DEBUG_bird
3193	if (RTEnvExist("VBOX_32BIT"))
3194	{
3195	enmShadowMode = PGMMODE_32_BIT;
3196	enmSwitcher = VMMSWITCHER_AMD64_TO_32;
3197	}
3198	#endif
3199	break;
3200
3201	default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
3202	}
3203	break;
3204
3205	case PGMMODE_32_BIT:
3206	switch (enmHostMode)
3207	{
3208	case SUPPAGINGMODE_32_BIT:
3209	case SUPPAGINGMODE_32_BIT_GLOBAL:
3210	enmShadowMode = PGMMODE_32_BIT;
3211	enmSwitcher = VMMSWITCHER_32_TO_32;
3212	break;
3213
3214	case SUPPAGINGMODE_PAE:
3215	case SUPPAGINGMODE_PAE_NX:
3216	case SUPPAGINGMODE_PAE_GLOBAL:
3217	case SUPPAGINGMODE_PAE_GLOBAL_NX:
3218	enmShadowMode = PGMMODE_PAE;
3219	enmSwitcher = VMMSWITCHER_PAE_TO_PAE;
3220	#ifdef DEBUG_bird
3221	if (RTEnvExist("VBOX_32BIT"))
3222	{
3223	enmShadowMode = PGMMODE_32_BIT;
3224	enmSwitcher = VMMSWITCHER_PAE_TO_32;
3225	}
3226	#endif
3227	break;
3228
3229	case SUPPAGINGMODE_AMD64:
3230	case SUPPAGINGMODE_AMD64_GLOBAL:
3231	case SUPPAGINGMODE_AMD64_NX:
3232	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
3233	enmShadowMode = PGMMODE_PAE;
3234	enmSwitcher = VMMSWITCHER_AMD64_TO_PAE;
3235	#ifdef DEBUG_bird
3236	if (RTEnvExist("VBOX_32BIT"))
3237	{
3238	enmShadowMode = PGMMODE_32_BIT;
3239	enmSwitcher = VMMSWITCHER_AMD64_TO_32;
3240	}
3241	#endif
3242	break;
3243
3244	default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
3245	}
3246	break;
3247
3248	case PGMMODE_PAE:
3249	case PGMMODE_PAE_NX: /** @todo This might require more switchers and guest+both modes. */
3250	switch (enmHostMode)
3251	{
3252	case SUPPAGINGMODE_32_BIT:
3253	case SUPPAGINGMODE_32_BIT_GLOBAL:
3254	enmShadowMode = PGMMODE_PAE;
3255	enmSwitcher = VMMSWITCHER_32_TO_PAE;
3256	break;
3257
3258	case SUPPAGINGMODE_PAE:
3259	case SUPPAGINGMODE_PAE_NX:
3260	case SUPPAGINGMODE_PAE_GLOBAL:
3261	case SUPPAGINGMODE_PAE_GLOBAL_NX:
3262	enmShadowMode = PGMMODE_PAE;
3263	enmSwitcher = VMMSWITCHER_PAE_TO_PAE;
3264	break;
3265
3266	case SUPPAGINGMODE_AMD64:
3267	case SUPPAGINGMODE_AMD64_GLOBAL:
3268	case SUPPAGINGMODE_AMD64_NX:
3269	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
3270	enmShadowMode = PGMMODE_PAE;
3271	enmSwitcher = VMMSWITCHER_AMD64_TO_PAE;
3272	break;
3273
3274	default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
3275	}
3276	break;
3277
3278	case PGMMODE_AMD64:
3279	case PGMMODE_AMD64_NX:
3280	switch (enmHostMode)
3281	{
3282	case SUPPAGINGMODE_32_BIT:
3283	case SUPPAGINGMODE_32_BIT_GLOBAL:
3284	enmShadowMode = PGMMODE_AMD64;
3285	enmSwitcher = VMMSWITCHER_32_TO_AMD64;
3286	break;
3287
3288	case SUPPAGINGMODE_PAE:
3289	case SUPPAGINGMODE_PAE_NX:
3290	case SUPPAGINGMODE_PAE_GLOBAL:
3291	case SUPPAGINGMODE_PAE_GLOBAL_NX:
3292	enmShadowMode = PGMMODE_AMD64;
3293	enmSwitcher = VMMSWITCHER_PAE_TO_AMD64;
3294	break;
3295
3296	case SUPPAGINGMODE_AMD64:
3297	case SUPPAGINGMODE_AMD64_GLOBAL:
3298	case SUPPAGINGMODE_AMD64_NX:
3299	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
3300	enmShadowMode = PGMMODE_AMD64;
3301	enmSwitcher = VMMSWITCHER_AMD64_TO_AMD64;
3302	break;
3303
3304	default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
3305	}
3306	break;
3307
3308
3309	default:
3310	AssertReleaseMsgFailed(("enmGuestMode=%d\n", enmGuestMode));
3311	return PGMMODE_INVALID;
3312	}
3313	/* Override the shadow mode is nested paging is active. */
3314	if (HWACCMIsNestedPagingActive(pVM))
3315	enmShadowMode = HWACCMGetShwPagingMode(pVM);
3316
3317	*penmSwitcher = enmSwitcher;
3318	return enmShadowMode;
3319	}
3320
3321
3322	/**
3323	* Performs the actual mode change.
3324	* This is called by PGMChangeMode and pgmR3InitPaging().
3325	*
3326	* @returns VBox status code.
3327	* @param pVM VM handle.
3328	* @param enmGuestMode The new guest mode. This is assumed to be different from
3329	* the current mode.
3330	*/
3331	VMMR3DECL(int) PGMR3ChangeMode(PVM pVM, PGMMODE enmGuestMode)
3332	{
3333	Log(("PGMR3ChangeMode: Guest mode: %s -> %s\n", PGMGetModeName(pVM->pgm.s.enmGuestMode), PGMGetModeName(enmGuestMode)));
3334	STAM_REL_COUNTER_INC(&pVM->pgm.s.cGuestModeChanges);
3335
3336	/*
3337	* Calc the shadow mode and switcher.
3338	*/
3339	VMMSWITCHER enmSwitcher;
3340	PGMMODE enmShadowMode = pgmR3CalcShadowMode(pVM, enmGuestMode, pVM->pgm.s.enmHostMode, pVM->pgm.s.enmShadowMode, &enmSwitcher);
3341	if (enmSwitcher != VMMSWITCHER_INVALID)
3342	{
3343	/*
3344	* Select new switcher.
3345	*/
3346	int rc = VMMR3SelectSwitcher(pVM, enmSwitcher);
3347	if (RT_FAILURE(rc))
3348	{
3349	AssertReleaseMsgFailed(("VMMR3SelectSwitcher(%d) -> %Rrc\n", enmSwitcher, rc));
3350	return rc;
3351	}
3352	}
3353
3354	/*
3355	* Exit old mode(s).
3356	*/
3357	/* shadow */
3358	if (enmShadowMode != pVM->pgm.s.enmShadowMode)
3359	{
3360	LogFlow(("PGMR3ChangeMode: Shadow mode: %s -> %s\n", PGMGetModeName(pVM->pgm.s.enmShadowMode), PGMGetModeName(enmShadowMode)));
3361	if (PGM_SHW_PFN(Exit, pVM))
3362	{
3363	int rc = PGM_SHW_PFN(Exit, pVM)(pVM);
3364	if (RT_FAILURE(rc))
3365	{
3366	AssertMsgFailed(("Exit failed for shadow mode %d: %Rrc\n", pVM->pgm.s.enmShadowMode, rc));
3367	return rc;
3368	}
3369	}
3370
3371	}
3372	else
3373	LogFlow(("PGMR3ChangeMode: Shadow mode remains: %s\n", PGMGetModeName(pVM->pgm.s.enmShadowMode)));
3374
3375	/* guest */
3376	if (PGM_GST_PFN(Exit, pVM))
3377	{
3378	int rc = PGM_GST_PFN(Exit, pVM)(pVM);
3379	if (RT_FAILURE(rc))
3380	{
3381	AssertMsgFailed(("Exit failed for guest mode %d: %Rrc\n", pVM->pgm.s.enmGuestMode, rc));
3382	return rc;
3383	}
3384	}
3385
3386	/*
3387	* Load new paging mode data.
3388	*/
3389	pgmR3ModeDataSwitch(pVM, enmShadowMode, enmGuestMode);
3390
3391	/*
3392	* Enter new shadow mode (if changed).
3393	*/
3394	if (enmShadowMode != pVM->pgm.s.enmShadowMode)
3395	{
3396	int rc;
3397	pVM->pgm.s.enmShadowMode = enmShadowMode;
3398	switch (enmShadowMode)
3399	{
3400	case PGMMODE_32_BIT:
3401	rc = PGM_SHW_NAME_32BIT(Enter)(pVM);
3402	break;
3403	case PGMMODE_PAE:
3404	case PGMMODE_PAE_NX:
3405	rc = PGM_SHW_NAME_PAE(Enter)(pVM);
3406	break;
3407	case PGMMODE_AMD64:
3408	case PGMMODE_AMD64_NX:
3409	rc = PGM_SHW_NAME_AMD64(Enter)(pVM);
3410	break;
3411	case PGMMODE_NESTED:
3412	rc = PGM_SHW_NAME_NESTED(Enter)(pVM);
3413	break;
3414	case PGMMODE_EPT:
3415	rc = PGM_SHW_NAME_EPT(Enter)(pVM);
3416	break;
3417	case PGMMODE_REAL:
3418	case PGMMODE_PROTECTED:
3419	default:
3420	AssertReleaseMsgFailed(("enmShadowMode=%d\n", enmShadowMode));
3421	return VERR_INTERNAL_ERROR;
3422	}
3423	if (RT_FAILURE(rc))
3424	{
3425	AssertReleaseMsgFailed(("Entering enmShadowMode=%d failed: %Rrc\n", enmShadowMode, rc));
3426	pVM->pgm.s.enmShadowMode = PGMMODE_INVALID;
3427	return rc;
3428	}
3429	}
3430
3431	#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
3432	/** @todo This is a bug!
3433	*
3434	* We must flush the PGM pool cache if the guest mode changes; we don't always
3435	* switch shadow paging mode (e.g. protected->32-bit) and shouldn't reuse
3436	* the shadow page tables.
3437	*
3438	* That only applies when switching between paging and non-paging modes.
3439	*/
3440	/** @todo A20 setting */
3441	if ( pVM->pgm.s.CTX_SUFF(pPool)
3442	&& !HWACCMIsNestedPagingActive(pVM)
3443	&& PGMMODE_WITH_PAGING(pVM->pgm.s.enmGuestMode) != PGMMODE_WITH_PAGING(enmGuestMode))
3444	{
3445	Log(("PGMR3ChangeMode: changing guest paging mode -> flush pgm pool cache!\n"));
3446	pgmPoolFlushAll(pVM);
3447	}
3448	#endif
3449
3450	/*
3451	* Enter the new guest and shadow+guest modes.
3452	*/
3453	int rc = -1;
3454	int rc2 = -1;
3455	RTGCPHYS GCPhysCR3 = NIL_RTGCPHYS;
3456	pVM->pgm.s.enmGuestMode = enmGuestMode;
3457	switch (enmGuestMode)
3458	{
3459	case PGMMODE_REAL:
3460	rc = PGM_GST_NAME_REAL(Enter)(pVM, NIL_RTGCPHYS);
3461	switch (pVM->pgm.s.enmShadowMode)
3462	{
3463	case PGMMODE_32_BIT:
3464	rc2 = PGM_BTH_NAME_32BIT_REAL(Enter)(pVM, NIL_RTGCPHYS);
3465	break;
3466	case PGMMODE_PAE:
3467	case PGMMODE_PAE_NX:
3468	rc2 = PGM_BTH_NAME_PAE_REAL(Enter)(pVM, NIL_RTGCPHYS);
3469	break;
3470	case PGMMODE_NESTED:
3471	rc2 = PGM_BTH_NAME_NESTED_REAL(Enter)(pVM, NIL_RTGCPHYS);
3472	break;
3473	case PGMMODE_EPT:
3474	rc2 = PGM_BTH_NAME_EPT_REAL(Enter)(pVM, NIL_RTGCPHYS);
3475	break;
3476	case PGMMODE_AMD64:
3477	case PGMMODE_AMD64_NX:
3478	AssertMsgFailed(("Should use PAE shadow mode!\n"));
3479	default: AssertFailed(); break;
3480	}
3481	break;
3482
3483	case PGMMODE_PROTECTED:
3484	rc = PGM_GST_NAME_PROT(Enter)(pVM, NIL_RTGCPHYS);
3485	switch (pVM->pgm.s.enmShadowMode)
3486	{
3487	case PGMMODE_32_BIT:
3488	rc2 = PGM_BTH_NAME_32BIT_PROT(Enter)(pVM, NIL_RTGCPHYS);
3489	break;
3490	case PGMMODE_PAE:
3491	case PGMMODE_PAE_NX:
3492	rc2 = PGM_BTH_NAME_PAE_PROT(Enter)(pVM, NIL_RTGCPHYS);
3493	break;
3494	case PGMMODE_NESTED:
3495	rc2 = PGM_BTH_NAME_NESTED_PROT(Enter)(pVM, NIL_RTGCPHYS);
3496	break;
3497	case PGMMODE_EPT:
3498	rc2 = PGM_BTH_NAME_EPT_PROT(Enter)(pVM, NIL_RTGCPHYS);
3499	break;
3500	case PGMMODE_AMD64:
3501	case PGMMODE_AMD64_NX:
3502	AssertMsgFailed(("Should use PAE shadow mode!\n"));
3503	default: AssertFailed(); break;
3504	}
3505	break;
3506
3507	case PGMMODE_32_BIT:
3508	GCPhysCR3 = CPUMGetGuestCR3(pVM) & X86_CR3_PAGE_MASK;
3509	rc = PGM_GST_NAME_32BIT(Enter)(pVM, GCPhysCR3);
3510	switch (pVM->pgm.s.enmShadowMode)
3511	{
3512	case PGMMODE_32_BIT:
3513	rc2 = PGM_BTH_NAME_32BIT_32BIT(Enter)(pVM, GCPhysCR3);
3514	break;
3515	case PGMMODE_PAE:
3516	case PGMMODE_PAE_NX:
3517	rc2 = PGM_BTH_NAME_PAE_32BIT(Enter)(pVM, GCPhysCR3);
3518	break;
3519	case PGMMODE_NESTED:
3520	rc2 = PGM_BTH_NAME_NESTED_32BIT(Enter)(pVM, GCPhysCR3);
3521	break;
3522	case PGMMODE_EPT:
3523	rc2 = PGM_BTH_NAME_EPT_32BIT(Enter)(pVM, GCPhysCR3);
3524	break;
3525	case PGMMODE_AMD64:
3526	case PGMMODE_AMD64_NX:
3527	AssertMsgFailed(("Should use PAE shadow mode!\n"));
3528	default: AssertFailed(); break;
3529	}
3530	break;
3531
3532	case PGMMODE_PAE_NX:
3533	case PGMMODE_PAE:
3534	{
3535	uint32_t u32Dummy, u32Features;
3536
3537	CPUMGetGuestCpuId(pVM, 1, &u32Dummy, &u32Dummy, &u32Dummy, &u32Features);
3538	if (!(u32Features & X86_CPUID_FEATURE_EDX_PAE))
3539	{
3540	/* Pause first, then inform Main. */
3541	rc = VMR3SuspendNoSave(pVM);
3542	AssertRC(rc);
3543
3544	VMSetRuntimeError(pVM, true, "PAEmode",
3545	N_("The guest is trying to switch to the PAE mode which is currently disabled by default in VirtualBox. PAE support can be enabled using the VM settings (General/Advanced)"));
3546	/* we must return VINF_SUCCESS here otherwise the recompiler will assert */
3547	return VINF_SUCCESS;
3548	}
3549	GCPhysCR3 = CPUMGetGuestCR3(pVM) & X86_CR3_PAE_PAGE_MASK;
3550	rc = PGM_GST_NAME_PAE(Enter)(pVM, GCPhysCR3);
3551	switch (pVM->pgm.s.enmShadowMode)
3552	{
3553	case PGMMODE_PAE:
3554	case PGMMODE_PAE_NX:
3555	rc2 = PGM_BTH_NAME_PAE_PAE(Enter)(pVM, GCPhysCR3);
3556	break;
3557	case PGMMODE_NESTED:
3558	rc2 = PGM_BTH_NAME_NESTED_PAE(Enter)(pVM, GCPhysCR3);
3559	break;
3560	case PGMMODE_EPT:
3561	rc2 = PGM_BTH_NAME_EPT_PAE(Enter)(pVM, GCPhysCR3);
3562	break;
3563	case PGMMODE_32_BIT:
3564	case PGMMODE_AMD64:
3565	case PGMMODE_AMD64_NX:
3566	AssertMsgFailed(("Should use PAE shadow mode!\n"));
3567	default: AssertFailed(); break;
3568	}
3569	break;
3570	}
3571
3572	#ifdef VBOX_WITH_64_BITS_GUESTS
3573	case PGMMODE_AMD64_NX:
3574	case PGMMODE_AMD64:
3575	GCPhysCR3 = CPUMGetGuestCR3(pVM) & UINT64_C(0xfffffffffffff000); /** @todo define this mask! */
3576	rc = PGM_GST_NAME_AMD64(Enter)(pVM, GCPhysCR3);
3577	switch (pVM->pgm.s.enmShadowMode)
3578	{
3579	case PGMMODE_AMD64:
3580	case PGMMODE_AMD64_NX:
3581	rc2 = PGM_BTH_NAME_AMD64_AMD64(Enter)(pVM, GCPhysCR3);
3582	break;
3583	case PGMMODE_NESTED:
3584	rc2 = PGM_BTH_NAME_NESTED_AMD64(Enter)(pVM, GCPhysCR3);
3585	break;
3586	case PGMMODE_EPT:
3587	rc2 = PGM_BTH_NAME_EPT_AMD64(Enter)(pVM, GCPhysCR3);
3588	break;
3589	case PGMMODE_32_BIT:
3590	case PGMMODE_PAE:
3591	case PGMMODE_PAE_NX:
3592	AssertMsgFailed(("Should use AMD64 shadow mode!\n"));
3593	default: AssertFailed(); break;
3594	}
3595	break;
3596	#endif
3597
3598	default:
3599	AssertReleaseMsgFailed(("enmGuestMode=%d\n", enmGuestMode));
3600	rc = VERR_NOT_IMPLEMENTED;
3601	break;
3602	}
3603
3604	/* status codes. */
3605	AssertRC(rc);
3606	AssertRC(rc2);
3607	if (RT_SUCCESS(rc))
3608	{
3609	rc = rc2;
3610	if (RT_SUCCESS(rc)) /* no informational status codes. */
3611	rc = VINF_SUCCESS;
3612	}
3613
3614	/*
3615	* Notify SELM so it can update the TSSes with correct CR3s.
3616	*/
3617	SELMR3PagingModeChanged(pVM);
3618
3619	/* Notify HWACCM as well. */
3620	HWACCMR3PagingModeChanged(pVM, pVM->pgm.s.enmShadowMode, pVM->pgm.s.enmGuestMode);
3621	return rc;
3622	}
3623
3624
3625	/**
3626	* Dumps a PAE shadow page table.
3627	*
3628	* @returns VBox status code (VINF_SUCCESS).
3629	* @param pVM The VM handle.
3630	* @param pPT Pointer to the page table.
3631	* @param u64Address The virtual address of the page table starts.
3632	* @param fLongMode Set if this a long mode table; clear if it's a legacy mode table.
3633	* @param cMaxDepth The maxium depth.
3634	* @param pHlp Pointer to the output functions.
3635	*/
3636	static int pgmR3DumpHierarchyHCPaePT(PVM pVM, PX86PTPAE pPT, uint64_t u64Address, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
3637	{
3638	for (unsigned i = 0; i < RT_ELEMENTS(pPT->a); i++)
3639	{
3640	X86PTEPAE Pte = pPT->a[i];
3641	if (Pte.n.u1Present)
3642	{
3643	pHlp->pfnPrintf(pHlp,
3644	fLongMode /P R S A D G WT CD AT NX 4M a p ? /
3645	? "%016llx 3 \| P %c %c %c %c %c %s %s %s %s 4K %c%c%c %016llx\n"
3646	: "%08llx 2 \| P %c %c %c %c %c %s %s %s %s 4K %c%c%c %016llx\n",
3647	u64Address + ((uint64_t)i << X86_PT_PAE_SHIFT),
3648	Pte.n.u1Write ? 'W' : 'R',
3649	Pte.n.u1User ? 'U' : 'S',
3650	Pte.n.u1Accessed ? 'A' : '-',
3651	Pte.n.u1Dirty ? 'D' : '-',
3652	Pte.n.u1Global ? 'G' : '-',
3653	Pte.n.u1WriteThru ? "WT" : "--",
3654	Pte.n.u1CacheDisable? "CD" : "--",
3655	Pte.n.u1PAT ? "AT" : "--",
3656	Pte.n.u1NoExecute ? "NX" : "--",
3657	Pte.u & PGM_PTFLAGS_TRACK_DIRTY ? 'd' : '-',
3658	Pte.u & RT_BIT(10) ? '1' : '0',
3659	Pte.u & PGM_PTFLAGS_CSAM_VALIDATED? 'v' : '-',
3660	Pte.u & X86_PTE_PAE_PG_MASK);
3661	}
3662	}
3663	return VINF_SUCCESS;
3664	}
3665
3666
3667	/**
3668	* Dumps a PAE shadow page directory table.
3669	*
3670	* @returns VBox status code (VINF_SUCCESS).
3671	* @param pVM The VM handle.
3672	* @param HCPhys The physical address of the page directory table.
3673	* @param u64Address The virtual address of the page table starts.
3674	* @param cr4 The CR4, PSE is currently used.
3675	* @param fLongMode Set if this a long mode table; clear if it's a legacy mode table.
3676	* @param cMaxDepth The maxium depth.
3677	* @param pHlp Pointer to the output functions.
3678	*/
3679	static int pgmR3DumpHierarchyHCPaePD(PVM pVM, RTHCPHYS HCPhys, uint64_t u64Address, uint32_t cr4, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
3680	{
3681	PX86PDPAE pPD = (PX86PDPAE)MMPagePhys2Page(pVM, HCPhys);
3682	if (!pPD)
3683	{
3684	pHlp->pfnPrintf(pHlp, "%0*llx error! Page directory at HCPhys=%RHp was not found in the page pool!\n",
3685	fLongMode ? 16 : 8, u64Address, HCPhys);
3686	return VERR_INVALID_PARAMETER;
3687	}
3688	const bool fBigPagesSupported = fLongMode \|\| !!(cr4 & X86_CR4_PSE);
3689
3690	int rc = VINF_SUCCESS;
3691	for (unsigned i = 0; i < RT_ELEMENTS(pPD->a); i++)
3692	{
3693	X86PDEPAE Pde = pPD->a[i];
3694	if (Pde.n.u1Present)
3695	{
3696	if (fBigPagesSupported && Pde.b.u1Size)
3697	pHlp->pfnPrintf(pHlp,
3698	fLongMode /P R S A D G WT CD AT NX 4M a p ? /
3699	? "%016llx 2 \| P %c %c %c %c %c %s %s %s %s 4M %c%c%c %016llx\n"
3700	: "%08llx 1 \| P %c %c %c %c %c %s %s %s %s 4M %c%c%c %016llx\n",
3701	u64Address + ((uint64_t)i << X86_PD_PAE_SHIFT),
3702	Pde.b.u1Write ? 'W' : 'R',
3703	Pde.b.u1User ? 'U' : 'S',
3704	Pde.b.u1Accessed ? 'A' : '-',
3705	Pde.b.u1Dirty ? 'D' : '-',
3706	Pde.b.u1Global ? 'G' : '-',
3707	Pde.b.u1WriteThru ? "WT" : "--",
3708	Pde.b.u1CacheDisable? "CD" : "--",
3709	Pde.b.u1PAT ? "AT" : "--",
3710	Pde.b.u1NoExecute ? "NX" : "--",
3711	Pde.u & RT_BIT_64(9) ? '1' : '0',
3712	Pde.u & PGM_PDFLAGS_MAPPING ? 'm' : '-',
3713	Pde.u & PGM_PDFLAGS_TRACK_DIRTY ? 'd' : '-',
3714	Pde.u & X86_PDE_PAE_PG_MASK);
3715	else
3716	{
3717	pHlp->pfnPrintf(pHlp,
3718	fLongMode /P R S A D G WT CD AT NX 4M a p ? /
3719	? "%016llx 2 \| P %c %c %c %c %c %s %s .. %s 4K %c%c%c %016llx\n"
3720	: "%08llx 1 \| P %c %c %c %c %c %s %s .. %s 4K %c%c%c %016llx\n",
3721	u64Address + ((uint64_t)i << X86_PD_PAE_SHIFT),
3722	Pde.n.u1Write ? 'W' : 'R',
3723	Pde.n.u1User ? 'U' : 'S',
3724	Pde.n.u1Accessed ? 'A' : '-',
3725	Pde.n.u1Reserved0 ? '?' : '.', /* ignored */
3726	Pde.n.u1Reserved1 ? '?' : '.', /* ignored */
3727	Pde.n.u1WriteThru ? "WT" : "--",
3728	Pde.n.u1CacheDisable? "CD" : "--",
3729	Pde.n.u1NoExecute ? "NX" : "--",
3730	Pde.u & RT_BIT_64(9) ? '1' : '0',
3731	Pde.u & PGM_PDFLAGS_MAPPING ? 'm' : '-',
3732	Pde.u & PGM_PDFLAGS_TRACK_DIRTY ? 'd' : '-',
3733	Pde.u & X86_PDE_PAE_PG_MASK);
3734	if (cMaxDepth >= 1)
3735	{
3736	/** @todo what about using the page pool for mapping PTs? */
3737	uint64_t u64AddressPT = u64Address + ((uint64_t)i << X86_PD_PAE_SHIFT);
3738	RTHCPHYS HCPhysPT = Pde.u & X86_PDE_PAE_PG_MASK;
3739	PX86PTPAE pPT = NULL;
3740	if (!(Pde.u & PGM_PDFLAGS_MAPPING))
3741	pPT = (PX86PTPAE)MMPagePhys2Page(pVM, HCPhysPT);
3742	else
3743	{
3744	for (PPGMMAPPING pMap = pVM->pgm.s.pMappingsR3; pMap; pMap = pMap->pNextR3)
3745	{
3746	uint64_t off = u64AddressPT - pMap->GCPtr;
3747	if (off < pMap->cb)
3748	{
3749	const int iPDE = (uint32_t)(off >> X86_PD_SHIFT);
3750	const int iSub = (int)((off >> X86_PD_PAE_SHIFT) & 1); /* MSC is a pain sometimes */
3751	if ((iSub ? pMap->aPTs[iPDE].HCPhysPaePT1 : pMap->aPTs[iPDE].HCPhysPaePT0) != HCPhysPT)
3752	pHlp->pfnPrintf(pHlp, "%0*llx error! Mapping error! PT %d has HCPhysPT=%RHp not %RHp is in the PD.\n",
3753	fLongMode ? 16 : 8, u64AddressPT, iPDE,
3754	iSub ? pMap->aPTs[iPDE].HCPhysPaePT1 : pMap->aPTs[iPDE].HCPhysPaePT0, HCPhysPT);
3755	pPT = &pMap->aPTs[iPDE].paPaePTsR3[iSub];
3756	}
3757	}
3758	}
3759	int rc2 = VERR_INVALID_PARAMETER;
3760	if (pPT)
3761	rc2 = pgmR3DumpHierarchyHCPaePT(pVM, pPT, u64AddressPT, fLongMode, cMaxDepth - 1, pHlp);
3762	else
3763	pHlp->pfnPrintf(pHlp, "%0*llx error! Page table at HCPhys=%RHp was not found in the page pool!\n",
3764	fLongMode ? 16 : 8, u64AddressPT, HCPhysPT);
3765	if (rc2 < rc && RT_SUCCESS(rc))
3766	rc = rc2;
3767	}
3768	}
3769	}
3770	}
3771	return rc;
3772	}
3773
3774
3775	/**
3776	* Dumps a PAE shadow page directory pointer table.
3777	*
3778	* @returns VBox status code (VINF_SUCCESS).
3779	* @param pVM The VM handle.
3780	* @param HCPhys The physical address of the page directory pointer table.
3781	* @param u64Address The virtual address of the page table starts.
3782	* @param cr4 The CR4, PSE is currently used.
3783	* @param fLongMode Set if this a long mode table; clear if it's a legacy mode table.
3784	* @param cMaxDepth The maxium depth.
3785	* @param pHlp Pointer to the output functions.
3786	*/
3787	static int pgmR3DumpHierarchyHCPaePDPT(PVM pVM, RTHCPHYS HCPhys, uint64_t u64Address, uint32_t cr4, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
3788	{
3789	PX86PDPT pPDPT = (PX86PDPT)MMPagePhys2Page(pVM, HCPhys);
3790	if (!pPDPT)
3791	{
3792	pHlp->pfnPrintf(pHlp, "%0*llx error! Page directory pointer table at HCPhys=%RHp was not found in the page pool!\n",
3793	fLongMode ? 16 : 8, u64Address, HCPhys);
3794	return VERR_INVALID_PARAMETER;
3795	}
3796
3797	int rc = VINF_SUCCESS;
3798	const unsigned c = fLongMode ? RT_ELEMENTS(pPDPT->a) : X86_PG_PAE_PDPE_ENTRIES;
3799	for (unsigned i = 0; i < c; i++)
3800	{
3801	X86PDPE Pdpe = pPDPT->a[i];
3802	if (Pdpe.n.u1Present)
3803	{
3804	if (fLongMode)
3805	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a p ? /
3806	"%016llx 1 \| P %c %c %c %c %c %s %s %s %s .. %c%c%c %016llx\n",
3807	u64Address + ((uint64_t)i << X86_PDPT_SHIFT),
3808	Pdpe.lm.u1Write ? 'W' : 'R',
3809	Pdpe.lm.u1User ? 'U' : 'S',
3810	Pdpe.lm.u1Accessed ? 'A' : '-',
3811	Pdpe.lm.u3Reserved & 1? '?' : '.', /* ignored */
3812	Pdpe.lm.u3Reserved & 4? '!' : '.', /* mbz */
3813	Pdpe.lm.u1WriteThru ? "WT" : "--",
3814	Pdpe.lm.u1CacheDisable? "CD" : "--",
3815	Pdpe.lm.u3Reserved & 2? "!" : "..",/* mbz */
3816	Pdpe.lm.u1NoExecute ? "NX" : "--",
3817	Pdpe.u & RT_BIT(9) ? '1' : '0',
3818	Pdpe.u & PGM_PLXFLAGS_PERMANENT ? 'p' : '-',
3819	Pdpe.u & RT_BIT(11) ? '1' : '0',
3820	Pdpe.u & X86_PDPE_PG_MASK);
3821	else
3822	pHlp->pfnPrintf(pHlp, /P G WT CD AT NX 4M a p ? /
3823	"%08x 0 \| P %c %s %s %s %s .. %c%c%c %016llx\n",
3824	i << X86_PDPT_SHIFT,
3825	Pdpe.n.u4Reserved & 1? '!' : '.', /* mbz */
3826	Pdpe.n.u4Reserved & 4? '!' : '.', /* mbz */
3827	Pdpe.n.u1WriteThru ? "WT" : "--",
3828	Pdpe.n.u1CacheDisable? "CD" : "--",
3829	Pdpe.n.u4Reserved & 2? "!" : "..",/* mbz */
3830	Pdpe.u & RT_BIT(9) ? '1' : '0',
3831	Pdpe.u & PGM_PLXFLAGS_PERMANENT ? 'p' : '-',
3832	Pdpe.u & RT_BIT(11) ? '1' : '0',
3833	Pdpe.u & X86_PDPE_PG_MASK);
3834	if (cMaxDepth >= 1)
3835	{
3836	int rc2 = pgmR3DumpHierarchyHCPaePD(pVM, Pdpe.u & X86_PDPE_PG_MASK, u64Address + ((uint64_t)i << X86_PDPT_SHIFT),
3837	cr4, fLongMode, cMaxDepth - 1, pHlp);
3838	if (rc2 < rc && RT_SUCCESS(rc))
3839	rc = rc2;
3840	}
3841	}
3842	}
3843	return rc;
3844	}
3845
3846
3847	/**
3848	* Dumps a 32-bit shadow page table.
3849	*
3850	* @returns VBox status code (VINF_SUCCESS).
3851	* @param pVM The VM handle.
3852	* @param HCPhys The physical address of the table.
3853	* @param cr4 The CR4, PSE is currently used.
3854	* @param cMaxDepth The maxium depth.
3855	* @param pHlp Pointer to the output functions.
3856	*/
3857	static int pgmR3DumpHierarchyHcPaePML4(PVM pVM, RTHCPHYS HCPhys, uint32_t cr4, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
3858	{
3859	PX86PML4 pPML4 = (PX86PML4)MMPagePhys2Page(pVM, HCPhys);
3860	if (!pPML4)
3861	{
3862	pHlp->pfnPrintf(pHlp, "Page map level 4 at HCPhys=%RHp was not found in the page pool!\n", HCPhys);
3863	return VERR_INVALID_PARAMETER;
3864	}
3865
3866	int rc = VINF_SUCCESS;
3867	for (unsigned i = 0; i < RT_ELEMENTS(pPML4->a); i++)
3868	{
3869	X86PML4E Pml4e = pPML4->a[i];
3870	if (Pml4e.n.u1Present)
3871	{
3872	uint64_t u64Address = ((uint64_t)i << X86_PML4_SHIFT) \| (((uint64_t)i >> (X86_PML4_SHIFT - X86_PDPT_SHIFT - 1)) * 0xffff000000000000ULL);
3873	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a p ? /
3874	"%016llx 0 \| P %c %c %c %c %c %s %s %s %s .. %c%c%c %016llx\n",
3875	u64Address,
3876	Pml4e.n.u1Write ? 'W' : 'R',
3877	Pml4e.n.u1User ? 'U' : 'S',
3878	Pml4e.n.u1Accessed ? 'A' : '-',
3879	Pml4e.n.u3Reserved & 1? '?' : '.', /* ignored */
3880	Pml4e.n.u3Reserved & 4? '!' : '.', /* mbz */
3881	Pml4e.n.u1WriteThru ? "WT" : "--",
3882	Pml4e.n.u1CacheDisable? "CD" : "--",
3883	Pml4e.n.u3Reserved & 2? "!" : "..",/* mbz */
3884	Pml4e.n.u1NoExecute ? "NX" : "--",
3885	Pml4e.u & RT_BIT(9) ? '1' : '0',
3886	Pml4e.u & PGM_PLXFLAGS_PERMANENT ? 'p' : '-',
3887	Pml4e.u & RT_BIT(11) ? '1' : '0',
3888	Pml4e.u & X86_PML4E_PG_MASK);
3889
3890	if (cMaxDepth >= 1)
3891	{
3892	int rc2 = pgmR3DumpHierarchyHCPaePDPT(pVM, Pml4e.u & X86_PML4E_PG_MASK, u64Address, cr4, true, cMaxDepth - 1, pHlp);
3893	if (rc2 < rc && RT_SUCCESS(rc))
3894	rc = rc2;
3895	}
3896	}
3897	}
3898	return rc;
3899	}
3900
3901
3902	/**
3903	* Dumps a 32-bit shadow page table.
3904	*
3905	* @returns VBox status code (VINF_SUCCESS).
3906	* @param pVM The VM handle.
3907	* @param pPT Pointer to the page table.
3908	* @param u32Address The virtual address this table starts at.
3909	* @param pHlp Pointer to the output functions.
3910	*/
3911	int pgmR3DumpHierarchyHC32BitPT(PVM pVM, PX86PT pPT, uint32_t u32Address, PCDBGFINFOHLP pHlp)
3912	{
3913	for (unsigned i = 0; i < RT_ELEMENTS(pPT->a); i++)
3914	{
3915	X86PTE Pte = pPT->a[i];
3916	if (Pte.n.u1Present)
3917	{
3918	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a m d /
3919	"%08x 1 \| P %c %c %c %c %c %s %s %s .. 4K %c%c%c %08x\n",
3920	u32Address + (i << X86_PT_SHIFT),
3921	Pte.n.u1Write ? 'W' : 'R',
3922	Pte.n.u1User ? 'U' : 'S',
3923	Pte.n.u1Accessed ? 'A' : '-',
3924	Pte.n.u1Dirty ? 'D' : '-',
3925	Pte.n.u1Global ? 'G' : '-',
3926	Pte.n.u1WriteThru ? "WT" : "--",
3927	Pte.n.u1CacheDisable? "CD" : "--",
3928	Pte.n.u1PAT ? "AT" : "--",
3929	Pte.u & PGM_PTFLAGS_TRACK_DIRTY ? 'd' : '-',
3930	Pte.u & RT_BIT(10) ? '1' : '0',
3931	Pte.u & PGM_PTFLAGS_CSAM_VALIDATED ? 'v' : '-',
3932	Pte.u & X86_PDE_PG_MASK);
3933	}
3934	}
3935	return VINF_SUCCESS;
3936	}
3937
3938
3939	/**
3940	* Dumps a 32-bit shadow page directory and page tables.
3941	*
3942	* @returns VBox status code (VINF_SUCCESS).
3943	* @param pVM The VM handle.
3944	* @param cr3 The root of the hierarchy.
3945	* @param cr4 The CR4, PSE is currently used.
3946	* @param cMaxDepth How deep into the hierarchy the dumper should go.
3947	* @param pHlp Pointer to the output functions.
3948	*/
3949	int pgmR3DumpHierarchyHC32BitPD(PVM pVM, uint32_t cr3, uint32_t cr4, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
3950	{
3951	PX86PD pPD = (PX86PD)MMPagePhys2Page(pVM, cr3 & X86_CR3_PAGE_MASK);
3952	if (!pPD)
3953	{
3954	pHlp->pfnPrintf(pHlp, "Page directory at %#x was not found in the page pool!\n", cr3 & X86_CR3_PAGE_MASK);
3955	return VERR_INVALID_PARAMETER;
3956	}
3957
3958	int rc = VINF_SUCCESS;
3959	for (unsigned i = 0; i < RT_ELEMENTS(pPD->a); i++)
3960	{
3961	X86PDE Pde = pPD->a[i];
3962	if (Pde.n.u1Present)
3963	{
3964	const uint32_t u32Address = i << X86_PD_SHIFT;
3965	if ((cr4 & X86_CR4_PSE) && Pde.b.u1Size)
3966	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a m d /
3967	"%08x 0 \| P %c %c %c %c %c %s %s %s .. 4M %c%c%c %08x\n",
3968	u32Address,
3969	Pde.b.u1Write ? 'W' : 'R',
3970	Pde.b.u1User ? 'U' : 'S',
3971	Pde.b.u1Accessed ? 'A' : '-',
3972	Pde.b.u1Dirty ? 'D' : '-',
3973	Pde.b.u1Global ? 'G' : '-',
3974	Pde.b.u1WriteThru ? "WT" : "--",
3975	Pde.b.u1CacheDisable? "CD" : "--",
3976	Pde.b.u1PAT ? "AT" : "--",
3977	Pde.u & RT_BIT_64(9) ? '1' : '0',
3978	Pde.u & PGM_PDFLAGS_MAPPING ? 'm' : '-',
3979	Pde.u & PGM_PDFLAGS_TRACK_DIRTY ? 'd' : '-',
3980	Pde.u & X86_PDE4M_PG_MASK);
3981	else
3982	{
3983	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a m d /
3984	"%08x 0 \| P %c %c %c %c %c %s %s .. .. 4K %c%c%c %08x\n",
3985	u32Address,
3986	Pde.n.u1Write ? 'W' : 'R',
3987	Pde.n.u1User ? 'U' : 'S',
3988	Pde.n.u1Accessed ? 'A' : '-',
3989	Pde.n.u1Reserved0 ? '?' : '.', /* ignored */
3990	Pde.n.u1Reserved1 ? '?' : '.', /* ignored */
3991	Pde.n.u1WriteThru ? "WT" : "--",
3992	Pde.n.u1CacheDisable? "CD" : "--",
3993	Pde.u & RT_BIT_64(9) ? '1' : '0',
3994	Pde.u & PGM_PDFLAGS_MAPPING ? 'm' : '-',
3995	Pde.u & PGM_PDFLAGS_TRACK_DIRTY ? 'd' : '-',
3996	Pde.u & X86_PDE_PG_MASK);
3997	if (cMaxDepth >= 1)
3998	{
3999	/** @todo what about using the page pool for mapping PTs? */
4000	RTHCPHYS HCPhys = Pde.u & X86_PDE_PG_MASK;
4001	PX86PT pPT = NULL;
4002	if (!(Pde.u & PGM_PDFLAGS_MAPPING))
4003	pPT = (PX86PT)MMPagePhys2Page(pVM, HCPhys);
4004	else
4005	{
4006	for (PPGMMAPPING pMap = pVM->pgm.s.pMappingsR3; pMap; pMap = pMap->pNextR3)
4007	if (u32Address - pMap->GCPtr < pMap->cb)
4008	{
4009	int iPDE = (u32Address - pMap->GCPtr) >> X86_PD_SHIFT;
4010	if (pMap->aPTs[iPDE].HCPhysPT != HCPhys)
4011	pHlp->pfnPrintf(pHlp, "%08x error! Mapping error! PT %d has HCPhysPT=%RHp not %RHp is in the PD.\n",
4012	u32Address, iPDE, pMap->aPTs[iPDE].HCPhysPT, HCPhys);
4013	pPT = pMap->aPTs[iPDE].pPTR3;
4014	}
4015	}
4016	int rc2 = VERR_INVALID_PARAMETER;
4017	if (pPT)
4018	rc2 = pgmR3DumpHierarchyHC32BitPT(pVM, pPT, u32Address, pHlp);
4019	else
4020	pHlp->pfnPrintf(pHlp, "%08x error! Page table at %#x was not found in the page pool!\n", u32Address, HCPhys);
4021	if (rc2 < rc && RT_SUCCESS(rc))
4022	rc = rc2;
4023	}
4024	}
4025	}
4026	}
4027
4028	return rc;
4029	}
4030
4031
4032	/**
4033	* Dumps a 32-bit shadow page table.
4034	*
4035	* @returns VBox status code (VINF_SUCCESS).
4036	* @param pVM The VM handle.
4037	* @param pPT Pointer to the page table.
4038	* @param u32Address The virtual address this table starts at.
4039	* @param PhysSearch Address to search for.
4040	*/
4041	int pgmR3DumpHierarchyGC32BitPT(PVM pVM, PX86PT pPT, uint32_t u32Address, RTGCPHYS PhysSearch)
4042	{
4043	for (unsigned i = 0; i < RT_ELEMENTS(pPT->a); i++)
4044	{
4045	X86PTE Pte = pPT->a[i];
4046	if (Pte.n.u1Present)
4047	{
4048	Log(( /P R S A D G WT CD AT NX 4M a m d /
4049	"%08x 1 \| P %c %c %c %c %c %s %s %s .. 4K %c%c%c %08x\n",
4050	u32Address + (i << X86_PT_SHIFT),
4051	Pte.n.u1Write ? 'W' : 'R',
4052	Pte.n.u1User ? 'U' : 'S',
4053	Pte.n.u1Accessed ? 'A' : '-',
4054	Pte.n.u1Dirty ? 'D' : '-',
4055	Pte.n.u1Global ? 'G' : '-',
4056	Pte.n.u1WriteThru ? "WT" : "--",
4057	Pte.n.u1CacheDisable? "CD" : "--",
4058	Pte.n.u1PAT ? "AT" : "--",
4059	Pte.u & PGM_PTFLAGS_TRACK_DIRTY ? 'd' : '-',
4060	Pte.u & RT_BIT(10) ? '1' : '0',
4061	Pte.u & PGM_PTFLAGS_CSAM_VALIDATED ? 'v' : '-',
4062	Pte.u & X86_PDE_PG_MASK));
4063
4064	if ((Pte.u & X86_PDE_PG_MASK) == PhysSearch)
4065	{
4066	uint64_t fPageShw = 0;
4067	RTHCPHYS pPhysHC = 0;
4068
4069	PGMShwGetPage(pVM, (RTGCPTR)(u32Address + (i << X86_PT_SHIFT)), &fPageShw, &pPhysHC);
4070	Log(("Found %RGp at %RGv -> flags=%llx\n", PhysSearch, (RTGCPTR)(u32Address + (i << X86_PT_SHIFT)), fPageShw));
4071	}
4072	}
4073	}
4074	return VINF_SUCCESS;
4075	}
4076
4077
4078	/**
4079	* Dumps a 32-bit guest page directory and page tables.
4080	*
4081	* @returns VBox status code (VINF_SUCCESS).
4082	* @param pVM The VM handle.
4083	* @param cr3 The root of the hierarchy.
4084	* @param cr4 The CR4, PSE is currently used.
4085	* @param PhysSearch Address to search for.
4086	*/
4087	VMMR3DECL(int) PGMR3DumpHierarchyGC(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCPHYS PhysSearch)
4088	{
4089	bool fLongMode = false;
4090	const unsigned cch = fLongMode ? 16 : 8; NOREF(cch);
4091	PX86PD pPD = 0;
4092
4093	int rc = PGM_GCPHYS_2_PTR(pVM, cr3 & X86_CR3_PAGE_MASK, &pPD);
4094	if (RT_FAILURE(rc) \|\| !pPD)
4095	{
4096	Log(("Page directory at %#x was not found in the page pool!\n", cr3 & X86_CR3_PAGE_MASK));
4097	return VERR_INVALID_PARAMETER;
4098	}
4099
4100	Log(("cr3=%08x cr4=%08x%s\n"
4101	"%-*s P - Present\n"
4102	"%-*s \| R/W - Read (0) / Write (1)\n"
4103	"%-*s \| \| U/S - User (1) / Supervisor (0)\n"
4104	"%-*s \| \| \| A - Accessed\n"
4105	"%-*s \| \| \| \| D - Dirty\n"
4106	"%-*s \| \| \| \| \| G - Global\n"
4107	"%-*s \| \| \| \| \| \| WT - Write thru\n"
4108	"%-*s \| \| \| \| \| \| \| CD - Cache disable\n"
4109	"%-*s \| \| \| \| \| \| \| \| AT - Attribute table (PAT)\n"
4110	"%-*s \| \| \| \| \| \| \| \| \| NX - No execute (K8)\n"
4111	"%-*s \| \| \| \| \| \| \| \| \| \| 4K/4M/2M - Page size.\n"
4112	"%-*s \| \| \| \| \| \| \| \| \| \| \| AVL - a=allocated; m=mapping; d=track dirty;\n"
4113	"%-*s \| \| \| \| \| \| \| \| \| \| \| \| p=permanent; v=validated;\n"
4114	"%-*s Level \| \| \| \| \| \| \| \| \| \| \| \| Page\n"
4115	/* xxxx n **** P R S A D G WT CD AT NX 4M AVL xxxxxxxxxxxxx
4116	- W U - - - -- -- -- -- -- 010 */
4117	, cr3, cr4, fLongMode ? " Long Mode" : "",
4118	cch, "", cch, "", cch, "", cch, "", cch, "", cch, "", cch, "",
4119	cch, "", cch, "", cch, "", cch, "", cch, "", cch, "", cch, "Address"));
4120
4121	for (unsigned i = 0; i < RT_ELEMENTS(pPD->a); i++)
4122	{
4123	X86PDE Pde = pPD->a[i];
4124	if (Pde.n.u1Present)
4125	{
4126	const uint32_t u32Address = i << X86_PD_SHIFT;
4127
4128	if ((cr4 & X86_CR4_PSE) && Pde.b.u1Size)
4129	Log(( /P R S A D G WT CD AT NX 4M a m d /
4130	"%08x 0 \| P %c %c %c %c %c %s %s %s .. 4M %c%c%c %08x\n",
4131	u32Address,
4132	Pde.b.u1Write ? 'W' : 'R',
4133	Pde.b.u1User ? 'U' : 'S',
4134	Pde.b.u1Accessed ? 'A' : '-',
4135	Pde.b.u1Dirty ? 'D' : '-',
4136	Pde.b.u1Global ? 'G' : '-',
4137	Pde.b.u1WriteThru ? "WT" : "--",
4138	Pde.b.u1CacheDisable? "CD" : "--",
4139	Pde.b.u1PAT ? "AT" : "--",
4140	Pde.u & RT_BIT(9) ? '1' : '0',
4141	Pde.u & RT_BIT(10) ? '1' : '0',
4142	Pde.u & RT_BIT(11) ? '1' : '0',
4143	pgmGstGet4MBPhysPage(&pVM->pgm.s, Pde)));
4144	/** @todo PhysSearch */
4145	else
4146	{
4147	Log(( /P R S A D G WT CD AT NX 4M a m d /
4148	"%08x 0 \| P %c %c %c %c %c %s %s .. .. 4K %c%c%c %08x\n",
4149	u32Address,
4150	Pde.n.u1Write ? 'W' : 'R',
4151	Pde.n.u1User ? 'U' : 'S',
4152	Pde.n.u1Accessed ? 'A' : '-',
4153	Pde.n.u1Reserved0 ? '?' : '.', /* ignored */
4154	Pde.n.u1Reserved1 ? '?' : '.', /* ignored */
4155	Pde.n.u1WriteThru ? "WT" : "--",
4156	Pde.n.u1CacheDisable? "CD" : "--",
4157	Pde.u & RT_BIT(9) ? '1' : '0',
4158	Pde.u & RT_BIT(10) ? '1' : '0',
4159	Pde.u & RT_BIT(11) ? '1' : '0',
4160	Pde.u & X86_PDE_PG_MASK));
4161	////if (cMaxDepth >= 1)
4162	{
4163	/** @todo what about using the page pool for mapping PTs? */
4164	RTGCPHYS GCPhys = Pde.u & X86_PDE_PG_MASK;
4165	PX86PT pPT = NULL;
4166
4167	rc = PGM_GCPHYS_2_PTR(pVM, GCPhys, &pPT);
4168
4169	int rc2 = VERR_INVALID_PARAMETER;
4170	if (pPT)
4171	rc2 = pgmR3DumpHierarchyGC32BitPT(pVM, pPT, u32Address, PhysSearch);
4172	else
4173	Log(("%08x error! Page table at %#x was not found in the page pool!\n", u32Address, GCPhys));
4174	if (rc2 < rc && RT_SUCCESS(rc))
4175	rc = rc2;
4176	}
4177	}
4178	}
4179	}
4180
4181	return rc;
4182	}
4183
4184
4185	/**
4186	* Dumps a page table hierarchy use only physical addresses and cr4/lm flags.
4187	*
4188	* @returns VBox status code (VINF_SUCCESS).
4189	* @param pVM The VM handle.
4190	* @param cr3 The root of the hierarchy.
4191	* @param cr4 The cr4, only PAE and PSE is currently used.
4192	* @param fLongMode Set if long mode, false if not long mode.
4193	* @param cMaxDepth Number of levels to dump.
4194	* @param pHlp Pointer to the output functions.
4195	*/
4196	VMMR3DECL(int) PGMR3DumpHierarchyHC(PVM pVM, uint64_t cr3, uint64_t cr4, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
4197	{
4198	if (!pHlp)
4199	pHlp = DBGFR3InfoLogHlp();
4200	if (!cMaxDepth)
4201	return VINF_SUCCESS;
4202	const unsigned cch = fLongMode ? 16 : 8;
4203	pHlp->pfnPrintf(pHlp,
4204	"cr3=%08x cr4=%08x%s\n"
4205	"%-*s P - Present\n"
4206	"%-*s \| R/W - Read (0) / Write (1)\n"
4207	"%-*s \| \| U/S - User (1) / Supervisor (0)\n"
4208	"%-*s \| \| \| A - Accessed\n"
4209	"%-*s \| \| \| \| D - Dirty\n"
4210	"%-*s \| \| \| \| \| G - Global\n"
4211	"%-*s \| \| \| \| \| \| WT - Write thru\n"
4212	"%-*s \| \| \| \| \| \| \| CD - Cache disable\n"
4213	"%-*s \| \| \| \| \| \| \| \| AT - Attribute table (PAT)\n"
4214	"%-*s \| \| \| \| \| \| \| \| \| NX - No execute (K8)\n"
4215	"%-*s \| \| \| \| \| \| \| \| \| \| 4K/4M/2M - Page size.\n"
4216	"%-*s \| \| \| \| \| \| \| \| \| \| \| AVL - a=allocated; m=mapping; d=track dirty;\n"
4217	"%-*s \| \| \| \| \| \| \| \| \| \| \| \| p=permanent; v=validated;\n"
4218	"%-*s Level \| \| \| \| \| \| \| \| \| \| \| \| Page\n"
4219	/* xxxx n **** P R S A D G WT CD AT NX 4M AVL xxxxxxxxxxxxx
4220	- W U - - - -- -- -- -- -- 010 */
4221	, cr3, cr4, fLongMode ? " Long Mode" : "",
4222	cch, "", cch, "", cch, "", cch, "", cch, "", cch, "", cch, "",
4223	cch, "", cch, "", cch, "", cch, "", cch, "", cch, "", cch, "Address");
4224	if (cr4 & X86_CR4_PAE)
4225	{
4226	if (fLongMode)
4227	return pgmR3DumpHierarchyHcPaePML4(pVM, cr3 & X86_CR3_PAGE_MASK, cr4, cMaxDepth, pHlp);
4228	return pgmR3DumpHierarchyHCPaePDPT(pVM, cr3 & X86_CR3_PAE_PAGE_MASK, 0, cr4, false, cMaxDepth, pHlp);
4229	}
4230	return pgmR3DumpHierarchyHC32BitPD(pVM, cr3 & X86_CR3_PAGE_MASK, cr4, cMaxDepth, pHlp);
4231	}
4232
4233	#ifdef VBOX_WITH_DEBUGGER
4234
4235	/**
4236	* The '.pgmram' command.
4237	*
4238	* @returns VBox status.
4239	* @param pCmd Pointer to the command descriptor (as registered).
4240	* @param pCmdHlp Pointer to command helper functions.
4241	* @param pVM Pointer to the current VM (if any).
4242	* @param paArgs Pointer to (readonly) array of arguments.
4243	* @param cArgs Number of arguments in the array.
4244	*/
4245	static DECLCALLBACK(int) pgmR3CmdRam(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4246	{
4247	/*
4248	* Validate input.
4249	*/
4250	if (!pVM)
4251	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4252	if (!pVM->pgm.s.pRamRangesRC)
4253	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Sorry, no Ram is registered.\n");
4254
4255	/*
4256	* Dump the ranges.
4257	*/
4258	int rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL, "From - To (incl) pvHC\n");
4259	PPGMRAMRANGE pRam;
4260	for (pRam = pVM->pgm.s.pRamRangesR3; pRam; pRam = pRam->pNextR3)
4261	{
4262	rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL,
4263	"%RGp - %RGp %p\n",
4264	pRam->GCPhys, pRam->GCPhysLast, pRam->pvR3);
4265	if (RT_FAILURE(rc))
4266	return rc;
4267	}
4268
4269	return VINF_SUCCESS;
4270	}
4271
4272
4273	/**
4274	* The '.pgmmap' command.
4275	*
4276	* @returns VBox status.
4277	* @param pCmd Pointer to the command descriptor (as registered).
4278	* @param pCmdHlp Pointer to command helper functions.
4279	* @param pVM Pointer to the current VM (if any).
4280	* @param paArgs Pointer to (readonly) array of arguments.
4281	* @param cArgs Number of arguments in the array.
4282	*/
4283	static DECLCALLBACK(int) pgmR3CmdMap(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4284	{
4285	/*
4286	* Validate input.
4287	*/
4288	if (!pVM)
4289	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4290	if (!pVM->pgm.s.pMappingsR3)
4291	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Sorry, no mappings are registered.\n");
4292
4293	/*
4294	* Print message about the fixedness of the mappings.
4295	*/
4296	int rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL, pVM->pgm.s.fMappingsFixed ? "The mappings are FIXED.\n" : "The mappings are FLOATING.\n");
4297	if (RT_FAILURE(rc))
4298	return rc;
4299
4300	/*
4301	* Dump the ranges.
4302	*/
4303	PPGMMAPPING pCur;
4304	for (pCur = pVM->pgm.s.pMappingsR3; pCur; pCur = pCur->pNextR3)
4305	{
4306	rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL,
4307	"%08x - %08x %s\n",
4308	pCur->GCPtr, pCur->GCPtrLast, pCur->pszDesc);
4309	if (RT_FAILURE(rc))
4310	return rc;
4311	}
4312
4313	return VINF_SUCCESS;
4314	}
4315
4316
4317	/**
4318	* The '.pgmsync' command.
4319	*
4320	* @returns VBox status.
4321	* @param pCmd Pointer to the command descriptor (as registered).
4322	* @param pCmdHlp Pointer to command helper functions.
4323	* @param pVM Pointer to the current VM (if any).
4324	* @param paArgs Pointer to (readonly) array of arguments.
4325	* @param cArgs Number of arguments in the array.
4326	*/
4327	static DECLCALLBACK(int) pgmR3CmdSync(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4328	{
4329	/*
4330	* Validate input.
4331	*/
4332	if (!pVM)
4333	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4334
4335	/*
4336	* Force page directory sync.
4337	*/
4338	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
4339
4340	int rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Forcing page directory sync.\n");
4341	if (RT_FAILURE(rc))
4342	return rc;
4343
4344	return VINF_SUCCESS;
4345	}
4346
4347
4348	#ifdef VBOX_STRICT
4349	/**
4350	* The '.pgmassertcr3' command.
4351	*
4352	* @returns VBox status.
4353	* @param pCmd Pointer to the command descriptor (as registered).
4354	* @param pCmdHlp Pointer to command helper functions.
4355	* @param pVM Pointer to the current VM (if any).
4356	* @param paArgs Pointer to (readonly) array of arguments.
4357	* @param cArgs Number of arguments in the array.
4358	*/
4359	static DECLCALLBACK(int) pgmR3CmdAssertCR3(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4360	{
4361	/*
4362	* Validate input.
4363	*/
4364	if (!pVM)
4365	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4366
4367	int rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Checking shadow CR3 page tables for consistency.\n");
4368	if (RT_FAILURE(rc))
4369	return rc;
4370
4371	PGMAssertCR3(pVM, CPUMGetGuestCR3(pVM), CPUMGetGuestCR4(pVM));
4372
4373	return VINF_SUCCESS;
4374	}
4375	#endif /* VBOX_STRICT */
4376
4377
4378	/**
4379	* The '.pgmsyncalways' command.
4380	*
4381	* @returns VBox status.
4382	* @param pCmd Pointer to the command descriptor (as registered).
4383	* @param pCmdHlp Pointer to command helper functions.
4384	* @param pVM Pointer to the current VM (if any).
4385	* @param paArgs Pointer to (readonly) array of arguments.
4386	* @param cArgs Number of arguments in the array.
4387	*/
4388	static DECLCALLBACK(int) pgmR3CmdSyncAlways(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4389	{
4390	/*
4391	* Validate input.
4392	*/
4393	if (!pVM)
4394	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4395
4396	/*
4397	* Force page directory sync.
4398	*/
4399	if (pVM->pgm.s.fSyncFlags & PGM_SYNC_ALWAYS)
4400	{
4401	ASMAtomicAndU32(&pVM->pgm.s.fSyncFlags, ~PGM_SYNC_ALWAYS);
4402	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Disabled permanent forced page directory syncing.\n");
4403	}
4404	else
4405	{
4406	ASMAtomicOrU32(&pVM->pgm.s.fSyncFlags, PGM_SYNC_ALWAYS);
4407	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
4408	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Enabled permanent forced page directory syncing.\n");
4409	}
4410	}
4411
4412	#endif /* VBOX_WITH_DEBUGGER */
4413
4414	/**
4415	* pvUser argument of the pgmR3CheckIntegrity*Node callbacks.
4416	*/
4417	typedef struct PGMCHECKINTARGS
4418	{
4419	bool fLeftToRight; /*< true: left-to-right; false: right-to-left. /
4420	PPGMPHYSHANDLER pPrevPhys;
4421	PPGMVIRTHANDLER pPrevVirt;
4422	PPGMPHYS2VIRTHANDLER pPrevPhys2Virt;
4423	PVM pVM;
4424	} PGMCHECKINTARGS, *PPGMCHECKINTARGS;
4425
4426	/**
4427	* Validate a node in the physical handler tree.
4428	*
4429	* @returns 0 on if ok, other wise 1.
4430	* @param pNode The handler node.
4431	* @param pvUser pVM.
4432	*/
4433	static DECLCALLBACK(int) pgmR3CheckIntegrityPhysHandlerNode(PAVLROGCPHYSNODECORE pNode, void *pvUser)
4434	{
4435	PPGMCHECKINTARGS pArgs = (PPGMCHECKINTARGS)pvUser;
4436	PPGMPHYSHANDLER pCur = (PPGMPHYSHANDLER)pNode;
4437	AssertReleaseReturn(!((uintptr_t)pCur & 7), 1);
4438	AssertReleaseMsg(pCur->Core.Key <= pCur->Core.KeyLast,("pCur=%p %RGp-%RGp %s\n", pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
4439	AssertReleaseMsg( !pArgs->pPrevPhys
4440	\|\| (pArgs->fLeftToRight ? pArgs->pPrevPhys->Core.KeyLast < pCur->Core.Key : pArgs->pPrevPhys->Core.KeyLast > pCur->Core.Key),
4441	("pPrevPhys=%p %RGp-%RGp %s\n"
4442	" pCur=%p %RGp-%RGp %s\n",
4443	pArgs->pPrevPhys, pArgs->pPrevPhys->Core.Key, pArgs->pPrevPhys->Core.KeyLast, pArgs->pPrevPhys->pszDesc,
4444	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
4445	pArgs->pPrevPhys = pCur;
4446	return 0;
4447	}
4448
4449
4450	/**
4451	* Validate a node in the virtual handler tree.
4452	*
4453	* @returns 0 on if ok, other wise 1.
4454	* @param pNode The handler node.
4455	* @param pvUser pVM.
4456	*/
4457	static DECLCALLBACK(int) pgmR3CheckIntegrityVirtHandlerNode(PAVLROGCPTRNODECORE pNode, void *pvUser)
4458	{
4459	PPGMCHECKINTARGS pArgs = (PPGMCHECKINTARGS)pvUser;
4460	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)pNode;
4461	AssertReleaseReturn(!((uintptr_t)pCur & 7), 1);
4462	AssertReleaseMsg(pCur->Core.Key <= pCur->Core.KeyLast,("pCur=%p %RGv-%RGv %s\n", pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
4463	AssertReleaseMsg( !pArgs->pPrevVirt
4464	\|\| (pArgs->fLeftToRight ? pArgs->pPrevVirt->Core.KeyLast < pCur->Core.Key : pArgs->pPrevVirt->Core.KeyLast > pCur->Core.Key),
4465	("pPrevVirt=%p %RGv-%RGv %s\n"
4466	" pCur=%p %RGv-%RGv %s\n",
4467	pArgs->pPrevVirt, pArgs->pPrevVirt->Core.Key, pArgs->pPrevVirt->Core.KeyLast, pArgs->pPrevVirt->pszDesc,
4468	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
4469	for (unsigned iPage = 0; iPage < pCur->cPages; iPage++)
4470	{
4471	AssertReleaseMsg(pCur->aPhysToVirt[iPage].offVirtHandler == -RT_OFFSETOF(PGMVIRTHANDLER, aPhysToVirt[iPage]),
4472	("pCur=%p %RGv-%RGv %s\n"
4473	"iPage=%d offVirtHandle=%#x expected %#x\n",
4474	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc,
4475	iPage, pCur->aPhysToVirt[iPage].offVirtHandler, -RT_OFFSETOF(PGMVIRTHANDLER, aPhysToVirt[iPage])));
4476	}
4477	pArgs->pPrevVirt = pCur;
4478	return 0;
4479	}
4480
4481
4482	/**
4483	* Validate a node in the virtual handler tree.
4484	*
4485	* @returns 0 on if ok, other wise 1.
4486	* @param pNode The handler node.
4487	* @param pvUser pVM.
4488	*/
4489	static DECLCALLBACK(int) pgmR3CheckIntegrityPhysToVirtHandlerNode(PAVLROGCPHYSNODECORE pNode, void *pvUser)
4490	{
4491	PPGMCHECKINTARGS pArgs = (PPGMCHECKINTARGS)pvUser;
4492	PPGMPHYS2VIRTHANDLER pCur = (PPGMPHYS2VIRTHANDLER)pNode;
4493	AssertReleaseMsgReturn(!((uintptr_t)pCur & 3), ("\n"), 1);
4494	AssertReleaseMsgReturn(!(pCur->offVirtHandler & 3), ("\n"), 1);
4495	AssertReleaseMsg(pCur->Core.Key <= pCur->Core.KeyLast,("pCur=%p %RGp-%RGp\n", pCur, pCur->Core.Key, pCur->Core.KeyLast));
4496	AssertReleaseMsg( !pArgs->pPrevPhys2Virt
4497	\|\| (pArgs->fLeftToRight ? pArgs->pPrevPhys2Virt->Core.KeyLast < pCur->Core.Key : pArgs->pPrevPhys2Virt->Core.KeyLast > pCur->Core.Key),
4498	("pPrevPhys2Virt=%p %RGp-%RGp\n"
4499	" pCur=%p %RGp-%RGp\n",
4500	pArgs->pPrevPhys2Virt, pArgs->pPrevPhys2Virt->Core.Key, pArgs->pPrevPhys2Virt->Core.KeyLast,
4501	pCur, pCur->Core.Key, pCur->Core.KeyLast));
4502	AssertReleaseMsg( !pArgs->pPrevPhys2Virt
4503	\|\| (pArgs->fLeftToRight ? pArgs->pPrevPhys2Virt->Core.KeyLast < pCur->Core.Key : pArgs->pPrevPhys2Virt->Core.KeyLast > pCur->Core.Key),
4504	("pPrevPhys2Virt=%p %RGp-%RGp\n"
4505	" pCur=%p %RGp-%RGp\n",
4506	pArgs->pPrevPhys2Virt, pArgs->pPrevPhys2Virt->Core.Key, pArgs->pPrevPhys2Virt->Core.KeyLast,
4507	pCur, pCur->Core.Key, pCur->Core.KeyLast));
4508	AssertReleaseMsg((pCur->offNextAlias & (PGMPHYS2VIRTHANDLER_IN_TREE \| PGMPHYS2VIRTHANDLER_IS_HEAD)) == (PGMPHYS2VIRTHANDLER_IN_TREE \| PGMPHYS2VIRTHANDLER_IS_HEAD),
4509	("pCur=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4510	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias));
4511	if (pCur->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK)
4512	{
4513	PPGMPHYS2VIRTHANDLER pCur2 = pCur;
4514	for (;;)
4515	{
4516	pCur2 = (PPGMPHYS2VIRTHANDLER)((intptr_t)pCur + (pCur->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK));
4517	AssertReleaseMsg(pCur2 != pCur,
4518	(" pCur=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4519	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias));
4520	AssertReleaseMsg((pCur2->offNextAlias & (PGMPHYS2VIRTHANDLER_IN_TREE \| PGMPHYS2VIRTHANDLER_IS_HEAD)) == PGMPHYS2VIRTHANDLER_IN_TREE,
4521	(" pCur=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
4522	"pCur2=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4523	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias,
4524	pCur2, pCur2->Core.Key, pCur2->Core.KeyLast, pCur2->offVirtHandler, pCur2->offNextAlias));
4525	AssertReleaseMsg((pCur2->Core.Key ^ pCur->Core.Key) < PAGE_SIZE,
4526	(" pCur=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
4527	"pCur2=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4528	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias,
4529	pCur2, pCur2->Core.Key, pCur2->Core.KeyLast, pCur2->offVirtHandler, pCur2->offNextAlias));
4530	AssertReleaseMsg((pCur2->Core.KeyLast ^ pCur->Core.KeyLast) < PAGE_SIZE,
4531	(" pCur=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
4532	"pCur2=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4533	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias,
4534	pCur2, pCur2->Core.Key, pCur2->Core.KeyLast, pCur2->offVirtHandler, pCur2->offNextAlias));
4535	if (!(pCur2->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK))
4536	break;
4537	}
4538	}
4539
4540	pArgs->pPrevPhys2Virt = pCur;
4541	return 0;
4542	}
4543
4544
4545	/**
4546	* Perform an integrity check on the PGM component.
4547	*
4548	* @returns VINF_SUCCESS if everything is fine.
4549	* @returns VBox error status after asserting on integrity breach.
4550	* @param pVM The VM handle.
4551	*/
4552	VMMR3DECL(int) PGMR3CheckIntegrity(PVM pVM)
4553	{
4554	AssertReleaseReturn(pVM->pgm.s.offVM, VERR_INTERNAL_ERROR);
4555
4556	/*
4557	* Check the trees.
4558	*/
4559	int cErrors = 0;
4560	const static PGMCHECKINTARGS s_LeftToRight = { true, NULL, NULL, NULL, pVM };
4561	const static PGMCHECKINTARGS s_RightToLeft = { false, NULL, NULL, NULL, pVM };
4562	PGMCHECKINTARGS Args = s_LeftToRight;
4563	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysHandlers, true, pgmR3CheckIntegrityPhysHandlerNode, &Args);
4564	Args = s_RightToLeft;
4565	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysHandlers, false, pgmR3CheckIntegrityPhysHandlerNode, &Args);
4566	Args = s_LeftToRight;
4567	cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesR3->VirtHandlers, true, pgmR3CheckIntegrityVirtHandlerNode, &Args);
4568	Args = s_RightToLeft;
4569	cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesR3->VirtHandlers, false, pgmR3CheckIntegrityVirtHandlerNode, &Args);
4570	Args = s_LeftToRight;
4571	cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesR3->HyperVirtHandlers, true, pgmR3CheckIntegrityVirtHandlerNode, &Args);
4572	Args = s_RightToLeft;
4573	cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesR3->HyperVirtHandlers, false, pgmR3CheckIntegrityVirtHandlerNode, &Args);
4574	Args = s_LeftToRight;
4575	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysToVirtHandlers, true, pgmR3CheckIntegrityPhysToVirtHandlerNode, &Args);
4576	Args = s_RightToLeft;
4577	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysToVirtHandlers, false, pgmR3CheckIntegrityPhysToVirtHandlerNode, &Args);
4578
4579	return !cErrors ? VINF_SUCCESS : VERR_INTERNAL_ERROR;
4580	}
4581
4582

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source: vbox/trunk/src/VBox/VMM/PGM.cpp@ 16416

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