PGM.cpp@ 17493

Last change on this file since 17493 was 17492, checked in by vboxsync, 16 years ago
Bugfix
Property svn:eol-style set to `native` Property svn:keywords set to `Id`
File size: 220.2 KB

Line
1	/* $Id: PGM.cpp 17492 2009-03-06 16:41:25Z vboxsync $ */
2	/** @file
3	* PGM - Page Manager and Monitor. (Mixing stuff here, not good?)
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22
23	/** @page pg_pgm PGM - The Page Manager and Monitor
24	*
25	* @see grp_pgm,
26	* @ref pg_pgm_pool,
27	* @ref pg_pgm_phys.
28	*
29	*
30	* @section sec_pgm_modes Paging Modes
31	*
32	* There are three memory contexts: Host Context (HC), Guest Context (GC)
33	* and intermediate context. When talking about paging HC can also be refered to
34	* as "host paging", and GC refered to as "shadow paging".
35	*
36	* We define three basic paging modes: 32-bit, PAE and AMD64. The host paging mode
37	* is defined by the host operating system. The mode used in the shadow paging mode
38	* depends on the host paging mode and what the mode the guest is currently in. The
39	* following relation between the two is defined:
40	*
41	* @verbatim
42	Host > 32-bit \| PAE \| AMD64 \|
43	Guest \| \| \| \|
44	==v================================
45	32-bit 32-bit PAE PAE
46	-------\|--------\|--------\|--------\|
47	PAE PAE PAE PAE
48	-------\|--------\|--------\|--------\|
49	AMD64 AMD64 AMD64 AMD64
50	-------\|--------\|--------\|--------\| @endverbatim
51	*
52	* All configuration except those in the diagonal (upper left) are expected to
53	* require special effort from the switcher (i.e. a bit slower).
54	*
55	*
56	*
57	*
58	* @section sec_pgm_shw The Shadow Memory Context
59	*
60	*
61	* [..]
62	*
63	* Because of guest context mappings requires PDPT and PML4 entries to allow
64	* writing on AMD64, the two upper levels will have fixed flags whatever the
65	* guest is thinking of using there. So, when shadowing the PD level we will
66	* calculate the effective flags of PD and all the higher levels. In legacy
67	* PAE mode this only applies to the PWT and PCD bits (the rest are
68	* ignored/reserved/MBZ). We will ignore those bits for the present.
69	*
70	*
71	*
72	* @section sec_pgm_int The Intermediate Memory Context
73	*
74	* The world switch goes thru an intermediate memory context which purpose it is
75	* to provide different mappings of the switcher code. All guest mappings are also
76	* present in this context.
77	*
78	* The switcher code is mapped at the same location as on the host, at an
79	* identity mapped location (physical equals virtual address), and at the
80	* hypervisor location. The identity mapped location is for when the world
81	* switches that involves disabling paging.
82	*
83	* PGM maintain page tables for 32-bit, PAE and AMD64 paging modes. This
84	* simplifies switching guest CPU mode and consistency at the cost of more
85	* code to do the work. All memory use for those page tables is located below
86	* 4GB (this includes page tables for guest context mappings).
87	*
88	*
89	* @subsection subsec_pgm_int_gc Guest Context Mappings
90	*
91	* During assignment and relocation of a guest context mapping the intermediate
92	* memory context is used to verify the new location.
93	*
94	* Guest context mappings are currently restricted to below 4GB, for reasons
95	* of simplicity. This may change when we implement AMD64 support.
96	*
97	*
98	*
99	*
100	* @section sec_pgm_misc Misc
101	*
102	* @subsection subsec_pgm_misc_diff Differences Between Legacy PAE and Long Mode PAE
103	*
104	* The differences between legacy PAE and long mode PAE are:
105	* -# PDPE bits 1, 2, 5 and 6 are defined differently. In leagcy mode they are
106	* all marked down as must-be-zero, while in long mode 1, 2 and 5 have the
107	* usual meanings while 6 is ignored (AMD). This means that upon switching to
108	* legacy PAE mode we'll have to clear these bits and when going to long mode
109	* they must be set. This applies to both intermediate and shadow contexts,
110	* however we don't need to do it for the intermediate one since we're
111	* executing with CR0.WP at that time.
112	* -# CR3 allows a 32-byte aligned address in legacy mode, while in long mode
113	* a page aligned one is required.
114	*
115	*
116	* @section sec_pgm_handlers Access Handlers
117	*
118	* Placeholder.
119	*
120	*
121	* @subsection sec_pgm_handlers_virt Virtual Access Handlers
122	*
123	* Placeholder.
124	*
125	*
126	* @subsection sec_pgm_handlers_virt Virtual Access Handlers
127	*
128	* We currently implement three types of virtual access handlers: ALL, WRITE
129	* and HYPERVISOR (WRITE). See PGMVIRTHANDLERTYPE for some more details.
130	*
131	* The HYPERVISOR access handlers is kept in a separate tree since it doesn't apply
132	* to physical pages (PGMTREES::HyperVirtHandlers) and only needs to be consulted in
133	* a special \#PF case. The ALL and WRITE are in the PGMTREES::VirtHandlers tree, the
134	* rest of this section is going to be about these handlers.
135	*
136	* We'll go thru the life cycle of a handler and try make sense of it all, don't know
137	* how successfull this is gonna be...
138	*
139	* 1. A handler is registered thru the PGMR3HandlerVirtualRegister and
140	* PGMHandlerVirtualRegisterEx APIs. We check for conflicting virtual handlers
141	* and create a new node that is inserted into the AVL tree (range key). Then
142	* a full PGM resync is flagged (clear pool, sync cr3, update virtual bit of PGMPAGE).
143	*
144	* 2. The following PGMSyncCR3/SyncCR3 operation will first make invoke HandlerVirtualUpdate.
145	*
146	* 2a. HandlerVirtualUpdate will will lookup all the pages covered by virtual handlers
147	* via the current guest CR3 and update the physical page -> virtual handler
148	* translation. Needless to say, this doesn't exactly scale very well. If any changes
149	* are detected, it will flag a virtual bit update just like we did on registration.
150	* PGMPHYS pages with changes will have their virtual handler state reset to NONE.
151	*
152	* 2b. The virtual bit update process will iterate all the pages covered by all the
153	* virtual handlers and update the PGMPAGE virtual handler state to the max of all
154	* virtual handlers on that page.
155	*
156	* 2c. Back in SyncCR3 we will now flush the entire shadow page cache to make sure
157	* we don't miss any alias mappings of the monitored pages.
158	*
159	* 2d. SyncCR3 will then proceed with syncing the CR3 table.
160	*
161	* 3. \#PF(np,read) on a page in the range. This will cause it to be synced
162	* read-only and resumed if it's a WRITE handler. If it's an ALL handler we
163	* will call the handlers like in the next step. If the physical mapping has
164	* changed we will - some time in the future - perform a handler callback
165	* (optional) and update the physical -> virtual handler cache.
166	*
167	* 4. \#PF(,write) on a page in the range. This will cause the handler to
168	* be invoked.
169	*
170	* 5. The guest invalidates the page and changes the physical backing or
171	* unmaps it. This should cause the invalidation callback to be invoked
172	* (it might not yet be 100% perfect). Exactly what happens next... is
173	* this where we mess up and end up out of sync for a while?
174	*
175	* 6. The handler is deregistered by the client via PGMHandlerVirtualDeregister.
176	* We will then set all PGMPAGEs in the physical -> virtual handler cache for
177	* this handler to NONE and trigger a full PGM resync (basically the same
178	* as int step 1). Which means 2 is executed again.
179	*
180	*
181	* @subsubsection sub_sec_pgm_handler_virt_todo TODOs
182	*
183	* There is a bunch of things that needs to be done to make the virtual handlers
184	* work 100% correctly and work more efficiently.
185	*
186	* The first bit hasn't been implemented yet because it's going to slow the
187	* whole mess down even more, and besides it seems to be working reliably for
188	* our current uses. OTOH, some of the optimizations might end up more or less
189	* implementing the missing bits, so we'll see.
190	*
191	* On the optimization side, the first thing to do is to try avoid unnecessary
192	* cache flushing. Then try team up with the shadowing code to track changes
193	* in mappings by means of access to them (shadow in), updates to shadows pages,
194	* invlpg, and shadow PT discarding (perhaps).
195	*
196	* Some idea that have popped up for optimization for current and new features:
197	* - bitmap indicating where there are virtual handlers installed.
198	* (4KB => 220 pages, page 212 => covers 32-bit address space 1:1!)
199	* - Further optimize this by min/max (needs min/max avl getters).
200	* - Shadow page table entry bit (if any left)?
201	*
202	*/
203
204
205	/** @page pg_pgm_phys PGM Physical Guest Memory Management
206	*
207	*
208	* Objectives:
209	* - Guest RAM over-commitment using memory ballooning,
210	* zero pages and general page sharing.
211	* - Moving or mirroring a VM onto a different physical machine.
212	*
213	*
214	* @subsection subsec_pgmPhys_Definitions Definitions
215	*
216	* Allocation chunk - A RTR0MemObjAllocPhysNC object and the tracking
217	* machinery assoicated with it.
218	*
219	*
220	*
221	*
222	* @subsection subsec_pgmPhys_AllocPage Allocating a page.
223	*
224	* Initially we map all guest memory to the (per VM) zero page, which
225	* means that none of the read functions will cause pages to be allocated.
226	*
227	* Exception, access bit in page tables that have been shared. This must
228	* be handled, but we must also make sure PGMGst*Modify doesn't make
229	* unnecessary modifications.
230	*
231	* Allocation points:
232	* - PGMPhysSimpleWriteGCPhys and PGMPhysWrite.
233	* - Replacing a zero page mapping at \#PF.
234	* - Replacing a shared page mapping at \#PF.
235	* - ROM registration (currently MMR3RomRegister).
236	* - VM restore (pgmR3Load).
237	*
238	* For the first three it would make sense to keep a few pages handy
239	* until we've reached the max memory commitment for the VM.
240	*
241	* For the ROM registration, we know exactly how many pages we need
242	* and will request these from ring-0. For restore, we will save
243	* the number of non-zero pages in the saved state and allocate
244	* them up front. This would allow the ring-0 component to refuse
245	* the request if the isn't sufficient memory available for VM use.
246	*
247	* Btw. for both ROM and restore allocations we won't be requiring
248	* zeroed pages as they are going to be filled instantly.
249	*
250	*
251	* @subsection subsec_pgmPhys_FreePage Freeing a page
252	*
253	* There are a few points where a page can be freed:
254	* - After being replaced by the zero page.
255	* - After being replaced by a shared page.
256	* - After being ballooned by the guest additions.
257	* - At reset.
258	* - At restore.
259	*
260	* When freeing one or more pages they will be returned to the ring-0
261	* component and replaced by the zero page.
262	*
263	* The reasoning for clearing out all the pages on reset is that it will
264	* return us to the exact same state as on power on, and may thereby help
265	* us reduce the memory load on the system. Further it might have a
266	* (temporary) positive influence on memory fragmentation (@see subsec_pgmPhys_Fragmentation).
267	*
268	* On restore, as mention under the allocation topic, pages should be
269	* freed / allocated depending on how many is actually required by the
270	* new VM state. The simplest approach is to do like on reset, and free
271	* all non-ROM pages and then allocate what we need.
272	*
273	* A measure to prevent some fragmentation, would be to let each allocation
274	* chunk have some affinity towards the VM having allocated the most pages
275	* from it. Also, try make sure to allocate from allocation chunks that
276	* are almost full. Admittedly, both these measures might work counter to
277	* our intentions and its probably not worth putting a lot of effort,
278	* cpu time or memory into this.
279	*
280	*
281	* @subsection subsec_pgmPhys_SharePage Sharing a page
282	*
283	* The basic idea is that there there will be a idle priority kernel
284	* thread walking the non-shared VM pages hashing them and looking for
285	* pages with the same checksum. If such pages are found, it will compare
286	* them byte-by-byte to see if they actually are identical. If found to be
287	* identical it will allocate a shared page, copy the content, check that
288	* the page didn't change while doing this, and finally request both the
289	* VMs to use the shared page instead. If the page is all zeros (special
290	* checksum and byte-by-byte check) it will request the VM that owns it
291	* to replace it with the zero page.
292	*
293	* To make this efficient, we will have to make sure not to try share a page
294	* that will change its contents soon. This part requires the most work.
295	* A simple idea would be to request the VM to write monitor the page for
296	* a while to make sure it isn't modified any time soon. Also, it may
297	* make sense to skip pages that are being write monitored since this
298	* information is readily available to the thread if it works on the
299	* per-VM guest memory structures (presently called PGMRAMRANGE).
300	*
301	*
302	* @subsection subsec_pgmPhys_Fragmentation Fragmentation Concerns and Counter Measures
303	*
304	* The pages are organized in allocation chunks in ring-0, this is a necessity
305	* if we wish to have an OS agnostic approach to this whole thing. (On Linux we
306	* could easily work on a page-by-page basis if we liked. Whether this is possible
307	* or efficient on NT I don't quite know.) Fragmentation within these chunks may
308	* become a problem as part of the idea here is that we wish to return memory to
309	* the host system.
310	*
311	* For instance, starting two VMs at the same time, they will both allocate the
312	* guest memory on-demand and if permitted their page allocations will be
313	* intermixed. Shut down one of the two VMs and it will be difficult to return
314	* any memory to the host system because the page allocation for the two VMs are
315	* mixed up in the same allocation chunks.
316	*
317	* To further complicate matters, when pages are freed because they have been
318	* ballooned or become shared/zero the whole idea is that the page is supposed
319	* to be reused by another VM or returned to the host system. This will cause
320	* allocation chunks to contain pages belonging to different VMs and prevent
321	* returning memory to the host when one of those VM shuts down.
322	*
323	* The only way to really deal with this problem is to move pages. This can
324	* either be done at VM shutdown and or by the idle priority worker thread
325	* that will be responsible for finding sharable/zero pages. The mechanisms
326	* involved for coercing a VM to move a page (or to do it for it) will be
327	* the same as when telling it to share/zero a page.
328	*
329	*
330	* @subsection subsec_pgmPhys_Tracking Tracking Structures And Their Cost
331	*
332	* There's a difficult balance between keeping the per-page tracking structures
333	* (global and guest page) easy to use and keeping them from eating too much
334	* memory. We have limited virtual memory resources available when operating in
335	* 32-bit kernel space (on 64-bit there'll it's quite a different story). The
336	* tracking structures will be attemted designed such that we can deal with up
337	* to 32GB of memory on a 32-bit system and essentially unlimited on 64-bit ones.
338	*
339	*
340	* @subsubsection subsubsec_pgmPhys_Tracking_Kernel Kernel Space
341	*
342	* @see pg_GMM
343	*
344	* @subsubsection subsubsec_pgmPhys_Tracking_PerVM Per-VM
345	*
346	* Fixed info is the physical address of the page (HCPhys) and the page id
347	* (described above). Theoretically we'll need 48(-12) bits for the HCPhys part.
348	* Today we've restricting ourselves to 40(-12) bits because this is the current
349	* restrictions of all AMD64 implementations (I think Barcelona will up this
350	* to 48(-12) bits, not that it really matters) and I needed the bits for
351	* tracking mappings of a page. 48-12 = 36. That leaves 28 bits, which means a
352	* decent range for the page id: 2^(28+12) = 1024TB.
353	*
354	* In additions to these, we'll have to keep maintaining the page flags as we
355	* currently do. Although it wouldn't harm to optimize these quite a bit, like
356	* for instance the ROM shouldn't depend on having a write handler installed
357	* in order for it to become read-only. A RO/RW bit should be considered so
358	* that the page syncing code doesn't have to mess about checking multiple
359	* flag combinations (ROM \|\| RW handler \|\| write monitored) in order to
360	* figure out how to setup a shadow PTE. But this of course, is second
361	* priority at present. Current this requires 12 bits, but could probably
362	* be optimized to ~8.
363	*
364	* Then there's the 24 bits used to track which shadow page tables are
365	* currently mapping a page for the purpose of speeding up physical
366	* access handlers, and thereby the page pool cache. More bit for this
367	* purpose wouldn't hurt IIRC.
368	*
369	* Then there is a new bit in which we need to record what kind of page
370	* this is, shared, zero, normal or write-monitored-normal. This'll
371	* require 2 bits. One bit might be needed for indicating whether a
372	* write monitored page has been written to. And yet another one or
373	* two for tracking migration status. 3-4 bits total then.
374	*
375	* Whatever is left will can be used to record the sharabilitiy of a
376	* page. The page checksum will not be stored in the per-VM table as
377	* the idle thread will not be permitted to do modifications to it.
378	* It will instead have to keep its own working set of potentially
379	* shareable pages and their check sums and stuff.
380	*
381	* For the present we'll keep the current packing of the
382	* PGMRAMRANGE::aHCPhys to keep the changes simple, only of course,
383	* we'll have to change it to a struct with a total of 128-bits at
384	* our disposal.
385	*
386	* The initial layout will be like this:
387	* @verbatim
388	RTHCPHYS HCPhys; The current stuff.
389	63:40 Current shadow PT tracking stuff.
390	39:12 The physical page frame number.
391	11:0 The current flags.
392	uint32_t u28PageId : 28; The page id.
393	uint32_t u2State : 2; The page state { zero, shared, normal, write monitored }.
394	uint32_t fWrittenTo : 1; Whether a write monitored page was written to.
395	uint32_t u1Reserved : 1; Reserved for later.
396	uint32_t u32Reserved; Reserved for later, mostly sharing stats.
397	@endverbatim
398	*
399	* The final layout will be something like this:
400	* @verbatim
401	RTHCPHYS HCPhys; The current stuff.
402	63:48 High page id (12+).
403	47:12 The physical page frame number.
404	11:0 Low page id.
405	uint32_t fReadOnly : 1; Whether it's readonly page (rom or monitored in some way).
406	uint32_t u3Type : 3; The page type {RESERVED, MMIO, MMIO2, ROM, shadowed ROM, RAM}.
407	uint32_t u2PhysMon : 2; Physical access handler type {none, read, write, all}.
408	uint32_t u2VirtMon : 2; Virtual access handler type {none, read, write, all}..
409	uint32_t u2State : 2; The page state { zero, shared, normal, write monitored }.
410	uint32_t fWrittenTo : 1; Whether a write monitored page was written to.
411	uint32_t u20Reserved : 20; Reserved for later, mostly sharing stats.
412	uint32_t u32Tracking; The shadow PT tracking stuff, roughly.
413	@endverbatim
414	*
415	* Cost wise, this means we'll double the cost for guest memory. There isn't anyway
416	* around that I'm afraid. It means that the cost of dealing out 32GB of memory
417	* to one or more VMs is: (32GB >> PAGE_SHIFT) * 16 bytes, or 128MBs. Or another
418	* example, the VM heap cost when assigning 1GB to a VM will be: 4MB.
419	*
420	* A couple of cost examples for the total cost per-VM + kernel.
421	* 32-bit Windows and 32-bit linux:
422	* 1GB guest ram, 256K pages: 4MB + 2MB(+) = 6MB
423	* 4GB guest ram, 1M pages: 16MB + 8MB(+) = 24MB
424	* 32GB guest ram, 8M pages: 128MB + 64MB(+) = 192MB
425	* 64-bit Windows and 64-bit linux:
426	* 1GB guest ram, 256K pages: 4MB + 3MB(+) = 7MB
427	* 4GB guest ram, 1M pages: 16MB + 12MB(+) = 28MB
428	* 32GB guest ram, 8M pages: 128MB + 96MB(+) = 224MB
429	*
430	* UPDATE - 2007-09-27:
431	* Will need a ballooned flag/state too because we cannot
432	* trust the guest 100% and reporting the same page as ballooned more
433	* than once will put the GMM off balance.
434	*
435	*
436	* @subsection subsec_pgmPhys_Serializing Serializing Access
437	*
438	* Initially, we'll try a simple scheme:
439	*
440	* - The per-VM RAM tracking structures (PGMRAMRANGE) is only modified
441	* by the EMT thread of that VM while in the pgm critsect.
442	* - Other threads in the VM process that needs to make reliable use of
443	* the per-VM RAM tracking structures will enter the critsect.
444	* - No process external thread or kernel thread will ever try enter
445	* the pgm critical section, as that just won't work.
446	* - The idle thread (and similar threads) doesn't not need 100% reliable
447	* data when performing it tasks as the EMT thread will be the one to
448	* do the actual changes later anyway. So, as long as it only accesses
449	* the main ram range, it can do so by somehow preventing the VM from
450	* being destroyed while it works on it...
451	*
452	* - The over-commitment management, including the allocating/freeing
453	* chunks, is serialized by a ring-0 mutex lock (a fast one since the
454	* more mundane mutex implementation is broken on Linux).
455	* - A separeate mutex is protecting the set of allocation chunks so
456	* that pages can be shared or/and freed up while some other VM is
457	* allocating more chunks. This mutex can be take from under the other
458	* one, but not the otherway around.
459	*
460	*
461	* @subsection subsec_pgmPhys_Request VM Request interface
462	*
463	* When in ring-0 it will become necessary to send requests to a VM so it can
464	* for instance move a page while defragmenting during VM destroy. The idle
465	* thread will make use of this interface to request VMs to setup shared
466	* pages and to perform write monitoring of pages.
467	*
468	* I would propose an interface similar to the current VMReq interface, similar
469	* in that it doesn't require locking and that the one sending the request may
470	* wait for completion if it wishes to. This shouldn't be very difficult to
471	* realize.
472	*
473	* The requests themselves are also pretty simple. They are basically:
474	* -# Check that some precondition is still true.
475	* -# Do the update.
476	* -# Update all shadow page tables involved with the page.
477	*
478	* The 3rd step is identical to what we're already doing when updating a
479	* physical handler, see pgmHandlerPhysicalSetRamFlagsAndFlushShadowPTs.
480	*
481	*
482	*
483	* @section sec_pgmPhys_MappingCaches Mapping Caches
484	*
485	* In order to be able to map in and out memory and to be able to support
486	* guest with more RAM than we've got virtual address space, we'll employing
487	* a mapping cache. There is already a tiny one for GC (see PGMGCDynMapGCPageEx)
488	* and we'll create a similar one for ring-0 unless we decide to setup a dedicate
489	* memory context for the HWACCM execution.
490	*
491	*
492	* @subsection subsec_pgmPhys_MappingCaches_R3 Ring-3
493	*
494	* We've considered implementing the ring-3 mapping cache page based but found
495	* that this was bother some when one had to take into account TLBs+SMP and
496	* portability (missing the necessary APIs on several platforms). There were
497	* also some performance concerns with this approach which hadn't quite been
498	* worked out.
499	*
500	* Instead, we'll be mapping allocation chunks into the VM process. This simplifies
501	* matters greatly quite a bit since we don't need to invent any new ring-0 stuff,
502	* only some minor RTR0MEMOBJ mapping stuff. The main concern here is that mapping
503	* compared to the previous idea is that mapping or unmapping a 1MB chunk is more
504	* costly than a single page, although how much more costly is uncertain. We'll
505	* try address this by using a very big cache, preferably bigger than the actual
506	* VM RAM size if possible. The current VM RAM sizes should give some idea for
507	* 32-bit boxes, while on 64-bit we can probably get away with employing an
508	* unlimited cache.
509	*
510	* The cache have to parts, as already indicated, the ring-3 side and the
511	* ring-0 side.
512	*
513	* The ring-0 will be tied to the page allocator since it will operate on the
514	* memory objects it contains. It will therefore require the first ring-0 mutex
515	* discussed in @ref subsec_pgmPhys_Serializing. We
516	* some double house keeping wrt to who has mapped what I think, since both
517	* VMMR0.r0 and RTR0MemObj will keep track of mapping relataions
518	*
519	* The ring-3 part will be protected by the pgm critsect. For simplicity, we'll
520	* require anyone that desires to do changes to the mapping cache to do that
521	* from within this critsect. Alternatively, we could employ a separate critsect
522	* for serializing changes to the mapping cache as this would reduce potential
523	* contention with other threads accessing mappings unrelated to the changes
524	* that are in process. We can see about this later, contention will show
525	* up in the statistics anyway, so it'll be simple to tell.
526	*
527	* The organization of the ring-3 part will be very much like how the allocation
528	* chunks are organized in ring-0, that is in an AVL tree by chunk id. To avoid
529	* having to walk the tree all the time, we'll have a couple of lookaside entries
530	* like in we do for I/O ports and MMIO in IOM.
531	*
532	* The simplified flow of a PGMPhysRead/Write function:
533	* -# Enter the PGM critsect.
534	* -# Lookup GCPhys in the ram ranges and get the Page ID.
535	* -# Calc the Allocation Chunk ID from the Page ID.
536	* -# Check the lookaside entries and then the AVL tree for the Chunk ID.
537	* If not found in cache:
538	* -# Call ring-0 and request it to be mapped and supply
539	* a chunk to be unmapped if the cache is maxed out already.
540	* -# Insert the new mapping into the AVL tree (id + R3 address).
541	* -# Update the relevant lookaside entry and return the mapping address.
542	* -# Do the read/write according to monitoring flags and everything.
543	* -# Leave the critsect.
544	*
545	*
546	* @section sec_pgmPhys_Fallback Fallback
547	*
548	* Current all the "second tier" hosts will not support the RTR0MemObjAllocPhysNC
549	* API and thus require a fallback.
550	*
551	* So, when RTR0MemObjAllocPhysNC returns VERR_NOT_SUPPORTED the page allocator
552	* will return to the ring-3 caller (and later ring-0) and asking it to seed
553	* the page allocator with some fresh pages (VERR_GMM_SEED_ME). Ring-3 will
554	* then perform an SUPPageAlloc(cbChunk >> PAGE_SHIFT) call and make a
555	* "SeededAllocPages" call to ring-0.
556	*
557	* The first time ring-0 sees the VERR_NOT_SUPPORTED failure it will disable
558	* all page sharing (zero page detection will continue). It will also force
559	* all allocations to come from the VM which seeded the page. Both these
560	* measures are taken to make sure that there will never be any need for
561	* mapping anything into ring-3 - everything will be mapped already.
562	*
563	* Whether we'll continue to use the current MM locked memory management
564	* for this I don't quite know (I'd prefer not to and just ditch that all
565	* togther), we'll see what's simplest to do.
566	*
567	*
568	*
569	* @section sec_pgmPhys_Changes Changes
570	*
571	* Breakdown of the changes involved?
572	*/
573
574
575	/** Saved state data unit version. */
576	#define PGM_SAVED_STATE_VERSION 6
577
578	/*******************************************************************************
579	* Header Files *
580	*******************************************************************************/
581	#define LOG_GROUP LOG_GROUP_PGM
582	#include <VBox/dbgf.h>
583	#include <VBox/pgm.h>
584	#include <VBox/cpum.h>
585	#include <VBox/iom.h>
586	#include <VBox/sup.h>
587	#include <VBox/mm.h>
588	#include <VBox/em.h>
589	#include <VBox/stam.h>
590	#include <VBox/rem.h>
591	#include <VBox/dbgf.h>
592	#include <VBox/rem.h>
593	#include <VBox/selm.h>
594	#include <VBox/ssm.h>
595	#include "PGMInternal.h"
596	#include <VBox/vm.h>
597	#include <VBox/dbg.h>
598	#include <VBox/hwaccm.h>
599
600	#include <iprt/assert.h>
601	#include <iprt/alloc.h>
602	#include <iprt/asm.h>
603	#include <iprt/thread.h>
604	#include <iprt/string.h>
605	#ifdef DEBUG_bird
606	# include <iprt/env.h>
607	#endif
608	#include <VBox/param.h>
609	#include <VBox/err.h>
610
611
612
613	/*******************************************************************************
614	* Internal Functions *
615	*******************************************************************************/
616	static int pgmR3InitPaging(PVM pVM);
617	static DECLCALLBACK(void) pgmR3PhysInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
618	static DECLCALLBACK(void) pgmR3InfoMode(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
619	static DECLCALLBACK(void) pgmR3InfoCr3(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
620	static DECLCALLBACK(int) pgmR3RelocatePhysHandler(PAVLROGCPHYSNODECORE pNode, void *pvUser);
621	static DECLCALLBACK(int) pgmR3RelocateVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser);
622	static DECLCALLBACK(int) pgmR3RelocateHyperVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser);
623	#ifdef VBOX_STRICT
624	static DECLCALLBACK(void) pgmR3ResetNoMorePhysWritesFlag(PVM pVM, VMSTATE enmState, VMSTATE enmOldState, void *pvUser);
625	#endif
626	static DECLCALLBACK(int) pgmR3Save(PVM pVM, PSSMHANDLE pSSM);
627	static DECLCALLBACK(int) pgmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version);
628	static int pgmR3ModeDataInit(PVM pVM, bool fResolveGCAndR0);
629	static void pgmR3ModeDataSwitch(PVM pVM, PGMMODE enmShw, PGMMODE enmGst);
630	static PGMMODE pgmR3CalcShadowMode(PVM pVM, PGMMODE enmGuestMode, SUPPAGINGMODE enmHostMode, PGMMODE enmShadowMode, VMMSWITCHER *penmSwitcher);
631
632	#ifdef VBOX_WITH_STATISTICS
633	static void pgmR3InitStats(PVM pVM);
634	#endif
635
636	#ifdef VBOX_WITH_DEBUGGER
637	/** @todo all but the two last commands must be converted to 'info'. */
638	static DECLCALLBACK(int) pgmR3CmdRam(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
639	static DECLCALLBACK(int) pgmR3CmdMap(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
640	static DECLCALLBACK(int) pgmR3CmdSync(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
641	static DECLCALLBACK(int) pgmR3CmdSyncAlways(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
642	# ifdef VBOX_STRICT
643	static DECLCALLBACK(int) pgmR3CmdAssertCR3(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
644	# endif
645	#endif
646
647
648	/*******************************************************************************
649	* Global Variables *
650	*******************************************************************************/
651	#ifdef VBOX_WITH_DEBUGGER
652	/** Command descriptors. */
653	static const DBGCCMD g_aCmds[] =
654	{
655	/* pszCmd, cArgsMin, cArgsMax, paArgDesc, cArgDescs, pResultDesc, fFlags, pfnHandler pszSyntax, ....pszDescription */
656	{ "pgmram", 0, 0, NULL, 0, NULL, 0, pgmR3CmdRam, "", "Display the ram ranges." },
657	{ "pgmmap", 0, 0, NULL, 0, NULL, 0, pgmR3CmdMap, "", "Display the mapping ranges." },
658	{ "pgmsync", 0, 0, NULL, 0, NULL, 0, pgmR3CmdSync, "", "Sync the CR3 page." },
659	#ifdef VBOX_STRICT
660	{ "pgmassertcr3", 0, 0, NULL, 0, NULL, 0, pgmR3CmdAssertCR3, "", "Check the shadow CR3 mapping." },
661	#endif
662	{ "pgmsyncalways", 0, 0, NULL, 0, NULL, 0, pgmR3CmdSyncAlways, "", "Toggle permanent CR3 syncing." },
663	};
664	#endif
665
666
667
668
669	/*
670	* Shadow - 32-bit mode
671	*/
672	#define PGM_SHW_TYPE PGM_TYPE_32BIT
673	#define PGM_SHW_NAME(name) PGM_SHW_NAME_32BIT(name)
674	#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_32BIT_STR(name)
675	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_32BIT_STR(name)
676	#include "PGMShw.h"
677
678	/* Guest - real mode */
679	#define PGM_GST_TYPE PGM_TYPE_REAL
680	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
681	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_REAL_STR(name)
682	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
683	#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_REAL(name)
684	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_32BIT_REAL_STR(name)
685	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_32BIT_REAL_STR(name)
686	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_PHYS
687	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_32BIT_PD_PHYS
688	#include "PGMBth.h"
689	#include "PGMGstDefs.h"
690	#include "PGMGst.h"
691	#undef BTH_PGMPOOLKIND_PT_FOR_PT
692	#undef BTH_PGMPOOLKIND_ROOT
693	#undef PGM_BTH_NAME
694	#undef PGM_BTH_NAME_RC_STR
695	#undef PGM_BTH_NAME_R0_STR
696	#undef PGM_GST_TYPE
697	#undef PGM_GST_NAME
698	#undef PGM_GST_NAME_RC_STR
699	#undef PGM_GST_NAME_R0_STR
700
701	/* Guest - protected mode */
702	#define PGM_GST_TYPE PGM_TYPE_PROT
703	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
704	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PROT_STR(name)
705	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
706	#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_PROT(name)
707	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_32BIT_PROT_STR(name)
708	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_32BIT_PROT_STR(name)
709	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_PHYS
710	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_32BIT_PD_PHYS
711	#include "PGMBth.h"
712	#include "PGMGstDefs.h"
713	#include "PGMGst.h"
714	#undef BTH_PGMPOOLKIND_PT_FOR_PT
715	#undef BTH_PGMPOOLKIND_ROOT
716	#undef PGM_BTH_NAME
717	#undef PGM_BTH_NAME_RC_STR
718	#undef PGM_BTH_NAME_R0_STR
719	#undef PGM_GST_TYPE
720	#undef PGM_GST_NAME
721	#undef PGM_GST_NAME_RC_STR
722	#undef PGM_GST_NAME_R0_STR
723
724	/* Guest - 32-bit mode */
725	#define PGM_GST_TYPE PGM_TYPE_32BIT
726	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
727	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_32BIT_STR(name)
728	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
729	#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_32BIT(name)
730	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_32BIT_32BIT_STR(name)
731	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_32BIT_32BIT_STR(name)
732	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT
733	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB
734	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_32BIT_PD
735	#include "PGMBth.h"
736	#include "PGMGstDefs.h"
737	#include "PGMGst.h"
738	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
739	#undef BTH_PGMPOOLKIND_PT_FOR_PT
740	#undef BTH_PGMPOOLKIND_ROOT
741	#undef PGM_BTH_NAME
742	#undef PGM_BTH_NAME_RC_STR
743	#undef PGM_BTH_NAME_R0_STR
744	#undef PGM_GST_TYPE
745	#undef PGM_GST_NAME
746	#undef PGM_GST_NAME_RC_STR
747	#undef PGM_GST_NAME_R0_STR
748
749	#undef PGM_SHW_TYPE
750	#undef PGM_SHW_NAME
751	#undef PGM_SHW_NAME_RC_STR
752	#undef PGM_SHW_NAME_R0_STR
753
754
755	/*
756	* Shadow - PAE mode
757	*/
758	#define PGM_SHW_TYPE PGM_TYPE_PAE
759	#define PGM_SHW_NAME(name) PGM_SHW_NAME_PAE(name)
760	#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_PAE_STR(name)
761	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_PAE_STR(name)
762	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_REAL(name)
763	#include "PGMShw.h"
764
765	/* Guest - real mode */
766	#define PGM_GST_TYPE PGM_TYPE_REAL
767	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
768	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_REAL_STR(name)
769	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
770	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_REAL(name)
771	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_PAE_REAL_STR(name)
772	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_REAL_STR(name)
773	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
774	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT_PHYS
775	#include "PGMGstDefs.h"
776	#include "PGMBth.h"
777	#undef BTH_PGMPOOLKIND_PT_FOR_PT
778	#undef BTH_PGMPOOLKIND_ROOT
779	#undef PGM_BTH_NAME
780	#undef PGM_BTH_NAME_RC_STR
781	#undef PGM_BTH_NAME_R0_STR
782	#undef PGM_GST_TYPE
783	#undef PGM_GST_NAME
784	#undef PGM_GST_NAME_RC_STR
785	#undef PGM_GST_NAME_R0_STR
786
787	/* Guest - protected mode */
788	#define PGM_GST_TYPE PGM_TYPE_PROT
789	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
790	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PROT_STR(name)
791	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
792	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_PROT(name)
793	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_PAE_PROT_STR(name)
794	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_PROT_STR(name)
795	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
796	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT_PHYS
797	#include "PGMGstDefs.h"
798	#include "PGMBth.h"
799	#undef BTH_PGMPOOLKIND_PT_FOR_PT
800	#undef BTH_PGMPOOLKIND_ROOT
801	#undef PGM_BTH_NAME
802	#undef PGM_BTH_NAME_RC_STR
803	#undef PGM_BTH_NAME_R0_STR
804	#undef PGM_GST_TYPE
805	#undef PGM_GST_NAME
806	#undef PGM_GST_NAME_RC_STR
807	#undef PGM_GST_NAME_R0_STR
808
809	/* Guest - 32-bit mode */
810	#define PGM_GST_TYPE PGM_TYPE_32BIT
811	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
812	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_32BIT_STR(name)
813	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
814	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_32BIT(name)
815	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_PAE_32BIT_STR(name)
816	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_32BIT_STR(name)
817	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_32BIT_PT
818	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB
819	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT_FOR_32BIT
820	#include "PGMGstDefs.h"
821	#include "PGMBth.h"
822	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
823	#undef BTH_PGMPOOLKIND_PT_FOR_PT
824	#undef BTH_PGMPOOLKIND_ROOT
825	#undef PGM_BTH_NAME
826	#undef PGM_BTH_NAME_RC_STR
827	#undef PGM_BTH_NAME_R0_STR
828	#undef PGM_GST_TYPE
829	#undef PGM_GST_NAME
830	#undef PGM_GST_NAME_RC_STR
831	#undef PGM_GST_NAME_R0_STR
832
833	/* Guest - PAE mode */
834	#define PGM_GST_TYPE PGM_TYPE_PAE
835	#define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
836	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PAE_STR(name)
837	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PAE_STR(name)
838	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_PAE(name)
839	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_PAE_PAE_STR(name)
840	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_PAE_STR(name)
841	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
842	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
843	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT
844	#include "PGMBth.h"
845	#include "PGMGstDefs.h"
846	#include "PGMGst.h"
847	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
848	#undef BTH_PGMPOOLKIND_PT_FOR_PT
849	#undef BTH_PGMPOOLKIND_ROOT
850	#undef PGM_BTH_NAME
851	#undef PGM_BTH_NAME_RC_STR
852	#undef PGM_BTH_NAME_R0_STR
853	#undef PGM_GST_TYPE
854	#undef PGM_GST_NAME
855	#undef PGM_GST_NAME_RC_STR
856	#undef PGM_GST_NAME_R0_STR
857
858	#undef PGM_SHW_TYPE
859	#undef PGM_SHW_NAME
860	#undef PGM_SHW_NAME_RC_STR
861	#undef PGM_SHW_NAME_R0_STR
862
863
864	/*
865	* Shadow - AMD64 mode
866	*/
867	#define PGM_SHW_TYPE PGM_TYPE_AMD64
868	#define PGM_SHW_NAME(name) PGM_SHW_NAME_AMD64(name)
869	#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_AMD64_STR(name)
870	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_AMD64_STR(name)
871	#include "PGMShw.h"
872
873	#ifdef VBOX_WITH_64_BITS_GUESTS
874	/* Guest - AMD64 mode */
875	# define PGM_GST_TYPE PGM_TYPE_AMD64
876	# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
877	# define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_AMD64_STR(name)
878	# define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_AMD64_STR(name)
879	# define PGM_BTH_NAME(name) PGM_BTH_NAME_AMD64_AMD64(name)
880	# define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_AMD64_AMD64_STR(name)
881	# define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_AMD64_AMD64_STR(name)
882	# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
883	# define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
884	# define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_64BIT_PML4
885	# include "PGMBth.h"
886	# include "PGMGstDefs.h"
887	# include "PGMGst.h"
888	# undef BTH_PGMPOOLKIND_PT_FOR_BIG
889	# undef BTH_PGMPOOLKIND_PT_FOR_PT
890	# undef BTH_PGMPOOLKIND_ROOT
891	# undef PGM_BTH_NAME
892	# undef PGM_BTH_NAME_RC_STR
893	# undef PGM_BTH_NAME_R0_STR
894	# undef PGM_GST_TYPE
895	# undef PGM_GST_NAME
896	# undef PGM_GST_NAME_RC_STR
897	# undef PGM_GST_NAME_R0_STR
898	#endif /* VBOX_WITH_64_BITS_GUESTS */
899
900	#undef PGM_SHW_TYPE
901	#undef PGM_SHW_NAME
902	#undef PGM_SHW_NAME_RC_STR
903	#undef PGM_SHW_NAME_R0_STR
904
905
906	/*
907	* Shadow - Nested paging mode
908	*/
909	#define PGM_SHW_TYPE PGM_TYPE_NESTED
910	#define PGM_SHW_NAME(name) PGM_SHW_NAME_NESTED(name)
911	#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_NESTED_STR(name)
912	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_NESTED_STR(name)
913	#include "PGMShw.h"
914
915	/* Guest - real mode */
916	#define PGM_GST_TYPE PGM_TYPE_REAL
917	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
918	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_REAL_STR(name)
919	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
920	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_REAL(name)
921	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_REAL_STR(name)
922	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_REAL_STR(name)
923	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
924	#include "PGMGstDefs.h"
925	#include "PGMBth.h"
926	#undef BTH_PGMPOOLKIND_PT_FOR_PT
927	#undef PGM_BTH_NAME
928	#undef PGM_BTH_NAME_RC_STR
929	#undef PGM_BTH_NAME_R0_STR
930	#undef PGM_GST_TYPE
931	#undef PGM_GST_NAME
932	#undef PGM_GST_NAME_RC_STR
933	#undef PGM_GST_NAME_R0_STR
934
935	/* Guest - protected mode */
936	#define PGM_GST_TYPE PGM_TYPE_PROT
937	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
938	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PROT_STR(name)
939	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
940	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_PROT(name)
941	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_PROT_STR(name)
942	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_PROT_STR(name)
943	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
944	#include "PGMGstDefs.h"
945	#include "PGMBth.h"
946	#undef BTH_PGMPOOLKIND_PT_FOR_PT
947	#undef PGM_BTH_NAME
948	#undef PGM_BTH_NAME_RC_STR
949	#undef PGM_BTH_NAME_R0_STR
950	#undef PGM_GST_TYPE
951	#undef PGM_GST_NAME
952	#undef PGM_GST_NAME_RC_STR
953	#undef PGM_GST_NAME_R0_STR
954
955	/* Guest - 32-bit mode */
956	#define PGM_GST_TYPE PGM_TYPE_32BIT
957	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
958	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_32BIT_STR(name)
959	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
960	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_32BIT(name)
961	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_32BIT_STR(name)
962	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_32BIT_STR(name)
963	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_32BIT_PT
964	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB
965	#include "PGMGstDefs.h"
966	#include "PGMBth.h"
967	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
968	#undef BTH_PGMPOOLKIND_PT_FOR_PT
969	#undef PGM_BTH_NAME
970	#undef PGM_BTH_NAME_RC_STR
971	#undef PGM_BTH_NAME_R0_STR
972	#undef PGM_GST_TYPE
973	#undef PGM_GST_NAME
974	#undef PGM_GST_NAME_RC_STR
975	#undef PGM_GST_NAME_R0_STR
976
977	/* Guest - PAE mode */
978	#define PGM_GST_TYPE PGM_TYPE_PAE
979	#define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
980	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PAE_STR(name)
981	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PAE_STR(name)
982	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_PAE(name)
983	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_PAE_STR(name)
984	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_PAE_STR(name)
985	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
986	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
987	#include "PGMGstDefs.h"
988	#include "PGMBth.h"
989	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
990	#undef BTH_PGMPOOLKIND_PT_FOR_PT
991	#undef PGM_BTH_NAME
992	#undef PGM_BTH_NAME_RC_STR
993	#undef PGM_BTH_NAME_R0_STR
994	#undef PGM_GST_TYPE
995	#undef PGM_GST_NAME
996	#undef PGM_GST_NAME_RC_STR
997	#undef PGM_GST_NAME_R0_STR
998
999	#ifdef VBOX_WITH_64_BITS_GUESTS
1000	/* Guest - AMD64 mode */
1001	# define PGM_GST_TYPE PGM_TYPE_AMD64
1002	# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
1003	# define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_AMD64_STR(name)
1004	# define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_AMD64_STR(name)
1005	# define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_AMD64(name)
1006	# define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_AMD64_STR(name)
1007	# define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_AMD64_STR(name)
1008	# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
1009	# define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
1010	# include "PGMGstDefs.h"
1011	# include "PGMBth.h"
1012	# undef BTH_PGMPOOLKIND_PT_FOR_BIG
1013	# undef BTH_PGMPOOLKIND_PT_FOR_PT
1014	# undef PGM_BTH_NAME
1015	# undef PGM_BTH_NAME_RC_STR
1016	# undef PGM_BTH_NAME_R0_STR
1017	# undef PGM_GST_TYPE
1018	# undef PGM_GST_NAME
1019	# undef PGM_GST_NAME_RC_STR
1020	# undef PGM_GST_NAME_R0_STR
1021	#endif /* VBOX_WITH_64_BITS_GUESTS */
1022
1023	#undef PGM_SHW_TYPE
1024	#undef PGM_SHW_NAME
1025	#undef PGM_SHW_NAME_RC_STR
1026	#undef PGM_SHW_NAME_R0_STR
1027
1028
1029	/*
1030	* Shadow - EPT
1031	*/
1032	#define PGM_SHW_TYPE PGM_TYPE_EPT
1033	#define PGM_SHW_NAME(name) PGM_SHW_NAME_EPT(name)
1034	#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_EPT_STR(name)
1035	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_EPT_STR(name)
1036	#include "PGMShw.h"
1037
1038	/* Guest - real mode */
1039	#define PGM_GST_TYPE PGM_TYPE_REAL
1040	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
1041	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_REAL_STR(name)
1042	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
1043	#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_REAL(name)
1044	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_REAL_STR(name)
1045	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_REAL_STR(name)
1046	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
1047	#include "PGMGstDefs.h"
1048	#include "PGMBth.h"
1049	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1050	#undef PGM_BTH_NAME
1051	#undef PGM_BTH_NAME_RC_STR
1052	#undef PGM_BTH_NAME_R0_STR
1053	#undef PGM_GST_TYPE
1054	#undef PGM_GST_NAME
1055	#undef PGM_GST_NAME_RC_STR
1056	#undef PGM_GST_NAME_R0_STR
1057
1058	/* Guest - protected mode */
1059	#define PGM_GST_TYPE PGM_TYPE_PROT
1060	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
1061	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PROT_STR(name)
1062	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
1063	#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_PROT(name)
1064	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_PROT_STR(name)
1065	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_PROT_STR(name)
1066	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
1067	#include "PGMGstDefs.h"
1068	#include "PGMBth.h"
1069	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1070	#undef PGM_BTH_NAME
1071	#undef PGM_BTH_NAME_RC_STR
1072	#undef PGM_BTH_NAME_R0_STR
1073	#undef PGM_GST_TYPE
1074	#undef PGM_GST_NAME
1075	#undef PGM_GST_NAME_RC_STR
1076	#undef PGM_GST_NAME_R0_STR
1077
1078	/* Guest - 32-bit mode */
1079	#define PGM_GST_TYPE PGM_TYPE_32BIT
1080	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
1081	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_32BIT_STR(name)
1082	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
1083	#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_32BIT(name)
1084	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_32BIT_STR(name)
1085	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_32BIT_STR(name)
1086	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_32BIT_PT
1087	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB
1088	#include "PGMGstDefs.h"
1089	#include "PGMBth.h"
1090	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
1091	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1092	#undef PGM_BTH_NAME
1093	#undef PGM_BTH_NAME_RC_STR
1094	#undef PGM_BTH_NAME_R0_STR
1095	#undef PGM_GST_TYPE
1096	#undef PGM_GST_NAME
1097	#undef PGM_GST_NAME_RC_STR
1098	#undef PGM_GST_NAME_R0_STR
1099
1100	/* Guest - PAE mode */
1101	#define PGM_GST_TYPE PGM_TYPE_PAE
1102	#define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
1103	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PAE_STR(name)
1104	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PAE_STR(name)
1105	#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_PAE(name)
1106	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_PAE_STR(name)
1107	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_PAE_STR(name)
1108	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
1109	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
1110	#include "PGMGstDefs.h"
1111	#include "PGMBth.h"
1112	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
1113	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1114	#undef PGM_BTH_NAME
1115	#undef PGM_BTH_NAME_RC_STR
1116	#undef PGM_BTH_NAME_R0_STR
1117	#undef PGM_GST_TYPE
1118	#undef PGM_GST_NAME
1119	#undef PGM_GST_NAME_RC_STR
1120	#undef PGM_GST_NAME_R0_STR
1121
1122	#ifdef VBOX_WITH_64_BITS_GUESTS
1123	/* Guest - AMD64 mode */
1124	# define PGM_GST_TYPE PGM_TYPE_AMD64
1125	# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
1126	# define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_AMD64_STR(name)
1127	# define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_AMD64_STR(name)
1128	# define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_AMD64(name)
1129	# define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_AMD64_STR(name)
1130	# define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_AMD64_STR(name)
1131	# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
1132	# define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
1133	# include "PGMGstDefs.h"
1134	# include "PGMBth.h"
1135	# undef BTH_PGMPOOLKIND_PT_FOR_BIG
1136	# undef BTH_PGMPOOLKIND_PT_FOR_PT
1137	# undef PGM_BTH_NAME
1138	# undef PGM_BTH_NAME_RC_STR
1139	# undef PGM_BTH_NAME_R0_STR
1140	# undef PGM_GST_TYPE
1141	# undef PGM_GST_NAME
1142	# undef PGM_GST_NAME_RC_STR
1143	# undef PGM_GST_NAME_R0_STR
1144	#endif /* VBOX_WITH_64_BITS_GUESTS */
1145
1146	#undef PGM_SHW_TYPE
1147	#undef PGM_SHW_NAME
1148	#undef PGM_SHW_NAME_RC_STR
1149	#undef PGM_SHW_NAME_R0_STR
1150
1151
1152
1153	/**
1154	* Initiates the paging of VM.
1155	*
1156	* @returns VBox status code.
1157	* @param pVM Pointer to VM structure.
1158	*/
1159	VMMR3DECL(int) PGMR3Init(PVM pVM)
1160	{
1161	LogFlow(("PGMR3Init:\n"));
1162	PCFGMNODE pCfgPGM = CFGMR3GetChild(CFGMR3GetRoot(pVM), "/PGM");
1163	int rc;
1164
1165	/*
1166	* Assert alignment and sizes.
1167	*/
1168	AssertRelease(sizeof(pVM->pgm.s) <= sizeof(pVM->pgm.padding));
1169
1170	/*
1171	* Init the structure.
1172	*/
1173	pVM->pgm.s.offVM = RT_OFFSETOF(VM, pgm.s);
1174	pVM->pgm.s.offVCpu = RT_OFFSETOF(VMCPU, pgm.s);
1175	pVM->pgm.s.enmShadowMode = PGMMODE_INVALID;
1176	pVM->pgm.s.enmGuestMode = PGMMODE_INVALID;
1177	pVM->pgm.s.enmHostMode = SUPPAGINGMODE_INVALID;
1178	pVM->pgm.s.GCPhysCR3 = NIL_RTGCPHYS;
1179	#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
1180	pVM->pgm.s.GCPhysGstCR3Monitored = NIL_RTGCPHYS;
1181	#endif
1182	pVM->pgm.s.fA20Enabled = true;
1183	pVM->pgm.s.GCPhys4MBPSEMask = RT_BIT_64(32) - 1; /* default; checked later */
1184	pVM->pgm.s.pGstPaePdptR3 = NULL;
1185	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
1186	pVM->pgm.s.pGstPaePdptR0 = NIL_RTR0PTR;
1187	#endif
1188	pVM->pgm.s.pGstPaePdptRC = NIL_RTRCPTR;
1189	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.apGstPaePDsR3); i++)
1190	{
1191	pVM->pgm.s.apGstPaePDsR3[i] = NULL;
1192	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
1193	pVM->pgm.s.apGstPaePDsR0[i] = NIL_RTR0PTR;
1194	#endif
1195	pVM->pgm.s.apGstPaePDsRC[i] = NIL_RTRCPTR;
1196	pVM->pgm.s.aGCPhysGstPaePDs[i] = NIL_RTGCPHYS;
1197	pVM->pgm.s.aGCPhysGstPaePDsMonitored[i] = NIL_RTGCPHYS;
1198	}
1199
1200	rc = CFGMR3QueryBoolDef(pCfgPGM, "RamPreAlloc", &pVM->pgm.s.fRamPreAlloc, false);
1201	AssertLogRelRCReturn(rc, rc);
1202
1203	#if HC_ARCH_BITS == 64
1204	rc = CFGMR3QueryU32Def(pCfgPGM, "MaxRing3Chunks", &pVM->pgm.s.ChunkR3Map.cMax, UINT32_MAX);
1205	#else
1206	rc = CFGMR3QueryU32Def(pCfgPGM, "MaxRing3Chunks", &pVM->pgm.s.ChunkR3Map.cMax, _1G / GMM_CHUNK_SIZE);
1207	#endif
1208	AssertLogRelRCReturn(rc, rc);
1209	for (uint32_t i = 0; i < RT_ELEMENTS(pVM->pgm.s.ChunkR3Map.Tlb.aEntries); i++)
1210	pVM->pgm.s.ChunkR3Map.Tlb.aEntries[i].idChunk = NIL_GMM_CHUNKID;
1211
1212	/*
1213	* Get the configured RAM size - to estimate saved state size.
1214	*/
1215	uint64_t cbRam;
1216	rc = CFGMR3QueryU64(CFGMR3GetRoot(pVM), "RamSize", &cbRam);
1217	if (rc == VERR_CFGM_VALUE_NOT_FOUND)
1218	cbRam = pVM->pgm.s.cbRamSize = 0;
1219	else if (RT_SUCCESS(rc))
1220	{
1221	if (cbRam < PAGE_SIZE)
1222	cbRam = 0;
1223	cbRam = RT_ALIGN_64(cbRam, PAGE_SIZE);
1224	pVM->pgm.s.cbRamSize = (RTUINT)cbRam;
1225	}
1226	else
1227	{
1228	AssertMsgFailed(("Configuration error: Failed to query integer \"RamSize\", rc=%Rrc.\n", rc));
1229	return rc;
1230	}
1231
1232	/*
1233	* Register callbacks, string formatters and the saved state data unit.
1234	*/
1235	#ifdef VBOX_STRICT
1236	VMR3AtStateRegister(pVM, pgmR3ResetNoMorePhysWritesFlag, NULL);
1237	#endif
1238	PGMRegisterStringFormatTypes();
1239
1240	rc = SSMR3RegisterInternal(pVM, "pgm", 1, PGM_SAVED_STATE_VERSION, (size_t)cbRam + sizeof(PGM),
1241	NULL, pgmR3Save, NULL,
1242	NULL, pgmR3Load, NULL);
1243	if (RT_FAILURE(rc))
1244	return rc;
1245
1246	/*
1247	* Initialize the PGM critical section and flush the phys TLBs
1248	*/
1249	rc = PDMR3CritSectInit(pVM, &pVM->pgm.s.CritSect, "PGM");
1250	AssertRCReturn(rc, rc);
1251
1252	PGMR3PhysChunkInvalidateTLB(pVM);
1253	PGMPhysInvalidatePageR3MapTLB(pVM);
1254	PGMPhysInvalidatePageR0MapTLB(pVM);
1255	PGMPhysInvalidatePageGCMapTLB(pVM);
1256
1257	/*
1258	* Trees
1259	*/
1260	rc = MMHyperAlloc(pVM, sizeof(PGMTREES), 0, MM_TAG_PGM, (void **)&pVM->pgm.s.pTreesR3);
1261	if (RT_SUCCESS(rc))
1262	{
1263	pVM->pgm.s.pTreesR0 = MMHyperR3ToR0(pVM, pVM->pgm.s.pTreesR3);
1264	pVM->pgm.s.pTreesRC = MMHyperR3ToRC(pVM, pVM->pgm.s.pTreesR3);
1265
1266	/*
1267	* Alocate the zero page.
1268	*/
1269	rc = MMHyperAlloc(pVM, PAGE_SIZE, PAGE_SIZE, MM_TAG_PGM, &pVM->pgm.s.pvZeroPgR3);
1270	}
1271	if (RT_SUCCESS(rc))
1272	{
1273	pVM->pgm.s.pvZeroPgGC = MMHyperR3ToRC(pVM, pVM->pgm.s.pvZeroPgR3);
1274	pVM->pgm.s.pvZeroPgR0 = MMHyperR3ToR0(pVM, pVM->pgm.s.pvZeroPgR3);
1275	AssertRelease(pVM->pgm.s.pvZeroPgR0 != NIL_RTHCPHYS);
1276	pVM->pgm.s.HCPhysZeroPg = MMR3HyperHCVirt2HCPhys(pVM, pVM->pgm.s.pvZeroPgR3);
1277	AssertRelease(pVM->pgm.s.HCPhysZeroPg != NIL_RTHCPHYS);
1278
1279	/*
1280	* Init the paging.
1281	*/
1282	rc = pgmR3InitPaging(pVM);
1283	}
1284	if (RT_SUCCESS(rc))
1285	{
1286	/*
1287	* Init the page pool.
1288	*/
1289	rc = pgmR3PoolInit(pVM);
1290	}
1291	#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
1292	if (RT_SUCCESS(rc))
1293	rc = PGMR3ChangeMode(pVM, PGMMODE_REAL);
1294	#endif
1295	if (RT_SUCCESS(rc))
1296	{
1297	/*
1298	* Info & statistics
1299	*/
1300	DBGFR3InfoRegisterInternal(pVM, "mode",
1301	"Shows the current paging mode. "
1302	"Recognizes 'all', 'guest', 'shadow' and 'host' as arguments, defaulting to 'all' if nothing's given.",
1303	pgmR3InfoMode);
1304	DBGFR3InfoRegisterInternal(pVM, "pgmcr3",
1305	"Dumps all the entries in the top level paging table. No arguments.",
1306	pgmR3InfoCr3);
1307	DBGFR3InfoRegisterInternal(pVM, "phys",
1308	"Dumps all the physical address ranges. No arguments.",
1309	pgmR3PhysInfo);
1310	DBGFR3InfoRegisterInternal(pVM, "handlers",
1311	"Dumps physical, virtual and hyper virtual handlers. "
1312	"Pass 'phys', 'virt', 'hyper' as argument if only one kind is wanted."
1313	"Add 'nost' if the statistics are unwanted, use together with 'all' or explicit selection.",
1314	pgmR3InfoHandlers);
1315	DBGFR3InfoRegisterInternal(pVM, "mappings",
1316	"Dumps guest mappings.",
1317	pgmR3MapInfo);
1318
1319	STAM_REL_REG(pVM, &pVM->pgm.s.cGuestModeChanges, STAMTYPE_COUNTER, "/PGM/cGuestModeChanges", STAMUNIT_OCCURENCES, "Number of guest mode changes.");
1320	STAM_REL_REG(pVM, &pVM->pgm.s.cRelocations, STAMTYPE_COUNTER, "/PGM/cRelocations", STAMUNIT_OCCURENCES, "Number of hypervisor relocations.");
1321	#ifdef VBOX_WITH_STATISTICS
1322	pgmR3InitStats(pVM);
1323	#endif
1324	#ifdef VBOX_WITH_DEBUGGER
1325	/*
1326	* Debugger commands.
1327	*/
1328	static bool fRegisteredCmds = false;
1329	if (!fRegisteredCmds)
1330	{
1331	int rc = DBGCRegisterCommands(&g_aCmds[0], RT_ELEMENTS(g_aCmds));
1332	if (RT_SUCCESS(rc))
1333	fRegisteredCmds = true;
1334	}
1335	#endif
1336	return VINF_SUCCESS;
1337	}
1338
1339	/* Almost no cleanup necessary, MM frees all memory. */
1340	PDMR3CritSectDelete(&pVM->pgm.s.CritSect);
1341
1342	return rc;
1343	}
1344
1345
1346	/**
1347	* Initializes the per-VCPU PGM.
1348	*
1349	* @returns VBox status code.
1350	* @param pVM The VM to operate on.
1351	*/
1352	VMMR3DECL(int) PGMR3InitCPU(PVM pVM)
1353	{
1354	LogFlow(("PGMR3InitCPU\n"));
1355	return VINF_SUCCESS;
1356	}
1357
1358
1359	/**
1360	* Init paging.
1361	*
1362	* Since we need to check what mode the host is operating in before we can choose
1363	* the right paging functions for the host we have to delay this until R0 has
1364	* been initialized.
1365	*
1366	* @returns VBox status code.
1367	* @param pVM VM handle.
1368	*/
1369	static int pgmR3InitPaging(PVM pVM)
1370	{
1371	/*
1372	* Force a recalculation of modes and switcher so everyone gets notified.
1373	*/
1374	pVM->pgm.s.enmShadowMode = PGMMODE_INVALID;
1375	pVM->pgm.s.enmGuestMode = PGMMODE_INVALID;
1376	pVM->pgm.s.enmHostMode = SUPPAGINGMODE_INVALID;
1377
1378	/*
1379	* Allocate static mapping space for whatever the cr3 register
1380	* points to and in the case of PAE mode to the 4 PDs.
1381	*/
1382	int rc = MMR3HyperReserve(pVM, PAGE_SIZE * 5, "CR3 mapping", &pVM->pgm.s.GCPtrCR3Mapping);
1383	if (RT_FAILURE(rc))
1384	{
1385	AssertMsgFailed(("Failed to reserve two pages for cr mapping in HMA, rc=%Rrc\n", rc));
1386	return rc;
1387	}
1388	MMR3HyperReserve(pVM, PAGE_SIZE, "fence", NULL);
1389
1390	/*
1391	* Allocate pages for the three possible intermediate contexts
1392	* (AMD64, PAE and plain 32-Bit). We maintain all three contexts
1393	* for the sake of simplicity. The AMD64 uses the PAE for the
1394	* lower levels, making the total number of pages 11 (3 + 7 + 1).
1395	*
1396	* We assume that two page tables will be enought for the core code
1397	* mappings (HC virtual and identity).
1398	*/
1399	pVM->pgm.s.pInterPD = (PX86PD)MMR3PageAllocLow(pVM);
1400	pVM->pgm.s.apInterPTs[0] = (PX86PT)MMR3PageAllocLow(pVM);
1401	pVM->pgm.s.apInterPTs[1] = (PX86PT)MMR3PageAllocLow(pVM);
1402	pVM->pgm.s.apInterPaePTs[0] = (PX86PTPAE)MMR3PageAlloc(pVM);
1403	pVM->pgm.s.apInterPaePTs[1] = (PX86PTPAE)MMR3PageAlloc(pVM);
1404	pVM->pgm.s.apInterPaePDs[0] = (PX86PDPAE)MMR3PageAlloc(pVM);
1405	pVM->pgm.s.apInterPaePDs[1] = (PX86PDPAE)MMR3PageAlloc(pVM);
1406	pVM->pgm.s.apInterPaePDs[2] = (PX86PDPAE)MMR3PageAlloc(pVM);
1407	pVM->pgm.s.apInterPaePDs[3] = (PX86PDPAE)MMR3PageAlloc(pVM);
1408	pVM->pgm.s.pInterPaePDPT = (PX86PDPT)MMR3PageAllocLow(pVM);
1409	pVM->pgm.s.pInterPaePDPT64 = (PX86PDPT)MMR3PageAllocLow(pVM);
1410	pVM->pgm.s.pInterPaePML4 = (PX86PML4)MMR3PageAllocLow(pVM);
1411	if ( !pVM->pgm.s.pInterPD
1412	\|\| !pVM->pgm.s.apInterPTs[0]
1413	\|\| !pVM->pgm.s.apInterPTs[1]
1414	\|\| !pVM->pgm.s.apInterPaePTs[0]
1415	\|\| !pVM->pgm.s.apInterPaePTs[1]
1416	\|\| !pVM->pgm.s.apInterPaePDs[0]
1417	\|\| !pVM->pgm.s.apInterPaePDs[1]
1418	\|\| !pVM->pgm.s.apInterPaePDs[2]
1419	\|\| !pVM->pgm.s.apInterPaePDs[3]
1420	\|\| !pVM->pgm.s.pInterPaePDPT
1421	\|\| !pVM->pgm.s.pInterPaePDPT64
1422	\|\| !pVM->pgm.s.pInterPaePML4)
1423	{
1424	AssertMsgFailed(("Failed to allocate pages for the intermediate context!\n"));
1425	return VERR_NO_PAGE_MEMORY;
1426	}
1427
1428	pVM->pgm.s.HCPhysInterPD = MMPage2Phys(pVM, pVM->pgm.s.pInterPD);
1429	AssertRelease(pVM->pgm.s.HCPhysInterPD != NIL_RTHCPHYS && !(pVM->pgm.s.HCPhysInterPD & PAGE_OFFSET_MASK));
1430	pVM->pgm.s.HCPhysInterPaePDPT = MMPage2Phys(pVM, pVM->pgm.s.pInterPaePDPT);
1431	AssertRelease(pVM->pgm.s.HCPhysInterPaePDPT != NIL_RTHCPHYS && !(pVM->pgm.s.HCPhysInterPaePDPT & PAGE_OFFSET_MASK));
1432	pVM->pgm.s.HCPhysInterPaePML4 = MMPage2Phys(pVM, pVM->pgm.s.pInterPaePML4);
1433	AssertRelease(pVM->pgm.s.HCPhysInterPaePML4 != NIL_RTHCPHYS && !(pVM->pgm.s.HCPhysInterPaePML4 & PAGE_OFFSET_MASK) && pVM->pgm.s.HCPhysInterPaePML4 < 0xffffffff);
1434
1435	/*
1436	* Initialize the pages, setting up the PML4 and PDPT for repetitive 4GB action.
1437	*/
1438	ASMMemZeroPage(pVM->pgm.s.pInterPD);
1439	ASMMemZeroPage(pVM->pgm.s.apInterPTs[0]);
1440	ASMMemZeroPage(pVM->pgm.s.apInterPTs[1]);
1441
1442	ASMMemZeroPage(pVM->pgm.s.apInterPaePTs[0]);
1443	ASMMemZeroPage(pVM->pgm.s.apInterPaePTs[1]);
1444
1445	ASMMemZeroPage(pVM->pgm.s.pInterPaePDPT);
1446	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.apInterPaePDs); i++)
1447	{
1448	ASMMemZeroPage(pVM->pgm.s.apInterPaePDs[i]);
1449	pVM->pgm.s.pInterPaePDPT->a[i].u = X86_PDPE_P \| PGM_PLXFLAGS_PERMANENT
1450	\| MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[i]);
1451	}
1452
1453	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.pInterPaePDPT64->a); i++)
1454	{
1455	const unsigned iPD = i % RT_ELEMENTS(pVM->pgm.s.apInterPaePDs);
1456	pVM->pgm.s.pInterPaePDPT64->a[i].u = X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_A \| PGM_PLXFLAGS_PERMANENT
1457	\| MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[iPD]);
1458	}
1459
1460	RTHCPHYS HCPhysInterPaePDPT64 = MMPage2Phys(pVM, pVM->pgm.s.pInterPaePDPT64);
1461	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.pInterPaePML4->a); i++)
1462	pVM->pgm.s.pInterPaePML4->a[i].u = X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_A \| PGM_PLXFLAGS_PERMANENT
1463	\| HCPhysInterPaePDPT64;
1464
1465	/*
1466	* Allocate pages for the three possible guest contexts (AMD64, PAE and plain 32-Bit).
1467	* We allocate pages for all three posibilities in order to simplify mappings and
1468	* avoid resource failure during mode switches. So, we need to cover all levels of the
1469	* of the first 4GB down to PD level.
1470	* As with the intermediate context, AMD64 uses the PAE PDPT and PDs.
1471	*/
1472	#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
1473	pVM->pgm.s.pShw32BitPdR3 = (PX86PD)MMR3PageAllocLow(pVM);
1474	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
1475	pVM->pgm.s.pShw32BitPdR0 = (uintptr_t)pVM->pgm.s.pShw32BitPdR3;
1476	# endif
1477	pVM->pgm.s.apShwPaePDsR3[0] = (PX86PDPAE)MMR3PageAlloc(pVM);
1478	pVM->pgm.s.apShwPaePDsR3[1] = (PX86PDPAE)MMR3PageAlloc(pVM);
1479	AssertRelease((uintptr_t)pVM->pgm.s.apShwPaePDsR3[0] + PAGE_SIZE == (uintptr_t)pVM->pgm.s.apShwPaePDsR3[1]);
1480	pVM->pgm.s.apShwPaePDsR3[2] = (PX86PDPAE)MMR3PageAlloc(pVM);
1481	AssertRelease((uintptr_t)pVM->pgm.s.apShwPaePDsR3[1] + PAGE_SIZE == (uintptr_t)pVM->pgm.s.apShwPaePDsR3[2]);
1482	pVM->pgm.s.apShwPaePDsR3[3] = (PX86PDPAE)MMR3PageAlloc(pVM);
1483	AssertRelease((uintptr_t)pVM->pgm.s.apShwPaePDsR3[2] + PAGE_SIZE == (uintptr_t)pVM->pgm.s.apShwPaePDsR3[3]);
1484	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
1485	pVM->pgm.s.apShwPaePDsR0[0] = (uintptr_t)pVM->pgm.s.apShwPaePDsR3[0];
1486	pVM->pgm.s.apShwPaePDsR0[1] = (uintptr_t)pVM->pgm.s.apShwPaePDsR3[1];
1487	pVM->pgm.s.apShwPaePDsR0[2] = (uintptr_t)pVM->pgm.s.apShwPaePDsR3[2];
1488	pVM->pgm.s.apShwPaePDsR0[3] = (uintptr_t)pVM->pgm.s.apShwPaePDsR3[3];
1489	# endif
1490	pVM->pgm.s.pShwPaePdptR3 = (PX86PDPT)MMR3PageAllocLow(pVM);
1491	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
1492	pVM->pgm.s.pShwPaePdptR0 = (uintptr_t)pVM->pgm.s.pShwPaePdptR3;
1493	# endif
1494	pVM->pgm.s.pShwNestedRootR3 = MMR3PageAllocLow(pVM);
1495	# ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
1496	pVM->pgm.s.pShwNestedRootR0 = (uintptr_t)pVM->pgm.s.pShwNestedRootR3;
1497	# endif
1498	#endif /* VBOX_WITH_PGMPOOL_PAGING_ONLY */
1499
1500	#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
1501	if ( !pVM->pgm.s.pShw32BitPdR3
1502	\|\| !pVM->pgm.s.apShwPaePDsR3[0]
1503	\|\| !pVM->pgm.s.apShwPaePDsR3[1]
1504	\|\| !pVM->pgm.s.apShwPaePDsR3[2]
1505	\|\| !pVM->pgm.s.apShwPaePDsR3[3]
1506	\|\| !pVM->pgm.s.pShwPaePdptR3
1507	\|\| !pVM->pgm.s.pShwNestedRootR3)
1508	{
1509	AssertMsgFailed(("Failed to allocate pages for the intermediate context!\n"));
1510	return VERR_NO_PAGE_MEMORY;
1511	}
1512	#endif
1513
1514	/* get physical addresses. */
1515	#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
1516	pVM->pgm.s.HCPhysShw32BitPD = MMPage2Phys(pVM, pVM->pgm.s.pShw32BitPdR3);
1517	Assert(MMPagePhys2Page(pVM, pVM->pgm.s.HCPhysShw32BitPD) == pVM->pgm.s.pShw32BitPdR3);
1518	pVM->pgm.s.aHCPhysPaePDs[0] = MMPage2Phys(pVM, pVM->pgm.s.apShwPaePDsR3[0]);
1519	pVM->pgm.s.aHCPhysPaePDs[1] = MMPage2Phys(pVM, pVM->pgm.s.apShwPaePDsR3[1]);
1520	pVM->pgm.s.aHCPhysPaePDs[2] = MMPage2Phys(pVM, pVM->pgm.s.apShwPaePDsR3[2]);
1521	pVM->pgm.s.aHCPhysPaePDs[3] = MMPage2Phys(pVM, pVM->pgm.s.apShwPaePDsR3[3]);
1522	pVM->pgm.s.HCPhysShwPaePdpt = MMPage2Phys(pVM, pVM->pgm.s.pShwPaePdptR3);
1523	pVM->pgm.s.HCPhysShwNestedRoot = MMPage2Phys(pVM, pVM->pgm.s.pShwNestedRootR3);
1524	#endif
1525
1526	/*
1527	* Initialize the pages, setting up the PML4 and PDPT for action below 4GB.
1528	*/
1529	#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
1530	ASMMemZero32(pVM->pgm.s.pShw32BitPdR3, PAGE_SIZE);
1531	ASMMemZero32(pVM->pgm.s.pShwPaePdptR3, PAGE_SIZE);
1532	ASMMemZero32(pVM->pgm.s.pShwNestedRootR3, PAGE_SIZE);
1533
1534	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.apShwPaePDsR3); i++)
1535	{
1536	ASMMemZero32(pVM->pgm.s.apShwPaePDsR3[i], PAGE_SIZE);
1537	pVM->pgm.s.pShwPaePdptR3->a[i].u = X86_PDPE_P \| PGM_PLXFLAGS_PERMANENT \| pVM->pgm.s.aHCPhysPaePDs[i];
1538	/* The flags will be corrected when entering and leaving long mode. */
1539	}
1540	#endif
1541
1542	/*
1543	* Initialize paging workers and mode from current host mode
1544	* and the guest running in real mode.
1545	*/
1546	pVM->pgm.s.enmHostMode = SUPGetPagingMode();
1547	switch (pVM->pgm.s.enmHostMode)
1548	{
1549	case SUPPAGINGMODE_32_BIT:
1550	case SUPPAGINGMODE_32_BIT_GLOBAL:
1551	case SUPPAGINGMODE_PAE:
1552	case SUPPAGINGMODE_PAE_GLOBAL:
1553	case SUPPAGINGMODE_PAE_NX:
1554	case SUPPAGINGMODE_PAE_GLOBAL_NX:
1555	break;
1556
1557	case SUPPAGINGMODE_AMD64:
1558	case SUPPAGINGMODE_AMD64_GLOBAL:
1559	case SUPPAGINGMODE_AMD64_NX:
1560	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
1561	#ifndef VBOX_WITH_HYBRID_32BIT_KERNEL
1562	if (ARCH_BITS != 64)
1563	{
1564	AssertMsgFailed(("Host mode %d (64-bit) is not supported by non-64bit builds\n", pVM->pgm.s.enmHostMode));
1565	LogRel(("Host mode %d (64-bit) is not supported by non-64bit builds\n", pVM->pgm.s.enmHostMode));
1566	return VERR_PGM_UNSUPPORTED_HOST_PAGING_MODE;
1567	}
1568	#endif
1569	break;
1570	default:
1571	AssertMsgFailed(("Host mode %d is not supported\n", pVM->pgm.s.enmHostMode));
1572	return VERR_PGM_UNSUPPORTED_HOST_PAGING_MODE;
1573	}
1574	rc = pgmR3ModeDataInit(pVM, false /* don't resolve GC and R0 syms yet */);
1575	#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
1576	if (RT_SUCCESS(rc))
1577	rc = PGMR3ChangeMode(pVM, PGMMODE_REAL);
1578	#endif
1579	if (RT_SUCCESS(rc))
1580	{
1581	LogFlow(("pgmR3InitPaging: returns successfully\n"));
1582	#if HC_ARCH_BITS == 64
1583	# ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
1584	LogRel(("Debug: HCPhysShw32BitPD=%RHp aHCPhysPaePDs={%RHp,%RHp,%RHp,%RHp} HCPhysShwPaePdpt=%RHp\n",
1585	pVM->pgm.s.HCPhysShw32BitPD,
1586	pVM->pgm.s.aHCPhysPaePDs[0], pVM->pgm.s.aHCPhysPaePDs[1], pVM->pgm.s.aHCPhysPaePDs[2], pVM->pgm.s.aHCPhysPaePDs[3],
1587	pVM->pgm.s.HCPhysShwPaePdpt));
1588	# endif
1589	LogRel(("Debug: HCPhysInterPD=%RHp HCPhysInterPaePDPT=%RHp HCPhysInterPaePML4=%RHp\n",
1590	pVM->pgm.s.HCPhysInterPD, pVM->pgm.s.HCPhysInterPaePDPT, pVM->pgm.s.HCPhysInterPaePML4));
1591	LogRel(("Debug: apInterPTs={%RHp,%RHp} apInterPaePTs={%RHp,%RHp} apInterPaePDs={%RHp,%RHp,%RHp,%RHp} pInterPaePDPT64=%RHp\n",
1592	MMPage2Phys(pVM, pVM->pgm.s.apInterPTs[0]), MMPage2Phys(pVM, pVM->pgm.s.apInterPTs[1]),
1593	MMPage2Phys(pVM, pVM->pgm.s.apInterPaePTs[0]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePTs[1]),
1594	MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[0]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[1]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[2]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[3]),
1595	MMPage2Phys(pVM, pVM->pgm.s.pInterPaePDPT64)));
1596	#endif
1597
1598	return VINF_SUCCESS;
1599	}
1600
1601	LogFlow(("pgmR3InitPaging: returns %Rrc\n", rc));
1602	return rc;
1603	}
1604
1605
1606	#ifdef VBOX_WITH_STATISTICS
1607	/**
1608	* Init statistics
1609	*/
1610	static void pgmR3InitStats(PVM pVM)
1611	{
1612	PPGM pPGM = &pVM->pgm.s;
1613	unsigned i;
1614
1615	/*
1616	* Note! The layout of this function matches the member layout exactly!
1617	*/
1618
1619	/* Common - misc variables */
1620	STAM_REG(pVM, &pPGM->cAllPages, STAMTYPE_U32, "/PGM/Page/cAllPages", STAMUNIT_OCCURENCES, "The total number of pages.");
1621	STAM_REG(pVM, &pPGM->cPrivatePages, STAMTYPE_U32, "/PGM/Page/cPrivatePages", STAMUNIT_OCCURENCES, "The number of private pages.");
1622	STAM_REG(pVM, &pPGM->cSharedPages, STAMTYPE_U32, "/PGM/Page/cSharedPages", STAMUNIT_OCCURENCES, "The number of shared pages.");
1623	STAM_REG(pVM, &pPGM->cZeroPages, STAMTYPE_U32, "/PGM/Page/cZeroPages", STAMUNIT_OCCURENCES, "The number of zero backed pages.");
1624	STAM_REG(pVM, &pPGM->ChunkR3Map.c, STAMTYPE_U32, "/PGM/ChunkR3Map/c", STAMUNIT_OCCURENCES, "Number of mapped chunks.");
1625	STAM_REG(pVM, &pPGM->ChunkR3Map.cMax, STAMTYPE_U32, "/PGM/ChunkR3Map/cMax", STAMUNIT_OCCURENCES, "Maximum number of mapped chunks.");
1626
1627	/* Common - stats */
1628	#ifdef PGMPOOL_WITH_GCPHYS_TRACKING
1629	STAM_REG(pVM, &pPGM->StatTrackVirgin, STAMTYPE_COUNTER, "/PGM/Track/Virgin", STAMUNIT_OCCURENCES, "The number of first time shadowings");
1630	STAM_REG(pVM, &pPGM->StatTrackAliased, STAMTYPE_COUNTER, "/PGM/Track/Aliased", STAMUNIT_OCCURENCES, "The number of times switching to cRef2, i.e. the page is being shadowed by two PTs.");
1631	STAM_REG(pVM, &pPGM->StatTrackAliasedMany, STAMTYPE_COUNTER, "/PGM/Track/AliasedMany", STAMUNIT_OCCURENCES, "The number of times we're tracking using cRef2.");
1632	STAM_REG(pVM, &pPGM->StatTrackAliasedLots, STAMTYPE_COUNTER, "/PGM/Track/AliasedLots", STAMUNIT_OCCURENCES, "The number of times we're hitting pages which has overflowed cRef2");
1633	STAM_REG(pVM, &pPGM->StatTrackOverflows, STAMTYPE_COUNTER, "/PGM/Track/Overflows", STAMUNIT_OCCURENCES, "The number of times the extent list grows to long.");
1634	STAM_REG(pVM, &pPGM->StatTrackDeref, STAMTYPE_PROFILE, "/PGM/Track/Deref", STAMUNIT_OCCURENCES, "Profiling of SyncPageWorkerTrackDeref (expensive).");
1635	#endif
1636	for (i = 0; i < RT_ELEMENTS(pPGM->StatSyncPtPD); i++)
1637	STAMR3RegisterF(pVM, &pPGM->StatSyncPtPD[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
1638	"The number of SyncPT per PD n.", "/PGM/PDSyncPT/%04X", i);
1639	for (i = 0; i < RT_ELEMENTS(pPGM->StatSyncPagePD); i++)
1640	STAMR3RegisterF(pVM, &pPGM->StatSyncPagePD[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
1641	"The number of SyncPage per PD n.", "/PGM/PDSyncPage/%04X", i);
1642
1643	/* R3 only: */
1644	STAM_REG(pVM, &pPGM->StatR3DetectedConflicts, STAMTYPE_COUNTER, "/PGM/R3/DetectedConflicts", STAMUNIT_OCCURENCES, "The number of times PGMR3CheckMappingConflicts() detected a conflict.");
1645	STAM_REG(pVM, &pPGM->StatR3ResolveConflict, STAMTYPE_PROFILE, "/PGM/R3/ResolveConflict", STAMUNIT_TICKS_PER_CALL, "pgmR3SyncPTResolveConflict() profiling (includes the entire relocation).");
1646	STAM_REG(pVM, &pPGM->StatR3GuestPDWrite, STAMTYPE_COUNTER, "/PGM/R3/PDWrite", STAMUNIT_OCCURENCES, "The total number of times pgmHCGuestPDWriteHandler() was called.");
1647	STAM_REG(pVM, &pPGM->StatR3GuestPDWriteConflict, STAMTYPE_COUNTER, "/PGM/R3/PDWriteConflict", STAMUNIT_OCCURENCES, "The number of times pgmHCGuestPDWriteHandler() detected a conflict.");
1648	STAM_REG(pVM, &pPGM->StatR3DynRamTotal, STAMTYPE_COUNTER, "/PGM/DynAlloc/TotalAlloc", STAMUNIT_MEGABYTES, "Allocated MBs of guest ram.");
1649	STAM_REG(pVM, &pPGM->StatR3DynRamGrow, STAMTYPE_COUNTER, "/PGM/DynAlloc/Grow", STAMUNIT_OCCURENCES, "Nr of pgmr3PhysGrowRange calls.");
1650
1651	/* R0 only: */
1652	STAM_REG(pVM, &pPGM->StatR0DynMapMigrateInvlPg, STAMTYPE_COUNTER, "/PGM/R0/DynMapMigrateInvlPg", STAMUNIT_OCCURENCES, "invlpg count in PGMDynMapMigrateAutoSet.");
1653	STAM_REG(pVM, &pPGM->StatR0DynMapGCPageInl, STAMTYPE_PROFILE, "/PGM/R0/DynMapPageGCPageInl", STAMUNIT_TICKS_PER_CALL, "Calls to pgmR0DynMapGCPageInlined.");
1654	STAM_REG(pVM, &pPGM->StatR0DynMapGCPageInlHits, STAMTYPE_COUNTER, "/PGM/R0/DynMapPageGCPageInl/Hits", STAMUNIT_OCCURENCES, "Hash table lookup hits.");
1655	STAM_REG(pVM, &pPGM->StatR0DynMapGCPageInlMisses, STAMTYPE_COUNTER, "/PGM/R0/DynMapPageGCPageInl/Misses", STAMUNIT_OCCURENCES, "Misses that falls back to code common with PGMDynMapHCPage.");
1656	STAM_REG(pVM, &pPGM->StatR0DynMapGCPageInlRamHits, STAMTYPE_COUNTER, "/PGM/R0/DynMapPageGCPageInl/RamHits", STAMUNIT_OCCURENCES, "1st ram range hits.");
1657	STAM_REG(pVM, &pPGM->StatR0DynMapGCPageInlRamMisses, STAMTYPE_COUNTER, "/PGM/R0/DynMapPageGCPageInl/RamMisses", STAMUNIT_OCCURENCES, "1st ram range misses, takes slow path.");
1658	STAM_REG(pVM, &pPGM->StatR0DynMapHCPageInl, STAMTYPE_PROFILE, "/PGM/R0/DynMapPageHCPageInl", STAMUNIT_TICKS_PER_CALL, "Calls to pgmR0DynMapHCPageInlined.");
1659	STAM_REG(pVM, &pPGM->StatR0DynMapHCPageInlHits, STAMTYPE_COUNTER, "/PGM/R0/DynMapPageHCPageInl/Hits", STAMUNIT_OCCURENCES, "Hash table lookup hits.");
1660	STAM_REG(pVM, &pPGM->StatR0DynMapHCPageInlMisses, STAMTYPE_COUNTER, "/PGM/R0/DynMapPageHCPageInl/Misses", STAMUNIT_OCCURENCES, "Misses that falls back to code common with PGMDynMapHCPage.");
1661	STAM_REG(pVM, &pPGM->StatR0DynMapPage, STAMTYPE_COUNTER, "/PGM/R0/DynMapPage", STAMUNIT_OCCURENCES, "Calls to pgmR0DynMapPage");
1662	STAM_REG(pVM, &pPGM->StatR0DynMapSetOptimize, STAMTYPE_COUNTER, "/PGM/R0/DynMapPage/SetOptimize", STAMUNIT_OCCURENCES, "Calls to pgmDynMapOptimizeAutoSet.");
1663	STAM_REG(pVM, &pPGM->StatR0DynMapSetSearchFlushes, STAMTYPE_COUNTER, "/PGM/R0/DynMapPage/SetSearchFlushes",STAMUNIT_OCCURENCES, "Set search restorting to subset flushes.");
1664	STAM_REG(pVM, &pPGM->StatR0DynMapSetSearchHits, STAMTYPE_COUNTER, "/PGM/R0/DynMapPage/SetSearchHits", STAMUNIT_OCCURENCES, "Set search hits.");
1665	STAM_REG(pVM, &pPGM->StatR0DynMapSetSearchMisses, STAMTYPE_COUNTER, "/PGM/R0/DynMapPage/SetSearchMisses", STAMUNIT_OCCURENCES, "Set search misses.");
1666	STAM_REG(pVM, &pPGM->StatR0DynMapHCPage, STAMTYPE_PROFILE, "/PGM/R0/DynMapPage/HCPage", STAMUNIT_TICKS_PER_CALL, "Calls to PGMDynMapHCPage (ring-0).");
1667	STAM_REG(pVM, &pPGM->StatR0DynMapPageHits0, STAMTYPE_COUNTER, "/PGM/R0/DynMapPage/Hits0", STAMUNIT_OCCURENCES, "Hits at iPage+0");
1668	STAM_REG(pVM, &pPGM->StatR0DynMapPageHits1, STAMTYPE_COUNTER, "/PGM/R0/DynMapPage/Hits1", STAMUNIT_OCCURENCES, "Hits at iPage+1");
1669	STAM_REG(pVM, &pPGM->StatR0DynMapPageHits2, STAMTYPE_COUNTER, "/PGM/R0/DynMapPage/Hits2", STAMUNIT_OCCURENCES, "Hits at iPage+2");
1670	STAM_REG(pVM, &pPGM->StatR0DynMapPageInvlPg, STAMTYPE_COUNTER, "/PGM/R0/DynMapPage/InvlPg", STAMUNIT_OCCURENCES, "invlpg count in pgmR0DynMapPageSlow.");
1671	STAM_REG(pVM, &pPGM->StatR0DynMapPageSlow, STAMTYPE_COUNTER, "/PGM/R0/DynMapPage/Slow", STAMUNIT_OCCURENCES, "Calls to pgmR0DynMapPageSlow - subtract this from pgmR0DynMapPage to get 1st level hits.");
1672	STAM_REG(pVM, &pPGM->StatR0DynMapPageSlowLoopHits, STAMTYPE_COUNTER, "/PGM/R0/DynMapPage/SlowLoopHits" , STAMUNIT_OCCURENCES, "Hits in the loop path.");
1673	STAM_REG(pVM, &pPGM->StatR0DynMapPageSlowLoopMisses, STAMTYPE_COUNTER, "/PGM/R0/DynMapPage/SlowLoopMisses", STAMUNIT_OCCURENCES, "Misses in the loop path. NonLoopMisses = Slow - SlowLoopHit - SlowLoopMisses");
1674	//STAM_REG(pVM, &pPGM->StatR0DynMapPageSlowLostHits, STAMTYPE_COUNTER, "/PGM/R0/DynMapPage/SlowLostHits", STAMUNIT_OCCURENCES, "Lost hits.");
1675	STAM_REG(pVM, &pPGM->StatR0DynMapSubsets, STAMTYPE_COUNTER, "/PGM/R0/Subsets", STAMUNIT_OCCURENCES, "Times PGMDynMapPushAutoSubset was called.");
1676	STAM_REG(pVM, &pPGM->StatR0DynMapPopFlushes, STAMTYPE_COUNTER, "/PGM/R0/SubsetPopFlushes", STAMUNIT_OCCURENCES, "Times PGMDynMapPopAutoSubset flushes the subset.");
1677	STAM_REG(pVM, &pPGM->aStatR0DynMapSetSize[0], STAMTYPE_COUNTER, "/PGM/R0/SetSize000..09", STAMUNIT_OCCURENCES, "00-09% filled");
1678	STAM_REG(pVM, &pPGM->aStatR0DynMapSetSize[1], STAMTYPE_COUNTER, "/PGM/R0/SetSize010..19", STAMUNIT_OCCURENCES, "10-19% filled");
1679	STAM_REG(pVM, &pPGM->aStatR0DynMapSetSize[2], STAMTYPE_COUNTER, "/PGM/R0/SetSize020..29", STAMUNIT_OCCURENCES, "20-29% filled");
1680	STAM_REG(pVM, &pPGM->aStatR0DynMapSetSize[3], STAMTYPE_COUNTER, "/PGM/R0/SetSize030..39", STAMUNIT_OCCURENCES, "30-39% filled");
1681	STAM_REG(pVM, &pPGM->aStatR0DynMapSetSize[4], STAMTYPE_COUNTER, "/PGM/R0/SetSize040..49", STAMUNIT_OCCURENCES, "40-49% filled");
1682	STAM_REG(pVM, &pPGM->aStatR0DynMapSetSize[5], STAMTYPE_COUNTER, "/PGM/R0/SetSize050..59", STAMUNIT_OCCURENCES, "50-59% filled");
1683	STAM_REG(pVM, &pPGM->aStatR0DynMapSetSize[6], STAMTYPE_COUNTER, "/PGM/R0/SetSize060..69", STAMUNIT_OCCURENCES, "60-69% filled");
1684	STAM_REG(pVM, &pPGM->aStatR0DynMapSetSize[7], STAMTYPE_COUNTER, "/PGM/R0/SetSize070..79", STAMUNIT_OCCURENCES, "70-79% filled");
1685	STAM_REG(pVM, &pPGM->aStatR0DynMapSetSize[8], STAMTYPE_COUNTER, "/PGM/R0/SetSize080..89", STAMUNIT_OCCURENCES, "80-89% filled");
1686	STAM_REG(pVM, &pPGM->aStatR0DynMapSetSize[9], STAMTYPE_COUNTER, "/PGM/R0/SetSize090..99", STAMUNIT_OCCURENCES, "90-99% filled");
1687	STAM_REG(pVM, &pPGM->aStatR0DynMapSetSize[10], STAMTYPE_COUNTER, "/PGM/R0/SetSize100", STAMUNIT_OCCURENCES, "100% filled");
1688
1689	/* GC only: */
1690	STAM_REG(pVM, &pPGM->StatRCDynMapCacheHits, STAMTYPE_COUNTER, "/PGM/RC/DynMapCache/Hits" , STAMUNIT_OCCURENCES, "Number of dynamic page mapping cache hits.");
1691	STAM_REG(pVM, &pPGM->StatRCDynMapCacheMisses, STAMTYPE_COUNTER, "/PGM/RC/DynMapCache/Misses" , STAMUNIT_OCCURENCES, "Number of dynamic page mapping cache misses.");
1692	STAM_REG(pVM, &pPGM->StatRCInvlPgConflict, STAMTYPE_COUNTER, "/PGM/RC/InvlPgConflict", STAMUNIT_OCCURENCES, "Number of times PGMInvalidatePage() detected a mapping conflict.");
1693	STAM_REG(pVM, &pPGM->StatRCInvlPgSyncMonCR3, STAMTYPE_COUNTER, "/PGM/RC/InvlPgSyncMonitorCR3", STAMUNIT_OCCURENCES, "Number of times PGMInvalidatePage() ran into PGM_SYNC_MONITOR_CR3.");
1694
1695	/* RZ only: */
1696	STAM_REG(pVM, &pPGM->StatRZTrap0e, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMTrap0eHandler() body.");
1697	STAM_REG(pVM, &pPGM->StatRZTrap0eTimeCheckPageFault, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time/CheckPageFault", STAMUNIT_TICKS_PER_CALL, "Profiling of checking for dirty/access emulation faults.");
1698	STAM_REG(pVM, &pPGM->StatRZTrap0eTimeSyncPT, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time/SyncPT", STAMUNIT_TICKS_PER_CALL, "Profiling of lazy page table syncing.");
1699	STAM_REG(pVM, &pPGM->StatRZTrap0eTimeMapping, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time/Mapping", STAMUNIT_TICKS_PER_CALL, "Profiling of checking virtual mappings.");
1700	STAM_REG(pVM, &pPGM->StatRZTrap0eTimeOutOfSync, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time/OutOfSync", STAMUNIT_TICKS_PER_CALL, "Profiling of out of sync page handling.");
1701	STAM_REG(pVM, &pPGM->StatRZTrap0eTimeHandlers, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time/Handlers", STAMUNIT_TICKS_PER_CALL, "Profiling of checking handlers.");
1702	STAM_REG(pVM, &pPGM->StatRZTrap0eTime2CSAM, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time2/CSAM", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is CSAM.");
1703	STAM_REG(pVM, &pPGM->StatRZTrap0eTime2DirtyAndAccessed, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time2/DirtyAndAccessedBits", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is dirty and/or accessed bit emulation.");
1704	STAM_REG(pVM, &pPGM->StatRZTrap0eTime2GuestTrap, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time2/GuestTrap", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is a guest trap.");
1705	STAM_REG(pVM, &pPGM->StatRZTrap0eTime2HndPhys, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time2/HandlerPhysical", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is a physical handler.");
1706	STAM_REG(pVM, &pPGM->StatRZTrap0eTime2HndVirt, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time2/HandlerVirtual", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is a virtual handler.");
1707	STAM_REG(pVM, &pPGM->StatRZTrap0eTime2HndUnhandled, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time2/HandlerUnhandled", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is access outside the monitored areas of a monitored page.");
1708	STAM_REG(pVM, &pPGM->StatRZTrap0eTime2Misc, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time2/Misc", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is not known.");
1709	STAM_REG(pVM, &pPGM->StatRZTrap0eTime2OutOfSync, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time2/OutOfSync", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is an out-of-sync page.");
1710	STAM_REG(pVM, &pPGM->StatRZTrap0eTime2OutOfSyncHndPhys, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time2/OutOfSyncHndPhys", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is an out-of-sync physical handler page.");
1711	STAM_REG(pVM, &pPGM->StatRZTrap0eTime2OutOfSyncHndVirt, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time2/OutOfSyncHndVirt", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is an out-of-sync virtual handler page.");
1712	STAM_REG(pVM, &pPGM->StatRZTrap0eTime2OutOfSyncHndObs, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time2/OutOfSyncObsHnd", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is an obsolete handler page.");
1713	STAM_REG(pVM, &pPGM->StatRZTrap0eTime2SyncPT, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time2/SyncPT", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is lazy syncing of a PT.");
1714	STAM_REG(pVM, &pPGM->StatRZTrap0eConflicts, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Conflicts", STAMUNIT_OCCURENCES, "The number of times #PF was caused by an undetected conflict.");
1715	STAM_REG(pVM, &pPGM->StatRZTrap0eHandlersMapping, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Handlers/Mapping", STAMUNIT_OCCURENCES, "Number of traps due to access handlers in mappings.");
1716	STAM_REG(pVM, &pPGM->StatRZTrap0eHandlersOutOfSync, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Handlers/OutOfSync", STAMUNIT_OCCURENCES, "Number of traps due to out-of-sync handled pages.");
1717	STAM_REG(pVM, &pPGM->StatRZTrap0eHandlersPhysical, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Handlers/Physical", STAMUNIT_OCCURENCES, "Number of traps due to physical access handlers.");
1718	STAM_REG(pVM, &pPGM->StatRZTrap0eHandlersVirtual, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Handlers/Virtual", STAMUNIT_OCCURENCES, "Number of traps due to virtual access handlers.");
1719	STAM_REG(pVM, &pPGM->StatRZTrap0eHandlersVirtualByPhys, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Handlers/VirtualByPhys", STAMUNIT_OCCURENCES, "Number of traps due to virtual access handlers by physical address.");
1720	STAM_REG(pVM, &pPGM->StatRZTrap0eHandlersVirtualUnmarked,STAMTYPE_COUNTER,"/PGM/RZ/Trap0e/Handlers/VirtualUnmarked",STAMUNIT_OCCURENCES, "Number of traps due to virtual access handlers by virtual address (without proper physical flags).");
1721	STAM_REG(pVM, &pPGM->StatRZTrap0eHandlersUnhandled, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Handlers/Unhandled", STAMUNIT_OCCURENCES, "Number of traps due to access outside range of monitored page(s).");
1722	STAM_REG(pVM, &pPGM->StatRZTrap0eHandlersInvalid, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Handlers/Invalid", STAMUNIT_OCCURENCES, "Number of traps due to access to invalid physical memory.");
1723	STAM_REG(pVM, &pPGM->StatRZTrap0eUSNotPresentRead, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Err/User/NPRead", STAMUNIT_OCCURENCES, "Number of user mode not present read page faults.");
1724	STAM_REG(pVM, &pPGM->StatRZTrap0eUSNotPresentWrite, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Err/User/NPWrite", STAMUNIT_OCCURENCES, "Number of user mode not present write page faults.");
1725	STAM_REG(pVM, &pPGM->StatRZTrap0eUSWrite, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Err/User/Write", STAMUNIT_OCCURENCES, "Number of user mode write page faults.");
1726	STAM_REG(pVM, &pPGM->StatRZTrap0eUSReserved, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Err/User/Reserved", STAMUNIT_OCCURENCES, "Number of user mode reserved bit page faults.");
1727	STAM_REG(pVM, &pPGM->StatRZTrap0eUSNXE, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Err/User/NXE", STAMUNIT_OCCURENCES, "Number of user mode NXE page faults.");
1728	STAM_REG(pVM, &pPGM->StatRZTrap0eUSRead, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Err/User/Read", STAMUNIT_OCCURENCES, "Number of user mode read page faults.");
1729	STAM_REG(pVM, &pPGM->StatRZTrap0eSVNotPresentRead, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Err/Supervisor/NPRead", STAMUNIT_OCCURENCES, "Number of supervisor mode not present read page faults.");
1730	STAM_REG(pVM, &pPGM->StatRZTrap0eSVNotPresentWrite, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Err/Supervisor/NPWrite", STAMUNIT_OCCURENCES, "Number of supervisor mode not present write page faults.");
1731	STAM_REG(pVM, &pPGM->StatRZTrap0eSVWrite, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Err/Supervisor/Write", STAMUNIT_OCCURENCES, "Number of supervisor mode write page faults.");
1732	STAM_REG(pVM, &pPGM->StatRZTrap0eSVReserved, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Err/Supervisor/Reserved", STAMUNIT_OCCURENCES, "Number of supervisor mode reserved bit page faults.");
1733	STAM_REG(pVM, &pPGM->StatRZTrap0eSNXE, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Err/Supervisor/NXE", STAMUNIT_OCCURENCES, "Number of supervisor mode NXE page faults.");
1734	STAM_REG(pVM, &pPGM->StatRZTrap0eGuestPF, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/GuestPF", STAMUNIT_OCCURENCES, "Number of real guest page faults.");
1735	STAM_REG(pVM, &pPGM->StatRZTrap0eGuestPFUnh, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/GuestPF/Unhandled", STAMUNIT_OCCURENCES, "Number of real guest page faults from the 'unhandled' case.");
1736	STAM_REG(pVM, &pPGM->StatRZTrap0eGuestPFMapping, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/GuestPF/InMapping", STAMUNIT_OCCURENCES, "Number of real guest page faults in a mapping.");
1737	STAM_REG(pVM, &pPGM->StatRZTrap0eWPEmulInRZ, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/WP/InRZ", STAMUNIT_OCCURENCES, "Number of guest page faults due to X86_CR0_WP emulation.");
1738	STAM_REG(pVM, &pPGM->StatRZTrap0eWPEmulToR3, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/WP/ToR3", STAMUNIT_OCCURENCES, "Number of guest page faults due to X86_CR0_WP emulation (forward to R3 for emulation).");
1739	for (i = 0; i < RT_ELEMENTS(pPGM->StatRZTrap0ePD); i++)
1740	STAMR3RegisterF(pVM, &pPGM->StatRZTrap0ePD[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
1741	"The number of traps in page directory n.", "/PGM/RZ/Trap0e/PD/%04X", i);
1742	STAM_REG(pVM, &pPGM->StatRZGuestCR3WriteHandled, STAMTYPE_COUNTER, "/PGM/RZ/CR3WriteHandled", STAMUNIT_OCCURENCES, "The number of times the Guest CR3 change was successfully handled.");
1743	STAM_REG(pVM, &pPGM->StatRZGuestCR3WriteUnhandled, STAMTYPE_COUNTER, "/PGM/RZ/CR3WriteUnhandled", STAMUNIT_OCCURENCES, "The number of times the Guest CR3 change was passed back to the recompiler.");
1744	STAM_REG(pVM, &pPGM->StatRZGuestCR3WriteConflict, STAMTYPE_COUNTER, "/PGM/RZ/CR3WriteConflict", STAMUNIT_OCCURENCES, "The number of times the Guest CR3 monitoring detected a conflict.");
1745	STAM_REG(pVM, &pPGM->StatRZGuestROMWriteHandled, STAMTYPE_COUNTER, "/PGM/RZ/ROMWriteHandled", STAMUNIT_OCCURENCES, "The number of times the Guest ROM change was successfully handled.");
1746	STAM_REG(pVM, &pPGM->StatRZGuestROMWriteUnhandled, STAMTYPE_COUNTER, "/PGM/RZ/ROMWriteUnhandled", STAMUNIT_OCCURENCES, "The number of times the Guest ROM change was passed back to the recompiler.");
1747
1748	/* HC only: */
1749
1750	/* RZ & R3: */
1751	STAM_REG(pVM, &pPGM->StatRZSyncCR3, STAMTYPE_PROFILE, "/PGM/RZ/SyncCR3", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMSyncCR3() body.");
1752	STAM_REG(pVM, &pPGM->StatRZSyncCR3Handlers, STAMTYPE_PROFILE, "/PGM/RZ/SyncCR3/Handlers", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMSyncCR3() update handler section.");
1753	STAM_REG(pVM, &pPGM->StatRZSyncCR3HandlerVirtualUpdate, STAMTYPE_PROFILE, "/PGM/RZ/SyncCR3/Handlers/VirtualUpdate", STAMUNIT_TICKS_PER_CALL, "Profiling of the virtual handler updates.");
1754	STAM_REG(pVM, &pPGM->StatRZSyncCR3HandlerVirtualReset, STAMTYPE_PROFILE, "/PGM/RZ/SyncCR3/Handlers/VirtualReset", STAMUNIT_TICKS_PER_CALL, "Profiling of the virtual handler resets.");
1755	STAM_REG(pVM, &pPGM->StatRZSyncCR3Global, STAMTYPE_COUNTER, "/PGM/RZ/SyncCR3/Global", STAMUNIT_OCCURENCES, "The number of global CR3 syncs.");
1756	STAM_REG(pVM, &pPGM->StatRZSyncCR3NotGlobal, STAMTYPE_COUNTER, "/PGM/RZ/SyncCR3/NotGlobal", STAMUNIT_OCCURENCES, "The number of non-global CR3 syncs.");
1757	STAM_REG(pVM, &pPGM->StatRZSyncCR3DstCacheHit, STAMTYPE_COUNTER, "/PGM/RZ/SyncCR3/DstChacheHit", STAMUNIT_OCCURENCES, "The number of times we got some kind of a cache hit.");
1758	STAM_REG(pVM, &pPGM->StatRZSyncCR3DstFreed, STAMTYPE_COUNTER, "/PGM/RZ/SyncCR3/DstFreed", STAMUNIT_OCCURENCES, "The number of times we've had to free a shadow entry.");
1759	STAM_REG(pVM, &pPGM->StatRZSyncCR3DstFreedSrcNP, STAMTYPE_COUNTER, "/PGM/RZ/SyncCR3/DstFreedSrcNP", STAMUNIT_OCCURENCES, "The number of times we've had to free a shadow entry for which the source entry was not present.");
1760	STAM_REG(pVM, &pPGM->StatRZSyncCR3DstNotPresent, STAMTYPE_COUNTER, "/PGM/RZ/SyncCR3/DstNotPresent", STAMUNIT_OCCURENCES, "The number of times we've encountered a not present shadow entry for a present guest entry.");
1761	STAM_REG(pVM, &pPGM->StatRZSyncCR3DstSkippedGlobalPD, STAMTYPE_COUNTER, "/PGM/RZ/SyncCR3/DstSkippedGlobalPD", STAMUNIT_OCCURENCES, "The number of times a global page directory wasn't flushed.");
1762	STAM_REG(pVM, &pPGM->StatRZSyncCR3DstSkippedGlobalPT, STAMTYPE_COUNTER, "/PGM/RZ/SyncCR3/DstSkippedGlobalPT", STAMUNIT_OCCURENCES, "The number of times a page table with only global entries wasn't flushed.");
1763	STAM_REG(pVM, &pPGM->StatRZSyncPT, STAMTYPE_PROFILE, "/PGM/RZ/SyncPT", STAMUNIT_TICKS_PER_CALL, "Profiling of the pfnSyncPT() body.");
1764	STAM_REG(pVM, &pPGM->StatRZSyncPTFailed, STAMTYPE_COUNTER, "/PGM/RZ/SyncPT/Failed", STAMUNIT_OCCURENCES, "The number of times pfnSyncPT() failed.");
1765	STAM_REG(pVM, &pPGM->StatRZSyncPT4K, STAMTYPE_COUNTER, "/PGM/RZ/SyncPT/4K", STAMUNIT_OCCURENCES, "Nr of 4K PT syncs");
1766	STAM_REG(pVM, &pPGM->StatRZSyncPT4M, STAMTYPE_COUNTER, "/PGM/RZ/SyncPT/4M", STAMUNIT_OCCURENCES, "Nr of 4M PT syncs");
1767	STAM_REG(pVM, &pPGM->StatRZSyncPagePDNAs, STAMTYPE_COUNTER, "/PGM/RZ/SyncPagePDNAs", STAMUNIT_OCCURENCES, "The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit.");
1768	STAM_REG(pVM, &pPGM->StatRZSyncPagePDOutOfSync, STAMTYPE_COUNTER, "/PGM/RZ/SyncPagePDOutOfSync", STAMUNIT_OCCURENCES, "The number of time we've encountered an out-of-sync PD in SyncPage.");
1769	STAM_REG(pVM, &pPGM->StatRZAccessedPage, STAMTYPE_COUNTER, "/PGM/RZ/AccessedPage", STAMUNIT_OCCURENCES, "The number of pages marked not present for accessed bit emulation.");
1770	STAM_REG(pVM, &pPGM->StatRZDirtyBitTracking, STAMTYPE_PROFILE, "/PGM/RZ/DirtyPage", STAMUNIT_TICKS_PER_CALL, "Profiling the dirty bit tracking in CheckPageFault().");
1771	STAM_REG(pVM, &pPGM->StatRZDirtyPage, STAMTYPE_COUNTER, "/PGM/RZ/DirtyPage/Mark", STAMUNIT_OCCURENCES, "The number of pages marked read-only for dirty bit tracking.");
1772	STAM_REG(pVM, &pPGM->StatRZDirtyPageBig, STAMTYPE_COUNTER, "/PGM/RZ/DirtyPage/MarkBig", STAMUNIT_OCCURENCES, "The number of 4MB pages marked read-only for dirty bit tracking.");
1773	STAM_REG(pVM, &pPGM->StatRZDirtyPageSkipped, STAMTYPE_COUNTER, "/PGM/RZ/DirtyPage/Skipped", STAMUNIT_OCCURENCES, "The number of pages already dirty or readonly.");
1774	STAM_REG(pVM, &pPGM->StatRZDirtyPageTrap, STAMTYPE_COUNTER, "/PGM/RZ/DirtyPage/Trap", STAMUNIT_OCCURENCES, "The number of traps generated for dirty bit tracking.");
1775	STAM_REG(pVM, &pPGM->StatRZDirtiedPage, STAMTYPE_COUNTER, "/PGM/RZ/DirtyPage/SetDirty", STAMUNIT_OCCURENCES, "The number of pages marked dirty because of write accesses.");
1776	STAM_REG(pVM, &pPGM->StatRZDirtyTrackRealPF, STAMTYPE_COUNTER, "/PGM/RZ/DirtyPage/RealPF", STAMUNIT_OCCURENCES, "The number of real pages faults during dirty bit tracking.");
1777	STAM_REG(pVM, &pPGM->StatRZPageAlreadyDirty, STAMTYPE_COUNTER, "/PGM/RZ/DirtyPage/AlreadySet", STAMUNIT_OCCURENCES, "The number of pages already marked dirty because of write accesses.");
1778	STAM_REG(pVM, &pPGM->StatRZInvalidatePage, STAMTYPE_PROFILE, "/PGM/RZ/InvalidatePage", STAMUNIT_TICKS_PER_CALL, "PGMInvalidatePage() profiling.");
1779	STAM_REG(pVM, &pPGM->StatRZInvalidatePage4KBPages, STAMTYPE_COUNTER, "/PGM/RZ/InvalidatePage/4KBPages", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was called for a 4KB page.");
1780	STAM_REG(pVM, &pPGM->StatRZInvalidatePage4MBPages, STAMTYPE_COUNTER, "/PGM/RZ/InvalidatePage/4MBPages", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was called for a 4MB page.");
1781	STAM_REG(pVM, &pPGM->StatRZInvalidatePage4MBPagesSkip, STAMTYPE_COUNTER, "/PGM/RZ/InvalidatePage/4MBPagesSkip",STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() skipped a 4MB page.");
1782	STAM_REG(pVM, &pPGM->StatRZInvalidatePagePDMappings, STAMTYPE_COUNTER, "/PGM/RZ/InvalidatePage/PDMappings", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict).");
1783	STAM_REG(pVM, &pPGM->StatRZInvalidatePagePDNAs, STAMTYPE_COUNTER, "/PGM/RZ/InvalidatePage/PDNAs", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was called for a not accessed page directory.");
1784	STAM_REG(pVM, &pPGM->StatRZInvalidatePagePDNPs, STAMTYPE_COUNTER, "/PGM/RZ/InvalidatePage/PDNPs", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was called for a not present page directory.");
1785	STAM_REG(pVM, &pPGM->StatRZInvalidatePagePDOutOfSync, STAMTYPE_COUNTER, "/PGM/RZ/InvalidatePage/PDOutOfSync", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was called for an out of sync page directory.");
1786	STAM_REG(pVM, &pPGM->StatRZInvalidatePageSkipped, STAMTYPE_COUNTER, "/PGM/RZ/InvalidatePage/Skipped", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3.");
1787	STAM_REG(pVM, &pPGM->StatRZVirtHandlerSearchByPhys, STAMTYPE_PROFILE, "/PGM/RZ/VirtHandlerSearchByPhys", STAMUNIT_TICKS_PER_CALL, "Profiling of pgmHandlerVirtualFindByPhysAddr.");
1788	STAM_REG(pVM, &pPGM->StatRZPhysHandlerReset, STAMTYPE_COUNTER, "/PGM/RZ/PhysHandlerReset", STAMUNIT_OCCURENCES, "The number of times PGMHandlerPhysicalReset is called.");
1789	STAM_REG(pVM, &pPGM->StatRZPageOutOfSyncSupervisor, STAMTYPE_COUNTER, "/PGM/RZ/OutOfSync/SuperVisor", STAMUNIT_OCCURENCES, "Number of traps due to pages out of sync and times VerifyAccessSyncPage calls SyncPage.");
1790	STAM_REG(pVM, &pPGM->StatRZPageOutOfSyncUser, STAMTYPE_COUNTER, "/PGM/RZ/OutOfSync/User", STAMUNIT_OCCURENCES, "Number of traps due to pages out of sync and times VerifyAccessSyncPage calls SyncPage.");
1791	STAM_REG(pVM, &pPGM->StatRZPrefetch, STAMTYPE_PROFILE, "/PGM/RZ/Prefetch", STAMUNIT_TICKS_PER_CALL, "PGMPrefetchPage profiling.");
1792	STAM_REG(pVM, &pPGM->StatRZChunkR3MapTlbHits, STAMTYPE_COUNTER, "/PGM/ChunkR3Map/TlbHitsRZ", STAMUNIT_OCCURENCES, "TLB hits.");
1793	STAM_REG(pVM, &pPGM->StatRZChunkR3MapTlbMisses, STAMTYPE_COUNTER, "/PGM/ChunkR3Map/TlbMissesRZ", STAMUNIT_OCCURENCES, "TLB misses.");
1794	STAM_REG(pVM, &pPGM->StatRZPageMapTlbHits, STAMTYPE_COUNTER, "/PGM/RZ/Page/MapTlbHits", STAMUNIT_OCCURENCES, "TLB hits.");
1795	STAM_REG(pVM, &pPGM->StatRZPageMapTlbMisses, STAMTYPE_COUNTER, "/PGM/RZ/Page/MapTlbMisses", STAMUNIT_OCCURENCES, "TLB misses.");
1796	STAM_REG(pVM, &pPGM->StatRZPageReplaceShared, STAMTYPE_COUNTER, "/PGM/RZ/Page/ReplacedShared", STAMUNIT_OCCURENCES, "Times a shared page was replaced.");
1797	STAM_REG(pVM, &pPGM->StatRZPageReplaceZero, STAMTYPE_COUNTER, "/PGM/RZ/Page/ReplacedZero", STAMUNIT_OCCURENCES, "Times the zero page was replaced.");
1798	/// @todo STAM_REG(pVM, &pPGM->StatRZPageHandyAllocs, STAMTYPE_COUNTER, "/PGM/RZ/Page/HandyAllocs", STAMUNIT_OCCURENCES, "Number of times we've allocated more handy pages.");
1799	STAM_REG(pVM, &pPGM->StatRZFlushTLB, STAMTYPE_PROFILE, "/PGM/RZ/FlushTLB", STAMUNIT_OCCURENCES, "Profiling of the PGMFlushTLB() body.");
1800	STAM_REG(pVM, &pPGM->StatRZFlushTLBNewCR3, STAMTYPE_COUNTER, "/PGM/RZ/FlushTLB/NewCR3", STAMUNIT_OCCURENCES, "The number of times PGMFlushTLB was called with a new CR3, non-global. (switch)");
1801	STAM_REG(pVM, &pPGM->StatRZFlushTLBNewCR3Global, STAMTYPE_COUNTER, "/PGM/RZ/FlushTLB/NewCR3Global", STAMUNIT_OCCURENCES, "The number of times PGMFlushTLB was called with a new CR3, global. (switch)");
1802	STAM_REG(pVM, &pPGM->StatRZFlushTLBSameCR3, STAMTYPE_COUNTER, "/PGM/RZ/FlushTLB/SameCR3", STAMUNIT_OCCURENCES, "The number of times PGMFlushTLB was called with the same CR3, non-global. (flush)");
1803	STAM_REG(pVM, &pPGM->StatRZFlushTLBSameCR3Global, STAMTYPE_COUNTER, "/PGM/RZ/FlushTLB/SameCR3Global", STAMUNIT_OCCURENCES, "The number of times PGMFlushTLB was called with the same CR3, global. (flush)");
1804	STAM_REG(pVM, &pPGM->StatRZGstModifyPage, STAMTYPE_PROFILE, "/PGM/RZ/GstModifyPage", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMGstModifyPage() body.");
1805
1806	STAM_REG(pVM, &pPGM->StatR3SyncCR3, STAMTYPE_PROFILE, "/PGM/R3/SyncCR3", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMSyncCR3() body.");
1807	STAM_REG(pVM, &pPGM->StatR3SyncCR3Handlers, STAMTYPE_PROFILE, "/PGM/R3/SyncCR3/Handlers", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMSyncCR3() update handler section.");
1808	STAM_REG(pVM, &pPGM->StatR3SyncCR3HandlerVirtualUpdate, STAMTYPE_PROFILE, "/PGM/R3/SyncCR3/Handlers/VirtualUpdate", STAMUNIT_TICKS_PER_CALL, "Profiling of the virtual handler updates.");
1809	STAM_REG(pVM, &pPGM->StatR3SyncCR3HandlerVirtualReset, STAMTYPE_PROFILE, "/PGM/R3/SyncCR3/Handlers/VirtualReset", STAMUNIT_TICKS_PER_CALL, "Profiling of the virtual handler resets.");
1810	STAM_REG(pVM, &pPGM->StatR3SyncCR3Global, STAMTYPE_COUNTER, "/PGM/R3/SyncCR3/Global", STAMUNIT_OCCURENCES, "The number of global CR3 syncs.");
1811	STAM_REG(pVM, &pPGM->StatR3SyncCR3NotGlobal, STAMTYPE_COUNTER, "/PGM/R3/SyncCR3/NotGlobal", STAMUNIT_OCCURENCES, "The number of non-global CR3 syncs.");
1812	STAM_REG(pVM, &pPGM->StatR3SyncCR3DstCacheHit, STAMTYPE_COUNTER, "/PGM/R3/SyncCR3/DstChacheHit", STAMUNIT_OCCURENCES, "The number of times we got some kind of a cache hit.");
1813	STAM_REG(pVM, &pPGM->StatR3SyncCR3DstFreed, STAMTYPE_COUNTER, "/PGM/R3/SyncCR3/DstFreed", STAMUNIT_OCCURENCES, "The number of times we've had to free a shadow entry.");
1814	STAM_REG(pVM, &pPGM->StatR3SyncCR3DstFreedSrcNP, STAMTYPE_COUNTER, "/PGM/R3/SyncCR3/DstFreedSrcNP", STAMUNIT_OCCURENCES, "The number of times we've had to free a shadow entry for which the source entry was not present.");
1815	STAM_REG(pVM, &pPGM->StatR3SyncCR3DstNotPresent, STAMTYPE_COUNTER, "/PGM/R3/SyncCR3/DstNotPresent", STAMUNIT_OCCURENCES, "The number of times we've encountered a not present shadow entry for a present guest entry.");
1816	STAM_REG(pVM, &pPGM->StatR3SyncCR3DstSkippedGlobalPD, STAMTYPE_COUNTER, "/PGM/R3/SyncCR3/DstSkippedGlobalPD", STAMUNIT_OCCURENCES, "The number of times a global page directory wasn't flushed.");
1817	STAM_REG(pVM, &pPGM->StatR3SyncCR3DstSkippedGlobalPT, STAMTYPE_COUNTER, "/PGM/R3/SyncCR3/DstSkippedGlobalPT", STAMUNIT_OCCURENCES, "The number of times a page table with only global entries wasn't flushed.");
1818	STAM_REG(pVM, &pPGM->StatR3SyncPT, STAMTYPE_PROFILE, "/PGM/R3/SyncPT", STAMUNIT_TICKS_PER_CALL, "Profiling of the pfnSyncPT() body.");
1819	STAM_REG(pVM, &pPGM->StatR3SyncPTFailed, STAMTYPE_COUNTER, "/PGM/R3/SyncPT/Failed", STAMUNIT_OCCURENCES, "The number of times pfnSyncPT() failed.");
1820	STAM_REG(pVM, &pPGM->StatR3SyncPT4K, STAMTYPE_COUNTER, "/PGM/R3/SyncPT/4K", STAMUNIT_OCCURENCES, "Nr of 4K PT syncs");
1821	STAM_REG(pVM, &pPGM->StatR3SyncPT4M, STAMTYPE_COUNTER, "/PGM/R3/SyncPT/4M", STAMUNIT_OCCURENCES, "Nr of 4M PT syncs");
1822	STAM_REG(pVM, &pPGM->StatR3SyncPagePDNAs, STAMTYPE_COUNTER, "/PGM/R3/SyncPagePDNAs", STAMUNIT_OCCURENCES, "The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit.");
1823	STAM_REG(pVM, &pPGM->StatR3SyncPagePDOutOfSync, STAMTYPE_COUNTER, "/PGM/R3/SyncPagePDOutOfSync", STAMUNIT_OCCURENCES, "The number of time we've encountered an out-of-sync PD in SyncPage.");
1824	STAM_REG(pVM, &pPGM->StatR3AccessedPage, STAMTYPE_COUNTER, "/PGM/R3/AccessedPage", STAMUNIT_OCCURENCES, "The number of pages marked not present for accessed bit emulation.");
1825	STAM_REG(pVM, &pPGM->StatR3DirtyBitTracking, STAMTYPE_PROFILE, "/PGM/R3/DirtyPage", STAMUNIT_TICKS_PER_CALL, "Profiling the dirty bit tracking in CheckPageFault().");
1826	STAM_REG(pVM, &pPGM->StatR3DirtyPage, STAMTYPE_COUNTER, "/PGM/R3/DirtyPage/Mark", STAMUNIT_OCCURENCES, "The number of pages marked read-only for dirty bit tracking.");
1827	STAM_REG(pVM, &pPGM->StatR3DirtyPageBig, STAMTYPE_COUNTER, "/PGM/R3/DirtyPage/MarkBig", STAMUNIT_OCCURENCES, "The number of 4MB pages marked read-only for dirty bit tracking.");
1828	STAM_REG(pVM, &pPGM->StatR3DirtyPageSkipped, STAMTYPE_COUNTER, "/PGM/R3/DirtyPage/Skipped", STAMUNIT_OCCURENCES, "The number of pages already dirty or readonly.");
1829	STAM_REG(pVM, &pPGM->StatR3DirtyPageTrap, STAMTYPE_COUNTER, "/PGM/R3/DirtyPage/Trap", STAMUNIT_OCCURENCES, "The number of traps generated for dirty bit tracking.");
1830	STAM_REG(pVM, &pPGM->StatR3DirtiedPage, STAMTYPE_COUNTER, "/PGM/R3/DirtyPage/SetDirty", STAMUNIT_OCCURENCES, "The number of pages marked dirty because of write accesses.");
1831	STAM_REG(pVM, &pPGM->StatR3DirtyTrackRealPF, STAMTYPE_COUNTER, "/PGM/R3/DirtyPage/RealPF", STAMUNIT_OCCURENCES, "The number of real pages faults during dirty bit tracking.");
1832	STAM_REG(pVM, &pPGM->StatR3PageAlreadyDirty, STAMTYPE_COUNTER, "/PGM/R3/DirtyPage/AlreadySet", STAMUNIT_OCCURENCES, "The number of pages already marked dirty because of write accesses.");
1833	STAM_REG(pVM, &pPGM->StatR3InvalidatePage, STAMTYPE_PROFILE, "/PGM/R3/InvalidatePage", STAMUNIT_TICKS_PER_CALL, "PGMInvalidatePage() profiling.");
1834	STAM_REG(pVM, &pPGM->StatR3InvalidatePage4KBPages, STAMTYPE_COUNTER, "/PGM/R3/InvalidatePage/4KBPages", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was called for a 4KB page.");
1835	STAM_REG(pVM, &pPGM->StatR3InvalidatePage4MBPages, STAMTYPE_COUNTER, "/PGM/R3/InvalidatePage/4MBPages", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was called for a 4MB page.");
1836	STAM_REG(pVM, &pPGM->StatR3InvalidatePage4MBPagesSkip, STAMTYPE_COUNTER, "/PGM/R3/InvalidatePage/4MBPagesSkip",STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() skipped a 4MB page.");
1837	STAM_REG(pVM, &pPGM->StatR3InvalidatePagePDMappings, STAMTYPE_COUNTER, "/PGM/R3/InvalidatePage/PDMappings", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict).");
1838	STAM_REG(pVM, &pPGM->StatR3InvalidatePagePDNAs, STAMTYPE_COUNTER, "/PGM/R3/InvalidatePage/PDNAs", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was called for a not accessed page directory.");
1839	STAM_REG(pVM, &pPGM->StatR3InvalidatePagePDNPs, STAMTYPE_COUNTER, "/PGM/R3/InvalidatePage/PDNPs", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was called for a not present page directory.");
1840	STAM_REG(pVM, &pPGM->StatR3InvalidatePagePDOutOfSync, STAMTYPE_COUNTER, "/PGM/R3/InvalidatePage/PDOutOfSync", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was called for an out of sync page directory.");
1841	STAM_REG(pVM, &pPGM->StatR3InvalidatePageSkipped, STAMTYPE_COUNTER, "/PGM/R3/InvalidatePage/Skipped", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3.");
1842	STAM_REG(pVM, &pPGM->StatR3VirtHandlerSearchByPhys, STAMTYPE_PROFILE, "/PGM/R3/VirtHandlerSearchByPhys", STAMUNIT_TICKS_PER_CALL, "Profiling of pgmHandlerVirtualFindByPhysAddr.");
1843	STAM_REG(pVM, &pPGM->StatR3PhysHandlerReset, STAMTYPE_COUNTER, "/PGM/R3/PhysHandlerReset", STAMUNIT_OCCURENCES, "The number of times PGMHandlerPhysicalReset is called.");
1844	STAM_REG(pVM, &pPGM->StatR3PageOutOfSyncSupervisor, STAMTYPE_COUNTER, "/PGM/R3/OutOfSync/SuperVisor", STAMUNIT_OCCURENCES, "Number of traps due to pages out of sync and times VerifyAccessSyncPage calls SyncPage.");
1845	STAM_REG(pVM, &pPGM->StatR3PageOutOfSyncUser, STAMTYPE_COUNTER, "/PGM/R3/OutOfSync/User", STAMUNIT_OCCURENCES, "Number of traps due to pages out of sync and times VerifyAccessSyncPage calls SyncPage.");
1846	STAM_REG(pVM, &pPGM->StatR3Prefetch, STAMTYPE_PROFILE, "/PGM/R3/Prefetch", STAMUNIT_TICKS_PER_CALL, "PGMPrefetchPage profiling.");
1847	STAM_REG(pVM, &pPGM->StatR3ChunkR3MapTlbHits, STAMTYPE_COUNTER, "/PGM/ChunkR3Map/TlbHitsR3", STAMUNIT_OCCURENCES, "TLB hits.");
1848	STAM_REG(pVM, &pPGM->StatR3ChunkR3MapTlbMisses, STAMTYPE_COUNTER, "/PGM/ChunkR3Map/TlbMissesR3", STAMUNIT_OCCURENCES, "TLB misses.");
1849	STAM_REG(pVM, &pPGM->StatR3PageMapTlbHits, STAMTYPE_COUNTER, "/PGM/R3/Page/MapTlbHits", STAMUNIT_OCCURENCES, "TLB hits.");
1850	STAM_REG(pVM, &pPGM->StatR3PageMapTlbMisses, STAMTYPE_COUNTER, "/PGM/R3/Page/MapTlbMisses", STAMUNIT_OCCURENCES, "TLB misses.");
1851	STAM_REG(pVM, &pPGM->StatR3PageReplaceShared, STAMTYPE_COUNTER, "/PGM/R3/Page/ReplacedShared", STAMUNIT_OCCURENCES, "Times a shared page was replaced.");
1852	STAM_REG(pVM, &pPGM->StatR3PageReplaceZero, STAMTYPE_COUNTER, "/PGM/R3/Page/ReplacedZero", STAMUNIT_OCCURENCES, "Times the zero page was replaced.");
1853	/// @todo STAM_REG(pVM, &pPGM->StatR3PageHandyAllocs, STAMTYPE_COUNTER, "/PGM/R3/Page/HandyAllocs", STAMUNIT_OCCURENCES, "Number of times we've allocated more handy pages.");
1854	STAM_REG(pVM, &pPGM->StatR3FlushTLB, STAMTYPE_PROFILE, "/PGM/R3/FlushTLB", STAMUNIT_OCCURENCES, "Profiling of the PGMFlushTLB() body.");
1855	STAM_REG(pVM, &pPGM->StatR3FlushTLBNewCR3, STAMTYPE_COUNTER, "/PGM/R3/FlushTLB/NewCR3", STAMUNIT_OCCURENCES, "The number of times PGMFlushTLB was called with a new CR3, non-global. (switch)");
1856	STAM_REG(pVM, &pPGM->StatR3FlushTLBNewCR3Global, STAMTYPE_COUNTER, "/PGM/R3/FlushTLB/NewCR3Global", STAMUNIT_OCCURENCES, "The number of times PGMFlushTLB was called with a new CR3, global. (switch)");
1857	STAM_REG(pVM, &pPGM->StatR3FlushTLBSameCR3, STAMTYPE_COUNTER, "/PGM/R3/FlushTLB/SameCR3", STAMUNIT_OCCURENCES, "The number of times PGMFlushTLB was called with the same CR3, non-global. (flush)");
1858	STAM_REG(pVM, &pPGM->StatR3FlushTLBSameCR3Global, STAMTYPE_COUNTER, "/PGM/R3/FlushTLB/SameCR3Global", STAMUNIT_OCCURENCES, "The number of times PGMFlushTLB was called with the same CR3, global. (flush)");
1859	STAM_REG(pVM, &pPGM->StatR3GstModifyPage, STAMTYPE_PROFILE, "/PGM/R3/GstModifyPage", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMGstModifyPage() body.");
1860
1861	}
1862	#endif /* VBOX_WITH_STATISTICS */
1863
1864
1865	/**
1866	* Init the PGM bits that rely on VMMR0 and MM to be fully initialized.
1867	*
1868	* The dynamic mapping area will also be allocated and initialized at this
1869	* time. We could allocate it during PGMR3Init of course, but the mapping
1870	* wouldn't be allocated at that time preventing us from setting up the
1871	* page table entries with the dummy page.
1872	*
1873	* @returns VBox status code.
1874	* @param pVM VM handle.
1875	*/
1876	VMMR3DECL(int) PGMR3InitDynMap(PVM pVM)
1877	{
1878	RTGCPTR GCPtr;
1879	int rc;
1880
1881	#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
1882	/*
1883	* Reserve space for mapping the paging pages into guest context.
1884	*/
1885	rc = MMR3HyperReserve(pVM, PAGE_SIZE * (2 + RT_ELEMENTS(pVM->pgm.s.apShwPaePDsR3) + 1 + 2 + 2), "Paging", &GCPtr);
1886	AssertRCReturn(rc, rc);
1887	pVM->pgm.s.pShw32BitPdRC = GCPtr;
1888	MMR3HyperReserve(pVM, PAGE_SIZE, "fence", NULL);
1889	#endif
1890
1891	/*
1892	* Reserve space for the dynamic mappings.
1893	*/
1894	rc = MMR3HyperReserve(pVM, MM_HYPER_DYNAMIC_SIZE, "Dynamic mapping", &GCPtr);
1895	if (RT_SUCCESS(rc))
1896	pVM->pgm.s.pbDynPageMapBaseGC = GCPtr;
1897
1898	if ( RT_SUCCESS(rc)
1899	&& (pVM->pgm.s.pbDynPageMapBaseGC >> X86_PD_PAE_SHIFT) != ((pVM->pgm.s.pbDynPageMapBaseGC + MM_HYPER_DYNAMIC_SIZE - 1) >> X86_PD_PAE_SHIFT))
1900	{
1901	rc = MMR3HyperReserve(pVM, MM_HYPER_DYNAMIC_SIZE, "Dynamic mapping not crossing", &GCPtr);
1902	if (RT_SUCCESS(rc))
1903	pVM->pgm.s.pbDynPageMapBaseGC = GCPtr;
1904	}
1905	if (RT_SUCCESS(rc))
1906	{
1907	AssertRelease((pVM->pgm.s.pbDynPageMapBaseGC >> X86_PD_PAE_SHIFT) == ((pVM->pgm.s.pbDynPageMapBaseGC + MM_HYPER_DYNAMIC_SIZE - 1) >> X86_PD_PAE_SHIFT));
1908	MMR3HyperReserve(pVM, PAGE_SIZE, "fence", NULL);
1909	}
1910	return rc;
1911	}
1912
1913
1914	/**
1915	* Ring-3 init finalizing.
1916	*
1917	* @returns VBox status code.
1918	* @param pVM The VM handle.
1919	*/
1920	VMMR3DECL(int) PGMR3InitFinalize(PVM pVM)
1921	{
1922	int rc;
1923
1924	#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
1925	/*
1926	* Map the paging pages into the guest context.
1927	*/
1928	RTGCPTR GCPtr = pVM->pgm.s.pShw32BitPdRC;
1929	AssertReleaseReturn(GCPtr, VERR_INTERNAL_ERROR);
1930
1931	rc = PGMMap(pVM, GCPtr, pVM->pgm.s.HCPhysShw32BitPD, PAGE_SIZE, 0);
1932	AssertRCReturn(rc, rc);
1933	pVM->pgm.s.pShw32BitPdRC = GCPtr;
1934	GCPtr += PAGE_SIZE;
1935	GCPtr += PAGE_SIZE; /* reserved page */
1936
1937	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.apShwPaePDsR3); i++)
1938	{
1939	rc = PGMMap(pVM, GCPtr, pVM->pgm.s.aHCPhysPaePDs[i], PAGE_SIZE, 0);
1940	AssertRCReturn(rc, rc);
1941	pVM->pgm.s.apShwPaePDsRC[i] = GCPtr;
1942	GCPtr += PAGE_SIZE;
1943	}
1944	/* A bit of paranoia is justified. */
1945	AssertRelease(pVM->pgm.s.apShwPaePDsRC[0] + PAGE_SIZE == pVM->pgm.s.apShwPaePDsRC[1]);
1946	AssertRelease(pVM->pgm.s.apShwPaePDsRC[1] + PAGE_SIZE == pVM->pgm.s.apShwPaePDsRC[2]);
1947	AssertRelease(pVM->pgm.s.apShwPaePDsRC[2] + PAGE_SIZE == pVM->pgm.s.apShwPaePDsRC[3]);
1948	GCPtr += PAGE_SIZE; /* reserved page */
1949
1950	rc = PGMMap(pVM, GCPtr, pVM->pgm.s.HCPhysShwPaePdpt, PAGE_SIZE, 0);
1951	AssertRCReturn(rc, rc);
1952	pVM->pgm.s.pShwPaePdptRC = GCPtr;
1953	GCPtr += PAGE_SIZE;
1954	GCPtr += PAGE_SIZE; /* reserved page */
1955	#endif
1956
1957	/*
1958	* Reserve space for the dynamic mappings.
1959	* Initialize the dynamic mapping pages with dummy pages to simply the cache.
1960	*/
1961	/* get the pointer to the page table entries. */
1962	PPGMMAPPING pMapping = pgmGetMapping(pVM, pVM->pgm.s.pbDynPageMapBaseGC);
1963	AssertRelease(pMapping);
1964	const uintptr_t off = pVM->pgm.s.pbDynPageMapBaseGC - pMapping->GCPtr;
1965	const unsigned iPT = off >> X86_PD_SHIFT;
1966	const unsigned iPG = (off >> X86_PT_SHIFT) & X86_PT_MASK;
1967	pVM->pgm.s.paDynPageMap32BitPTEsGC = pMapping->aPTs[iPT].pPTRC + iPG * sizeof(pMapping->aPTs[0].pPTR3->a[0]);
1968	pVM->pgm.s.paDynPageMapPaePTEsGC = pMapping->aPTs[iPT].paPaePTsRC + iPG * sizeof(pMapping->aPTs[0].paPaePTsR3->a[0]);
1969
1970	/* init cache */
1971	RTHCPHYS HCPhysDummy = MMR3PageDummyHCPhys(pVM);
1972	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.aHCPhysDynPageMapCache); i++)
1973	pVM->pgm.s.aHCPhysDynPageMapCache[i] = HCPhysDummy;
1974
1975	for (unsigned i = 0; i < MM_HYPER_DYNAMIC_SIZE; i += PAGE_SIZE)
1976	{
1977	rc = PGMMap(pVM, pVM->pgm.s.pbDynPageMapBaseGC + i, HCPhysDummy, PAGE_SIZE, 0);
1978	AssertRCReturn(rc, rc);
1979	}
1980
1981	/*
1982	* Note that AMD uses all the 8 reserved bits for the address (so 40 bits in total);
1983	* Intel only goes up to 36 bits, so we stick to 36 as well.
1984	*/
1985	/** @todo How to test for the 40 bits support? Long mode seems to be the test criterium. */
1986	uint32_t u32Dummy, u32Features;
1987	CPUMGetGuestCpuId(pVM, 1, &u32Dummy, &u32Dummy, &u32Dummy, &u32Features);
1988
1989	if (u32Features & X86_CPUID_FEATURE_EDX_PSE36)
1990	pVM->pgm.s.GCPhys4MBPSEMask = RT_BIT_64(36) - 1;
1991	else
1992	pVM->pgm.s.GCPhys4MBPSEMask = RT_BIT_64(32) - 1;
1993
1994	LogRel(("PGMR3InitFinalize: 4 MB PSE mask %RGp\n", pVM->pgm.s.GCPhys4MBPSEMask));
1995	return rc;
1996	}
1997
1998
1999	/**
2000	* Applies relocations to data and code managed by this component.
2001	*
2002	* This function will be called at init and whenever the VMM need to relocate it
2003	* self inside the GC.
2004	*
2005	* @param pVM The VM.
2006	* @param offDelta Relocation delta relative to old location.
2007	*/
2008	VMMR3DECL(void) PGMR3Relocate(PVM pVM, RTGCINTPTR offDelta)
2009	{
2010	LogFlow(("PGMR3Relocate\n"));
2011
2012	/*
2013	* Paging stuff.
2014	*/
2015	pVM->pgm.s.GCPtrCR3Mapping += offDelta;
2016	/** @todo move this into shadow and guest specific relocation functions. */
2017	#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
2018	AssertMsg(pVM->pgm.s.pShw32BitPdR3, ("Init order, no relocation before paging is initialized!\n"));
2019	pVM->pgm.s.pShw32BitPdRC += offDelta;
2020	#endif
2021	pVM->pgm.s.pGst32BitPdRC += offDelta;
2022	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.apGstPaePDsRC); i++)
2023	{
2024	#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
2025	AssertCompile(RT_ELEMENTS(pVM->pgm.s.apShwPaePDsRC) == RT_ELEMENTS(pVM->pgm.s.apGstPaePDsRC));
2026	pVM->pgm.s.apShwPaePDsRC[i] += offDelta;
2027	#endif
2028	pVM->pgm.s.apGstPaePDsRC[i] += offDelta;
2029	}
2030	pVM->pgm.s.pGstPaePdptRC += offDelta;
2031	#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
2032	pVM->pgm.s.pShwPaePdptRC += offDelta;
2033	#endif
2034
2035	#ifdef VBOX_WITH_PGMPOOL_PAGING_ONLY
2036	pVM->pgm.s.pShwPageCR3RC += offDelta;
2037	#endif
2038
2039	pgmR3ModeDataInit(pVM, true /* resolve GC/R0 symbols */);
2040	pgmR3ModeDataSwitch(pVM, pVM->pgm.s.enmShadowMode, pVM->pgm.s.enmGuestMode);
2041
2042	PGM_SHW_PFN(Relocate, pVM)(pVM, offDelta);
2043	PGM_GST_PFN(Relocate, pVM)(pVM, offDelta);
2044	PGM_BTH_PFN(Relocate, pVM)(pVM, offDelta);
2045
2046	/*
2047	* Trees.
2048	*/
2049	pVM->pgm.s.pTreesRC = MMHyperR3ToRC(pVM, pVM->pgm.s.pTreesR3);
2050
2051	/*
2052	* Ram ranges.
2053	*/
2054	if (pVM->pgm.s.pRamRangesR3)
2055	{
2056	pVM->pgm.s.pRamRangesRC = MMHyperR3ToRC(pVM, pVM->pgm.s.pRamRangesR3);
2057	for (PPGMRAMRANGE pCur = pVM->pgm.s.pRamRangesR3; pCur->pNextR3; pCur = pCur->pNextR3)
2058	pCur->pNextRC = MMHyperR3ToRC(pVM, pCur->pNextR3);
2059	}
2060
2061	/*
2062	* Update the two page directories with all page table mappings.
2063	* (One or more of them have changed, that's why we're here.)
2064	*/
2065	pVM->pgm.s.pMappingsRC = MMHyperR3ToRC(pVM, pVM->pgm.s.pMappingsR3);
2066	for (PPGMMAPPING pCur = pVM->pgm.s.pMappingsR3; pCur->pNextR3; pCur = pCur->pNextR3)
2067	pCur->pNextRC = MMHyperR3ToRC(pVM, pCur->pNextR3);
2068
2069	/* Relocate GC addresses of Page Tables. */
2070	for (PPGMMAPPING pCur = pVM->pgm.s.pMappingsR3; pCur; pCur = pCur->pNextR3)
2071	{
2072	for (RTHCUINT i = 0; i < pCur->cPTs; i++)
2073	{
2074	pCur->aPTs[i].pPTRC = MMHyperR3ToRC(pVM, pCur->aPTs[i].pPTR3);
2075	pCur->aPTs[i].paPaePTsRC = MMHyperR3ToRC(pVM, pCur->aPTs[i].paPaePTsR3);
2076	}
2077	}
2078
2079	/*
2080	* Dynamic page mapping area.
2081	*/
2082	pVM->pgm.s.paDynPageMap32BitPTEsGC += offDelta;
2083	pVM->pgm.s.paDynPageMapPaePTEsGC += offDelta;
2084	pVM->pgm.s.pbDynPageMapBaseGC += offDelta;
2085
2086	/*
2087	* The Zero page.
2088	*/
2089	pVM->pgm.s.pvZeroPgR0 = MMHyperR3ToR0(pVM, pVM->pgm.s.pvZeroPgR3);
2090	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
2091	AssertRelease(pVM->pgm.s.pvZeroPgR0 != NIL_RTR0PTR \|\| !VMMIsHwVirtExtForced(pVM));
2092	#else
2093	AssertRelease(pVM->pgm.s.pvZeroPgR0 != NIL_RTR0PTR);
2094	#endif
2095
2096	/*
2097	* Physical and virtual handlers.
2098	*/
2099	RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysHandlers, true, pgmR3RelocatePhysHandler, &offDelta);
2100	RTAvlroGCPtrDoWithAll(&pVM->pgm.s.pTreesR3->VirtHandlers, true, pgmR3RelocateVirtHandler, &offDelta);
2101	RTAvlroGCPtrDoWithAll(&pVM->pgm.s.pTreesR3->HyperVirtHandlers, true, pgmR3RelocateHyperVirtHandler, &offDelta);
2102
2103	/*
2104	* The page pool.
2105	*/
2106	pgmR3PoolRelocate(pVM);
2107	}
2108
2109
2110	/**
2111	* Callback function for relocating a physical access handler.
2112	*
2113	* @returns 0 (continue enum)
2114	* @param pNode Pointer to a PGMPHYSHANDLER node.
2115	* @param pvUser Pointer to the offDelta. This is a pointer to the delta since we're
2116	* not certain the delta will fit in a void pointer for all possible configs.
2117	*/
2118	static DECLCALLBACK(int) pgmR3RelocatePhysHandler(PAVLROGCPHYSNODECORE pNode, void *pvUser)
2119	{
2120	PPGMPHYSHANDLER pHandler = (PPGMPHYSHANDLER)pNode;
2121	RTGCINTPTR offDelta = *(PRTGCINTPTR)pvUser;
2122	if (pHandler->pfnHandlerRC)
2123	pHandler->pfnHandlerRC += offDelta;
2124	if (pHandler->pvUserRC >= 0x10000)
2125	pHandler->pvUserRC += offDelta;
2126	return 0;
2127	}
2128
2129
2130	/**
2131	* Callback function for relocating a virtual access handler.
2132	*
2133	* @returns 0 (continue enum)
2134	* @param pNode Pointer to a PGMVIRTHANDLER node.
2135	* @param pvUser Pointer to the offDelta. This is a pointer to the delta since we're
2136	* not certain the delta will fit in a void pointer for all possible configs.
2137	*/
2138	static DECLCALLBACK(int) pgmR3RelocateVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser)
2139	{
2140	PPGMVIRTHANDLER pHandler = (PPGMVIRTHANDLER)pNode;
2141	RTGCINTPTR offDelta = *(PRTGCINTPTR)pvUser;
2142	Assert( pHandler->enmType == PGMVIRTHANDLERTYPE_ALL
2143	\|\| pHandler->enmType == PGMVIRTHANDLERTYPE_WRITE);
2144	Assert(pHandler->pfnHandlerRC);
2145	pHandler->pfnHandlerRC += offDelta;
2146	return 0;
2147	}
2148
2149
2150	/**
2151	* Callback function for relocating a virtual access handler for the hypervisor mapping.
2152	*
2153	* @returns 0 (continue enum)
2154	* @param pNode Pointer to a PGMVIRTHANDLER node.
2155	* @param pvUser Pointer to the offDelta. This is a pointer to the delta since we're
2156	* not certain the delta will fit in a void pointer for all possible configs.
2157	*/
2158	static DECLCALLBACK(int) pgmR3RelocateHyperVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser)
2159	{
2160	PPGMVIRTHANDLER pHandler = (PPGMVIRTHANDLER)pNode;
2161	RTGCINTPTR offDelta = *(PRTGCINTPTR)pvUser;
2162	Assert(pHandler->enmType == PGMVIRTHANDLERTYPE_HYPERVISOR);
2163	Assert(pHandler->pfnHandlerRC);
2164	pHandler->pfnHandlerRC += offDelta;
2165	return 0;
2166	}
2167
2168
2169	/**
2170	* The VM is being reset.
2171	*
2172	* For the PGM component this means that any PD write monitors
2173	* needs to be removed.
2174	*
2175	* @param pVM VM handle.
2176	*/
2177	VMMR3DECL(void) PGMR3Reset(PVM pVM)
2178	{
2179	LogFlow(("PGMR3Reset:\n"));
2180	VM_ASSERT_EMT(pVM);
2181
2182	pgmLock(pVM);
2183
2184	/*
2185	* Unfix any fixed mappings and disable CR3 monitoring.
2186	*/
2187	pVM->pgm.s.fMappingsFixed = false;
2188	pVM->pgm.s.GCPtrMappingFixed = 0;
2189	pVM->pgm.s.cbMappingFixed = 0;
2190
2191	/* Exit the guest paging mode before the pgm pool gets reset.
2192	* Important to clean up the amd64 case.
2193	*/
2194	int rc = PGM_GST_PFN(Exit, pVM)(pVM);
2195	AssertRC(rc);
2196	#ifdef DEBUG
2197	DBGFR3InfoLog(pVM, "mappings", NULL);
2198	DBGFR3InfoLog(pVM, "handlers", "all nostat");
2199	#endif
2200
2201	/*
2202	* Reset the shadow page pool.
2203	*/
2204	pgmR3PoolReset(pVM);
2205
2206	/*
2207	* Re-init other members.
2208	*/
2209	pVM->pgm.s.fA20Enabled = true;
2210
2211	/*
2212	* Clear the FFs PGM owns.
2213	*/
2214	VM_FF_CLEAR(pVM, VM_FF_PGM_SYNC_CR3);
2215	VM_FF_CLEAR(pVM, VM_FF_PGM_SYNC_CR3_NON_GLOBAL);
2216
2217	/*
2218	* Reset (zero) RAM pages.
2219	*/
2220	rc = pgmR3PhysRamReset(pVM);
2221	if (RT_SUCCESS(rc))
2222	{
2223	#ifdef VBOX_WITH_NEW_PHYS_CODE
2224	/*
2225	* Reset (zero) shadow ROM pages.
2226	*/
2227	rc = pgmR3PhysRomReset(pVM);
2228	#endif
2229	if (RT_SUCCESS(rc))
2230	{
2231	/*
2232	* Switch mode back to real mode.
2233	*/
2234	rc = PGMR3ChangeMode(pVM, PGMMODE_REAL);
2235	STAM_REL_COUNTER_RESET(&pVM->pgm.s.cGuestModeChanges);
2236	}
2237	}
2238
2239	pgmUnlock(pVM);
2240	//return rc;
2241	AssertReleaseRC(rc);
2242	}
2243
2244
2245	#ifdef VBOX_STRICT
2246	/**
2247	* VM state change callback for clearing fNoMorePhysWrites after
2248	* a snapshot has been created.
2249	*/
2250	static DECLCALLBACK(void) pgmR3ResetNoMorePhysWritesFlag(PVM pVM, VMSTATE enmState, VMSTATE enmOldState, void *pvUser)
2251	{
2252	if (enmState == VMSTATE_RUNNING)
2253	pVM->pgm.s.fNoMorePhysWrites = false;
2254	}
2255	#endif
2256
2257
2258	/**
2259	* Terminates the PGM.
2260	*
2261	* @returns VBox status code.
2262	* @param pVM Pointer to VM structure.
2263	*/
2264	VMMR3DECL(int) PGMR3Term(PVM pVM)
2265	{
2266	PGMDeregisterStringFormatTypes();
2267	return PDMR3CritSectDelete(&pVM->pgm.s.CritSect);
2268	}
2269
2270
2271	/**
2272	* Terminates the per-VCPU PGM.
2273	*
2274	* Termination means cleaning up and freeing all resources,
2275	* the VM it self is at this point powered off or suspended.
2276	*
2277	* @returns VBox status code.
2278	* @param pVM The VM to operate on.
2279	*/
2280	VMMR3DECL(int) PGMR3TermCPU(PVM pVM)
2281	{
2282	return 0;
2283	}
2284
2285
2286	/**
2287	* Execute state save operation.
2288	*
2289	* @returns VBox status code.
2290	* @param pVM VM Handle.
2291	* @param pSSM SSM operation handle.
2292	*/
2293	static DECLCALLBACK(int) pgmR3Save(PVM pVM, PSSMHANDLE pSSM)
2294	{
2295	#ifdef VBOX_WITH_NEW_PHYS_CODE
2296	AssertReleaseFailed(); /** @todo */
2297	#else
2298	PPGM pPGM = &pVM->pgm.s;
2299
2300	/* No more writes to physical memory after this point! */
2301	pVM->pgm.s.fNoMorePhysWrites = true;
2302
2303	/*
2304	* Save basic data (required / unaffected by relocation).
2305	*/
2306	#if 1
2307	SSMR3PutBool(pSSM, pPGM->fMappingsFixed);
2308	#else
2309	SSMR3PutUInt(pSSM, pPGM->fMappingsFixed);
2310	#endif
2311	SSMR3PutGCPtr(pSSM, pPGM->GCPtrMappingFixed);
2312	SSMR3PutU32(pSSM, pPGM->cbMappingFixed);
2313	SSMR3PutUInt(pSSM, pPGM->cbRamSize);
2314	SSMR3PutGCPhys(pSSM, pPGM->GCPhysA20Mask);
2315	SSMR3PutUInt(pSSM, pPGM->fA20Enabled);
2316	SSMR3PutUInt(pSSM, pPGM->fSyncFlags);
2317	SSMR3PutUInt(pSSM, pPGM->enmGuestMode);
2318	SSMR3PutU32(pSSM, ~0); /* Separator. */
2319
2320	/*
2321	* The guest mappings.
2322	*/
2323	uint32_t i = 0;
2324	for (PPGMMAPPING pMapping = pPGM->pMappingsR3; pMapping; pMapping = pMapping->pNextR3, i++)
2325	{
2326	SSMR3PutU32(pSSM, i);
2327	SSMR3PutStrZ(pSSM, pMapping->pszDesc); /* This is the best unique id we have... */
2328	SSMR3PutGCPtr(pSSM, pMapping->GCPtr);
2329	SSMR3PutGCUIntPtr(pSSM, pMapping->cPTs);
2330	/* flags are done by the mapping owners! */
2331	}
2332	SSMR3PutU32(pSSM, ~0); /* terminator. */
2333
2334	/*
2335	* Ram range flags and bits.
2336	*/
2337	i = 0;
2338	for (PPGMRAMRANGE pRam = pPGM->pRamRangesR3; pRam; pRam = pRam->pNextR3, i++)
2339	{
2340	/** @todo MMIO ranges may move (PCI reconfig), we currently assume they don't. */
2341
2342	SSMR3PutU32(pSSM, i);
2343	SSMR3PutGCPhys(pSSM, pRam->GCPhys);
2344	SSMR3PutGCPhys(pSSM, pRam->GCPhysLast);
2345	SSMR3PutGCPhys(pSSM, pRam->cb);
2346	SSMR3PutU8(pSSM, !!pRam->pvR3); /* boolean indicating memory or not. */
2347
2348	/* Flags. */
2349	const unsigned cPages = pRam->cb >> PAGE_SHIFT;
2350	for (unsigned iPage = 0; iPage < cPages; iPage++)
2351	SSMR3PutU16(pSSM, (uint16_t)(pRam->aPages[iPage].HCPhys & ~X86_PTE_PAE_PG_MASK)); /** @todo PAGE FLAGS */
2352
2353	/* any memory associated with the range. */
2354	if (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)
2355	{
2356	for (unsigned iChunk = 0; iChunk < (pRam->cb >> PGM_DYNAMIC_CHUNK_SHIFT); iChunk++)
2357	{
2358	if (pRam->paChunkR3Ptrs[iChunk])
2359	{
2360	SSMR3PutU8(pSSM, 1); /* chunk present */
2361	SSMR3PutMem(pSSM, (void *)pRam->paChunkR3Ptrs[iChunk], PGM_DYNAMIC_CHUNK_SIZE);
2362	}
2363	else
2364	SSMR3PutU8(pSSM, 0); /* no chunk present */
2365	}
2366	}
2367	else if (pRam->pvR3)
2368	{
2369	int rc = SSMR3PutMem(pSSM, pRam->pvR3, pRam->cb);
2370	if (RT_FAILURE(rc))
2371	{
2372	Log(("pgmR3Save: SSMR3PutMem(, %p, %#x) -> %Rrc\n", pRam->pvR3, pRam->cb, rc));
2373	return rc;
2374	}
2375	}
2376	}
2377	#endif /* !VBOX_WITH_NEW_PHYS_CODE */
2378	return SSMR3PutU32(pSSM, ~0); /* terminator. */
2379	}
2380
2381
2382	/**
2383	* Execute state load operation.
2384	*
2385	* @returns VBox status code.
2386	* @param pVM VM Handle.
2387	* @param pSSM SSM operation handle.
2388	* @param u32Version Data layout version.
2389	*/
2390	static DECLCALLBACK(int) pgmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version)
2391	{
2392	#ifdef VBOX_WITH_NEW_PHYS_CODE
2393	AssertReleaseFailed(); /** @todo */
2394	#else
2395	/*
2396	* Validate version.
2397	*/
2398	if (u32Version != PGM_SAVED_STATE_VERSION)
2399	{
2400	AssertMsgFailed(("pgmR3Load: Invalid version u32Version=%d (current %d)!\n", u32Version, PGM_SAVED_STATE_VERSION));
2401	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
2402	}
2403
2404	/*
2405	* Call the reset function to make sure all the memory is cleared.
2406	*/
2407	PGMR3Reset(pVM);
2408
2409	/*
2410	* Load basic data (required / unaffected by relocation).
2411	*/
2412	PPGM pPGM = &pVM->pgm.s;
2413	#if 1
2414	SSMR3GetBool(pSSM, &pPGM->fMappingsFixed);
2415	#else
2416	uint32_t u;
2417	SSMR3GetU32(pSSM, &u);
2418	pPGM->fMappingsFixed = u;
2419	#endif
2420	SSMR3GetGCPtr(pSSM, &pPGM->GCPtrMappingFixed);
2421	SSMR3GetU32(pSSM, &pPGM->cbMappingFixed);
2422
2423	RTUINT cbRamSize;
2424	int rc = SSMR3GetU32(pSSM, &cbRamSize);
2425	if (RT_FAILURE(rc))
2426	return rc;
2427	if (cbRamSize != pPGM->cbRamSize)
2428	return VERR_SSM_LOAD_MEMORY_SIZE_MISMATCH;
2429	SSMR3GetGCPhys(pSSM, &pPGM->GCPhysA20Mask);
2430	SSMR3GetUInt(pSSM, &pPGM->fA20Enabled);
2431	SSMR3GetUInt(pSSM, &pPGM->fSyncFlags);
2432	RTUINT uGuestMode;
2433	SSMR3GetUInt(pSSM, &uGuestMode);
2434	pPGM->enmGuestMode = (PGMMODE)uGuestMode;
2435
2436	/* check separator. */
2437	uint32_t u32Sep;
2438	SSMR3GetU32(pSSM, &u32Sep);
2439	if (RT_FAILURE(rc))
2440	return rc;
2441	if (u32Sep != (uint32_t)~0)
2442	{
2443	AssertMsgFailed(("u32Sep=%#x (first)\n", u32Sep));
2444	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2445	}
2446
2447	/*
2448	* The guest mappings.
2449	*/
2450	uint32_t i = 0;
2451	for (;; i++)
2452	{
2453	/* Check the seqence number / separator. */
2454	rc = SSMR3GetU32(pSSM, &u32Sep);
2455	if (RT_FAILURE(rc))
2456	return rc;
2457	if (u32Sep == ~0U)
2458	break;
2459	if (u32Sep != i)
2460	{
2461	AssertMsgFailed(("u32Sep=%#x (last)\n", u32Sep));
2462	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2463	}
2464
2465	/* get the mapping details. */
2466	char szDesc[256];
2467	szDesc[0] = '\0';
2468	rc = SSMR3GetStrZ(pSSM, szDesc, sizeof(szDesc));
2469	if (RT_FAILURE(rc))
2470	return rc;
2471	RTGCPTR GCPtr;
2472	SSMR3GetGCPtr(pSSM, &GCPtr);
2473	RTGCPTR cPTs;
2474	rc = SSMR3GetGCUIntPtr(pSSM, &cPTs);
2475	if (RT_FAILURE(rc))
2476	return rc;
2477
2478	/* find matching range. */
2479	PPGMMAPPING pMapping;
2480	for (pMapping = pPGM->pMappingsR3; pMapping; pMapping = pMapping->pNextR3)
2481	if ( pMapping->cPTs == cPTs
2482	&& !strcmp(pMapping->pszDesc, szDesc))
2483	break;
2484	if (!pMapping)
2485	{
2486	LogRel(("Couldn't find mapping: cPTs=%#x szDesc=%s (GCPtr=%RGv)\n",
2487	cPTs, szDesc, GCPtr));
2488	AssertFailed();
2489	return VERR_SSM_LOAD_CONFIG_MISMATCH;
2490	}
2491
2492	/* relocate it. */
2493	if (pMapping->GCPtr != GCPtr)
2494	{
2495	AssertMsg((GCPtr >> X86_PD_SHIFT << X86_PD_SHIFT) == GCPtr, ("GCPtr=%RGv\n", GCPtr));
2496	pgmR3MapRelocate(pVM, pMapping, pMapping->GCPtr, GCPtr);
2497	}
2498	else
2499	Log(("pgmR3Load: '%s' needed no relocation (%RGv)\n", szDesc, GCPtr));
2500	}
2501
2502	/*
2503	* Ram range flags and bits.
2504	*/
2505	i = 0;
2506	for (PPGMRAMRANGE pRam = pPGM->pRamRangesR3; pRam; pRam = pRam->pNextR3, i++)
2507	{
2508	/** @todo MMIO ranges may move (PCI reconfig), we currently assume they don't. */
2509	/* Check the seqence number / separator. */
2510	rc = SSMR3GetU32(pSSM, &u32Sep);
2511	if (RT_FAILURE(rc))
2512	return rc;
2513	if (u32Sep == ~0U)
2514	break;
2515	if (u32Sep != i)
2516	{
2517	AssertMsgFailed(("u32Sep=%#x (last)\n", u32Sep));
2518	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2519	}
2520
2521	/* Get the range details. */
2522	RTGCPHYS GCPhys;
2523	SSMR3GetGCPhys(pSSM, &GCPhys);
2524	RTGCPHYS GCPhysLast;
2525	SSMR3GetGCPhys(pSSM, &GCPhysLast);
2526	RTGCPHYS cb;
2527	SSMR3GetGCPhys(pSSM, &cb);
2528	uint8_t fHaveBits;
2529	rc = SSMR3GetU8(pSSM, &fHaveBits);
2530	if (RT_FAILURE(rc))
2531	return rc;
2532	if (fHaveBits & ~1)
2533	{
2534	AssertMsgFailed(("u32Sep=%#x (last)\n", u32Sep));
2535	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2536	}
2537
2538	/* Match it up with the current range. */
2539	if ( GCPhys != pRam->GCPhys
2540	\|\| GCPhysLast != pRam->GCPhysLast
2541	\|\| cb != pRam->cb
2542	\|\| fHaveBits != !!pRam->pvR3)
2543	{
2544	LogRel(("Ram range: %RGp-%RGp %RGp bytes %s\n"
2545	"State : %RGp-%RGp %RGp bytes %s\n",
2546	pRam->GCPhys, pRam->GCPhysLast, pRam->cb, pRam->pvR3 ? "bits" : "nobits",
2547	GCPhys, GCPhysLast, cb, fHaveBits ? "bits" : "nobits"));
2548	/*
2549	* If we're loading a state for debugging purpose, don't make a fuss if
2550	* the MMIO[2] and ROM stuff isn't 100% right, just skip the mismatches.
2551	*/
2552	if ( SSMR3HandleGetAfter(pSSM) != SSMAFTER_DEBUG_IT
2553	\|\| GCPhys < 8 * _1M)
2554	AssertFailedReturn(VERR_SSM_LOAD_CONFIG_MISMATCH);
2555
2556	RTGCPHYS cPages = ((GCPhysLast - GCPhys) + 1) >> PAGE_SHIFT;
2557	while (cPages-- > 0)
2558	{
2559	uint16_t u16Ignore;
2560	SSMR3GetU16(pSSM, &u16Ignore);
2561	}
2562	continue;
2563	}
2564
2565	/* Flags. */
2566	const unsigned cPages = pRam->cb >> PAGE_SHIFT;
2567	for (unsigned iPage = 0; iPage < cPages; iPage++)
2568	{
2569	uint16_t u16 = 0;
2570	SSMR3GetU16(pSSM, &u16);
2571	u16 &= PAGE_OFFSET_MASK & ~( RT_BIT(4) \| RT_BIT(5) \| RT_BIT(6)
2572	\| RT_BIT(7) \| RT_BIT(8) \| RT_BIT(9) \| RT_BIT(10) );
2573	// &= MM_RAM_FLAGS_DYNAMIC_ALLOC \| MM_RAM_FLAGS_RESERVED \| MM_RAM_FLAGS_ROM \| MM_RAM_FLAGS_MMIO \| MM_RAM_FLAGS_MMIO2
2574	pRam->aPages[iPage].HCPhys = PGM_PAGE_GET_HCPHYS(&pRam->aPages[iPage]) \| (RTHCPHYS)u16; /** @todo PAGE FLAGS */
2575	}
2576
2577	/* any memory associated with the range. */
2578	if (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)
2579	{
2580	for (unsigned iChunk = 0; iChunk < (pRam->cb >> PGM_DYNAMIC_CHUNK_SHIFT); iChunk++)
2581	{
2582	uint8_t fValidChunk;
2583
2584	rc = SSMR3GetU8(pSSM, &fValidChunk);
2585	if (RT_FAILURE(rc))
2586	return rc;
2587	if (fValidChunk > 1)
2588	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2589
2590	if (fValidChunk)
2591	{
2592	if (!pRam->paChunkR3Ptrs[iChunk])
2593	{
2594	rc = pgmr3PhysGrowRange(pVM, pRam->GCPhys + iChunk * PGM_DYNAMIC_CHUNK_SIZE);
2595	if (RT_FAILURE(rc))
2596	return rc;
2597	}
2598	Assert(pRam->paChunkR3Ptrs[iChunk]);
2599
2600	SSMR3GetMem(pSSM, (void *)pRam->paChunkR3Ptrs[iChunk], PGM_DYNAMIC_CHUNK_SIZE);
2601	}
2602	/* else nothing to do */
2603	}
2604	}
2605	else if (pRam->pvR3)
2606	{
2607	int rc = SSMR3GetMem(pSSM, pRam->pvR3, pRam->cb);
2608	if (RT_FAILURE(rc))
2609	{
2610	Log(("pgmR3Save: SSMR3GetMem(, %p, %#x) -> %Rrc\n", pRam->pvR3, pRam->cb, rc));
2611	return rc;
2612	}
2613	}
2614	}
2615
2616	/*
2617	* We require a full resync now.
2618	*/
2619	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3_NON_GLOBAL);
2620	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
2621	pPGM->fSyncFlags \|= PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL;
2622	pPGM->fPhysCacheFlushPending = true;
2623	pgmR3HandlerPhysicalUpdateAll(pVM);
2624
2625	/*
2626	* Change the paging mode.
2627	*/
2628	rc = PGMR3ChangeMode(pVM, pPGM->enmGuestMode);
2629
2630	/* Restore pVM->pgm.s.GCPhysCR3. */
2631	Assert(pVM->pgm.s.GCPhysCR3 == NIL_RTGCPHYS);
2632	RTGCPHYS GCPhysCR3 = CPUMGetGuestCR3(pVM);
2633	if ( pVM->pgm.s.enmGuestMode == PGMMODE_PAE
2634	\|\| pVM->pgm.s.enmGuestMode == PGMMODE_PAE_NX
2635	\|\| pVM->pgm.s.enmGuestMode == PGMMODE_AMD64
2636	\|\| pVM->pgm.s.enmGuestMode == PGMMODE_AMD64_NX)
2637	GCPhysCR3 = (GCPhysCR3 & X86_CR3_PAE_PAGE_MASK);
2638	else
2639	GCPhysCR3 = (GCPhysCR3 & X86_CR3_PAGE_MASK);
2640	pVM->pgm.s.GCPhysCR3 = GCPhysCR3;
2641
2642	return rc;
2643	#endif /* !VBOX_WITH_NEW_PHYS_CODE */
2644	}
2645
2646
2647	/**
2648	* Show paging mode.
2649	*
2650	* @param pVM VM Handle.
2651	* @param pHlp The info helpers.
2652	* @param pszArgs "all" (default), "guest", "shadow" or "host".
2653	*/
2654	static DECLCALLBACK(void) pgmR3InfoMode(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2655	{
2656	/* digest argument. */
2657	bool fGuest, fShadow, fHost;
2658	if (pszArgs)
2659	pszArgs = RTStrStripL(pszArgs);
2660	if (!pszArgs \|\| !*pszArgs \|\| strstr(pszArgs, "all"))
2661	fShadow = fHost = fGuest = true;
2662	else
2663	{
2664	fShadow = fHost = fGuest = false;
2665	if (strstr(pszArgs, "guest"))
2666	fGuest = true;
2667	if (strstr(pszArgs, "shadow"))
2668	fShadow = true;
2669	if (strstr(pszArgs, "host"))
2670	fHost = true;
2671	}
2672
2673	/* print info. */
2674	if (fGuest)
2675	pHlp->pfnPrintf(pHlp, "Guest paging mode: %s, changed %RU64 times, A20 %s\n",
2676	PGMGetModeName(pVM->pgm.s.enmGuestMode), pVM->pgm.s.cGuestModeChanges.c,
2677	pVM->pgm.s.fA20Enabled ? "enabled" : "disabled");
2678	if (fShadow)
2679	pHlp->pfnPrintf(pHlp, "Shadow paging mode: %s\n", PGMGetModeName(pVM->pgm.s.enmShadowMode));
2680	if (fHost)
2681	{
2682	const char *psz;
2683	switch (pVM->pgm.s.enmHostMode)
2684	{
2685	case SUPPAGINGMODE_INVALID: psz = "invalid"; break;
2686	case SUPPAGINGMODE_32_BIT: psz = "32-bit"; break;
2687	case SUPPAGINGMODE_32_BIT_GLOBAL: psz = "32-bit+G"; break;
2688	case SUPPAGINGMODE_PAE: psz = "PAE"; break;
2689	case SUPPAGINGMODE_PAE_GLOBAL: psz = "PAE+G"; break;
2690	case SUPPAGINGMODE_PAE_NX: psz = "PAE+NX"; break;
2691	case SUPPAGINGMODE_PAE_GLOBAL_NX: psz = "PAE+G+NX"; break;
2692	case SUPPAGINGMODE_AMD64: psz = "AMD64"; break;
2693	case SUPPAGINGMODE_AMD64_GLOBAL: psz = "AMD64+G"; break;
2694	case SUPPAGINGMODE_AMD64_NX: psz = "AMD64+NX"; break;
2695	case SUPPAGINGMODE_AMD64_GLOBAL_NX: psz = "AMD64+G+NX"; break;
2696	default: psz = "unknown"; break;
2697	}
2698	pHlp->pfnPrintf(pHlp, "Host paging mode: %s\n", psz);
2699	}
2700	}
2701
2702
2703	/**
2704	* Dump registered MMIO ranges to the log.
2705	*
2706	* @param pVM VM Handle.
2707	* @param pHlp The info helpers.
2708	* @param pszArgs Arguments, ignored.
2709	*/
2710	static DECLCALLBACK(void) pgmR3PhysInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2711	{
2712	NOREF(pszArgs);
2713	pHlp->pfnPrintf(pHlp,
2714	"RAM ranges (pVM=%p)\n"
2715	"%.s %.s\n",
2716	pVM,
2717	sizeof(RTGCPHYS) * 4 + 1, "GC Phys Range ",
2718	sizeof(RTHCPTR) * 2, "pvHC ");
2719
2720	for (PPGMRAMRANGE pCur = pVM->pgm.s.pRamRangesR3; pCur; pCur = pCur->pNextR3)
2721	pHlp->pfnPrintf(pHlp,
2722	"%RGp-%RGp %RHv %s\n",
2723	pCur->GCPhys,
2724	pCur->GCPhysLast,
2725	pCur->pvR3,
2726	pCur->pszDesc);
2727	}
2728
2729	/**
2730	* Dump the page directory to the log.
2731	*
2732	* @param pVM VM Handle.
2733	* @param pHlp The info helpers.
2734	* @param pszArgs Arguments, ignored.
2735	*/
2736	static DECLCALLBACK(void) pgmR3InfoCr3(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2737	{
2738	/** @todo fix this! Convert the PGMR3DumpHierarchyHC functions to do guest stuff. */
2739	/* Big pages supported? */
2740	const bool fPSE = !!(CPUMGetGuestCR4(pVM) & X86_CR4_PSE);
2741
2742	/* Global pages supported? */
2743	const bool fPGE = !!(CPUMGetGuestCR4(pVM) & X86_CR4_PGE);
2744
2745	NOREF(pszArgs);
2746
2747	/*
2748	* Get page directory addresses.
2749	*/
2750	PX86PD pPDSrc = pVM->pgm.s.pGst32BitPdR3;
2751	Assert(pPDSrc);
2752	Assert(PGMPhysGCPhys2R3PtrAssert(pVM, (RTGCPHYS)(CPUMGetGuestCR3(pVM) & X86_CR3_PAGE_MASK), sizeof(*pPDSrc)) == pPDSrc);
2753
2754	/*
2755	* Iterate the page directory.
2756	*/
2757	for (unsigned iPD = 0; iPD < RT_ELEMENTS(pPDSrc->a); iPD++)
2758	{
2759	X86PDE PdeSrc = pPDSrc->a[iPD];
2760	if (PdeSrc.n.u1Present)
2761	{
2762	if (PdeSrc.b.u1Size && fPSE)
2763	pHlp->pfnPrintf(pHlp,
2764	"%04X - %RGp P=%d U=%d RW=%d G=%d - BIG\n",
2765	iPD,
2766	pgmGstGet4MBPhysPage(&pVM->pgm.s, PdeSrc),
2767	PdeSrc.b.u1Present, PdeSrc.b.u1User, PdeSrc.b.u1Write, PdeSrc.b.u1Global && fPGE);
2768	else
2769	pHlp->pfnPrintf(pHlp,
2770	"%04X - %RGp P=%d U=%d RW=%d [G=%d]\n",
2771	iPD,
2772	(RTGCPHYS)(PdeSrc.u & X86_PDE_PG_MASK),
2773	PdeSrc.n.u1Present, PdeSrc.n.u1User, PdeSrc.n.u1Write, PdeSrc.b.u1Global && fPGE);
2774	}
2775	}
2776	}
2777
2778
2779	/**
2780	* Serivce a VMMCALLHOST_PGM_LOCK call.
2781	*
2782	* @returns VBox status code.
2783	* @param pVM The VM handle.
2784	*/
2785	VMMR3DECL(int) PGMR3LockCall(PVM pVM)
2786	{
2787	int rc = PDMR3CritSectEnterEx(&pVM->pgm.s.CritSect, true /* fHostCall */);
2788	AssertRC(rc);
2789	return rc;
2790	}
2791
2792
2793	/**
2794	* Converts a PGMMODE value to a PGM_TYPE_* \#define.
2795	*
2796	* @returns PGM_TYPE_*.
2797	* @param pgmMode The mode value to convert.
2798	*/
2799	DECLINLINE(unsigned) pgmModeToType(PGMMODE pgmMode)
2800	{
2801	switch (pgmMode)
2802	{
2803	case PGMMODE_REAL: return PGM_TYPE_REAL;
2804	case PGMMODE_PROTECTED: return PGM_TYPE_PROT;
2805	case PGMMODE_32_BIT: return PGM_TYPE_32BIT;
2806	case PGMMODE_PAE:
2807	case PGMMODE_PAE_NX: return PGM_TYPE_PAE;
2808	case PGMMODE_AMD64:
2809	case PGMMODE_AMD64_NX: return PGM_TYPE_AMD64;
2810	case PGMMODE_NESTED: return PGM_TYPE_NESTED;
2811	case PGMMODE_EPT: return PGM_TYPE_EPT;
2812	default:
2813	AssertFatalMsgFailed(("pgmMode=%d\n", pgmMode));
2814	}
2815	}
2816
2817
2818	/**
2819	* Gets the index into the paging mode data array of a SHW+GST mode.
2820	*
2821	* @returns PGM::paPagingData index.
2822	* @param uShwType The shadow paging mode type.
2823	* @param uGstType The guest paging mode type.
2824	*/
2825	DECLINLINE(unsigned) pgmModeDataIndex(unsigned uShwType, unsigned uGstType)
2826	{
2827	Assert(uShwType >= PGM_TYPE_32BIT && uShwType <= PGM_TYPE_MAX);
2828	Assert(uGstType >= PGM_TYPE_REAL && uGstType <= PGM_TYPE_AMD64);
2829	return (uShwType - PGM_TYPE_32BIT) * (PGM_TYPE_AMD64 - PGM_TYPE_REAL + 1)
2830	+ (uGstType - PGM_TYPE_REAL);
2831	}
2832
2833
2834	/**
2835	* Gets the index into the paging mode data array of a SHW+GST mode.
2836	*
2837	* @returns PGM::paPagingData index.
2838	* @param enmShw The shadow paging mode.
2839	* @param enmGst The guest paging mode.
2840	*/
2841	DECLINLINE(unsigned) pgmModeDataIndexByMode(PGMMODE enmShw, PGMMODE enmGst)
2842	{
2843	Assert(enmShw >= PGMMODE_32_BIT && enmShw <= PGMMODE_MAX);
2844	Assert(enmGst > PGMMODE_INVALID && enmGst < PGMMODE_MAX);
2845	return pgmModeDataIndex(pgmModeToType(enmShw), pgmModeToType(enmGst));
2846	}
2847
2848
2849	/**
2850	* Calculates the max data index.
2851	* @returns The number of entries in the paging data array.
2852	*/
2853	DECLINLINE(unsigned) pgmModeDataMaxIndex(void)
2854	{
2855	return pgmModeDataIndex(PGM_TYPE_MAX, PGM_TYPE_AMD64) + 1;
2856	}
2857
2858
2859	/**
2860	* Initializes the paging mode data kept in PGM::paModeData.
2861	*
2862	* @param pVM The VM handle.
2863	* @param fResolveGCAndR0 Indicate whether or not GC and Ring-0 symbols can be resolved now.
2864	* This is used early in the init process to avoid trouble with PDM
2865	* not being initialized yet.
2866	*/
2867	static int pgmR3ModeDataInit(PVM pVM, bool fResolveGCAndR0)
2868	{
2869	PPGMMODEDATA pModeData;
2870	int rc;
2871
2872	/*
2873	* Allocate the array on the first call.
2874	*/
2875	if (!pVM->pgm.s.paModeData)
2876	{
2877	pVM->pgm.s.paModeData = (PPGMMODEDATA)MMR3HeapAllocZ(pVM, MM_TAG_PGM, sizeof(PGMMODEDATA) * pgmModeDataMaxIndex());
2878	AssertReturn(pVM->pgm.s.paModeData, VERR_NO_MEMORY);
2879	}
2880
2881	/*
2882	* Initialize the array entries.
2883	*/
2884	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_32BIT, PGM_TYPE_REAL)];
2885	pModeData->uShwType = PGM_TYPE_32BIT;
2886	pModeData->uGstType = PGM_TYPE_REAL;
2887	rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2888	rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2889	rc = PGM_BTH_NAME_32BIT_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2890
2891	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_32BIT, PGMMODE_PROTECTED)];
2892	pModeData->uShwType = PGM_TYPE_32BIT;
2893	pModeData->uGstType = PGM_TYPE_PROT;
2894	rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2895	rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2896	rc = PGM_BTH_NAME_32BIT_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2897
2898	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_32BIT, PGM_TYPE_32BIT)];
2899	pModeData->uShwType = PGM_TYPE_32BIT;
2900	pModeData->uGstType = PGM_TYPE_32BIT;
2901	rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2902	rc = PGM_GST_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2903	rc = PGM_BTH_NAME_32BIT_32BIT(InitData)(pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2904
2905	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_REAL)];
2906	pModeData->uShwType = PGM_TYPE_PAE;
2907	pModeData->uGstType = PGM_TYPE_REAL;
2908	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2909	rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2910	rc = PGM_BTH_NAME_PAE_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2911
2912	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_PROT)];
2913	pModeData->uShwType = PGM_TYPE_PAE;
2914	pModeData->uGstType = PGM_TYPE_PROT;
2915	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2916	rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2917	rc = PGM_BTH_NAME_PAE_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2918
2919	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_32BIT)];
2920	pModeData->uShwType = PGM_TYPE_PAE;
2921	pModeData->uGstType = PGM_TYPE_32BIT;
2922	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2923	rc = PGM_GST_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2924	rc = PGM_BTH_NAME_PAE_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2925
2926	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_PAE)];
2927	pModeData->uShwType = PGM_TYPE_PAE;
2928	pModeData->uGstType = PGM_TYPE_PAE;
2929	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2930	rc = PGM_GST_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2931	rc = PGM_BTH_NAME_PAE_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2932
2933	#ifdef VBOX_WITH_64_BITS_GUESTS
2934	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_AMD64, PGM_TYPE_AMD64)];
2935	pModeData->uShwType = PGM_TYPE_AMD64;
2936	pModeData->uGstType = PGM_TYPE_AMD64;
2937	rc = PGM_SHW_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2938	rc = PGM_GST_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2939	rc = PGM_BTH_NAME_AMD64_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2940	#endif
2941
2942	/* The nested paging mode. */
2943	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_REAL)];
2944	pModeData->uShwType = PGM_TYPE_NESTED;
2945	pModeData->uGstType = PGM_TYPE_REAL;
2946	rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2947	rc = PGM_BTH_NAME_NESTED_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2948
2949	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGMMODE_PROTECTED)];
2950	pModeData->uShwType = PGM_TYPE_NESTED;
2951	pModeData->uGstType = PGM_TYPE_PROT;
2952	rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2953	rc = PGM_BTH_NAME_NESTED_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2954
2955	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_32BIT)];
2956	pModeData->uShwType = PGM_TYPE_NESTED;
2957	pModeData->uGstType = PGM_TYPE_32BIT;
2958	rc = PGM_GST_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2959	rc = PGM_BTH_NAME_NESTED_32BIT(InitData)(pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2960
2961	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_PAE)];
2962	pModeData->uShwType = PGM_TYPE_NESTED;
2963	pModeData->uGstType = PGM_TYPE_PAE;
2964	rc = PGM_GST_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2965	rc = PGM_BTH_NAME_NESTED_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2966
2967	#ifdef VBOX_WITH_64_BITS_GUESTS
2968	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_AMD64)];
2969	pModeData->uShwType = PGM_TYPE_NESTED;
2970	pModeData->uGstType = PGM_TYPE_AMD64;
2971	rc = PGM_GST_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2972	rc = PGM_BTH_NAME_NESTED_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2973	#endif
2974
2975	/* The shadow part of the nested callback mode depends on the host paging mode (AMD-V only). */
2976	switch (pVM->pgm.s.enmHostMode)
2977	{
2978	#if HC_ARCH_BITS == 32
2979	case SUPPAGINGMODE_32_BIT:
2980	case SUPPAGINGMODE_32_BIT_GLOBAL:
2981	for (unsigned i = PGM_TYPE_REAL; i <= PGM_TYPE_PAE; i++)
2982	{
2983	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, i)];
2984	rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2985	}
2986	# ifdef VBOX_WITH_64_BITS_GUESTS
2987	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_AMD64)];
2988	rc = PGM_SHW_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2989	# endif
2990	break;
2991
2992	case SUPPAGINGMODE_PAE:
2993	case SUPPAGINGMODE_PAE_NX:
2994	case SUPPAGINGMODE_PAE_GLOBAL:
2995	case SUPPAGINGMODE_PAE_GLOBAL_NX:
2996	for (unsigned i = PGM_TYPE_REAL; i <= PGM_TYPE_PAE; i++)
2997	{
2998	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, i)];
2999	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3000	}
3001	# ifdef VBOX_WITH_64_BITS_GUESTS
3002	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_AMD64)];
3003	rc = PGM_SHW_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3004	# endif
3005	break;
3006	#endif /* HC_ARCH_BITS == 32 */
3007
3008	#if HC_ARCH_BITS == 64 \|\| defined(RT_OS_DARWIN)
3009	case SUPPAGINGMODE_AMD64:
3010	case SUPPAGINGMODE_AMD64_GLOBAL:
3011	case SUPPAGINGMODE_AMD64_NX:
3012	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
3013	# ifdef VBOX_WITH_64_BITS_GUESTS
3014	for (unsigned i = PGM_TYPE_REAL; i <= PGM_TYPE_AMD64; i++)
3015	# else
3016	for (unsigned i = PGM_TYPE_REAL; i <= PGM_TYPE_PAE; i++)
3017	# endif
3018	{
3019	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, i)];
3020	rc = PGM_SHW_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3021	}
3022	break;
3023	#endif /* HC_ARCH_BITS == 64 \|\| RT_OS_DARWIN */
3024
3025	default:
3026	AssertFailed();
3027	break;
3028	}
3029
3030	/* Extended paging (EPT) / Intel VT-x */
3031	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_REAL)];
3032	pModeData->uShwType = PGM_TYPE_EPT;
3033	pModeData->uGstType = PGM_TYPE_REAL;
3034	rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3035	rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3036	rc = PGM_BTH_NAME_EPT_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3037
3038	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_PROT)];
3039	pModeData->uShwType = PGM_TYPE_EPT;
3040	pModeData->uGstType = PGM_TYPE_PROT;
3041	rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3042	rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3043	rc = PGM_BTH_NAME_EPT_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3044
3045	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_32BIT)];
3046	pModeData->uShwType = PGM_TYPE_EPT;
3047	pModeData->uGstType = PGM_TYPE_32BIT;
3048	rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3049	rc = PGM_GST_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3050	rc = PGM_BTH_NAME_EPT_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3051
3052	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_PAE)];
3053	pModeData->uShwType = PGM_TYPE_EPT;
3054	pModeData->uGstType = PGM_TYPE_PAE;
3055	rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3056	rc = PGM_GST_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3057	rc = PGM_BTH_NAME_EPT_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3058
3059	#ifdef VBOX_WITH_64_BITS_GUESTS
3060	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_AMD64)];
3061	pModeData->uShwType = PGM_TYPE_EPT;
3062	pModeData->uGstType = PGM_TYPE_AMD64;
3063	rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3064	rc = PGM_GST_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3065	rc = PGM_BTH_NAME_EPT_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3066	#endif
3067	return VINF_SUCCESS;
3068	}
3069
3070
3071	/**
3072	* Switch to different (or relocated in the relocate case) mode data.
3073	*
3074	* @param pVM The VM handle.
3075	* @param enmShw The the shadow paging mode.
3076	* @param enmGst The the guest paging mode.
3077	*/
3078	static void pgmR3ModeDataSwitch(PVM pVM, PGMMODE enmShw, PGMMODE enmGst)
3079	{
3080	PPGMMODEDATA pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndexByMode(enmShw, enmGst)];
3081
3082	Assert(pModeData->uGstType == pgmModeToType(enmGst));
3083	Assert(pModeData->uShwType == pgmModeToType(enmShw));
3084
3085	/* shadow */
3086	pVM->pgm.s.pfnR3ShwRelocate = pModeData->pfnR3ShwRelocate;
3087	pVM->pgm.s.pfnR3ShwExit = pModeData->pfnR3ShwExit;
3088	pVM->pgm.s.pfnR3ShwGetPage = pModeData->pfnR3ShwGetPage;
3089	Assert(pVM->pgm.s.pfnR3ShwGetPage);
3090	pVM->pgm.s.pfnR3ShwModifyPage = pModeData->pfnR3ShwModifyPage;
3091
3092	pVM->pgm.s.pfnRCShwGetPage = pModeData->pfnRCShwGetPage;
3093	pVM->pgm.s.pfnRCShwModifyPage = pModeData->pfnRCShwModifyPage;
3094
3095	pVM->pgm.s.pfnR0ShwGetPage = pModeData->pfnR0ShwGetPage;
3096	pVM->pgm.s.pfnR0ShwModifyPage = pModeData->pfnR0ShwModifyPage;
3097
3098
3099	/* guest */
3100	pVM->pgm.s.pfnR3GstRelocate = pModeData->pfnR3GstRelocate;
3101	pVM->pgm.s.pfnR3GstExit = pModeData->pfnR3GstExit;
3102	pVM->pgm.s.pfnR3GstGetPage = pModeData->pfnR3GstGetPage;
3103	Assert(pVM->pgm.s.pfnR3GstGetPage);
3104	pVM->pgm.s.pfnR3GstModifyPage = pModeData->pfnR3GstModifyPage;
3105	pVM->pgm.s.pfnR3GstGetPDE = pModeData->pfnR3GstGetPDE;
3106	#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
3107	pVM->pgm.s.pfnR3GstMonitorCR3 = pModeData->pfnR3GstMonitorCR3;
3108	pVM->pgm.s.pfnR3GstUnmonitorCR3 = pModeData->pfnR3GstUnmonitorCR3;
3109	#endif
3110	#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
3111	pVM->pgm.s.pfnR3GstWriteHandlerCR3 = pModeData->pfnR3GstWriteHandlerCR3;
3112	pVM->pgm.s.pszR3GstWriteHandlerCR3 = pModeData->pszR3GstWriteHandlerCR3;
3113	pVM->pgm.s.pfnR3GstPAEWriteHandlerCR3 = pModeData->pfnR3GstPAEWriteHandlerCR3;
3114	pVM->pgm.s.pszR3GstPAEWriteHandlerCR3 = pModeData->pszR3GstPAEWriteHandlerCR3;
3115	#endif
3116	pVM->pgm.s.pfnRCGstGetPage = pModeData->pfnRCGstGetPage;
3117	pVM->pgm.s.pfnRCGstModifyPage = pModeData->pfnRCGstModifyPage;
3118	pVM->pgm.s.pfnRCGstGetPDE = pModeData->pfnRCGstGetPDE;
3119	#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
3120	pVM->pgm.s.pfnRCGstMonitorCR3 = pModeData->pfnRCGstMonitorCR3;
3121	pVM->pgm.s.pfnRCGstUnmonitorCR3 = pModeData->pfnRCGstUnmonitorCR3;
3122	#endif
3123	#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
3124	pVM->pgm.s.pfnRCGstWriteHandlerCR3 = pModeData->pfnRCGstWriteHandlerCR3;
3125	pVM->pgm.s.pfnRCGstPAEWriteHandlerCR3 = pModeData->pfnRCGstPAEWriteHandlerCR3;
3126	#endif
3127	pVM->pgm.s.pfnR0GstGetPage = pModeData->pfnR0GstGetPage;
3128	pVM->pgm.s.pfnR0GstModifyPage = pModeData->pfnR0GstModifyPage;
3129	pVM->pgm.s.pfnR0GstGetPDE = pModeData->pfnR0GstGetPDE;
3130	#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
3131	pVM->pgm.s.pfnR0GstMonitorCR3 = pModeData->pfnR0GstMonitorCR3;
3132	pVM->pgm.s.pfnR0GstUnmonitorCR3 = pModeData->pfnR0GstUnmonitorCR3;
3133	#endif
3134	#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
3135	pVM->pgm.s.pfnR0GstWriteHandlerCR3 = pModeData->pfnR0GstWriteHandlerCR3;
3136	pVM->pgm.s.pfnR0GstPAEWriteHandlerCR3 = pModeData->pfnR0GstPAEWriteHandlerCR3;
3137	#endif
3138
3139	/* both */
3140	pVM->pgm.s.pfnR3BthRelocate = pModeData->pfnR3BthRelocate;
3141	pVM->pgm.s.pfnR3BthInvalidatePage = pModeData->pfnR3BthInvalidatePage;
3142	pVM->pgm.s.pfnR3BthSyncCR3 = pModeData->pfnR3BthSyncCR3;
3143	Assert(pVM->pgm.s.pfnR3BthSyncCR3);
3144	pVM->pgm.s.pfnR3BthSyncPage = pModeData->pfnR3BthSyncPage;
3145	pVM->pgm.s.pfnR3BthPrefetchPage = pModeData->pfnR3BthPrefetchPage;
3146	pVM->pgm.s.pfnR3BthVerifyAccessSyncPage = pModeData->pfnR3BthVerifyAccessSyncPage;
3147	#ifdef VBOX_STRICT
3148	pVM->pgm.s.pfnR3BthAssertCR3 = pModeData->pfnR3BthAssertCR3;
3149	#endif
3150	pVM->pgm.s.pfnR3BthMapCR3 = pModeData->pfnR3BthMapCR3;
3151	pVM->pgm.s.pfnR3BthUnmapCR3 = pModeData->pfnR3BthUnmapCR3;
3152
3153	pVM->pgm.s.pfnRCBthTrap0eHandler = pModeData->pfnRCBthTrap0eHandler;
3154	pVM->pgm.s.pfnRCBthInvalidatePage = pModeData->pfnRCBthInvalidatePage;
3155	pVM->pgm.s.pfnRCBthSyncCR3 = pModeData->pfnRCBthSyncCR3;
3156	pVM->pgm.s.pfnRCBthSyncPage = pModeData->pfnRCBthSyncPage;
3157	pVM->pgm.s.pfnRCBthPrefetchPage = pModeData->pfnRCBthPrefetchPage;
3158	pVM->pgm.s.pfnRCBthVerifyAccessSyncPage = pModeData->pfnRCBthVerifyAccessSyncPage;
3159	#ifdef VBOX_STRICT
3160	pVM->pgm.s.pfnRCBthAssertCR3 = pModeData->pfnRCBthAssertCR3;
3161	#endif
3162	pVM->pgm.s.pfnRCBthMapCR3 = pModeData->pfnRCBthMapCR3;
3163	pVM->pgm.s.pfnRCBthUnmapCR3 = pModeData->pfnRCBthUnmapCR3;
3164
3165	pVM->pgm.s.pfnR0BthTrap0eHandler = pModeData->pfnR0BthTrap0eHandler;
3166	pVM->pgm.s.pfnR0BthInvalidatePage = pModeData->pfnR0BthInvalidatePage;
3167	pVM->pgm.s.pfnR0BthSyncCR3 = pModeData->pfnR0BthSyncCR3;
3168	pVM->pgm.s.pfnR0BthSyncPage = pModeData->pfnR0BthSyncPage;
3169	pVM->pgm.s.pfnR0BthPrefetchPage = pModeData->pfnR0BthPrefetchPage;
3170	pVM->pgm.s.pfnR0BthVerifyAccessSyncPage = pModeData->pfnR0BthVerifyAccessSyncPage;
3171	#ifdef VBOX_STRICT
3172	pVM->pgm.s.pfnR0BthAssertCR3 = pModeData->pfnR0BthAssertCR3;
3173	#endif
3174	pVM->pgm.s.pfnR0BthMapCR3 = pModeData->pfnR0BthMapCR3;
3175	pVM->pgm.s.pfnR0BthUnmapCR3 = pModeData->pfnR0BthUnmapCR3;
3176	}
3177
3178
3179	/**
3180	* Calculates the shadow paging mode.
3181	*
3182	* @returns The shadow paging mode.
3183	* @param pVM VM handle.
3184	* @param enmGuestMode The guest mode.
3185	* @param enmHostMode The host mode.
3186	* @param enmShadowMode The current shadow mode.
3187	* @param penmSwitcher Where to store the switcher to use.
3188	* VMMSWITCHER_INVALID means no change.
3189	*/
3190	static PGMMODE pgmR3CalcShadowMode(PVM pVM, PGMMODE enmGuestMode, SUPPAGINGMODE enmHostMode, PGMMODE enmShadowMode, VMMSWITCHER *penmSwitcher)
3191	{
3192	VMMSWITCHER enmSwitcher = VMMSWITCHER_INVALID;
3193	switch (enmGuestMode)
3194	{
3195	/*
3196	* When switching to real or protected mode we don't change
3197	* anything since it's likely that we'll switch back pretty soon.
3198	*
3199	* During pgmR3InitPaging we'll end up here with PGMMODE_INVALID
3200	* and is supposed to determine which shadow paging and switcher to
3201	* use during init.
3202	*/
3203	case PGMMODE_REAL:
3204	case PGMMODE_PROTECTED:
3205	if ( enmShadowMode != PGMMODE_INVALID
3206	&& !HWACCMIsEnabled(pVM) /* always switch in hwaccm mode! */)
3207	break; /* (no change) */
3208
3209	switch (enmHostMode)
3210	{
3211	case SUPPAGINGMODE_32_BIT:
3212	case SUPPAGINGMODE_32_BIT_GLOBAL:
3213	enmShadowMode = PGMMODE_32_BIT;
3214	enmSwitcher = VMMSWITCHER_32_TO_32;
3215	break;
3216
3217	case SUPPAGINGMODE_PAE:
3218	case SUPPAGINGMODE_PAE_NX:
3219	case SUPPAGINGMODE_PAE_GLOBAL:
3220	case SUPPAGINGMODE_PAE_GLOBAL_NX:
3221	enmShadowMode = PGMMODE_PAE;
3222	enmSwitcher = VMMSWITCHER_PAE_TO_PAE;
3223	#ifdef DEBUG_bird
3224	if (RTEnvExist("VBOX_32BIT"))
3225	{
3226	enmShadowMode = PGMMODE_32_BIT;
3227	enmSwitcher = VMMSWITCHER_PAE_TO_32;
3228	}
3229	#endif
3230	break;
3231
3232	case SUPPAGINGMODE_AMD64:
3233	case SUPPAGINGMODE_AMD64_GLOBAL:
3234	case SUPPAGINGMODE_AMD64_NX:
3235	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
3236	enmShadowMode = PGMMODE_PAE;
3237	enmSwitcher = VMMSWITCHER_AMD64_TO_PAE;
3238	#ifdef DEBUG_bird
3239	if (RTEnvExist("VBOX_32BIT"))
3240	{
3241	enmShadowMode = PGMMODE_32_BIT;
3242	enmSwitcher = VMMSWITCHER_AMD64_TO_32;
3243	}
3244	#endif
3245	break;
3246
3247	default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
3248	}
3249	break;
3250
3251	case PGMMODE_32_BIT:
3252	switch (enmHostMode)
3253	{
3254	case SUPPAGINGMODE_32_BIT:
3255	case SUPPAGINGMODE_32_BIT_GLOBAL:
3256	enmShadowMode = PGMMODE_32_BIT;
3257	enmSwitcher = VMMSWITCHER_32_TO_32;
3258	break;
3259
3260	case SUPPAGINGMODE_PAE:
3261	case SUPPAGINGMODE_PAE_NX:
3262	case SUPPAGINGMODE_PAE_GLOBAL:
3263	case SUPPAGINGMODE_PAE_GLOBAL_NX:
3264	enmShadowMode = PGMMODE_PAE;
3265	enmSwitcher = VMMSWITCHER_PAE_TO_PAE;
3266	#ifdef DEBUG_bird
3267	if (RTEnvExist("VBOX_32BIT"))
3268	{
3269	enmShadowMode = PGMMODE_32_BIT;
3270	enmSwitcher = VMMSWITCHER_PAE_TO_32;
3271	}
3272	#endif
3273	break;
3274
3275	case SUPPAGINGMODE_AMD64:
3276	case SUPPAGINGMODE_AMD64_GLOBAL:
3277	case SUPPAGINGMODE_AMD64_NX:
3278	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
3279	enmShadowMode = PGMMODE_PAE;
3280	enmSwitcher = VMMSWITCHER_AMD64_TO_PAE;
3281	#ifdef DEBUG_bird
3282	if (RTEnvExist("VBOX_32BIT"))
3283	{
3284	enmShadowMode = PGMMODE_32_BIT;
3285	enmSwitcher = VMMSWITCHER_AMD64_TO_32;
3286	}
3287	#endif
3288	break;
3289
3290	default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
3291	}
3292	break;
3293
3294	case PGMMODE_PAE:
3295	case PGMMODE_PAE_NX: /** @todo This might require more switchers and guest+both modes. */
3296	switch (enmHostMode)
3297	{
3298	case SUPPAGINGMODE_32_BIT:
3299	case SUPPAGINGMODE_32_BIT_GLOBAL:
3300	enmShadowMode = PGMMODE_PAE;
3301	enmSwitcher = VMMSWITCHER_32_TO_PAE;
3302	break;
3303
3304	case SUPPAGINGMODE_PAE:
3305	case SUPPAGINGMODE_PAE_NX:
3306	case SUPPAGINGMODE_PAE_GLOBAL:
3307	case SUPPAGINGMODE_PAE_GLOBAL_NX:
3308	enmShadowMode = PGMMODE_PAE;
3309	enmSwitcher = VMMSWITCHER_PAE_TO_PAE;
3310	break;
3311
3312	case SUPPAGINGMODE_AMD64:
3313	case SUPPAGINGMODE_AMD64_GLOBAL:
3314	case SUPPAGINGMODE_AMD64_NX:
3315	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
3316	enmShadowMode = PGMMODE_PAE;
3317	enmSwitcher = VMMSWITCHER_AMD64_TO_PAE;
3318	break;
3319
3320	default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
3321	}
3322	break;
3323
3324	case PGMMODE_AMD64:
3325	case PGMMODE_AMD64_NX:
3326	switch (enmHostMode)
3327	{
3328	case SUPPAGINGMODE_32_BIT:
3329	case SUPPAGINGMODE_32_BIT_GLOBAL:
3330	enmShadowMode = PGMMODE_AMD64;
3331	enmSwitcher = VMMSWITCHER_32_TO_AMD64;
3332	break;
3333
3334	case SUPPAGINGMODE_PAE:
3335	case SUPPAGINGMODE_PAE_NX:
3336	case SUPPAGINGMODE_PAE_GLOBAL:
3337	case SUPPAGINGMODE_PAE_GLOBAL_NX:
3338	enmShadowMode = PGMMODE_AMD64;
3339	enmSwitcher = VMMSWITCHER_PAE_TO_AMD64;
3340	break;
3341
3342	case SUPPAGINGMODE_AMD64:
3343	case SUPPAGINGMODE_AMD64_GLOBAL:
3344	case SUPPAGINGMODE_AMD64_NX:
3345	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
3346	enmShadowMode = PGMMODE_AMD64;
3347	enmSwitcher = VMMSWITCHER_AMD64_TO_AMD64;
3348	break;
3349
3350	default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
3351	}
3352	break;
3353
3354
3355	default:
3356	AssertReleaseMsgFailed(("enmGuestMode=%d\n", enmGuestMode));
3357	return PGMMODE_INVALID;
3358	}
3359	/* Override the shadow mode is nested paging is active. */
3360	if (HWACCMIsNestedPagingActive(pVM))
3361	enmShadowMode = HWACCMGetShwPagingMode(pVM);
3362
3363	*penmSwitcher = enmSwitcher;
3364	return enmShadowMode;
3365	}
3366
3367
3368	/**
3369	* Performs the actual mode change.
3370	* This is called by PGMChangeMode and pgmR3InitPaging().
3371	*
3372	* @returns VBox status code.
3373	* @param pVM VM handle.
3374	* @param enmGuestMode The new guest mode. This is assumed to be different from
3375	* the current mode.
3376	*/
3377	VMMR3DECL(int) PGMR3ChangeMode(PVM pVM, PGMMODE enmGuestMode)
3378	{
3379	Log(("PGMR3ChangeMode: Guest mode: %s -> %s\n", PGMGetModeName(pVM->pgm.s.enmGuestMode), PGMGetModeName(enmGuestMode)));
3380	STAM_REL_COUNTER_INC(&pVM->pgm.s.cGuestModeChanges);
3381
3382	/*
3383	* Calc the shadow mode and switcher.
3384	*/
3385	VMMSWITCHER enmSwitcher;
3386	PGMMODE enmShadowMode = pgmR3CalcShadowMode(pVM, enmGuestMode, pVM->pgm.s.enmHostMode, pVM->pgm.s.enmShadowMode, &enmSwitcher);
3387	if (enmSwitcher != VMMSWITCHER_INVALID)
3388	{
3389	/*
3390	* Select new switcher.
3391	*/
3392	int rc = VMMR3SelectSwitcher(pVM, enmSwitcher);
3393	if (RT_FAILURE(rc))
3394	{
3395	AssertReleaseMsgFailed(("VMMR3SelectSwitcher(%d) -> %Rrc\n", enmSwitcher, rc));
3396	return rc;
3397	}
3398	}
3399
3400	/*
3401	* Exit old mode(s).
3402	*/
3403	/* shadow */
3404	if (enmShadowMode != pVM->pgm.s.enmShadowMode)
3405	{
3406	LogFlow(("PGMR3ChangeMode: Shadow mode: %s -> %s\n", PGMGetModeName(pVM->pgm.s.enmShadowMode), PGMGetModeName(enmShadowMode)));
3407	if (PGM_SHW_PFN(Exit, pVM))
3408	{
3409	int rc = PGM_SHW_PFN(Exit, pVM)(pVM);
3410	if (RT_FAILURE(rc))
3411	{
3412	AssertMsgFailed(("Exit failed for shadow mode %d: %Rrc\n", pVM->pgm.s.enmShadowMode, rc));
3413	return rc;
3414	}
3415	}
3416
3417	}
3418	else
3419	LogFlow(("PGMR3ChangeMode: Shadow mode remains: %s\n", PGMGetModeName(pVM->pgm.s.enmShadowMode)));
3420
3421	/* guest */
3422	if (PGM_GST_PFN(Exit, pVM))
3423	{
3424	int rc = PGM_GST_PFN(Exit, pVM)(pVM);
3425	if (RT_FAILURE(rc))
3426	{
3427	AssertMsgFailed(("Exit failed for guest mode %d: %Rrc\n", pVM->pgm.s.enmGuestMode, rc));
3428	return rc;
3429	}
3430	}
3431
3432	/*
3433	* Load new paging mode data.
3434	*/
3435	pgmR3ModeDataSwitch(pVM, enmShadowMode, enmGuestMode);
3436
3437	/*
3438	* Enter new shadow mode (if changed).
3439	*/
3440	if (enmShadowMode != pVM->pgm.s.enmShadowMode)
3441	{
3442	int rc;
3443	pVM->pgm.s.enmShadowMode = enmShadowMode;
3444	switch (enmShadowMode)
3445	{
3446	case PGMMODE_32_BIT:
3447	rc = PGM_SHW_NAME_32BIT(Enter)(pVM);
3448	break;
3449	case PGMMODE_PAE:
3450	case PGMMODE_PAE_NX:
3451	rc = PGM_SHW_NAME_PAE(Enter)(pVM);
3452	break;
3453	case PGMMODE_AMD64:
3454	case PGMMODE_AMD64_NX:
3455	rc = PGM_SHW_NAME_AMD64(Enter)(pVM);
3456	break;
3457	case PGMMODE_NESTED:
3458	rc = PGM_SHW_NAME_NESTED(Enter)(pVM);
3459	break;
3460	case PGMMODE_EPT:
3461	rc = PGM_SHW_NAME_EPT(Enter)(pVM);
3462	break;
3463	case PGMMODE_REAL:
3464	case PGMMODE_PROTECTED:
3465	default:
3466	AssertReleaseMsgFailed(("enmShadowMode=%d\n", enmShadowMode));
3467	return VERR_INTERNAL_ERROR;
3468	}
3469	if (RT_FAILURE(rc))
3470	{
3471	AssertReleaseMsgFailed(("Entering enmShadowMode=%d failed: %Rrc\n", enmShadowMode, rc));
3472	pVM->pgm.s.enmShadowMode = PGMMODE_INVALID;
3473	return rc;
3474	}
3475	}
3476
3477	#ifndef VBOX_WITH_PGMPOOL_PAGING_ONLY
3478	/** @todo This is a bug!
3479	*
3480	* We must flush the PGM pool cache if the guest mode changes; we don't always
3481	* switch shadow paging mode (e.g. protected->32-bit) and shouldn't reuse
3482	* the shadow page tables.
3483	*
3484	* That only applies when switching between paging and non-paging modes.
3485	*/
3486	/** @todo A20 setting */
3487	if ( pVM->pgm.s.CTX_SUFF(pPool)
3488	&& !HWACCMIsNestedPagingActive(pVM)
3489	&& PGMMODE_WITH_PAGING(pVM->pgm.s.enmGuestMode) != PGMMODE_WITH_PAGING(enmGuestMode))
3490	{
3491	Log(("PGMR3ChangeMode: changing guest paging mode -> flush pgm pool cache!\n"));
3492	pgmPoolFlushAll(pVM);
3493	}
3494	#endif
3495
3496	/*
3497	* Enter the new guest and shadow+guest modes.
3498	*/
3499	int rc = -1;
3500	int rc2 = -1;
3501	RTGCPHYS GCPhysCR3 = NIL_RTGCPHYS;
3502	pVM->pgm.s.enmGuestMode = enmGuestMode;
3503	switch (enmGuestMode)
3504	{
3505	case PGMMODE_REAL:
3506	rc = PGM_GST_NAME_REAL(Enter)(pVM, NIL_RTGCPHYS);
3507	switch (pVM->pgm.s.enmShadowMode)
3508	{
3509	case PGMMODE_32_BIT:
3510	rc2 = PGM_BTH_NAME_32BIT_REAL(Enter)(pVM, NIL_RTGCPHYS);
3511	break;
3512	case PGMMODE_PAE:
3513	case PGMMODE_PAE_NX:
3514	rc2 = PGM_BTH_NAME_PAE_REAL(Enter)(pVM, NIL_RTGCPHYS);
3515	break;
3516	case PGMMODE_NESTED:
3517	rc2 = PGM_BTH_NAME_NESTED_REAL(Enter)(pVM, NIL_RTGCPHYS);
3518	break;
3519	case PGMMODE_EPT:
3520	rc2 = PGM_BTH_NAME_EPT_REAL(Enter)(pVM, NIL_RTGCPHYS);
3521	break;
3522	case PGMMODE_AMD64:
3523	case PGMMODE_AMD64_NX:
3524	AssertMsgFailed(("Should use PAE shadow mode!\n"));
3525	default: AssertFailed(); break;
3526	}
3527	break;
3528
3529	case PGMMODE_PROTECTED:
3530	rc = PGM_GST_NAME_PROT(Enter)(pVM, NIL_RTGCPHYS);
3531	switch (pVM->pgm.s.enmShadowMode)
3532	{
3533	case PGMMODE_32_BIT:
3534	rc2 = PGM_BTH_NAME_32BIT_PROT(Enter)(pVM, NIL_RTGCPHYS);
3535	break;
3536	case PGMMODE_PAE:
3537	case PGMMODE_PAE_NX:
3538	rc2 = PGM_BTH_NAME_PAE_PROT(Enter)(pVM, NIL_RTGCPHYS);
3539	break;
3540	case PGMMODE_NESTED:
3541	rc2 = PGM_BTH_NAME_NESTED_PROT(Enter)(pVM, NIL_RTGCPHYS);
3542	break;
3543	case PGMMODE_EPT:
3544	rc2 = PGM_BTH_NAME_EPT_PROT(Enter)(pVM, NIL_RTGCPHYS);
3545	break;
3546	case PGMMODE_AMD64:
3547	case PGMMODE_AMD64_NX:
3548	AssertMsgFailed(("Should use PAE shadow mode!\n"));
3549	default: AssertFailed(); break;
3550	}
3551	break;
3552
3553	case PGMMODE_32_BIT:
3554	GCPhysCR3 = CPUMGetGuestCR3(pVM) & X86_CR3_PAGE_MASK;
3555	rc = PGM_GST_NAME_32BIT(Enter)(pVM, GCPhysCR3);
3556	switch (pVM->pgm.s.enmShadowMode)
3557	{
3558	case PGMMODE_32_BIT:
3559	rc2 = PGM_BTH_NAME_32BIT_32BIT(Enter)(pVM, GCPhysCR3);
3560	break;
3561	case PGMMODE_PAE:
3562	case PGMMODE_PAE_NX:
3563	rc2 = PGM_BTH_NAME_PAE_32BIT(Enter)(pVM, GCPhysCR3);
3564	break;
3565	case PGMMODE_NESTED:
3566	rc2 = PGM_BTH_NAME_NESTED_32BIT(Enter)(pVM, GCPhysCR3);
3567	break;
3568	case PGMMODE_EPT:
3569	rc2 = PGM_BTH_NAME_EPT_32BIT(Enter)(pVM, GCPhysCR3);
3570	break;
3571	case PGMMODE_AMD64:
3572	case PGMMODE_AMD64_NX:
3573	AssertMsgFailed(("Should use PAE shadow mode!\n"));
3574	default: AssertFailed(); break;
3575	}
3576	break;
3577
3578	case PGMMODE_PAE_NX:
3579	case PGMMODE_PAE:
3580	{
3581	uint32_t u32Dummy, u32Features;
3582
3583	CPUMGetGuestCpuId(pVM, 1, &u32Dummy, &u32Dummy, &u32Dummy, &u32Features);
3584	if (!(u32Features & X86_CPUID_FEATURE_EDX_PAE))
3585	{
3586	/* Pause first, then inform Main. */
3587	rc = VMR3SuspendNoSave(pVM);
3588	AssertRC(rc);
3589
3590	VMSetRuntimeError(pVM, true, "PAEmode",
3591	N_("The guest is trying to switch to the PAE mode which is currently disabled by default in VirtualBox. PAE support can be enabled using the VM settings (General/Advanced)"));
3592	/* we must return VINF_SUCCESS here otherwise the recompiler will assert */
3593	return VINF_SUCCESS;
3594	}
3595	GCPhysCR3 = CPUMGetGuestCR3(pVM) & X86_CR3_PAE_PAGE_MASK;
3596	rc = PGM_GST_NAME_PAE(Enter)(pVM, GCPhysCR3);
3597	switch (pVM->pgm.s.enmShadowMode)
3598	{
3599	case PGMMODE_PAE:
3600	case PGMMODE_PAE_NX:
3601	rc2 = PGM_BTH_NAME_PAE_PAE(Enter)(pVM, GCPhysCR3);
3602	break;
3603	case PGMMODE_NESTED:
3604	rc2 = PGM_BTH_NAME_NESTED_PAE(Enter)(pVM, GCPhysCR3);
3605	break;
3606	case PGMMODE_EPT:
3607	rc2 = PGM_BTH_NAME_EPT_PAE(Enter)(pVM, GCPhysCR3);
3608	break;
3609	case PGMMODE_32_BIT:
3610	case PGMMODE_AMD64:
3611	case PGMMODE_AMD64_NX:
3612	AssertMsgFailed(("Should use PAE shadow mode!\n"));
3613	default: AssertFailed(); break;
3614	}
3615	break;
3616	}
3617
3618	#ifdef VBOX_WITH_64_BITS_GUESTS
3619	case PGMMODE_AMD64_NX:
3620	case PGMMODE_AMD64:
3621	GCPhysCR3 = CPUMGetGuestCR3(pVM) & UINT64_C(0xfffffffffffff000); /** @todo define this mask! */
3622	rc = PGM_GST_NAME_AMD64(Enter)(pVM, GCPhysCR3);
3623	switch (pVM->pgm.s.enmShadowMode)
3624	{
3625	case PGMMODE_AMD64:
3626	case PGMMODE_AMD64_NX:
3627	rc2 = PGM_BTH_NAME_AMD64_AMD64(Enter)(pVM, GCPhysCR3);
3628	break;
3629	case PGMMODE_NESTED:
3630	rc2 = PGM_BTH_NAME_NESTED_AMD64(Enter)(pVM, GCPhysCR3);
3631	break;
3632	case PGMMODE_EPT:
3633	rc2 = PGM_BTH_NAME_EPT_AMD64(Enter)(pVM, GCPhysCR3);
3634	break;
3635	case PGMMODE_32_BIT:
3636	case PGMMODE_PAE:
3637	case PGMMODE_PAE_NX:
3638	AssertMsgFailed(("Should use AMD64 shadow mode!\n"));
3639	default: AssertFailed(); break;
3640	}
3641	break;
3642	#endif
3643
3644	default:
3645	AssertReleaseMsgFailed(("enmGuestMode=%d\n", enmGuestMode));
3646	rc = VERR_NOT_IMPLEMENTED;
3647	break;
3648	}
3649
3650	/* status codes. */
3651	AssertRC(rc);
3652	AssertRC(rc2);
3653	if (RT_SUCCESS(rc))
3654	{
3655	rc = rc2;
3656	if (RT_SUCCESS(rc)) /* no informational status codes. */
3657	rc = VINF_SUCCESS;
3658	}
3659
3660	/*
3661	* Notify SELM so it can update the TSSes with correct CR3s.
3662	*/
3663	SELMR3PagingModeChanged(pVM);
3664
3665	/* Notify HWACCM as well. */
3666	HWACCMR3PagingModeChanged(pVM, pVM->pgm.s.enmShadowMode, pVM->pgm.s.enmGuestMode);
3667	return rc;
3668	}
3669
3670
3671	/**
3672	* Dumps a PAE shadow page table.
3673	*
3674	* @returns VBox status code (VINF_SUCCESS).
3675	* @param pVM The VM handle.
3676	* @param pPT Pointer to the page table.
3677	* @param u64Address The virtual address of the page table starts.
3678	* @param fLongMode Set if this a long mode table; clear if it's a legacy mode table.
3679	* @param cMaxDepth The maxium depth.
3680	* @param pHlp Pointer to the output functions.
3681	*/
3682	static int pgmR3DumpHierarchyHCPaePT(PVM pVM, PX86PTPAE pPT, uint64_t u64Address, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
3683	{
3684	for (unsigned i = 0; i < RT_ELEMENTS(pPT->a); i++)
3685	{
3686	X86PTEPAE Pte = pPT->a[i];
3687	if (Pte.n.u1Present)
3688	{
3689	pHlp->pfnPrintf(pHlp,
3690	fLongMode /P R S A D G WT CD AT NX 4M a p ? /
3691	? "%016llx 3 \| P %c %c %c %c %c %s %s %s %s 4K %c%c%c %016llx\n"
3692	: "%08llx 2 \| P %c %c %c %c %c %s %s %s %s 4K %c%c%c %016llx\n",
3693	u64Address + ((uint64_t)i << X86_PT_PAE_SHIFT),
3694	Pte.n.u1Write ? 'W' : 'R',
3695	Pte.n.u1User ? 'U' : 'S',
3696	Pte.n.u1Accessed ? 'A' : '-',
3697	Pte.n.u1Dirty ? 'D' : '-',
3698	Pte.n.u1Global ? 'G' : '-',
3699	Pte.n.u1WriteThru ? "WT" : "--",
3700	Pte.n.u1CacheDisable? "CD" : "--",
3701	Pte.n.u1PAT ? "AT" : "--",
3702	Pte.n.u1NoExecute ? "NX" : "--",
3703	Pte.u & PGM_PTFLAGS_TRACK_DIRTY ? 'd' : '-',
3704	Pte.u & RT_BIT(10) ? '1' : '0',
3705	Pte.u & PGM_PTFLAGS_CSAM_VALIDATED? 'v' : '-',
3706	Pte.u & X86_PTE_PAE_PG_MASK);
3707	}
3708	}
3709	return VINF_SUCCESS;
3710	}
3711
3712
3713	/**
3714	* Dumps a PAE shadow page directory table.
3715	*
3716	* @returns VBox status code (VINF_SUCCESS).
3717	* @param pVM The VM handle.
3718	* @param HCPhys The physical address of the page directory table.
3719	* @param u64Address The virtual address of the page table starts.
3720	* @param cr4 The CR4, PSE is currently used.
3721	* @param fLongMode Set if this a long mode table; clear if it's a legacy mode table.
3722	* @param cMaxDepth The maxium depth.
3723	* @param pHlp Pointer to the output functions.
3724	*/
3725	static int pgmR3DumpHierarchyHCPaePD(PVM pVM, RTHCPHYS HCPhys, uint64_t u64Address, uint32_t cr4, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
3726	{
3727	PX86PDPAE pPD = (PX86PDPAE)MMPagePhys2Page(pVM, HCPhys);
3728	if (!pPD)
3729	{
3730	pHlp->pfnPrintf(pHlp, "%0*llx error! Page directory at HCPhys=%RHp was not found in the page pool!\n",
3731	fLongMode ? 16 : 8, u64Address, HCPhys);
3732	return VERR_INVALID_PARAMETER;
3733	}
3734	const bool fBigPagesSupported = fLongMode \|\| !!(cr4 & X86_CR4_PSE);
3735
3736	int rc = VINF_SUCCESS;
3737	for (unsigned i = 0; i < RT_ELEMENTS(pPD->a); i++)
3738	{
3739	X86PDEPAE Pde = pPD->a[i];
3740	if (Pde.n.u1Present)
3741	{
3742	if (fBigPagesSupported && Pde.b.u1Size)
3743	pHlp->pfnPrintf(pHlp,
3744	fLongMode /P R S A D G WT CD AT NX 4M a p ? /
3745	? "%016llx 2 \| P %c %c %c %c %c %s %s %s %s 4M %c%c%c %016llx\n"
3746	: "%08llx 1 \| P %c %c %c %c %c %s %s %s %s 4M %c%c%c %016llx\n",
3747	u64Address + ((uint64_t)i << X86_PD_PAE_SHIFT),
3748	Pde.b.u1Write ? 'W' : 'R',
3749	Pde.b.u1User ? 'U' : 'S',
3750	Pde.b.u1Accessed ? 'A' : '-',
3751	Pde.b.u1Dirty ? 'D' : '-',
3752	Pde.b.u1Global ? 'G' : '-',
3753	Pde.b.u1WriteThru ? "WT" : "--",
3754	Pde.b.u1CacheDisable? "CD" : "--",
3755	Pde.b.u1PAT ? "AT" : "--",
3756	Pde.b.u1NoExecute ? "NX" : "--",
3757	Pde.u & RT_BIT_64(9) ? '1' : '0',
3758	Pde.u & PGM_PDFLAGS_MAPPING ? 'm' : '-',
3759	Pde.u & PGM_PDFLAGS_TRACK_DIRTY ? 'd' : '-',
3760	Pde.u & X86_PDE_PAE_PG_MASK);
3761	else
3762	{
3763	pHlp->pfnPrintf(pHlp,
3764	fLongMode /P R S A D G WT CD AT NX 4M a p ? /
3765	? "%016llx 2 \| P %c %c %c %c %c %s %s .. %s 4K %c%c%c %016llx\n"
3766	: "%08llx 1 \| P %c %c %c %c %c %s %s .. %s 4K %c%c%c %016llx\n",
3767	u64Address + ((uint64_t)i << X86_PD_PAE_SHIFT),
3768	Pde.n.u1Write ? 'W' : 'R',
3769	Pde.n.u1User ? 'U' : 'S',
3770	Pde.n.u1Accessed ? 'A' : '-',
3771	Pde.n.u1Reserved0 ? '?' : '.', /* ignored */
3772	Pde.n.u1Reserved1 ? '?' : '.', /* ignored */
3773	Pde.n.u1WriteThru ? "WT" : "--",
3774	Pde.n.u1CacheDisable? "CD" : "--",
3775	Pde.n.u1NoExecute ? "NX" : "--",
3776	Pde.u & RT_BIT_64(9) ? '1' : '0',
3777	Pde.u & PGM_PDFLAGS_MAPPING ? 'm' : '-',
3778	Pde.u & PGM_PDFLAGS_TRACK_DIRTY ? 'd' : '-',
3779	Pde.u & X86_PDE_PAE_PG_MASK);
3780	if (cMaxDepth >= 1)
3781	{
3782	/** @todo what about using the page pool for mapping PTs? */
3783	uint64_t u64AddressPT = u64Address + ((uint64_t)i << X86_PD_PAE_SHIFT);
3784	RTHCPHYS HCPhysPT = Pde.u & X86_PDE_PAE_PG_MASK;
3785	PX86PTPAE pPT = NULL;
3786	if (!(Pde.u & PGM_PDFLAGS_MAPPING))
3787	pPT = (PX86PTPAE)MMPagePhys2Page(pVM, HCPhysPT);
3788	else
3789	{
3790	for (PPGMMAPPING pMap = pVM->pgm.s.pMappingsR3; pMap; pMap = pMap->pNextR3)
3791	{
3792	uint64_t off = u64AddressPT - pMap->GCPtr;
3793	if (off < pMap->cb)
3794	{
3795	const int iPDE = (uint32_t)(off >> X86_PD_SHIFT);
3796	const int iSub = (int)((off >> X86_PD_PAE_SHIFT) & 1); /* MSC is a pain sometimes */
3797	if ((iSub ? pMap->aPTs[iPDE].HCPhysPaePT1 : pMap->aPTs[iPDE].HCPhysPaePT0) != HCPhysPT)
3798	pHlp->pfnPrintf(pHlp, "%0*llx error! Mapping error! PT %d has HCPhysPT=%RHp not %RHp is in the PD.\n",
3799	fLongMode ? 16 : 8, u64AddressPT, iPDE,
3800	iSub ? pMap->aPTs[iPDE].HCPhysPaePT1 : pMap->aPTs[iPDE].HCPhysPaePT0, HCPhysPT);
3801	pPT = &pMap->aPTs[iPDE].paPaePTsR3[iSub];
3802	}
3803	}
3804	}
3805	int rc2 = VERR_INVALID_PARAMETER;
3806	if (pPT)
3807	rc2 = pgmR3DumpHierarchyHCPaePT(pVM, pPT, u64AddressPT, fLongMode, cMaxDepth - 1, pHlp);
3808	else
3809	pHlp->pfnPrintf(pHlp, "%0*llx error! Page table at HCPhys=%RHp was not found in the page pool!\n",
3810	fLongMode ? 16 : 8, u64AddressPT, HCPhysPT);
3811	if (rc2 < rc && RT_SUCCESS(rc))
3812	rc = rc2;
3813	}
3814	}
3815	}
3816	}
3817	return rc;
3818	}
3819
3820
3821	/**
3822	* Dumps a PAE shadow page directory pointer table.
3823	*
3824	* @returns VBox status code (VINF_SUCCESS).
3825	* @param pVM The VM handle.
3826	* @param HCPhys The physical address of the page directory pointer table.
3827	* @param u64Address The virtual address of the page table starts.
3828	* @param cr4 The CR4, PSE is currently used.
3829	* @param fLongMode Set if this a long mode table; clear if it's a legacy mode table.
3830	* @param cMaxDepth The maxium depth.
3831	* @param pHlp Pointer to the output functions.
3832	*/
3833	static int pgmR3DumpHierarchyHCPaePDPT(PVM pVM, RTHCPHYS HCPhys, uint64_t u64Address, uint32_t cr4, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
3834	{
3835	PX86PDPT pPDPT = (PX86PDPT)MMPagePhys2Page(pVM, HCPhys);
3836	if (!pPDPT)
3837	{
3838	pHlp->pfnPrintf(pHlp, "%0*llx error! Page directory pointer table at HCPhys=%RHp was not found in the page pool!\n",
3839	fLongMode ? 16 : 8, u64Address, HCPhys);
3840	return VERR_INVALID_PARAMETER;
3841	}
3842
3843	int rc = VINF_SUCCESS;
3844	const unsigned c = fLongMode ? RT_ELEMENTS(pPDPT->a) : X86_PG_PAE_PDPE_ENTRIES;
3845	for (unsigned i = 0; i < c; i++)
3846	{
3847	X86PDPE Pdpe = pPDPT->a[i];
3848	if (Pdpe.n.u1Present)
3849	{
3850	if (fLongMode)
3851	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a p ? /
3852	"%016llx 1 \| P %c %c %c %c %c %s %s %s %s .. %c%c%c %016llx\n",
3853	u64Address + ((uint64_t)i << X86_PDPT_SHIFT),
3854	Pdpe.lm.u1Write ? 'W' : 'R',
3855	Pdpe.lm.u1User ? 'U' : 'S',
3856	Pdpe.lm.u1Accessed ? 'A' : '-',
3857	Pdpe.lm.u3Reserved & 1? '?' : '.', /* ignored */
3858	Pdpe.lm.u3Reserved & 4? '!' : '.', /* mbz */
3859	Pdpe.lm.u1WriteThru ? "WT" : "--",
3860	Pdpe.lm.u1CacheDisable? "CD" : "--",
3861	Pdpe.lm.u3Reserved & 2? "!" : "..",/* mbz */
3862	Pdpe.lm.u1NoExecute ? "NX" : "--",
3863	Pdpe.u & RT_BIT(9) ? '1' : '0',
3864	Pdpe.u & PGM_PLXFLAGS_PERMANENT ? 'p' : '-',
3865	Pdpe.u & RT_BIT(11) ? '1' : '0',
3866	Pdpe.u & X86_PDPE_PG_MASK);
3867	else
3868	pHlp->pfnPrintf(pHlp, /P G WT CD AT NX 4M a p ? /
3869	"%08x 0 \| P %c %s %s %s %s .. %c%c%c %016llx\n",
3870	i << X86_PDPT_SHIFT,
3871	Pdpe.n.u4Reserved & 1? '!' : '.', /* mbz */
3872	Pdpe.n.u4Reserved & 4? '!' : '.', /* mbz */
3873	Pdpe.n.u1WriteThru ? "WT" : "--",
3874	Pdpe.n.u1CacheDisable? "CD" : "--",
3875	Pdpe.n.u4Reserved & 2? "!" : "..",/* mbz */
3876	Pdpe.u & RT_BIT(9) ? '1' : '0',
3877	Pdpe.u & PGM_PLXFLAGS_PERMANENT ? 'p' : '-',
3878	Pdpe.u & RT_BIT(11) ? '1' : '0',
3879	Pdpe.u & X86_PDPE_PG_MASK);
3880	if (cMaxDepth >= 1)
3881	{
3882	int rc2 = pgmR3DumpHierarchyHCPaePD(pVM, Pdpe.u & X86_PDPE_PG_MASK, u64Address + ((uint64_t)i << X86_PDPT_SHIFT),
3883	cr4, fLongMode, cMaxDepth - 1, pHlp);
3884	if (rc2 < rc && RT_SUCCESS(rc))
3885	rc = rc2;
3886	}
3887	}
3888	}
3889	return rc;
3890	}
3891
3892
3893	/**
3894	* Dumps a 32-bit shadow page table.
3895	*
3896	* @returns VBox status code (VINF_SUCCESS).
3897	* @param pVM The VM handle.
3898	* @param HCPhys The physical address of the table.
3899	* @param cr4 The CR4, PSE is currently used.
3900	* @param cMaxDepth The maxium depth.
3901	* @param pHlp Pointer to the output functions.
3902	*/
3903	static int pgmR3DumpHierarchyHcPaePML4(PVM pVM, RTHCPHYS HCPhys, uint32_t cr4, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
3904	{
3905	PX86PML4 pPML4 = (PX86PML4)MMPagePhys2Page(pVM, HCPhys);
3906	if (!pPML4)
3907	{
3908	pHlp->pfnPrintf(pHlp, "Page map level 4 at HCPhys=%RHp was not found in the page pool!\n", HCPhys);
3909	return VERR_INVALID_PARAMETER;
3910	}
3911
3912	int rc = VINF_SUCCESS;
3913	for (unsigned i = 0; i < RT_ELEMENTS(pPML4->a); i++)
3914	{
3915	X86PML4E Pml4e = pPML4->a[i];
3916	if (Pml4e.n.u1Present)
3917	{
3918	uint64_t u64Address = ((uint64_t)i << X86_PML4_SHIFT) \| (((uint64_t)i >> (X86_PML4_SHIFT - X86_PDPT_SHIFT - 1)) * 0xffff000000000000ULL);
3919	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a p ? /
3920	"%016llx 0 \| P %c %c %c %c %c %s %s %s %s .. %c%c%c %016llx\n",
3921	u64Address,
3922	Pml4e.n.u1Write ? 'W' : 'R',
3923	Pml4e.n.u1User ? 'U' : 'S',
3924	Pml4e.n.u1Accessed ? 'A' : '-',
3925	Pml4e.n.u3Reserved & 1? '?' : '.', /* ignored */
3926	Pml4e.n.u3Reserved & 4? '!' : '.', /* mbz */
3927	Pml4e.n.u1WriteThru ? "WT" : "--",
3928	Pml4e.n.u1CacheDisable? "CD" : "--",
3929	Pml4e.n.u3Reserved & 2? "!" : "..",/* mbz */
3930	Pml4e.n.u1NoExecute ? "NX" : "--",
3931	Pml4e.u & RT_BIT(9) ? '1' : '0',
3932	Pml4e.u & PGM_PLXFLAGS_PERMANENT ? 'p' : '-',
3933	Pml4e.u & RT_BIT(11) ? '1' : '0',
3934	Pml4e.u & X86_PML4E_PG_MASK);
3935
3936	if (cMaxDepth >= 1)
3937	{
3938	int rc2 = pgmR3DumpHierarchyHCPaePDPT(pVM, Pml4e.u & X86_PML4E_PG_MASK, u64Address, cr4, true, cMaxDepth - 1, pHlp);
3939	if (rc2 < rc && RT_SUCCESS(rc))
3940	rc = rc2;
3941	}
3942	}
3943	}
3944	return rc;
3945	}
3946
3947
3948	/**
3949	* Dumps a 32-bit shadow page table.
3950	*
3951	* @returns VBox status code (VINF_SUCCESS).
3952	* @param pVM The VM handle.
3953	* @param pPT Pointer to the page table.
3954	* @param u32Address The virtual address this table starts at.
3955	* @param pHlp Pointer to the output functions.
3956	*/
3957	int pgmR3DumpHierarchyHC32BitPT(PVM pVM, PX86PT pPT, uint32_t u32Address, PCDBGFINFOHLP pHlp)
3958	{
3959	for (unsigned i = 0; i < RT_ELEMENTS(pPT->a); i++)
3960	{
3961	X86PTE Pte = pPT->a[i];
3962	if (Pte.n.u1Present)
3963	{
3964	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a m d /
3965	"%08x 1 \| P %c %c %c %c %c %s %s %s .. 4K %c%c%c %08x\n",
3966	u32Address + (i << X86_PT_SHIFT),
3967	Pte.n.u1Write ? 'W' : 'R',
3968	Pte.n.u1User ? 'U' : 'S',
3969	Pte.n.u1Accessed ? 'A' : '-',
3970	Pte.n.u1Dirty ? 'D' : '-',
3971	Pte.n.u1Global ? 'G' : '-',
3972	Pte.n.u1WriteThru ? "WT" : "--",
3973	Pte.n.u1CacheDisable? "CD" : "--",
3974	Pte.n.u1PAT ? "AT" : "--",
3975	Pte.u & PGM_PTFLAGS_TRACK_DIRTY ? 'd' : '-',
3976	Pte.u & RT_BIT(10) ? '1' : '0',
3977	Pte.u & PGM_PTFLAGS_CSAM_VALIDATED ? 'v' : '-',
3978	Pte.u & X86_PDE_PG_MASK);
3979	}
3980	}
3981	return VINF_SUCCESS;
3982	}
3983
3984
3985	/**
3986	* Dumps a 32-bit shadow page directory and page tables.
3987	*
3988	* @returns VBox status code (VINF_SUCCESS).
3989	* @param pVM The VM handle.
3990	* @param cr3 The root of the hierarchy.
3991	* @param cr4 The CR4, PSE is currently used.
3992	* @param cMaxDepth How deep into the hierarchy the dumper should go.
3993	* @param pHlp Pointer to the output functions.
3994	*/
3995	int pgmR3DumpHierarchyHC32BitPD(PVM pVM, uint32_t cr3, uint32_t cr4, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
3996	{
3997	PX86PD pPD = (PX86PD)MMPagePhys2Page(pVM, cr3 & X86_CR3_PAGE_MASK);
3998	if (!pPD)
3999	{
4000	pHlp->pfnPrintf(pHlp, "Page directory at %#x was not found in the page pool!\n", cr3 & X86_CR3_PAGE_MASK);
4001	return VERR_INVALID_PARAMETER;
4002	}
4003
4004	int rc = VINF_SUCCESS;
4005	for (unsigned i = 0; i < RT_ELEMENTS(pPD->a); i++)
4006	{
4007	X86PDE Pde = pPD->a[i];
4008	if (Pde.n.u1Present)
4009	{
4010	const uint32_t u32Address = i << X86_PD_SHIFT;
4011	if ((cr4 & X86_CR4_PSE) && Pde.b.u1Size)
4012	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a m d /
4013	"%08x 0 \| P %c %c %c %c %c %s %s %s .. 4M %c%c%c %08x\n",
4014	u32Address,
4015	Pde.b.u1Write ? 'W' : 'R',
4016	Pde.b.u1User ? 'U' : 'S',
4017	Pde.b.u1Accessed ? 'A' : '-',
4018	Pde.b.u1Dirty ? 'D' : '-',
4019	Pde.b.u1Global ? 'G' : '-',
4020	Pde.b.u1WriteThru ? "WT" : "--",
4021	Pde.b.u1CacheDisable? "CD" : "--",
4022	Pde.b.u1PAT ? "AT" : "--",
4023	Pde.u & RT_BIT_64(9) ? '1' : '0',
4024	Pde.u & PGM_PDFLAGS_MAPPING ? 'm' : '-',
4025	Pde.u & PGM_PDFLAGS_TRACK_DIRTY ? 'd' : '-',
4026	Pde.u & X86_PDE4M_PG_MASK);
4027	else
4028	{
4029	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a m d /
4030	"%08x 0 \| P %c %c %c %c %c %s %s .. .. 4K %c%c%c %08x\n",
4031	u32Address,
4032	Pde.n.u1Write ? 'W' : 'R',
4033	Pde.n.u1User ? 'U' : 'S',
4034	Pde.n.u1Accessed ? 'A' : '-',
4035	Pde.n.u1Reserved0 ? '?' : '.', /* ignored */
4036	Pde.n.u1Reserved1 ? '?' : '.', /* ignored */
4037	Pde.n.u1WriteThru ? "WT" : "--",
4038	Pde.n.u1CacheDisable? "CD" : "--",
4039	Pde.u & RT_BIT_64(9) ? '1' : '0',
4040	Pde.u & PGM_PDFLAGS_MAPPING ? 'm' : '-',
4041	Pde.u & PGM_PDFLAGS_TRACK_DIRTY ? 'd' : '-',
4042	Pde.u & X86_PDE_PG_MASK);
4043	if (cMaxDepth >= 1)
4044	{
4045	/** @todo what about using the page pool for mapping PTs? */
4046	RTHCPHYS HCPhys = Pde.u & X86_PDE_PG_MASK;
4047	PX86PT pPT = NULL;
4048	if (!(Pde.u & PGM_PDFLAGS_MAPPING))
4049	pPT = (PX86PT)MMPagePhys2Page(pVM, HCPhys);
4050	else
4051	{
4052	for (PPGMMAPPING pMap = pVM->pgm.s.pMappingsR3; pMap; pMap = pMap->pNextR3)
4053	if (u32Address - pMap->GCPtr < pMap->cb)
4054	{
4055	int iPDE = (u32Address - pMap->GCPtr) >> X86_PD_SHIFT;
4056	if (pMap->aPTs[iPDE].HCPhysPT != HCPhys)
4057	pHlp->pfnPrintf(pHlp, "%08x error! Mapping error! PT %d has HCPhysPT=%RHp not %RHp is in the PD.\n",
4058	u32Address, iPDE, pMap->aPTs[iPDE].HCPhysPT, HCPhys);
4059	pPT = pMap->aPTs[iPDE].pPTR3;
4060	}
4061	}
4062	int rc2 = VERR_INVALID_PARAMETER;
4063	if (pPT)
4064	rc2 = pgmR3DumpHierarchyHC32BitPT(pVM, pPT, u32Address, pHlp);
4065	else
4066	pHlp->pfnPrintf(pHlp, "%08x error! Page table at %#x was not found in the page pool!\n", u32Address, HCPhys);
4067	if (rc2 < rc && RT_SUCCESS(rc))
4068	rc = rc2;
4069	}
4070	}
4071	}
4072	}
4073
4074	return rc;
4075	}
4076
4077
4078	/**
4079	* Dumps a 32-bit shadow page table.
4080	*
4081	* @returns VBox status code (VINF_SUCCESS).
4082	* @param pVM The VM handle.
4083	* @param pPT Pointer to the page table.
4084	* @param u32Address The virtual address this table starts at.
4085	* @param PhysSearch Address to search for.
4086	*/
4087	int pgmR3DumpHierarchyGC32BitPT(PVM pVM, PX86PT pPT, uint32_t u32Address, RTGCPHYS PhysSearch)
4088	{
4089	for (unsigned i = 0; i < RT_ELEMENTS(pPT->a); i++)
4090	{
4091	X86PTE Pte = pPT->a[i];
4092	if (Pte.n.u1Present)
4093	{
4094	Log(( /P R S A D G WT CD AT NX 4M a m d /
4095	"%08x 1 \| P %c %c %c %c %c %s %s %s .. 4K %c%c%c %08x\n",
4096	u32Address + (i << X86_PT_SHIFT),
4097	Pte.n.u1Write ? 'W' : 'R',
4098	Pte.n.u1User ? 'U' : 'S',
4099	Pte.n.u1Accessed ? 'A' : '-',
4100	Pte.n.u1Dirty ? 'D' : '-',
4101	Pte.n.u1Global ? 'G' : '-',
4102	Pte.n.u1WriteThru ? "WT" : "--",
4103	Pte.n.u1CacheDisable? "CD" : "--",
4104	Pte.n.u1PAT ? "AT" : "--",
4105	Pte.u & PGM_PTFLAGS_TRACK_DIRTY ? 'd' : '-',
4106	Pte.u & RT_BIT(10) ? '1' : '0',
4107	Pte.u & PGM_PTFLAGS_CSAM_VALIDATED ? 'v' : '-',
4108	Pte.u & X86_PDE_PG_MASK));
4109
4110	if ((Pte.u & X86_PDE_PG_MASK) == PhysSearch)
4111	{
4112	uint64_t fPageShw = 0;
4113	RTHCPHYS pPhysHC = 0;
4114
4115	PGMShwGetPage(pVM, (RTGCPTR)(u32Address + (i << X86_PT_SHIFT)), &fPageShw, &pPhysHC);
4116	Log(("Found %RGp at %RGv -> flags=%llx\n", PhysSearch, (RTGCPTR)(u32Address + (i << X86_PT_SHIFT)), fPageShw));
4117	}
4118	}
4119	}
4120	return VINF_SUCCESS;
4121	}
4122
4123
4124	/**
4125	* Dumps a 32-bit guest page directory and page tables.
4126	*
4127	* @returns VBox status code (VINF_SUCCESS).
4128	* @param pVM The VM handle.
4129	* @param cr3 The root of the hierarchy.
4130	* @param cr4 The CR4, PSE is currently used.
4131	* @param PhysSearch Address to search for.
4132	*/
4133	VMMR3DECL(int) PGMR3DumpHierarchyGC(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCPHYS PhysSearch)
4134	{
4135	bool fLongMode = false;
4136	const unsigned cch = fLongMode ? 16 : 8; NOREF(cch);
4137	PX86PD pPD = 0;
4138
4139	int rc = PGM_GCPHYS_2_PTR(pVM, cr3 & X86_CR3_PAGE_MASK, &pPD);
4140	if (RT_FAILURE(rc) \|\| !pPD)
4141	{
4142	Log(("Page directory at %#x was not found in the page pool!\n", cr3 & X86_CR3_PAGE_MASK));
4143	return VERR_INVALID_PARAMETER;
4144	}
4145
4146	Log(("cr3=%08x cr4=%08x%s\n"
4147	"%-*s P - Present\n"
4148	"%-*s \| R/W - Read (0) / Write (1)\n"
4149	"%-*s \| \| U/S - User (1) / Supervisor (0)\n"
4150	"%-*s \| \| \| A - Accessed\n"
4151	"%-*s \| \| \| \| D - Dirty\n"
4152	"%-*s \| \| \| \| \| G - Global\n"
4153	"%-*s \| \| \| \| \| \| WT - Write thru\n"
4154	"%-*s \| \| \| \| \| \| \| CD - Cache disable\n"
4155	"%-*s \| \| \| \| \| \| \| \| AT - Attribute table (PAT)\n"
4156	"%-*s \| \| \| \| \| \| \| \| \| NX - No execute (K8)\n"
4157	"%-*s \| \| \| \| \| \| \| \| \| \| 4K/4M/2M - Page size.\n"
4158	"%-*s \| \| \| \| \| \| \| \| \| \| \| AVL - a=allocated; m=mapping; d=track dirty;\n"
4159	"%-*s \| \| \| \| \| \| \| \| \| \| \| \| p=permanent; v=validated;\n"
4160	"%-*s Level \| \| \| \| \| \| \| \| \| \| \| \| Page\n"
4161	/* xxxx n **** P R S A D G WT CD AT NX 4M AVL xxxxxxxxxxxxx
4162	- W U - - - -- -- -- -- -- 010 */
4163	, cr3, cr4, fLongMode ? " Long Mode" : "",
4164	cch, "", cch, "", cch, "", cch, "", cch, "", cch, "", cch, "",
4165	cch, "", cch, "", cch, "", cch, "", cch, "", cch, "", cch, "Address"));
4166
4167	for (unsigned i = 0; i < RT_ELEMENTS(pPD->a); i++)
4168	{
4169	X86PDE Pde = pPD->a[i];
4170	if (Pde.n.u1Present)
4171	{
4172	const uint32_t u32Address = i << X86_PD_SHIFT;
4173
4174	if ((cr4 & X86_CR4_PSE) && Pde.b.u1Size)
4175	Log(( /P R S A D G WT CD AT NX 4M a m d /
4176	"%08x 0 \| P %c %c %c %c %c %s %s %s .. 4M %c%c%c %08x\n",
4177	u32Address,
4178	Pde.b.u1Write ? 'W' : 'R',
4179	Pde.b.u1User ? 'U' : 'S',
4180	Pde.b.u1Accessed ? 'A' : '-',
4181	Pde.b.u1Dirty ? 'D' : '-',
4182	Pde.b.u1Global ? 'G' : '-',
4183	Pde.b.u1WriteThru ? "WT" : "--",
4184	Pde.b.u1CacheDisable? "CD" : "--",
4185	Pde.b.u1PAT ? "AT" : "--",
4186	Pde.u & RT_BIT(9) ? '1' : '0',
4187	Pde.u & RT_BIT(10) ? '1' : '0',
4188	Pde.u & RT_BIT(11) ? '1' : '0',
4189	pgmGstGet4MBPhysPage(&pVM->pgm.s, Pde)));
4190	/** @todo PhysSearch */
4191	else
4192	{
4193	Log(( /P R S A D G WT CD AT NX 4M a m d /
4194	"%08x 0 \| P %c %c %c %c %c %s %s .. .. 4K %c%c%c %08x\n",
4195	u32Address,
4196	Pde.n.u1Write ? 'W' : 'R',
4197	Pde.n.u1User ? 'U' : 'S',
4198	Pde.n.u1Accessed ? 'A' : '-',
4199	Pde.n.u1Reserved0 ? '?' : '.', /* ignored */
4200	Pde.n.u1Reserved1 ? '?' : '.', /* ignored */
4201	Pde.n.u1WriteThru ? "WT" : "--",
4202	Pde.n.u1CacheDisable? "CD" : "--",
4203	Pde.u & RT_BIT(9) ? '1' : '0',
4204	Pde.u & RT_BIT(10) ? '1' : '0',
4205	Pde.u & RT_BIT(11) ? '1' : '0',
4206	Pde.u & X86_PDE_PG_MASK));
4207	////if (cMaxDepth >= 1)
4208	{
4209	/** @todo what about using the page pool for mapping PTs? */
4210	RTGCPHYS GCPhys = Pde.u & X86_PDE_PG_MASK;
4211	PX86PT pPT = NULL;
4212
4213	rc = PGM_GCPHYS_2_PTR(pVM, GCPhys, &pPT);
4214
4215	int rc2 = VERR_INVALID_PARAMETER;
4216	if (pPT)
4217	rc2 = pgmR3DumpHierarchyGC32BitPT(pVM, pPT, u32Address, PhysSearch);
4218	else
4219	Log(("%08x error! Page table at %#x was not found in the page pool!\n", u32Address, GCPhys));
4220	if (rc2 < rc && RT_SUCCESS(rc))
4221	rc = rc2;
4222	}
4223	}
4224	}
4225	}
4226
4227	return rc;
4228	}
4229
4230
4231	/**
4232	* Dumps a page table hierarchy use only physical addresses and cr4/lm flags.
4233	*
4234	* @returns VBox status code (VINF_SUCCESS).
4235	* @param pVM The VM handle.
4236	* @param cr3 The root of the hierarchy.
4237	* @param cr4 The cr4, only PAE and PSE is currently used.
4238	* @param fLongMode Set if long mode, false if not long mode.
4239	* @param cMaxDepth Number of levels to dump.
4240	* @param pHlp Pointer to the output functions.
4241	*/
4242	VMMR3DECL(int) PGMR3DumpHierarchyHC(PVM pVM, uint64_t cr3, uint64_t cr4, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
4243	{
4244	if (!pHlp)
4245	pHlp = DBGFR3InfoLogHlp();
4246	if (!cMaxDepth)
4247	return VINF_SUCCESS;
4248	const unsigned cch = fLongMode ? 16 : 8;
4249	pHlp->pfnPrintf(pHlp,
4250	"cr3=%08x cr4=%08x%s\n"
4251	"%-*s P - Present\n"
4252	"%-*s \| R/W - Read (0) / Write (1)\n"
4253	"%-*s \| \| U/S - User (1) / Supervisor (0)\n"
4254	"%-*s \| \| \| A - Accessed\n"
4255	"%-*s \| \| \| \| D - Dirty\n"
4256	"%-*s \| \| \| \| \| G - Global\n"
4257	"%-*s \| \| \| \| \| \| WT - Write thru\n"
4258	"%-*s \| \| \| \| \| \| \| CD - Cache disable\n"
4259	"%-*s \| \| \| \| \| \| \| \| AT - Attribute table (PAT)\n"
4260	"%-*s \| \| \| \| \| \| \| \| \| NX - No execute (K8)\n"
4261	"%-*s \| \| \| \| \| \| \| \| \| \| 4K/4M/2M - Page size.\n"
4262	"%-*s \| \| \| \| \| \| \| \| \| \| \| AVL - a=allocated; m=mapping; d=track dirty;\n"
4263	"%-*s \| \| \| \| \| \| \| \| \| \| \| \| p=permanent; v=validated;\n"
4264	"%-*s Level \| \| \| \| \| \| \| \| \| \| \| \| Page\n"
4265	/* xxxx n **** P R S A D G WT CD AT NX 4M AVL xxxxxxxxxxxxx
4266	- W U - - - -- -- -- -- -- 010 */
4267	, cr3, cr4, fLongMode ? " Long Mode" : "",
4268	cch, "", cch, "", cch, "", cch, "", cch, "", cch, "", cch, "",
4269	cch, "", cch, "", cch, "", cch, "", cch, "", cch, "", cch, "Address");
4270	if (cr4 & X86_CR4_PAE)
4271	{
4272	if (fLongMode)
4273	return pgmR3DumpHierarchyHcPaePML4(pVM, cr3 & X86_CR3_PAGE_MASK, cr4, cMaxDepth, pHlp);
4274	return pgmR3DumpHierarchyHCPaePDPT(pVM, cr3 & X86_CR3_PAE_PAGE_MASK, 0, cr4, false, cMaxDepth, pHlp);
4275	}
4276	return pgmR3DumpHierarchyHC32BitPD(pVM, cr3 & X86_CR3_PAGE_MASK, cr4, cMaxDepth, pHlp);
4277	}
4278
4279	#ifdef VBOX_WITH_DEBUGGER
4280
4281	/**
4282	* The '.pgmram' command.
4283	*
4284	* @returns VBox status.
4285	* @param pCmd Pointer to the command descriptor (as registered).
4286	* @param pCmdHlp Pointer to command helper functions.
4287	* @param pVM Pointer to the current VM (if any).
4288	* @param paArgs Pointer to (readonly) array of arguments.
4289	* @param cArgs Number of arguments in the array.
4290	*/
4291	static DECLCALLBACK(int) pgmR3CmdRam(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4292	{
4293	/*
4294	* Validate input.
4295	*/
4296	if (!pVM)
4297	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4298	if (!pVM->pgm.s.pRamRangesRC)
4299	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Sorry, no Ram is registered.\n");
4300
4301	/*
4302	* Dump the ranges.
4303	*/
4304	int rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL, "From - To (incl) pvHC\n");
4305	PPGMRAMRANGE pRam;
4306	for (pRam = pVM->pgm.s.pRamRangesR3; pRam; pRam = pRam->pNextR3)
4307	{
4308	rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL,
4309	"%RGp - %RGp %p\n",
4310	pRam->GCPhys, pRam->GCPhysLast, pRam->pvR3);
4311	if (RT_FAILURE(rc))
4312	return rc;
4313	}
4314
4315	return VINF_SUCCESS;
4316	}
4317
4318
4319	/**
4320	* The '.pgmmap' command.
4321	*
4322	* @returns VBox status.
4323	* @param pCmd Pointer to the command descriptor (as registered).
4324	* @param pCmdHlp Pointer to command helper functions.
4325	* @param pVM Pointer to the current VM (if any).
4326	* @param paArgs Pointer to (readonly) array of arguments.
4327	* @param cArgs Number of arguments in the array.
4328	*/
4329	static DECLCALLBACK(int) pgmR3CmdMap(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4330	{
4331	/*
4332	* Validate input.
4333	*/
4334	if (!pVM)
4335	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4336	if (!pVM->pgm.s.pMappingsR3)
4337	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Sorry, no mappings are registered.\n");
4338
4339	/*
4340	* Print message about the fixedness of the mappings.
4341	*/
4342	int rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL, pVM->pgm.s.fMappingsFixed ? "The mappings are FIXED.\n" : "The mappings are FLOATING.\n");
4343	if (RT_FAILURE(rc))
4344	return rc;
4345
4346	/*
4347	* Dump the ranges.
4348	*/
4349	PPGMMAPPING pCur;
4350	for (pCur = pVM->pgm.s.pMappingsR3; pCur; pCur = pCur->pNextR3)
4351	{
4352	rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL,
4353	"%08x - %08x %s\n",
4354	pCur->GCPtr, pCur->GCPtrLast, pCur->pszDesc);
4355	if (RT_FAILURE(rc))
4356	return rc;
4357	}
4358
4359	return VINF_SUCCESS;
4360	}
4361
4362
4363	/**
4364	* The '.pgmsync' command.
4365	*
4366	* @returns VBox status.
4367	* @param pCmd Pointer to the command descriptor (as registered).
4368	* @param pCmdHlp Pointer to command helper functions.
4369	* @param pVM Pointer to the current VM (if any).
4370	* @param paArgs Pointer to (readonly) array of arguments.
4371	* @param cArgs Number of arguments in the array.
4372	*/
4373	static DECLCALLBACK(int) pgmR3CmdSync(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4374	{
4375	/*
4376	* Validate input.
4377	*/
4378	if (!pVM)
4379	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4380
4381	/*
4382	* Force page directory sync.
4383	*/
4384	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
4385
4386	int rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Forcing page directory sync.\n");
4387	if (RT_FAILURE(rc))
4388	return rc;
4389
4390	return VINF_SUCCESS;
4391	}
4392
4393
4394	#ifdef VBOX_STRICT
4395	/**
4396	* The '.pgmassertcr3' command.
4397	*
4398	* @returns VBox status.
4399	* @param pCmd Pointer to the command descriptor (as registered).
4400	* @param pCmdHlp Pointer to command helper functions.
4401	* @param pVM Pointer to the current VM (if any).
4402	* @param paArgs Pointer to (readonly) array of arguments.
4403	* @param cArgs Number of arguments in the array.
4404	*/
4405	static DECLCALLBACK(int) pgmR3CmdAssertCR3(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4406	{
4407	/*
4408	* Validate input.
4409	*/
4410	if (!pVM)
4411	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4412
4413	int rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Checking shadow CR3 page tables for consistency.\n");
4414	if (RT_FAILURE(rc))
4415	return rc;
4416
4417	PGMAssertCR3(pVM, CPUMGetGuestCR3(pVM), CPUMGetGuestCR4(pVM));
4418
4419	return VINF_SUCCESS;
4420	}
4421	#endif /* VBOX_STRICT */
4422
4423
4424	/**
4425	* The '.pgmsyncalways' command.
4426	*
4427	* @returns VBox status.
4428	* @param pCmd Pointer to the command descriptor (as registered).
4429	* @param pCmdHlp Pointer to command helper functions.
4430	* @param pVM Pointer to the current VM (if any).
4431	* @param paArgs Pointer to (readonly) array of arguments.
4432	* @param cArgs Number of arguments in the array.
4433	*/
4434	static DECLCALLBACK(int) pgmR3CmdSyncAlways(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4435	{
4436	/*
4437	* Validate input.
4438	*/
4439	if (!pVM)
4440	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4441
4442	/*
4443	* Force page directory sync.
4444	*/
4445	if (pVM->pgm.s.fSyncFlags & PGM_SYNC_ALWAYS)
4446	{
4447	ASMAtomicAndU32(&pVM->pgm.s.fSyncFlags, ~PGM_SYNC_ALWAYS);
4448	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Disabled permanent forced page directory syncing.\n");
4449	}
4450	else
4451	{
4452	ASMAtomicOrU32(&pVM->pgm.s.fSyncFlags, PGM_SYNC_ALWAYS);
4453	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
4454	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Enabled permanent forced page directory syncing.\n");
4455	}
4456	}
4457
4458	#endif /* VBOX_WITH_DEBUGGER */
4459
4460	/**
4461	* pvUser argument of the pgmR3CheckIntegrity*Node callbacks.
4462	*/
4463	typedef struct PGMCHECKINTARGS
4464	{
4465	bool fLeftToRight; /*< true: left-to-right; false: right-to-left. /
4466	PPGMPHYSHANDLER pPrevPhys;
4467	PPGMVIRTHANDLER pPrevVirt;
4468	PPGMPHYS2VIRTHANDLER pPrevPhys2Virt;
4469	PVM pVM;
4470	} PGMCHECKINTARGS, *PPGMCHECKINTARGS;
4471
4472	/**
4473	* Validate a node in the physical handler tree.
4474	*
4475	* @returns 0 on if ok, other wise 1.
4476	* @param pNode The handler node.
4477	* @param pvUser pVM.
4478	*/
4479	static DECLCALLBACK(int) pgmR3CheckIntegrityPhysHandlerNode(PAVLROGCPHYSNODECORE pNode, void *pvUser)
4480	{
4481	PPGMCHECKINTARGS pArgs = (PPGMCHECKINTARGS)pvUser;
4482	PPGMPHYSHANDLER pCur = (PPGMPHYSHANDLER)pNode;
4483	AssertReleaseReturn(!((uintptr_t)pCur & 7), 1);
4484	AssertReleaseMsg(pCur->Core.Key <= pCur->Core.KeyLast,("pCur=%p %RGp-%RGp %s\n", pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
4485	AssertReleaseMsg( !pArgs->pPrevPhys
4486	\|\| (pArgs->fLeftToRight ? pArgs->pPrevPhys->Core.KeyLast < pCur->Core.Key : pArgs->pPrevPhys->Core.KeyLast > pCur->Core.Key),
4487	("pPrevPhys=%p %RGp-%RGp %s\n"
4488	" pCur=%p %RGp-%RGp %s\n",
4489	pArgs->pPrevPhys, pArgs->pPrevPhys->Core.Key, pArgs->pPrevPhys->Core.KeyLast, pArgs->pPrevPhys->pszDesc,
4490	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
4491	pArgs->pPrevPhys = pCur;
4492	return 0;
4493	}
4494
4495
4496	/**
4497	* Validate a node in the virtual handler tree.
4498	*
4499	* @returns 0 on if ok, other wise 1.
4500	* @param pNode The handler node.
4501	* @param pvUser pVM.
4502	*/
4503	static DECLCALLBACK(int) pgmR3CheckIntegrityVirtHandlerNode(PAVLROGCPTRNODECORE pNode, void *pvUser)
4504	{
4505	PPGMCHECKINTARGS pArgs = (PPGMCHECKINTARGS)pvUser;
4506	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)pNode;
4507	AssertReleaseReturn(!((uintptr_t)pCur & 7), 1);
4508	AssertReleaseMsg(pCur->Core.Key <= pCur->Core.KeyLast,("pCur=%p %RGv-%RGv %s\n", pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
4509	AssertReleaseMsg( !pArgs->pPrevVirt
4510	\|\| (pArgs->fLeftToRight ? pArgs->pPrevVirt->Core.KeyLast < pCur->Core.Key : pArgs->pPrevVirt->Core.KeyLast > pCur->Core.Key),
4511	("pPrevVirt=%p %RGv-%RGv %s\n"
4512	" pCur=%p %RGv-%RGv %s\n",
4513	pArgs->pPrevVirt, pArgs->pPrevVirt->Core.Key, pArgs->pPrevVirt->Core.KeyLast, pArgs->pPrevVirt->pszDesc,
4514	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
4515	for (unsigned iPage = 0; iPage < pCur->cPages; iPage++)
4516	{
4517	AssertReleaseMsg(pCur->aPhysToVirt[iPage].offVirtHandler == -RT_OFFSETOF(PGMVIRTHANDLER, aPhysToVirt[iPage]),
4518	("pCur=%p %RGv-%RGv %s\n"
4519	"iPage=%d offVirtHandle=%#x expected %#x\n",
4520	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc,
4521	iPage, pCur->aPhysToVirt[iPage].offVirtHandler, -RT_OFFSETOF(PGMVIRTHANDLER, aPhysToVirt[iPage])));
4522	}
4523	pArgs->pPrevVirt = pCur;
4524	return 0;
4525	}
4526
4527
4528	/**
4529	* Validate a node in the virtual handler tree.
4530	*
4531	* @returns 0 on if ok, other wise 1.
4532	* @param pNode The handler node.
4533	* @param pvUser pVM.
4534	*/
4535	static DECLCALLBACK(int) pgmR3CheckIntegrityPhysToVirtHandlerNode(PAVLROGCPHYSNODECORE pNode, void *pvUser)
4536	{
4537	PPGMCHECKINTARGS pArgs = (PPGMCHECKINTARGS)pvUser;
4538	PPGMPHYS2VIRTHANDLER pCur = (PPGMPHYS2VIRTHANDLER)pNode;
4539	AssertReleaseMsgReturn(!((uintptr_t)pCur & 3), ("\n"), 1);
4540	AssertReleaseMsgReturn(!(pCur->offVirtHandler & 3), ("\n"), 1);
4541	AssertReleaseMsg(pCur->Core.Key <= pCur->Core.KeyLast,("pCur=%p %RGp-%RGp\n", pCur, pCur->Core.Key, pCur->Core.KeyLast));
4542	AssertReleaseMsg( !pArgs->pPrevPhys2Virt
4543	\|\| (pArgs->fLeftToRight ? pArgs->pPrevPhys2Virt->Core.KeyLast < pCur->Core.Key : pArgs->pPrevPhys2Virt->Core.KeyLast > pCur->Core.Key),
4544	("pPrevPhys2Virt=%p %RGp-%RGp\n"
4545	" pCur=%p %RGp-%RGp\n",
4546	pArgs->pPrevPhys2Virt, pArgs->pPrevPhys2Virt->Core.Key, pArgs->pPrevPhys2Virt->Core.KeyLast,
4547	pCur, pCur->Core.Key, pCur->Core.KeyLast));
4548	AssertReleaseMsg( !pArgs->pPrevPhys2Virt
4549	\|\| (pArgs->fLeftToRight ? pArgs->pPrevPhys2Virt->Core.KeyLast < pCur->Core.Key : pArgs->pPrevPhys2Virt->Core.KeyLast > pCur->Core.Key),
4550	("pPrevPhys2Virt=%p %RGp-%RGp\n"
4551	" pCur=%p %RGp-%RGp\n",
4552	pArgs->pPrevPhys2Virt, pArgs->pPrevPhys2Virt->Core.Key, pArgs->pPrevPhys2Virt->Core.KeyLast,
4553	pCur, pCur->Core.Key, pCur->Core.KeyLast));
4554	AssertReleaseMsg((pCur->offNextAlias & (PGMPHYS2VIRTHANDLER_IN_TREE \| PGMPHYS2VIRTHANDLER_IS_HEAD)) == (PGMPHYS2VIRTHANDLER_IN_TREE \| PGMPHYS2VIRTHANDLER_IS_HEAD),
4555	("pCur=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4556	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias));
4557	if (pCur->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK)
4558	{
4559	PPGMPHYS2VIRTHANDLER pCur2 = pCur;
4560	for (;;)
4561	{
4562	pCur2 = (PPGMPHYS2VIRTHANDLER)((intptr_t)pCur + (pCur->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK));
4563	AssertReleaseMsg(pCur2 != pCur,
4564	(" pCur=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4565	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias));
4566	AssertReleaseMsg((pCur2->offNextAlias & (PGMPHYS2VIRTHANDLER_IN_TREE \| PGMPHYS2VIRTHANDLER_IS_HEAD)) == PGMPHYS2VIRTHANDLER_IN_TREE,
4567	(" pCur=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
4568	"pCur2=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4569	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias,
4570	pCur2, pCur2->Core.Key, pCur2->Core.KeyLast, pCur2->offVirtHandler, pCur2->offNextAlias));
4571	AssertReleaseMsg((pCur2->Core.Key ^ pCur->Core.Key) < PAGE_SIZE,
4572	(" pCur=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
4573	"pCur2=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4574	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias,
4575	pCur2, pCur2->Core.Key, pCur2->Core.KeyLast, pCur2->offVirtHandler, pCur2->offNextAlias));
4576	AssertReleaseMsg((pCur2->Core.KeyLast ^ pCur->Core.KeyLast) < PAGE_SIZE,
4577	(" pCur=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
4578	"pCur2=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4579	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias,
4580	pCur2, pCur2->Core.Key, pCur2->Core.KeyLast, pCur2->offVirtHandler, pCur2->offNextAlias));
4581	if (!(pCur2->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK))
4582	break;
4583	}
4584	}
4585
4586	pArgs->pPrevPhys2Virt = pCur;
4587	return 0;
4588	}
4589
4590
4591	/**
4592	* Perform an integrity check on the PGM component.
4593	*
4594	* @returns VINF_SUCCESS if everything is fine.
4595	* @returns VBox error status after asserting on integrity breach.
4596	* @param pVM The VM handle.
4597	*/
4598	VMMR3DECL(int) PGMR3CheckIntegrity(PVM pVM)
4599	{
4600	AssertReleaseReturn(pVM->pgm.s.offVM, VERR_INTERNAL_ERROR);
4601
4602	/*
4603	* Check the trees.
4604	*/
4605	int cErrors = 0;
4606	const static PGMCHECKINTARGS s_LeftToRight = { true, NULL, NULL, NULL, pVM };
4607	const static PGMCHECKINTARGS s_RightToLeft = { false, NULL, NULL, NULL, pVM };
4608	PGMCHECKINTARGS Args = s_LeftToRight;
4609	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysHandlers, true, pgmR3CheckIntegrityPhysHandlerNode, &Args);
4610	Args = s_RightToLeft;
4611	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysHandlers, false, pgmR3CheckIntegrityPhysHandlerNode, &Args);
4612	Args = s_LeftToRight;
4613	cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesR3->VirtHandlers, true, pgmR3CheckIntegrityVirtHandlerNode, &Args);
4614	Args = s_RightToLeft;
4615	cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesR3->VirtHandlers, false, pgmR3CheckIntegrityVirtHandlerNode, &Args);
4616	Args = s_LeftToRight;
4617	cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesR3->HyperVirtHandlers, true, pgmR3CheckIntegrityVirtHandlerNode, &Args);
4618	Args = s_RightToLeft;
4619	cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesR3->HyperVirtHandlers, false, pgmR3CheckIntegrityVirtHandlerNode, &Args);
4620	Args = s_LeftToRight;
4621	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysToVirtHandlers, true, pgmR3CheckIntegrityPhysToVirtHandlerNode, &Args);
4622	Args = s_RightToLeft;
4623	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysToVirtHandlers, false, pgmR3CheckIntegrityPhysToVirtHandlerNode, &Args);
4624
4625	return !cErrors ? VINF_SUCCESS : VERR_INTERNAL_ERROR;
4626	}
4627
4628

Note: See TracBrowser for help on using the repository browser.

source: vbox/trunk/src/VBox/VMM/PGM.cpp@ 17493

Download in other formats: