PGM.cpp@ 17639

Last change on this file since 17639 was 17627, checked in by vboxsync, 16 years ago
Always set VM_FF_PGM_SYNC_CR3 when changing mode
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1	/* $Id: PGM.cpp 17627 2009-03-10 13:45:46Z vboxsync $ */
2	/** @file
3	* PGM - Page Manager and Monitor. (Mixing stuff here, not good?)
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22
23	/** @page pg_pgm PGM - The Page Manager and Monitor
24	*
25	* @see grp_pgm,
26	* @ref pg_pgm_pool,
27	* @ref pg_pgm_phys.
28	*
29	*
30	* @section sec_pgm_modes Paging Modes
31	*
32	* There are three memory contexts: Host Context (HC), Guest Context (GC)
33	* and intermediate context. When talking about paging HC can also be refered to
34	* as "host paging", and GC refered to as "shadow paging".
35	*
36	* We define three basic paging modes: 32-bit, PAE and AMD64. The host paging mode
37	* is defined by the host operating system. The mode used in the shadow paging mode
38	* depends on the host paging mode and what the mode the guest is currently in. The
39	* following relation between the two is defined:
40	*
41	* @verbatim
42	Host > 32-bit \| PAE \| AMD64 \|
43	Guest \| \| \| \|
44	==v================================
45	32-bit 32-bit PAE PAE
46	-------\|--------\|--------\|--------\|
47	PAE PAE PAE PAE
48	-------\|--------\|--------\|--------\|
49	AMD64 AMD64 AMD64 AMD64
50	-------\|--------\|--------\|--------\| @endverbatim
51	*
52	* All configuration except those in the diagonal (upper left) are expected to
53	* require special effort from the switcher (i.e. a bit slower).
54	*
55	*
56	*
57	*
58	* @section sec_pgm_shw The Shadow Memory Context
59	*
60	*
61	* [..]
62	*
63	* Because of guest context mappings requires PDPT and PML4 entries to allow
64	* writing on AMD64, the two upper levels will have fixed flags whatever the
65	* guest is thinking of using there. So, when shadowing the PD level we will
66	* calculate the effective flags of PD and all the higher levels. In legacy
67	* PAE mode this only applies to the PWT and PCD bits (the rest are
68	* ignored/reserved/MBZ). We will ignore those bits for the present.
69	*
70	*
71	*
72	* @section sec_pgm_int The Intermediate Memory Context
73	*
74	* The world switch goes thru an intermediate memory context which purpose it is
75	* to provide different mappings of the switcher code. All guest mappings are also
76	* present in this context.
77	*
78	* The switcher code is mapped at the same location as on the host, at an
79	* identity mapped location (physical equals virtual address), and at the
80	* hypervisor location. The identity mapped location is for when the world
81	* switches that involves disabling paging.
82	*
83	* PGM maintain page tables for 32-bit, PAE and AMD64 paging modes. This
84	* simplifies switching guest CPU mode and consistency at the cost of more
85	* code to do the work. All memory use for those page tables is located below
86	* 4GB (this includes page tables for guest context mappings).
87	*
88	*
89	* @subsection subsec_pgm_int_gc Guest Context Mappings
90	*
91	* During assignment and relocation of a guest context mapping the intermediate
92	* memory context is used to verify the new location.
93	*
94	* Guest context mappings are currently restricted to below 4GB, for reasons
95	* of simplicity. This may change when we implement AMD64 support.
96	*
97	*
98	*
99	*
100	* @section sec_pgm_misc Misc
101	*
102	* @subsection subsec_pgm_misc_diff Differences Between Legacy PAE and Long Mode PAE
103	*
104	* The differences between legacy PAE and long mode PAE are:
105	* -# PDPE bits 1, 2, 5 and 6 are defined differently. In leagcy mode they are
106	* all marked down as must-be-zero, while in long mode 1, 2 and 5 have the
107	* usual meanings while 6 is ignored (AMD). This means that upon switching to
108	* legacy PAE mode we'll have to clear these bits and when going to long mode
109	* they must be set. This applies to both intermediate and shadow contexts,
110	* however we don't need to do it for the intermediate one since we're
111	* executing with CR0.WP at that time.
112	* -# CR3 allows a 32-byte aligned address in legacy mode, while in long mode
113	* a page aligned one is required.
114	*
115	*
116	* @section sec_pgm_handlers Access Handlers
117	*
118	* Placeholder.
119	*
120	*
121	* @subsection sec_pgm_handlers_virt Virtual Access Handlers
122	*
123	* Placeholder.
124	*
125	*
126	* @subsection sec_pgm_handlers_virt Virtual Access Handlers
127	*
128	* We currently implement three types of virtual access handlers: ALL, WRITE
129	* and HYPERVISOR (WRITE). See PGMVIRTHANDLERTYPE for some more details.
130	*
131	* The HYPERVISOR access handlers is kept in a separate tree since it doesn't apply
132	* to physical pages (PGMTREES::HyperVirtHandlers) and only needs to be consulted in
133	* a special \#PF case. The ALL and WRITE are in the PGMTREES::VirtHandlers tree, the
134	* rest of this section is going to be about these handlers.
135	*
136	* We'll go thru the life cycle of a handler and try make sense of it all, don't know
137	* how successfull this is gonna be...
138	*
139	* 1. A handler is registered thru the PGMR3HandlerVirtualRegister and
140	* PGMHandlerVirtualRegisterEx APIs. We check for conflicting virtual handlers
141	* and create a new node that is inserted into the AVL tree (range key). Then
142	* a full PGM resync is flagged (clear pool, sync cr3, update virtual bit of PGMPAGE).
143	*
144	* 2. The following PGMSyncCR3/SyncCR3 operation will first make invoke HandlerVirtualUpdate.
145	*
146	* 2a. HandlerVirtualUpdate will will lookup all the pages covered by virtual handlers
147	* via the current guest CR3 and update the physical page -> virtual handler
148	* translation. Needless to say, this doesn't exactly scale very well. If any changes
149	* are detected, it will flag a virtual bit update just like we did on registration.
150	* PGMPHYS pages with changes will have their virtual handler state reset to NONE.
151	*
152	* 2b. The virtual bit update process will iterate all the pages covered by all the
153	* virtual handlers and update the PGMPAGE virtual handler state to the max of all
154	* virtual handlers on that page.
155	*
156	* 2c. Back in SyncCR3 we will now flush the entire shadow page cache to make sure
157	* we don't miss any alias mappings of the monitored pages.
158	*
159	* 2d. SyncCR3 will then proceed with syncing the CR3 table.
160	*
161	* 3. \#PF(np,read) on a page in the range. This will cause it to be synced
162	* read-only and resumed if it's a WRITE handler. If it's an ALL handler we
163	* will call the handlers like in the next step. If the physical mapping has
164	* changed we will - some time in the future - perform a handler callback
165	* (optional) and update the physical -> virtual handler cache.
166	*
167	* 4. \#PF(,write) on a page in the range. This will cause the handler to
168	* be invoked.
169	*
170	* 5. The guest invalidates the page and changes the physical backing or
171	* unmaps it. This should cause the invalidation callback to be invoked
172	* (it might not yet be 100% perfect). Exactly what happens next... is
173	* this where we mess up and end up out of sync for a while?
174	*
175	* 6. The handler is deregistered by the client via PGMHandlerVirtualDeregister.
176	* We will then set all PGMPAGEs in the physical -> virtual handler cache for
177	* this handler to NONE and trigger a full PGM resync (basically the same
178	* as int step 1). Which means 2 is executed again.
179	*
180	*
181	* @subsubsection sub_sec_pgm_handler_virt_todo TODOs
182	*
183	* There is a bunch of things that needs to be done to make the virtual handlers
184	* work 100% correctly and work more efficiently.
185	*
186	* The first bit hasn't been implemented yet because it's going to slow the
187	* whole mess down even more, and besides it seems to be working reliably for
188	* our current uses. OTOH, some of the optimizations might end up more or less
189	* implementing the missing bits, so we'll see.
190	*
191	* On the optimization side, the first thing to do is to try avoid unnecessary
192	* cache flushing. Then try team up with the shadowing code to track changes
193	* in mappings by means of access to them (shadow in), updates to shadows pages,
194	* invlpg, and shadow PT discarding (perhaps).
195	*
196	* Some idea that have popped up for optimization for current and new features:
197	* - bitmap indicating where there are virtual handlers installed.
198	* (4KB => 220 pages, page 212 => covers 32-bit address space 1:1!)
199	* - Further optimize this by min/max (needs min/max avl getters).
200	* - Shadow page table entry bit (if any left)?
201	*
202	*/
203
204
205	/** @page pg_pgm_phys PGM Physical Guest Memory Management
206	*
207	*
208	* Objectives:
209	* - Guest RAM over-commitment using memory ballooning,
210	* zero pages and general page sharing.
211	* - Moving or mirroring a VM onto a different physical machine.
212	*
213	*
214	* @subsection subsec_pgmPhys_Definitions Definitions
215	*
216	* Allocation chunk - A RTR0MemObjAllocPhysNC object and the tracking
217	* machinery assoicated with it.
218	*
219	*
220	*
221	*
222	* @subsection subsec_pgmPhys_AllocPage Allocating a page.
223	*
224	* Initially we map all guest memory to the (per VM) zero page, which
225	* means that none of the read functions will cause pages to be allocated.
226	*
227	* Exception, access bit in page tables that have been shared. This must
228	* be handled, but we must also make sure PGMGst*Modify doesn't make
229	* unnecessary modifications.
230	*
231	* Allocation points:
232	* - PGMPhysSimpleWriteGCPhys and PGMPhysWrite.
233	* - Replacing a zero page mapping at \#PF.
234	* - Replacing a shared page mapping at \#PF.
235	* - ROM registration (currently MMR3RomRegister).
236	* - VM restore (pgmR3Load).
237	*
238	* For the first three it would make sense to keep a few pages handy
239	* until we've reached the max memory commitment for the VM.
240	*
241	* For the ROM registration, we know exactly how many pages we need
242	* and will request these from ring-0. For restore, we will save
243	* the number of non-zero pages in the saved state and allocate
244	* them up front. This would allow the ring-0 component to refuse
245	* the request if the isn't sufficient memory available for VM use.
246	*
247	* Btw. for both ROM and restore allocations we won't be requiring
248	* zeroed pages as they are going to be filled instantly.
249	*
250	*
251	* @subsection subsec_pgmPhys_FreePage Freeing a page
252	*
253	* There are a few points where a page can be freed:
254	* - After being replaced by the zero page.
255	* - After being replaced by a shared page.
256	* - After being ballooned by the guest additions.
257	* - At reset.
258	* - At restore.
259	*
260	* When freeing one or more pages they will be returned to the ring-0
261	* component and replaced by the zero page.
262	*
263	* The reasoning for clearing out all the pages on reset is that it will
264	* return us to the exact same state as on power on, and may thereby help
265	* us reduce the memory load on the system. Further it might have a
266	* (temporary) positive influence on memory fragmentation (@see subsec_pgmPhys_Fragmentation).
267	*
268	* On restore, as mention under the allocation topic, pages should be
269	* freed / allocated depending on how many is actually required by the
270	* new VM state. The simplest approach is to do like on reset, and free
271	* all non-ROM pages and then allocate what we need.
272	*
273	* A measure to prevent some fragmentation, would be to let each allocation
274	* chunk have some affinity towards the VM having allocated the most pages
275	* from it. Also, try make sure to allocate from allocation chunks that
276	* are almost full. Admittedly, both these measures might work counter to
277	* our intentions and its probably not worth putting a lot of effort,
278	* cpu time or memory into this.
279	*
280	*
281	* @subsection subsec_pgmPhys_SharePage Sharing a page
282	*
283	* The basic idea is that there there will be a idle priority kernel
284	* thread walking the non-shared VM pages hashing them and looking for
285	* pages with the same checksum. If such pages are found, it will compare
286	* them byte-by-byte to see if they actually are identical. If found to be
287	* identical it will allocate a shared page, copy the content, check that
288	* the page didn't change while doing this, and finally request both the
289	* VMs to use the shared page instead. If the page is all zeros (special
290	* checksum and byte-by-byte check) it will request the VM that owns it
291	* to replace it with the zero page.
292	*
293	* To make this efficient, we will have to make sure not to try share a page
294	* that will change its contents soon. This part requires the most work.
295	* A simple idea would be to request the VM to write monitor the page for
296	* a while to make sure it isn't modified any time soon. Also, it may
297	* make sense to skip pages that are being write monitored since this
298	* information is readily available to the thread if it works on the
299	* per-VM guest memory structures (presently called PGMRAMRANGE).
300	*
301	*
302	* @subsection subsec_pgmPhys_Fragmentation Fragmentation Concerns and Counter Measures
303	*
304	* The pages are organized in allocation chunks in ring-0, this is a necessity
305	* if we wish to have an OS agnostic approach to this whole thing. (On Linux we
306	* could easily work on a page-by-page basis if we liked. Whether this is possible
307	* or efficient on NT I don't quite know.) Fragmentation within these chunks may
308	* become a problem as part of the idea here is that we wish to return memory to
309	* the host system.
310	*
311	* For instance, starting two VMs at the same time, they will both allocate the
312	* guest memory on-demand and if permitted their page allocations will be
313	* intermixed. Shut down one of the two VMs and it will be difficult to return
314	* any memory to the host system because the page allocation for the two VMs are
315	* mixed up in the same allocation chunks.
316	*
317	* To further complicate matters, when pages are freed because they have been
318	* ballooned or become shared/zero the whole idea is that the page is supposed
319	* to be reused by another VM or returned to the host system. This will cause
320	* allocation chunks to contain pages belonging to different VMs and prevent
321	* returning memory to the host when one of those VM shuts down.
322	*
323	* The only way to really deal with this problem is to move pages. This can
324	* either be done at VM shutdown and or by the idle priority worker thread
325	* that will be responsible for finding sharable/zero pages. The mechanisms
326	* involved for coercing a VM to move a page (or to do it for it) will be
327	* the same as when telling it to share/zero a page.
328	*
329	*
330	* @subsection subsec_pgmPhys_Tracking Tracking Structures And Their Cost
331	*
332	* There's a difficult balance between keeping the per-page tracking structures
333	* (global and guest page) easy to use and keeping them from eating too much
334	* memory. We have limited virtual memory resources available when operating in
335	* 32-bit kernel space (on 64-bit there'll it's quite a different story). The
336	* tracking structures will be attemted designed such that we can deal with up
337	* to 32GB of memory on a 32-bit system and essentially unlimited on 64-bit ones.
338	*
339	*
340	* @subsubsection subsubsec_pgmPhys_Tracking_Kernel Kernel Space
341	*
342	* @see pg_GMM
343	*
344	* @subsubsection subsubsec_pgmPhys_Tracking_PerVM Per-VM
345	*
346	* Fixed info is the physical address of the page (HCPhys) and the page id
347	* (described above). Theoretically we'll need 48(-12) bits for the HCPhys part.
348	* Today we've restricting ourselves to 40(-12) bits because this is the current
349	* restrictions of all AMD64 implementations (I think Barcelona will up this
350	* to 48(-12) bits, not that it really matters) and I needed the bits for
351	* tracking mappings of a page. 48-12 = 36. That leaves 28 bits, which means a
352	* decent range for the page id: 2^(28+12) = 1024TB.
353	*
354	* In additions to these, we'll have to keep maintaining the page flags as we
355	* currently do. Although it wouldn't harm to optimize these quite a bit, like
356	* for instance the ROM shouldn't depend on having a write handler installed
357	* in order for it to become read-only. A RO/RW bit should be considered so
358	* that the page syncing code doesn't have to mess about checking multiple
359	* flag combinations (ROM \|\| RW handler \|\| write monitored) in order to
360	* figure out how to setup a shadow PTE. But this of course, is second
361	* priority at present. Current this requires 12 bits, but could probably
362	* be optimized to ~8.
363	*
364	* Then there's the 24 bits used to track which shadow page tables are
365	* currently mapping a page for the purpose of speeding up physical
366	* access handlers, and thereby the page pool cache. More bit for this
367	* purpose wouldn't hurt IIRC.
368	*
369	* Then there is a new bit in which we need to record what kind of page
370	* this is, shared, zero, normal or write-monitored-normal. This'll
371	* require 2 bits. One bit might be needed for indicating whether a
372	* write monitored page has been written to. And yet another one or
373	* two for tracking migration status. 3-4 bits total then.
374	*
375	* Whatever is left will can be used to record the sharabilitiy of a
376	* page. The page checksum will not be stored in the per-VM table as
377	* the idle thread will not be permitted to do modifications to it.
378	* It will instead have to keep its own working set of potentially
379	* shareable pages and their check sums and stuff.
380	*
381	* For the present we'll keep the current packing of the
382	* PGMRAMRANGE::aHCPhys to keep the changes simple, only of course,
383	* we'll have to change it to a struct with a total of 128-bits at
384	* our disposal.
385	*
386	* The initial layout will be like this:
387	* @verbatim
388	RTHCPHYS HCPhys; The current stuff.
389	63:40 Current shadow PT tracking stuff.
390	39:12 The physical page frame number.
391	11:0 The current flags.
392	uint32_t u28PageId : 28; The page id.
393	uint32_t u2State : 2; The page state { zero, shared, normal, write monitored }.
394	uint32_t fWrittenTo : 1; Whether a write monitored page was written to.
395	uint32_t u1Reserved : 1; Reserved for later.
396	uint32_t u32Reserved; Reserved for later, mostly sharing stats.
397	@endverbatim
398	*
399	* The final layout will be something like this:
400	* @verbatim
401	RTHCPHYS HCPhys; The current stuff.
402	63:48 High page id (12+).
403	47:12 The physical page frame number.
404	11:0 Low page id.
405	uint32_t fReadOnly : 1; Whether it's readonly page (rom or monitored in some way).
406	uint32_t u3Type : 3; The page type {RESERVED, MMIO, MMIO2, ROM, shadowed ROM, RAM}.
407	uint32_t u2PhysMon : 2; Physical access handler type {none, read, write, all}.
408	uint32_t u2VirtMon : 2; Virtual access handler type {none, read, write, all}..
409	uint32_t u2State : 2; The page state { zero, shared, normal, write monitored }.
410	uint32_t fWrittenTo : 1; Whether a write monitored page was written to.
411	uint32_t u20Reserved : 20; Reserved for later, mostly sharing stats.
412	uint32_t u32Tracking; The shadow PT tracking stuff, roughly.
413	@endverbatim
414	*
415	* Cost wise, this means we'll double the cost for guest memory. There isn't anyway
416	* around that I'm afraid. It means that the cost of dealing out 32GB of memory
417	* to one or more VMs is: (32GB >> PAGE_SHIFT) * 16 bytes, or 128MBs. Or another
418	* example, the VM heap cost when assigning 1GB to a VM will be: 4MB.
419	*
420	* A couple of cost examples for the total cost per-VM + kernel.
421	* 32-bit Windows and 32-bit linux:
422	* 1GB guest ram, 256K pages: 4MB + 2MB(+) = 6MB
423	* 4GB guest ram, 1M pages: 16MB + 8MB(+) = 24MB
424	* 32GB guest ram, 8M pages: 128MB + 64MB(+) = 192MB
425	* 64-bit Windows and 64-bit linux:
426	* 1GB guest ram, 256K pages: 4MB + 3MB(+) = 7MB
427	* 4GB guest ram, 1M pages: 16MB + 12MB(+) = 28MB
428	* 32GB guest ram, 8M pages: 128MB + 96MB(+) = 224MB
429	*
430	* UPDATE - 2007-09-27:
431	* Will need a ballooned flag/state too because we cannot
432	* trust the guest 100% and reporting the same page as ballooned more
433	* than once will put the GMM off balance.
434	*
435	*
436	* @subsection subsec_pgmPhys_Serializing Serializing Access
437	*
438	* Initially, we'll try a simple scheme:
439	*
440	* - The per-VM RAM tracking structures (PGMRAMRANGE) is only modified
441	* by the EMT thread of that VM while in the pgm critsect.
442	* - Other threads in the VM process that needs to make reliable use of
443	* the per-VM RAM tracking structures will enter the critsect.
444	* - No process external thread or kernel thread will ever try enter
445	* the pgm critical section, as that just won't work.
446	* - The idle thread (and similar threads) doesn't not need 100% reliable
447	* data when performing it tasks as the EMT thread will be the one to
448	* do the actual changes later anyway. So, as long as it only accesses
449	* the main ram range, it can do so by somehow preventing the VM from
450	* being destroyed while it works on it...
451	*
452	* - The over-commitment management, including the allocating/freeing
453	* chunks, is serialized by a ring-0 mutex lock (a fast one since the
454	* more mundane mutex implementation is broken on Linux).
455	* - A separeate mutex is protecting the set of allocation chunks so
456	* that pages can be shared or/and freed up while some other VM is
457	* allocating more chunks. This mutex can be take from under the other
458	* one, but not the otherway around.
459	*
460	*
461	* @subsection subsec_pgmPhys_Request VM Request interface
462	*
463	* When in ring-0 it will become necessary to send requests to a VM so it can
464	* for instance move a page while defragmenting during VM destroy. The idle
465	* thread will make use of this interface to request VMs to setup shared
466	* pages and to perform write monitoring of pages.
467	*
468	* I would propose an interface similar to the current VMReq interface, similar
469	* in that it doesn't require locking and that the one sending the request may
470	* wait for completion if it wishes to. This shouldn't be very difficult to
471	* realize.
472	*
473	* The requests themselves are also pretty simple. They are basically:
474	* -# Check that some precondition is still true.
475	* -# Do the update.
476	* -# Update all shadow page tables involved with the page.
477	*
478	* The 3rd step is identical to what we're already doing when updating a
479	* physical handler, see pgmHandlerPhysicalSetRamFlagsAndFlushShadowPTs.
480	*
481	*
482	*
483	* @section sec_pgmPhys_MappingCaches Mapping Caches
484	*
485	* In order to be able to map in and out memory and to be able to support
486	* guest with more RAM than we've got virtual address space, we'll employing
487	* a mapping cache. There is already a tiny one for GC (see PGMGCDynMapGCPageEx)
488	* and we'll create a similar one for ring-0 unless we decide to setup a dedicate
489	* memory context for the HWACCM execution.
490	*
491	*
492	* @subsection subsec_pgmPhys_MappingCaches_R3 Ring-3
493	*
494	* We've considered implementing the ring-3 mapping cache page based but found
495	* that this was bother some when one had to take into account TLBs+SMP and
496	* portability (missing the necessary APIs on several platforms). There were
497	* also some performance concerns with this approach which hadn't quite been
498	* worked out.
499	*
500	* Instead, we'll be mapping allocation chunks into the VM process. This simplifies
501	* matters greatly quite a bit since we don't need to invent any new ring-0 stuff,
502	* only some minor RTR0MEMOBJ mapping stuff. The main concern here is that mapping
503	* compared to the previous idea is that mapping or unmapping a 1MB chunk is more
504	* costly than a single page, although how much more costly is uncertain. We'll
505	* try address this by using a very big cache, preferably bigger than the actual
506	* VM RAM size if possible. The current VM RAM sizes should give some idea for
507	* 32-bit boxes, while on 64-bit we can probably get away with employing an
508	* unlimited cache.
509	*
510	* The cache have to parts, as already indicated, the ring-3 side and the
511	* ring-0 side.
512	*
513	* The ring-0 will be tied to the page allocator since it will operate on the
514	* memory objects it contains. It will therefore require the first ring-0 mutex
515	* discussed in @ref subsec_pgmPhys_Serializing. We
516	* some double house keeping wrt to who has mapped what I think, since both
517	* VMMR0.r0 and RTR0MemObj will keep track of mapping relataions
518	*
519	* The ring-3 part will be protected by the pgm critsect. For simplicity, we'll
520	* require anyone that desires to do changes to the mapping cache to do that
521	* from within this critsect. Alternatively, we could employ a separate critsect
522	* for serializing changes to the mapping cache as this would reduce potential
523	* contention with other threads accessing mappings unrelated to the changes
524	* that are in process. We can see about this later, contention will show
525	* up in the statistics anyway, so it'll be simple to tell.
526	*
527	* The organization of the ring-3 part will be very much like how the allocation
528	* chunks are organized in ring-0, that is in an AVL tree by chunk id. To avoid
529	* having to walk the tree all the time, we'll have a couple of lookaside entries
530	* like in we do for I/O ports and MMIO in IOM.
531	*
532	* The simplified flow of a PGMPhysRead/Write function:
533	* -# Enter the PGM critsect.
534	* -# Lookup GCPhys in the ram ranges and get the Page ID.
535	* -# Calc the Allocation Chunk ID from the Page ID.
536	* -# Check the lookaside entries and then the AVL tree for the Chunk ID.
537	* If not found in cache:
538	* -# Call ring-0 and request it to be mapped and supply
539	* a chunk to be unmapped if the cache is maxed out already.
540	* -# Insert the new mapping into the AVL tree (id + R3 address).
541	* -# Update the relevant lookaside entry and return the mapping address.
542	* -# Do the read/write according to monitoring flags and everything.
543	* -# Leave the critsect.
544	*
545	*
546	* @section sec_pgmPhys_Fallback Fallback
547	*
548	* Current all the "second tier" hosts will not support the RTR0MemObjAllocPhysNC
549	* API and thus require a fallback.
550	*
551	* So, when RTR0MemObjAllocPhysNC returns VERR_NOT_SUPPORTED the page allocator
552	* will return to the ring-3 caller (and later ring-0) and asking it to seed
553	* the page allocator with some fresh pages (VERR_GMM_SEED_ME). Ring-3 will
554	* then perform an SUPPageAlloc(cbChunk >> PAGE_SHIFT) call and make a
555	* "SeededAllocPages" call to ring-0.
556	*
557	* The first time ring-0 sees the VERR_NOT_SUPPORTED failure it will disable
558	* all page sharing (zero page detection will continue). It will also force
559	* all allocations to come from the VM which seeded the page. Both these
560	* measures are taken to make sure that there will never be any need for
561	* mapping anything into ring-3 - everything will be mapped already.
562	*
563	* Whether we'll continue to use the current MM locked memory management
564	* for this I don't quite know (I'd prefer not to and just ditch that all
565	* togther), we'll see what's simplest to do.
566	*
567	*
568	*
569	* @section sec_pgmPhys_Changes Changes
570	*
571	* Breakdown of the changes involved?
572	*/
573
574
575	/** Saved state data unit version. */
576	#define PGM_SAVED_STATE_VERSION 6
577
578	/*******************************************************************************
579	* Header Files *
580	*******************************************************************************/
581	#define LOG_GROUP LOG_GROUP_PGM
582	#include <VBox/dbgf.h>
583	#include <VBox/pgm.h>
584	#include <VBox/cpum.h>
585	#include <VBox/iom.h>
586	#include <VBox/sup.h>
587	#include <VBox/mm.h>
588	#include <VBox/em.h>
589	#include <VBox/stam.h>
590	#include <VBox/rem.h>
591	#include <VBox/dbgf.h>
592	#include <VBox/rem.h>
593	#include <VBox/selm.h>
594	#include <VBox/ssm.h>
595	#include "PGMInternal.h"
596	#include <VBox/vm.h>
597	#include <VBox/dbg.h>
598	#include <VBox/hwaccm.h>
599
600	#include <iprt/assert.h>
601	#include <iprt/alloc.h>
602	#include <iprt/asm.h>
603	#include <iprt/thread.h>
604	#include <iprt/string.h>
605	#ifdef DEBUG_bird
606	# include <iprt/env.h>
607	#endif
608	#include <VBox/param.h>
609	#include <VBox/err.h>
610
611
612
613	/*******************************************************************************
614	* Internal Functions *
615	*******************************************************************************/
616	static int pgmR3InitPaging(PVM pVM);
617	static DECLCALLBACK(void) pgmR3PhysInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
618	static DECLCALLBACK(void) pgmR3InfoMode(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
619	static DECLCALLBACK(void) pgmR3InfoCr3(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
620	static DECLCALLBACK(int) pgmR3RelocatePhysHandler(PAVLROGCPHYSNODECORE pNode, void *pvUser);
621	static DECLCALLBACK(int) pgmR3RelocateVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser);
622	static DECLCALLBACK(int) pgmR3RelocateHyperVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser);
623	#ifdef VBOX_STRICT
624	static DECLCALLBACK(void) pgmR3ResetNoMorePhysWritesFlag(PVM pVM, VMSTATE enmState, VMSTATE enmOldState, void *pvUser);
625	#endif
626	static DECLCALLBACK(int) pgmR3Save(PVM pVM, PSSMHANDLE pSSM);
627	static DECLCALLBACK(int) pgmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version);
628	static int pgmR3ModeDataInit(PVM pVM, bool fResolveGCAndR0);
629	static void pgmR3ModeDataSwitch(PVM pVM, PGMMODE enmShw, PGMMODE enmGst);
630	static PGMMODE pgmR3CalcShadowMode(PVM pVM, PGMMODE enmGuestMode, SUPPAGINGMODE enmHostMode, PGMMODE enmShadowMode, VMMSWITCHER *penmSwitcher);
631
632	#ifdef VBOX_WITH_STATISTICS
633	static void pgmR3InitStats(PVM pVM);
634	#endif
635
636	#ifdef VBOX_WITH_DEBUGGER
637	/** @todo all but the two last commands must be converted to 'info'. */
638	static DECLCALLBACK(int) pgmR3CmdRam(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
639	static DECLCALLBACK(int) pgmR3CmdMap(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
640	static DECLCALLBACK(int) pgmR3CmdSync(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
641	static DECLCALLBACK(int) pgmR3CmdSyncAlways(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
642	# ifdef VBOX_STRICT
643	static DECLCALLBACK(int) pgmR3CmdAssertCR3(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
644	# endif
645	#endif
646
647
648	/*******************************************************************************
649	* Global Variables *
650	*******************************************************************************/
651	#ifdef VBOX_WITH_DEBUGGER
652	/** Command descriptors. */
653	static const DBGCCMD g_aCmds[] =
654	{
655	/* pszCmd, cArgsMin, cArgsMax, paArgDesc, cArgDescs, pResultDesc, fFlags, pfnHandler pszSyntax, ....pszDescription */
656	{ "pgmram", 0, 0, NULL, 0, NULL, 0, pgmR3CmdRam, "", "Display the ram ranges." },
657	{ "pgmmap", 0, 0, NULL, 0, NULL, 0, pgmR3CmdMap, "", "Display the mapping ranges." },
658	{ "pgmsync", 0, 0, NULL, 0, NULL, 0, pgmR3CmdSync, "", "Sync the CR3 page." },
659	#ifdef VBOX_STRICT
660	{ "pgmassertcr3", 0, 0, NULL, 0, NULL, 0, pgmR3CmdAssertCR3, "", "Check the shadow CR3 mapping." },
661	#endif
662	{ "pgmsyncalways", 0, 0, NULL, 0, NULL, 0, pgmR3CmdSyncAlways, "", "Toggle permanent CR3 syncing." },
663	};
664	#endif
665
666
667
668
669	/*
670	* Shadow - 32-bit mode
671	*/
672	#define PGM_SHW_TYPE PGM_TYPE_32BIT
673	#define PGM_SHW_NAME(name) PGM_SHW_NAME_32BIT(name)
674	#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_32BIT_STR(name)
675	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_32BIT_STR(name)
676	#include "PGMShw.h"
677
678	/* Guest - real mode */
679	#define PGM_GST_TYPE PGM_TYPE_REAL
680	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
681	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_REAL_STR(name)
682	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
683	#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_REAL(name)
684	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_32BIT_REAL_STR(name)
685	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_32BIT_REAL_STR(name)
686	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_PHYS
687	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_32BIT_PD_PHYS
688	#include "PGMBth.h"
689	#include "PGMGstDefs.h"
690	#include "PGMGst.h"
691	#undef BTH_PGMPOOLKIND_PT_FOR_PT
692	#undef BTH_PGMPOOLKIND_ROOT
693	#undef PGM_BTH_NAME
694	#undef PGM_BTH_NAME_RC_STR
695	#undef PGM_BTH_NAME_R0_STR
696	#undef PGM_GST_TYPE
697	#undef PGM_GST_NAME
698	#undef PGM_GST_NAME_RC_STR
699	#undef PGM_GST_NAME_R0_STR
700
701	/* Guest - protected mode */
702	#define PGM_GST_TYPE PGM_TYPE_PROT
703	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
704	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PROT_STR(name)
705	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
706	#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_PROT(name)
707	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_32BIT_PROT_STR(name)
708	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_32BIT_PROT_STR(name)
709	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_PHYS
710	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_32BIT_PD_PHYS
711	#include "PGMBth.h"
712	#include "PGMGstDefs.h"
713	#include "PGMGst.h"
714	#undef BTH_PGMPOOLKIND_PT_FOR_PT
715	#undef BTH_PGMPOOLKIND_ROOT
716	#undef PGM_BTH_NAME
717	#undef PGM_BTH_NAME_RC_STR
718	#undef PGM_BTH_NAME_R0_STR
719	#undef PGM_GST_TYPE
720	#undef PGM_GST_NAME
721	#undef PGM_GST_NAME_RC_STR
722	#undef PGM_GST_NAME_R0_STR
723
724	/* Guest - 32-bit mode */
725	#define PGM_GST_TYPE PGM_TYPE_32BIT
726	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
727	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_32BIT_STR(name)
728	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
729	#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_32BIT(name)
730	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_32BIT_32BIT_STR(name)
731	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_32BIT_32BIT_STR(name)
732	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT
733	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB
734	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_32BIT_PD
735	#include "PGMBth.h"
736	#include "PGMGstDefs.h"
737	#include "PGMGst.h"
738	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
739	#undef BTH_PGMPOOLKIND_PT_FOR_PT
740	#undef BTH_PGMPOOLKIND_ROOT
741	#undef PGM_BTH_NAME
742	#undef PGM_BTH_NAME_RC_STR
743	#undef PGM_BTH_NAME_R0_STR
744	#undef PGM_GST_TYPE
745	#undef PGM_GST_NAME
746	#undef PGM_GST_NAME_RC_STR
747	#undef PGM_GST_NAME_R0_STR
748
749	#undef PGM_SHW_TYPE
750	#undef PGM_SHW_NAME
751	#undef PGM_SHW_NAME_RC_STR
752	#undef PGM_SHW_NAME_R0_STR
753
754
755	/*
756	* Shadow - PAE mode
757	*/
758	#define PGM_SHW_TYPE PGM_TYPE_PAE
759	#define PGM_SHW_NAME(name) PGM_SHW_NAME_PAE(name)
760	#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_PAE_STR(name)
761	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_PAE_STR(name)
762	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_REAL(name)
763	#include "PGMShw.h"
764
765	/* Guest - real mode */
766	#define PGM_GST_TYPE PGM_TYPE_REAL
767	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
768	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_REAL_STR(name)
769	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
770	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_REAL(name)
771	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_PAE_REAL_STR(name)
772	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_REAL_STR(name)
773	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
774	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT_PHYS
775	#include "PGMGstDefs.h"
776	#include "PGMBth.h"
777	#undef BTH_PGMPOOLKIND_PT_FOR_PT
778	#undef BTH_PGMPOOLKIND_ROOT
779	#undef PGM_BTH_NAME
780	#undef PGM_BTH_NAME_RC_STR
781	#undef PGM_BTH_NAME_R0_STR
782	#undef PGM_GST_TYPE
783	#undef PGM_GST_NAME
784	#undef PGM_GST_NAME_RC_STR
785	#undef PGM_GST_NAME_R0_STR
786
787	/* Guest - protected mode */
788	#define PGM_GST_TYPE PGM_TYPE_PROT
789	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
790	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PROT_STR(name)
791	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
792	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_PROT(name)
793	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_PAE_PROT_STR(name)
794	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_PROT_STR(name)
795	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
796	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT_PHYS
797	#include "PGMGstDefs.h"
798	#include "PGMBth.h"
799	#undef BTH_PGMPOOLKIND_PT_FOR_PT
800	#undef BTH_PGMPOOLKIND_ROOT
801	#undef PGM_BTH_NAME
802	#undef PGM_BTH_NAME_RC_STR
803	#undef PGM_BTH_NAME_R0_STR
804	#undef PGM_GST_TYPE
805	#undef PGM_GST_NAME
806	#undef PGM_GST_NAME_RC_STR
807	#undef PGM_GST_NAME_R0_STR
808
809	/* Guest - 32-bit mode */
810	#define PGM_GST_TYPE PGM_TYPE_32BIT
811	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
812	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_32BIT_STR(name)
813	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
814	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_32BIT(name)
815	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_PAE_32BIT_STR(name)
816	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_32BIT_STR(name)
817	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_32BIT_PT
818	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB
819	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT_FOR_32BIT
820	#include "PGMGstDefs.h"
821	#include "PGMBth.h"
822	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
823	#undef BTH_PGMPOOLKIND_PT_FOR_PT
824	#undef BTH_PGMPOOLKIND_ROOT
825	#undef PGM_BTH_NAME
826	#undef PGM_BTH_NAME_RC_STR
827	#undef PGM_BTH_NAME_R0_STR
828	#undef PGM_GST_TYPE
829	#undef PGM_GST_NAME
830	#undef PGM_GST_NAME_RC_STR
831	#undef PGM_GST_NAME_R0_STR
832
833	/* Guest - PAE mode */
834	#define PGM_GST_TYPE PGM_TYPE_PAE
835	#define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
836	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PAE_STR(name)
837	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PAE_STR(name)
838	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_PAE(name)
839	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_PAE_PAE_STR(name)
840	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_PAE_STR(name)
841	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
842	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
843	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT
844	#include "PGMBth.h"
845	#include "PGMGstDefs.h"
846	#include "PGMGst.h"
847	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
848	#undef BTH_PGMPOOLKIND_PT_FOR_PT
849	#undef BTH_PGMPOOLKIND_ROOT
850	#undef PGM_BTH_NAME
851	#undef PGM_BTH_NAME_RC_STR
852	#undef PGM_BTH_NAME_R0_STR
853	#undef PGM_GST_TYPE
854	#undef PGM_GST_NAME
855	#undef PGM_GST_NAME_RC_STR
856	#undef PGM_GST_NAME_R0_STR
857
858	#undef PGM_SHW_TYPE
859	#undef PGM_SHW_NAME
860	#undef PGM_SHW_NAME_RC_STR
861	#undef PGM_SHW_NAME_R0_STR
862
863
864	/*
865	* Shadow - AMD64 mode
866	*/
867	#define PGM_SHW_TYPE PGM_TYPE_AMD64
868	#define PGM_SHW_NAME(name) PGM_SHW_NAME_AMD64(name)
869	#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_AMD64_STR(name)
870	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_AMD64_STR(name)
871	#include "PGMShw.h"
872
873	#ifdef VBOX_WITH_64_BITS_GUESTS
874	/* Guest - AMD64 mode */
875	# define PGM_GST_TYPE PGM_TYPE_AMD64
876	# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
877	# define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_AMD64_STR(name)
878	# define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_AMD64_STR(name)
879	# define PGM_BTH_NAME(name) PGM_BTH_NAME_AMD64_AMD64(name)
880	# define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_AMD64_AMD64_STR(name)
881	# define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_AMD64_AMD64_STR(name)
882	# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
883	# define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
884	# define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_64BIT_PML4
885	# include "PGMBth.h"
886	# include "PGMGstDefs.h"
887	# include "PGMGst.h"
888	# undef BTH_PGMPOOLKIND_PT_FOR_BIG
889	# undef BTH_PGMPOOLKIND_PT_FOR_PT
890	# undef BTH_PGMPOOLKIND_ROOT
891	# undef PGM_BTH_NAME
892	# undef PGM_BTH_NAME_RC_STR
893	# undef PGM_BTH_NAME_R0_STR
894	# undef PGM_GST_TYPE
895	# undef PGM_GST_NAME
896	# undef PGM_GST_NAME_RC_STR
897	# undef PGM_GST_NAME_R0_STR
898	#endif /* VBOX_WITH_64_BITS_GUESTS */
899
900	#undef PGM_SHW_TYPE
901	#undef PGM_SHW_NAME
902	#undef PGM_SHW_NAME_RC_STR
903	#undef PGM_SHW_NAME_R0_STR
904
905
906	/*
907	* Shadow - Nested paging mode
908	*/
909	#define PGM_SHW_TYPE PGM_TYPE_NESTED
910	#define PGM_SHW_NAME(name) PGM_SHW_NAME_NESTED(name)
911	#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_NESTED_STR(name)
912	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_NESTED_STR(name)
913	#include "PGMShw.h"
914
915	/* Guest - real mode */
916	#define PGM_GST_TYPE PGM_TYPE_REAL
917	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
918	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_REAL_STR(name)
919	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
920	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_REAL(name)
921	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_REAL_STR(name)
922	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_REAL_STR(name)
923	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
924	#include "PGMGstDefs.h"
925	#include "PGMBth.h"
926	#undef BTH_PGMPOOLKIND_PT_FOR_PT
927	#undef PGM_BTH_NAME
928	#undef PGM_BTH_NAME_RC_STR
929	#undef PGM_BTH_NAME_R0_STR
930	#undef PGM_GST_TYPE
931	#undef PGM_GST_NAME
932	#undef PGM_GST_NAME_RC_STR
933	#undef PGM_GST_NAME_R0_STR
934
935	/* Guest - protected mode */
936	#define PGM_GST_TYPE PGM_TYPE_PROT
937	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
938	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PROT_STR(name)
939	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
940	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_PROT(name)
941	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_PROT_STR(name)
942	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_PROT_STR(name)
943	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
944	#include "PGMGstDefs.h"
945	#include "PGMBth.h"
946	#undef BTH_PGMPOOLKIND_PT_FOR_PT
947	#undef PGM_BTH_NAME
948	#undef PGM_BTH_NAME_RC_STR
949	#undef PGM_BTH_NAME_R0_STR
950	#undef PGM_GST_TYPE
951	#undef PGM_GST_NAME
952	#undef PGM_GST_NAME_RC_STR
953	#undef PGM_GST_NAME_R0_STR
954
955	/* Guest - 32-bit mode */
956	#define PGM_GST_TYPE PGM_TYPE_32BIT
957	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
958	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_32BIT_STR(name)
959	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
960	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_32BIT(name)
961	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_32BIT_STR(name)
962	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_32BIT_STR(name)
963	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_32BIT_PT
964	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB
965	#include "PGMGstDefs.h"
966	#include "PGMBth.h"
967	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
968	#undef BTH_PGMPOOLKIND_PT_FOR_PT
969	#undef PGM_BTH_NAME
970	#undef PGM_BTH_NAME_RC_STR
971	#undef PGM_BTH_NAME_R0_STR
972	#undef PGM_GST_TYPE
973	#undef PGM_GST_NAME
974	#undef PGM_GST_NAME_RC_STR
975	#undef PGM_GST_NAME_R0_STR
976
977	/* Guest - PAE mode */
978	#define PGM_GST_TYPE PGM_TYPE_PAE
979	#define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
980	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PAE_STR(name)
981	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PAE_STR(name)
982	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_PAE(name)
983	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_PAE_STR(name)
984	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_PAE_STR(name)
985	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
986	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
987	#include "PGMGstDefs.h"
988	#include "PGMBth.h"
989	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
990	#undef BTH_PGMPOOLKIND_PT_FOR_PT
991	#undef PGM_BTH_NAME
992	#undef PGM_BTH_NAME_RC_STR
993	#undef PGM_BTH_NAME_R0_STR
994	#undef PGM_GST_TYPE
995	#undef PGM_GST_NAME
996	#undef PGM_GST_NAME_RC_STR
997	#undef PGM_GST_NAME_R0_STR
998
999	#ifdef VBOX_WITH_64_BITS_GUESTS
1000	/* Guest - AMD64 mode */
1001	# define PGM_GST_TYPE PGM_TYPE_AMD64
1002	# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
1003	# define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_AMD64_STR(name)
1004	# define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_AMD64_STR(name)
1005	# define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_AMD64(name)
1006	# define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_AMD64_STR(name)
1007	# define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_AMD64_STR(name)
1008	# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
1009	# define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
1010	# include "PGMGstDefs.h"
1011	# include "PGMBth.h"
1012	# undef BTH_PGMPOOLKIND_PT_FOR_BIG
1013	# undef BTH_PGMPOOLKIND_PT_FOR_PT
1014	# undef PGM_BTH_NAME
1015	# undef PGM_BTH_NAME_RC_STR
1016	# undef PGM_BTH_NAME_R0_STR
1017	# undef PGM_GST_TYPE
1018	# undef PGM_GST_NAME
1019	# undef PGM_GST_NAME_RC_STR
1020	# undef PGM_GST_NAME_R0_STR
1021	#endif /* VBOX_WITH_64_BITS_GUESTS */
1022
1023	#undef PGM_SHW_TYPE
1024	#undef PGM_SHW_NAME
1025	#undef PGM_SHW_NAME_RC_STR
1026	#undef PGM_SHW_NAME_R0_STR
1027
1028
1029	/*
1030	* Shadow - EPT
1031	*/
1032	#define PGM_SHW_TYPE PGM_TYPE_EPT
1033	#define PGM_SHW_NAME(name) PGM_SHW_NAME_EPT(name)
1034	#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_EPT_STR(name)
1035	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_EPT_STR(name)
1036	#include "PGMShw.h"
1037
1038	/* Guest - real mode */
1039	#define PGM_GST_TYPE PGM_TYPE_REAL
1040	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
1041	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_REAL_STR(name)
1042	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
1043	#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_REAL(name)
1044	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_REAL_STR(name)
1045	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_REAL_STR(name)
1046	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
1047	#include "PGMGstDefs.h"
1048	#include "PGMBth.h"
1049	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1050	#undef PGM_BTH_NAME
1051	#undef PGM_BTH_NAME_RC_STR
1052	#undef PGM_BTH_NAME_R0_STR
1053	#undef PGM_GST_TYPE
1054	#undef PGM_GST_NAME
1055	#undef PGM_GST_NAME_RC_STR
1056	#undef PGM_GST_NAME_R0_STR
1057
1058	/* Guest - protected mode */
1059	#define PGM_GST_TYPE PGM_TYPE_PROT
1060	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
1061	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PROT_STR(name)
1062	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
1063	#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_PROT(name)
1064	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_PROT_STR(name)
1065	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_PROT_STR(name)
1066	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
1067	#include "PGMGstDefs.h"
1068	#include "PGMBth.h"
1069	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1070	#undef PGM_BTH_NAME
1071	#undef PGM_BTH_NAME_RC_STR
1072	#undef PGM_BTH_NAME_R0_STR
1073	#undef PGM_GST_TYPE
1074	#undef PGM_GST_NAME
1075	#undef PGM_GST_NAME_RC_STR
1076	#undef PGM_GST_NAME_R0_STR
1077
1078	/* Guest - 32-bit mode */
1079	#define PGM_GST_TYPE PGM_TYPE_32BIT
1080	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
1081	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_32BIT_STR(name)
1082	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
1083	#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_32BIT(name)
1084	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_32BIT_STR(name)
1085	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_32BIT_STR(name)
1086	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_32BIT_PT
1087	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB
1088	#include "PGMGstDefs.h"
1089	#include "PGMBth.h"
1090	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
1091	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1092	#undef PGM_BTH_NAME
1093	#undef PGM_BTH_NAME_RC_STR
1094	#undef PGM_BTH_NAME_R0_STR
1095	#undef PGM_GST_TYPE
1096	#undef PGM_GST_NAME
1097	#undef PGM_GST_NAME_RC_STR
1098	#undef PGM_GST_NAME_R0_STR
1099
1100	/* Guest - PAE mode */
1101	#define PGM_GST_TYPE PGM_TYPE_PAE
1102	#define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
1103	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PAE_STR(name)
1104	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PAE_STR(name)
1105	#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_PAE(name)
1106	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_PAE_STR(name)
1107	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_PAE_STR(name)
1108	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
1109	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
1110	#include "PGMGstDefs.h"
1111	#include "PGMBth.h"
1112	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
1113	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1114	#undef PGM_BTH_NAME
1115	#undef PGM_BTH_NAME_RC_STR
1116	#undef PGM_BTH_NAME_R0_STR
1117	#undef PGM_GST_TYPE
1118	#undef PGM_GST_NAME
1119	#undef PGM_GST_NAME_RC_STR
1120	#undef PGM_GST_NAME_R0_STR
1121
1122	#ifdef VBOX_WITH_64_BITS_GUESTS
1123	/* Guest - AMD64 mode */
1124	# define PGM_GST_TYPE PGM_TYPE_AMD64
1125	# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
1126	# define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_AMD64_STR(name)
1127	# define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_AMD64_STR(name)
1128	# define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_AMD64(name)
1129	# define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_AMD64_STR(name)
1130	# define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_AMD64_STR(name)
1131	# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
1132	# define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
1133	# include "PGMGstDefs.h"
1134	# include "PGMBth.h"
1135	# undef BTH_PGMPOOLKIND_PT_FOR_BIG
1136	# undef BTH_PGMPOOLKIND_PT_FOR_PT
1137	# undef PGM_BTH_NAME
1138	# undef PGM_BTH_NAME_RC_STR
1139	# undef PGM_BTH_NAME_R0_STR
1140	# undef PGM_GST_TYPE
1141	# undef PGM_GST_NAME
1142	# undef PGM_GST_NAME_RC_STR
1143	# undef PGM_GST_NAME_R0_STR
1144	#endif /* VBOX_WITH_64_BITS_GUESTS */
1145
1146	#undef PGM_SHW_TYPE
1147	#undef PGM_SHW_NAME
1148	#undef PGM_SHW_NAME_RC_STR
1149	#undef PGM_SHW_NAME_R0_STR
1150
1151
1152
1153	/**
1154	* Initiates the paging of VM.
1155	*
1156	* @returns VBox status code.
1157	* @param pVM Pointer to VM structure.
1158	*/
1159	VMMR3DECL(int) PGMR3Init(PVM pVM)
1160	{
1161	LogFlow(("PGMR3Init:\n"));
1162	PCFGMNODE pCfgPGM = CFGMR3GetChild(CFGMR3GetRoot(pVM), "/PGM");
1163	int rc;
1164
1165	/*
1166	* Assert alignment and sizes.
1167	*/
1168	AssertRelease(sizeof(pVM->pgm.s) <= sizeof(pVM->pgm.padding));
1169
1170	/*
1171	* Init the structure.
1172	*/
1173	pVM->pgm.s.offVM = RT_OFFSETOF(VM, pgm.s);
1174	pVM->pgm.s.offVCpu = RT_OFFSETOF(VMCPU, pgm.s);
1175	pVM->pgm.s.enmShadowMode = PGMMODE_INVALID;
1176	pVM->pgm.s.enmGuestMode = PGMMODE_INVALID;
1177	pVM->pgm.s.enmHostMode = SUPPAGINGMODE_INVALID;
1178	pVM->pgm.s.GCPhysCR3 = NIL_RTGCPHYS;
1179	pVM->pgm.s.fA20Enabled = true;
1180	pVM->pgm.s.GCPhys4MBPSEMask = RT_BIT_64(32) - 1; /* default; checked later */
1181	pVM->pgm.s.pGstPaePdptR3 = NULL;
1182	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
1183	pVM->pgm.s.pGstPaePdptR0 = NIL_RTR0PTR;
1184	#endif
1185	pVM->pgm.s.pGstPaePdptRC = NIL_RTRCPTR;
1186	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.apGstPaePDsR3); i++)
1187	{
1188	pVM->pgm.s.apGstPaePDsR3[i] = NULL;
1189	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
1190	pVM->pgm.s.apGstPaePDsR0[i] = NIL_RTR0PTR;
1191	#endif
1192	pVM->pgm.s.apGstPaePDsRC[i] = NIL_RTRCPTR;
1193	pVM->pgm.s.aGCPhysGstPaePDs[i] = NIL_RTGCPHYS;
1194	pVM->pgm.s.aGCPhysGstPaePDsMonitored[i] = NIL_RTGCPHYS;
1195	}
1196
1197	rc = CFGMR3QueryBoolDef(pCfgPGM, "RamPreAlloc", &pVM->pgm.s.fRamPreAlloc, false);
1198	AssertLogRelRCReturn(rc, rc);
1199
1200	#if HC_ARCH_BITS == 64
1201	rc = CFGMR3QueryU32Def(pCfgPGM, "MaxRing3Chunks", &pVM->pgm.s.ChunkR3Map.cMax, UINT32_MAX);
1202	#else
1203	rc = CFGMR3QueryU32Def(pCfgPGM, "MaxRing3Chunks", &pVM->pgm.s.ChunkR3Map.cMax, _1G / GMM_CHUNK_SIZE);
1204	#endif
1205	AssertLogRelRCReturn(rc, rc);
1206	for (uint32_t i = 0; i < RT_ELEMENTS(pVM->pgm.s.ChunkR3Map.Tlb.aEntries); i++)
1207	pVM->pgm.s.ChunkR3Map.Tlb.aEntries[i].idChunk = NIL_GMM_CHUNKID;
1208
1209	/*
1210	* Get the configured RAM size - to estimate saved state size.
1211	*/
1212	uint64_t cbRam;
1213	rc = CFGMR3QueryU64(CFGMR3GetRoot(pVM), "RamSize", &cbRam);
1214	if (rc == VERR_CFGM_VALUE_NOT_FOUND)
1215	cbRam = pVM->pgm.s.cbRamSize = 0;
1216	else if (RT_SUCCESS(rc))
1217	{
1218	if (cbRam < PAGE_SIZE)
1219	cbRam = 0;
1220	cbRam = RT_ALIGN_64(cbRam, PAGE_SIZE);
1221	pVM->pgm.s.cbRamSize = (RTUINT)cbRam;
1222	}
1223	else
1224	{
1225	AssertMsgFailed(("Configuration error: Failed to query integer \"RamSize\", rc=%Rrc.\n", rc));
1226	return rc;
1227	}
1228
1229	/*
1230	* Register callbacks, string formatters and the saved state data unit.
1231	*/
1232	#ifdef VBOX_STRICT
1233	VMR3AtStateRegister(pVM, pgmR3ResetNoMorePhysWritesFlag, NULL);
1234	#endif
1235	PGMRegisterStringFormatTypes();
1236
1237	rc = SSMR3RegisterInternal(pVM, "pgm", 1, PGM_SAVED_STATE_VERSION, (size_t)cbRam + sizeof(PGM),
1238	NULL, pgmR3Save, NULL,
1239	NULL, pgmR3Load, NULL);
1240	if (RT_FAILURE(rc))
1241	return rc;
1242
1243	/*
1244	* Initialize the PGM critical section and flush the phys TLBs
1245	*/
1246	rc = PDMR3CritSectInit(pVM, &pVM->pgm.s.CritSect, "PGM");
1247	AssertRCReturn(rc, rc);
1248
1249	PGMR3PhysChunkInvalidateTLB(pVM);
1250	PGMPhysInvalidatePageR3MapTLB(pVM);
1251	PGMPhysInvalidatePageR0MapTLB(pVM);
1252	PGMPhysInvalidatePageGCMapTLB(pVM);
1253
1254	#ifdef VBOX_WITH_NEW_PHYS_CODE
1255	/*
1256	* For the time being we sport a full set of handy pages in addition to the base
1257	* memory to simplify things.
1258	*/
1259	rc = MMR3ReserveHandyPages(pVM, RT_ELEMENTS(pVM->pgm.s.aHandyPages));
1260	AssertRCReturn(rc, rc);
1261	#endif
1262
1263	/*
1264	* Trees
1265	*/
1266	rc = MMHyperAlloc(pVM, sizeof(PGMTREES), 0, MM_TAG_PGM, (void **)&pVM->pgm.s.pTreesR3);
1267	if (RT_SUCCESS(rc))
1268	{
1269	pVM->pgm.s.pTreesR0 = MMHyperR3ToR0(pVM, pVM->pgm.s.pTreesR3);
1270	pVM->pgm.s.pTreesRC = MMHyperR3ToRC(pVM, pVM->pgm.s.pTreesR3);
1271
1272	/*
1273	* Alocate the zero page.
1274	*/
1275	rc = MMHyperAlloc(pVM, PAGE_SIZE, PAGE_SIZE, MM_TAG_PGM, &pVM->pgm.s.pvZeroPgR3);
1276	}
1277	if (RT_SUCCESS(rc))
1278	{
1279	pVM->pgm.s.pvZeroPgGC = MMHyperR3ToRC(pVM, pVM->pgm.s.pvZeroPgR3);
1280	pVM->pgm.s.pvZeroPgR0 = MMHyperR3ToR0(pVM, pVM->pgm.s.pvZeroPgR3);
1281	AssertRelease(pVM->pgm.s.pvZeroPgR0 != NIL_RTHCPHYS);
1282	pVM->pgm.s.HCPhysZeroPg = MMR3HyperHCVirt2HCPhys(pVM, pVM->pgm.s.pvZeroPgR3);
1283	AssertRelease(pVM->pgm.s.HCPhysZeroPg != NIL_RTHCPHYS);
1284
1285	/*
1286	* Init the paging.
1287	*/
1288	rc = pgmR3InitPaging(pVM);
1289	}
1290	if (RT_SUCCESS(rc))
1291	{
1292	/*
1293	* Init the page pool.
1294	*/
1295	rc = pgmR3PoolInit(pVM);
1296	}
1297	if (RT_SUCCESS(rc))
1298	rc = PGMR3ChangeMode(pVM, PGMMODE_REAL);
1299
1300	if (RT_SUCCESS(rc))
1301	{
1302	/*
1303	* Info & statistics
1304	*/
1305	DBGFR3InfoRegisterInternal(pVM, "mode",
1306	"Shows the current paging mode. "
1307	"Recognizes 'all', 'guest', 'shadow' and 'host' as arguments, defaulting to 'all' if nothing's given.",
1308	pgmR3InfoMode);
1309	DBGFR3InfoRegisterInternal(pVM, "pgmcr3",
1310	"Dumps all the entries in the top level paging table. No arguments.",
1311	pgmR3InfoCr3);
1312	DBGFR3InfoRegisterInternal(pVM, "phys",
1313	"Dumps all the physical address ranges. No arguments.",
1314	pgmR3PhysInfo);
1315	DBGFR3InfoRegisterInternal(pVM, "handlers",
1316	"Dumps physical, virtual and hyper virtual handlers. "
1317	"Pass 'phys', 'virt', 'hyper' as argument if only one kind is wanted."
1318	"Add 'nost' if the statistics are unwanted, use together with 'all' or explicit selection.",
1319	pgmR3InfoHandlers);
1320	DBGFR3InfoRegisterInternal(pVM, "mappings",
1321	"Dumps guest mappings.",
1322	pgmR3MapInfo);
1323
1324	STAM_REL_REG(pVM, &pVM->pgm.s.cGuestModeChanges, STAMTYPE_COUNTER, "/PGM/cGuestModeChanges", STAMUNIT_OCCURENCES, "Number of guest mode changes.");
1325	STAM_REL_REG(pVM, &pVM->pgm.s.cRelocations, STAMTYPE_COUNTER, "/PGM/cRelocations", STAMUNIT_OCCURENCES, "Number of hypervisor relocations.");
1326	#ifdef VBOX_WITH_STATISTICS
1327	pgmR3InitStats(pVM);
1328	#endif
1329	#ifdef VBOX_WITH_DEBUGGER
1330	/*
1331	* Debugger commands.
1332	*/
1333	static bool fRegisteredCmds = false;
1334	if (!fRegisteredCmds)
1335	{
1336	int rc = DBGCRegisterCommands(&g_aCmds[0], RT_ELEMENTS(g_aCmds));
1337	if (RT_SUCCESS(rc))
1338	fRegisteredCmds = true;
1339	}
1340	#endif
1341	return VINF_SUCCESS;
1342	}
1343
1344	/* Almost no cleanup necessary, MM frees all memory. */
1345	PDMR3CritSectDelete(&pVM->pgm.s.CritSect);
1346
1347	return rc;
1348	}
1349
1350
1351	/**
1352	* Initializes the per-VCPU PGM.
1353	*
1354	* @returns VBox status code.
1355	* @param pVM The VM to operate on.
1356	*/
1357	VMMR3DECL(int) PGMR3InitCPU(PVM pVM)
1358	{
1359	LogFlow(("PGMR3InitCPU\n"));
1360	return VINF_SUCCESS;
1361	}
1362
1363
1364	/**
1365	* Init paging.
1366	*
1367	* Since we need to check what mode the host is operating in before we can choose
1368	* the right paging functions for the host we have to delay this until R0 has
1369	* been initialized.
1370	*
1371	* @returns VBox status code.
1372	* @param pVM VM handle.
1373	*/
1374	static int pgmR3InitPaging(PVM pVM)
1375	{
1376	/*
1377	* Force a recalculation of modes and switcher so everyone gets notified.
1378	*/
1379	pVM->pgm.s.enmShadowMode = PGMMODE_INVALID;
1380	pVM->pgm.s.enmGuestMode = PGMMODE_INVALID;
1381	pVM->pgm.s.enmHostMode = SUPPAGINGMODE_INVALID;
1382
1383	/*
1384	* Allocate static mapping space for whatever the cr3 register
1385	* points to and in the case of PAE mode to the 4 PDs.
1386	*/
1387	int rc = MMR3HyperReserve(pVM, PAGE_SIZE * 5, "CR3 mapping", &pVM->pgm.s.GCPtrCR3Mapping);
1388	if (RT_FAILURE(rc))
1389	{
1390	AssertMsgFailed(("Failed to reserve two pages for cr mapping in HMA, rc=%Rrc\n", rc));
1391	return rc;
1392	}
1393	MMR3HyperReserve(pVM, PAGE_SIZE, "fence", NULL);
1394
1395	/*
1396	* Allocate pages for the three possible intermediate contexts
1397	* (AMD64, PAE and plain 32-Bit). We maintain all three contexts
1398	* for the sake of simplicity. The AMD64 uses the PAE for the
1399	* lower levels, making the total number of pages 11 (3 + 7 + 1).
1400	*
1401	* We assume that two page tables will be enought for the core code
1402	* mappings (HC virtual and identity).
1403	*/
1404	pVM->pgm.s.pInterPD = (PX86PD)MMR3PageAllocLow(pVM);
1405	pVM->pgm.s.apInterPTs[0] = (PX86PT)MMR3PageAllocLow(pVM);
1406	pVM->pgm.s.apInterPTs[1] = (PX86PT)MMR3PageAllocLow(pVM);
1407	pVM->pgm.s.apInterPaePTs[0] = (PX86PTPAE)MMR3PageAlloc(pVM);
1408	pVM->pgm.s.apInterPaePTs[1] = (PX86PTPAE)MMR3PageAlloc(pVM);
1409	pVM->pgm.s.apInterPaePDs[0] = (PX86PDPAE)MMR3PageAlloc(pVM);
1410	pVM->pgm.s.apInterPaePDs[1] = (PX86PDPAE)MMR3PageAlloc(pVM);
1411	pVM->pgm.s.apInterPaePDs[2] = (PX86PDPAE)MMR3PageAlloc(pVM);
1412	pVM->pgm.s.apInterPaePDs[3] = (PX86PDPAE)MMR3PageAlloc(pVM);
1413	pVM->pgm.s.pInterPaePDPT = (PX86PDPT)MMR3PageAllocLow(pVM);
1414	pVM->pgm.s.pInterPaePDPT64 = (PX86PDPT)MMR3PageAllocLow(pVM);
1415	pVM->pgm.s.pInterPaePML4 = (PX86PML4)MMR3PageAllocLow(pVM);
1416	if ( !pVM->pgm.s.pInterPD
1417	\|\| !pVM->pgm.s.apInterPTs[0]
1418	\|\| !pVM->pgm.s.apInterPTs[1]
1419	\|\| !pVM->pgm.s.apInterPaePTs[0]
1420	\|\| !pVM->pgm.s.apInterPaePTs[1]
1421	\|\| !pVM->pgm.s.apInterPaePDs[0]
1422	\|\| !pVM->pgm.s.apInterPaePDs[1]
1423	\|\| !pVM->pgm.s.apInterPaePDs[2]
1424	\|\| !pVM->pgm.s.apInterPaePDs[3]
1425	\|\| !pVM->pgm.s.pInterPaePDPT
1426	\|\| !pVM->pgm.s.pInterPaePDPT64
1427	\|\| !pVM->pgm.s.pInterPaePML4)
1428	{
1429	AssertMsgFailed(("Failed to allocate pages for the intermediate context!\n"));
1430	return VERR_NO_PAGE_MEMORY;
1431	}
1432
1433	pVM->pgm.s.HCPhysInterPD = MMPage2Phys(pVM, pVM->pgm.s.pInterPD);
1434	AssertRelease(pVM->pgm.s.HCPhysInterPD != NIL_RTHCPHYS && !(pVM->pgm.s.HCPhysInterPD & PAGE_OFFSET_MASK));
1435	pVM->pgm.s.HCPhysInterPaePDPT = MMPage2Phys(pVM, pVM->pgm.s.pInterPaePDPT);
1436	AssertRelease(pVM->pgm.s.HCPhysInterPaePDPT != NIL_RTHCPHYS && !(pVM->pgm.s.HCPhysInterPaePDPT & PAGE_OFFSET_MASK));
1437	pVM->pgm.s.HCPhysInterPaePML4 = MMPage2Phys(pVM, pVM->pgm.s.pInterPaePML4);
1438	AssertRelease(pVM->pgm.s.HCPhysInterPaePML4 != NIL_RTHCPHYS && !(pVM->pgm.s.HCPhysInterPaePML4 & PAGE_OFFSET_MASK) && pVM->pgm.s.HCPhysInterPaePML4 < 0xffffffff);
1439
1440	/*
1441	* Initialize the pages, setting up the PML4 and PDPT for repetitive 4GB action.
1442	*/
1443	ASMMemZeroPage(pVM->pgm.s.pInterPD);
1444	ASMMemZeroPage(pVM->pgm.s.apInterPTs[0]);
1445	ASMMemZeroPage(pVM->pgm.s.apInterPTs[1]);
1446
1447	ASMMemZeroPage(pVM->pgm.s.apInterPaePTs[0]);
1448	ASMMemZeroPage(pVM->pgm.s.apInterPaePTs[1]);
1449
1450	ASMMemZeroPage(pVM->pgm.s.pInterPaePDPT);
1451	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.apInterPaePDs); i++)
1452	{
1453	ASMMemZeroPage(pVM->pgm.s.apInterPaePDs[i]);
1454	pVM->pgm.s.pInterPaePDPT->a[i].u = X86_PDPE_P \| PGM_PLXFLAGS_PERMANENT
1455	\| MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[i]);
1456	}
1457
1458	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.pInterPaePDPT64->a); i++)
1459	{
1460	const unsigned iPD = i % RT_ELEMENTS(pVM->pgm.s.apInterPaePDs);
1461	pVM->pgm.s.pInterPaePDPT64->a[i].u = X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_A \| PGM_PLXFLAGS_PERMANENT
1462	\| MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[iPD]);
1463	}
1464
1465	RTHCPHYS HCPhysInterPaePDPT64 = MMPage2Phys(pVM, pVM->pgm.s.pInterPaePDPT64);
1466	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.pInterPaePML4->a); i++)
1467	pVM->pgm.s.pInterPaePML4->a[i].u = X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_A \| PGM_PLXFLAGS_PERMANENT
1468	\| HCPhysInterPaePDPT64;
1469
1470	/*
1471	* Initialize paging workers and mode from current host mode
1472	* and the guest running in real mode.
1473	*/
1474	pVM->pgm.s.enmHostMode = SUPGetPagingMode();
1475	switch (pVM->pgm.s.enmHostMode)
1476	{
1477	case SUPPAGINGMODE_32_BIT:
1478	case SUPPAGINGMODE_32_BIT_GLOBAL:
1479	case SUPPAGINGMODE_PAE:
1480	case SUPPAGINGMODE_PAE_GLOBAL:
1481	case SUPPAGINGMODE_PAE_NX:
1482	case SUPPAGINGMODE_PAE_GLOBAL_NX:
1483	break;
1484
1485	case SUPPAGINGMODE_AMD64:
1486	case SUPPAGINGMODE_AMD64_GLOBAL:
1487	case SUPPAGINGMODE_AMD64_NX:
1488	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
1489	#ifndef VBOX_WITH_HYBRID_32BIT_KERNEL
1490	if (ARCH_BITS != 64)
1491	{
1492	AssertMsgFailed(("Host mode %d (64-bit) is not supported by non-64bit builds\n", pVM->pgm.s.enmHostMode));
1493	LogRel(("Host mode %d (64-bit) is not supported by non-64bit builds\n", pVM->pgm.s.enmHostMode));
1494	return VERR_PGM_UNSUPPORTED_HOST_PAGING_MODE;
1495	}
1496	#endif
1497	break;
1498	default:
1499	AssertMsgFailed(("Host mode %d is not supported\n", pVM->pgm.s.enmHostMode));
1500	return VERR_PGM_UNSUPPORTED_HOST_PAGING_MODE;
1501	}
1502	rc = pgmR3ModeDataInit(pVM, false /* don't resolve GC and R0 syms yet */);
1503	if (RT_SUCCESS(rc))
1504	{
1505	LogFlow(("pgmR3InitPaging: returns successfully\n"));
1506	#if HC_ARCH_BITS == 64
1507	LogRel(("Debug: HCPhysInterPD=%RHp HCPhysInterPaePDPT=%RHp HCPhysInterPaePML4=%RHp\n",
1508	pVM->pgm.s.HCPhysInterPD, pVM->pgm.s.HCPhysInterPaePDPT, pVM->pgm.s.HCPhysInterPaePML4));
1509	LogRel(("Debug: apInterPTs={%RHp,%RHp} apInterPaePTs={%RHp,%RHp} apInterPaePDs={%RHp,%RHp,%RHp,%RHp} pInterPaePDPT64=%RHp\n",
1510	MMPage2Phys(pVM, pVM->pgm.s.apInterPTs[0]), MMPage2Phys(pVM, pVM->pgm.s.apInterPTs[1]),
1511	MMPage2Phys(pVM, pVM->pgm.s.apInterPaePTs[0]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePTs[1]),
1512	MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[0]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[1]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[2]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[3]),
1513	MMPage2Phys(pVM, pVM->pgm.s.pInterPaePDPT64)));
1514	#endif
1515
1516	return VINF_SUCCESS;
1517	}
1518
1519	LogFlow(("pgmR3InitPaging: returns %Rrc\n", rc));
1520	return rc;
1521	}
1522
1523
1524	#ifdef VBOX_WITH_STATISTICS
1525	/**
1526	* Init statistics
1527	*/
1528	static void pgmR3InitStats(PVM pVM)
1529	{
1530	PPGM pPGM = &pVM->pgm.s;
1531	unsigned i;
1532
1533	/*
1534	* Note! The layout of this function matches the member layout exactly!
1535	*/
1536
1537	/* Common - misc variables */
1538	STAM_REG(pVM, &pPGM->cAllPages, STAMTYPE_U32, "/PGM/Page/cAllPages", STAMUNIT_OCCURENCES, "The total number of pages.");
1539	STAM_REG(pVM, &pPGM->cPrivatePages, STAMTYPE_U32, "/PGM/Page/cPrivatePages", STAMUNIT_OCCURENCES, "The number of private pages.");
1540	STAM_REG(pVM, &pPGM->cSharedPages, STAMTYPE_U32, "/PGM/Page/cSharedPages", STAMUNIT_OCCURENCES, "The number of shared pages.");
1541	STAM_REG(pVM, &pPGM->cZeroPages, STAMTYPE_U32, "/PGM/Page/cZeroPages", STAMUNIT_OCCURENCES, "The number of zero backed pages.");
1542	STAM_REG(pVM, &pPGM->cHandyPages, STAMTYPE_U32, "/PGM/Page/cHandyPages", STAMUNIT_OCCURENCES, "The number of handy pages (not included in cAllPages).");
1543	STAM_REG(pVM, &pPGM->ChunkR3Map.c, STAMTYPE_U32, "/PGM/ChunkR3Map/c", STAMUNIT_OCCURENCES, "Number of mapped chunks.");
1544	STAM_REG(pVM, &pPGM->ChunkR3Map.cMax, STAMTYPE_U32, "/PGM/ChunkR3Map/cMax", STAMUNIT_OCCURENCES, "Maximum number of mapped chunks.");
1545
1546	/* Common - stats */
1547	#ifdef PGMPOOL_WITH_GCPHYS_TRACKING
1548	STAM_REG(pVM, &pPGM->StatTrackVirgin, STAMTYPE_COUNTER, "/PGM/Track/Virgin", STAMUNIT_OCCURENCES, "The number of first time shadowings");
1549	STAM_REG(pVM, &pPGM->StatTrackAliased, STAMTYPE_COUNTER, "/PGM/Track/Aliased", STAMUNIT_OCCURENCES, "The number of times switching to cRef2, i.e. the page is being shadowed by two PTs.");
1550	STAM_REG(pVM, &pPGM->StatTrackAliasedMany, STAMTYPE_COUNTER, "/PGM/Track/AliasedMany", STAMUNIT_OCCURENCES, "The number of times we're tracking using cRef2.");
1551	STAM_REG(pVM, &pPGM->StatTrackAliasedLots, STAMTYPE_COUNTER, "/PGM/Track/AliasedLots", STAMUNIT_OCCURENCES, "The number of times we're hitting pages which has overflowed cRef2");
1552	STAM_REG(pVM, &pPGM->StatTrackOverflows, STAMTYPE_COUNTER, "/PGM/Track/Overflows", STAMUNIT_OCCURENCES, "The number of times the extent list grows to long.");
1553	STAM_REG(pVM, &pPGM->StatTrackDeref, STAMTYPE_PROFILE, "/PGM/Track/Deref", STAMUNIT_OCCURENCES, "Profiling of SyncPageWorkerTrackDeref (expensive).");
1554	#endif
1555	for (i = 0; i < RT_ELEMENTS(pPGM->StatSyncPtPD); i++)
1556	STAMR3RegisterF(pVM, &pPGM->StatSyncPtPD[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
1557	"The number of SyncPT per PD n.", "/PGM/PDSyncPT/%04X", i);
1558	for (i = 0; i < RT_ELEMENTS(pPGM->StatSyncPagePD); i++)
1559	STAMR3RegisterF(pVM, &pPGM->StatSyncPagePD[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
1560	"The number of SyncPage per PD n.", "/PGM/PDSyncPage/%04X", i);
1561
1562	/* R3 only: */
1563	STAM_REG(pVM, &pPGM->StatR3DetectedConflicts, STAMTYPE_COUNTER, "/PGM/R3/DetectedConflicts", STAMUNIT_OCCURENCES, "The number of times PGMR3CheckMappingConflicts() detected a conflict.");
1564	STAM_REG(pVM, &pPGM->StatR3ResolveConflict, STAMTYPE_PROFILE, "/PGM/R3/ResolveConflict", STAMUNIT_TICKS_PER_CALL, "pgmR3SyncPTResolveConflict() profiling (includes the entire relocation).");
1565	STAM_REG(pVM, &pPGM->StatR3GuestPDWrite, STAMTYPE_COUNTER, "/PGM/R3/PDWrite", STAMUNIT_OCCURENCES, "The total number of times pgmHCGuestPDWriteHandler() was called.");
1566	STAM_REG(pVM, &pPGM->StatR3GuestPDWriteConflict, STAMTYPE_COUNTER, "/PGM/R3/PDWriteConflict", STAMUNIT_OCCURENCES, "The number of times pgmHCGuestPDWriteHandler() detected a conflict.");
1567	#ifndef VBOX_WITH_NEW_PHYS_CODE
1568	STAM_REG(pVM, &pPGM->StatR3DynRamTotal, STAMTYPE_COUNTER, "/PGM/DynAlloc/TotalAlloc", STAMUNIT_MEGABYTES, "Allocated MBs of guest ram.");
1569	STAM_REG(pVM, &pPGM->StatR3DynRamGrow, STAMTYPE_COUNTER, "/PGM/DynAlloc/Grow", STAMUNIT_OCCURENCES, "Nr of pgmr3PhysGrowRange calls.");
1570	#endif
1571
1572	/* R0 only: */
1573	STAM_REG(pVM, &pPGM->StatR0DynMapMigrateInvlPg, STAMTYPE_COUNTER, "/PGM/R0/DynMapMigrateInvlPg", STAMUNIT_OCCURENCES, "invlpg count in PGMDynMapMigrateAutoSet.");
1574	STAM_REG(pVM, &pPGM->StatR0DynMapGCPageInl, STAMTYPE_PROFILE, "/PGM/R0/DynMapPageGCPageInl", STAMUNIT_TICKS_PER_CALL, "Calls to pgmR0DynMapGCPageInlined.");
1575	STAM_REG(pVM, &pPGM->StatR0DynMapGCPageInlHits, STAMTYPE_COUNTER, "/PGM/R0/DynMapPageGCPageInl/Hits", STAMUNIT_OCCURENCES, "Hash table lookup hits.");
1576	STAM_REG(pVM, &pPGM->StatR0DynMapGCPageInlMisses, STAMTYPE_COUNTER, "/PGM/R0/DynMapPageGCPageInl/Misses", STAMUNIT_OCCURENCES, "Misses that falls back to code common with PGMDynMapHCPage.");
1577	STAM_REG(pVM, &pPGM->StatR0DynMapGCPageInlRamHits, STAMTYPE_COUNTER, "/PGM/R0/DynMapPageGCPageInl/RamHits", STAMUNIT_OCCURENCES, "1st ram range hits.");
1578	STAM_REG(pVM, &pPGM->StatR0DynMapGCPageInlRamMisses, STAMTYPE_COUNTER, "/PGM/R0/DynMapPageGCPageInl/RamMisses", STAMUNIT_OCCURENCES, "1st ram range misses, takes slow path.");
1579	STAM_REG(pVM, &pPGM->StatR0DynMapHCPageInl, STAMTYPE_PROFILE, "/PGM/R0/DynMapPageHCPageInl", STAMUNIT_TICKS_PER_CALL, "Calls to pgmR0DynMapHCPageInlined.");
1580	STAM_REG(pVM, &pPGM->StatR0DynMapHCPageInlHits, STAMTYPE_COUNTER, "/PGM/R0/DynMapPageHCPageInl/Hits", STAMUNIT_OCCURENCES, "Hash table lookup hits.");
1581	STAM_REG(pVM, &pPGM->StatR0DynMapHCPageInlMisses, STAMTYPE_COUNTER, "/PGM/R0/DynMapPageHCPageInl/Misses", STAMUNIT_OCCURENCES, "Misses that falls back to code common with PGMDynMapHCPage.");
1582	STAM_REG(pVM, &pPGM->StatR0DynMapPage, STAMTYPE_COUNTER, "/PGM/R0/DynMapPage", STAMUNIT_OCCURENCES, "Calls to pgmR0DynMapPage");
1583	STAM_REG(pVM, &pPGM->StatR0DynMapSetOptimize, STAMTYPE_COUNTER, "/PGM/R0/DynMapPage/SetOptimize", STAMUNIT_OCCURENCES, "Calls to pgmDynMapOptimizeAutoSet.");
1584	STAM_REG(pVM, &pPGM->StatR0DynMapSetSearchFlushes, STAMTYPE_COUNTER, "/PGM/R0/DynMapPage/SetSearchFlushes",STAMUNIT_OCCURENCES, "Set search restorting to subset flushes.");
1585	STAM_REG(pVM, &pPGM->StatR0DynMapSetSearchHits, STAMTYPE_COUNTER, "/PGM/R0/DynMapPage/SetSearchHits", STAMUNIT_OCCURENCES, "Set search hits.");
1586	STAM_REG(pVM, &pPGM->StatR0DynMapSetSearchMisses, STAMTYPE_COUNTER, "/PGM/R0/DynMapPage/SetSearchMisses", STAMUNIT_OCCURENCES, "Set search misses.");
1587	STAM_REG(pVM, &pPGM->StatR0DynMapHCPage, STAMTYPE_PROFILE, "/PGM/R0/DynMapPage/HCPage", STAMUNIT_TICKS_PER_CALL, "Calls to PGMDynMapHCPage (ring-0).");
1588	STAM_REG(pVM, &pPGM->StatR0DynMapPageHits0, STAMTYPE_COUNTER, "/PGM/R0/DynMapPage/Hits0", STAMUNIT_OCCURENCES, "Hits at iPage+0");
1589	STAM_REG(pVM, &pPGM->StatR0DynMapPageHits1, STAMTYPE_COUNTER, "/PGM/R0/DynMapPage/Hits1", STAMUNIT_OCCURENCES, "Hits at iPage+1");
1590	STAM_REG(pVM, &pPGM->StatR0DynMapPageHits2, STAMTYPE_COUNTER, "/PGM/R0/DynMapPage/Hits2", STAMUNIT_OCCURENCES, "Hits at iPage+2");
1591	STAM_REG(pVM, &pPGM->StatR0DynMapPageInvlPg, STAMTYPE_COUNTER, "/PGM/R0/DynMapPage/InvlPg", STAMUNIT_OCCURENCES, "invlpg count in pgmR0DynMapPageSlow.");
1592	STAM_REG(pVM, &pPGM->StatR0DynMapPageSlow, STAMTYPE_COUNTER, "/PGM/R0/DynMapPage/Slow", STAMUNIT_OCCURENCES, "Calls to pgmR0DynMapPageSlow - subtract this from pgmR0DynMapPage to get 1st level hits.");
1593	STAM_REG(pVM, &pPGM->StatR0DynMapPageSlowLoopHits, STAMTYPE_COUNTER, "/PGM/R0/DynMapPage/SlowLoopHits" , STAMUNIT_OCCURENCES, "Hits in the loop path.");
1594	STAM_REG(pVM, &pPGM->StatR0DynMapPageSlowLoopMisses, STAMTYPE_COUNTER, "/PGM/R0/DynMapPage/SlowLoopMisses", STAMUNIT_OCCURENCES, "Misses in the loop path. NonLoopMisses = Slow - SlowLoopHit - SlowLoopMisses");
1595	//STAM_REG(pVM, &pPGM->StatR0DynMapPageSlowLostHits, STAMTYPE_COUNTER, "/PGM/R0/DynMapPage/SlowLostHits", STAMUNIT_OCCURENCES, "Lost hits.");
1596	STAM_REG(pVM, &pPGM->StatR0DynMapSubsets, STAMTYPE_COUNTER, "/PGM/R0/Subsets", STAMUNIT_OCCURENCES, "Times PGMDynMapPushAutoSubset was called.");
1597	STAM_REG(pVM, &pPGM->StatR0DynMapPopFlushes, STAMTYPE_COUNTER, "/PGM/R0/SubsetPopFlushes", STAMUNIT_OCCURENCES, "Times PGMDynMapPopAutoSubset flushes the subset.");
1598	STAM_REG(pVM, &pPGM->aStatR0DynMapSetSize[0], STAMTYPE_COUNTER, "/PGM/R0/SetSize000..09", STAMUNIT_OCCURENCES, "00-09% filled");
1599	STAM_REG(pVM, &pPGM->aStatR0DynMapSetSize[1], STAMTYPE_COUNTER, "/PGM/R0/SetSize010..19", STAMUNIT_OCCURENCES, "10-19% filled");
1600	STAM_REG(pVM, &pPGM->aStatR0DynMapSetSize[2], STAMTYPE_COUNTER, "/PGM/R0/SetSize020..29", STAMUNIT_OCCURENCES, "20-29% filled");
1601	STAM_REG(pVM, &pPGM->aStatR0DynMapSetSize[3], STAMTYPE_COUNTER, "/PGM/R0/SetSize030..39", STAMUNIT_OCCURENCES, "30-39% filled");
1602	STAM_REG(pVM, &pPGM->aStatR0DynMapSetSize[4], STAMTYPE_COUNTER, "/PGM/R0/SetSize040..49", STAMUNIT_OCCURENCES, "40-49% filled");
1603	STAM_REG(pVM, &pPGM->aStatR0DynMapSetSize[5], STAMTYPE_COUNTER, "/PGM/R0/SetSize050..59", STAMUNIT_OCCURENCES, "50-59% filled");
1604	STAM_REG(pVM, &pPGM->aStatR0DynMapSetSize[6], STAMTYPE_COUNTER, "/PGM/R0/SetSize060..69", STAMUNIT_OCCURENCES, "60-69% filled");
1605	STAM_REG(pVM, &pPGM->aStatR0DynMapSetSize[7], STAMTYPE_COUNTER, "/PGM/R0/SetSize070..79", STAMUNIT_OCCURENCES, "70-79% filled");
1606	STAM_REG(pVM, &pPGM->aStatR0DynMapSetSize[8], STAMTYPE_COUNTER, "/PGM/R0/SetSize080..89", STAMUNIT_OCCURENCES, "80-89% filled");
1607	STAM_REG(pVM, &pPGM->aStatR0DynMapSetSize[9], STAMTYPE_COUNTER, "/PGM/R0/SetSize090..99", STAMUNIT_OCCURENCES, "90-99% filled");
1608	STAM_REG(pVM, &pPGM->aStatR0DynMapSetSize[10], STAMTYPE_COUNTER, "/PGM/R0/SetSize100", STAMUNIT_OCCURENCES, "100% filled");
1609
1610	/* GC only: */
1611	STAM_REG(pVM, &pPGM->StatRCDynMapCacheHits, STAMTYPE_COUNTER, "/PGM/RC/DynMapCache/Hits" , STAMUNIT_OCCURENCES, "Number of dynamic page mapping cache hits.");
1612	STAM_REG(pVM, &pPGM->StatRCDynMapCacheMisses, STAMTYPE_COUNTER, "/PGM/RC/DynMapCache/Misses" , STAMUNIT_OCCURENCES, "Number of dynamic page mapping cache misses.");
1613	STAM_REG(pVM, &pPGM->StatRCInvlPgConflict, STAMTYPE_COUNTER, "/PGM/RC/InvlPgConflict", STAMUNIT_OCCURENCES, "Number of times PGMInvalidatePage() detected a mapping conflict.");
1614	STAM_REG(pVM, &pPGM->StatRCInvlPgSyncMonCR3, STAMTYPE_COUNTER, "/PGM/RC/InvlPgSyncMonitorCR3", STAMUNIT_OCCURENCES, "Number of times PGMInvalidatePage() ran into PGM_SYNC_MONITOR_CR3.");
1615
1616	/* RZ only: */
1617	STAM_REG(pVM, &pPGM->StatRZTrap0e, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMTrap0eHandler() body.");
1618	STAM_REG(pVM, &pPGM->StatRZTrap0eTimeCheckPageFault, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time/CheckPageFault", STAMUNIT_TICKS_PER_CALL, "Profiling of checking for dirty/access emulation faults.");
1619	STAM_REG(pVM, &pPGM->StatRZTrap0eTimeSyncPT, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time/SyncPT", STAMUNIT_TICKS_PER_CALL, "Profiling of lazy page table syncing.");
1620	STAM_REG(pVM, &pPGM->StatRZTrap0eTimeMapping, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time/Mapping", STAMUNIT_TICKS_PER_CALL, "Profiling of checking virtual mappings.");
1621	STAM_REG(pVM, &pPGM->StatRZTrap0eTimeOutOfSync, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time/OutOfSync", STAMUNIT_TICKS_PER_CALL, "Profiling of out of sync page handling.");
1622	STAM_REG(pVM, &pPGM->StatRZTrap0eTimeHandlers, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time/Handlers", STAMUNIT_TICKS_PER_CALL, "Profiling of checking handlers.");
1623	STAM_REG(pVM, &pPGM->StatRZTrap0eTime2CSAM, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time2/CSAM", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is CSAM.");
1624	STAM_REG(pVM, &pPGM->StatRZTrap0eTime2DirtyAndAccessed, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time2/DirtyAndAccessedBits", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is dirty and/or accessed bit emulation.");
1625	STAM_REG(pVM, &pPGM->StatRZTrap0eTime2GuestTrap, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time2/GuestTrap", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is a guest trap.");
1626	STAM_REG(pVM, &pPGM->StatRZTrap0eTime2HndPhys, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time2/HandlerPhysical", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is a physical handler.");
1627	STAM_REG(pVM, &pPGM->StatRZTrap0eTime2HndVirt, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time2/HandlerVirtual", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is a virtual handler.");
1628	STAM_REG(pVM, &pPGM->StatRZTrap0eTime2HndUnhandled, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time2/HandlerUnhandled", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is access outside the monitored areas of a monitored page.");
1629	STAM_REG(pVM, &pPGM->StatRZTrap0eTime2Misc, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time2/Misc", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is not known.");
1630	STAM_REG(pVM, &pPGM->StatRZTrap0eTime2OutOfSync, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time2/OutOfSync", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is an out-of-sync page.");
1631	STAM_REG(pVM, &pPGM->StatRZTrap0eTime2OutOfSyncHndPhys, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time2/OutOfSyncHndPhys", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is an out-of-sync physical handler page.");
1632	STAM_REG(pVM, &pPGM->StatRZTrap0eTime2OutOfSyncHndVirt, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time2/OutOfSyncHndVirt", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is an out-of-sync virtual handler page.");
1633	STAM_REG(pVM, &pPGM->StatRZTrap0eTime2OutOfSyncHndObs, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time2/OutOfSyncObsHnd", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is an obsolete handler page.");
1634	STAM_REG(pVM, &pPGM->StatRZTrap0eTime2SyncPT, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time2/SyncPT", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is lazy syncing of a PT.");
1635	STAM_REG(pVM, &pPGM->StatRZTrap0eConflicts, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Conflicts", STAMUNIT_OCCURENCES, "The number of times #PF was caused by an undetected conflict.");
1636	STAM_REG(pVM, &pPGM->StatRZTrap0eHandlersMapping, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Handlers/Mapping", STAMUNIT_OCCURENCES, "Number of traps due to access handlers in mappings.");
1637	STAM_REG(pVM, &pPGM->StatRZTrap0eHandlersOutOfSync, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Handlers/OutOfSync", STAMUNIT_OCCURENCES, "Number of traps due to out-of-sync handled pages.");
1638	STAM_REG(pVM, &pPGM->StatRZTrap0eHandlersPhysical, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Handlers/Physical", STAMUNIT_OCCURENCES, "Number of traps due to physical access handlers.");
1639	STAM_REG(pVM, &pPGM->StatRZTrap0eHandlersVirtual, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Handlers/Virtual", STAMUNIT_OCCURENCES, "Number of traps due to virtual access handlers.");
1640	STAM_REG(pVM, &pPGM->StatRZTrap0eHandlersVirtualByPhys, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Handlers/VirtualByPhys", STAMUNIT_OCCURENCES, "Number of traps due to virtual access handlers by physical address.");
1641	STAM_REG(pVM, &pPGM->StatRZTrap0eHandlersVirtualUnmarked,STAMTYPE_COUNTER,"/PGM/RZ/Trap0e/Handlers/VirtualUnmarked",STAMUNIT_OCCURENCES, "Number of traps due to virtual access handlers by virtual address (without proper physical flags).");
1642	STAM_REG(pVM, &pPGM->StatRZTrap0eHandlersUnhandled, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Handlers/Unhandled", STAMUNIT_OCCURENCES, "Number of traps due to access outside range of monitored page(s).");
1643	STAM_REG(pVM, &pPGM->StatRZTrap0eHandlersInvalid, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Handlers/Invalid", STAMUNIT_OCCURENCES, "Number of traps due to access to invalid physical memory.");
1644	STAM_REG(pVM, &pPGM->StatRZTrap0eUSNotPresentRead, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Err/User/NPRead", STAMUNIT_OCCURENCES, "Number of user mode not present read page faults.");
1645	STAM_REG(pVM, &pPGM->StatRZTrap0eUSNotPresentWrite, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Err/User/NPWrite", STAMUNIT_OCCURENCES, "Number of user mode not present write page faults.");
1646	STAM_REG(pVM, &pPGM->StatRZTrap0eUSWrite, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Err/User/Write", STAMUNIT_OCCURENCES, "Number of user mode write page faults.");
1647	STAM_REG(pVM, &pPGM->StatRZTrap0eUSReserved, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Err/User/Reserved", STAMUNIT_OCCURENCES, "Number of user mode reserved bit page faults.");
1648	STAM_REG(pVM, &pPGM->StatRZTrap0eUSNXE, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Err/User/NXE", STAMUNIT_OCCURENCES, "Number of user mode NXE page faults.");
1649	STAM_REG(pVM, &pPGM->StatRZTrap0eUSRead, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Err/User/Read", STAMUNIT_OCCURENCES, "Number of user mode read page faults.");
1650	STAM_REG(pVM, &pPGM->StatRZTrap0eSVNotPresentRead, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Err/Supervisor/NPRead", STAMUNIT_OCCURENCES, "Number of supervisor mode not present read page faults.");
1651	STAM_REG(pVM, &pPGM->StatRZTrap0eSVNotPresentWrite, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Err/Supervisor/NPWrite", STAMUNIT_OCCURENCES, "Number of supervisor mode not present write page faults.");
1652	STAM_REG(pVM, &pPGM->StatRZTrap0eSVWrite, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Err/Supervisor/Write", STAMUNIT_OCCURENCES, "Number of supervisor mode write page faults.");
1653	STAM_REG(pVM, &pPGM->StatRZTrap0eSVReserved, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Err/Supervisor/Reserved", STAMUNIT_OCCURENCES, "Number of supervisor mode reserved bit page faults.");
1654	STAM_REG(pVM, &pPGM->StatRZTrap0eSNXE, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Err/Supervisor/NXE", STAMUNIT_OCCURENCES, "Number of supervisor mode NXE page faults.");
1655	STAM_REG(pVM, &pPGM->StatRZTrap0eGuestPF, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/GuestPF", STAMUNIT_OCCURENCES, "Number of real guest page faults.");
1656	STAM_REG(pVM, &pPGM->StatRZTrap0eGuestPFUnh, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/GuestPF/Unhandled", STAMUNIT_OCCURENCES, "Number of real guest page faults from the 'unhandled' case.");
1657	STAM_REG(pVM, &pPGM->StatRZTrap0eGuestPFMapping, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/GuestPF/InMapping", STAMUNIT_OCCURENCES, "Number of real guest page faults in a mapping.");
1658	STAM_REG(pVM, &pPGM->StatRZTrap0eWPEmulInRZ, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/WP/InRZ", STAMUNIT_OCCURENCES, "Number of guest page faults due to X86_CR0_WP emulation.");
1659	STAM_REG(pVM, &pPGM->StatRZTrap0eWPEmulToR3, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/WP/ToR3", STAMUNIT_OCCURENCES, "Number of guest page faults due to X86_CR0_WP emulation (forward to R3 for emulation).");
1660	for (i = 0; i < RT_ELEMENTS(pPGM->StatRZTrap0ePD); i++)
1661	STAMR3RegisterF(pVM, &pPGM->StatRZTrap0ePD[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
1662	"The number of traps in page directory n.", "/PGM/RZ/Trap0e/PD/%04X", i);
1663	STAM_REG(pVM, &pPGM->StatRZGuestCR3WriteHandled, STAMTYPE_COUNTER, "/PGM/RZ/CR3WriteHandled", STAMUNIT_OCCURENCES, "The number of times the Guest CR3 change was successfully handled.");
1664	STAM_REG(pVM, &pPGM->StatRZGuestCR3WriteUnhandled, STAMTYPE_COUNTER, "/PGM/RZ/CR3WriteUnhandled", STAMUNIT_OCCURENCES, "The number of times the Guest CR3 change was passed back to the recompiler.");
1665	STAM_REG(pVM, &pPGM->StatRZGuestCR3WriteConflict, STAMTYPE_COUNTER, "/PGM/RZ/CR3WriteConflict", STAMUNIT_OCCURENCES, "The number of times the Guest CR3 monitoring detected a conflict.");
1666	STAM_REG(pVM, &pPGM->StatRZGuestROMWriteHandled, STAMTYPE_COUNTER, "/PGM/RZ/ROMWriteHandled", STAMUNIT_OCCURENCES, "The number of times the Guest ROM change was successfully handled.");
1667	STAM_REG(pVM, &pPGM->StatRZGuestROMWriteUnhandled, STAMTYPE_COUNTER, "/PGM/RZ/ROMWriteUnhandled", STAMUNIT_OCCURENCES, "The number of times the Guest ROM change was passed back to the recompiler.");
1668
1669	/* HC only: */
1670
1671	/* RZ & R3: */
1672	STAM_REG(pVM, &pPGM->StatRZSyncCR3, STAMTYPE_PROFILE, "/PGM/RZ/SyncCR3", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMSyncCR3() body.");
1673	STAM_REG(pVM, &pPGM->StatRZSyncCR3Handlers, STAMTYPE_PROFILE, "/PGM/RZ/SyncCR3/Handlers", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMSyncCR3() update handler section.");
1674	STAM_REG(pVM, &pPGM->StatRZSyncCR3HandlerVirtualUpdate, STAMTYPE_PROFILE, "/PGM/RZ/SyncCR3/Handlers/VirtualUpdate", STAMUNIT_TICKS_PER_CALL, "Profiling of the virtual handler updates.");
1675	STAM_REG(pVM, &pPGM->StatRZSyncCR3HandlerVirtualReset, STAMTYPE_PROFILE, "/PGM/RZ/SyncCR3/Handlers/VirtualReset", STAMUNIT_TICKS_PER_CALL, "Profiling of the virtual handler resets.");
1676	STAM_REG(pVM, &pPGM->StatRZSyncCR3Global, STAMTYPE_COUNTER, "/PGM/RZ/SyncCR3/Global", STAMUNIT_OCCURENCES, "The number of global CR3 syncs.");
1677	STAM_REG(pVM, &pPGM->StatRZSyncCR3NotGlobal, STAMTYPE_COUNTER, "/PGM/RZ/SyncCR3/NotGlobal", STAMUNIT_OCCURENCES, "The number of non-global CR3 syncs.");
1678	STAM_REG(pVM, &pPGM->StatRZSyncCR3DstCacheHit, STAMTYPE_COUNTER, "/PGM/RZ/SyncCR3/DstChacheHit", STAMUNIT_OCCURENCES, "The number of times we got some kind of a cache hit.");
1679	STAM_REG(pVM, &pPGM->StatRZSyncCR3DstFreed, STAMTYPE_COUNTER, "/PGM/RZ/SyncCR3/DstFreed", STAMUNIT_OCCURENCES, "The number of times we've had to free a shadow entry.");
1680	STAM_REG(pVM, &pPGM->StatRZSyncCR3DstFreedSrcNP, STAMTYPE_COUNTER, "/PGM/RZ/SyncCR3/DstFreedSrcNP", STAMUNIT_OCCURENCES, "The number of times we've had to free a shadow entry for which the source entry was not present.");
1681	STAM_REG(pVM, &pPGM->StatRZSyncCR3DstNotPresent, STAMTYPE_COUNTER, "/PGM/RZ/SyncCR3/DstNotPresent", STAMUNIT_OCCURENCES, "The number of times we've encountered a not present shadow entry for a present guest entry.");
1682	STAM_REG(pVM, &pPGM->StatRZSyncCR3DstSkippedGlobalPD, STAMTYPE_COUNTER, "/PGM/RZ/SyncCR3/DstSkippedGlobalPD", STAMUNIT_OCCURENCES, "The number of times a global page directory wasn't flushed.");
1683	STAM_REG(pVM, &pPGM->StatRZSyncCR3DstSkippedGlobalPT, STAMTYPE_COUNTER, "/PGM/RZ/SyncCR3/DstSkippedGlobalPT", STAMUNIT_OCCURENCES, "The number of times a page table with only global entries wasn't flushed.");
1684	STAM_REG(pVM, &pPGM->StatRZSyncPT, STAMTYPE_PROFILE, "/PGM/RZ/SyncPT", STAMUNIT_TICKS_PER_CALL, "Profiling of the pfnSyncPT() body.");
1685	STAM_REG(pVM, &pPGM->StatRZSyncPTFailed, STAMTYPE_COUNTER, "/PGM/RZ/SyncPT/Failed", STAMUNIT_OCCURENCES, "The number of times pfnSyncPT() failed.");
1686	STAM_REG(pVM, &pPGM->StatRZSyncPT4K, STAMTYPE_COUNTER, "/PGM/RZ/SyncPT/4K", STAMUNIT_OCCURENCES, "Nr of 4K PT syncs");
1687	STAM_REG(pVM, &pPGM->StatRZSyncPT4M, STAMTYPE_COUNTER, "/PGM/RZ/SyncPT/4M", STAMUNIT_OCCURENCES, "Nr of 4M PT syncs");
1688	STAM_REG(pVM, &pPGM->StatRZSyncPagePDNAs, STAMTYPE_COUNTER, "/PGM/RZ/SyncPagePDNAs", STAMUNIT_OCCURENCES, "The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit.");
1689	STAM_REG(pVM, &pPGM->StatRZSyncPagePDOutOfSync, STAMTYPE_COUNTER, "/PGM/RZ/SyncPagePDOutOfSync", STAMUNIT_OCCURENCES, "The number of time we've encountered an out-of-sync PD in SyncPage.");
1690	STAM_REG(pVM, &pPGM->StatRZAccessedPage, STAMTYPE_COUNTER, "/PGM/RZ/AccessedPage", STAMUNIT_OCCURENCES, "The number of pages marked not present for accessed bit emulation.");
1691	STAM_REG(pVM, &pPGM->StatRZDirtyBitTracking, STAMTYPE_PROFILE, "/PGM/RZ/DirtyPage", STAMUNIT_TICKS_PER_CALL, "Profiling the dirty bit tracking in CheckPageFault().");
1692	STAM_REG(pVM, &pPGM->StatRZDirtyPage, STAMTYPE_COUNTER, "/PGM/RZ/DirtyPage/Mark", STAMUNIT_OCCURENCES, "The number of pages marked read-only for dirty bit tracking.");
1693	STAM_REG(pVM, &pPGM->StatRZDirtyPageBig, STAMTYPE_COUNTER, "/PGM/RZ/DirtyPage/MarkBig", STAMUNIT_OCCURENCES, "The number of 4MB pages marked read-only for dirty bit tracking.");
1694	STAM_REG(pVM, &pPGM->StatRZDirtyPageSkipped, STAMTYPE_COUNTER, "/PGM/RZ/DirtyPage/Skipped", STAMUNIT_OCCURENCES, "The number of pages already dirty or readonly.");
1695	STAM_REG(pVM, &pPGM->StatRZDirtyPageTrap, STAMTYPE_COUNTER, "/PGM/RZ/DirtyPage/Trap", STAMUNIT_OCCURENCES, "The number of traps generated for dirty bit tracking.");
1696	STAM_REG(pVM, &pPGM->StatRZDirtiedPage, STAMTYPE_COUNTER, "/PGM/RZ/DirtyPage/SetDirty", STAMUNIT_OCCURENCES, "The number of pages marked dirty because of write accesses.");
1697	STAM_REG(pVM, &pPGM->StatRZDirtyTrackRealPF, STAMTYPE_COUNTER, "/PGM/RZ/DirtyPage/RealPF", STAMUNIT_OCCURENCES, "The number of real pages faults during dirty bit tracking.");
1698	STAM_REG(pVM, &pPGM->StatRZPageAlreadyDirty, STAMTYPE_COUNTER, "/PGM/RZ/DirtyPage/AlreadySet", STAMUNIT_OCCURENCES, "The number of pages already marked dirty because of write accesses.");
1699	STAM_REG(pVM, &pPGM->StatRZInvalidatePage, STAMTYPE_PROFILE, "/PGM/RZ/InvalidatePage", STAMUNIT_TICKS_PER_CALL, "PGMInvalidatePage() profiling.");
1700	STAM_REG(pVM, &pPGM->StatRZInvalidatePage4KBPages, STAMTYPE_COUNTER, "/PGM/RZ/InvalidatePage/4KBPages", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was called for a 4KB page.");
1701	STAM_REG(pVM, &pPGM->StatRZInvalidatePage4MBPages, STAMTYPE_COUNTER, "/PGM/RZ/InvalidatePage/4MBPages", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was called for a 4MB page.");
1702	STAM_REG(pVM, &pPGM->StatRZInvalidatePage4MBPagesSkip, STAMTYPE_COUNTER, "/PGM/RZ/InvalidatePage/4MBPagesSkip",STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() skipped a 4MB page.");
1703	STAM_REG(pVM, &pPGM->StatRZInvalidatePagePDMappings, STAMTYPE_COUNTER, "/PGM/RZ/InvalidatePage/PDMappings", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict).");
1704	STAM_REG(pVM, &pPGM->StatRZInvalidatePagePDNAs, STAMTYPE_COUNTER, "/PGM/RZ/InvalidatePage/PDNAs", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was called for a not accessed page directory.");
1705	STAM_REG(pVM, &pPGM->StatRZInvalidatePagePDNPs, STAMTYPE_COUNTER, "/PGM/RZ/InvalidatePage/PDNPs", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was called for a not present page directory.");
1706	STAM_REG(pVM, &pPGM->StatRZInvalidatePagePDOutOfSync, STAMTYPE_COUNTER, "/PGM/RZ/InvalidatePage/PDOutOfSync", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was called for an out of sync page directory.");
1707	STAM_REG(pVM, &pPGM->StatRZInvalidatePageSkipped, STAMTYPE_COUNTER, "/PGM/RZ/InvalidatePage/Skipped", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3.");
1708	STAM_REG(pVM, &pPGM->StatRZVirtHandlerSearchByPhys, STAMTYPE_PROFILE, "/PGM/RZ/VirtHandlerSearchByPhys", STAMUNIT_TICKS_PER_CALL, "Profiling of pgmHandlerVirtualFindByPhysAddr.");
1709	STAM_REG(pVM, &pPGM->StatRZPhysHandlerReset, STAMTYPE_COUNTER, "/PGM/RZ/PhysHandlerReset", STAMUNIT_OCCURENCES, "The number of times PGMHandlerPhysicalReset is called.");
1710	STAM_REG(pVM, &pPGM->StatRZPageOutOfSyncSupervisor, STAMTYPE_COUNTER, "/PGM/RZ/OutOfSync/SuperVisor", STAMUNIT_OCCURENCES, "Number of traps due to pages out of sync and times VerifyAccessSyncPage calls SyncPage.");
1711	STAM_REG(pVM, &pPGM->StatRZPageOutOfSyncUser, STAMTYPE_COUNTER, "/PGM/RZ/OutOfSync/User", STAMUNIT_OCCURENCES, "Number of traps due to pages out of sync and times VerifyAccessSyncPage calls SyncPage.");
1712	STAM_REG(pVM, &pPGM->StatRZPrefetch, STAMTYPE_PROFILE, "/PGM/RZ/Prefetch", STAMUNIT_TICKS_PER_CALL, "PGMPrefetchPage profiling.");
1713	STAM_REG(pVM, &pPGM->StatRZChunkR3MapTlbHits, STAMTYPE_COUNTER, "/PGM/ChunkR3Map/TlbHitsRZ", STAMUNIT_OCCURENCES, "TLB hits.");
1714	STAM_REG(pVM, &pPGM->StatRZChunkR3MapTlbMisses, STAMTYPE_COUNTER, "/PGM/ChunkR3Map/TlbMissesRZ", STAMUNIT_OCCURENCES, "TLB misses.");
1715	STAM_REG(pVM, &pPGM->StatRZPageMapTlbHits, STAMTYPE_COUNTER, "/PGM/RZ/Page/MapTlbHits", STAMUNIT_OCCURENCES, "TLB hits.");
1716	STAM_REG(pVM, &pPGM->StatRZPageMapTlbMisses, STAMTYPE_COUNTER, "/PGM/RZ/Page/MapTlbMisses", STAMUNIT_OCCURENCES, "TLB misses.");
1717	STAM_REG(pVM, &pPGM->StatRZPageReplaceShared, STAMTYPE_COUNTER, "/PGM/RZ/Page/ReplacedShared", STAMUNIT_OCCURENCES, "Times a shared page was replaced.");
1718	STAM_REG(pVM, &pPGM->StatRZPageReplaceZero, STAMTYPE_COUNTER, "/PGM/RZ/Page/ReplacedZero", STAMUNIT_OCCURENCES, "Times the zero page was replaced.");
1719	/// @todo STAM_REG(pVM, &pPGM->StatRZPageHandyAllocs, STAMTYPE_COUNTER, "/PGM/RZ/Page/HandyAllocs", STAMUNIT_OCCURENCES, "Number of times we've allocated more handy pages.");
1720	STAM_REG(pVM, &pPGM->StatRZFlushTLB, STAMTYPE_PROFILE, "/PGM/RZ/FlushTLB", STAMUNIT_OCCURENCES, "Profiling of the PGMFlushTLB() body.");
1721	STAM_REG(pVM, &pPGM->StatRZFlushTLBNewCR3, STAMTYPE_COUNTER, "/PGM/RZ/FlushTLB/NewCR3", STAMUNIT_OCCURENCES, "The number of times PGMFlushTLB was called with a new CR3, non-global. (switch)");
1722	STAM_REG(pVM, &pPGM->StatRZFlushTLBNewCR3Global, STAMTYPE_COUNTER, "/PGM/RZ/FlushTLB/NewCR3Global", STAMUNIT_OCCURENCES, "The number of times PGMFlushTLB was called with a new CR3, global. (switch)");
1723	STAM_REG(pVM, &pPGM->StatRZFlushTLBSameCR3, STAMTYPE_COUNTER, "/PGM/RZ/FlushTLB/SameCR3", STAMUNIT_OCCURENCES, "The number of times PGMFlushTLB was called with the same CR3, non-global. (flush)");
1724	STAM_REG(pVM, &pPGM->StatRZFlushTLBSameCR3Global, STAMTYPE_COUNTER, "/PGM/RZ/FlushTLB/SameCR3Global", STAMUNIT_OCCURENCES, "The number of times PGMFlushTLB was called with the same CR3, global. (flush)");
1725	STAM_REG(pVM, &pPGM->StatRZGstModifyPage, STAMTYPE_PROFILE, "/PGM/RZ/GstModifyPage", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMGstModifyPage() body.");
1726
1727	STAM_REG(pVM, &pPGM->StatR3SyncCR3, STAMTYPE_PROFILE, "/PGM/R3/SyncCR3", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMSyncCR3() body.");
1728	STAM_REG(pVM, &pPGM->StatR3SyncCR3Handlers, STAMTYPE_PROFILE, "/PGM/R3/SyncCR3/Handlers", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMSyncCR3() update handler section.");
1729	STAM_REG(pVM, &pPGM->StatR3SyncCR3HandlerVirtualUpdate, STAMTYPE_PROFILE, "/PGM/R3/SyncCR3/Handlers/VirtualUpdate", STAMUNIT_TICKS_PER_CALL, "Profiling of the virtual handler updates.");
1730	STAM_REG(pVM, &pPGM->StatR3SyncCR3HandlerVirtualReset, STAMTYPE_PROFILE, "/PGM/R3/SyncCR3/Handlers/VirtualReset", STAMUNIT_TICKS_PER_CALL, "Profiling of the virtual handler resets.");
1731	STAM_REG(pVM, &pPGM->StatR3SyncCR3Global, STAMTYPE_COUNTER, "/PGM/R3/SyncCR3/Global", STAMUNIT_OCCURENCES, "The number of global CR3 syncs.");
1732	STAM_REG(pVM, &pPGM->StatR3SyncCR3NotGlobal, STAMTYPE_COUNTER, "/PGM/R3/SyncCR3/NotGlobal", STAMUNIT_OCCURENCES, "The number of non-global CR3 syncs.");
1733	STAM_REG(pVM, &pPGM->StatR3SyncCR3DstCacheHit, STAMTYPE_COUNTER, "/PGM/R3/SyncCR3/DstChacheHit", STAMUNIT_OCCURENCES, "The number of times we got some kind of a cache hit.");
1734	STAM_REG(pVM, &pPGM->StatR3SyncCR3DstFreed, STAMTYPE_COUNTER, "/PGM/R3/SyncCR3/DstFreed", STAMUNIT_OCCURENCES, "The number of times we've had to free a shadow entry.");
1735	STAM_REG(pVM, &pPGM->StatR3SyncCR3DstFreedSrcNP, STAMTYPE_COUNTER, "/PGM/R3/SyncCR3/DstFreedSrcNP", STAMUNIT_OCCURENCES, "The number of times we've had to free a shadow entry for which the source entry was not present.");
1736	STAM_REG(pVM, &pPGM->StatR3SyncCR3DstNotPresent, STAMTYPE_COUNTER, "/PGM/R3/SyncCR3/DstNotPresent", STAMUNIT_OCCURENCES, "The number of times we've encountered a not present shadow entry for a present guest entry.");
1737	STAM_REG(pVM, &pPGM->StatR3SyncCR3DstSkippedGlobalPD, STAMTYPE_COUNTER, "/PGM/R3/SyncCR3/DstSkippedGlobalPD", STAMUNIT_OCCURENCES, "The number of times a global page directory wasn't flushed.");
1738	STAM_REG(pVM, &pPGM->StatR3SyncCR3DstSkippedGlobalPT, STAMTYPE_COUNTER, "/PGM/R3/SyncCR3/DstSkippedGlobalPT", STAMUNIT_OCCURENCES, "The number of times a page table with only global entries wasn't flushed.");
1739	STAM_REG(pVM, &pPGM->StatR3SyncPT, STAMTYPE_PROFILE, "/PGM/R3/SyncPT", STAMUNIT_TICKS_PER_CALL, "Profiling of the pfnSyncPT() body.");
1740	STAM_REG(pVM, &pPGM->StatR3SyncPTFailed, STAMTYPE_COUNTER, "/PGM/R3/SyncPT/Failed", STAMUNIT_OCCURENCES, "The number of times pfnSyncPT() failed.");
1741	STAM_REG(pVM, &pPGM->StatR3SyncPT4K, STAMTYPE_COUNTER, "/PGM/R3/SyncPT/4K", STAMUNIT_OCCURENCES, "Nr of 4K PT syncs");
1742	STAM_REG(pVM, &pPGM->StatR3SyncPT4M, STAMTYPE_COUNTER, "/PGM/R3/SyncPT/4M", STAMUNIT_OCCURENCES, "Nr of 4M PT syncs");
1743	STAM_REG(pVM, &pPGM->StatR3SyncPagePDNAs, STAMTYPE_COUNTER, "/PGM/R3/SyncPagePDNAs", STAMUNIT_OCCURENCES, "The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit.");
1744	STAM_REG(pVM, &pPGM->StatR3SyncPagePDOutOfSync, STAMTYPE_COUNTER, "/PGM/R3/SyncPagePDOutOfSync", STAMUNIT_OCCURENCES, "The number of time we've encountered an out-of-sync PD in SyncPage.");
1745	STAM_REG(pVM, &pPGM->StatR3AccessedPage, STAMTYPE_COUNTER, "/PGM/R3/AccessedPage", STAMUNIT_OCCURENCES, "The number of pages marked not present for accessed bit emulation.");
1746	STAM_REG(pVM, &pPGM->StatR3DirtyBitTracking, STAMTYPE_PROFILE, "/PGM/R3/DirtyPage", STAMUNIT_TICKS_PER_CALL, "Profiling the dirty bit tracking in CheckPageFault().");
1747	STAM_REG(pVM, &pPGM->StatR3DirtyPage, STAMTYPE_COUNTER, "/PGM/R3/DirtyPage/Mark", STAMUNIT_OCCURENCES, "The number of pages marked read-only for dirty bit tracking.");
1748	STAM_REG(pVM, &pPGM->StatR3DirtyPageBig, STAMTYPE_COUNTER, "/PGM/R3/DirtyPage/MarkBig", STAMUNIT_OCCURENCES, "The number of 4MB pages marked read-only for dirty bit tracking.");
1749	STAM_REG(pVM, &pPGM->StatR3DirtyPageSkipped, STAMTYPE_COUNTER, "/PGM/R3/DirtyPage/Skipped", STAMUNIT_OCCURENCES, "The number of pages already dirty or readonly.");
1750	STAM_REG(pVM, &pPGM->StatR3DirtyPageTrap, STAMTYPE_COUNTER, "/PGM/R3/DirtyPage/Trap", STAMUNIT_OCCURENCES, "The number of traps generated for dirty bit tracking.");
1751	STAM_REG(pVM, &pPGM->StatR3DirtiedPage, STAMTYPE_COUNTER, "/PGM/R3/DirtyPage/SetDirty", STAMUNIT_OCCURENCES, "The number of pages marked dirty because of write accesses.");
1752	STAM_REG(pVM, &pPGM->StatR3DirtyTrackRealPF, STAMTYPE_COUNTER, "/PGM/R3/DirtyPage/RealPF", STAMUNIT_OCCURENCES, "The number of real pages faults during dirty bit tracking.");
1753	STAM_REG(pVM, &pPGM->StatR3PageAlreadyDirty, STAMTYPE_COUNTER, "/PGM/R3/DirtyPage/AlreadySet", STAMUNIT_OCCURENCES, "The number of pages already marked dirty because of write accesses.");
1754	STAM_REG(pVM, &pPGM->StatR3InvalidatePage, STAMTYPE_PROFILE, "/PGM/R3/InvalidatePage", STAMUNIT_TICKS_PER_CALL, "PGMInvalidatePage() profiling.");
1755	STAM_REG(pVM, &pPGM->StatR3InvalidatePage4KBPages, STAMTYPE_COUNTER, "/PGM/R3/InvalidatePage/4KBPages", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was called for a 4KB page.");
1756	STAM_REG(pVM, &pPGM->StatR3InvalidatePage4MBPages, STAMTYPE_COUNTER, "/PGM/R3/InvalidatePage/4MBPages", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was called for a 4MB page.");
1757	STAM_REG(pVM, &pPGM->StatR3InvalidatePage4MBPagesSkip, STAMTYPE_COUNTER, "/PGM/R3/InvalidatePage/4MBPagesSkip",STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() skipped a 4MB page.");
1758	STAM_REG(pVM, &pPGM->StatR3InvalidatePagePDMappings, STAMTYPE_COUNTER, "/PGM/R3/InvalidatePage/PDMappings", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict).");
1759	STAM_REG(pVM, &pPGM->StatR3InvalidatePagePDNAs, STAMTYPE_COUNTER, "/PGM/R3/InvalidatePage/PDNAs", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was called for a not accessed page directory.");
1760	STAM_REG(pVM, &pPGM->StatR3InvalidatePagePDNPs, STAMTYPE_COUNTER, "/PGM/R3/InvalidatePage/PDNPs", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was called for a not present page directory.");
1761	STAM_REG(pVM, &pPGM->StatR3InvalidatePagePDOutOfSync, STAMTYPE_COUNTER, "/PGM/R3/InvalidatePage/PDOutOfSync", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was called for an out of sync page directory.");
1762	STAM_REG(pVM, &pPGM->StatR3InvalidatePageSkipped, STAMTYPE_COUNTER, "/PGM/R3/InvalidatePage/Skipped", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3.");
1763	STAM_REG(pVM, &pPGM->StatR3VirtHandlerSearchByPhys, STAMTYPE_PROFILE, "/PGM/R3/VirtHandlerSearchByPhys", STAMUNIT_TICKS_PER_CALL, "Profiling of pgmHandlerVirtualFindByPhysAddr.");
1764	STAM_REG(pVM, &pPGM->StatR3PhysHandlerReset, STAMTYPE_COUNTER, "/PGM/R3/PhysHandlerReset", STAMUNIT_OCCURENCES, "The number of times PGMHandlerPhysicalReset is called.");
1765	STAM_REG(pVM, &pPGM->StatR3PageOutOfSyncSupervisor, STAMTYPE_COUNTER, "/PGM/R3/OutOfSync/SuperVisor", STAMUNIT_OCCURENCES, "Number of traps due to pages out of sync and times VerifyAccessSyncPage calls SyncPage.");
1766	STAM_REG(pVM, &pPGM->StatR3PageOutOfSyncUser, STAMTYPE_COUNTER, "/PGM/R3/OutOfSync/User", STAMUNIT_OCCURENCES, "Number of traps due to pages out of sync and times VerifyAccessSyncPage calls SyncPage.");
1767	STAM_REG(pVM, &pPGM->StatR3Prefetch, STAMTYPE_PROFILE, "/PGM/R3/Prefetch", STAMUNIT_TICKS_PER_CALL, "PGMPrefetchPage profiling.");
1768	STAM_REG(pVM, &pPGM->StatR3ChunkR3MapTlbHits, STAMTYPE_COUNTER, "/PGM/ChunkR3Map/TlbHitsR3", STAMUNIT_OCCURENCES, "TLB hits.");
1769	STAM_REG(pVM, &pPGM->StatR3ChunkR3MapTlbMisses, STAMTYPE_COUNTER, "/PGM/ChunkR3Map/TlbMissesR3", STAMUNIT_OCCURENCES, "TLB misses.");
1770	STAM_REG(pVM, &pPGM->StatR3PageMapTlbHits, STAMTYPE_COUNTER, "/PGM/R3/Page/MapTlbHits", STAMUNIT_OCCURENCES, "TLB hits.");
1771	STAM_REG(pVM, &pPGM->StatR3PageMapTlbMisses, STAMTYPE_COUNTER, "/PGM/R3/Page/MapTlbMisses", STAMUNIT_OCCURENCES, "TLB misses.");
1772	STAM_REG(pVM, &pPGM->StatR3PageReplaceShared, STAMTYPE_COUNTER, "/PGM/R3/Page/ReplacedShared", STAMUNIT_OCCURENCES, "Times a shared page was replaced.");
1773	STAM_REG(pVM, &pPGM->StatR3PageReplaceZero, STAMTYPE_COUNTER, "/PGM/R3/Page/ReplacedZero", STAMUNIT_OCCURENCES, "Times the zero page was replaced.");
1774	/// @todo STAM_REG(pVM, &pPGM->StatR3PageHandyAllocs, STAMTYPE_COUNTER, "/PGM/R3/Page/HandyAllocs", STAMUNIT_OCCURENCES, "Number of times we've allocated more handy pages.");
1775	STAM_REG(pVM, &pPGM->StatR3FlushTLB, STAMTYPE_PROFILE, "/PGM/R3/FlushTLB", STAMUNIT_OCCURENCES, "Profiling of the PGMFlushTLB() body.");
1776	STAM_REG(pVM, &pPGM->StatR3FlushTLBNewCR3, STAMTYPE_COUNTER, "/PGM/R3/FlushTLB/NewCR3", STAMUNIT_OCCURENCES, "The number of times PGMFlushTLB was called with a new CR3, non-global. (switch)");
1777	STAM_REG(pVM, &pPGM->StatR3FlushTLBNewCR3Global, STAMTYPE_COUNTER, "/PGM/R3/FlushTLB/NewCR3Global", STAMUNIT_OCCURENCES, "The number of times PGMFlushTLB was called with a new CR3, global. (switch)");
1778	STAM_REG(pVM, &pPGM->StatR3FlushTLBSameCR3, STAMTYPE_COUNTER, "/PGM/R3/FlushTLB/SameCR3", STAMUNIT_OCCURENCES, "The number of times PGMFlushTLB was called with the same CR3, non-global. (flush)");
1779	STAM_REG(pVM, &pPGM->StatR3FlushTLBSameCR3Global, STAMTYPE_COUNTER, "/PGM/R3/FlushTLB/SameCR3Global", STAMUNIT_OCCURENCES, "The number of times PGMFlushTLB was called with the same CR3, global. (flush)");
1780	STAM_REG(pVM, &pPGM->StatR3GstModifyPage, STAMTYPE_PROFILE, "/PGM/R3/GstModifyPage", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMGstModifyPage() body.");
1781
1782	}
1783	#endif /* VBOX_WITH_STATISTICS */
1784
1785
1786	/**
1787	* Init the PGM bits that rely on VMMR0 and MM to be fully initialized.
1788	*
1789	* The dynamic mapping area will also be allocated and initialized at this
1790	* time. We could allocate it during PGMR3Init of course, but the mapping
1791	* wouldn't be allocated at that time preventing us from setting up the
1792	* page table entries with the dummy page.
1793	*
1794	* @returns VBox status code.
1795	* @param pVM VM handle.
1796	*/
1797	VMMR3DECL(int) PGMR3InitDynMap(PVM pVM)
1798	{
1799	RTGCPTR GCPtr;
1800	int rc;
1801
1802	/*
1803	* Reserve space for the dynamic mappings.
1804	*/
1805	rc = MMR3HyperReserve(pVM, MM_HYPER_DYNAMIC_SIZE, "Dynamic mapping", &GCPtr);
1806	if (RT_SUCCESS(rc))
1807	pVM->pgm.s.pbDynPageMapBaseGC = GCPtr;
1808
1809	if ( RT_SUCCESS(rc)
1810	&& (pVM->pgm.s.pbDynPageMapBaseGC >> X86_PD_PAE_SHIFT) != ((pVM->pgm.s.pbDynPageMapBaseGC + MM_HYPER_DYNAMIC_SIZE - 1) >> X86_PD_PAE_SHIFT))
1811	{
1812	rc = MMR3HyperReserve(pVM, MM_HYPER_DYNAMIC_SIZE, "Dynamic mapping not crossing", &GCPtr);
1813	if (RT_SUCCESS(rc))
1814	pVM->pgm.s.pbDynPageMapBaseGC = GCPtr;
1815	}
1816	if (RT_SUCCESS(rc))
1817	{
1818	AssertRelease((pVM->pgm.s.pbDynPageMapBaseGC >> X86_PD_PAE_SHIFT) == ((pVM->pgm.s.pbDynPageMapBaseGC + MM_HYPER_DYNAMIC_SIZE - 1) >> X86_PD_PAE_SHIFT));
1819	MMR3HyperReserve(pVM, PAGE_SIZE, "fence", NULL);
1820	}
1821	return rc;
1822	}
1823
1824
1825	/**
1826	* Ring-3 init finalizing.
1827	*
1828	* @returns VBox status code.
1829	* @param pVM The VM handle.
1830	*/
1831	VMMR3DECL(int) PGMR3InitFinalize(PVM pVM)
1832	{
1833	int rc;
1834
1835	/*
1836	* Reserve space for the dynamic mappings.
1837	* Initialize the dynamic mapping pages with dummy pages to simply the cache.
1838	*/
1839	/* get the pointer to the page table entries. */
1840	PPGMMAPPING pMapping = pgmGetMapping(pVM, pVM->pgm.s.pbDynPageMapBaseGC);
1841	AssertRelease(pMapping);
1842	const uintptr_t off = pVM->pgm.s.pbDynPageMapBaseGC - pMapping->GCPtr;
1843	const unsigned iPT = off >> X86_PD_SHIFT;
1844	const unsigned iPG = (off >> X86_PT_SHIFT) & X86_PT_MASK;
1845	pVM->pgm.s.paDynPageMap32BitPTEsGC = pMapping->aPTs[iPT].pPTRC + iPG * sizeof(pMapping->aPTs[0].pPTR3->a[0]);
1846	pVM->pgm.s.paDynPageMapPaePTEsGC = pMapping->aPTs[iPT].paPaePTsRC + iPG * sizeof(pMapping->aPTs[0].paPaePTsR3->a[0]);
1847
1848	/* init cache */
1849	RTHCPHYS HCPhysDummy = MMR3PageDummyHCPhys(pVM);
1850	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.aHCPhysDynPageMapCache); i++)
1851	pVM->pgm.s.aHCPhysDynPageMapCache[i] = HCPhysDummy;
1852
1853	for (unsigned i = 0; i < MM_HYPER_DYNAMIC_SIZE; i += PAGE_SIZE)
1854	{
1855	rc = PGMMap(pVM, pVM->pgm.s.pbDynPageMapBaseGC + i, HCPhysDummy, PAGE_SIZE, 0);
1856	AssertRCReturn(rc, rc);
1857	}
1858
1859	/*
1860	* Note that AMD uses all the 8 reserved bits for the address (so 40 bits in total);
1861	* Intel only goes up to 36 bits, so we stick to 36 as well.
1862	*/
1863	/** @todo How to test for the 40 bits support? Long mode seems to be the test criterium. */
1864	uint32_t u32Dummy, u32Features;
1865	CPUMGetGuestCpuId(pVM, 1, &u32Dummy, &u32Dummy, &u32Dummy, &u32Features);
1866
1867	if (u32Features & X86_CPUID_FEATURE_EDX_PSE36)
1868	pVM->pgm.s.GCPhys4MBPSEMask = RT_BIT_64(36) - 1;
1869	else
1870	pVM->pgm.s.GCPhys4MBPSEMask = RT_BIT_64(32) - 1;
1871
1872	LogRel(("PGMR3InitFinalize: 4 MB PSE mask %RGp\n", pVM->pgm.s.GCPhys4MBPSEMask));
1873	return rc;
1874	}
1875
1876
1877	/**
1878	* Applies relocations to data and code managed by this component.
1879	*
1880	* This function will be called at init and whenever the VMM need to relocate it
1881	* self inside the GC.
1882	*
1883	* @param pVM The VM.
1884	* @param offDelta Relocation delta relative to old location.
1885	*/
1886	VMMR3DECL(void) PGMR3Relocate(PVM pVM, RTGCINTPTR offDelta)
1887	{
1888	LogFlow(("PGMR3Relocate %RGv to %RGv\n", pVM->pgm.s.GCPtrCR3Mapping, pVM->pgm.s.GCPtrCR3Mapping + offDelta));
1889
1890	/*
1891	* Paging stuff.
1892	*/
1893	pVM->pgm.s.GCPtrCR3Mapping += offDelta;
1894	/** @todo move this into shadow and guest specific relocation functions. */
1895	pVM->pgm.s.pGst32BitPdRC += offDelta;
1896	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.apGstPaePDsRC); i++)
1897	{
1898	pVM->pgm.s.apGstPaePDsRC[i] += offDelta;
1899	}
1900	pVM->pgm.s.pGstPaePdptRC += offDelta;
1901
1902	pVM->pgm.s.pShwPageCR3RC += offDelta;
1903
1904	pgmR3ModeDataInit(pVM, true /* resolve GC/R0 symbols */);
1905	pgmR3ModeDataSwitch(pVM, pVM->pgm.s.enmShadowMode, pVM->pgm.s.enmGuestMode);
1906
1907	PGM_SHW_PFN(Relocate, pVM)(pVM, offDelta);
1908	PGM_GST_PFN(Relocate, pVM)(pVM, offDelta);
1909	PGM_BTH_PFN(Relocate, pVM)(pVM, offDelta);
1910
1911	/*
1912	* Trees.
1913	*/
1914	pVM->pgm.s.pTreesRC = MMHyperR3ToRC(pVM, pVM->pgm.s.pTreesR3);
1915
1916	/*
1917	* Ram ranges.
1918	*/
1919	if (pVM->pgm.s.pRamRangesR3)
1920	{
1921	pVM->pgm.s.pRamRangesRC = MMHyperR3ToRC(pVM, pVM->pgm.s.pRamRangesR3);
1922	for (PPGMRAMRANGE pCur = pVM->pgm.s.pRamRangesR3; pCur->pNextR3; pCur = pCur->pNextR3)
1923	pCur->pNextRC = MMHyperR3ToRC(pVM, pCur->pNextR3);
1924	}
1925
1926	/*
1927	* Update the two page directories with all page table mappings.
1928	* (One or more of them have changed, that's why we're here.)
1929	*/
1930	pVM->pgm.s.pMappingsRC = MMHyperR3ToRC(pVM, pVM->pgm.s.pMappingsR3);
1931	for (PPGMMAPPING pCur = pVM->pgm.s.pMappingsR3; pCur->pNextR3; pCur = pCur->pNextR3)
1932	pCur->pNextRC = MMHyperR3ToRC(pVM, pCur->pNextR3);
1933
1934	/* Relocate GC addresses of Page Tables. */
1935	for (PPGMMAPPING pCur = pVM->pgm.s.pMappingsR3; pCur; pCur = pCur->pNextR3)
1936	{
1937	for (RTHCUINT i = 0; i < pCur->cPTs; i++)
1938	{
1939	pCur->aPTs[i].pPTRC = MMHyperR3ToRC(pVM, pCur->aPTs[i].pPTR3);
1940	pCur->aPTs[i].paPaePTsRC = MMHyperR3ToRC(pVM, pCur->aPTs[i].paPaePTsR3);
1941	}
1942	}
1943
1944	/*
1945	* Dynamic page mapping area.
1946	*/
1947	pVM->pgm.s.paDynPageMap32BitPTEsGC += offDelta;
1948	pVM->pgm.s.paDynPageMapPaePTEsGC += offDelta;
1949	pVM->pgm.s.pbDynPageMapBaseGC += offDelta;
1950
1951	/*
1952	* The Zero page.
1953	*/
1954	pVM->pgm.s.pvZeroPgR0 = MMHyperR3ToR0(pVM, pVM->pgm.s.pvZeroPgR3);
1955	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1956	AssertRelease(pVM->pgm.s.pvZeroPgR0 != NIL_RTR0PTR \|\| !VMMIsHwVirtExtForced(pVM));
1957	#else
1958	AssertRelease(pVM->pgm.s.pvZeroPgR0 != NIL_RTR0PTR);
1959	#endif
1960
1961	/*
1962	* Physical and virtual handlers.
1963	*/
1964	RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysHandlers, true, pgmR3RelocatePhysHandler, &offDelta);
1965	RTAvlroGCPtrDoWithAll(&pVM->pgm.s.pTreesR3->VirtHandlers, true, pgmR3RelocateVirtHandler, &offDelta);
1966	RTAvlroGCPtrDoWithAll(&pVM->pgm.s.pTreesR3->HyperVirtHandlers, true, pgmR3RelocateHyperVirtHandler, &offDelta);
1967
1968	/*
1969	* The page pool.
1970	*/
1971	pgmR3PoolRelocate(pVM);
1972	}
1973
1974
1975	/**
1976	* Callback function for relocating a physical access handler.
1977	*
1978	* @returns 0 (continue enum)
1979	* @param pNode Pointer to a PGMPHYSHANDLER node.
1980	* @param pvUser Pointer to the offDelta. This is a pointer to the delta since we're
1981	* not certain the delta will fit in a void pointer for all possible configs.
1982	*/
1983	static DECLCALLBACK(int) pgmR3RelocatePhysHandler(PAVLROGCPHYSNODECORE pNode, void *pvUser)
1984	{
1985	PPGMPHYSHANDLER pHandler = (PPGMPHYSHANDLER)pNode;
1986	RTGCINTPTR offDelta = *(PRTGCINTPTR)pvUser;
1987	if (pHandler->pfnHandlerRC)
1988	pHandler->pfnHandlerRC += offDelta;
1989	if (pHandler->pvUserRC >= 0x10000)
1990	pHandler->pvUserRC += offDelta;
1991	return 0;
1992	}
1993
1994
1995	/**
1996	* Callback function for relocating a virtual access handler.
1997	*
1998	* @returns 0 (continue enum)
1999	* @param pNode Pointer to a PGMVIRTHANDLER node.
2000	* @param pvUser Pointer to the offDelta. This is a pointer to the delta since we're
2001	* not certain the delta will fit in a void pointer for all possible configs.
2002	*/
2003	static DECLCALLBACK(int) pgmR3RelocateVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser)
2004	{
2005	PPGMVIRTHANDLER pHandler = (PPGMVIRTHANDLER)pNode;
2006	RTGCINTPTR offDelta = *(PRTGCINTPTR)pvUser;
2007	Assert( pHandler->enmType == PGMVIRTHANDLERTYPE_ALL
2008	\|\| pHandler->enmType == PGMVIRTHANDLERTYPE_WRITE);
2009	Assert(pHandler->pfnHandlerRC);
2010	pHandler->pfnHandlerRC += offDelta;
2011	return 0;
2012	}
2013
2014
2015	/**
2016	* Callback function for relocating a virtual access handler for the hypervisor mapping.
2017	*
2018	* @returns 0 (continue enum)
2019	* @param pNode Pointer to a PGMVIRTHANDLER node.
2020	* @param pvUser Pointer to the offDelta. This is a pointer to the delta since we're
2021	* not certain the delta will fit in a void pointer for all possible configs.
2022	*/
2023	static DECLCALLBACK(int) pgmR3RelocateHyperVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser)
2024	{
2025	PPGMVIRTHANDLER pHandler = (PPGMVIRTHANDLER)pNode;
2026	RTGCINTPTR offDelta = *(PRTGCINTPTR)pvUser;
2027	Assert(pHandler->enmType == PGMVIRTHANDLERTYPE_HYPERVISOR);
2028	Assert(pHandler->pfnHandlerRC);
2029	pHandler->pfnHandlerRC += offDelta;
2030	return 0;
2031	}
2032
2033
2034	/**
2035	* The VM is being reset.
2036	*
2037	* For the PGM component this means that any PD write monitors
2038	* needs to be removed.
2039	*
2040	* @param pVM VM handle.
2041	*/
2042	VMMR3DECL(void) PGMR3Reset(PVM pVM)
2043	{
2044	LogFlow(("PGMR3Reset:\n"));
2045	VM_ASSERT_EMT(pVM);
2046
2047	pgmLock(pVM);
2048
2049	/*
2050	* Unfix any fixed mappings and disable CR3 monitoring.
2051	*/
2052	pVM->pgm.s.fMappingsFixed = false;
2053	pVM->pgm.s.GCPtrMappingFixed = 0;
2054	pVM->pgm.s.cbMappingFixed = 0;
2055
2056	/* Exit the guest paging mode before the pgm pool gets reset.
2057	* Important to clean up the amd64 case.
2058	*/
2059	int rc = PGM_GST_PFN(Exit, pVM)(pVM);
2060	AssertRC(rc);
2061	#ifdef DEBUG
2062	DBGFR3InfoLog(pVM, "mappings", NULL);
2063	DBGFR3InfoLog(pVM, "handlers", "all nostat");
2064	#endif
2065
2066	/*
2067	* Reset the shadow page pool.
2068	*/
2069	pgmR3PoolReset(pVM);
2070
2071	/*
2072	* Re-init other members.
2073	*/
2074	pVM->pgm.s.fA20Enabled = true;
2075
2076	/*
2077	* Clear the FFs PGM owns.
2078	*/
2079	VM_FF_CLEAR(pVM, VM_FF_PGM_SYNC_CR3);
2080	VM_FF_CLEAR(pVM, VM_FF_PGM_SYNC_CR3_NON_GLOBAL);
2081
2082	/*
2083	* Reset (zero) RAM pages.
2084	*/
2085	rc = pgmR3PhysRamReset(pVM);
2086	if (RT_SUCCESS(rc))
2087	{
2088	#ifdef VBOX_WITH_NEW_PHYS_CODE
2089	/*
2090	* Reset (zero) shadow ROM pages.
2091	*/
2092	rc = pgmR3PhysRomReset(pVM);
2093	#endif
2094	if (RT_SUCCESS(rc))
2095	{
2096	/*
2097	* Switch mode back to real mode.
2098	*/
2099	rc = PGMR3ChangeMode(pVM, PGMMODE_REAL);
2100	STAM_REL_COUNTER_RESET(&pVM->pgm.s.cGuestModeChanges);
2101	}
2102	}
2103
2104	pgmUnlock(pVM);
2105	//return rc;
2106	AssertReleaseRC(rc);
2107	}
2108
2109
2110	#ifdef VBOX_STRICT
2111	/**
2112	* VM state change callback for clearing fNoMorePhysWrites after
2113	* a snapshot has been created.
2114	*/
2115	static DECLCALLBACK(void) pgmR3ResetNoMorePhysWritesFlag(PVM pVM, VMSTATE enmState, VMSTATE enmOldState, void *pvUser)
2116	{
2117	if (enmState == VMSTATE_RUNNING)
2118	pVM->pgm.s.fNoMorePhysWrites = false;
2119	}
2120	#endif
2121
2122
2123	/**
2124	* Terminates the PGM.
2125	*
2126	* @returns VBox status code.
2127	* @param pVM Pointer to VM structure.
2128	*/
2129	VMMR3DECL(int) PGMR3Term(PVM pVM)
2130	{
2131	PGMDeregisterStringFormatTypes();
2132	return PDMR3CritSectDelete(&pVM->pgm.s.CritSect);
2133	}
2134
2135
2136	/**
2137	* Terminates the per-VCPU PGM.
2138	*
2139	* Termination means cleaning up and freeing all resources,
2140	* the VM it self is at this point powered off or suspended.
2141	*
2142	* @returns VBox status code.
2143	* @param pVM The VM to operate on.
2144	*/
2145	VMMR3DECL(int) PGMR3TermCPU(PVM pVM)
2146	{
2147	return 0;
2148	}
2149
2150
2151	/**
2152	* Execute state save operation.
2153	*
2154	* @returns VBox status code.
2155	* @param pVM VM Handle.
2156	* @param pSSM SSM operation handle.
2157	*/
2158	static DECLCALLBACK(int) pgmR3Save(PVM pVM, PSSMHANDLE pSSM)
2159	{
2160	#ifdef VBOX_WITH_NEW_PHYS_CODE
2161	AssertReleaseFailedReturn(VERR_NOT_IMPLEMENTED); /** @todo */
2162	#else
2163	PPGM pPGM = &pVM->pgm.s;
2164
2165	/* No more writes to physical memory after this point! */
2166	pVM->pgm.s.fNoMorePhysWrites = true;
2167
2168	/*
2169	* Save basic data (required / unaffected by relocation).
2170	*/
2171	#if 1
2172	SSMR3PutBool(pSSM, pPGM->fMappingsFixed);
2173	#else
2174	SSMR3PutUInt(pSSM, pPGM->fMappingsFixed);
2175	#endif
2176	SSMR3PutGCPtr(pSSM, pPGM->GCPtrMappingFixed);
2177	SSMR3PutU32(pSSM, pPGM->cbMappingFixed);
2178	SSMR3PutUInt(pSSM, pPGM->cbRamSize);
2179	SSMR3PutGCPhys(pSSM, pPGM->GCPhysA20Mask);
2180	SSMR3PutUInt(pSSM, pPGM->fA20Enabled);
2181	SSMR3PutUInt(pSSM, pPGM->fSyncFlags);
2182	SSMR3PutUInt(pSSM, pPGM->enmGuestMode);
2183	SSMR3PutU32(pSSM, ~0); /* Separator. */
2184
2185	/*
2186	* The guest mappings.
2187	*/
2188	uint32_t i = 0;
2189	for (PPGMMAPPING pMapping = pPGM->pMappingsR3; pMapping; pMapping = pMapping->pNextR3, i++)
2190	{
2191	SSMR3PutU32(pSSM, i);
2192	SSMR3PutStrZ(pSSM, pMapping->pszDesc); /* This is the best unique id we have... */
2193	SSMR3PutGCPtr(pSSM, pMapping->GCPtr);
2194	SSMR3PutGCUIntPtr(pSSM, pMapping->cPTs);
2195	/* flags are done by the mapping owners! */
2196	}
2197	SSMR3PutU32(pSSM, ~0); /* terminator. */
2198
2199	/*
2200	* Ram range flags and bits.
2201	*/
2202	i = 0;
2203	for (PPGMRAMRANGE pRam = pPGM->pRamRangesR3; pRam; pRam = pRam->pNextR3, i++)
2204	{
2205	/** @todo MMIO ranges may move (PCI reconfig), we currently assume they don't. */
2206
2207	SSMR3PutU32(pSSM, i);
2208	SSMR3PutGCPhys(pSSM, pRam->GCPhys);
2209	SSMR3PutGCPhys(pSSM, pRam->GCPhysLast);
2210	SSMR3PutGCPhys(pSSM, pRam->cb);
2211	SSMR3PutU8(pSSM, !!pRam->pvR3); /* boolean indicating memory or not. */
2212
2213	/* Flags. */
2214	const unsigned cPages = pRam->cb >> PAGE_SHIFT;
2215	for (unsigned iPage = 0; iPage < cPages; iPage++)
2216	SSMR3PutU16(pSSM, (uint16_t)(pRam->aPages[iPage].HCPhys & ~X86_PTE_PAE_PG_MASK)); /** @todo PAGE FLAGS */
2217
2218	/* any memory associated with the range. */
2219	if (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)
2220	{
2221	for (unsigned iChunk = 0; iChunk < (pRam->cb >> PGM_DYNAMIC_CHUNK_SHIFT); iChunk++)
2222	{
2223	if (pRam->paChunkR3Ptrs[iChunk])
2224	{
2225	SSMR3PutU8(pSSM, 1); /* chunk present */
2226	SSMR3PutMem(pSSM, (void *)pRam->paChunkR3Ptrs[iChunk], PGM_DYNAMIC_CHUNK_SIZE);
2227	}
2228	else
2229	SSMR3PutU8(pSSM, 0); /* no chunk present */
2230	}
2231	}
2232	else if (pRam->pvR3)
2233	{
2234	int rc = SSMR3PutMem(pSSM, pRam->pvR3, pRam->cb);
2235	if (RT_FAILURE(rc))
2236	{
2237	Log(("pgmR3Save: SSMR3PutMem(, %p, %#x) -> %Rrc\n", pRam->pvR3, pRam->cb, rc));
2238	return rc;
2239	}
2240	}
2241	}
2242	#endif /* !VBOX_WITH_NEW_PHYS_CODE */
2243	return SSMR3PutU32(pSSM, ~0); /* terminator. */
2244	}
2245
2246
2247	/**
2248	* Execute state load operation.
2249	*
2250	* @returns VBox status code.
2251	* @param pVM VM Handle.
2252	* @param pSSM SSM operation handle.
2253	* @param u32Version Data layout version.
2254	*/
2255	static DECLCALLBACK(int) pgmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version)
2256	{
2257	#ifdef VBOX_WITH_NEW_PHYS_CODE
2258	AssertReleaseFailedReturn(VERR_NOT_IMPLEMENTED); /** @todo */
2259	#else
2260	/*
2261	* Validate version.
2262	*/
2263	if (u32Version != PGM_SAVED_STATE_VERSION)
2264	{
2265	AssertMsgFailed(("pgmR3Load: Invalid version u32Version=%d (current %d)!\n", u32Version, PGM_SAVED_STATE_VERSION));
2266	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
2267	}
2268
2269	/*
2270	* Call the reset function to make sure all the memory is cleared.
2271	*/
2272	PGMR3Reset(pVM);
2273
2274	/*
2275	* Load basic data (required / unaffected by relocation).
2276	*/
2277	PPGM pPGM = &pVM->pgm.s;
2278	#if 1
2279	SSMR3GetBool(pSSM, &pPGM->fMappingsFixed);
2280	#else
2281	uint32_t u;
2282	SSMR3GetU32(pSSM, &u);
2283	pPGM->fMappingsFixed = u;
2284	#endif
2285	SSMR3GetGCPtr(pSSM, &pPGM->GCPtrMappingFixed);
2286	SSMR3GetU32(pSSM, &pPGM->cbMappingFixed);
2287
2288	RTUINT cbRamSize;
2289	int rc = SSMR3GetU32(pSSM, &cbRamSize);
2290	if (RT_FAILURE(rc))
2291	return rc;
2292	if (cbRamSize != pPGM->cbRamSize)
2293	return VERR_SSM_LOAD_MEMORY_SIZE_MISMATCH;
2294	SSMR3GetGCPhys(pSSM, &pPGM->GCPhysA20Mask);
2295	SSMR3GetUInt(pSSM, &pPGM->fA20Enabled);
2296	SSMR3GetUInt(pSSM, &pPGM->fSyncFlags);
2297	RTUINT uGuestMode;
2298	SSMR3GetUInt(pSSM, &uGuestMode);
2299	pPGM->enmGuestMode = (PGMMODE)uGuestMode;
2300
2301	/* check separator. */
2302	uint32_t u32Sep;
2303	SSMR3GetU32(pSSM, &u32Sep);
2304	if (RT_FAILURE(rc))
2305	return rc;
2306	if (u32Sep != (uint32_t)~0)
2307	{
2308	AssertMsgFailed(("u32Sep=%#x (first)\n", u32Sep));
2309	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2310	}
2311
2312	/*
2313	* The guest mappings.
2314	*/
2315	uint32_t i = 0;
2316	for (;; i++)
2317	{
2318	/* Check the seqence number / separator. */
2319	rc = SSMR3GetU32(pSSM, &u32Sep);
2320	if (RT_FAILURE(rc))
2321	return rc;
2322	if (u32Sep == ~0U)
2323	break;
2324	if (u32Sep != i)
2325	{
2326	AssertMsgFailed(("u32Sep=%#x (last)\n", u32Sep));
2327	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2328	}
2329
2330	/* get the mapping details. */
2331	char szDesc[256];
2332	szDesc[0] = '\0';
2333	rc = SSMR3GetStrZ(pSSM, szDesc, sizeof(szDesc));
2334	if (RT_FAILURE(rc))
2335	return rc;
2336	RTGCPTR GCPtr;
2337	SSMR3GetGCPtr(pSSM, &GCPtr);
2338	RTGCPTR cPTs;
2339	rc = SSMR3GetGCUIntPtr(pSSM, &cPTs);
2340	if (RT_FAILURE(rc))
2341	return rc;
2342
2343	/* find matching range. */
2344	PPGMMAPPING pMapping;
2345	for (pMapping = pPGM->pMappingsR3; pMapping; pMapping = pMapping->pNextR3)
2346	if ( pMapping->cPTs == cPTs
2347	&& !strcmp(pMapping->pszDesc, szDesc))
2348	break;
2349	if (!pMapping)
2350	{
2351	LogRel(("Couldn't find mapping: cPTs=%#x szDesc=%s (GCPtr=%RGv)\n",
2352	cPTs, szDesc, GCPtr));
2353	AssertFailed();
2354	return VERR_SSM_LOAD_CONFIG_MISMATCH;
2355	}
2356
2357	/* relocate it. */
2358	if (pMapping->GCPtr != GCPtr)
2359	{
2360	AssertMsg((GCPtr >> X86_PD_SHIFT << X86_PD_SHIFT) == GCPtr, ("GCPtr=%RGv\n", GCPtr));
2361	pgmR3MapRelocate(pVM, pMapping, pMapping->GCPtr, GCPtr);
2362	}
2363	else
2364	Log(("pgmR3Load: '%s' needed no relocation (%RGv)\n", szDesc, GCPtr));
2365	}
2366
2367	/*
2368	* Ram range flags and bits.
2369	*/
2370	i = 0;
2371	for (PPGMRAMRANGE pRam = pPGM->pRamRangesR3; pRam; pRam = pRam->pNextR3, i++)
2372	{
2373	/** @todo MMIO ranges may move (PCI reconfig), we currently assume they don't. */
2374	/* Check the seqence number / separator. */
2375	rc = SSMR3GetU32(pSSM, &u32Sep);
2376	if (RT_FAILURE(rc))
2377	return rc;
2378	if (u32Sep == ~0U)
2379	break;
2380	if (u32Sep != i)
2381	{
2382	AssertMsgFailed(("u32Sep=%#x (last)\n", u32Sep));
2383	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2384	}
2385
2386	/* Get the range details. */
2387	RTGCPHYS GCPhys;
2388	SSMR3GetGCPhys(pSSM, &GCPhys);
2389	RTGCPHYS GCPhysLast;
2390	SSMR3GetGCPhys(pSSM, &GCPhysLast);
2391	RTGCPHYS cb;
2392	SSMR3GetGCPhys(pSSM, &cb);
2393	uint8_t fHaveBits;
2394	rc = SSMR3GetU8(pSSM, &fHaveBits);
2395	if (RT_FAILURE(rc))
2396	return rc;
2397	if (fHaveBits & ~1)
2398	{
2399	AssertMsgFailed(("u32Sep=%#x (last)\n", u32Sep));
2400	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2401	}
2402
2403	/* Match it up with the current range. */
2404	if ( GCPhys != pRam->GCPhys
2405	\|\| GCPhysLast != pRam->GCPhysLast
2406	\|\| cb != pRam->cb
2407	\|\| fHaveBits != !!pRam->pvR3)
2408	{
2409	LogRel(("Ram range: %RGp-%RGp %RGp bytes %s\n"
2410	"State : %RGp-%RGp %RGp bytes %s\n",
2411	pRam->GCPhys, pRam->GCPhysLast, pRam->cb, pRam->pvR3 ? "bits" : "nobits",
2412	GCPhys, GCPhysLast, cb, fHaveBits ? "bits" : "nobits"));
2413	/*
2414	* If we're loading a state for debugging purpose, don't make a fuss if
2415	* the MMIO[2] and ROM stuff isn't 100% right, just skip the mismatches.
2416	*/
2417	if ( SSMR3HandleGetAfter(pSSM) != SSMAFTER_DEBUG_IT
2418	\|\| GCPhys < 8 * _1M)
2419	AssertFailedReturn(VERR_SSM_LOAD_CONFIG_MISMATCH);
2420
2421	RTGCPHYS cPages = ((GCPhysLast - GCPhys) + 1) >> PAGE_SHIFT;
2422	while (cPages-- > 0)
2423	{
2424	uint16_t u16Ignore;
2425	SSMR3GetU16(pSSM, &u16Ignore);
2426	}
2427	continue;
2428	}
2429
2430	/* Flags. */
2431	const unsigned cPages = pRam->cb >> PAGE_SHIFT;
2432	for (unsigned iPage = 0; iPage < cPages; iPage++)
2433	{
2434	uint16_t u16 = 0;
2435	SSMR3GetU16(pSSM, &u16);
2436	u16 &= PAGE_OFFSET_MASK & ~( RT_BIT(4) \| RT_BIT(5) \| RT_BIT(6)
2437	\| RT_BIT(7) \| RT_BIT(8) \| RT_BIT(9) \| RT_BIT(10) );
2438	// &= MM_RAM_FLAGS_DYNAMIC_ALLOC \| MM_RAM_FLAGS_RESERVED \| MM_RAM_FLAGS_ROM \| MM_RAM_FLAGS_MMIO \| MM_RAM_FLAGS_MMIO2
2439	pRam->aPages[iPage].HCPhys = PGM_PAGE_GET_HCPHYS(&pRam->aPages[iPage]) \| (RTHCPHYS)u16; /** @todo PAGE FLAGS */
2440	}
2441
2442	/* any memory associated with the range. */
2443	if (pRam->fFlags & MM_RAM_FLAGS_DYNAMIC_ALLOC)
2444	{
2445	for (unsigned iChunk = 0; iChunk < (pRam->cb >> PGM_DYNAMIC_CHUNK_SHIFT); iChunk++)
2446	{
2447	uint8_t fValidChunk;
2448
2449	rc = SSMR3GetU8(pSSM, &fValidChunk);
2450	if (RT_FAILURE(rc))
2451	return rc;
2452	if (fValidChunk > 1)
2453	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2454
2455	if (fValidChunk)
2456	{
2457	if (!pRam->paChunkR3Ptrs[iChunk])
2458	{
2459	rc = pgmr3PhysGrowRange(pVM, pRam->GCPhys + iChunk * PGM_DYNAMIC_CHUNK_SIZE);
2460	if (RT_FAILURE(rc))
2461	return rc;
2462	}
2463	Assert(pRam->paChunkR3Ptrs[iChunk]);
2464
2465	SSMR3GetMem(pSSM, (void *)pRam->paChunkR3Ptrs[iChunk], PGM_DYNAMIC_CHUNK_SIZE);
2466	}
2467	/* else nothing to do */
2468	}
2469	}
2470	else if (pRam->pvR3)
2471	{
2472	int rc = SSMR3GetMem(pSSM, pRam->pvR3, pRam->cb);
2473	if (RT_FAILURE(rc))
2474	{
2475	Log(("pgmR3Save: SSMR3GetMem(, %p, %#x) -> %Rrc\n", pRam->pvR3, pRam->cb, rc));
2476	return rc;
2477	}
2478	}
2479	}
2480
2481	/*
2482	* We require a full resync now.
2483	*/
2484	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3_NON_GLOBAL);
2485	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
2486	pPGM->fSyncFlags \|= PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL;
2487	pPGM->fPhysCacheFlushPending = true;
2488	pgmR3HandlerPhysicalUpdateAll(pVM);
2489
2490	/*
2491	* Change the paging mode.
2492	*/
2493	rc = PGMR3ChangeMode(pVM, pPGM->enmGuestMode);
2494
2495	/* Restore pVM->pgm.s.GCPhysCR3. */
2496	Assert(pVM->pgm.s.GCPhysCR3 == NIL_RTGCPHYS);
2497	RTGCPHYS GCPhysCR3 = CPUMGetGuestCR3(pVM);
2498	if ( pVM->pgm.s.enmGuestMode == PGMMODE_PAE
2499	\|\| pVM->pgm.s.enmGuestMode == PGMMODE_PAE_NX
2500	\|\| pVM->pgm.s.enmGuestMode == PGMMODE_AMD64
2501	\|\| pVM->pgm.s.enmGuestMode == PGMMODE_AMD64_NX)
2502	GCPhysCR3 = (GCPhysCR3 & X86_CR3_PAE_PAGE_MASK);
2503	else
2504	GCPhysCR3 = (GCPhysCR3 & X86_CR3_PAGE_MASK);
2505	pVM->pgm.s.GCPhysCR3 = GCPhysCR3;
2506
2507	return rc;
2508	#endif /* !VBOX_WITH_NEW_PHYS_CODE */
2509	}
2510
2511
2512	/**
2513	* Show paging mode.
2514	*
2515	* @param pVM VM Handle.
2516	* @param pHlp The info helpers.
2517	* @param pszArgs "all" (default), "guest", "shadow" or "host".
2518	*/
2519	static DECLCALLBACK(void) pgmR3InfoMode(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2520	{
2521	/* digest argument. */
2522	bool fGuest, fShadow, fHost;
2523	if (pszArgs)
2524	pszArgs = RTStrStripL(pszArgs);
2525	if (!pszArgs \|\| !*pszArgs \|\| strstr(pszArgs, "all"))
2526	fShadow = fHost = fGuest = true;
2527	else
2528	{
2529	fShadow = fHost = fGuest = false;
2530	if (strstr(pszArgs, "guest"))
2531	fGuest = true;
2532	if (strstr(pszArgs, "shadow"))
2533	fShadow = true;
2534	if (strstr(pszArgs, "host"))
2535	fHost = true;
2536	}
2537
2538	/* print info. */
2539	if (fGuest)
2540	pHlp->pfnPrintf(pHlp, "Guest paging mode: %s, changed %RU64 times, A20 %s\n",
2541	PGMGetModeName(pVM->pgm.s.enmGuestMode), pVM->pgm.s.cGuestModeChanges.c,
2542	pVM->pgm.s.fA20Enabled ? "enabled" : "disabled");
2543	if (fShadow)
2544	pHlp->pfnPrintf(pHlp, "Shadow paging mode: %s\n", PGMGetModeName(pVM->pgm.s.enmShadowMode));
2545	if (fHost)
2546	{
2547	const char *psz;
2548	switch (pVM->pgm.s.enmHostMode)
2549	{
2550	case SUPPAGINGMODE_INVALID: psz = "invalid"; break;
2551	case SUPPAGINGMODE_32_BIT: psz = "32-bit"; break;
2552	case SUPPAGINGMODE_32_BIT_GLOBAL: psz = "32-bit+G"; break;
2553	case SUPPAGINGMODE_PAE: psz = "PAE"; break;
2554	case SUPPAGINGMODE_PAE_GLOBAL: psz = "PAE+G"; break;
2555	case SUPPAGINGMODE_PAE_NX: psz = "PAE+NX"; break;
2556	case SUPPAGINGMODE_PAE_GLOBAL_NX: psz = "PAE+G+NX"; break;
2557	case SUPPAGINGMODE_AMD64: psz = "AMD64"; break;
2558	case SUPPAGINGMODE_AMD64_GLOBAL: psz = "AMD64+G"; break;
2559	case SUPPAGINGMODE_AMD64_NX: psz = "AMD64+NX"; break;
2560	case SUPPAGINGMODE_AMD64_GLOBAL_NX: psz = "AMD64+G+NX"; break;
2561	default: psz = "unknown"; break;
2562	}
2563	pHlp->pfnPrintf(pHlp, "Host paging mode: %s\n", psz);
2564	}
2565	}
2566
2567
2568	/**
2569	* Dump registered MMIO ranges to the log.
2570	*
2571	* @param pVM VM Handle.
2572	* @param pHlp The info helpers.
2573	* @param pszArgs Arguments, ignored.
2574	*/
2575	static DECLCALLBACK(void) pgmR3PhysInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2576	{
2577	NOREF(pszArgs);
2578	pHlp->pfnPrintf(pHlp,
2579	"RAM ranges (pVM=%p)\n"
2580	"%.s %.s\n",
2581	pVM,
2582	sizeof(RTGCPHYS) * 4 + 1, "GC Phys Range ",
2583	sizeof(RTHCPTR) * 2, "pvHC ");
2584
2585	for (PPGMRAMRANGE pCur = pVM->pgm.s.pRamRangesR3; pCur; pCur = pCur->pNextR3)
2586	pHlp->pfnPrintf(pHlp,
2587	"%RGp-%RGp %RHv %s\n",
2588	pCur->GCPhys,
2589	pCur->GCPhysLast,
2590	pCur->pvR3,
2591	pCur->pszDesc);
2592	}
2593
2594	/**
2595	* Dump the page directory to the log.
2596	*
2597	* @param pVM VM Handle.
2598	* @param pHlp The info helpers.
2599	* @param pszArgs Arguments, ignored.
2600	*/
2601	static DECLCALLBACK(void) pgmR3InfoCr3(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2602	{
2603	/** @todo fix this! Convert the PGMR3DumpHierarchyHC functions to do guest stuff. */
2604	/* Big pages supported? */
2605	const bool fPSE = !!(CPUMGetGuestCR4(pVM) & X86_CR4_PSE);
2606
2607	/* Global pages supported? */
2608	const bool fPGE = !!(CPUMGetGuestCR4(pVM) & X86_CR4_PGE);
2609
2610	NOREF(pszArgs);
2611
2612	/*
2613	* Get page directory addresses.
2614	*/
2615	PX86PD pPDSrc = pVM->pgm.s.pGst32BitPdR3;
2616	Assert(pPDSrc);
2617	Assert(PGMPhysGCPhys2R3PtrAssert(pVM, (RTGCPHYS)(CPUMGetGuestCR3(pVM) & X86_CR3_PAGE_MASK), sizeof(*pPDSrc)) == pPDSrc);
2618
2619	/*
2620	* Iterate the page directory.
2621	*/
2622	for (unsigned iPD = 0; iPD < RT_ELEMENTS(pPDSrc->a); iPD++)
2623	{
2624	X86PDE PdeSrc = pPDSrc->a[iPD];
2625	if (PdeSrc.n.u1Present)
2626	{
2627	if (PdeSrc.b.u1Size && fPSE)
2628	pHlp->pfnPrintf(pHlp,
2629	"%04X - %RGp P=%d U=%d RW=%d G=%d - BIG\n",
2630	iPD,
2631	pgmGstGet4MBPhysPage(&pVM->pgm.s, PdeSrc),
2632	PdeSrc.b.u1Present, PdeSrc.b.u1User, PdeSrc.b.u1Write, PdeSrc.b.u1Global && fPGE);
2633	else
2634	pHlp->pfnPrintf(pHlp,
2635	"%04X - %RGp P=%d U=%d RW=%d [G=%d]\n",
2636	iPD,
2637	(RTGCPHYS)(PdeSrc.u & X86_PDE_PG_MASK),
2638	PdeSrc.n.u1Present, PdeSrc.n.u1User, PdeSrc.n.u1Write, PdeSrc.b.u1Global && fPGE);
2639	}
2640	}
2641	}
2642
2643
2644	/**
2645	* Serivce a VMMCALLHOST_PGM_LOCK call.
2646	*
2647	* @returns VBox status code.
2648	* @param pVM The VM handle.
2649	*/
2650	VMMR3DECL(int) PGMR3LockCall(PVM pVM)
2651	{
2652	int rc = PDMR3CritSectEnterEx(&pVM->pgm.s.CritSect, true /* fHostCall */);
2653	AssertRC(rc);
2654	return rc;
2655	}
2656
2657
2658	/**
2659	* Converts a PGMMODE value to a PGM_TYPE_* \#define.
2660	*
2661	* @returns PGM_TYPE_*.
2662	* @param pgmMode The mode value to convert.
2663	*/
2664	DECLINLINE(unsigned) pgmModeToType(PGMMODE pgmMode)
2665	{
2666	switch (pgmMode)
2667	{
2668	case PGMMODE_REAL: return PGM_TYPE_REAL;
2669	case PGMMODE_PROTECTED: return PGM_TYPE_PROT;
2670	case PGMMODE_32_BIT: return PGM_TYPE_32BIT;
2671	case PGMMODE_PAE:
2672	case PGMMODE_PAE_NX: return PGM_TYPE_PAE;
2673	case PGMMODE_AMD64:
2674	case PGMMODE_AMD64_NX: return PGM_TYPE_AMD64;
2675	case PGMMODE_NESTED: return PGM_TYPE_NESTED;
2676	case PGMMODE_EPT: return PGM_TYPE_EPT;
2677	default:
2678	AssertFatalMsgFailed(("pgmMode=%d\n", pgmMode));
2679	}
2680	}
2681
2682
2683	/**
2684	* Gets the index into the paging mode data array of a SHW+GST mode.
2685	*
2686	* @returns PGM::paPagingData index.
2687	* @param uShwType The shadow paging mode type.
2688	* @param uGstType The guest paging mode type.
2689	*/
2690	DECLINLINE(unsigned) pgmModeDataIndex(unsigned uShwType, unsigned uGstType)
2691	{
2692	Assert(uShwType >= PGM_TYPE_32BIT && uShwType <= PGM_TYPE_MAX);
2693	Assert(uGstType >= PGM_TYPE_REAL && uGstType <= PGM_TYPE_AMD64);
2694	return (uShwType - PGM_TYPE_32BIT) * (PGM_TYPE_AMD64 - PGM_TYPE_REAL + 1)
2695	+ (uGstType - PGM_TYPE_REAL);
2696	}
2697
2698
2699	/**
2700	* Gets the index into the paging mode data array of a SHW+GST mode.
2701	*
2702	* @returns PGM::paPagingData index.
2703	* @param enmShw The shadow paging mode.
2704	* @param enmGst The guest paging mode.
2705	*/
2706	DECLINLINE(unsigned) pgmModeDataIndexByMode(PGMMODE enmShw, PGMMODE enmGst)
2707	{
2708	Assert(enmShw >= PGMMODE_32_BIT && enmShw <= PGMMODE_MAX);
2709	Assert(enmGst > PGMMODE_INVALID && enmGst < PGMMODE_MAX);
2710	return pgmModeDataIndex(pgmModeToType(enmShw), pgmModeToType(enmGst));
2711	}
2712
2713
2714	/**
2715	* Calculates the max data index.
2716	* @returns The number of entries in the paging data array.
2717	*/
2718	DECLINLINE(unsigned) pgmModeDataMaxIndex(void)
2719	{
2720	return pgmModeDataIndex(PGM_TYPE_MAX, PGM_TYPE_AMD64) + 1;
2721	}
2722
2723
2724	/**
2725	* Initializes the paging mode data kept in PGM::paModeData.
2726	*
2727	* @param pVM The VM handle.
2728	* @param fResolveGCAndR0 Indicate whether or not GC and Ring-0 symbols can be resolved now.
2729	* This is used early in the init process to avoid trouble with PDM
2730	* not being initialized yet.
2731	*/
2732	static int pgmR3ModeDataInit(PVM pVM, bool fResolveGCAndR0)
2733	{
2734	PPGMMODEDATA pModeData;
2735	int rc;
2736
2737	/*
2738	* Allocate the array on the first call.
2739	*/
2740	if (!pVM->pgm.s.paModeData)
2741	{
2742	pVM->pgm.s.paModeData = (PPGMMODEDATA)MMR3HeapAllocZ(pVM, MM_TAG_PGM, sizeof(PGMMODEDATA) * pgmModeDataMaxIndex());
2743	AssertReturn(pVM->pgm.s.paModeData, VERR_NO_MEMORY);
2744	}
2745
2746	/*
2747	* Initialize the array entries.
2748	*/
2749	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_32BIT, PGM_TYPE_REAL)];
2750	pModeData->uShwType = PGM_TYPE_32BIT;
2751	pModeData->uGstType = PGM_TYPE_REAL;
2752	rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2753	rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2754	rc = PGM_BTH_NAME_32BIT_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2755
2756	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_32BIT, PGMMODE_PROTECTED)];
2757	pModeData->uShwType = PGM_TYPE_32BIT;
2758	pModeData->uGstType = PGM_TYPE_PROT;
2759	rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2760	rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2761	rc = PGM_BTH_NAME_32BIT_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2762
2763	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_32BIT, PGM_TYPE_32BIT)];
2764	pModeData->uShwType = PGM_TYPE_32BIT;
2765	pModeData->uGstType = PGM_TYPE_32BIT;
2766	rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2767	rc = PGM_GST_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2768	rc = PGM_BTH_NAME_32BIT_32BIT(InitData)(pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2769
2770	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_REAL)];
2771	pModeData->uShwType = PGM_TYPE_PAE;
2772	pModeData->uGstType = PGM_TYPE_REAL;
2773	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2774	rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2775	rc = PGM_BTH_NAME_PAE_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2776
2777	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_PROT)];
2778	pModeData->uShwType = PGM_TYPE_PAE;
2779	pModeData->uGstType = PGM_TYPE_PROT;
2780	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2781	rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2782	rc = PGM_BTH_NAME_PAE_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2783
2784	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_32BIT)];
2785	pModeData->uShwType = PGM_TYPE_PAE;
2786	pModeData->uGstType = PGM_TYPE_32BIT;
2787	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2788	rc = PGM_GST_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2789	rc = PGM_BTH_NAME_PAE_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2790
2791	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_PAE)];
2792	pModeData->uShwType = PGM_TYPE_PAE;
2793	pModeData->uGstType = PGM_TYPE_PAE;
2794	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2795	rc = PGM_GST_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2796	rc = PGM_BTH_NAME_PAE_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2797
2798	#ifdef VBOX_WITH_64_BITS_GUESTS
2799	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_AMD64, PGM_TYPE_AMD64)];
2800	pModeData->uShwType = PGM_TYPE_AMD64;
2801	pModeData->uGstType = PGM_TYPE_AMD64;
2802	rc = PGM_SHW_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2803	rc = PGM_GST_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2804	rc = PGM_BTH_NAME_AMD64_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2805	#endif
2806
2807	/* The nested paging mode. */
2808	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_REAL)];
2809	pModeData->uShwType = PGM_TYPE_NESTED;
2810	pModeData->uGstType = PGM_TYPE_REAL;
2811	rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2812	rc = PGM_BTH_NAME_NESTED_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2813
2814	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGMMODE_PROTECTED)];
2815	pModeData->uShwType = PGM_TYPE_NESTED;
2816	pModeData->uGstType = PGM_TYPE_PROT;
2817	rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2818	rc = PGM_BTH_NAME_NESTED_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2819
2820	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_32BIT)];
2821	pModeData->uShwType = PGM_TYPE_NESTED;
2822	pModeData->uGstType = PGM_TYPE_32BIT;
2823	rc = PGM_GST_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2824	rc = PGM_BTH_NAME_NESTED_32BIT(InitData)(pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2825
2826	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_PAE)];
2827	pModeData->uShwType = PGM_TYPE_NESTED;
2828	pModeData->uGstType = PGM_TYPE_PAE;
2829	rc = PGM_GST_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2830	rc = PGM_BTH_NAME_NESTED_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2831
2832	#ifdef VBOX_WITH_64_BITS_GUESTS
2833	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_AMD64)];
2834	pModeData->uShwType = PGM_TYPE_NESTED;
2835	pModeData->uGstType = PGM_TYPE_AMD64;
2836	rc = PGM_GST_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2837	rc = PGM_BTH_NAME_NESTED_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2838	#endif
2839
2840	/* The shadow part of the nested callback mode depends on the host paging mode (AMD-V only). */
2841	switch (pVM->pgm.s.enmHostMode)
2842	{
2843	#if HC_ARCH_BITS == 32
2844	case SUPPAGINGMODE_32_BIT:
2845	case SUPPAGINGMODE_32_BIT_GLOBAL:
2846	for (unsigned i = PGM_TYPE_REAL; i <= PGM_TYPE_PAE; i++)
2847	{
2848	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, i)];
2849	rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2850	}
2851	# ifdef VBOX_WITH_64_BITS_GUESTS
2852	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_AMD64)];
2853	rc = PGM_SHW_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2854	# endif
2855	break;
2856
2857	case SUPPAGINGMODE_PAE:
2858	case SUPPAGINGMODE_PAE_NX:
2859	case SUPPAGINGMODE_PAE_GLOBAL:
2860	case SUPPAGINGMODE_PAE_GLOBAL_NX:
2861	for (unsigned i = PGM_TYPE_REAL; i <= PGM_TYPE_PAE; i++)
2862	{
2863	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, i)];
2864	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2865	}
2866	# ifdef VBOX_WITH_64_BITS_GUESTS
2867	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_AMD64)];
2868	rc = PGM_SHW_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2869	# endif
2870	break;
2871	#endif /* HC_ARCH_BITS == 32 */
2872
2873	#if HC_ARCH_BITS == 64 \|\| defined(RT_OS_DARWIN)
2874	case SUPPAGINGMODE_AMD64:
2875	case SUPPAGINGMODE_AMD64_GLOBAL:
2876	case SUPPAGINGMODE_AMD64_NX:
2877	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
2878	# ifdef VBOX_WITH_64_BITS_GUESTS
2879	for (unsigned i = PGM_TYPE_REAL; i <= PGM_TYPE_AMD64; i++)
2880	# else
2881	for (unsigned i = PGM_TYPE_REAL; i <= PGM_TYPE_PAE; i++)
2882	# endif
2883	{
2884	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, i)];
2885	rc = PGM_SHW_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2886	}
2887	break;
2888	#endif /* HC_ARCH_BITS == 64 \|\| RT_OS_DARWIN */
2889
2890	default:
2891	AssertFailed();
2892	break;
2893	}
2894
2895	/* Extended paging (EPT) / Intel VT-x */
2896	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_REAL)];
2897	pModeData->uShwType = PGM_TYPE_EPT;
2898	pModeData->uGstType = PGM_TYPE_REAL;
2899	rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2900	rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2901	rc = PGM_BTH_NAME_EPT_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2902
2903	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_PROT)];
2904	pModeData->uShwType = PGM_TYPE_EPT;
2905	pModeData->uGstType = PGM_TYPE_PROT;
2906	rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2907	rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2908	rc = PGM_BTH_NAME_EPT_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2909
2910	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_32BIT)];
2911	pModeData->uShwType = PGM_TYPE_EPT;
2912	pModeData->uGstType = PGM_TYPE_32BIT;
2913	rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2914	rc = PGM_GST_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2915	rc = PGM_BTH_NAME_EPT_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2916
2917	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_PAE)];
2918	pModeData->uShwType = PGM_TYPE_EPT;
2919	pModeData->uGstType = PGM_TYPE_PAE;
2920	rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2921	rc = PGM_GST_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2922	rc = PGM_BTH_NAME_EPT_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2923
2924	#ifdef VBOX_WITH_64_BITS_GUESTS
2925	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_AMD64)];
2926	pModeData->uShwType = PGM_TYPE_EPT;
2927	pModeData->uGstType = PGM_TYPE_AMD64;
2928	rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2929	rc = PGM_GST_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2930	rc = PGM_BTH_NAME_EPT_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2931	#endif
2932	return VINF_SUCCESS;
2933	}
2934
2935
2936	/**
2937	* Switch to different (or relocated in the relocate case) mode data.
2938	*
2939	* @param pVM The VM handle.
2940	* @param enmShw The the shadow paging mode.
2941	* @param enmGst The the guest paging mode.
2942	*/
2943	static void pgmR3ModeDataSwitch(PVM pVM, PGMMODE enmShw, PGMMODE enmGst)
2944	{
2945	PPGMMODEDATA pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndexByMode(enmShw, enmGst)];
2946
2947	Assert(pModeData->uGstType == pgmModeToType(enmGst));
2948	Assert(pModeData->uShwType == pgmModeToType(enmShw));
2949
2950	/* shadow */
2951	pVM->pgm.s.pfnR3ShwRelocate = pModeData->pfnR3ShwRelocate;
2952	pVM->pgm.s.pfnR3ShwExit = pModeData->pfnR3ShwExit;
2953	pVM->pgm.s.pfnR3ShwGetPage = pModeData->pfnR3ShwGetPage;
2954	Assert(pVM->pgm.s.pfnR3ShwGetPage);
2955	pVM->pgm.s.pfnR3ShwModifyPage = pModeData->pfnR3ShwModifyPage;
2956
2957	pVM->pgm.s.pfnRCShwGetPage = pModeData->pfnRCShwGetPage;
2958	pVM->pgm.s.pfnRCShwModifyPage = pModeData->pfnRCShwModifyPage;
2959
2960	pVM->pgm.s.pfnR0ShwGetPage = pModeData->pfnR0ShwGetPage;
2961	pVM->pgm.s.pfnR0ShwModifyPage = pModeData->pfnR0ShwModifyPage;
2962
2963
2964	/* guest */
2965	pVM->pgm.s.pfnR3GstRelocate = pModeData->pfnR3GstRelocate;
2966	pVM->pgm.s.pfnR3GstExit = pModeData->pfnR3GstExit;
2967	pVM->pgm.s.pfnR3GstGetPage = pModeData->pfnR3GstGetPage;
2968	Assert(pVM->pgm.s.pfnR3GstGetPage);
2969	pVM->pgm.s.pfnR3GstModifyPage = pModeData->pfnR3GstModifyPage;
2970	pVM->pgm.s.pfnR3GstGetPDE = pModeData->pfnR3GstGetPDE;
2971	pVM->pgm.s.pfnRCGstGetPage = pModeData->pfnRCGstGetPage;
2972	pVM->pgm.s.pfnRCGstModifyPage = pModeData->pfnRCGstModifyPage;
2973	pVM->pgm.s.pfnRCGstGetPDE = pModeData->pfnRCGstGetPDE;
2974	pVM->pgm.s.pfnR0GstGetPage = pModeData->pfnR0GstGetPage;
2975	pVM->pgm.s.pfnR0GstModifyPage = pModeData->pfnR0GstModifyPage;
2976	pVM->pgm.s.pfnR0GstGetPDE = pModeData->pfnR0GstGetPDE;
2977
2978	/* both */
2979	pVM->pgm.s.pfnR3BthRelocate = pModeData->pfnR3BthRelocate;
2980	pVM->pgm.s.pfnR3BthInvalidatePage = pModeData->pfnR3BthInvalidatePage;
2981	pVM->pgm.s.pfnR3BthSyncCR3 = pModeData->pfnR3BthSyncCR3;
2982	Assert(pVM->pgm.s.pfnR3BthSyncCR3);
2983	pVM->pgm.s.pfnR3BthSyncPage = pModeData->pfnR3BthSyncPage;
2984	pVM->pgm.s.pfnR3BthPrefetchPage = pModeData->pfnR3BthPrefetchPage;
2985	pVM->pgm.s.pfnR3BthVerifyAccessSyncPage = pModeData->pfnR3BthVerifyAccessSyncPage;
2986	#ifdef VBOX_STRICT
2987	pVM->pgm.s.pfnR3BthAssertCR3 = pModeData->pfnR3BthAssertCR3;
2988	#endif
2989	pVM->pgm.s.pfnR3BthMapCR3 = pModeData->pfnR3BthMapCR3;
2990	pVM->pgm.s.pfnR3BthUnmapCR3 = pModeData->pfnR3BthUnmapCR3;
2991
2992	pVM->pgm.s.pfnRCBthTrap0eHandler = pModeData->pfnRCBthTrap0eHandler;
2993	pVM->pgm.s.pfnRCBthInvalidatePage = pModeData->pfnRCBthInvalidatePage;
2994	pVM->pgm.s.pfnRCBthSyncCR3 = pModeData->pfnRCBthSyncCR3;
2995	pVM->pgm.s.pfnRCBthSyncPage = pModeData->pfnRCBthSyncPage;
2996	pVM->pgm.s.pfnRCBthPrefetchPage = pModeData->pfnRCBthPrefetchPage;
2997	pVM->pgm.s.pfnRCBthVerifyAccessSyncPage = pModeData->pfnRCBthVerifyAccessSyncPage;
2998	#ifdef VBOX_STRICT
2999	pVM->pgm.s.pfnRCBthAssertCR3 = pModeData->pfnRCBthAssertCR3;
3000	#endif
3001	pVM->pgm.s.pfnRCBthMapCR3 = pModeData->pfnRCBthMapCR3;
3002	pVM->pgm.s.pfnRCBthUnmapCR3 = pModeData->pfnRCBthUnmapCR3;
3003
3004	pVM->pgm.s.pfnR0BthTrap0eHandler = pModeData->pfnR0BthTrap0eHandler;
3005	pVM->pgm.s.pfnR0BthInvalidatePage = pModeData->pfnR0BthInvalidatePage;
3006	pVM->pgm.s.pfnR0BthSyncCR3 = pModeData->pfnR0BthSyncCR3;
3007	pVM->pgm.s.pfnR0BthSyncPage = pModeData->pfnR0BthSyncPage;
3008	pVM->pgm.s.pfnR0BthPrefetchPage = pModeData->pfnR0BthPrefetchPage;
3009	pVM->pgm.s.pfnR0BthVerifyAccessSyncPage = pModeData->pfnR0BthVerifyAccessSyncPage;
3010	#ifdef VBOX_STRICT
3011	pVM->pgm.s.pfnR0BthAssertCR3 = pModeData->pfnR0BthAssertCR3;
3012	#endif
3013	pVM->pgm.s.pfnR0BthMapCR3 = pModeData->pfnR0BthMapCR3;
3014	pVM->pgm.s.pfnR0BthUnmapCR3 = pModeData->pfnR0BthUnmapCR3;
3015	}
3016
3017
3018	/**
3019	* Calculates the shadow paging mode.
3020	*
3021	* @returns The shadow paging mode.
3022	* @param pVM VM handle.
3023	* @param enmGuestMode The guest mode.
3024	* @param enmHostMode The host mode.
3025	* @param enmShadowMode The current shadow mode.
3026	* @param penmSwitcher Where to store the switcher to use.
3027	* VMMSWITCHER_INVALID means no change.
3028	*/
3029	static PGMMODE pgmR3CalcShadowMode(PVM pVM, PGMMODE enmGuestMode, SUPPAGINGMODE enmHostMode, PGMMODE enmShadowMode, VMMSWITCHER *penmSwitcher)
3030	{
3031	VMMSWITCHER enmSwitcher = VMMSWITCHER_INVALID;
3032	switch (enmGuestMode)
3033	{
3034	/*
3035	* When switching to real or protected mode we don't change
3036	* anything since it's likely that we'll switch back pretty soon.
3037	*
3038	* During pgmR3InitPaging we'll end up here with PGMMODE_INVALID
3039	* and is supposed to determine which shadow paging and switcher to
3040	* use during init.
3041	*/
3042	case PGMMODE_REAL:
3043	case PGMMODE_PROTECTED:
3044	if ( enmShadowMode != PGMMODE_INVALID
3045	&& !HWACCMIsEnabled(pVM) /* always switch in hwaccm mode! */)
3046	break; /* (no change) */
3047
3048	switch (enmHostMode)
3049	{
3050	case SUPPAGINGMODE_32_BIT:
3051	case SUPPAGINGMODE_32_BIT_GLOBAL:
3052	enmShadowMode = PGMMODE_32_BIT;
3053	enmSwitcher = VMMSWITCHER_32_TO_32;
3054	break;
3055
3056	case SUPPAGINGMODE_PAE:
3057	case SUPPAGINGMODE_PAE_NX:
3058	case SUPPAGINGMODE_PAE_GLOBAL:
3059	case SUPPAGINGMODE_PAE_GLOBAL_NX:
3060	enmShadowMode = PGMMODE_PAE;
3061	enmSwitcher = VMMSWITCHER_PAE_TO_PAE;
3062	#ifdef DEBUG_bird
3063	if (RTEnvExist("VBOX_32BIT"))
3064	{
3065	enmShadowMode = PGMMODE_32_BIT;
3066	enmSwitcher = VMMSWITCHER_PAE_TO_32;
3067	}
3068	#endif
3069	break;
3070
3071	case SUPPAGINGMODE_AMD64:
3072	case SUPPAGINGMODE_AMD64_GLOBAL:
3073	case SUPPAGINGMODE_AMD64_NX:
3074	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
3075	enmShadowMode = PGMMODE_PAE;
3076	enmSwitcher = VMMSWITCHER_AMD64_TO_PAE;
3077	#ifdef DEBUG_bird
3078	if (RTEnvExist("VBOX_32BIT"))
3079	{
3080	enmShadowMode = PGMMODE_32_BIT;
3081	enmSwitcher = VMMSWITCHER_AMD64_TO_32;
3082	}
3083	#endif
3084	break;
3085
3086	default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
3087	}
3088	break;
3089
3090	case PGMMODE_32_BIT:
3091	switch (enmHostMode)
3092	{
3093	case SUPPAGINGMODE_32_BIT:
3094	case SUPPAGINGMODE_32_BIT_GLOBAL:
3095	enmShadowMode = PGMMODE_32_BIT;
3096	enmSwitcher = VMMSWITCHER_32_TO_32;
3097	break;
3098
3099	case SUPPAGINGMODE_PAE:
3100	case SUPPAGINGMODE_PAE_NX:
3101	case SUPPAGINGMODE_PAE_GLOBAL:
3102	case SUPPAGINGMODE_PAE_GLOBAL_NX:
3103	enmShadowMode = PGMMODE_PAE;
3104	enmSwitcher = VMMSWITCHER_PAE_TO_PAE;
3105	#ifdef DEBUG_bird
3106	if (RTEnvExist("VBOX_32BIT"))
3107	{
3108	enmShadowMode = PGMMODE_32_BIT;
3109	enmSwitcher = VMMSWITCHER_PAE_TO_32;
3110	}
3111	#endif
3112	break;
3113
3114	case SUPPAGINGMODE_AMD64:
3115	case SUPPAGINGMODE_AMD64_GLOBAL:
3116	case SUPPAGINGMODE_AMD64_NX:
3117	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
3118	enmShadowMode = PGMMODE_PAE;
3119	enmSwitcher = VMMSWITCHER_AMD64_TO_PAE;
3120	#ifdef DEBUG_bird
3121	if (RTEnvExist("VBOX_32BIT"))
3122	{
3123	enmShadowMode = PGMMODE_32_BIT;
3124	enmSwitcher = VMMSWITCHER_AMD64_TO_32;
3125	}
3126	#endif
3127	break;
3128
3129	default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
3130	}
3131	break;
3132
3133	case PGMMODE_PAE:
3134	case PGMMODE_PAE_NX: /** @todo This might require more switchers and guest+both modes. */
3135	switch (enmHostMode)
3136	{
3137	case SUPPAGINGMODE_32_BIT:
3138	case SUPPAGINGMODE_32_BIT_GLOBAL:
3139	enmShadowMode = PGMMODE_PAE;
3140	enmSwitcher = VMMSWITCHER_32_TO_PAE;
3141	break;
3142
3143	case SUPPAGINGMODE_PAE:
3144	case SUPPAGINGMODE_PAE_NX:
3145	case SUPPAGINGMODE_PAE_GLOBAL:
3146	case SUPPAGINGMODE_PAE_GLOBAL_NX:
3147	enmShadowMode = PGMMODE_PAE;
3148	enmSwitcher = VMMSWITCHER_PAE_TO_PAE;
3149	break;
3150
3151	case SUPPAGINGMODE_AMD64:
3152	case SUPPAGINGMODE_AMD64_GLOBAL:
3153	case SUPPAGINGMODE_AMD64_NX:
3154	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
3155	enmShadowMode = PGMMODE_PAE;
3156	enmSwitcher = VMMSWITCHER_AMD64_TO_PAE;
3157	break;
3158
3159	default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
3160	}
3161	break;
3162
3163	case PGMMODE_AMD64:
3164	case PGMMODE_AMD64_NX:
3165	switch (enmHostMode)
3166	{
3167	case SUPPAGINGMODE_32_BIT:
3168	case SUPPAGINGMODE_32_BIT_GLOBAL:
3169	enmShadowMode = PGMMODE_AMD64;
3170	enmSwitcher = VMMSWITCHER_32_TO_AMD64;
3171	break;
3172
3173	case SUPPAGINGMODE_PAE:
3174	case SUPPAGINGMODE_PAE_NX:
3175	case SUPPAGINGMODE_PAE_GLOBAL:
3176	case SUPPAGINGMODE_PAE_GLOBAL_NX:
3177	enmShadowMode = PGMMODE_AMD64;
3178	enmSwitcher = VMMSWITCHER_PAE_TO_AMD64;
3179	break;
3180
3181	case SUPPAGINGMODE_AMD64:
3182	case SUPPAGINGMODE_AMD64_GLOBAL:
3183	case SUPPAGINGMODE_AMD64_NX:
3184	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
3185	enmShadowMode = PGMMODE_AMD64;
3186	enmSwitcher = VMMSWITCHER_AMD64_TO_AMD64;
3187	break;
3188
3189	default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
3190	}
3191	break;
3192
3193
3194	default:
3195	AssertReleaseMsgFailed(("enmGuestMode=%d\n", enmGuestMode));
3196	return PGMMODE_INVALID;
3197	}
3198	/* Override the shadow mode is nested paging is active. */
3199	if (HWACCMIsNestedPagingActive(pVM))
3200	enmShadowMode = HWACCMGetShwPagingMode(pVM);
3201
3202	*penmSwitcher = enmSwitcher;
3203	return enmShadowMode;
3204	}
3205
3206
3207	/**
3208	* Performs the actual mode change.
3209	* This is called by PGMChangeMode and pgmR3InitPaging().
3210	*
3211	* @returns VBox status code.
3212	* @param pVM VM handle.
3213	* @param enmGuestMode The new guest mode. This is assumed to be different from
3214	* the current mode.
3215	*/
3216	VMMR3DECL(int) PGMR3ChangeMode(PVM pVM, PGMMODE enmGuestMode)
3217	{
3218	Log(("PGMR3ChangeMode: Guest mode: %s -> %s\n", PGMGetModeName(pVM->pgm.s.enmGuestMode), PGMGetModeName(enmGuestMode)));
3219	STAM_REL_COUNTER_INC(&pVM->pgm.s.cGuestModeChanges);
3220
3221	/*
3222	* Calc the shadow mode and switcher.
3223	*/
3224	VMMSWITCHER enmSwitcher;
3225	PGMMODE enmShadowMode = pgmR3CalcShadowMode(pVM, enmGuestMode, pVM->pgm.s.enmHostMode, pVM->pgm.s.enmShadowMode, &enmSwitcher);
3226	if (enmSwitcher != VMMSWITCHER_INVALID)
3227	{
3228	/*
3229	* Select new switcher.
3230	*/
3231	int rc = VMMR3SelectSwitcher(pVM, enmSwitcher);
3232	if (RT_FAILURE(rc))
3233	{
3234	AssertReleaseMsgFailed(("VMMR3SelectSwitcher(%d) -> %Rrc\n", enmSwitcher, rc));
3235	return rc;
3236	}
3237	}
3238
3239	/*
3240	* Exit old mode(s).
3241	*/
3242	/* shadow */
3243	if (enmShadowMode != pVM->pgm.s.enmShadowMode)
3244	{
3245	LogFlow(("PGMR3ChangeMode: Shadow mode: %s -> %s\n", PGMGetModeName(pVM->pgm.s.enmShadowMode), PGMGetModeName(enmShadowMode)));
3246	if (PGM_SHW_PFN(Exit, pVM))
3247	{
3248	int rc = PGM_SHW_PFN(Exit, pVM)(pVM);
3249	if (RT_FAILURE(rc))
3250	{
3251	AssertMsgFailed(("Exit failed for shadow mode %d: %Rrc\n", pVM->pgm.s.enmShadowMode, rc));
3252	return rc;
3253	}
3254	}
3255
3256	}
3257	else
3258	LogFlow(("PGMR3ChangeMode: Shadow mode remains: %s\n", PGMGetModeName(pVM->pgm.s.enmShadowMode)));
3259
3260	/* guest */
3261	if (PGM_GST_PFN(Exit, pVM))
3262	{
3263	int rc = PGM_GST_PFN(Exit, pVM)(pVM);
3264	if (RT_FAILURE(rc))
3265	{
3266	AssertMsgFailed(("Exit failed for guest mode %d: %Rrc\n", pVM->pgm.s.enmGuestMode, rc));
3267	return rc;
3268	}
3269	}
3270
3271	/*
3272	* Load new paging mode data.
3273	*/
3274	pgmR3ModeDataSwitch(pVM, enmShadowMode, enmGuestMode);
3275
3276	/*
3277	* Enter new shadow mode (if changed).
3278	*/
3279	if (enmShadowMode != pVM->pgm.s.enmShadowMode)
3280	{
3281	int rc;
3282	pVM->pgm.s.enmShadowMode = enmShadowMode;
3283	switch (enmShadowMode)
3284	{
3285	case PGMMODE_32_BIT:
3286	rc = PGM_SHW_NAME_32BIT(Enter)(pVM);
3287	break;
3288	case PGMMODE_PAE:
3289	case PGMMODE_PAE_NX:
3290	rc = PGM_SHW_NAME_PAE(Enter)(pVM);
3291	break;
3292	case PGMMODE_AMD64:
3293	case PGMMODE_AMD64_NX:
3294	rc = PGM_SHW_NAME_AMD64(Enter)(pVM);
3295	break;
3296	case PGMMODE_NESTED:
3297	rc = PGM_SHW_NAME_NESTED(Enter)(pVM);
3298	break;
3299	case PGMMODE_EPT:
3300	rc = PGM_SHW_NAME_EPT(Enter)(pVM);
3301	break;
3302	case PGMMODE_REAL:
3303	case PGMMODE_PROTECTED:
3304	default:
3305	AssertReleaseMsgFailed(("enmShadowMode=%d\n", enmShadowMode));
3306	return VERR_INTERNAL_ERROR;
3307	}
3308	if (RT_FAILURE(rc))
3309	{
3310	AssertReleaseMsgFailed(("Entering enmShadowMode=%d failed: %Rrc\n", enmShadowMode, rc));
3311	pVM->pgm.s.enmShadowMode = PGMMODE_INVALID;
3312	return rc;
3313	}
3314	}
3315
3316	/*
3317	* Always flag the necessary updates
3318	*/
3319	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
3320
3321	/*
3322	* Enter the new guest and shadow+guest modes.
3323	*/
3324	int rc = -1;
3325	int rc2 = -1;
3326	RTGCPHYS GCPhysCR3 = NIL_RTGCPHYS;
3327	pVM->pgm.s.enmGuestMode = enmGuestMode;
3328	switch (enmGuestMode)
3329	{
3330	case PGMMODE_REAL:
3331	rc = PGM_GST_NAME_REAL(Enter)(pVM, NIL_RTGCPHYS);
3332	switch (pVM->pgm.s.enmShadowMode)
3333	{
3334	case PGMMODE_32_BIT:
3335	rc2 = PGM_BTH_NAME_32BIT_REAL(Enter)(pVM, NIL_RTGCPHYS);
3336	break;
3337	case PGMMODE_PAE:
3338	case PGMMODE_PAE_NX:
3339	rc2 = PGM_BTH_NAME_PAE_REAL(Enter)(pVM, NIL_RTGCPHYS);
3340	break;
3341	case PGMMODE_NESTED:
3342	rc2 = PGM_BTH_NAME_NESTED_REAL(Enter)(pVM, NIL_RTGCPHYS);
3343	break;
3344	case PGMMODE_EPT:
3345	rc2 = PGM_BTH_NAME_EPT_REAL(Enter)(pVM, NIL_RTGCPHYS);
3346	break;
3347	case PGMMODE_AMD64:
3348	case PGMMODE_AMD64_NX:
3349	AssertMsgFailed(("Should use PAE shadow mode!\n"));
3350	default: AssertFailed(); break;
3351	}
3352	break;
3353
3354	case PGMMODE_PROTECTED:
3355	rc = PGM_GST_NAME_PROT(Enter)(pVM, NIL_RTGCPHYS);
3356	switch (pVM->pgm.s.enmShadowMode)
3357	{
3358	case PGMMODE_32_BIT:
3359	rc2 = PGM_BTH_NAME_32BIT_PROT(Enter)(pVM, NIL_RTGCPHYS);
3360	break;
3361	case PGMMODE_PAE:
3362	case PGMMODE_PAE_NX:
3363	rc2 = PGM_BTH_NAME_PAE_PROT(Enter)(pVM, NIL_RTGCPHYS);
3364	break;
3365	case PGMMODE_NESTED:
3366	rc2 = PGM_BTH_NAME_NESTED_PROT(Enter)(pVM, NIL_RTGCPHYS);
3367	break;
3368	case PGMMODE_EPT:
3369	rc2 = PGM_BTH_NAME_EPT_PROT(Enter)(pVM, NIL_RTGCPHYS);
3370	break;
3371	case PGMMODE_AMD64:
3372	case PGMMODE_AMD64_NX:
3373	AssertMsgFailed(("Should use PAE shadow mode!\n"));
3374	default: AssertFailed(); break;
3375	}
3376	break;
3377
3378	case PGMMODE_32_BIT:
3379	GCPhysCR3 = CPUMGetGuestCR3(pVM) & X86_CR3_PAGE_MASK;
3380	rc = PGM_GST_NAME_32BIT(Enter)(pVM, GCPhysCR3);
3381	switch (pVM->pgm.s.enmShadowMode)
3382	{
3383	case PGMMODE_32_BIT:
3384	rc2 = PGM_BTH_NAME_32BIT_32BIT(Enter)(pVM, GCPhysCR3);
3385	break;
3386	case PGMMODE_PAE:
3387	case PGMMODE_PAE_NX:
3388	rc2 = PGM_BTH_NAME_PAE_32BIT(Enter)(pVM, GCPhysCR3);
3389	break;
3390	case PGMMODE_NESTED:
3391	rc2 = PGM_BTH_NAME_NESTED_32BIT(Enter)(pVM, GCPhysCR3);
3392	break;
3393	case PGMMODE_EPT:
3394	rc2 = PGM_BTH_NAME_EPT_32BIT(Enter)(pVM, GCPhysCR3);
3395	break;
3396	case PGMMODE_AMD64:
3397	case PGMMODE_AMD64_NX:
3398	AssertMsgFailed(("Should use PAE shadow mode!\n"));
3399	default: AssertFailed(); break;
3400	}
3401	break;
3402
3403	case PGMMODE_PAE_NX:
3404	case PGMMODE_PAE:
3405	{
3406	uint32_t u32Dummy, u32Features;
3407
3408	CPUMGetGuestCpuId(pVM, 1, &u32Dummy, &u32Dummy, &u32Dummy, &u32Features);
3409	if (!(u32Features & X86_CPUID_FEATURE_EDX_PAE))
3410	{
3411	/* Pause first, then inform Main. */
3412	rc = VMR3SuspendNoSave(pVM);
3413	AssertRC(rc);
3414
3415	VMSetRuntimeError(pVM, true, "PAEmode",
3416	N_("The guest is trying to switch to the PAE mode which is currently disabled by default in VirtualBox. PAE support can be enabled using the VM settings (General/Advanced)"));
3417	/* we must return VINF_SUCCESS here otherwise the recompiler will assert */
3418	return VINF_SUCCESS;
3419	}
3420	GCPhysCR3 = CPUMGetGuestCR3(pVM) & X86_CR3_PAE_PAGE_MASK;
3421	rc = PGM_GST_NAME_PAE(Enter)(pVM, GCPhysCR3);
3422	switch (pVM->pgm.s.enmShadowMode)
3423	{
3424	case PGMMODE_PAE:
3425	case PGMMODE_PAE_NX:
3426	rc2 = PGM_BTH_NAME_PAE_PAE(Enter)(pVM, GCPhysCR3);
3427	break;
3428	case PGMMODE_NESTED:
3429	rc2 = PGM_BTH_NAME_NESTED_PAE(Enter)(pVM, GCPhysCR3);
3430	break;
3431	case PGMMODE_EPT:
3432	rc2 = PGM_BTH_NAME_EPT_PAE(Enter)(pVM, GCPhysCR3);
3433	break;
3434	case PGMMODE_32_BIT:
3435	case PGMMODE_AMD64:
3436	case PGMMODE_AMD64_NX:
3437	AssertMsgFailed(("Should use PAE shadow mode!\n"));
3438	default: AssertFailed(); break;
3439	}
3440	break;
3441	}
3442
3443	#ifdef VBOX_WITH_64_BITS_GUESTS
3444	case PGMMODE_AMD64_NX:
3445	case PGMMODE_AMD64:
3446	GCPhysCR3 = CPUMGetGuestCR3(pVM) & UINT64_C(0xfffffffffffff000); /** @todo define this mask! */
3447	rc = PGM_GST_NAME_AMD64(Enter)(pVM, GCPhysCR3);
3448	switch (pVM->pgm.s.enmShadowMode)
3449	{
3450	case PGMMODE_AMD64:
3451	case PGMMODE_AMD64_NX:
3452	rc2 = PGM_BTH_NAME_AMD64_AMD64(Enter)(pVM, GCPhysCR3);
3453	break;
3454	case PGMMODE_NESTED:
3455	rc2 = PGM_BTH_NAME_NESTED_AMD64(Enter)(pVM, GCPhysCR3);
3456	break;
3457	case PGMMODE_EPT:
3458	rc2 = PGM_BTH_NAME_EPT_AMD64(Enter)(pVM, GCPhysCR3);
3459	break;
3460	case PGMMODE_32_BIT:
3461	case PGMMODE_PAE:
3462	case PGMMODE_PAE_NX:
3463	AssertMsgFailed(("Should use AMD64 shadow mode!\n"));
3464	default: AssertFailed(); break;
3465	}
3466	break;
3467	#endif
3468
3469	default:
3470	AssertReleaseMsgFailed(("enmGuestMode=%d\n", enmGuestMode));
3471	rc = VERR_NOT_IMPLEMENTED;
3472	break;
3473	}
3474
3475	/* status codes. */
3476	AssertRC(rc);
3477	AssertRC(rc2);
3478	if (RT_SUCCESS(rc))
3479	{
3480	rc = rc2;
3481	if (RT_SUCCESS(rc)) /* no informational status codes. */
3482	rc = VINF_SUCCESS;
3483	}
3484
3485	/* Notify HWACCM as well. */
3486	HWACCMR3PagingModeChanged(pVM, pVM->pgm.s.enmShadowMode, pVM->pgm.s.enmGuestMode);
3487	return rc;
3488	}
3489
3490
3491	/**
3492	* Dumps a PAE shadow page table.
3493	*
3494	* @returns VBox status code (VINF_SUCCESS).
3495	* @param pVM The VM handle.
3496	* @param pPT Pointer to the page table.
3497	* @param u64Address The virtual address of the page table starts.
3498	* @param fLongMode Set if this a long mode table; clear if it's a legacy mode table.
3499	* @param cMaxDepth The maxium depth.
3500	* @param pHlp Pointer to the output functions.
3501	*/
3502	static int pgmR3DumpHierarchyHCPaePT(PVM pVM, PX86PTPAE pPT, uint64_t u64Address, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
3503	{
3504	for (unsigned i = 0; i < RT_ELEMENTS(pPT->a); i++)
3505	{
3506	X86PTEPAE Pte = pPT->a[i];
3507	if (Pte.n.u1Present)
3508	{
3509	pHlp->pfnPrintf(pHlp,
3510	fLongMode /P R S A D G WT CD AT NX 4M a p ? /
3511	? "%016llx 3 \| P %c %c %c %c %c %s %s %s %s 4K %c%c%c %016llx\n"
3512	: "%08llx 2 \| P %c %c %c %c %c %s %s %s %s 4K %c%c%c %016llx\n",
3513	u64Address + ((uint64_t)i << X86_PT_PAE_SHIFT),
3514	Pte.n.u1Write ? 'W' : 'R',
3515	Pte.n.u1User ? 'U' : 'S',
3516	Pte.n.u1Accessed ? 'A' : '-',
3517	Pte.n.u1Dirty ? 'D' : '-',
3518	Pte.n.u1Global ? 'G' : '-',
3519	Pte.n.u1WriteThru ? "WT" : "--",
3520	Pte.n.u1CacheDisable? "CD" : "--",
3521	Pte.n.u1PAT ? "AT" : "--",
3522	Pte.n.u1NoExecute ? "NX" : "--",
3523	Pte.u & PGM_PTFLAGS_TRACK_DIRTY ? 'd' : '-',
3524	Pte.u & RT_BIT(10) ? '1' : '0',
3525	Pte.u & PGM_PTFLAGS_CSAM_VALIDATED? 'v' : '-',
3526	Pte.u & X86_PTE_PAE_PG_MASK);
3527	}
3528	}
3529	return VINF_SUCCESS;
3530	}
3531
3532
3533	/**
3534	* Dumps a PAE shadow page directory table.
3535	*
3536	* @returns VBox status code (VINF_SUCCESS).
3537	* @param pVM The VM handle.
3538	* @param HCPhys The physical address of the page directory table.
3539	* @param u64Address The virtual address of the page table starts.
3540	* @param cr4 The CR4, PSE is currently used.
3541	* @param fLongMode Set if this a long mode table; clear if it's a legacy mode table.
3542	* @param cMaxDepth The maxium depth.
3543	* @param pHlp Pointer to the output functions.
3544	*/
3545	static int pgmR3DumpHierarchyHCPaePD(PVM pVM, RTHCPHYS HCPhys, uint64_t u64Address, uint32_t cr4, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
3546	{
3547	PX86PDPAE pPD = (PX86PDPAE)MMPagePhys2Page(pVM, HCPhys);
3548	if (!pPD)
3549	{
3550	pHlp->pfnPrintf(pHlp, "%0*llx error! Page directory at HCPhys=%RHp was not found in the page pool!\n",
3551	fLongMode ? 16 : 8, u64Address, HCPhys);
3552	return VERR_INVALID_PARAMETER;
3553	}
3554	const bool fBigPagesSupported = fLongMode \|\| !!(cr4 & X86_CR4_PSE);
3555
3556	int rc = VINF_SUCCESS;
3557	for (unsigned i = 0; i < RT_ELEMENTS(pPD->a); i++)
3558	{
3559	X86PDEPAE Pde = pPD->a[i];
3560	if (Pde.n.u1Present)
3561	{
3562	if (fBigPagesSupported && Pde.b.u1Size)
3563	pHlp->pfnPrintf(pHlp,
3564	fLongMode /P R S A D G WT CD AT NX 4M a p ? /
3565	? "%016llx 2 \| P %c %c %c %c %c %s %s %s %s 4M %c%c%c %016llx\n"
3566	: "%08llx 1 \| P %c %c %c %c %c %s %s %s %s 4M %c%c%c %016llx\n",
3567	u64Address + ((uint64_t)i << X86_PD_PAE_SHIFT),
3568	Pde.b.u1Write ? 'W' : 'R',
3569	Pde.b.u1User ? 'U' : 'S',
3570	Pde.b.u1Accessed ? 'A' : '-',
3571	Pde.b.u1Dirty ? 'D' : '-',
3572	Pde.b.u1Global ? 'G' : '-',
3573	Pde.b.u1WriteThru ? "WT" : "--",
3574	Pde.b.u1CacheDisable? "CD" : "--",
3575	Pde.b.u1PAT ? "AT" : "--",
3576	Pde.b.u1NoExecute ? "NX" : "--",
3577	Pde.u & RT_BIT_64(9) ? '1' : '0',
3578	Pde.u & PGM_PDFLAGS_MAPPING ? 'm' : '-',
3579	Pde.u & PGM_PDFLAGS_TRACK_DIRTY ? 'd' : '-',
3580	Pde.u & X86_PDE_PAE_PG_MASK);
3581	else
3582	{
3583	pHlp->pfnPrintf(pHlp,
3584	fLongMode /P R S A D G WT CD AT NX 4M a p ? /
3585	? "%016llx 2 \| P %c %c %c %c %c %s %s .. %s 4K %c%c%c %016llx\n"
3586	: "%08llx 1 \| P %c %c %c %c %c %s %s .. %s 4K %c%c%c %016llx\n",
3587	u64Address + ((uint64_t)i << X86_PD_PAE_SHIFT),
3588	Pde.n.u1Write ? 'W' : 'R',
3589	Pde.n.u1User ? 'U' : 'S',
3590	Pde.n.u1Accessed ? 'A' : '-',
3591	Pde.n.u1Reserved0 ? '?' : '.', /* ignored */
3592	Pde.n.u1Reserved1 ? '?' : '.', /* ignored */
3593	Pde.n.u1WriteThru ? "WT" : "--",
3594	Pde.n.u1CacheDisable? "CD" : "--",
3595	Pde.n.u1NoExecute ? "NX" : "--",
3596	Pde.u & RT_BIT_64(9) ? '1' : '0',
3597	Pde.u & PGM_PDFLAGS_MAPPING ? 'm' : '-',
3598	Pde.u & PGM_PDFLAGS_TRACK_DIRTY ? 'd' : '-',
3599	Pde.u & X86_PDE_PAE_PG_MASK);
3600	if (cMaxDepth >= 1)
3601	{
3602	/** @todo what about using the page pool for mapping PTs? */
3603	uint64_t u64AddressPT = u64Address + ((uint64_t)i << X86_PD_PAE_SHIFT);
3604	RTHCPHYS HCPhysPT = Pde.u & X86_PDE_PAE_PG_MASK;
3605	PX86PTPAE pPT = NULL;
3606	if (!(Pde.u & PGM_PDFLAGS_MAPPING))
3607	pPT = (PX86PTPAE)MMPagePhys2Page(pVM, HCPhysPT);
3608	else
3609	{
3610	for (PPGMMAPPING pMap = pVM->pgm.s.pMappingsR3; pMap; pMap = pMap->pNextR3)
3611	{
3612	uint64_t off = u64AddressPT - pMap->GCPtr;
3613	if (off < pMap->cb)
3614	{
3615	const int iPDE = (uint32_t)(off >> X86_PD_SHIFT);
3616	const int iSub = (int)((off >> X86_PD_PAE_SHIFT) & 1); /* MSC is a pain sometimes */
3617	if ((iSub ? pMap->aPTs[iPDE].HCPhysPaePT1 : pMap->aPTs[iPDE].HCPhysPaePT0) != HCPhysPT)
3618	pHlp->pfnPrintf(pHlp, "%0*llx error! Mapping error! PT %d has HCPhysPT=%RHp not %RHp is in the PD.\n",
3619	fLongMode ? 16 : 8, u64AddressPT, iPDE,
3620	iSub ? pMap->aPTs[iPDE].HCPhysPaePT1 : pMap->aPTs[iPDE].HCPhysPaePT0, HCPhysPT);
3621	pPT = &pMap->aPTs[iPDE].paPaePTsR3[iSub];
3622	}
3623	}
3624	}
3625	int rc2 = VERR_INVALID_PARAMETER;
3626	if (pPT)
3627	rc2 = pgmR3DumpHierarchyHCPaePT(pVM, pPT, u64AddressPT, fLongMode, cMaxDepth - 1, pHlp);
3628	else
3629	pHlp->pfnPrintf(pHlp, "%0*llx error! Page table at HCPhys=%RHp was not found in the page pool!\n",
3630	fLongMode ? 16 : 8, u64AddressPT, HCPhysPT);
3631	if (rc2 < rc && RT_SUCCESS(rc))
3632	rc = rc2;
3633	}
3634	}
3635	}
3636	}
3637	return rc;
3638	}
3639
3640
3641	/**
3642	* Dumps a PAE shadow page directory pointer table.
3643	*
3644	* @returns VBox status code (VINF_SUCCESS).
3645	* @param pVM The VM handle.
3646	* @param HCPhys The physical address of the page directory pointer table.
3647	* @param u64Address The virtual address of the page table starts.
3648	* @param cr4 The CR4, PSE is currently used.
3649	* @param fLongMode Set if this a long mode table; clear if it's a legacy mode table.
3650	* @param cMaxDepth The maxium depth.
3651	* @param pHlp Pointer to the output functions.
3652	*/
3653	static int pgmR3DumpHierarchyHCPaePDPT(PVM pVM, RTHCPHYS HCPhys, uint64_t u64Address, uint32_t cr4, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
3654	{
3655	PX86PDPT pPDPT = (PX86PDPT)MMPagePhys2Page(pVM, HCPhys);
3656	if (!pPDPT)
3657	{
3658	pHlp->pfnPrintf(pHlp, "%0*llx error! Page directory pointer table at HCPhys=%RHp was not found in the page pool!\n",
3659	fLongMode ? 16 : 8, u64Address, HCPhys);
3660	return VERR_INVALID_PARAMETER;
3661	}
3662
3663	int rc = VINF_SUCCESS;
3664	const unsigned c = fLongMode ? RT_ELEMENTS(pPDPT->a) : X86_PG_PAE_PDPE_ENTRIES;
3665	for (unsigned i = 0; i < c; i++)
3666	{
3667	X86PDPE Pdpe = pPDPT->a[i];
3668	if (Pdpe.n.u1Present)
3669	{
3670	if (fLongMode)
3671	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a p ? /
3672	"%016llx 1 \| P %c %c %c %c %c %s %s %s %s .. %c%c%c %016llx\n",
3673	u64Address + ((uint64_t)i << X86_PDPT_SHIFT),
3674	Pdpe.lm.u1Write ? 'W' : 'R',
3675	Pdpe.lm.u1User ? 'U' : 'S',
3676	Pdpe.lm.u1Accessed ? 'A' : '-',
3677	Pdpe.lm.u3Reserved & 1? '?' : '.', /* ignored */
3678	Pdpe.lm.u3Reserved & 4? '!' : '.', /* mbz */
3679	Pdpe.lm.u1WriteThru ? "WT" : "--",
3680	Pdpe.lm.u1CacheDisable? "CD" : "--",
3681	Pdpe.lm.u3Reserved & 2? "!" : "..",/* mbz */
3682	Pdpe.lm.u1NoExecute ? "NX" : "--",
3683	Pdpe.u & RT_BIT(9) ? '1' : '0',
3684	Pdpe.u & PGM_PLXFLAGS_PERMANENT ? 'p' : '-',
3685	Pdpe.u & RT_BIT(11) ? '1' : '0',
3686	Pdpe.u & X86_PDPE_PG_MASK);
3687	else
3688	pHlp->pfnPrintf(pHlp, /P G WT CD AT NX 4M a p ? /
3689	"%08x 0 \| P %c %s %s %s %s .. %c%c%c %016llx\n",
3690	i << X86_PDPT_SHIFT,
3691	Pdpe.n.u4Reserved & 1? '!' : '.', /* mbz */
3692	Pdpe.n.u4Reserved & 4? '!' : '.', /* mbz */
3693	Pdpe.n.u1WriteThru ? "WT" : "--",
3694	Pdpe.n.u1CacheDisable? "CD" : "--",
3695	Pdpe.n.u4Reserved & 2? "!" : "..",/* mbz */
3696	Pdpe.u & RT_BIT(9) ? '1' : '0',
3697	Pdpe.u & PGM_PLXFLAGS_PERMANENT ? 'p' : '-',
3698	Pdpe.u & RT_BIT(11) ? '1' : '0',
3699	Pdpe.u & X86_PDPE_PG_MASK);
3700	if (cMaxDepth >= 1)
3701	{
3702	int rc2 = pgmR3DumpHierarchyHCPaePD(pVM, Pdpe.u & X86_PDPE_PG_MASK, u64Address + ((uint64_t)i << X86_PDPT_SHIFT),
3703	cr4, fLongMode, cMaxDepth - 1, pHlp);
3704	if (rc2 < rc && RT_SUCCESS(rc))
3705	rc = rc2;
3706	}
3707	}
3708	}
3709	return rc;
3710	}
3711
3712
3713	/**
3714	* Dumps a 32-bit shadow page table.
3715	*
3716	* @returns VBox status code (VINF_SUCCESS).
3717	* @param pVM The VM handle.
3718	* @param HCPhys The physical address of the table.
3719	* @param cr4 The CR4, PSE is currently used.
3720	* @param cMaxDepth The maxium depth.
3721	* @param pHlp Pointer to the output functions.
3722	*/
3723	static int pgmR3DumpHierarchyHcPaePML4(PVM pVM, RTHCPHYS HCPhys, uint32_t cr4, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
3724	{
3725	PX86PML4 pPML4 = (PX86PML4)MMPagePhys2Page(pVM, HCPhys);
3726	if (!pPML4)
3727	{
3728	pHlp->pfnPrintf(pHlp, "Page map level 4 at HCPhys=%RHp was not found in the page pool!\n", HCPhys);
3729	return VERR_INVALID_PARAMETER;
3730	}
3731
3732	int rc = VINF_SUCCESS;
3733	for (unsigned i = 0; i < RT_ELEMENTS(pPML4->a); i++)
3734	{
3735	X86PML4E Pml4e = pPML4->a[i];
3736	if (Pml4e.n.u1Present)
3737	{
3738	uint64_t u64Address = ((uint64_t)i << X86_PML4_SHIFT) \| (((uint64_t)i >> (X86_PML4_SHIFT - X86_PDPT_SHIFT - 1)) * 0xffff000000000000ULL);
3739	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a p ? /
3740	"%016llx 0 \| P %c %c %c %c %c %s %s %s %s .. %c%c%c %016llx\n",
3741	u64Address,
3742	Pml4e.n.u1Write ? 'W' : 'R',
3743	Pml4e.n.u1User ? 'U' : 'S',
3744	Pml4e.n.u1Accessed ? 'A' : '-',
3745	Pml4e.n.u3Reserved & 1? '?' : '.', /* ignored */
3746	Pml4e.n.u3Reserved & 4? '!' : '.', /* mbz */
3747	Pml4e.n.u1WriteThru ? "WT" : "--",
3748	Pml4e.n.u1CacheDisable? "CD" : "--",
3749	Pml4e.n.u3Reserved & 2? "!" : "..",/* mbz */
3750	Pml4e.n.u1NoExecute ? "NX" : "--",
3751	Pml4e.u & RT_BIT(9) ? '1' : '0',
3752	Pml4e.u & PGM_PLXFLAGS_PERMANENT ? 'p' : '-',
3753	Pml4e.u & RT_BIT(11) ? '1' : '0',
3754	Pml4e.u & X86_PML4E_PG_MASK);
3755
3756	if (cMaxDepth >= 1)
3757	{
3758	int rc2 = pgmR3DumpHierarchyHCPaePDPT(pVM, Pml4e.u & X86_PML4E_PG_MASK, u64Address, cr4, true, cMaxDepth - 1, pHlp);
3759	if (rc2 < rc && RT_SUCCESS(rc))
3760	rc = rc2;
3761	}
3762	}
3763	}
3764	return rc;
3765	}
3766
3767
3768	/**
3769	* Dumps a 32-bit shadow page table.
3770	*
3771	* @returns VBox status code (VINF_SUCCESS).
3772	* @param pVM The VM handle.
3773	* @param pPT Pointer to the page table.
3774	* @param u32Address The virtual address this table starts at.
3775	* @param pHlp Pointer to the output functions.
3776	*/
3777	int pgmR3DumpHierarchyHC32BitPT(PVM pVM, PX86PT pPT, uint32_t u32Address, PCDBGFINFOHLP pHlp)
3778	{
3779	for (unsigned i = 0; i < RT_ELEMENTS(pPT->a); i++)
3780	{
3781	X86PTE Pte = pPT->a[i];
3782	if (Pte.n.u1Present)
3783	{
3784	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a m d /
3785	"%08x 1 \| P %c %c %c %c %c %s %s %s .. 4K %c%c%c %08x\n",
3786	u32Address + (i << X86_PT_SHIFT),
3787	Pte.n.u1Write ? 'W' : 'R',
3788	Pte.n.u1User ? 'U' : 'S',
3789	Pte.n.u1Accessed ? 'A' : '-',
3790	Pte.n.u1Dirty ? 'D' : '-',
3791	Pte.n.u1Global ? 'G' : '-',
3792	Pte.n.u1WriteThru ? "WT" : "--",
3793	Pte.n.u1CacheDisable? "CD" : "--",
3794	Pte.n.u1PAT ? "AT" : "--",
3795	Pte.u & PGM_PTFLAGS_TRACK_DIRTY ? 'd' : '-',
3796	Pte.u & RT_BIT(10) ? '1' : '0',
3797	Pte.u & PGM_PTFLAGS_CSAM_VALIDATED ? 'v' : '-',
3798	Pte.u & X86_PDE_PG_MASK);
3799	}
3800	}
3801	return VINF_SUCCESS;
3802	}
3803
3804
3805	/**
3806	* Dumps a 32-bit shadow page directory and page tables.
3807	*
3808	* @returns VBox status code (VINF_SUCCESS).
3809	* @param pVM The VM handle.
3810	* @param cr3 The root of the hierarchy.
3811	* @param cr4 The CR4, PSE is currently used.
3812	* @param cMaxDepth How deep into the hierarchy the dumper should go.
3813	* @param pHlp Pointer to the output functions.
3814	*/
3815	int pgmR3DumpHierarchyHC32BitPD(PVM pVM, uint32_t cr3, uint32_t cr4, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
3816	{
3817	PX86PD pPD = (PX86PD)MMPagePhys2Page(pVM, cr3 & X86_CR3_PAGE_MASK);
3818	if (!pPD)
3819	{
3820	pHlp->pfnPrintf(pHlp, "Page directory at %#x was not found in the page pool!\n", cr3 & X86_CR3_PAGE_MASK);
3821	return VERR_INVALID_PARAMETER;
3822	}
3823
3824	int rc = VINF_SUCCESS;
3825	for (unsigned i = 0; i < RT_ELEMENTS(pPD->a); i++)
3826	{
3827	X86PDE Pde = pPD->a[i];
3828	if (Pde.n.u1Present)
3829	{
3830	const uint32_t u32Address = i << X86_PD_SHIFT;
3831	if ((cr4 & X86_CR4_PSE) && Pde.b.u1Size)
3832	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a m d /
3833	"%08x 0 \| P %c %c %c %c %c %s %s %s .. 4M %c%c%c %08x\n",
3834	u32Address,
3835	Pde.b.u1Write ? 'W' : 'R',
3836	Pde.b.u1User ? 'U' : 'S',
3837	Pde.b.u1Accessed ? 'A' : '-',
3838	Pde.b.u1Dirty ? 'D' : '-',
3839	Pde.b.u1Global ? 'G' : '-',
3840	Pde.b.u1WriteThru ? "WT" : "--",
3841	Pde.b.u1CacheDisable? "CD" : "--",
3842	Pde.b.u1PAT ? "AT" : "--",
3843	Pde.u & RT_BIT_64(9) ? '1' : '0',
3844	Pde.u & PGM_PDFLAGS_MAPPING ? 'm' : '-',
3845	Pde.u & PGM_PDFLAGS_TRACK_DIRTY ? 'd' : '-',
3846	Pde.u & X86_PDE4M_PG_MASK);
3847	else
3848	{
3849	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a m d /
3850	"%08x 0 \| P %c %c %c %c %c %s %s .. .. 4K %c%c%c %08x\n",
3851	u32Address,
3852	Pde.n.u1Write ? 'W' : 'R',
3853	Pde.n.u1User ? 'U' : 'S',
3854	Pde.n.u1Accessed ? 'A' : '-',
3855	Pde.n.u1Reserved0 ? '?' : '.', /* ignored */
3856	Pde.n.u1Reserved1 ? '?' : '.', /* ignored */
3857	Pde.n.u1WriteThru ? "WT" : "--",
3858	Pde.n.u1CacheDisable? "CD" : "--",
3859	Pde.u & RT_BIT_64(9) ? '1' : '0',
3860	Pde.u & PGM_PDFLAGS_MAPPING ? 'm' : '-',
3861	Pde.u & PGM_PDFLAGS_TRACK_DIRTY ? 'd' : '-',
3862	Pde.u & X86_PDE_PG_MASK);
3863	if (cMaxDepth >= 1)
3864	{
3865	/** @todo what about using the page pool for mapping PTs? */
3866	RTHCPHYS HCPhys = Pde.u & X86_PDE_PG_MASK;
3867	PX86PT pPT = NULL;
3868	if (!(Pde.u & PGM_PDFLAGS_MAPPING))
3869	pPT = (PX86PT)MMPagePhys2Page(pVM, HCPhys);
3870	else
3871	{
3872	for (PPGMMAPPING pMap = pVM->pgm.s.pMappingsR3; pMap; pMap = pMap->pNextR3)
3873	if (u32Address - pMap->GCPtr < pMap->cb)
3874	{
3875	int iPDE = (u32Address - pMap->GCPtr) >> X86_PD_SHIFT;
3876	if (pMap->aPTs[iPDE].HCPhysPT != HCPhys)
3877	pHlp->pfnPrintf(pHlp, "%08x error! Mapping error! PT %d has HCPhysPT=%RHp not %RHp is in the PD.\n",
3878	u32Address, iPDE, pMap->aPTs[iPDE].HCPhysPT, HCPhys);
3879	pPT = pMap->aPTs[iPDE].pPTR3;
3880	}
3881	}
3882	int rc2 = VERR_INVALID_PARAMETER;
3883	if (pPT)
3884	rc2 = pgmR3DumpHierarchyHC32BitPT(pVM, pPT, u32Address, pHlp);
3885	else
3886	pHlp->pfnPrintf(pHlp, "%08x error! Page table at %#x was not found in the page pool!\n", u32Address, HCPhys);
3887	if (rc2 < rc && RT_SUCCESS(rc))
3888	rc = rc2;
3889	}
3890	}
3891	}
3892	}
3893
3894	return rc;
3895	}
3896
3897
3898	/**
3899	* Dumps a 32-bit shadow page table.
3900	*
3901	* @returns VBox status code (VINF_SUCCESS).
3902	* @param pVM The VM handle.
3903	* @param pPT Pointer to the page table.
3904	* @param u32Address The virtual address this table starts at.
3905	* @param PhysSearch Address to search for.
3906	*/
3907	int pgmR3DumpHierarchyGC32BitPT(PVM pVM, PX86PT pPT, uint32_t u32Address, RTGCPHYS PhysSearch)
3908	{
3909	for (unsigned i = 0; i < RT_ELEMENTS(pPT->a); i++)
3910	{
3911	X86PTE Pte = pPT->a[i];
3912	if (Pte.n.u1Present)
3913	{
3914	Log(( /P R S A D G WT CD AT NX 4M a m d /
3915	"%08x 1 \| P %c %c %c %c %c %s %s %s .. 4K %c%c%c %08x\n",
3916	u32Address + (i << X86_PT_SHIFT),
3917	Pte.n.u1Write ? 'W' : 'R',
3918	Pte.n.u1User ? 'U' : 'S',
3919	Pte.n.u1Accessed ? 'A' : '-',
3920	Pte.n.u1Dirty ? 'D' : '-',
3921	Pte.n.u1Global ? 'G' : '-',
3922	Pte.n.u1WriteThru ? "WT" : "--",
3923	Pte.n.u1CacheDisable? "CD" : "--",
3924	Pte.n.u1PAT ? "AT" : "--",
3925	Pte.u & PGM_PTFLAGS_TRACK_DIRTY ? 'd' : '-',
3926	Pte.u & RT_BIT(10) ? '1' : '0',
3927	Pte.u & PGM_PTFLAGS_CSAM_VALIDATED ? 'v' : '-',
3928	Pte.u & X86_PDE_PG_MASK));
3929
3930	if ((Pte.u & X86_PDE_PG_MASK) == PhysSearch)
3931	{
3932	uint64_t fPageShw = 0;
3933	RTHCPHYS pPhysHC = 0;
3934
3935	PGMShwGetPage(pVM, (RTGCPTR)(u32Address + (i << X86_PT_SHIFT)), &fPageShw, &pPhysHC);
3936	Log(("Found %RGp at %RGv -> flags=%llx\n", PhysSearch, (RTGCPTR)(u32Address + (i << X86_PT_SHIFT)), fPageShw));
3937	}
3938	}
3939	}
3940	return VINF_SUCCESS;
3941	}
3942
3943
3944	/**
3945	* Dumps a 32-bit guest page directory and page tables.
3946	*
3947	* @returns VBox status code (VINF_SUCCESS).
3948	* @param pVM The VM handle.
3949	* @param cr3 The root of the hierarchy.
3950	* @param cr4 The CR4, PSE is currently used.
3951	* @param PhysSearch Address to search for.
3952	*/
3953	VMMR3DECL(int) PGMR3DumpHierarchyGC(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCPHYS PhysSearch)
3954	{
3955	bool fLongMode = false;
3956	const unsigned cch = fLongMode ? 16 : 8; NOREF(cch);
3957	PX86PD pPD = 0;
3958
3959	int rc = PGM_GCPHYS_2_PTR(pVM, cr3 & X86_CR3_PAGE_MASK, &pPD);
3960	if (RT_FAILURE(rc) \|\| !pPD)
3961	{
3962	Log(("Page directory at %#x was not found in the page pool!\n", cr3 & X86_CR3_PAGE_MASK));
3963	return VERR_INVALID_PARAMETER;
3964	}
3965
3966	Log(("cr3=%08x cr4=%08x%s\n"
3967	"%-*s P - Present\n"
3968	"%-*s \| R/W - Read (0) / Write (1)\n"
3969	"%-*s \| \| U/S - User (1) / Supervisor (0)\n"
3970	"%-*s \| \| \| A - Accessed\n"
3971	"%-*s \| \| \| \| D - Dirty\n"
3972	"%-*s \| \| \| \| \| G - Global\n"
3973	"%-*s \| \| \| \| \| \| WT - Write thru\n"
3974	"%-*s \| \| \| \| \| \| \| CD - Cache disable\n"
3975	"%-*s \| \| \| \| \| \| \| \| AT - Attribute table (PAT)\n"
3976	"%-*s \| \| \| \| \| \| \| \| \| NX - No execute (K8)\n"
3977	"%-*s \| \| \| \| \| \| \| \| \| \| 4K/4M/2M - Page size.\n"
3978	"%-*s \| \| \| \| \| \| \| \| \| \| \| AVL - a=allocated; m=mapping; d=track dirty;\n"
3979	"%-*s \| \| \| \| \| \| \| \| \| \| \| \| p=permanent; v=validated;\n"
3980	"%-*s Level \| \| \| \| \| \| \| \| \| \| \| \| Page\n"
3981	/* xxxx n **** P R S A D G WT CD AT NX 4M AVL xxxxxxxxxxxxx
3982	- W U - - - -- -- -- -- -- 010 */
3983	, cr3, cr4, fLongMode ? " Long Mode" : "",
3984	cch, "", cch, "", cch, "", cch, "", cch, "", cch, "", cch, "",
3985	cch, "", cch, "", cch, "", cch, "", cch, "", cch, "", cch, "Address"));
3986
3987	for (unsigned i = 0; i < RT_ELEMENTS(pPD->a); i++)
3988	{
3989	X86PDE Pde = pPD->a[i];
3990	if (Pde.n.u1Present)
3991	{
3992	const uint32_t u32Address = i << X86_PD_SHIFT;
3993
3994	if ((cr4 & X86_CR4_PSE) && Pde.b.u1Size)
3995	Log(( /P R S A D G WT CD AT NX 4M a m d /
3996	"%08x 0 \| P %c %c %c %c %c %s %s %s .. 4M %c%c%c %08x\n",
3997	u32Address,
3998	Pde.b.u1Write ? 'W' : 'R',
3999	Pde.b.u1User ? 'U' : 'S',
4000	Pde.b.u1Accessed ? 'A' : '-',
4001	Pde.b.u1Dirty ? 'D' : '-',
4002	Pde.b.u1Global ? 'G' : '-',
4003	Pde.b.u1WriteThru ? "WT" : "--",
4004	Pde.b.u1CacheDisable? "CD" : "--",
4005	Pde.b.u1PAT ? "AT" : "--",
4006	Pde.u & RT_BIT(9) ? '1' : '0',
4007	Pde.u & RT_BIT(10) ? '1' : '0',
4008	Pde.u & RT_BIT(11) ? '1' : '0',
4009	pgmGstGet4MBPhysPage(&pVM->pgm.s, Pde)));
4010	/** @todo PhysSearch */
4011	else
4012	{
4013	Log(( /P R S A D G WT CD AT NX 4M a m d /
4014	"%08x 0 \| P %c %c %c %c %c %s %s .. .. 4K %c%c%c %08x\n",
4015	u32Address,
4016	Pde.n.u1Write ? 'W' : 'R',
4017	Pde.n.u1User ? 'U' : 'S',
4018	Pde.n.u1Accessed ? 'A' : '-',
4019	Pde.n.u1Reserved0 ? '?' : '.', /* ignored */
4020	Pde.n.u1Reserved1 ? '?' : '.', /* ignored */
4021	Pde.n.u1WriteThru ? "WT" : "--",
4022	Pde.n.u1CacheDisable? "CD" : "--",
4023	Pde.u & RT_BIT(9) ? '1' : '0',
4024	Pde.u & RT_BIT(10) ? '1' : '0',
4025	Pde.u & RT_BIT(11) ? '1' : '0',
4026	Pde.u & X86_PDE_PG_MASK));
4027	////if (cMaxDepth >= 1)
4028	{
4029	/** @todo what about using the page pool for mapping PTs? */
4030	RTGCPHYS GCPhys = Pde.u & X86_PDE_PG_MASK;
4031	PX86PT pPT = NULL;
4032
4033	rc = PGM_GCPHYS_2_PTR(pVM, GCPhys, &pPT);
4034
4035	int rc2 = VERR_INVALID_PARAMETER;
4036	if (pPT)
4037	rc2 = pgmR3DumpHierarchyGC32BitPT(pVM, pPT, u32Address, PhysSearch);
4038	else
4039	Log(("%08x error! Page table at %#x was not found in the page pool!\n", u32Address, GCPhys));
4040	if (rc2 < rc && RT_SUCCESS(rc))
4041	rc = rc2;
4042	}
4043	}
4044	}
4045	}
4046
4047	return rc;
4048	}
4049
4050
4051	/**
4052	* Dumps a page table hierarchy use only physical addresses and cr4/lm flags.
4053	*
4054	* @returns VBox status code (VINF_SUCCESS).
4055	* @param pVM The VM handle.
4056	* @param cr3 The root of the hierarchy.
4057	* @param cr4 The cr4, only PAE and PSE is currently used.
4058	* @param fLongMode Set if long mode, false if not long mode.
4059	* @param cMaxDepth Number of levels to dump.
4060	* @param pHlp Pointer to the output functions.
4061	*/
4062	VMMR3DECL(int) PGMR3DumpHierarchyHC(PVM pVM, uint64_t cr3, uint64_t cr4, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
4063	{
4064	if (!pHlp)
4065	pHlp = DBGFR3InfoLogHlp();
4066	if (!cMaxDepth)
4067	return VINF_SUCCESS;
4068	const unsigned cch = fLongMode ? 16 : 8;
4069	pHlp->pfnPrintf(pHlp,
4070	"cr3=%08x cr4=%08x%s\n"
4071	"%-*s P - Present\n"
4072	"%-*s \| R/W - Read (0) / Write (1)\n"
4073	"%-*s \| \| U/S - User (1) / Supervisor (0)\n"
4074	"%-*s \| \| \| A - Accessed\n"
4075	"%-*s \| \| \| \| D - Dirty\n"
4076	"%-*s \| \| \| \| \| G - Global\n"
4077	"%-*s \| \| \| \| \| \| WT - Write thru\n"
4078	"%-*s \| \| \| \| \| \| \| CD - Cache disable\n"
4079	"%-*s \| \| \| \| \| \| \| \| AT - Attribute table (PAT)\n"
4080	"%-*s \| \| \| \| \| \| \| \| \| NX - No execute (K8)\n"
4081	"%-*s \| \| \| \| \| \| \| \| \| \| 4K/4M/2M - Page size.\n"
4082	"%-*s \| \| \| \| \| \| \| \| \| \| \| AVL - a=allocated; m=mapping; d=track dirty;\n"
4083	"%-*s \| \| \| \| \| \| \| \| \| \| \| \| p=permanent; v=validated;\n"
4084	"%-*s Level \| \| \| \| \| \| \| \| \| \| \| \| Page\n"
4085	/* xxxx n **** P R S A D G WT CD AT NX 4M AVL xxxxxxxxxxxxx
4086	- W U - - - -- -- -- -- -- 010 */
4087	, cr3, cr4, fLongMode ? " Long Mode" : "",
4088	cch, "", cch, "", cch, "", cch, "", cch, "", cch, "", cch, "",
4089	cch, "", cch, "", cch, "", cch, "", cch, "", cch, "", cch, "Address");
4090	if (cr4 & X86_CR4_PAE)
4091	{
4092	if (fLongMode)
4093	return pgmR3DumpHierarchyHcPaePML4(pVM, cr3 & X86_CR3_PAGE_MASK, cr4, cMaxDepth, pHlp);
4094	return pgmR3DumpHierarchyHCPaePDPT(pVM, cr3 & X86_CR3_PAE_PAGE_MASK, 0, cr4, false, cMaxDepth, pHlp);
4095	}
4096	return pgmR3DumpHierarchyHC32BitPD(pVM, cr3 & X86_CR3_PAGE_MASK, cr4, cMaxDepth, pHlp);
4097	}
4098
4099	#ifdef VBOX_WITH_DEBUGGER
4100
4101	/**
4102	* The '.pgmram' command.
4103	*
4104	* @returns VBox status.
4105	* @param pCmd Pointer to the command descriptor (as registered).
4106	* @param pCmdHlp Pointer to command helper functions.
4107	* @param pVM Pointer to the current VM (if any).
4108	* @param paArgs Pointer to (readonly) array of arguments.
4109	* @param cArgs Number of arguments in the array.
4110	*/
4111	static DECLCALLBACK(int) pgmR3CmdRam(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4112	{
4113	/*
4114	* Validate input.
4115	*/
4116	if (!pVM)
4117	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4118	if (!pVM->pgm.s.pRamRangesRC)
4119	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Sorry, no Ram is registered.\n");
4120
4121	/*
4122	* Dump the ranges.
4123	*/
4124	int rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL, "From - To (incl) pvHC\n");
4125	PPGMRAMRANGE pRam;
4126	for (pRam = pVM->pgm.s.pRamRangesR3; pRam; pRam = pRam->pNextR3)
4127	{
4128	rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL,
4129	"%RGp - %RGp %p\n",
4130	pRam->GCPhys, pRam->GCPhysLast, pRam->pvR3);
4131	if (RT_FAILURE(rc))
4132	return rc;
4133	}
4134
4135	return VINF_SUCCESS;
4136	}
4137
4138
4139	/**
4140	* The '.pgmmap' command.
4141	*
4142	* @returns VBox status.
4143	* @param pCmd Pointer to the command descriptor (as registered).
4144	* @param pCmdHlp Pointer to command helper functions.
4145	* @param pVM Pointer to the current VM (if any).
4146	* @param paArgs Pointer to (readonly) array of arguments.
4147	* @param cArgs Number of arguments in the array.
4148	*/
4149	static DECLCALLBACK(int) pgmR3CmdMap(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4150	{
4151	/*
4152	* Validate input.
4153	*/
4154	if (!pVM)
4155	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4156	if (!pVM->pgm.s.pMappingsR3)
4157	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Sorry, no mappings are registered.\n");
4158
4159	/*
4160	* Print message about the fixedness of the mappings.
4161	*/
4162	int rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL, pVM->pgm.s.fMappingsFixed ? "The mappings are FIXED.\n" : "The mappings are FLOATING.\n");
4163	if (RT_FAILURE(rc))
4164	return rc;
4165
4166	/*
4167	* Dump the ranges.
4168	*/
4169	PPGMMAPPING pCur;
4170	for (pCur = pVM->pgm.s.pMappingsR3; pCur; pCur = pCur->pNextR3)
4171	{
4172	rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL,
4173	"%08x - %08x %s\n",
4174	pCur->GCPtr, pCur->GCPtrLast, pCur->pszDesc);
4175	if (RT_FAILURE(rc))
4176	return rc;
4177	}
4178
4179	return VINF_SUCCESS;
4180	}
4181
4182
4183	/**
4184	* The '.pgmsync' command.
4185	*
4186	* @returns VBox status.
4187	* @param pCmd Pointer to the command descriptor (as registered).
4188	* @param pCmdHlp Pointer to command helper functions.
4189	* @param pVM Pointer to the current VM (if any).
4190	* @param paArgs Pointer to (readonly) array of arguments.
4191	* @param cArgs Number of arguments in the array.
4192	*/
4193	static DECLCALLBACK(int) pgmR3CmdSync(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4194	{
4195	/*
4196	* Validate input.
4197	*/
4198	if (!pVM)
4199	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4200
4201	/*
4202	* Force page directory sync.
4203	*/
4204	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
4205
4206	int rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Forcing page directory sync.\n");
4207	if (RT_FAILURE(rc))
4208	return rc;
4209
4210	return VINF_SUCCESS;
4211	}
4212
4213
4214	#ifdef VBOX_STRICT
4215	/**
4216	* The '.pgmassertcr3' command.
4217	*
4218	* @returns VBox status.
4219	* @param pCmd Pointer to the command descriptor (as registered).
4220	* @param pCmdHlp Pointer to command helper functions.
4221	* @param pVM Pointer to the current VM (if any).
4222	* @param paArgs Pointer to (readonly) array of arguments.
4223	* @param cArgs Number of arguments in the array.
4224	*/
4225	static DECLCALLBACK(int) pgmR3CmdAssertCR3(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4226	{
4227	/*
4228	* Validate input.
4229	*/
4230	if (!pVM)
4231	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4232
4233	int rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Checking shadow CR3 page tables for consistency.\n");
4234	if (RT_FAILURE(rc))
4235	return rc;
4236
4237	PGMAssertCR3(pVM, CPUMGetGuestCR3(pVM), CPUMGetGuestCR4(pVM));
4238
4239	return VINF_SUCCESS;
4240	}
4241	#endif /* VBOX_STRICT */
4242
4243
4244	/**
4245	* The '.pgmsyncalways' command.
4246	*
4247	* @returns VBox status.
4248	* @param pCmd Pointer to the command descriptor (as registered).
4249	* @param pCmdHlp Pointer to command helper functions.
4250	* @param pVM Pointer to the current VM (if any).
4251	* @param paArgs Pointer to (readonly) array of arguments.
4252	* @param cArgs Number of arguments in the array.
4253	*/
4254	static DECLCALLBACK(int) pgmR3CmdSyncAlways(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4255	{
4256	/*
4257	* Validate input.
4258	*/
4259	if (!pVM)
4260	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4261
4262	/*
4263	* Force page directory sync.
4264	*/
4265	if (pVM->pgm.s.fSyncFlags & PGM_SYNC_ALWAYS)
4266	{
4267	ASMAtomicAndU32(&pVM->pgm.s.fSyncFlags, ~PGM_SYNC_ALWAYS);
4268	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Disabled permanent forced page directory syncing.\n");
4269	}
4270	else
4271	{
4272	ASMAtomicOrU32(&pVM->pgm.s.fSyncFlags, PGM_SYNC_ALWAYS);
4273	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
4274	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Enabled permanent forced page directory syncing.\n");
4275	}
4276	}
4277
4278	#endif /* VBOX_WITH_DEBUGGER */
4279
4280	/**
4281	* pvUser argument of the pgmR3CheckIntegrity*Node callbacks.
4282	*/
4283	typedef struct PGMCHECKINTARGS
4284	{
4285	bool fLeftToRight; /*< true: left-to-right; false: right-to-left. /
4286	PPGMPHYSHANDLER pPrevPhys;
4287	PPGMVIRTHANDLER pPrevVirt;
4288	PPGMPHYS2VIRTHANDLER pPrevPhys2Virt;
4289	PVM pVM;
4290	} PGMCHECKINTARGS, *PPGMCHECKINTARGS;
4291
4292	/**
4293	* Validate a node in the physical handler tree.
4294	*
4295	* @returns 0 on if ok, other wise 1.
4296	* @param pNode The handler node.
4297	* @param pvUser pVM.
4298	*/
4299	static DECLCALLBACK(int) pgmR3CheckIntegrityPhysHandlerNode(PAVLROGCPHYSNODECORE pNode, void *pvUser)
4300	{
4301	PPGMCHECKINTARGS pArgs = (PPGMCHECKINTARGS)pvUser;
4302	PPGMPHYSHANDLER pCur = (PPGMPHYSHANDLER)pNode;
4303	AssertReleaseReturn(!((uintptr_t)pCur & 7), 1);
4304	AssertReleaseMsg(pCur->Core.Key <= pCur->Core.KeyLast,("pCur=%p %RGp-%RGp %s\n", pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
4305	AssertReleaseMsg( !pArgs->pPrevPhys
4306	\|\| (pArgs->fLeftToRight ? pArgs->pPrevPhys->Core.KeyLast < pCur->Core.Key : pArgs->pPrevPhys->Core.KeyLast > pCur->Core.Key),
4307	("pPrevPhys=%p %RGp-%RGp %s\n"
4308	" pCur=%p %RGp-%RGp %s\n",
4309	pArgs->pPrevPhys, pArgs->pPrevPhys->Core.Key, pArgs->pPrevPhys->Core.KeyLast, pArgs->pPrevPhys->pszDesc,
4310	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
4311	pArgs->pPrevPhys = pCur;
4312	return 0;
4313	}
4314
4315
4316	/**
4317	* Validate a node in the virtual handler tree.
4318	*
4319	* @returns 0 on if ok, other wise 1.
4320	* @param pNode The handler node.
4321	* @param pvUser pVM.
4322	*/
4323	static DECLCALLBACK(int) pgmR3CheckIntegrityVirtHandlerNode(PAVLROGCPTRNODECORE pNode, void *pvUser)
4324	{
4325	PPGMCHECKINTARGS pArgs = (PPGMCHECKINTARGS)pvUser;
4326	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)pNode;
4327	AssertReleaseReturn(!((uintptr_t)pCur & 7), 1);
4328	AssertReleaseMsg(pCur->Core.Key <= pCur->Core.KeyLast,("pCur=%p %RGv-%RGv %s\n", pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
4329	AssertReleaseMsg( !pArgs->pPrevVirt
4330	\|\| (pArgs->fLeftToRight ? pArgs->pPrevVirt->Core.KeyLast < pCur->Core.Key : pArgs->pPrevVirt->Core.KeyLast > pCur->Core.Key),
4331	("pPrevVirt=%p %RGv-%RGv %s\n"
4332	" pCur=%p %RGv-%RGv %s\n",
4333	pArgs->pPrevVirt, pArgs->pPrevVirt->Core.Key, pArgs->pPrevVirt->Core.KeyLast, pArgs->pPrevVirt->pszDesc,
4334	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
4335	for (unsigned iPage = 0; iPage < pCur->cPages; iPage++)
4336	{
4337	AssertReleaseMsg(pCur->aPhysToVirt[iPage].offVirtHandler == -RT_OFFSETOF(PGMVIRTHANDLER, aPhysToVirt[iPage]),
4338	("pCur=%p %RGv-%RGv %s\n"
4339	"iPage=%d offVirtHandle=%#x expected %#x\n",
4340	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc,
4341	iPage, pCur->aPhysToVirt[iPage].offVirtHandler, -RT_OFFSETOF(PGMVIRTHANDLER, aPhysToVirt[iPage])));
4342	}
4343	pArgs->pPrevVirt = pCur;
4344	return 0;
4345	}
4346
4347
4348	/**
4349	* Validate a node in the virtual handler tree.
4350	*
4351	* @returns 0 on if ok, other wise 1.
4352	* @param pNode The handler node.
4353	* @param pvUser pVM.
4354	*/
4355	static DECLCALLBACK(int) pgmR3CheckIntegrityPhysToVirtHandlerNode(PAVLROGCPHYSNODECORE pNode, void *pvUser)
4356	{
4357	PPGMCHECKINTARGS pArgs = (PPGMCHECKINTARGS)pvUser;
4358	PPGMPHYS2VIRTHANDLER pCur = (PPGMPHYS2VIRTHANDLER)pNode;
4359	AssertReleaseMsgReturn(!((uintptr_t)pCur & 3), ("\n"), 1);
4360	AssertReleaseMsgReturn(!(pCur->offVirtHandler & 3), ("\n"), 1);
4361	AssertReleaseMsg(pCur->Core.Key <= pCur->Core.KeyLast,("pCur=%p %RGp-%RGp\n", pCur, pCur->Core.Key, pCur->Core.KeyLast));
4362	AssertReleaseMsg( !pArgs->pPrevPhys2Virt
4363	\|\| (pArgs->fLeftToRight ? pArgs->pPrevPhys2Virt->Core.KeyLast < pCur->Core.Key : pArgs->pPrevPhys2Virt->Core.KeyLast > pCur->Core.Key),
4364	("pPrevPhys2Virt=%p %RGp-%RGp\n"
4365	" pCur=%p %RGp-%RGp\n",
4366	pArgs->pPrevPhys2Virt, pArgs->pPrevPhys2Virt->Core.Key, pArgs->pPrevPhys2Virt->Core.KeyLast,
4367	pCur, pCur->Core.Key, pCur->Core.KeyLast));
4368	AssertReleaseMsg( !pArgs->pPrevPhys2Virt
4369	\|\| (pArgs->fLeftToRight ? pArgs->pPrevPhys2Virt->Core.KeyLast < pCur->Core.Key : pArgs->pPrevPhys2Virt->Core.KeyLast > pCur->Core.Key),
4370	("pPrevPhys2Virt=%p %RGp-%RGp\n"
4371	" pCur=%p %RGp-%RGp\n",
4372	pArgs->pPrevPhys2Virt, pArgs->pPrevPhys2Virt->Core.Key, pArgs->pPrevPhys2Virt->Core.KeyLast,
4373	pCur, pCur->Core.Key, pCur->Core.KeyLast));
4374	AssertReleaseMsg((pCur->offNextAlias & (PGMPHYS2VIRTHANDLER_IN_TREE \| PGMPHYS2VIRTHANDLER_IS_HEAD)) == (PGMPHYS2VIRTHANDLER_IN_TREE \| PGMPHYS2VIRTHANDLER_IS_HEAD),
4375	("pCur=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4376	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias));
4377	if (pCur->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK)
4378	{
4379	PPGMPHYS2VIRTHANDLER pCur2 = pCur;
4380	for (;;)
4381	{
4382	pCur2 = (PPGMPHYS2VIRTHANDLER)((intptr_t)pCur + (pCur->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK));
4383	AssertReleaseMsg(pCur2 != pCur,
4384	(" pCur=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4385	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias));
4386	AssertReleaseMsg((pCur2->offNextAlias & (PGMPHYS2VIRTHANDLER_IN_TREE \| PGMPHYS2VIRTHANDLER_IS_HEAD)) == PGMPHYS2VIRTHANDLER_IN_TREE,
4387	(" pCur=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
4388	"pCur2=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4389	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias,
4390	pCur2, pCur2->Core.Key, pCur2->Core.KeyLast, pCur2->offVirtHandler, pCur2->offNextAlias));
4391	AssertReleaseMsg((pCur2->Core.Key ^ pCur->Core.Key) < PAGE_SIZE,
4392	(" pCur=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
4393	"pCur2=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4394	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias,
4395	pCur2, pCur2->Core.Key, pCur2->Core.KeyLast, pCur2->offVirtHandler, pCur2->offNextAlias));
4396	AssertReleaseMsg((pCur2->Core.KeyLast ^ pCur->Core.KeyLast) < PAGE_SIZE,
4397	(" pCur=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
4398	"pCur2=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4399	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias,
4400	pCur2, pCur2->Core.Key, pCur2->Core.KeyLast, pCur2->offVirtHandler, pCur2->offNextAlias));
4401	if (!(pCur2->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK))
4402	break;
4403	}
4404	}
4405
4406	pArgs->pPrevPhys2Virt = pCur;
4407	return 0;
4408	}
4409
4410
4411	/**
4412	* Perform an integrity check on the PGM component.
4413	*
4414	* @returns VINF_SUCCESS if everything is fine.
4415	* @returns VBox error status after asserting on integrity breach.
4416	* @param pVM The VM handle.
4417	*/
4418	VMMR3DECL(int) PGMR3CheckIntegrity(PVM pVM)
4419	{
4420	AssertReleaseReturn(pVM->pgm.s.offVM, VERR_INTERNAL_ERROR);
4421
4422	/*
4423	* Check the trees.
4424	*/
4425	int cErrors = 0;
4426	const static PGMCHECKINTARGS s_LeftToRight = { true, NULL, NULL, NULL, pVM };
4427	const static PGMCHECKINTARGS s_RightToLeft = { false, NULL, NULL, NULL, pVM };
4428	PGMCHECKINTARGS Args = s_LeftToRight;
4429	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysHandlers, true, pgmR3CheckIntegrityPhysHandlerNode, &Args);
4430	Args = s_RightToLeft;
4431	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysHandlers, false, pgmR3CheckIntegrityPhysHandlerNode, &Args);
4432	Args = s_LeftToRight;
4433	cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesR3->VirtHandlers, true, pgmR3CheckIntegrityVirtHandlerNode, &Args);
4434	Args = s_RightToLeft;
4435	cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesR3->VirtHandlers, false, pgmR3CheckIntegrityVirtHandlerNode, &Args);
4436	Args = s_LeftToRight;
4437	cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesR3->HyperVirtHandlers, true, pgmR3CheckIntegrityVirtHandlerNode, &Args);
4438	Args = s_RightToLeft;
4439	cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesR3->HyperVirtHandlers, false, pgmR3CheckIntegrityVirtHandlerNode, &Args);
4440	Args = s_LeftToRight;
4441	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysToVirtHandlers, true, pgmR3CheckIntegrityPhysToVirtHandlerNode, &Args);
4442	Args = s_RightToLeft;
4443	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysToVirtHandlers, false, pgmR3CheckIntegrityPhysToVirtHandlerNode, &Args);
4444
4445	return !cErrors ? VINF_SUCCESS : VERR_INTERNAL_ERROR;
4446	}
4447
4448

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source: vbox/trunk/src/VBox/VMM/PGM.cpp@ 17639

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