PGM.cpp@ 18880

Last change on this file since 18880 was 18880, checked in by vboxsync, 16 years ago
PGM/MM: Implemented the /RamPreAlloc CFGM option.
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1	/* $Id: PGM.cpp 18880 2009-04-14 09:42:01Z vboxsync $ */
2	/** @file
3	* PGM - Page Manager and Monitor. (Mixing stuff here, not good?)
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22
23	/** @page pg_pgm PGM - The Page Manager and Monitor
24	*
25	* @see grp_pgm,
26	* @ref pg_pgm_pool,
27	* @ref pg_pgm_phys.
28	*
29	*
30	* @section sec_pgm_modes Paging Modes
31	*
32	* There are three memory contexts: Host Context (HC), Guest Context (GC)
33	* and intermediate context. When talking about paging HC can also be refered to
34	* as "host paging", and GC refered to as "shadow paging".
35	*
36	* We define three basic paging modes: 32-bit, PAE and AMD64. The host paging mode
37	* is defined by the host operating system. The mode used in the shadow paging mode
38	* depends on the host paging mode and what the mode the guest is currently in. The
39	* following relation between the two is defined:
40	*
41	* @verbatim
42	Host > 32-bit \| PAE \| AMD64 \|
43	Guest \| \| \| \|
44	==v================================
45	32-bit 32-bit PAE PAE
46	-------\|--------\|--------\|--------\|
47	PAE PAE PAE PAE
48	-------\|--------\|--------\|--------\|
49	AMD64 AMD64 AMD64 AMD64
50	-------\|--------\|--------\|--------\| @endverbatim
51	*
52	* All configuration except those in the diagonal (upper left) are expected to
53	* require special effort from the switcher (i.e. a bit slower).
54	*
55	*
56	*
57	*
58	* @section sec_pgm_shw The Shadow Memory Context
59	*
60	*
61	* [..]
62	*
63	* Because of guest context mappings requires PDPT and PML4 entries to allow
64	* writing on AMD64, the two upper levels will have fixed flags whatever the
65	* guest is thinking of using there. So, when shadowing the PD level we will
66	* calculate the effective flags of PD and all the higher levels. In legacy
67	* PAE mode this only applies to the PWT and PCD bits (the rest are
68	* ignored/reserved/MBZ). We will ignore those bits for the present.
69	*
70	*
71	*
72	* @section sec_pgm_int The Intermediate Memory Context
73	*
74	* The world switch goes thru an intermediate memory context which purpose it is
75	* to provide different mappings of the switcher code. All guest mappings are also
76	* present in this context.
77	*
78	* The switcher code is mapped at the same location as on the host, at an
79	* identity mapped location (physical equals virtual address), and at the
80	* hypervisor location. The identity mapped location is for when the world
81	* switches that involves disabling paging.
82	*
83	* PGM maintain page tables for 32-bit, PAE and AMD64 paging modes. This
84	* simplifies switching guest CPU mode and consistency at the cost of more
85	* code to do the work. All memory use for those page tables is located below
86	* 4GB (this includes page tables for guest context mappings).
87	*
88	*
89	* @subsection subsec_pgm_int_gc Guest Context Mappings
90	*
91	* During assignment and relocation of a guest context mapping the intermediate
92	* memory context is used to verify the new location.
93	*
94	* Guest context mappings are currently restricted to below 4GB, for reasons
95	* of simplicity. This may change when we implement AMD64 support.
96	*
97	*
98	*
99	*
100	* @section sec_pgm_misc Misc
101	*
102	* @subsection subsec_pgm_misc_diff Differences Between Legacy PAE and Long Mode PAE
103	*
104	* The differences between legacy PAE and long mode PAE are:
105	* -# PDPE bits 1, 2, 5 and 6 are defined differently. In leagcy mode they are
106	* all marked down as must-be-zero, while in long mode 1, 2 and 5 have the
107	* usual meanings while 6 is ignored (AMD). This means that upon switching to
108	* legacy PAE mode we'll have to clear these bits and when going to long mode
109	* they must be set. This applies to both intermediate and shadow contexts,
110	* however we don't need to do it for the intermediate one since we're
111	* executing with CR0.WP at that time.
112	* -# CR3 allows a 32-byte aligned address in legacy mode, while in long mode
113	* a page aligned one is required.
114	*
115	*
116	* @section sec_pgm_handlers Access Handlers
117	*
118	* Placeholder.
119	*
120	*
121	* @subsection sec_pgm_handlers_virt Virtual Access Handlers
122	*
123	* Placeholder.
124	*
125	*
126	* @subsection sec_pgm_handlers_virt Virtual Access Handlers
127	*
128	* We currently implement three types of virtual access handlers: ALL, WRITE
129	* and HYPERVISOR (WRITE). See PGMVIRTHANDLERTYPE for some more details.
130	*
131	* The HYPERVISOR access handlers is kept in a separate tree since it doesn't apply
132	* to physical pages (PGMTREES::HyperVirtHandlers) and only needs to be consulted in
133	* a special \#PF case. The ALL and WRITE are in the PGMTREES::VirtHandlers tree, the
134	* rest of this section is going to be about these handlers.
135	*
136	* We'll go thru the life cycle of a handler and try make sense of it all, don't know
137	* how successfull this is gonna be...
138	*
139	* 1. A handler is registered thru the PGMR3HandlerVirtualRegister and
140	* PGMHandlerVirtualRegisterEx APIs. We check for conflicting virtual handlers
141	* and create a new node that is inserted into the AVL tree (range key). Then
142	* a full PGM resync is flagged (clear pool, sync cr3, update virtual bit of PGMPAGE).
143	*
144	* 2. The following PGMSyncCR3/SyncCR3 operation will first make invoke HandlerVirtualUpdate.
145	*
146	* 2a. HandlerVirtualUpdate will will lookup all the pages covered by virtual handlers
147	* via the current guest CR3 and update the physical page -> virtual handler
148	* translation. Needless to say, this doesn't exactly scale very well. If any changes
149	* are detected, it will flag a virtual bit update just like we did on registration.
150	* PGMPHYS pages with changes will have their virtual handler state reset to NONE.
151	*
152	* 2b. The virtual bit update process will iterate all the pages covered by all the
153	* virtual handlers and update the PGMPAGE virtual handler state to the max of all
154	* virtual handlers on that page.
155	*
156	* 2c. Back in SyncCR3 we will now flush the entire shadow page cache to make sure
157	* we don't miss any alias mappings of the monitored pages.
158	*
159	* 2d. SyncCR3 will then proceed with syncing the CR3 table.
160	*
161	* 3. \#PF(np,read) on a page in the range. This will cause it to be synced
162	* read-only and resumed if it's a WRITE handler. If it's an ALL handler we
163	* will call the handlers like in the next step. If the physical mapping has
164	* changed we will - some time in the future - perform a handler callback
165	* (optional) and update the physical -> virtual handler cache.
166	*
167	* 4. \#PF(,write) on a page in the range. This will cause the handler to
168	* be invoked.
169	*
170	* 5. The guest invalidates the page and changes the physical backing or
171	* unmaps it. This should cause the invalidation callback to be invoked
172	* (it might not yet be 100% perfect). Exactly what happens next... is
173	* this where we mess up and end up out of sync for a while?
174	*
175	* 6. The handler is deregistered by the client via PGMHandlerVirtualDeregister.
176	* We will then set all PGMPAGEs in the physical -> virtual handler cache for
177	* this handler to NONE and trigger a full PGM resync (basically the same
178	* as int step 1). Which means 2 is executed again.
179	*
180	*
181	* @subsubsection sub_sec_pgm_handler_virt_todo TODOs
182	*
183	* There is a bunch of things that needs to be done to make the virtual handlers
184	* work 100% correctly and work more efficiently.
185	*
186	* The first bit hasn't been implemented yet because it's going to slow the
187	* whole mess down even more, and besides it seems to be working reliably for
188	* our current uses. OTOH, some of the optimizations might end up more or less
189	* implementing the missing bits, so we'll see.
190	*
191	* On the optimization side, the first thing to do is to try avoid unnecessary
192	* cache flushing. Then try team up with the shadowing code to track changes
193	* in mappings by means of access to them (shadow in), updates to shadows pages,
194	* invlpg, and shadow PT discarding (perhaps).
195	*
196	* Some idea that have popped up for optimization for current and new features:
197	* - bitmap indicating where there are virtual handlers installed.
198	* (4KB => 220 pages, page 212 => covers 32-bit address space 1:1!)
199	* - Further optimize this by min/max (needs min/max avl getters).
200	* - Shadow page table entry bit (if any left)?
201	*
202	*/
203
204
205	/** @page pg_pgm_phys PGM Physical Guest Memory Management
206	*
207	*
208	* Objectives:
209	* - Guest RAM over-commitment using memory ballooning,
210	* zero pages and general page sharing.
211	* - Moving or mirroring a VM onto a different physical machine.
212	*
213	*
214	* @subsection subsec_pgmPhys_Definitions Definitions
215	*
216	* Allocation chunk - A RTR0MemObjAllocPhysNC object and the tracking
217	* machinery assoicated with it.
218	*
219	*
220	*
221	*
222	* @subsection subsec_pgmPhys_AllocPage Allocating a page.
223	*
224	* Initially we map all guest memory to the (per VM) zero page, which
225	* means that none of the read functions will cause pages to be allocated.
226	*
227	* Exception, access bit in page tables that have been shared. This must
228	* be handled, but we must also make sure PGMGst*Modify doesn't make
229	* unnecessary modifications.
230	*
231	* Allocation points:
232	* - PGMPhysSimpleWriteGCPhys and PGMPhysWrite.
233	* - Replacing a zero page mapping at \#PF.
234	* - Replacing a shared page mapping at \#PF.
235	* - ROM registration (currently MMR3RomRegister).
236	* - VM restore (pgmR3Load).
237	*
238	* For the first three it would make sense to keep a few pages handy
239	* until we've reached the max memory commitment for the VM.
240	*
241	* For the ROM registration, we know exactly how many pages we need
242	* and will request these from ring-0. For restore, we will save
243	* the number of non-zero pages in the saved state and allocate
244	* them up front. This would allow the ring-0 component to refuse
245	* the request if the isn't sufficient memory available for VM use.
246	*
247	* Btw. for both ROM and restore allocations we won't be requiring
248	* zeroed pages as they are going to be filled instantly.
249	*
250	*
251	* @subsection subsec_pgmPhys_FreePage Freeing a page
252	*
253	* There are a few points where a page can be freed:
254	* - After being replaced by the zero page.
255	* - After being replaced by a shared page.
256	* - After being ballooned by the guest additions.
257	* - At reset.
258	* - At restore.
259	*
260	* When freeing one or more pages they will be returned to the ring-0
261	* component and replaced by the zero page.
262	*
263	* The reasoning for clearing out all the pages on reset is that it will
264	* return us to the exact same state as on power on, and may thereby help
265	* us reduce the memory load on the system. Further it might have a
266	* (temporary) positive influence on memory fragmentation (@see subsec_pgmPhys_Fragmentation).
267	*
268	* On restore, as mention under the allocation topic, pages should be
269	* freed / allocated depending on how many is actually required by the
270	* new VM state. The simplest approach is to do like on reset, and free
271	* all non-ROM pages and then allocate what we need.
272	*
273	* A measure to prevent some fragmentation, would be to let each allocation
274	* chunk have some affinity towards the VM having allocated the most pages
275	* from it. Also, try make sure to allocate from allocation chunks that
276	* are almost full. Admittedly, both these measures might work counter to
277	* our intentions and its probably not worth putting a lot of effort,
278	* cpu time or memory into this.
279	*
280	*
281	* @subsection subsec_pgmPhys_SharePage Sharing a page
282	*
283	* The basic idea is that there there will be a idle priority kernel
284	* thread walking the non-shared VM pages hashing them and looking for
285	* pages with the same checksum. If such pages are found, it will compare
286	* them byte-by-byte to see if they actually are identical. If found to be
287	* identical it will allocate a shared page, copy the content, check that
288	* the page didn't change while doing this, and finally request both the
289	* VMs to use the shared page instead. If the page is all zeros (special
290	* checksum and byte-by-byte check) it will request the VM that owns it
291	* to replace it with the zero page.
292	*
293	* To make this efficient, we will have to make sure not to try share a page
294	* that will change its contents soon. This part requires the most work.
295	* A simple idea would be to request the VM to write monitor the page for
296	* a while to make sure it isn't modified any time soon. Also, it may
297	* make sense to skip pages that are being write monitored since this
298	* information is readily available to the thread if it works on the
299	* per-VM guest memory structures (presently called PGMRAMRANGE).
300	*
301	*
302	* @subsection subsec_pgmPhys_Fragmentation Fragmentation Concerns and Counter Measures
303	*
304	* The pages are organized in allocation chunks in ring-0, this is a necessity
305	* if we wish to have an OS agnostic approach to this whole thing. (On Linux we
306	* could easily work on a page-by-page basis if we liked. Whether this is possible
307	* or efficient on NT I don't quite know.) Fragmentation within these chunks may
308	* become a problem as part of the idea here is that we wish to return memory to
309	* the host system.
310	*
311	* For instance, starting two VMs at the same time, they will both allocate the
312	* guest memory on-demand and if permitted their page allocations will be
313	* intermixed. Shut down one of the two VMs and it will be difficult to return
314	* any memory to the host system because the page allocation for the two VMs are
315	* mixed up in the same allocation chunks.
316	*
317	* To further complicate matters, when pages are freed because they have been
318	* ballooned or become shared/zero the whole idea is that the page is supposed
319	* to be reused by another VM or returned to the host system. This will cause
320	* allocation chunks to contain pages belonging to different VMs and prevent
321	* returning memory to the host when one of those VM shuts down.
322	*
323	* The only way to really deal with this problem is to move pages. This can
324	* either be done at VM shutdown and or by the idle priority worker thread
325	* that will be responsible for finding sharable/zero pages. The mechanisms
326	* involved for coercing a VM to move a page (or to do it for it) will be
327	* the same as when telling it to share/zero a page.
328	*
329	*
330	* @subsection subsec_pgmPhys_Tracking Tracking Structures And Their Cost
331	*
332	* There's a difficult balance between keeping the per-page tracking structures
333	* (global and guest page) easy to use and keeping them from eating too much
334	* memory. We have limited virtual memory resources available when operating in
335	* 32-bit kernel space (on 64-bit there'll it's quite a different story). The
336	* tracking structures will be attemted designed such that we can deal with up
337	* to 32GB of memory on a 32-bit system and essentially unlimited on 64-bit ones.
338	*
339	*
340	* @subsubsection subsubsec_pgmPhys_Tracking_Kernel Kernel Space
341	*
342	* @see pg_GMM
343	*
344	* @subsubsection subsubsec_pgmPhys_Tracking_PerVM Per-VM
345	*
346	* Fixed info is the physical address of the page (HCPhys) and the page id
347	* (described above). Theoretically we'll need 48(-12) bits for the HCPhys part.
348	* Today we've restricting ourselves to 40(-12) bits because this is the current
349	* restrictions of all AMD64 implementations (I think Barcelona will up this
350	* to 48(-12) bits, not that it really matters) and I needed the bits for
351	* tracking mappings of a page. 48-12 = 36. That leaves 28 bits, which means a
352	* decent range for the page id: 2^(28+12) = 1024TB.
353	*
354	* In additions to these, we'll have to keep maintaining the page flags as we
355	* currently do. Although it wouldn't harm to optimize these quite a bit, like
356	* for instance the ROM shouldn't depend on having a write handler installed
357	* in order for it to become read-only. A RO/RW bit should be considered so
358	* that the page syncing code doesn't have to mess about checking multiple
359	* flag combinations (ROM \|\| RW handler \|\| write monitored) in order to
360	* figure out how to setup a shadow PTE. But this of course, is second
361	* priority at present. Current this requires 12 bits, but could probably
362	* be optimized to ~8.
363	*
364	* Then there's the 24 bits used to track which shadow page tables are
365	* currently mapping a page for the purpose of speeding up physical
366	* access handlers, and thereby the page pool cache. More bit for this
367	* purpose wouldn't hurt IIRC.
368	*
369	* Then there is a new bit in which we need to record what kind of page
370	* this is, shared, zero, normal or write-monitored-normal. This'll
371	* require 2 bits. One bit might be needed for indicating whether a
372	* write monitored page has been written to. And yet another one or
373	* two for tracking migration status. 3-4 bits total then.
374	*
375	* Whatever is left will can be used to record the sharabilitiy of a
376	* page. The page checksum will not be stored in the per-VM table as
377	* the idle thread will not be permitted to do modifications to it.
378	* It will instead have to keep its own working set of potentially
379	* shareable pages and their check sums and stuff.
380	*
381	* For the present we'll keep the current packing of the
382	* PGMRAMRANGE::aHCPhys to keep the changes simple, only of course,
383	* we'll have to change it to a struct with a total of 128-bits at
384	* our disposal.
385	*
386	* The initial layout will be like this:
387	* @verbatim
388	RTHCPHYS HCPhys; The current stuff.
389	63:40 Current shadow PT tracking stuff.
390	39:12 The physical page frame number.
391	11:0 The current flags.
392	uint32_t u28PageId : 28; The page id.
393	uint32_t u2State : 2; The page state { zero, shared, normal, write monitored }.
394	uint32_t fWrittenTo : 1; Whether a write monitored page was written to.
395	uint32_t u1Reserved : 1; Reserved for later.
396	uint32_t u32Reserved; Reserved for later, mostly sharing stats.
397	@endverbatim
398	*
399	* The final layout will be something like this:
400	* @verbatim
401	RTHCPHYS HCPhys; The current stuff.
402	63:48 High page id (12+).
403	47:12 The physical page frame number.
404	11:0 Low page id.
405	uint32_t fReadOnly : 1; Whether it's readonly page (rom or monitored in some way).
406	uint32_t u3Type : 3; The page type {RESERVED, MMIO, MMIO2, ROM, shadowed ROM, RAM}.
407	uint32_t u2PhysMon : 2; Physical access handler type {none, read, write, all}.
408	uint32_t u2VirtMon : 2; Virtual access handler type {none, read, write, all}..
409	uint32_t u2State : 2; The page state { zero, shared, normal, write monitored }.
410	uint32_t fWrittenTo : 1; Whether a write monitored page was written to.
411	uint32_t u20Reserved : 20; Reserved for later, mostly sharing stats.
412	uint32_t u32Tracking; The shadow PT tracking stuff, roughly.
413	@endverbatim
414	*
415	* Cost wise, this means we'll double the cost for guest memory. There isn't anyway
416	* around that I'm afraid. It means that the cost of dealing out 32GB of memory
417	* to one or more VMs is: (32GB >> PAGE_SHIFT) * 16 bytes, or 128MBs. Or another
418	* example, the VM heap cost when assigning 1GB to a VM will be: 4MB.
419	*
420	* A couple of cost examples for the total cost per-VM + kernel.
421	* 32-bit Windows and 32-bit linux:
422	* 1GB guest ram, 256K pages: 4MB + 2MB(+) = 6MB
423	* 4GB guest ram, 1M pages: 16MB + 8MB(+) = 24MB
424	* 32GB guest ram, 8M pages: 128MB + 64MB(+) = 192MB
425	* 64-bit Windows and 64-bit linux:
426	* 1GB guest ram, 256K pages: 4MB + 3MB(+) = 7MB
427	* 4GB guest ram, 1M pages: 16MB + 12MB(+) = 28MB
428	* 32GB guest ram, 8M pages: 128MB + 96MB(+) = 224MB
429	*
430	* UPDATE - 2007-09-27:
431	* Will need a ballooned flag/state too because we cannot
432	* trust the guest 100% and reporting the same page as ballooned more
433	* than once will put the GMM off balance.
434	*
435	*
436	* @subsection subsec_pgmPhys_Serializing Serializing Access
437	*
438	* Initially, we'll try a simple scheme:
439	*
440	* - The per-VM RAM tracking structures (PGMRAMRANGE) is only modified
441	* by the EMT thread of that VM while in the pgm critsect.
442	* - Other threads in the VM process that needs to make reliable use of
443	* the per-VM RAM tracking structures will enter the critsect.
444	* - No process external thread or kernel thread will ever try enter
445	* the pgm critical section, as that just won't work.
446	* - The idle thread (and similar threads) doesn't not need 100% reliable
447	* data when performing it tasks as the EMT thread will be the one to
448	* do the actual changes later anyway. So, as long as it only accesses
449	* the main ram range, it can do so by somehow preventing the VM from
450	* being destroyed while it works on it...
451	*
452	* - The over-commitment management, including the allocating/freeing
453	* chunks, is serialized by a ring-0 mutex lock (a fast one since the
454	* more mundane mutex implementation is broken on Linux).
455	* - A separeate mutex is protecting the set of allocation chunks so
456	* that pages can be shared or/and freed up while some other VM is
457	* allocating more chunks. This mutex can be take from under the other
458	* one, but not the otherway around.
459	*
460	*
461	* @subsection subsec_pgmPhys_Request VM Request interface
462	*
463	* When in ring-0 it will become necessary to send requests to a VM so it can
464	* for instance move a page while defragmenting during VM destroy. The idle
465	* thread will make use of this interface to request VMs to setup shared
466	* pages and to perform write monitoring of pages.
467	*
468	* I would propose an interface similar to the current VMReq interface, similar
469	* in that it doesn't require locking and that the one sending the request may
470	* wait for completion if it wishes to. This shouldn't be very difficult to
471	* realize.
472	*
473	* The requests themselves are also pretty simple. They are basically:
474	* -# Check that some precondition is still true.
475	* -# Do the update.
476	* -# Update all shadow page tables involved with the page.
477	*
478	* The 3rd step is identical to what we're already doing when updating a
479	* physical handler, see pgmHandlerPhysicalSetRamFlagsAndFlushShadowPTs.
480	*
481	*
482	*
483	* @section sec_pgmPhys_MappingCaches Mapping Caches
484	*
485	* In order to be able to map in and out memory and to be able to support
486	* guest with more RAM than we've got virtual address space, we'll employing
487	* a mapping cache. There is already a tiny one for GC (see PGMGCDynMapGCPageEx)
488	* and we'll create a similar one for ring-0 unless we decide to setup a dedicate
489	* memory context for the HWACCM execution.
490	*
491	*
492	* @subsection subsec_pgmPhys_MappingCaches_R3 Ring-3
493	*
494	* We've considered implementing the ring-3 mapping cache page based but found
495	* that this was bother some when one had to take into account TLBs+SMP and
496	* portability (missing the necessary APIs on several platforms). There were
497	* also some performance concerns with this approach which hadn't quite been
498	* worked out.
499	*
500	* Instead, we'll be mapping allocation chunks into the VM process. This simplifies
501	* matters greatly quite a bit since we don't need to invent any new ring-0 stuff,
502	* only some minor RTR0MEMOBJ mapping stuff. The main concern here is that mapping
503	* compared to the previous idea is that mapping or unmapping a 1MB chunk is more
504	* costly than a single page, although how much more costly is uncertain. We'll
505	* try address this by using a very big cache, preferably bigger than the actual
506	* VM RAM size if possible. The current VM RAM sizes should give some idea for
507	* 32-bit boxes, while on 64-bit we can probably get away with employing an
508	* unlimited cache.
509	*
510	* The cache have to parts, as already indicated, the ring-3 side and the
511	* ring-0 side.
512	*
513	* The ring-0 will be tied to the page allocator since it will operate on the
514	* memory objects it contains. It will therefore require the first ring-0 mutex
515	* discussed in @ref subsec_pgmPhys_Serializing. We
516	* some double house keeping wrt to who has mapped what I think, since both
517	* VMMR0.r0 and RTR0MemObj will keep track of mapping relataions
518	*
519	* The ring-3 part will be protected by the pgm critsect. For simplicity, we'll
520	* require anyone that desires to do changes to the mapping cache to do that
521	* from within this critsect. Alternatively, we could employ a separate critsect
522	* for serializing changes to the mapping cache as this would reduce potential
523	* contention with other threads accessing mappings unrelated to the changes
524	* that are in process. We can see about this later, contention will show
525	* up in the statistics anyway, so it'll be simple to tell.
526	*
527	* The organization of the ring-3 part will be very much like how the allocation
528	* chunks are organized in ring-0, that is in an AVL tree by chunk id. To avoid
529	* having to walk the tree all the time, we'll have a couple of lookaside entries
530	* like in we do for I/O ports and MMIO in IOM.
531	*
532	* The simplified flow of a PGMPhysRead/Write function:
533	* -# Enter the PGM critsect.
534	* -# Lookup GCPhys in the ram ranges and get the Page ID.
535	* -# Calc the Allocation Chunk ID from the Page ID.
536	* -# Check the lookaside entries and then the AVL tree for the Chunk ID.
537	* If not found in cache:
538	* -# Call ring-0 and request it to be mapped and supply
539	* a chunk to be unmapped if the cache is maxed out already.
540	* -# Insert the new mapping into the AVL tree (id + R3 address).
541	* -# Update the relevant lookaside entry and return the mapping address.
542	* -# Do the read/write according to monitoring flags and everything.
543	* -# Leave the critsect.
544	*
545	*
546	* @section sec_pgmPhys_Fallback Fallback
547	*
548	* Current all the "second tier" hosts will not support the RTR0MemObjAllocPhysNC
549	* API and thus require a fallback.
550	*
551	* So, when RTR0MemObjAllocPhysNC returns VERR_NOT_SUPPORTED the page allocator
552	* will return to the ring-3 caller (and later ring-0) and asking it to seed
553	* the page allocator with some fresh pages (VERR_GMM_SEED_ME). Ring-3 will
554	* then perform an SUPPageAlloc(cbChunk >> PAGE_SHIFT) call and make a
555	* "SeededAllocPages" call to ring-0.
556	*
557	* The first time ring-0 sees the VERR_NOT_SUPPORTED failure it will disable
558	* all page sharing (zero page detection will continue). It will also force
559	* all allocations to come from the VM which seeded the page. Both these
560	* measures are taken to make sure that there will never be any need for
561	* mapping anything into ring-3 - everything will be mapped already.
562	*
563	* Whether we'll continue to use the current MM locked memory management
564	* for this I don't quite know (I'd prefer not to and just ditch that all
565	* togther), we'll see what's simplest to do.
566	*
567	*
568	*
569	* @section sec_pgmPhys_Changes Changes
570	*
571	* Breakdown of the changes involved?
572	*/
573
574	/*******************************************************************************
575	* Header Files *
576	*******************************************************************************/
577	#define LOG_GROUP LOG_GROUP_PGM
578	#include <VBox/dbgf.h>
579	#include <VBox/pgm.h>
580	#include <VBox/cpum.h>
581	#include <VBox/iom.h>
582	#include <VBox/sup.h>
583	#include <VBox/mm.h>
584	#include <VBox/em.h>
585	#include <VBox/stam.h>
586	#include <VBox/rem.h>
587	#include <VBox/dbgf.h>
588	#include <VBox/rem.h>
589	#include <VBox/selm.h>
590	#include <VBox/ssm.h>
591	#include "PGMInternal.h"
592	#include <VBox/vm.h>
593	#include <VBox/dbg.h>
594	#include <VBox/hwaccm.h>
595
596	#include <iprt/assert.h>
597	#include <iprt/alloc.h>
598	#include <iprt/asm.h>
599	#include <iprt/thread.h>
600	#include <iprt/string.h>
601	#ifdef DEBUG_bird
602	# include <iprt/env.h>
603	#endif
604	#include <VBox/param.h>
605	#include <VBox/err.h>
606
607
608	/*******************************************************************************
609	* Defined Constants And Macros *
610	*******************************************************************************/
611	/** Saved state data unit version for 2.2.2 and later. */
612	#define PGM_SAVED_STATE_VERSION 8
613	/** Saved state data unit version for 2.2.0. */
614	#define PGM_SAVED_STATE_VERSION_RR_DESC 7
615	/** Saved state data unit version 2.1.x and earlier. */
616	#define PGM_SAVED_STATE_VERSION_OLD_PHYS_CODE 6
617
618
619	/*******************************************************************************
620	* Internal Functions *
621	*******************************************************************************/
622	static int pgmR3InitPaging(PVM pVM);
623	static void pgmR3InitStats(PVM pVM);
624	static DECLCALLBACK(void) pgmR3PhysInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
625	static DECLCALLBACK(void) pgmR3InfoMode(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
626	static DECLCALLBACK(void) pgmR3InfoCr3(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
627	static DECLCALLBACK(int) pgmR3RelocatePhysHandler(PAVLROGCPHYSNODECORE pNode, void *pvUser);
628	static DECLCALLBACK(int) pgmR3RelocateVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser);
629	static DECLCALLBACK(int) pgmR3RelocateHyperVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser);
630	#ifdef VBOX_STRICT
631	static DECLCALLBACK(void) pgmR3ResetNoMorePhysWritesFlag(PVM pVM, VMSTATE enmState, VMSTATE enmOldState, void *pvUser);
632	#endif
633	static DECLCALLBACK(int) pgmR3Save(PVM pVM, PSSMHANDLE pSSM);
634	static DECLCALLBACK(int) pgmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version);
635	static int pgmR3ModeDataInit(PVM pVM, bool fResolveGCAndR0);
636	static void pgmR3ModeDataSwitch(PVM pVM, PGMMODE enmShw, PGMMODE enmGst);
637	static PGMMODE pgmR3CalcShadowMode(PVM pVM, PGMMODE enmGuestMode, SUPPAGINGMODE enmHostMode, PGMMODE enmShadowMode, VMMSWITCHER *penmSwitcher);
638
639	#ifdef VBOX_WITH_DEBUGGER
640	/** @todo Convert the first two commands to 'info' items. */
641	static DECLCALLBACK(int) pgmR3CmdRam(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
642	static DECLCALLBACK(int) pgmR3CmdMap(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
643	static DECLCALLBACK(int) pgmR3CmdError(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
644	static DECLCALLBACK(int) pgmR3CmdSync(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
645	static DECLCALLBACK(int) pgmR3CmdSyncAlways(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
646	# ifdef VBOX_STRICT
647	static DECLCALLBACK(int) pgmR3CmdAssertCR3(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
648	# endif
649	#endif
650
651
652	/*******************************************************************************
653	* Global Variables *
654	*******************************************************************************/
655	#ifdef VBOX_WITH_DEBUGGER
656	/** Argument descriptors for '.pgmerror' and '.pgmerroroff'. */
657	static const DBGCVARDESC g_aPgmErrorArgs[] =
658	{
659	/* cTimesMin, cTimesMax, enmCategory, fFlags, pszName, pszDescription */
660	{ 0, 1, DBGCVAR_CAT_STRING, 0, "where", "Error injection location." },
661	};
662
663	/** Command descriptors. */
664	static const DBGCCMD g_aCmds[] =
665	{
666	/* pszCmd, cArgsMin, cArgsMax, paArgDesc, cArgDescs, pResultDesc, fFlags, pfnHandler pszSyntax, ....pszDescription */
667	{ "pgmram", 0, 0, NULL, 0, NULL, 0, pgmR3CmdRam, "", "Display the ram ranges." },
668	{ "pgmmap", 0, 0, NULL, 0, NULL, 0, pgmR3CmdMap, "", "Display the mapping ranges." },
669	{ "pgmsync", 0, 0, NULL, 0, NULL, 0, pgmR3CmdSync, "", "Sync the CR3 page." },
670	{ "pgmerror", 0, 1, &g_aPgmErrorArgs[0],1, NULL, 0, pgmR3CmdError, "", "Enables inject runtime of errors into parts of PGM." },
671	{ "pgmerroroff", 0, 1, &g_aPgmErrorArgs[0],1, NULL, 0, pgmR3CmdError, "", "Disables inject runtime errors into parts of PGM." },
672	#ifdef VBOX_STRICT
673	{ "pgmassertcr3", 0, 0, NULL, 0, NULL, 0, pgmR3CmdAssertCR3, "", "Check the shadow CR3 mapping." },
674	#endif
675	{ "pgmsyncalways", 0, 0, NULL, 0, NULL, 0, pgmR3CmdSyncAlways, "", "Toggle permanent CR3 syncing." },
676	};
677	#endif
678
679
680
681
682	/*
683	* Shadow - 32-bit mode
684	*/
685	#define PGM_SHW_TYPE PGM_TYPE_32BIT
686	#define PGM_SHW_NAME(name) PGM_SHW_NAME_32BIT(name)
687	#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_32BIT_STR(name)
688	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_32BIT_STR(name)
689	#include "PGMShw.h"
690
691	/* Guest - real mode */
692	#define PGM_GST_TYPE PGM_TYPE_REAL
693	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
694	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_REAL_STR(name)
695	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
696	#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_REAL(name)
697	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_32BIT_REAL_STR(name)
698	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_32BIT_REAL_STR(name)
699	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_PHYS
700	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_32BIT_PD_PHYS
701	#include "PGMBth.h"
702	#include "PGMGstDefs.h"
703	#include "PGMGst.h"
704	#undef BTH_PGMPOOLKIND_PT_FOR_PT
705	#undef BTH_PGMPOOLKIND_ROOT
706	#undef PGM_BTH_NAME
707	#undef PGM_BTH_NAME_RC_STR
708	#undef PGM_BTH_NAME_R0_STR
709	#undef PGM_GST_TYPE
710	#undef PGM_GST_NAME
711	#undef PGM_GST_NAME_RC_STR
712	#undef PGM_GST_NAME_R0_STR
713
714	/* Guest - protected mode */
715	#define PGM_GST_TYPE PGM_TYPE_PROT
716	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
717	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PROT_STR(name)
718	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
719	#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_PROT(name)
720	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_32BIT_PROT_STR(name)
721	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_32BIT_PROT_STR(name)
722	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_PHYS
723	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_32BIT_PD_PHYS
724	#include "PGMBth.h"
725	#include "PGMGstDefs.h"
726	#include "PGMGst.h"
727	#undef BTH_PGMPOOLKIND_PT_FOR_PT
728	#undef BTH_PGMPOOLKIND_ROOT
729	#undef PGM_BTH_NAME
730	#undef PGM_BTH_NAME_RC_STR
731	#undef PGM_BTH_NAME_R0_STR
732	#undef PGM_GST_TYPE
733	#undef PGM_GST_NAME
734	#undef PGM_GST_NAME_RC_STR
735	#undef PGM_GST_NAME_R0_STR
736
737	/* Guest - 32-bit mode */
738	#define PGM_GST_TYPE PGM_TYPE_32BIT
739	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
740	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_32BIT_STR(name)
741	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
742	#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_32BIT(name)
743	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_32BIT_32BIT_STR(name)
744	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_32BIT_32BIT_STR(name)
745	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT
746	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB
747	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_32BIT_PD
748	#include "PGMBth.h"
749	#include "PGMGstDefs.h"
750	#include "PGMGst.h"
751	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
752	#undef BTH_PGMPOOLKIND_PT_FOR_PT
753	#undef BTH_PGMPOOLKIND_ROOT
754	#undef PGM_BTH_NAME
755	#undef PGM_BTH_NAME_RC_STR
756	#undef PGM_BTH_NAME_R0_STR
757	#undef PGM_GST_TYPE
758	#undef PGM_GST_NAME
759	#undef PGM_GST_NAME_RC_STR
760	#undef PGM_GST_NAME_R0_STR
761
762	#undef PGM_SHW_TYPE
763	#undef PGM_SHW_NAME
764	#undef PGM_SHW_NAME_RC_STR
765	#undef PGM_SHW_NAME_R0_STR
766
767
768	/*
769	* Shadow - PAE mode
770	*/
771	#define PGM_SHW_TYPE PGM_TYPE_PAE
772	#define PGM_SHW_NAME(name) PGM_SHW_NAME_PAE(name)
773	#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_PAE_STR(name)
774	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_PAE_STR(name)
775	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_REAL(name)
776	#include "PGMShw.h"
777
778	/* Guest - real mode */
779	#define PGM_GST_TYPE PGM_TYPE_REAL
780	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
781	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_REAL_STR(name)
782	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
783	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_REAL(name)
784	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_PAE_REAL_STR(name)
785	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_REAL_STR(name)
786	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
787	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT_PHYS
788	#include "PGMGstDefs.h"
789	#include "PGMBth.h"
790	#undef BTH_PGMPOOLKIND_PT_FOR_PT
791	#undef BTH_PGMPOOLKIND_ROOT
792	#undef PGM_BTH_NAME
793	#undef PGM_BTH_NAME_RC_STR
794	#undef PGM_BTH_NAME_R0_STR
795	#undef PGM_GST_TYPE
796	#undef PGM_GST_NAME
797	#undef PGM_GST_NAME_RC_STR
798	#undef PGM_GST_NAME_R0_STR
799
800	/* Guest - protected mode */
801	#define PGM_GST_TYPE PGM_TYPE_PROT
802	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
803	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PROT_STR(name)
804	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
805	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_PROT(name)
806	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_PAE_PROT_STR(name)
807	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_PROT_STR(name)
808	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
809	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT_PHYS
810	#include "PGMGstDefs.h"
811	#include "PGMBth.h"
812	#undef BTH_PGMPOOLKIND_PT_FOR_PT
813	#undef BTH_PGMPOOLKIND_ROOT
814	#undef PGM_BTH_NAME
815	#undef PGM_BTH_NAME_RC_STR
816	#undef PGM_BTH_NAME_R0_STR
817	#undef PGM_GST_TYPE
818	#undef PGM_GST_NAME
819	#undef PGM_GST_NAME_RC_STR
820	#undef PGM_GST_NAME_R0_STR
821
822	/* Guest - 32-bit mode */
823	#define PGM_GST_TYPE PGM_TYPE_32BIT
824	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
825	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_32BIT_STR(name)
826	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
827	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_32BIT(name)
828	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_PAE_32BIT_STR(name)
829	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_32BIT_STR(name)
830	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_32BIT_PT
831	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB
832	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT_FOR_32BIT
833	#include "PGMGstDefs.h"
834	#include "PGMBth.h"
835	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
836	#undef BTH_PGMPOOLKIND_PT_FOR_PT
837	#undef BTH_PGMPOOLKIND_ROOT
838	#undef PGM_BTH_NAME
839	#undef PGM_BTH_NAME_RC_STR
840	#undef PGM_BTH_NAME_R0_STR
841	#undef PGM_GST_TYPE
842	#undef PGM_GST_NAME
843	#undef PGM_GST_NAME_RC_STR
844	#undef PGM_GST_NAME_R0_STR
845
846	/* Guest - PAE mode */
847	#define PGM_GST_TYPE PGM_TYPE_PAE
848	#define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
849	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PAE_STR(name)
850	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PAE_STR(name)
851	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_PAE(name)
852	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_PAE_PAE_STR(name)
853	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_PAE_STR(name)
854	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
855	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
856	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT
857	#include "PGMBth.h"
858	#include "PGMGstDefs.h"
859	#include "PGMGst.h"
860	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
861	#undef BTH_PGMPOOLKIND_PT_FOR_PT
862	#undef BTH_PGMPOOLKIND_ROOT
863	#undef PGM_BTH_NAME
864	#undef PGM_BTH_NAME_RC_STR
865	#undef PGM_BTH_NAME_R0_STR
866	#undef PGM_GST_TYPE
867	#undef PGM_GST_NAME
868	#undef PGM_GST_NAME_RC_STR
869	#undef PGM_GST_NAME_R0_STR
870
871	#undef PGM_SHW_TYPE
872	#undef PGM_SHW_NAME
873	#undef PGM_SHW_NAME_RC_STR
874	#undef PGM_SHW_NAME_R0_STR
875
876
877	/*
878	* Shadow - AMD64 mode
879	*/
880	#define PGM_SHW_TYPE PGM_TYPE_AMD64
881	#define PGM_SHW_NAME(name) PGM_SHW_NAME_AMD64(name)
882	#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_AMD64_STR(name)
883	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_AMD64_STR(name)
884	#include "PGMShw.h"
885
886	#ifdef VBOX_WITH_64_BITS_GUESTS
887	/* Guest - AMD64 mode */
888	# define PGM_GST_TYPE PGM_TYPE_AMD64
889	# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
890	# define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_AMD64_STR(name)
891	# define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_AMD64_STR(name)
892	# define PGM_BTH_NAME(name) PGM_BTH_NAME_AMD64_AMD64(name)
893	# define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_AMD64_AMD64_STR(name)
894	# define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_AMD64_AMD64_STR(name)
895	# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
896	# define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
897	# define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_64BIT_PML4
898	# include "PGMBth.h"
899	# include "PGMGstDefs.h"
900	# include "PGMGst.h"
901	# undef BTH_PGMPOOLKIND_PT_FOR_BIG
902	# undef BTH_PGMPOOLKIND_PT_FOR_PT
903	# undef BTH_PGMPOOLKIND_ROOT
904	# undef PGM_BTH_NAME
905	# undef PGM_BTH_NAME_RC_STR
906	# undef PGM_BTH_NAME_R0_STR
907	# undef PGM_GST_TYPE
908	# undef PGM_GST_NAME
909	# undef PGM_GST_NAME_RC_STR
910	# undef PGM_GST_NAME_R0_STR
911	#endif /* VBOX_WITH_64_BITS_GUESTS */
912
913	#undef PGM_SHW_TYPE
914	#undef PGM_SHW_NAME
915	#undef PGM_SHW_NAME_RC_STR
916	#undef PGM_SHW_NAME_R0_STR
917
918
919	/*
920	* Shadow - Nested paging mode
921	*/
922	#define PGM_SHW_TYPE PGM_TYPE_NESTED
923	#define PGM_SHW_NAME(name) PGM_SHW_NAME_NESTED(name)
924	#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_NESTED_STR(name)
925	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_NESTED_STR(name)
926	#include "PGMShw.h"
927
928	/* Guest - real mode */
929	#define PGM_GST_TYPE PGM_TYPE_REAL
930	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
931	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_REAL_STR(name)
932	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
933	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_REAL(name)
934	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_REAL_STR(name)
935	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_REAL_STR(name)
936	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
937	#include "PGMGstDefs.h"
938	#include "PGMBth.h"
939	#undef BTH_PGMPOOLKIND_PT_FOR_PT
940	#undef PGM_BTH_NAME
941	#undef PGM_BTH_NAME_RC_STR
942	#undef PGM_BTH_NAME_R0_STR
943	#undef PGM_GST_TYPE
944	#undef PGM_GST_NAME
945	#undef PGM_GST_NAME_RC_STR
946	#undef PGM_GST_NAME_R0_STR
947
948	/* Guest - protected mode */
949	#define PGM_GST_TYPE PGM_TYPE_PROT
950	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
951	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PROT_STR(name)
952	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
953	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_PROT(name)
954	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_PROT_STR(name)
955	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_PROT_STR(name)
956	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
957	#include "PGMGstDefs.h"
958	#include "PGMBth.h"
959	#undef BTH_PGMPOOLKIND_PT_FOR_PT
960	#undef PGM_BTH_NAME
961	#undef PGM_BTH_NAME_RC_STR
962	#undef PGM_BTH_NAME_R0_STR
963	#undef PGM_GST_TYPE
964	#undef PGM_GST_NAME
965	#undef PGM_GST_NAME_RC_STR
966	#undef PGM_GST_NAME_R0_STR
967
968	/* Guest - 32-bit mode */
969	#define PGM_GST_TYPE PGM_TYPE_32BIT
970	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
971	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_32BIT_STR(name)
972	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
973	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_32BIT(name)
974	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_32BIT_STR(name)
975	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_32BIT_STR(name)
976	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_32BIT_PT
977	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB
978	#include "PGMGstDefs.h"
979	#include "PGMBth.h"
980	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
981	#undef BTH_PGMPOOLKIND_PT_FOR_PT
982	#undef PGM_BTH_NAME
983	#undef PGM_BTH_NAME_RC_STR
984	#undef PGM_BTH_NAME_R0_STR
985	#undef PGM_GST_TYPE
986	#undef PGM_GST_NAME
987	#undef PGM_GST_NAME_RC_STR
988	#undef PGM_GST_NAME_R0_STR
989
990	/* Guest - PAE mode */
991	#define PGM_GST_TYPE PGM_TYPE_PAE
992	#define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
993	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PAE_STR(name)
994	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PAE_STR(name)
995	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_PAE(name)
996	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_PAE_STR(name)
997	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_PAE_STR(name)
998	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
999	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
1000	#include "PGMGstDefs.h"
1001	#include "PGMBth.h"
1002	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
1003	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1004	#undef PGM_BTH_NAME
1005	#undef PGM_BTH_NAME_RC_STR
1006	#undef PGM_BTH_NAME_R0_STR
1007	#undef PGM_GST_TYPE
1008	#undef PGM_GST_NAME
1009	#undef PGM_GST_NAME_RC_STR
1010	#undef PGM_GST_NAME_R0_STR
1011
1012	#ifdef VBOX_WITH_64_BITS_GUESTS
1013	/* Guest - AMD64 mode */
1014	# define PGM_GST_TYPE PGM_TYPE_AMD64
1015	# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
1016	# define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_AMD64_STR(name)
1017	# define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_AMD64_STR(name)
1018	# define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_AMD64(name)
1019	# define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_AMD64_STR(name)
1020	# define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_AMD64_STR(name)
1021	# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
1022	# define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
1023	# include "PGMGstDefs.h"
1024	# include "PGMBth.h"
1025	# undef BTH_PGMPOOLKIND_PT_FOR_BIG
1026	# undef BTH_PGMPOOLKIND_PT_FOR_PT
1027	# undef PGM_BTH_NAME
1028	# undef PGM_BTH_NAME_RC_STR
1029	# undef PGM_BTH_NAME_R0_STR
1030	# undef PGM_GST_TYPE
1031	# undef PGM_GST_NAME
1032	# undef PGM_GST_NAME_RC_STR
1033	# undef PGM_GST_NAME_R0_STR
1034	#endif /* VBOX_WITH_64_BITS_GUESTS */
1035
1036	#undef PGM_SHW_TYPE
1037	#undef PGM_SHW_NAME
1038	#undef PGM_SHW_NAME_RC_STR
1039	#undef PGM_SHW_NAME_R0_STR
1040
1041
1042	/*
1043	* Shadow - EPT
1044	*/
1045	#define PGM_SHW_TYPE PGM_TYPE_EPT
1046	#define PGM_SHW_NAME(name) PGM_SHW_NAME_EPT(name)
1047	#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_EPT_STR(name)
1048	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_EPT_STR(name)
1049	#include "PGMShw.h"
1050
1051	/* Guest - real mode */
1052	#define PGM_GST_TYPE PGM_TYPE_REAL
1053	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
1054	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_REAL_STR(name)
1055	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
1056	#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_REAL(name)
1057	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_REAL_STR(name)
1058	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_REAL_STR(name)
1059	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
1060	#include "PGMGstDefs.h"
1061	#include "PGMBth.h"
1062	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1063	#undef PGM_BTH_NAME
1064	#undef PGM_BTH_NAME_RC_STR
1065	#undef PGM_BTH_NAME_R0_STR
1066	#undef PGM_GST_TYPE
1067	#undef PGM_GST_NAME
1068	#undef PGM_GST_NAME_RC_STR
1069	#undef PGM_GST_NAME_R0_STR
1070
1071	/* Guest - protected mode */
1072	#define PGM_GST_TYPE PGM_TYPE_PROT
1073	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
1074	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PROT_STR(name)
1075	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
1076	#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_PROT(name)
1077	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_PROT_STR(name)
1078	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_PROT_STR(name)
1079	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
1080	#include "PGMGstDefs.h"
1081	#include "PGMBth.h"
1082	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1083	#undef PGM_BTH_NAME
1084	#undef PGM_BTH_NAME_RC_STR
1085	#undef PGM_BTH_NAME_R0_STR
1086	#undef PGM_GST_TYPE
1087	#undef PGM_GST_NAME
1088	#undef PGM_GST_NAME_RC_STR
1089	#undef PGM_GST_NAME_R0_STR
1090
1091	/* Guest - 32-bit mode */
1092	#define PGM_GST_TYPE PGM_TYPE_32BIT
1093	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
1094	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_32BIT_STR(name)
1095	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
1096	#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_32BIT(name)
1097	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_32BIT_STR(name)
1098	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_32BIT_STR(name)
1099	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_32BIT_PT
1100	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB
1101	#include "PGMGstDefs.h"
1102	#include "PGMBth.h"
1103	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
1104	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1105	#undef PGM_BTH_NAME
1106	#undef PGM_BTH_NAME_RC_STR
1107	#undef PGM_BTH_NAME_R0_STR
1108	#undef PGM_GST_TYPE
1109	#undef PGM_GST_NAME
1110	#undef PGM_GST_NAME_RC_STR
1111	#undef PGM_GST_NAME_R0_STR
1112
1113	/* Guest - PAE mode */
1114	#define PGM_GST_TYPE PGM_TYPE_PAE
1115	#define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
1116	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PAE_STR(name)
1117	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PAE_STR(name)
1118	#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_PAE(name)
1119	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_PAE_STR(name)
1120	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_PAE_STR(name)
1121	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
1122	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
1123	#include "PGMGstDefs.h"
1124	#include "PGMBth.h"
1125	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
1126	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1127	#undef PGM_BTH_NAME
1128	#undef PGM_BTH_NAME_RC_STR
1129	#undef PGM_BTH_NAME_R0_STR
1130	#undef PGM_GST_TYPE
1131	#undef PGM_GST_NAME
1132	#undef PGM_GST_NAME_RC_STR
1133	#undef PGM_GST_NAME_R0_STR
1134
1135	#ifdef VBOX_WITH_64_BITS_GUESTS
1136	/* Guest - AMD64 mode */
1137	# define PGM_GST_TYPE PGM_TYPE_AMD64
1138	# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
1139	# define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_AMD64_STR(name)
1140	# define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_AMD64_STR(name)
1141	# define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_AMD64(name)
1142	# define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_AMD64_STR(name)
1143	# define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_AMD64_STR(name)
1144	# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
1145	# define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
1146	# include "PGMGstDefs.h"
1147	# include "PGMBth.h"
1148	# undef BTH_PGMPOOLKIND_PT_FOR_BIG
1149	# undef BTH_PGMPOOLKIND_PT_FOR_PT
1150	# undef PGM_BTH_NAME
1151	# undef PGM_BTH_NAME_RC_STR
1152	# undef PGM_BTH_NAME_R0_STR
1153	# undef PGM_GST_TYPE
1154	# undef PGM_GST_NAME
1155	# undef PGM_GST_NAME_RC_STR
1156	# undef PGM_GST_NAME_R0_STR
1157	#endif /* VBOX_WITH_64_BITS_GUESTS */
1158
1159	#undef PGM_SHW_TYPE
1160	#undef PGM_SHW_NAME
1161	#undef PGM_SHW_NAME_RC_STR
1162	#undef PGM_SHW_NAME_R0_STR
1163
1164
1165
1166	/**
1167	* Initiates the paging of VM.
1168	*
1169	* @returns VBox status code.
1170	* @param pVM Pointer to VM structure.
1171	*/
1172	VMMR3DECL(int) PGMR3Init(PVM pVM)
1173	{
1174	LogFlow(("PGMR3Init:\n"));
1175	PCFGMNODE pCfgPGM = CFGMR3GetChild(CFGMR3GetRoot(pVM), "/PGM");
1176	int rc;
1177
1178	/*
1179	* Assert alignment and sizes.
1180	*/
1181	AssertRelease(sizeof(pVM->pgm.s) <= sizeof(pVM->pgm.padding));
1182
1183	/*
1184	* Init the structure.
1185	*/
1186	pVM->pgm.s.offVM = RT_OFFSETOF(VM, pgm.s);
1187	pVM->pgm.s.offVCpu = RT_OFFSETOF(VMCPU, pgm.s);
1188	pVM->pgm.s.enmShadowMode = PGMMODE_INVALID;
1189	pVM->pgm.s.enmGuestMode = PGMMODE_INVALID;
1190	pVM->pgm.s.enmHostMode = SUPPAGINGMODE_INVALID;
1191	pVM->pgm.s.GCPhysCR3 = NIL_RTGCPHYS;
1192	pVM->pgm.s.GCPtrPrevRamRangeMapping = MM_HYPER_AREA_ADDRESS;
1193	pVM->pgm.s.fA20Enabled = true;
1194	pVM->pgm.s.GCPhys4MBPSEMask = RT_BIT_64(32) - 1; /* default; checked later */
1195	pVM->pgm.s.pGstPaePdptR3 = NULL;
1196	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
1197	pVM->pgm.s.pGstPaePdptR0 = NIL_RTR0PTR;
1198	#endif
1199	pVM->pgm.s.pGstPaePdptRC = NIL_RTRCPTR;
1200	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.apGstPaePDsR3); i++)
1201	{
1202	pVM->pgm.s.apGstPaePDsR3[i] = NULL;
1203	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
1204	pVM->pgm.s.apGstPaePDsR0[i] = NIL_RTR0PTR;
1205	#endif
1206	pVM->pgm.s.apGstPaePDsRC[i] = NIL_RTRCPTR;
1207	pVM->pgm.s.aGCPhysGstPaePDs[i] = NIL_RTGCPHYS;
1208	pVM->pgm.s.aGCPhysGstPaePDsMonitored[i] = NIL_RTGCPHYS;
1209	}
1210
1211	rc = CFGMR3QueryBoolDef(CFGMR3GetRoot(pVM), "RamPreAlloc", &pVM->pgm.s.fRamPreAlloc, false);
1212	AssertLogRelRCReturn(rc, rc);
1213
1214	#if HC_ARCH_BITS == 64 \|\| 1 /** @todo 4GB/32-bit: remove \|\| 1 later and adjust the limit. */
1215	rc = CFGMR3QueryU32Def(pCfgPGM, "MaxRing3Chunks", &pVM->pgm.s.ChunkR3Map.cMax, UINT32_MAX);
1216	#else
1217	rc = CFGMR3QueryU32Def(pCfgPGM, "MaxRing3Chunks", &pVM->pgm.s.ChunkR3Map.cMax, _1G / GMM_CHUNK_SIZE);
1218	#endif
1219	AssertLogRelRCReturn(rc, rc);
1220	for (uint32_t i = 0; i < RT_ELEMENTS(pVM->pgm.s.ChunkR3Map.Tlb.aEntries); i++)
1221	pVM->pgm.s.ChunkR3Map.Tlb.aEntries[i].idChunk = NIL_GMM_CHUNKID;
1222
1223	/*
1224	* Get the configured RAM size - to estimate saved state size.
1225	*/
1226	uint64_t cbRam;
1227	rc = CFGMR3QueryU64(CFGMR3GetRoot(pVM), "RamSize", &cbRam);
1228	if (rc == VERR_CFGM_VALUE_NOT_FOUND)
1229	cbRam = 0;
1230	else if (RT_SUCCESS(rc))
1231	{
1232	if (cbRam < PAGE_SIZE)
1233	cbRam = 0;
1234	cbRam = RT_ALIGN_64(cbRam, PAGE_SIZE);
1235	}
1236	else
1237	{
1238	AssertMsgFailed(("Configuration error: Failed to query integer \"RamSize\", rc=%Rrc.\n", rc));
1239	return rc;
1240	}
1241
1242	/*
1243	* Register callbacks, string formatters and the saved state data unit.
1244	*/
1245	#ifdef VBOX_STRICT
1246	VMR3AtStateRegister(pVM, pgmR3ResetNoMorePhysWritesFlag, NULL);
1247	#endif
1248	PGMRegisterStringFormatTypes();
1249
1250	rc = SSMR3RegisterInternal(pVM, "pgm", 1, PGM_SAVED_STATE_VERSION, (size_t)cbRam + sizeof(PGM),
1251	NULL, pgmR3Save, NULL,
1252	NULL, pgmR3Load, NULL);
1253	if (RT_FAILURE(rc))
1254	return rc;
1255
1256	/*
1257	* Initialize the PGM critical section and flush the phys TLBs
1258	*/
1259	rc = PDMR3CritSectInit(pVM, &pVM->pgm.s.CritSect, "PGM");
1260	AssertRCReturn(rc, rc);
1261
1262	PGMR3PhysChunkInvalidateTLB(pVM);
1263	PGMPhysInvalidatePageR3MapTLB(pVM);
1264	PGMPhysInvalidatePageR0MapTLB(pVM);
1265	PGMPhysInvalidatePageGCMapTLB(pVM);
1266
1267	/*
1268	* For the time being we sport a full set of handy pages in addition to the base
1269	* memory to simplify things.
1270	*/
1271	rc = MMR3ReserveHandyPages(pVM, RT_ELEMENTS(pVM->pgm.s.aHandyPages)); /** @todo this should be changed to PGM_HANDY_PAGES_MIN but this needs proper testing... */
1272	AssertRCReturn(rc, rc);
1273
1274	/*
1275	* Trees
1276	*/
1277	rc = MMHyperAlloc(pVM, sizeof(PGMTREES), 0, MM_TAG_PGM, (void **)&pVM->pgm.s.pTreesR3);
1278	if (RT_SUCCESS(rc))
1279	{
1280	pVM->pgm.s.pTreesR0 = MMHyperR3ToR0(pVM, pVM->pgm.s.pTreesR3);
1281	pVM->pgm.s.pTreesRC = MMHyperR3ToRC(pVM, pVM->pgm.s.pTreesR3);
1282
1283	/*
1284	* Alocate the zero page.
1285	*/
1286	rc = MMHyperAlloc(pVM, PAGE_SIZE, PAGE_SIZE, MM_TAG_PGM, &pVM->pgm.s.pvZeroPgR3);
1287	}
1288	if (RT_SUCCESS(rc))
1289	{
1290	pVM->pgm.s.pvZeroPgRC = MMHyperR3ToRC(pVM, pVM->pgm.s.pvZeroPgR3);
1291	pVM->pgm.s.pvZeroPgR0 = MMHyperR3ToR0(pVM, pVM->pgm.s.pvZeroPgR3);
1292	pVM->pgm.s.HCPhysZeroPg = MMR3HyperHCVirt2HCPhys(pVM, pVM->pgm.s.pvZeroPgR3);
1293	AssertRelease(pVM->pgm.s.HCPhysZeroPg != NIL_RTHCPHYS);
1294
1295	/*
1296	* Init the paging.
1297	*/
1298	rc = pgmR3InitPaging(pVM);
1299	}
1300	if (RT_SUCCESS(rc))
1301	{
1302	/*
1303	* Init the page pool.
1304	*/
1305	rc = pgmR3PoolInit(pVM);
1306	}
1307	if (RT_SUCCESS(rc))
1308	rc = PGMR3ChangeMode(pVM, PGMMODE_REAL);
1309
1310	if (RT_SUCCESS(rc))
1311	{
1312	/*
1313	* Info & statistics
1314	*/
1315	DBGFR3InfoRegisterInternal(pVM, "mode",
1316	"Shows the current paging mode. "
1317	"Recognizes 'all', 'guest', 'shadow' and 'host' as arguments, defaulting to 'all' if nothing's given.",
1318	pgmR3InfoMode);
1319	DBGFR3InfoRegisterInternal(pVM, "pgmcr3",
1320	"Dumps all the entries in the top level paging table. No arguments.",
1321	pgmR3InfoCr3);
1322	DBGFR3InfoRegisterInternal(pVM, "phys",
1323	"Dumps all the physical address ranges. No arguments.",
1324	pgmR3PhysInfo);
1325	DBGFR3InfoRegisterInternal(pVM, "handlers",
1326	"Dumps physical, virtual and hyper virtual handlers. "
1327	"Pass 'phys', 'virt', 'hyper' as argument if only one kind is wanted."
1328	"Add 'nost' if the statistics are unwanted, use together with 'all' or explicit selection.",
1329	pgmR3InfoHandlers);
1330	DBGFR3InfoRegisterInternal(pVM, "mappings",
1331	"Dumps guest mappings.",
1332	pgmR3MapInfo);
1333
1334	pgmR3InitStats(pVM);
1335
1336	#ifdef VBOX_WITH_DEBUGGER
1337	/*
1338	* Debugger commands.
1339	*/
1340	static bool s_fRegisteredCmds = false;
1341	if (!s_fRegisteredCmds)
1342	{
1343	int rc = DBGCRegisterCommands(&g_aCmds[0], RT_ELEMENTS(g_aCmds));
1344	if (RT_SUCCESS(rc))
1345	s_fRegisteredCmds = true;
1346	}
1347	#endif
1348	return VINF_SUCCESS;
1349	}
1350
1351	/* Almost no cleanup necessary, MM frees all memory. */
1352	PDMR3CritSectDelete(&pVM->pgm.s.CritSect);
1353
1354	return rc;
1355	}
1356
1357
1358	/**
1359	* Initializes the per-VCPU PGM.
1360	*
1361	* @returns VBox status code.
1362	* @param pVM The VM to operate on.
1363	*/
1364	VMMR3DECL(int) PGMR3InitCPU(PVM pVM)
1365	{
1366	LogFlow(("PGMR3InitCPU\n"));
1367	return VINF_SUCCESS;
1368	}
1369
1370
1371	/**
1372	* Init paging.
1373	*
1374	* Since we need to check what mode the host is operating in before we can choose
1375	* the right paging functions for the host we have to delay this until R0 has
1376	* been initialized.
1377	*
1378	* @returns VBox status code.
1379	* @param pVM VM handle.
1380	*/
1381	static int pgmR3InitPaging(PVM pVM)
1382	{
1383	/*
1384	* Force a recalculation of modes and switcher so everyone gets notified.
1385	*/
1386	pVM->pgm.s.enmShadowMode = PGMMODE_INVALID;
1387	pVM->pgm.s.enmGuestMode = PGMMODE_INVALID;
1388	pVM->pgm.s.enmHostMode = SUPPAGINGMODE_INVALID;
1389
1390	/*
1391	* Allocate static mapping space for whatever the cr3 register
1392	* points to and in the case of PAE mode to the 4 PDs.
1393	*/
1394	int rc = MMR3HyperReserve(pVM, PAGE_SIZE * 5, "CR3 mapping", &pVM->pgm.s.GCPtrCR3Mapping);
1395	if (RT_FAILURE(rc))
1396	{
1397	AssertMsgFailed(("Failed to reserve two pages for cr mapping in HMA, rc=%Rrc\n", rc));
1398	return rc;
1399	}
1400	MMR3HyperReserve(pVM, PAGE_SIZE, "fence", NULL);
1401
1402	/*
1403	* Allocate pages for the three possible intermediate contexts
1404	* (AMD64, PAE and plain 32-Bit). We maintain all three contexts
1405	* for the sake of simplicity. The AMD64 uses the PAE for the
1406	* lower levels, making the total number of pages 11 (3 + 7 + 1).
1407	*
1408	* We assume that two page tables will be enought for the core code
1409	* mappings (HC virtual and identity).
1410	*/
1411	pVM->pgm.s.pInterPD = (PX86PD)MMR3PageAllocLow(pVM);
1412	pVM->pgm.s.apInterPTs[0] = (PX86PT)MMR3PageAllocLow(pVM);
1413	pVM->pgm.s.apInterPTs[1] = (PX86PT)MMR3PageAllocLow(pVM);
1414	pVM->pgm.s.apInterPaePTs[0] = (PX86PTPAE)MMR3PageAlloc(pVM);
1415	pVM->pgm.s.apInterPaePTs[1] = (PX86PTPAE)MMR3PageAlloc(pVM);
1416	pVM->pgm.s.apInterPaePDs[0] = (PX86PDPAE)MMR3PageAlloc(pVM);
1417	pVM->pgm.s.apInterPaePDs[1] = (PX86PDPAE)MMR3PageAlloc(pVM);
1418	pVM->pgm.s.apInterPaePDs[2] = (PX86PDPAE)MMR3PageAlloc(pVM);
1419	pVM->pgm.s.apInterPaePDs[3] = (PX86PDPAE)MMR3PageAlloc(pVM);
1420	pVM->pgm.s.pInterPaePDPT = (PX86PDPT)MMR3PageAllocLow(pVM);
1421	pVM->pgm.s.pInterPaePDPT64 = (PX86PDPT)MMR3PageAllocLow(pVM);
1422	pVM->pgm.s.pInterPaePML4 = (PX86PML4)MMR3PageAllocLow(pVM);
1423	if ( !pVM->pgm.s.pInterPD
1424	\|\| !pVM->pgm.s.apInterPTs[0]
1425	\|\| !pVM->pgm.s.apInterPTs[1]
1426	\|\| !pVM->pgm.s.apInterPaePTs[0]
1427	\|\| !pVM->pgm.s.apInterPaePTs[1]
1428	\|\| !pVM->pgm.s.apInterPaePDs[0]
1429	\|\| !pVM->pgm.s.apInterPaePDs[1]
1430	\|\| !pVM->pgm.s.apInterPaePDs[2]
1431	\|\| !pVM->pgm.s.apInterPaePDs[3]
1432	\|\| !pVM->pgm.s.pInterPaePDPT
1433	\|\| !pVM->pgm.s.pInterPaePDPT64
1434	\|\| !pVM->pgm.s.pInterPaePML4)
1435	{
1436	AssertMsgFailed(("Failed to allocate pages for the intermediate context!\n"));
1437	return VERR_NO_PAGE_MEMORY;
1438	}
1439
1440	pVM->pgm.s.HCPhysInterPD = MMPage2Phys(pVM, pVM->pgm.s.pInterPD);
1441	AssertRelease(pVM->pgm.s.HCPhysInterPD != NIL_RTHCPHYS && !(pVM->pgm.s.HCPhysInterPD & PAGE_OFFSET_MASK));
1442	pVM->pgm.s.HCPhysInterPaePDPT = MMPage2Phys(pVM, pVM->pgm.s.pInterPaePDPT);
1443	AssertRelease(pVM->pgm.s.HCPhysInterPaePDPT != NIL_RTHCPHYS && !(pVM->pgm.s.HCPhysInterPaePDPT & PAGE_OFFSET_MASK));
1444	pVM->pgm.s.HCPhysInterPaePML4 = MMPage2Phys(pVM, pVM->pgm.s.pInterPaePML4);
1445	AssertRelease(pVM->pgm.s.HCPhysInterPaePML4 != NIL_RTHCPHYS && !(pVM->pgm.s.HCPhysInterPaePML4 & PAGE_OFFSET_MASK) && pVM->pgm.s.HCPhysInterPaePML4 < 0xffffffff);
1446
1447	/*
1448	* Initialize the pages, setting up the PML4 and PDPT for repetitive 4GB action.
1449	*/
1450	ASMMemZeroPage(pVM->pgm.s.pInterPD);
1451	ASMMemZeroPage(pVM->pgm.s.apInterPTs[0]);
1452	ASMMemZeroPage(pVM->pgm.s.apInterPTs[1]);
1453
1454	ASMMemZeroPage(pVM->pgm.s.apInterPaePTs[0]);
1455	ASMMemZeroPage(pVM->pgm.s.apInterPaePTs[1]);
1456
1457	ASMMemZeroPage(pVM->pgm.s.pInterPaePDPT);
1458	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.apInterPaePDs); i++)
1459	{
1460	ASMMemZeroPage(pVM->pgm.s.apInterPaePDs[i]);
1461	pVM->pgm.s.pInterPaePDPT->a[i].u = X86_PDPE_P \| PGM_PLXFLAGS_PERMANENT
1462	\| MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[i]);
1463	}
1464
1465	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.pInterPaePDPT64->a); i++)
1466	{
1467	const unsigned iPD = i % RT_ELEMENTS(pVM->pgm.s.apInterPaePDs);
1468	pVM->pgm.s.pInterPaePDPT64->a[i].u = X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_A \| PGM_PLXFLAGS_PERMANENT
1469	\| MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[iPD]);
1470	}
1471
1472	RTHCPHYS HCPhysInterPaePDPT64 = MMPage2Phys(pVM, pVM->pgm.s.pInterPaePDPT64);
1473	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.pInterPaePML4->a); i++)
1474	pVM->pgm.s.pInterPaePML4->a[i].u = X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_A \| PGM_PLXFLAGS_PERMANENT
1475	\| HCPhysInterPaePDPT64;
1476
1477	/*
1478	* Initialize paging workers and mode from current host mode
1479	* and the guest running in real mode.
1480	*/
1481	pVM->pgm.s.enmHostMode = SUPGetPagingMode();
1482	switch (pVM->pgm.s.enmHostMode)
1483	{
1484	case SUPPAGINGMODE_32_BIT:
1485	case SUPPAGINGMODE_32_BIT_GLOBAL:
1486	case SUPPAGINGMODE_PAE:
1487	case SUPPAGINGMODE_PAE_GLOBAL:
1488	case SUPPAGINGMODE_PAE_NX:
1489	case SUPPAGINGMODE_PAE_GLOBAL_NX:
1490	break;
1491
1492	case SUPPAGINGMODE_AMD64:
1493	case SUPPAGINGMODE_AMD64_GLOBAL:
1494	case SUPPAGINGMODE_AMD64_NX:
1495	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
1496	#ifndef VBOX_WITH_HYBRID_32BIT_KERNEL
1497	if (ARCH_BITS != 64)
1498	{
1499	AssertMsgFailed(("Host mode %d (64-bit) is not supported by non-64bit builds\n", pVM->pgm.s.enmHostMode));
1500	LogRel(("Host mode %d (64-bit) is not supported by non-64bit builds\n", pVM->pgm.s.enmHostMode));
1501	return VERR_PGM_UNSUPPORTED_HOST_PAGING_MODE;
1502	}
1503	#endif
1504	break;
1505	default:
1506	AssertMsgFailed(("Host mode %d is not supported\n", pVM->pgm.s.enmHostMode));
1507	return VERR_PGM_UNSUPPORTED_HOST_PAGING_MODE;
1508	}
1509	rc = pgmR3ModeDataInit(pVM, false /* don't resolve GC and R0 syms yet */);
1510	if (RT_SUCCESS(rc))
1511	{
1512	LogFlow(("pgmR3InitPaging: returns successfully\n"));
1513	#if HC_ARCH_BITS == 64
1514	LogRel(("Debug: HCPhysInterPD=%RHp HCPhysInterPaePDPT=%RHp HCPhysInterPaePML4=%RHp\n",
1515	pVM->pgm.s.HCPhysInterPD, pVM->pgm.s.HCPhysInterPaePDPT, pVM->pgm.s.HCPhysInterPaePML4));
1516	LogRel(("Debug: apInterPTs={%RHp,%RHp} apInterPaePTs={%RHp,%RHp} apInterPaePDs={%RHp,%RHp,%RHp,%RHp} pInterPaePDPT64=%RHp\n",
1517	MMPage2Phys(pVM, pVM->pgm.s.apInterPTs[0]), MMPage2Phys(pVM, pVM->pgm.s.apInterPTs[1]),
1518	MMPage2Phys(pVM, pVM->pgm.s.apInterPaePTs[0]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePTs[1]),
1519	MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[0]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[1]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[2]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[3]),
1520	MMPage2Phys(pVM, pVM->pgm.s.pInterPaePDPT64)));
1521	#endif
1522
1523	return VINF_SUCCESS;
1524	}
1525
1526	LogFlow(("pgmR3InitPaging: returns %Rrc\n", rc));
1527	return rc;
1528	}
1529
1530
1531	/**
1532	* Init statistics
1533	*/
1534	static void pgmR3InitStats(PVM pVM)
1535	{
1536	PPGM pPGM = &pVM->pgm.s;
1537	unsigned i;
1538
1539	/* Common - misc variables */
1540	STAM_REL_REG(pVM, &pPGM->cAllPages, STAMTYPE_U32, "/PGM/Page/cAllPages", STAMUNIT_OCCURENCES, "The total number of pages.");
1541	STAM_REL_REG(pVM, &pPGM->cPrivatePages, STAMTYPE_U32, "/PGM/Page/cPrivatePages", STAMUNIT_OCCURENCES, "The number of private pages.");
1542	STAM_REL_REG(pVM, &pPGM->cSharedPages, STAMTYPE_U32, "/PGM/Page/cSharedPages", STAMUNIT_OCCURENCES, "The number of shared pages.");
1543	STAM_REL_REG(pVM, &pPGM->cZeroPages, STAMTYPE_U32, "/PGM/Page/cZeroPages", STAMUNIT_OCCURENCES, "The number of zero backed pages.");
1544	STAM_REL_REG(pVM, &pPGM->cHandyPages, STAMTYPE_U32, "/PGM/Page/cHandyPages", STAMUNIT_OCCURENCES, "The number of handy pages (not included in cAllPages).");
1545	STAM_REL_REG(pVM, &pPGM->cGuestModeChanges, STAMTYPE_COUNTER, "/PGM/cGuestModeChanges", STAMUNIT_OCCURENCES, "Number of guest mode changes.");
1546	STAM_REL_REG(pVM, &pPGM->cRelocations, STAMTYPE_COUNTER, "/PGM/cRelocations", STAMUNIT_OCCURENCES, "Number of hypervisor relocations.");
1547	STAM_REL_REG(pVM, &pPGM->ChunkR3Map.c, STAMTYPE_U32, "/PGM/ChunkR3Map/c", STAMUNIT_OCCURENCES, "Number of mapped chunks.");
1548	STAM_REL_REG(pVM, &pPGM->ChunkR3Map.cMax, STAMTYPE_U32, "/PGM/ChunkR3Map/cMax", STAMUNIT_OCCURENCES, "Maximum number of mapped chunks.");
1549
1550	/*
1551	* Note! The layout below matches the member layout exactly!
1552	*/
1553
1554	#ifdef VBOX_WITH_STATISTICS
1555	/* Common - stats */
1556	# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
1557	STAM_REG(pVM, &pPGM->StatTrackVirgin, STAMTYPE_COUNTER, "/PGM/Track/Virgin", STAMUNIT_OCCURENCES, "The number of first time shadowings");
1558	STAM_REG(pVM, &pPGM->StatTrackAliased, STAMTYPE_COUNTER, "/PGM/Track/Aliased", STAMUNIT_OCCURENCES, "The number of times switching to cRef2, i.e. the page is being shadowed by two PTs.");
1559	STAM_REG(pVM, &pPGM->StatTrackAliasedMany, STAMTYPE_COUNTER, "/PGM/Track/AliasedMany", STAMUNIT_OCCURENCES, "The number of times we're tracking using cRef2.");
1560	STAM_REG(pVM, &pPGM->StatTrackAliasedLots, STAMTYPE_COUNTER, "/PGM/Track/AliasedLots", STAMUNIT_OCCURENCES, "The number of times we're hitting pages which has overflowed cRef2");
1561	STAM_REG(pVM, &pPGM->StatTrackOverflows, STAMTYPE_COUNTER, "/PGM/Track/Overflows", STAMUNIT_OCCURENCES, "The number of times the extent list grows to long.");
1562	STAM_REG(pVM, &pPGM->StatTrackDeref, STAMTYPE_PROFILE, "/PGM/Track/Deref", STAMUNIT_OCCURENCES, "Profiling of SyncPageWorkerTrackDeref (expensive).");
1563	# endif
1564	for (i = 0; i < RT_ELEMENTS(pPGM->StatSyncPtPD); i++)
1565	STAMR3RegisterF(pVM, &pPGM->StatSyncPtPD[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
1566	"The number of SyncPT per PD n.", "/PGM/PDSyncPT/%04X", i);
1567	for (i = 0; i < RT_ELEMENTS(pPGM->StatSyncPagePD); i++)
1568	STAMR3RegisterF(pVM, &pPGM->StatSyncPagePD[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
1569	"The number of SyncPage per PD n.", "/PGM/PDSyncPage/%04X", i);
1570
1571	/* R3 only: */
1572	STAM_REG(pVM, &pPGM->StatR3DetectedConflicts, STAMTYPE_COUNTER, "/PGM/R3/DetectedConflicts", STAMUNIT_OCCURENCES, "The number of times PGMR3CheckMappingConflicts() detected a conflict.");
1573	STAM_REG(pVM, &pPGM->StatR3ResolveConflict, STAMTYPE_PROFILE, "/PGM/R3/ResolveConflict", STAMUNIT_TICKS_PER_CALL, "pgmR3SyncPTResolveConflict() profiling (includes the entire relocation).");
1574	STAM_REG(pVM, &pPGM->StatR3GuestPDWrite, STAMTYPE_COUNTER, "/PGM/R3/PDWrite", STAMUNIT_OCCURENCES, "The total number of times pgmHCGuestPDWriteHandler() was called.");
1575	STAM_REG(pVM, &pPGM->StatR3GuestPDWriteConflict, STAMTYPE_COUNTER, "/PGM/R3/PDWriteConflict", STAMUNIT_OCCURENCES, "The number of times pgmHCGuestPDWriteHandler() detected a conflict.");
1576
1577	/* R0 only: */
1578	STAM_REG(pVM, &pPGM->StatR0DynMapMigrateInvlPg, STAMTYPE_COUNTER, "/PGM/R0/DynMapMigrateInvlPg", STAMUNIT_OCCURENCES, "invlpg count in PGMDynMapMigrateAutoSet.");
1579	STAM_REG(pVM, &pPGM->StatR0DynMapGCPageInl, STAMTYPE_PROFILE, "/PGM/R0/DynMapPageGCPageInl", STAMUNIT_TICKS_PER_CALL, "Calls to pgmR0DynMapGCPageInlined.");
1580	STAM_REG(pVM, &pPGM->StatR0DynMapGCPageInlHits, STAMTYPE_COUNTER, "/PGM/R0/DynMapPageGCPageInl/Hits", STAMUNIT_OCCURENCES, "Hash table lookup hits.");
1581	STAM_REG(pVM, &pPGM->StatR0DynMapGCPageInlMisses, STAMTYPE_COUNTER, "/PGM/R0/DynMapPageGCPageInl/Misses", STAMUNIT_OCCURENCES, "Misses that falls back to code common with PGMDynMapHCPage.");
1582	STAM_REG(pVM, &pPGM->StatR0DynMapGCPageInlRamHits, STAMTYPE_COUNTER, "/PGM/R0/DynMapPageGCPageInl/RamHits", STAMUNIT_OCCURENCES, "1st ram range hits.");
1583	STAM_REG(pVM, &pPGM->StatR0DynMapGCPageInlRamMisses, STAMTYPE_COUNTER, "/PGM/R0/DynMapPageGCPageInl/RamMisses", STAMUNIT_OCCURENCES, "1st ram range misses, takes slow path.");
1584	STAM_REG(pVM, &pPGM->StatR0DynMapHCPageInl, STAMTYPE_PROFILE, "/PGM/R0/DynMapPageHCPageInl", STAMUNIT_TICKS_PER_CALL, "Calls to pgmR0DynMapHCPageInlined.");
1585	STAM_REG(pVM, &pPGM->StatR0DynMapHCPageInlHits, STAMTYPE_COUNTER, "/PGM/R0/DynMapPageHCPageInl/Hits", STAMUNIT_OCCURENCES, "Hash table lookup hits.");
1586	STAM_REG(pVM, &pPGM->StatR0DynMapHCPageInlMisses, STAMTYPE_COUNTER, "/PGM/R0/DynMapPageHCPageInl/Misses", STAMUNIT_OCCURENCES, "Misses that falls back to code common with PGMDynMapHCPage.");
1587	STAM_REG(pVM, &pPGM->StatR0DynMapPage, STAMTYPE_COUNTER, "/PGM/R0/DynMapPage", STAMUNIT_OCCURENCES, "Calls to pgmR0DynMapPage");
1588	STAM_REG(pVM, &pPGM->StatR0DynMapSetOptimize, STAMTYPE_COUNTER, "/PGM/R0/DynMapPage/SetOptimize", STAMUNIT_OCCURENCES, "Calls to pgmDynMapOptimizeAutoSet.");
1589	STAM_REG(pVM, &pPGM->StatR0DynMapSetSearchFlushes, STAMTYPE_COUNTER, "/PGM/R0/DynMapPage/SetSearchFlushes",STAMUNIT_OCCURENCES, "Set search restorting to subset flushes.");
1590	STAM_REG(pVM, &pPGM->StatR0DynMapSetSearchHits, STAMTYPE_COUNTER, "/PGM/R0/DynMapPage/SetSearchHits", STAMUNIT_OCCURENCES, "Set search hits.");
1591	STAM_REG(pVM, &pPGM->StatR0DynMapSetSearchMisses, STAMTYPE_COUNTER, "/PGM/R0/DynMapPage/SetSearchMisses", STAMUNIT_OCCURENCES, "Set search misses.");
1592	STAM_REG(pVM, &pPGM->StatR0DynMapHCPage, STAMTYPE_PROFILE, "/PGM/R0/DynMapPage/HCPage", STAMUNIT_TICKS_PER_CALL, "Calls to PGMDynMapHCPage (ring-0).");
1593	STAM_REG(pVM, &pPGM->StatR0DynMapPageHits0, STAMTYPE_COUNTER, "/PGM/R0/DynMapPage/Hits0", STAMUNIT_OCCURENCES, "Hits at iPage+0");
1594	STAM_REG(pVM, &pPGM->StatR0DynMapPageHits1, STAMTYPE_COUNTER, "/PGM/R0/DynMapPage/Hits1", STAMUNIT_OCCURENCES, "Hits at iPage+1");
1595	STAM_REG(pVM, &pPGM->StatR0DynMapPageHits2, STAMTYPE_COUNTER, "/PGM/R0/DynMapPage/Hits2", STAMUNIT_OCCURENCES, "Hits at iPage+2");
1596	STAM_REG(pVM, &pPGM->StatR0DynMapPageInvlPg, STAMTYPE_COUNTER, "/PGM/R0/DynMapPage/InvlPg", STAMUNIT_OCCURENCES, "invlpg count in pgmR0DynMapPageSlow.");
1597	STAM_REG(pVM, &pPGM->StatR0DynMapPageSlow, STAMTYPE_COUNTER, "/PGM/R0/DynMapPage/Slow", STAMUNIT_OCCURENCES, "Calls to pgmR0DynMapPageSlow - subtract this from pgmR0DynMapPage to get 1st level hits.");
1598	STAM_REG(pVM, &pPGM->StatR0DynMapPageSlowLoopHits, STAMTYPE_COUNTER, "/PGM/R0/DynMapPage/SlowLoopHits" , STAMUNIT_OCCURENCES, "Hits in the loop path.");
1599	STAM_REG(pVM, &pPGM->StatR0DynMapPageSlowLoopMisses, STAMTYPE_COUNTER, "/PGM/R0/DynMapPage/SlowLoopMisses", STAMUNIT_OCCURENCES, "Misses in the loop path. NonLoopMisses = Slow - SlowLoopHit - SlowLoopMisses");
1600	//STAM_REG(pVM, &pPGM->StatR0DynMapPageSlowLostHits, STAMTYPE_COUNTER, "/PGM/R0/DynMapPage/SlowLostHits", STAMUNIT_OCCURENCES, "Lost hits.");
1601	STAM_REG(pVM, &pPGM->StatR0DynMapSubsets, STAMTYPE_COUNTER, "/PGM/R0/Subsets", STAMUNIT_OCCURENCES, "Times PGMDynMapPushAutoSubset was called.");
1602	STAM_REG(pVM, &pPGM->StatR0DynMapPopFlushes, STAMTYPE_COUNTER, "/PGM/R0/SubsetPopFlushes", STAMUNIT_OCCURENCES, "Times PGMDynMapPopAutoSubset flushes the subset.");
1603	STAM_REG(pVM, &pPGM->aStatR0DynMapSetSize[0], STAMTYPE_COUNTER, "/PGM/R0/SetSize000..09", STAMUNIT_OCCURENCES, "00-09% filled");
1604	STAM_REG(pVM, &pPGM->aStatR0DynMapSetSize[1], STAMTYPE_COUNTER, "/PGM/R0/SetSize010..19", STAMUNIT_OCCURENCES, "10-19% filled");
1605	STAM_REG(pVM, &pPGM->aStatR0DynMapSetSize[2], STAMTYPE_COUNTER, "/PGM/R0/SetSize020..29", STAMUNIT_OCCURENCES, "20-29% filled");
1606	STAM_REG(pVM, &pPGM->aStatR0DynMapSetSize[3], STAMTYPE_COUNTER, "/PGM/R0/SetSize030..39", STAMUNIT_OCCURENCES, "30-39% filled");
1607	STAM_REG(pVM, &pPGM->aStatR0DynMapSetSize[4], STAMTYPE_COUNTER, "/PGM/R0/SetSize040..49", STAMUNIT_OCCURENCES, "40-49% filled");
1608	STAM_REG(pVM, &pPGM->aStatR0DynMapSetSize[5], STAMTYPE_COUNTER, "/PGM/R0/SetSize050..59", STAMUNIT_OCCURENCES, "50-59% filled");
1609	STAM_REG(pVM, &pPGM->aStatR0DynMapSetSize[6], STAMTYPE_COUNTER, "/PGM/R0/SetSize060..69", STAMUNIT_OCCURENCES, "60-69% filled");
1610	STAM_REG(pVM, &pPGM->aStatR0DynMapSetSize[7], STAMTYPE_COUNTER, "/PGM/R0/SetSize070..79", STAMUNIT_OCCURENCES, "70-79% filled");
1611	STAM_REG(pVM, &pPGM->aStatR0DynMapSetSize[8], STAMTYPE_COUNTER, "/PGM/R0/SetSize080..89", STAMUNIT_OCCURENCES, "80-89% filled");
1612	STAM_REG(pVM, &pPGM->aStatR0DynMapSetSize[9], STAMTYPE_COUNTER, "/PGM/R0/SetSize090..99", STAMUNIT_OCCURENCES, "90-99% filled");
1613	STAM_REG(pVM, &pPGM->aStatR0DynMapSetSize[10], STAMTYPE_COUNTER, "/PGM/R0/SetSize100", STAMUNIT_OCCURENCES, "100% filled");
1614
1615	/* GC only: */
1616	STAM_REG(pVM, &pPGM->StatRCDynMapCacheHits, STAMTYPE_COUNTER, "/PGM/RC/DynMapCache/Hits" , STAMUNIT_OCCURENCES, "Number of dynamic page mapping cache hits.");
1617	STAM_REG(pVM, &pPGM->StatRCDynMapCacheMisses, STAMTYPE_COUNTER, "/PGM/RC/DynMapCache/Misses" , STAMUNIT_OCCURENCES, "Number of dynamic page mapping cache misses.");
1618	STAM_REG(pVM, &pPGM->StatRCInvlPgConflict, STAMTYPE_COUNTER, "/PGM/RC/InvlPgConflict", STAMUNIT_OCCURENCES, "Number of times PGMInvalidatePage() detected a mapping conflict.");
1619	STAM_REG(pVM, &pPGM->StatRCInvlPgSyncMonCR3, STAMTYPE_COUNTER, "/PGM/RC/InvlPgSyncMonitorCR3", STAMUNIT_OCCURENCES, "Number of times PGMInvalidatePage() ran into PGM_SYNC_MONITOR_CR3.");
1620
1621	/* RZ only: */
1622	STAM_REG(pVM, &pPGM->StatRZTrap0e, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMTrap0eHandler() body.");
1623	STAM_REG(pVM, &pPGM->StatRZTrap0eTimeCheckPageFault, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time/CheckPageFault", STAMUNIT_TICKS_PER_CALL, "Profiling of checking for dirty/access emulation faults.");
1624	STAM_REG(pVM, &pPGM->StatRZTrap0eTimeSyncPT, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time/SyncPT", STAMUNIT_TICKS_PER_CALL, "Profiling of lazy page table syncing.");
1625	STAM_REG(pVM, &pPGM->StatRZTrap0eTimeMapping, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time/Mapping", STAMUNIT_TICKS_PER_CALL, "Profiling of checking virtual mappings.");
1626	STAM_REG(pVM, &pPGM->StatRZTrap0eTimeOutOfSync, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time/OutOfSync", STAMUNIT_TICKS_PER_CALL, "Profiling of out of sync page handling.");
1627	STAM_REG(pVM, &pPGM->StatRZTrap0eTimeHandlers, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time/Handlers", STAMUNIT_TICKS_PER_CALL, "Profiling of checking handlers.");
1628	STAM_REG(pVM, &pPGM->StatRZTrap0eTime2CSAM, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time2/CSAM", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is CSAM.");
1629	STAM_REG(pVM, &pPGM->StatRZTrap0eTime2DirtyAndAccessed, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time2/DirtyAndAccessedBits", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is dirty and/or accessed bit emulation.");
1630	STAM_REG(pVM, &pPGM->StatRZTrap0eTime2GuestTrap, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time2/GuestTrap", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is a guest trap.");
1631	STAM_REG(pVM, &pPGM->StatRZTrap0eTime2HndPhys, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time2/HandlerPhysical", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is a physical handler.");
1632	STAM_REG(pVM, &pPGM->StatRZTrap0eTime2HndVirt, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time2/HandlerVirtual", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is a virtual handler.");
1633	STAM_REG(pVM, &pPGM->StatRZTrap0eTime2HndUnhandled, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time2/HandlerUnhandled", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is access outside the monitored areas of a monitored page.");
1634	STAM_REG(pVM, &pPGM->StatRZTrap0eTime2Misc, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time2/Misc", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is not known.");
1635	STAM_REG(pVM, &pPGM->StatRZTrap0eTime2OutOfSync, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time2/OutOfSync", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is an out-of-sync page.");
1636	STAM_REG(pVM, &pPGM->StatRZTrap0eTime2OutOfSyncHndPhys, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time2/OutOfSyncHndPhys", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is an out-of-sync physical handler page.");
1637	STAM_REG(pVM, &pPGM->StatRZTrap0eTime2OutOfSyncHndVirt, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time2/OutOfSyncHndVirt", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is an out-of-sync virtual handler page.");
1638	STAM_REG(pVM, &pPGM->StatRZTrap0eTime2OutOfSyncHndObs, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time2/OutOfSyncObsHnd", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is an obsolete handler page.");
1639	STAM_REG(pVM, &pPGM->StatRZTrap0eTime2SyncPT, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time2/SyncPT", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is lazy syncing of a PT.");
1640	STAM_REG(pVM, &pPGM->StatRZTrap0eConflicts, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Conflicts", STAMUNIT_OCCURENCES, "The number of times #PF was caused by an undetected conflict.");
1641	STAM_REG(pVM, &pPGM->StatRZTrap0eHandlersMapping, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Handlers/Mapping", STAMUNIT_OCCURENCES, "Number of traps due to access handlers in mappings.");
1642	STAM_REG(pVM, &pPGM->StatRZTrap0eHandlersOutOfSync, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Handlers/OutOfSync", STAMUNIT_OCCURENCES, "Number of traps due to out-of-sync handled pages.");
1643	STAM_REG(pVM, &pPGM->StatRZTrap0eHandlersPhysical, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Handlers/Physical", STAMUNIT_OCCURENCES, "Number of traps due to physical access handlers.");
1644	STAM_REG(pVM, &pPGM->StatRZTrap0eHandlersVirtual, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Handlers/Virtual", STAMUNIT_OCCURENCES, "Number of traps due to virtual access handlers.");
1645	STAM_REG(pVM, &pPGM->StatRZTrap0eHandlersVirtualByPhys, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Handlers/VirtualByPhys", STAMUNIT_OCCURENCES, "Number of traps due to virtual access handlers by physical address.");
1646	STAM_REG(pVM, &pPGM->StatRZTrap0eHandlersVirtualUnmarked,STAMTYPE_COUNTER,"/PGM/RZ/Trap0e/Handlers/VirtualUnmarked",STAMUNIT_OCCURENCES, "Number of traps due to virtual access handlers by virtual address (without proper physical flags).");
1647	STAM_REG(pVM, &pPGM->StatRZTrap0eHandlersUnhandled, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Handlers/Unhandled", STAMUNIT_OCCURENCES, "Number of traps due to access outside range of monitored page(s).");
1648	STAM_REG(pVM, &pPGM->StatRZTrap0eHandlersInvalid, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Handlers/Invalid", STAMUNIT_OCCURENCES, "Number of traps due to access to invalid physical memory.");
1649	STAM_REG(pVM, &pPGM->StatRZTrap0eUSNotPresentRead, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Err/User/NPRead", STAMUNIT_OCCURENCES, "Number of user mode not present read page faults.");
1650	STAM_REG(pVM, &pPGM->StatRZTrap0eUSNotPresentWrite, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Err/User/NPWrite", STAMUNIT_OCCURENCES, "Number of user mode not present write page faults.");
1651	STAM_REG(pVM, &pPGM->StatRZTrap0eUSWrite, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Err/User/Write", STAMUNIT_OCCURENCES, "Number of user mode write page faults.");
1652	STAM_REG(pVM, &pPGM->StatRZTrap0eUSReserved, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Err/User/Reserved", STAMUNIT_OCCURENCES, "Number of user mode reserved bit page faults.");
1653	STAM_REG(pVM, &pPGM->StatRZTrap0eUSNXE, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Err/User/NXE", STAMUNIT_OCCURENCES, "Number of user mode NXE page faults.");
1654	STAM_REG(pVM, &pPGM->StatRZTrap0eUSRead, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Err/User/Read", STAMUNIT_OCCURENCES, "Number of user mode read page faults.");
1655	STAM_REG(pVM, &pPGM->StatRZTrap0eSVNotPresentRead, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Err/Supervisor/NPRead", STAMUNIT_OCCURENCES, "Number of supervisor mode not present read page faults.");
1656	STAM_REG(pVM, &pPGM->StatRZTrap0eSVNotPresentWrite, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Err/Supervisor/NPWrite", STAMUNIT_OCCURENCES, "Number of supervisor mode not present write page faults.");
1657	STAM_REG(pVM, &pPGM->StatRZTrap0eSVWrite, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Err/Supervisor/Write", STAMUNIT_OCCURENCES, "Number of supervisor mode write page faults.");
1658	STAM_REG(pVM, &pPGM->StatRZTrap0eSVReserved, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Err/Supervisor/Reserved", STAMUNIT_OCCURENCES, "Number of supervisor mode reserved bit page faults.");
1659	STAM_REG(pVM, &pPGM->StatRZTrap0eSNXE, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Err/Supervisor/NXE", STAMUNIT_OCCURENCES, "Number of supervisor mode NXE page faults.");
1660	STAM_REG(pVM, &pPGM->StatRZTrap0eGuestPF, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/GuestPF", STAMUNIT_OCCURENCES, "Number of real guest page faults.");
1661	STAM_REG(pVM, &pPGM->StatRZTrap0eGuestPFUnh, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/GuestPF/Unhandled", STAMUNIT_OCCURENCES, "Number of real guest page faults from the 'unhandled' case.");
1662	STAM_REG(pVM, &pPGM->StatRZTrap0eGuestPFMapping, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/GuestPF/InMapping", STAMUNIT_OCCURENCES, "Number of real guest page faults in a mapping.");
1663	STAM_REG(pVM, &pPGM->StatRZTrap0eWPEmulInRZ, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/WP/InRZ", STAMUNIT_OCCURENCES, "Number of guest page faults due to X86_CR0_WP emulation.");
1664	STAM_REG(pVM, &pPGM->StatRZTrap0eWPEmulToR3, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/WP/ToR3", STAMUNIT_OCCURENCES, "Number of guest page faults due to X86_CR0_WP emulation (forward to R3 for emulation).");
1665	for (i = 0; i < RT_ELEMENTS(pPGM->StatRZTrap0ePD); i++)
1666	STAMR3RegisterF(pVM, &pPGM->StatRZTrap0ePD[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
1667	"The number of traps in page directory n.", "/PGM/RZ/Trap0e/PD/%04X", i);
1668	STAM_REG(pVM, &pPGM->StatRZGuestCR3WriteHandled, STAMTYPE_COUNTER, "/PGM/RZ/CR3WriteHandled", STAMUNIT_OCCURENCES, "The number of times the Guest CR3 change was successfully handled.");
1669	STAM_REG(pVM, &pPGM->StatRZGuestCR3WriteUnhandled, STAMTYPE_COUNTER, "/PGM/RZ/CR3WriteUnhandled", STAMUNIT_OCCURENCES, "The number of times the Guest CR3 change was passed back to the recompiler.");
1670	STAM_REG(pVM, &pPGM->StatRZGuestCR3WriteConflict, STAMTYPE_COUNTER, "/PGM/RZ/CR3WriteConflict", STAMUNIT_OCCURENCES, "The number of times the Guest CR3 monitoring detected a conflict.");
1671	STAM_REG(pVM, &pPGM->StatRZGuestROMWriteHandled, STAMTYPE_COUNTER, "/PGM/RZ/ROMWriteHandled", STAMUNIT_OCCURENCES, "The number of times the Guest ROM change was successfully handled.");
1672	STAM_REG(pVM, &pPGM->StatRZGuestROMWriteUnhandled, STAMTYPE_COUNTER, "/PGM/RZ/ROMWriteUnhandled", STAMUNIT_OCCURENCES, "The number of times the Guest ROM change was passed back to the recompiler.");
1673
1674	/* HC only: */
1675
1676	/* RZ & R3: */
1677	STAM_REG(pVM, &pPGM->StatRZSyncCR3, STAMTYPE_PROFILE, "/PGM/RZ/SyncCR3", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMSyncCR3() body.");
1678	STAM_REG(pVM, &pPGM->StatRZSyncCR3Handlers, STAMTYPE_PROFILE, "/PGM/RZ/SyncCR3/Handlers", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMSyncCR3() update handler section.");
1679	STAM_REG(pVM, &pPGM->StatRZSyncCR3HandlerVirtualUpdate, STAMTYPE_PROFILE, "/PGM/RZ/SyncCR3/Handlers/VirtualUpdate", STAMUNIT_TICKS_PER_CALL, "Profiling of the virtual handler updates.");
1680	STAM_REG(pVM, &pPGM->StatRZSyncCR3HandlerVirtualReset, STAMTYPE_PROFILE, "/PGM/RZ/SyncCR3/Handlers/VirtualReset", STAMUNIT_TICKS_PER_CALL, "Profiling of the virtual handler resets.");
1681	STAM_REG(pVM, &pPGM->StatRZSyncCR3Global, STAMTYPE_COUNTER, "/PGM/RZ/SyncCR3/Global", STAMUNIT_OCCURENCES, "The number of global CR3 syncs.");
1682	STAM_REG(pVM, &pPGM->StatRZSyncCR3NotGlobal, STAMTYPE_COUNTER, "/PGM/RZ/SyncCR3/NotGlobal", STAMUNIT_OCCURENCES, "The number of non-global CR3 syncs.");
1683	STAM_REG(pVM, &pPGM->StatRZSyncCR3DstCacheHit, STAMTYPE_COUNTER, "/PGM/RZ/SyncCR3/DstChacheHit", STAMUNIT_OCCURENCES, "The number of times we got some kind of a cache hit.");
1684	STAM_REG(pVM, &pPGM->StatRZSyncCR3DstFreed, STAMTYPE_COUNTER, "/PGM/RZ/SyncCR3/DstFreed", STAMUNIT_OCCURENCES, "The number of times we've had to free a shadow entry.");
1685	STAM_REG(pVM, &pPGM->StatRZSyncCR3DstFreedSrcNP, STAMTYPE_COUNTER, "/PGM/RZ/SyncCR3/DstFreedSrcNP", STAMUNIT_OCCURENCES, "The number of times we've had to free a shadow entry for which the source entry was not present.");
1686	STAM_REG(pVM, &pPGM->StatRZSyncCR3DstNotPresent, STAMTYPE_COUNTER, "/PGM/RZ/SyncCR3/DstNotPresent", STAMUNIT_OCCURENCES, "The number of times we've encountered a not present shadow entry for a present guest entry.");
1687	STAM_REG(pVM, &pPGM->StatRZSyncCR3DstSkippedGlobalPD, STAMTYPE_COUNTER, "/PGM/RZ/SyncCR3/DstSkippedGlobalPD", STAMUNIT_OCCURENCES, "The number of times a global page directory wasn't flushed.");
1688	STAM_REG(pVM, &pPGM->StatRZSyncCR3DstSkippedGlobalPT, STAMTYPE_COUNTER, "/PGM/RZ/SyncCR3/DstSkippedGlobalPT", STAMUNIT_OCCURENCES, "The number of times a page table with only global entries wasn't flushed.");
1689	STAM_REG(pVM, &pPGM->StatRZSyncPT, STAMTYPE_PROFILE, "/PGM/RZ/SyncPT", STAMUNIT_TICKS_PER_CALL, "Profiling of the pfnSyncPT() body.");
1690	STAM_REG(pVM, &pPGM->StatRZSyncPTFailed, STAMTYPE_COUNTER, "/PGM/RZ/SyncPT/Failed", STAMUNIT_OCCURENCES, "The number of times pfnSyncPT() failed.");
1691	STAM_REG(pVM, &pPGM->StatRZSyncPT4K, STAMTYPE_COUNTER, "/PGM/RZ/SyncPT/4K", STAMUNIT_OCCURENCES, "Nr of 4K PT syncs");
1692	STAM_REG(pVM, &pPGM->StatRZSyncPT4M, STAMTYPE_COUNTER, "/PGM/RZ/SyncPT/4M", STAMUNIT_OCCURENCES, "Nr of 4M PT syncs");
1693	STAM_REG(pVM, &pPGM->StatRZSyncPagePDNAs, STAMTYPE_COUNTER, "/PGM/RZ/SyncPagePDNAs", STAMUNIT_OCCURENCES, "The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit.");
1694	STAM_REG(pVM, &pPGM->StatRZSyncPagePDOutOfSync, STAMTYPE_COUNTER, "/PGM/RZ/SyncPagePDOutOfSync", STAMUNIT_OCCURENCES, "The number of time we've encountered an out-of-sync PD in SyncPage.");
1695	STAM_REG(pVM, &pPGM->StatRZAccessedPage, STAMTYPE_COUNTER, "/PGM/RZ/AccessedPage", STAMUNIT_OCCURENCES, "The number of pages marked not present for accessed bit emulation.");
1696	STAM_REG(pVM, &pPGM->StatRZDirtyBitTracking, STAMTYPE_PROFILE, "/PGM/RZ/DirtyPage", STAMUNIT_TICKS_PER_CALL, "Profiling the dirty bit tracking in CheckPageFault().");
1697	STAM_REG(pVM, &pPGM->StatRZDirtyPage, STAMTYPE_COUNTER, "/PGM/RZ/DirtyPage/Mark", STAMUNIT_OCCURENCES, "The number of pages marked read-only for dirty bit tracking.");
1698	STAM_REG(pVM, &pPGM->StatRZDirtyPageBig, STAMTYPE_COUNTER, "/PGM/RZ/DirtyPage/MarkBig", STAMUNIT_OCCURENCES, "The number of 4MB pages marked read-only for dirty bit tracking.");
1699	STAM_REG(pVM, &pPGM->StatRZDirtyPageSkipped, STAMTYPE_COUNTER, "/PGM/RZ/DirtyPage/Skipped", STAMUNIT_OCCURENCES, "The number of pages already dirty or readonly.");
1700	STAM_REG(pVM, &pPGM->StatRZDirtyPageTrap, STAMTYPE_COUNTER, "/PGM/RZ/DirtyPage/Trap", STAMUNIT_OCCURENCES, "The number of traps generated for dirty bit tracking.");
1701	STAM_REG(pVM, &pPGM->StatRZDirtiedPage, STAMTYPE_COUNTER, "/PGM/RZ/DirtyPage/SetDirty", STAMUNIT_OCCURENCES, "The number of pages marked dirty because of write accesses.");
1702	STAM_REG(pVM, &pPGM->StatRZDirtyTrackRealPF, STAMTYPE_COUNTER, "/PGM/RZ/DirtyPage/RealPF", STAMUNIT_OCCURENCES, "The number of real pages faults during dirty bit tracking.");
1703	STAM_REG(pVM, &pPGM->StatRZPageAlreadyDirty, STAMTYPE_COUNTER, "/PGM/RZ/DirtyPage/AlreadySet", STAMUNIT_OCCURENCES, "The number of pages already marked dirty because of write accesses.");
1704	STAM_REG(pVM, &pPGM->StatRZInvalidatePage, STAMTYPE_PROFILE, "/PGM/RZ/InvalidatePage", STAMUNIT_TICKS_PER_CALL, "PGMInvalidatePage() profiling.");
1705	STAM_REG(pVM, &pPGM->StatRZInvalidatePage4KBPages, STAMTYPE_COUNTER, "/PGM/RZ/InvalidatePage/4KBPages", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was called for a 4KB page.");
1706	STAM_REG(pVM, &pPGM->StatRZInvalidatePage4MBPages, STAMTYPE_COUNTER, "/PGM/RZ/InvalidatePage/4MBPages", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was called for a 4MB page.");
1707	STAM_REG(pVM, &pPGM->StatRZInvalidatePage4MBPagesSkip, STAMTYPE_COUNTER, "/PGM/RZ/InvalidatePage/4MBPagesSkip",STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() skipped a 4MB page.");
1708	STAM_REG(pVM, &pPGM->StatRZInvalidatePagePDMappings, STAMTYPE_COUNTER, "/PGM/RZ/InvalidatePage/PDMappings", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict).");
1709	STAM_REG(pVM, &pPGM->StatRZInvalidatePagePDNAs, STAMTYPE_COUNTER, "/PGM/RZ/InvalidatePage/PDNAs", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was called for a not accessed page directory.");
1710	STAM_REG(pVM, &pPGM->StatRZInvalidatePagePDNPs, STAMTYPE_COUNTER, "/PGM/RZ/InvalidatePage/PDNPs", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was called for a not present page directory.");
1711	STAM_REG(pVM, &pPGM->StatRZInvalidatePagePDOutOfSync, STAMTYPE_COUNTER, "/PGM/RZ/InvalidatePage/PDOutOfSync", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was called for an out of sync page directory.");
1712	STAM_REG(pVM, &pPGM->StatRZInvalidatePageSkipped, STAMTYPE_COUNTER, "/PGM/RZ/InvalidatePage/Skipped", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3.");
1713	STAM_REG(pVM, &pPGM->StatRZVirtHandlerSearchByPhys, STAMTYPE_PROFILE, "/PGM/RZ/VirtHandlerSearchByPhys", STAMUNIT_TICKS_PER_CALL, "Profiling of pgmHandlerVirtualFindByPhysAddr.");
1714	STAM_REG(pVM, &pPGM->StatRZPhysHandlerReset, STAMTYPE_COUNTER, "/PGM/RZ/PhysHandlerReset", STAMUNIT_OCCURENCES, "The number of times PGMHandlerPhysicalReset is called.");
1715	STAM_REG(pVM, &pPGM->StatRZPageOutOfSyncSupervisor, STAMTYPE_COUNTER, "/PGM/RZ/OutOfSync/SuperVisor", STAMUNIT_OCCURENCES, "Number of traps due to pages out of sync and times VerifyAccessSyncPage calls SyncPage.");
1716	STAM_REG(pVM, &pPGM->StatRZPageOutOfSyncUser, STAMTYPE_COUNTER, "/PGM/RZ/OutOfSync/User", STAMUNIT_OCCURENCES, "Number of traps due to pages out of sync and times VerifyAccessSyncPage calls SyncPage.");
1717	STAM_REG(pVM, &pPGM->StatRZPrefetch, STAMTYPE_PROFILE, "/PGM/RZ/Prefetch", STAMUNIT_TICKS_PER_CALL, "PGMPrefetchPage profiling.");
1718	STAM_REG(pVM, &pPGM->StatRZChunkR3MapTlbHits, STAMTYPE_COUNTER, "/PGM/ChunkR3Map/TlbHitsRZ", STAMUNIT_OCCURENCES, "TLB hits.");
1719	STAM_REG(pVM, &pPGM->StatRZChunkR3MapTlbMisses, STAMTYPE_COUNTER, "/PGM/ChunkR3Map/TlbMissesRZ", STAMUNIT_OCCURENCES, "TLB misses.");
1720	STAM_REG(pVM, &pPGM->StatRZPageMapTlbHits, STAMTYPE_COUNTER, "/PGM/RZ/Page/MapTlbHits", STAMUNIT_OCCURENCES, "TLB hits.");
1721	STAM_REG(pVM, &pPGM->StatRZPageMapTlbMisses, STAMTYPE_COUNTER, "/PGM/RZ/Page/MapTlbMisses", STAMUNIT_OCCURENCES, "TLB misses.");
1722	STAM_REG(pVM, &pPGM->StatRZPageReplaceShared, STAMTYPE_COUNTER, "/PGM/RZ/Page/ReplacedShared", STAMUNIT_OCCURENCES, "Times a shared page was replaced.");
1723	STAM_REG(pVM, &pPGM->StatRZPageReplaceZero, STAMTYPE_COUNTER, "/PGM/RZ/Page/ReplacedZero", STAMUNIT_OCCURENCES, "Times the zero page was replaced.");
1724	/// @todo STAM_REG(pVM, &pPGM->StatRZPageHandyAllocs, STAMTYPE_COUNTER, "/PGM/RZ/Page/HandyAllocs", STAMUNIT_OCCURENCES, "Number of times we've allocated more handy pages.");
1725	STAM_REG(pVM, &pPGM->StatRZFlushTLB, STAMTYPE_PROFILE, "/PGM/RZ/FlushTLB", STAMUNIT_OCCURENCES, "Profiling of the PGMFlushTLB() body.");
1726	STAM_REG(pVM, &pPGM->StatRZFlushTLBNewCR3, STAMTYPE_COUNTER, "/PGM/RZ/FlushTLB/NewCR3", STAMUNIT_OCCURENCES, "The number of times PGMFlushTLB was called with a new CR3, non-global. (switch)");
1727	STAM_REG(pVM, &pPGM->StatRZFlushTLBNewCR3Global, STAMTYPE_COUNTER, "/PGM/RZ/FlushTLB/NewCR3Global", STAMUNIT_OCCURENCES, "The number of times PGMFlushTLB was called with a new CR3, global. (switch)");
1728	STAM_REG(pVM, &pPGM->StatRZFlushTLBSameCR3, STAMTYPE_COUNTER, "/PGM/RZ/FlushTLB/SameCR3", STAMUNIT_OCCURENCES, "The number of times PGMFlushTLB was called with the same CR3, non-global. (flush)");
1729	STAM_REG(pVM, &pPGM->StatRZFlushTLBSameCR3Global, STAMTYPE_COUNTER, "/PGM/RZ/FlushTLB/SameCR3Global", STAMUNIT_OCCURENCES, "The number of times PGMFlushTLB was called with the same CR3, global. (flush)");
1730	STAM_REG(pVM, &pPGM->StatRZGstModifyPage, STAMTYPE_PROFILE, "/PGM/RZ/GstModifyPage", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMGstModifyPage() body.");
1731
1732	STAM_REG(pVM, &pPGM->StatR3SyncCR3, STAMTYPE_PROFILE, "/PGM/R3/SyncCR3", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMSyncCR3() body.");
1733	STAM_REG(pVM, &pPGM->StatR3SyncCR3Handlers, STAMTYPE_PROFILE, "/PGM/R3/SyncCR3/Handlers", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMSyncCR3() update handler section.");
1734	STAM_REG(pVM, &pPGM->StatR3SyncCR3HandlerVirtualUpdate, STAMTYPE_PROFILE, "/PGM/R3/SyncCR3/Handlers/VirtualUpdate", STAMUNIT_TICKS_PER_CALL, "Profiling of the virtual handler updates.");
1735	STAM_REG(pVM, &pPGM->StatR3SyncCR3HandlerVirtualReset, STAMTYPE_PROFILE, "/PGM/R3/SyncCR3/Handlers/VirtualReset", STAMUNIT_TICKS_PER_CALL, "Profiling of the virtual handler resets.");
1736	STAM_REG(pVM, &pPGM->StatR3SyncCR3Global, STAMTYPE_COUNTER, "/PGM/R3/SyncCR3/Global", STAMUNIT_OCCURENCES, "The number of global CR3 syncs.");
1737	STAM_REG(pVM, &pPGM->StatR3SyncCR3NotGlobal, STAMTYPE_COUNTER, "/PGM/R3/SyncCR3/NotGlobal", STAMUNIT_OCCURENCES, "The number of non-global CR3 syncs.");
1738	STAM_REG(pVM, &pPGM->StatR3SyncCR3DstCacheHit, STAMTYPE_COUNTER, "/PGM/R3/SyncCR3/DstChacheHit", STAMUNIT_OCCURENCES, "The number of times we got some kind of a cache hit.");
1739	STAM_REG(pVM, &pPGM->StatR3SyncCR3DstFreed, STAMTYPE_COUNTER, "/PGM/R3/SyncCR3/DstFreed", STAMUNIT_OCCURENCES, "The number of times we've had to free a shadow entry.");
1740	STAM_REG(pVM, &pPGM->StatR3SyncCR3DstFreedSrcNP, STAMTYPE_COUNTER, "/PGM/R3/SyncCR3/DstFreedSrcNP", STAMUNIT_OCCURENCES, "The number of times we've had to free a shadow entry for which the source entry was not present.");
1741	STAM_REG(pVM, &pPGM->StatR3SyncCR3DstNotPresent, STAMTYPE_COUNTER, "/PGM/R3/SyncCR3/DstNotPresent", STAMUNIT_OCCURENCES, "The number of times we've encountered a not present shadow entry for a present guest entry.");
1742	STAM_REG(pVM, &pPGM->StatR3SyncCR3DstSkippedGlobalPD, STAMTYPE_COUNTER, "/PGM/R3/SyncCR3/DstSkippedGlobalPD", STAMUNIT_OCCURENCES, "The number of times a global page directory wasn't flushed.");
1743	STAM_REG(pVM, &pPGM->StatR3SyncCR3DstSkippedGlobalPT, STAMTYPE_COUNTER, "/PGM/R3/SyncCR3/DstSkippedGlobalPT", STAMUNIT_OCCURENCES, "The number of times a page table with only global entries wasn't flushed.");
1744	STAM_REG(pVM, &pPGM->StatR3SyncPT, STAMTYPE_PROFILE, "/PGM/R3/SyncPT", STAMUNIT_TICKS_PER_CALL, "Profiling of the pfnSyncPT() body.");
1745	STAM_REG(pVM, &pPGM->StatR3SyncPTFailed, STAMTYPE_COUNTER, "/PGM/R3/SyncPT/Failed", STAMUNIT_OCCURENCES, "The number of times pfnSyncPT() failed.");
1746	STAM_REG(pVM, &pPGM->StatR3SyncPT4K, STAMTYPE_COUNTER, "/PGM/R3/SyncPT/4K", STAMUNIT_OCCURENCES, "Nr of 4K PT syncs");
1747	STAM_REG(pVM, &pPGM->StatR3SyncPT4M, STAMTYPE_COUNTER, "/PGM/R3/SyncPT/4M", STAMUNIT_OCCURENCES, "Nr of 4M PT syncs");
1748	STAM_REG(pVM, &pPGM->StatR3SyncPagePDNAs, STAMTYPE_COUNTER, "/PGM/R3/SyncPagePDNAs", STAMUNIT_OCCURENCES, "The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit.");
1749	STAM_REG(pVM, &pPGM->StatR3SyncPagePDOutOfSync, STAMTYPE_COUNTER, "/PGM/R3/SyncPagePDOutOfSync", STAMUNIT_OCCURENCES, "The number of time we've encountered an out-of-sync PD in SyncPage.");
1750	STAM_REG(pVM, &pPGM->StatR3AccessedPage, STAMTYPE_COUNTER, "/PGM/R3/AccessedPage", STAMUNIT_OCCURENCES, "The number of pages marked not present for accessed bit emulation.");
1751	STAM_REG(pVM, &pPGM->StatR3DirtyBitTracking, STAMTYPE_PROFILE, "/PGM/R3/DirtyPage", STAMUNIT_TICKS_PER_CALL, "Profiling the dirty bit tracking in CheckPageFault().");
1752	STAM_REG(pVM, &pPGM->StatR3DirtyPage, STAMTYPE_COUNTER, "/PGM/R3/DirtyPage/Mark", STAMUNIT_OCCURENCES, "The number of pages marked read-only for dirty bit tracking.");
1753	STAM_REG(pVM, &pPGM->StatR3DirtyPageBig, STAMTYPE_COUNTER, "/PGM/R3/DirtyPage/MarkBig", STAMUNIT_OCCURENCES, "The number of 4MB pages marked read-only for dirty bit tracking.");
1754	STAM_REG(pVM, &pPGM->StatR3DirtyPageSkipped, STAMTYPE_COUNTER, "/PGM/R3/DirtyPage/Skipped", STAMUNIT_OCCURENCES, "The number of pages already dirty or readonly.");
1755	STAM_REG(pVM, &pPGM->StatR3DirtyPageTrap, STAMTYPE_COUNTER, "/PGM/R3/DirtyPage/Trap", STAMUNIT_OCCURENCES, "The number of traps generated for dirty bit tracking.");
1756	STAM_REG(pVM, &pPGM->StatR3DirtiedPage, STAMTYPE_COUNTER, "/PGM/R3/DirtyPage/SetDirty", STAMUNIT_OCCURENCES, "The number of pages marked dirty because of write accesses.");
1757	STAM_REG(pVM, &pPGM->StatR3DirtyTrackRealPF, STAMTYPE_COUNTER, "/PGM/R3/DirtyPage/RealPF", STAMUNIT_OCCURENCES, "The number of real pages faults during dirty bit tracking.");
1758	STAM_REG(pVM, &pPGM->StatR3PageAlreadyDirty, STAMTYPE_COUNTER, "/PGM/R3/DirtyPage/AlreadySet", STAMUNIT_OCCURENCES, "The number of pages already marked dirty because of write accesses.");
1759	STAM_REG(pVM, &pPGM->StatR3InvalidatePage, STAMTYPE_PROFILE, "/PGM/R3/InvalidatePage", STAMUNIT_TICKS_PER_CALL, "PGMInvalidatePage() profiling.");
1760	STAM_REG(pVM, &pPGM->StatR3InvalidatePage4KBPages, STAMTYPE_COUNTER, "/PGM/R3/InvalidatePage/4KBPages", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was called for a 4KB page.");
1761	STAM_REG(pVM, &pPGM->StatR3InvalidatePage4MBPages, STAMTYPE_COUNTER, "/PGM/R3/InvalidatePage/4MBPages", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was called for a 4MB page.");
1762	STAM_REG(pVM, &pPGM->StatR3InvalidatePage4MBPagesSkip, STAMTYPE_COUNTER, "/PGM/R3/InvalidatePage/4MBPagesSkip",STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() skipped a 4MB page.");
1763	STAM_REG(pVM, &pPGM->StatR3InvalidatePagePDMappings, STAMTYPE_COUNTER, "/PGM/R3/InvalidatePage/PDMappings", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict).");
1764	STAM_REG(pVM, &pPGM->StatR3InvalidatePagePDNAs, STAMTYPE_COUNTER, "/PGM/R3/InvalidatePage/PDNAs", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was called for a not accessed page directory.");
1765	STAM_REG(pVM, &pPGM->StatR3InvalidatePagePDNPs, STAMTYPE_COUNTER, "/PGM/R3/InvalidatePage/PDNPs", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was called for a not present page directory.");
1766	STAM_REG(pVM, &pPGM->StatR3InvalidatePagePDOutOfSync, STAMTYPE_COUNTER, "/PGM/R3/InvalidatePage/PDOutOfSync", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was called for an out of sync page directory.");
1767	STAM_REG(pVM, &pPGM->StatR3InvalidatePageSkipped, STAMTYPE_COUNTER, "/PGM/R3/InvalidatePage/Skipped", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3.");
1768	STAM_REG(pVM, &pPGM->StatR3VirtHandlerSearchByPhys, STAMTYPE_PROFILE, "/PGM/R3/VirtHandlerSearchByPhys", STAMUNIT_TICKS_PER_CALL, "Profiling of pgmHandlerVirtualFindByPhysAddr.");
1769	STAM_REG(pVM, &pPGM->StatR3PhysHandlerReset, STAMTYPE_COUNTER, "/PGM/R3/PhysHandlerReset", STAMUNIT_OCCURENCES, "The number of times PGMHandlerPhysicalReset is called.");
1770	STAM_REG(pVM, &pPGM->StatR3PageOutOfSyncSupervisor, STAMTYPE_COUNTER, "/PGM/R3/OutOfSync/SuperVisor", STAMUNIT_OCCURENCES, "Number of traps due to pages out of sync and times VerifyAccessSyncPage calls SyncPage.");
1771	STAM_REG(pVM, &pPGM->StatR3PageOutOfSyncUser, STAMTYPE_COUNTER, "/PGM/R3/OutOfSync/User", STAMUNIT_OCCURENCES, "Number of traps due to pages out of sync and times VerifyAccessSyncPage calls SyncPage.");
1772	STAM_REG(pVM, &pPGM->StatR3Prefetch, STAMTYPE_PROFILE, "/PGM/R3/Prefetch", STAMUNIT_TICKS_PER_CALL, "PGMPrefetchPage profiling.");
1773	STAM_REG(pVM, &pPGM->StatR3ChunkR3MapTlbHits, STAMTYPE_COUNTER, "/PGM/ChunkR3Map/TlbHitsR3", STAMUNIT_OCCURENCES, "TLB hits.");
1774	STAM_REG(pVM, &pPGM->StatR3ChunkR3MapTlbMisses, STAMTYPE_COUNTER, "/PGM/ChunkR3Map/TlbMissesR3", STAMUNIT_OCCURENCES, "TLB misses.");
1775	STAM_REG(pVM, &pPGM->StatR3PageMapTlbHits, STAMTYPE_COUNTER, "/PGM/R3/Page/MapTlbHits", STAMUNIT_OCCURENCES, "TLB hits.");
1776	STAM_REG(pVM, &pPGM->StatR3PageMapTlbMisses, STAMTYPE_COUNTER, "/PGM/R3/Page/MapTlbMisses", STAMUNIT_OCCURENCES, "TLB misses.");
1777	STAM_REG(pVM, &pPGM->StatR3PageReplaceShared, STAMTYPE_COUNTER, "/PGM/R3/Page/ReplacedShared", STAMUNIT_OCCURENCES, "Times a shared page was replaced.");
1778	STAM_REG(pVM, &pPGM->StatR3PageReplaceZero, STAMTYPE_COUNTER, "/PGM/R3/Page/ReplacedZero", STAMUNIT_OCCURENCES, "Times the zero page was replaced.");
1779	/// @todo STAM_REG(pVM, &pPGM->StatR3PageHandyAllocs, STAMTYPE_COUNTER, "/PGM/R3/Page/HandyAllocs", STAMUNIT_OCCURENCES, "Number of times we've allocated more handy pages.");
1780	STAM_REG(pVM, &pPGM->StatR3FlushTLB, STAMTYPE_PROFILE, "/PGM/R3/FlushTLB", STAMUNIT_OCCURENCES, "Profiling of the PGMFlushTLB() body.");
1781	STAM_REG(pVM, &pPGM->StatR3FlushTLBNewCR3, STAMTYPE_COUNTER, "/PGM/R3/FlushTLB/NewCR3", STAMUNIT_OCCURENCES, "The number of times PGMFlushTLB was called with a new CR3, non-global. (switch)");
1782	STAM_REG(pVM, &pPGM->StatR3FlushTLBNewCR3Global, STAMTYPE_COUNTER, "/PGM/R3/FlushTLB/NewCR3Global", STAMUNIT_OCCURENCES, "The number of times PGMFlushTLB was called with a new CR3, global. (switch)");
1783	STAM_REG(pVM, &pPGM->StatR3FlushTLBSameCR3, STAMTYPE_COUNTER, "/PGM/R3/FlushTLB/SameCR3", STAMUNIT_OCCURENCES, "The number of times PGMFlushTLB was called with the same CR3, non-global. (flush)");
1784	STAM_REG(pVM, &pPGM->StatR3FlushTLBSameCR3Global, STAMTYPE_COUNTER, "/PGM/R3/FlushTLB/SameCR3Global", STAMUNIT_OCCURENCES, "The number of times PGMFlushTLB was called with the same CR3, global. (flush)");
1785	STAM_REG(pVM, &pPGM->StatR3GstModifyPage, STAMTYPE_PROFILE, "/PGM/R3/GstModifyPage", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMGstModifyPage() body.");
1786	#endif /* VBOX_WITH_STATISTICS */
1787	}
1788
1789
1790	/**
1791	* Init the PGM bits that rely on VMMR0 and MM to be fully initialized.
1792	*
1793	* The dynamic mapping area will also be allocated and initialized at this
1794	* time. We could allocate it during PGMR3Init of course, but the mapping
1795	* wouldn't be allocated at that time preventing us from setting up the
1796	* page table entries with the dummy page.
1797	*
1798	* @returns VBox status code.
1799	* @param pVM VM handle.
1800	*/
1801	VMMR3DECL(int) PGMR3InitDynMap(PVM pVM)
1802	{
1803	RTGCPTR GCPtr;
1804	int rc;
1805
1806	/*
1807	* Reserve space for the dynamic mappings.
1808	*/
1809	rc = MMR3HyperReserve(pVM, MM_HYPER_DYNAMIC_SIZE, "Dynamic mapping", &GCPtr);
1810	if (RT_SUCCESS(rc))
1811	pVM->pgm.s.pbDynPageMapBaseGC = GCPtr;
1812
1813	if ( RT_SUCCESS(rc)
1814	&& (pVM->pgm.s.pbDynPageMapBaseGC >> X86_PD_PAE_SHIFT) != ((pVM->pgm.s.pbDynPageMapBaseGC + MM_HYPER_DYNAMIC_SIZE - 1) >> X86_PD_PAE_SHIFT))
1815	{
1816	rc = MMR3HyperReserve(pVM, MM_HYPER_DYNAMIC_SIZE, "Dynamic mapping not crossing", &GCPtr);
1817	if (RT_SUCCESS(rc))
1818	pVM->pgm.s.pbDynPageMapBaseGC = GCPtr;
1819	}
1820	if (RT_SUCCESS(rc))
1821	{
1822	AssertRelease((pVM->pgm.s.pbDynPageMapBaseGC >> X86_PD_PAE_SHIFT) == ((pVM->pgm.s.pbDynPageMapBaseGC + MM_HYPER_DYNAMIC_SIZE - 1) >> X86_PD_PAE_SHIFT));
1823	MMR3HyperReserve(pVM, PAGE_SIZE, "fence", NULL);
1824	}
1825	return rc;
1826	}
1827
1828
1829	/**
1830	* Ring-3 init finalizing.
1831	*
1832	* @returns VBox status code.
1833	* @param pVM The VM handle.
1834	*/
1835	VMMR3DECL(int) PGMR3InitFinalize(PVM pVM)
1836	{
1837	int rc;
1838
1839	/*
1840	* Reserve space for the dynamic mappings.
1841	* Initialize the dynamic mapping pages with dummy pages to simply the cache.
1842	*/
1843	/* get the pointer to the page table entries. */
1844	PPGMMAPPING pMapping = pgmGetMapping(pVM, pVM->pgm.s.pbDynPageMapBaseGC);
1845	AssertRelease(pMapping);
1846	const uintptr_t off = pVM->pgm.s.pbDynPageMapBaseGC - pMapping->GCPtr;
1847	const unsigned iPT = off >> X86_PD_SHIFT;
1848	const unsigned iPG = (off >> X86_PT_SHIFT) & X86_PT_MASK;
1849	pVM->pgm.s.paDynPageMap32BitPTEsGC = pMapping->aPTs[iPT].pPTRC + iPG * sizeof(pMapping->aPTs[0].pPTR3->a[0]);
1850	pVM->pgm.s.paDynPageMapPaePTEsGC = pMapping->aPTs[iPT].paPaePTsRC + iPG * sizeof(pMapping->aPTs[0].paPaePTsR3->a[0]);
1851
1852	/* init cache */
1853	RTHCPHYS HCPhysDummy = MMR3PageDummyHCPhys(pVM);
1854	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.aHCPhysDynPageMapCache); i++)
1855	pVM->pgm.s.aHCPhysDynPageMapCache[i] = HCPhysDummy;
1856
1857	for (unsigned i = 0; i < MM_HYPER_DYNAMIC_SIZE; i += PAGE_SIZE)
1858	{
1859	rc = PGMMap(pVM, pVM->pgm.s.pbDynPageMapBaseGC + i, HCPhysDummy, PAGE_SIZE, 0);
1860	AssertRCReturn(rc, rc);
1861	}
1862
1863	/*
1864	* Note that AMD uses all the 8 reserved bits for the address (so 40 bits in total);
1865	* Intel only goes up to 36 bits, so we stick to 36 as well.
1866	*/
1867	/** @todo How to test for the 40 bits support? Long mode seems to be the test criterium. */
1868	uint32_t u32Dummy, u32Features;
1869	CPUMGetGuestCpuId(pVM, 1, &u32Dummy, &u32Dummy, &u32Dummy, &u32Features);
1870
1871	if (u32Features & X86_CPUID_FEATURE_EDX_PSE36)
1872	pVM->pgm.s.GCPhys4MBPSEMask = RT_BIT_64(36) - 1;
1873	else
1874	pVM->pgm.s.GCPhys4MBPSEMask = RT_BIT_64(32) - 1;
1875
1876	/*
1877	* Allocate memory if we're supposed to do that.
1878	*/
1879	if (pVM->pgm.s.fRamPreAlloc)
1880	rc = pgmR3PhysRamPreAllocate(pVM);
1881
1882	LogRel(("PGMR3InitFinalize: 4 MB PSE mask %RGp\n", pVM->pgm.s.GCPhys4MBPSEMask));
1883	return rc;
1884	}
1885
1886
1887	/**
1888	* Applies relocations to data and code managed by this component.
1889	*
1890	* This function will be called at init and whenever the VMM need to relocate it
1891	* self inside the GC.
1892	*
1893	* @param pVM The VM.
1894	* @param offDelta Relocation delta relative to old location.
1895	*/
1896	VMMR3DECL(void) PGMR3Relocate(PVM pVM, RTGCINTPTR offDelta)
1897	{
1898	LogFlow(("PGMR3Relocate %RGv to %RGv\n", pVM->pgm.s.GCPtrCR3Mapping, pVM->pgm.s.GCPtrCR3Mapping + offDelta));
1899
1900	/*
1901	* Paging stuff.
1902	*/
1903	pVM->pgm.s.GCPtrCR3Mapping += offDelta;
1904	/** @todo move this into shadow and guest specific relocation functions. */
1905	pVM->pgm.s.pGst32BitPdRC += offDelta;
1906	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.apGstPaePDsRC); i++)
1907	{
1908	pVM->pgm.s.apGstPaePDsRC[i] += offDelta;
1909	}
1910	pVM->pgm.s.pGstPaePdptRC += offDelta;
1911
1912	pVM->pgm.s.pShwPageCR3RC += offDelta;
1913
1914	pgmR3ModeDataInit(pVM, true /* resolve GC/R0 symbols */);
1915	pgmR3ModeDataSwitch(pVM, pVM->pgm.s.enmShadowMode, pVM->pgm.s.enmGuestMode);
1916
1917	PGM_SHW_PFN(Relocate, pVM)(pVM, offDelta);
1918	PGM_GST_PFN(Relocate, pVM)(pVM, offDelta);
1919	PGM_BTH_PFN(Relocate, pVM)(pVM, offDelta);
1920
1921	/*
1922	* Trees.
1923	*/
1924	pVM->pgm.s.pTreesRC = MMHyperR3ToRC(pVM, pVM->pgm.s.pTreesR3);
1925
1926	/*
1927	* Ram ranges.
1928	*/
1929	if (pVM->pgm.s.pRamRangesR3)
1930	{
1931	/* Update the pSelfRC pointers and relink them. */
1932	for (PPGMRAMRANGE pCur = pVM->pgm.s.pRamRangesR3; pCur; pCur = pCur->pNextR3)
1933	if (!(pCur->fFlags & PGM_RAM_RANGE_FLAGS_FLOATING))
1934	pCur->pSelfRC = MMHyperCCToRC(pVM, pCur);
1935	pgmR3PhysRelinkRamRanges(pVM);
1936	}
1937
1938	/*
1939	* Update the two page directories with all page table mappings.
1940	* (One or more of them have changed, that's why we're here.)
1941	*/
1942	pVM->pgm.s.pMappingsRC = MMHyperR3ToRC(pVM, pVM->pgm.s.pMappingsR3);
1943	for (PPGMMAPPING pCur = pVM->pgm.s.pMappingsR3; pCur->pNextR3; pCur = pCur->pNextR3)
1944	pCur->pNextRC = MMHyperR3ToRC(pVM, pCur->pNextR3);
1945
1946	/* Relocate GC addresses of Page Tables. */
1947	for (PPGMMAPPING pCur = pVM->pgm.s.pMappingsR3; pCur; pCur = pCur->pNextR3)
1948	{
1949	for (RTHCUINT i = 0; i < pCur->cPTs; i++)
1950	{
1951	pCur->aPTs[i].pPTRC = MMHyperR3ToRC(pVM, pCur->aPTs[i].pPTR3);
1952	pCur->aPTs[i].paPaePTsRC = MMHyperR3ToRC(pVM, pCur->aPTs[i].paPaePTsR3);
1953	}
1954	}
1955
1956	/*
1957	* Dynamic page mapping area.
1958	*/
1959	pVM->pgm.s.paDynPageMap32BitPTEsGC += offDelta;
1960	pVM->pgm.s.paDynPageMapPaePTEsGC += offDelta;
1961	pVM->pgm.s.pbDynPageMapBaseGC += offDelta;
1962
1963	/*
1964	* The Zero page.
1965	*/
1966	pVM->pgm.s.pvZeroPgR0 = MMHyperR3ToR0(pVM, pVM->pgm.s.pvZeroPgR3);
1967	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1968	AssertRelease(pVM->pgm.s.pvZeroPgR0 != NIL_RTR0PTR \|\| !VMMIsHwVirtExtForced(pVM));
1969	#else
1970	AssertRelease(pVM->pgm.s.pvZeroPgR0 != NIL_RTR0PTR);
1971	#endif
1972
1973	/*
1974	* Physical and virtual handlers.
1975	*/
1976	RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysHandlers, true, pgmR3RelocatePhysHandler, &offDelta);
1977	RTAvlroGCPtrDoWithAll(&pVM->pgm.s.pTreesR3->VirtHandlers, true, pgmR3RelocateVirtHandler, &offDelta);
1978	RTAvlroGCPtrDoWithAll(&pVM->pgm.s.pTreesR3->HyperVirtHandlers, true, pgmR3RelocateHyperVirtHandler, &offDelta);
1979
1980	/*
1981	* The page pool.
1982	*/
1983	pgmR3PoolRelocate(pVM);
1984	}
1985
1986
1987	/**
1988	* Callback function for relocating a physical access handler.
1989	*
1990	* @returns 0 (continue enum)
1991	* @param pNode Pointer to a PGMPHYSHANDLER node.
1992	* @param pvUser Pointer to the offDelta. This is a pointer to the delta since we're
1993	* not certain the delta will fit in a void pointer for all possible configs.
1994	*/
1995	static DECLCALLBACK(int) pgmR3RelocatePhysHandler(PAVLROGCPHYSNODECORE pNode, void *pvUser)
1996	{
1997	PPGMPHYSHANDLER pHandler = (PPGMPHYSHANDLER)pNode;
1998	RTGCINTPTR offDelta = *(PRTGCINTPTR)pvUser;
1999	if (pHandler->pfnHandlerRC)
2000	pHandler->pfnHandlerRC += offDelta;
2001	if (pHandler->pvUserRC >= 0x10000)
2002	pHandler->pvUserRC += offDelta;
2003	return 0;
2004	}
2005
2006
2007	/**
2008	* Callback function for relocating a virtual access handler.
2009	*
2010	* @returns 0 (continue enum)
2011	* @param pNode Pointer to a PGMVIRTHANDLER node.
2012	* @param pvUser Pointer to the offDelta. This is a pointer to the delta since we're
2013	* not certain the delta will fit in a void pointer for all possible configs.
2014	*/
2015	static DECLCALLBACK(int) pgmR3RelocateVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser)
2016	{
2017	PPGMVIRTHANDLER pHandler = (PPGMVIRTHANDLER)pNode;
2018	RTGCINTPTR offDelta = *(PRTGCINTPTR)pvUser;
2019	Assert( pHandler->enmType == PGMVIRTHANDLERTYPE_ALL
2020	\|\| pHandler->enmType == PGMVIRTHANDLERTYPE_WRITE);
2021	Assert(pHandler->pfnHandlerRC);
2022	pHandler->pfnHandlerRC += offDelta;
2023	return 0;
2024	}
2025
2026
2027	/**
2028	* Callback function for relocating a virtual access handler for the hypervisor mapping.
2029	*
2030	* @returns 0 (continue enum)
2031	* @param pNode Pointer to a PGMVIRTHANDLER node.
2032	* @param pvUser Pointer to the offDelta. This is a pointer to the delta since we're
2033	* not certain the delta will fit in a void pointer for all possible configs.
2034	*/
2035	static DECLCALLBACK(int) pgmR3RelocateHyperVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser)
2036	{
2037	PPGMVIRTHANDLER pHandler = (PPGMVIRTHANDLER)pNode;
2038	RTGCINTPTR offDelta = *(PRTGCINTPTR)pvUser;
2039	Assert(pHandler->enmType == PGMVIRTHANDLERTYPE_HYPERVISOR);
2040	Assert(pHandler->pfnHandlerRC);
2041	pHandler->pfnHandlerRC += offDelta;
2042	return 0;
2043	}
2044
2045
2046	/**
2047	* The VM is being reset.
2048	*
2049	* For the PGM component this means that any PD write monitors
2050	* needs to be removed.
2051	*
2052	* @param pVM VM handle.
2053	*/
2054	VMMR3DECL(void) PGMR3Reset(PVM pVM)
2055	{
2056	LogFlow(("PGMR3Reset:\n"));
2057	VM_ASSERT_EMT(pVM);
2058
2059	pgmLock(pVM);
2060
2061	/*
2062	* Unfix any fixed mappings and disable CR3 monitoring.
2063	*/
2064	pVM->pgm.s.fMappingsFixed = false;
2065	pVM->pgm.s.GCPtrMappingFixed = 0;
2066	pVM->pgm.s.cbMappingFixed = 0;
2067
2068	/* Exit the guest paging mode before the pgm pool gets reset.
2069	* Important to clean up the amd64 case.
2070	*/
2071	int rc = PGM_GST_PFN(Exit, pVM)(pVM);
2072	AssertRC(rc);
2073	#ifdef DEBUG
2074	DBGFR3InfoLog(pVM, "mappings", NULL);
2075	DBGFR3InfoLog(pVM, "handlers", "all nostat");
2076	#endif
2077
2078	/*
2079	* Reset the shadow page pool.
2080	*/
2081	pgmR3PoolReset(pVM);
2082
2083	/*
2084	* Re-init other members.
2085	*/
2086	pVM->pgm.s.fA20Enabled = true;
2087
2088	/*
2089	* Clear the FFs PGM owns.
2090	*/
2091	VM_FF_CLEAR(pVM, VM_FF_PGM_SYNC_CR3);
2092	VM_FF_CLEAR(pVM, VM_FF_PGM_SYNC_CR3_NON_GLOBAL);
2093
2094	/*
2095	* Reset (zero) RAM pages.
2096	*/
2097	rc = pgmR3PhysRamReset(pVM);
2098	if (RT_SUCCESS(rc))
2099	{
2100	/*
2101	* Reset (zero) shadow ROM pages.
2102	*/
2103	rc = pgmR3PhysRomReset(pVM);
2104	if (RT_SUCCESS(rc))
2105	{
2106	/*
2107	* Switch mode back to real mode.
2108	*/
2109	rc = PGMR3ChangeMode(pVM, PGMMODE_REAL);
2110	STAM_REL_COUNTER_RESET(&pVM->pgm.s.cGuestModeChanges);
2111	}
2112	}
2113
2114	pgmUnlock(pVM);
2115	//return rc;
2116	AssertReleaseRC(rc);
2117	}
2118
2119
2120	#ifdef VBOX_STRICT
2121	/**
2122	* VM state change callback for clearing fNoMorePhysWrites after
2123	* a snapshot has been created.
2124	*/
2125	static DECLCALLBACK(void) pgmR3ResetNoMorePhysWritesFlag(PVM pVM, VMSTATE enmState, VMSTATE enmOldState, void *pvUser)
2126	{
2127	if (enmState == VMSTATE_RUNNING)
2128	pVM->pgm.s.fNoMorePhysWrites = false;
2129	}
2130	#endif
2131
2132
2133	/**
2134	* Terminates the PGM.
2135	*
2136	* @returns VBox status code.
2137	* @param pVM Pointer to VM structure.
2138	*/
2139	VMMR3DECL(int) PGMR3Term(PVM pVM)
2140	{
2141	PGMDeregisterStringFormatTypes();
2142	return PDMR3CritSectDelete(&pVM->pgm.s.CritSect);
2143	}
2144
2145
2146	/**
2147	* Terminates the per-VCPU PGM.
2148	*
2149	* Termination means cleaning up and freeing all resources,
2150	* the VM it self is at this point powered off or suspended.
2151	*
2152	* @returns VBox status code.
2153	* @param pVM The VM to operate on.
2154	*/
2155	VMMR3DECL(int) PGMR3TermCPU(PVM pVM)
2156	{
2157	return 0;
2158	}
2159
2160
2161	/**
2162	* Find the ROM tracking structure for the given page.
2163	*
2164	* @returns Pointer to the ROM page structure. NULL if the caller didn't check
2165	* that it's a ROM page.
2166	* @param pVM The VM handle.
2167	* @param GCPhys The address of the ROM page.
2168	*/
2169	static PPGMROMPAGE pgmR3GetRomPage(PVM pVM, RTGCPHYS GCPhys)
2170	{
2171	for (PPGMROMRANGE pRomRange = pVM->pgm.s.CTX_SUFF(pRomRanges);
2172	pRomRange;
2173	pRomRange = pRomRange->CTX_SUFF(pNext))
2174	{
2175	RTGCPHYS off = GCPhys - pRomRange->GCPhys;
2176	if (GCPhys - pRomRange->GCPhys < pRomRange->cb)
2177	return &pRomRange->aPages[off >> PAGE_SHIFT];
2178	}
2179	return NULL;
2180	}
2181
2182
2183	/**
2184	* Save zero indicator + bits for the specified page.
2185	*
2186	* @returns VBox status code, errors are logged/asserted before returning.
2187	* @param pVM The VM handle.
2188	* @param pSSH The saved state handle.
2189	* @param pPage The page to save.
2190	* @param GCPhys The address of the page.
2191	* @param pRam The ram range (for error logging).
2192	*/
2193	static int pgmR3SavePage(PVM pVM, PSSMHANDLE pSSM, PPGMPAGE pPage, RTGCPHYS GCPhys, PPGMRAMRANGE pRam)
2194	{
2195	int rc;
2196	if (PGM_PAGE_IS_ZERO(pPage))
2197	rc = SSMR3PutU8(pSSM, 0);
2198	else
2199	{
2200	void const *pvPage;
2201	rc = pgmPhysGCPhys2CCPtrInternalReadOnly(pVM, pPage, GCPhys, &pvPage);
2202	AssertLogRelMsgRCReturn(rc, ("pPage=%R[pgmpage] GCPhys=%#x %s\n", pPage, GCPhys, pRam->pszDesc), rc);
2203
2204	SSMR3PutU8(pSSM, 1);
2205	rc = SSMR3PutMem(pSSM, pvPage, PAGE_SIZE);
2206	}
2207	return rc;
2208	}
2209
2210
2211	/**
2212	* Save a shadowed ROM page.
2213	*
2214	* Format: Type, protection, and two pages with zero indicators.
2215	*
2216	* @returns VBox status code, errors are logged/asserted before returning.
2217	* @param pVM The VM handle.
2218	* @param pSSH The saved state handle.
2219	* @param pPage The page to save.
2220	* @param GCPhys The address of the page.
2221	* @param pRam The ram range (for error logging).
2222	*/
2223	static int pgmR3SaveShadowedRomPage(PVM pVM, PSSMHANDLE pSSM, PPGMPAGE pPage, RTGCPHYS GCPhys, PPGMRAMRANGE pRam)
2224	{
2225	/* Need to save both pages and the current state. */
2226	PPGMROMPAGE pRomPage = pgmR3GetRomPage(pVM, GCPhys);
2227	AssertLogRelMsgReturn(pRomPage, ("GCPhys=%RGp %s\n", GCPhys, pRam->pszDesc), VERR_INTERNAL_ERROR);
2228
2229	SSMR3PutU8(pSSM, PGMPAGETYPE_ROM_SHADOW);
2230	SSMR3PutU8(pSSM, pRomPage->enmProt);
2231
2232	int rc = pgmR3SavePage(pVM, pSSM, pPage, GCPhys, pRam);
2233	if (RT_SUCCESS(rc))
2234	{
2235	PPGMPAGE pPagePassive = PGMROMPROT_IS_ROM(pRomPage->enmProt) ? &pRomPage->Shadow : &pRomPage->Virgin;
2236	rc = pgmR3SavePage(pVM, pSSM, pPagePassive, GCPhys, pRam);
2237	}
2238	return rc;
2239	}
2240
2241	/** PGM fields to save/load. */
2242	static SSMFIELD s_aPGMFields[] =
2243	{
2244	SSMFIELD_ENTRY( PGM, fMappingsFixed),
2245	SSMFIELD_ENTRY_GCPTR( PGM, GCPtrMappingFixed),
2246	SSMFIELD_ENTRY( PGM, cbMappingFixed),
2247	SSMFIELD_ENTRY( PGM, fA20Enabled),
2248	SSMFIELD_ENTRY_GCPHYS( PGM, GCPhysA20Mask),
2249	SSMFIELD_ENTRY( PGM, enmGuestMode),
2250	SSMFIELD_ENTRY_TERM()
2251	};
2252
2253
2254	/**
2255	* Execute state save operation.
2256	*
2257	* @returns VBox status code.
2258	* @param pVM VM Handle.
2259	* @param pSSM SSM operation handle.
2260	*/
2261	static DECLCALLBACK(int) pgmR3Save(PVM pVM, PSSMHANDLE pSSM)
2262	{
2263	int rc;
2264	PPGM pPGM = &pVM->pgm.s;
2265
2266	/*
2267	* Lock PGM and set the no-more-writes indicator.
2268	*/
2269	pgmLock(pVM);
2270	pVM->pgm.s.fNoMorePhysWrites = true;
2271
2272	/*
2273	* Save basic data (required / unaffected by relocation).
2274	*/
2275	SSMR3PutStruct(pSSM, pPGM, &s_aPGMFields[0]);
2276
2277	/*
2278	* The guest mappings.
2279	*/
2280	uint32_t i = 0;
2281	for (PPGMMAPPING pMapping = pPGM->pMappingsR3; pMapping; pMapping = pMapping->pNextR3, i++)
2282	{
2283	SSMR3PutU32( pSSM, i);
2284	SSMR3PutStrZ( pSSM, pMapping->pszDesc); /* This is the best unique id we have... */
2285	SSMR3PutGCPtr( pSSM, pMapping->GCPtr);
2286	SSMR3PutGCUIntPtr(pSSM, pMapping->cPTs);
2287	}
2288	rc = SSMR3PutU32(pSSM, ~0); /* terminator. */
2289
2290	/*
2291	* Ram ranges and the memory they describe.
2292	*/
2293	i = 0;
2294	for (PPGMRAMRANGE pRam = pPGM->pRamRangesR3; pRam; pRam = pRam->pNextR3, i++)
2295	{
2296	/*
2297	* Save the ram range details.
2298	*/
2299	SSMR3PutU32(pSSM, i);
2300	SSMR3PutGCPhys(pSSM, pRam->GCPhys);
2301	SSMR3PutGCPhys(pSSM, pRam->GCPhysLast);
2302	SSMR3PutGCPhys(pSSM, pRam->cb);
2303	SSMR3PutU8(pSSM, !!pRam->pvR3); /* Boolean indicating memory or not. */
2304	SSMR3PutStrZ(pSSM, pRam->pszDesc); /* This is the best unique id we have... */
2305
2306	/*
2307	* Iterate the pages, only two special case.
2308	*/
2309	uint32_t const cPages = pRam->cb >> PAGE_SHIFT;
2310	for (uint32_t iPage = 0; iPage < cPages; iPage++)
2311	{
2312	RTGCPHYS GCPhysPage = pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT);
2313	PPGMPAGE pPage = &pRam->aPages[iPage];
2314	uint8_t uType = PGM_PAGE_GET_TYPE(pPage);
2315
2316	if (uType == PGMPAGETYPE_ROM_SHADOW)
2317	rc = pgmR3SaveShadowedRomPage(pVM, pSSM, pPage, GCPhysPage, pRam);
2318	else if (uType == PGMPAGETYPE_MMIO2_ALIAS_MMIO)
2319	{
2320	/* MMIO2 alias -> MMIO; the device will just have to deal with this. */
2321	SSMR3PutU8(pSSM, PGMPAGETYPE_MMIO);
2322	rc = SSMR3PutU8(pSSM, 0 /* ZERO */);
2323	}
2324	else
2325	{
2326	SSMR3PutU8(pSSM, uType);
2327	rc = pgmR3SavePage(pVM, pSSM, pPage, GCPhysPage, pRam);
2328	}
2329	if (RT_FAILURE(rc))
2330	break;
2331	}
2332	if (RT_FAILURE(rc))
2333	break;
2334	}
2335
2336	pgmUnlock(pVM);
2337	return SSMR3PutU32(pSSM, ~0); /* terminator. */
2338	}
2339
2340
2341	/**
2342	* Load an ignored page.
2343	*
2344	* @returns VBox status code.
2345	* @param pSSM The saved state handle.
2346	*/
2347	static int pgmR3LoadPageToDevNull(PSSMHANDLE pSSM)
2348	{
2349	uint8_t abPage[PAGE_SIZE];
2350	return SSMR3GetMem(pSSM, &abPage[0], sizeof(abPage));
2351	}
2352
2353
2354	/**
2355	* Loads a page without any bits in the saved state, i.e. making sure it's
2356	* really zero.
2357	*
2358	* @returns VBox status code.
2359	* @param pVM The VM handle.
2360	* @param uType The page type or PGMPAGETYPE_INVALID (old saved
2361	* state).
2362	* @param pPage The guest page tracking structure.
2363	* @param GCPhys The page address.
2364	* @param pRam The ram range (logging).
2365	*/
2366	static int pgmR3LoadPageZero(PVM pVM, uint8_t uType, PPGMPAGE pPage, RTGCPHYS GCPhys, PPGMRAMRANGE pRam)
2367	{
2368	if ( PGM_PAGE_GET_TYPE(pPage) != uType
2369	&& uType != PGMPAGETYPE_INVALID)
2370	return VERR_SSM_UNEXPECTED_DATA;
2371
2372	/* I think this should be sufficient. */
2373	if (!PGM_PAGE_IS_ZERO(pPage))
2374	return VERR_SSM_UNEXPECTED_DATA;
2375
2376	NOREF(pVM);
2377	NOREF(GCPhys);
2378	NOREF(pRam);
2379	return VINF_SUCCESS;
2380	}
2381
2382
2383	/**
2384	* Loads a page from the saved state.
2385	*
2386	* @returns VBox status code.
2387	* @param pVM The VM handle.
2388	* @param pSSM The SSM handle.
2389	* @param uType The page type or PGMPAGETYEP_INVALID (old saved
2390	* state).
2391	* @param pPage The guest page tracking structure.
2392	* @param GCPhys The page address.
2393	* @param pRam The ram range (logging).
2394	*/
2395	static int pgmR3LoadPageBits(PVM pVM, PSSMHANDLE pSSM, uint8_t uType, PPGMPAGE pPage, RTGCPHYS GCPhys, PPGMRAMRANGE pRam)
2396	{
2397	int rc;
2398
2399	/*
2400	* Match up the type, dealing with MMIO2 aliases (dropped).
2401	*/
2402	AssertLogRelMsgReturn( PGM_PAGE_GET_TYPE(pPage) == uType
2403	\|\| uType == PGMPAGETYPE_INVALID,
2404	("pPage=%R[pgmpage] GCPhys=%#x %s\n", pPage, GCPhys, pRam->pszDesc),
2405	VERR_SSM_UNEXPECTED_DATA);
2406
2407	/*
2408	* Load the page.
2409	*/
2410	void *pvPage;
2411	rc = pgmPhysGCPhys2CCPtrInternal(pVM, pPage, GCPhys, &pvPage);
2412	if (RT_SUCCESS(rc))
2413	rc = SSMR3GetMem(pSSM, pvPage, PAGE_SIZE);
2414
2415	return rc;
2416	}
2417
2418
2419	/**
2420	* Loads a page (counter part to pgmR3SavePage).
2421	*
2422	* @returns VBox status code, fully bitched errors.
2423	* @param pVM The VM handle.
2424	* @param pSSM The SSM handle.
2425	* @param uType The page type.
2426	* @param pPage The page.
2427	* @param GCPhys The page address.
2428	* @param pRam The RAM range (for error messages).
2429	*/
2430	static int pgmR3LoadPage(PVM pVM, PSSMHANDLE pSSM, uint8_t uType, PPGMPAGE pPage, RTGCPHYS GCPhys, PPGMRAMRANGE pRam)
2431	{
2432	uint8_t uState;
2433	int rc = SSMR3GetU8(pSSM, &uState);
2434	AssertLogRelMsgRCReturn(rc, ("pPage=%R[pgmpage] GCPhys=%#x %s rc=%Rrc\n", pPage, GCPhys, pRam->pszDesc, rc), rc);
2435	if (uState == 0 /* zero */)
2436	rc = pgmR3LoadPageZero(pVM, uType, pPage, GCPhys, pRam);
2437	else if (uState == 1)
2438	rc = pgmR3LoadPageBits(pVM, pSSM, uType, pPage, GCPhys, pRam);
2439	else
2440	rc = VERR_INTERNAL_ERROR;
2441	AssertLogRelMsgRCReturn(rc, ("pPage=%R[pgmpage] uState=%d uType=%d GCPhys=%RGp %s rc=%Rrc\n",
2442	pPage, uState, uType, GCPhys, pRam->pszDesc, rc),
2443	rc);
2444	return VINF_SUCCESS;
2445	}
2446
2447
2448	/**
2449	* Loads a shadowed ROM page.
2450	*
2451	* @returns VBox status code, errors are fully bitched.
2452	* @param pVM The VM handle.
2453	* @param pSSM The saved state handle.
2454	* @param pPage The page.
2455	* @param GCPhys The page address.
2456	* @param pRam The RAM range (for error messages).
2457	*/
2458	static int pgmR3LoadShadowedRomPage(PVM pVM, PSSMHANDLE pSSM, PPGMPAGE pPage, RTGCPHYS GCPhys, PPGMRAMRANGE pRam)
2459	{
2460	/*
2461	* Load and set the protection first, then load the two pages, the first
2462	* one is the active the other is the passive.
2463	*/
2464	PPGMROMPAGE pRomPage = pgmR3GetRomPage(pVM, GCPhys);
2465	AssertLogRelMsgReturn(pRomPage, ("GCPhys=%RGp %s\n", GCPhys, pRam->pszDesc), VERR_INTERNAL_ERROR);
2466
2467	uint8_t uProt;
2468	int rc = SSMR3GetU8(pSSM, &uProt);
2469	AssertLogRelMsgRCReturn(rc, ("pPage=%R[pgmpage] GCPhys=%#x %s\n", pPage, GCPhys, pRam->pszDesc), rc);
2470	PGMROMPROT enmProt = (PGMROMPROT)uProt;
2471	AssertLogRelMsgReturn( enmProt >= PGMROMPROT_INVALID
2472	&& enmProt < PGMROMPROT_END,
2473	("enmProt=%d pPage=%R[pgmpage] GCPhys=%#x %s\n", enmProt, pPage, GCPhys, pRam->pszDesc),
2474	VERR_SSM_UNEXPECTED_DATA);
2475
2476	if (pRomPage->enmProt != enmProt)
2477	{
2478	rc = PGMR3PhysRomProtect(pVM, GCPhys, PAGE_SIZE, enmProt);
2479	AssertLogRelRCReturn(rc, rc);
2480	AssertLogRelReturn(pRomPage->enmProt == enmProt, VERR_INTERNAL_ERROR);
2481	}
2482
2483	PPGMPAGE pPageActive = PGMROMPROT_IS_ROM(enmProt) ? &pRomPage->Virgin : &pRomPage->Shadow;
2484	PPGMPAGE pPagePassive = PGMROMPROT_IS_ROM(enmProt) ? &pRomPage->Shadow : &pRomPage->Virgin;
2485	uint8_t u8ActiveType = PGMROMPROT_IS_ROM(enmProt) ? PGMPAGETYPE_ROM : PGMPAGETYPE_ROM_SHADOW;
2486	uint8_t u8PassiveType= PGMROMPROT_IS_ROM(enmProt) ? PGMPAGETYPE_ROM_SHADOW : PGMPAGETYPE_ROM;
2487
2488	rc = pgmR3LoadPage(pVM, pSSM, u8ActiveType, pPage, GCPhys, pRam);
2489	if (RT_SUCCESS(rc))
2490	{
2491	pPageActive = pPage;
2492	rc = pgmR3LoadPage(pVM, pSSM, u8PassiveType, pPagePassive, GCPhys, pRam);
2493	}
2494	return rc;
2495	}
2496
2497
2498	/**
2499	* Worker for pgmR3Load.
2500	*
2501	* @returns VBox status code.
2502	*
2503	* @param pVM The VM handle.
2504	* @param pSSM The SSM handle.
2505	* @param u32Version The saved state version.
2506	*/
2507	static int pgmR3LoadLocked(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version)
2508	{
2509	int rc;
2510	PPGM pPGM = &pVM->pgm.s;
2511	uint32_t u32Sep;
2512
2513	/*
2514	* Load basic data (required / unaffected by relocation).
2515	*/
2516	if (u32Version >= PGM_SAVED_STATE_VERSION_RR_DESC)
2517	{
2518	rc = SSMR3GetStruct(pSSM, pPGM, &s_aPGMFields[0]);
2519	AssertLogRelRCReturn(rc, rc);
2520	}
2521	else
2522	{
2523	SSMR3GetBool(pSSM, &pPGM->fMappingsFixed);
2524	SSMR3GetGCPtr(pSSM, &pPGM->GCPtrMappingFixed);
2525	SSMR3GetU32(pSSM, &pPGM->cbMappingFixed);
2526
2527	uint32_t cbRamSizeIgnored;
2528	rc = SSMR3GetU32(pSSM, &cbRamSizeIgnored);
2529	if (RT_FAILURE(rc))
2530	return rc;
2531	SSMR3GetGCPhys(pSSM, &pPGM->GCPhysA20Mask);
2532
2533	uint32_t u32 = 0;
2534	SSMR3GetUInt(pSSM, &u32);
2535	pPGM->fA20Enabled = !!u32;
2536	SSMR3GetUInt(pSSM, &pPGM->fSyncFlags);
2537	RTUINT uGuestMode;
2538	SSMR3GetUInt(pSSM, &uGuestMode);
2539	pPGM->enmGuestMode = (PGMMODE)uGuestMode;
2540
2541	/* check separator. */
2542	SSMR3GetU32(pSSM, &u32Sep);
2543	if (RT_FAILURE(rc))
2544	return rc;
2545	if (u32Sep != (uint32_t)~0)
2546	{
2547	AssertMsgFailed(("u32Sep=%#x (first)\n", u32Sep));
2548	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2549	}
2550	}
2551
2552	/*
2553	* The guest mappings.
2554	*/
2555	uint32_t i = 0;
2556	for (;; i++)
2557	{
2558	/* Check the seqence number / separator. */
2559	rc = SSMR3GetU32(pSSM, &u32Sep);
2560	if (RT_FAILURE(rc))
2561	return rc;
2562	if (u32Sep == ~0U)
2563	break;
2564	if (u32Sep != i)
2565	{
2566	AssertMsgFailed(("u32Sep=%#x (last)\n", u32Sep));
2567	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2568	}
2569
2570	/* get the mapping details. */
2571	char szDesc[256];
2572	szDesc[0] = '\0';
2573	rc = SSMR3GetStrZ(pSSM, szDesc, sizeof(szDesc));
2574	if (RT_FAILURE(rc))
2575	return rc;
2576	RTGCPTR GCPtr;
2577	SSMR3GetGCPtr(pSSM, &GCPtr);
2578	RTGCPTR cPTs;
2579	rc = SSMR3GetGCUIntPtr(pSSM, &cPTs);
2580	if (RT_FAILURE(rc))
2581	return rc;
2582
2583	/* find matching range. */
2584	PPGMMAPPING pMapping;
2585	for (pMapping = pPGM->pMappingsR3; pMapping; pMapping = pMapping->pNextR3)
2586	if ( pMapping->cPTs == cPTs
2587	&& !strcmp(pMapping->pszDesc, szDesc))
2588	break;
2589	AssertLogRelMsgReturn(pMapping, ("Couldn't find mapping: cPTs=%#x szDesc=%s (GCPtr=%RGv)\n",
2590	cPTs, szDesc, GCPtr),
2591	VERR_SSM_LOAD_CONFIG_MISMATCH);
2592
2593	/* relocate it. */
2594	if (pMapping->GCPtr != GCPtr)
2595	{
2596	AssertMsg((GCPtr >> X86_PD_SHIFT << X86_PD_SHIFT) == GCPtr, ("GCPtr=%RGv\n", GCPtr));
2597	pgmR3MapRelocate(pVM, pMapping, pMapping->GCPtr, GCPtr);
2598	}
2599	else
2600	Log(("pgmR3Load: '%s' needed no relocation (%RGv)\n", szDesc, GCPtr));
2601	}
2602
2603	/*
2604	* Ram range flags and bits.
2605	*/
2606	i = 0;
2607	for (PPGMRAMRANGE pRam = pPGM->pRamRangesR3; pRam; pRam = pRam->pNextR3, i++)
2608	{
2609	/** @todo MMIO ranges may move (PCI reconfig), we currently assume they don't. */
2610
2611	/* Check the seqence number / separator. */
2612	rc = SSMR3GetU32(pSSM, &u32Sep);
2613	if (RT_FAILURE(rc))
2614	return rc;
2615	if (u32Sep == ~0U)
2616	break;
2617	if (u32Sep != i)
2618	{
2619	AssertMsgFailed(("u32Sep=%#x (last)\n", u32Sep));
2620	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2621	}
2622
2623	/* Get the range details. */
2624	RTGCPHYS GCPhys;
2625	SSMR3GetGCPhys(pSSM, &GCPhys);
2626	RTGCPHYS GCPhysLast;
2627	SSMR3GetGCPhys(pSSM, &GCPhysLast);
2628	RTGCPHYS cb;
2629	SSMR3GetGCPhys(pSSM, &cb);
2630	uint8_t fHaveBits;
2631	rc = SSMR3GetU8(pSSM, &fHaveBits);
2632	if (RT_FAILURE(rc))
2633	return rc;
2634	if (fHaveBits & ~1)
2635	{
2636	AssertMsgFailed(("u32Sep=%#x (last)\n", u32Sep));
2637	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2638	}
2639	size_t cchDesc = 0;
2640	char szDesc[256];
2641	szDesc[0] = '\0';
2642	if (u32Version >= PGM_SAVED_STATE_VERSION_RR_DESC)
2643	{
2644	rc = SSMR3GetStrZ(pSSM, szDesc, sizeof(szDesc));
2645	if (RT_FAILURE(rc))
2646	return rc;
2647	/* Since we've modified the description strings in r45878, only compare
2648	them if the saved state is more recent. */
2649	if (u32Version != PGM_SAVED_STATE_VERSION_RR_DESC)
2650	cchDesc = strlen(szDesc);
2651	}
2652
2653	/*
2654	* Match it up with the current range.
2655	*
2656	* Note there is a hack for dealing with the high BIOS mapping
2657	* in the old saved state format, this means we might not have
2658	* a 1:1 match on success.
2659	*/
2660	if ( ( GCPhys != pRam->GCPhys
2661	\|\| GCPhysLast != pRam->GCPhysLast
2662	\|\| cb != pRam->cb
2663	\|\| ( cchDesc
2664	&& strcmp(szDesc, pRam->pszDesc)) )
2665	/* Hack for PDMDevHlpPhysReserve(pDevIns, 0xfff80000, 0x80000, "High ROM Region"); */
2666	&& ( u32Version != PGM_SAVED_STATE_VERSION_OLD_PHYS_CODE
2667	\|\| GCPhys != UINT32_C(0xfff80000)
2668	\|\| GCPhysLast != UINT32_C(0xffffffff)
2669	\|\| pRam->GCPhysLast != GCPhysLast
2670	\|\| pRam->GCPhys < GCPhys
2671	\|\| !fHaveBits)
2672	)
2673	{
2674	LogRel(("Ram range: %RGp-%RGp %RGp bytes %s %s\n"
2675	"State : %RGp-%RGp %RGp bytes %s %s\n",
2676	pRam->GCPhys, pRam->GCPhysLast, pRam->cb, pRam->pvR3 ? "bits" : "nobits", pRam->pszDesc,
2677	GCPhys, GCPhysLast, cb, fHaveBits ? "bits" : "nobits", szDesc));
2678	/*
2679	* If we're loading a state for debugging purpose, don't make a fuss if
2680	* the MMIO and ROM stuff isn't 100% right, just skip the mismatches.
2681	*/
2682	if ( SSMR3HandleGetAfter(pSSM) != SSMAFTER_DEBUG_IT
2683	\|\| GCPhys < 8 * _1M)
2684	AssertFailedReturn(VERR_SSM_LOAD_CONFIG_MISMATCH);
2685
2686	AssertMsgFailed(("debug skipping not implemented, sorry\n"));
2687	continue;
2688	}
2689
2690	uint32_t cPages = (GCPhysLast - GCPhys + 1) >> PAGE_SHIFT;
2691	if (u32Version >= PGM_SAVED_STATE_VERSION_RR_DESC)
2692	{
2693	/*
2694	* Load the pages one by one.
2695	*/
2696	for (uint32_t iPage = 0; iPage < cPages; iPage++)
2697	{
2698	RTGCPHYS const GCPhysPage = ((RTGCPHYS)iPage << PAGE_SHIFT) + pRam->GCPhys;
2699	PPGMPAGE pPage = &pRam->aPages[iPage];
2700	uint8_t uType;
2701	rc = SSMR3GetU8(pSSM, &uType);
2702	AssertLogRelMsgRCReturn(rc, ("pPage=%R[pgmpage] iPage=%#x GCPhysPage=%#x %s\n", pPage, iPage, GCPhysPage, pRam->pszDesc), rc);
2703	if (uType == PGMPAGETYPE_ROM_SHADOW)
2704	rc = pgmR3LoadShadowedRomPage(pVM, pSSM, pPage, GCPhysPage, pRam);
2705	else
2706	rc = pgmR3LoadPage(pVM, pSSM, uType, pPage, GCPhysPage, pRam);
2707	AssertLogRelMsgRCReturn(rc, ("rc=%Rrc iPage=%#x GCPhysPage=%#x %s\n", rc, iPage, GCPhysPage, pRam->pszDesc), rc);
2708	}
2709	}
2710	else
2711	{
2712	/*
2713	* Old format.
2714	*/
2715	AssertLogRelReturn(!pVM->pgm.s.fRamPreAlloc, VERR_NOT_SUPPORTED); /* can't be detected. */
2716
2717	/* Of the page flags, pick up MMIO2 and ROM/RESERVED for the !fHaveBits case.
2718	The rest is generally irrelevant and wrong since the stuff have to match registrations. */
2719	uint32_t fFlags = 0;
2720	for (uint32_t iPage = 0; iPage < cPages; iPage++)
2721	{
2722	uint16_t u16Flags;
2723	rc = SSMR3GetU16(pSSM, &u16Flags);
2724	AssertLogRelMsgRCReturn(rc, ("rc=%Rrc iPage=%#x GCPhys=%#x %s\n", rc, iPage, pRam->GCPhys, pRam->pszDesc), rc);
2725	fFlags \|= u16Flags;
2726	}
2727
2728	/* Load the bits */
2729	if ( !fHaveBits
2730	&& GCPhysLast < UINT32_C(0xe0000000))
2731	{
2732	/*
2733	* Dynamic chunks.
2734	*/
2735	const uint32_t cPagesInChunk = (110241024) >> PAGE_SHIFT;
2736	AssertLogRelMsgReturn(cPages % cPagesInChunk == 0,
2737	("cPages=%#x cPagesInChunk=%#x\n", cPages, cPagesInChunk, pRam->GCPhys, pRam->pszDesc),
2738	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2739
2740	for (uint32_t iPage = 0; iPage < cPages; /* incremented by inner loop */ )
2741	{
2742	uint8_t fPresent;
2743	rc = SSMR3GetU8(pSSM, &fPresent);
2744	AssertLogRelMsgRCReturn(rc, ("rc=%Rrc iPage=%#x GCPhys=%#x %s\n", rc, iPage, pRam->GCPhys, pRam->pszDesc), rc);
2745	AssertLogRelMsgReturn(fPresent == (uint8_t)true \|\| fPresent == (uint8_t)false,
2746	("fPresent=%#x iPage=%#x GCPhys=%#x %s\n", fPresent, iPage, pRam->GCPhys, pRam->pszDesc),
2747	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2748
2749	for (uint32_t iChunkPage = 0; iChunkPage < cPagesInChunk; iChunkPage++, iPage++)
2750	{
2751	RTGCPHYS const GCPhysPage = ((RTGCPHYS)iPage << PAGE_SHIFT) + pRam->GCPhys;
2752	PPGMPAGE pPage = &pRam->aPages[iPage];
2753	if (fPresent)
2754	{
2755	if (PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_MMIO)
2756	rc = pgmR3LoadPageToDevNull(pSSM);
2757	else
2758	rc = pgmR3LoadPageBits(pVM, pSSM, PGMPAGETYPE_INVALID, pPage, GCPhysPage, pRam);
2759	}
2760	else
2761	rc = pgmR3LoadPageZero(pVM, PGMPAGETYPE_INVALID, pPage, GCPhysPage, pRam);
2762	AssertLogRelMsgRCReturn(rc, ("rc=%Rrc iPage=%#x GCPhysPage=%#x %s\n", rc, iPage, GCPhysPage, pRam->pszDesc), rc);
2763	}
2764	}
2765	}
2766	else if (pRam->pvR3)
2767	{
2768	/*
2769	* MMIO2.
2770	*/
2771	AssertLogRelMsgReturn((fFlags & 0x0f) == RT_BIT(3) /MM_RAM_FLAGS_MMIO2/,
2772	("fFlags=%#x GCPhys=%#x %s\n", fFlags, pRam->GCPhys, pRam->pszDesc),
2773	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2774	AssertLogRelMsgReturn(pRam->pvR3,
2775	("GCPhys=%#x %s\n", pRam->GCPhys, pRam->pszDesc),
2776	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2777
2778	rc = SSMR3GetMem(pSSM, pRam->pvR3, pRam->cb);
2779	AssertLogRelMsgRCReturn(rc, ("GCPhys=%#x %s\n", pRam->GCPhys, pRam->pszDesc), rc);
2780	}
2781	else if (GCPhysLast < UINT32_C(0xfff80000))
2782	{
2783	/*
2784	* PCI MMIO, no pages saved.
2785	*/
2786	}
2787	else
2788	{
2789	/*
2790	* Load the 0xfff80000..0xffffffff BIOS range.
2791	* It starts with X reserved pages that we have to skip over since
2792	* the RAMRANGE create by the new code won't include those.
2793	*/
2794	AssertLogRelMsgReturn( !(fFlags & RT_BIT(3) /MM_RAM_FLAGS_MMIO2/)
2795	&& (fFlags & RT_BIT(0) /MM_RAM_FLAGS_RESERVED/),
2796	("fFlags=%#x GCPhys=%#x %s\n", fFlags, pRam->GCPhys, pRam->pszDesc),
2797	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2798	AssertLogRelMsgReturn(GCPhys == UINT32_C(0xfff80000),
2799	("GCPhys=%RGp pRamRange{GCPhys=%#x %s}\n", GCPhys, pRam->GCPhys, pRam->pszDesc),
2800	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2801
2802	/* Skip wasted reserved pages before the ROM. */
2803	while (GCPhys < pRam->GCPhys)
2804	{
2805	rc = pgmR3LoadPageToDevNull(pSSM);
2806	GCPhys += PAGE_SIZE;
2807	}
2808
2809	/* Load the bios pages. */
2810	cPages = pRam->cb >> PAGE_SHIFT;
2811	for (uint32_t iPage = 0; iPage < cPages; iPage++)
2812	{
2813	RTGCPHYS const GCPhysPage = ((RTGCPHYS)iPage << PAGE_SHIFT) + pRam->GCPhys;
2814	PPGMPAGE pPage = &pRam->aPages[iPage];
2815
2816	AssertLogRelMsgReturn(PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_ROM,
2817	("GCPhys=%RGp pPage=%R[pgmpage]\n", GCPhys, GCPhys),
2818	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2819	rc = pgmR3LoadPageBits(pVM, pSSM, PGMPAGETYPE_ROM, pPage, GCPhysPage, pRam);
2820	AssertLogRelMsgRCReturn(rc, ("rc=%Rrc iPage=%#x GCPhys=%#x %s\n", rc, iPage, pRam->GCPhys, pRam->pszDesc), rc);
2821	}
2822	}
2823	}
2824	}
2825
2826	return rc;
2827	}
2828
2829
2830	/**
2831	* Execute state load operation.
2832	*
2833	* @returns VBox status code.
2834	* @param pVM VM Handle.
2835	* @param pSSM SSM operation handle.
2836	* @param u32Version Data layout version.
2837	*/
2838	static DECLCALLBACK(int) pgmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version)
2839	{
2840	int rc;
2841	PPGM pPGM = &pVM->pgm.s;
2842
2843	/*
2844	* Validate version.
2845	*/
2846	if ( u32Version != PGM_SAVED_STATE_VERSION
2847	&& u32Version != PGM_SAVED_STATE_VERSION_RR_DESC
2848	&& u32Version != PGM_SAVED_STATE_VERSION_OLD_PHYS_CODE)
2849	{
2850	AssertMsgFailed(("pgmR3Load: Invalid version u32Version=%d (current %d)!\n", u32Version, PGM_SAVED_STATE_VERSION));
2851	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
2852	}
2853
2854	/*
2855	* Call the reset function to make sure all the memory is cleared.
2856	*/
2857	PGMR3Reset(pVM);
2858
2859	/*
2860	* Do the loading while owning the lock because a bunch of the functions
2861	* we're using requires this.
2862	*/
2863	pgmLock(pVM);
2864	rc = pgmR3LoadLocked(pVM, pSSM, u32Version);
2865	pgmUnlock(pVM);
2866	if (RT_SUCCESS(rc))
2867	{
2868	/*
2869	* We require a full resync now.
2870	*/
2871	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3_NON_GLOBAL);
2872	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
2873	pPGM->fSyncFlags \|= PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL;
2874	pPGM->fPhysCacheFlushPending = true;
2875	pgmR3HandlerPhysicalUpdateAll(pVM);
2876
2877	/*
2878	* Change the paging mode.
2879	*/
2880	rc = PGMR3ChangeMode(pVM, pPGM->enmGuestMode);
2881
2882	/* Restore pVM->pgm.s.GCPhysCR3. */
2883	Assert(pVM->pgm.s.GCPhysCR3 == NIL_RTGCPHYS);
2884	RTGCPHYS GCPhysCR3 = CPUMGetGuestCR3(pVM);
2885	if ( pVM->pgm.s.enmGuestMode == PGMMODE_PAE
2886	\|\| pVM->pgm.s.enmGuestMode == PGMMODE_PAE_NX
2887	\|\| pVM->pgm.s.enmGuestMode == PGMMODE_AMD64
2888	\|\| pVM->pgm.s.enmGuestMode == PGMMODE_AMD64_NX)
2889	GCPhysCR3 = (GCPhysCR3 & X86_CR3_PAE_PAGE_MASK);
2890	else
2891	GCPhysCR3 = (GCPhysCR3 & X86_CR3_PAGE_MASK);
2892	pVM->pgm.s.GCPhysCR3 = GCPhysCR3;
2893	}
2894
2895	return rc;
2896	}
2897
2898
2899	/**
2900	* Show paging mode.
2901	*
2902	* @param pVM VM Handle.
2903	* @param pHlp The info helpers.
2904	* @param pszArgs "all" (default), "guest", "shadow" or "host".
2905	*/
2906	static DECLCALLBACK(void) pgmR3InfoMode(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2907	{
2908	/* digest argument. */
2909	bool fGuest, fShadow, fHost;
2910	if (pszArgs)
2911	pszArgs = RTStrStripL(pszArgs);
2912	if (!pszArgs \|\| !*pszArgs \|\| strstr(pszArgs, "all"))
2913	fShadow = fHost = fGuest = true;
2914	else
2915	{
2916	fShadow = fHost = fGuest = false;
2917	if (strstr(pszArgs, "guest"))
2918	fGuest = true;
2919	if (strstr(pszArgs, "shadow"))
2920	fShadow = true;
2921	if (strstr(pszArgs, "host"))
2922	fHost = true;
2923	}
2924
2925	/* print info. */
2926	if (fGuest)
2927	pHlp->pfnPrintf(pHlp, "Guest paging mode: %s, changed %RU64 times, A20 %s\n",
2928	PGMGetModeName(pVM->pgm.s.enmGuestMode), pVM->pgm.s.cGuestModeChanges.c,
2929	pVM->pgm.s.fA20Enabled ? "enabled" : "disabled");
2930	if (fShadow)
2931	pHlp->pfnPrintf(pHlp, "Shadow paging mode: %s\n", PGMGetModeName(pVM->pgm.s.enmShadowMode));
2932	if (fHost)
2933	{
2934	const char *psz;
2935	switch (pVM->pgm.s.enmHostMode)
2936	{
2937	case SUPPAGINGMODE_INVALID: psz = "invalid"; break;
2938	case SUPPAGINGMODE_32_BIT: psz = "32-bit"; break;
2939	case SUPPAGINGMODE_32_BIT_GLOBAL: psz = "32-bit+G"; break;
2940	case SUPPAGINGMODE_PAE: psz = "PAE"; break;
2941	case SUPPAGINGMODE_PAE_GLOBAL: psz = "PAE+G"; break;
2942	case SUPPAGINGMODE_PAE_NX: psz = "PAE+NX"; break;
2943	case SUPPAGINGMODE_PAE_GLOBAL_NX: psz = "PAE+G+NX"; break;
2944	case SUPPAGINGMODE_AMD64: psz = "AMD64"; break;
2945	case SUPPAGINGMODE_AMD64_GLOBAL: psz = "AMD64+G"; break;
2946	case SUPPAGINGMODE_AMD64_NX: psz = "AMD64+NX"; break;
2947	case SUPPAGINGMODE_AMD64_GLOBAL_NX: psz = "AMD64+G+NX"; break;
2948	default: psz = "unknown"; break;
2949	}
2950	pHlp->pfnPrintf(pHlp, "Host paging mode: %s\n", psz);
2951	}
2952	}
2953
2954
2955	/**
2956	* Dump registered MMIO ranges to the log.
2957	*
2958	* @param pVM VM Handle.
2959	* @param pHlp The info helpers.
2960	* @param pszArgs Arguments, ignored.
2961	*/
2962	static DECLCALLBACK(void) pgmR3PhysInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2963	{
2964	NOREF(pszArgs);
2965	pHlp->pfnPrintf(pHlp,
2966	"RAM ranges (pVM=%p)\n"
2967	"%.s %.s\n",
2968	pVM,
2969	sizeof(RTGCPHYS) * 4 + 1, "GC Phys Range ",
2970	sizeof(RTHCPTR) * 2, "pvHC ");
2971
2972	for (PPGMRAMRANGE pCur = pVM->pgm.s.pRamRangesR3; pCur; pCur = pCur->pNextR3)
2973	pHlp->pfnPrintf(pHlp,
2974	"%RGp-%RGp %RHv %s\n",
2975	pCur->GCPhys,
2976	pCur->GCPhysLast,
2977	pCur->pvR3,
2978	pCur->pszDesc);
2979	}
2980
2981	/**
2982	* Dump the page directory to the log.
2983	*
2984	* @param pVM VM Handle.
2985	* @param pHlp The info helpers.
2986	* @param pszArgs Arguments, ignored.
2987	*/
2988	static DECLCALLBACK(void) pgmR3InfoCr3(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2989	{
2990	/** @todo fix this! Convert the PGMR3DumpHierarchyHC functions to do guest stuff. */
2991	/* Big pages supported? */
2992	const bool fPSE = !!(CPUMGetGuestCR4(pVM) & X86_CR4_PSE);
2993
2994	/* Global pages supported? */
2995	const bool fPGE = !!(CPUMGetGuestCR4(pVM) & X86_CR4_PGE);
2996
2997	NOREF(pszArgs);
2998
2999	/*
3000	* Get page directory addresses.
3001	*/
3002	PX86PD pPDSrc = pgmGstGet32bitPDPtr(&pVM->pgm.s);
3003	Assert(pPDSrc);
3004	Assert(PGMPhysGCPhys2R3PtrAssert(pVM, (RTGCPHYS)(CPUMGetGuestCR3(pVM) & X86_CR3_PAGE_MASK), sizeof(*pPDSrc)) == pPDSrc);
3005
3006	/*
3007	* Iterate the page directory.
3008	*/
3009	for (unsigned iPD = 0; iPD < RT_ELEMENTS(pPDSrc->a); iPD++)
3010	{
3011	X86PDE PdeSrc = pPDSrc->a[iPD];
3012	if (PdeSrc.n.u1Present)
3013	{
3014	if (PdeSrc.b.u1Size && fPSE)
3015	pHlp->pfnPrintf(pHlp,
3016	"%04X - %RGp P=%d U=%d RW=%d G=%d - BIG\n",
3017	iPD,
3018	pgmGstGet4MBPhysPage(&pVM->pgm.s, PdeSrc),
3019	PdeSrc.b.u1Present, PdeSrc.b.u1User, PdeSrc.b.u1Write, PdeSrc.b.u1Global && fPGE);
3020	else
3021	pHlp->pfnPrintf(pHlp,
3022	"%04X - %RGp P=%d U=%d RW=%d [G=%d]\n",
3023	iPD,
3024	(RTGCPHYS)(PdeSrc.u & X86_PDE_PG_MASK),
3025	PdeSrc.n.u1Present, PdeSrc.n.u1User, PdeSrc.n.u1Write, PdeSrc.b.u1Global && fPGE);
3026	}
3027	}
3028	}
3029
3030
3031	/**
3032	* Serivce a VMMCALLHOST_PGM_LOCK call.
3033	*
3034	* @returns VBox status code.
3035	* @param pVM The VM handle.
3036	*/
3037	VMMR3DECL(int) PGMR3LockCall(PVM pVM)
3038	{
3039	int rc = PDMR3CritSectEnterEx(&pVM->pgm.s.CritSect, true /* fHostCall */);
3040	AssertRC(rc);
3041	return rc;
3042	}
3043
3044
3045	/**
3046	* Converts a PGMMODE value to a PGM_TYPE_* \#define.
3047	*
3048	* @returns PGM_TYPE_*.
3049	* @param pgmMode The mode value to convert.
3050	*/
3051	DECLINLINE(unsigned) pgmModeToType(PGMMODE pgmMode)
3052	{
3053	switch (pgmMode)
3054	{
3055	case PGMMODE_REAL: return PGM_TYPE_REAL;
3056	case PGMMODE_PROTECTED: return PGM_TYPE_PROT;
3057	case PGMMODE_32_BIT: return PGM_TYPE_32BIT;
3058	case PGMMODE_PAE:
3059	case PGMMODE_PAE_NX: return PGM_TYPE_PAE;
3060	case PGMMODE_AMD64:
3061	case PGMMODE_AMD64_NX: return PGM_TYPE_AMD64;
3062	case PGMMODE_NESTED: return PGM_TYPE_NESTED;
3063	case PGMMODE_EPT: return PGM_TYPE_EPT;
3064	default:
3065	AssertFatalMsgFailed(("pgmMode=%d\n", pgmMode));
3066	}
3067	}
3068
3069
3070	/**
3071	* Gets the index into the paging mode data array of a SHW+GST mode.
3072	*
3073	* @returns PGM::paPagingData index.
3074	* @param uShwType The shadow paging mode type.
3075	* @param uGstType The guest paging mode type.
3076	*/
3077	DECLINLINE(unsigned) pgmModeDataIndex(unsigned uShwType, unsigned uGstType)
3078	{
3079	Assert(uShwType >= PGM_TYPE_32BIT && uShwType <= PGM_TYPE_MAX);
3080	Assert(uGstType >= PGM_TYPE_REAL && uGstType <= PGM_TYPE_AMD64);
3081	return (uShwType - PGM_TYPE_32BIT) * (PGM_TYPE_AMD64 - PGM_TYPE_REAL + 1)
3082	+ (uGstType - PGM_TYPE_REAL);
3083	}
3084
3085
3086	/**
3087	* Gets the index into the paging mode data array of a SHW+GST mode.
3088	*
3089	* @returns PGM::paPagingData index.
3090	* @param enmShw The shadow paging mode.
3091	* @param enmGst The guest paging mode.
3092	*/
3093	DECLINLINE(unsigned) pgmModeDataIndexByMode(PGMMODE enmShw, PGMMODE enmGst)
3094	{
3095	Assert(enmShw >= PGMMODE_32_BIT && enmShw <= PGMMODE_MAX);
3096	Assert(enmGst > PGMMODE_INVALID && enmGst < PGMMODE_MAX);
3097	return pgmModeDataIndex(pgmModeToType(enmShw), pgmModeToType(enmGst));
3098	}
3099
3100
3101	/**
3102	* Calculates the max data index.
3103	* @returns The number of entries in the paging data array.
3104	*/
3105	DECLINLINE(unsigned) pgmModeDataMaxIndex(void)
3106	{
3107	return pgmModeDataIndex(PGM_TYPE_MAX, PGM_TYPE_AMD64) + 1;
3108	}
3109
3110
3111	/**
3112	* Initializes the paging mode data kept in PGM::paModeData.
3113	*
3114	* @param pVM The VM handle.
3115	* @param fResolveGCAndR0 Indicate whether or not GC and Ring-0 symbols can be resolved now.
3116	* This is used early in the init process to avoid trouble with PDM
3117	* not being initialized yet.
3118	*/
3119	static int pgmR3ModeDataInit(PVM pVM, bool fResolveGCAndR0)
3120	{
3121	PPGMMODEDATA pModeData;
3122	int rc;
3123
3124	/*
3125	* Allocate the array on the first call.
3126	*/
3127	if (!pVM->pgm.s.paModeData)
3128	{
3129	pVM->pgm.s.paModeData = (PPGMMODEDATA)MMR3HeapAllocZ(pVM, MM_TAG_PGM, sizeof(PGMMODEDATA) * pgmModeDataMaxIndex());
3130	AssertReturn(pVM->pgm.s.paModeData, VERR_NO_MEMORY);
3131	}
3132
3133	/*
3134	* Initialize the array entries.
3135	*/
3136	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_32BIT, PGM_TYPE_REAL)];
3137	pModeData->uShwType = PGM_TYPE_32BIT;
3138	pModeData->uGstType = PGM_TYPE_REAL;
3139	rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3140	rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3141	rc = PGM_BTH_NAME_32BIT_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3142
3143	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_32BIT, PGMMODE_PROTECTED)];
3144	pModeData->uShwType = PGM_TYPE_32BIT;
3145	pModeData->uGstType = PGM_TYPE_PROT;
3146	rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3147	rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3148	rc = PGM_BTH_NAME_32BIT_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3149
3150	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_32BIT, PGM_TYPE_32BIT)];
3151	pModeData->uShwType = PGM_TYPE_32BIT;
3152	pModeData->uGstType = PGM_TYPE_32BIT;
3153	rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3154	rc = PGM_GST_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3155	rc = PGM_BTH_NAME_32BIT_32BIT(InitData)(pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3156
3157	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_REAL)];
3158	pModeData->uShwType = PGM_TYPE_PAE;
3159	pModeData->uGstType = PGM_TYPE_REAL;
3160	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3161	rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3162	rc = PGM_BTH_NAME_PAE_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3163
3164	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_PROT)];
3165	pModeData->uShwType = PGM_TYPE_PAE;
3166	pModeData->uGstType = PGM_TYPE_PROT;
3167	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3168	rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3169	rc = PGM_BTH_NAME_PAE_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3170
3171	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_32BIT)];
3172	pModeData->uShwType = PGM_TYPE_PAE;
3173	pModeData->uGstType = PGM_TYPE_32BIT;
3174	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3175	rc = PGM_GST_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3176	rc = PGM_BTH_NAME_PAE_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3177
3178	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_PAE)];
3179	pModeData->uShwType = PGM_TYPE_PAE;
3180	pModeData->uGstType = PGM_TYPE_PAE;
3181	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3182	rc = PGM_GST_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3183	rc = PGM_BTH_NAME_PAE_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3184
3185	#ifdef VBOX_WITH_64_BITS_GUESTS
3186	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_AMD64, PGM_TYPE_AMD64)];
3187	pModeData->uShwType = PGM_TYPE_AMD64;
3188	pModeData->uGstType = PGM_TYPE_AMD64;
3189	rc = PGM_SHW_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3190	rc = PGM_GST_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3191	rc = PGM_BTH_NAME_AMD64_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3192	#endif
3193
3194	/* The nested paging mode. */
3195	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_REAL)];
3196	pModeData->uShwType = PGM_TYPE_NESTED;
3197	pModeData->uGstType = PGM_TYPE_REAL;
3198	rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3199	rc = PGM_BTH_NAME_NESTED_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3200
3201	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGMMODE_PROTECTED)];
3202	pModeData->uShwType = PGM_TYPE_NESTED;
3203	pModeData->uGstType = PGM_TYPE_PROT;
3204	rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3205	rc = PGM_BTH_NAME_NESTED_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3206
3207	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_32BIT)];
3208	pModeData->uShwType = PGM_TYPE_NESTED;
3209	pModeData->uGstType = PGM_TYPE_32BIT;
3210	rc = PGM_GST_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3211	rc = PGM_BTH_NAME_NESTED_32BIT(InitData)(pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3212
3213	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_PAE)];
3214	pModeData->uShwType = PGM_TYPE_NESTED;
3215	pModeData->uGstType = PGM_TYPE_PAE;
3216	rc = PGM_GST_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3217	rc = PGM_BTH_NAME_NESTED_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3218
3219	#ifdef VBOX_WITH_64_BITS_GUESTS
3220	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_AMD64)];
3221	pModeData->uShwType = PGM_TYPE_NESTED;
3222	pModeData->uGstType = PGM_TYPE_AMD64;
3223	rc = PGM_GST_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3224	rc = PGM_BTH_NAME_NESTED_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3225	#endif
3226
3227	/* The shadow part of the nested callback mode depends on the host paging mode (AMD-V only). */
3228	switch (pVM->pgm.s.enmHostMode)
3229	{
3230	#if HC_ARCH_BITS == 32
3231	case SUPPAGINGMODE_32_BIT:
3232	case SUPPAGINGMODE_32_BIT_GLOBAL:
3233	for (unsigned i = PGM_TYPE_REAL; i <= PGM_TYPE_PAE; i++)
3234	{
3235	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, i)];
3236	rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3237	}
3238	# ifdef VBOX_WITH_64_BITS_GUESTS
3239	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_AMD64)];
3240	rc = PGM_SHW_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3241	# endif
3242	break;
3243
3244	case SUPPAGINGMODE_PAE:
3245	case SUPPAGINGMODE_PAE_NX:
3246	case SUPPAGINGMODE_PAE_GLOBAL:
3247	case SUPPAGINGMODE_PAE_GLOBAL_NX:
3248	for (unsigned i = PGM_TYPE_REAL; i <= PGM_TYPE_PAE; i++)
3249	{
3250	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, i)];
3251	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3252	}
3253	# ifdef VBOX_WITH_64_BITS_GUESTS
3254	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_AMD64)];
3255	rc = PGM_SHW_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3256	# endif
3257	break;
3258	#endif /* HC_ARCH_BITS == 32 */
3259
3260	#if HC_ARCH_BITS == 64 \|\| defined(RT_OS_DARWIN)
3261	case SUPPAGINGMODE_AMD64:
3262	case SUPPAGINGMODE_AMD64_GLOBAL:
3263	case SUPPAGINGMODE_AMD64_NX:
3264	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
3265	# ifdef VBOX_WITH_64_BITS_GUESTS
3266	for (unsigned i = PGM_TYPE_REAL; i <= PGM_TYPE_AMD64; i++)
3267	# else
3268	for (unsigned i = PGM_TYPE_REAL; i <= PGM_TYPE_PAE; i++)
3269	# endif
3270	{
3271	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, i)];
3272	rc = PGM_SHW_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3273	}
3274	break;
3275	#endif /* HC_ARCH_BITS == 64 \|\| RT_OS_DARWIN */
3276
3277	default:
3278	AssertFailed();
3279	break;
3280	}
3281
3282	/* Extended paging (EPT) / Intel VT-x */
3283	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_REAL)];
3284	pModeData->uShwType = PGM_TYPE_EPT;
3285	pModeData->uGstType = PGM_TYPE_REAL;
3286	rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3287	rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3288	rc = PGM_BTH_NAME_EPT_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3289
3290	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_PROT)];
3291	pModeData->uShwType = PGM_TYPE_EPT;
3292	pModeData->uGstType = PGM_TYPE_PROT;
3293	rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3294	rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3295	rc = PGM_BTH_NAME_EPT_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3296
3297	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_32BIT)];
3298	pModeData->uShwType = PGM_TYPE_EPT;
3299	pModeData->uGstType = PGM_TYPE_32BIT;
3300	rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3301	rc = PGM_GST_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3302	rc = PGM_BTH_NAME_EPT_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3303
3304	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_PAE)];
3305	pModeData->uShwType = PGM_TYPE_EPT;
3306	pModeData->uGstType = PGM_TYPE_PAE;
3307	rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3308	rc = PGM_GST_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3309	rc = PGM_BTH_NAME_EPT_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3310
3311	#ifdef VBOX_WITH_64_BITS_GUESTS
3312	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_AMD64)];
3313	pModeData->uShwType = PGM_TYPE_EPT;
3314	pModeData->uGstType = PGM_TYPE_AMD64;
3315	rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3316	rc = PGM_GST_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3317	rc = PGM_BTH_NAME_EPT_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3318	#endif
3319	return VINF_SUCCESS;
3320	}
3321
3322
3323	/**
3324	* Switch to different (or relocated in the relocate case) mode data.
3325	*
3326	* @param pVM The VM handle.
3327	* @param enmShw The the shadow paging mode.
3328	* @param enmGst The the guest paging mode.
3329	*/
3330	static void pgmR3ModeDataSwitch(PVM pVM, PGMMODE enmShw, PGMMODE enmGst)
3331	{
3332	PPGMMODEDATA pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndexByMode(enmShw, enmGst)];
3333
3334	Assert(pModeData->uGstType == pgmModeToType(enmGst));
3335	Assert(pModeData->uShwType == pgmModeToType(enmShw));
3336
3337	/* shadow */
3338	pVM->pgm.s.pfnR3ShwRelocate = pModeData->pfnR3ShwRelocate;
3339	pVM->pgm.s.pfnR3ShwExit = pModeData->pfnR3ShwExit;
3340	pVM->pgm.s.pfnR3ShwGetPage = pModeData->pfnR3ShwGetPage;
3341	Assert(pVM->pgm.s.pfnR3ShwGetPage);
3342	pVM->pgm.s.pfnR3ShwModifyPage = pModeData->pfnR3ShwModifyPage;
3343
3344	pVM->pgm.s.pfnRCShwGetPage = pModeData->pfnRCShwGetPage;
3345	pVM->pgm.s.pfnRCShwModifyPage = pModeData->pfnRCShwModifyPage;
3346
3347	pVM->pgm.s.pfnR0ShwGetPage = pModeData->pfnR0ShwGetPage;
3348	pVM->pgm.s.pfnR0ShwModifyPage = pModeData->pfnR0ShwModifyPage;
3349
3350
3351	/* guest */
3352	pVM->pgm.s.pfnR3GstRelocate = pModeData->pfnR3GstRelocate;
3353	pVM->pgm.s.pfnR3GstExit = pModeData->pfnR3GstExit;
3354	pVM->pgm.s.pfnR3GstGetPage = pModeData->pfnR3GstGetPage;
3355	Assert(pVM->pgm.s.pfnR3GstGetPage);
3356	pVM->pgm.s.pfnR3GstModifyPage = pModeData->pfnR3GstModifyPage;
3357	pVM->pgm.s.pfnR3GstGetPDE = pModeData->pfnR3GstGetPDE;
3358	pVM->pgm.s.pfnRCGstGetPage = pModeData->pfnRCGstGetPage;
3359	pVM->pgm.s.pfnRCGstModifyPage = pModeData->pfnRCGstModifyPage;
3360	pVM->pgm.s.pfnRCGstGetPDE = pModeData->pfnRCGstGetPDE;
3361	pVM->pgm.s.pfnR0GstGetPage = pModeData->pfnR0GstGetPage;
3362	pVM->pgm.s.pfnR0GstModifyPage = pModeData->pfnR0GstModifyPage;
3363	pVM->pgm.s.pfnR0GstGetPDE = pModeData->pfnR0GstGetPDE;
3364
3365	/* both */
3366	pVM->pgm.s.pfnR3BthRelocate = pModeData->pfnR3BthRelocate;
3367	pVM->pgm.s.pfnR3BthInvalidatePage = pModeData->pfnR3BthInvalidatePage;
3368	pVM->pgm.s.pfnR3BthSyncCR3 = pModeData->pfnR3BthSyncCR3;
3369	Assert(pVM->pgm.s.pfnR3BthSyncCR3);
3370	pVM->pgm.s.pfnR3BthSyncPage = pModeData->pfnR3BthSyncPage;
3371	pVM->pgm.s.pfnR3BthPrefetchPage = pModeData->pfnR3BthPrefetchPage;
3372	pVM->pgm.s.pfnR3BthVerifyAccessSyncPage = pModeData->pfnR3BthVerifyAccessSyncPage;
3373	#ifdef VBOX_STRICT
3374	pVM->pgm.s.pfnR3BthAssertCR3 = pModeData->pfnR3BthAssertCR3;
3375	#endif
3376	pVM->pgm.s.pfnR3BthMapCR3 = pModeData->pfnR3BthMapCR3;
3377	pVM->pgm.s.pfnR3BthUnmapCR3 = pModeData->pfnR3BthUnmapCR3;
3378
3379	pVM->pgm.s.pfnRCBthTrap0eHandler = pModeData->pfnRCBthTrap0eHandler;
3380	pVM->pgm.s.pfnRCBthInvalidatePage = pModeData->pfnRCBthInvalidatePage;
3381	pVM->pgm.s.pfnRCBthSyncCR3 = pModeData->pfnRCBthSyncCR3;
3382	pVM->pgm.s.pfnRCBthSyncPage = pModeData->pfnRCBthSyncPage;
3383	pVM->pgm.s.pfnRCBthPrefetchPage = pModeData->pfnRCBthPrefetchPage;
3384	pVM->pgm.s.pfnRCBthVerifyAccessSyncPage = pModeData->pfnRCBthVerifyAccessSyncPage;
3385	#ifdef VBOX_STRICT
3386	pVM->pgm.s.pfnRCBthAssertCR3 = pModeData->pfnRCBthAssertCR3;
3387	#endif
3388	pVM->pgm.s.pfnRCBthMapCR3 = pModeData->pfnRCBthMapCR3;
3389	pVM->pgm.s.pfnRCBthUnmapCR3 = pModeData->pfnRCBthUnmapCR3;
3390
3391	pVM->pgm.s.pfnR0BthTrap0eHandler = pModeData->pfnR0BthTrap0eHandler;
3392	pVM->pgm.s.pfnR0BthInvalidatePage = pModeData->pfnR0BthInvalidatePage;
3393	pVM->pgm.s.pfnR0BthSyncCR3 = pModeData->pfnR0BthSyncCR3;
3394	pVM->pgm.s.pfnR0BthSyncPage = pModeData->pfnR0BthSyncPage;
3395	pVM->pgm.s.pfnR0BthPrefetchPage = pModeData->pfnR0BthPrefetchPage;
3396	pVM->pgm.s.pfnR0BthVerifyAccessSyncPage = pModeData->pfnR0BthVerifyAccessSyncPage;
3397	#ifdef VBOX_STRICT
3398	pVM->pgm.s.pfnR0BthAssertCR3 = pModeData->pfnR0BthAssertCR3;
3399	#endif
3400	pVM->pgm.s.pfnR0BthMapCR3 = pModeData->pfnR0BthMapCR3;
3401	pVM->pgm.s.pfnR0BthUnmapCR3 = pModeData->pfnR0BthUnmapCR3;
3402	}
3403
3404
3405	/**
3406	* Calculates the shadow paging mode.
3407	*
3408	* @returns The shadow paging mode.
3409	* @param pVM VM handle.
3410	* @param enmGuestMode The guest mode.
3411	* @param enmHostMode The host mode.
3412	* @param enmShadowMode The current shadow mode.
3413	* @param penmSwitcher Where to store the switcher to use.
3414	* VMMSWITCHER_INVALID means no change.
3415	*/
3416	static PGMMODE pgmR3CalcShadowMode(PVM pVM, PGMMODE enmGuestMode, SUPPAGINGMODE enmHostMode, PGMMODE enmShadowMode, VMMSWITCHER *penmSwitcher)
3417	{
3418	VMMSWITCHER enmSwitcher = VMMSWITCHER_INVALID;
3419	switch (enmGuestMode)
3420	{
3421	/*
3422	* When switching to real or protected mode we don't change
3423	* anything since it's likely that we'll switch back pretty soon.
3424	*
3425	* During pgmR3InitPaging we'll end up here with PGMMODE_INVALID
3426	* and is supposed to determine which shadow paging and switcher to
3427	* use during init.
3428	*/
3429	case PGMMODE_REAL:
3430	case PGMMODE_PROTECTED:
3431	if ( enmShadowMode != PGMMODE_INVALID
3432	&& !HWACCMIsEnabled(pVM) /* always switch in hwaccm mode! */)
3433	break; /* (no change) */
3434
3435	switch (enmHostMode)
3436	{
3437	case SUPPAGINGMODE_32_BIT:
3438	case SUPPAGINGMODE_32_BIT_GLOBAL:
3439	enmShadowMode = PGMMODE_32_BIT;
3440	enmSwitcher = VMMSWITCHER_32_TO_32;
3441	break;
3442
3443	case SUPPAGINGMODE_PAE:
3444	case SUPPAGINGMODE_PAE_NX:
3445	case SUPPAGINGMODE_PAE_GLOBAL:
3446	case SUPPAGINGMODE_PAE_GLOBAL_NX:
3447	enmShadowMode = PGMMODE_PAE;
3448	enmSwitcher = VMMSWITCHER_PAE_TO_PAE;
3449	#ifdef DEBUG_bird
3450	if (RTEnvExist("VBOX_32BIT"))
3451	{
3452	enmShadowMode = PGMMODE_32_BIT;
3453	enmSwitcher = VMMSWITCHER_PAE_TO_32;
3454	}
3455	#endif
3456	break;
3457
3458	case SUPPAGINGMODE_AMD64:
3459	case SUPPAGINGMODE_AMD64_GLOBAL:
3460	case SUPPAGINGMODE_AMD64_NX:
3461	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
3462	enmShadowMode = PGMMODE_PAE;
3463	enmSwitcher = VMMSWITCHER_AMD64_TO_PAE;
3464	#ifdef DEBUG_bird
3465	if (RTEnvExist("VBOX_32BIT"))
3466	{
3467	enmShadowMode = PGMMODE_32_BIT;
3468	enmSwitcher = VMMSWITCHER_AMD64_TO_32;
3469	}
3470	#endif
3471	break;
3472
3473	default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
3474	}
3475	break;
3476
3477	case PGMMODE_32_BIT:
3478	switch (enmHostMode)
3479	{
3480	case SUPPAGINGMODE_32_BIT:
3481	case SUPPAGINGMODE_32_BIT_GLOBAL:
3482	enmShadowMode = PGMMODE_32_BIT;
3483	enmSwitcher = VMMSWITCHER_32_TO_32;
3484	break;
3485
3486	case SUPPAGINGMODE_PAE:
3487	case SUPPAGINGMODE_PAE_NX:
3488	case SUPPAGINGMODE_PAE_GLOBAL:
3489	case SUPPAGINGMODE_PAE_GLOBAL_NX:
3490	enmShadowMode = PGMMODE_PAE;
3491	enmSwitcher = VMMSWITCHER_PAE_TO_PAE;
3492	#ifdef DEBUG_bird
3493	if (RTEnvExist("VBOX_32BIT"))
3494	{
3495	enmShadowMode = PGMMODE_32_BIT;
3496	enmSwitcher = VMMSWITCHER_PAE_TO_32;
3497	}
3498	#endif
3499	break;
3500
3501	case SUPPAGINGMODE_AMD64:
3502	case SUPPAGINGMODE_AMD64_GLOBAL:
3503	case SUPPAGINGMODE_AMD64_NX:
3504	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
3505	enmShadowMode = PGMMODE_PAE;
3506	enmSwitcher = VMMSWITCHER_AMD64_TO_PAE;
3507	#ifdef DEBUG_bird
3508	if (RTEnvExist("VBOX_32BIT"))
3509	{
3510	enmShadowMode = PGMMODE_32_BIT;
3511	enmSwitcher = VMMSWITCHER_AMD64_TO_32;
3512	}
3513	#endif
3514	break;
3515
3516	default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
3517	}
3518	break;
3519
3520	case PGMMODE_PAE:
3521	case PGMMODE_PAE_NX: /** @todo This might require more switchers and guest+both modes. */
3522	switch (enmHostMode)
3523	{
3524	case SUPPAGINGMODE_32_BIT:
3525	case SUPPAGINGMODE_32_BIT_GLOBAL:
3526	enmShadowMode = PGMMODE_PAE;
3527	enmSwitcher = VMMSWITCHER_32_TO_PAE;
3528	break;
3529
3530	case SUPPAGINGMODE_PAE:
3531	case SUPPAGINGMODE_PAE_NX:
3532	case SUPPAGINGMODE_PAE_GLOBAL:
3533	case SUPPAGINGMODE_PAE_GLOBAL_NX:
3534	enmShadowMode = PGMMODE_PAE;
3535	enmSwitcher = VMMSWITCHER_PAE_TO_PAE;
3536	break;
3537
3538	case SUPPAGINGMODE_AMD64:
3539	case SUPPAGINGMODE_AMD64_GLOBAL:
3540	case SUPPAGINGMODE_AMD64_NX:
3541	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
3542	enmShadowMode = PGMMODE_PAE;
3543	enmSwitcher = VMMSWITCHER_AMD64_TO_PAE;
3544	break;
3545
3546	default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
3547	}
3548	break;
3549
3550	case PGMMODE_AMD64:
3551	case PGMMODE_AMD64_NX:
3552	switch (enmHostMode)
3553	{
3554	case SUPPAGINGMODE_32_BIT:
3555	case SUPPAGINGMODE_32_BIT_GLOBAL:
3556	enmShadowMode = PGMMODE_AMD64;
3557	enmSwitcher = VMMSWITCHER_32_TO_AMD64;
3558	break;
3559
3560	case SUPPAGINGMODE_PAE:
3561	case SUPPAGINGMODE_PAE_NX:
3562	case SUPPAGINGMODE_PAE_GLOBAL:
3563	case SUPPAGINGMODE_PAE_GLOBAL_NX:
3564	enmShadowMode = PGMMODE_AMD64;
3565	enmSwitcher = VMMSWITCHER_PAE_TO_AMD64;
3566	break;
3567
3568	case SUPPAGINGMODE_AMD64:
3569	case SUPPAGINGMODE_AMD64_GLOBAL:
3570	case SUPPAGINGMODE_AMD64_NX:
3571	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
3572	enmShadowMode = PGMMODE_AMD64;
3573	enmSwitcher = VMMSWITCHER_AMD64_TO_AMD64;
3574	break;
3575
3576	default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
3577	}
3578	break;
3579
3580
3581	default:
3582	AssertReleaseMsgFailed(("enmGuestMode=%d\n", enmGuestMode));
3583	return PGMMODE_INVALID;
3584	}
3585	/* Override the shadow mode is nested paging is active. */
3586	if (HWACCMIsNestedPagingActive(pVM))
3587	enmShadowMode = HWACCMGetShwPagingMode(pVM);
3588
3589	*penmSwitcher = enmSwitcher;
3590	return enmShadowMode;
3591	}
3592
3593
3594	/**
3595	* Performs the actual mode change.
3596	* This is called by PGMChangeMode and pgmR3InitPaging().
3597	*
3598	* @returns VBox status code. May suspend or power off the VM on error, but this
3599	* will trigger using FFs and not status codes.
3600	*
3601	* @param pVM VM handle.
3602	* @param enmGuestMode The new guest mode. This is assumed to be different from
3603	* the current mode.
3604	*/
3605	VMMR3DECL(int) PGMR3ChangeMode(PVM pVM, PGMMODE enmGuestMode)
3606	{
3607	Log(("PGMR3ChangeMode: Guest mode: %s -> %s\n", PGMGetModeName(pVM->pgm.s.enmGuestMode), PGMGetModeName(enmGuestMode)));
3608	STAM_REL_COUNTER_INC(&pVM->pgm.s.cGuestModeChanges);
3609
3610	/*
3611	* Calc the shadow mode and switcher.
3612	*/
3613	VMMSWITCHER enmSwitcher;
3614	PGMMODE enmShadowMode = pgmR3CalcShadowMode(pVM, enmGuestMode, pVM->pgm.s.enmHostMode, pVM->pgm.s.enmShadowMode, &enmSwitcher);
3615	if (enmSwitcher != VMMSWITCHER_INVALID)
3616	{
3617	/*
3618	* Select new switcher.
3619	*/
3620	int rc = VMMR3SelectSwitcher(pVM, enmSwitcher);
3621	if (RT_FAILURE(rc))
3622	{
3623	AssertReleaseMsgFailed(("VMMR3SelectSwitcher(%d) -> %Rrc\n", enmSwitcher, rc));
3624	return rc;
3625	}
3626	}
3627
3628	/*
3629	* Exit old mode(s).
3630	*/
3631	/* shadow */
3632	if (enmShadowMode != pVM->pgm.s.enmShadowMode)
3633	{
3634	LogFlow(("PGMR3ChangeMode: Shadow mode: %s -> %s\n", PGMGetModeName(pVM->pgm.s.enmShadowMode), PGMGetModeName(enmShadowMode)));
3635	if (PGM_SHW_PFN(Exit, pVM))
3636	{
3637	int rc = PGM_SHW_PFN(Exit, pVM)(pVM);
3638	if (RT_FAILURE(rc))
3639	{
3640	AssertMsgFailed(("Exit failed for shadow mode %d: %Rrc\n", pVM->pgm.s.enmShadowMode, rc));
3641	return rc;
3642	}
3643	}
3644
3645	}
3646	else
3647	LogFlow(("PGMR3ChangeMode: Shadow mode remains: %s\n", PGMGetModeName(pVM->pgm.s.enmShadowMode)));
3648
3649	/* guest */
3650	if (PGM_GST_PFN(Exit, pVM))
3651	{
3652	int rc = PGM_GST_PFN(Exit, pVM)(pVM);
3653	if (RT_FAILURE(rc))
3654	{
3655	AssertMsgFailed(("Exit failed for guest mode %d: %Rrc\n", pVM->pgm.s.enmGuestMode, rc));
3656	return rc;
3657	}
3658	}
3659
3660	/*
3661	* Load new paging mode data.
3662	*/
3663	pgmR3ModeDataSwitch(pVM, enmShadowMode, enmGuestMode);
3664
3665	/*
3666	* Enter new shadow mode (if changed).
3667	*/
3668	if (enmShadowMode != pVM->pgm.s.enmShadowMode)
3669	{
3670	int rc;
3671	pVM->pgm.s.enmShadowMode = enmShadowMode;
3672	switch (enmShadowMode)
3673	{
3674	case PGMMODE_32_BIT:
3675	rc = PGM_SHW_NAME_32BIT(Enter)(pVM);
3676	break;
3677	case PGMMODE_PAE:
3678	case PGMMODE_PAE_NX:
3679	rc = PGM_SHW_NAME_PAE(Enter)(pVM);
3680	break;
3681	case PGMMODE_AMD64:
3682	case PGMMODE_AMD64_NX:
3683	rc = PGM_SHW_NAME_AMD64(Enter)(pVM);
3684	break;
3685	case PGMMODE_NESTED:
3686	rc = PGM_SHW_NAME_NESTED(Enter)(pVM);
3687	break;
3688	case PGMMODE_EPT:
3689	rc = PGM_SHW_NAME_EPT(Enter)(pVM);
3690	break;
3691	case PGMMODE_REAL:
3692	case PGMMODE_PROTECTED:
3693	default:
3694	AssertReleaseMsgFailed(("enmShadowMode=%d\n", enmShadowMode));
3695	return VERR_INTERNAL_ERROR;
3696	}
3697	if (RT_FAILURE(rc))
3698	{
3699	AssertReleaseMsgFailed(("Entering enmShadowMode=%d failed: %Rrc\n", enmShadowMode, rc));
3700	pVM->pgm.s.enmShadowMode = PGMMODE_INVALID;
3701	return rc;
3702	}
3703	}
3704
3705	/*
3706	* Always flag the necessary updates
3707	*/
3708	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
3709
3710	/*
3711	* Enter the new guest and shadow+guest modes.
3712	*/
3713	int rc = -1;
3714	int rc2 = -1;
3715	RTGCPHYS GCPhysCR3 = NIL_RTGCPHYS;
3716	pVM->pgm.s.enmGuestMode = enmGuestMode;
3717	switch (enmGuestMode)
3718	{
3719	case PGMMODE_REAL:
3720	rc = PGM_GST_NAME_REAL(Enter)(pVM, NIL_RTGCPHYS);
3721	switch (pVM->pgm.s.enmShadowMode)
3722	{
3723	case PGMMODE_32_BIT:
3724	rc2 = PGM_BTH_NAME_32BIT_REAL(Enter)(pVM, NIL_RTGCPHYS);
3725	break;
3726	case PGMMODE_PAE:
3727	case PGMMODE_PAE_NX:
3728	rc2 = PGM_BTH_NAME_PAE_REAL(Enter)(pVM, NIL_RTGCPHYS);
3729	break;
3730	case PGMMODE_NESTED:
3731	rc2 = PGM_BTH_NAME_NESTED_REAL(Enter)(pVM, NIL_RTGCPHYS);
3732	break;
3733	case PGMMODE_EPT:
3734	rc2 = PGM_BTH_NAME_EPT_REAL(Enter)(pVM, NIL_RTGCPHYS);
3735	break;
3736	case PGMMODE_AMD64:
3737	case PGMMODE_AMD64_NX:
3738	AssertMsgFailed(("Should use PAE shadow mode!\n"));
3739	default: AssertFailed(); break;
3740	}
3741	break;
3742
3743	case PGMMODE_PROTECTED:
3744	rc = PGM_GST_NAME_PROT(Enter)(pVM, NIL_RTGCPHYS);
3745	switch (pVM->pgm.s.enmShadowMode)
3746	{
3747	case PGMMODE_32_BIT:
3748	rc2 = PGM_BTH_NAME_32BIT_PROT(Enter)(pVM, NIL_RTGCPHYS);
3749	break;
3750	case PGMMODE_PAE:
3751	case PGMMODE_PAE_NX:
3752	rc2 = PGM_BTH_NAME_PAE_PROT(Enter)(pVM, NIL_RTGCPHYS);
3753	break;
3754	case PGMMODE_NESTED:
3755	rc2 = PGM_BTH_NAME_NESTED_PROT(Enter)(pVM, NIL_RTGCPHYS);
3756	break;
3757	case PGMMODE_EPT:
3758	rc2 = PGM_BTH_NAME_EPT_PROT(Enter)(pVM, NIL_RTGCPHYS);
3759	break;
3760	case PGMMODE_AMD64:
3761	case PGMMODE_AMD64_NX:
3762	AssertMsgFailed(("Should use PAE shadow mode!\n"));
3763	default: AssertFailed(); break;
3764	}
3765	break;
3766
3767	case PGMMODE_32_BIT:
3768	GCPhysCR3 = CPUMGetGuestCR3(pVM) & X86_CR3_PAGE_MASK;
3769	rc = PGM_GST_NAME_32BIT(Enter)(pVM, GCPhysCR3);
3770	switch (pVM->pgm.s.enmShadowMode)
3771	{
3772	case PGMMODE_32_BIT:
3773	rc2 = PGM_BTH_NAME_32BIT_32BIT(Enter)(pVM, GCPhysCR3);
3774	break;
3775	case PGMMODE_PAE:
3776	case PGMMODE_PAE_NX:
3777	rc2 = PGM_BTH_NAME_PAE_32BIT(Enter)(pVM, GCPhysCR3);
3778	break;
3779	case PGMMODE_NESTED:
3780	rc2 = PGM_BTH_NAME_NESTED_32BIT(Enter)(pVM, GCPhysCR3);
3781	break;
3782	case PGMMODE_EPT:
3783	rc2 = PGM_BTH_NAME_EPT_32BIT(Enter)(pVM, GCPhysCR3);
3784	break;
3785	case PGMMODE_AMD64:
3786	case PGMMODE_AMD64_NX:
3787	AssertMsgFailed(("Should use PAE shadow mode!\n"));
3788	default: AssertFailed(); break;
3789	}
3790	break;
3791
3792	case PGMMODE_PAE_NX:
3793	case PGMMODE_PAE:
3794	{
3795	uint32_t u32Dummy, u32Features;
3796
3797	CPUMGetGuestCpuId(pVM, 1, &u32Dummy, &u32Dummy, &u32Dummy, &u32Features);
3798	if (!(u32Features & X86_CPUID_FEATURE_EDX_PAE))
3799	return VMSetRuntimeError(pVM, VMSETRTERR_FLAGS_FATAL, "PAEmode",
3800	N_("The guest is trying to switch to the PAE mode which is currently disabled by default in VirtualBox. PAE support can be enabled using the VM settings (General/Advanced)"));
3801
3802	GCPhysCR3 = CPUMGetGuestCR3(pVM) & X86_CR3_PAE_PAGE_MASK;
3803	rc = PGM_GST_NAME_PAE(Enter)(pVM, GCPhysCR3);
3804	switch (pVM->pgm.s.enmShadowMode)
3805	{
3806	case PGMMODE_PAE:
3807	case PGMMODE_PAE_NX:
3808	rc2 = PGM_BTH_NAME_PAE_PAE(Enter)(pVM, GCPhysCR3);
3809	break;
3810	case PGMMODE_NESTED:
3811	rc2 = PGM_BTH_NAME_NESTED_PAE(Enter)(pVM, GCPhysCR3);
3812	break;
3813	case PGMMODE_EPT:
3814	rc2 = PGM_BTH_NAME_EPT_PAE(Enter)(pVM, GCPhysCR3);
3815	break;
3816	case PGMMODE_32_BIT:
3817	case PGMMODE_AMD64:
3818	case PGMMODE_AMD64_NX:
3819	AssertMsgFailed(("Should use PAE shadow mode!\n"));
3820	default: AssertFailed(); break;
3821	}
3822	break;
3823	}
3824
3825	#ifdef VBOX_WITH_64_BITS_GUESTS
3826	case PGMMODE_AMD64_NX:
3827	case PGMMODE_AMD64:
3828	GCPhysCR3 = CPUMGetGuestCR3(pVM) & UINT64_C(0xfffffffffffff000); /** @todo define this mask! */
3829	rc = PGM_GST_NAME_AMD64(Enter)(pVM, GCPhysCR3);
3830	switch (pVM->pgm.s.enmShadowMode)
3831	{
3832	case PGMMODE_AMD64:
3833	case PGMMODE_AMD64_NX:
3834	rc2 = PGM_BTH_NAME_AMD64_AMD64(Enter)(pVM, GCPhysCR3);
3835	break;
3836	case PGMMODE_NESTED:
3837	rc2 = PGM_BTH_NAME_NESTED_AMD64(Enter)(pVM, GCPhysCR3);
3838	break;
3839	case PGMMODE_EPT:
3840	rc2 = PGM_BTH_NAME_EPT_AMD64(Enter)(pVM, GCPhysCR3);
3841	break;
3842	case PGMMODE_32_BIT:
3843	case PGMMODE_PAE:
3844	case PGMMODE_PAE_NX:
3845	AssertMsgFailed(("Should use AMD64 shadow mode!\n"));
3846	default: AssertFailed(); break;
3847	}
3848	break;
3849	#endif
3850
3851	default:
3852	AssertReleaseMsgFailed(("enmGuestMode=%d\n", enmGuestMode));
3853	rc = VERR_NOT_IMPLEMENTED;
3854	break;
3855	}
3856
3857	/* status codes. */
3858	AssertRC(rc);
3859	AssertRC(rc2);
3860	if (RT_SUCCESS(rc))
3861	{
3862	rc = rc2;
3863	if (RT_SUCCESS(rc)) /* no informational status codes. */
3864	rc = VINF_SUCCESS;
3865	}
3866
3867	/* Notify HWACCM as well. */
3868	HWACCMR3PagingModeChanged(pVM, pVM->pgm.s.enmShadowMode, pVM->pgm.s.enmGuestMode);
3869	return rc;
3870	}
3871
3872
3873	/**
3874	* Dumps a PAE shadow page table.
3875	*
3876	* @returns VBox status code (VINF_SUCCESS).
3877	* @param pVM The VM handle.
3878	* @param pPT Pointer to the page table.
3879	* @param u64Address The virtual address of the page table starts.
3880	* @param fLongMode Set if this a long mode table; clear if it's a legacy mode table.
3881	* @param cMaxDepth The maxium depth.
3882	* @param pHlp Pointer to the output functions.
3883	*/
3884	static int pgmR3DumpHierarchyHCPaePT(PVM pVM, PX86PTPAE pPT, uint64_t u64Address, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
3885	{
3886	for (unsigned i = 0; i < RT_ELEMENTS(pPT->a); i++)
3887	{
3888	X86PTEPAE Pte = pPT->a[i];
3889	if (Pte.n.u1Present)
3890	{
3891	pHlp->pfnPrintf(pHlp,
3892	fLongMode /P R S A D G WT CD AT NX 4M a p ? /
3893	? "%016llx 3 \| P %c %c %c %c %c %s %s %s %s 4K %c%c%c %016llx\n"
3894	: "%08llx 2 \| P %c %c %c %c %c %s %s %s %s 4K %c%c%c %016llx\n",
3895	u64Address + ((uint64_t)i << X86_PT_PAE_SHIFT),
3896	Pte.n.u1Write ? 'W' : 'R',
3897	Pte.n.u1User ? 'U' : 'S',
3898	Pte.n.u1Accessed ? 'A' : '-',
3899	Pte.n.u1Dirty ? 'D' : '-',
3900	Pte.n.u1Global ? 'G' : '-',
3901	Pte.n.u1WriteThru ? "WT" : "--",
3902	Pte.n.u1CacheDisable? "CD" : "--",
3903	Pte.n.u1PAT ? "AT" : "--",
3904	Pte.n.u1NoExecute ? "NX" : "--",
3905	Pte.u & PGM_PTFLAGS_TRACK_DIRTY ? 'd' : '-',
3906	Pte.u & RT_BIT(10) ? '1' : '0',
3907	Pte.u & PGM_PTFLAGS_CSAM_VALIDATED? 'v' : '-',
3908	Pte.u & X86_PTE_PAE_PG_MASK);
3909	}
3910	}
3911	return VINF_SUCCESS;
3912	}
3913
3914
3915	/**
3916	* Dumps a PAE shadow page directory table.
3917	*
3918	* @returns VBox status code (VINF_SUCCESS).
3919	* @param pVM The VM handle.
3920	* @param HCPhys The physical address of the page directory table.
3921	* @param u64Address The virtual address of the page table starts.
3922	* @param cr4 The CR4, PSE is currently used.
3923	* @param fLongMode Set if this a long mode table; clear if it's a legacy mode table.
3924	* @param cMaxDepth The maxium depth.
3925	* @param pHlp Pointer to the output functions.
3926	*/
3927	static int pgmR3DumpHierarchyHCPaePD(PVM pVM, RTHCPHYS HCPhys, uint64_t u64Address, uint32_t cr4, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
3928	{
3929	PX86PDPAE pPD = (PX86PDPAE)MMPagePhys2Page(pVM, HCPhys);
3930	if (!pPD)
3931	{
3932	pHlp->pfnPrintf(pHlp, "%0*llx error! Page directory at HCPhys=%RHp was not found in the page pool!\n",
3933	fLongMode ? 16 : 8, u64Address, HCPhys);
3934	return VERR_INVALID_PARAMETER;
3935	}
3936	const bool fBigPagesSupported = fLongMode \|\| !!(cr4 & X86_CR4_PSE);
3937
3938	int rc = VINF_SUCCESS;
3939	for (unsigned i = 0; i < RT_ELEMENTS(pPD->a); i++)
3940	{
3941	X86PDEPAE Pde = pPD->a[i];
3942	if (Pde.n.u1Present)
3943	{
3944	if (fBigPagesSupported && Pde.b.u1Size)
3945	pHlp->pfnPrintf(pHlp,
3946	fLongMode /P R S A D G WT CD AT NX 4M a p ? /
3947	? "%016llx 2 \| P %c %c %c %c %c %s %s %s %s 4M %c%c%c %016llx\n"
3948	: "%08llx 1 \| P %c %c %c %c %c %s %s %s %s 4M %c%c%c %016llx\n",
3949	u64Address + ((uint64_t)i << X86_PD_PAE_SHIFT),
3950	Pde.b.u1Write ? 'W' : 'R',
3951	Pde.b.u1User ? 'U' : 'S',
3952	Pde.b.u1Accessed ? 'A' : '-',
3953	Pde.b.u1Dirty ? 'D' : '-',
3954	Pde.b.u1Global ? 'G' : '-',
3955	Pde.b.u1WriteThru ? "WT" : "--",
3956	Pde.b.u1CacheDisable? "CD" : "--",
3957	Pde.b.u1PAT ? "AT" : "--",
3958	Pde.b.u1NoExecute ? "NX" : "--",
3959	Pde.u & RT_BIT_64(9) ? '1' : '0',
3960	Pde.u & PGM_PDFLAGS_MAPPING ? 'm' : '-',
3961	Pde.u & PGM_PDFLAGS_TRACK_DIRTY ? 'd' : '-',
3962	Pde.u & X86_PDE_PAE_PG_MASK);
3963	else
3964	{
3965	pHlp->pfnPrintf(pHlp,
3966	fLongMode /P R S A D G WT CD AT NX 4M a p ? /
3967	? "%016llx 2 \| P %c %c %c %c %c %s %s .. %s 4K %c%c%c %016llx\n"
3968	: "%08llx 1 \| P %c %c %c %c %c %s %s .. %s 4K %c%c%c %016llx\n",
3969	u64Address + ((uint64_t)i << X86_PD_PAE_SHIFT),
3970	Pde.n.u1Write ? 'W' : 'R',
3971	Pde.n.u1User ? 'U' : 'S',
3972	Pde.n.u1Accessed ? 'A' : '-',
3973	Pde.n.u1Reserved0 ? '?' : '.', /* ignored */
3974	Pde.n.u1Reserved1 ? '?' : '.', /* ignored */
3975	Pde.n.u1WriteThru ? "WT" : "--",
3976	Pde.n.u1CacheDisable? "CD" : "--",
3977	Pde.n.u1NoExecute ? "NX" : "--",
3978	Pde.u & RT_BIT_64(9) ? '1' : '0',
3979	Pde.u & PGM_PDFLAGS_MAPPING ? 'm' : '-',
3980	Pde.u & PGM_PDFLAGS_TRACK_DIRTY ? 'd' : '-',
3981	Pde.u & X86_PDE_PAE_PG_MASK);
3982	if (cMaxDepth >= 1)
3983	{
3984	/** @todo what about using the page pool for mapping PTs? */
3985	uint64_t u64AddressPT = u64Address + ((uint64_t)i << X86_PD_PAE_SHIFT);
3986	RTHCPHYS HCPhysPT = Pde.u & X86_PDE_PAE_PG_MASK;
3987	PX86PTPAE pPT = NULL;
3988	if (!(Pde.u & PGM_PDFLAGS_MAPPING))
3989	pPT = (PX86PTPAE)MMPagePhys2Page(pVM, HCPhysPT);
3990	else
3991	{
3992	for (PPGMMAPPING pMap = pVM->pgm.s.pMappingsR3; pMap; pMap = pMap->pNextR3)
3993	{
3994	uint64_t off = u64AddressPT - pMap->GCPtr;
3995	if (off < pMap->cb)
3996	{
3997	const int iPDE = (uint32_t)(off >> X86_PD_SHIFT);
3998	const int iSub = (int)((off >> X86_PD_PAE_SHIFT) & 1); /* MSC is a pain sometimes */
3999	if ((iSub ? pMap->aPTs[iPDE].HCPhysPaePT1 : pMap->aPTs[iPDE].HCPhysPaePT0) != HCPhysPT)
4000	pHlp->pfnPrintf(pHlp, "%0*llx error! Mapping error! PT %d has HCPhysPT=%RHp not %RHp is in the PD.\n",
4001	fLongMode ? 16 : 8, u64AddressPT, iPDE,
4002	iSub ? pMap->aPTs[iPDE].HCPhysPaePT1 : pMap->aPTs[iPDE].HCPhysPaePT0, HCPhysPT);
4003	pPT = &pMap->aPTs[iPDE].paPaePTsR3[iSub];
4004	}
4005	}
4006	}
4007	int rc2 = VERR_INVALID_PARAMETER;
4008	if (pPT)
4009	rc2 = pgmR3DumpHierarchyHCPaePT(pVM, pPT, u64AddressPT, fLongMode, cMaxDepth - 1, pHlp);
4010	else
4011	pHlp->pfnPrintf(pHlp, "%0*llx error! Page table at HCPhys=%RHp was not found in the page pool!\n",
4012	fLongMode ? 16 : 8, u64AddressPT, HCPhysPT);
4013	if (rc2 < rc && RT_SUCCESS(rc))
4014	rc = rc2;
4015	}
4016	}
4017	}
4018	}
4019	return rc;
4020	}
4021
4022
4023	/**
4024	* Dumps a PAE shadow page directory pointer table.
4025	*
4026	* @returns VBox status code (VINF_SUCCESS).
4027	* @param pVM The VM handle.
4028	* @param HCPhys The physical address of the page directory pointer table.
4029	* @param u64Address The virtual address of the page table starts.
4030	* @param cr4 The CR4, PSE is currently used.
4031	* @param fLongMode Set if this a long mode table; clear if it's a legacy mode table.
4032	* @param cMaxDepth The maxium depth.
4033	* @param pHlp Pointer to the output functions.
4034	*/
4035	static int pgmR3DumpHierarchyHCPaePDPT(PVM pVM, RTHCPHYS HCPhys, uint64_t u64Address, uint32_t cr4, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
4036	{
4037	PX86PDPT pPDPT = (PX86PDPT)MMPagePhys2Page(pVM, HCPhys);
4038	if (!pPDPT)
4039	{
4040	pHlp->pfnPrintf(pHlp, "%0*llx error! Page directory pointer table at HCPhys=%RHp was not found in the page pool!\n",
4041	fLongMode ? 16 : 8, u64Address, HCPhys);
4042	return VERR_INVALID_PARAMETER;
4043	}
4044
4045	int rc = VINF_SUCCESS;
4046	const unsigned c = fLongMode ? RT_ELEMENTS(pPDPT->a) : X86_PG_PAE_PDPE_ENTRIES;
4047	for (unsigned i = 0; i < c; i++)
4048	{
4049	X86PDPE Pdpe = pPDPT->a[i];
4050	if (Pdpe.n.u1Present)
4051	{
4052	if (fLongMode)
4053	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a p ? /
4054	"%016llx 1 \| P %c %c %c %c %c %s %s %s %s .. %c%c%c %016llx\n",
4055	u64Address + ((uint64_t)i << X86_PDPT_SHIFT),
4056	Pdpe.lm.u1Write ? 'W' : 'R',
4057	Pdpe.lm.u1User ? 'U' : 'S',
4058	Pdpe.lm.u1Accessed ? 'A' : '-',
4059	Pdpe.lm.u3Reserved & 1? '?' : '.', /* ignored */
4060	Pdpe.lm.u3Reserved & 4? '!' : '.', /* mbz */
4061	Pdpe.lm.u1WriteThru ? "WT" : "--",
4062	Pdpe.lm.u1CacheDisable? "CD" : "--",
4063	Pdpe.lm.u3Reserved & 2? "!" : "..",/* mbz */
4064	Pdpe.lm.u1NoExecute ? "NX" : "--",
4065	Pdpe.u & RT_BIT(9) ? '1' : '0',
4066	Pdpe.u & PGM_PLXFLAGS_PERMANENT ? 'p' : '-',
4067	Pdpe.u & RT_BIT(11) ? '1' : '0',
4068	Pdpe.u & X86_PDPE_PG_MASK);
4069	else
4070	pHlp->pfnPrintf(pHlp, /P G WT CD AT NX 4M a p ? /
4071	"%08x 0 \| P %c %s %s %s %s .. %c%c%c %016llx\n",
4072	i << X86_PDPT_SHIFT,
4073	Pdpe.n.u4Reserved & 1? '!' : '.', /* mbz */
4074	Pdpe.n.u4Reserved & 4? '!' : '.', /* mbz */
4075	Pdpe.n.u1WriteThru ? "WT" : "--",
4076	Pdpe.n.u1CacheDisable? "CD" : "--",
4077	Pdpe.n.u4Reserved & 2? "!" : "..",/* mbz */
4078	Pdpe.u & RT_BIT(9) ? '1' : '0',
4079	Pdpe.u & PGM_PLXFLAGS_PERMANENT ? 'p' : '-',
4080	Pdpe.u & RT_BIT(11) ? '1' : '0',
4081	Pdpe.u & X86_PDPE_PG_MASK);
4082	if (cMaxDepth >= 1)
4083	{
4084	int rc2 = pgmR3DumpHierarchyHCPaePD(pVM, Pdpe.u & X86_PDPE_PG_MASK, u64Address + ((uint64_t)i << X86_PDPT_SHIFT),
4085	cr4, fLongMode, cMaxDepth - 1, pHlp);
4086	if (rc2 < rc && RT_SUCCESS(rc))
4087	rc = rc2;
4088	}
4089	}
4090	}
4091	return rc;
4092	}
4093
4094
4095	/**
4096	* Dumps a 32-bit shadow page table.
4097	*
4098	* @returns VBox status code (VINF_SUCCESS).
4099	* @param pVM The VM handle.
4100	* @param HCPhys The physical address of the table.
4101	* @param cr4 The CR4, PSE is currently used.
4102	* @param cMaxDepth The maxium depth.
4103	* @param pHlp Pointer to the output functions.
4104	*/
4105	static int pgmR3DumpHierarchyHcPaePML4(PVM pVM, RTHCPHYS HCPhys, uint32_t cr4, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
4106	{
4107	PX86PML4 pPML4 = (PX86PML4)MMPagePhys2Page(pVM, HCPhys);
4108	if (!pPML4)
4109	{
4110	pHlp->pfnPrintf(pHlp, "Page map level 4 at HCPhys=%RHp was not found in the page pool!\n", HCPhys);
4111	return VERR_INVALID_PARAMETER;
4112	}
4113
4114	int rc = VINF_SUCCESS;
4115	for (unsigned i = 0; i < RT_ELEMENTS(pPML4->a); i++)
4116	{
4117	X86PML4E Pml4e = pPML4->a[i];
4118	if (Pml4e.n.u1Present)
4119	{
4120	uint64_t u64Address = ((uint64_t)i << X86_PML4_SHIFT) \| (((uint64_t)i >> (X86_PML4_SHIFT - X86_PDPT_SHIFT - 1)) * 0xffff000000000000ULL);
4121	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a p ? /
4122	"%016llx 0 \| P %c %c %c %c %c %s %s %s %s .. %c%c%c %016llx\n",
4123	u64Address,
4124	Pml4e.n.u1Write ? 'W' : 'R',
4125	Pml4e.n.u1User ? 'U' : 'S',
4126	Pml4e.n.u1Accessed ? 'A' : '-',
4127	Pml4e.n.u3Reserved & 1? '?' : '.', /* ignored */
4128	Pml4e.n.u3Reserved & 4? '!' : '.', /* mbz */
4129	Pml4e.n.u1WriteThru ? "WT" : "--",
4130	Pml4e.n.u1CacheDisable? "CD" : "--",
4131	Pml4e.n.u3Reserved & 2? "!" : "..",/* mbz */
4132	Pml4e.n.u1NoExecute ? "NX" : "--",
4133	Pml4e.u & RT_BIT(9) ? '1' : '0',
4134	Pml4e.u & PGM_PLXFLAGS_PERMANENT ? 'p' : '-',
4135	Pml4e.u & RT_BIT(11) ? '1' : '0',
4136	Pml4e.u & X86_PML4E_PG_MASK);
4137
4138	if (cMaxDepth >= 1)
4139	{
4140	int rc2 = pgmR3DumpHierarchyHCPaePDPT(pVM, Pml4e.u & X86_PML4E_PG_MASK, u64Address, cr4, true, cMaxDepth - 1, pHlp);
4141	if (rc2 < rc && RT_SUCCESS(rc))
4142	rc = rc2;
4143	}
4144	}
4145	}
4146	return rc;
4147	}
4148
4149
4150	/**
4151	* Dumps a 32-bit shadow page table.
4152	*
4153	* @returns VBox status code (VINF_SUCCESS).
4154	* @param pVM The VM handle.
4155	* @param pPT Pointer to the page table.
4156	* @param u32Address The virtual address this table starts at.
4157	* @param pHlp Pointer to the output functions.
4158	*/
4159	int pgmR3DumpHierarchyHC32BitPT(PVM pVM, PX86PT pPT, uint32_t u32Address, PCDBGFINFOHLP pHlp)
4160	{
4161	for (unsigned i = 0; i < RT_ELEMENTS(pPT->a); i++)
4162	{
4163	X86PTE Pte = pPT->a[i];
4164	if (Pte.n.u1Present)
4165	{
4166	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a m d /
4167	"%08x 1 \| P %c %c %c %c %c %s %s %s .. 4K %c%c%c %08x\n",
4168	u32Address + (i << X86_PT_SHIFT),
4169	Pte.n.u1Write ? 'W' : 'R',
4170	Pte.n.u1User ? 'U' : 'S',
4171	Pte.n.u1Accessed ? 'A' : '-',
4172	Pte.n.u1Dirty ? 'D' : '-',
4173	Pte.n.u1Global ? 'G' : '-',
4174	Pte.n.u1WriteThru ? "WT" : "--",
4175	Pte.n.u1CacheDisable? "CD" : "--",
4176	Pte.n.u1PAT ? "AT" : "--",
4177	Pte.u & PGM_PTFLAGS_TRACK_DIRTY ? 'd' : '-',
4178	Pte.u & RT_BIT(10) ? '1' : '0',
4179	Pte.u & PGM_PTFLAGS_CSAM_VALIDATED ? 'v' : '-',
4180	Pte.u & X86_PDE_PG_MASK);
4181	}
4182	}
4183	return VINF_SUCCESS;
4184	}
4185
4186
4187	/**
4188	* Dumps a 32-bit shadow page directory and page tables.
4189	*
4190	* @returns VBox status code (VINF_SUCCESS).
4191	* @param pVM The VM handle.
4192	* @param cr3 The root of the hierarchy.
4193	* @param cr4 The CR4, PSE is currently used.
4194	* @param cMaxDepth How deep into the hierarchy the dumper should go.
4195	* @param pHlp Pointer to the output functions.
4196	*/
4197	int pgmR3DumpHierarchyHC32BitPD(PVM pVM, uint32_t cr3, uint32_t cr4, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
4198	{
4199	PX86PD pPD = (PX86PD)MMPagePhys2Page(pVM, cr3 & X86_CR3_PAGE_MASK);
4200	if (!pPD)
4201	{
4202	pHlp->pfnPrintf(pHlp, "Page directory at %#x was not found in the page pool!\n", cr3 & X86_CR3_PAGE_MASK);
4203	return VERR_INVALID_PARAMETER;
4204	}
4205
4206	int rc = VINF_SUCCESS;
4207	for (unsigned i = 0; i < RT_ELEMENTS(pPD->a); i++)
4208	{
4209	X86PDE Pde = pPD->a[i];
4210	if (Pde.n.u1Present)
4211	{
4212	const uint32_t u32Address = i << X86_PD_SHIFT;
4213	if ((cr4 & X86_CR4_PSE) && Pde.b.u1Size)
4214	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a m d /
4215	"%08x 0 \| P %c %c %c %c %c %s %s %s .. 4M %c%c%c %08x\n",
4216	u32Address,
4217	Pde.b.u1Write ? 'W' : 'R',
4218	Pde.b.u1User ? 'U' : 'S',
4219	Pde.b.u1Accessed ? 'A' : '-',
4220	Pde.b.u1Dirty ? 'D' : '-',
4221	Pde.b.u1Global ? 'G' : '-',
4222	Pde.b.u1WriteThru ? "WT" : "--",
4223	Pde.b.u1CacheDisable? "CD" : "--",
4224	Pde.b.u1PAT ? "AT" : "--",
4225	Pde.u & RT_BIT_64(9) ? '1' : '0',
4226	Pde.u & PGM_PDFLAGS_MAPPING ? 'm' : '-',
4227	Pde.u & PGM_PDFLAGS_TRACK_DIRTY ? 'd' : '-',
4228	Pde.u & X86_PDE4M_PG_MASK);
4229	else
4230	{
4231	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a m d /
4232	"%08x 0 \| P %c %c %c %c %c %s %s .. .. 4K %c%c%c %08x\n",
4233	u32Address,
4234	Pde.n.u1Write ? 'W' : 'R',
4235	Pde.n.u1User ? 'U' : 'S',
4236	Pde.n.u1Accessed ? 'A' : '-',
4237	Pde.n.u1Reserved0 ? '?' : '.', /* ignored */
4238	Pde.n.u1Reserved1 ? '?' : '.', /* ignored */
4239	Pde.n.u1WriteThru ? "WT" : "--",
4240	Pde.n.u1CacheDisable? "CD" : "--",
4241	Pde.u & RT_BIT_64(9) ? '1' : '0',
4242	Pde.u & PGM_PDFLAGS_MAPPING ? 'm' : '-',
4243	Pde.u & PGM_PDFLAGS_TRACK_DIRTY ? 'd' : '-',
4244	Pde.u & X86_PDE_PG_MASK);
4245	if (cMaxDepth >= 1)
4246	{
4247	/** @todo what about using the page pool for mapping PTs? */
4248	RTHCPHYS HCPhys = Pde.u & X86_PDE_PG_MASK;
4249	PX86PT pPT = NULL;
4250	if (!(Pde.u & PGM_PDFLAGS_MAPPING))
4251	pPT = (PX86PT)MMPagePhys2Page(pVM, HCPhys);
4252	else
4253	{
4254	for (PPGMMAPPING pMap = pVM->pgm.s.pMappingsR3; pMap; pMap = pMap->pNextR3)
4255	if (u32Address - pMap->GCPtr < pMap->cb)
4256	{
4257	int iPDE = (u32Address - pMap->GCPtr) >> X86_PD_SHIFT;
4258	if (pMap->aPTs[iPDE].HCPhysPT != HCPhys)
4259	pHlp->pfnPrintf(pHlp, "%08x error! Mapping error! PT %d has HCPhysPT=%RHp not %RHp is in the PD.\n",
4260	u32Address, iPDE, pMap->aPTs[iPDE].HCPhysPT, HCPhys);
4261	pPT = pMap->aPTs[iPDE].pPTR3;
4262	}
4263	}
4264	int rc2 = VERR_INVALID_PARAMETER;
4265	if (pPT)
4266	rc2 = pgmR3DumpHierarchyHC32BitPT(pVM, pPT, u32Address, pHlp);
4267	else
4268	pHlp->pfnPrintf(pHlp, "%08x error! Page table at %#x was not found in the page pool!\n", u32Address, HCPhys);
4269	if (rc2 < rc && RT_SUCCESS(rc))
4270	rc = rc2;
4271	}
4272	}
4273	}
4274	}
4275
4276	return rc;
4277	}
4278
4279
4280	/**
4281	* Dumps a 32-bit shadow page table.
4282	*
4283	* @returns VBox status code (VINF_SUCCESS).
4284	* @param pVM The VM handle.
4285	* @param pPT Pointer to the page table.
4286	* @param u32Address The virtual address this table starts at.
4287	* @param PhysSearch Address to search for.
4288	*/
4289	int pgmR3DumpHierarchyGC32BitPT(PVM pVM, PX86PT pPT, uint32_t u32Address, RTGCPHYS PhysSearch)
4290	{
4291	for (unsigned i = 0; i < RT_ELEMENTS(pPT->a); i++)
4292	{
4293	X86PTE Pte = pPT->a[i];
4294	if (Pte.n.u1Present)
4295	{
4296	Log(( /P R S A D G WT CD AT NX 4M a m d /
4297	"%08x 1 \| P %c %c %c %c %c %s %s %s .. 4K %c%c%c %08x\n",
4298	u32Address + (i << X86_PT_SHIFT),
4299	Pte.n.u1Write ? 'W' : 'R',
4300	Pte.n.u1User ? 'U' : 'S',
4301	Pte.n.u1Accessed ? 'A' : '-',
4302	Pte.n.u1Dirty ? 'D' : '-',
4303	Pte.n.u1Global ? 'G' : '-',
4304	Pte.n.u1WriteThru ? "WT" : "--",
4305	Pte.n.u1CacheDisable? "CD" : "--",
4306	Pte.n.u1PAT ? "AT" : "--",
4307	Pte.u & PGM_PTFLAGS_TRACK_DIRTY ? 'd' : '-',
4308	Pte.u & RT_BIT(10) ? '1' : '0',
4309	Pte.u & PGM_PTFLAGS_CSAM_VALIDATED ? 'v' : '-',
4310	Pte.u & X86_PDE_PG_MASK));
4311
4312	if ((Pte.u & X86_PDE_PG_MASK) == PhysSearch)
4313	{
4314	uint64_t fPageShw = 0;
4315	RTHCPHYS pPhysHC = 0;
4316
4317	PGMShwGetPage(pVM, (RTGCPTR)(u32Address + (i << X86_PT_SHIFT)), &fPageShw, &pPhysHC);
4318	Log(("Found %RGp at %RGv -> flags=%llx\n", PhysSearch, (RTGCPTR)(u32Address + (i << X86_PT_SHIFT)), fPageShw));
4319	}
4320	}
4321	}
4322	return VINF_SUCCESS;
4323	}
4324
4325
4326	/**
4327	* Dumps a 32-bit guest page directory and page tables.
4328	*
4329	* @returns VBox status code (VINF_SUCCESS).
4330	* @param pVM The VM handle.
4331	* @param cr3 The root of the hierarchy.
4332	* @param cr4 The CR4, PSE is currently used.
4333	* @param PhysSearch Address to search for.
4334	*/
4335	VMMR3DECL(int) PGMR3DumpHierarchyGC(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCPHYS PhysSearch)
4336	{
4337	bool fLongMode = false;
4338	const unsigned cch = fLongMode ? 16 : 8; NOREF(cch);
4339	PX86PD pPD = 0;
4340
4341	int rc = PGM_GCPHYS_2_PTR(pVM, cr3 & X86_CR3_PAGE_MASK, &pPD);
4342	if (RT_FAILURE(rc) \|\| !pPD)
4343	{
4344	Log(("Page directory at %#x was not found in the page pool!\n", cr3 & X86_CR3_PAGE_MASK));
4345	return VERR_INVALID_PARAMETER;
4346	}
4347
4348	Log(("cr3=%08x cr4=%08x%s\n"
4349	"%-*s P - Present\n"
4350	"%-*s \| R/W - Read (0) / Write (1)\n"
4351	"%-*s \| \| U/S - User (1) / Supervisor (0)\n"
4352	"%-*s \| \| \| A - Accessed\n"
4353	"%-*s \| \| \| \| D - Dirty\n"
4354	"%-*s \| \| \| \| \| G - Global\n"
4355	"%-*s \| \| \| \| \| \| WT - Write thru\n"
4356	"%-*s \| \| \| \| \| \| \| CD - Cache disable\n"
4357	"%-*s \| \| \| \| \| \| \| \| AT - Attribute table (PAT)\n"
4358	"%-*s \| \| \| \| \| \| \| \| \| NX - No execute (K8)\n"
4359	"%-*s \| \| \| \| \| \| \| \| \| \| 4K/4M/2M - Page size.\n"
4360	"%-*s \| \| \| \| \| \| \| \| \| \| \| AVL - a=allocated; m=mapping; d=track dirty;\n"
4361	"%-*s \| \| \| \| \| \| \| \| \| \| \| \| p=permanent; v=validated;\n"
4362	"%-*s Level \| \| \| \| \| \| \| \| \| \| \| \| Page\n"
4363	/* xxxx n **** P R S A D G WT CD AT NX 4M AVL xxxxxxxxxxxxx
4364	- W U - - - -- -- -- -- -- 010 */
4365	, cr3, cr4, fLongMode ? " Long Mode" : "",
4366	cch, "", cch, "", cch, "", cch, "", cch, "", cch, "", cch, "",
4367	cch, "", cch, "", cch, "", cch, "", cch, "", cch, "", cch, "Address"));
4368
4369	for (unsigned i = 0; i < RT_ELEMENTS(pPD->a); i++)
4370	{
4371	X86PDE Pde = pPD->a[i];
4372	if (Pde.n.u1Present)
4373	{
4374	const uint32_t u32Address = i << X86_PD_SHIFT;
4375
4376	if ((cr4 & X86_CR4_PSE) && Pde.b.u1Size)
4377	Log(( /P R S A D G WT CD AT NX 4M a m d /
4378	"%08x 0 \| P %c %c %c %c %c %s %s %s .. 4M %c%c%c %08x\n",
4379	u32Address,
4380	Pde.b.u1Write ? 'W' : 'R',
4381	Pde.b.u1User ? 'U' : 'S',
4382	Pde.b.u1Accessed ? 'A' : '-',
4383	Pde.b.u1Dirty ? 'D' : '-',
4384	Pde.b.u1Global ? 'G' : '-',
4385	Pde.b.u1WriteThru ? "WT" : "--",
4386	Pde.b.u1CacheDisable? "CD" : "--",
4387	Pde.b.u1PAT ? "AT" : "--",
4388	Pde.u & RT_BIT(9) ? '1' : '0',
4389	Pde.u & RT_BIT(10) ? '1' : '0',
4390	Pde.u & RT_BIT(11) ? '1' : '0',
4391	pgmGstGet4MBPhysPage(&pVM->pgm.s, Pde)));
4392	/** @todo PhysSearch */
4393	else
4394	{
4395	Log(( /P R S A D G WT CD AT NX 4M a m d /
4396	"%08x 0 \| P %c %c %c %c %c %s %s .. .. 4K %c%c%c %08x\n",
4397	u32Address,
4398	Pde.n.u1Write ? 'W' : 'R',
4399	Pde.n.u1User ? 'U' : 'S',
4400	Pde.n.u1Accessed ? 'A' : '-',
4401	Pde.n.u1Reserved0 ? '?' : '.', /* ignored */
4402	Pde.n.u1Reserved1 ? '?' : '.', /* ignored */
4403	Pde.n.u1WriteThru ? "WT" : "--",
4404	Pde.n.u1CacheDisable? "CD" : "--",
4405	Pde.u & RT_BIT(9) ? '1' : '0',
4406	Pde.u & RT_BIT(10) ? '1' : '0',
4407	Pde.u & RT_BIT(11) ? '1' : '0',
4408	Pde.u & X86_PDE_PG_MASK));
4409	////if (cMaxDepth >= 1)
4410	{
4411	/** @todo what about using the page pool for mapping PTs? */
4412	RTGCPHYS GCPhys = Pde.u & X86_PDE_PG_MASK;
4413	PX86PT pPT = NULL;
4414
4415	rc = PGM_GCPHYS_2_PTR(pVM, GCPhys, &pPT);
4416
4417	int rc2 = VERR_INVALID_PARAMETER;
4418	if (pPT)
4419	rc2 = pgmR3DumpHierarchyGC32BitPT(pVM, pPT, u32Address, PhysSearch);
4420	else
4421	Log(("%08x error! Page table at %#x was not found in the page pool!\n", u32Address, GCPhys));
4422	if (rc2 < rc && RT_SUCCESS(rc))
4423	rc = rc2;
4424	}
4425	}
4426	}
4427	}
4428
4429	return rc;
4430	}
4431
4432
4433	/**
4434	* Dumps a page table hierarchy use only physical addresses and cr4/lm flags.
4435	*
4436	* @returns VBox status code (VINF_SUCCESS).
4437	* @param pVM The VM handle.
4438	* @param cr3 The root of the hierarchy.
4439	* @param cr4 The cr4, only PAE and PSE is currently used.
4440	* @param fLongMode Set if long mode, false if not long mode.
4441	* @param cMaxDepth Number of levels to dump.
4442	* @param pHlp Pointer to the output functions.
4443	*/
4444	VMMR3DECL(int) PGMR3DumpHierarchyHC(PVM pVM, uint64_t cr3, uint64_t cr4, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
4445	{
4446	if (!pHlp)
4447	pHlp = DBGFR3InfoLogHlp();
4448	if (!cMaxDepth)
4449	return VINF_SUCCESS;
4450	const unsigned cch = fLongMode ? 16 : 8;
4451	pHlp->pfnPrintf(pHlp,
4452	"cr3=%08x cr4=%08x%s\n"
4453	"%-*s P - Present\n"
4454	"%-*s \| R/W - Read (0) / Write (1)\n"
4455	"%-*s \| \| U/S - User (1) / Supervisor (0)\n"
4456	"%-*s \| \| \| A - Accessed\n"
4457	"%-*s \| \| \| \| D - Dirty\n"
4458	"%-*s \| \| \| \| \| G - Global\n"
4459	"%-*s \| \| \| \| \| \| WT - Write thru\n"
4460	"%-*s \| \| \| \| \| \| \| CD - Cache disable\n"
4461	"%-*s \| \| \| \| \| \| \| \| AT - Attribute table (PAT)\n"
4462	"%-*s \| \| \| \| \| \| \| \| \| NX - No execute (K8)\n"
4463	"%-*s \| \| \| \| \| \| \| \| \| \| 4K/4M/2M - Page size.\n"
4464	"%-*s \| \| \| \| \| \| \| \| \| \| \| AVL - a=allocated; m=mapping; d=track dirty;\n"
4465	"%-*s \| \| \| \| \| \| \| \| \| \| \| \| p=permanent; v=validated;\n"
4466	"%-*s Level \| \| \| \| \| \| \| \| \| \| \| \| Page\n"
4467	/* xxxx n **** P R S A D G WT CD AT NX 4M AVL xxxxxxxxxxxxx
4468	- W U - - - -- -- -- -- -- 010 */
4469	, cr3, cr4, fLongMode ? " Long Mode" : "",
4470	cch, "", cch, "", cch, "", cch, "", cch, "", cch, "", cch, "",
4471	cch, "", cch, "", cch, "", cch, "", cch, "", cch, "", cch, "Address");
4472	if (cr4 & X86_CR4_PAE)
4473	{
4474	if (fLongMode)
4475	return pgmR3DumpHierarchyHcPaePML4(pVM, cr3 & X86_CR3_PAGE_MASK, cr4, cMaxDepth, pHlp);
4476	return pgmR3DumpHierarchyHCPaePDPT(pVM, cr3 & X86_CR3_PAE_PAGE_MASK, 0, cr4, false, cMaxDepth, pHlp);
4477	}
4478	return pgmR3DumpHierarchyHC32BitPD(pVM, cr3 & X86_CR3_PAGE_MASK, cr4, cMaxDepth, pHlp);
4479	}
4480
4481	#ifdef VBOX_WITH_DEBUGGER
4482
4483	/**
4484	* The '.pgmram' command.
4485	*
4486	* @returns VBox status.
4487	* @param pCmd Pointer to the command descriptor (as registered).
4488	* @param pCmdHlp Pointer to command helper functions.
4489	* @param pVM Pointer to the current VM (if any).
4490	* @param paArgs Pointer to (readonly) array of arguments.
4491	* @param cArgs Number of arguments in the array.
4492	*/
4493	static DECLCALLBACK(int) pgmR3CmdRam(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4494	{
4495	/*
4496	* Validate input.
4497	*/
4498	if (!pVM)
4499	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4500	if (!pVM->pgm.s.pRamRangesRC)
4501	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Sorry, no Ram is registered.\n");
4502
4503	/*
4504	* Dump the ranges.
4505	*/
4506	int rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL, "From - To (incl) pvHC\n");
4507	PPGMRAMRANGE pRam;
4508	for (pRam = pVM->pgm.s.pRamRangesR3; pRam; pRam = pRam->pNextR3)
4509	{
4510	rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL,
4511	"%RGp - %RGp %p\n",
4512	pRam->GCPhys, pRam->GCPhysLast, pRam->pvR3);
4513	if (RT_FAILURE(rc))
4514	return rc;
4515	}
4516
4517	return VINF_SUCCESS;
4518	}
4519
4520
4521	/**
4522	* The '.pgmmap' command.
4523	*
4524	* @returns VBox status.
4525	* @param pCmd Pointer to the command descriptor (as registered).
4526	* @param pCmdHlp Pointer to command helper functions.
4527	* @param pVM Pointer to the current VM (if any).
4528	* @param paArgs Pointer to (readonly) array of arguments.
4529	* @param cArgs Number of arguments in the array.
4530	*/
4531	static DECLCALLBACK(int) pgmR3CmdMap(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4532	{
4533	/*
4534	* Validate input.
4535	*/
4536	if (!pVM)
4537	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4538	if (!pVM->pgm.s.pMappingsR3)
4539	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Sorry, no mappings are registered.\n");
4540
4541	/*
4542	* Print message about the fixedness of the mappings.
4543	*/
4544	int rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL, pVM->pgm.s.fMappingsFixed ? "The mappings are FIXED.\n" : "The mappings are FLOATING.\n");
4545	if (RT_FAILURE(rc))
4546	return rc;
4547
4548	/*
4549	* Dump the ranges.
4550	*/
4551	PPGMMAPPING pCur;
4552	for (pCur = pVM->pgm.s.pMappingsR3; pCur; pCur = pCur->pNextR3)
4553	{
4554	rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL,
4555	"%08x - %08x %s\n",
4556	pCur->GCPtr, pCur->GCPtrLast, pCur->pszDesc);
4557	if (RT_FAILURE(rc))
4558	return rc;
4559	}
4560
4561	return VINF_SUCCESS;
4562	}
4563
4564
4565	/**
4566	* The '.pgmerror' and '.pgmerroroff' commands.
4567	*
4568	* @returns VBox status.
4569	* @param pCmd Pointer to the command descriptor (as registered).
4570	* @param pCmdHlp Pointer to command helper functions.
4571	* @param pVM Pointer to the current VM (if any).
4572	* @param paArgs Pointer to (readonly) array of arguments.
4573	* @param cArgs Number of arguments in the array.
4574	*/
4575	static DECLCALLBACK(int) pgmR3CmdError(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4576	{
4577	/*
4578	* Validate input.
4579	*/
4580	if (!pVM)
4581	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4582	AssertReturn(cArgs == 0 \|\| (cArgs == 1 && paArgs[0].enmType == DBGCVAR_TYPE_STRING),
4583	pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: Hit bug in the parser.\n"));
4584
4585	if (!cArgs)
4586	{
4587	/*
4588	* Print the list of error injection locations with status.
4589	*/
4590	pCmdHlp->pfnPrintf(pCmdHlp, NULL, "PGM error inject locations:\n");
4591	pCmdHlp->pfnPrintf(pCmdHlp, NULL, " handy - %RTbool\n", pVM->pgm.s.fErrInjHandyPages);
4592	}
4593	else
4594	{
4595
4596	/*
4597	* String switch on where to inject the error.
4598	*/
4599	bool const fNewState = !strcmp(pCmd->pszCmd, "pgmerror");
4600	const char *pszWhere = paArgs[0].u.pszString;
4601	if (!strcmp(pszWhere, "handy"))
4602	ASMAtomicWriteBool(&pVM->pgm.s.fErrInjHandyPages, fNewState);
4603	else
4604	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: Invalid 'where' value: %s.\n", pszWhere);
4605	pCmdHlp->pfnPrintf(pCmdHlp, NULL, "done\n");
4606	}
4607	return VINF_SUCCESS;
4608	}
4609
4610
4611	/**
4612	* The '.pgmsync' command.
4613	*
4614	* @returns VBox status.
4615	* @param pCmd Pointer to the command descriptor (as registered).
4616	* @param pCmdHlp Pointer to command helper functions.
4617	* @param pVM Pointer to the current VM (if any).
4618	* @param paArgs Pointer to (readonly) array of arguments.
4619	* @param cArgs Number of arguments in the array.
4620	*/
4621	static DECLCALLBACK(int) pgmR3CmdSync(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4622	{
4623	/*
4624	* Validate input.
4625	*/
4626	if (!pVM)
4627	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4628
4629	/*
4630	* Force page directory sync.
4631	*/
4632	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
4633
4634	int rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Forcing page directory sync.\n");
4635	if (RT_FAILURE(rc))
4636	return rc;
4637
4638	return VINF_SUCCESS;
4639	}
4640
4641
4642	#ifdef VBOX_STRICT
4643	/**
4644	* The '.pgmassertcr3' command.
4645	*
4646	* @returns VBox status.
4647	* @param pCmd Pointer to the command descriptor (as registered).
4648	* @param pCmdHlp Pointer to command helper functions.
4649	* @param pVM Pointer to the current VM (if any).
4650	* @param paArgs Pointer to (readonly) array of arguments.
4651	* @param cArgs Number of arguments in the array.
4652	*/
4653	static DECLCALLBACK(int) pgmR3CmdAssertCR3(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4654	{
4655	/*
4656	* Validate input.
4657	*/
4658	if (!pVM)
4659	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4660
4661	int rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Checking shadow CR3 page tables for consistency.\n");
4662	if (RT_FAILURE(rc))
4663	return rc;
4664
4665	PGMAssertCR3(pVM, CPUMGetGuestCR3(pVM), CPUMGetGuestCR4(pVM));
4666
4667	return VINF_SUCCESS;
4668	}
4669	#endif /* VBOX_STRICT */
4670
4671
4672	/**
4673	* The '.pgmsyncalways' command.
4674	*
4675	* @returns VBox status.
4676	* @param pCmd Pointer to the command descriptor (as registered).
4677	* @param pCmdHlp Pointer to command helper functions.
4678	* @param pVM Pointer to the current VM (if any).
4679	* @param paArgs Pointer to (readonly) array of arguments.
4680	* @param cArgs Number of arguments in the array.
4681	*/
4682	static DECLCALLBACK(int) pgmR3CmdSyncAlways(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4683	{
4684	/*
4685	* Validate input.
4686	*/
4687	if (!pVM)
4688	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4689
4690	/*
4691	* Force page directory sync.
4692	*/
4693	if (pVM->pgm.s.fSyncFlags & PGM_SYNC_ALWAYS)
4694	{
4695	ASMAtomicAndU32(&pVM->pgm.s.fSyncFlags, ~PGM_SYNC_ALWAYS);
4696	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Disabled permanent forced page directory syncing.\n");
4697	}
4698	else
4699	{
4700	ASMAtomicOrU32(&pVM->pgm.s.fSyncFlags, PGM_SYNC_ALWAYS);
4701	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
4702	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Enabled permanent forced page directory syncing.\n");
4703	}
4704	}
4705
4706	#endif /* VBOX_WITH_DEBUGGER */
4707
4708	/**
4709	* pvUser argument of the pgmR3CheckIntegrity*Node callbacks.
4710	*/
4711	typedef struct PGMCHECKINTARGS
4712	{
4713	bool fLeftToRight; /*< true: left-to-right; false: right-to-left. /
4714	PPGMPHYSHANDLER pPrevPhys;
4715	PPGMVIRTHANDLER pPrevVirt;
4716	PPGMPHYS2VIRTHANDLER pPrevPhys2Virt;
4717	PVM pVM;
4718	} PGMCHECKINTARGS, *PPGMCHECKINTARGS;
4719
4720	/**
4721	* Validate a node in the physical handler tree.
4722	*
4723	* @returns 0 on if ok, other wise 1.
4724	* @param pNode The handler node.
4725	* @param pvUser pVM.
4726	*/
4727	static DECLCALLBACK(int) pgmR3CheckIntegrityPhysHandlerNode(PAVLROGCPHYSNODECORE pNode, void *pvUser)
4728	{
4729	PPGMCHECKINTARGS pArgs = (PPGMCHECKINTARGS)pvUser;
4730	PPGMPHYSHANDLER pCur = (PPGMPHYSHANDLER)pNode;
4731	AssertReleaseReturn(!((uintptr_t)pCur & 7), 1);
4732	AssertReleaseMsg(pCur->Core.Key <= pCur->Core.KeyLast,("pCur=%p %RGp-%RGp %s\n", pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
4733	AssertReleaseMsg( !pArgs->pPrevPhys
4734	\|\| (pArgs->fLeftToRight ? pArgs->pPrevPhys->Core.KeyLast < pCur->Core.Key : pArgs->pPrevPhys->Core.KeyLast > pCur->Core.Key),
4735	("pPrevPhys=%p %RGp-%RGp %s\n"
4736	" pCur=%p %RGp-%RGp %s\n",
4737	pArgs->pPrevPhys, pArgs->pPrevPhys->Core.Key, pArgs->pPrevPhys->Core.KeyLast, pArgs->pPrevPhys->pszDesc,
4738	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
4739	pArgs->pPrevPhys = pCur;
4740	return 0;
4741	}
4742
4743
4744	/**
4745	* Validate a node in the virtual handler tree.
4746	*
4747	* @returns 0 on if ok, other wise 1.
4748	* @param pNode The handler node.
4749	* @param pvUser pVM.
4750	*/
4751	static DECLCALLBACK(int) pgmR3CheckIntegrityVirtHandlerNode(PAVLROGCPTRNODECORE pNode, void *pvUser)
4752	{
4753	PPGMCHECKINTARGS pArgs = (PPGMCHECKINTARGS)pvUser;
4754	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)pNode;
4755	AssertReleaseReturn(!((uintptr_t)pCur & 7), 1);
4756	AssertReleaseMsg(pCur->Core.Key <= pCur->Core.KeyLast,("pCur=%p %RGv-%RGv %s\n", pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
4757	AssertReleaseMsg( !pArgs->pPrevVirt
4758	\|\| (pArgs->fLeftToRight ? pArgs->pPrevVirt->Core.KeyLast < pCur->Core.Key : pArgs->pPrevVirt->Core.KeyLast > pCur->Core.Key),
4759	("pPrevVirt=%p %RGv-%RGv %s\n"
4760	" pCur=%p %RGv-%RGv %s\n",
4761	pArgs->pPrevVirt, pArgs->pPrevVirt->Core.Key, pArgs->pPrevVirt->Core.KeyLast, pArgs->pPrevVirt->pszDesc,
4762	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
4763	for (unsigned iPage = 0; iPage < pCur->cPages; iPage++)
4764	{
4765	AssertReleaseMsg(pCur->aPhysToVirt[iPage].offVirtHandler == -RT_OFFSETOF(PGMVIRTHANDLER, aPhysToVirt[iPage]),
4766	("pCur=%p %RGv-%RGv %s\n"
4767	"iPage=%d offVirtHandle=%#x expected %#x\n",
4768	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc,
4769	iPage, pCur->aPhysToVirt[iPage].offVirtHandler, -RT_OFFSETOF(PGMVIRTHANDLER, aPhysToVirt[iPage])));
4770	}
4771	pArgs->pPrevVirt = pCur;
4772	return 0;
4773	}
4774
4775
4776	/**
4777	* Validate a node in the virtual handler tree.
4778	*
4779	* @returns 0 on if ok, other wise 1.
4780	* @param pNode The handler node.
4781	* @param pvUser pVM.
4782	*/
4783	static DECLCALLBACK(int) pgmR3CheckIntegrityPhysToVirtHandlerNode(PAVLROGCPHYSNODECORE pNode, void *pvUser)
4784	{
4785	PPGMCHECKINTARGS pArgs = (PPGMCHECKINTARGS)pvUser;
4786	PPGMPHYS2VIRTHANDLER pCur = (PPGMPHYS2VIRTHANDLER)pNode;
4787	AssertReleaseMsgReturn(!((uintptr_t)pCur & 3), ("\n"), 1);
4788	AssertReleaseMsgReturn(!(pCur->offVirtHandler & 3), ("\n"), 1);
4789	AssertReleaseMsg(pCur->Core.Key <= pCur->Core.KeyLast,("pCur=%p %RGp-%RGp\n", pCur, pCur->Core.Key, pCur->Core.KeyLast));
4790	AssertReleaseMsg( !pArgs->pPrevPhys2Virt
4791	\|\| (pArgs->fLeftToRight ? pArgs->pPrevPhys2Virt->Core.KeyLast < pCur->Core.Key : pArgs->pPrevPhys2Virt->Core.KeyLast > pCur->Core.Key),
4792	("pPrevPhys2Virt=%p %RGp-%RGp\n"
4793	" pCur=%p %RGp-%RGp\n",
4794	pArgs->pPrevPhys2Virt, pArgs->pPrevPhys2Virt->Core.Key, pArgs->pPrevPhys2Virt->Core.KeyLast,
4795	pCur, pCur->Core.Key, pCur->Core.KeyLast));
4796	AssertReleaseMsg( !pArgs->pPrevPhys2Virt
4797	\|\| (pArgs->fLeftToRight ? pArgs->pPrevPhys2Virt->Core.KeyLast < pCur->Core.Key : pArgs->pPrevPhys2Virt->Core.KeyLast > pCur->Core.Key),
4798	("pPrevPhys2Virt=%p %RGp-%RGp\n"
4799	" pCur=%p %RGp-%RGp\n",
4800	pArgs->pPrevPhys2Virt, pArgs->pPrevPhys2Virt->Core.Key, pArgs->pPrevPhys2Virt->Core.KeyLast,
4801	pCur, pCur->Core.Key, pCur->Core.KeyLast));
4802	AssertReleaseMsg((pCur->offNextAlias & (PGMPHYS2VIRTHANDLER_IN_TREE \| PGMPHYS2VIRTHANDLER_IS_HEAD)) == (PGMPHYS2VIRTHANDLER_IN_TREE \| PGMPHYS2VIRTHANDLER_IS_HEAD),
4803	("pCur=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4804	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias));
4805	if (pCur->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK)
4806	{
4807	PPGMPHYS2VIRTHANDLER pCur2 = pCur;
4808	for (;;)
4809	{
4810	pCur2 = (PPGMPHYS2VIRTHANDLER)((intptr_t)pCur + (pCur->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK));
4811	AssertReleaseMsg(pCur2 != pCur,
4812	(" pCur=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4813	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias));
4814	AssertReleaseMsg((pCur2->offNextAlias & (PGMPHYS2VIRTHANDLER_IN_TREE \| PGMPHYS2VIRTHANDLER_IS_HEAD)) == PGMPHYS2VIRTHANDLER_IN_TREE,
4815	(" pCur=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
4816	"pCur2=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4817	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias,
4818	pCur2, pCur2->Core.Key, pCur2->Core.KeyLast, pCur2->offVirtHandler, pCur2->offNextAlias));
4819	AssertReleaseMsg((pCur2->Core.Key ^ pCur->Core.Key) < PAGE_SIZE,
4820	(" pCur=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
4821	"pCur2=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4822	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias,
4823	pCur2, pCur2->Core.Key, pCur2->Core.KeyLast, pCur2->offVirtHandler, pCur2->offNextAlias));
4824	AssertReleaseMsg((pCur2->Core.KeyLast ^ pCur->Core.KeyLast) < PAGE_SIZE,
4825	(" pCur=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
4826	"pCur2=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4827	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias,
4828	pCur2, pCur2->Core.Key, pCur2->Core.KeyLast, pCur2->offVirtHandler, pCur2->offNextAlias));
4829	if (!(pCur2->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK))
4830	break;
4831	}
4832	}
4833
4834	pArgs->pPrevPhys2Virt = pCur;
4835	return 0;
4836	}
4837
4838
4839	/**
4840	* Perform an integrity check on the PGM component.
4841	*
4842	* @returns VINF_SUCCESS if everything is fine.
4843	* @returns VBox error status after asserting on integrity breach.
4844	* @param pVM The VM handle.
4845	*/
4846	VMMR3DECL(int) PGMR3CheckIntegrity(PVM pVM)
4847	{
4848	AssertReleaseReturn(pVM->pgm.s.offVM, VERR_INTERNAL_ERROR);
4849
4850	/*
4851	* Check the trees.
4852	*/
4853	int cErrors = 0;
4854	const static PGMCHECKINTARGS s_LeftToRight = { true, NULL, NULL, NULL, pVM };
4855	const static PGMCHECKINTARGS s_RightToLeft = { false, NULL, NULL, NULL, pVM };
4856	PGMCHECKINTARGS Args = s_LeftToRight;
4857	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysHandlers, true, pgmR3CheckIntegrityPhysHandlerNode, &Args);
4858	Args = s_RightToLeft;
4859	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysHandlers, false, pgmR3CheckIntegrityPhysHandlerNode, &Args);
4860	Args = s_LeftToRight;
4861	cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesR3->VirtHandlers, true, pgmR3CheckIntegrityVirtHandlerNode, &Args);
4862	Args = s_RightToLeft;
4863	cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesR3->VirtHandlers, false, pgmR3CheckIntegrityVirtHandlerNode, &Args);
4864	Args = s_LeftToRight;
4865	cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesR3->HyperVirtHandlers, true, pgmR3CheckIntegrityVirtHandlerNode, &Args);
4866	Args = s_RightToLeft;
4867	cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesR3->HyperVirtHandlers, false, pgmR3CheckIntegrityVirtHandlerNode, &Args);
4868	Args = s_LeftToRight;
4869	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysToVirtHandlers, true, pgmR3CheckIntegrityPhysToVirtHandlerNode, &Args);
4870	Args = s_RightToLeft;
4871	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysToVirtHandlers, false, pgmR3CheckIntegrityPhysToVirtHandlerNode, &Args);
4872
4873	return !cErrors ? VINF_SUCCESS : VERR_INTERNAL_ERROR;
4874	}
4875
4876

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source: vbox/trunk/src/VBox/VMM/PGM.cpp@ 18880

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