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1	/* $Id: PGM.cpp 18889 2009-04-14 12:33:29Z vboxsync $ */
2	/** @file
3	* PGM - Page Manager and Monitor. (Mixing stuff here, not good?)
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22
23	/** @page pg_pgm PGM - The Page Manager and Monitor
24	*
25	* @see grp_pgm,
26	* @ref pg_pgm_pool,
27	* @ref pg_pgm_phys.
28	*
29	*
30	* @section sec_pgm_modes Paging Modes
31	*
32	* There are three memory contexts: Host Context (HC), Guest Context (GC)
33	* and intermediate context. When talking about paging HC can also be refered to
34	* as "host paging", and GC refered to as "shadow paging".
35	*
36	* We define three basic paging modes: 32-bit, PAE and AMD64. The host paging mode
37	* is defined by the host operating system. The mode used in the shadow paging mode
38	* depends on the host paging mode and what the mode the guest is currently in. The
39	* following relation between the two is defined:
40	*
41	* @verbatim
42	Host > 32-bit \| PAE \| AMD64 \|
43	Guest \| \| \| \|
44	==v================================
45	32-bit 32-bit PAE PAE
46	-------\|--------\|--------\|--------\|
47	PAE PAE PAE PAE
48	-------\|--------\|--------\|--------\|
49	AMD64 AMD64 AMD64 AMD64
50	-------\|--------\|--------\|--------\| @endverbatim
51	*
52	* All configuration except those in the diagonal (upper left) are expected to
53	* require special effort from the switcher (i.e. a bit slower).
54	*
55	*
56	*
57	*
58	* @section sec_pgm_shw The Shadow Memory Context
59	*
60	*
61	* [..]
62	*
63	* Because of guest context mappings requires PDPT and PML4 entries to allow
64	* writing on AMD64, the two upper levels will have fixed flags whatever the
65	* guest is thinking of using there. So, when shadowing the PD level we will
66	* calculate the effective flags of PD and all the higher levels. In legacy
67	* PAE mode this only applies to the PWT and PCD bits (the rest are
68	* ignored/reserved/MBZ). We will ignore those bits for the present.
69	*
70	*
71	*
72	* @section sec_pgm_int The Intermediate Memory Context
73	*
74	* The world switch goes thru an intermediate memory context which purpose it is
75	* to provide different mappings of the switcher code. All guest mappings are also
76	* present in this context.
77	*
78	* The switcher code is mapped at the same location as on the host, at an
79	* identity mapped location (physical equals virtual address), and at the
80	* hypervisor location. The identity mapped location is for when the world
81	* switches that involves disabling paging.
82	*
83	* PGM maintain page tables for 32-bit, PAE and AMD64 paging modes. This
84	* simplifies switching guest CPU mode and consistency at the cost of more
85	* code to do the work. All memory use for those page tables is located below
86	* 4GB (this includes page tables for guest context mappings).
87	*
88	*
89	* @subsection subsec_pgm_int_gc Guest Context Mappings
90	*
91	* During assignment and relocation of a guest context mapping the intermediate
92	* memory context is used to verify the new location.
93	*
94	* Guest context mappings are currently restricted to below 4GB, for reasons
95	* of simplicity. This may change when we implement AMD64 support.
96	*
97	*
98	*
99	*
100	* @section sec_pgm_misc Misc
101	*
102	* @subsection subsec_pgm_misc_diff Differences Between Legacy PAE and Long Mode PAE
103	*
104	* The differences between legacy PAE and long mode PAE are:
105	* -# PDPE bits 1, 2, 5 and 6 are defined differently. In leagcy mode they are
106	* all marked down as must-be-zero, while in long mode 1, 2 and 5 have the
107	* usual meanings while 6 is ignored (AMD). This means that upon switching to
108	* legacy PAE mode we'll have to clear these bits and when going to long mode
109	* they must be set. This applies to both intermediate and shadow contexts,
110	* however we don't need to do it for the intermediate one since we're
111	* executing with CR0.WP at that time.
112	* -# CR3 allows a 32-byte aligned address in legacy mode, while in long mode
113	* a page aligned one is required.
114	*
115	*
116	* @section sec_pgm_handlers Access Handlers
117	*
118	* Placeholder.
119	*
120	*
121	* @subsection sec_pgm_handlers_virt Virtual Access Handlers
122	*
123	* Placeholder.
124	*
125	*
126	* @subsection sec_pgm_handlers_virt Virtual Access Handlers
127	*
128	* We currently implement three types of virtual access handlers: ALL, WRITE
129	* and HYPERVISOR (WRITE). See PGMVIRTHANDLERTYPE for some more details.
130	*
131	* The HYPERVISOR access handlers is kept in a separate tree since it doesn't apply
132	* to physical pages (PGMTREES::HyperVirtHandlers) and only needs to be consulted in
133	* a special \#PF case. The ALL and WRITE are in the PGMTREES::VirtHandlers tree, the
134	* rest of this section is going to be about these handlers.
135	*
136	* We'll go thru the life cycle of a handler and try make sense of it all, don't know
137	* how successfull this is gonna be...
138	*
139	* 1. A handler is registered thru the PGMR3HandlerVirtualRegister and
140	* PGMHandlerVirtualRegisterEx APIs. We check for conflicting virtual handlers
141	* and create a new node that is inserted into the AVL tree (range key). Then
142	* a full PGM resync is flagged (clear pool, sync cr3, update virtual bit of PGMPAGE).
143	*
144	* 2. The following PGMSyncCR3/SyncCR3 operation will first make invoke HandlerVirtualUpdate.
145	*
146	* 2a. HandlerVirtualUpdate will will lookup all the pages covered by virtual handlers
147	* via the current guest CR3 and update the physical page -> virtual handler
148	* translation. Needless to say, this doesn't exactly scale very well. If any changes
149	* are detected, it will flag a virtual bit update just like we did on registration.
150	* PGMPHYS pages with changes will have their virtual handler state reset to NONE.
151	*
152	* 2b. The virtual bit update process will iterate all the pages covered by all the
153	* virtual handlers and update the PGMPAGE virtual handler state to the max of all
154	* virtual handlers on that page.
155	*
156	* 2c. Back in SyncCR3 we will now flush the entire shadow page cache to make sure
157	* we don't miss any alias mappings of the monitored pages.
158	*
159	* 2d. SyncCR3 will then proceed with syncing the CR3 table.
160	*
161	* 3. \#PF(np,read) on a page in the range. This will cause it to be synced
162	* read-only and resumed if it's a WRITE handler. If it's an ALL handler we
163	* will call the handlers like in the next step. If the physical mapping has
164	* changed we will - some time in the future - perform a handler callback
165	* (optional) and update the physical -> virtual handler cache.
166	*
167	* 4. \#PF(,write) on a page in the range. This will cause the handler to
168	* be invoked.
169	*
170	* 5. The guest invalidates the page and changes the physical backing or
171	* unmaps it. This should cause the invalidation callback to be invoked
172	* (it might not yet be 100% perfect). Exactly what happens next... is
173	* this where we mess up and end up out of sync for a while?
174	*
175	* 6. The handler is deregistered by the client via PGMHandlerVirtualDeregister.
176	* We will then set all PGMPAGEs in the physical -> virtual handler cache for
177	* this handler to NONE and trigger a full PGM resync (basically the same
178	* as int step 1). Which means 2 is executed again.
179	*
180	*
181	* @subsubsection sub_sec_pgm_handler_virt_todo TODOs
182	*
183	* There is a bunch of things that needs to be done to make the virtual handlers
184	* work 100% correctly and work more efficiently.
185	*
186	* The first bit hasn't been implemented yet because it's going to slow the
187	* whole mess down even more, and besides it seems to be working reliably for
188	* our current uses. OTOH, some of the optimizations might end up more or less
189	* implementing the missing bits, so we'll see.
190	*
191	* On the optimization side, the first thing to do is to try avoid unnecessary
192	* cache flushing. Then try team up with the shadowing code to track changes
193	* in mappings by means of access to them (shadow in), updates to shadows pages,
194	* invlpg, and shadow PT discarding (perhaps).
195	*
196	* Some idea that have popped up for optimization for current and new features:
197	* - bitmap indicating where there are virtual handlers installed.
198	* (4KB => 220 pages, page 212 => covers 32-bit address space 1:1!)
199	* - Further optimize this by min/max (needs min/max avl getters).
200	* - Shadow page table entry bit (if any left)?
201	*
202	*/
203
204
205	/** @page pg_pgm_phys PGM Physical Guest Memory Management
206	*
207	*
208	* Objectives:
209	* - Guest RAM over-commitment using memory ballooning,
210	* zero pages and general page sharing.
211	* - Moving or mirroring a VM onto a different physical machine.
212	*
213	*
214	* @subsection subsec_pgmPhys_Definitions Definitions
215	*
216	* Allocation chunk - A RTR0MemObjAllocPhysNC object and the tracking
217	* machinery assoicated with it.
218	*
219	*
220	*
221	*
222	* @subsection subsec_pgmPhys_AllocPage Allocating a page.
223	*
224	* Initially we map all guest memory to the (per VM) zero page, which
225	* means that none of the read functions will cause pages to be allocated.
226	*
227	* Exception, access bit in page tables that have been shared. This must
228	* be handled, but we must also make sure PGMGst*Modify doesn't make
229	* unnecessary modifications.
230	*
231	* Allocation points:
232	* - PGMPhysSimpleWriteGCPhys and PGMPhysWrite.
233	* - Replacing a zero page mapping at \#PF.
234	* - Replacing a shared page mapping at \#PF.
235	* - ROM registration (currently MMR3RomRegister).
236	* - VM restore (pgmR3Load).
237	*
238	* For the first three it would make sense to keep a few pages handy
239	* until we've reached the max memory commitment for the VM.
240	*
241	* For the ROM registration, we know exactly how many pages we need
242	* and will request these from ring-0. For restore, we will save
243	* the number of non-zero pages in the saved state and allocate
244	* them up front. This would allow the ring-0 component to refuse
245	* the request if the isn't sufficient memory available for VM use.
246	*
247	* Btw. for both ROM and restore allocations we won't be requiring
248	* zeroed pages as they are going to be filled instantly.
249	*
250	*
251	* @subsection subsec_pgmPhys_FreePage Freeing a page
252	*
253	* There are a few points where a page can be freed:
254	* - After being replaced by the zero page.
255	* - After being replaced by a shared page.
256	* - After being ballooned by the guest additions.
257	* - At reset.
258	* - At restore.
259	*
260	* When freeing one or more pages they will be returned to the ring-0
261	* component and replaced by the zero page.
262	*
263	* The reasoning for clearing out all the pages on reset is that it will
264	* return us to the exact same state as on power on, and may thereby help
265	* us reduce the memory load on the system. Further it might have a
266	* (temporary) positive influence on memory fragmentation (@see subsec_pgmPhys_Fragmentation).
267	*
268	* On restore, as mention under the allocation topic, pages should be
269	* freed / allocated depending on how many is actually required by the
270	* new VM state. The simplest approach is to do like on reset, and free
271	* all non-ROM pages and then allocate what we need.
272	*
273	* A measure to prevent some fragmentation, would be to let each allocation
274	* chunk have some affinity towards the VM having allocated the most pages
275	* from it. Also, try make sure to allocate from allocation chunks that
276	* are almost full. Admittedly, both these measures might work counter to
277	* our intentions and its probably not worth putting a lot of effort,
278	* cpu time or memory into this.
279	*
280	*
281	* @subsection subsec_pgmPhys_SharePage Sharing a page
282	*
283	* The basic idea is that there there will be a idle priority kernel
284	* thread walking the non-shared VM pages hashing them and looking for
285	* pages with the same checksum. If such pages are found, it will compare
286	* them byte-by-byte to see if they actually are identical. If found to be
287	* identical it will allocate a shared page, copy the content, check that
288	* the page didn't change while doing this, and finally request both the
289	* VMs to use the shared page instead. If the page is all zeros (special
290	* checksum and byte-by-byte check) it will request the VM that owns it
291	* to replace it with the zero page.
292	*
293	* To make this efficient, we will have to make sure not to try share a page
294	* that will change its contents soon. This part requires the most work.
295	* A simple idea would be to request the VM to write monitor the page for
296	* a while to make sure it isn't modified any time soon. Also, it may
297	* make sense to skip pages that are being write monitored since this
298	* information is readily available to the thread if it works on the
299	* per-VM guest memory structures (presently called PGMRAMRANGE).
300	*
301	*
302	* @subsection subsec_pgmPhys_Fragmentation Fragmentation Concerns and Counter Measures
303	*
304	* The pages are organized in allocation chunks in ring-0, this is a necessity
305	* if we wish to have an OS agnostic approach to this whole thing. (On Linux we
306	* could easily work on a page-by-page basis if we liked. Whether this is possible
307	* or efficient on NT I don't quite know.) Fragmentation within these chunks may
308	* become a problem as part of the idea here is that we wish to return memory to
309	* the host system.
310	*
311	* For instance, starting two VMs at the same time, they will both allocate the
312	* guest memory on-demand and if permitted their page allocations will be
313	* intermixed. Shut down one of the two VMs and it will be difficult to return
314	* any memory to the host system because the page allocation for the two VMs are
315	* mixed up in the same allocation chunks.
316	*
317	* To further complicate matters, when pages are freed because they have been
318	* ballooned or become shared/zero the whole idea is that the page is supposed
319	* to be reused by another VM or returned to the host system. This will cause
320	* allocation chunks to contain pages belonging to different VMs and prevent
321	* returning memory to the host when one of those VM shuts down.
322	*
323	* The only way to really deal with this problem is to move pages. This can
324	* either be done at VM shutdown and or by the idle priority worker thread
325	* that will be responsible for finding sharable/zero pages. The mechanisms
326	* involved for coercing a VM to move a page (or to do it for it) will be
327	* the same as when telling it to share/zero a page.
328	*
329	*
330	* @subsection subsec_pgmPhys_Tracking Tracking Structures And Their Cost
331	*
332	* There's a difficult balance between keeping the per-page tracking structures
333	* (global and guest page) easy to use and keeping them from eating too much
334	* memory. We have limited virtual memory resources available when operating in
335	* 32-bit kernel space (on 64-bit there'll it's quite a different story). The
336	* tracking structures will be attemted designed such that we can deal with up
337	* to 32GB of memory on a 32-bit system and essentially unlimited on 64-bit ones.
338	*
339	*
340	* @subsubsection subsubsec_pgmPhys_Tracking_Kernel Kernel Space
341	*
342	* @see pg_GMM
343	*
344	* @subsubsection subsubsec_pgmPhys_Tracking_PerVM Per-VM
345	*
346	* Fixed info is the physical address of the page (HCPhys) and the page id
347	* (described above). Theoretically we'll need 48(-12) bits for the HCPhys part.
348	* Today we've restricting ourselves to 40(-12) bits because this is the current
349	* restrictions of all AMD64 implementations (I think Barcelona will up this
350	* to 48(-12) bits, not that it really matters) and I needed the bits for
351	* tracking mappings of a page. 48-12 = 36. That leaves 28 bits, which means a
352	* decent range for the page id: 2^(28+12) = 1024TB.
353	*
354	* In additions to these, we'll have to keep maintaining the page flags as we
355	* currently do. Although it wouldn't harm to optimize these quite a bit, like
356	* for instance the ROM shouldn't depend on having a write handler installed
357	* in order for it to become read-only. A RO/RW bit should be considered so
358	* that the page syncing code doesn't have to mess about checking multiple
359	* flag combinations (ROM \|\| RW handler \|\| write monitored) in order to
360	* figure out how to setup a shadow PTE. But this of course, is second
361	* priority at present. Current this requires 12 bits, but could probably
362	* be optimized to ~8.
363	*
364	* Then there's the 24 bits used to track which shadow page tables are
365	* currently mapping a page for the purpose of speeding up physical
366	* access handlers, and thereby the page pool cache. More bit for this
367	* purpose wouldn't hurt IIRC.
368	*
369	* Then there is a new bit in which we need to record what kind of page
370	* this is, shared, zero, normal or write-monitored-normal. This'll
371	* require 2 bits. One bit might be needed for indicating whether a
372	* write monitored page has been written to. And yet another one or
373	* two for tracking migration status. 3-4 bits total then.
374	*
375	* Whatever is left will can be used to record the sharabilitiy of a
376	* page. The page checksum will not be stored in the per-VM table as
377	* the idle thread will not be permitted to do modifications to it.
378	* It will instead have to keep its own working set of potentially
379	* shareable pages and their check sums and stuff.
380	*
381	* For the present we'll keep the current packing of the
382	* PGMRAMRANGE::aHCPhys to keep the changes simple, only of course,
383	* we'll have to change it to a struct with a total of 128-bits at
384	* our disposal.
385	*
386	* The initial layout will be like this:
387	* @verbatim
388	RTHCPHYS HCPhys; The current stuff.
389	63:40 Current shadow PT tracking stuff.
390	39:12 The physical page frame number.
391	11:0 The current flags.
392	uint32_t u28PageId : 28; The page id.
393	uint32_t u2State : 2; The page state { zero, shared, normal, write monitored }.
394	uint32_t fWrittenTo : 1; Whether a write monitored page was written to.
395	uint32_t u1Reserved : 1; Reserved for later.
396	uint32_t u32Reserved; Reserved for later, mostly sharing stats.
397	@endverbatim
398	*
399	* The final layout will be something like this:
400	* @verbatim
401	RTHCPHYS HCPhys; The current stuff.
402	63:48 High page id (12+).
403	47:12 The physical page frame number.
404	11:0 Low page id.
405	uint32_t fReadOnly : 1; Whether it's readonly page (rom or monitored in some way).
406	uint32_t u3Type : 3; The page type {RESERVED, MMIO, MMIO2, ROM, shadowed ROM, RAM}.
407	uint32_t u2PhysMon : 2; Physical access handler type {none, read, write, all}.
408	uint32_t u2VirtMon : 2; Virtual access handler type {none, read, write, all}..
409	uint32_t u2State : 2; The page state { zero, shared, normal, write monitored }.
410	uint32_t fWrittenTo : 1; Whether a write monitored page was written to.
411	uint32_t u20Reserved : 20; Reserved for later, mostly sharing stats.
412	uint32_t u32Tracking; The shadow PT tracking stuff, roughly.
413	@endverbatim
414	*
415	* Cost wise, this means we'll double the cost for guest memory. There isn't anyway
416	* around that I'm afraid. It means that the cost of dealing out 32GB of memory
417	* to one or more VMs is: (32GB >> PAGE_SHIFT) * 16 bytes, or 128MBs. Or another
418	* example, the VM heap cost when assigning 1GB to a VM will be: 4MB.
419	*
420	* A couple of cost examples for the total cost per-VM + kernel.
421	* 32-bit Windows and 32-bit linux:
422	* 1GB guest ram, 256K pages: 4MB + 2MB(+) = 6MB
423	* 4GB guest ram, 1M pages: 16MB + 8MB(+) = 24MB
424	* 32GB guest ram, 8M pages: 128MB + 64MB(+) = 192MB
425	* 64-bit Windows and 64-bit linux:
426	* 1GB guest ram, 256K pages: 4MB + 3MB(+) = 7MB
427	* 4GB guest ram, 1M pages: 16MB + 12MB(+) = 28MB
428	* 32GB guest ram, 8M pages: 128MB + 96MB(+) = 224MB
429	*
430	* UPDATE - 2007-09-27:
431	* Will need a ballooned flag/state too because we cannot
432	* trust the guest 100% and reporting the same page as ballooned more
433	* than once will put the GMM off balance.
434	*
435	*
436	* @subsection subsec_pgmPhys_Serializing Serializing Access
437	*
438	* Initially, we'll try a simple scheme:
439	*
440	* - The per-VM RAM tracking structures (PGMRAMRANGE) is only modified
441	* by the EMT thread of that VM while in the pgm critsect.
442	* - Other threads in the VM process that needs to make reliable use of
443	* the per-VM RAM tracking structures will enter the critsect.
444	* - No process external thread or kernel thread will ever try enter
445	* the pgm critical section, as that just won't work.
446	* - The idle thread (and similar threads) doesn't not need 100% reliable
447	* data when performing it tasks as the EMT thread will be the one to
448	* do the actual changes later anyway. So, as long as it only accesses
449	* the main ram range, it can do so by somehow preventing the VM from
450	* being destroyed while it works on it...
451	*
452	* - The over-commitment management, including the allocating/freeing
453	* chunks, is serialized by a ring-0 mutex lock (a fast one since the
454	* more mundane mutex implementation is broken on Linux).
455	* - A separeate mutex is protecting the set of allocation chunks so
456	* that pages can be shared or/and freed up while some other VM is
457	* allocating more chunks. This mutex can be take from under the other
458	* one, but not the otherway around.
459	*
460	*
461	* @subsection subsec_pgmPhys_Request VM Request interface
462	*
463	* When in ring-0 it will become necessary to send requests to a VM so it can
464	* for instance move a page while defragmenting during VM destroy. The idle
465	* thread will make use of this interface to request VMs to setup shared
466	* pages and to perform write monitoring of pages.
467	*
468	* I would propose an interface similar to the current VMReq interface, similar
469	* in that it doesn't require locking and that the one sending the request may
470	* wait for completion if it wishes to. This shouldn't be very difficult to
471	* realize.
472	*
473	* The requests themselves are also pretty simple. They are basically:
474	* -# Check that some precondition is still true.
475	* -# Do the update.
476	* -# Update all shadow page tables involved with the page.
477	*
478	* The 3rd step is identical to what we're already doing when updating a
479	* physical handler, see pgmHandlerPhysicalSetRamFlagsAndFlushShadowPTs.
480	*
481	*
482	*
483	* @section sec_pgmPhys_MappingCaches Mapping Caches
484	*
485	* In order to be able to map in and out memory and to be able to support
486	* guest with more RAM than we've got virtual address space, we'll employing
487	* a mapping cache. There is already a tiny one for GC (see PGMGCDynMapGCPageEx)
488	* and we'll create a similar one for ring-0 unless we decide to setup a dedicate
489	* memory context for the HWACCM execution.
490	*
491	*
492	* @subsection subsec_pgmPhys_MappingCaches_R3 Ring-3
493	*
494	* We've considered implementing the ring-3 mapping cache page based but found
495	* that this was bother some when one had to take into account TLBs+SMP and
496	* portability (missing the necessary APIs on several platforms). There were
497	* also some performance concerns with this approach which hadn't quite been
498	* worked out.
499	*
500	* Instead, we'll be mapping allocation chunks into the VM process. This simplifies
501	* matters greatly quite a bit since we don't need to invent any new ring-0 stuff,
502	* only some minor RTR0MEMOBJ mapping stuff. The main concern here is that mapping
503	* compared to the previous idea is that mapping or unmapping a 1MB chunk is more
504	* costly than a single page, although how much more costly is uncertain. We'll
505	* try address this by using a very big cache, preferably bigger than the actual
506	* VM RAM size if possible. The current VM RAM sizes should give some idea for
507	* 32-bit boxes, while on 64-bit we can probably get away with employing an
508	* unlimited cache.
509	*
510	* The cache have to parts, as already indicated, the ring-3 side and the
511	* ring-0 side.
512	*
513	* The ring-0 will be tied to the page allocator since it will operate on the
514	* memory objects it contains. It will therefore require the first ring-0 mutex
515	* discussed in @ref subsec_pgmPhys_Serializing. We
516	* some double house keeping wrt to who has mapped what I think, since both
517	* VMMR0.r0 and RTR0MemObj will keep track of mapping relataions
518	*
519	* The ring-3 part will be protected by the pgm critsect. For simplicity, we'll
520	* require anyone that desires to do changes to the mapping cache to do that
521	* from within this critsect. Alternatively, we could employ a separate critsect
522	* for serializing changes to the mapping cache as this would reduce potential
523	* contention with other threads accessing mappings unrelated to the changes
524	* that are in process. We can see about this later, contention will show
525	* up in the statistics anyway, so it'll be simple to tell.
526	*
527	* The organization of the ring-3 part will be very much like how the allocation
528	* chunks are organized in ring-0, that is in an AVL tree by chunk id. To avoid
529	* having to walk the tree all the time, we'll have a couple of lookaside entries
530	* like in we do for I/O ports and MMIO in IOM.
531	*
532	* The simplified flow of a PGMPhysRead/Write function:
533	* -# Enter the PGM critsect.
534	* -# Lookup GCPhys in the ram ranges and get the Page ID.
535	* -# Calc the Allocation Chunk ID from the Page ID.
536	* -# Check the lookaside entries and then the AVL tree for the Chunk ID.
537	* If not found in cache:
538	* -# Call ring-0 and request it to be mapped and supply
539	* a chunk to be unmapped if the cache is maxed out already.
540	* -# Insert the new mapping into the AVL tree (id + R3 address).
541	* -# Update the relevant lookaside entry and return the mapping address.
542	* -# Do the read/write according to monitoring flags and everything.
543	* -# Leave the critsect.
544	*
545	*
546	* @section sec_pgmPhys_Fallback Fallback
547	*
548	* Current all the "second tier" hosts will not support the RTR0MemObjAllocPhysNC
549	* API and thus require a fallback.
550	*
551	* So, when RTR0MemObjAllocPhysNC returns VERR_NOT_SUPPORTED the page allocator
552	* will return to the ring-3 caller (and later ring-0) and asking it to seed
553	* the page allocator with some fresh pages (VERR_GMM_SEED_ME). Ring-3 will
554	* then perform an SUPPageAlloc(cbChunk >> PAGE_SHIFT) call and make a
555	* "SeededAllocPages" call to ring-0.
556	*
557	* The first time ring-0 sees the VERR_NOT_SUPPORTED failure it will disable
558	* all page sharing (zero page detection will continue). It will also force
559	* all allocations to come from the VM which seeded the page. Both these
560	* measures are taken to make sure that there will never be any need for
561	* mapping anything into ring-3 - everything will be mapped already.
562	*
563	* Whether we'll continue to use the current MM locked memory management
564	* for this I don't quite know (I'd prefer not to and just ditch that all
565	* togther), we'll see what's simplest to do.
566	*
567	*
568	*
569	* @section sec_pgmPhys_Changes Changes
570	*
571	* Breakdown of the changes involved?
572	*/
573
574	/*******************************************************************************
575	* Header Files *
576	*******************************************************************************/
577	#define LOG_GROUP LOG_GROUP_PGM
578	#include <VBox/dbgf.h>
579	#include <VBox/pgm.h>
580	#include <VBox/cpum.h>
581	#include <VBox/iom.h>
582	#include <VBox/sup.h>
583	#include <VBox/mm.h>
584	#include <VBox/em.h>
585	#include <VBox/stam.h>
586	#include <VBox/rem.h>
587	#include <VBox/dbgf.h>
588	#include <VBox/rem.h>
589	#include <VBox/selm.h>
590	#include <VBox/ssm.h>
591	#include "PGMInternal.h"
592	#include <VBox/vm.h>
593	#include <VBox/dbg.h>
594	#include <VBox/hwaccm.h>
595
596	#include <iprt/assert.h>
597	#include <iprt/alloc.h>
598	#include <iprt/asm.h>
599	#include <iprt/thread.h>
600	#include <iprt/string.h>
601	#ifdef DEBUG_bird
602	# include <iprt/env.h>
603	#endif
604	#include <VBox/param.h>
605	#include <VBox/err.h>
606
607
608	/*******************************************************************************
609	* Defined Constants And Macros *
610	*******************************************************************************/
611	/** Saved state data unit version for 2.2.2 and later. */
612	#define PGM_SAVED_STATE_VERSION 8
613	/** Saved state data unit version for 2.2.0. */
614	#define PGM_SAVED_STATE_VERSION_RR_DESC 7
615	/** Saved state data unit version 2.1.x and earlier. */
616	#define PGM_SAVED_STATE_VERSION_OLD_PHYS_CODE 6
617
618
619	/*******************************************************************************
620	* Internal Functions *
621	*******************************************************************************/
622	static int pgmR3InitPaging(PVM pVM);
623	static void pgmR3InitStats(PVM pVM);
624	static DECLCALLBACK(void) pgmR3PhysInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
625	static DECLCALLBACK(void) pgmR3InfoMode(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
626	static DECLCALLBACK(void) pgmR3InfoCr3(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
627	static DECLCALLBACK(int) pgmR3RelocatePhysHandler(PAVLROGCPHYSNODECORE pNode, void *pvUser);
628	static DECLCALLBACK(int) pgmR3RelocateVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser);
629	static DECLCALLBACK(int) pgmR3RelocateHyperVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser);
630	#ifdef VBOX_STRICT
631	static DECLCALLBACK(void) pgmR3ResetNoMorePhysWritesFlag(PVM pVM, VMSTATE enmState, VMSTATE enmOldState, void *pvUser);
632	#endif
633	static DECLCALLBACK(int) pgmR3Save(PVM pVM, PSSMHANDLE pSSM);
634	static DECLCALLBACK(int) pgmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version);
635	static int pgmR3ModeDataInit(PVM pVM, bool fResolveGCAndR0);
636	static void pgmR3ModeDataSwitch(PVM pVM, PGMMODE enmShw, PGMMODE enmGst);
637	static PGMMODE pgmR3CalcShadowMode(PVM pVM, PGMMODE enmGuestMode, SUPPAGINGMODE enmHostMode, PGMMODE enmShadowMode, VMMSWITCHER *penmSwitcher);
638
639	#ifdef VBOX_WITH_DEBUGGER
640	/** @todo Convert the first two commands to 'info' items. */
641	static DECLCALLBACK(int) pgmR3CmdRam(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
642	static DECLCALLBACK(int) pgmR3CmdMap(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
643	static DECLCALLBACK(int) pgmR3CmdError(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
644	static DECLCALLBACK(int) pgmR3CmdSync(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
645	static DECLCALLBACK(int) pgmR3CmdSyncAlways(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
646	# ifdef VBOX_STRICT
647	static DECLCALLBACK(int) pgmR3CmdAssertCR3(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
648	# endif
649	#endif
650
651
652	/*******************************************************************************
653	* Global Variables *
654	*******************************************************************************/
655	#ifdef VBOX_WITH_DEBUGGER
656	/** Argument descriptors for '.pgmerror' and '.pgmerroroff'. */
657	static const DBGCVARDESC g_aPgmErrorArgs[] =
658	{
659	/* cTimesMin, cTimesMax, enmCategory, fFlags, pszName, pszDescription */
660	{ 0, 1, DBGCVAR_CAT_STRING, 0, "where", "Error injection location." },
661	};
662
663	/** Command descriptors. */
664	static const DBGCCMD g_aCmds[] =
665	{
666	/* pszCmd, cArgsMin, cArgsMax, paArgDesc, cArgDescs, pResultDesc, fFlags, pfnHandler pszSyntax, ....pszDescription */
667	{ "pgmram", 0, 0, NULL, 0, NULL, 0, pgmR3CmdRam, "", "Display the ram ranges." },
668	{ "pgmmap", 0, 0, NULL, 0, NULL, 0, pgmR3CmdMap, "", "Display the mapping ranges." },
669	{ "pgmsync", 0, 0, NULL, 0, NULL, 0, pgmR3CmdSync, "", "Sync the CR3 page." },
670	{ "pgmerror", 0, 1, &g_aPgmErrorArgs[0],1, NULL, 0, pgmR3CmdError, "", "Enables inject runtime of errors into parts of PGM." },
671	{ "pgmerroroff", 0, 1, &g_aPgmErrorArgs[0],1, NULL, 0, pgmR3CmdError, "", "Disables inject runtime errors into parts of PGM." },
672	#ifdef VBOX_STRICT
673	{ "pgmassertcr3", 0, 0, NULL, 0, NULL, 0, pgmR3CmdAssertCR3, "", "Check the shadow CR3 mapping." },
674	#endif
675	{ "pgmsyncalways", 0, 0, NULL, 0, NULL, 0, pgmR3CmdSyncAlways, "", "Toggle permanent CR3 syncing." },
676	};
677	#endif
678
679
680
681
682	/*
683	* Shadow - 32-bit mode
684	*/
685	#define PGM_SHW_TYPE PGM_TYPE_32BIT
686	#define PGM_SHW_NAME(name) PGM_SHW_NAME_32BIT(name)
687	#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_32BIT_STR(name)
688	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_32BIT_STR(name)
689	#include "PGMShw.h"
690
691	/* Guest - real mode */
692	#define PGM_GST_TYPE PGM_TYPE_REAL
693	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
694	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_REAL_STR(name)
695	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
696	#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_REAL(name)
697	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_32BIT_REAL_STR(name)
698	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_32BIT_REAL_STR(name)
699	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_PHYS
700	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_32BIT_PD_PHYS
701	#include "PGMBth.h"
702	#include "PGMGstDefs.h"
703	#include "PGMGst.h"
704	#undef BTH_PGMPOOLKIND_PT_FOR_PT
705	#undef BTH_PGMPOOLKIND_ROOT
706	#undef PGM_BTH_NAME
707	#undef PGM_BTH_NAME_RC_STR
708	#undef PGM_BTH_NAME_R0_STR
709	#undef PGM_GST_TYPE
710	#undef PGM_GST_NAME
711	#undef PGM_GST_NAME_RC_STR
712	#undef PGM_GST_NAME_R0_STR
713
714	/* Guest - protected mode */
715	#define PGM_GST_TYPE PGM_TYPE_PROT
716	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
717	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PROT_STR(name)
718	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
719	#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_PROT(name)
720	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_32BIT_PROT_STR(name)
721	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_32BIT_PROT_STR(name)
722	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_PHYS
723	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_32BIT_PD_PHYS
724	#include "PGMBth.h"
725	#include "PGMGstDefs.h"
726	#include "PGMGst.h"
727	#undef BTH_PGMPOOLKIND_PT_FOR_PT
728	#undef BTH_PGMPOOLKIND_ROOT
729	#undef PGM_BTH_NAME
730	#undef PGM_BTH_NAME_RC_STR
731	#undef PGM_BTH_NAME_R0_STR
732	#undef PGM_GST_TYPE
733	#undef PGM_GST_NAME
734	#undef PGM_GST_NAME_RC_STR
735	#undef PGM_GST_NAME_R0_STR
736
737	/* Guest - 32-bit mode */
738	#define PGM_GST_TYPE PGM_TYPE_32BIT
739	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
740	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_32BIT_STR(name)
741	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
742	#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_32BIT(name)
743	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_32BIT_32BIT_STR(name)
744	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_32BIT_32BIT_STR(name)
745	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT
746	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB
747	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_32BIT_PD
748	#include "PGMBth.h"
749	#include "PGMGstDefs.h"
750	#include "PGMGst.h"
751	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
752	#undef BTH_PGMPOOLKIND_PT_FOR_PT
753	#undef BTH_PGMPOOLKIND_ROOT
754	#undef PGM_BTH_NAME
755	#undef PGM_BTH_NAME_RC_STR
756	#undef PGM_BTH_NAME_R0_STR
757	#undef PGM_GST_TYPE
758	#undef PGM_GST_NAME
759	#undef PGM_GST_NAME_RC_STR
760	#undef PGM_GST_NAME_R0_STR
761
762	#undef PGM_SHW_TYPE
763	#undef PGM_SHW_NAME
764	#undef PGM_SHW_NAME_RC_STR
765	#undef PGM_SHW_NAME_R0_STR
766
767
768	/*
769	* Shadow - PAE mode
770	*/
771	#define PGM_SHW_TYPE PGM_TYPE_PAE
772	#define PGM_SHW_NAME(name) PGM_SHW_NAME_PAE(name)
773	#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_PAE_STR(name)
774	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_PAE_STR(name)
775	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_REAL(name)
776	#include "PGMShw.h"
777
778	/* Guest - real mode */
779	#define PGM_GST_TYPE PGM_TYPE_REAL
780	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
781	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_REAL_STR(name)
782	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
783	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_REAL(name)
784	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_PAE_REAL_STR(name)
785	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_REAL_STR(name)
786	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
787	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT_PHYS
788	#include "PGMGstDefs.h"
789	#include "PGMBth.h"
790	#undef BTH_PGMPOOLKIND_PT_FOR_PT
791	#undef BTH_PGMPOOLKIND_ROOT
792	#undef PGM_BTH_NAME
793	#undef PGM_BTH_NAME_RC_STR
794	#undef PGM_BTH_NAME_R0_STR
795	#undef PGM_GST_TYPE
796	#undef PGM_GST_NAME
797	#undef PGM_GST_NAME_RC_STR
798	#undef PGM_GST_NAME_R0_STR
799
800	/* Guest - protected mode */
801	#define PGM_GST_TYPE PGM_TYPE_PROT
802	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
803	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PROT_STR(name)
804	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
805	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_PROT(name)
806	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_PAE_PROT_STR(name)
807	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_PROT_STR(name)
808	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
809	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT_PHYS
810	#include "PGMGstDefs.h"
811	#include "PGMBth.h"
812	#undef BTH_PGMPOOLKIND_PT_FOR_PT
813	#undef BTH_PGMPOOLKIND_ROOT
814	#undef PGM_BTH_NAME
815	#undef PGM_BTH_NAME_RC_STR
816	#undef PGM_BTH_NAME_R0_STR
817	#undef PGM_GST_TYPE
818	#undef PGM_GST_NAME
819	#undef PGM_GST_NAME_RC_STR
820	#undef PGM_GST_NAME_R0_STR
821
822	/* Guest - 32-bit mode */
823	#define PGM_GST_TYPE PGM_TYPE_32BIT
824	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
825	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_32BIT_STR(name)
826	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
827	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_32BIT(name)
828	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_PAE_32BIT_STR(name)
829	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_32BIT_STR(name)
830	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_32BIT_PT
831	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB
832	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT_FOR_32BIT
833	#include "PGMGstDefs.h"
834	#include "PGMBth.h"
835	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
836	#undef BTH_PGMPOOLKIND_PT_FOR_PT
837	#undef BTH_PGMPOOLKIND_ROOT
838	#undef PGM_BTH_NAME
839	#undef PGM_BTH_NAME_RC_STR
840	#undef PGM_BTH_NAME_R0_STR
841	#undef PGM_GST_TYPE
842	#undef PGM_GST_NAME
843	#undef PGM_GST_NAME_RC_STR
844	#undef PGM_GST_NAME_R0_STR
845
846	/* Guest - PAE mode */
847	#define PGM_GST_TYPE PGM_TYPE_PAE
848	#define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
849	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PAE_STR(name)
850	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PAE_STR(name)
851	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_PAE(name)
852	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_PAE_PAE_STR(name)
853	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_PAE_STR(name)
854	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
855	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
856	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT
857	#include "PGMBth.h"
858	#include "PGMGstDefs.h"
859	#include "PGMGst.h"
860	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
861	#undef BTH_PGMPOOLKIND_PT_FOR_PT
862	#undef BTH_PGMPOOLKIND_ROOT
863	#undef PGM_BTH_NAME
864	#undef PGM_BTH_NAME_RC_STR
865	#undef PGM_BTH_NAME_R0_STR
866	#undef PGM_GST_TYPE
867	#undef PGM_GST_NAME
868	#undef PGM_GST_NAME_RC_STR
869	#undef PGM_GST_NAME_R0_STR
870
871	#undef PGM_SHW_TYPE
872	#undef PGM_SHW_NAME
873	#undef PGM_SHW_NAME_RC_STR
874	#undef PGM_SHW_NAME_R0_STR
875
876
877	/*
878	* Shadow - AMD64 mode
879	*/
880	#define PGM_SHW_TYPE PGM_TYPE_AMD64
881	#define PGM_SHW_NAME(name) PGM_SHW_NAME_AMD64(name)
882	#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_AMD64_STR(name)
883	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_AMD64_STR(name)
884	#include "PGMShw.h"
885
886	#ifdef VBOX_WITH_64_BITS_GUESTS
887	/* Guest - AMD64 mode */
888	# define PGM_GST_TYPE PGM_TYPE_AMD64
889	# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
890	# define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_AMD64_STR(name)
891	# define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_AMD64_STR(name)
892	# define PGM_BTH_NAME(name) PGM_BTH_NAME_AMD64_AMD64(name)
893	# define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_AMD64_AMD64_STR(name)
894	# define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_AMD64_AMD64_STR(name)
895	# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
896	# define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
897	# define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_64BIT_PML4
898	# include "PGMBth.h"
899	# include "PGMGstDefs.h"
900	# include "PGMGst.h"
901	# undef BTH_PGMPOOLKIND_PT_FOR_BIG
902	# undef BTH_PGMPOOLKIND_PT_FOR_PT
903	# undef BTH_PGMPOOLKIND_ROOT
904	# undef PGM_BTH_NAME
905	# undef PGM_BTH_NAME_RC_STR
906	# undef PGM_BTH_NAME_R0_STR
907	# undef PGM_GST_TYPE
908	# undef PGM_GST_NAME
909	# undef PGM_GST_NAME_RC_STR
910	# undef PGM_GST_NAME_R0_STR
911	#endif /* VBOX_WITH_64_BITS_GUESTS */
912
913	#undef PGM_SHW_TYPE
914	#undef PGM_SHW_NAME
915	#undef PGM_SHW_NAME_RC_STR
916	#undef PGM_SHW_NAME_R0_STR
917
918
919	/*
920	* Shadow - Nested paging mode
921	*/
922	#define PGM_SHW_TYPE PGM_TYPE_NESTED
923	#define PGM_SHW_NAME(name) PGM_SHW_NAME_NESTED(name)
924	#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_NESTED_STR(name)
925	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_NESTED_STR(name)
926	#include "PGMShw.h"
927
928	/* Guest - real mode */
929	#define PGM_GST_TYPE PGM_TYPE_REAL
930	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
931	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_REAL_STR(name)
932	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
933	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_REAL(name)
934	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_REAL_STR(name)
935	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_REAL_STR(name)
936	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
937	#include "PGMGstDefs.h"
938	#include "PGMBth.h"
939	#undef BTH_PGMPOOLKIND_PT_FOR_PT
940	#undef PGM_BTH_NAME
941	#undef PGM_BTH_NAME_RC_STR
942	#undef PGM_BTH_NAME_R0_STR
943	#undef PGM_GST_TYPE
944	#undef PGM_GST_NAME
945	#undef PGM_GST_NAME_RC_STR
946	#undef PGM_GST_NAME_R0_STR
947
948	/* Guest - protected mode */
949	#define PGM_GST_TYPE PGM_TYPE_PROT
950	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
951	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PROT_STR(name)
952	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
953	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_PROT(name)
954	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_PROT_STR(name)
955	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_PROT_STR(name)
956	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
957	#include "PGMGstDefs.h"
958	#include "PGMBth.h"
959	#undef BTH_PGMPOOLKIND_PT_FOR_PT
960	#undef PGM_BTH_NAME
961	#undef PGM_BTH_NAME_RC_STR
962	#undef PGM_BTH_NAME_R0_STR
963	#undef PGM_GST_TYPE
964	#undef PGM_GST_NAME
965	#undef PGM_GST_NAME_RC_STR
966	#undef PGM_GST_NAME_R0_STR
967
968	/* Guest - 32-bit mode */
969	#define PGM_GST_TYPE PGM_TYPE_32BIT
970	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
971	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_32BIT_STR(name)
972	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
973	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_32BIT(name)
974	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_32BIT_STR(name)
975	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_32BIT_STR(name)
976	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_32BIT_PT
977	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB
978	#include "PGMGstDefs.h"
979	#include "PGMBth.h"
980	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
981	#undef BTH_PGMPOOLKIND_PT_FOR_PT
982	#undef PGM_BTH_NAME
983	#undef PGM_BTH_NAME_RC_STR
984	#undef PGM_BTH_NAME_R0_STR
985	#undef PGM_GST_TYPE
986	#undef PGM_GST_NAME
987	#undef PGM_GST_NAME_RC_STR
988	#undef PGM_GST_NAME_R0_STR
989
990	/* Guest - PAE mode */
991	#define PGM_GST_TYPE PGM_TYPE_PAE
992	#define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
993	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PAE_STR(name)
994	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PAE_STR(name)
995	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_PAE(name)
996	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_PAE_STR(name)
997	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_PAE_STR(name)
998	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
999	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
1000	#include "PGMGstDefs.h"
1001	#include "PGMBth.h"
1002	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
1003	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1004	#undef PGM_BTH_NAME
1005	#undef PGM_BTH_NAME_RC_STR
1006	#undef PGM_BTH_NAME_R0_STR
1007	#undef PGM_GST_TYPE
1008	#undef PGM_GST_NAME
1009	#undef PGM_GST_NAME_RC_STR
1010	#undef PGM_GST_NAME_R0_STR
1011
1012	#ifdef VBOX_WITH_64_BITS_GUESTS
1013	/* Guest - AMD64 mode */
1014	# define PGM_GST_TYPE PGM_TYPE_AMD64
1015	# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
1016	# define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_AMD64_STR(name)
1017	# define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_AMD64_STR(name)
1018	# define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_AMD64(name)
1019	# define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_AMD64_STR(name)
1020	# define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_AMD64_STR(name)
1021	# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
1022	# define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
1023	# include "PGMGstDefs.h"
1024	# include "PGMBth.h"
1025	# undef BTH_PGMPOOLKIND_PT_FOR_BIG
1026	# undef BTH_PGMPOOLKIND_PT_FOR_PT
1027	# undef PGM_BTH_NAME
1028	# undef PGM_BTH_NAME_RC_STR
1029	# undef PGM_BTH_NAME_R0_STR
1030	# undef PGM_GST_TYPE
1031	# undef PGM_GST_NAME
1032	# undef PGM_GST_NAME_RC_STR
1033	# undef PGM_GST_NAME_R0_STR
1034	#endif /* VBOX_WITH_64_BITS_GUESTS */
1035
1036	#undef PGM_SHW_TYPE
1037	#undef PGM_SHW_NAME
1038	#undef PGM_SHW_NAME_RC_STR
1039	#undef PGM_SHW_NAME_R0_STR
1040
1041
1042	/*
1043	* Shadow - EPT
1044	*/
1045	#define PGM_SHW_TYPE PGM_TYPE_EPT
1046	#define PGM_SHW_NAME(name) PGM_SHW_NAME_EPT(name)
1047	#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_EPT_STR(name)
1048	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_EPT_STR(name)
1049	#include "PGMShw.h"
1050
1051	/* Guest - real mode */
1052	#define PGM_GST_TYPE PGM_TYPE_REAL
1053	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
1054	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_REAL_STR(name)
1055	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
1056	#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_REAL(name)
1057	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_REAL_STR(name)
1058	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_REAL_STR(name)
1059	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
1060	#include "PGMGstDefs.h"
1061	#include "PGMBth.h"
1062	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1063	#undef PGM_BTH_NAME
1064	#undef PGM_BTH_NAME_RC_STR
1065	#undef PGM_BTH_NAME_R0_STR
1066	#undef PGM_GST_TYPE
1067	#undef PGM_GST_NAME
1068	#undef PGM_GST_NAME_RC_STR
1069	#undef PGM_GST_NAME_R0_STR
1070
1071	/* Guest - protected mode */
1072	#define PGM_GST_TYPE PGM_TYPE_PROT
1073	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
1074	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PROT_STR(name)
1075	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
1076	#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_PROT(name)
1077	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_PROT_STR(name)
1078	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_PROT_STR(name)
1079	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
1080	#include "PGMGstDefs.h"
1081	#include "PGMBth.h"
1082	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1083	#undef PGM_BTH_NAME
1084	#undef PGM_BTH_NAME_RC_STR
1085	#undef PGM_BTH_NAME_R0_STR
1086	#undef PGM_GST_TYPE
1087	#undef PGM_GST_NAME
1088	#undef PGM_GST_NAME_RC_STR
1089	#undef PGM_GST_NAME_R0_STR
1090
1091	/* Guest - 32-bit mode */
1092	#define PGM_GST_TYPE PGM_TYPE_32BIT
1093	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
1094	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_32BIT_STR(name)
1095	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
1096	#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_32BIT(name)
1097	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_32BIT_STR(name)
1098	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_32BIT_STR(name)
1099	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_32BIT_PT
1100	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB
1101	#include "PGMGstDefs.h"
1102	#include "PGMBth.h"
1103	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
1104	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1105	#undef PGM_BTH_NAME
1106	#undef PGM_BTH_NAME_RC_STR
1107	#undef PGM_BTH_NAME_R0_STR
1108	#undef PGM_GST_TYPE
1109	#undef PGM_GST_NAME
1110	#undef PGM_GST_NAME_RC_STR
1111	#undef PGM_GST_NAME_R0_STR
1112
1113	/* Guest - PAE mode */
1114	#define PGM_GST_TYPE PGM_TYPE_PAE
1115	#define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
1116	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PAE_STR(name)
1117	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PAE_STR(name)
1118	#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_PAE(name)
1119	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_PAE_STR(name)
1120	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_PAE_STR(name)
1121	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
1122	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
1123	#include "PGMGstDefs.h"
1124	#include "PGMBth.h"
1125	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
1126	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1127	#undef PGM_BTH_NAME
1128	#undef PGM_BTH_NAME_RC_STR
1129	#undef PGM_BTH_NAME_R0_STR
1130	#undef PGM_GST_TYPE
1131	#undef PGM_GST_NAME
1132	#undef PGM_GST_NAME_RC_STR
1133	#undef PGM_GST_NAME_R0_STR
1134
1135	#ifdef VBOX_WITH_64_BITS_GUESTS
1136	/* Guest - AMD64 mode */
1137	# define PGM_GST_TYPE PGM_TYPE_AMD64
1138	# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
1139	# define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_AMD64_STR(name)
1140	# define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_AMD64_STR(name)
1141	# define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_AMD64(name)
1142	# define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_AMD64_STR(name)
1143	# define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_AMD64_STR(name)
1144	# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
1145	# define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
1146	# include "PGMGstDefs.h"
1147	# include "PGMBth.h"
1148	# undef BTH_PGMPOOLKIND_PT_FOR_BIG
1149	# undef BTH_PGMPOOLKIND_PT_FOR_PT
1150	# undef PGM_BTH_NAME
1151	# undef PGM_BTH_NAME_RC_STR
1152	# undef PGM_BTH_NAME_R0_STR
1153	# undef PGM_GST_TYPE
1154	# undef PGM_GST_NAME
1155	# undef PGM_GST_NAME_RC_STR
1156	# undef PGM_GST_NAME_R0_STR
1157	#endif /* VBOX_WITH_64_BITS_GUESTS */
1158
1159	#undef PGM_SHW_TYPE
1160	#undef PGM_SHW_NAME
1161	#undef PGM_SHW_NAME_RC_STR
1162	#undef PGM_SHW_NAME_R0_STR
1163
1164
1165
1166	/**
1167	* Initiates the paging of VM.
1168	*
1169	* @returns VBox status code.
1170	* @param pVM Pointer to VM structure.
1171	*/
1172	VMMR3DECL(int) PGMR3Init(PVM pVM)
1173	{
1174	LogFlow(("PGMR3Init:\n"));
1175	PCFGMNODE pCfgPGM = CFGMR3GetChild(CFGMR3GetRoot(pVM), "/PGM");
1176	int rc;
1177
1178	/*
1179	* Assert alignment and sizes.
1180	*/
1181	AssertRelease(sizeof(pVM->pgm.s) <= sizeof(pVM->pgm.padding));
1182
1183	/*
1184	* Init the structure.
1185	*/
1186	pVM->pgm.s.offVM = RT_OFFSETOF(VM, pgm.s);
1187	pVM->pgm.s.offVCpu = RT_OFFSETOF(VMCPU, pgm.s);
1188	pVM->pgm.s.enmShadowMode = PGMMODE_INVALID;
1189	pVM->pgm.s.enmGuestMode = PGMMODE_INVALID;
1190	pVM->pgm.s.enmHostMode = SUPPAGINGMODE_INVALID;
1191	pVM->pgm.s.GCPhysCR3 = NIL_RTGCPHYS;
1192	pVM->pgm.s.GCPtrPrevRamRangeMapping = MM_HYPER_AREA_ADDRESS;
1193	pVM->pgm.s.fA20Enabled = true;
1194	pVM->pgm.s.GCPhys4MBPSEMask = RT_BIT_64(32) - 1; /* default; checked later */
1195	pVM->pgm.s.pGstPaePdptR3 = NULL;
1196	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
1197	pVM->pgm.s.pGstPaePdptR0 = NIL_RTR0PTR;
1198	#endif
1199	pVM->pgm.s.pGstPaePdptRC = NIL_RTRCPTR;
1200	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.apGstPaePDsR3); i++)
1201	{
1202	pVM->pgm.s.apGstPaePDsR3[i] = NULL;
1203	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
1204	pVM->pgm.s.apGstPaePDsR0[i] = NIL_RTR0PTR;
1205	#endif
1206	pVM->pgm.s.apGstPaePDsRC[i] = NIL_RTRCPTR;
1207	pVM->pgm.s.aGCPhysGstPaePDs[i] = NIL_RTGCPHYS;
1208	pVM->pgm.s.aGCPhysGstPaePDsMonitored[i] = NIL_RTGCPHYS;
1209	}
1210
1211	rc = CFGMR3QueryBoolDef(CFGMR3GetRoot(pVM), "RamPreAlloc", &pVM->pgm.s.fRamPreAlloc,
1212	#ifdef VBOX_WITH_PREALLOC_RAM_BY_DEFAULT
1213	true
1214	#else
1215	false
1216	#endif
1217	);
1218	AssertLogRelRCReturn(rc, rc);
1219
1220	#if HC_ARCH_BITS == 64 \|\| 1 /** @todo 4GB/32-bit: remove \|\| 1 later and adjust the limit. */
1221	rc = CFGMR3QueryU32Def(pCfgPGM, "MaxRing3Chunks", &pVM->pgm.s.ChunkR3Map.cMax, UINT32_MAX);
1222	#else
1223	rc = CFGMR3QueryU32Def(pCfgPGM, "MaxRing3Chunks", &pVM->pgm.s.ChunkR3Map.cMax, _1G / GMM_CHUNK_SIZE);
1224	#endif
1225	AssertLogRelRCReturn(rc, rc);
1226	for (uint32_t i = 0; i < RT_ELEMENTS(pVM->pgm.s.ChunkR3Map.Tlb.aEntries); i++)
1227	pVM->pgm.s.ChunkR3Map.Tlb.aEntries[i].idChunk = NIL_GMM_CHUNKID;
1228
1229	/*
1230	* Get the configured RAM size - to estimate saved state size.
1231	*/
1232	uint64_t cbRam;
1233	rc = CFGMR3QueryU64(CFGMR3GetRoot(pVM), "RamSize", &cbRam);
1234	if (rc == VERR_CFGM_VALUE_NOT_FOUND)
1235	cbRam = 0;
1236	else if (RT_SUCCESS(rc))
1237	{
1238	if (cbRam < PAGE_SIZE)
1239	cbRam = 0;
1240	cbRam = RT_ALIGN_64(cbRam, PAGE_SIZE);
1241	}
1242	else
1243	{
1244	AssertMsgFailed(("Configuration error: Failed to query integer \"RamSize\", rc=%Rrc.\n", rc));
1245	return rc;
1246	}
1247
1248	/*
1249	* Register callbacks, string formatters and the saved state data unit.
1250	*/
1251	#ifdef VBOX_STRICT
1252	VMR3AtStateRegister(pVM, pgmR3ResetNoMorePhysWritesFlag, NULL);
1253	#endif
1254	PGMRegisterStringFormatTypes();
1255
1256	rc = SSMR3RegisterInternal(pVM, "pgm", 1, PGM_SAVED_STATE_VERSION, (size_t)cbRam + sizeof(PGM),
1257	NULL, pgmR3Save, NULL,
1258	NULL, pgmR3Load, NULL);
1259	if (RT_FAILURE(rc))
1260	return rc;
1261
1262	/*
1263	* Initialize the PGM critical section and flush the phys TLBs
1264	*/
1265	rc = PDMR3CritSectInit(pVM, &pVM->pgm.s.CritSect, "PGM");
1266	AssertRCReturn(rc, rc);
1267
1268	PGMR3PhysChunkInvalidateTLB(pVM);
1269	PGMPhysInvalidatePageR3MapTLB(pVM);
1270	PGMPhysInvalidatePageR0MapTLB(pVM);
1271	PGMPhysInvalidatePageGCMapTLB(pVM);
1272
1273	/*
1274	* For the time being we sport a full set of handy pages in addition to the base
1275	* memory to simplify things.
1276	*/
1277	rc = MMR3ReserveHandyPages(pVM, RT_ELEMENTS(pVM->pgm.s.aHandyPages)); /** @todo this should be changed to PGM_HANDY_PAGES_MIN but this needs proper testing... */
1278	AssertRCReturn(rc, rc);
1279
1280	/*
1281	* Trees
1282	*/
1283	rc = MMHyperAlloc(pVM, sizeof(PGMTREES), 0, MM_TAG_PGM, (void **)&pVM->pgm.s.pTreesR3);
1284	if (RT_SUCCESS(rc))
1285	{
1286	pVM->pgm.s.pTreesR0 = MMHyperR3ToR0(pVM, pVM->pgm.s.pTreesR3);
1287	pVM->pgm.s.pTreesRC = MMHyperR3ToRC(pVM, pVM->pgm.s.pTreesR3);
1288
1289	/*
1290	* Alocate the zero page.
1291	*/
1292	rc = MMHyperAlloc(pVM, PAGE_SIZE, PAGE_SIZE, MM_TAG_PGM, &pVM->pgm.s.pvZeroPgR3);
1293	}
1294	if (RT_SUCCESS(rc))
1295	{
1296	pVM->pgm.s.pvZeroPgRC = MMHyperR3ToRC(pVM, pVM->pgm.s.pvZeroPgR3);
1297	pVM->pgm.s.pvZeroPgR0 = MMHyperR3ToR0(pVM, pVM->pgm.s.pvZeroPgR3);
1298	pVM->pgm.s.HCPhysZeroPg = MMR3HyperHCVirt2HCPhys(pVM, pVM->pgm.s.pvZeroPgR3);
1299	AssertRelease(pVM->pgm.s.HCPhysZeroPg != NIL_RTHCPHYS);
1300
1301	/*
1302	* Init the paging.
1303	*/
1304	rc = pgmR3InitPaging(pVM);
1305	}
1306	if (RT_SUCCESS(rc))
1307	{
1308	/*
1309	* Init the page pool.
1310	*/
1311	rc = pgmR3PoolInit(pVM);
1312	}
1313	if (RT_SUCCESS(rc))
1314	rc = PGMR3ChangeMode(pVM, PGMMODE_REAL);
1315
1316	if (RT_SUCCESS(rc))
1317	{
1318	/*
1319	* Info & statistics
1320	*/
1321	DBGFR3InfoRegisterInternal(pVM, "mode",
1322	"Shows the current paging mode. "
1323	"Recognizes 'all', 'guest', 'shadow' and 'host' as arguments, defaulting to 'all' if nothing's given.",
1324	pgmR3InfoMode);
1325	DBGFR3InfoRegisterInternal(pVM, "pgmcr3",
1326	"Dumps all the entries in the top level paging table. No arguments.",
1327	pgmR3InfoCr3);
1328	DBGFR3InfoRegisterInternal(pVM, "phys",
1329	"Dumps all the physical address ranges. No arguments.",
1330	pgmR3PhysInfo);
1331	DBGFR3InfoRegisterInternal(pVM, "handlers",
1332	"Dumps physical, virtual and hyper virtual handlers. "
1333	"Pass 'phys', 'virt', 'hyper' as argument if only one kind is wanted."
1334	"Add 'nost' if the statistics are unwanted, use together with 'all' or explicit selection.",
1335	pgmR3InfoHandlers);
1336	DBGFR3InfoRegisterInternal(pVM, "mappings",
1337	"Dumps guest mappings.",
1338	pgmR3MapInfo);
1339
1340	pgmR3InitStats(pVM);
1341
1342	#ifdef VBOX_WITH_DEBUGGER
1343	/*
1344	* Debugger commands.
1345	*/
1346	static bool s_fRegisteredCmds = false;
1347	if (!s_fRegisteredCmds)
1348	{
1349	int rc = DBGCRegisterCommands(&g_aCmds[0], RT_ELEMENTS(g_aCmds));
1350	if (RT_SUCCESS(rc))
1351	s_fRegisteredCmds = true;
1352	}
1353	#endif
1354	return VINF_SUCCESS;
1355	}
1356
1357	/* Almost no cleanup necessary, MM frees all memory. */
1358	PDMR3CritSectDelete(&pVM->pgm.s.CritSect);
1359
1360	return rc;
1361	}
1362
1363
1364	/**
1365	* Initializes the per-VCPU PGM.
1366	*
1367	* @returns VBox status code.
1368	* @param pVM The VM to operate on.
1369	*/
1370	VMMR3DECL(int) PGMR3InitCPU(PVM pVM)
1371	{
1372	LogFlow(("PGMR3InitCPU\n"));
1373	return VINF_SUCCESS;
1374	}
1375
1376
1377	/**
1378	* Init paging.
1379	*
1380	* Since we need to check what mode the host is operating in before we can choose
1381	* the right paging functions for the host we have to delay this until R0 has
1382	* been initialized.
1383	*
1384	* @returns VBox status code.
1385	* @param pVM VM handle.
1386	*/
1387	static int pgmR3InitPaging(PVM pVM)
1388	{
1389	/*
1390	* Force a recalculation of modes and switcher so everyone gets notified.
1391	*/
1392	pVM->pgm.s.enmShadowMode = PGMMODE_INVALID;
1393	pVM->pgm.s.enmGuestMode = PGMMODE_INVALID;
1394	pVM->pgm.s.enmHostMode = SUPPAGINGMODE_INVALID;
1395
1396	/*
1397	* Allocate static mapping space for whatever the cr3 register
1398	* points to and in the case of PAE mode to the 4 PDs.
1399	*/
1400	int rc = MMR3HyperReserve(pVM, PAGE_SIZE * 5, "CR3 mapping", &pVM->pgm.s.GCPtrCR3Mapping);
1401	if (RT_FAILURE(rc))
1402	{
1403	AssertMsgFailed(("Failed to reserve two pages for cr mapping in HMA, rc=%Rrc\n", rc));
1404	return rc;
1405	}
1406	MMR3HyperReserve(pVM, PAGE_SIZE, "fence", NULL);
1407
1408	/*
1409	* Allocate pages for the three possible intermediate contexts
1410	* (AMD64, PAE and plain 32-Bit). We maintain all three contexts
1411	* for the sake of simplicity. The AMD64 uses the PAE for the
1412	* lower levels, making the total number of pages 11 (3 + 7 + 1).
1413	*
1414	* We assume that two page tables will be enought for the core code
1415	* mappings (HC virtual and identity).
1416	*/
1417	pVM->pgm.s.pInterPD = (PX86PD)MMR3PageAllocLow(pVM);
1418	pVM->pgm.s.apInterPTs[0] = (PX86PT)MMR3PageAllocLow(pVM);
1419	pVM->pgm.s.apInterPTs[1] = (PX86PT)MMR3PageAllocLow(pVM);
1420	pVM->pgm.s.apInterPaePTs[0] = (PX86PTPAE)MMR3PageAlloc(pVM);
1421	pVM->pgm.s.apInterPaePTs[1] = (PX86PTPAE)MMR3PageAlloc(pVM);
1422	pVM->pgm.s.apInterPaePDs[0] = (PX86PDPAE)MMR3PageAlloc(pVM);
1423	pVM->pgm.s.apInterPaePDs[1] = (PX86PDPAE)MMR3PageAlloc(pVM);
1424	pVM->pgm.s.apInterPaePDs[2] = (PX86PDPAE)MMR3PageAlloc(pVM);
1425	pVM->pgm.s.apInterPaePDs[3] = (PX86PDPAE)MMR3PageAlloc(pVM);
1426	pVM->pgm.s.pInterPaePDPT = (PX86PDPT)MMR3PageAllocLow(pVM);
1427	pVM->pgm.s.pInterPaePDPT64 = (PX86PDPT)MMR3PageAllocLow(pVM);
1428	pVM->pgm.s.pInterPaePML4 = (PX86PML4)MMR3PageAllocLow(pVM);
1429	if ( !pVM->pgm.s.pInterPD
1430	\|\| !pVM->pgm.s.apInterPTs[0]
1431	\|\| !pVM->pgm.s.apInterPTs[1]
1432	\|\| !pVM->pgm.s.apInterPaePTs[0]
1433	\|\| !pVM->pgm.s.apInterPaePTs[1]
1434	\|\| !pVM->pgm.s.apInterPaePDs[0]
1435	\|\| !pVM->pgm.s.apInterPaePDs[1]
1436	\|\| !pVM->pgm.s.apInterPaePDs[2]
1437	\|\| !pVM->pgm.s.apInterPaePDs[3]
1438	\|\| !pVM->pgm.s.pInterPaePDPT
1439	\|\| !pVM->pgm.s.pInterPaePDPT64
1440	\|\| !pVM->pgm.s.pInterPaePML4)
1441	{
1442	AssertMsgFailed(("Failed to allocate pages for the intermediate context!\n"));
1443	return VERR_NO_PAGE_MEMORY;
1444	}
1445
1446	pVM->pgm.s.HCPhysInterPD = MMPage2Phys(pVM, pVM->pgm.s.pInterPD);
1447	AssertRelease(pVM->pgm.s.HCPhysInterPD != NIL_RTHCPHYS && !(pVM->pgm.s.HCPhysInterPD & PAGE_OFFSET_MASK));
1448	pVM->pgm.s.HCPhysInterPaePDPT = MMPage2Phys(pVM, pVM->pgm.s.pInterPaePDPT);
1449	AssertRelease(pVM->pgm.s.HCPhysInterPaePDPT != NIL_RTHCPHYS && !(pVM->pgm.s.HCPhysInterPaePDPT & PAGE_OFFSET_MASK));
1450	pVM->pgm.s.HCPhysInterPaePML4 = MMPage2Phys(pVM, pVM->pgm.s.pInterPaePML4);
1451	AssertRelease(pVM->pgm.s.HCPhysInterPaePML4 != NIL_RTHCPHYS && !(pVM->pgm.s.HCPhysInterPaePML4 & PAGE_OFFSET_MASK) && pVM->pgm.s.HCPhysInterPaePML4 < 0xffffffff);
1452
1453	/*
1454	* Initialize the pages, setting up the PML4 and PDPT for repetitive 4GB action.
1455	*/
1456	ASMMemZeroPage(pVM->pgm.s.pInterPD);
1457	ASMMemZeroPage(pVM->pgm.s.apInterPTs[0]);
1458	ASMMemZeroPage(pVM->pgm.s.apInterPTs[1]);
1459
1460	ASMMemZeroPage(pVM->pgm.s.apInterPaePTs[0]);
1461	ASMMemZeroPage(pVM->pgm.s.apInterPaePTs[1]);
1462
1463	ASMMemZeroPage(pVM->pgm.s.pInterPaePDPT);
1464	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.apInterPaePDs); i++)
1465	{
1466	ASMMemZeroPage(pVM->pgm.s.apInterPaePDs[i]);
1467	pVM->pgm.s.pInterPaePDPT->a[i].u = X86_PDPE_P \| PGM_PLXFLAGS_PERMANENT
1468	\| MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[i]);
1469	}
1470
1471	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.pInterPaePDPT64->a); i++)
1472	{
1473	const unsigned iPD = i % RT_ELEMENTS(pVM->pgm.s.apInterPaePDs);
1474	pVM->pgm.s.pInterPaePDPT64->a[i].u = X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_A \| PGM_PLXFLAGS_PERMANENT
1475	\| MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[iPD]);
1476	}
1477
1478	RTHCPHYS HCPhysInterPaePDPT64 = MMPage2Phys(pVM, pVM->pgm.s.pInterPaePDPT64);
1479	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.pInterPaePML4->a); i++)
1480	pVM->pgm.s.pInterPaePML4->a[i].u = X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_A \| PGM_PLXFLAGS_PERMANENT
1481	\| HCPhysInterPaePDPT64;
1482
1483	/*
1484	* Initialize paging workers and mode from current host mode
1485	* and the guest running in real mode.
1486	*/
1487	pVM->pgm.s.enmHostMode = SUPGetPagingMode();
1488	switch (pVM->pgm.s.enmHostMode)
1489	{
1490	case SUPPAGINGMODE_32_BIT:
1491	case SUPPAGINGMODE_32_BIT_GLOBAL:
1492	case SUPPAGINGMODE_PAE:
1493	case SUPPAGINGMODE_PAE_GLOBAL:
1494	case SUPPAGINGMODE_PAE_NX:
1495	case SUPPAGINGMODE_PAE_GLOBAL_NX:
1496	break;
1497
1498	case SUPPAGINGMODE_AMD64:
1499	case SUPPAGINGMODE_AMD64_GLOBAL:
1500	case SUPPAGINGMODE_AMD64_NX:
1501	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
1502	#ifndef VBOX_WITH_HYBRID_32BIT_KERNEL
1503	if (ARCH_BITS != 64)
1504	{
1505	AssertMsgFailed(("Host mode %d (64-bit) is not supported by non-64bit builds\n", pVM->pgm.s.enmHostMode));
1506	LogRel(("Host mode %d (64-bit) is not supported by non-64bit builds\n", pVM->pgm.s.enmHostMode));
1507	return VERR_PGM_UNSUPPORTED_HOST_PAGING_MODE;
1508	}
1509	#endif
1510	break;
1511	default:
1512	AssertMsgFailed(("Host mode %d is not supported\n", pVM->pgm.s.enmHostMode));
1513	return VERR_PGM_UNSUPPORTED_HOST_PAGING_MODE;
1514	}
1515	rc = pgmR3ModeDataInit(pVM, false /* don't resolve GC and R0 syms yet */);
1516	if (RT_SUCCESS(rc))
1517	{
1518	LogFlow(("pgmR3InitPaging: returns successfully\n"));
1519	#if HC_ARCH_BITS == 64
1520	LogRel(("Debug: HCPhysInterPD=%RHp HCPhysInterPaePDPT=%RHp HCPhysInterPaePML4=%RHp\n",
1521	pVM->pgm.s.HCPhysInterPD, pVM->pgm.s.HCPhysInterPaePDPT, pVM->pgm.s.HCPhysInterPaePML4));
1522	LogRel(("Debug: apInterPTs={%RHp,%RHp} apInterPaePTs={%RHp,%RHp} apInterPaePDs={%RHp,%RHp,%RHp,%RHp} pInterPaePDPT64=%RHp\n",
1523	MMPage2Phys(pVM, pVM->pgm.s.apInterPTs[0]), MMPage2Phys(pVM, pVM->pgm.s.apInterPTs[1]),
1524	MMPage2Phys(pVM, pVM->pgm.s.apInterPaePTs[0]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePTs[1]),
1525	MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[0]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[1]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[2]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[3]),
1526	MMPage2Phys(pVM, pVM->pgm.s.pInterPaePDPT64)));
1527	#endif
1528
1529	return VINF_SUCCESS;
1530	}
1531
1532	LogFlow(("pgmR3InitPaging: returns %Rrc\n", rc));
1533	return rc;
1534	}
1535
1536
1537	/**
1538	* Init statistics
1539	*/
1540	static void pgmR3InitStats(PVM pVM)
1541	{
1542	PPGM pPGM = &pVM->pgm.s;
1543	unsigned i;
1544
1545	/* Common - misc variables */
1546	STAM_REL_REG(pVM, &pPGM->cAllPages, STAMTYPE_U32, "/PGM/Page/cAllPages", STAMUNIT_OCCURENCES, "The total number of pages.");
1547	STAM_REL_REG(pVM, &pPGM->cPrivatePages, STAMTYPE_U32, "/PGM/Page/cPrivatePages", STAMUNIT_OCCURENCES, "The number of private pages.");
1548	STAM_REL_REG(pVM, &pPGM->cSharedPages, STAMTYPE_U32, "/PGM/Page/cSharedPages", STAMUNIT_OCCURENCES, "The number of shared pages.");
1549	STAM_REL_REG(pVM, &pPGM->cZeroPages, STAMTYPE_U32, "/PGM/Page/cZeroPages", STAMUNIT_OCCURENCES, "The number of zero backed pages.");
1550	STAM_REL_REG(pVM, &pPGM->cHandyPages, STAMTYPE_U32, "/PGM/Page/cHandyPages", STAMUNIT_OCCURENCES, "The number of handy pages (not included in cAllPages).");
1551	STAM_REL_REG(pVM, &pPGM->cGuestModeChanges, STAMTYPE_COUNTER, "/PGM/cGuestModeChanges", STAMUNIT_OCCURENCES, "Number of guest mode changes.");
1552	STAM_REL_REG(pVM, &pPGM->cRelocations, STAMTYPE_COUNTER, "/PGM/cRelocations", STAMUNIT_OCCURENCES, "Number of hypervisor relocations.");
1553	STAM_REL_REG(pVM, &pPGM->ChunkR3Map.c, STAMTYPE_U32, "/PGM/ChunkR3Map/c", STAMUNIT_OCCURENCES, "Number of mapped chunks.");
1554	STAM_REL_REG(pVM, &pPGM->ChunkR3Map.cMax, STAMTYPE_U32, "/PGM/ChunkR3Map/cMax", STAMUNIT_OCCURENCES, "Maximum number of mapped chunks.");
1555
1556	/*
1557	* Note! The layout below matches the member layout exactly!
1558	*/
1559
1560	#ifdef VBOX_WITH_STATISTICS
1561	/* Common - stats */
1562	# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
1563	STAM_REG(pVM, &pPGM->StatTrackVirgin, STAMTYPE_COUNTER, "/PGM/Track/Virgin", STAMUNIT_OCCURENCES, "The number of first time shadowings");
1564	STAM_REG(pVM, &pPGM->StatTrackAliased, STAMTYPE_COUNTER, "/PGM/Track/Aliased", STAMUNIT_OCCURENCES, "The number of times switching to cRef2, i.e. the page is being shadowed by two PTs.");
1565	STAM_REG(pVM, &pPGM->StatTrackAliasedMany, STAMTYPE_COUNTER, "/PGM/Track/AliasedMany", STAMUNIT_OCCURENCES, "The number of times we're tracking using cRef2.");
1566	STAM_REG(pVM, &pPGM->StatTrackAliasedLots, STAMTYPE_COUNTER, "/PGM/Track/AliasedLots", STAMUNIT_OCCURENCES, "The number of times we're hitting pages which has overflowed cRef2");
1567	STAM_REG(pVM, &pPGM->StatTrackOverflows, STAMTYPE_COUNTER, "/PGM/Track/Overflows", STAMUNIT_OCCURENCES, "The number of times the extent list grows to long.");
1568	STAM_REG(pVM, &pPGM->StatTrackDeref, STAMTYPE_PROFILE, "/PGM/Track/Deref", STAMUNIT_OCCURENCES, "Profiling of SyncPageWorkerTrackDeref (expensive).");
1569	# endif
1570	for (i = 0; i < RT_ELEMENTS(pPGM->StatSyncPtPD); i++)
1571	STAMR3RegisterF(pVM, &pPGM->StatSyncPtPD[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
1572	"The number of SyncPT per PD n.", "/PGM/PDSyncPT/%04X", i);
1573	for (i = 0; i < RT_ELEMENTS(pPGM->StatSyncPagePD); i++)
1574	STAMR3RegisterF(pVM, &pPGM->StatSyncPagePD[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
1575	"The number of SyncPage per PD n.", "/PGM/PDSyncPage/%04X", i);
1576
1577	/* R3 only: */
1578	STAM_REG(pVM, &pPGM->StatR3DetectedConflicts, STAMTYPE_COUNTER, "/PGM/R3/DetectedConflicts", STAMUNIT_OCCURENCES, "The number of times PGMR3CheckMappingConflicts() detected a conflict.");
1579	STAM_REG(pVM, &pPGM->StatR3ResolveConflict, STAMTYPE_PROFILE, "/PGM/R3/ResolveConflict", STAMUNIT_TICKS_PER_CALL, "pgmR3SyncPTResolveConflict() profiling (includes the entire relocation).");
1580	STAM_REG(pVM, &pPGM->StatR3GuestPDWrite, STAMTYPE_COUNTER, "/PGM/R3/PDWrite", STAMUNIT_OCCURENCES, "The total number of times pgmHCGuestPDWriteHandler() was called.");
1581	STAM_REG(pVM, &pPGM->StatR3GuestPDWriteConflict, STAMTYPE_COUNTER, "/PGM/R3/PDWriteConflict", STAMUNIT_OCCURENCES, "The number of times pgmHCGuestPDWriteHandler() detected a conflict.");
1582
1583	/* R0 only: */
1584	STAM_REG(pVM, &pPGM->StatR0DynMapMigrateInvlPg, STAMTYPE_COUNTER, "/PGM/R0/DynMapMigrateInvlPg", STAMUNIT_OCCURENCES, "invlpg count in PGMDynMapMigrateAutoSet.");
1585	STAM_REG(pVM, &pPGM->StatR0DynMapGCPageInl, STAMTYPE_PROFILE, "/PGM/R0/DynMapPageGCPageInl", STAMUNIT_TICKS_PER_CALL, "Calls to pgmR0DynMapGCPageInlined.");
1586	STAM_REG(pVM, &pPGM->StatR0DynMapGCPageInlHits, STAMTYPE_COUNTER, "/PGM/R0/DynMapPageGCPageInl/Hits", STAMUNIT_OCCURENCES, "Hash table lookup hits.");
1587	STAM_REG(pVM, &pPGM->StatR0DynMapGCPageInlMisses, STAMTYPE_COUNTER, "/PGM/R0/DynMapPageGCPageInl/Misses", STAMUNIT_OCCURENCES, "Misses that falls back to code common with PGMDynMapHCPage.");
1588	STAM_REG(pVM, &pPGM->StatR0DynMapGCPageInlRamHits, STAMTYPE_COUNTER, "/PGM/R0/DynMapPageGCPageInl/RamHits", STAMUNIT_OCCURENCES, "1st ram range hits.");
1589	STAM_REG(pVM, &pPGM->StatR0DynMapGCPageInlRamMisses, STAMTYPE_COUNTER, "/PGM/R0/DynMapPageGCPageInl/RamMisses", STAMUNIT_OCCURENCES, "1st ram range misses, takes slow path.");
1590	STAM_REG(pVM, &pPGM->StatR0DynMapHCPageInl, STAMTYPE_PROFILE, "/PGM/R0/DynMapPageHCPageInl", STAMUNIT_TICKS_PER_CALL, "Calls to pgmR0DynMapHCPageInlined.");
1591	STAM_REG(pVM, &pPGM->StatR0DynMapHCPageInlHits, STAMTYPE_COUNTER, "/PGM/R0/DynMapPageHCPageInl/Hits", STAMUNIT_OCCURENCES, "Hash table lookup hits.");
1592	STAM_REG(pVM, &pPGM->StatR0DynMapHCPageInlMisses, STAMTYPE_COUNTER, "/PGM/R0/DynMapPageHCPageInl/Misses", STAMUNIT_OCCURENCES, "Misses that falls back to code common with PGMDynMapHCPage.");
1593	STAM_REG(pVM, &pPGM->StatR0DynMapPage, STAMTYPE_COUNTER, "/PGM/R0/DynMapPage", STAMUNIT_OCCURENCES, "Calls to pgmR0DynMapPage");
1594	STAM_REG(pVM, &pPGM->StatR0DynMapSetOptimize, STAMTYPE_COUNTER, "/PGM/R0/DynMapPage/SetOptimize", STAMUNIT_OCCURENCES, "Calls to pgmDynMapOptimizeAutoSet.");
1595	STAM_REG(pVM, &pPGM->StatR0DynMapSetSearchFlushes, STAMTYPE_COUNTER, "/PGM/R0/DynMapPage/SetSearchFlushes",STAMUNIT_OCCURENCES, "Set search restorting to subset flushes.");
1596	STAM_REG(pVM, &pPGM->StatR0DynMapSetSearchHits, STAMTYPE_COUNTER, "/PGM/R0/DynMapPage/SetSearchHits", STAMUNIT_OCCURENCES, "Set search hits.");
1597	STAM_REG(pVM, &pPGM->StatR0DynMapSetSearchMisses, STAMTYPE_COUNTER, "/PGM/R0/DynMapPage/SetSearchMisses", STAMUNIT_OCCURENCES, "Set search misses.");
1598	STAM_REG(pVM, &pPGM->StatR0DynMapHCPage, STAMTYPE_PROFILE, "/PGM/R0/DynMapPage/HCPage", STAMUNIT_TICKS_PER_CALL, "Calls to PGMDynMapHCPage (ring-0).");
1599	STAM_REG(pVM, &pPGM->StatR0DynMapPageHits0, STAMTYPE_COUNTER, "/PGM/R0/DynMapPage/Hits0", STAMUNIT_OCCURENCES, "Hits at iPage+0");
1600	STAM_REG(pVM, &pPGM->StatR0DynMapPageHits1, STAMTYPE_COUNTER, "/PGM/R0/DynMapPage/Hits1", STAMUNIT_OCCURENCES, "Hits at iPage+1");
1601	STAM_REG(pVM, &pPGM->StatR0DynMapPageHits2, STAMTYPE_COUNTER, "/PGM/R0/DynMapPage/Hits2", STAMUNIT_OCCURENCES, "Hits at iPage+2");
1602	STAM_REG(pVM, &pPGM->StatR0DynMapPageInvlPg, STAMTYPE_COUNTER, "/PGM/R0/DynMapPage/InvlPg", STAMUNIT_OCCURENCES, "invlpg count in pgmR0DynMapPageSlow.");
1603	STAM_REG(pVM, &pPGM->StatR0DynMapPageSlow, STAMTYPE_COUNTER, "/PGM/R0/DynMapPage/Slow", STAMUNIT_OCCURENCES, "Calls to pgmR0DynMapPageSlow - subtract this from pgmR0DynMapPage to get 1st level hits.");
1604	STAM_REG(pVM, &pPGM->StatR0DynMapPageSlowLoopHits, STAMTYPE_COUNTER, "/PGM/R0/DynMapPage/SlowLoopHits" , STAMUNIT_OCCURENCES, "Hits in the loop path.");
1605	STAM_REG(pVM, &pPGM->StatR0DynMapPageSlowLoopMisses, STAMTYPE_COUNTER, "/PGM/R0/DynMapPage/SlowLoopMisses", STAMUNIT_OCCURENCES, "Misses in the loop path. NonLoopMisses = Slow - SlowLoopHit - SlowLoopMisses");
1606	//STAM_REG(pVM, &pPGM->StatR0DynMapPageSlowLostHits, STAMTYPE_COUNTER, "/PGM/R0/DynMapPage/SlowLostHits", STAMUNIT_OCCURENCES, "Lost hits.");
1607	STAM_REG(pVM, &pPGM->StatR0DynMapSubsets, STAMTYPE_COUNTER, "/PGM/R0/Subsets", STAMUNIT_OCCURENCES, "Times PGMDynMapPushAutoSubset was called.");
1608	STAM_REG(pVM, &pPGM->StatR0DynMapPopFlushes, STAMTYPE_COUNTER, "/PGM/R0/SubsetPopFlushes", STAMUNIT_OCCURENCES, "Times PGMDynMapPopAutoSubset flushes the subset.");
1609	STAM_REG(pVM, &pPGM->aStatR0DynMapSetSize[0], STAMTYPE_COUNTER, "/PGM/R0/SetSize000..09", STAMUNIT_OCCURENCES, "00-09% filled");
1610	STAM_REG(pVM, &pPGM->aStatR0DynMapSetSize[1], STAMTYPE_COUNTER, "/PGM/R0/SetSize010..19", STAMUNIT_OCCURENCES, "10-19% filled");
1611	STAM_REG(pVM, &pPGM->aStatR0DynMapSetSize[2], STAMTYPE_COUNTER, "/PGM/R0/SetSize020..29", STAMUNIT_OCCURENCES, "20-29% filled");
1612	STAM_REG(pVM, &pPGM->aStatR0DynMapSetSize[3], STAMTYPE_COUNTER, "/PGM/R0/SetSize030..39", STAMUNIT_OCCURENCES, "30-39% filled");
1613	STAM_REG(pVM, &pPGM->aStatR0DynMapSetSize[4], STAMTYPE_COUNTER, "/PGM/R0/SetSize040..49", STAMUNIT_OCCURENCES, "40-49% filled");
1614	STAM_REG(pVM, &pPGM->aStatR0DynMapSetSize[5], STAMTYPE_COUNTER, "/PGM/R0/SetSize050..59", STAMUNIT_OCCURENCES, "50-59% filled");
1615	STAM_REG(pVM, &pPGM->aStatR0DynMapSetSize[6], STAMTYPE_COUNTER, "/PGM/R0/SetSize060..69", STAMUNIT_OCCURENCES, "60-69% filled");
1616	STAM_REG(pVM, &pPGM->aStatR0DynMapSetSize[7], STAMTYPE_COUNTER, "/PGM/R0/SetSize070..79", STAMUNIT_OCCURENCES, "70-79% filled");
1617	STAM_REG(pVM, &pPGM->aStatR0DynMapSetSize[8], STAMTYPE_COUNTER, "/PGM/R0/SetSize080..89", STAMUNIT_OCCURENCES, "80-89% filled");
1618	STAM_REG(pVM, &pPGM->aStatR0DynMapSetSize[9], STAMTYPE_COUNTER, "/PGM/R0/SetSize090..99", STAMUNIT_OCCURENCES, "90-99% filled");
1619	STAM_REG(pVM, &pPGM->aStatR0DynMapSetSize[10], STAMTYPE_COUNTER, "/PGM/R0/SetSize100", STAMUNIT_OCCURENCES, "100% filled");
1620
1621	/* GC only: */
1622	STAM_REG(pVM, &pPGM->StatRCDynMapCacheHits, STAMTYPE_COUNTER, "/PGM/RC/DynMapCache/Hits" , STAMUNIT_OCCURENCES, "Number of dynamic page mapping cache hits.");
1623	STAM_REG(pVM, &pPGM->StatRCDynMapCacheMisses, STAMTYPE_COUNTER, "/PGM/RC/DynMapCache/Misses" , STAMUNIT_OCCURENCES, "Number of dynamic page mapping cache misses.");
1624	STAM_REG(pVM, &pPGM->StatRCInvlPgConflict, STAMTYPE_COUNTER, "/PGM/RC/InvlPgConflict", STAMUNIT_OCCURENCES, "Number of times PGMInvalidatePage() detected a mapping conflict.");
1625	STAM_REG(pVM, &pPGM->StatRCInvlPgSyncMonCR3, STAMTYPE_COUNTER, "/PGM/RC/InvlPgSyncMonitorCR3", STAMUNIT_OCCURENCES, "Number of times PGMInvalidatePage() ran into PGM_SYNC_MONITOR_CR3.");
1626
1627	/* RZ only: */
1628	STAM_REG(pVM, &pPGM->StatRZTrap0e, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMTrap0eHandler() body.");
1629	STAM_REG(pVM, &pPGM->StatRZTrap0eTimeCheckPageFault, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time/CheckPageFault", STAMUNIT_TICKS_PER_CALL, "Profiling of checking for dirty/access emulation faults.");
1630	STAM_REG(pVM, &pPGM->StatRZTrap0eTimeSyncPT, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time/SyncPT", STAMUNIT_TICKS_PER_CALL, "Profiling of lazy page table syncing.");
1631	STAM_REG(pVM, &pPGM->StatRZTrap0eTimeMapping, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time/Mapping", STAMUNIT_TICKS_PER_CALL, "Profiling of checking virtual mappings.");
1632	STAM_REG(pVM, &pPGM->StatRZTrap0eTimeOutOfSync, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time/OutOfSync", STAMUNIT_TICKS_PER_CALL, "Profiling of out of sync page handling.");
1633	STAM_REG(pVM, &pPGM->StatRZTrap0eTimeHandlers, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time/Handlers", STAMUNIT_TICKS_PER_CALL, "Profiling of checking handlers.");
1634	STAM_REG(pVM, &pPGM->StatRZTrap0eTime2CSAM, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time2/CSAM", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is CSAM.");
1635	STAM_REG(pVM, &pPGM->StatRZTrap0eTime2DirtyAndAccessed, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time2/DirtyAndAccessedBits", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is dirty and/or accessed bit emulation.");
1636	STAM_REG(pVM, &pPGM->StatRZTrap0eTime2GuestTrap, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time2/GuestTrap", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is a guest trap.");
1637	STAM_REG(pVM, &pPGM->StatRZTrap0eTime2HndPhys, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time2/HandlerPhysical", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is a physical handler.");
1638	STAM_REG(pVM, &pPGM->StatRZTrap0eTime2HndVirt, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time2/HandlerVirtual", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is a virtual handler.");
1639	STAM_REG(pVM, &pPGM->StatRZTrap0eTime2HndUnhandled, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time2/HandlerUnhandled", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is access outside the monitored areas of a monitored page.");
1640	STAM_REG(pVM, &pPGM->StatRZTrap0eTime2Misc, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time2/Misc", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is not known.");
1641	STAM_REG(pVM, &pPGM->StatRZTrap0eTime2OutOfSync, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time2/OutOfSync", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is an out-of-sync page.");
1642	STAM_REG(pVM, &pPGM->StatRZTrap0eTime2OutOfSyncHndPhys, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time2/OutOfSyncHndPhys", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is an out-of-sync physical handler page.");
1643	STAM_REG(pVM, &pPGM->StatRZTrap0eTime2OutOfSyncHndVirt, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time2/OutOfSyncHndVirt", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is an out-of-sync virtual handler page.");
1644	STAM_REG(pVM, &pPGM->StatRZTrap0eTime2OutOfSyncHndObs, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time2/OutOfSyncObsHnd", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is an obsolete handler page.");
1645	STAM_REG(pVM, &pPGM->StatRZTrap0eTime2SyncPT, STAMTYPE_PROFILE, "/PGM/RZ/Trap0e/Time2/SyncPT", STAMUNIT_TICKS_PER_CALL, "Profiling of the Trap0eHandler body when the cause is lazy syncing of a PT.");
1646	STAM_REG(pVM, &pPGM->StatRZTrap0eConflicts, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Conflicts", STAMUNIT_OCCURENCES, "The number of times #PF was caused by an undetected conflict.");
1647	STAM_REG(pVM, &pPGM->StatRZTrap0eHandlersMapping, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Handlers/Mapping", STAMUNIT_OCCURENCES, "Number of traps due to access handlers in mappings.");
1648	STAM_REG(pVM, &pPGM->StatRZTrap0eHandlersOutOfSync, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Handlers/OutOfSync", STAMUNIT_OCCURENCES, "Number of traps due to out-of-sync handled pages.");
1649	STAM_REG(pVM, &pPGM->StatRZTrap0eHandlersPhysical, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Handlers/Physical", STAMUNIT_OCCURENCES, "Number of traps due to physical access handlers.");
1650	STAM_REG(pVM, &pPGM->StatRZTrap0eHandlersVirtual, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Handlers/Virtual", STAMUNIT_OCCURENCES, "Number of traps due to virtual access handlers.");
1651	STAM_REG(pVM, &pPGM->StatRZTrap0eHandlersVirtualByPhys, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Handlers/VirtualByPhys", STAMUNIT_OCCURENCES, "Number of traps due to virtual access handlers by physical address.");
1652	STAM_REG(pVM, &pPGM->StatRZTrap0eHandlersVirtualUnmarked,STAMTYPE_COUNTER,"/PGM/RZ/Trap0e/Handlers/VirtualUnmarked",STAMUNIT_OCCURENCES, "Number of traps due to virtual access handlers by virtual address (without proper physical flags).");
1653	STAM_REG(pVM, &pPGM->StatRZTrap0eHandlersUnhandled, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Handlers/Unhandled", STAMUNIT_OCCURENCES, "Number of traps due to access outside range of monitored page(s).");
1654	STAM_REG(pVM, &pPGM->StatRZTrap0eHandlersInvalid, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Handlers/Invalid", STAMUNIT_OCCURENCES, "Number of traps due to access to invalid physical memory.");
1655	STAM_REG(pVM, &pPGM->StatRZTrap0eUSNotPresentRead, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Err/User/NPRead", STAMUNIT_OCCURENCES, "Number of user mode not present read page faults.");
1656	STAM_REG(pVM, &pPGM->StatRZTrap0eUSNotPresentWrite, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Err/User/NPWrite", STAMUNIT_OCCURENCES, "Number of user mode not present write page faults.");
1657	STAM_REG(pVM, &pPGM->StatRZTrap0eUSWrite, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Err/User/Write", STAMUNIT_OCCURENCES, "Number of user mode write page faults.");
1658	STAM_REG(pVM, &pPGM->StatRZTrap0eUSReserved, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Err/User/Reserved", STAMUNIT_OCCURENCES, "Number of user mode reserved bit page faults.");
1659	STAM_REG(pVM, &pPGM->StatRZTrap0eUSNXE, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Err/User/NXE", STAMUNIT_OCCURENCES, "Number of user mode NXE page faults.");
1660	STAM_REG(pVM, &pPGM->StatRZTrap0eUSRead, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Err/User/Read", STAMUNIT_OCCURENCES, "Number of user mode read page faults.");
1661	STAM_REG(pVM, &pPGM->StatRZTrap0eSVNotPresentRead, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Err/Supervisor/NPRead", STAMUNIT_OCCURENCES, "Number of supervisor mode not present read page faults.");
1662	STAM_REG(pVM, &pPGM->StatRZTrap0eSVNotPresentWrite, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Err/Supervisor/NPWrite", STAMUNIT_OCCURENCES, "Number of supervisor mode not present write page faults.");
1663	STAM_REG(pVM, &pPGM->StatRZTrap0eSVWrite, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Err/Supervisor/Write", STAMUNIT_OCCURENCES, "Number of supervisor mode write page faults.");
1664	STAM_REG(pVM, &pPGM->StatRZTrap0eSVReserved, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Err/Supervisor/Reserved", STAMUNIT_OCCURENCES, "Number of supervisor mode reserved bit page faults.");
1665	STAM_REG(pVM, &pPGM->StatRZTrap0eSNXE, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/Err/Supervisor/NXE", STAMUNIT_OCCURENCES, "Number of supervisor mode NXE page faults.");
1666	STAM_REG(pVM, &pPGM->StatRZTrap0eGuestPF, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/GuestPF", STAMUNIT_OCCURENCES, "Number of real guest page faults.");
1667	STAM_REG(pVM, &pPGM->StatRZTrap0eGuestPFUnh, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/GuestPF/Unhandled", STAMUNIT_OCCURENCES, "Number of real guest page faults from the 'unhandled' case.");
1668	STAM_REG(pVM, &pPGM->StatRZTrap0eGuestPFMapping, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/GuestPF/InMapping", STAMUNIT_OCCURENCES, "Number of real guest page faults in a mapping.");
1669	STAM_REG(pVM, &pPGM->StatRZTrap0eWPEmulInRZ, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/WP/InRZ", STAMUNIT_OCCURENCES, "Number of guest page faults due to X86_CR0_WP emulation.");
1670	STAM_REG(pVM, &pPGM->StatRZTrap0eWPEmulToR3, STAMTYPE_COUNTER, "/PGM/RZ/Trap0e/WP/ToR3", STAMUNIT_OCCURENCES, "Number of guest page faults due to X86_CR0_WP emulation (forward to R3 for emulation).");
1671	for (i = 0; i < RT_ELEMENTS(pPGM->StatRZTrap0ePD); i++)
1672	STAMR3RegisterF(pVM, &pPGM->StatRZTrap0ePD[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
1673	"The number of traps in page directory n.", "/PGM/RZ/Trap0e/PD/%04X", i);
1674	STAM_REG(pVM, &pPGM->StatRZGuestCR3WriteHandled, STAMTYPE_COUNTER, "/PGM/RZ/CR3WriteHandled", STAMUNIT_OCCURENCES, "The number of times the Guest CR3 change was successfully handled.");
1675	STAM_REG(pVM, &pPGM->StatRZGuestCR3WriteUnhandled, STAMTYPE_COUNTER, "/PGM/RZ/CR3WriteUnhandled", STAMUNIT_OCCURENCES, "The number of times the Guest CR3 change was passed back to the recompiler.");
1676	STAM_REG(pVM, &pPGM->StatRZGuestCR3WriteConflict, STAMTYPE_COUNTER, "/PGM/RZ/CR3WriteConflict", STAMUNIT_OCCURENCES, "The number of times the Guest CR3 monitoring detected a conflict.");
1677	STAM_REG(pVM, &pPGM->StatRZGuestROMWriteHandled, STAMTYPE_COUNTER, "/PGM/RZ/ROMWriteHandled", STAMUNIT_OCCURENCES, "The number of times the Guest ROM change was successfully handled.");
1678	STAM_REG(pVM, &pPGM->StatRZGuestROMWriteUnhandled, STAMTYPE_COUNTER, "/PGM/RZ/ROMWriteUnhandled", STAMUNIT_OCCURENCES, "The number of times the Guest ROM change was passed back to the recompiler.");
1679
1680	/* HC only: */
1681
1682	/* RZ & R3: */
1683	STAM_REG(pVM, &pPGM->StatRZSyncCR3, STAMTYPE_PROFILE, "/PGM/RZ/SyncCR3", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMSyncCR3() body.");
1684	STAM_REG(pVM, &pPGM->StatRZSyncCR3Handlers, STAMTYPE_PROFILE, "/PGM/RZ/SyncCR3/Handlers", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMSyncCR3() update handler section.");
1685	STAM_REG(pVM, &pPGM->StatRZSyncCR3HandlerVirtualUpdate, STAMTYPE_PROFILE, "/PGM/RZ/SyncCR3/Handlers/VirtualUpdate", STAMUNIT_TICKS_PER_CALL, "Profiling of the virtual handler updates.");
1686	STAM_REG(pVM, &pPGM->StatRZSyncCR3HandlerVirtualReset, STAMTYPE_PROFILE, "/PGM/RZ/SyncCR3/Handlers/VirtualReset", STAMUNIT_TICKS_PER_CALL, "Profiling of the virtual handler resets.");
1687	STAM_REG(pVM, &pPGM->StatRZSyncCR3Global, STAMTYPE_COUNTER, "/PGM/RZ/SyncCR3/Global", STAMUNIT_OCCURENCES, "The number of global CR3 syncs.");
1688	STAM_REG(pVM, &pPGM->StatRZSyncCR3NotGlobal, STAMTYPE_COUNTER, "/PGM/RZ/SyncCR3/NotGlobal", STAMUNIT_OCCURENCES, "The number of non-global CR3 syncs.");
1689	STAM_REG(pVM, &pPGM->StatRZSyncCR3DstCacheHit, STAMTYPE_COUNTER, "/PGM/RZ/SyncCR3/DstChacheHit", STAMUNIT_OCCURENCES, "The number of times we got some kind of a cache hit.");
1690	STAM_REG(pVM, &pPGM->StatRZSyncCR3DstFreed, STAMTYPE_COUNTER, "/PGM/RZ/SyncCR3/DstFreed", STAMUNIT_OCCURENCES, "The number of times we've had to free a shadow entry.");
1691	STAM_REG(pVM, &pPGM->StatRZSyncCR3DstFreedSrcNP, STAMTYPE_COUNTER, "/PGM/RZ/SyncCR3/DstFreedSrcNP", STAMUNIT_OCCURENCES, "The number of times we've had to free a shadow entry for which the source entry was not present.");
1692	STAM_REG(pVM, &pPGM->StatRZSyncCR3DstNotPresent, STAMTYPE_COUNTER, "/PGM/RZ/SyncCR3/DstNotPresent", STAMUNIT_OCCURENCES, "The number of times we've encountered a not present shadow entry for a present guest entry.");
1693	STAM_REG(pVM, &pPGM->StatRZSyncCR3DstSkippedGlobalPD, STAMTYPE_COUNTER, "/PGM/RZ/SyncCR3/DstSkippedGlobalPD", STAMUNIT_OCCURENCES, "The number of times a global page directory wasn't flushed.");
1694	STAM_REG(pVM, &pPGM->StatRZSyncCR3DstSkippedGlobalPT, STAMTYPE_COUNTER, "/PGM/RZ/SyncCR3/DstSkippedGlobalPT", STAMUNIT_OCCURENCES, "The number of times a page table with only global entries wasn't flushed.");
1695	STAM_REG(pVM, &pPGM->StatRZSyncPT, STAMTYPE_PROFILE, "/PGM/RZ/SyncPT", STAMUNIT_TICKS_PER_CALL, "Profiling of the pfnSyncPT() body.");
1696	STAM_REG(pVM, &pPGM->StatRZSyncPTFailed, STAMTYPE_COUNTER, "/PGM/RZ/SyncPT/Failed", STAMUNIT_OCCURENCES, "The number of times pfnSyncPT() failed.");
1697	STAM_REG(pVM, &pPGM->StatRZSyncPT4K, STAMTYPE_COUNTER, "/PGM/RZ/SyncPT/4K", STAMUNIT_OCCURENCES, "Nr of 4K PT syncs");
1698	STAM_REG(pVM, &pPGM->StatRZSyncPT4M, STAMTYPE_COUNTER, "/PGM/RZ/SyncPT/4M", STAMUNIT_OCCURENCES, "Nr of 4M PT syncs");
1699	STAM_REG(pVM, &pPGM->StatRZSyncPagePDNAs, STAMTYPE_COUNTER, "/PGM/RZ/SyncPagePDNAs", STAMUNIT_OCCURENCES, "The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit.");
1700	STAM_REG(pVM, &pPGM->StatRZSyncPagePDOutOfSync, STAMTYPE_COUNTER, "/PGM/RZ/SyncPagePDOutOfSync", STAMUNIT_OCCURENCES, "The number of time we've encountered an out-of-sync PD in SyncPage.");
1701	STAM_REG(pVM, &pPGM->StatRZAccessedPage, STAMTYPE_COUNTER, "/PGM/RZ/AccessedPage", STAMUNIT_OCCURENCES, "The number of pages marked not present for accessed bit emulation.");
1702	STAM_REG(pVM, &pPGM->StatRZDirtyBitTracking, STAMTYPE_PROFILE, "/PGM/RZ/DirtyPage", STAMUNIT_TICKS_PER_CALL, "Profiling the dirty bit tracking in CheckPageFault().");
1703	STAM_REG(pVM, &pPGM->StatRZDirtyPage, STAMTYPE_COUNTER, "/PGM/RZ/DirtyPage/Mark", STAMUNIT_OCCURENCES, "The number of pages marked read-only for dirty bit tracking.");
1704	STAM_REG(pVM, &pPGM->StatRZDirtyPageBig, STAMTYPE_COUNTER, "/PGM/RZ/DirtyPage/MarkBig", STAMUNIT_OCCURENCES, "The number of 4MB pages marked read-only for dirty bit tracking.");
1705	STAM_REG(pVM, &pPGM->StatRZDirtyPageSkipped, STAMTYPE_COUNTER, "/PGM/RZ/DirtyPage/Skipped", STAMUNIT_OCCURENCES, "The number of pages already dirty or readonly.");
1706	STAM_REG(pVM, &pPGM->StatRZDirtyPageTrap, STAMTYPE_COUNTER, "/PGM/RZ/DirtyPage/Trap", STAMUNIT_OCCURENCES, "The number of traps generated for dirty bit tracking.");
1707	STAM_REG(pVM, &pPGM->StatRZDirtiedPage, STAMTYPE_COUNTER, "/PGM/RZ/DirtyPage/SetDirty", STAMUNIT_OCCURENCES, "The number of pages marked dirty because of write accesses.");
1708	STAM_REG(pVM, &pPGM->StatRZDirtyTrackRealPF, STAMTYPE_COUNTER, "/PGM/RZ/DirtyPage/RealPF", STAMUNIT_OCCURENCES, "The number of real pages faults during dirty bit tracking.");
1709	STAM_REG(pVM, &pPGM->StatRZPageAlreadyDirty, STAMTYPE_COUNTER, "/PGM/RZ/DirtyPage/AlreadySet", STAMUNIT_OCCURENCES, "The number of pages already marked dirty because of write accesses.");
1710	STAM_REG(pVM, &pPGM->StatRZInvalidatePage, STAMTYPE_PROFILE, "/PGM/RZ/InvalidatePage", STAMUNIT_TICKS_PER_CALL, "PGMInvalidatePage() profiling.");
1711	STAM_REG(pVM, &pPGM->StatRZInvalidatePage4KBPages, STAMTYPE_COUNTER, "/PGM/RZ/InvalidatePage/4KBPages", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was called for a 4KB page.");
1712	STAM_REG(pVM, &pPGM->StatRZInvalidatePage4MBPages, STAMTYPE_COUNTER, "/PGM/RZ/InvalidatePage/4MBPages", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was called for a 4MB page.");
1713	STAM_REG(pVM, &pPGM->StatRZInvalidatePage4MBPagesSkip, STAMTYPE_COUNTER, "/PGM/RZ/InvalidatePage/4MBPagesSkip",STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() skipped a 4MB page.");
1714	STAM_REG(pVM, &pPGM->StatRZInvalidatePagePDMappings, STAMTYPE_COUNTER, "/PGM/RZ/InvalidatePage/PDMappings", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict).");
1715	STAM_REG(pVM, &pPGM->StatRZInvalidatePagePDNAs, STAMTYPE_COUNTER, "/PGM/RZ/InvalidatePage/PDNAs", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was called for a not accessed page directory.");
1716	STAM_REG(pVM, &pPGM->StatRZInvalidatePagePDNPs, STAMTYPE_COUNTER, "/PGM/RZ/InvalidatePage/PDNPs", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was called for a not present page directory.");
1717	STAM_REG(pVM, &pPGM->StatRZInvalidatePagePDOutOfSync, STAMTYPE_COUNTER, "/PGM/RZ/InvalidatePage/PDOutOfSync", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was called for an out of sync page directory.");
1718	STAM_REG(pVM, &pPGM->StatRZInvalidatePageSkipped, STAMTYPE_COUNTER, "/PGM/RZ/InvalidatePage/Skipped", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3.");
1719	STAM_REG(pVM, &pPGM->StatRZVirtHandlerSearchByPhys, STAMTYPE_PROFILE, "/PGM/RZ/VirtHandlerSearchByPhys", STAMUNIT_TICKS_PER_CALL, "Profiling of pgmHandlerVirtualFindByPhysAddr.");
1720	STAM_REG(pVM, &pPGM->StatRZPhysHandlerReset, STAMTYPE_COUNTER, "/PGM/RZ/PhysHandlerReset", STAMUNIT_OCCURENCES, "The number of times PGMHandlerPhysicalReset is called.");
1721	STAM_REG(pVM, &pPGM->StatRZPageOutOfSyncSupervisor, STAMTYPE_COUNTER, "/PGM/RZ/OutOfSync/SuperVisor", STAMUNIT_OCCURENCES, "Number of traps due to pages out of sync and times VerifyAccessSyncPage calls SyncPage.");
1722	STAM_REG(pVM, &pPGM->StatRZPageOutOfSyncUser, STAMTYPE_COUNTER, "/PGM/RZ/OutOfSync/User", STAMUNIT_OCCURENCES, "Number of traps due to pages out of sync and times VerifyAccessSyncPage calls SyncPage.");
1723	STAM_REG(pVM, &pPGM->StatRZPrefetch, STAMTYPE_PROFILE, "/PGM/RZ/Prefetch", STAMUNIT_TICKS_PER_CALL, "PGMPrefetchPage profiling.");
1724	STAM_REG(pVM, &pPGM->StatRZChunkR3MapTlbHits, STAMTYPE_COUNTER, "/PGM/ChunkR3Map/TlbHitsRZ", STAMUNIT_OCCURENCES, "TLB hits.");
1725	STAM_REG(pVM, &pPGM->StatRZChunkR3MapTlbMisses, STAMTYPE_COUNTER, "/PGM/ChunkR3Map/TlbMissesRZ", STAMUNIT_OCCURENCES, "TLB misses.");
1726	STAM_REG(pVM, &pPGM->StatRZPageMapTlbHits, STAMTYPE_COUNTER, "/PGM/RZ/Page/MapTlbHits", STAMUNIT_OCCURENCES, "TLB hits.");
1727	STAM_REG(pVM, &pPGM->StatRZPageMapTlbMisses, STAMTYPE_COUNTER, "/PGM/RZ/Page/MapTlbMisses", STAMUNIT_OCCURENCES, "TLB misses.");
1728	STAM_REG(pVM, &pPGM->StatRZPageReplaceShared, STAMTYPE_COUNTER, "/PGM/RZ/Page/ReplacedShared", STAMUNIT_OCCURENCES, "Times a shared page was replaced.");
1729	STAM_REG(pVM, &pPGM->StatRZPageReplaceZero, STAMTYPE_COUNTER, "/PGM/RZ/Page/ReplacedZero", STAMUNIT_OCCURENCES, "Times the zero page was replaced.");
1730	/// @todo STAM_REG(pVM, &pPGM->StatRZPageHandyAllocs, STAMTYPE_COUNTER, "/PGM/RZ/Page/HandyAllocs", STAMUNIT_OCCURENCES, "Number of times we've allocated more handy pages.");
1731	STAM_REG(pVM, &pPGM->StatRZFlushTLB, STAMTYPE_PROFILE, "/PGM/RZ/FlushTLB", STAMUNIT_OCCURENCES, "Profiling of the PGMFlushTLB() body.");
1732	STAM_REG(pVM, &pPGM->StatRZFlushTLBNewCR3, STAMTYPE_COUNTER, "/PGM/RZ/FlushTLB/NewCR3", STAMUNIT_OCCURENCES, "The number of times PGMFlushTLB was called with a new CR3, non-global. (switch)");
1733	STAM_REG(pVM, &pPGM->StatRZFlushTLBNewCR3Global, STAMTYPE_COUNTER, "/PGM/RZ/FlushTLB/NewCR3Global", STAMUNIT_OCCURENCES, "The number of times PGMFlushTLB was called with a new CR3, global. (switch)");
1734	STAM_REG(pVM, &pPGM->StatRZFlushTLBSameCR3, STAMTYPE_COUNTER, "/PGM/RZ/FlushTLB/SameCR3", STAMUNIT_OCCURENCES, "The number of times PGMFlushTLB was called with the same CR3, non-global. (flush)");
1735	STAM_REG(pVM, &pPGM->StatRZFlushTLBSameCR3Global, STAMTYPE_COUNTER, "/PGM/RZ/FlushTLB/SameCR3Global", STAMUNIT_OCCURENCES, "The number of times PGMFlushTLB was called with the same CR3, global. (flush)");
1736	STAM_REG(pVM, &pPGM->StatRZGstModifyPage, STAMTYPE_PROFILE, "/PGM/RZ/GstModifyPage", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMGstModifyPage() body.");
1737
1738	STAM_REG(pVM, &pPGM->StatR3SyncCR3, STAMTYPE_PROFILE, "/PGM/R3/SyncCR3", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMSyncCR3() body.");
1739	STAM_REG(pVM, &pPGM->StatR3SyncCR3Handlers, STAMTYPE_PROFILE, "/PGM/R3/SyncCR3/Handlers", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMSyncCR3() update handler section.");
1740	STAM_REG(pVM, &pPGM->StatR3SyncCR3HandlerVirtualUpdate, STAMTYPE_PROFILE, "/PGM/R3/SyncCR3/Handlers/VirtualUpdate", STAMUNIT_TICKS_PER_CALL, "Profiling of the virtual handler updates.");
1741	STAM_REG(pVM, &pPGM->StatR3SyncCR3HandlerVirtualReset, STAMTYPE_PROFILE, "/PGM/R3/SyncCR3/Handlers/VirtualReset", STAMUNIT_TICKS_PER_CALL, "Profiling of the virtual handler resets.");
1742	STAM_REG(pVM, &pPGM->StatR3SyncCR3Global, STAMTYPE_COUNTER, "/PGM/R3/SyncCR3/Global", STAMUNIT_OCCURENCES, "The number of global CR3 syncs.");
1743	STAM_REG(pVM, &pPGM->StatR3SyncCR3NotGlobal, STAMTYPE_COUNTER, "/PGM/R3/SyncCR3/NotGlobal", STAMUNIT_OCCURENCES, "The number of non-global CR3 syncs.");
1744	STAM_REG(pVM, &pPGM->StatR3SyncCR3DstCacheHit, STAMTYPE_COUNTER, "/PGM/R3/SyncCR3/DstChacheHit", STAMUNIT_OCCURENCES, "The number of times we got some kind of a cache hit.");
1745	STAM_REG(pVM, &pPGM->StatR3SyncCR3DstFreed, STAMTYPE_COUNTER, "/PGM/R3/SyncCR3/DstFreed", STAMUNIT_OCCURENCES, "The number of times we've had to free a shadow entry.");
1746	STAM_REG(pVM, &pPGM->StatR3SyncCR3DstFreedSrcNP, STAMTYPE_COUNTER, "/PGM/R3/SyncCR3/DstFreedSrcNP", STAMUNIT_OCCURENCES, "The number of times we've had to free a shadow entry for which the source entry was not present.");
1747	STAM_REG(pVM, &pPGM->StatR3SyncCR3DstNotPresent, STAMTYPE_COUNTER, "/PGM/R3/SyncCR3/DstNotPresent", STAMUNIT_OCCURENCES, "The number of times we've encountered a not present shadow entry for a present guest entry.");
1748	STAM_REG(pVM, &pPGM->StatR3SyncCR3DstSkippedGlobalPD, STAMTYPE_COUNTER, "/PGM/R3/SyncCR3/DstSkippedGlobalPD", STAMUNIT_OCCURENCES, "The number of times a global page directory wasn't flushed.");
1749	STAM_REG(pVM, &pPGM->StatR3SyncCR3DstSkippedGlobalPT, STAMTYPE_COUNTER, "/PGM/R3/SyncCR3/DstSkippedGlobalPT", STAMUNIT_OCCURENCES, "The number of times a page table with only global entries wasn't flushed.");
1750	STAM_REG(pVM, &pPGM->StatR3SyncPT, STAMTYPE_PROFILE, "/PGM/R3/SyncPT", STAMUNIT_TICKS_PER_CALL, "Profiling of the pfnSyncPT() body.");
1751	STAM_REG(pVM, &pPGM->StatR3SyncPTFailed, STAMTYPE_COUNTER, "/PGM/R3/SyncPT/Failed", STAMUNIT_OCCURENCES, "The number of times pfnSyncPT() failed.");
1752	STAM_REG(pVM, &pPGM->StatR3SyncPT4K, STAMTYPE_COUNTER, "/PGM/R3/SyncPT/4K", STAMUNIT_OCCURENCES, "Nr of 4K PT syncs");
1753	STAM_REG(pVM, &pPGM->StatR3SyncPT4M, STAMTYPE_COUNTER, "/PGM/R3/SyncPT/4M", STAMUNIT_OCCURENCES, "Nr of 4M PT syncs");
1754	STAM_REG(pVM, &pPGM->StatR3SyncPagePDNAs, STAMTYPE_COUNTER, "/PGM/R3/SyncPagePDNAs", STAMUNIT_OCCURENCES, "The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit.");
1755	STAM_REG(pVM, &pPGM->StatR3SyncPagePDOutOfSync, STAMTYPE_COUNTER, "/PGM/R3/SyncPagePDOutOfSync", STAMUNIT_OCCURENCES, "The number of time we've encountered an out-of-sync PD in SyncPage.");
1756	STAM_REG(pVM, &pPGM->StatR3AccessedPage, STAMTYPE_COUNTER, "/PGM/R3/AccessedPage", STAMUNIT_OCCURENCES, "The number of pages marked not present for accessed bit emulation.");
1757	STAM_REG(pVM, &pPGM->StatR3DirtyBitTracking, STAMTYPE_PROFILE, "/PGM/R3/DirtyPage", STAMUNIT_TICKS_PER_CALL, "Profiling the dirty bit tracking in CheckPageFault().");
1758	STAM_REG(pVM, &pPGM->StatR3DirtyPage, STAMTYPE_COUNTER, "/PGM/R3/DirtyPage/Mark", STAMUNIT_OCCURENCES, "The number of pages marked read-only for dirty bit tracking.");
1759	STAM_REG(pVM, &pPGM->StatR3DirtyPageBig, STAMTYPE_COUNTER, "/PGM/R3/DirtyPage/MarkBig", STAMUNIT_OCCURENCES, "The number of 4MB pages marked read-only for dirty bit tracking.");
1760	STAM_REG(pVM, &pPGM->StatR3DirtyPageSkipped, STAMTYPE_COUNTER, "/PGM/R3/DirtyPage/Skipped", STAMUNIT_OCCURENCES, "The number of pages already dirty or readonly.");
1761	STAM_REG(pVM, &pPGM->StatR3DirtyPageTrap, STAMTYPE_COUNTER, "/PGM/R3/DirtyPage/Trap", STAMUNIT_OCCURENCES, "The number of traps generated for dirty bit tracking.");
1762	STAM_REG(pVM, &pPGM->StatR3DirtiedPage, STAMTYPE_COUNTER, "/PGM/R3/DirtyPage/SetDirty", STAMUNIT_OCCURENCES, "The number of pages marked dirty because of write accesses.");
1763	STAM_REG(pVM, &pPGM->StatR3DirtyTrackRealPF, STAMTYPE_COUNTER, "/PGM/R3/DirtyPage/RealPF", STAMUNIT_OCCURENCES, "The number of real pages faults during dirty bit tracking.");
1764	STAM_REG(pVM, &pPGM->StatR3PageAlreadyDirty, STAMTYPE_COUNTER, "/PGM/R3/DirtyPage/AlreadySet", STAMUNIT_OCCURENCES, "The number of pages already marked dirty because of write accesses.");
1765	STAM_REG(pVM, &pPGM->StatR3InvalidatePage, STAMTYPE_PROFILE, "/PGM/R3/InvalidatePage", STAMUNIT_TICKS_PER_CALL, "PGMInvalidatePage() profiling.");
1766	STAM_REG(pVM, &pPGM->StatR3InvalidatePage4KBPages, STAMTYPE_COUNTER, "/PGM/R3/InvalidatePage/4KBPages", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was called for a 4KB page.");
1767	STAM_REG(pVM, &pPGM->StatR3InvalidatePage4MBPages, STAMTYPE_COUNTER, "/PGM/R3/InvalidatePage/4MBPages", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was called for a 4MB page.");
1768	STAM_REG(pVM, &pPGM->StatR3InvalidatePage4MBPagesSkip, STAMTYPE_COUNTER, "/PGM/R3/InvalidatePage/4MBPagesSkip",STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() skipped a 4MB page.");
1769	STAM_REG(pVM, &pPGM->StatR3InvalidatePagePDMappings, STAMTYPE_COUNTER, "/PGM/R3/InvalidatePage/PDMappings", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict).");
1770	STAM_REG(pVM, &pPGM->StatR3InvalidatePagePDNAs, STAMTYPE_COUNTER, "/PGM/R3/InvalidatePage/PDNAs", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was called for a not accessed page directory.");
1771	STAM_REG(pVM, &pPGM->StatR3InvalidatePagePDNPs, STAMTYPE_COUNTER, "/PGM/R3/InvalidatePage/PDNPs", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was called for a not present page directory.");
1772	STAM_REG(pVM, &pPGM->StatR3InvalidatePagePDOutOfSync, STAMTYPE_COUNTER, "/PGM/R3/InvalidatePage/PDOutOfSync", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was called for an out of sync page directory.");
1773	STAM_REG(pVM, &pPGM->StatR3InvalidatePageSkipped, STAMTYPE_COUNTER, "/PGM/R3/InvalidatePage/Skipped", STAMUNIT_OCCURENCES, "The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3.");
1774	STAM_REG(pVM, &pPGM->StatR3VirtHandlerSearchByPhys, STAMTYPE_PROFILE, "/PGM/R3/VirtHandlerSearchByPhys", STAMUNIT_TICKS_PER_CALL, "Profiling of pgmHandlerVirtualFindByPhysAddr.");
1775	STAM_REG(pVM, &pPGM->StatR3PhysHandlerReset, STAMTYPE_COUNTER, "/PGM/R3/PhysHandlerReset", STAMUNIT_OCCURENCES, "The number of times PGMHandlerPhysicalReset is called.");
1776	STAM_REG(pVM, &pPGM->StatR3PageOutOfSyncSupervisor, STAMTYPE_COUNTER, "/PGM/R3/OutOfSync/SuperVisor", STAMUNIT_OCCURENCES, "Number of traps due to pages out of sync and times VerifyAccessSyncPage calls SyncPage.");
1777	STAM_REG(pVM, &pPGM->StatR3PageOutOfSyncUser, STAMTYPE_COUNTER, "/PGM/R3/OutOfSync/User", STAMUNIT_OCCURENCES, "Number of traps due to pages out of sync and times VerifyAccessSyncPage calls SyncPage.");
1778	STAM_REG(pVM, &pPGM->StatR3Prefetch, STAMTYPE_PROFILE, "/PGM/R3/Prefetch", STAMUNIT_TICKS_PER_CALL, "PGMPrefetchPage profiling.");
1779	STAM_REG(pVM, &pPGM->StatR3ChunkR3MapTlbHits, STAMTYPE_COUNTER, "/PGM/ChunkR3Map/TlbHitsR3", STAMUNIT_OCCURENCES, "TLB hits.");
1780	STAM_REG(pVM, &pPGM->StatR3ChunkR3MapTlbMisses, STAMTYPE_COUNTER, "/PGM/ChunkR3Map/TlbMissesR3", STAMUNIT_OCCURENCES, "TLB misses.");
1781	STAM_REG(pVM, &pPGM->StatR3PageMapTlbHits, STAMTYPE_COUNTER, "/PGM/R3/Page/MapTlbHits", STAMUNIT_OCCURENCES, "TLB hits.");
1782	STAM_REG(pVM, &pPGM->StatR3PageMapTlbMisses, STAMTYPE_COUNTER, "/PGM/R3/Page/MapTlbMisses", STAMUNIT_OCCURENCES, "TLB misses.");
1783	STAM_REG(pVM, &pPGM->StatR3PageReplaceShared, STAMTYPE_COUNTER, "/PGM/R3/Page/ReplacedShared", STAMUNIT_OCCURENCES, "Times a shared page was replaced.");
1784	STAM_REG(pVM, &pPGM->StatR3PageReplaceZero, STAMTYPE_COUNTER, "/PGM/R3/Page/ReplacedZero", STAMUNIT_OCCURENCES, "Times the zero page was replaced.");
1785	/// @todo STAM_REG(pVM, &pPGM->StatR3PageHandyAllocs, STAMTYPE_COUNTER, "/PGM/R3/Page/HandyAllocs", STAMUNIT_OCCURENCES, "Number of times we've allocated more handy pages.");
1786	STAM_REG(pVM, &pPGM->StatR3FlushTLB, STAMTYPE_PROFILE, "/PGM/R3/FlushTLB", STAMUNIT_OCCURENCES, "Profiling of the PGMFlushTLB() body.");
1787	STAM_REG(pVM, &pPGM->StatR3FlushTLBNewCR3, STAMTYPE_COUNTER, "/PGM/R3/FlushTLB/NewCR3", STAMUNIT_OCCURENCES, "The number of times PGMFlushTLB was called with a new CR3, non-global. (switch)");
1788	STAM_REG(pVM, &pPGM->StatR3FlushTLBNewCR3Global, STAMTYPE_COUNTER, "/PGM/R3/FlushTLB/NewCR3Global", STAMUNIT_OCCURENCES, "The number of times PGMFlushTLB was called with a new CR3, global. (switch)");
1789	STAM_REG(pVM, &pPGM->StatR3FlushTLBSameCR3, STAMTYPE_COUNTER, "/PGM/R3/FlushTLB/SameCR3", STAMUNIT_OCCURENCES, "The number of times PGMFlushTLB was called with the same CR3, non-global. (flush)");
1790	STAM_REG(pVM, &pPGM->StatR3FlushTLBSameCR3Global, STAMTYPE_COUNTER, "/PGM/R3/FlushTLB/SameCR3Global", STAMUNIT_OCCURENCES, "The number of times PGMFlushTLB was called with the same CR3, global. (flush)");
1791	STAM_REG(pVM, &pPGM->StatR3GstModifyPage, STAMTYPE_PROFILE, "/PGM/R3/GstModifyPage", STAMUNIT_TICKS_PER_CALL, "Profiling of the PGMGstModifyPage() body.");
1792	#endif /* VBOX_WITH_STATISTICS */
1793	}
1794
1795
1796	/**
1797	* Init the PGM bits that rely on VMMR0 and MM to be fully initialized.
1798	*
1799	* The dynamic mapping area will also be allocated and initialized at this
1800	* time. We could allocate it during PGMR3Init of course, but the mapping
1801	* wouldn't be allocated at that time preventing us from setting up the
1802	* page table entries with the dummy page.
1803	*
1804	* @returns VBox status code.
1805	* @param pVM VM handle.
1806	*/
1807	VMMR3DECL(int) PGMR3InitDynMap(PVM pVM)
1808	{
1809	RTGCPTR GCPtr;
1810	int rc;
1811
1812	/*
1813	* Reserve space for the dynamic mappings.
1814	*/
1815	rc = MMR3HyperReserve(pVM, MM_HYPER_DYNAMIC_SIZE, "Dynamic mapping", &GCPtr);
1816	if (RT_SUCCESS(rc))
1817	pVM->pgm.s.pbDynPageMapBaseGC = GCPtr;
1818
1819	if ( RT_SUCCESS(rc)
1820	&& (pVM->pgm.s.pbDynPageMapBaseGC >> X86_PD_PAE_SHIFT) != ((pVM->pgm.s.pbDynPageMapBaseGC + MM_HYPER_DYNAMIC_SIZE - 1) >> X86_PD_PAE_SHIFT))
1821	{
1822	rc = MMR3HyperReserve(pVM, MM_HYPER_DYNAMIC_SIZE, "Dynamic mapping not crossing", &GCPtr);
1823	if (RT_SUCCESS(rc))
1824	pVM->pgm.s.pbDynPageMapBaseGC = GCPtr;
1825	}
1826	if (RT_SUCCESS(rc))
1827	{
1828	AssertRelease((pVM->pgm.s.pbDynPageMapBaseGC >> X86_PD_PAE_SHIFT) == ((pVM->pgm.s.pbDynPageMapBaseGC + MM_HYPER_DYNAMIC_SIZE - 1) >> X86_PD_PAE_SHIFT));
1829	MMR3HyperReserve(pVM, PAGE_SIZE, "fence", NULL);
1830	}
1831	return rc;
1832	}
1833
1834
1835	/**
1836	* Ring-3 init finalizing.
1837	*
1838	* @returns VBox status code.
1839	* @param pVM The VM handle.
1840	*/
1841	VMMR3DECL(int) PGMR3InitFinalize(PVM pVM)
1842	{
1843	int rc;
1844
1845	/*
1846	* Reserve space for the dynamic mappings.
1847	* Initialize the dynamic mapping pages with dummy pages to simply the cache.
1848	*/
1849	/* get the pointer to the page table entries. */
1850	PPGMMAPPING pMapping = pgmGetMapping(pVM, pVM->pgm.s.pbDynPageMapBaseGC);
1851	AssertRelease(pMapping);
1852	const uintptr_t off = pVM->pgm.s.pbDynPageMapBaseGC - pMapping->GCPtr;
1853	const unsigned iPT = off >> X86_PD_SHIFT;
1854	const unsigned iPG = (off >> X86_PT_SHIFT) & X86_PT_MASK;
1855	pVM->pgm.s.paDynPageMap32BitPTEsGC = pMapping->aPTs[iPT].pPTRC + iPG * sizeof(pMapping->aPTs[0].pPTR3->a[0]);
1856	pVM->pgm.s.paDynPageMapPaePTEsGC = pMapping->aPTs[iPT].paPaePTsRC + iPG * sizeof(pMapping->aPTs[0].paPaePTsR3->a[0]);
1857
1858	/* init cache */
1859	RTHCPHYS HCPhysDummy = MMR3PageDummyHCPhys(pVM);
1860	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.aHCPhysDynPageMapCache); i++)
1861	pVM->pgm.s.aHCPhysDynPageMapCache[i] = HCPhysDummy;
1862
1863	for (unsigned i = 0; i < MM_HYPER_DYNAMIC_SIZE; i += PAGE_SIZE)
1864	{
1865	rc = PGMMap(pVM, pVM->pgm.s.pbDynPageMapBaseGC + i, HCPhysDummy, PAGE_SIZE, 0);
1866	AssertRCReturn(rc, rc);
1867	}
1868
1869	/*
1870	* Note that AMD uses all the 8 reserved bits for the address (so 40 bits in total);
1871	* Intel only goes up to 36 bits, so we stick to 36 as well.
1872	*/
1873	/** @todo How to test for the 40 bits support? Long mode seems to be the test criterium. */
1874	uint32_t u32Dummy, u32Features;
1875	CPUMGetGuestCpuId(pVM, 1, &u32Dummy, &u32Dummy, &u32Dummy, &u32Features);
1876
1877	if (u32Features & X86_CPUID_FEATURE_EDX_PSE36)
1878	pVM->pgm.s.GCPhys4MBPSEMask = RT_BIT_64(36) - 1;
1879	else
1880	pVM->pgm.s.GCPhys4MBPSEMask = RT_BIT_64(32) - 1;
1881
1882	/*
1883	* Allocate memory if we're supposed to do that.
1884	*/
1885	if (pVM->pgm.s.fRamPreAlloc)
1886	rc = pgmR3PhysRamPreAllocate(pVM);
1887
1888	LogRel(("PGMR3InitFinalize: 4 MB PSE mask %RGp\n", pVM->pgm.s.GCPhys4MBPSEMask));
1889	return rc;
1890	}
1891
1892
1893	/**
1894	* Applies relocations to data and code managed by this component.
1895	*
1896	* This function will be called at init and whenever the VMM need to relocate it
1897	* self inside the GC.
1898	*
1899	* @param pVM The VM.
1900	* @param offDelta Relocation delta relative to old location.
1901	*/
1902	VMMR3DECL(void) PGMR3Relocate(PVM pVM, RTGCINTPTR offDelta)
1903	{
1904	LogFlow(("PGMR3Relocate %RGv to %RGv\n", pVM->pgm.s.GCPtrCR3Mapping, pVM->pgm.s.GCPtrCR3Mapping + offDelta));
1905
1906	/*
1907	* Paging stuff.
1908	*/
1909	pVM->pgm.s.GCPtrCR3Mapping += offDelta;
1910	/** @todo move this into shadow and guest specific relocation functions. */
1911	pVM->pgm.s.pGst32BitPdRC += offDelta;
1912	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.apGstPaePDsRC); i++)
1913	{
1914	pVM->pgm.s.apGstPaePDsRC[i] += offDelta;
1915	}
1916	pVM->pgm.s.pGstPaePdptRC += offDelta;
1917
1918	pVM->pgm.s.pShwPageCR3RC += offDelta;
1919
1920	pgmR3ModeDataInit(pVM, true /* resolve GC/R0 symbols */);
1921	pgmR3ModeDataSwitch(pVM, pVM->pgm.s.enmShadowMode, pVM->pgm.s.enmGuestMode);
1922
1923	PGM_SHW_PFN(Relocate, pVM)(pVM, offDelta);
1924	PGM_GST_PFN(Relocate, pVM)(pVM, offDelta);
1925	PGM_BTH_PFN(Relocate, pVM)(pVM, offDelta);
1926
1927	/*
1928	* Trees.
1929	*/
1930	pVM->pgm.s.pTreesRC = MMHyperR3ToRC(pVM, pVM->pgm.s.pTreesR3);
1931
1932	/*
1933	* Ram ranges.
1934	*/
1935	if (pVM->pgm.s.pRamRangesR3)
1936	{
1937	/* Update the pSelfRC pointers and relink them. */
1938	for (PPGMRAMRANGE pCur = pVM->pgm.s.pRamRangesR3; pCur; pCur = pCur->pNextR3)
1939	if (!(pCur->fFlags & PGM_RAM_RANGE_FLAGS_FLOATING))
1940	pCur->pSelfRC = MMHyperCCToRC(pVM, pCur);
1941	pgmR3PhysRelinkRamRanges(pVM);
1942	}
1943
1944	/*
1945	* Update the two page directories with all page table mappings.
1946	* (One or more of them have changed, that's why we're here.)
1947	*/
1948	pVM->pgm.s.pMappingsRC = MMHyperR3ToRC(pVM, pVM->pgm.s.pMappingsR3);
1949	for (PPGMMAPPING pCur = pVM->pgm.s.pMappingsR3; pCur->pNextR3; pCur = pCur->pNextR3)
1950	pCur->pNextRC = MMHyperR3ToRC(pVM, pCur->pNextR3);
1951
1952	/* Relocate GC addresses of Page Tables. */
1953	for (PPGMMAPPING pCur = pVM->pgm.s.pMappingsR3; pCur; pCur = pCur->pNextR3)
1954	{
1955	for (RTHCUINT i = 0; i < pCur->cPTs; i++)
1956	{
1957	pCur->aPTs[i].pPTRC = MMHyperR3ToRC(pVM, pCur->aPTs[i].pPTR3);
1958	pCur->aPTs[i].paPaePTsRC = MMHyperR3ToRC(pVM, pCur->aPTs[i].paPaePTsR3);
1959	}
1960	}
1961
1962	/*
1963	* Dynamic page mapping area.
1964	*/
1965	pVM->pgm.s.paDynPageMap32BitPTEsGC += offDelta;
1966	pVM->pgm.s.paDynPageMapPaePTEsGC += offDelta;
1967	pVM->pgm.s.pbDynPageMapBaseGC += offDelta;
1968
1969	/*
1970	* The Zero page.
1971	*/
1972	pVM->pgm.s.pvZeroPgR0 = MMHyperR3ToR0(pVM, pVM->pgm.s.pvZeroPgR3);
1973	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1974	AssertRelease(pVM->pgm.s.pvZeroPgR0 != NIL_RTR0PTR \|\| !VMMIsHwVirtExtForced(pVM));
1975	#else
1976	AssertRelease(pVM->pgm.s.pvZeroPgR0 != NIL_RTR0PTR);
1977	#endif
1978
1979	/*
1980	* Physical and virtual handlers.
1981	*/
1982	RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysHandlers, true, pgmR3RelocatePhysHandler, &offDelta);
1983	RTAvlroGCPtrDoWithAll(&pVM->pgm.s.pTreesR3->VirtHandlers, true, pgmR3RelocateVirtHandler, &offDelta);
1984	RTAvlroGCPtrDoWithAll(&pVM->pgm.s.pTreesR3->HyperVirtHandlers, true, pgmR3RelocateHyperVirtHandler, &offDelta);
1985
1986	/*
1987	* The page pool.
1988	*/
1989	pgmR3PoolRelocate(pVM);
1990	}
1991
1992
1993	/**
1994	* Callback function for relocating a physical access handler.
1995	*
1996	* @returns 0 (continue enum)
1997	* @param pNode Pointer to a PGMPHYSHANDLER node.
1998	* @param pvUser Pointer to the offDelta. This is a pointer to the delta since we're
1999	* not certain the delta will fit in a void pointer for all possible configs.
2000	*/
2001	static DECLCALLBACK(int) pgmR3RelocatePhysHandler(PAVLROGCPHYSNODECORE pNode, void *pvUser)
2002	{
2003	PPGMPHYSHANDLER pHandler = (PPGMPHYSHANDLER)pNode;
2004	RTGCINTPTR offDelta = *(PRTGCINTPTR)pvUser;
2005	if (pHandler->pfnHandlerRC)
2006	pHandler->pfnHandlerRC += offDelta;
2007	if (pHandler->pvUserRC >= 0x10000)
2008	pHandler->pvUserRC += offDelta;
2009	return 0;
2010	}
2011
2012
2013	/**
2014	* Callback function for relocating a virtual access handler.
2015	*
2016	* @returns 0 (continue enum)
2017	* @param pNode Pointer to a PGMVIRTHANDLER node.
2018	* @param pvUser Pointer to the offDelta. This is a pointer to the delta since we're
2019	* not certain the delta will fit in a void pointer for all possible configs.
2020	*/
2021	static DECLCALLBACK(int) pgmR3RelocateVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser)
2022	{
2023	PPGMVIRTHANDLER pHandler = (PPGMVIRTHANDLER)pNode;
2024	RTGCINTPTR offDelta = *(PRTGCINTPTR)pvUser;
2025	Assert( pHandler->enmType == PGMVIRTHANDLERTYPE_ALL
2026	\|\| pHandler->enmType == PGMVIRTHANDLERTYPE_WRITE);
2027	Assert(pHandler->pfnHandlerRC);
2028	pHandler->pfnHandlerRC += offDelta;
2029	return 0;
2030	}
2031
2032
2033	/**
2034	* Callback function for relocating a virtual access handler for the hypervisor mapping.
2035	*
2036	* @returns 0 (continue enum)
2037	* @param pNode Pointer to a PGMVIRTHANDLER node.
2038	* @param pvUser Pointer to the offDelta. This is a pointer to the delta since we're
2039	* not certain the delta will fit in a void pointer for all possible configs.
2040	*/
2041	static DECLCALLBACK(int) pgmR3RelocateHyperVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser)
2042	{
2043	PPGMVIRTHANDLER pHandler = (PPGMVIRTHANDLER)pNode;
2044	RTGCINTPTR offDelta = *(PRTGCINTPTR)pvUser;
2045	Assert(pHandler->enmType == PGMVIRTHANDLERTYPE_HYPERVISOR);
2046	Assert(pHandler->pfnHandlerRC);
2047	pHandler->pfnHandlerRC += offDelta;
2048	return 0;
2049	}
2050
2051
2052	/**
2053	* The VM is being reset.
2054	*
2055	* For the PGM component this means that any PD write monitors
2056	* needs to be removed.
2057	*
2058	* @param pVM VM handle.
2059	*/
2060	VMMR3DECL(void) PGMR3Reset(PVM pVM)
2061	{
2062	LogFlow(("PGMR3Reset:\n"));
2063	VM_ASSERT_EMT(pVM);
2064
2065	pgmLock(pVM);
2066
2067	/*
2068	* Unfix any fixed mappings and disable CR3 monitoring.
2069	*/
2070	pVM->pgm.s.fMappingsFixed = false;
2071	pVM->pgm.s.GCPtrMappingFixed = 0;
2072	pVM->pgm.s.cbMappingFixed = 0;
2073
2074	/* Exit the guest paging mode before the pgm pool gets reset.
2075	* Important to clean up the amd64 case.
2076	*/
2077	int rc = PGM_GST_PFN(Exit, pVM)(pVM);
2078	AssertRC(rc);
2079	#ifdef DEBUG
2080	DBGFR3InfoLog(pVM, "mappings", NULL);
2081	DBGFR3InfoLog(pVM, "handlers", "all nostat");
2082	#endif
2083
2084	/*
2085	* Reset the shadow page pool.
2086	*/
2087	pgmR3PoolReset(pVM);
2088
2089	/*
2090	* Re-init other members.
2091	*/
2092	pVM->pgm.s.fA20Enabled = true;
2093
2094	/*
2095	* Clear the FFs PGM owns.
2096	*/
2097	VM_FF_CLEAR(pVM, VM_FF_PGM_SYNC_CR3);
2098	VM_FF_CLEAR(pVM, VM_FF_PGM_SYNC_CR3_NON_GLOBAL);
2099
2100	/*
2101	* Reset (zero) RAM pages.
2102	*/
2103	rc = pgmR3PhysRamReset(pVM);
2104	if (RT_SUCCESS(rc))
2105	{
2106	/*
2107	* Reset (zero) shadow ROM pages.
2108	*/
2109	rc = pgmR3PhysRomReset(pVM);
2110	if (RT_SUCCESS(rc))
2111	{
2112	/*
2113	* Switch mode back to real mode.
2114	*/
2115	rc = PGMR3ChangeMode(pVM, PGMMODE_REAL);
2116	STAM_REL_COUNTER_RESET(&pVM->pgm.s.cGuestModeChanges);
2117	}
2118	}
2119
2120	pgmUnlock(pVM);
2121	//return rc;
2122	AssertReleaseRC(rc);
2123	}
2124
2125
2126	#ifdef VBOX_STRICT
2127	/**
2128	* VM state change callback for clearing fNoMorePhysWrites after
2129	* a snapshot has been created.
2130	*/
2131	static DECLCALLBACK(void) pgmR3ResetNoMorePhysWritesFlag(PVM pVM, VMSTATE enmState, VMSTATE enmOldState, void *pvUser)
2132	{
2133	if (enmState == VMSTATE_RUNNING)
2134	pVM->pgm.s.fNoMorePhysWrites = false;
2135	}
2136	#endif
2137
2138
2139	/**
2140	* Terminates the PGM.
2141	*
2142	* @returns VBox status code.
2143	* @param pVM Pointer to VM structure.
2144	*/
2145	VMMR3DECL(int) PGMR3Term(PVM pVM)
2146	{
2147	PGMDeregisterStringFormatTypes();
2148	return PDMR3CritSectDelete(&pVM->pgm.s.CritSect);
2149	}
2150
2151
2152	/**
2153	* Terminates the per-VCPU PGM.
2154	*
2155	* Termination means cleaning up and freeing all resources,
2156	* the VM it self is at this point powered off or suspended.
2157	*
2158	* @returns VBox status code.
2159	* @param pVM The VM to operate on.
2160	*/
2161	VMMR3DECL(int) PGMR3TermCPU(PVM pVM)
2162	{
2163	return 0;
2164	}
2165
2166
2167	/**
2168	* Find the ROM tracking structure for the given page.
2169	*
2170	* @returns Pointer to the ROM page structure. NULL if the caller didn't check
2171	* that it's a ROM page.
2172	* @param pVM The VM handle.
2173	* @param GCPhys The address of the ROM page.
2174	*/
2175	static PPGMROMPAGE pgmR3GetRomPage(PVM pVM, RTGCPHYS GCPhys)
2176	{
2177	for (PPGMROMRANGE pRomRange = pVM->pgm.s.CTX_SUFF(pRomRanges);
2178	pRomRange;
2179	pRomRange = pRomRange->CTX_SUFF(pNext))
2180	{
2181	RTGCPHYS off = GCPhys - pRomRange->GCPhys;
2182	if (GCPhys - pRomRange->GCPhys < pRomRange->cb)
2183	return &pRomRange->aPages[off >> PAGE_SHIFT];
2184	}
2185	return NULL;
2186	}
2187
2188
2189	/**
2190	* Save zero indicator + bits for the specified page.
2191	*
2192	* @returns VBox status code, errors are logged/asserted before returning.
2193	* @param pVM The VM handle.
2194	* @param pSSH The saved state handle.
2195	* @param pPage The page to save.
2196	* @param GCPhys The address of the page.
2197	* @param pRam The ram range (for error logging).
2198	*/
2199	static int pgmR3SavePage(PVM pVM, PSSMHANDLE pSSM, PPGMPAGE pPage, RTGCPHYS GCPhys, PPGMRAMRANGE pRam)
2200	{
2201	int rc;
2202	if (PGM_PAGE_IS_ZERO(pPage))
2203	rc = SSMR3PutU8(pSSM, 0);
2204	else
2205	{
2206	void const *pvPage;
2207	rc = pgmPhysGCPhys2CCPtrInternalReadOnly(pVM, pPage, GCPhys, &pvPage);
2208	AssertLogRelMsgRCReturn(rc, ("pPage=%R[pgmpage] GCPhys=%#x %s\n", pPage, GCPhys, pRam->pszDesc), rc);
2209
2210	SSMR3PutU8(pSSM, 1);
2211	rc = SSMR3PutMem(pSSM, pvPage, PAGE_SIZE);
2212	}
2213	return rc;
2214	}
2215
2216
2217	/**
2218	* Save a shadowed ROM page.
2219	*
2220	* Format: Type, protection, and two pages with zero indicators.
2221	*
2222	* @returns VBox status code, errors are logged/asserted before returning.
2223	* @param pVM The VM handle.
2224	* @param pSSH The saved state handle.
2225	* @param pPage The page to save.
2226	* @param GCPhys The address of the page.
2227	* @param pRam The ram range (for error logging).
2228	*/
2229	static int pgmR3SaveShadowedRomPage(PVM pVM, PSSMHANDLE pSSM, PPGMPAGE pPage, RTGCPHYS GCPhys, PPGMRAMRANGE pRam)
2230	{
2231	/* Need to save both pages and the current state. */
2232	PPGMROMPAGE pRomPage = pgmR3GetRomPage(pVM, GCPhys);
2233	AssertLogRelMsgReturn(pRomPage, ("GCPhys=%RGp %s\n", GCPhys, pRam->pszDesc), VERR_INTERNAL_ERROR);
2234
2235	SSMR3PutU8(pSSM, PGMPAGETYPE_ROM_SHADOW);
2236	SSMR3PutU8(pSSM, pRomPage->enmProt);
2237
2238	int rc = pgmR3SavePage(pVM, pSSM, pPage, GCPhys, pRam);
2239	if (RT_SUCCESS(rc))
2240	{
2241	PPGMPAGE pPagePassive = PGMROMPROT_IS_ROM(pRomPage->enmProt) ? &pRomPage->Shadow : &pRomPage->Virgin;
2242	rc = pgmR3SavePage(pVM, pSSM, pPagePassive, GCPhys, pRam);
2243	}
2244	return rc;
2245	}
2246
2247	/** PGM fields to save/load. */
2248	static SSMFIELD s_aPGMFields[] =
2249	{
2250	SSMFIELD_ENTRY( PGM, fMappingsFixed),
2251	SSMFIELD_ENTRY_GCPTR( PGM, GCPtrMappingFixed),
2252	SSMFIELD_ENTRY( PGM, cbMappingFixed),
2253	SSMFIELD_ENTRY( PGM, fA20Enabled),
2254	SSMFIELD_ENTRY_GCPHYS( PGM, GCPhysA20Mask),
2255	SSMFIELD_ENTRY( PGM, enmGuestMode),
2256	SSMFIELD_ENTRY_TERM()
2257	};
2258
2259
2260	/**
2261	* Execute state save operation.
2262	*
2263	* @returns VBox status code.
2264	* @param pVM VM Handle.
2265	* @param pSSM SSM operation handle.
2266	*/
2267	static DECLCALLBACK(int) pgmR3Save(PVM pVM, PSSMHANDLE pSSM)
2268	{
2269	int rc;
2270	PPGM pPGM = &pVM->pgm.s;
2271
2272	/*
2273	* Lock PGM and set the no-more-writes indicator.
2274	*/
2275	pgmLock(pVM);
2276	pVM->pgm.s.fNoMorePhysWrites = true;
2277
2278	/*
2279	* Save basic data (required / unaffected by relocation).
2280	*/
2281	SSMR3PutStruct(pSSM, pPGM, &s_aPGMFields[0]);
2282
2283	/*
2284	* The guest mappings.
2285	*/
2286	uint32_t i = 0;
2287	for (PPGMMAPPING pMapping = pPGM->pMappingsR3; pMapping; pMapping = pMapping->pNextR3, i++)
2288	{
2289	SSMR3PutU32( pSSM, i);
2290	SSMR3PutStrZ( pSSM, pMapping->pszDesc); /* This is the best unique id we have... */
2291	SSMR3PutGCPtr( pSSM, pMapping->GCPtr);
2292	SSMR3PutGCUIntPtr(pSSM, pMapping->cPTs);
2293	}
2294	rc = SSMR3PutU32(pSSM, ~0); /* terminator. */
2295
2296	/*
2297	* Ram ranges and the memory they describe.
2298	*/
2299	i = 0;
2300	for (PPGMRAMRANGE pRam = pPGM->pRamRangesR3; pRam; pRam = pRam->pNextR3, i++)
2301	{
2302	/*
2303	* Save the ram range details.
2304	*/
2305	SSMR3PutU32(pSSM, i);
2306	SSMR3PutGCPhys(pSSM, pRam->GCPhys);
2307	SSMR3PutGCPhys(pSSM, pRam->GCPhysLast);
2308	SSMR3PutGCPhys(pSSM, pRam->cb);
2309	SSMR3PutU8(pSSM, !!pRam->pvR3); /* Boolean indicating memory or not. */
2310	SSMR3PutStrZ(pSSM, pRam->pszDesc); /* This is the best unique id we have... */
2311
2312	/*
2313	* Iterate the pages, only two special case.
2314	*/
2315	uint32_t const cPages = pRam->cb >> PAGE_SHIFT;
2316	for (uint32_t iPage = 0; iPage < cPages; iPage++)
2317	{
2318	RTGCPHYS GCPhysPage = pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT);
2319	PPGMPAGE pPage = &pRam->aPages[iPage];
2320	uint8_t uType = PGM_PAGE_GET_TYPE(pPage);
2321
2322	if (uType == PGMPAGETYPE_ROM_SHADOW)
2323	rc = pgmR3SaveShadowedRomPage(pVM, pSSM, pPage, GCPhysPage, pRam);
2324	else if (uType == PGMPAGETYPE_MMIO2_ALIAS_MMIO)
2325	{
2326	/* MMIO2 alias -> MMIO; the device will just have to deal with this. */
2327	SSMR3PutU8(pSSM, PGMPAGETYPE_MMIO);
2328	rc = SSMR3PutU8(pSSM, 0 /* ZERO */);
2329	}
2330	else
2331	{
2332	SSMR3PutU8(pSSM, uType);
2333	rc = pgmR3SavePage(pVM, pSSM, pPage, GCPhysPage, pRam);
2334	}
2335	if (RT_FAILURE(rc))
2336	break;
2337	}
2338	if (RT_FAILURE(rc))
2339	break;
2340	}
2341
2342	pgmUnlock(pVM);
2343	return SSMR3PutU32(pSSM, ~0); /* terminator. */
2344	}
2345
2346
2347	/**
2348	* Load an ignored page.
2349	*
2350	* @returns VBox status code.
2351	* @param pSSM The saved state handle.
2352	*/
2353	static int pgmR3LoadPageToDevNull(PSSMHANDLE pSSM)
2354	{
2355	uint8_t abPage[PAGE_SIZE];
2356	return SSMR3GetMem(pSSM, &abPage[0], sizeof(abPage));
2357	}
2358
2359
2360	/**
2361	* Loads a page without any bits in the saved state, i.e. making sure it's
2362	* really zero.
2363	*
2364	* @returns VBox status code.
2365	* @param pVM The VM handle.
2366	* @param uType The page type or PGMPAGETYPE_INVALID (old saved
2367	* state).
2368	* @param pPage The guest page tracking structure.
2369	* @param GCPhys The page address.
2370	* @param pRam The ram range (logging).
2371	*/
2372	static int pgmR3LoadPageZero(PVM pVM, uint8_t uType, PPGMPAGE pPage, RTGCPHYS GCPhys, PPGMRAMRANGE pRam)
2373	{
2374	if ( PGM_PAGE_GET_TYPE(pPage) != uType
2375	&& uType != PGMPAGETYPE_INVALID)
2376	return VERR_SSM_UNEXPECTED_DATA;
2377
2378	/* I think this should be sufficient. */
2379	if (!PGM_PAGE_IS_ZERO(pPage))
2380	return VERR_SSM_UNEXPECTED_DATA;
2381
2382	NOREF(pVM);
2383	NOREF(GCPhys);
2384	NOREF(pRam);
2385	return VINF_SUCCESS;
2386	}
2387
2388
2389	/**
2390	* Loads a page from the saved state.
2391	*
2392	* @returns VBox status code.
2393	* @param pVM The VM handle.
2394	* @param pSSM The SSM handle.
2395	* @param uType The page type or PGMPAGETYEP_INVALID (old saved
2396	* state).
2397	* @param pPage The guest page tracking structure.
2398	* @param GCPhys The page address.
2399	* @param pRam The ram range (logging).
2400	*/
2401	static int pgmR3LoadPageBits(PVM pVM, PSSMHANDLE pSSM, uint8_t uType, PPGMPAGE pPage, RTGCPHYS GCPhys, PPGMRAMRANGE pRam)
2402	{
2403	int rc;
2404
2405	/*
2406	* Match up the type, dealing with MMIO2 aliases (dropped).
2407	*/
2408	AssertLogRelMsgReturn( PGM_PAGE_GET_TYPE(pPage) == uType
2409	\|\| uType == PGMPAGETYPE_INVALID,
2410	("pPage=%R[pgmpage] GCPhys=%#x %s\n", pPage, GCPhys, pRam->pszDesc),
2411	VERR_SSM_UNEXPECTED_DATA);
2412
2413	/*
2414	* Load the page.
2415	*/
2416	void *pvPage;
2417	rc = pgmPhysGCPhys2CCPtrInternal(pVM, pPage, GCPhys, &pvPage);
2418	if (RT_SUCCESS(rc))
2419	rc = SSMR3GetMem(pSSM, pvPage, PAGE_SIZE);
2420
2421	return rc;
2422	}
2423
2424
2425	/**
2426	* Loads a page (counter part to pgmR3SavePage).
2427	*
2428	* @returns VBox status code, fully bitched errors.
2429	* @param pVM The VM handle.
2430	* @param pSSM The SSM handle.
2431	* @param uType The page type.
2432	* @param pPage The page.
2433	* @param GCPhys The page address.
2434	* @param pRam The RAM range (for error messages).
2435	*/
2436	static int pgmR3LoadPage(PVM pVM, PSSMHANDLE pSSM, uint8_t uType, PPGMPAGE pPage, RTGCPHYS GCPhys, PPGMRAMRANGE pRam)
2437	{
2438	uint8_t uState;
2439	int rc = SSMR3GetU8(pSSM, &uState);
2440	AssertLogRelMsgRCReturn(rc, ("pPage=%R[pgmpage] GCPhys=%#x %s rc=%Rrc\n", pPage, GCPhys, pRam->pszDesc, rc), rc);
2441	if (uState == 0 /* zero */)
2442	rc = pgmR3LoadPageZero(pVM, uType, pPage, GCPhys, pRam);
2443	else if (uState == 1)
2444	rc = pgmR3LoadPageBits(pVM, pSSM, uType, pPage, GCPhys, pRam);
2445	else
2446	rc = VERR_INTERNAL_ERROR;
2447	AssertLogRelMsgRCReturn(rc, ("pPage=%R[pgmpage] uState=%d uType=%d GCPhys=%RGp %s rc=%Rrc\n",
2448	pPage, uState, uType, GCPhys, pRam->pszDesc, rc),
2449	rc);
2450	return VINF_SUCCESS;
2451	}
2452
2453
2454	/**
2455	* Loads a shadowed ROM page.
2456	*
2457	* @returns VBox status code, errors are fully bitched.
2458	* @param pVM The VM handle.
2459	* @param pSSM The saved state handle.
2460	* @param pPage The page.
2461	* @param GCPhys The page address.
2462	* @param pRam The RAM range (for error messages).
2463	*/
2464	static int pgmR3LoadShadowedRomPage(PVM pVM, PSSMHANDLE pSSM, PPGMPAGE pPage, RTGCPHYS GCPhys, PPGMRAMRANGE pRam)
2465	{
2466	/*
2467	* Load and set the protection first, then load the two pages, the first
2468	* one is the active the other is the passive.
2469	*/
2470	PPGMROMPAGE pRomPage = pgmR3GetRomPage(pVM, GCPhys);
2471	AssertLogRelMsgReturn(pRomPage, ("GCPhys=%RGp %s\n", GCPhys, pRam->pszDesc), VERR_INTERNAL_ERROR);
2472
2473	uint8_t uProt;
2474	int rc = SSMR3GetU8(pSSM, &uProt);
2475	AssertLogRelMsgRCReturn(rc, ("pPage=%R[pgmpage] GCPhys=%#x %s\n", pPage, GCPhys, pRam->pszDesc), rc);
2476	PGMROMPROT enmProt = (PGMROMPROT)uProt;
2477	AssertLogRelMsgReturn( enmProt >= PGMROMPROT_INVALID
2478	&& enmProt < PGMROMPROT_END,
2479	("enmProt=%d pPage=%R[pgmpage] GCPhys=%#x %s\n", enmProt, pPage, GCPhys, pRam->pszDesc),
2480	VERR_SSM_UNEXPECTED_DATA);
2481
2482	if (pRomPage->enmProt != enmProt)
2483	{
2484	rc = PGMR3PhysRomProtect(pVM, GCPhys, PAGE_SIZE, enmProt);
2485	AssertLogRelRCReturn(rc, rc);
2486	AssertLogRelReturn(pRomPage->enmProt == enmProt, VERR_INTERNAL_ERROR);
2487	}
2488
2489	PPGMPAGE pPageActive = PGMROMPROT_IS_ROM(enmProt) ? &pRomPage->Virgin : &pRomPage->Shadow;
2490	PPGMPAGE pPagePassive = PGMROMPROT_IS_ROM(enmProt) ? &pRomPage->Shadow : &pRomPage->Virgin;
2491	uint8_t u8ActiveType = PGMROMPROT_IS_ROM(enmProt) ? PGMPAGETYPE_ROM : PGMPAGETYPE_ROM_SHADOW;
2492	uint8_t u8PassiveType= PGMROMPROT_IS_ROM(enmProt) ? PGMPAGETYPE_ROM_SHADOW : PGMPAGETYPE_ROM;
2493
2494	rc = pgmR3LoadPage(pVM, pSSM, u8ActiveType, pPage, GCPhys, pRam);
2495	if (RT_SUCCESS(rc))
2496	{
2497	pPageActive = pPage;
2498	rc = pgmR3LoadPage(pVM, pSSM, u8PassiveType, pPagePassive, GCPhys, pRam);
2499	}
2500	return rc;
2501	}
2502
2503
2504	/**
2505	* Worker for pgmR3Load.
2506	*
2507	* @returns VBox status code.
2508	*
2509	* @param pVM The VM handle.
2510	* @param pSSM The SSM handle.
2511	* @param u32Version The saved state version.
2512	*/
2513	static int pgmR3LoadLocked(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version)
2514	{
2515	int rc;
2516	PPGM pPGM = &pVM->pgm.s;
2517	uint32_t u32Sep;
2518
2519	/*
2520	* Load basic data (required / unaffected by relocation).
2521	*/
2522	if (u32Version >= PGM_SAVED_STATE_VERSION_RR_DESC)
2523	{
2524	rc = SSMR3GetStruct(pSSM, pPGM, &s_aPGMFields[0]);
2525	AssertLogRelRCReturn(rc, rc);
2526	}
2527	else
2528	{
2529	SSMR3GetBool(pSSM, &pPGM->fMappingsFixed);
2530	SSMR3GetGCPtr(pSSM, &pPGM->GCPtrMappingFixed);
2531	SSMR3GetU32(pSSM, &pPGM->cbMappingFixed);
2532
2533	uint32_t cbRamSizeIgnored;
2534	rc = SSMR3GetU32(pSSM, &cbRamSizeIgnored);
2535	if (RT_FAILURE(rc))
2536	return rc;
2537	SSMR3GetGCPhys(pSSM, &pPGM->GCPhysA20Mask);
2538
2539	uint32_t u32 = 0;
2540	SSMR3GetUInt(pSSM, &u32);
2541	pPGM->fA20Enabled = !!u32;
2542	SSMR3GetUInt(pSSM, &pPGM->fSyncFlags);
2543	RTUINT uGuestMode;
2544	SSMR3GetUInt(pSSM, &uGuestMode);
2545	pPGM->enmGuestMode = (PGMMODE)uGuestMode;
2546
2547	/* check separator. */
2548	SSMR3GetU32(pSSM, &u32Sep);
2549	if (RT_FAILURE(rc))
2550	return rc;
2551	if (u32Sep != (uint32_t)~0)
2552	{
2553	AssertMsgFailed(("u32Sep=%#x (first)\n", u32Sep));
2554	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2555	}
2556	}
2557
2558	/*
2559	* The guest mappings.
2560	*/
2561	uint32_t i = 0;
2562	for (;; i++)
2563	{
2564	/* Check the seqence number / separator. */
2565	rc = SSMR3GetU32(pSSM, &u32Sep);
2566	if (RT_FAILURE(rc))
2567	return rc;
2568	if (u32Sep == ~0U)
2569	break;
2570	if (u32Sep != i)
2571	{
2572	AssertMsgFailed(("u32Sep=%#x (last)\n", u32Sep));
2573	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2574	}
2575
2576	/* get the mapping details. */
2577	char szDesc[256];
2578	szDesc[0] = '\0';
2579	rc = SSMR3GetStrZ(pSSM, szDesc, sizeof(szDesc));
2580	if (RT_FAILURE(rc))
2581	return rc;
2582	RTGCPTR GCPtr;
2583	SSMR3GetGCPtr(pSSM, &GCPtr);
2584	RTGCPTR cPTs;
2585	rc = SSMR3GetGCUIntPtr(pSSM, &cPTs);
2586	if (RT_FAILURE(rc))
2587	return rc;
2588
2589	/* find matching range. */
2590	PPGMMAPPING pMapping;
2591	for (pMapping = pPGM->pMappingsR3; pMapping; pMapping = pMapping->pNextR3)
2592	if ( pMapping->cPTs == cPTs
2593	&& !strcmp(pMapping->pszDesc, szDesc))
2594	break;
2595	AssertLogRelMsgReturn(pMapping, ("Couldn't find mapping: cPTs=%#x szDesc=%s (GCPtr=%RGv)\n",
2596	cPTs, szDesc, GCPtr),
2597	VERR_SSM_LOAD_CONFIG_MISMATCH);
2598
2599	/* relocate it. */
2600	if (pMapping->GCPtr != GCPtr)
2601	{
2602	AssertMsg((GCPtr >> X86_PD_SHIFT << X86_PD_SHIFT) == GCPtr, ("GCPtr=%RGv\n", GCPtr));
2603	pgmR3MapRelocate(pVM, pMapping, pMapping->GCPtr, GCPtr);
2604	}
2605	else
2606	Log(("pgmR3Load: '%s' needed no relocation (%RGv)\n", szDesc, GCPtr));
2607	}
2608
2609	/*
2610	* Ram range flags and bits.
2611	*/
2612	i = 0;
2613	for (PPGMRAMRANGE pRam = pPGM->pRamRangesR3; pRam; pRam = pRam->pNextR3, i++)
2614	{
2615	/** @todo MMIO ranges may move (PCI reconfig), we currently assume they don't. */
2616
2617	/* Check the seqence number / separator. */
2618	rc = SSMR3GetU32(pSSM, &u32Sep);
2619	if (RT_FAILURE(rc))
2620	return rc;
2621	if (u32Sep == ~0U)
2622	break;
2623	if (u32Sep != i)
2624	{
2625	AssertMsgFailed(("u32Sep=%#x (last)\n", u32Sep));
2626	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2627	}
2628
2629	/* Get the range details. */
2630	RTGCPHYS GCPhys;
2631	SSMR3GetGCPhys(pSSM, &GCPhys);
2632	RTGCPHYS GCPhysLast;
2633	SSMR3GetGCPhys(pSSM, &GCPhysLast);
2634	RTGCPHYS cb;
2635	SSMR3GetGCPhys(pSSM, &cb);
2636	uint8_t fHaveBits;
2637	rc = SSMR3GetU8(pSSM, &fHaveBits);
2638	if (RT_FAILURE(rc))
2639	return rc;
2640	if (fHaveBits & ~1)
2641	{
2642	AssertMsgFailed(("u32Sep=%#x (last)\n", u32Sep));
2643	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2644	}
2645	size_t cchDesc = 0;
2646	char szDesc[256];
2647	szDesc[0] = '\0';
2648	if (u32Version >= PGM_SAVED_STATE_VERSION_RR_DESC)
2649	{
2650	rc = SSMR3GetStrZ(pSSM, szDesc, sizeof(szDesc));
2651	if (RT_FAILURE(rc))
2652	return rc;
2653	/* Since we've modified the description strings in r45878, only compare
2654	them if the saved state is more recent. */
2655	if (u32Version != PGM_SAVED_STATE_VERSION_RR_DESC)
2656	cchDesc = strlen(szDesc);
2657	}
2658
2659	/*
2660	* Match it up with the current range.
2661	*
2662	* Note there is a hack for dealing with the high BIOS mapping
2663	* in the old saved state format, this means we might not have
2664	* a 1:1 match on success.
2665	*/
2666	if ( ( GCPhys != pRam->GCPhys
2667	\|\| GCPhysLast != pRam->GCPhysLast
2668	\|\| cb != pRam->cb
2669	\|\| ( cchDesc
2670	&& strcmp(szDesc, pRam->pszDesc)) )
2671	/* Hack for PDMDevHlpPhysReserve(pDevIns, 0xfff80000, 0x80000, "High ROM Region"); */
2672	&& ( u32Version != PGM_SAVED_STATE_VERSION_OLD_PHYS_CODE
2673	\|\| GCPhys != UINT32_C(0xfff80000)
2674	\|\| GCPhysLast != UINT32_C(0xffffffff)
2675	\|\| pRam->GCPhysLast != GCPhysLast
2676	\|\| pRam->GCPhys < GCPhys
2677	\|\| !fHaveBits)
2678	)
2679	{
2680	LogRel(("Ram range: %RGp-%RGp %RGp bytes %s %s\n"
2681	"State : %RGp-%RGp %RGp bytes %s %s\n",
2682	pRam->GCPhys, pRam->GCPhysLast, pRam->cb, pRam->pvR3 ? "bits" : "nobits", pRam->pszDesc,
2683	GCPhys, GCPhysLast, cb, fHaveBits ? "bits" : "nobits", szDesc));
2684	/*
2685	* If we're loading a state for debugging purpose, don't make a fuss if
2686	* the MMIO and ROM stuff isn't 100% right, just skip the mismatches.
2687	*/
2688	if ( SSMR3HandleGetAfter(pSSM) != SSMAFTER_DEBUG_IT
2689	\|\| GCPhys < 8 * _1M)
2690	AssertFailedReturn(VERR_SSM_LOAD_CONFIG_MISMATCH);
2691
2692	AssertMsgFailed(("debug skipping not implemented, sorry\n"));
2693	continue;
2694	}
2695
2696	uint32_t cPages = (GCPhysLast - GCPhys + 1) >> PAGE_SHIFT;
2697	if (u32Version >= PGM_SAVED_STATE_VERSION_RR_DESC)
2698	{
2699	/*
2700	* Load the pages one by one.
2701	*/
2702	for (uint32_t iPage = 0; iPage < cPages; iPage++)
2703	{
2704	RTGCPHYS const GCPhysPage = ((RTGCPHYS)iPage << PAGE_SHIFT) + pRam->GCPhys;
2705	PPGMPAGE pPage = &pRam->aPages[iPage];
2706	uint8_t uType;
2707	rc = SSMR3GetU8(pSSM, &uType);
2708	AssertLogRelMsgRCReturn(rc, ("pPage=%R[pgmpage] iPage=%#x GCPhysPage=%#x %s\n", pPage, iPage, GCPhysPage, pRam->pszDesc), rc);
2709	if (uType == PGMPAGETYPE_ROM_SHADOW)
2710	rc = pgmR3LoadShadowedRomPage(pVM, pSSM, pPage, GCPhysPage, pRam);
2711	else
2712	rc = pgmR3LoadPage(pVM, pSSM, uType, pPage, GCPhysPage, pRam);
2713	AssertLogRelMsgRCReturn(rc, ("rc=%Rrc iPage=%#x GCPhysPage=%#x %s\n", rc, iPage, GCPhysPage, pRam->pszDesc), rc);
2714	}
2715	}
2716	else
2717	{
2718	/*
2719	* Old format.
2720	*/
2721	AssertLogRelReturn(!pVM->pgm.s.fRamPreAlloc, VERR_NOT_SUPPORTED); /* can't be detected. */
2722
2723	/* Of the page flags, pick up MMIO2 and ROM/RESERVED for the !fHaveBits case.
2724	The rest is generally irrelevant and wrong since the stuff have to match registrations. */
2725	uint32_t fFlags = 0;
2726	for (uint32_t iPage = 0; iPage < cPages; iPage++)
2727	{
2728	uint16_t u16Flags;
2729	rc = SSMR3GetU16(pSSM, &u16Flags);
2730	AssertLogRelMsgRCReturn(rc, ("rc=%Rrc iPage=%#x GCPhys=%#x %s\n", rc, iPage, pRam->GCPhys, pRam->pszDesc), rc);
2731	fFlags \|= u16Flags;
2732	}
2733
2734	/* Load the bits */
2735	if ( !fHaveBits
2736	&& GCPhysLast < UINT32_C(0xe0000000))
2737	{
2738	/*
2739	* Dynamic chunks.
2740	*/
2741	const uint32_t cPagesInChunk = (110241024) >> PAGE_SHIFT;
2742	AssertLogRelMsgReturn(cPages % cPagesInChunk == 0,
2743	("cPages=%#x cPagesInChunk=%#x\n", cPages, cPagesInChunk, pRam->GCPhys, pRam->pszDesc),
2744	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2745
2746	for (uint32_t iPage = 0; iPage < cPages; /* incremented by inner loop */ )
2747	{
2748	uint8_t fPresent;
2749	rc = SSMR3GetU8(pSSM, &fPresent);
2750	AssertLogRelMsgRCReturn(rc, ("rc=%Rrc iPage=%#x GCPhys=%#x %s\n", rc, iPage, pRam->GCPhys, pRam->pszDesc), rc);
2751	AssertLogRelMsgReturn(fPresent == (uint8_t)true \|\| fPresent == (uint8_t)false,
2752	("fPresent=%#x iPage=%#x GCPhys=%#x %s\n", fPresent, iPage, pRam->GCPhys, pRam->pszDesc),
2753	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2754
2755	for (uint32_t iChunkPage = 0; iChunkPage < cPagesInChunk; iChunkPage++, iPage++)
2756	{
2757	RTGCPHYS const GCPhysPage = ((RTGCPHYS)iPage << PAGE_SHIFT) + pRam->GCPhys;
2758	PPGMPAGE pPage = &pRam->aPages[iPage];
2759	if (fPresent)
2760	{
2761	if (PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_MMIO)
2762	rc = pgmR3LoadPageToDevNull(pSSM);
2763	else
2764	rc = pgmR3LoadPageBits(pVM, pSSM, PGMPAGETYPE_INVALID, pPage, GCPhysPage, pRam);
2765	}
2766	else
2767	rc = pgmR3LoadPageZero(pVM, PGMPAGETYPE_INVALID, pPage, GCPhysPage, pRam);
2768	AssertLogRelMsgRCReturn(rc, ("rc=%Rrc iPage=%#x GCPhysPage=%#x %s\n", rc, iPage, GCPhysPage, pRam->pszDesc), rc);
2769	}
2770	}
2771	}
2772	else if (pRam->pvR3)
2773	{
2774	/*
2775	* MMIO2.
2776	*/
2777	AssertLogRelMsgReturn((fFlags & 0x0f) == RT_BIT(3) /MM_RAM_FLAGS_MMIO2/,
2778	("fFlags=%#x GCPhys=%#x %s\n", fFlags, pRam->GCPhys, pRam->pszDesc),
2779	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2780	AssertLogRelMsgReturn(pRam->pvR3,
2781	("GCPhys=%#x %s\n", pRam->GCPhys, pRam->pszDesc),
2782	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2783
2784	rc = SSMR3GetMem(pSSM, pRam->pvR3, pRam->cb);
2785	AssertLogRelMsgRCReturn(rc, ("GCPhys=%#x %s\n", pRam->GCPhys, pRam->pszDesc), rc);
2786	}
2787	else if (GCPhysLast < UINT32_C(0xfff80000))
2788	{
2789	/*
2790	* PCI MMIO, no pages saved.
2791	*/
2792	}
2793	else
2794	{
2795	/*
2796	* Load the 0xfff80000..0xffffffff BIOS range.
2797	* It starts with X reserved pages that we have to skip over since
2798	* the RAMRANGE create by the new code won't include those.
2799	*/
2800	AssertLogRelMsgReturn( !(fFlags & RT_BIT(3) /MM_RAM_FLAGS_MMIO2/)
2801	&& (fFlags & RT_BIT(0) /MM_RAM_FLAGS_RESERVED/),
2802	("fFlags=%#x GCPhys=%#x %s\n", fFlags, pRam->GCPhys, pRam->pszDesc),
2803	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2804	AssertLogRelMsgReturn(GCPhys == UINT32_C(0xfff80000),
2805	("GCPhys=%RGp pRamRange{GCPhys=%#x %s}\n", GCPhys, pRam->GCPhys, pRam->pszDesc),
2806	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2807
2808	/* Skip wasted reserved pages before the ROM. */
2809	while (GCPhys < pRam->GCPhys)
2810	{
2811	rc = pgmR3LoadPageToDevNull(pSSM);
2812	GCPhys += PAGE_SIZE;
2813	}
2814
2815	/* Load the bios pages. */
2816	cPages = pRam->cb >> PAGE_SHIFT;
2817	for (uint32_t iPage = 0; iPage < cPages; iPage++)
2818	{
2819	RTGCPHYS const GCPhysPage = ((RTGCPHYS)iPage << PAGE_SHIFT) + pRam->GCPhys;
2820	PPGMPAGE pPage = &pRam->aPages[iPage];
2821
2822	AssertLogRelMsgReturn(PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_ROM,
2823	("GCPhys=%RGp pPage=%R[pgmpage]\n", GCPhys, GCPhys),
2824	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2825	rc = pgmR3LoadPageBits(pVM, pSSM, PGMPAGETYPE_ROM, pPage, GCPhysPage, pRam);
2826	AssertLogRelMsgRCReturn(rc, ("rc=%Rrc iPage=%#x GCPhys=%#x %s\n", rc, iPage, pRam->GCPhys, pRam->pszDesc), rc);
2827	}
2828	}
2829	}
2830	}
2831
2832	return rc;
2833	}
2834
2835
2836	/**
2837	* Execute state load operation.
2838	*
2839	* @returns VBox status code.
2840	* @param pVM VM Handle.
2841	* @param pSSM SSM operation handle.
2842	* @param u32Version Data layout version.
2843	*/
2844	static DECLCALLBACK(int) pgmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version)
2845	{
2846	int rc;
2847	PPGM pPGM = &pVM->pgm.s;
2848
2849	/*
2850	* Validate version.
2851	*/
2852	if ( u32Version != PGM_SAVED_STATE_VERSION
2853	&& u32Version != PGM_SAVED_STATE_VERSION_RR_DESC
2854	&& u32Version != PGM_SAVED_STATE_VERSION_OLD_PHYS_CODE)
2855	{
2856	AssertMsgFailed(("pgmR3Load: Invalid version u32Version=%d (current %d)!\n", u32Version, PGM_SAVED_STATE_VERSION));
2857	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
2858	}
2859
2860	/*
2861	* Call the reset function to make sure all the memory is cleared.
2862	*/
2863	PGMR3Reset(pVM);
2864
2865	/*
2866	* Do the loading while owning the lock because a bunch of the functions
2867	* we're using requires this.
2868	*/
2869	pgmLock(pVM);
2870	rc = pgmR3LoadLocked(pVM, pSSM, u32Version);
2871	pgmUnlock(pVM);
2872	if (RT_SUCCESS(rc))
2873	{
2874	/*
2875	* We require a full resync now.
2876	*/
2877	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3_NON_GLOBAL);
2878	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
2879	pPGM->fSyncFlags \|= PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL;
2880	pPGM->fPhysCacheFlushPending = true;
2881	pgmR3HandlerPhysicalUpdateAll(pVM);
2882
2883	/*
2884	* Change the paging mode.
2885	*/
2886	rc = PGMR3ChangeMode(pVM, pPGM->enmGuestMode);
2887
2888	/* Restore pVM->pgm.s.GCPhysCR3. */
2889	Assert(pVM->pgm.s.GCPhysCR3 == NIL_RTGCPHYS);
2890	RTGCPHYS GCPhysCR3 = CPUMGetGuestCR3(pVM);
2891	if ( pVM->pgm.s.enmGuestMode == PGMMODE_PAE
2892	\|\| pVM->pgm.s.enmGuestMode == PGMMODE_PAE_NX
2893	\|\| pVM->pgm.s.enmGuestMode == PGMMODE_AMD64
2894	\|\| pVM->pgm.s.enmGuestMode == PGMMODE_AMD64_NX)
2895	GCPhysCR3 = (GCPhysCR3 & X86_CR3_PAE_PAGE_MASK);
2896	else
2897	GCPhysCR3 = (GCPhysCR3 & X86_CR3_PAGE_MASK);
2898	pVM->pgm.s.GCPhysCR3 = GCPhysCR3;
2899	}
2900
2901	return rc;
2902	}
2903
2904
2905	/**
2906	* Show paging mode.
2907	*
2908	* @param pVM VM Handle.
2909	* @param pHlp The info helpers.
2910	* @param pszArgs "all" (default), "guest", "shadow" or "host".
2911	*/
2912	static DECLCALLBACK(void) pgmR3InfoMode(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2913	{
2914	/* digest argument. */
2915	bool fGuest, fShadow, fHost;
2916	if (pszArgs)
2917	pszArgs = RTStrStripL(pszArgs);
2918	if (!pszArgs \|\| !*pszArgs \|\| strstr(pszArgs, "all"))
2919	fShadow = fHost = fGuest = true;
2920	else
2921	{
2922	fShadow = fHost = fGuest = false;
2923	if (strstr(pszArgs, "guest"))
2924	fGuest = true;
2925	if (strstr(pszArgs, "shadow"))
2926	fShadow = true;
2927	if (strstr(pszArgs, "host"))
2928	fHost = true;
2929	}
2930
2931	/* print info. */
2932	if (fGuest)
2933	pHlp->pfnPrintf(pHlp, "Guest paging mode: %s, changed %RU64 times, A20 %s\n",
2934	PGMGetModeName(pVM->pgm.s.enmGuestMode), pVM->pgm.s.cGuestModeChanges.c,
2935	pVM->pgm.s.fA20Enabled ? "enabled" : "disabled");
2936	if (fShadow)
2937	pHlp->pfnPrintf(pHlp, "Shadow paging mode: %s\n", PGMGetModeName(pVM->pgm.s.enmShadowMode));
2938	if (fHost)
2939	{
2940	const char *psz;
2941	switch (pVM->pgm.s.enmHostMode)
2942	{
2943	case SUPPAGINGMODE_INVALID: psz = "invalid"; break;
2944	case SUPPAGINGMODE_32_BIT: psz = "32-bit"; break;
2945	case SUPPAGINGMODE_32_BIT_GLOBAL: psz = "32-bit+G"; break;
2946	case SUPPAGINGMODE_PAE: psz = "PAE"; break;
2947	case SUPPAGINGMODE_PAE_GLOBAL: psz = "PAE+G"; break;
2948	case SUPPAGINGMODE_PAE_NX: psz = "PAE+NX"; break;
2949	case SUPPAGINGMODE_PAE_GLOBAL_NX: psz = "PAE+G+NX"; break;
2950	case SUPPAGINGMODE_AMD64: psz = "AMD64"; break;
2951	case SUPPAGINGMODE_AMD64_GLOBAL: psz = "AMD64+G"; break;
2952	case SUPPAGINGMODE_AMD64_NX: psz = "AMD64+NX"; break;
2953	case SUPPAGINGMODE_AMD64_GLOBAL_NX: psz = "AMD64+G+NX"; break;
2954	default: psz = "unknown"; break;
2955	}
2956	pHlp->pfnPrintf(pHlp, "Host paging mode: %s\n", psz);
2957	}
2958	}
2959
2960
2961	/**
2962	* Dump registered MMIO ranges to the log.
2963	*
2964	* @param pVM VM Handle.
2965	* @param pHlp The info helpers.
2966	* @param pszArgs Arguments, ignored.
2967	*/
2968	static DECLCALLBACK(void) pgmR3PhysInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2969	{
2970	NOREF(pszArgs);
2971	pHlp->pfnPrintf(pHlp,
2972	"RAM ranges (pVM=%p)\n"
2973	"%.s %.s\n",
2974	pVM,
2975	sizeof(RTGCPHYS) * 4 + 1, "GC Phys Range ",
2976	sizeof(RTHCPTR) * 2, "pvHC ");
2977
2978	for (PPGMRAMRANGE pCur = pVM->pgm.s.pRamRangesR3; pCur; pCur = pCur->pNextR3)
2979	pHlp->pfnPrintf(pHlp,
2980	"%RGp-%RGp %RHv %s\n",
2981	pCur->GCPhys,
2982	pCur->GCPhysLast,
2983	pCur->pvR3,
2984	pCur->pszDesc);
2985	}
2986
2987	/**
2988	* Dump the page directory to the log.
2989	*
2990	* @param pVM VM Handle.
2991	* @param pHlp The info helpers.
2992	* @param pszArgs Arguments, ignored.
2993	*/
2994	static DECLCALLBACK(void) pgmR3InfoCr3(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2995	{
2996	/** @todo fix this! Convert the PGMR3DumpHierarchyHC functions to do guest stuff. */
2997	/* Big pages supported? */
2998	const bool fPSE = !!(CPUMGetGuestCR4(pVM) & X86_CR4_PSE);
2999
3000	/* Global pages supported? */
3001	const bool fPGE = !!(CPUMGetGuestCR4(pVM) & X86_CR4_PGE);
3002
3003	NOREF(pszArgs);
3004
3005	/*
3006	* Get page directory addresses.
3007	*/
3008	PX86PD pPDSrc = pgmGstGet32bitPDPtr(&pVM->pgm.s);
3009	Assert(pPDSrc);
3010	Assert(PGMPhysGCPhys2R3PtrAssert(pVM, (RTGCPHYS)(CPUMGetGuestCR3(pVM) & X86_CR3_PAGE_MASK), sizeof(*pPDSrc)) == pPDSrc);
3011
3012	/*
3013	* Iterate the page directory.
3014	*/
3015	for (unsigned iPD = 0; iPD < RT_ELEMENTS(pPDSrc->a); iPD++)
3016	{
3017	X86PDE PdeSrc = pPDSrc->a[iPD];
3018	if (PdeSrc.n.u1Present)
3019	{
3020	if (PdeSrc.b.u1Size && fPSE)
3021	pHlp->pfnPrintf(pHlp,
3022	"%04X - %RGp P=%d U=%d RW=%d G=%d - BIG\n",
3023	iPD,
3024	pgmGstGet4MBPhysPage(&pVM->pgm.s, PdeSrc),
3025	PdeSrc.b.u1Present, PdeSrc.b.u1User, PdeSrc.b.u1Write, PdeSrc.b.u1Global && fPGE);
3026	else
3027	pHlp->pfnPrintf(pHlp,
3028	"%04X - %RGp P=%d U=%d RW=%d [G=%d]\n",
3029	iPD,
3030	(RTGCPHYS)(PdeSrc.u & X86_PDE_PG_MASK),
3031	PdeSrc.n.u1Present, PdeSrc.n.u1User, PdeSrc.n.u1Write, PdeSrc.b.u1Global && fPGE);
3032	}
3033	}
3034	}
3035
3036
3037	/**
3038	* Serivce a VMMCALLHOST_PGM_LOCK call.
3039	*
3040	* @returns VBox status code.
3041	* @param pVM The VM handle.
3042	*/
3043	VMMR3DECL(int) PGMR3LockCall(PVM pVM)
3044	{
3045	int rc = PDMR3CritSectEnterEx(&pVM->pgm.s.CritSect, true /* fHostCall */);
3046	AssertRC(rc);
3047	return rc;
3048	}
3049
3050
3051	/**
3052	* Converts a PGMMODE value to a PGM_TYPE_* \#define.
3053	*
3054	* @returns PGM_TYPE_*.
3055	* @param pgmMode The mode value to convert.
3056	*/
3057	DECLINLINE(unsigned) pgmModeToType(PGMMODE pgmMode)
3058	{
3059	switch (pgmMode)
3060	{
3061	case PGMMODE_REAL: return PGM_TYPE_REAL;
3062	case PGMMODE_PROTECTED: return PGM_TYPE_PROT;
3063	case PGMMODE_32_BIT: return PGM_TYPE_32BIT;
3064	case PGMMODE_PAE:
3065	case PGMMODE_PAE_NX: return PGM_TYPE_PAE;
3066	case PGMMODE_AMD64:
3067	case PGMMODE_AMD64_NX: return PGM_TYPE_AMD64;
3068	case PGMMODE_NESTED: return PGM_TYPE_NESTED;
3069	case PGMMODE_EPT: return PGM_TYPE_EPT;
3070	default:
3071	AssertFatalMsgFailed(("pgmMode=%d\n", pgmMode));
3072	}
3073	}
3074
3075
3076	/**
3077	* Gets the index into the paging mode data array of a SHW+GST mode.
3078	*
3079	* @returns PGM::paPagingData index.
3080	* @param uShwType The shadow paging mode type.
3081	* @param uGstType The guest paging mode type.
3082	*/
3083	DECLINLINE(unsigned) pgmModeDataIndex(unsigned uShwType, unsigned uGstType)
3084	{
3085	Assert(uShwType >= PGM_TYPE_32BIT && uShwType <= PGM_TYPE_MAX);
3086	Assert(uGstType >= PGM_TYPE_REAL && uGstType <= PGM_TYPE_AMD64);
3087	return (uShwType - PGM_TYPE_32BIT) * (PGM_TYPE_AMD64 - PGM_TYPE_REAL + 1)
3088	+ (uGstType - PGM_TYPE_REAL);
3089	}
3090
3091
3092	/**
3093	* Gets the index into the paging mode data array of a SHW+GST mode.
3094	*
3095	* @returns PGM::paPagingData index.
3096	* @param enmShw The shadow paging mode.
3097	* @param enmGst The guest paging mode.
3098	*/
3099	DECLINLINE(unsigned) pgmModeDataIndexByMode(PGMMODE enmShw, PGMMODE enmGst)
3100	{
3101	Assert(enmShw >= PGMMODE_32_BIT && enmShw <= PGMMODE_MAX);
3102	Assert(enmGst > PGMMODE_INVALID && enmGst < PGMMODE_MAX);
3103	return pgmModeDataIndex(pgmModeToType(enmShw), pgmModeToType(enmGst));
3104	}
3105
3106
3107	/**
3108	* Calculates the max data index.
3109	* @returns The number of entries in the paging data array.
3110	*/
3111	DECLINLINE(unsigned) pgmModeDataMaxIndex(void)
3112	{
3113	return pgmModeDataIndex(PGM_TYPE_MAX, PGM_TYPE_AMD64) + 1;
3114	}
3115
3116
3117	/**
3118	* Initializes the paging mode data kept in PGM::paModeData.
3119	*
3120	* @param pVM The VM handle.
3121	* @param fResolveGCAndR0 Indicate whether or not GC and Ring-0 symbols can be resolved now.
3122	* This is used early in the init process to avoid trouble with PDM
3123	* not being initialized yet.
3124	*/
3125	static int pgmR3ModeDataInit(PVM pVM, bool fResolveGCAndR0)
3126	{
3127	PPGMMODEDATA pModeData;
3128	int rc;
3129
3130	/*
3131	* Allocate the array on the first call.
3132	*/
3133	if (!pVM->pgm.s.paModeData)
3134	{
3135	pVM->pgm.s.paModeData = (PPGMMODEDATA)MMR3HeapAllocZ(pVM, MM_TAG_PGM, sizeof(PGMMODEDATA) * pgmModeDataMaxIndex());
3136	AssertReturn(pVM->pgm.s.paModeData, VERR_NO_MEMORY);
3137	}
3138
3139	/*
3140	* Initialize the array entries.
3141	*/
3142	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_32BIT, PGM_TYPE_REAL)];
3143	pModeData->uShwType = PGM_TYPE_32BIT;
3144	pModeData->uGstType = PGM_TYPE_REAL;
3145	rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3146	rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3147	rc = PGM_BTH_NAME_32BIT_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3148
3149	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_32BIT, PGMMODE_PROTECTED)];
3150	pModeData->uShwType = PGM_TYPE_32BIT;
3151	pModeData->uGstType = PGM_TYPE_PROT;
3152	rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3153	rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3154	rc = PGM_BTH_NAME_32BIT_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3155
3156	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_32BIT, PGM_TYPE_32BIT)];
3157	pModeData->uShwType = PGM_TYPE_32BIT;
3158	pModeData->uGstType = PGM_TYPE_32BIT;
3159	rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3160	rc = PGM_GST_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3161	rc = PGM_BTH_NAME_32BIT_32BIT(InitData)(pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3162
3163	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_REAL)];
3164	pModeData->uShwType = PGM_TYPE_PAE;
3165	pModeData->uGstType = PGM_TYPE_REAL;
3166	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3167	rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3168	rc = PGM_BTH_NAME_PAE_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3169
3170	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_PROT)];
3171	pModeData->uShwType = PGM_TYPE_PAE;
3172	pModeData->uGstType = PGM_TYPE_PROT;
3173	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3174	rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3175	rc = PGM_BTH_NAME_PAE_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3176
3177	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_32BIT)];
3178	pModeData->uShwType = PGM_TYPE_PAE;
3179	pModeData->uGstType = PGM_TYPE_32BIT;
3180	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3181	rc = PGM_GST_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3182	rc = PGM_BTH_NAME_PAE_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3183
3184	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_PAE)];
3185	pModeData->uShwType = PGM_TYPE_PAE;
3186	pModeData->uGstType = PGM_TYPE_PAE;
3187	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3188	rc = PGM_GST_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3189	rc = PGM_BTH_NAME_PAE_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3190
3191	#ifdef VBOX_WITH_64_BITS_GUESTS
3192	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_AMD64, PGM_TYPE_AMD64)];
3193	pModeData->uShwType = PGM_TYPE_AMD64;
3194	pModeData->uGstType = PGM_TYPE_AMD64;
3195	rc = PGM_SHW_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3196	rc = PGM_GST_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3197	rc = PGM_BTH_NAME_AMD64_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3198	#endif
3199
3200	/* The nested paging mode. */
3201	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_REAL)];
3202	pModeData->uShwType = PGM_TYPE_NESTED;
3203	pModeData->uGstType = PGM_TYPE_REAL;
3204	rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3205	rc = PGM_BTH_NAME_NESTED_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3206
3207	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGMMODE_PROTECTED)];
3208	pModeData->uShwType = PGM_TYPE_NESTED;
3209	pModeData->uGstType = PGM_TYPE_PROT;
3210	rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3211	rc = PGM_BTH_NAME_NESTED_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3212
3213	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_32BIT)];
3214	pModeData->uShwType = PGM_TYPE_NESTED;
3215	pModeData->uGstType = PGM_TYPE_32BIT;
3216	rc = PGM_GST_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3217	rc = PGM_BTH_NAME_NESTED_32BIT(InitData)(pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3218
3219	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_PAE)];
3220	pModeData->uShwType = PGM_TYPE_NESTED;
3221	pModeData->uGstType = PGM_TYPE_PAE;
3222	rc = PGM_GST_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3223	rc = PGM_BTH_NAME_NESTED_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3224
3225	#ifdef VBOX_WITH_64_BITS_GUESTS
3226	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_AMD64)];
3227	pModeData->uShwType = PGM_TYPE_NESTED;
3228	pModeData->uGstType = PGM_TYPE_AMD64;
3229	rc = PGM_GST_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3230	rc = PGM_BTH_NAME_NESTED_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3231	#endif
3232
3233	/* The shadow part of the nested callback mode depends on the host paging mode (AMD-V only). */
3234	switch (pVM->pgm.s.enmHostMode)
3235	{
3236	#if HC_ARCH_BITS == 32
3237	case SUPPAGINGMODE_32_BIT:
3238	case SUPPAGINGMODE_32_BIT_GLOBAL:
3239	for (unsigned i = PGM_TYPE_REAL; i <= PGM_TYPE_PAE; i++)
3240	{
3241	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, i)];
3242	rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3243	}
3244	# ifdef VBOX_WITH_64_BITS_GUESTS
3245	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_AMD64)];
3246	rc = PGM_SHW_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3247	# endif
3248	break;
3249
3250	case SUPPAGINGMODE_PAE:
3251	case SUPPAGINGMODE_PAE_NX:
3252	case SUPPAGINGMODE_PAE_GLOBAL:
3253	case SUPPAGINGMODE_PAE_GLOBAL_NX:
3254	for (unsigned i = PGM_TYPE_REAL; i <= PGM_TYPE_PAE; i++)
3255	{
3256	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, i)];
3257	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3258	}
3259	# ifdef VBOX_WITH_64_BITS_GUESTS
3260	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_AMD64)];
3261	rc = PGM_SHW_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3262	# endif
3263	break;
3264	#endif /* HC_ARCH_BITS == 32 */
3265
3266	#if HC_ARCH_BITS == 64 \|\| defined(RT_OS_DARWIN)
3267	case SUPPAGINGMODE_AMD64:
3268	case SUPPAGINGMODE_AMD64_GLOBAL:
3269	case SUPPAGINGMODE_AMD64_NX:
3270	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
3271	# ifdef VBOX_WITH_64_BITS_GUESTS
3272	for (unsigned i = PGM_TYPE_REAL; i <= PGM_TYPE_AMD64; i++)
3273	# else
3274	for (unsigned i = PGM_TYPE_REAL; i <= PGM_TYPE_PAE; i++)
3275	# endif
3276	{
3277	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, i)];
3278	rc = PGM_SHW_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3279	}
3280	break;
3281	#endif /* HC_ARCH_BITS == 64 \|\| RT_OS_DARWIN */
3282
3283	default:
3284	AssertFailed();
3285	break;
3286	}
3287
3288	/* Extended paging (EPT) / Intel VT-x */
3289	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_REAL)];
3290	pModeData->uShwType = PGM_TYPE_EPT;
3291	pModeData->uGstType = PGM_TYPE_REAL;
3292	rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3293	rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3294	rc = PGM_BTH_NAME_EPT_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3295
3296	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_PROT)];
3297	pModeData->uShwType = PGM_TYPE_EPT;
3298	pModeData->uGstType = PGM_TYPE_PROT;
3299	rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3300	rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3301	rc = PGM_BTH_NAME_EPT_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3302
3303	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_32BIT)];
3304	pModeData->uShwType = PGM_TYPE_EPT;
3305	pModeData->uGstType = PGM_TYPE_32BIT;
3306	rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3307	rc = PGM_GST_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3308	rc = PGM_BTH_NAME_EPT_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3309
3310	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_PAE)];
3311	pModeData->uShwType = PGM_TYPE_EPT;
3312	pModeData->uGstType = PGM_TYPE_PAE;
3313	rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3314	rc = PGM_GST_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3315	rc = PGM_BTH_NAME_EPT_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3316
3317	#ifdef VBOX_WITH_64_BITS_GUESTS
3318	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_AMD64)];
3319	pModeData->uShwType = PGM_TYPE_EPT;
3320	pModeData->uGstType = PGM_TYPE_AMD64;
3321	rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3322	rc = PGM_GST_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3323	rc = PGM_BTH_NAME_EPT_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3324	#endif
3325	return VINF_SUCCESS;
3326	}
3327
3328
3329	/**
3330	* Switch to different (or relocated in the relocate case) mode data.
3331	*
3332	* @param pVM The VM handle.
3333	* @param enmShw The the shadow paging mode.
3334	* @param enmGst The the guest paging mode.
3335	*/
3336	static void pgmR3ModeDataSwitch(PVM pVM, PGMMODE enmShw, PGMMODE enmGst)
3337	{
3338	PPGMMODEDATA pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndexByMode(enmShw, enmGst)];
3339
3340	Assert(pModeData->uGstType == pgmModeToType(enmGst));
3341	Assert(pModeData->uShwType == pgmModeToType(enmShw));
3342
3343	/* shadow */
3344	pVM->pgm.s.pfnR3ShwRelocate = pModeData->pfnR3ShwRelocate;
3345	pVM->pgm.s.pfnR3ShwExit = pModeData->pfnR3ShwExit;
3346	pVM->pgm.s.pfnR3ShwGetPage = pModeData->pfnR3ShwGetPage;
3347	Assert(pVM->pgm.s.pfnR3ShwGetPage);
3348	pVM->pgm.s.pfnR3ShwModifyPage = pModeData->pfnR3ShwModifyPage;
3349
3350	pVM->pgm.s.pfnRCShwGetPage = pModeData->pfnRCShwGetPage;
3351	pVM->pgm.s.pfnRCShwModifyPage = pModeData->pfnRCShwModifyPage;
3352
3353	pVM->pgm.s.pfnR0ShwGetPage = pModeData->pfnR0ShwGetPage;
3354	pVM->pgm.s.pfnR0ShwModifyPage = pModeData->pfnR0ShwModifyPage;
3355
3356
3357	/* guest */
3358	pVM->pgm.s.pfnR3GstRelocate = pModeData->pfnR3GstRelocate;
3359	pVM->pgm.s.pfnR3GstExit = pModeData->pfnR3GstExit;
3360	pVM->pgm.s.pfnR3GstGetPage = pModeData->pfnR3GstGetPage;
3361	Assert(pVM->pgm.s.pfnR3GstGetPage);
3362	pVM->pgm.s.pfnR3GstModifyPage = pModeData->pfnR3GstModifyPage;
3363	pVM->pgm.s.pfnR3GstGetPDE = pModeData->pfnR3GstGetPDE;
3364	pVM->pgm.s.pfnRCGstGetPage = pModeData->pfnRCGstGetPage;
3365	pVM->pgm.s.pfnRCGstModifyPage = pModeData->pfnRCGstModifyPage;
3366	pVM->pgm.s.pfnRCGstGetPDE = pModeData->pfnRCGstGetPDE;
3367	pVM->pgm.s.pfnR0GstGetPage = pModeData->pfnR0GstGetPage;
3368	pVM->pgm.s.pfnR0GstModifyPage = pModeData->pfnR0GstModifyPage;
3369	pVM->pgm.s.pfnR0GstGetPDE = pModeData->pfnR0GstGetPDE;
3370
3371	/* both */
3372	pVM->pgm.s.pfnR3BthRelocate = pModeData->pfnR3BthRelocate;
3373	pVM->pgm.s.pfnR3BthInvalidatePage = pModeData->pfnR3BthInvalidatePage;
3374	pVM->pgm.s.pfnR3BthSyncCR3 = pModeData->pfnR3BthSyncCR3;
3375	Assert(pVM->pgm.s.pfnR3BthSyncCR3);
3376	pVM->pgm.s.pfnR3BthSyncPage = pModeData->pfnR3BthSyncPage;
3377	pVM->pgm.s.pfnR3BthPrefetchPage = pModeData->pfnR3BthPrefetchPage;
3378	pVM->pgm.s.pfnR3BthVerifyAccessSyncPage = pModeData->pfnR3BthVerifyAccessSyncPage;
3379	#ifdef VBOX_STRICT
3380	pVM->pgm.s.pfnR3BthAssertCR3 = pModeData->pfnR3BthAssertCR3;
3381	#endif
3382	pVM->pgm.s.pfnR3BthMapCR3 = pModeData->pfnR3BthMapCR3;
3383	pVM->pgm.s.pfnR3BthUnmapCR3 = pModeData->pfnR3BthUnmapCR3;
3384
3385	pVM->pgm.s.pfnRCBthTrap0eHandler = pModeData->pfnRCBthTrap0eHandler;
3386	pVM->pgm.s.pfnRCBthInvalidatePage = pModeData->pfnRCBthInvalidatePage;
3387	pVM->pgm.s.pfnRCBthSyncCR3 = pModeData->pfnRCBthSyncCR3;
3388	pVM->pgm.s.pfnRCBthSyncPage = pModeData->pfnRCBthSyncPage;
3389	pVM->pgm.s.pfnRCBthPrefetchPage = pModeData->pfnRCBthPrefetchPage;
3390	pVM->pgm.s.pfnRCBthVerifyAccessSyncPage = pModeData->pfnRCBthVerifyAccessSyncPage;
3391	#ifdef VBOX_STRICT
3392	pVM->pgm.s.pfnRCBthAssertCR3 = pModeData->pfnRCBthAssertCR3;
3393	#endif
3394	pVM->pgm.s.pfnRCBthMapCR3 = pModeData->pfnRCBthMapCR3;
3395	pVM->pgm.s.pfnRCBthUnmapCR3 = pModeData->pfnRCBthUnmapCR3;
3396
3397	pVM->pgm.s.pfnR0BthTrap0eHandler = pModeData->pfnR0BthTrap0eHandler;
3398	pVM->pgm.s.pfnR0BthInvalidatePage = pModeData->pfnR0BthInvalidatePage;
3399	pVM->pgm.s.pfnR0BthSyncCR3 = pModeData->pfnR0BthSyncCR3;
3400	pVM->pgm.s.pfnR0BthSyncPage = pModeData->pfnR0BthSyncPage;
3401	pVM->pgm.s.pfnR0BthPrefetchPage = pModeData->pfnR0BthPrefetchPage;
3402	pVM->pgm.s.pfnR0BthVerifyAccessSyncPage = pModeData->pfnR0BthVerifyAccessSyncPage;
3403	#ifdef VBOX_STRICT
3404	pVM->pgm.s.pfnR0BthAssertCR3 = pModeData->pfnR0BthAssertCR3;
3405	#endif
3406	pVM->pgm.s.pfnR0BthMapCR3 = pModeData->pfnR0BthMapCR3;
3407	pVM->pgm.s.pfnR0BthUnmapCR3 = pModeData->pfnR0BthUnmapCR3;
3408	}
3409
3410
3411	/**
3412	* Calculates the shadow paging mode.
3413	*
3414	* @returns The shadow paging mode.
3415	* @param pVM VM handle.
3416	* @param enmGuestMode The guest mode.
3417	* @param enmHostMode The host mode.
3418	* @param enmShadowMode The current shadow mode.
3419	* @param penmSwitcher Where to store the switcher to use.
3420	* VMMSWITCHER_INVALID means no change.
3421	*/
3422	static PGMMODE pgmR3CalcShadowMode(PVM pVM, PGMMODE enmGuestMode, SUPPAGINGMODE enmHostMode, PGMMODE enmShadowMode, VMMSWITCHER *penmSwitcher)
3423	{
3424	VMMSWITCHER enmSwitcher = VMMSWITCHER_INVALID;
3425	switch (enmGuestMode)
3426	{
3427	/*
3428	* When switching to real or protected mode we don't change
3429	* anything since it's likely that we'll switch back pretty soon.
3430	*
3431	* During pgmR3InitPaging we'll end up here with PGMMODE_INVALID
3432	* and is supposed to determine which shadow paging and switcher to
3433	* use during init.
3434	*/
3435	case PGMMODE_REAL:
3436	case PGMMODE_PROTECTED:
3437	if ( enmShadowMode != PGMMODE_INVALID
3438	&& !HWACCMIsEnabled(pVM) /* always switch in hwaccm mode! */)
3439	break; /* (no change) */
3440
3441	switch (enmHostMode)
3442	{
3443	case SUPPAGINGMODE_32_BIT:
3444	case SUPPAGINGMODE_32_BIT_GLOBAL:
3445	enmShadowMode = PGMMODE_32_BIT;
3446	enmSwitcher = VMMSWITCHER_32_TO_32;
3447	break;
3448
3449	case SUPPAGINGMODE_PAE:
3450	case SUPPAGINGMODE_PAE_NX:
3451	case SUPPAGINGMODE_PAE_GLOBAL:
3452	case SUPPAGINGMODE_PAE_GLOBAL_NX:
3453	enmShadowMode = PGMMODE_PAE;
3454	enmSwitcher = VMMSWITCHER_PAE_TO_PAE;
3455	#ifdef DEBUG_bird
3456	if (RTEnvExist("VBOX_32BIT"))
3457	{
3458	enmShadowMode = PGMMODE_32_BIT;
3459	enmSwitcher = VMMSWITCHER_PAE_TO_32;
3460	}
3461	#endif
3462	break;
3463
3464	case SUPPAGINGMODE_AMD64:
3465	case SUPPAGINGMODE_AMD64_GLOBAL:
3466	case SUPPAGINGMODE_AMD64_NX:
3467	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
3468	enmShadowMode = PGMMODE_PAE;
3469	enmSwitcher = VMMSWITCHER_AMD64_TO_PAE;
3470	#ifdef DEBUG_bird
3471	if (RTEnvExist("VBOX_32BIT"))
3472	{
3473	enmShadowMode = PGMMODE_32_BIT;
3474	enmSwitcher = VMMSWITCHER_AMD64_TO_32;
3475	}
3476	#endif
3477	break;
3478
3479	default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
3480	}
3481	break;
3482
3483	case PGMMODE_32_BIT:
3484	switch (enmHostMode)
3485	{
3486	case SUPPAGINGMODE_32_BIT:
3487	case SUPPAGINGMODE_32_BIT_GLOBAL:
3488	enmShadowMode = PGMMODE_32_BIT;
3489	enmSwitcher = VMMSWITCHER_32_TO_32;
3490	break;
3491
3492	case SUPPAGINGMODE_PAE:
3493	case SUPPAGINGMODE_PAE_NX:
3494	case SUPPAGINGMODE_PAE_GLOBAL:
3495	case SUPPAGINGMODE_PAE_GLOBAL_NX:
3496	enmShadowMode = PGMMODE_PAE;
3497	enmSwitcher = VMMSWITCHER_PAE_TO_PAE;
3498	#ifdef DEBUG_bird
3499	if (RTEnvExist("VBOX_32BIT"))
3500	{
3501	enmShadowMode = PGMMODE_32_BIT;
3502	enmSwitcher = VMMSWITCHER_PAE_TO_32;
3503	}
3504	#endif
3505	break;
3506
3507	case SUPPAGINGMODE_AMD64:
3508	case SUPPAGINGMODE_AMD64_GLOBAL:
3509	case SUPPAGINGMODE_AMD64_NX:
3510	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
3511	enmShadowMode = PGMMODE_PAE;
3512	enmSwitcher = VMMSWITCHER_AMD64_TO_PAE;
3513	#ifdef DEBUG_bird
3514	if (RTEnvExist("VBOX_32BIT"))
3515	{
3516	enmShadowMode = PGMMODE_32_BIT;
3517	enmSwitcher = VMMSWITCHER_AMD64_TO_32;
3518	}
3519	#endif
3520	break;
3521
3522	default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
3523	}
3524	break;
3525
3526	case PGMMODE_PAE:
3527	case PGMMODE_PAE_NX: /** @todo This might require more switchers and guest+both modes. */
3528	switch (enmHostMode)
3529	{
3530	case SUPPAGINGMODE_32_BIT:
3531	case SUPPAGINGMODE_32_BIT_GLOBAL:
3532	enmShadowMode = PGMMODE_PAE;
3533	enmSwitcher = VMMSWITCHER_32_TO_PAE;
3534	break;
3535
3536	case SUPPAGINGMODE_PAE:
3537	case SUPPAGINGMODE_PAE_NX:
3538	case SUPPAGINGMODE_PAE_GLOBAL:
3539	case SUPPAGINGMODE_PAE_GLOBAL_NX:
3540	enmShadowMode = PGMMODE_PAE;
3541	enmSwitcher = VMMSWITCHER_PAE_TO_PAE;
3542	break;
3543
3544	case SUPPAGINGMODE_AMD64:
3545	case SUPPAGINGMODE_AMD64_GLOBAL:
3546	case SUPPAGINGMODE_AMD64_NX:
3547	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
3548	enmShadowMode = PGMMODE_PAE;
3549	enmSwitcher = VMMSWITCHER_AMD64_TO_PAE;
3550	break;
3551
3552	default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
3553	}
3554	break;
3555
3556	case PGMMODE_AMD64:
3557	case PGMMODE_AMD64_NX:
3558	switch (enmHostMode)
3559	{
3560	case SUPPAGINGMODE_32_BIT:
3561	case SUPPAGINGMODE_32_BIT_GLOBAL:
3562	enmShadowMode = PGMMODE_AMD64;
3563	enmSwitcher = VMMSWITCHER_32_TO_AMD64;
3564	break;
3565
3566	case SUPPAGINGMODE_PAE:
3567	case SUPPAGINGMODE_PAE_NX:
3568	case SUPPAGINGMODE_PAE_GLOBAL:
3569	case SUPPAGINGMODE_PAE_GLOBAL_NX:
3570	enmShadowMode = PGMMODE_AMD64;
3571	enmSwitcher = VMMSWITCHER_PAE_TO_AMD64;
3572	break;
3573
3574	case SUPPAGINGMODE_AMD64:
3575	case SUPPAGINGMODE_AMD64_GLOBAL:
3576	case SUPPAGINGMODE_AMD64_NX:
3577	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
3578	enmShadowMode = PGMMODE_AMD64;
3579	enmSwitcher = VMMSWITCHER_AMD64_TO_AMD64;
3580	break;
3581
3582	default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
3583	}
3584	break;
3585
3586
3587	default:
3588	AssertReleaseMsgFailed(("enmGuestMode=%d\n", enmGuestMode));
3589	return PGMMODE_INVALID;
3590	}
3591	/* Override the shadow mode is nested paging is active. */
3592	if (HWACCMIsNestedPagingActive(pVM))
3593	enmShadowMode = HWACCMGetShwPagingMode(pVM);
3594
3595	*penmSwitcher = enmSwitcher;
3596	return enmShadowMode;
3597	}
3598
3599
3600	/**
3601	* Performs the actual mode change.
3602	* This is called by PGMChangeMode and pgmR3InitPaging().
3603	*
3604	* @returns VBox status code. May suspend or power off the VM on error, but this
3605	* will trigger using FFs and not status codes.
3606	*
3607	* @param pVM VM handle.
3608	* @param enmGuestMode The new guest mode. This is assumed to be different from
3609	* the current mode.
3610	*/
3611	VMMR3DECL(int) PGMR3ChangeMode(PVM pVM, PGMMODE enmGuestMode)
3612	{
3613	Log(("PGMR3ChangeMode: Guest mode: %s -> %s\n", PGMGetModeName(pVM->pgm.s.enmGuestMode), PGMGetModeName(enmGuestMode)));
3614	STAM_REL_COUNTER_INC(&pVM->pgm.s.cGuestModeChanges);
3615
3616	/*
3617	* Calc the shadow mode and switcher.
3618	*/
3619	VMMSWITCHER enmSwitcher;
3620	PGMMODE enmShadowMode = pgmR3CalcShadowMode(pVM, enmGuestMode, pVM->pgm.s.enmHostMode, pVM->pgm.s.enmShadowMode, &enmSwitcher);
3621	if (enmSwitcher != VMMSWITCHER_INVALID)
3622	{
3623	/*
3624	* Select new switcher.
3625	*/
3626	int rc = VMMR3SelectSwitcher(pVM, enmSwitcher);
3627	if (RT_FAILURE(rc))
3628	{
3629	AssertReleaseMsgFailed(("VMMR3SelectSwitcher(%d) -> %Rrc\n", enmSwitcher, rc));
3630	return rc;
3631	}
3632	}
3633
3634	/*
3635	* Exit old mode(s).
3636	*/
3637	/* shadow */
3638	if (enmShadowMode != pVM->pgm.s.enmShadowMode)
3639	{
3640	LogFlow(("PGMR3ChangeMode: Shadow mode: %s -> %s\n", PGMGetModeName(pVM->pgm.s.enmShadowMode), PGMGetModeName(enmShadowMode)));
3641	if (PGM_SHW_PFN(Exit, pVM))
3642	{
3643	int rc = PGM_SHW_PFN(Exit, pVM)(pVM);
3644	if (RT_FAILURE(rc))
3645	{
3646	AssertMsgFailed(("Exit failed for shadow mode %d: %Rrc\n", pVM->pgm.s.enmShadowMode, rc));
3647	return rc;
3648	}
3649	}
3650
3651	}
3652	else
3653	LogFlow(("PGMR3ChangeMode: Shadow mode remains: %s\n", PGMGetModeName(pVM->pgm.s.enmShadowMode)));
3654
3655	/* guest */
3656	if (PGM_GST_PFN(Exit, pVM))
3657	{
3658	int rc = PGM_GST_PFN(Exit, pVM)(pVM);
3659	if (RT_FAILURE(rc))
3660	{
3661	AssertMsgFailed(("Exit failed for guest mode %d: %Rrc\n", pVM->pgm.s.enmGuestMode, rc));
3662	return rc;
3663	}
3664	}
3665
3666	/*
3667	* Load new paging mode data.
3668	*/
3669	pgmR3ModeDataSwitch(pVM, enmShadowMode, enmGuestMode);
3670
3671	/*
3672	* Enter new shadow mode (if changed).
3673	*/
3674	if (enmShadowMode != pVM->pgm.s.enmShadowMode)
3675	{
3676	int rc;
3677	pVM->pgm.s.enmShadowMode = enmShadowMode;
3678	switch (enmShadowMode)
3679	{
3680	case PGMMODE_32_BIT:
3681	rc = PGM_SHW_NAME_32BIT(Enter)(pVM);
3682	break;
3683	case PGMMODE_PAE:
3684	case PGMMODE_PAE_NX:
3685	rc = PGM_SHW_NAME_PAE(Enter)(pVM);
3686	break;
3687	case PGMMODE_AMD64:
3688	case PGMMODE_AMD64_NX:
3689	rc = PGM_SHW_NAME_AMD64(Enter)(pVM);
3690	break;
3691	case PGMMODE_NESTED:
3692	rc = PGM_SHW_NAME_NESTED(Enter)(pVM);
3693	break;
3694	case PGMMODE_EPT:
3695	rc = PGM_SHW_NAME_EPT(Enter)(pVM);
3696	break;
3697	case PGMMODE_REAL:
3698	case PGMMODE_PROTECTED:
3699	default:
3700	AssertReleaseMsgFailed(("enmShadowMode=%d\n", enmShadowMode));
3701	return VERR_INTERNAL_ERROR;
3702	}
3703	if (RT_FAILURE(rc))
3704	{
3705	AssertReleaseMsgFailed(("Entering enmShadowMode=%d failed: %Rrc\n", enmShadowMode, rc));
3706	pVM->pgm.s.enmShadowMode = PGMMODE_INVALID;
3707	return rc;
3708	}
3709	}
3710
3711	/*
3712	* Always flag the necessary updates
3713	*/
3714	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
3715
3716	/*
3717	* Enter the new guest and shadow+guest modes.
3718	*/
3719	int rc = -1;
3720	int rc2 = -1;
3721	RTGCPHYS GCPhysCR3 = NIL_RTGCPHYS;
3722	pVM->pgm.s.enmGuestMode = enmGuestMode;
3723	switch (enmGuestMode)
3724	{
3725	case PGMMODE_REAL:
3726	rc = PGM_GST_NAME_REAL(Enter)(pVM, NIL_RTGCPHYS);
3727	switch (pVM->pgm.s.enmShadowMode)
3728	{
3729	case PGMMODE_32_BIT:
3730	rc2 = PGM_BTH_NAME_32BIT_REAL(Enter)(pVM, NIL_RTGCPHYS);
3731	break;
3732	case PGMMODE_PAE:
3733	case PGMMODE_PAE_NX:
3734	rc2 = PGM_BTH_NAME_PAE_REAL(Enter)(pVM, NIL_RTGCPHYS);
3735	break;
3736	case PGMMODE_NESTED:
3737	rc2 = PGM_BTH_NAME_NESTED_REAL(Enter)(pVM, NIL_RTGCPHYS);
3738	break;
3739	case PGMMODE_EPT:
3740	rc2 = PGM_BTH_NAME_EPT_REAL(Enter)(pVM, NIL_RTGCPHYS);
3741	break;
3742	case PGMMODE_AMD64:
3743	case PGMMODE_AMD64_NX:
3744	AssertMsgFailed(("Should use PAE shadow mode!\n"));
3745	default: AssertFailed(); break;
3746	}
3747	break;
3748
3749	case PGMMODE_PROTECTED:
3750	rc = PGM_GST_NAME_PROT(Enter)(pVM, NIL_RTGCPHYS);
3751	switch (pVM->pgm.s.enmShadowMode)
3752	{
3753	case PGMMODE_32_BIT:
3754	rc2 = PGM_BTH_NAME_32BIT_PROT(Enter)(pVM, NIL_RTGCPHYS);
3755	break;
3756	case PGMMODE_PAE:
3757	case PGMMODE_PAE_NX:
3758	rc2 = PGM_BTH_NAME_PAE_PROT(Enter)(pVM, NIL_RTGCPHYS);
3759	break;
3760	case PGMMODE_NESTED:
3761	rc2 = PGM_BTH_NAME_NESTED_PROT(Enter)(pVM, NIL_RTGCPHYS);
3762	break;
3763	case PGMMODE_EPT:
3764	rc2 = PGM_BTH_NAME_EPT_PROT(Enter)(pVM, NIL_RTGCPHYS);
3765	break;
3766	case PGMMODE_AMD64:
3767	case PGMMODE_AMD64_NX:
3768	AssertMsgFailed(("Should use PAE shadow mode!\n"));
3769	default: AssertFailed(); break;
3770	}
3771	break;
3772
3773	case PGMMODE_32_BIT:
3774	GCPhysCR3 = CPUMGetGuestCR3(pVM) & X86_CR3_PAGE_MASK;
3775	rc = PGM_GST_NAME_32BIT(Enter)(pVM, GCPhysCR3);
3776	switch (pVM->pgm.s.enmShadowMode)
3777	{
3778	case PGMMODE_32_BIT:
3779	rc2 = PGM_BTH_NAME_32BIT_32BIT(Enter)(pVM, GCPhysCR3);
3780	break;
3781	case PGMMODE_PAE:
3782	case PGMMODE_PAE_NX:
3783	rc2 = PGM_BTH_NAME_PAE_32BIT(Enter)(pVM, GCPhysCR3);
3784	break;
3785	case PGMMODE_NESTED:
3786	rc2 = PGM_BTH_NAME_NESTED_32BIT(Enter)(pVM, GCPhysCR3);
3787	break;
3788	case PGMMODE_EPT:
3789	rc2 = PGM_BTH_NAME_EPT_32BIT(Enter)(pVM, GCPhysCR3);
3790	break;
3791	case PGMMODE_AMD64:
3792	case PGMMODE_AMD64_NX:
3793	AssertMsgFailed(("Should use PAE shadow mode!\n"));
3794	default: AssertFailed(); break;
3795	}
3796	break;
3797
3798	case PGMMODE_PAE_NX:
3799	case PGMMODE_PAE:
3800	{
3801	uint32_t u32Dummy, u32Features;
3802
3803	CPUMGetGuestCpuId(pVM, 1, &u32Dummy, &u32Dummy, &u32Dummy, &u32Features);
3804	if (!(u32Features & X86_CPUID_FEATURE_EDX_PAE))
3805	return VMSetRuntimeError(pVM, VMSETRTERR_FLAGS_FATAL, "PAEmode",
3806	N_("The guest is trying to switch to the PAE mode which is currently disabled by default in VirtualBox. PAE support can be enabled using the VM settings (General/Advanced)"));
3807
3808	GCPhysCR3 = CPUMGetGuestCR3(pVM) & X86_CR3_PAE_PAGE_MASK;
3809	rc = PGM_GST_NAME_PAE(Enter)(pVM, GCPhysCR3);
3810	switch (pVM->pgm.s.enmShadowMode)
3811	{
3812	case PGMMODE_PAE:
3813	case PGMMODE_PAE_NX:
3814	rc2 = PGM_BTH_NAME_PAE_PAE(Enter)(pVM, GCPhysCR3);
3815	break;
3816	case PGMMODE_NESTED:
3817	rc2 = PGM_BTH_NAME_NESTED_PAE(Enter)(pVM, GCPhysCR3);
3818	break;
3819	case PGMMODE_EPT:
3820	rc2 = PGM_BTH_NAME_EPT_PAE(Enter)(pVM, GCPhysCR3);
3821	break;
3822	case PGMMODE_32_BIT:
3823	case PGMMODE_AMD64:
3824	case PGMMODE_AMD64_NX:
3825	AssertMsgFailed(("Should use PAE shadow mode!\n"));
3826	default: AssertFailed(); break;
3827	}
3828	break;
3829	}
3830
3831	#ifdef VBOX_WITH_64_BITS_GUESTS
3832	case PGMMODE_AMD64_NX:
3833	case PGMMODE_AMD64:
3834	GCPhysCR3 = CPUMGetGuestCR3(pVM) & UINT64_C(0xfffffffffffff000); /** @todo define this mask! */
3835	rc = PGM_GST_NAME_AMD64(Enter)(pVM, GCPhysCR3);
3836	switch (pVM->pgm.s.enmShadowMode)
3837	{
3838	case PGMMODE_AMD64:
3839	case PGMMODE_AMD64_NX:
3840	rc2 = PGM_BTH_NAME_AMD64_AMD64(Enter)(pVM, GCPhysCR3);
3841	break;
3842	case PGMMODE_NESTED:
3843	rc2 = PGM_BTH_NAME_NESTED_AMD64(Enter)(pVM, GCPhysCR3);
3844	break;
3845	case PGMMODE_EPT:
3846	rc2 = PGM_BTH_NAME_EPT_AMD64(Enter)(pVM, GCPhysCR3);
3847	break;
3848	case PGMMODE_32_BIT:
3849	case PGMMODE_PAE:
3850	case PGMMODE_PAE_NX:
3851	AssertMsgFailed(("Should use AMD64 shadow mode!\n"));
3852	default: AssertFailed(); break;
3853	}
3854	break;
3855	#endif
3856
3857	default:
3858	AssertReleaseMsgFailed(("enmGuestMode=%d\n", enmGuestMode));
3859	rc = VERR_NOT_IMPLEMENTED;
3860	break;
3861	}
3862
3863	/* status codes. */
3864	AssertRC(rc);
3865	AssertRC(rc2);
3866	if (RT_SUCCESS(rc))
3867	{
3868	rc = rc2;
3869	if (RT_SUCCESS(rc)) /* no informational status codes. */
3870	rc = VINF_SUCCESS;
3871	}
3872
3873	/* Notify HWACCM as well. */
3874	HWACCMR3PagingModeChanged(pVM, pVM->pgm.s.enmShadowMode, pVM->pgm.s.enmGuestMode);
3875	return rc;
3876	}
3877
3878
3879	/**
3880	* Dumps a PAE shadow page table.
3881	*
3882	* @returns VBox status code (VINF_SUCCESS).
3883	* @param pVM The VM handle.
3884	* @param pPT Pointer to the page table.
3885	* @param u64Address The virtual address of the page table starts.
3886	* @param fLongMode Set if this a long mode table; clear if it's a legacy mode table.
3887	* @param cMaxDepth The maxium depth.
3888	* @param pHlp Pointer to the output functions.
3889	*/
3890	static int pgmR3DumpHierarchyHCPaePT(PVM pVM, PX86PTPAE pPT, uint64_t u64Address, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
3891	{
3892	for (unsigned i = 0; i < RT_ELEMENTS(pPT->a); i++)
3893	{
3894	X86PTEPAE Pte = pPT->a[i];
3895	if (Pte.n.u1Present)
3896	{
3897	pHlp->pfnPrintf(pHlp,
3898	fLongMode /P R S A D G WT CD AT NX 4M a p ? /
3899	? "%016llx 3 \| P %c %c %c %c %c %s %s %s %s 4K %c%c%c %016llx\n"
3900	: "%08llx 2 \| P %c %c %c %c %c %s %s %s %s 4K %c%c%c %016llx\n",
3901	u64Address + ((uint64_t)i << X86_PT_PAE_SHIFT),
3902	Pte.n.u1Write ? 'W' : 'R',
3903	Pte.n.u1User ? 'U' : 'S',
3904	Pte.n.u1Accessed ? 'A' : '-',
3905	Pte.n.u1Dirty ? 'D' : '-',
3906	Pte.n.u1Global ? 'G' : '-',
3907	Pte.n.u1WriteThru ? "WT" : "--",
3908	Pte.n.u1CacheDisable? "CD" : "--",
3909	Pte.n.u1PAT ? "AT" : "--",
3910	Pte.n.u1NoExecute ? "NX" : "--",
3911	Pte.u & PGM_PTFLAGS_TRACK_DIRTY ? 'd' : '-',
3912	Pte.u & RT_BIT(10) ? '1' : '0',
3913	Pte.u & PGM_PTFLAGS_CSAM_VALIDATED? 'v' : '-',
3914	Pte.u & X86_PTE_PAE_PG_MASK);
3915	}
3916	}
3917	return VINF_SUCCESS;
3918	}
3919
3920
3921	/**
3922	* Dumps a PAE shadow page directory table.
3923	*
3924	* @returns VBox status code (VINF_SUCCESS).
3925	* @param pVM The VM handle.
3926	* @param HCPhys The physical address of the page directory table.
3927	* @param u64Address The virtual address of the page table starts.
3928	* @param cr4 The CR4, PSE is currently used.
3929	* @param fLongMode Set if this a long mode table; clear if it's a legacy mode table.
3930	* @param cMaxDepth The maxium depth.
3931	* @param pHlp Pointer to the output functions.
3932	*/
3933	static int pgmR3DumpHierarchyHCPaePD(PVM pVM, RTHCPHYS HCPhys, uint64_t u64Address, uint32_t cr4, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
3934	{
3935	PX86PDPAE pPD = (PX86PDPAE)MMPagePhys2Page(pVM, HCPhys);
3936	if (!pPD)
3937	{
3938	pHlp->pfnPrintf(pHlp, "%0*llx error! Page directory at HCPhys=%RHp was not found in the page pool!\n",
3939	fLongMode ? 16 : 8, u64Address, HCPhys);
3940	return VERR_INVALID_PARAMETER;
3941	}
3942	const bool fBigPagesSupported = fLongMode \|\| !!(cr4 & X86_CR4_PSE);
3943
3944	int rc = VINF_SUCCESS;
3945	for (unsigned i = 0; i < RT_ELEMENTS(pPD->a); i++)
3946	{
3947	X86PDEPAE Pde = pPD->a[i];
3948	if (Pde.n.u1Present)
3949	{
3950	if (fBigPagesSupported && Pde.b.u1Size)
3951	pHlp->pfnPrintf(pHlp,
3952	fLongMode /P R S A D G WT CD AT NX 4M a p ? /
3953	? "%016llx 2 \| P %c %c %c %c %c %s %s %s %s 4M %c%c%c %016llx\n"
3954	: "%08llx 1 \| P %c %c %c %c %c %s %s %s %s 4M %c%c%c %016llx\n",
3955	u64Address + ((uint64_t)i << X86_PD_PAE_SHIFT),
3956	Pde.b.u1Write ? 'W' : 'R',
3957	Pde.b.u1User ? 'U' : 'S',
3958	Pde.b.u1Accessed ? 'A' : '-',
3959	Pde.b.u1Dirty ? 'D' : '-',
3960	Pde.b.u1Global ? 'G' : '-',
3961	Pde.b.u1WriteThru ? "WT" : "--",
3962	Pde.b.u1CacheDisable? "CD" : "--",
3963	Pde.b.u1PAT ? "AT" : "--",
3964	Pde.b.u1NoExecute ? "NX" : "--",
3965	Pde.u & RT_BIT_64(9) ? '1' : '0',
3966	Pde.u & PGM_PDFLAGS_MAPPING ? 'm' : '-',
3967	Pde.u & PGM_PDFLAGS_TRACK_DIRTY ? 'd' : '-',
3968	Pde.u & X86_PDE_PAE_PG_MASK);
3969	else
3970	{
3971	pHlp->pfnPrintf(pHlp,
3972	fLongMode /P R S A D G WT CD AT NX 4M a p ? /
3973	? "%016llx 2 \| P %c %c %c %c %c %s %s .. %s 4K %c%c%c %016llx\n"
3974	: "%08llx 1 \| P %c %c %c %c %c %s %s .. %s 4K %c%c%c %016llx\n",
3975	u64Address + ((uint64_t)i << X86_PD_PAE_SHIFT),
3976	Pde.n.u1Write ? 'W' : 'R',
3977	Pde.n.u1User ? 'U' : 'S',
3978	Pde.n.u1Accessed ? 'A' : '-',
3979	Pde.n.u1Reserved0 ? '?' : '.', /* ignored */
3980	Pde.n.u1Reserved1 ? '?' : '.', /* ignored */
3981	Pde.n.u1WriteThru ? "WT" : "--",
3982	Pde.n.u1CacheDisable? "CD" : "--",
3983	Pde.n.u1NoExecute ? "NX" : "--",
3984	Pde.u & RT_BIT_64(9) ? '1' : '0',
3985	Pde.u & PGM_PDFLAGS_MAPPING ? 'm' : '-',
3986	Pde.u & PGM_PDFLAGS_TRACK_DIRTY ? 'd' : '-',
3987	Pde.u & X86_PDE_PAE_PG_MASK);
3988	if (cMaxDepth >= 1)
3989	{
3990	/** @todo what about using the page pool for mapping PTs? */
3991	uint64_t u64AddressPT = u64Address + ((uint64_t)i << X86_PD_PAE_SHIFT);
3992	RTHCPHYS HCPhysPT = Pde.u & X86_PDE_PAE_PG_MASK;
3993	PX86PTPAE pPT = NULL;
3994	if (!(Pde.u & PGM_PDFLAGS_MAPPING))
3995	pPT = (PX86PTPAE)MMPagePhys2Page(pVM, HCPhysPT);
3996	else
3997	{
3998	for (PPGMMAPPING pMap = pVM->pgm.s.pMappingsR3; pMap; pMap = pMap->pNextR3)
3999	{
4000	uint64_t off = u64AddressPT - pMap->GCPtr;
4001	if (off < pMap->cb)
4002	{
4003	const int iPDE = (uint32_t)(off >> X86_PD_SHIFT);
4004	const int iSub = (int)((off >> X86_PD_PAE_SHIFT) & 1); /* MSC is a pain sometimes */
4005	if ((iSub ? pMap->aPTs[iPDE].HCPhysPaePT1 : pMap->aPTs[iPDE].HCPhysPaePT0) != HCPhysPT)
4006	pHlp->pfnPrintf(pHlp, "%0*llx error! Mapping error! PT %d has HCPhysPT=%RHp not %RHp is in the PD.\n",
4007	fLongMode ? 16 : 8, u64AddressPT, iPDE,
4008	iSub ? pMap->aPTs[iPDE].HCPhysPaePT1 : pMap->aPTs[iPDE].HCPhysPaePT0, HCPhysPT);
4009	pPT = &pMap->aPTs[iPDE].paPaePTsR3[iSub];
4010	}
4011	}
4012	}
4013	int rc2 = VERR_INVALID_PARAMETER;
4014	if (pPT)
4015	rc2 = pgmR3DumpHierarchyHCPaePT(pVM, pPT, u64AddressPT, fLongMode, cMaxDepth - 1, pHlp);
4016	else
4017	pHlp->pfnPrintf(pHlp, "%0*llx error! Page table at HCPhys=%RHp was not found in the page pool!\n",
4018	fLongMode ? 16 : 8, u64AddressPT, HCPhysPT);
4019	if (rc2 < rc && RT_SUCCESS(rc))
4020	rc = rc2;
4021	}
4022	}
4023	}
4024	}
4025	return rc;
4026	}
4027
4028
4029	/**
4030	* Dumps a PAE shadow page directory pointer table.
4031	*
4032	* @returns VBox status code (VINF_SUCCESS).
4033	* @param pVM The VM handle.
4034	* @param HCPhys The physical address of the page directory pointer table.
4035	* @param u64Address The virtual address of the page table starts.
4036	* @param cr4 The CR4, PSE is currently used.
4037	* @param fLongMode Set if this a long mode table; clear if it's a legacy mode table.
4038	* @param cMaxDepth The maxium depth.
4039	* @param pHlp Pointer to the output functions.
4040	*/
4041	static int pgmR3DumpHierarchyHCPaePDPT(PVM pVM, RTHCPHYS HCPhys, uint64_t u64Address, uint32_t cr4, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
4042	{
4043	PX86PDPT pPDPT = (PX86PDPT)MMPagePhys2Page(pVM, HCPhys);
4044	if (!pPDPT)
4045	{
4046	pHlp->pfnPrintf(pHlp, "%0*llx error! Page directory pointer table at HCPhys=%RHp was not found in the page pool!\n",
4047	fLongMode ? 16 : 8, u64Address, HCPhys);
4048	return VERR_INVALID_PARAMETER;
4049	}
4050
4051	int rc = VINF_SUCCESS;
4052	const unsigned c = fLongMode ? RT_ELEMENTS(pPDPT->a) : X86_PG_PAE_PDPE_ENTRIES;
4053	for (unsigned i = 0; i < c; i++)
4054	{
4055	X86PDPE Pdpe = pPDPT->a[i];
4056	if (Pdpe.n.u1Present)
4057	{
4058	if (fLongMode)
4059	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a p ? /
4060	"%016llx 1 \| P %c %c %c %c %c %s %s %s %s .. %c%c%c %016llx\n",
4061	u64Address + ((uint64_t)i << X86_PDPT_SHIFT),
4062	Pdpe.lm.u1Write ? 'W' : 'R',
4063	Pdpe.lm.u1User ? 'U' : 'S',
4064	Pdpe.lm.u1Accessed ? 'A' : '-',
4065	Pdpe.lm.u3Reserved & 1? '?' : '.', /* ignored */
4066	Pdpe.lm.u3Reserved & 4? '!' : '.', /* mbz */
4067	Pdpe.lm.u1WriteThru ? "WT" : "--",
4068	Pdpe.lm.u1CacheDisable? "CD" : "--",
4069	Pdpe.lm.u3Reserved & 2? "!" : "..",/* mbz */
4070	Pdpe.lm.u1NoExecute ? "NX" : "--",
4071	Pdpe.u & RT_BIT(9) ? '1' : '0',
4072	Pdpe.u & PGM_PLXFLAGS_PERMANENT ? 'p' : '-',
4073	Pdpe.u & RT_BIT(11) ? '1' : '0',
4074	Pdpe.u & X86_PDPE_PG_MASK);
4075	else
4076	pHlp->pfnPrintf(pHlp, /P G WT CD AT NX 4M a p ? /
4077	"%08x 0 \| P %c %s %s %s %s .. %c%c%c %016llx\n",
4078	i << X86_PDPT_SHIFT,
4079	Pdpe.n.u4Reserved & 1? '!' : '.', /* mbz */
4080	Pdpe.n.u4Reserved & 4? '!' : '.', /* mbz */
4081	Pdpe.n.u1WriteThru ? "WT" : "--",
4082	Pdpe.n.u1CacheDisable? "CD" : "--",
4083	Pdpe.n.u4Reserved & 2? "!" : "..",/* mbz */
4084	Pdpe.u & RT_BIT(9) ? '1' : '0',
4085	Pdpe.u & PGM_PLXFLAGS_PERMANENT ? 'p' : '-',
4086	Pdpe.u & RT_BIT(11) ? '1' : '0',
4087	Pdpe.u & X86_PDPE_PG_MASK);
4088	if (cMaxDepth >= 1)
4089	{
4090	int rc2 = pgmR3DumpHierarchyHCPaePD(pVM, Pdpe.u & X86_PDPE_PG_MASK, u64Address + ((uint64_t)i << X86_PDPT_SHIFT),
4091	cr4, fLongMode, cMaxDepth - 1, pHlp);
4092	if (rc2 < rc && RT_SUCCESS(rc))
4093	rc = rc2;
4094	}
4095	}
4096	}
4097	return rc;
4098	}
4099
4100
4101	/**
4102	* Dumps a 32-bit shadow page table.
4103	*
4104	* @returns VBox status code (VINF_SUCCESS).
4105	* @param pVM The VM handle.
4106	* @param HCPhys The physical address of the table.
4107	* @param cr4 The CR4, PSE is currently used.
4108	* @param cMaxDepth The maxium depth.
4109	* @param pHlp Pointer to the output functions.
4110	*/
4111	static int pgmR3DumpHierarchyHcPaePML4(PVM pVM, RTHCPHYS HCPhys, uint32_t cr4, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
4112	{
4113	PX86PML4 pPML4 = (PX86PML4)MMPagePhys2Page(pVM, HCPhys);
4114	if (!pPML4)
4115	{
4116	pHlp->pfnPrintf(pHlp, "Page map level 4 at HCPhys=%RHp was not found in the page pool!\n", HCPhys);
4117	return VERR_INVALID_PARAMETER;
4118	}
4119
4120	int rc = VINF_SUCCESS;
4121	for (unsigned i = 0; i < RT_ELEMENTS(pPML4->a); i++)
4122	{
4123	X86PML4E Pml4e = pPML4->a[i];
4124	if (Pml4e.n.u1Present)
4125	{
4126	uint64_t u64Address = ((uint64_t)i << X86_PML4_SHIFT) \| (((uint64_t)i >> (X86_PML4_SHIFT - X86_PDPT_SHIFT - 1)) * 0xffff000000000000ULL);
4127	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a p ? /
4128	"%016llx 0 \| P %c %c %c %c %c %s %s %s %s .. %c%c%c %016llx\n",
4129	u64Address,
4130	Pml4e.n.u1Write ? 'W' : 'R',
4131	Pml4e.n.u1User ? 'U' : 'S',
4132	Pml4e.n.u1Accessed ? 'A' : '-',
4133	Pml4e.n.u3Reserved & 1? '?' : '.', /* ignored */
4134	Pml4e.n.u3Reserved & 4? '!' : '.', /* mbz */
4135	Pml4e.n.u1WriteThru ? "WT" : "--",
4136	Pml4e.n.u1CacheDisable? "CD" : "--",
4137	Pml4e.n.u3Reserved & 2? "!" : "..",/* mbz */
4138	Pml4e.n.u1NoExecute ? "NX" : "--",
4139	Pml4e.u & RT_BIT(9) ? '1' : '0',
4140	Pml4e.u & PGM_PLXFLAGS_PERMANENT ? 'p' : '-',
4141	Pml4e.u & RT_BIT(11) ? '1' : '0',
4142	Pml4e.u & X86_PML4E_PG_MASK);
4143
4144	if (cMaxDepth >= 1)
4145	{
4146	int rc2 = pgmR3DumpHierarchyHCPaePDPT(pVM, Pml4e.u & X86_PML4E_PG_MASK, u64Address, cr4, true, cMaxDepth - 1, pHlp);
4147	if (rc2 < rc && RT_SUCCESS(rc))
4148	rc = rc2;
4149	}
4150	}
4151	}
4152	return rc;
4153	}
4154
4155
4156	/**
4157	* Dumps a 32-bit shadow page table.
4158	*
4159	* @returns VBox status code (VINF_SUCCESS).
4160	* @param pVM The VM handle.
4161	* @param pPT Pointer to the page table.
4162	* @param u32Address The virtual address this table starts at.
4163	* @param pHlp Pointer to the output functions.
4164	*/
4165	int pgmR3DumpHierarchyHC32BitPT(PVM pVM, PX86PT pPT, uint32_t u32Address, PCDBGFINFOHLP pHlp)
4166	{
4167	for (unsigned i = 0; i < RT_ELEMENTS(pPT->a); i++)
4168	{
4169	X86PTE Pte = pPT->a[i];
4170	if (Pte.n.u1Present)
4171	{
4172	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a m d /
4173	"%08x 1 \| P %c %c %c %c %c %s %s %s .. 4K %c%c%c %08x\n",
4174	u32Address + (i << X86_PT_SHIFT),
4175	Pte.n.u1Write ? 'W' : 'R',
4176	Pte.n.u1User ? 'U' : 'S',
4177	Pte.n.u1Accessed ? 'A' : '-',
4178	Pte.n.u1Dirty ? 'D' : '-',
4179	Pte.n.u1Global ? 'G' : '-',
4180	Pte.n.u1WriteThru ? "WT" : "--",
4181	Pte.n.u1CacheDisable? "CD" : "--",
4182	Pte.n.u1PAT ? "AT" : "--",
4183	Pte.u & PGM_PTFLAGS_TRACK_DIRTY ? 'd' : '-',
4184	Pte.u & RT_BIT(10) ? '1' : '0',
4185	Pte.u & PGM_PTFLAGS_CSAM_VALIDATED ? 'v' : '-',
4186	Pte.u & X86_PDE_PG_MASK);
4187	}
4188	}
4189	return VINF_SUCCESS;
4190	}
4191
4192
4193	/**
4194	* Dumps a 32-bit shadow page directory and page tables.
4195	*
4196	* @returns VBox status code (VINF_SUCCESS).
4197	* @param pVM The VM handle.
4198	* @param cr3 The root of the hierarchy.
4199	* @param cr4 The CR4, PSE is currently used.
4200	* @param cMaxDepth How deep into the hierarchy the dumper should go.
4201	* @param pHlp Pointer to the output functions.
4202	*/
4203	int pgmR3DumpHierarchyHC32BitPD(PVM pVM, uint32_t cr3, uint32_t cr4, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
4204	{
4205	PX86PD pPD = (PX86PD)MMPagePhys2Page(pVM, cr3 & X86_CR3_PAGE_MASK);
4206	if (!pPD)
4207	{
4208	pHlp->pfnPrintf(pHlp, "Page directory at %#x was not found in the page pool!\n", cr3 & X86_CR3_PAGE_MASK);
4209	return VERR_INVALID_PARAMETER;
4210	}
4211
4212	int rc = VINF_SUCCESS;
4213	for (unsigned i = 0; i < RT_ELEMENTS(pPD->a); i++)
4214	{
4215	X86PDE Pde = pPD->a[i];
4216	if (Pde.n.u1Present)
4217	{
4218	const uint32_t u32Address = i << X86_PD_SHIFT;
4219	if ((cr4 & X86_CR4_PSE) && Pde.b.u1Size)
4220	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a m d /
4221	"%08x 0 \| P %c %c %c %c %c %s %s %s .. 4M %c%c%c %08x\n",
4222	u32Address,
4223	Pde.b.u1Write ? 'W' : 'R',
4224	Pde.b.u1User ? 'U' : 'S',
4225	Pde.b.u1Accessed ? 'A' : '-',
4226	Pde.b.u1Dirty ? 'D' : '-',
4227	Pde.b.u1Global ? 'G' : '-',
4228	Pde.b.u1WriteThru ? "WT" : "--",
4229	Pde.b.u1CacheDisable? "CD" : "--",
4230	Pde.b.u1PAT ? "AT" : "--",
4231	Pde.u & RT_BIT_64(9) ? '1' : '0',
4232	Pde.u & PGM_PDFLAGS_MAPPING ? 'm' : '-',
4233	Pde.u & PGM_PDFLAGS_TRACK_DIRTY ? 'd' : '-',
4234	Pde.u & X86_PDE4M_PG_MASK);
4235	else
4236	{
4237	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a m d /
4238	"%08x 0 \| P %c %c %c %c %c %s %s .. .. 4K %c%c%c %08x\n",
4239	u32Address,
4240	Pde.n.u1Write ? 'W' : 'R',
4241	Pde.n.u1User ? 'U' : 'S',
4242	Pde.n.u1Accessed ? 'A' : '-',
4243	Pde.n.u1Reserved0 ? '?' : '.', /* ignored */
4244	Pde.n.u1Reserved1 ? '?' : '.', /* ignored */
4245	Pde.n.u1WriteThru ? "WT" : "--",
4246	Pde.n.u1CacheDisable? "CD" : "--",
4247	Pde.u & RT_BIT_64(9) ? '1' : '0',
4248	Pde.u & PGM_PDFLAGS_MAPPING ? 'm' : '-',
4249	Pde.u & PGM_PDFLAGS_TRACK_DIRTY ? 'd' : '-',
4250	Pde.u & X86_PDE_PG_MASK);
4251	if (cMaxDepth >= 1)
4252	{
4253	/** @todo what about using the page pool for mapping PTs? */
4254	RTHCPHYS HCPhys = Pde.u & X86_PDE_PG_MASK;
4255	PX86PT pPT = NULL;
4256	if (!(Pde.u & PGM_PDFLAGS_MAPPING))
4257	pPT = (PX86PT)MMPagePhys2Page(pVM, HCPhys);
4258	else
4259	{
4260	for (PPGMMAPPING pMap = pVM->pgm.s.pMappingsR3; pMap; pMap = pMap->pNextR3)
4261	if (u32Address - pMap->GCPtr < pMap->cb)
4262	{
4263	int iPDE = (u32Address - pMap->GCPtr) >> X86_PD_SHIFT;
4264	if (pMap->aPTs[iPDE].HCPhysPT != HCPhys)
4265	pHlp->pfnPrintf(pHlp, "%08x error! Mapping error! PT %d has HCPhysPT=%RHp not %RHp is in the PD.\n",
4266	u32Address, iPDE, pMap->aPTs[iPDE].HCPhysPT, HCPhys);
4267	pPT = pMap->aPTs[iPDE].pPTR3;
4268	}
4269	}
4270	int rc2 = VERR_INVALID_PARAMETER;
4271	if (pPT)
4272	rc2 = pgmR3DumpHierarchyHC32BitPT(pVM, pPT, u32Address, pHlp);
4273	else
4274	pHlp->pfnPrintf(pHlp, "%08x error! Page table at %#x was not found in the page pool!\n", u32Address, HCPhys);
4275	if (rc2 < rc && RT_SUCCESS(rc))
4276	rc = rc2;
4277	}
4278	}
4279	}
4280	}
4281
4282	return rc;
4283	}
4284
4285
4286	/**
4287	* Dumps a 32-bit shadow page table.
4288	*
4289	* @returns VBox status code (VINF_SUCCESS).
4290	* @param pVM The VM handle.
4291	* @param pPT Pointer to the page table.
4292	* @param u32Address The virtual address this table starts at.
4293	* @param PhysSearch Address to search for.
4294	*/
4295	int pgmR3DumpHierarchyGC32BitPT(PVM pVM, PX86PT pPT, uint32_t u32Address, RTGCPHYS PhysSearch)
4296	{
4297	for (unsigned i = 0; i < RT_ELEMENTS(pPT->a); i++)
4298	{
4299	X86PTE Pte = pPT->a[i];
4300	if (Pte.n.u1Present)
4301	{
4302	Log(( /P R S A D G WT CD AT NX 4M a m d /
4303	"%08x 1 \| P %c %c %c %c %c %s %s %s .. 4K %c%c%c %08x\n",
4304	u32Address + (i << X86_PT_SHIFT),
4305	Pte.n.u1Write ? 'W' : 'R',
4306	Pte.n.u1User ? 'U' : 'S',
4307	Pte.n.u1Accessed ? 'A' : '-',
4308	Pte.n.u1Dirty ? 'D' : '-',
4309	Pte.n.u1Global ? 'G' : '-',
4310	Pte.n.u1WriteThru ? "WT" : "--",
4311	Pte.n.u1CacheDisable? "CD" : "--",
4312	Pte.n.u1PAT ? "AT" : "--",
4313	Pte.u & PGM_PTFLAGS_TRACK_DIRTY ? 'd' : '-',
4314	Pte.u & RT_BIT(10) ? '1' : '0',
4315	Pte.u & PGM_PTFLAGS_CSAM_VALIDATED ? 'v' : '-',
4316	Pte.u & X86_PDE_PG_MASK));
4317
4318	if ((Pte.u & X86_PDE_PG_MASK) == PhysSearch)
4319	{
4320	uint64_t fPageShw = 0;
4321	RTHCPHYS pPhysHC = 0;
4322
4323	PGMShwGetPage(pVM, (RTGCPTR)(u32Address + (i << X86_PT_SHIFT)), &fPageShw, &pPhysHC);
4324	Log(("Found %RGp at %RGv -> flags=%llx\n", PhysSearch, (RTGCPTR)(u32Address + (i << X86_PT_SHIFT)), fPageShw));
4325	}
4326	}
4327	}
4328	return VINF_SUCCESS;
4329	}
4330
4331
4332	/**
4333	* Dumps a 32-bit guest page directory and page tables.
4334	*
4335	* @returns VBox status code (VINF_SUCCESS).
4336	* @param pVM The VM handle.
4337	* @param cr3 The root of the hierarchy.
4338	* @param cr4 The CR4, PSE is currently used.
4339	* @param PhysSearch Address to search for.
4340	*/
4341	VMMR3DECL(int) PGMR3DumpHierarchyGC(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCPHYS PhysSearch)
4342	{
4343	bool fLongMode = false;
4344	const unsigned cch = fLongMode ? 16 : 8; NOREF(cch);
4345	PX86PD pPD = 0;
4346
4347	int rc = PGM_GCPHYS_2_PTR(pVM, cr3 & X86_CR3_PAGE_MASK, &pPD);
4348	if (RT_FAILURE(rc) \|\| !pPD)
4349	{
4350	Log(("Page directory at %#x was not found in the page pool!\n", cr3 & X86_CR3_PAGE_MASK));
4351	return VERR_INVALID_PARAMETER;
4352	}
4353
4354	Log(("cr3=%08x cr4=%08x%s\n"
4355	"%-*s P - Present\n"
4356	"%-*s \| R/W - Read (0) / Write (1)\n"
4357	"%-*s \| \| U/S - User (1) / Supervisor (0)\n"
4358	"%-*s \| \| \| A - Accessed\n"
4359	"%-*s \| \| \| \| D - Dirty\n"
4360	"%-*s \| \| \| \| \| G - Global\n"
4361	"%-*s \| \| \| \| \| \| WT - Write thru\n"
4362	"%-*s \| \| \| \| \| \| \| CD - Cache disable\n"
4363	"%-*s \| \| \| \| \| \| \| \| AT - Attribute table (PAT)\n"
4364	"%-*s \| \| \| \| \| \| \| \| \| NX - No execute (K8)\n"
4365	"%-*s \| \| \| \| \| \| \| \| \| \| 4K/4M/2M - Page size.\n"
4366	"%-*s \| \| \| \| \| \| \| \| \| \| \| AVL - a=allocated; m=mapping; d=track dirty;\n"
4367	"%-*s \| \| \| \| \| \| \| \| \| \| \| \| p=permanent; v=validated;\n"
4368	"%-*s Level \| \| \| \| \| \| \| \| \| \| \| \| Page\n"
4369	/* xxxx n **** P R S A D G WT CD AT NX 4M AVL xxxxxxxxxxxxx
4370	- W U - - - -- -- -- -- -- 010 */
4371	, cr3, cr4, fLongMode ? " Long Mode" : "",
4372	cch, "", cch, "", cch, "", cch, "", cch, "", cch, "", cch, "",
4373	cch, "", cch, "", cch, "", cch, "", cch, "", cch, "", cch, "Address"));
4374
4375	for (unsigned i = 0; i < RT_ELEMENTS(pPD->a); i++)
4376	{
4377	X86PDE Pde = pPD->a[i];
4378	if (Pde.n.u1Present)
4379	{
4380	const uint32_t u32Address = i << X86_PD_SHIFT;
4381
4382	if ((cr4 & X86_CR4_PSE) && Pde.b.u1Size)
4383	Log(( /P R S A D G WT CD AT NX 4M a m d /
4384	"%08x 0 \| P %c %c %c %c %c %s %s %s .. 4M %c%c%c %08x\n",
4385	u32Address,
4386	Pde.b.u1Write ? 'W' : 'R',
4387	Pde.b.u1User ? 'U' : 'S',
4388	Pde.b.u1Accessed ? 'A' : '-',
4389	Pde.b.u1Dirty ? 'D' : '-',
4390	Pde.b.u1Global ? 'G' : '-',
4391	Pde.b.u1WriteThru ? "WT" : "--",
4392	Pde.b.u1CacheDisable? "CD" : "--",
4393	Pde.b.u1PAT ? "AT" : "--",
4394	Pde.u & RT_BIT(9) ? '1' : '0',
4395	Pde.u & RT_BIT(10) ? '1' : '0',
4396	Pde.u & RT_BIT(11) ? '1' : '0',
4397	pgmGstGet4MBPhysPage(&pVM->pgm.s, Pde)));
4398	/** @todo PhysSearch */
4399	else
4400	{
4401	Log(( /P R S A D G WT CD AT NX 4M a m d /
4402	"%08x 0 \| P %c %c %c %c %c %s %s .. .. 4K %c%c%c %08x\n",
4403	u32Address,
4404	Pde.n.u1Write ? 'W' : 'R',
4405	Pde.n.u1User ? 'U' : 'S',
4406	Pde.n.u1Accessed ? 'A' : '-',
4407	Pde.n.u1Reserved0 ? '?' : '.', /* ignored */
4408	Pde.n.u1Reserved1 ? '?' : '.', /* ignored */
4409	Pde.n.u1WriteThru ? "WT" : "--",
4410	Pde.n.u1CacheDisable? "CD" : "--",
4411	Pde.u & RT_BIT(9) ? '1' : '0',
4412	Pde.u & RT_BIT(10) ? '1' : '0',
4413	Pde.u & RT_BIT(11) ? '1' : '0',
4414	Pde.u & X86_PDE_PG_MASK));
4415	////if (cMaxDepth >= 1)
4416	{
4417	/** @todo what about using the page pool for mapping PTs? */
4418	RTGCPHYS GCPhys = Pde.u & X86_PDE_PG_MASK;
4419	PX86PT pPT = NULL;
4420
4421	rc = PGM_GCPHYS_2_PTR(pVM, GCPhys, &pPT);
4422
4423	int rc2 = VERR_INVALID_PARAMETER;
4424	if (pPT)
4425	rc2 = pgmR3DumpHierarchyGC32BitPT(pVM, pPT, u32Address, PhysSearch);
4426	else
4427	Log(("%08x error! Page table at %#x was not found in the page pool!\n", u32Address, GCPhys));
4428	if (rc2 < rc && RT_SUCCESS(rc))
4429	rc = rc2;
4430	}
4431	}
4432	}
4433	}
4434
4435	return rc;
4436	}
4437
4438
4439	/**
4440	* Dumps a page table hierarchy use only physical addresses and cr4/lm flags.
4441	*
4442	* @returns VBox status code (VINF_SUCCESS).
4443	* @param pVM The VM handle.
4444	* @param cr3 The root of the hierarchy.
4445	* @param cr4 The cr4, only PAE and PSE is currently used.
4446	* @param fLongMode Set if long mode, false if not long mode.
4447	* @param cMaxDepth Number of levels to dump.
4448	* @param pHlp Pointer to the output functions.
4449	*/
4450	VMMR3DECL(int) PGMR3DumpHierarchyHC(PVM pVM, uint64_t cr3, uint64_t cr4, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
4451	{
4452	if (!pHlp)
4453	pHlp = DBGFR3InfoLogHlp();
4454	if (!cMaxDepth)
4455	return VINF_SUCCESS;
4456	const unsigned cch = fLongMode ? 16 : 8;
4457	pHlp->pfnPrintf(pHlp,
4458	"cr3=%08x cr4=%08x%s\n"
4459	"%-*s P - Present\n"
4460	"%-*s \| R/W - Read (0) / Write (1)\n"
4461	"%-*s \| \| U/S - User (1) / Supervisor (0)\n"
4462	"%-*s \| \| \| A - Accessed\n"
4463	"%-*s \| \| \| \| D - Dirty\n"
4464	"%-*s \| \| \| \| \| G - Global\n"
4465	"%-*s \| \| \| \| \| \| WT - Write thru\n"
4466	"%-*s \| \| \| \| \| \| \| CD - Cache disable\n"
4467	"%-*s \| \| \| \| \| \| \| \| AT - Attribute table (PAT)\n"
4468	"%-*s \| \| \| \| \| \| \| \| \| NX - No execute (K8)\n"
4469	"%-*s \| \| \| \| \| \| \| \| \| \| 4K/4M/2M - Page size.\n"
4470	"%-*s \| \| \| \| \| \| \| \| \| \| \| AVL - a=allocated; m=mapping; d=track dirty;\n"
4471	"%-*s \| \| \| \| \| \| \| \| \| \| \| \| p=permanent; v=validated;\n"
4472	"%-*s Level \| \| \| \| \| \| \| \| \| \| \| \| Page\n"
4473	/* xxxx n **** P R S A D G WT CD AT NX 4M AVL xxxxxxxxxxxxx
4474	- W U - - - -- -- -- -- -- 010 */
4475	, cr3, cr4, fLongMode ? " Long Mode" : "",
4476	cch, "", cch, "", cch, "", cch, "", cch, "", cch, "", cch, "",
4477	cch, "", cch, "", cch, "", cch, "", cch, "", cch, "", cch, "Address");
4478	if (cr4 & X86_CR4_PAE)
4479	{
4480	if (fLongMode)
4481	return pgmR3DumpHierarchyHcPaePML4(pVM, cr3 & X86_CR3_PAGE_MASK, cr4, cMaxDepth, pHlp);
4482	return pgmR3DumpHierarchyHCPaePDPT(pVM, cr3 & X86_CR3_PAE_PAGE_MASK, 0, cr4, false, cMaxDepth, pHlp);
4483	}
4484	return pgmR3DumpHierarchyHC32BitPD(pVM, cr3 & X86_CR3_PAGE_MASK, cr4, cMaxDepth, pHlp);
4485	}
4486
4487	#ifdef VBOX_WITH_DEBUGGER
4488
4489	/**
4490	* The '.pgmram' command.
4491	*
4492	* @returns VBox status.
4493	* @param pCmd Pointer to the command descriptor (as registered).
4494	* @param pCmdHlp Pointer to command helper functions.
4495	* @param pVM Pointer to the current VM (if any).
4496	* @param paArgs Pointer to (readonly) array of arguments.
4497	* @param cArgs Number of arguments in the array.
4498	*/
4499	static DECLCALLBACK(int) pgmR3CmdRam(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4500	{
4501	/*
4502	* Validate input.
4503	*/
4504	if (!pVM)
4505	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4506	if (!pVM->pgm.s.pRamRangesRC)
4507	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Sorry, no Ram is registered.\n");
4508
4509	/*
4510	* Dump the ranges.
4511	*/
4512	int rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL, "From - To (incl) pvHC\n");
4513	PPGMRAMRANGE pRam;
4514	for (pRam = pVM->pgm.s.pRamRangesR3; pRam; pRam = pRam->pNextR3)
4515	{
4516	rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL,
4517	"%RGp - %RGp %p\n",
4518	pRam->GCPhys, pRam->GCPhysLast, pRam->pvR3);
4519	if (RT_FAILURE(rc))
4520	return rc;
4521	}
4522
4523	return VINF_SUCCESS;
4524	}
4525
4526
4527	/**
4528	* The '.pgmmap' command.
4529	*
4530	* @returns VBox status.
4531	* @param pCmd Pointer to the command descriptor (as registered).
4532	* @param pCmdHlp Pointer to command helper functions.
4533	* @param pVM Pointer to the current VM (if any).
4534	* @param paArgs Pointer to (readonly) array of arguments.
4535	* @param cArgs Number of arguments in the array.
4536	*/
4537	static DECLCALLBACK(int) pgmR3CmdMap(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4538	{
4539	/*
4540	* Validate input.
4541	*/
4542	if (!pVM)
4543	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4544	if (!pVM->pgm.s.pMappingsR3)
4545	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Sorry, no mappings are registered.\n");
4546
4547	/*
4548	* Print message about the fixedness of the mappings.
4549	*/
4550	int rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL, pVM->pgm.s.fMappingsFixed ? "The mappings are FIXED.\n" : "The mappings are FLOATING.\n");
4551	if (RT_FAILURE(rc))
4552	return rc;
4553
4554	/*
4555	* Dump the ranges.
4556	*/
4557	PPGMMAPPING pCur;
4558	for (pCur = pVM->pgm.s.pMappingsR3; pCur; pCur = pCur->pNextR3)
4559	{
4560	rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL,
4561	"%08x - %08x %s\n",
4562	pCur->GCPtr, pCur->GCPtrLast, pCur->pszDesc);
4563	if (RT_FAILURE(rc))
4564	return rc;
4565	}
4566
4567	return VINF_SUCCESS;
4568	}
4569
4570
4571	/**
4572	* The '.pgmerror' and '.pgmerroroff' commands.
4573	*
4574	* @returns VBox status.
4575	* @param pCmd Pointer to the command descriptor (as registered).
4576	* @param pCmdHlp Pointer to command helper functions.
4577	* @param pVM Pointer to the current VM (if any).
4578	* @param paArgs Pointer to (readonly) array of arguments.
4579	* @param cArgs Number of arguments in the array.
4580	*/
4581	static DECLCALLBACK(int) pgmR3CmdError(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4582	{
4583	/*
4584	* Validate input.
4585	*/
4586	if (!pVM)
4587	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4588	AssertReturn(cArgs == 0 \|\| (cArgs == 1 && paArgs[0].enmType == DBGCVAR_TYPE_STRING),
4589	pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: Hit bug in the parser.\n"));
4590
4591	if (!cArgs)
4592	{
4593	/*
4594	* Print the list of error injection locations with status.
4595	*/
4596	pCmdHlp->pfnPrintf(pCmdHlp, NULL, "PGM error inject locations:\n");
4597	pCmdHlp->pfnPrintf(pCmdHlp, NULL, " handy - %RTbool\n", pVM->pgm.s.fErrInjHandyPages);
4598	}
4599	else
4600	{
4601
4602	/*
4603	* String switch on where to inject the error.
4604	*/
4605	bool const fNewState = !strcmp(pCmd->pszCmd, "pgmerror");
4606	const char *pszWhere = paArgs[0].u.pszString;
4607	if (!strcmp(pszWhere, "handy"))
4608	ASMAtomicWriteBool(&pVM->pgm.s.fErrInjHandyPages, fNewState);
4609	else
4610	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: Invalid 'where' value: %s.\n", pszWhere);
4611	pCmdHlp->pfnPrintf(pCmdHlp, NULL, "done\n");
4612	}
4613	return VINF_SUCCESS;
4614	}
4615
4616
4617	/**
4618	* The '.pgmsync' command.
4619	*
4620	* @returns VBox status.
4621	* @param pCmd Pointer to the command descriptor (as registered).
4622	* @param pCmdHlp Pointer to command helper functions.
4623	* @param pVM Pointer to the current VM (if any).
4624	* @param paArgs Pointer to (readonly) array of arguments.
4625	* @param cArgs Number of arguments in the array.
4626	*/
4627	static DECLCALLBACK(int) pgmR3CmdSync(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4628	{
4629	/*
4630	* Validate input.
4631	*/
4632	if (!pVM)
4633	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4634
4635	/*
4636	* Force page directory sync.
4637	*/
4638	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
4639
4640	int rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Forcing page directory sync.\n");
4641	if (RT_FAILURE(rc))
4642	return rc;
4643
4644	return VINF_SUCCESS;
4645	}
4646
4647
4648	#ifdef VBOX_STRICT
4649	/**
4650	* The '.pgmassertcr3' command.
4651	*
4652	* @returns VBox status.
4653	* @param pCmd Pointer to the command descriptor (as registered).
4654	* @param pCmdHlp Pointer to command helper functions.
4655	* @param pVM Pointer to the current VM (if any).
4656	* @param paArgs Pointer to (readonly) array of arguments.
4657	* @param cArgs Number of arguments in the array.
4658	*/
4659	static DECLCALLBACK(int) pgmR3CmdAssertCR3(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4660	{
4661	/*
4662	* Validate input.
4663	*/
4664	if (!pVM)
4665	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4666
4667	int rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Checking shadow CR3 page tables for consistency.\n");
4668	if (RT_FAILURE(rc))
4669	return rc;
4670
4671	PGMAssertCR3(pVM, CPUMGetGuestCR3(pVM), CPUMGetGuestCR4(pVM));
4672
4673	return VINF_SUCCESS;
4674	}
4675	#endif /* VBOX_STRICT */
4676
4677
4678	/**
4679	* The '.pgmsyncalways' command.
4680	*
4681	* @returns VBox status.
4682	* @param pCmd Pointer to the command descriptor (as registered).
4683	* @param pCmdHlp Pointer to command helper functions.
4684	* @param pVM Pointer to the current VM (if any).
4685	* @param paArgs Pointer to (readonly) array of arguments.
4686	* @param cArgs Number of arguments in the array.
4687	*/
4688	static DECLCALLBACK(int) pgmR3CmdSyncAlways(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4689	{
4690	/*
4691	* Validate input.
4692	*/
4693	if (!pVM)
4694	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4695
4696	/*
4697	* Force page directory sync.
4698	*/
4699	if (pVM->pgm.s.fSyncFlags & PGM_SYNC_ALWAYS)
4700	{
4701	ASMAtomicAndU32(&pVM->pgm.s.fSyncFlags, ~PGM_SYNC_ALWAYS);
4702	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Disabled permanent forced page directory syncing.\n");
4703	}
4704	else
4705	{
4706	ASMAtomicOrU32(&pVM->pgm.s.fSyncFlags, PGM_SYNC_ALWAYS);
4707	VM_FF_SET(pVM, VM_FF_PGM_SYNC_CR3);
4708	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Enabled permanent forced page directory syncing.\n");
4709	}
4710	}
4711
4712	#endif /* VBOX_WITH_DEBUGGER */
4713
4714	/**
4715	* pvUser argument of the pgmR3CheckIntegrity*Node callbacks.
4716	*/
4717	typedef struct PGMCHECKINTARGS
4718	{
4719	bool fLeftToRight; /*< true: left-to-right; false: right-to-left. /
4720	PPGMPHYSHANDLER pPrevPhys;
4721	PPGMVIRTHANDLER pPrevVirt;
4722	PPGMPHYS2VIRTHANDLER pPrevPhys2Virt;
4723	PVM pVM;
4724	} PGMCHECKINTARGS, *PPGMCHECKINTARGS;
4725
4726	/**
4727	* Validate a node in the physical handler tree.
4728	*
4729	* @returns 0 on if ok, other wise 1.
4730	* @param pNode The handler node.
4731	* @param pvUser pVM.
4732	*/
4733	static DECLCALLBACK(int) pgmR3CheckIntegrityPhysHandlerNode(PAVLROGCPHYSNODECORE pNode, void *pvUser)
4734	{
4735	PPGMCHECKINTARGS pArgs = (PPGMCHECKINTARGS)pvUser;
4736	PPGMPHYSHANDLER pCur = (PPGMPHYSHANDLER)pNode;
4737	AssertReleaseReturn(!((uintptr_t)pCur & 7), 1);
4738	AssertReleaseMsg(pCur->Core.Key <= pCur->Core.KeyLast,("pCur=%p %RGp-%RGp %s\n", pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
4739	AssertReleaseMsg( !pArgs->pPrevPhys
4740	\|\| (pArgs->fLeftToRight ? pArgs->pPrevPhys->Core.KeyLast < pCur->Core.Key : pArgs->pPrevPhys->Core.KeyLast > pCur->Core.Key),
4741	("pPrevPhys=%p %RGp-%RGp %s\n"
4742	" pCur=%p %RGp-%RGp %s\n",
4743	pArgs->pPrevPhys, pArgs->pPrevPhys->Core.Key, pArgs->pPrevPhys->Core.KeyLast, pArgs->pPrevPhys->pszDesc,
4744	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
4745	pArgs->pPrevPhys = pCur;
4746	return 0;
4747	}
4748
4749
4750	/**
4751	* Validate a node in the virtual handler tree.
4752	*
4753	* @returns 0 on if ok, other wise 1.
4754	* @param pNode The handler node.
4755	* @param pvUser pVM.
4756	*/
4757	static DECLCALLBACK(int) pgmR3CheckIntegrityVirtHandlerNode(PAVLROGCPTRNODECORE pNode, void *pvUser)
4758	{
4759	PPGMCHECKINTARGS pArgs = (PPGMCHECKINTARGS)pvUser;
4760	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)pNode;
4761	AssertReleaseReturn(!((uintptr_t)pCur & 7), 1);
4762	AssertReleaseMsg(pCur->Core.Key <= pCur->Core.KeyLast,("pCur=%p %RGv-%RGv %s\n", pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
4763	AssertReleaseMsg( !pArgs->pPrevVirt
4764	\|\| (pArgs->fLeftToRight ? pArgs->pPrevVirt->Core.KeyLast < pCur->Core.Key : pArgs->pPrevVirt->Core.KeyLast > pCur->Core.Key),
4765	("pPrevVirt=%p %RGv-%RGv %s\n"
4766	" pCur=%p %RGv-%RGv %s\n",
4767	pArgs->pPrevVirt, pArgs->pPrevVirt->Core.Key, pArgs->pPrevVirt->Core.KeyLast, pArgs->pPrevVirt->pszDesc,
4768	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
4769	for (unsigned iPage = 0; iPage < pCur->cPages; iPage++)
4770	{
4771	AssertReleaseMsg(pCur->aPhysToVirt[iPage].offVirtHandler == -RT_OFFSETOF(PGMVIRTHANDLER, aPhysToVirt[iPage]),
4772	("pCur=%p %RGv-%RGv %s\n"
4773	"iPage=%d offVirtHandle=%#x expected %#x\n",
4774	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc,
4775	iPage, pCur->aPhysToVirt[iPage].offVirtHandler, -RT_OFFSETOF(PGMVIRTHANDLER, aPhysToVirt[iPage])));
4776	}
4777	pArgs->pPrevVirt = pCur;
4778	return 0;
4779	}
4780
4781
4782	/**
4783	* Validate a node in the virtual handler tree.
4784	*
4785	* @returns 0 on if ok, other wise 1.
4786	* @param pNode The handler node.
4787	* @param pvUser pVM.
4788	*/
4789	static DECLCALLBACK(int) pgmR3CheckIntegrityPhysToVirtHandlerNode(PAVLROGCPHYSNODECORE pNode, void *pvUser)
4790	{
4791	PPGMCHECKINTARGS pArgs = (PPGMCHECKINTARGS)pvUser;
4792	PPGMPHYS2VIRTHANDLER pCur = (PPGMPHYS2VIRTHANDLER)pNode;
4793	AssertReleaseMsgReturn(!((uintptr_t)pCur & 3), ("\n"), 1);
4794	AssertReleaseMsgReturn(!(pCur->offVirtHandler & 3), ("\n"), 1);
4795	AssertReleaseMsg(pCur->Core.Key <= pCur->Core.KeyLast,("pCur=%p %RGp-%RGp\n", pCur, pCur->Core.Key, pCur->Core.KeyLast));
4796	AssertReleaseMsg( !pArgs->pPrevPhys2Virt
4797	\|\| (pArgs->fLeftToRight ? pArgs->pPrevPhys2Virt->Core.KeyLast < pCur->Core.Key : pArgs->pPrevPhys2Virt->Core.KeyLast > pCur->Core.Key),
4798	("pPrevPhys2Virt=%p %RGp-%RGp\n"
4799	" pCur=%p %RGp-%RGp\n",
4800	pArgs->pPrevPhys2Virt, pArgs->pPrevPhys2Virt->Core.Key, pArgs->pPrevPhys2Virt->Core.KeyLast,
4801	pCur, pCur->Core.Key, pCur->Core.KeyLast));
4802	AssertReleaseMsg( !pArgs->pPrevPhys2Virt
4803	\|\| (pArgs->fLeftToRight ? pArgs->pPrevPhys2Virt->Core.KeyLast < pCur->Core.Key : pArgs->pPrevPhys2Virt->Core.KeyLast > pCur->Core.Key),
4804	("pPrevPhys2Virt=%p %RGp-%RGp\n"
4805	" pCur=%p %RGp-%RGp\n",
4806	pArgs->pPrevPhys2Virt, pArgs->pPrevPhys2Virt->Core.Key, pArgs->pPrevPhys2Virt->Core.KeyLast,
4807	pCur, pCur->Core.Key, pCur->Core.KeyLast));
4808	AssertReleaseMsg((pCur->offNextAlias & (PGMPHYS2VIRTHANDLER_IN_TREE \| PGMPHYS2VIRTHANDLER_IS_HEAD)) == (PGMPHYS2VIRTHANDLER_IN_TREE \| PGMPHYS2VIRTHANDLER_IS_HEAD),
4809	("pCur=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4810	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias));
4811	if (pCur->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK)
4812	{
4813	PPGMPHYS2VIRTHANDLER pCur2 = pCur;
4814	for (;;)
4815	{
4816	pCur2 = (PPGMPHYS2VIRTHANDLER)((intptr_t)pCur + (pCur->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK));
4817	AssertReleaseMsg(pCur2 != pCur,
4818	(" pCur=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4819	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias));
4820	AssertReleaseMsg((pCur2->offNextAlias & (PGMPHYS2VIRTHANDLER_IN_TREE \| PGMPHYS2VIRTHANDLER_IS_HEAD)) == PGMPHYS2VIRTHANDLER_IN_TREE,
4821	(" pCur=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
4822	"pCur2=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4823	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias,
4824	pCur2, pCur2->Core.Key, pCur2->Core.KeyLast, pCur2->offVirtHandler, pCur2->offNextAlias));
4825	AssertReleaseMsg((pCur2->Core.Key ^ pCur->Core.Key) < PAGE_SIZE,
4826	(" pCur=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
4827	"pCur2=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4828	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias,
4829	pCur2, pCur2->Core.Key, pCur2->Core.KeyLast, pCur2->offVirtHandler, pCur2->offNextAlias));
4830	AssertReleaseMsg((pCur2->Core.KeyLast ^ pCur->Core.KeyLast) < PAGE_SIZE,
4831	(" pCur=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
4832	"pCur2=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4833	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias,
4834	pCur2, pCur2->Core.Key, pCur2->Core.KeyLast, pCur2->offVirtHandler, pCur2->offNextAlias));
4835	if (!(pCur2->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK))
4836	break;
4837	}
4838	}
4839
4840	pArgs->pPrevPhys2Virt = pCur;
4841	return 0;
4842	}
4843
4844
4845	/**
4846	* Perform an integrity check on the PGM component.
4847	*
4848	* @returns VINF_SUCCESS if everything is fine.
4849	* @returns VBox error status after asserting on integrity breach.
4850	* @param pVM The VM handle.
4851	*/
4852	VMMR3DECL(int) PGMR3CheckIntegrity(PVM pVM)
4853	{
4854	AssertReleaseReturn(pVM->pgm.s.offVM, VERR_INTERNAL_ERROR);
4855
4856	/*
4857	* Check the trees.
4858	*/
4859	int cErrors = 0;
4860	const static PGMCHECKINTARGS s_LeftToRight = { true, NULL, NULL, NULL, pVM };
4861	const static PGMCHECKINTARGS s_RightToLeft = { false, NULL, NULL, NULL, pVM };
4862	PGMCHECKINTARGS Args = s_LeftToRight;
4863	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysHandlers, true, pgmR3CheckIntegrityPhysHandlerNode, &Args);
4864	Args = s_RightToLeft;
4865	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysHandlers, false, pgmR3CheckIntegrityPhysHandlerNode, &Args);
4866	Args = s_LeftToRight;
4867	cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesR3->VirtHandlers, true, pgmR3CheckIntegrityVirtHandlerNode, &Args);
4868	Args = s_RightToLeft;
4869	cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesR3->VirtHandlers, false, pgmR3CheckIntegrityVirtHandlerNode, &Args);
4870	Args = s_LeftToRight;
4871	cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesR3->HyperVirtHandlers, true, pgmR3CheckIntegrityVirtHandlerNode, &Args);
4872	Args = s_RightToLeft;
4873	cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesR3->HyperVirtHandlers, false, pgmR3CheckIntegrityVirtHandlerNode, &Args);
4874	Args = s_LeftToRight;
4875	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysToVirtHandlers, true, pgmR3CheckIntegrityPhysToVirtHandlerNode, &Args);
4876	Args = s_RightToLeft;
4877	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysToVirtHandlers, false, pgmR3CheckIntegrityPhysToVirtHandlerNode, &Args);
4878
4879	return !cErrors ? VINF_SUCCESS : VERR_INTERNAL_ERROR;
4880	}
4881
4882

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source: vbox/trunk/src/VBox/VMM/PGM.cpp@ 18891

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