PGM.cpp@ 21982

Last change on this file since 21982 was 21928, checked in by vboxsync, 15 years ago
PGM: Fixed restore bug where pgmR3LoadLocked left a 32-bit ~0U behind.
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1	/* $Id: PGM.cpp 21928 2009-08-02 17:20:20Z vboxsync $ */
2	/** @file
3	* PGM - Page Manager and Monitor. (Mixing stuff here, not good?)
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22
23	/** @page pg_pgm PGM - The Page Manager and Monitor
24	*
25	* @see grp_pgm,
26	* @ref pg_pgm_pool,
27	* @ref pg_pgm_phys.
28	*
29	*
30	* @section sec_pgm_modes Paging Modes
31	*
32	* There are three memory contexts: Host Context (HC), Guest Context (GC)
33	* and intermediate context. When talking about paging HC can also be refered to
34	* as "host paging", and GC refered to as "shadow paging".
35	*
36	* We define three basic paging modes: 32-bit, PAE and AMD64. The host paging mode
37	* is defined by the host operating system. The mode used in the shadow paging mode
38	* depends on the host paging mode and what the mode the guest is currently in. The
39	* following relation between the two is defined:
40	*
41	* @verbatim
42	Host > 32-bit \| PAE \| AMD64 \|
43	Guest \| \| \| \|
44	==v================================
45	32-bit 32-bit PAE PAE
46	-------\|--------\|--------\|--------\|
47	PAE PAE PAE PAE
48	-------\|--------\|--------\|--------\|
49	AMD64 AMD64 AMD64 AMD64
50	-------\|--------\|--------\|--------\| @endverbatim
51	*
52	* All configuration except those in the diagonal (upper left) are expected to
53	* require special effort from the switcher (i.e. a bit slower).
54	*
55	*
56	*
57	*
58	* @section sec_pgm_shw The Shadow Memory Context
59	*
60	*
61	* [..]
62	*
63	* Because of guest context mappings requires PDPT and PML4 entries to allow
64	* writing on AMD64, the two upper levels will have fixed flags whatever the
65	* guest is thinking of using there. So, when shadowing the PD level we will
66	* calculate the effective flags of PD and all the higher levels. In legacy
67	* PAE mode this only applies to the PWT and PCD bits (the rest are
68	* ignored/reserved/MBZ). We will ignore those bits for the present.
69	*
70	*
71	*
72	* @section sec_pgm_int The Intermediate Memory Context
73	*
74	* The world switch goes thru an intermediate memory context which purpose it is
75	* to provide different mappings of the switcher code. All guest mappings are also
76	* present in this context.
77	*
78	* The switcher code is mapped at the same location as on the host, at an
79	* identity mapped location (physical equals virtual address), and at the
80	* hypervisor location. The identity mapped location is for when the world
81	* switches that involves disabling paging.
82	*
83	* PGM maintain page tables for 32-bit, PAE and AMD64 paging modes. This
84	* simplifies switching guest CPU mode and consistency at the cost of more
85	* code to do the work. All memory use for those page tables is located below
86	* 4GB (this includes page tables for guest context mappings).
87	*
88	*
89	* @subsection subsec_pgm_int_gc Guest Context Mappings
90	*
91	* During assignment and relocation of a guest context mapping the intermediate
92	* memory context is used to verify the new location.
93	*
94	* Guest context mappings are currently restricted to below 4GB, for reasons
95	* of simplicity. This may change when we implement AMD64 support.
96	*
97	*
98	*
99	*
100	* @section sec_pgm_misc Misc
101	*
102	* @subsection subsec_pgm_misc_diff Differences Between Legacy PAE and Long Mode PAE
103	*
104	* The differences between legacy PAE and long mode PAE are:
105	* -# PDPE bits 1, 2, 5 and 6 are defined differently. In leagcy mode they are
106	* all marked down as must-be-zero, while in long mode 1, 2 and 5 have the
107	* usual meanings while 6 is ignored (AMD). This means that upon switching to
108	* legacy PAE mode we'll have to clear these bits and when going to long mode
109	* they must be set. This applies to both intermediate and shadow contexts,
110	* however we don't need to do it for the intermediate one since we're
111	* executing with CR0.WP at that time.
112	* -# CR3 allows a 32-byte aligned address in legacy mode, while in long mode
113	* a page aligned one is required.
114	*
115	*
116	* @section sec_pgm_handlers Access Handlers
117	*
118	* Placeholder.
119	*
120	*
121	* @subsection sec_pgm_handlers_virt Virtual Access Handlers
122	*
123	* Placeholder.
124	*
125	*
126	* @subsection sec_pgm_handlers_virt Virtual Access Handlers
127	*
128	* We currently implement three types of virtual access handlers: ALL, WRITE
129	* and HYPERVISOR (WRITE). See PGMVIRTHANDLERTYPE for some more details.
130	*
131	* The HYPERVISOR access handlers is kept in a separate tree since it doesn't apply
132	* to physical pages (PGMTREES::HyperVirtHandlers) and only needs to be consulted in
133	* a special \#PF case. The ALL and WRITE are in the PGMTREES::VirtHandlers tree, the
134	* rest of this section is going to be about these handlers.
135	*
136	* We'll go thru the life cycle of a handler and try make sense of it all, don't know
137	* how successfull this is gonna be...
138	*
139	* 1. A handler is registered thru the PGMR3HandlerVirtualRegister and
140	* PGMHandlerVirtualRegisterEx APIs. We check for conflicting virtual handlers
141	* and create a new node that is inserted into the AVL tree (range key). Then
142	* a full PGM resync is flagged (clear pool, sync cr3, update virtual bit of PGMPAGE).
143	*
144	* 2. The following PGMSyncCR3/SyncCR3 operation will first make invoke HandlerVirtualUpdate.
145	*
146	* 2a. HandlerVirtualUpdate will will lookup all the pages covered by virtual handlers
147	* via the current guest CR3 and update the physical page -> virtual handler
148	* translation. Needless to say, this doesn't exactly scale very well. If any changes
149	* are detected, it will flag a virtual bit update just like we did on registration.
150	* PGMPHYS pages with changes will have their virtual handler state reset to NONE.
151	*
152	* 2b. The virtual bit update process will iterate all the pages covered by all the
153	* virtual handlers and update the PGMPAGE virtual handler state to the max of all
154	* virtual handlers on that page.
155	*
156	* 2c. Back in SyncCR3 we will now flush the entire shadow page cache to make sure
157	* we don't miss any alias mappings of the monitored pages.
158	*
159	* 2d. SyncCR3 will then proceed with syncing the CR3 table.
160	*
161	* 3. \#PF(np,read) on a page in the range. This will cause it to be synced
162	* read-only and resumed if it's a WRITE handler. If it's an ALL handler we
163	* will call the handlers like in the next step. If the physical mapping has
164	* changed we will - some time in the future - perform a handler callback
165	* (optional) and update the physical -> virtual handler cache.
166	*
167	* 4. \#PF(,write) on a page in the range. This will cause the handler to
168	* be invoked.
169	*
170	* 5. The guest invalidates the page and changes the physical backing or
171	* unmaps it. This should cause the invalidation callback to be invoked
172	* (it might not yet be 100% perfect). Exactly what happens next... is
173	* this where we mess up and end up out of sync for a while?
174	*
175	* 6. The handler is deregistered by the client via PGMHandlerVirtualDeregister.
176	* We will then set all PGMPAGEs in the physical -> virtual handler cache for
177	* this handler to NONE and trigger a full PGM resync (basically the same
178	* as int step 1). Which means 2 is executed again.
179	*
180	*
181	* @subsubsection sub_sec_pgm_handler_virt_todo TODOs
182	*
183	* There is a bunch of things that needs to be done to make the virtual handlers
184	* work 100% correctly and work more efficiently.
185	*
186	* The first bit hasn't been implemented yet because it's going to slow the
187	* whole mess down even more, and besides it seems to be working reliably for
188	* our current uses. OTOH, some of the optimizations might end up more or less
189	* implementing the missing bits, so we'll see.
190	*
191	* On the optimization side, the first thing to do is to try avoid unnecessary
192	* cache flushing. Then try team up with the shadowing code to track changes
193	* in mappings by means of access to them (shadow in), updates to shadows pages,
194	* invlpg, and shadow PT discarding (perhaps).
195	*
196	* Some idea that have popped up for optimization for current and new features:
197	* - bitmap indicating where there are virtual handlers installed.
198	* (4KB => 220 pages, page 212 => covers 32-bit address space 1:1!)
199	* - Further optimize this by min/max (needs min/max avl getters).
200	* - Shadow page table entry bit (if any left)?
201	*
202	*/
203
204
205	/** @page pg_pgm_phys PGM Physical Guest Memory Management
206	*
207	*
208	* Objectives:
209	* - Guest RAM over-commitment using memory ballooning,
210	* zero pages and general page sharing.
211	* - Moving or mirroring a VM onto a different physical machine.
212	*
213	*
214	* @subsection subsec_pgmPhys_Definitions Definitions
215	*
216	* Allocation chunk - A RTR0MemObjAllocPhysNC object and the tracking
217	* machinery assoicated with it.
218	*
219	*
220	*
221	*
222	* @subsection subsec_pgmPhys_AllocPage Allocating a page.
223	*
224	* Initially we map all guest memory to the (per VM) zero page, which
225	* means that none of the read functions will cause pages to be allocated.
226	*
227	* Exception, access bit in page tables that have been shared. This must
228	* be handled, but we must also make sure PGMGst*Modify doesn't make
229	* unnecessary modifications.
230	*
231	* Allocation points:
232	* - PGMPhysSimpleWriteGCPhys and PGMPhysWrite.
233	* - Replacing a zero page mapping at \#PF.
234	* - Replacing a shared page mapping at \#PF.
235	* - ROM registration (currently MMR3RomRegister).
236	* - VM restore (pgmR3Load).
237	*
238	* For the first three it would make sense to keep a few pages handy
239	* until we've reached the max memory commitment for the VM.
240	*
241	* For the ROM registration, we know exactly how many pages we need
242	* and will request these from ring-0. For restore, we will save
243	* the number of non-zero pages in the saved state and allocate
244	* them up front. This would allow the ring-0 component to refuse
245	* the request if the isn't sufficient memory available for VM use.
246	*
247	* Btw. for both ROM and restore allocations we won't be requiring
248	* zeroed pages as they are going to be filled instantly.
249	*
250	*
251	* @subsection subsec_pgmPhys_FreePage Freeing a page
252	*
253	* There are a few points where a page can be freed:
254	* - After being replaced by the zero page.
255	* - After being replaced by a shared page.
256	* - After being ballooned by the guest additions.
257	* - At reset.
258	* - At restore.
259	*
260	* When freeing one or more pages they will be returned to the ring-0
261	* component and replaced by the zero page.
262	*
263	* The reasoning for clearing out all the pages on reset is that it will
264	* return us to the exact same state as on power on, and may thereby help
265	* us reduce the memory load on the system. Further it might have a
266	* (temporary) positive influence on memory fragmentation (@see subsec_pgmPhys_Fragmentation).
267	*
268	* On restore, as mention under the allocation topic, pages should be
269	* freed / allocated depending on how many is actually required by the
270	* new VM state. The simplest approach is to do like on reset, and free
271	* all non-ROM pages and then allocate what we need.
272	*
273	* A measure to prevent some fragmentation, would be to let each allocation
274	* chunk have some affinity towards the VM having allocated the most pages
275	* from it. Also, try make sure to allocate from allocation chunks that
276	* are almost full. Admittedly, both these measures might work counter to
277	* our intentions and its probably not worth putting a lot of effort,
278	* cpu time or memory into this.
279	*
280	*
281	* @subsection subsec_pgmPhys_SharePage Sharing a page
282	*
283	* The basic idea is that there there will be a idle priority kernel
284	* thread walking the non-shared VM pages hashing them and looking for
285	* pages with the same checksum. If such pages are found, it will compare
286	* them byte-by-byte to see if they actually are identical. If found to be
287	* identical it will allocate a shared page, copy the content, check that
288	* the page didn't change while doing this, and finally request both the
289	* VMs to use the shared page instead. If the page is all zeros (special
290	* checksum and byte-by-byte check) it will request the VM that owns it
291	* to replace it with the zero page.
292	*
293	* To make this efficient, we will have to make sure not to try share a page
294	* that will change its contents soon. This part requires the most work.
295	* A simple idea would be to request the VM to write monitor the page for
296	* a while to make sure it isn't modified any time soon. Also, it may
297	* make sense to skip pages that are being write monitored since this
298	* information is readily available to the thread if it works on the
299	* per-VM guest memory structures (presently called PGMRAMRANGE).
300	*
301	*
302	* @subsection subsec_pgmPhys_Fragmentation Fragmentation Concerns and Counter Measures
303	*
304	* The pages are organized in allocation chunks in ring-0, this is a necessity
305	* if we wish to have an OS agnostic approach to this whole thing. (On Linux we
306	* could easily work on a page-by-page basis if we liked. Whether this is possible
307	* or efficient on NT I don't quite know.) Fragmentation within these chunks may
308	* become a problem as part of the idea here is that we wish to return memory to
309	* the host system.
310	*
311	* For instance, starting two VMs at the same time, they will both allocate the
312	* guest memory on-demand and if permitted their page allocations will be
313	* intermixed. Shut down one of the two VMs and it will be difficult to return
314	* any memory to the host system because the page allocation for the two VMs are
315	* mixed up in the same allocation chunks.
316	*
317	* To further complicate matters, when pages are freed because they have been
318	* ballooned or become shared/zero the whole idea is that the page is supposed
319	* to be reused by another VM or returned to the host system. This will cause
320	* allocation chunks to contain pages belonging to different VMs and prevent
321	* returning memory to the host when one of those VM shuts down.
322	*
323	* The only way to really deal with this problem is to move pages. This can
324	* either be done at VM shutdown and or by the idle priority worker thread
325	* that will be responsible for finding sharable/zero pages. The mechanisms
326	* involved for coercing a VM to move a page (or to do it for it) will be
327	* the same as when telling it to share/zero a page.
328	*
329	*
330	* @subsection subsec_pgmPhys_Tracking Tracking Structures And Their Cost
331	*
332	* There's a difficult balance between keeping the per-page tracking structures
333	* (global and guest page) easy to use and keeping them from eating too much
334	* memory. We have limited virtual memory resources available when operating in
335	* 32-bit kernel space (on 64-bit there'll it's quite a different story). The
336	* tracking structures will be attemted designed such that we can deal with up
337	* to 32GB of memory on a 32-bit system and essentially unlimited on 64-bit ones.
338	*
339	*
340	* @subsubsection subsubsec_pgmPhys_Tracking_Kernel Kernel Space
341	*
342	* @see pg_GMM
343	*
344	* @subsubsection subsubsec_pgmPhys_Tracking_PerVM Per-VM
345	*
346	* Fixed info is the physical address of the page (HCPhys) and the page id
347	* (described above). Theoretically we'll need 48(-12) bits for the HCPhys part.
348	* Today we've restricting ourselves to 40(-12) bits because this is the current
349	* restrictions of all AMD64 implementations (I think Barcelona will up this
350	* to 48(-12) bits, not that it really matters) and I needed the bits for
351	* tracking mappings of a page. 48-12 = 36. That leaves 28 bits, which means a
352	* decent range for the page id: 2^(28+12) = 1024TB.
353	*
354	* In additions to these, we'll have to keep maintaining the page flags as we
355	* currently do. Although it wouldn't harm to optimize these quite a bit, like
356	* for instance the ROM shouldn't depend on having a write handler installed
357	* in order for it to become read-only. A RO/RW bit should be considered so
358	* that the page syncing code doesn't have to mess about checking multiple
359	* flag combinations (ROM \|\| RW handler \|\| write monitored) in order to
360	* figure out how to setup a shadow PTE. But this of course, is second
361	* priority at present. Current this requires 12 bits, but could probably
362	* be optimized to ~8.
363	*
364	* Then there's the 24 bits used to track which shadow page tables are
365	* currently mapping a page for the purpose of speeding up physical
366	* access handlers, and thereby the page pool cache. More bit for this
367	* purpose wouldn't hurt IIRC.
368	*
369	* Then there is a new bit in which we need to record what kind of page
370	* this is, shared, zero, normal or write-monitored-normal. This'll
371	* require 2 bits. One bit might be needed for indicating whether a
372	* write monitored page has been written to. And yet another one or
373	* two for tracking migration status. 3-4 bits total then.
374	*
375	* Whatever is left will can be used to record the sharabilitiy of a
376	* page. The page checksum will not be stored in the per-VM table as
377	* the idle thread will not be permitted to do modifications to it.
378	* It will instead have to keep its own working set of potentially
379	* shareable pages and their check sums and stuff.
380	*
381	* For the present we'll keep the current packing of the
382	* PGMRAMRANGE::aHCPhys to keep the changes simple, only of course,
383	* we'll have to change it to a struct with a total of 128-bits at
384	* our disposal.
385	*
386	* The initial layout will be like this:
387	* @verbatim
388	RTHCPHYS HCPhys; The current stuff.
389	63:40 Current shadow PT tracking stuff.
390	39:12 The physical page frame number.
391	11:0 The current flags.
392	uint32_t u28PageId : 28; The page id.
393	uint32_t u2State : 2; The page state { zero, shared, normal, write monitored }.
394	uint32_t fWrittenTo : 1; Whether a write monitored page was written to.
395	uint32_t u1Reserved : 1; Reserved for later.
396	uint32_t u32Reserved; Reserved for later, mostly sharing stats.
397	@endverbatim
398	*
399	* The final layout will be something like this:
400	* @verbatim
401	RTHCPHYS HCPhys; The current stuff.
402	63:48 High page id (12+).
403	47:12 The physical page frame number.
404	11:0 Low page id.
405	uint32_t fReadOnly : 1; Whether it's readonly page (rom or monitored in some way).
406	uint32_t u3Type : 3; The page type {RESERVED, MMIO, MMIO2, ROM, shadowed ROM, RAM}.
407	uint32_t u2PhysMon : 2; Physical access handler type {none, read, write, all}.
408	uint32_t u2VirtMon : 2; Virtual access handler type {none, read, write, all}..
409	uint32_t u2State : 2; The page state { zero, shared, normal, write monitored }.
410	uint32_t fWrittenTo : 1; Whether a write monitored page was written to.
411	uint32_t u20Reserved : 20; Reserved for later, mostly sharing stats.
412	uint32_t u32Tracking; The shadow PT tracking stuff, roughly.
413	@endverbatim
414	*
415	* Cost wise, this means we'll double the cost for guest memory. There isn't anyway
416	* around that I'm afraid. It means that the cost of dealing out 32GB of memory
417	* to one or more VMs is: (32GB >> PAGE_SHIFT) * 16 bytes, or 128MBs. Or another
418	* example, the VM heap cost when assigning 1GB to a VM will be: 4MB.
419	*
420	* A couple of cost examples for the total cost per-VM + kernel.
421	* 32-bit Windows and 32-bit linux:
422	* 1GB guest ram, 256K pages: 4MB + 2MB(+) = 6MB
423	* 4GB guest ram, 1M pages: 16MB + 8MB(+) = 24MB
424	* 32GB guest ram, 8M pages: 128MB + 64MB(+) = 192MB
425	* 64-bit Windows and 64-bit linux:
426	* 1GB guest ram, 256K pages: 4MB + 3MB(+) = 7MB
427	* 4GB guest ram, 1M pages: 16MB + 12MB(+) = 28MB
428	* 32GB guest ram, 8M pages: 128MB + 96MB(+) = 224MB
429	*
430	* UPDATE - 2007-09-27:
431	* Will need a ballooned flag/state too because we cannot
432	* trust the guest 100% and reporting the same page as ballooned more
433	* than once will put the GMM off balance.
434	*
435	*
436	* @subsection subsec_pgmPhys_Serializing Serializing Access
437	*
438	* Initially, we'll try a simple scheme:
439	*
440	* - The per-VM RAM tracking structures (PGMRAMRANGE) is only modified
441	* by the EMT thread of that VM while in the pgm critsect.
442	* - Other threads in the VM process that needs to make reliable use of
443	* the per-VM RAM tracking structures will enter the critsect.
444	* - No process external thread or kernel thread will ever try enter
445	* the pgm critical section, as that just won't work.
446	* - The idle thread (and similar threads) doesn't not need 100% reliable
447	* data when performing it tasks as the EMT thread will be the one to
448	* do the actual changes later anyway. So, as long as it only accesses
449	* the main ram range, it can do so by somehow preventing the VM from
450	* being destroyed while it works on it...
451	*
452	* - The over-commitment management, including the allocating/freeing
453	* chunks, is serialized by a ring-0 mutex lock (a fast one since the
454	* more mundane mutex implementation is broken on Linux).
455	* - A separeate mutex is protecting the set of allocation chunks so
456	* that pages can be shared or/and freed up while some other VM is
457	* allocating more chunks. This mutex can be take from under the other
458	* one, but not the otherway around.
459	*
460	*
461	* @subsection subsec_pgmPhys_Request VM Request interface
462	*
463	* When in ring-0 it will become necessary to send requests to a VM so it can
464	* for instance move a page while defragmenting during VM destroy. The idle
465	* thread will make use of this interface to request VMs to setup shared
466	* pages and to perform write monitoring of pages.
467	*
468	* I would propose an interface similar to the current VMReq interface, similar
469	* in that it doesn't require locking and that the one sending the request may
470	* wait for completion if it wishes to. This shouldn't be very difficult to
471	* realize.
472	*
473	* The requests themselves are also pretty simple. They are basically:
474	* -# Check that some precondition is still true.
475	* -# Do the update.
476	* -# Update all shadow page tables involved with the page.
477	*
478	* The 3rd step is identical to what we're already doing when updating a
479	* physical handler, see pgmHandlerPhysicalSetRamFlagsAndFlushShadowPTs.
480	*
481	*
482	*
483	* @section sec_pgmPhys_MappingCaches Mapping Caches
484	*
485	* In order to be able to map in and out memory and to be able to support
486	* guest with more RAM than we've got virtual address space, we'll employing
487	* a mapping cache. There is already a tiny one for GC (see PGMGCDynMapGCPageEx)
488	* and we'll create a similar one for ring-0 unless we decide to setup a dedicate
489	* memory context for the HWACCM execution.
490	*
491	*
492	* @subsection subsec_pgmPhys_MappingCaches_R3 Ring-3
493	*
494	* We've considered implementing the ring-3 mapping cache page based but found
495	* that this was bother some when one had to take into account TLBs+SMP and
496	* portability (missing the necessary APIs on several platforms). There were
497	* also some performance concerns with this approach which hadn't quite been
498	* worked out.
499	*
500	* Instead, we'll be mapping allocation chunks into the VM process. This simplifies
501	* matters greatly quite a bit since we don't need to invent any new ring-0 stuff,
502	* only some minor RTR0MEMOBJ mapping stuff. The main concern here is that mapping
503	* compared to the previous idea is that mapping or unmapping a 1MB chunk is more
504	* costly than a single page, although how much more costly is uncertain. We'll
505	* try address this by using a very big cache, preferably bigger than the actual
506	* VM RAM size if possible. The current VM RAM sizes should give some idea for
507	* 32-bit boxes, while on 64-bit we can probably get away with employing an
508	* unlimited cache.
509	*
510	* The cache have to parts, as already indicated, the ring-3 side and the
511	* ring-0 side.
512	*
513	* The ring-0 will be tied to the page allocator since it will operate on the
514	* memory objects it contains. It will therefore require the first ring-0 mutex
515	* discussed in @ref subsec_pgmPhys_Serializing. We
516	* some double house keeping wrt to who has mapped what I think, since both
517	* VMMR0.r0 and RTR0MemObj will keep track of mapping relataions
518	*
519	* The ring-3 part will be protected by the pgm critsect. For simplicity, we'll
520	* require anyone that desires to do changes to the mapping cache to do that
521	* from within this critsect. Alternatively, we could employ a separate critsect
522	* for serializing changes to the mapping cache as this would reduce potential
523	* contention with other threads accessing mappings unrelated to the changes
524	* that are in process. We can see about this later, contention will show
525	* up in the statistics anyway, so it'll be simple to tell.
526	*
527	* The organization of the ring-3 part will be very much like how the allocation
528	* chunks are organized in ring-0, that is in an AVL tree by chunk id. To avoid
529	* having to walk the tree all the time, we'll have a couple of lookaside entries
530	* like in we do for I/O ports and MMIO in IOM.
531	*
532	* The simplified flow of a PGMPhysRead/Write function:
533	* -# Enter the PGM critsect.
534	* -# Lookup GCPhys in the ram ranges and get the Page ID.
535	* -# Calc the Allocation Chunk ID from the Page ID.
536	* -# Check the lookaside entries and then the AVL tree for the Chunk ID.
537	* If not found in cache:
538	* -# Call ring-0 and request it to be mapped and supply
539	* a chunk to be unmapped if the cache is maxed out already.
540	* -# Insert the new mapping into the AVL tree (id + R3 address).
541	* -# Update the relevant lookaside entry and return the mapping address.
542	* -# Do the read/write according to monitoring flags and everything.
543	* -# Leave the critsect.
544	*
545	*
546	* @section sec_pgmPhys_Fallback Fallback
547	*
548	* Current all the "second tier" hosts will not support the RTR0MemObjAllocPhysNC
549	* API and thus require a fallback.
550	*
551	* So, when RTR0MemObjAllocPhysNC returns VERR_NOT_SUPPORTED the page allocator
552	* will return to the ring-3 caller (and later ring-0) and asking it to seed
553	* the page allocator with some fresh pages (VERR_GMM_SEED_ME). Ring-3 will
554	* then perform an SUPR3PageAlloc(cbChunk >> PAGE_SHIFT) call and make a
555	* "SeededAllocPages" call to ring-0.
556	*
557	* The first time ring-0 sees the VERR_NOT_SUPPORTED failure it will disable
558	* all page sharing (zero page detection will continue). It will also force
559	* all allocations to come from the VM which seeded the page. Both these
560	* measures are taken to make sure that there will never be any need for
561	* mapping anything into ring-3 - everything will be mapped already.
562	*
563	* Whether we'll continue to use the current MM locked memory management
564	* for this I don't quite know (I'd prefer not to and just ditch that all
565	* togther), we'll see what's simplest to do.
566	*
567	*
568	*
569	* @section sec_pgmPhys_Changes Changes
570	*
571	* Breakdown of the changes involved?
572	*/
573
574	/*******************************************************************************
575	* Header Files *
576	*******************************************************************************/
577	#define LOG_GROUP LOG_GROUP_PGM
578	#include <VBox/dbgf.h>
579	#include <VBox/pgm.h>
580	#include <VBox/cpum.h>
581	#include <VBox/iom.h>
582	#include <VBox/sup.h>
583	#include <VBox/mm.h>
584	#include <VBox/em.h>
585	#include <VBox/stam.h>
586	#include <VBox/rem.h>
587	#include <VBox/dbgf.h>
588	#include <VBox/rem.h>
589	#include <VBox/selm.h>
590	#include <VBox/ssm.h>
591	#include "PGMInternal.h"
592	#include <VBox/vm.h>
593	#include <VBox/dbg.h>
594	#include <VBox/hwaccm.h>
595
596	#include <iprt/assert.h>
597	#include <iprt/alloc.h>
598	#include <iprt/asm.h>
599	#include <iprt/thread.h>
600	#include <iprt/string.h>
601	#ifdef DEBUG_bird
602	# include <iprt/env.h>
603	#endif
604	#include <VBox/param.h>
605	#include <VBox/err.h>
606
607
608	/*******************************************************************************
609	* Defined Constants And Macros *
610	*******************************************************************************/
611	/** Saved state data unit version for 2.5.x and later. */
612	#define PGM_SAVED_STATE_VERSION 9
613	/** Saved state data unit version for 2.2.2 and later. */
614	#define PGM_SAVED_STATE_VERSION_2_2_2 8
615	/** Saved state data unit version for 2.2.0. */
616	#define PGM_SAVED_STATE_VERSION_RR_DESC 7
617	/** Saved state data unit version. */
618	#define PGM_SAVED_STATE_VERSION_OLD_PHYS_CODE 6
619
620
621	/*******************************************************************************
622	* Internal Functions *
623	*******************************************************************************/
624	static int pgmR3InitPaging(PVM pVM);
625	static void pgmR3InitStats(PVM pVM);
626	static DECLCALLBACK(void) pgmR3PhysInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
627	static DECLCALLBACK(void) pgmR3InfoMode(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
628	static DECLCALLBACK(void) pgmR3InfoCr3(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
629	static DECLCALLBACK(int) pgmR3RelocatePhysHandler(PAVLROGCPHYSNODECORE pNode, void *pvUser);
630	static DECLCALLBACK(int) pgmR3RelocateVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser);
631	static DECLCALLBACK(int) pgmR3RelocateHyperVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser);
632	#ifdef VBOX_STRICT
633	static DECLCALLBACK(void) pgmR3ResetNoMorePhysWritesFlag(PVM pVM, VMSTATE enmState, VMSTATE enmOldState, void *pvUser);
634	#endif
635	static DECLCALLBACK(int) pgmR3Save(PVM pVM, PSSMHANDLE pSSM);
636	static DECLCALLBACK(int) pgmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version);
637	static int pgmR3ModeDataInit(PVM pVM, bool fResolveGCAndR0);
638	static void pgmR3ModeDataSwitch(PVM pVM, PVMCPU pVCpu, PGMMODE enmShw, PGMMODE enmGst);
639	static PGMMODE pgmR3CalcShadowMode(PVM pVM, PGMMODE enmGuestMode, SUPPAGINGMODE enmHostMode, PGMMODE enmShadowMode, VMMSWITCHER *penmSwitcher);
640
641	#ifdef VBOX_WITH_DEBUGGER
642	/** @todo Convert the first two commands to 'info' items. */
643	static DECLCALLBACK(int) pgmR3CmdRam(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
644	static DECLCALLBACK(int) pgmR3CmdMap(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
645	static DECLCALLBACK(int) pgmR3CmdError(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
646	static DECLCALLBACK(int) pgmR3CmdSync(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
647	static DECLCALLBACK(int) pgmR3CmdSyncAlways(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
648	# ifdef VBOX_STRICT
649	static DECLCALLBACK(int) pgmR3CmdAssertCR3(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
650	# endif
651	#endif
652
653
654	/*******************************************************************************
655	* Global Variables *
656	*******************************************************************************/
657	#ifdef VBOX_WITH_DEBUGGER
658	/** Argument descriptors for '.pgmerror' and '.pgmerroroff'. */
659	static const DBGCVARDESC g_aPgmErrorArgs[] =
660	{
661	/* cTimesMin, cTimesMax, enmCategory, fFlags, pszName, pszDescription */
662	{ 0, 1, DBGCVAR_CAT_STRING, 0, "where", "Error injection location." },
663	};
664
665	/** Command descriptors. */
666	static const DBGCCMD g_aCmds[] =
667	{
668	/* pszCmd, cArgsMin, cArgsMax, paArgDesc, cArgDescs, pResultDesc, fFlags, pfnHandler pszSyntax, ....pszDescription */
669	{ "pgmram", 0, 0, NULL, 0, NULL, 0, pgmR3CmdRam, "", "Display the ram ranges." },
670	{ "pgmmap", 0, 0, NULL, 0, NULL, 0, pgmR3CmdMap, "", "Display the mapping ranges." },
671	{ "pgmsync", 0, 0, NULL, 0, NULL, 0, pgmR3CmdSync, "", "Sync the CR3 page." },
672	{ "pgmerror", 0, 1, &g_aPgmErrorArgs[0],1, NULL, 0, pgmR3CmdError, "", "Enables inject runtime of errors into parts of PGM." },
673	{ "pgmerroroff", 0, 1, &g_aPgmErrorArgs[0],1, NULL, 0, pgmR3CmdError, "", "Disables inject runtime errors into parts of PGM." },
674	#ifdef VBOX_STRICT
675	{ "pgmassertcr3", 0, 0, NULL, 0, NULL, 0, pgmR3CmdAssertCR3, "", "Check the shadow CR3 mapping." },
676	#endif
677	{ "pgmsyncalways", 0, 0, NULL, 0, NULL, 0, pgmR3CmdSyncAlways, "", "Toggle permanent CR3 syncing." },
678	};
679	#endif
680
681
682
683
684	/*
685	* Shadow - 32-bit mode
686	*/
687	#define PGM_SHW_TYPE PGM_TYPE_32BIT
688	#define PGM_SHW_NAME(name) PGM_SHW_NAME_32BIT(name)
689	#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_32BIT_STR(name)
690	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_32BIT_STR(name)
691	#include "PGMShw.h"
692
693	/* Guest - real mode */
694	#define PGM_GST_TYPE PGM_TYPE_REAL
695	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
696	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_REAL_STR(name)
697	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
698	#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_REAL(name)
699	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_32BIT_REAL_STR(name)
700	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_32BIT_REAL_STR(name)
701	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_PHYS
702	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_32BIT_PD_PHYS
703	#include "PGMBth.h"
704	#include "PGMGstDefs.h"
705	#include "PGMGst.h"
706	#undef BTH_PGMPOOLKIND_PT_FOR_PT
707	#undef BTH_PGMPOOLKIND_ROOT
708	#undef PGM_BTH_NAME
709	#undef PGM_BTH_NAME_RC_STR
710	#undef PGM_BTH_NAME_R0_STR
711	#undef PGM_GST_TYPE
712	#undef PGM_GST_NAME
713	#undef PGM_GST_NAME_RC_STR
714	#undef PGM_GST_NAME_R0_STR
715
716	/* Guest - protected mode */
717	#define PGM_GST_TYPE PGM_TYPE_PROT
718	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
719	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PROT_STR(name)
720	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
721	#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_PROT(name)
722	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_32BIT_PROT_STR(name)
723	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_32BIT_PROT_STR(name)
724	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_PHYS
725	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_32BIT_PD_PHYS
726	#include "PGMBth.h"
727	#include "PGMGstDefs.h"
728	#include "PGMGst.h"
729	#undef BTH_PGMPOOLKIND_PT_FOR_PT
730	#undef BTH_PGMPOOLKIND_ROOT
731	#undef PGM_BTH_NAME
732	#undef PGM_BTH_NAME_RC_STR
733	#undef PGM_BTH_NAME_R0_STR
734	#undef PGM_GST_TYPE
735	#undef PGM_GST_NAME
736	#undef PGM_GST_NAME_RC_STR
737	#undef PGM_GST_NAME_R0_STR
738
739	/* Guest - 32-bit mode */
740	#define PGM_GST_TYPE PGM_TYPE_32BIT
741	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
742	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_32BIT_STR(name)
743	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
744	#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_32BIT(name)
745	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_32BIT_32BIT_STR(name)
746	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_32BIT_32BIT_STR(name)
747	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT
748	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB
749	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_32BIT_PD
750	#include "PGMBth.h"
751	#include "PGMGstDefs.h"
752	#include "PGMGst.h"
753	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
754	#undef BTH_PGMPOOLKIND_PT_FOR_PT
755	#undef BTH_PGMPOOLKIND_ROOT
756	#undef PGM_BTH_NAME
757	#undef PGM_BTH_NAME_RC_STR
758	#undef PGM_BTH_NAME_R0_STR
759	#undef PGM_GST_TYPE
760	#undef PGM_GST_NAME
761	#undef PGM_GST_NAME_RC_STR
762	#undef PGM_GST_NAME_R0_STR
763
764	#undef PGM_SHW_TYPE
765	#undef PGM_SHW_NAME
766	#undef PGM_SHW_NAME_RC_STR
767	#undef PGM_SHW_NAME_R0_STR
768
769
770	/*
771	* Shadow - PAE mode
772	*/
773	#define PGM_SHW_TYPE PGM_TYPE_PAE
774	#define PGM_SHW_NAME(name) PGM_SHW_NAME_PAE(name)
775	#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_PAE_STR(name)
776	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_PAE_STR(name)
777	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_REAL(name)
778	#include "PGMShw.h"
779
780	/* Guest - real mode */
781	#define PGM_GST_TYPE PGM_TYPE_REAL
782	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
783	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_REAL_STR(name)
784	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
785	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_REAL(name)
786	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_PAE_REAL_STR(name)
787	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_REAL_STR(name)
788	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
789	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT_PHYS
790	#include "PGMGstDefs.h"
791	#include "PGMBth.h"
792	#undef BTH_PGMPOOLKIND_PT_FOR_PT
793	#undef BTH_PGMPOOLKIND_ROOT
794	#undef PGM_BTH_NAME
795	#undef PGM_BTH_NAME_RC_STR
796	#undef PGM_BTH_NAME_R0_STR
797	#undef PGM_GST_TYPE
798	#undef PGM_GST_NAME
799	#undef PGM_GST_NAME_RC_STR
800	#undef PGM_GST_NAME_R0_STR
801
802	/* Guest - protected mode */
803	#define PGM_GST_TYPE PGM_TYPE_PROT
804	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
805	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PROT_STR(name)
806	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
807	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_PROT(name)
808	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_PAE_PROT_STR(name)
809	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_PROT_STR(name)
810	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
811	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT_PHYS
812	#include "PGMGstDefs.h"
813	#include "PGMBth.h"
814	#undef BTH_PGMPOOLKIND_PT_FOR_PT
815	#undef BTH_PGMPOOLKIND_ROOT
816	#undef PGM_BTH_NAME
817	#undef PGM_BTH_NAME_RC_STR
818	#undef PGM_BTH_NAME_R0_STR
819	#undef PGM_GST_TYPE
820	#undef PGM_GST_NAME
821	#undef PGM_GST_NAME_RC_STR
822	#undef PGM_GST_NAME_R0_STR
823
824	/* Guest - 32-bit mode */
825	#define PGM_GST_TYPE PGM_TYPE_32BIT
826	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
827	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_32BIT_STR(name)
828	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
829	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_32BIT(name)
830	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_PAE_32BIT_STR(name)
831	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_32BIT_STR(name)
832	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_32BIT_PT
833	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB
834	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT_FOR_32BIT
835	#include "PGMGstDefs.h"
836	#include "PGMBth.h"
837	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
838	#undef BTH_PGMPOOLKIND_PT_FOR_PT
839	#undef BTH_PGMPOOLKIND_ROOT
840	#undef PGM_BTH_NAME
841	#undef PGM_BTH_NAME_RC_STR
842	#undef PGM_BTH_NAME_R0_STR
843	#undef PGM_GST_TYPE
844	#undef PGM_GST_NAME
845	#undef PGM_GST_NAME_RC_STR
846	#undef PGM_GST_NAME_R0_STR
847
848	/* Guest - PAE mode */
849	#define PGM_GST_TYPE PGM_TYPE_PAE
850	#define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
851	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PAE_STR(name)
852	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PAE_STR(name)
853	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_PAE(name)
854	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_PAE_PAE_STR(name)
855	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_PAE_STR(name)
856	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
857	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
858	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT
859	#include "PGMBth.h"
860	#include "PGMGstDefs.h"
861	#include "PGMGst.h"
862	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
863	#undef BTH_PGMPOOLKIND_PT_FOR_PT
864	#undef BTH_PGMPOOLKIND_ROOT
865	#undef PGM_BTH_NAME
866	#undef PGM_BTH_NAME_RC_STR
867	#undef PGM_BTH_NAME_R0_STR
868	#undef PGM_GST_TYPE
869	#undef PGM_GST_NAME
870	#undef PGM_GST_NAME_RC_STR
871	#undef PGM_GST_NAME_R0_STR
872
873	#undef PGM_SHW_TYPE
874	#undef PGM_SHW_NAME
875	#undef PGM_SHW_NAME_RC_STR
876	#undef PGM_SHW_NAME_R0_STR
877
878
879	/*
880	* Shadow - AMD64 mode
881	*/
882	#define PGM_SHW_TYPE PGM_TYPE_AMD64
883	#define PGM_SHW_NAME(name) PGM_SHW_NAME_AMD64(name)
884	#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_AMD64_STR(name)
885	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_AMD64_STR(name)
886	#include "PGMShw.h"
887
888	#ifdef VBOX_WITH_64_BITS_GUESTS
889	/* Guest - AMD64 mode */
890	# define PGM_GST_TYPE PGM_TYPE_AMD64
891	# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
892	# define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_AMD64_STR(name)
893	# define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_AMD64_STR(name)
894	# define PGM_BTH_NAME(name) PGM_BTH_NAME_AMD64_AMD64(name)
895	# define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_AMD64_AMD64_STR(name)
896	# define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_AMD64_AMD64_STR(name)
897	# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
898	# define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
899	# define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_64BIT_PML4
900	# include "PGMBth.h"
901	# include "PGMGstDefs.h"
902	# include "PGMGst.h"
903	# undef BTH_PGMPOOLKIND_PT_FOR_BIG
904	# undef BTH_PGMPOOLKIND_PT_FOR_PT
905	# undef BTH_PGMPOOLKIND_ROOT
906	# undef PGM_BTH_NAME
907	# undef PGM_BTH_NAME_RC_STR
908	# undef PGM_BTH_NAME_R0_STR
909	# undef PGM_GST_TYPE
910	# undef PGM_GST_NAME
911	# undef PGM_GST_NAME_RC_STR
912	# undef PGM_GST_NAME_R0_STR
913	#endif /* VBOX_WITH_64_BITS_GUESTS */
914
915	#undef PGM_SHW_TYPE
916	#undef PGM_SHW_NAME
917	#undef PGM_SHW_NAME_RC_STR
918	#undef PGM_SHW_NAME_R0_STR
919
920
921	/*
922	* Shadow - Nested paging mode
923	*/
924	#define PGM_SHW_TYPE PGM_TYPE_NESTED
925	#define PGM_SHW_NAME(name) PGM_SHW_NAME_NESTED(name)
926	#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_NESTED_STR(name)
927	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_NESTED_STR(name)
928	#include "PGMShw.h"
929
930	/* Guest - real mode */
931	#define PGM_GST_TYPE PGM_TYPE_REAL
932	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
933	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_REAL_STR(name)
934	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
935	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_REAL(name)
936	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_REAL_STR(name)
937	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_REAL_STR(name)
938	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
939	#include "PGMGstDefs.h"
940	#include "PGMBth.h"
941	#undef BTH_PGMPOOLKIND_PT_FOR_PT
942	#undef PGM_BTH_NAME
943	#undef PGM_BTH_NAME_RC_STR
944	#undef PGM_BTH_NAME_R0_STR
945	#undef PGM_GST_TYPE
946	#undef PGM_GST_NAME
947	#undef PGM_GST_NAME_RC_STR
948	#undef PGM_GST_NAME_R0_STR
949
950	/* Guest - protected mode */
951	#define PGM_GST_TYPE PGM_TYPE_PROT
952	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
953	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PROT_STR(name)
954	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
955	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_PROT(name)
956	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_PROT_STR(name)
957	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_PROT_STR(name)
958	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
959	#include "PGMGstDefs.h"
960	#include "PGMBth.h"
961	#undef BTH_PGMPOOLKIND_PT_FOR_PT
962	#undef PGM_BTH_NAME
963	#undef PGM_BTH_NAME_RC_STR
964	#undef PGM_BTH_NAME_R0_STR
965	#undef PGM_GST_TYPE
966	#undef PGM_GST_NAME
967	#undef PGM_GST_NAME_RC_STR
968	#undef PGM_GST_NAME_R0_STR
969
970	/* Guest - 32-bit mode */
971	#define PGM_GST_TYPE PGM_TYPE_32BIT
972	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
973	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_32BIT_STR(name)
974	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
975	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_32BIT(name)
976	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_32BIT_STR(name)
977	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_32BIT_STR(name)
978	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_32BIT_PT
979	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB
980	#include "PGMGstDefs.h"
981	#include "PGMBth.h"
982	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
983	#undef BTH_PGMPOOLKIND_PT_FOR_PT
984	#undef PGM_BTH_NAME
985	#undef PGM_BTH_NAME_RC_STR
986	#undef PGM_BTH_NAME_R0_STR
987	#undef PGM_GST_TYPE
988	#undef PGM_GST_NAME
989	#undef PGM_GST_NAME_RC_STR
990	#undef PGM_GST_NAME_R0_STR
991
992	/* Guest - PAE mode */
993	#define PGM_GST_TYPE PGM_TYPE_PAE
994	#define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
995	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PAE_STR(name)
996	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PAE_STR(name)
997	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_PAE(name)
998	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_PAE_STR(name)
999	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_PAE_STR(name)
1000	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
1001	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
1002	#include "PGMGstDefs.h"
1003	#include "PGMBth.h"
1004	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
1005	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1006	#undef PGM_BTH_NAME
1007	#undef PGM_BTH_NAME_RC_STR
1008	#undef PGM_BTH_NAME_R0_STR
1009	#undef PGM_GST_TYPE
1010	#undef PGM_GST_NAME
1011	#undef PGM_GST_NAME_RC_STR
1012	#undef PGM_GST_NAME_R0_STR
1013
1014	#ifdef VBOX_WITH_64_BITS_GUESTS
1015	/* Guest - AMD64 mode */
1016	# define PGM_GST_TYPE PGM_TYPE_AMD64
1017	# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
1018	# define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_AMD64_STR(name)
1019	# define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_AMD64_STR(name)
1020	# define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_AMD64(name)
1021	# define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_AMD64_STR(name)
1022	# define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_AMD64_STR(name)
1023	# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
1024	# define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
1025	# include "PGMGstDefs.h"
1026	# include "PGMBth.h"
1027	# undef BTH_PGMPOOLKIND_PT_FOR_BIG
1028	# undef BTH_PGMPOOLKIND_PT_FOR_PT
1029	# undef PGM_BTH_NAME
1030	# undef PGM_BTH_NAME_RC_STR
1031	# undef PGM_BTH_NAME_R0_STR
1032	# undef PGM_GST_TYPE
1033	# undef PGM_GST_NAME
1034	# undef PGM_GST_NAME_RC_STR
1035	# undef PGM_GST_NAME_R0_STR
1036	#endif /* VBOX_WITH_64_BITS_GUESTS */
1037
1038	#undef PGM_SHW_TYPE
1039	#undef PGM_SHW_NAME
1040	#undef PGM_SHW_NAME_RC_STR
1041	#undef PGM_SHW_NAME_R0_STR
1042
1043
1044	/*
1045	* Shadow - EPT
1046	*/
1047	#define PGM_SHW_TYPE PGM_TYPE_EPT
1048	#define PGM_SHW_NAME(name) PGM_SHW_NAME_EPT(name)
1049	#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_EPT_STR(name)
1050	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_EPT_STR(name)
1051	#include "PGMShw.h"
1052
1053	/* Guest - real mode */
1054	#define PGM_GST_TYPE PGM_TYPE_REAL
1055	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
1056	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_REAL_STR(name)
1057	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
1058	#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_REAL(name)
1059	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_REAL_STR(name)
1060	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_REAL_STR(name)
1061	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
1062	#include "PGMGstDefs.h"
1063	#include "PGMBth.h"
1064	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1065	#undef PGM_BTH_NAME
1066	#undef PGM_BTH_NAME_RC_STR
1067	#undef PGM_BTH_NAME_R0_STR
1068	#undef PGM_GST_TYPE
1069	#undef PGM_GST_NAME
1070	#undef PGM_GST_NAME_RC_STR
1071	#undef PGM_GST_NAME_R0_STR
1072
1073	/* Guest - protected mode */
1074	#define PGM_GST_TYPE PGM_TYPE_PROT
1075	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
1076	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PROT_STR(name)
1077	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
1078	#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_PROT(name)
1079	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_PROT_STR(name)
1080	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_PROT_STR(name)
1081	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
1082	#include "PGMGstDefs.h"
1083	#include "PGMBth.h"
1084	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1085	#undef PGM_BTH_NAME
1086	#undef PGM_BTH_NAME_RC_STR
1087	#undef PGM_BTH_NAME_R0_STR
1088	#undef PGM_GST_TYPE
1089	#undef PGM_GST_NAME
1090	#undef PGM_GST_NAME_RC_STR
1091	#undef PGM_GST_NAME_R0_STR
1092
1093	/* Guest - 32-bit mode */
1094	#define PGM_GST_TYPE PGM_TYPE_32BIT
1095	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
1096	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_32BIT_STR(name)
1097	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
1098	#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_32BIT(name)
1099	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_32BIT_STR(name)
1100	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_32BIT_STR(name)
1101	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_32BIT_PT
1102	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB
1103	#include "PGMGstDefs.h"
1104	#include "PGMBth.h"
1105	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
1106	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1107	#undef PGM_BTH_NAME
1108	#undef PGM_BTH_NAME_RC_STR
1109	#undef PGM_BTH_NAME_R0_STR
1110	#undef PGM_GST_TYPE
1111	#undef PGM_GST_NAME
1112	#undef PGM_GST_NAME_RC_STR
1113	#undef PGM_GST_NAME_R0_STR
1114
1115	/* Guest - PAE mode */
1116	#define PGM_GST_TYPE PGM_TYPE_PAE
1117	#define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
1118	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PAE_STR(name)
1119	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PAE_STR(name)
1120	#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_PAE(name)
1121	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_PAE_STR(name)
1122	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_PAE_STR(name)
1123	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
1124	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
1125	#include "PGMGstDefs.h"
1126	#include "PGMBth.h"
1127	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
1128	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1129	#undef PGM_BTH_NAME
1130	#undef PGM_BTH_NAME_RC_STR
1131	#undef PGM_BTH_NAME_R0_STR
1132	#undef PGM_GST_TYPE
1133	#undef PGM_GST_NAME
1134	#undef PGM_GST_NAME_RC_STR
1135	#undef PGM_GST_NAME_R0_STR
1136
1137	#ifdef VBOX_WITH_64_BITS_GUESTS
1138	/* Guest - AMD64 mode */
1139	# define PGM_GST_TYPE PGM_TYPE_AMD64
1140	# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
1141	# define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_AMD64_STR(name)
1142	# define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_AMD64_STR(name)
1143	# define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_AMD64(name)
1144	# define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_AMD64_STR(name)
1145	# define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_AMD64_STR(name)
1146	# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
1147	# define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
1148	# include "PGMGstDefs.h"
1149	# include "PGMBth.h"
1150	# undef BTH_PGMPOOLKIND_PT_FOR_BIG
1151	# undef BTH_PGMPOOLKIND_PT_FOR_PT
1152	# undef PGM_BTH_NAME
1153	# undef PGM_BTH_NAME_RC_STR
1154	# undef PGM_BTH_NAME_R0_STR
1155	# undef PGM_GST_TYPE
1156	# undef PGM_GST_NAME
1157	# undef PGM_GST_NAME_RC_STR
1158	# undef PGM_GST_NAME_R0_STR
1159	#endif /* VBOX_WITH_64_BITS_GUESTS */
1160
1161	#undef PGM_SHW_TYPE
1162	#undef PGM_SHW_NAME
1163	#undef PGM_SHW_NAME_RC_STR
1164	#undef PGM_SHW_NAME_R0_STR
1165
1166
1167
1168	/**
1169	* Initiates the paging of VM.
1170	*
1171	* @returns VBox status code.
1172	* @param pVM Pointer to VM structure.
1173	*/
1174	VMMR3DECL(int) PGMR3Init(PVM pVM)
1175	{
1176	LogFlow(("PGMR3Init:\n"));
1177	PCFGMNODE pCfgPGM = CFGMR3GetChild(CFGMR3GetRoot(pVM), "/PGM");
1178	int rc;
1179
1180	/*
1181	* Assert alignment and sizes.
1182	*/
1183	AssertCompile(sizeof(pVM->pgm.s) <= sizeof(pVM->pgm.padding));
1184	AssertCompileMemberAlignment(PGM, CritSect, sizeof(uintptr_t));
1185
1186	/*
1187	* Init the structure.
1188	*/
1189	pVM->pgm.s.offVM = RT_OFFSETOF(VM, pgm.s);
1190	pVM->pgm.s.offVCpuPGM = RT_OFFSETOF(VMCPU, pgm.s);
1191
1192	/* Init the per-CPU part. */
1193	for (unsigned i=0;i<pVM->cCPUs;i++)
1194	{
1195	PVMCPU pVCpu = &pVM->aCpus[i];
1196	PPGMCPU pPGM = &pVCpu->pgm.s;
1197
1198	pPGM->offVM = (uintptr_t)&pVCpu->pgm.s - (uintptr_t)pVM;
1199	pPGM->offVCpu = RT_OFFSETOF(VMCPU, pgm.s);
1200	pPGM->offPGM = (uintptr_t)&pVCpu->pgm.s - (uintptr_t)&pVM->pgm.s;
1201
1202	pPGM->enmShadowMode = PGMMODE_INVALID;
1203	pPGM->enmGuestMode = PGMMODE_INVALID;
1204
1205	pPGM->GCPhysCR3 = NIL_RTGCPHYS;
1206
1207	pPGM->pGstPaePdptR3 = NULL;
1208	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
1209	pPGM->pGstPaePdptR0 = NIL_RTR0PTR;
1210	#endif
1211	pPGM->pGstPaePdptRC = NIL_RTRCPTR;
1212	for (unsigned i = 0; i < RT_ELEMENTS(pVCpu->pgm.s.apGstPaePDsR3); i++)
1213	{
1214	pPGM->apGstPaePDsR3[i] = NULL;
1215	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
1216	pPGM->apGstPaePDsR0[i] = NIL_RTR0PTR;
1217	#endif
1218	pPGM->apGstPaePDsRC[i] = NIL_RTRCPTR;
1219	pPGM->aGCPhysGstPaePDs[i] = NIL_RTGCPHYS;
1220	pPGM->aGCPhysGstPaePDsMonitored[i] = NIL_RTGCPHYS;
1221	}
1222
1223	pPGM->fA20Enabled = true;
1224	}
1225
1226	pVM->pgm.s.enmHostMode = SUPPAGINGMODE_INVALID;
1227	pVM->pgm.s.GCPhys4MBPSEMask = RT_BIT_64(32) - 1; /* default; checked later */
1228	pVM->pgm.s.GCPtrPrevRamRangeMapping = MM_HYPER_AREA_ADDRESS;
1229
1230	rc = CFGMR3QueryBoolDef(CFGMR3GetRoot(pVM), "RamPreAlloc", &pVM->pgm.s.fRamPreAlloc,
1231	#ifdef VBOX_WITH_PREALLOC_RAM_BY_DEFAULT
1232	true
1233	#else
1234	false
1235	#endif
1236	);
1237	AssertLogRelRCReturn(rc, rc);
1238
1239	#if HC_ARCH_BITS == 64 \|\| 1 /** @todo 4GB/32-bit: remove \|\| 1 later and adjust the limit. */
1240	rc = CFGMR3QueryU32Def(pCfgPGM, "MaxRing3Chunks", &pVM->pgm.s.ChunkR3Map.cMax, UINT32_MAX);
1241	#else
1242	rc = CFGMR3QueryU32Def(pCfgPGM, "MaxRing3Chunks", &pVM->pgm.s.ChunkR3Map.cMax, _1G / GMM_CHUNK_SIZE);
1243	#endif
1244	AssertLogRelRCReturn(rc, rc);
1245	for (uint32_t i = 0; i < RT_ELEMENTS(pVM->pgm.s.ChunkR3Map.Tlb.aEntries); i++)
1246	pVM->pgm.s.ChunkR3Map.Tlb.aEntries[i].idChunk = NIL_GMM_CHUNKID;
1247
1248	/*
1249	* Get the configured RAM size - to estimate saved state size.
1250	*/
1251	uint64_t cbRam;
1252	rc = CFGMR3QueryU64(CFGMR3GetRoot(pVM), "RamSize", &cbRam);
1253	if (rc == VERR_CFGM_VALUE_NOT_FOUND)
1254	cbRam = 0;
1255	else if (RT_SUCCESS(rc))
1256	{
1257	if (cbRam < PAGE_SIZE)
1258	cbRam = 0;
1259	cbRam = RT_ALIGN_64(cbRam, PAGE_SIZE);
1260	}
1261	else
1262	{
1263	AssertMsgFailed(("Configuration error: Failed to query integer \"RamSize\", rc=%Rrc.\n", rc));
1264	return rc;
1265	}
1266
1267	/*
1268	* Register callbacks, string formatters and the saved state data unit.
1269	*/
1270	#ifdef VBOX_STRICT
1271	VMR3AtStateRegister(pVM, pgmR3ResetNoMorePhysWritesFlag, NULL);
1272	#endif
1273	PGMRegisterStringFormatTypes();
1274
1275	rc = SSMR3RegisterInternal(pVM, "pgm", 1, PGM_SAVED_STATE_VERSION, (size_t)cbRam + sizeof(PGM),
1276	NULL, pgmR3Save, NULL,
1277	NULL, pgmR3Load, NULL);
1278	if (RT_FAILURE(rc))
1279	return rc;
1280
1281	/*
1282	* Initialize the PGM critical section and flush the phys TLBs
1283	*/
1284	rc = PDMR3CritSectInit(pVM, &pVM->pgm.s.CritSect, "PGM");
1285	AssertRCReturn(rc, rc);
1286
1287	PGMR3PhysChunkInvalidateTLB(pVM);
1288	PGMPhysInvalidatePageR3MapTLB(pVM);
1289	PGMPhysInvalidatePageR0MapTLB(pVM);
1290	PGMPhysInvalidatePageGCMapTLB(pVM);
1291
1292	/*
1293	* For the time being we sport a full set of handy pages in addition to the base
1294	* memory to simplify things.
1295	*/
1296	rc = MMR3ReserveHandyPages(pVM, RT_ELEMENTS(pVM->pgm.s.aHandyPages)); /** @todo this should be changed to PGM_HANDY_PAGES_MIN but this needs proper testing... */
1297	AssertRCReturn(rc, rc);
1298
1299	/*
1300	* Trees
1301	*/
1302	rc = MMHyperAlloc(pVM, sizeof(PGMTREES), 0, MM_TAG_PGM, (void **)&pVM->pgm.s.pTreesR3);
1303	if (RT_SUCCESS(rc))
1304	{
1305	pVM->pgm.s.pTreesR0 = MMHyperR3ToR0(pVM, pVM->pgm.s.pTreesR3);
1306	pVM->pgm.s.pTreesRC = MMHyperR3ToRC(pVM, pVM->pgm.s.pTreesR3);
1307
1308	/*
1309	* Alocate the zero page.
1310	*/
1311	rc = MMHyperAlloc(pVM, PAGE_SIZE, PAGE_SIZE, MM_TAG_PGM, &pVM->pgm.s.pvZeroPgR3);
1312	}
1313	if (RT_SUCCESS(rc))
1314	{
1315	pVM->pgm.s.pvZeroPgRC = MMHyperR3ToRC(pVM, pVM->pgm.s.pvZeroPgR3);
1316	pVM->pgm.s.pvZeroPgR0 = MMHyperR3ToR0(pVM, pVM->pgm.s.pvZeroPgR3);
1317	pVM->pgm.s.HCPhysZeroPg = MMR3HyperHCVirt2HCPhys(pVM, pVM->pgm.s.pvZeroPgR3);
1318	AssertRelease(pVM->pgm.s.HCPhysZeroPg != NIL_RTHCPHYS);
1319
1320	/*
1321	* Init the paging.
1322	*/
1323	rc = pgmR3InitPaging(pVM);
1324	}
1325	if (RT_SUCCESS(rc))
1326	{
1327	/*
1328	* Init the page pool.
1329	*/
1330	rc = pgmR3PoolInit(pVM);
1331	}
1332	if (RT_SUCCESS(rc))
1333	{
1334	for (unsigned i=0;i<pVM->cCPUs;i++)
1335	{
1336	PVMCPU pVCpu = &pVM->aCpus[i];
1337
1338	rc = PGMR3ChangeMode(pVM, pVCpu, PGMMODE_REAL);
1339	if (RT_FAILURE(rc))
1340	break;
1341	}
1342	}
1343
1344	if (RT_SUCCESS(rc))
1345	{
1346	/*
1347	* Info & statistics
1348	*/
1349	DBGFR3InfoRegisterInternal(pVM, "mode",
1350	"Shows the current paging mode. "
1351	"Recognizes 'all', 'guest', 'shadow' and 'host' as arguments, defaulting to 'all' if nothing's given.",
1352	pgmR3InfoMode);
1353	DBGFR3InfoRegisterInternal(pVM, "pgmcr3",
1354	"Dumps all the entries in the top level paging table. No arguments.",
1355	pgmR3InfoCr3);
1356	DBGFR3InfoRegisterInternal(pVM, "phys",
1357	"Dumps all the physical address ranges. No arguments.",
1358	pgmR3PhysInfo);
1359	DBGFR3InfoRegisterInternal(pVM, "handlers",
1360	"Dumps physical, virtual and hyper virtual handlers. "
1361	"Pass 'phys', 'virt', 'hyper' as argument if only one kind is wanted."
1362	"Add 'nost' if the statistics are unwanted, use together with 'all' or explicit selection.",
1363	pgmR3InfoHandlers);
1364	DBGFR3InfoRegisterInternal(pVM, "mappings",
1365	"Dumps guest mappings.",
1366	pgmR3MapInfo);
1367
1368	pgmR3InitStats(pVM);
1369
1370	#ifdef VBOX_WITH_DEBUGGER
1371	/*
1372	* Debugger commands.
1373	*/
1374	static bool s_fRegisteredCmds = false;
1375	if (!s_fRegisteredCmds)
1376	{
1377	int rc = DBGCRegisterCommands(&g_aCmds[0], RT_ELEMENTS(g_aCmds));
1378	if (RT_SUCCESS(rc))
1379	s_fRegisteredCmds = true;
1380	}
1381	#endif
1382	return VINF_SUCCESS;
1383	}
1384
1385	/* Almost no cleanup necessary, MM frees all memory. */
1386	PDMR3CritSectDelete(&pVM->pgm.s.CritSect);
1387
1388	return rc;
1389	}
1390
1391
1392	/**
1393	* Initializes the per-VCPU PGM.
1394	*
1395	* @returns VBox status code.
1396	* @param pVM The VM to operate on.
1397	*/
1398	VMMR3DECL(int) PGMR3InitCPU(PVM pVM)
1399	{
1400	LogFlow(("PGMR3InitCPU\n"));
1401	return VINF_SUCCESS;
1402	}
1403
1404
1405	/**
1406	* Init paging.
1407	*
1408	* Since we need to check what mode the host is operating in before we can choose
1409	* the right paging functions for the host we have to delay this until R0 has
1410	* been initialized.
1411	*
1412	* @returns VBox status code.
1413	* @param pVM VM handle.
1414	*/
1415	static int pgmR3InitPaging(PVM pVM)
1416	{
1417	/*
1418	* Force a recalculation of modes and switcher so everyone gets notified.
1419	*/
1420	for (unsigned i=0;i<pVM->cCPUs;i++)
1421	{
1422	PVMCPU pVCpu = &pVM->aCpus[i];
1423
1424	pVCpu->pgm.s.enmShadowMode = PGMMODE_INVALID;
1425	pVCpu->pgm.s.enmGuestMode = PGMMODE_INVALID;
1426	}
1427
1428	pVM->pgm.s.enmHostMode = SUPPAGINGMODE_INVALID;
1429
1430	/*
1431	* Allocate static mapping space for whatever the cr3 register
1432	* points to and in the case of PAE mode to the 4 PDs.
1433	*/
1434	int rc = MMR3HyperReserve(pVM, PAGE_SIZE * 5, "CR3 mapping", &pVM->pgm.s.GCPtrCR3Mapping);
1435	if (RT_FAILURE(rc))
1436	{
1437	AssertMsgFailed(("Failed to reserve two pages for cr mapping in HMA, rc=%Rrc\n", rc));
1438	return rc;
1439	}
1440	MMR3HyperReserve(pVM, PAGE_SIZE, "fence", NULL);
1441
1442	/*
1443	* Allocate pages for the three possible intermediate contexts
1444	* (AMD64, PAE and plain 32-Bit). We maintain all three contexts
1445	* for the sake of simplicity. The AMD64 uses the PAE for the
1446	* lower levels, making the total number of pages 11 (3 + 7 + 1).
1447	*
1448	* We assume that two page tables will be enought for the core code
1449	* mappings (HC virtual and identity).
1450	*/
1451	pVM->pgm.s.pInterPD = (PX86PD)MMR3PageAllocLow(pVM); AssertReturn(pVM->pgm.s.pInterPD, VERR_NO_PAGE_MEMORY);
1452	pVM->pgm.s.apInterPTs[0] = (PX86PT)MMR3PageAllocLow(pVM); AssertReturn(pVM->pgm.s.apInterPTs[0], VERR_NO_PAGE_MEMORY);
1453	pVM->pgm.s.apInterPTs[1] = (PX86PT)MMR3PageAllocLow(pVM); AssertReturn(pVM->pgm.s.apInterPTs[1], VERR_NO_PAGE_MEMORY);
1454	pVM->pgm.s.apInterPaePTs[0] = (PX86PTPAE)MMR3PageAlloc(pVM); AssertReturn(pVM->pgm.s.apInterPaePTs[0], VERR_NO_PAGE_MEMORY);
1455	pVM->pgm.s.apInterPaePTs[1] = (PX86PTPAE)MMR3PageAlloc(pVM); AssertReturn(pVM->pgm.s.apInterPaePTs[1], VERR_NO_PAGE_MEMORY);
1456	pVM->pgm.s.apInterPaePDs[0] = (PX86PDPAE)MMR3PageAlloc(pVM); AssertReturn(pVM->pgm.s.apInterPaePDs[0], VERR_NO_PAGE_MEMORY);
1457	pVM->pgm.s.apInterPaePDs[1] = (PX86PDPAE)MMR3PageAlloc(pVM); AssertReturn(pVM->pgm.s.apInterPaePDs[1], VERR_NO_PAGE_MEMORY);
1458	pVM->pgm.s.apInterPaePDs[2] = (PX86PDPAE)MMR3PageAlloc(pVM); AssertReturn(pVM->pgm.s.apInterPaePDs[2], VERR_NO_PAGE_MEMORY);
1459	pVM->pgm.s.apInterPaePDs[3] = (PX86PDPAE)MMR3PageAlloc(pVM); AssertReturn(pVM->pgm.s.apInterPaePDs[3], VERR_NO_PAGE_MEMORY);
1460	pVM->pgm.s.pInterPaePDPT = (PX86PDPT)MMR3PageAllocLow(pVM); AssertReturn(pVM->pgm.s.pInterPaePDPT, VERR_NO_PAGE_MEMORY);
1461	pVM->pgm.s.pInterPaePDPT64 = (PX86PDPT)MMR3PageAllocLow(pVM); AssertReturn(pVM->pgm.s.pInterPaePDPT64, VERR_NO_PAGE_MEMORY);
1462	pVM->pgm.s.pInterPaePML4 = (PX86PML4)MMR3PageAllocLow(pVM); AssertReturn(pVM->pgm.s.pInterPaePML4, VERR_NO_PAGE_MEMORY);
1463
1464	pVM->pgm.s.HCPhysInterPD = MMPage2Phys(pVM, pVM->pgm.s.pInterPD);
1465	AssertRelease(pVM->pgm.s.HCPhysInterPD != NIL_RTHCPHYS && !(pVM->pgm.s.HCPhysInterPD & PAGE_OFFSET_MASK));
1466	pVM->pgm.s.HCPhysInterPaePDPT = MMPage2Phys(pVM, pVM->pgm.s.pInterPaePDPT);
1467	AssertRelease(pVM->pgm.s.HCPhysInterPaePDPT != NIL_RTHCPHYS && !(pVM->pgm.s.HCPhysInterPaePDPT & PAGE_OFFSET_MASK));
1468	pVM->pgm.s.HCPhysInterPaePML4 = MMPage2Phys(pVM, pVM->pgm.s.pInterPaePML4);
1469	AssertRelease(pVM->pgm.s.HCPhysInterPaePML4 != NIL_RTHCPHYS && !(pVM->pgm.s.HCPhysInterPaePML4 & PAGE_OFFSET_MASK) && pVM->pgm.s.HCPhysInterPaePML4 < 0xffffffff);
1470
1471	/*
1472	* Initialize the pages, setting up the PML4 and PDPT for repetitive 4GB action.
1473	*/
1474	ASMMemZeroPage(pVM->pgm.s.pInterPD);
1475	ASMMemZeroPage(pVM->pgm.s.apInterPTs[0]);
1476	ASMMemZeroPage(pVM->pgm.s.apInterPTs[1]);
1477
1478	ASMMemZeroPage(pVM->pgm.s.apInterPaePTs[0]);
1479	ASMMemZeroPage(pVM->pgm.s.apInterPaePTs[1]);
1480
1481	ASMMemZeroPage(pVM->pgm.s.pInterPaePDPT);
1482	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.apInterPaePDs); i++)
1483	{
1484	ASMMemZeroPage(pVM->pgm.s.apInterPaePDs[i]);
1485	pVM->pgm.s.pInterPaePDPT->a[i].u = X86_PDPE_P \| PGM_PLXFLAGS_PERMANENT
1486	\| MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[i]);
1487	}
1488
1489	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.pInterPaePDPT64->a); i++)
1490	{
1491	const unsigned iPD = i % RT_ELEMENTS(pVM->pgm.s.apInterPaePDs);
1492	pVM->pgm.s.pInterPaePDPT64->a[i].u = X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_A \| PGM_PLXFLAGS_PERMANENT
1493	\| MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[iPD]);
1494	}
1495
1496	RTHCPHYS HCPhysInterPaePDPT64 = MMPage2Phys(pVM, pVM->pgm.s.pInterPaePDPT64);
1497	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.pInterPaePML4->a); i++)
1498	pVM->pgm.s.pInterPaePML4->a[i].u = X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_A \| PGM_PLXFLAGS_PERMANENT
1499	\| HCPhysInterPaePDPT64;
1500
1501	/*
1502	* Initialize paging workers and mode from current host mode
1503	* and the guest running in real mode.
1504	*/
1505	pVM->pgm.s.enmHostMode = SUPR3GetPagingMode();
1506	switch (pVM->pgm.s.enmHostMode)
1507	{
1508	case SUPPAGINGMODE_32_BIT:
1509	case SUPPAGINGMODE_32_BIT_GLOBAL:
1510	case SUPPAGINGMODE_PAE:
1511	case SUPPAGINGMODE_PAE_GLOBAL:
1512	case SUPPAGINGMODE_PAE_NX:
1513	case SUPPAGINGMODE_PAE_GLOBAL_NX:
1514	break;
1515
1516	case SUPPAGINGMODE_AMD64:
1517	case SUPPAGINGMODE_AMD64_GLOBAL:
1518	case SUPPAGINGMODE_AMD64_NX:
1519	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
1520	#ifndef VBOX_WITH_HYBRID_32BIT_KERNEL
1521	if (ARCH_BITS != 64)
1522	{
1523	AssertMsgFailed(("Host mode %d (64-bit) is not supported by non-64bit builds\n", pVM->pgm.s.enmHostMode));
1524	LogRel(("Host mode %d (64-bit) is not supported by non-64bit builds\n", pVM->pgm.s.enmHostMode));
1525	return VERR_PGM_UNSUPPORTED_HOST_PAGING_MODE;
1526	}
1527	#endif
1528	break;
1529	default:
1530	AssertMsgFailed(("Host mode %d is not supported\n", pVM->pgm.s.enmHostMode));
1531	return VERR_PGM_UNSUPPORTED_HOST_PAGING_MODE;
1532	}
1533	rc = pgmR3ModeDataInit(pVM, false /* don't resolve GC and R0 syms yet */);
1534	if (RT_SUCCESS(rc))
1535	{
1536	LogFlow(("pgmR3InitPaging: returns successfully\n"));
1537	#if HC_ARCH_BITS == 64
1538	LogRel(("Debug: HCPhysInterPD=%RHp HCPhysInterPaePDPT=%RHp HCPhysInterPaePML4=%RHp\n",
1539	pVM->pgm.s.HCPhysInterPD, pVM->pgm.s.HCPhysInterPaePDPT, pVM->pgm.s.HCPhysInterPaePML4));
1540	LogRel(("Debug: apInterPTs={%RHp,%RHp} apInterPaePTs={%RHp,%RHp} apInterPaePDs={%RHp,%RHp,%RHp,%RHp} pInterPaePDPT64=%RHp\n",
1541	MMPage2Phys(pVM, pVM->pgm.s.apInterPTs[0]), MMPage2Phys(pVM, pVM->pgm.s.apInterPTs[1]),
1542	MMPage2Phys(pVM, pVM->pgm.s.apInterPaePTs[0]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePTs[1]),
1543	MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[0]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[1]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[2]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[3]),
1544	MMPage2Phys(pVM, pVM->pgm.s.pInterPaePDPT64)));
1545	#endif
1546
1547	return VINF_SUCCESS;
1548	}
1549
1550	LogFlow(("pgmR3InitPaging: returns %Rrc\n", rc));
1551	return rc;
1552	}
1553
1554
1555	/**
1556	* Init statistics
1557	*/
1558	static void pgmR3InitStats(PVM pVM)
1559	{
1560	PPGM pPGM = &pVM->pgm.s;
1561	int rc;
1562
1563	/* Common - misc variables */
1564	STAM_REL_REG(pVM, &pPGM->cAllPages, STAMTYPE_U32, "/PGM/Page/cAllPages", STAMUNIT_OCCURENCES, "The total number of pages.");
1565	STAM_REL_REG(pVM, &pPGM->cPrivatePages, STAMTYPE_U32, "/PGM/Page/cPrivatePages", STAMUNIT_OCCURENCES, "The number of private pages.");
1566	STAM_REL_REG(pVM, &pPGM->cSharedPages, STAMTYPE_U32, "/PGM/Page/cSharedPages", STAMUNIT_OCCURENCES, "The number of shared pages.");
1567	STAM_REL_REG(pVM, &pPGM->cZeroPages, STAMTYPE_U32, "/PGM/Page/cZeroPages", STAMUNIT_OCCURENCES, "The number of zero backed pages.");
1568	STAM_REL_REG(pVM, &pPGM->cHandyPages, STAMTYPE_U32, "/PGM/Page/cHandyPages", STAMUNIT_OCCURENCES, "The number of handy pages (not included in cAllPages).");
1569	STAM_REL_REG(pVM, &pPGM->cRelocations, STAMTYPE_COUNTER, "/PGM/cRelocations", STAMUNIT_OCCURENCES, "Number of hypervisor relocations.");
1570	STAM_REL_REG(pVM, &pPGM->ChunkR3Map.c, STAMTYPE_U32, "/PGM/ChunkR3Map/c", STAMUNIT_OCCURENCES, "Number of mapped chunks.");
1571	STAM_REL_REG(pVM, &pPGM->ChunkR3Map.cMax, STAMTYPE_U32, "/PGM/ChunkR3Map/cMax", STAMUNIT_OCCURENCES, "Maximum number of mapped chunks.");
1572
1573	#ifdef VBOX_WITH_STATISTICS
1574
1575	# define PGM_REG_COUNTER(a, b, c) \
1576	rc = STAMR3RegisterF(pVM, a, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, c, b); \
1577	AssertRC(rc);
1578
1579	# define PGM_REG_COUNTER_BYTES(a, b, c) \
1580	rc = STAMR3RegisterF(pVM, a, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_BYTES, c, b); \
1581	AssertRC(rc);
1582
1583	# define PGM_REG_PROFILE(a, b, c) \
1584	rc = STAMR3RegisterF(pVM, a, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, c, b); \
1585	AssertRC(rc);
1586
1587	PGM_REG_COUNTER(&pPGM->StatR3DetectedConflicts, "/PGM/R3/DetectedConflicts", "The number of times PGMR3CheckMappingConflicts() detected a conflict.");
1588	PGM_REG_PROFILE(&pPGM->StatR3ResolveConflict, "/PGM/R3/ResolveConflict", "pgmR3SyncPTResolveConflict() profiling (includes the entire relocation).");
1589	PGM_REG_COUNTER(&pPGM->StatR3PhysRead, "/PGM/R3/Phys/Read", "The number of times PGMPhysRead was called.");
1590	PGM_REG_COUNTER_BYTES(&pPGM->StatR3PhysReadBytes, "/PGM/R3/Phys/Read/Bytes", "The number of bytes read by PGMPhysRead.");
1591	PGM_REG_COUNTER(&pPGM->StatR3PhysWrite, "/PGM/R3/Phys/Write", "The number of times PGMPhysWrite was called.");
1592	PGM_REG_COUNTER_BYTES(&pPGM->StatR3PhysWriteBytes, "/PGM/R3/Phys/Write/Bytes", "The number of bytes written by PGMPhysWrite.");
1593	PGM_REG_COUNTER(&pPGM->StatR3PhysSimpleRead, "/PGM/R3/Phys/Simple/Read", "The number of times PGMPhysSimpleReadGCPtr was called.");
1594	PGM_REG_COUNTER_BYTES(&pPGM->StatR3PhysSimpleReadBytes, "/PGM/R3/Phys/Simple/Read/Bytes", "The number of bytes read by PGMPhysSimpleReadGCPtr.");
1595	PGM_REG_COUNTER(&pPGM->StatR3PhysSimpleWrite, "/PGM/R3/Phys/Simple/Write", "The number of times PGMPhysSimpleWriteGCPtr was called.");
1596	PGM_REG_COUNTER_BYTES(&pPGM->StatR3PhysSimpleWriteBytes, "/PGM/R3/Phys/Simple/Write/Bytes", "The number of bytes written by PGMPhysSimpleWriteGCPtr.");
1597
1598	PGM_REG_COUNTER(&pPGM->StatRZChunkR3MapTlbHits, "/PGM/ChunkR3Map/TlbHitsRZ", "TLB hits.");
1599	PGM_REG_COUNTER(&pPGM->StatRZChunkR3MapTlbMisses, "/PGM/ChunkR3Map/TlbMissesRZ", "TLB misses.");
1600	PGM_REG_COUNTER(&pPGM->StatRZPageMapTlbHits, "/PGM/RZ/Page/MapTlbHits", "TLB hits.");
1601	PGM_REG_COUNTER(&pPGM->StatRZPageMapTlbMisses, "/PGM/RZ/Page/MapTlbMisses", "TLB misses.");
1602	PGM_REG_COUNTER(&pPGM->StatR3ChunkR3MapTlbHits, "/PGM/ChunkR3Map/TlbHitsR3", "TLB hits.");
1603	PGM_REG_COUNTER(&pPGM->StatR3ChunkR3MapTlbMisses, "/PGM/ChunkR3Map/TlbMissesR3", "TLB misses.");
1604	PGM_REG_COUNTER(&pPGM->StatR3PageMapTlbHits, "/PGM/R3/Page/MapTlbHits", "TLB hits.");
1605	PGM_REG_COUNTER(&pPGM->StatR3PageMapTlbMisses, "/PGM/R3/Page/MapTlbMisses", "TLB misses.");
1606
1607	PGM_REG_PROFILE(&pPGM->StatRZSyncCR3HandlerVirtualUpdate, "/PGM/RZ/SyncCR3/Handlers/VirtualUpdate", "Profiling of the virtual handler updates.");
1608	PGM_REG_PROFILE(&pPGM->StatRZSyncCR3HandlerVirtualReset, "/PGM/RZ/SyncCR3/Handlers/VirtualReset", "Profiling of the virtual handler resets.");
1609	PGM_REG_PROFILE(&pPGM->StatR3SyncCR3HandlerVirtualUpdate, "/PGM/R3/SyncCR3/Handlers/VirtualUpdate", "Profiling of the virtual handler updates.");
1610	PGM_REG_PROFILE(&pPGM->StatR3SyncCR3HandlerVirtualReset, "/PGM/R3/SyncCR3/Handlers/VirtualReset", "Profiling of the virtual handler resets.");
1611
1612	PGM_REG_COUNTER(&pPGM->StatRZPhysHandlerReset, "/PGM/RZ/PhysHandlerReset", "The number of times PGMHandlerPhysicalReset is called.");
1613	PGM_REG_COUNTER(&pPGM->StatR3PhysHandlerReset, "/PGM/R3/PhysHandlerReset", "The number of times PGMHandlerPhysicalReset is called.");
1614	PGM_REG_PROFILE(&pPGM->StatRZVirtHandlerSearchByPhys, "/PGM/RZ/VirtHandlerSearchByPhys", "Profiling of pgmHandlerVirtualFindByPhysAddr.");
1615	PGM_REG_PROFILE(&pPGM->StatR3VirtHandlerSearchByPhys, "/PGM/R3/VirtHandlerSearchByPhys", "Profiling of pgmHandlerVirtualFindByPhysAddr.");
1616
1617	PGM_REG_COUNTER(&pPGM->StatRZPageReplaceShared, "/PGM/RZ/Page/ReplacedShared", "Times a shared page was replaced.");
1618	PGM_REG_COUNTER(&pPGM->StatRZPageReplaceZero, "/PGM/RZ/Page/ReplacedZero", "Times the zero page was replaced.");
1619	/// @todo PGM_REG_COUNTER(&pPGM->StatRZPageHandyAllocs, "/PGM/RZ/Page/HandyAllocs", "Number of times we've allocated more handy pages.");
1620	PGM_REG_COUNTER(&pPGM->StatR3PageReplaceShared, "/PGM/R3/Page/ReplacedShared", "Times a shared page was replaced.");
1621	PGM_REG_COUNTER(&pPGM->StatR3PageReplaceZero, "/PGM/R3/Page/ReplacedZero", "Times the zero page was replaced.");
1622	/// @todo PGM_REG_COUNTER(&pPGM->StatR3PageHandyAllocs, "/PGM/R3/Page/HandyAllocs", "Number of times we've allocated more handy pages.");
1623
1624	PGM_REG_COUNTER(&pPGM->StatRZPhysRead, "/PGM/RZ/Phys/Read", "The number of times PGMPhysRead was called.");
1625	PGM_REG_COUNTER_BYTES(&pPGM->StatRZPhysReadBytes, "/PGM/RZ/Phys/Read/Bytes", "The number of bytes read by PGMPhysRead.");
1626	PGM_REG_COUNTER(&pPGM->StatRZPhysWrite, "/PGM/RZ/Phys/Write", "The number of times PGMPhysWrite was called.");
1627	PGM_REG_COUNTER_BYTES(&pPGM->StatRZPhysWriteBytes, "/PGM/RZ/Phys/Write/Bytes", "The number of bytes written by PGMPhysWrite.");
1628	PGM_REG_COUNTER(&pPGM->StatRZPhysSimpleRead, "/PGM/RZ/Phys/Simple/Read", "The number of times PGMPhysSimpleReadGCPtr was called.");
1629	PGM_REG_COUNTER_BYTES(&pPGM->StatRZPhysSimpleReadBytes, "/PGM/RZ/Phys/Simple/Read/Bytes", "The number of bytes read by PGMPhysSimpleReadGCPtr.");
1630	PGM_REG_COUNTER(&pPGM->StatRZPhysSimpleWrite, "/PGM/RZ/Phys/Simple/Write", "The number of times PGMPhysSimpleWriteGCPtr was called.");
1631	PGM_REG_COUNTER_BYTES(&pPGM->StatRZPhysSimpleWriteBytes, "/PGM/RZ/Phys/Simple/Write/Bytes", "The number of bytes written by PGMPhysSimpleWriteGCPtr.");
1632
1633	/* GC only: */
1634	PGM_REG_COUNTER(&pPGM->StatRCDynMapCacheHits, "/PGM/RC/DynMapCache/Hits" , "Number of dynamic page mapping cache hits.");
1635	PGM_REG_COUNTER(&pPGM->StatRCDynMapCacheMisses, "/PGM/RC/DynMapCache/Misses" , "Number of dynamic page mapping cache misses.");
1636	PGM_REG_COUNTER(&pPGM->StatRCInvlPgConflict, "/PGM/RC/InvlPgConflict", "Number of times PGMInvalidatePage() detected a mapping conflict.");
1637	PGM_REG_COUNTER(&pPGM->StatRCInvlPgSyncMonCR3, "/PGM/RC/InvlPgSyncMonitorCR3", "Number of times PGMInvalidatePage() ran into PGM_SYNC_MONITOR_CR3.");
1638
1639	PGM_REG_COUNTER(&pPGM->StatRCPhysRead, "/PGM/RC/Phys/Read", "The number of times PGMPhysRead was called.");
1640	PGM_REG_COUNTER_BYTES(&pPGM->StatRCPhysReadBytes, "/PGM/RC/Phys/Read/Bytes", "The number of bytes read by PGMPhysRead.");
1641	PGM_REG_COUNTER(&pPGM->StatRCPhysWrite, "/PGM/RC/Phys/Write", "The number of times PGMPhysWrite was called.");
1642	PGM_REG_COUNTER_BYTES(&pPGM->StatRCPhysWriteBytes, "/PGM/RC/Phys/Write/Bytes", "The number of bytes written by PGMPhysWrite.");
1643	PGM_REG_COUNTER(&pPGM->StatRCPhysSimpleRead, "/PGM/RC/Phys/Simple/Read", "The number of times PGMPhysSimpleReadGCPtr was called.");
1644	PGM_REG_COUNTER_BYTES(&pPGM->StatRCPhysSimpleReadBytes, "/PGM/RC/Phys/Simple/Read/Bytes", "The number of bytes read by PGMPhysSimpleReadGCPtr.");
1645	PGM_REG_COUNTER(&pPGM->StatRCPhysSimpleWrite, "/PGM/RC/Phys/Simple/Write", "The number of times PGMPhysSimpleWriteGCPtr was called.");
1646	PGM_REG_COUNTER_BYTES(&pPGM->StatRCPhysSimpleWriteBytes, "/PGM/RC/Phys/Simple/Write/Bytes", "The number of bytes written by PGMPhysSimpleWriteGCPtr.");
1647
1648	# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
1649	PGM_REG_COUNTER(&pPGM->StatTrackVirgin, "/PGM/Track/Virgin", "The number of first time shadowings");
1650	PGM_REG_COUNTER(&pPGM->StatTrackAliased, "/PGM/Track/Aliased", "The number of times switching to cRef2, i.e. the page is being shadowed by two PTs.");
1651	PGM_REG_COUNTER(&pPGM->StatTrackAliasedMany, "/PGM/Track/AliasedMany", "The number of times we're tracking using cRef2.");
1652	PGM_REG_COUNTER(&pPGM->StatTrackAliasedLots, "/PGM/Track/AliasedLots", "The number of times we're hitting pages which has overflowed cRef2");
1653	PGM_REG_COUNTER(&pPGM->StatTrackOverflows, "/PGM/Track/Overflows", "The number of times the extent list grows too long.");
1654	PGM_REG_PROFILE(&pPGM->StatTrackDeref, "/PGM/Track/Deref", "Profiling of SyncPageWorkerTrackDeref (expensive).");
1655	# endif
1656
1657	# undef PGM_REG_COUNTER
1658	# undef PGM_REG_PROFILE
1659	#endif
1660
1661	/*
1662	* Note! The layout below matches the member layout exactly!
1663	*/
1664
1665	/*
1666	* Common - stats
1667	*/
1668	for (unsigned i=0;i<pVM->cCPUs;i++)
1669	{
1670	PVMCPU pVCpu = &pVM->aCpus[i];
1671	PPGMCPU pPGM = &pVCpu->pgm.s;
1672
1673	#define PGM_REG_COUNTER(a, b, c) \
1674	rc = STAMR3RegisterF(pVM, a, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, c, b, i); \
1675	AssertRC(rc);
1676	#define PGM_REG_PROFILE(a, b, c) \
1677	rc = STAMR3RegisterF(pVM, a, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, c, b, i); \
1678	AssertRC(rc);
1679
1680	PGM_REG_COUNTER(&pPGM->cGuestModeChanges, "/PGM/CPU%d/cGuestModeChanges", "Number of guest mode changes.");
1681
1682	#ifdef VBOX_WITH_STATISTICS
1683	for (unsigned j = 0; j < RT_ELEMENTS(pPGM->StatSyncPtPD); j++)
1684	STAMR3RegisterF(pVM, &pPGM->StatSyncPtPD[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
1685	"The number of SyncPT per PD n.", "/PGM/CPU%d/PDSyncPT/%04X", i, j);
1686	for (unsigned j = 0; j < RT_ELEMENTS(pPGM->StatSyncPagePD); j++)
1687	STAMR3RegisterF(pVM, &pPGM->StatSyncPagePD[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
1688	"The number of SyncPage per PD n.", "/PGM/CPU%d/PDSyncPage/%04X", i, j);
1689
1690	/* R0 only: */
1691	PGM_REG_COUNTER(&pPGM->StatR0DynMapMigrateInvlPg, "/PGM/CPU%d/R0/DynMapMigrateInvlPg", "invlpg count in PGMDynMapMigrateAutoSet.");
1692	PGM_REG_PROFILE(&pPGM->StatR0DynMapGCPageInl, "/PGM/CPU%d/R0/DynMapPageGCPageInl", "Calls to pgmR0DynMapGCPageInlined.");
1693	PGM_REG_COUNTER(&pPGM->StatR0DynMapGCPageInlHits, "/PGM/CPU%d/R0/DynMapPageGCPageInl/Hits", "Hash table lookup hits.");
1694	PGM_REG_COUNTER(&pPGM->StatR0DynMapGCPageInlMisses, "/PGM/CPU%d/R0/DynMapPageGCPageInl/Misses", "Misses that falls back to code common with PGMDynMapHCPage.");
1695	PGM_REG_COUNTER(&pPGM->StatR0DynMapGCPageInlRamHits, "/PGM/CPU%d/R0/DynMapPageGCPageInl/RamHits", "1st ram range hits.");
1696	PGM_REG_COUNTER(&pPGM->StatR0DynMapGCPageInlRamMisses, "/PGM/CPU%d/R0/DynMapPageGCPageInl/RamMisses", "1st ram range misses, takes slow path.");
1697	PGM_REG_PROFILE(&pPGM->StatR0DynMapHCPageInl, "/PGM/CPU%d/R0/DynMapPageHCPageInl", "Calls to pgmR0DynMapHCPageInlined.");
1698	PGM_REG_COUNTER(&pPGM->StatR0DynMapHCPageInlHits, "/PGM/CPU%d/R0/DynMapPageHCPageInl/Hits", "Hash table lookup hits.");
1699	PGM_REG_COUNTER(&pPGM->StatR0DynMapHCPageInlMisses, "/PGM/CPU%d/R0/DynMapPageHCPageInl/Misses", "Misses that falls back to code common with PGMDynMapHCPage.");
1700	PGM_REG_COUNTER(&pPGM->StatR0DynMapPage, "/PGM/CPU%d/R0/DynMapPage", "Calls to pgmR0DynMapPage");
1701	PGM_REG_COUNTER(&pPGM->StatR0DynMapSetOptimize, "/PGM/CPU%d/R0/DynMapPage/SetOptimize", "Calls to pgmDynMapOptimizeAutoSet.");
1702	PGM_REG_COUNTER(&pPGM->StatR0DynMapSetSearchFlushes, "/PGM/CPU%d/R0/DynMapPage/SetSearchFlushes","Set search restorting to subset flushes.");
1703	PGM_REG_COUNTER(&pPGM->StatR0DynMapSetSearchHits, "/PGM/CPU%d/R0/DynMapPage/SetSearchHits", "Set search hits.");
1704	PGM_REG_COUNTER(&pPGM->StatR0DynMapSetSearchMisses, "/PGM/CPU%d/R0/DynMapPage/SetSearchMisses", "Set search misses.");
1705	PGM_REG_PROFILE(&pPGM->StatR0DynMapHCPage, "/PGM/CPU%d/R0/DynMapPage/HCPage", "Calls to PGMDynMapHCPage (ring-0).");
1706	PGM_REG_COUNTER(&pPGM->StatR0DynMapPageHits0, "/PGM/CPU%d/R0/DynMapPage/Hits0", "Hits at iPage+0");
1707	PGM_REG_COUNTER(&pPGM->StatR0DynMapPageHits1, "/PGM/CPU%d/R0/DynMapPage/Hits1", "Hits at iPage+1");
1708	PGM_REG_COUNTER(&pPGM->StatR0DynMapPageHits2, "/PGM/CPU%d/R0/DynMapPage/Hits2", "Hits at iPage+2");
1709	PGM_REG_COUNTER(&pPGM->StatR0DynMapPageInvlPg, "/PGM/CPU%d/R0/DynMapPage/InvlPg", "invlpg count in pgmR0DynMapPageSlow.");
1710	PGM_REG_COUNTER(&pPGM->StatR0DynMapPageSlow, "/PGM/CPU%d/R0/DynMapPage/Slow", "Calls to pgmR0DynMapPageSlow - subtract this from pgmR0DynMapPage to get 1st level hits.");
1711	PGM_REG_COUNTER(&pPGM->StatR0DynMapPageSlowLoopHits, "/PGM/CPU%d/R0/DynMapPage/SlowLoopHits" , "Hits in the loop path.");
1712	PGM_REG_COUNTER(&pPGM->StatR0DynMapPageSlowLoopMisses, "/PGM/CPU%d/R0/DynMapPage/SlowLoopMisses", "Misses in the loop path. NonLoopMisses = Slow - SlowLoopHit - SlowLoopMisses");
1713	//PGM_REG_COUNTER(&pPGM->StatR0DynMapPageSlowLostHits, "/PGM/CPU%d/R0/DynMapPage/SlowLostHits", "Lost hits.");
1714	PGM_REG_COUNTER(&pPGM->StatR0DynMapSubsets, "/PGM/CPU%d/R0/Subsets", "Times PGMDynMapPushAutoSubset was called.");
1715	PGM_REG_COUNTER(&pPGM->StatR0DynMapPopFlushes, "/PGM/CPU%d/R0/SubsetPopFlushes", "Times PGMDynMapPopAutoSubset flushes the subset.");
1716	PGM_REG_COUNTER(&pPGM->aStatR0DynMapSetSize[0], "/PGM/CPU%d/R0/SetSize000..09", "00-09% filled");
1717	PGM_REG_COUNTER(&pPGM->aStatR0DynMapSetSize[1], "/PGM/CPU%d/R0/SetSize010..19", "10-19% filled");
1718	PGM_REG_COUNTER(&pPGM->aStatR0DynMapSetSize[2], "/PGM/CPU%d/R0/SetSize020..29", "20-29% filled");
1719	PGM_REG_COUNTER(&pPGM->aStatR0DynMapSetSize[3], "/PGM/CPU%d/R0/SetSize030..39", "30-39% filled");
1720	PGM_REG_COUNTER(&pPGM->aStatR0DynMapSetSize[4], "/PGM/CPU%d/R0/SetSize040..49", "40-49% filled");
1721	PGM_REG_COUNTER(&pPGM->aStatR0DynMapSetSize[5], "/PGM/CPU%d/R0/SetSize050..59", "50-59% filled");
1722	PGM_REG_COUNTER(&pPGM->aStatR0DynMapSetSize[6], "/PGM/CPU%d/R0/SetSize060..69", "60-69% filled");
1723	PGM_REG_COUNTER(&pPGM->aStatR0DynMapSetSize[7], "/PGM/CPU%d/R0/SetSize070..79", "70-79% filled");
1724	PGM_REG_COUNTER(&pPGM->aStatR0DynMapSetSize[8], "/PGM/CPU%d/R0/SetSize080..89", "80-89% filled");
1725	PGM_REG_COUNTER(&pPGM->aStatR0DynMapSetSize[9], "/PGM/CPU%d/R0/SetSize090..99", "90-99% filled");
1726	PGM_REG_COUNTER(&pPGM->aStatR0DynMapSetSize[10], "/PGM/CPU%d/R0/SetSize100", "100% filled");
1727
1728	/* RZ only: */
1729	PGM_REG_PROFILE(&pPGM->StatRZTrap0e, "/PGM/CPU%d/RZ/Trap0e", "Profiling of the PGMTrap0eHandler() body.");
1730	PGM_REG_PROFILE(&pPGM->StatRZTrap0eTimeCheckPageFault, "/PGM/CPU%d/RZ/Trap0e/Time/CheckPageFault", "Profiling of checking for dirty/access emulation faults.");
1731	PGM_REG_PROFILE(&pPGM->StatRZTrap0eTimeSyncPT, "/PGM/CPU%d/RZ/Trap0e/Time/SyncPT", "Profiling of lazy page table syncing.");
1732	PGM_REG_PROFILE(&pPGM->StatRZTrap0eTimeMapping, "/PGM/CPU%d/RZ/Trap0e/Time/Mapping", "Profiling of checking virtual mappings.");
1733	PGM_REG_PROFILE(&pPGM->StatRZTrap0eTimeOutOfSync, "/PGM/CPU%d/RZ/Trap0e/Time/OutOfSync", "Profiling of out of sync page handling.");
1734	PGM_REG_PROFILE(&pPGM->StatRZTrap0eTimeHandlers, "/PGM/CPU%d/RZ/Trap0e/Time/Handlers", "Profiling of checking handlers.");
1735	PGM_REG_PROFILE(&pPGM->StatRZTrap0eTime2CSAM, "/PGM/CPU%d/RZ/Trap0e/Time2/CSAM", "Profiling of the Trap0eHandler body when the cause is CSAM.");
1736	PGM_REG_PROFILE(&pPGM->StatRZTrap0eTime2DirtyAndAccessed, "/PGM/CPU%d/RZ/Trap0e/Time2/DirtyAndAccessedBits", "Profiling of the Trap0eHandler body when the cause is dirty and/or accessed bit emulation.");
1737	PGM_REG_PROFILE(&pPGM->StatRZTrap0eTime2GuestTrap, "/PGM/CPU%d/RZ/Trap0e/Time2/GuestTrap", "Profiling of the Trap0eHandler body when the cause is a guest trap.");
1738	PGM_REG_PROFILE(&pPGM->StatRZTrap0eTime2HndPhys, "/PGM/CPU%d/RZ/Trap0e/Time2/HandlerPhysical", "Profiling of the Trap0eHandler body when the cause is a physical handler.");
1739	PGM_REG_PROFILE(&pPGM->StatRZTrap0eTime2HndVirt, "/PGM/CPU%d/RZ/Trap0e/Time2/HandlerVirtual", "Profiling of the Trap0eHandler body when the cause is a virtual handler.");
1740	PGM_REG_PROFILE(&pPGM->StatRZTrap0eTime2HndUnhandled, "/PGM/CPU%d/RZ/Trap0e/Time2/HandlerUnhandled", "Profiling of the Trap0eHandler body when the cause is access outside the monitored areas of a monitored page.");
1741	PGM_REG_PROFILE(&pPGM->StatRZTrap0eTime2Misc, "/PGM/CPU%d/RZ/Trap0e/Time2/Misc", "Profiling of the Trap0eHandler body when the cause is not known.");
1742	PGM_REG_PROFILE(&pPGM->StatRZTrap0eTime2OutOfSync, "/PGM/CPU%d/RZ/Trap0e/Time2/OutOfSync", "Profiling of the Trap0eHandler body when the cause is an out-of-sync page.");
1743	PGM_REG_PROFILE(&pPGM->StatRZTrap0eTime2OutOfSyncHndPhys, "/PGM/CPU%d/RZ/Trap0e/Time2/OutOfSyncHndPhys", "Profiling of the Trap0eHandler body when the cause is an out-of-sync physical handler page.");
1744	PGM_REG_PROFILE(&pPGM->StatRZTrap0eTime2OutOfSyncHndVirt, "/PGM/CPU%d/RZ/Trap0e/Time2/OutOfSyncHndVirt", "Profiling of the Trap0eHandler body when the cause is an out-of-sync virtual handler page.");
1745	PGM_REG_PROFILE(&pPGM->StatRZTrap0eTime2OutOfSyncHndObs, "/PGM/CPU%d/RZ/Trap0e/Time2/OutOfSyncObsHnd", "Profiling of the Trap0eHandler body when the cause is an obsolete handler page.");
1746	PGM_REG_PROFILE(&pPGM->StatRZTrap0eTime2SyncPT, "/PGM/CPU%d/RZ/Trap0e/Time2/SyncPT", "Profiling of the Trap0eHandler body when the cause is lazy syncing of a PT.");
1747	PGM_REG_COUNTER(&pPGM->StatRZTrap0eConflicts, "/PGM/CPU%d/RZ/Trap0e/Conflicts", "The number of times #PF was caused by an undetected conflict.");
1748	PGM_REG_COUNTER(&pPGM->StatRZTrap0eHandlersMapping, "/PGM/CPU%d/RZ/Trap0e/Handlers/Mapping", "Number of traps due to access handlers in mappings.");
1749	PGM_REG_COUNTER(&pPGM->StatRZTrap0eHandlersOutOfSync, "/PGM/CPU%d/RZ/Trap0e/Handlers/OutOfSync", "Number of traps due to out-of-sync handled pages.");
1750	PGM_REG_COUNTER(&pPGM->StatRZTrap0eHandlersPhysical, "/PGM/CPU%d/RZ/Trap0e/Handlers/Physical", "Number of traps due to physical access handlers.");
1751	PGM_REG_COUNTER(&pPGM->StatRZTrap0eHandlersVirtual, "/PGM/CPU%d/RZ/Trap0e/Handlers/Virtual", "Number of traps due to virtual access handlers.");
1752	PGM_REG_COUNTER(&pPGM->StatRZTrap0eHandlersVirtualByPhys, "/PGM/CPU%d/RZ/Trap0e/Handlers/VirtualByPhys", "Number of traps due to virtual access handlers by physical address.");
1753	PGM_REG_COUNTER(&pPGM->StatRZTrap0eHandlersVirtualUnmarked,"/PGM/CPU%d/RZ/Trap0e/Handlers/VirtualUnmarked","Number of traps due to virtual access handlers by virtual address (without proper physical flags).");
1754	PGM_REG_COUNTER(&pPGM->StatRZTrap0eHandlersUnhandled, "/PGM/CPU%d/RZ/Trap0e/Handlers/Unhandled", "Number of traps due to access outside range of monitored page(s).");
1755	PGM_REG_COUNTER(&pPGM->StatRZTrap0eHandlersInvalid, "/PGM/CPU%d/RZ/Trap0e/Handlers/Invalid", "Number of traps due to access to invalid physical memory.");
1756	PGM_REG_COUNTER(&pPGM->StatRZTrap0eUSNotPresentRead, "/PGM/CPU%d/RZ/Trap0e/Err/User/NPRead", "Number of user mode not present read page faults.");
1757	PGM_REG_COUNTER(&pPGM->StatRZTrap0eUSNotPresentWrite, "/PGM/CPU%d/RZ/Trap0e/Err/User/NPWrite", "Number of user mode not present write page faults.");
1758	PGM_REG_COUNTER(&pPGM->StatRZTrap0eUSWrite, "/PGM/CPU%d/RZ/Trap0e/Err/User/Write", "Number of user mode write page faults.");
1759	PGM_REG_COUNTER(&pPGM->StatRZTrap0eUSReserved, "/PGM/CPU%d/RZ/Trap0e/Err/User/Reserved", "Number of user mode reserved bit page faults.");
1760	PGM_REG_COUNTER(&pPGM->StatRZTrap0eUSNXE, "/PGM/CPU%d/RZ/Trap0e/Err/User/NXE", "Number of user mode NXE page faults.");
1761	PGM_REG_COUNTER(&pPGM->StatRZTrap0eUSRead, "/PGM/CPU%d/RZ/Trap0e/Err/User/Read", "Number of user mode read page faults.");
1762	PGM_REG_COUNTER(&pPGM->StatRZTrap0eSVNotPresentRead, "/PGM/CPU%d/RZ/Trap0e/Err/Supervisor/NPRead", "Number of supervisor mode not present read page faults.");
1763	PGM_REG_COUNTER(&pPGM->StatRZTrap0eSVNotPresentWrite, "/PGM/CPU%d/RZ/Trap0e/Err/Supervisor/NPWrite", "Number of supervisor mode not present write page faults.");
1764	PGM_REG_COUNTER(&pPGM->StatRZTrap0eSVWrite, "/PGM/CPU%d/RZ/Trap0e/Err/Supervisor/Write", "Number of supervisor mode write page faults.");
1765	PGM_REG_COUNTER(&pPGM->StatRZTrap0eSVReserved, "/PGM/CPU%d/RZ/Trap0e/Err/Supervisor/Reserved", "Number of supervisor mode reserved bit page faults.");
1766	PGM_REG_COUNTER(&pPGM->StatRZTrap0eSNXE, "/PGM/CPU%d/RZ/Trap0e/Err/Supervisor/NXE", "Number of supervisor mode NXE page faults.");
1767	PGM_REG_COUNTER(&pPGM->StatRZTrap0eGuestPF, "/PGM/CPU%d/RZ/Trap0e/GuestPF", "Number of real guest page faults.");
1768	PGM_REG_COUNTER(&pPGM->StatRZTrap0eGuestPFUnh, "/PGM/CPU%d/RZ/Trap0e/GuestPF/Unhandled", "Number of real guest page faults from the 'unhandled' case.");
1769	PGM_REG_COUNTER(&pPGM->StatRZTrap0eGuestPFMapping, "/PGM/CPU%d/RZ/Trap0e/GuestPF/InMapping", "Number of real guest page faults in a mapping.");
1770	PGM_REG_COUNTER(&pPGM->StatRZTrap0eWPEmulInRZ, "/PGM/CPU%d/RZ/Trap0e/WP/InRZ", "Number of guest page faults due to X86_CR0_WP emulation.");
1771	PGM_REG_COUNTER(&pPGM->StatRZTrap0eWPEmulToR3, "/PGM/CPU%d/RZ/Trap0e/WP/ToR3", "Number of guest page faults due to X86_CR0_WP emulation (forward to R3 for emulation).");
1772	for (unsigned j = 0; j < RT_ELEMENTS(pPGM->StatRZTrap0ePD); j++)
1773	STAMR3RegisterF(pVM, &pPGM->StatRZTrap0ePD[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
1774	"The number of traps in page directory n.", "/PGM/CPU%d/RZ/Trap0e/PD/%04X", i, j);
1775
1776	PGM_REG_COUNTER(&pPGM->StatRZGuestCR3WriteHandled, "/PGM/CPU%d/RZ/CR3WriteHandled", "The number of times the Guest CR3 change was successfully handled.");
1777	PGM_REG_COUNTER(&pPGM->StatRZGuestCR3WriteUnhandled, "/PGM/CPU%d/RZ/CR3WriteUnhandled", "The number of times the Guest CR3 change was passed back to the recompiler.");
1778	PGM_REG_COUNTER(&pPGM->StatRZGuestCR3WriteConflict, "/PGM/CPU%d/RZ/CR3WriteConflict", "The number of times the Guest CR3 monitoring detected a conflict.");
1779	PGM_REG_COUNTER(&pPGM->StatRZGuestROMWriteHandled, "/PGM/CPU%d/RZ/ROMWriteHandled", "The number of times the Guest ROM change was successfully handled.");
1780	PGM_REG_COUNTER(&pPGM->StatRZGuestROMWriteUnhandled, "/PGM/CPU%d/RZ/ROMWriteUnhandled", "The number of times the Guest ROM change was passed back to the recompiler.");
1781
1782	/* HC only: */
1783
1784	/* RZ & R3: */
1785	PGM_REG_PROFILE(&pPGM->StatRZSyncCR3, "/PGM/CPU%d/RZ/SyncCR3", "Profiling of the PGMSyncCR3() body.");
1786	PGM_REG_PROFILE(&pPGM->StatRZSyncCR3Handlers, "/PGM/CPU%d/RZ/SyncCR3/Handlers", "Profiling of the PGMSyncCR3() update handler section.");
1787	PGM_REG_COUNTER(&pPGM->StatRZSyncCR3Global, "/PGM/CPU%d/RZ/SyncCR3/Global", "The number of global CR3 syncs.");
1788	PGM_REG_COUNTER(&pPGM->StatRZSyncCR3NotGlobal, "/PGM/CPU%d/RZ/SyncCR3/NotGlobal", "The number of non-global CR3 syncs.");
1789	PGM_REG_COUNTER(&pPGM->StatRZSyncCR3DstCacheHit, "/PGM/CPU%d/RZ/SyncCR3/DstChacheHit", "The number of times we got some kind of a cache hit.");
1790	PGM_REG_COUNTER(&pPGM->StatRZSyncCR3DstFreed, "/PGM/CPU%d/RZ/SyncCR3/DstFreed", "The number of times we've had to free a shadow entry.");
1791	PGM_REG_COUNTER(&pPGM->StatRZSyncCR3DstFreedSrcNP, "/PGM/CPU%d/RZ/SyncCR3/DstFreedSrcNP", "The number of times we've had to free a shadow entry for which the source entry was not present.");
1792	PGM_REG_COUNTER(&pPGM->StatRZSyncCR3DstNotPresent, "/PGM/CPU%d/RZ/SyncCR3/DstNotPresent", "The number of times we've encountered a not present shadow entry for a present guest entry.");
1793	PGM_REG_COUNTER(&pPGM->StatRZSyncCR3DstSkippedGlobalPD, "/PGM/CPU%d/RZ/SyncCR3/DstSkippedGlobalPD", "The number of times a global page directory wasn't flushed.");
1794	PGM_REG_COUNTER(&pPGM->StatRZSyncCR3DstSkippedGlobalPT, "/PGM/CPU%d/RZ/SyncCR3/DstSkippedGlobalPT", "The number of times a page table with only global entries wasn't flushed.");
1795	PGM_REG_PROFILE(&pPGM->StatRZSyncPT, "/PGM/CPU%d/RZ/SyncPT", "Profiling of the pfnSyncPT() body.");
1796	PGM_REG_COUNTER(&pPGM->StatRZSyncPTFailed, "/PGM/CPU%d/RZ/SyncPT/Failed", "The number of times pfnSyncPT() failed.");
1797	PGM_REG_COUNTER(&pPGM->StatRZSyncPT4K, "/PGM/CPU%d/RZ/SyncPT/4K", "Nr of 4K PT syncs");
1798	PGM_REG_COUNTER(&pPGM->StatRZSyncPT4M, "/PGM/CPU%d/RZ/SyncPT/4M", "Nr of 4M PT syncs");
1799	PGM_REG_COUNTER(&pPGM->StatRZSyncPagePDNAs, "/PGM/CPU%d/RZ/SyncPagePDNAs", "The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit.");
1800	PGM_REG_COUNTER(&pPGM->StatRZSyncPagePDOutOfSync, "/PGM/CPU%d/RZ/SyncPagePDOutOfSync", "The number of time we've encountered an out-of-sync PD in SyncPage.");
1801	PGM_REG_COUNTER(&pPGM->StatRZAccessedPage, "/PGM/CPU%d/RZ/AccessedPage", "The number of pages marked not present for accessed bit emulation.");
1802	PGM_REG_PROFILE(&pPGM->StatRZDirtyBitTracking, "/PGM/CPU%d/RZ/DirtyPage", "Profiling the dirty bit tracking in CheckPageFault().");
1803	PGM_REG_COUNTER(&pPGM->StatRZDirtyPage, "/PGM/CPU%d/RZ/DirtyPage/Mark", "The number of pages marked read-only for dirty bit tracking.");
1804	PGM_REG_COUNTER(&pPGM->StatRZDirtyPageBig, "/PGM/CPU%d/RZ/DirtyPage/MarkBig", "The number of 4MB pages marked read-only for dirty bit tracking.");
1805	PGM_REG_COUNTER(&pPGM->StatRZDirtyPageSkipped, "/PGM/CPU%d/RZ/DirtyPage/Skipped", "The number of pages already dirty or readonly.");
1806	PGM_REG_COUNTER(&pPGM->StatRZDirtyPageTrap, "/PGM/CPU%d/RZ/DirtyPage/Trap", "The number of traps generated for dirty bit tracking.");
1807	PGM_REG_COUNTER(&pPGM->StatRZDirtyPageStale, "/PGM/CPU%d/RZ/DirtyPage/Stale", "The number of traps generated for dirty bit tracking (stale tlb entries).");
1808	PGM_REG_COUNTER(&pPGM->StatRZDirtiedPage, "/PGM/CPU%d/RZ/DirtyPage/SetDirty", "The number of pages marked dirty because of write accesses.");
1809	PGM_REG_COUNTER(&pPGM->StatRZDirtyTrackRealPF, "/PGM/CPU%d/RZ/DirtyPage/RealPF", "The number of real pages faults during dirty bit tracking.");
1810	PGM_REG_COUNTER(&pPGM->StatRZPageAlreadyDirty, "/PGM/CPU%d/RZ/DirtyPage/AlreadySet", "The number of pages already marked dirty because of write accesses.");
1811	PGM_REG_PROFILE(&pPGM->StatRZInvalidatePage, "/PGM/CPU%d/RZ/InvalidatePage", "PGMInvalidatePage() profiling.");
1812	PGM_REG_COUNTER(&pPGM->StatRZInvalidatePage4KBPages, "/PGM/CPU%d/RZ/InvalidatePage/4KBPages", "The number of times PGMInvalidatePage() was called for a 4KB page.");
1813	PGM_REG_COUNTER(&pPGM->StatRZInvalidatePage4MBPages, "/PGM/CPU%d/RZ/InvalidatePage/4MBPages", "The number of times PGMInvalidatePage() was called for a 4MB page.");
1814	PGM_REG_COUNTER(&pPGM->StatRZInvalidatePage4MBPagesSkip, "/PGM/CPU%d/RZ/InvalidatePage/4MBPagesSkip","The number of times PGMInvalidatePage() skipped a 4MB page.");
1815	PGM_REG_COUNTER(&pPGM->StatRZInvalidatePagePDMappings, "/PGM/CPU%d/RZ/InvalidatePage/PDMappings", "The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict).");
1816	PGM_REG_COUNTER(&pPGM->StatRZInvalidatePagePDNAs, "/PGM/CPU%d/RZ/InvalidatePage/PDNAs", "The number of times PGMInvalidatePage() was called for a not accessed page directory.");
1817	PGM_REG_COUNTER(&pPGM->StatRZInvalidatePagePDNPs, "/PGM/CPU%d/RZ/InvalidatePage/PDNPs", "The number of times PGMInvalidatePage() was called for a not present page directory.");
1818	PGM_REG_COUNTER(&pPGM->StatRZInvalidatePagePDOutOfSync, "/PGM/CPU%d/RZ/InvalidatePage/PDOutOfSync", "The number of times PGMInvalidatePage() was called for an out of sync page directory.");
1819	PGM_REG_COUNTER(&pPGM->StatRZInvalidatePageSkipped, "/PGM/CPU%d/RZ/InvalidatePage/Skipped", "The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3.");
1820	PGM_REG_COUNTER(&pPGM->StatRZPageOutOfSyncSupervisor, "/PGM/CPU%d/RZ/OutOfSync/SuperVisor", "Number of traps due to pages out of sync and times VerifyAccessSyncPage calls SyncPage.");
1821	PGM_REG_COUNTER(&pPGM->StatRZPageOutOfSyncUser, "/PGM/CPU%d/RZ/OutOfSync/User", "Number of traps due to pages out of sync and times VerifyAccessSyncPage calls SyncPage.");
1822	PGM_REG_PROFILE(&pPGM->StatRZPrefetch, "/PGM/CPU%d/RZ/Prefetch", "PGMPrefetchPage profiling.");
1823	PGM_REG_PROFILE(&pPGM->StatRZFlushTLB, "/PGM/CPU%d/RZ/FlushTLB", "Profiling of the PGMFlushTLB() body.");
1824	PGM_REG_COUNTER(&pPGM->StatRZFlushTLBNewCR3, "/PGM/CPU%d/RZ/FlushTLB/NewCR3", "The number of times PGMFlushTLB was called with a new CR3, non-global. (switch)");
1825	PGM_REG_COUNTER(&pPGM->StatRZFlushTLBNewCR3Global, "/PGM/CPU%d/RZ/FlushTLB/NewCR3Global", "The number of times PGMFlushTLB was called with a new CR3, global. (switch)");
1826	PGM_REG_COUNTER(&pPGM->StatRZFlushTLBSameCR3, "/PGM/CPU%d/RZ/FlushTLB/SameCR3", "The number of times PGMFlushTLB was called with the same CR3, non-global. (flush)");
1827	PGM_REG_COUNTER(&pPGM->StatRZFlushTLBSameCR3Global, "/PGM/CPU%d/RZ/FlushTLB/SameCR3Global", "The number of times PGMFlushTLB was called with the same CR3, global. (flush)");
1828	PGM_REG_PROFILE(&pPGM->StatRZGstModifyPage, "/PGM/CPU%d/RZ/GstModifyPage", "Profiling of the PGMGstModifyPage() body.");
1829
1830	PGM_REG_PROFILE(&pPGM->StatR3SyncCR3, "/PGM/CPU%d/R3/SyncCR3", "Profiling of the PGMSyncCR3() body.");
1831	PGM_REG_PROFILE(&pPGM->StatR3SyncCR3Handlers, "/PGM/CPU%d/R3/SyncCR3/Handlers", "Profiling of the PGMSyncCR3() update handler section.");
1832	PGM_REG_COUNTER(&pPGM->StatR3SyncCR3Global, "/PGM/CPU%d/R3/SyncCR3/Global", "The number of global CR3 syncs.");
1833	PGM_REG_COUNTER(&pPGM->StatR3SyncCR3NotGlobal, "/PGM/CPU%d/R3/SyncCR3/NotGlobal", "The number of non-global CR3 syncs.");
1834	PGM_REG_COUNTER(&pPGM->StatR3SyncCR3DstCacheHit, "/PGM/CPU%d/R3/SyncCR3/DstChacheHit", "The number of times we got some kind of a cache hit.");
1835	PGM_REG_COUNTER(&pPGM->StatR3SyncCR3DstFreed, "/PGM/CPU%d/R3/SyncCR3/DstFreed", "The number of times we've had to free a shadow entry.");
1836	PGM_REG_COUNTER(&pPGM->StatR3SyncCR3DstFreedSrcNP, "/PGM/CPU%d/R3/SyncCR3/DstFreedSrcNP", "The number of times we've had to free a shadow entry for which the source entry was not present.");
1837	PGM_REG_COUNTER(&pPGM->StatR3SyncCR3DstNotPresent, "/PGM/CPU%d/R3/SyncCR3/DstNotPresent", "The number of times we've encountered a not present shadow entry for a present guest entry.");
1838	PGM_REG_COUNTER(&pPGM->StatR3SyncCR3DstSkippedGlobalPD, "/PGM/CPU%d/R3/SyncCR3/DstSkippedGlobalPD", "The number of times a global page directory wasn't flushed.");
1839	PGM_REG_COUNTER(&pPGM->StatR3SyncCR3DstSkippedGlobalPT, "/PGM/CPU%d/R3/SyncCR3/DstSkippedGlobalPT", "The number of times a page table with only global entries wasn't flushed.");
1840	PGM_REG_PROFILE(&pPGM->StatR3SyncPT, "/PGM/CPU%d/R3/SyncPT", "Profiling of the pfnSyncPT() body.");
1841	PGM_REG_COUNTER(&pPGM->StatR3SyncPTFailed, "/PGM/CPU%d/R3/SyncPT/Failed", "The number of times pfnSyncPT() failed.");
1842	PGM_REG_COUNTER(&pPGM->StatR3SyncPT4K, "/PGM/CPU%d/R3/SyncPT/4K", "Nr of 4K PT syncs");
1843	PGM_REG_COUNTER(&pPGM->StatR3SyncPT4M, "/PGM/CPU%d/R3/SyncPT/4M", "Nr of 4M PT syncs");
1844	PGM_REG_COUNTER(&pPGM->StatR3SyncPagePDNAs, "/PGM/CPU%d/R3/SyncPagePDNAs", "The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit.");
1845	PGM_REG_COUNTER(&pPGM->StatR3SyncPagePDOutOfSync, "/PGM/CPU%d/R3/SyncPagePDOutOfSync", "The number of time we've encountered an out-of-sync PD in SyncPage.");
1846	PGM_REG_COUNTER(&pPGM->StatR3AccessedPage, "/PGM/CPU%d/R3/AccessedPage", "The number of pages marked not present for accessed bit emulation.");
1847	PGM_REG_PROFILE(&pPGM->StatR3DirtyBitTracking, "/PGM/CPU%d/R3/DirtyPage", "Profiling the dirty bit tracking in CheckPageFault().");
1848	PGM_REG_COUNTER(&pPGM->StatR3DirtyPage, "/PGM/CPU%d/R3/DirtyPage/Mark", "The number of pages marked read-only for dirty bit tracking.");
1849	PGM_REG_COUNTER(&pPGM->StatR3DirtyPageBig, "/PGM/CPU%d/R3/DirtyPage/MarkBig", "The number of 4MB pages marked read-only for dirty bit tracking.");
1850	PGM_REG_COUNTER(&pPGM->StatR3DirtyPageSkipped, "/PGM/CPU%d/R3/DirtyPage/Skipped", "The number of pages already dirty or readonly.");
1851	PGM_REG_COUNTER(&pPGM->StatR3DirtyPageTrap, "/PGM/CPU%d/R3/DirtyPage/Trap", "The number of traps generated for dirty bit tracking.");
1852	PGM_REG_COUNTER(&pPGM->StatR3DirtiedPage, "/PGM/CPU%d/R3/DirtyPage/SetDirty", "The number of pages marked dirty because of write accesses.");
1853	PGM_REG_COUNTER(&pPGM->StatR3DirtyTrackRealPF, "/PGM/CPU%d/R3/DirtyPage/RealPF", "The number of real pages faults during dirty bit tracking.");
1854	PGM_REG_COUNTER(&pPGM->StatR3PageAlreadyDirty, "/PGM/CPU%d/R3/DirtyPage/AlreadySet", "The number of pages already marked dirty because of write accesses.");
1855	PGM_REG_PROFILE(&pPGM->StatR3InvalidatePage, "/PGM/CPU%d/R3/InvalidatePage", "PGMInvalidatePage() profiling.");
1856	PGM_REG_COUNTER(&pPGM->StatR3InvalidatePage4KBPages, "/PGM/CPU%d/R3/InvalidatePage/4KBPages", "The number of times PGMInvalidatePage() was called for a 4KB page.");
1857	PGM_REG_COUNTER(&pPGM->StatR3InvalidatePage4MBPages, "/PGM/CPU%d/R3/InvalidatePage/4MBPages", "The number of times PGMInvalidatePage() was called for a 4MB page.");
1858	PGM_REG_COUNTER(&pPGM->StatR3InvalidatePage4MBPagesSkip, "/PGM/CPU%d/R3/InvalidatePage/4MBPagesSkip","The number of times PGMInvalidatePage() skipped a 4MB page.");
1859	PGM_REG_COUNTER(&pPGM->StatR3InvalidatePagePDMappings, "/PGM/CPU%d/R3/InvalidatePage/PDMappings", "The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict).");
1860	PGM_REG_COUNTER(&pPGM->StatR3InvalidatePagePDNAs, "/PGM/CPU%d/R3/InvalidatePage/PDNAs", "The number of times PGMInvalidatePage() was called for a not accessed page directory.");
1861	PGM_REG_COUNTER(&pPGM->StatR3InvalidatePagePDNPs, "/PGM/CPU%d/R3/InvalidatePage/PDNPs", "The number of times PGMInvalidatePage() was called for a not present page directory.");
1862	PGM_REG_COUNTER(&pPGM->StatR3InvalidatePagePDOutOfSync, "/PGM/CPU%d/R3/InvalidatePage/PDOutOfSync", "The number of times PGMInvalidatePage() was called for an out of sync page directory.");
1863	PGM_REG_COUNTER(&pPGM->StatR3InvalidatePageSkipped, "/PGM/CPU%d/R3/InvalidatePage/Skipped", "The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3.");
1864	PGM_REG_COUNTER(&pPGM->StatR3PageOutOfSyncSupervisor, "/PGM/CPU%d/R3/OutOfSync/SuperVisor", "Number of traps due to pages out of sync and times VerifyAccessSyncPage calls SyncPage.");
1865	PGM_REG_COUNTER(&pPGM->StatR3PageOutOfSyncUser, "/PGM/CPU%d/R3/OutOfSync/User", "Number of traps due to pages out of sync and times VerifyAccessSyncPage calls SyncPage.");
1866	PGM_REG_PROFILE(&pPGM->StatR3Prefetch, "/PGM/CPU%d/R3/Prefetch", "PGMPrefetchPage profiling.");
1867	PGM_REG_PROFILE(&pPGM->StatR3FlushTLB, "/PGM/CPU%d/R3/FlushTLB", "Profiling of the PGMFlushTLB() body.");
1868	PGM_REG_COUNTER(&pPGM->StatR3FlushTLBNewCR3, "/PGM/CPU%d/R3/FlushTLB/NewCR3", "The number of times PGMFlushTLB was called with a new CR3, non-global. (switch)");
1869	PGM_REG_COUNTER(&pPGM->StatR3FlushTLBNewCR3Global, "/PGM/CPU%d/R3/FlushTLB/NewCR3Global", "The number of times PGMFlushTLB was called with a new CR3, global. (switch)");
1870	PGM_REG_COUNTER(&pPGM->StatR3FlushTLBSameCR3, "/PGM/CPU%d/R3/FlushTLB/SameCR3", "The number of times PGMFlushTLB was called with the same CR3, non-global. (flush)");
1871	PGM_REG_COUNTER(&pPGM->StatR3FlushTLBSameCR3Global, "/PGM/CPU%d/R3/FlushTLB/SameCR3Global", "The number of times PGMFlushTLB was called with the same CR3, global. (flush)");
1872	PGM_REG_PROFILE(&pPGM->StatR3GstModifyPage, "/PGM/CPU%d/R3/GstModifyPage", "Profiling of the PGMGstModifyPage() body.");
1873	#endif /* VBOX_WITH_STATISTICS */
1874
1875	#undef PGM_REG_PROFILE
1876	#undef PGM_REG_COUNTER
1877
1878	}
1879	}
1880
1881
1882	/**
1883	* Init the PGM bits that rely on VMMR0 and MM to be fully initialized.
1884	*
1885	* The dynamic mapping area will also be allocated and initialized at this
1886	* time. We could allocate it during PGMR3Init of course, but the mapping
1887	* wouldn't be allocated at that time preventing us from setting up the
1888	* page table entries with the dummy page.
1889	*
1890	* @returns VBox status code.
1891	* @param pVM VM handle.
1892	*/
1893	VMMR3DECL(int) PGMR3InitDynMap(PVM pVM)
1894	{
1895	RTGCPTR GCPtr;
1896	int rc;
1897
1898	/*
1899	* Reserve space for the dynamic mappings.
1900	*/
1901	rc = MMR3HyperReserve(pVM, MM_HYPER_DYNAMIC_SIZE, "Dynamic mapping", &GCPtr);
1902	if (RT_SUCCESS(rc))
1903	pVM->pgm.s.pbDynPageMapBaseGC = GCPtr;
1904
1905	if ( RT_SUCCESS(rc)
1906	&& (pVM->pgm.s.pbDynPageMapBaseGC >> X86_PD_PAE_SHIFT) != ((pVM->pgm.s.pbDynPageMapBaseGC + MM_HYPER_DYNAMIC_SIZE - 1) >> X86_PD_PAE_SHIFT))
1907	{
1908	rc = MMR3HyperReserve(pVM, MM_HYPER_DYNAMIC_SIZE, "Dynamic mapping not crossing", &GCPtr);
1909	if (RT_SUCCESS(rc))
1910	pVM->pgm.s.pbDynPageMapBaseGC = GCPtr;
1911	}
1912	if (RT_SUCCESS(rc))
1913	{
1914	AssertRelease((pVM->pgm.s.pbDynPageMapBaseGC >> X86_PD_PAE_SHIFT) == ((pVM->pgm.s.pbDynPageMapBaseGC + MM_HYPER_DYNAMIC_SIZE - 1) >> X86_PD_PAE_SHIFT));
1915	MMR3HyperReserve(pVM, PAGE_SIZE, "fence", NULL);
1916	}
1917	return rc;
1918	}
1919
1920
1921	/**
1922	* Ring-3 init finalizing.
1923	*
1924	* @returns VBox status code.
1925	* @param pVM The VM handle.
1926	*/
1927	VMMR3DECL(int) PGMR3InitFinalize(PVM pVM)
1928	{
1929	int rc;
1930
1931	/*
1932	* Reserve space for the dynamic mappings.
1933	* Initialize the dynamic mapping pages with dummy pages to simply the cache.
1934	*/
1935	/* get the pointer to the page table entries. */
1936	PPGMMAPPING pMapping = pgmGetMapping(pVM, pVM->pgm.s.pbDynPageMapBaseGC);
1937	AssertRelease(pMapping);
1938	const uintptr_t off = pVM->pgm.s.pbDynPageMapBaseGC - pMapping->GCPtr;
1939	const unsigned iPT = off >> X86_PD_SHIFT;
1940	const unsigned iPG = (off >> X86_PT_SHIFT) & X86_PT_MASK;
1941	pVM->pgm.s.paDynPageMap32BitPTEsGC = pMapping->aPTs[iPT].pPTRC + iPG * sizeof(pMapping->aPTs[0].pPTR3->a[0]);
1942	pVM->pgm.s.paDynPageMapPaePTEsGC = pMapping->aPTs[iPT].paPaePTsRC + iPG * sizeof(pMapping->aPTs[0].paPaePTsR3->a[0]);
1943
1944	/* init cache */
1945	RTHCPHYS HCPhysDummy = MMR3PageDummyHCPhys(pVM);
1946	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.aHCPhysDynPageMapCache); i++)
1947	pVM->pgm.s.aHCPhysDynPageMapCache[i] = HCPhysDummy;
1948
1949	for (unsigned i = 0; i < MM_HYPER_DYNAMIC_SIZE; i += PAGE_SIZE)
1950	{
1951	rc = PGMMap(pVM, pVM->pgm.s.pbDynPageMapBaseGC + i, HCPhysDummy, PAGE_SIZE, 0);
1952	AssertRCReturn(rc, rc);
1953	}
1954
1955	/*
1956	* Note that AMD uses all the 8 reserved bits for the address (so 40 bits in total);
1957	* Intel only goes up to 36 bits, so we stick to 36 as well.
1958	*/
1959	/** @todo How to test for the 40 bits support? Long mode seems to be the test criterium. */
1960	uint32_t u32Dummy, u32Features;
1961	CPUMGetGuestCpuId(VMMGetCpu(pVM), 1, &u32Dummy, &u32Dummy, &u32Dummy, &u32Features);
1962
1963	if (u32Features & X86_CPUID_FEATURE_EDX_PSE36)
1964	pVM->pgm.s.GCPhys4MBPSEMask = RT_BIT_64(36) - 1;
1965	else
1966	pVM->pgm.s.GCPhys4MBPSEMask = RT_BIT_64(32) - 1;
1967
1968	/*
1969	* Allocate memory if we're supposed to do that.
1970	*/
1971	if (pVM->pgm.s.fRamPreAlloc)
1972	rc = pgmR3PhysRamPreAllocate(pVM);
1973
1974	LogRel(("PGMR3InitFinalize: 4 MB PSE mask %RGp\n", pVM->pgm.s.GCPhys4MBPSEMask));
1975	return rc;
1976	}
1977
1978
1979	/**
1980	* Applies relocations to data and code managed by this component.
1981	*
1982	* This function will be called at init and whenever the VMM need to relocate it
1983	* self inside the GC.
1984	*
1985	* @param pVM The VM.
1986	* @param offDelta Relocation delta relative to old location.
1987	*/
1988	VMMR3DECL(void) PGMR3Relocate(PVM pVM, RTGCINTPTR offDelta)
1989	{
1990	LogFlow(("PGMR3Relocate %RGv to %RGv\n", pVM->pgm.s.GCPtrCR3Mapping, pVM->pgm.s.GCPtrCR3Mapping + offDelta));
1991
1992	/*
1993	* Paging stuff.
1994	*/
1995	pVM->pgm.s.GCPtrCR3Mapping += offDelta;
1996
1997	pgmR3ModeDataInit(pVM, true /* resolve GC/R0 symbols */);
1998
1999	/* Shadow, guest and both mode switch & relocation for each VCPU. */
2000	for (unsigned i=0;i<pVM->cCPUs;i++)
2001	{
2002	PVMCPU pVCpu = &pVM->aCpus[i];
2003
2004	pgmR3ModeDataSwitch(pVM, pVCpu, pVCpu->pgm.s.enmShadowMode, pVCpu->pgm.s.enmGuestMode);
2005
2006	PGM_SHW_PFN(Relocate, pVCpu)(pVCpu, offDelta);
2007	PGM_GST_PFN(Relocate, pVCpu)(pVCpu, offDelta);
2008	PGM_BTH_PFN(Relocate, pVCpu)(pVCpu, offDelta);
2009	}
2010
2011	/*
2012	* Trees.
2013	*/
2014	pVM->pgm.s.pTreesRC = MMHyperR3ToRC(pVM, pVM->pgm.s.pTreesR3);
2015
2016	/*
2017	* Ram ranges.
2018	*/
2019	if (pVM->pgm.s.pRamRangesR3)
2020	{
2021	/* Update the pSelfRC pointers and relink them. */
2022	for (PPGMRAMRANGE pCur = pVM->pgm.s.pRamRangesR3; pCur; pCur = pCur->pNextR3)
2023	if (!(pCur->fFlags & PGM_RAM_RANGE_FLAGS_FLOATING))
2024	pCur->pSelfRC = MMHyperCCToRC(pVM, pCur);
2025	pgmR3PhysRelinkRamRanges(pVM);
2026	}
2027
2028	/*
2029	* Update the two page directories with all page table mappings.
2030	* (One or more of them have changed, that's why we're here.)
2031	*/
2032	pVM->pgm.s.pMappingsRC = MMHyperR3ToRC(pVM, pVM->pgm.s.pMappingsR3);
2033	for (PPGMMAPPING pCur = pVM->pgm.s.pMappingsR3; pCur->pNextR3; pCur = pCur->pNextR3)
2034	pCur->pNextRC = MMHyperR3ToRC(pVM, pCur->pNextR3);
2035
2036	/* Relocate GC addresses of Page Tables. */
2037	for (PPGMMAPPING pCur = pVM->pgm.s.pMappingsR3; pCur; pCur = pCur->pNextR3)
2038	{
2039	for (RTHCUINT i = 0; i < pCur->cPTs; i++)
2040	{
2041	pCur->aPTs[i].pPTRC = MMHyperR3ToRC(pVM, pCur->aPTs[i].pPTR3);
2042	pCur->aPTs[i].paPaePTsRC = MMHyperR3ToRC(pVM, pCur->aPTs[i].paPaePTsR3);
2043	}
2044	}
2045
2046	/*
2047	* Dynamic page mapping area.
2048	*/
2049	pVM->pgm.s.paDynPageMap32BitPTEsGC += offDelta;
2050	pVM->pgm.s.paDynPageMapPaePTEsGC += offDelta;
2051	pVM->pgm.s.pbDynPageMapBaseGC += offDelta;
2052
2053	/*
2054	* The Zero page.
2055	*/
2056	pVM->pgm.s.pvZeroPgR0 = MMHyperR3ToR0(pVM, pVM->pgm.s.pvZeroPgR3);
2057	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
2058	AssertRelease(pVM->pgm.s.pvZeroPgR0 != NIL_RTR0PTR \|\| !VMMIsHwVirtExtForced(pVM));
2059	#else
2060	AssertRelease(pVM->pgm.s.pvZeroPgR0 != NIL_RTR0PTR);
2061	#endif
2062
2063	/*
2064	* Physical and virtual handlers.
2065	*/
2066	RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysHandlers, true, pgmR3RelocatePhysHandler, &offDelta);
2067	RTAvlroGCPtrDoWithAll(&pVM->pgm.s.pTreesR3->VirtHandlers, true, pgmR3RelocateVirtHandler, &offDelta);
2068	RTAvlroGCPtrDoWithAll(&pVM->pgm.s.pTreesR3->HyperVirtHandlers, true, pgmR3RelocateHyperVirtHandler, &offDelta);
2069
2070	/*
2071	* The page pool.
2072	*/
2073	pgmR3PoolRelocate(pVM);
2074	}
2075
2076
2077	/**
2078	* Callback function for relocating a physical access handler.
2079	*
2080	* @returns 0 (continue enum)
2081	* @param pNode Pointer to a PGMPHYSHANDLER node.
2082	* @param pvUser Pointer to the offDelta. This is a pointer to the delta since we're
2083	* not certain the delta will fit in a void pointer for all possible configs.
2084	*/
2085	static DECLCALLBACK(int) pgmR3RelocatePhysHandler(PAVLROGCPHYSNODECORE pNode, void *pvUser)
2086	{
2087	PPGMPHYSHANDLER pHandler = (PPGMPHYSHANDLER)pNode;
2088	RTGCINTPTR offDelta = *(PRTGCINTPTR)pvUser;
2089	if (pHandler->pfnHandlerRC)
2090	pHandler->pfnHandlerRC += offDelta;
2091	if (pHandler->pvUserRC >= 0x10000)
2092	pHandler->pvUserRC += offDelta;
2093	return 0;
2094	}
2095
2096
2097	/**
2098	* Callback function for relocating a virtual access handler.
2099	*
2100	* @returns 0 (continue enum)
2101	* @param pNode Pointer to a PGMVIRTHANDLER node.
2102	* @param pvUser Pointer to the offDelta. This is a pointer to the delta since we're
2103	* not certain the delta will fit in a void pointer for all possible configs.
2104	*/
2105	static DECLCALLBACK(int) pgmR3RelocateVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser)
2106	{
2107	PPGMVIRTHANDLER pHandler = (PPGMVIRTHANDLER)pNode;
2108	RTGCINTPTR offDelta = *(PRTGCINTPTR)pvUser;
2109	Assert( pHandler->enmType == PGMVIRTHANDLERTYPE_ALL
2110	\|\| pHandler->enmType == PGMVIRTHANDLERTYPE_WRITE);
2111	Assert(pHandler->pfnHandlerRC);
2112	pHandler->pfnHandlerRC += offDelta;
2113	return 0;
2114	}
2115
2116
2117	/**
2118	* Callback function for relocating a virtual access handler for the hypervisor mapping.
2119	*
2120	* @returns 0 (continue enum)
2121	* @param pNode Pointer to a PGMVIRTHANDLER node.
2122	* @param pvUser Pointer to the offDelta. This is a pointer to the delta since we're
2123	* not certain the delta will fit in a void pointer for all possible configs.
2124	*/
2125	static DECLCALLBACK(int) pgmR3RelocateHyperVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser)
2126	{
2127	PPGMVIRTHANDLER pHandler = (PPGMVIRTHANDLER)pNode;
2128	RTGCINTPTR offDelta = *(PRTGCINTPTR)pvUser;
2129	Assert(pHandler->enmType == PGMVIRTHANDLERTYPE_HYPERVISOR);
2130	Assert(pHandler->pfnHandlerRC);
2131	pHandler->pfnHandlerRC += offDelta;
2132	return 0;
2133	}
2134
2135
2136	/**
2137	* The VM is being reset.
2138	*
2139	* For the PGM component this means that any PD write monitors
2140	* needs to be removed.
2141	*
2142	* @param pVM VM handle.
2143	*/
2144	VMMR3DECL(void) PGMR3Reset(PVM pVM)
2145	{
2146	int rc;
2147
2148	LogFlow(("PGMR3Reset:\n"));
2149	VM_ASSERT_EMT(pVM);
2150
2151	pgmLock(pVM);
2152
2153	/*
2154	* Unfix any fixed mappings and disable CR3 monitoring.
2155	*/
2156	pVM->pgm.s.fMappingsFixed = false;
2157	pVM->pgm.s.GCPtrMappingFixed = 0;
2158	pVM->pgm.s.cbMappingFixed = 0;
2159
2160	/* Exit the guest paging mode before the pgm pool gets reset.
2161	* Important to clean up the amd64 case.
2162	*/
2163	for (unsigned i=0;i<pVM->cCPUs;i++)
2164	{
2165	PVMCPU pVCpu = &pVM->aCpus[i];
2166
2167	rc = PGM_GST_PFN(Exit, pVCpu)(pVCpu);
2168	AssertRC(rc);
2169	}
2170
2171	#ifdef DEBUG
2172	DBGFR3InfoLog(pVM, "mappings", NULL);
2173	DBGFR3InfoLog(pVM, "handlers", "all nostat");
2174	#endif
2175
2176	/*
2177	* Switch mode back to real mode. (before resetting the pgm pool!)
2178	*/
2179	for (unsigned i=0;i<pVM->cCPUs;i++)
2180	{
2181	PVMCPU pVCpu = &pVM->aCpus[i];
2182
2183	rc = PGMR3ChangeMode(pVM, pVCpu, PGMMODE_REAL);
2184	AssertRC(rc);
2185
2186	STAM_REL_COUNTER_RESET(&pVCpu->pgm.s.cGuestModeChanges);
2187	}
2188
2189	/*
2190	* Reset the shadow page pool.
2191	*/
2192	pgmR3PoolReset(pVM);
2193
2194	for (unsigned i=0;i<pVM->cCPUs;i++)
2195	{
2196	PVMCPU pVCpu = &pVM->aCpus[i];
2197
2198	/*
2199	* Re-init other members.
2200	*/
2201	pVCpu->pgm.s.fA20Enabled = true;
2202
2203	/*
2204	* Clear the FFs PGM owns.
2205	*/
2206	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
2207	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL);
2208	}
2209
2210	/*
2211	* Reset (zero) RAM pages.
2212	*/
2213	rc = pgmR3PhysRamReset(pVM);
2214	if (RT_SUCCESS(rc))
2215	{
2216	/*
2217	* Reset (zero) shadow ROM pages.
2218	*/
2219	rc = pgmR3PhysRomReset(pVM);
2220	}
2221
2222	pgmUnlock(pVM);
2223	//return rc;
2224	AssertReleaseRC(rc);
2225	}
2226
2227
2228	#ifdef VBOX_STRICT
2229	/**
2230	* VM state change callback for clearing fNoMorePhysWrites after
2231	* a snapshot has been created.
2232	*/
2233	static DECLCALLBACK(void) pgmR3ResetNoMorePhysWritesFlag(PVM pVM, VMSTATE enmState, VMSTATE enmOldState, void *pvUser)
2234	{
2235	if (enmState == VMSTATE_RUNNING)
2236	pVM->pgm.s.fNoMorePhysWrites = false;
2237	}
2238	#endif
2239
2240
2241	/**
2242	* Terminates the PGM.
2243	*
2244	* @returns VBox status code.
2245	* @param pVM Pointer to VM structure.
2246	*/
2247	VMMR3DECL(int) PGMR3Term(PVM pVM)
2248	{
2249	PGMDeregisterStringFormatTypes();
2250	return PDMR3CritSectDelete(&pVM->pgm.s.CritSect);
2251	}
2252
2253
2254	/**
2255	* Terminates the per-VCPU PGM.
2256	*
2257	* Termination means cleaning up and freeing all resources,
2258	* the VM it self is at this point powered off or suspended.
2259	*
2260	* @returns VBox status code.
2261	* @param pVM The VM to operate on.
2262	*/
2263	VMMR3DECL(int) PGMR3TermCPU(PVM pVM)
2264	{
2265	return 0;
2266	}
2267
2268
2269	/**
2270	* Find the ROM tracking structure for the given page.
2271	*
2272	* @returns Pointer to the ROM page structure. NULL if the caller didn't check
2273	* that it's a ROM page.
2274	* @param pVM The VM handle.
2275	* @param GCPhys The address of the ROM page.
2276	*/
2277	static PPGMROMPAGE pgmR3GetRomPage(PVM pVM, RTGCPHYS GCPhys)
2278	{
2279	for (PPGMROMRANGE pRomRange = pVM->pgm.s.CTX_SUFF(pRomRanges);
2280	pRomRange;
2281	pRomRange = pRomRange->CTX_SUFF(pNext))
2282	{
2283	RTGCPHYS off = GCPhys - pRomRange->GCPhys;
2284	if (GCPhys - pRomRange->GCPhys < pRomRange->cb)
2285	return &pRomRange->aPages[off >> PAGE_SHIFT];
2286	}
2287	return NULL;
2288	}
2289
2290
2291	/**
2292	* Save zero indicator + bits for the specified page.
2293	*
2294	* @returns VBox status code, errors are logged/asserted before returning.
2295	* @param pVM The VM handle.
2296	* @param pSSH The saved state handle.
2297	* @param pPage The page to save.
2298	* @param GCPhys The address of the page.
2299	* @param pRam The ram range (for error logging).
2300	*/
2301	static int pgmR3SavePage(PVM pVM, PSSMHANDLE pSSM, PPGMPAGE pPage, RTGCPHYS GCPhys, PPGMRAMRANGE pRam)
2302	{
2303	int rc;
2304	if (PGM_PAGE_IS_ZERO(pPage))
2305	rc = SSMR3PutU8(pSSM, 0);
2306	else
2307	{
2308	void const *pvPage;
2309	rc = pgmPhysGCPhys2CCPtrInternalReadOnly(pVM, pPage, GCPhys, &pvPage);
2310	AssertLogRelMsgRCReturn(rc, ("pPage=%R[pgmpage] GCPhys=%#x %s\n", pPage, GCPhys, pRam->pszDesc), rc);
2311
2312	SSMR3PutU8(pSSM, 1);
2313	rc = SSMR3PutMem(pSSM, pvPage, PAGE_SIZE);
2314	}
2315	return rc;
2316	}
2317
2318
2319	/**
2320	* Save a shadowed ROM page.
2321	*
2322	* Format: Type, protection, and two pages with zero indicators.
2323	*
2324	* @returns VBox status code, errors are logged/asserted before returning.
2325	* @param pVM The VM handle.
2326	* @param pSSH The saved state handle.
2327	* @param pPage The page to save.
2328	* @param GCPhys The address of the page.
2329	* @param pRam The ram range (for error logging).
2330	*/
2331	static int pgmR3SaveShadowedRomPage(PVM pVM, PSSMHANDLE pSSM, PPGMPAGE pPage, RTGCPHYS GCPhys, PPGMRAMRANGE pRam)
2332	{
2333	/* Need to save both pages and the current state. */
2334	PPGMROMPAGE pRomPage = pgmR3GetRomPage(pVM, GCPhys);
2335	AssertLogRelMsgReturn(pRomPage, ("GCPhys=%RGp %s\n", GCPhys, pRam->pszDesc), VERR_INTERNAL_ERROR);
2336
2337	SSMR3PutU8(pSSM, PGMPAGETYPE_ROM_SHADOW);
2338	SSMR3PutU8(pSSM, pRomPage->enmProt);
2339
2340	int rc = pgmR3SavePage(pVM, pSSM, pPage, GCPhys, pRam);
2341	if (RT_SUCCESS(rc))
2342	{
2343	PPGMPAGE pPagePassive = PGMROMPROT_IS_ROM(pRomPage->enmProt) ? &pRomPage->Shadow : &pRomPage->Virgin;
2344	rc = pgmR3SavePage(pVM, pSSM, pPagePassive, GCPhys, pRam);
2345	}
2346	return rc;
2347	}
2348
2349	/** PGM fields to save/load. */
2350	static const SSMFIELD s_aPGMFields[] =
2351	{
2352	SSMFIELD_ENTRY( PGM, fMappingsFixed),
2353	SSMFIELD_ENTRY_GCPTR( PGM, GCPtrMappingFixed),
2354	SSMFIELD_ENTRY( PGM, cbMappingFixed),
2355	SSMFIELD_ENTRY_TERM()
2356	};
2357
2358	static const SSMFIELD s_aPGMCpuFields[] =
2359	{
2360	SSMFIELD_ENTRY( PGMCPU, fA20Enabled),
2361	SSMFIELD_ENTRY_GCPHYS( PGMCPU, GCPhysA20Mask),
2362	SSMFIELD_ENTRY( PGMCPU, enmGuestMode),
2363	SSMFIELD_ENTRY_TERM()
2364	};
2365
2366	/* For loading old saved states. (pre-smp) */
2367	typedef struct
2368	{
2369	/** If set no conflict checks are required. (boolean) */
2370	bool fMappingsFixed;
2371	/** Size of fixed mapping */
2372	uint32_t cbMappingFixed;
2373	/** Base address (GC) of fixed mapping */
2374	RTGCPTR GCPtrMappingFixed;
2375	/** A20 gate mask.
2376	* Our current approach to A20 emulation is to let REM do it and don't bother
2377	* anywhere else. The interesting Guests will be operating with it enabled anyway.
2378	* But whould need arrise, we'll subject physical addresses to this mask. */
2379	RTGCPHYS GCPhysA20Mask;
2380	/** A20 gate state - boolean! */
2381	bool fA20Enabled;
2382	/** The guest paging mode. */
2383	PGMMODE enmGuestMode;
2384	} PGMOLD;
2385
2386	static const SSMFIELD s_aPGMFields_Old[] =
2387	{
2388	SSMFIELD_ENTRY( PGMOLD, fMappingsFixed),
2389	SSMFIELD_ENTRY_GCPTR( PGMOLD, GCPtrMappingFixed),
2390	SSMFIELD_ENTRY( PGMOLD, cbMappingFixed),
2391	SSMFIELD_ENTRY( PGMOLD, fA20Enabled),
2392	SSMFIELD_ENTRY_GCPHYS( PGMOLD, GCPhysA20Mask),
2393	SSMFIELD_ENTRY( PGMOLD, enmGuestMode),
2394	SSMFIELD_ENTRY_TERM()
2395	};
2396
2397
2398	/**
2399	* Execute state save operation.
2400	*
2401	* @returns VBox status code.
2402	* @param pVM VM Handle.
2403	* @param pSSM SSM operation handle.
2404	*/
2405	static DECLCALLBACK(int) pgmR3Save(PVM pVM, PSSMHANDLE pSSM)
2406	{
2407	int rc;
2408	unsigned i;
2409	PPGM pPGM = &pVM->pgm.s;
2410
2411	/*
2412	* Lock PGM and set the no-more-writes indicator.
2413	*/
2414	pgmLock(pVM);
2415	pVM->pgm.s.fNoMorePhysWrites = true;
2416
2417	/*
2418	* Save basic data (required / unaffected by relocation).
2419	*/
2420	SSMR3PutStruct(pSSM, pPGM, &s_aPGMFields[0]);
2421
2422	for (i=0;i<pVM->cCPUs;i++)
2423	{
2424	PVMCPU pVCpu = &pVM->aCpus[i];
2425
2426	SSMR3PutStruct(pSSM, &pVCpu->pgm.s, &s_aPGMCpuFields[0]);
2427	}
2428
2429	/*
2430	* The guest mappings.
2431	*/
2432	i = 0;
2433	for (PPGMMAPPING pMapping = pPGM->pMappingsR3; pMapping; pMapping = pMapping->pNextR3, i++)
2434	{
2435	SSMR3PutU32( pSSM, i);
2436	SSMR3PutStrZ( pSSM, pMapping->pszDesc); /* This is the best unique id we have... */
2437	SSMR3PutGCPtr( pSSM, pMapping->GCPtr);
2438	SSMR3PutGCUIntPtr(pSSM, pMapping->cPTs);
2439	}
2440	rc = SSMR3PutU32(pSSM, ~0); /* terminator. */
2441
2442	/*
2443	* Ram ranges and the memory they describe.
2444	*/
2445	i = 0;
2446	for (PPGMRAMRANGE pRam = pPGM->pRamRangesR3; pRam; pRam = pRam->pNextR3, i++)
2447	{
2448	/*
2449	* Save the ram range details.
2450	*/
2451	SSMR3PutU32(pSSM, i);
2452	SSMR3PutGCPhys(pSSM, pRam->GCPhys);
2453	SSMR3PutGCPhys(pSSM, pRam->GCPhysLast);
2454	SSMR3PutGCPhys(pSSM, pRam->cb);
2455	SSMR3PutU8(pSSM, !!pRam->pvR3); /* Boolean indicating memory or not. */
2456	SSMR3PutStrZ(pSSM, pRam->pszDesc); /* This is the best unique id we have... */
2457
2458	/*
2459	* Iterate the pages, only two special case.
2460	*/
2461	uint32_t const cPages = pRam->cb >> PAGE_SHIFT;
2462	for (uint32_t iPage = 0; iPage < cPages; iPage++)
2463	{
2464	RTGCPHYS GCPhysPage = pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT);
2465	PPGMPAGE pPage = &pRam->aPages[iPage];
2466	uint8_t uType = PGM_PAGE_GET_TYPE(pPage);
2467
2468	if (uType == PGMPAGETYPE_ROM_SHADOW)
2469	rc = pgmR3SaveShadowedRomPage(pVM, pSSM, pPage, GCPhysPage, pRam);
2470	else if (uType == PGMPAGETYPE_MMIO2_ALIAS_MMIO)
2471	{
2472	/* MMIO2 alias -> MMIO; the device will just have to deal with this. */
2473	SSMR3PutU8(pSSM, PGMPAGETYPE_MMIO);
2474	rc = SSMR3PutU8(pSSM, 0 /* ZERO */);
2475	}
2476	else
2477	{
2478	SSMR3PutU8(pSSM, uType);
2479	rc = pgmR3SavePage(pVM, pSSM, pPage, GCPhysPage, pRam);
2480	}
2481	if (RT_FAILURE(rc))
2482	break;
2483	}
2484	if (RT_FAILURE(rc))
2485	break;
2486	}
2487
2488	pgmUnlock(pVM);
2489	return SSMR3PutU32(pSSM, ~0); /* terminator. */
2490	}
2491
2492
2493	/**
2494	* Load an ignored page.
2495	*
2496	* @returns VBox status code.
2497	* @param pSSM The saved state handle.
2498	*/
2499	static int pgmR3LoadPageToDevNull(PSSMHANDLE pSSM)
2500	{
2501	uint8_t abPage[PAGE_SIZE];
2502	return SSMR3GetMem(pSSM, &abPage[0], sizeof(abPage));
2503	}
2504
2505
2506	/**
2507	* Loads a page without any bits in the saved state, i.e. making sure it's
2508	* really zero.
2509	*
2510	* @returns VBox status code.
2511	* @param pVM The VM handle.
2512	* @param uType The page type or PGMPAGETYPE_INVALID (old saved
2513	* state).
2514	* @param pPage The guest page tracking structure.
2515	* @param GCPhys The page address.
2516	* @param pRam The ram range (logging).
2517	*/
2518	static int pgmR3LoadPageZero(PVM pVM, uint8_t uType, PPGMPAGE pPage, RTGCPHYS GCPhys, PPGMRAMRANGE pRam)
2519	{
2520	if ( PGM_PAGE_GET_TYPE(pPage) != uType
2521	&& uType != PGMPAGETYPE_INVALID)
2522	return VERR_SSM_UNEXPECTED_DATA;
2523
2524	/* I think this should be sufficient. */
2525	if (!PGM_PAGE_IS_ZERO(pPage))
2526	return VERR_SSM_UNEXPECTED_DATA;
2527
2528	NOREF(pVM);
2529	NOREF(GCPhys);
2530	NOREF(pRam);
2531	return VINF_SUCCESS;
2532	}
2533
2534
2535	/**
2536	* Loads a page from the saved state.
2537	*
2538	* @returns VBox status code.
2539	* @param pVM The VM handle.
2540	* @param pSSM The SSM handle.
2541	* @param uType The page type or PGMPAGETYEP_INVALID (old saved
2542	* state).
2543	* @param pPage The guest page tracking structure.
2544	* @param GCPhys The page address.
2545	* @param pRam The ram range (logging).
2546	*/
2547	static int pgmR3LoadPageBits(PVM pVM, PSSMHANDLE pSSM, uint8_t uType, PPGMPAGE pPage, RTGCPHYS GCPhys, PPGMRAMRANGE pRam)
2548	{
2549	int rc;
2550
2551	/*
2552	* Match up the type, dealing with MMIO2 aliases (dropped).
2553	*/
2554	AssertLogRelMsgReturn( PGM_PAGE_GET_TYPE(pPage) == uType
2555	\|\| uType == PGMPAGETYPE_INVALID,
2556	("pPage=%R[pgmpage] GCPhys=%#x %s\n", pPage, GCPhys, pRam->pszDesc),
2557	VERR_SSM_UNEXPECTED_DATA);
2558
2559	/*
2560	* Load the page.
2561	*/
2562	void *pvPage;
2563	rc = pgmPhysGCPhys2CCPtrInternal(pVM, pPage, GCPhys, &pvPage);
2564	if (RT_SUCCESS(rc))
2565	rc = SSMR3GetMem(pSSM, pvPage, PAGE_SIZE);
2566
2567	return rc;
2568	}
2569
2570
2571	/**
2572	* Loads a page (counter part to pgmR3SavePage).
2573	*
2574	* @returns VBox status code, fully bitched errors.
2575	* @param pVM The VM handle.
2576	* @param pSSM The SSM handle.
2577	* @param uType The page type.
2578	* @param pPage The page.
2579	* @param GCPhys The page address.
2580	* @param pRam The RAM range (for error messages).
2581	*/
2582	static int pgmR3LoadPage(PVM pVM, PSSMHANDLE pSSM, uint8_t uType, PPGMPAGE pPage, RTGCPHYS GCPhys, PPGMRAMRANGE pRam)
2583	{
2584	uint8_t uState;
2585	int rc = SSMR3GetU8(pSSM, &uState);
2586	AssertLogRelMsgRCReturn(rc, ("pPage=%R[pgmpage] GCPhys=%#x %s rc=%Rrc\n", pPage, GCPhys, pRam->pszDesc, rc), rc);
2587	if (uState == 0 /* zero */)
2588	rc = pgmR3LoadPageZero(pVM, uType, pPage, GCPhys, pRam);
2589	else if (uState == 1)
2590	rc = pgmR3LoadPageBits(pVM, pSSM, uType, pPage, GCPhys, pRam);
2591	else
2592	rc = VERR_INTERNAL_ERROR;
2593	AssertLogRelMsgRCReturn(rc, ("pPage=%R[pgmpage] uState=%d uType=%d GCPhys=%RGp %s rc=%Rrc\n",
2594	pPage, uState, uType, GCPhys, pRam->pszDesc, rc),
2595	rc);
2596	return VINF_SUCCESS;
2597	}
2598
2599
2600	/**
2601	* Loads a shadowed ROM page.
2602	*
2603	* @returns VBox status code, errors are fully bitched.
2604	* @param pVM The VM handle.
2605	* @param pSSM The saved state handle.
2606	* @param pPage The page.
2607	* @param GCPhys The page address.
2608	* @param pRam The RAM range (for error messages).
2609	*/
2610	static int pgmR3LoadShadowedRomPage(PVM pVM, PSSMHANDLE pSSM, PPGMPAGE pPage, RTGCPHYS GCPhys, PPGMRAMRANGE pRam)
2611	{
2612	/*
2613	* Load and set the protection first, then load the two pages, the first
2614	* one is the active the other is the passive.
2615	*/
2616	PPGMROMPAGE pRomPage = pgmR3GetRomPage(pVM, GCPhys);
2617	AssertLogRelMsgReturn(pRomPage, ("GCPhys=%RGp %s\n", GCPhys, pRam->pszDesc), VERR_INTERNAL_ERROR);
2618
2619	uint8_t uProt;
2620	int rc = SSMR3GetU8(pSSM, &uProt);
2621	AssertLogRelMsgRCReturn(rc, ("pPage=%R[pgmpage] GCPhys=%#x %s\n", pPage, GCPhys, pRam->pszDesc), rc);
2622	PGMROMPROT enmProt = (PGMROMPROT)uProt;
2623	AssertLogRelMsgReturn( enmProt >= PGMROMPROT_INVALID
2624	&& enmProt < PGMROMPROT_END,
2625	("enmProt=%d pPage=%R[pgmpage] GCPhys=%#x %s\n", enmProt, pPage, GCPhys, pRam->pszDesc),
2626	VERR_SSM_UNEXPECTED_DATA);
2627
2628	if (pRomPage->enmProt != enmProt)
2629	{
2630	rc = PGMR3PhysRomProtect(pVM, GCPhys, PAGE_SIZE, enmProt);
2631	AssertLogRelRCReturn(rc, rc);
2632	AssertLogRelReturn(pRomPage->enmProt == enmProt, VERR_INTERNAL_ERROR);
2633	}
2634
2635	PPGMPAGE pPageActive = PGMROMPROT_IS_ROM(enmProt) ? &pRomPage->Virgin : &pRomPage->Shadow;
2636	PPGMPAGE pPagePassive = PGMROMPROT_IS_ROM(enmProt) ? &pRomPage->Shadow : &pRomPage->Virgin;
2637	uint8_t u8ActiveType = PGMROMPROT_IS_ROM(enmProt) ? PGMPAGETYPE_ROM : PGMPAGETYPE_ROM_SHADOW;
2638	uint8_t u8PassiveType= PGMROMPROT_IS_ROM(enmProt) ? PGMPAGETYPE_ROM_SHADOW : PGMPAGETYPE_ROM;
2639
2640	rc = pgmR3LoadPage(pVM, pSSM, u8ActiveType, pPage, GCPhys, pRam);
2641	if (RT_SUCCESS(rc))
2642	{
2643	pPageActive = pPage;
2644	rc = pgmR3LoadPage(pVM, pSSM, u8PassiveType, pPagePassive, GCPhys, pRam);
2645	}
2646	return rc;
2647	}
2648
2649
2650	/**
2651	* Worker for pgmR3Load.
2652	*
2653	* @returns VBox status code.
2654	*
2655	* @param pVM The VM handle.
2656	* @param pSSM The SSM handle.
2657	* @param u32Version The saved state version.
2658	*/
2659	static int pgmR3LoadLocked(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version)
2660	{
2661	PPGM pPGM = &pVM->pgm.s;
2662	int rc;
2663	uint32_t u32Sep;
2664
2665	/*
2666	* Load basic data (required / unaffected by relocation).
2667	*/
2668	if (u32Version >= PGM_SAVED_STATE_VERSION)
2669	{
2670	rc = SSMR3GetStruct(pSSM, pPGM, &s_aPGMFields[0]);
2671	AssertLogRelRCReturn(rc, rc);
2672
2673	for (VMCPUID i = 0; i < pVM->cCPUs; i++)
2674	{
2675	rc = SSMR3GetStruct(pSSM, &pVM->aCpus[i].pgm.s, &s_aPGMCpuFields[0]);
2676	AssertLogRelRCReturn(rc, rc);
2677	}
2678	}
2679	else if (u32Version >= PGM_SAVED_STATE_VERSION_RR_DESC)
2680	{
2681	AssertRelease(pVM->cCPUs == 1);
2682
2683	PGMOLD pgmOld;
2684	rc = SSMR3GetStruct(pSSM, &pgmOld, &s_aPGMFields_Old[0]);
2685	AssertLogRelRCReturn(rc, rc);
2686
2687	pPGM->fMappingsFixed = pgmOld.fMappingsFixed;
2688	pPGM->GCPtrMappingFixed = pgmOld.GCPtrMappingFixed;
2689	pPGM->cbMappingFixed = pgmOld.cbMappingFixed;
2690
2691	pVM->aCpus[0].pgm.s.fA20Enabled = pgmOld.fA20Enabled;
2692	pVM->aCpus[0].pgm.s.GCPhysA20Mask = pgmOld.GCPhysA20Mask;
2693	pVM->aCpus[0].pgm.s.enmGuestMode = pgmOld.enmGuestMode;
2694	}
2695	else
2696	{
2697	AssertRelease(pVM->cCPUs == 1);
2698
2699	SSMR3GetBool(pSSM, &pPGM->fMappingsFixed);
2700	SSMR3GetGCPtr(pSSM, &pPGM->GCPtrMappingFixed);
2701	SSMR3GetU32(pSSM, &pPGM->cbMappingFixed);
2702
2703	uint32_t cbRamSizeIgnored;
2704	rc = SSMR3GetU32(pSSM, &cbRamSizeIgnored);
2705	if (RT_FAILURE(rc))
2706	return rc;
2707	SSMR3GetGCPhys(pSSM, &pVM->aCpus[0].pgm.s.GCPhysA20Mask);
2708
2709	uint32_t u32 = 0;
2710	SSMR3GetUInt(pSSM, &u32);
2711	pVM->aCpus[0].pgm.s.fA20Enabled = !!u32;
2712	SSMR3GetUInt(pSSM, &pVM->aCpus[0].pgm.s.fSyncFlags);
2713	RTUINT uGuestMode;
2714	SSMR3GetUInt(pSSM, &uGuestMode);
2715	pVM->aCpus[0].pgm.s.enmGuestMode = (PGMMODE)uGuestMode;
2716
2717	/* check separator. */
2718	SSMR3GetU32(pSSM, &u32Sep);
2719	if (RT_FAILURE(rc))
2720	return rc;
2721	if (u32Sep != (uint32_t)~0)
2722	{
2723	AssertMsgFailed(("u32Sep=%#x (first)\n", u32Sep));
2724	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2725	}
2726	}
2727
2728	/*
2729	* The guest mappings.
2730	*/
2731	uint32_t i = 0;
2732	for (;; i++)
2733	{
2734	/* Check the seqence number / separator. */
2735	rc = SSMR3GetU32(pSSM, &u32Sep);
2736	if (RT_FAILURE(rc))
2737	return rc;
2738	if (u32Sep == ~0U)
2739	break;
2740	if (u32Sep != i)
2741	{
2742	AssertMsgFailed(("u32Sep=%#x (last)\n", u32Sep));
2743	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2744	}
2745
2746	/* get the mapping details. */
2747	char szDesc[256];
2748	szDesc[0] = '\0';
2749	rc = SSMR3GetStrZ(pSSM, szDesc, sizeof(szDesc));
2750	if (RT_FAILURE(rc))
2751	return rc;
2752	RTGCPTR GCPtr;
2753	SSMR3GetGCPtr(pSSM, &GCPtr);
2754	RTGCPTR cPTs;
2755	rc = SSMR3GetGCUIntPtr(pSSM, &cPTs);
2756	if (RT_FAILURE(rc))
2757	return rc;
2758
2759	/* find matching range. */
2760	PPGMMAPPING pMapping;
2761	for (pMapping = pPGM->pMappingsR3; pMapping; pMapping = pMapping->pNextR3)
2762	if ( pMapping->cPTs == cPTs
2763	&& !strcmp(pMapping->pszDesc, szDesc))
2764	break;
2765	AssertLogRelMsgReturn(pMapping, ("Couldn't find mapping: cPTs=%#x szDesc=%s (GCPtr=%RGv)\n",
2766	cPTs, szDesc, GCPtr),
2767	VERR_SSM_LOAD_CONFIG_MISMATCH);
2768
2769	/* relocate it. */
2770	if (pMapping->GCPtr != GCPtr)
2771	{
2772	AssertMsg((GCPtr >> X86_PD_SHIFT << X86_PD_SHIFT) == GCPtr, ("GCPtr=%RGv\n", GCPtr));
2773	pgmR3MapRelocate(pVM, pMapping, pMapping->GCPtr, GCPtr);
2774	}
2775	else
2776	Log(("pgmR3Load: '%s' needed no relocation (%RGv)\n", szDesc, GCPtr));
2777	}
2778
2779	/*
2780	* Ram range flags and bits.
2781	*/
2782	i = 0;
2783	for (PPGMRAMRANGE pRam = pPGM->pRamRangesR3; ; pRam = pRam->pNextR3, i++)
2784	{
2785	/* Check the seqence number / separator. */
2786	rc = SSMR3GetU32(pSSM, &u32Sep);
2787	if (RT_FAILURE(rc))
2788	return rc;
2789	if (u32Sep == ~0U)
2790	break;
2791	if (u32Sep != i)
2792	{
2793	AssertMsgFailed(("u32Sep=%#x (last)\n", u32Sep));
2794	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2795	}
2796	AssertLogRelReturn(pRam, VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2797
2798	/* Get the range details. */
2799	RTGCPHYS GCPhys;
2800	SSMR3GetGCPhys(pSSM, &GCPhys);
2801	RTGCPHYS GCPhysLast;
2802	SSMR3GetGCPhys(pSSM, &GCPhysLast);
2803	RTGCPHYS cb;
2804	SSMR3GetGCPhys(pSSM, &cb);
2805	uint8_t fHaveBits;
2806	rc = SSMR3GetU8(pSSM, &fHaveBits);
2807	if (RT_FAILURE(rc))
2808	return rc;
2809	if (fHaveBits & ~1)
2810	{
2811	AssertMsgFailed(("u32Sep=%#x (last)\n", u32Sep));
2812	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2813	}
2814	size_t cchDesc = 0;
2815	char szDesc[256];
2816	szDesc[0] = '\0';
2817	if (u32Version >= PGM_SAVED_STATE_VERSION_RR_DESC)
2818	{
2819	rc = SSMR3GetStrZ(pSSM, szDesc, sizeof(szDesc));
2820	if (RT_FAILURE(rc))
2821	return rc;
2822	/* Since we've modified the description strings in r45878, only compare
2823	them if the saved state is more recent. */
2824	if (u32Version != PGM_SAVED_STATE_VERSION_RR_DESC)
2825	cchDesc = strlen(szDesc);
2826	}
2827
2828	/*
2829	* Match it up with the current range.
2830	*
2831	* Note there is a hack for dealing with the high BIOS mapping
2832	* in the old saved state format, this means we might not have
2833	* a 1:1 match on success.
2834	*/
2835	if ( ( GCPhys != pRam->GCPhys
2836	\|\| GCPhysLast != pRam->GCPhysLast
2837	\|\| cb != pRam->cb
2838	\|\| ( cchDesc
2839	&& strcmp(szDesc, pRam->pszDesc)) )
2840	/* Hack for PDMDevHlpPhysReserve(pDevIns, 0xfff80000, 0x80000, "High ROM Region"); */
2841	&& ( u32Version != PGM_SAVED_STATE_VERSION_OLD_PHYS_CODE
2842	\|\| GCPhys != UINT32_C(0xfff80000)
2843	\|\| GCPhysLast != UINT32_C(0xffffffff)
2844	\|\| pRam->GCPhysLast != GCPhysLast
2845	\|\| pRam->GCPhys < GCPhys
2846	\|\| !fHaveBits)
2847	)
2848	{
2849	LogRel(("Ram range: %RGp-%RGp %RGp bytes %s %s\n"
2850	"State : %RGp-%RGp %RGp bytes %s %s\n",
2851	pRam->GCPhys, pRam->GCPhysLast, pRam->cb, pRam->pvR3 ? "bits" : "nobits", pRam->pszDesc,
2852	GCPhys, GCPhysLast, cb, fHaveBits ? "bits" : "nobits", szDesc));
2853	/*
2854	* If we're loading a state for debugging purpose, don't make a fuss if
2855	* the MMIO and ROM stuff isn't 100% right, just skip the mismatches.
2856	*/
2857	if ( SSMR3HandleGetAfter(pSSM) != SSMAFTER_DEBUG_IT
2858	\|\| GCPhys < 8 * _1M)
2859	AssertFailedReturn(VERR_SSM_LOAD_CONFIG_MISMATCH);
2860
2861	AssertMsgFailed(("debug skipping not implemented, sorry\n"));
2862	continue;
2863	}
2864
2865	uint32_t cPages = (GCPhysLast - GCPhys + 1) >> PAGE_SHIFT;
2866	if (u32Version >= PGM_SAVED_STATE_VERSION_RR_DESC)
2867	{
2868	/*
2869	* Load the pages one by one.
2870	*/
2871	for (uint32_t iPage = 0; iPage < cPages; iPage++)
2872	{
2873	RTGCPHYS const GCPhysPage = ((RTGCPHYS)iPage << PAGE_SHIFT) + pRam->GCPhys;
2874	PPGMPAGE pPage = &pRam->aPages[iPage];
2875	uint8_t uType;
2876	rc = SSMR3GetU8(pSSM, &uType);
2877	AssertLogRelMsgRCReturn(rc, ("pPage=%R[pgmpage] iPage=%#x GCPhysPage=%#x %s\n", pPage, iPage, GCPhysPage, pRam->pszDesc), rc);
2878	if (uType == PGMPAGETYPE_ROM_SHADOW)
2879	rc = pgmR3LoadShadowedRomPage(pVM, pSSM, pPage, GCPhysPage, pRam);
2880	else
2881	rc = pgmR3LoadPage(pVM, pSSM, uType, pPage, GCPhysPage, pRam);
2882	AssertLogRelMsgRCReturn(rc, ("rc=%Rrc iPage=%#x GCPhysPage=%#x %s\n", rc, iPage, GCPhysPage, pRam->pszDesc), rc);
2883	}
2884	}
2885	else
2886	{
2887	/*
2888	* Old format.
2889	*/
2890	AssertLogRelReturn(!pVM->pgm.s.fRamPreAlloc, VERR_NOT_SUPPORTED); /* can't be detected. */
2891
2892	/* Of the page flags, pick up MMIO2 and ROM/RESERVED for the !fHaveBits case.
2893	The rest is generally irrelevant and wrong since the stuff have to match registrations. */
2894	uint32_t fFlags = 0;
2895	for (uint32_t iPage = 0; iPage < cPages; iPage++)
2896	{
2897	uint16_t u16Flags;
2898	rc = SSMR3GetU16(pSSM, &u16Flags);
2899	AssertLogRelMsgRCReturn(rc, ("rc=%Rrc iPage=%#x GCPhys=%#x %s\n", rc, iPage, pRam->GCPhys, pRam->pszDesc), rc);
2900	fFlags \|= u16Flags;
2901	}
2902
2903	/* Load the bits */
2904	if ( !fHaveBits
2905	&& GCPhysLast < UINT32_C(0xe0000000))
2906	{
2907	/*
2908	* Dynamic chunks.
2909	*/
2910	const uint32_t cPagesInChunk = (110241024) >> PAGE_SHIFT;
2911	AssertLogRelMsgReturn(cPages % cPagesInChunk == 0,
2912	("cPages=%#x cPagesInChunk=%#x\n", cPages, cPagesInChunk, pRam->GCPhys, pRam->pszDesc),
2913	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2914
2915	for (uint32_t iPage = 0; iPage < cPages; /* incremented by inner loop */ )
2916	{
2917	uint8_t fPresent;
2918	rc = SSMR3GetU8(pSSM, &fPresent);
2919	AssertLogRelMsgRCReturn(rc, ("rc=%Rrc iPage=%#x GCPhys=%#x %s\n", rc, iPage, pRam->GCPhys, pRam->pszDesc), rc);
2920	AssertLogRelMsgReturn(fPresent == (uint8_t)true \|\| fPresent == (uint8_t)false,
2921	("fPresent=%#x iPage=%#x GCPhys=%#x %s\n", fPresent, iPage, pRam->GCPhys, pRam->pszDesc),
2922	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2923
2924	for (uint32_t iChunkPage = 0; iChunkPage < cPagesInChunk; iChunkPage++, iPage++)
2925	{
2926	RTGCPHYS const GCPhysPage = ((RTGCPHYS)iPage << PAGE_SHIFT) + pRam->GCPhys;
2927	PPGMPAGE pPage = &pRam->aPages[iPage];
2928	if (fPresent)
2929	{
2930	if (PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_MMIO)
2931	rc = pgmR3LoadPageToDevNull(pSSM);
2932	else
2933	rc = pgmR3LoadPageBits(pVM, pSSM, PGMPAGETYPE_INVALID, pPage, GCPhysPage, pRam);
2934	}
2935	else
2936	rc = pgmR3LoadPageZero(pVM, PGMPAGETYPE_INVALID, pPage, GCPhysPage, pRam);
2937	AssertLogRelMsgRCReturn(rc, ("rc=%Rrc iPage=%#x GCPhysPage=%#x %s\n", rc, iPage, GCPhysPage, pRam->pszDesc), rc);
2938	}
2939	}
2940	}
2941	else if (pRam->pvR3)
2942	{
2943	/*
2944	* MMIO2.
2945	*/
2946	AssertLogRelMsgReturn((fFlags & 0x0f) == RT_BIT(3) /MM_RAM_FLAGS_MMIO2/,
2947	("fFlags=%#x GCPhys=%#x %s\n", fFlags, pRam->GCPhys, pRam->pszDesc),
2948	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2949	AssertLogRelMsgReturn(pRam->pvR3,
2950	("GCPhys=%#x %s\n", pRam->GCPhys, pRam->pszDesc),
2951	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2952
2953	rc = SSMR3GetMem(pSSM, pRam->pvR3, pRam->cb);
2954	AssertLogRelMsgRCReturn(rc, ("GCPhys=%#x %s\n", pRam->GCPhys, pRam->pszDesc), rc);
2955	}
2956	else if (GCPhysLast < UINT32_C(0xfff80000))
2957	{
2958	/*
2959	* PCI MMIO, no pages saved.
2960	*/
2961	}
2962	else
2963	{
2964	/*
2965	* Load the 0xfff80000..0xffffffff BIOS range.
2966	* It starts with X reserved pages that we have to skip over since
2967	* the RAMRANGE create by the new code won't include those.
2968	*/
2969	AssertLogRelMsgReturn( !(fFlags & RT_BIT(3) /MM_RAM_FLAGS_MMIO2/)
2970	&& (fFlags & RT_BIT(0) /MM_RAM_FLAGS_RESERVED/),
2971	("fFlags=%#x GCPhys=%#x %s\n", fFlags, pRam->GCPhys, pRam->pszDesc),
2972	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2973	AssertLogRelMsgReturn(GCPhys == UINT32_C(0xfff80000),
2974	("GCPhys=%RGp pRamRange{GCPhys=%#x %s}\n", GCPhys, pRam->GCPhys, pRam->pszDesc),
2975	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2976
2977	/* Skip wasted reserved pages before the ROM. */
2978	while (GCPhys < pRam->GCPhys)
2979	{
2980	rc = pgmR3LoadPageToDevNull(pSSM);
2981	GCPhys += PAGE_SIZE;
2982	}
2983
2984	/* Load the bios pages. */
2985	cPages = pRam->cb >> PAGE_SHIFT;
2986	for (uint32_t iPage = 0; iPage < cPages; iPage++)
2987	{
2988	RTGCPHYS const GCPhysPage = ((RTGCPHYS)iPage << PAGE_SHIFT) + pRam->GCPhys;
2989	PPGMPAGE pPage = &pRam->aPages[iPage];
2990
2991	AssertLogRelMsgReturn(PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_ROM,
2992	("GCPhys=%RGp pPage=%R[pgmpage]\n", GCPhys, GCPhys),
2993	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2994	rc = pgmR3LoadPageBits(pVM, pSSM, PGMPAGETYPE_ROM, pPage, GCPhysPage, pRam);
2995	AssertLogRelMsgRCReturn(rc, ("rc=%Rrc iPage=%#x GCPhys=%#x %s\n", rc, iPage, pRam->GCPhys, pRam->pszDesc), rc);
2996	}
2997	}
2998	}
2999	}
3000
3001	return rc;
3002	}
3003
3004
3005	/**
3006	* Execute state load operation.
3007	*
3008	* @returns VBox status code.
3009	* @param pVM VM Handle.
3010	* @param pSSM SSM operation handle.
3011	* @param u32Version Data layout version.
3012	*/
3013	static DECLCALLBACK(int) pgmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version)
3014	{
3015	int rc;
3016	PPGM pPGM = &pVM->pgm.s;
3017
3018	/*
3019	* Validate version.
3020	*/
3021	if ( u32Version != PGM_SAVED_STATE_VERSION
3022	&& u32Version != PGM_SAVED_STATE_VERSION_2_2_2
3023	&& u32Version != PGM_SAVED_STATE_VERSION_RR_DESC
3024	&& u32Version != PGM_SAVED_STATE_VERSION_OLD_PHYS_CODE)
3025	{
3026	AssertMsgFailed(("pgmR3Load: Invalid version u32Version=%d (current %d)!\n", u32Version, PGM_SAVED_STATE_VERSION));
3027	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
3028	}
3029
3030	/*
3031	* Call the reset function to make sure all the memory is cleared.
3032	*/
3033	PGMR3Reset(pVM);
3034
3035	/*
3036	* Do the loading while owning the lock because a bunch of the functions
3037	* we're using requires this.
3038	*/
3039	pgmLock(pVM);
3040	rc = pgmR3LoadLocked(pVM, pSSM, u32Version);
3041	pgmUnlock(pVM);
3042	if (RT_SUCCESS(rc))
3043	{
3044	/*
3045	* We require a full resync now.
3046	*/
3047	for (unsigned i=0;i<pVM->cCPUs;i++)
3048	{
3049	PVMCPU pVCpu = &pVM->aCpus[i];
3050	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL);
3051	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
3052
3053	pVCpu->pgm.s.fSyncFlags \|= PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL;
3054	}
3055
3056	pgmR3HandlerPhysicalUpdateAll(pVM);
3057
3058	for (unsigned i=0;i<pVM->cCPUs;i++)
3059	{
3060	PVMCPU pVCpu = &pVM->aCpus[i];
3061
3062	/*
3063	* Change the paging mode.
3064	*/
3065	rc = PGMR3ChangeMode(pVM, pVCpu, pVCpu->pgm.s.enmGuestMode);
3066
3067	/* Restore pVM->pgm.s.GCPhysCR3. */
3068	Assert(pVCpu->pgm.s.GCPhysCR3 == NIL_RTGCPHYS);
3069	RTGCPHYS GCPhysCR3 = CPUMGetGuestCR3(pVCpu);
3070	if ( pVCpu->pgm.s.enmGuestMode == PGMMODE_PAE
3071	\|\| pVCpu->pgm.s.enmGuestMode == PGMMODE_PAE_NX
3072	\|\| pVCpu->pgm.s.enmGuestMode == PGMMODE_AMD64
3073	\|\| pVCpu->pgm.s.enmGuestMode == PGMMODE_AMD64_NX)
3074	GCPhysCR3 = (GCPhysCR3 & X86_CR3_PAE_PAGE_MASK);
3075	else
3076	GCPhysCR3 = (GCPhysCR3 & X86_CR3_PAGE_MASK);
3077	pVCpu->pgm.s.GCPhysCR3 = GCPhysCR3;
3078	}
3079	}
3080
3081	return rc;
3082	}
3083
3084
3085	/**
3086	* Show paging mode.
3087	*
3088	* @param pVM VM Handle.
3089	* @param pHlp The info helpers.
3090	* @param pszArgs "all" (default), "guest", "shadow" or "host".
3091	*/
3092	static DECLCALLBACK(void) pgmR3InfoMode(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3093	{
3094	/* digest argument. */
3095	bool fGuest, fShadow, fHost;
3096	if (pszArgs)
3097	pszArgs = RTStrStripL(pszArgs);
3098	if (!pszArgs \|\| !*pszArgs \|\| strstr(pszArgs, "all"))
3099	fShadow = fHost = fGuest = true;
3100	else
3101	{
3102	fShadow = fHost = fGuest = false;
3103	if (strstr(pszArgs, "guest"))
3104	fGuest = true;
3105	if (strstr(pszArgs, "shadow"))
3106	fShadow = true;
3107	if (strstr(pszArgs, "host"))
3108	fHost = true;
3109	}
3110
3111	/** @todo SMP support! */
3112	/* print info. */
3113	if (fGuest)
3114	pHlp->pfnPrintf(pHlp, "Guest paging mode: %s, changed %RU64 times, A20 %s\n",
3115	PGMGetModeName(pVM->aCpus[0].pgm.s.enmGuestMode), pVM->aCpus[0].pgm.s.cGuestModeChanges.c,
3116	pVM->aCpus[0].pgm.s.fA20Enabled ? "enabled" : "disabled");
3117	if (fShadow)
3118	pHlp->pfnPrintf(pHlp, "Shadow paging mode: %s\n", PGMGetModeName(pVM->aCpus[0].pgm.s.enmShadowMode));
3119	if (fHost)
3120	{
3121	const char *psz;
3122	switch (pVM->pgm.s.enmHostMode)
3123	{
3124	case SUPPAGINGMODE_INVALID: psz = "invalid"; break;
3125	case SUPPAGINGMODE_32_BIT: psz = "32-bit"; break;
3126	case SUPPAGINGMODE_32_BIT_GLOBAL: psz = "32-bit+G"; break;
3127	case SUPPAGINGMODE_PAE: psz = "PAE"; break;
3128	case SUPPAGINGMODE_PAE_GLOBAL: psz = "PAE+G"; break;
3129	case SUPPAGINGMODE_PAE_NX: psz = "PAE+NX"; break;
3130	case SUPPAGINGMODE_PAE_GLOBAL_NX: psz = "PAE+G+NX"; break;
3131	case SUPPAGINGMODE_AMD64: psz = "AMD64"; break;
3132	case SUPPAGINGMODE_AMD64_GLOBAL: psz = "AMD64+G"; break;
3133	case SUPPAGINGMODE_AMD64_NX: psz = "AMD64+NX"; break;
3134	case SUPPAGINGMODE_AMD64_GLOBAL_NX: psz = "AMD64+G+NX"; break;
3135	default: psz = "unknown"; break;
3136	}
3137	pHlp->pfnPrintf(pHlp, "Host paging mode: %s\n", psz);
3138	}
3139	}
3140
3141
3142	/**
3143	* Dump registered MMIO ranges to the log.
3144	*
3145	* @param pVM VM Handle.
3146	* @param pHlp The info helpers.
3147	* @param pszArgs Arguments, ignored.
3148	*/
3149	static DECLCALLBACK(void) pgmR3PhysInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3150	{
3151	NOREF(pszArgs);
3152	pHlp->pfnPrintf(pHlp,
3153	"RAM ranges (pVM=%p)\n"
3154	"%.s %.s\n",
3155	pVM,
3156	sizeof(RTGCPHYS) * 4 + 1, "GC Phys Range ",
3157	sizeof(RTHCPTR) * 2, "pvHC ");
3158
3159	for (PPGMRAMRANGE pCur = pVM->pgm.s.pRamRangesR3; pCur; pCur = pCur->pNextR3)
3160	pHlp->pfnPrintf(pHlp,
3161	"%RGp-%RGp %RHv %s\n",
3162	pCur->GCPhys,
3163	pCur->GCPhysLast,
3164	pCur->pvR3,
3165	pCur->pszDesc);
3166	}
3167
3168	/**
3169	* Dump the page directory to the log.
3170	*
3171	* @param pVM VM Handle.
3172	* @param pHlp The info helpers.
3173	* @param pszArgs Arguments, ignored.
3174	*/
3175	static DECLCALLBACK(void) pgmR3InfoCr3(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3176	{
3177	/** @todo SMP support!! */
3178	PVMCPU pVCpu = &pVM->aCpus[0];
3179
3180	/** @todo fix this! Convert the PGMR3DumpHierarchyHC functions to do guest stuff. */
3181	/* Big pages supported? */
3182	const bool fPSE = !!(CPUMGetGuestCR4(pVCpu) & X86_CR4_PSE);
3183
3184	/* Global pages supported? */
3185	const bool fPGE = !!(CPUMGetGuestCR4(pVCpu) & X86_CR4_PGE);
3186
3187	NOREF(pszArgs);
3188
3189	/*
3190	* Get page directory addresses.
3191	*/
3192	PX86PD pPDSrc = pgmGstGet32bitPDPtr(&pVCpu->pgm.s);
3193	Assert(pPDSrc);
3194	Assert(PGMPhysGCPhys2R3PtrAssert(pVM, (RTGCPHYS)(CPUMGetGuestCR3(pVCpu) & X86_CR3_PAGE_MASK), sizeof(*pPDSrc)) == pPDSrc);
3195
3196	/*
3197	* Iterate the page directory.
3198	*/
3199	for (unsigned iPD = 0; iPD < RT_ELEMENTS(pPDSrc->a); iPD++)
3200	{
3201	X86PDE PdeSrc = pPDSrc->a[iPD];
3202	if (PdeSrc.n.u1Present)
3203	{
3204	if (PdeSrc.b.u1Size && fPSE)
3205	pHlp->pfnPrintf(pHlp,
3206	"%04X - %RGp P=%d U=%d RW=%d G=%d - BIG\n",
3207	iPD,
3208	pgmGstGet4MBPhysPage(&pVM->pgm.s, PdeSrc),
3209	PdeSrc.b.u1Present, PdeSrc.b.u1User, PdeSrc.b.u1Write, PdeSrc.b.u1Global && fPGE);
3210	else
3211	pHlp->pfnPrintf(pHlp,
3212	"%04X - %RGp P=%d U=%d RW=%d [G=%d]\n",
3213	iPD,
3214	(RTGCPHYS)(PdeSrc.u & X86_PDE_PG_MASK),
3215	PdeSrc.n.u1Present, PdeSrc.n.u1User, PdeSrc.n.u1Write, PdeSrc.b.u1Global && fPGE);
3216	}
3217	}
3218	}
3219
3220
3221	/**
3222	* Service a VMMCALLRING3_PGM_LOCK call.
3223	*
3224	* @returns VBox status code.
3225	* @param pVM The VM handle.
3226	*/
3227	VMMR3DECL(int) PGMR3LockCall(PVM pVM)
3228	{
3229	int rc = PDMR3CritSectEnterEx(&pVM->pgm.s.CritSect, true /* fHostCall */);
3230	AssertRC(rc);
3231	return rc;
3232	}
3233
3234
3235	/**
3236	* Converts a PGMMODE value to a PGM_TYPE_* \#define.
3237	*
3238	* @returns PGM_TYPE_*.
3239	* @param pgmMode The mode value to convert.
3240	*/
3241	DECLINLINE(unsigned) pgmModeToType(PGMMODE pgmMode)
3242	{
3243	switch (pgmMode)
3244	{
3245	case PGMMODE_REAL: return PGM_TYPE_REAL;
3246	case PGMMODE_PROTECTED: return PGM_TYPE_PROT;
3247	case PGMMODE_32_BIT: return PGM_TYPE_32BIT;
3248	case PGMMODE_PAE:
3249	case PGMMODE_PAE_NX: return PGM_TYPE_PAE;
3250	case PGMMODE_AMD64:
3251	case PGMMODE_AMD64_NX: return PGM_TYPE_AMD64;
3252	case PGMMODE_NESTED: return PGM_TYPE_NESTED;
3253	case PGMMODE_EPT: return PGM_TYPE_EPT;
3254	default:
3255	AssertFatalMsgFailed(("pgmMode=%d\n", pgmMode));
3256	}
3257	}
3258
3259
3260	/**
3261	* Gets the index into the paging mode data array of a SHW+GST mode.
3262	*
3263	* @returns PGM::paPagingData index.
3264	* @param uShwType The shadow paging mode type.
3265	* @param uGstType The guest paging mode type.
3266	*/
3267	DECLINLINE(unsigned) pgmModeDataIndex(unsigned uShwType, unsigned uGstType)
3268	{
3269	Assert(uShwType >= PGM_TYPE_32BIT && uShwType <= PGM_TYPE_MAX);
3270	Assert(uGstType >= PGM_TYPE_REAL && uGstType <= PGM_TYPE_AMD64);
3271	return (uShwType - PGM_TYPE_32BIT) * (PGM_TYPE_AMD64 - PGM_TYPE_REAL + 1)
3272	+ (uGstType - PGM_TYPE_REAL);
3273	}
3274
3275
3276	/**
3277	* Gets the index into the paging mode data array of a SHW+GST mode.
3278	*
3279	* @returns PGM::paPagingData index.
3280	* @param enmShw The shadow paging mode.
3281	* @param enmGst The guest paging mode.
3282	*/
3283	DECLINLINE(unsigned) pgmModeDataIndexByMode(PGMMODE enmShw, PGMMODE enmGst)
3284	{
3285	Assert(enmShw >= PGMMODE_32_BIT && enmShw <= PGMMODE_MAX);
3286	Assert(enmGst > PGMMODE_INVALID && enmGst < PGMMODE_MAX);
3287	return pgmModeDataIndex(pgmModeToType(enmShw), pgmModeToType(enmGst));
3288	}
3289
3290
3291	/**
3292	* Calculates the max data index.
3293	* @returns The number of entries in the paging data array.
3294	*/
3295	DECLINLINE(unsigned) pgmModeDataMaxIndex(void)
3296	{
3297	return pgmModeDataIndex(PGM_TYPE_MAX, PGM_TYPE_AMD64) + 1;
3298	}
3299
3300
3301	/**
3302	* Initializes the paging mode data kept in PGM::paModeData.
3303	*
3304	* @param pVM The VM handle.
3305	* @param fResolveGCAndR0 Indicate whether or not GC and Ring-0 symbols can be resolved now.
3306	* This is used early in the init process to avoid trouble with PDM
3307	* not being initialized yet.
3308	*/
3309	static int pgmR3ModeDataInit(PVM pVM, bool fResolveGCAndR0)
3310	{
3311	PPGMMODEDATA pModeData;
3312	int rc;
3313
3314	/*
3315	* Allocate the array on the first call.
3316	*/
3317	if (!pVM->pgm.s.paModeData)
3318	{
3319	pVM->pgm.s.paModeData = (PPGMMODEDATA)MMR3HeapAllocZ(pVM, MM_TAG_PGM, sizeof(PGMMODEDATA) * pgmModeDataMaxIndex());
3320	AssertReturn(pVM->pgm.s.paModeData, VERR_NO_MEMORY);
3321	}
3322
3323	/*
3324	* Initialize the array entries.
3325	*/
3326	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_32BIT, PGM_TYPE_REAL)];
3327	pModeData->uShwType = PGM_TYPE_32BIT;
3328	pModeData->uGstType = PGM_TYPE_REAL;
3329	rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3330	rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3331	rc = PGM_BTH_NAME_32BIT_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3332
3333	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_32BIT, PGMMODE_PROTECTED)];
3334	pModeData->uShwType = PGM_TYPE_32BIT;
3335	pModeData->uGstType = PGM_TYPE_PROT;
3336	rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3337	rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3338	rc = PGM_BTH_NAME_32BIT_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3339
3340	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_32BIT, PGM_TYPE_32BIT)];
3341	pModeData->uShwType = PGM_TYPE_32BIT;
3342	pModeData->uGstType = PGM_TYPE_32BIT;
3343	rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3344	rc = PGM_GST_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3345	rc = PGM_BTH_NAME_32BIT_32BIT(InitData)(pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3346
3347	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_REAL)];
3348	pModeData->uShwType = PGM_TYPE_PAE;
3349	pModeData->uGstType = PGM_TYPE_REAL;
3350	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3351	rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3352	rc = PGM_BTH_NAME_PAE_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3353
3354	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_PROT)];
3355	pModeData->uShwType = PGM_TYPE_PAE;
3356	pModeData->uGstType = PGM_TYPE_PROT;
3357	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3358	rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3359	rc = PGM_BTH_NAME_PAE_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3360
3361	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_32BIT)];
3362	pModeData->uShwType = PGM_TYPE_PAE;
3363	pModeData->uGstType = PGM_TYPE_32BIT;
3364	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3365	rc = PGM_GST_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3366	rc = PGM_BTH_NAME_PAE_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3367
3368	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_PAE)];
3369	pModeData->uShwType = PGM_TYPE_PAE;
3370	pModeData->uGstType = PGM_TYPE_PAE;
3371	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3372	rc = PGM_GST_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3373	rc = PGM_BTH_NAME_PAE_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3374
3375	#ifdef VBOX_WITH_64_BITS_GUESTS
3376	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_AMD64, PGM_TYPE_AMD64)];
3377	pModeData->uShwType = PGM_TYPE_AMD64;
3378	pModeData->uGstType = PGM_TYPE_AMD64;
3379	rc = PGM_SHW_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3380	rc = PGM_GST_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3381	rc = PGM_BTH_NAME_AMD64_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3382	#endif
3383
3384	/* The nested paging mode. */
3385	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_REAL)];
3386	pModeData->uShwType = PGM_TYPE_NESTED;
3387	pModeData->uGstType = PGM_TYPE_REAL;
3388	rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3389	rc = PGM_BTH_NAME_NESTED_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3390
3391	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGMMODE_PROTECTED)];
3392	pModeData->uShwType = PGM_TYPE_NESTED;
3393	pModeData->uGstType = PGM_TYPE_PROT;
3394	rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3395	rc = PGM_BTH_NAME_NESTED_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3396
3397	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_32BIT)];
3398	pModeData->uShwType = PGM_TYPE_NESTED;
3399	pModeData->uGstType = PGM_TYPE_32BIT;
3400	rc = PGM_GST_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3401	rc = PGM_BTH_NAME_NESTED_32BIT(InitData)(pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3402
3403	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_PAE)];
3404	pModeData->uShwType = PGM_TYPE_NESTED;
3405	pModeData->uGstType = PGM_TYPE_PAE;
3406	rc = PGM_GST_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3407	rc = PGM_BTH_NAME_NESTED_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3408
3409	#ifdef VBOX_WITH_64_BITS_GUESTS
3410	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_AMD64)];
3411	pModeData->uShwType = PGM_TYPE_NESTED;
3412	pModeData->uGstType = PGM_TYPE_AMD64;
3413	rc = PGM_GST_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3414	rc = PGM_BTH_NAME_NESTED_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3415	#endif
3416
3417	/* The shadow part of the nested callback mode depends on the host paging mode (AMD-V only). */
3418	switch (pVM->pgm.s.enmHostMode)
3419	{
3420	#if HC_ARCH_BITS == 32
3421	case SUPPAGINGMODE_32_BIT:
3422	case SUPPAGINGMODE_32_BIT_GLOBAL:
3423	for (unsigned i = PGM_TYPE_REAL; i <= PGM_TYPE_PAE; i++)
3424	{
3425	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, i)];
3426	rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3427	}
3428	# ifdef VBOX_WITH_64_BITS_GUESTS
3429	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_AMD64)];
3430	rc = PGM_SHW_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3431	# endif
3432	break;
3433
3434	case SUPPAGINGMODE_PAE:
3435	case SUPPAGINGMODE_PAE_NX:
3436	case SUPPAGINGMODE_PAE_GLOBAL:
3437	case SUPPAGINGMODE_PAE_GLOBAL_NX:
3438	for (unsigned i = PGM_TYPE_REAL; i <= PGM_TYPE_PAE; i++)
3439	{
3440	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, i)];
3441	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3442	}
3443	# ifdef VBOX_WITH_64_BITS_GUESTS
3444	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_AMD64)];
3445	rc = PGM_SHW_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3446	# endif
3447	break;
3448	#endif /* HC_ARCH_BITS == 32 */
3449
3450	#if HC_ARCH_BITS == 64 \|\| defined(RT_OS_DARWIN)
3451	case SUPPAGINGMODE_AMD64:
3452	case SUPPAGINGMODE_AMD64_GLOBAL:
3453	case SUPPAGINGMODE_AMD64_NX:
3454	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
3455	# ifdef VBOX_WITH_64_BITS_GUESTS
3456	for (unsigned i = PGM_TYPE_REAL; i <= PGM_TYPE_AMD64; i++)
3457	# else
3458	for (unsigned i = PGM_TYPE_REAL; i <= PGM_TYPE_PAE; i++)
3459	# endif
3460	{
3461	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, i)];
3462	rc = PGM_SHW_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3463	}
3464	break;
3465	#endif /* HC_ARCH_BITS == 64 \|\| RT_OS_DARWIN */
3466
3467	default:
3468	AssertFailed();
3469	break;
3470	}
3471
3472	/* Extended paging (EPT) / Intel VT-x */
3473	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_REAL)];
3474	pModeData->uShwType = PGM_TYPE_EPT;
3475	pModeData->uGstType = PGM_TYPE_REAL;
3476	rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3477	rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3478	rc = PGM_BTH_NAME_EPT_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3479
3480	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_PROT)];
3481	pModeData->uShwType = PGM_TYPE_EPT;
3482	pModeData->uGstType = PGM_TYPE_PROT;
3483	rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3484	rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3485	rc = PGM_BTH_NAME_EPT_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3486
3487	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_32BIT)];
3488	pModeData->uShwType = PGM_TYPE_EPT;
3489	pModeData->uGstType = PGM_TYPE_32BIT;
3490	rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3491	rc = PGM_GST_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3492	rc = PGM_BTH_NAME_EPT_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3493
3494	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_PAE)];
3495	pModeData->uShwType = PGM_TYPE_EPT;
3496	pModeData->uGstType = PGM_TYPE_PAE;
3497	rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3498	rc = PGM_GST_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3499	rc = PGM_BTH_NAME_EPT_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3500
3501	#ifdef VBOX_WITH_64_BITS_GUESTS
3502	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_AMD64)];
3503	pModeData->uShwType = PGM_TYPE_EPT;
3504	pModeData->uGstType = PGM_TYPE_AMD64;
3505	rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3506	rc = PGM_GST_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3507	rc = PGM_BTH_NAME_EPT_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3508	#endif
3509	return VINF_SUCCESS;
3510	}
3511
3512
3513	/**
3514	* Switch to different (or relocated in the relocate case) mode data.
3515	*
3516	* @param pVM The VM handle.
3517	* @param pVCpu The VMCPU to operate on.
3518	* @param enmShw The the shadow paging mode.
3519	* @param enmGst The the guest paging mode.
3520	*/
3521	static void pgmR3ModeDataSwitch(PVM pVM, PVMCPU pVCpu, PGMMODE enmShw, PGMMODE enmGst)
3522	{
3523	PPGMMODEDATA pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndexByMode(enmShw, enmGst)];
3524
3525	Assert(pModeData->uGstType == pgmModeToType(enmGst));
3526	Assert(pModeData->uShwType == pgmModeToType(enmShw));
3527
3528	/* shadow */
3529	pVCpu->pgm.s.pfnR3ShwRelocate = pModeData->pfnR3ShwRelocate;
3530	pVCpu->pgm.s.pfnR3ShwExit = pModeData->pfnR3ShwExit;
3531	pVCpu->pgm.s.pfnR3ShwGetPage = pModeData->pfnR3ShwGetPage;
3532	Assert(pVCpu->pgm.s.pfnR3ShwGetPage);
3533	pVCpu->pgm.s.pfnR3ShwModifyPage = pModeData->pfnR3ShwModifyPage;
3534
3535	pVCpu->pgm.s.pfnRCShwGetPage = pModeData->pfnRCShwGetPage;
3536	pVCpu->pgm.s.pfnRCShwModifyPage = pModeData->pfnRCShwModifyPage;
3537
3538	pVCpu->pgm.s.pfnR0ShwGetPage = pModeData->pfnR0ShwGetPage;
3539	pVCpu->pgm.s.pfnR0ShwModifyPage = pModeData->pfnR0ShwModifyPage;
3540
3541
3542	/* guest */
3543	pVCpu->pgm.s.pfnR3GstRelocate = pModeData->pfnR3GstRelocate;
3544	pVCpu->pgm.s.pfnR3GstExit = pModeData->pfnR3GstExit;
3545	pVCpu->pgm.s.pfnR3GstGetPage = pModeData->pfnR3GstGetPage;
3546	Assert(pVCpu->pgm.s.pfnR3GstGetPage);
3547	pVCpu->pgm.s.pfnR3GstModifyPage = pModeData->pfnR3GstModifyPage;
3548	pVCpu->pgm.s.pfnR3GstGetPDE = pModeData->pfnR3GstGetPDE;
3549	pVCpu->pgm.s.pfnRCGstGetPage = pModeData->pfnRCGstGetPage;
3550	pVCpu->pgm.s.pfnRCGstModifyPage = pModeData->pfnRCGstModifyPage;
3551	pVCpu->pgm.s.pfnRCGstGetPDE = pModeData->pfnRCGstGetPDE;
3552	pVCpu->pgm.s.pfnR0GstGetPage = pModeData->pfnR0GstGetPage;
3553	pVCpu->pgm.s.pfnR0GstModifyPage = pModeData->pfnR0GstModifyPage;
3554	pVCpu->pgm.s.pfnR0GstGetPDE = pModeData->pfnR0GstGetPDE;
3555
3556	/* both */
3557	pVCpu->pgm.s.pfnR3BthRelocate = pModeData->pfnR3BthRelocate;
3558	pVCpu->pgm.s.pfnR3BthInvalidatePage = pModeData->pfnR3BthInvalidatePage;
3559	pVCpu->pgm.s.pfnR3BthSyncCR3 = pModeData->pfnR3BthSyncCR3;
3560	Assert(pVCpu->pgm.s.pfnR3BthSyncCR3);
3561	pVCpu->pgm.s.pfnR3BthSyncPage = pModeData->pfnR3BthSyncPage;
3562	pVCpu->pgm.s.pfnR3BthPrefetchPage = pModeData->pfnR3BthPrefetchPage;
3563	pVCpu->pgm.s.pfnR3BthVerifyAccessSyncPage = pModeData->pfnR3BthVerifyAccessSyncPage;
3564	#ifdef VBOX_STRICT
3565	pVCpu->pgm.s.pfnR3BthAssertCR3 = pModeData->pfnR3BthAssertCR3;
3566	#endif
3567	pVCpu->pgm.s.pfnR3BthMapCR3 = pModeData->pfnR3BthMapCR3;
3568	pVCpu->pgm.s.pfnR3BthUnmapCR3 = pModeData->pfnR3BthUnmapCR3;
3569
3570	pVCpu->pgm.s.pfnRCBthTrap0eHandler = pModeData->pfnRCBthTrap0eHandler;
3571	pVCpu->pgm.s.pfnRCBthInvalidatePage = pModeData->pfnRCBthInvalidatePage;
3572	pVCpu->pgm.s.pfnRCBthSyncCR3 = pModeData->pfnRCBthSyncCR3;
3573	pVCpu->pgm.s.pfnRCBthSyncPage = pModeData->pfnRCBthSyncPage;
3574	pVCpu->pgm.s.pfnRCBthPrefetchPage = pModeData->pfnRCBthPrefetchPage;
3575	pVCpu->pgm.s.pfnRCBthVerifyAccessSyncPage = pModeData->pfnRCBthVerifyAccessSyncPage;
3576	#ifdef VBOX_STRICT
3577	pVCpu->pgm.s.pfnRCBthAssertCR3 = pModeData->pfnRCBthAssertCR3;
3578	#endif
3579	pVCpu->pgm.s.pfnRCBthMapCR3 = pModeData->pfnRCBthMapCR3;
3580	pVCpu->pgm.s.pfnRCBthUnmapCR3 = pModeData->pfnRCBthUnmapCR3;
3581
3582	pVCpu->pgm.s.pfnR0BthTrap0eHandler = pModeData->pfnR0BthTrap0eHandler;
3583	pVCpu->pgm.s.pfnR0BthInvalidatePage = pModeData->pfnR0BthInvalidatePage;
3584	pVCpu->pgm.s.pfnR0BthSyncCR3 = pModeData->pfnR0BthSyncCR3;
3585	pVCpu->pgm.s.pfnR0BthSyncPage = pModeData->pfnR0BthSyncPage;
3586	pVCpu->pgm.s.pfnR0BthPrefetchPage = pModeData->pfnR0BthPrefetchPage;
3587	pVCpu->pgm.s.pfnR0BthVerifyAccessSyncPage = pModeData->pfnR0BthVerifyAccessSyncPage;
3588	#ifdef VBOX_STRICT
3589	pVCpu->pgm.s.pfnR0BthAssertCR3 = pModeData->pfnR0BthAssertCR3;
3590	#endif
3591	pVCpu->pgm.s.pfnR0BthMapCR3 = pModeData->pfnR0BthMapCR3;
3592	pVCpu->pgm.s.pfnR0BthUnmapCR3 = pModeData->pfnR0BthUnmapCR3;
3593	}
3594
3595
3596	/**
3597	* Calculates the shadow paging mode.
3598	*
3599	* @returns The shadow paging mode.
3600	* @param pVM VM handle.
3601	* @param enmGuestMode The guest mode.
3602	* @param enmHostMode The host mode.
3603	* @param enmShadowMode The current shadow mode.
3604	* @param penmSwitcher Where to store the switcher to use.
3605	* VMMSWITCHER_INVALID means no change.
3606	*/
3607	static PGMMODE pgmR3CalcShadowMode(PVM pVM, PGMMODE enmGuestMode, SUPPAGINGMODE enmHostMode, PGMMODE enmShadowMode, VMMSWITCHER *penmSwitcher)
3608	{
3609	VMMSWITCHER enmSwitcher = VMMSWITCHER_INVALID;
3610	switch (enmGuestMode)
3611	{
3612	/*
3613	* When switching to real or protected mode we don't change
3614	* anything since it's likely that we'll switch back pretty soon.
3615	*
3616	* During pgmR3InitPaging we'll end up here with PGMMODE_INVALID
3617	* and is supposed to determine which shadow paging and switcher to
3618	* use during init.
3619	*/
3620	case PGMMODE_REAL:
3621	case PGMMODE_PROTECTED:
3622	if ( enmShadowMode != PGMMODE_INVALID
3623	&& !HWACCMIsEnabled(pVM) /* always switch in hwaccm mode! */)
3624	break; /* (no change) */
3625
3626	switch (enmHostMode)
3627	{
3628	case SUPPAGINGMODE_32_BIT:
3629	case SUPPAGINGMODE_32_BIT_GLOBAL:
3630	enmShadowMode = PGMMODE_32_BIT;
3631	enmSwitcher = VMMSWITCHER_32_TO_32;
3632	break;
3633
3634	case SUPPAGINGMODE_PAE:
3635	case SUPPAGINGMODE_PAE_NX:
3636	case SUPPAGINGMODE_PAE_GLOBAL:
3637	case SUPPAGINGMODE_PAE_GLOBAL_NX:
3638	enmShadowMode = PGMMODE_PAE;
3639	enmSwitcher = VMMSWITCHER_PAE_TO_PAE;
3640	#ifdef DEBUG_bird
3641	if (RTEnvExist("VBOX_32BIT"))
3642	{
3643	enmShadowMode = PGMMODE_32_BIT;
3644	enmSwitcher = VMMSWITCHER_PAE_TO_32;
3645	}
3646	#endif
3647	break;
3648
3649	case SUPPAGINGMODE_AMD64:
3650	case SUPPAGINGMODE_AMD64_GLOBAL:
3651	case SUPPAGINGMODE_AMD64_NX:
3652	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
3653	enmShadowMode = PGMMODE_PAE;
3654	enmSwitcher = VMMSWITCHER_AMD64_TO_PAE;
3655	#ifdef DEBUG_bird
3656	if (RTEnvExist("VBOX_32BIT"))
3657	{
3658	enmShadowMode = PGMMODE_32_BIT;
3659	enmSwitcher = VMMSWITCHER_AMD64_TO_32;
3660	}
3661	#endif
3662	break;
3663
3664	default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
3665	}
3666	break;
3667
3668	case PGMMODE_32_BIT:
3669	switch (enmHostMode)
3670	{
3671	case SUPPAGINGMODE_32_BIT:
3672	case SUPPAGINGMODE_32_BIT_GLOBAL:
3673	enmShadowMode = PGMMODE_32_BIT;
3674	enmSwitcher = VMMSWITCHER_32_TO_32;
3675	break;
3676
3677	case SUPPAGINGMODE_PAE:
3678	case SUPPAGINGMODE_PAE_NX:
3679	case SUPPAGINGMODE_PAE_GLOBAL:
3680	case SUPPAGINGMODE_PAE_GLOBAL_NX:
3681	enmShadowMode = PGMMODE_PAE;
3682	enmSwitcher = VMMSWITCHER_PAE_TO_PAE;
3683	#ifdef DEBUG_bird
3684	if (RTEnvExist("VBOX_32BIT"))
3685	{
3686	enmShadowMode = PGMMODE_32_BIT;
3687	enmSwitcher = VMMSWITCHER_PAE_TO_32;
3688	}
3689	#endif
3690	break;
3691
3692	case SUPPAGINGMODE_AMD64:
3693	case SUPPAGINGMODE_AMD64_GLOBAL:
3694	case SUPPAGINGMODE_AMD64_NX:
3695	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
3696	enmShadowMode = PGMMODE_PAE;
3697	enmSwitcher = VMMSWITCHER_AMD64_TO_PAE;
3698	#ifdef DEBUG_bird
3699	if (RTEnvExist("VBOX_32BIT"))
3700	{
3701	enmShadowMode = PGMMODE_32_BIT;
3702	enmSwitcher = VMMSWITCHER_AMD64_TO_32;
3703	}
3704	#endif
3705	break;
3706
3707	default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
3708	}
3709	break;
3710
3711	case PGMMODE_PAE:
3712	case PGMMODE_PAE_NX: /** @todo This might require more switchers and guest+both modes. */
3713	switch (enmHostMode)
3714	{
3715	case SUPPAGINGMODE_32_BIT:
3716	case SUPPAGINGMODE_32_BIT_GLOBAL:
3717	enmShadowMode = PGMMODE_PAE;
3718	enmSwitcher = VMMSWITCHER_32_TO_PAE;
3719	break;
3720
3721	case SUPPAGINGMODE_PAE:
3722	case SUPPAGINGMODE_PAE_NX:
3723	case SUPPAGINGMODE_PAE_GLOBAL:
3724	case SUPPAGINGMODE_PAE_GLOBAL_NX:
3725	enmShadowMode = PGMMODE_PAE;
3726	enmSwitcher = VMMSWITCHER_PAE_TO_PAE;
3727	break;
3728
3729	case SUPPAGINGMODE_AMD64:
3730	case SUPPAGINGMODE_AMD64_GLOBAL:
3731	case SUPPAGINGMODE_AMD64_NX:
3732	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
3733	enmShadowMode = PGMMODE_PAE;
3734	enmSwitcher = VMMSWITCHER_AMD64_TO_PAE;
3735	break;
3736
3737	default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
3738	}
3739	break;
3740
3741	case PGMMODE_AMD64:
3742	case PGMMODE_AMD64_NX:
3743	switch (enmHostMode)
3744	{
3745	case SUPPAGINGMODE_32_BIT:
3746	case SUPPAGINGMODE_32_BIT_GLOBAL:
3747	enmShadowMode = PGMMODE_AMD64;
3748	enmSwitcher = VMMSWITCHER_32_TO_AMD64;
3749	break;
3750
3751	case SUPPAGINGMODE_PAE:
3752	case SUPPAGINGMODE_PAE_NX:
3753	case SUPPAGINGMODE_PAE_GLOBAL:
3754	case SUPPAGINGMODE_PAE_GLOBAL_NX:
3755	enmShadowMode = PGMMODE_AMD64;
3756	enmSwitcher = VMMSWITCHER_PAE_TO_AMD64;
3757	break;
3758
3759	case SUPPAGINGMODE_AMD64:
3760	case SUPPAGINGMODE_AMD64_GLOBAL:
3761	case SUPPAGINGMODE_AMD64_NX:
3762	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
3763	enmShadowMode = PGMMODE_AMD64;
3764	enmSwitcher = VMMSWITCHER_AMD64_TO_AMD64;
3765	break;
3766
3767	default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
3768	}
3769	break;
3770
3771
3772	default:
3773	AssertReleaseMsgFailed(("enmGuestMode=%d\n", enmGuestMode));
3774	return PGMMODE_INVALID;
3775	}
3776	/* Override the shadow mode is nested paging is active. */
3777	if (HWACCMIsNestedPagingActive(pVM))
3778	enmShadowMode = HWACCMGetShwPagingMode(pVM);
3779
3780	*penmSwitcher = enmSwitcher;
3781	return enmShadowMode;
3782	}
3783
3784
3785	/**
3786	* Performs the actual mode change.
3787	* This is called by PGMChangeMode and pgmR3InitPaging().
3788	*
3789	* @returns VBox status code. May suspend or power off the VM on error, but this
3790	* will trigger using FFs and not status codes.
3791	*
3792	* @param pVM VM handle.
3793	* @param pVCpu The VMCPU to operate on.
3794	* @param enmGuestMode The new guest mode. This is assumed to be different from
3795	* the current mode.
3796	*/
3797	VMMR3DECL(int) PGMR3ChangeMode(PVM pVM, PVMCPU pVCpu, PGMMODE enmGuestMode)
3798	{
3799	Log(("PGMR3ChangeMode: Guest mode: %s -> %s\n", PGMGetModeName(pVCpu->pgm.s.enmGuestMode), PGMGetModeName(enmGuestMode)));
3800	STAM_REL_COUNTER_INC(&pVCpu->pgm.s.cGuestModeChanges);
3801
3802	/*
3803	* Calc the shadow mode and switcher.
3804	*/
3805	VMMSWITCHER enmSwitcher;
3806	PGMMODE enmShadowMode = pgmR3CalcShadowMode(pVM, enmGuestMode, pVM->pgm.s.enmHostMode, pVCpu->pgm.s.enmShadowMode, &enmSwitcher);
3807	if (enmSwitcher != VMMSWITCHER_INVALID)
3808	{
3809	/*
3810	* Select new switcher.
3811	*/
3812	int rc = VMMR3SelectSwitcher(pVM, enmSwitcher);
3813	if (RT_FAILURE(rc))
3814	{
3815	AssertReleaseMsgFailed(("VMMR3SelectSwitcher(%d) -> %Rrc\n", enmSwitcher, rc));
3816	return rc;
3817	}
3818	}
3819
3820	/*
3821	* Exit old mode(s).
3822	*/
3823	/* shadow */
3824	if (enmShadowMode != pVCpu->pgm.s.enmShadowMode)
3825	{
3826	LogFlow(("PGMR3ChangeMode: Shadow mode: %s -> %s\n", PGMGetModeName(pVCpu->pgm.s.enmShadowMode), PGMGetModeName(enmShadowMode)));
3827	if (PGM_SHW_PFN(Exit, pVCpu))
3828	{
3829	int rc = PGM_SHW_PFN(Exit, pVCpu)(pVCpu);
3830	if (RT_FAILURE(rc))
3831	{
3832	AssertMsgFailed(("Exit failed for shadow mode %d: %Rrc\n", pVCpu->pgm.s.enmShadowMode, rc));
3833	return rc;
3834	}
3835	}
3836
3837	}
3838	else
3839	LogFlow(("PGMR3ChangeMode: Shadow mode remains: %s\n", PGMGetModeName(pVCpu->pgm.s.enmShadowMode)));
3840
3841	/* guest */
3842	if (PGM_GST_PFN(Exit, pVCpu))
3843	{
3844	int rc = PGM_GST_PFN(Exit, pVCpu)(pVCpu);
3845	if (RT_FAILURE(rc))
3846	{
3847	AssertMsgFailed(("Exit failed for guest mode %d: %Rrc\n", pVCpu->pgm.s.enmGuestMode, rc));
3848	return rc;
3849	}
3850	}
3851
3852	/*
3853	* Load new paging mode data.
3854	*/
3855	pgmR3ModeDataSwitch(pVM, pVCpu, enmShadowMode, enmGuestMode);
3856
3857	/*
3858	* Enter new shadow mode (if changed).
3859	*/
3860	if (enmShadowMode != pVCpu->pgm.s.enmShadowMode)
3861	{
3862	int rc;
3863	pVCpu->pgm.s.enmShadowMode = enmShadowMode;
3864	switch (enmShadowMode)
3865	{
3866	case PGMMODE_32_BIT:
3867	rc = PGM_SHW_NAME_32BIT(Enter)(pVCpu);
3868	break;
3869	case PGMMODE_PAE:
3870	case PGMMODE_PAE_NX:
3871	rc = PGM_SHW_NAME_PAE(Enter)(pVCpu);
3872	break;
3873	case PGMMODE_AMD64:
3874	case PGMMODE_AMD64_NX:
3875	rc = PGM_SHW_NAME_AMD64(Enter)(pVCpu);
3876	break;
3877	case PGMMODE_NESTED:
3878	rc = PGM_SHW_NAME_NESTED(Enter)(pVCpu);
3879	break;
3880	case PGMMODE_EPT:
3881	rc = PGM_SHW_NAME_EPT(Enter)(pVCpu);
3882	break;
3883	case PGMMODE_REAL:
3884	case PGMMODE_PROTECTED:
3885	default:
3886	AssertReleaseMsgFailed(("enmShadowMode=%d\n", enmShadowMode));
3887	return VERR_INTERNAL_ERROR;
3888	}
3889	if (RT_FAILURE(rc))
3890	{
3891	AssertReleaseMsgFailed(("Entering enmShadowMode=%d failed: %Rrc\n", enmShadowMode, rc));
3892	pVCpu->pgm.s.enmShadowMode = PGMMODE_INVALID;
3893	return rc;
3894	}
3895	}
3896
3897	/*
3898	* Always flag the necessary updates
3899	*/
3900	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
3901
3902	/*
3903	* Enter the new guest and shadow+guest modes.
3904	*/
3905	int rc = -1;
3906	int rc2 = -1;
3907	RTGCPHYS GCPhysCR3 = NIL_RTGCPHYS;
3908	pVCpu->pgm.s.enmGuestMode = enmGuestMode;
3909	switch (enmGuestMode)
3910	{
3911	case PGMMODE_REAL:
3912	rc = PGM_GST_NAME_REAL(Enter)(pVCpu, NIL_RTGCPHYS);
3913	switch (pVCpu->pgm.s.enmShadowMode)
3914	{
3915	case PGMMODE_32_BIT:
3916	rc2 = PGM_BTH_NAME_32BIT_REAL(Enter)(pVCpu, NIL_RTGCPHYS);
3917	break;
3918	case PGMMODE_PAE:
3919	case PGMMODE_PAE_NX:
3920	rc2 = PGM_BTH_NAME_PAE_REAL(Enter)(pVCpu, NIL_RTGCPHYS);
3921	break;
3922	case PGMMODE_NESTED:
3923	rc2 = PGM_BTH_NAME_NESTED_REAL(Enter)(pVCpu, NIL_RTGCPHYS);
3924	break;
3925	case PGMMODE_EPT:
3926	rc2 = PGM_BTH_NAME_EPT_REAL(Enter)(pVCpu, NIL_RTGCPHYS);
3927	break;
3928	case PGMMODE_AMD64:
3929	case PGMMODE_AMD64_NX:
3930	AssertMsgFailed(("Should use PAE shadow mode!\n"));
3931	default: AssertFailed(); break;
3932	}
3933	break;
3934
3935	case PGMMODE_PROTECTED:
3936	rc = PGM_GST_NAME_PROT(Enter)(pVCpu, NIL_RTGCPHYS);
3937	switch (pVCpu->pgm.s.enmShadowMode)
3938	{
3939	case PGMMODE_32_BIT:
3940	rc2 = PGM_BTH_NAME_32BIT_PROT(Enter)(pVCpu, NIL_RTGCPHYS);
3941	break;
3942	case PGMMODE_PAE:
3943	case PGMMODE_PAE_NX:
3944	rc2 = PGM_BTH_NAME_PAE_PROT(Enter)(pVCpu, NIL_RTGCPHYS);
3945	break;
3946	case PGMMODE_NESTED:
3947	rc2 = PGM_BTH_NAME_NESTED_PROT(Enter)(pVCpu, NIL_RTGCPHYS);
3948	break;
3949	case PGMMODE_EPT:
3950	rc2 = PGM_BTH_NAME_EPT_PROT(Enter)(pVCpu, NIL_RTGCPHYS);
3951	break;
3952	case PGMMODE_AMD64:
3953	case PGMMODE_AMD64_NX:
3954	AssertMsgFailed(("Should use PAE shadow mode!\n"));
3955	default: AssertFailed(); break;
3956	}
3957	break;
3958
3959	case PGMMODE_32_BIT:
3960	GCPhysCR3 = CPUMGetGuestCR3(pVCpu) & X86_CR3_PAGE_MASK;
3961	rc = PGM_GST_NAME_32BIT(Enter)(pVCpu, GCPhysCR3);
3962	switch (pVCpu->pgm.s.enmShadowMode)
3963	{
3964	case PGMMODE_32_BIT:
3965	rc2 = PGM_BTH_NAME_32BIT_32BIT(Enter)(pVCpu, GCPhysCR3);
3966	break;
3967	case PGMMODE_PAE:
3968	case PGMMODE_PAE_NX:
3969	rc2 = PGM_BTH_NAME_PAE_32BIT(Enter)(pVCpu, GCPhysCR3);
3970	break;
3971	case PGMMODE_NESTED:
3972	rc2 = PGM_BTH_NAME_NESTED_32BIT(Enter)(pVCpu, GCPhysCR3);
3973	break;
3974	case PGMMODE_EPT:
3975	rc2 = PGM_BTH_NAME_EPT_32BIT(Enter)(pVCpu, GCPhysCR3);
3976	break;
3977	case PGMMODE_AMD64:
3978	case PGMMODE_AMD64_NX:
3979	AssertMsgFailed(("Should use PAE shadow mode!\n"));
3980	default: AssertFailed(); break;
3981	}
3982	break;
3983
3984	case PGMMODE_PAE_NX:
3985	case PGMMODE_PAE:
3986	{
3987	uint32_t u32Dummy, u32Features;
3988
3989	CPUMGetGuestCpuId(pVCpu, 1, &u32Dummy, &u32Dummy, &u32Dummy, &u32Features);
3990	if (!(u32Features & X86_CPUID_FEATURE_EDX_PAE))
3991	return VMSetRuntimeError(pVM, VMSETRTERR_FLAGS_FATAL, "PAEmode",
3992	N_("The guest is trying to switch to the PAE mode which is currently disabled by default in VirtualBox. PAE support can be enabled using the VM settings (General/Advanced)"));
3993
3994	GCPhysCR3 = CPUMGetGuestCR3(pVCpu) & X86_CR3_PAE_PAGE_MASK;
3995	rc = PGM_GST_NAME_PAE(Enter)(pVCpu, GCPhysCR3);
3996	switch (pVCpu->pgm.s.enmShadowMode)
3997	{
3998	case PGMMODE_PAE:
3999	case PGMMODE_PAE_NX:
4000	rc2 = PGM_BTH_NAME_PAE_PAE(Enter)(pVCpu, GCPhysCR3);
4001	break;
4002	case PGMMODE_NESTED:
4003	rc2 = PGM_BTH_NAME_NESTED_PAE(Enter)(pVCpu, GCPhysCR3);
4004	break;
4005	case PGMMODE_EPT:
4006	rc2 = PGM_BTH_NAME_EPT_PAE(Enter)(pVCpu, GCPhysCR3);
4007	break;
4008	case PGMMODE_32_BIT:
4009	case PGMMODE_AMD64:
4010	case PGMMODE_AMD64_NX:
4011	AssertMsgFailed(("Should use PAE shadow mode!\n"));
4012	default: AssertFailed(); break;
4013	}
4014	break;
4015	}
4016
4017	#ifdef VBOX_WITH_64_BITS_GUESTS
4018	case PGMMODE_AMD64_NX:
4019	case PGMMODE_AMD64:
4020	GCPhysCR3 = CPUMGetGuestCR3(pVCpu) & UINT64_C(0xfffffffffffff000); /** @todo define this mask! */
4021	rc = PGM_GST_NAME_AMD64(Enter)(pVCpu, GCPhysCR3);
4022	switch (pVCpu->pgm.s.enmShadowMode)
4023	{
4024	case PGMMODE_AMD64:
4025	case PGMMODE_AMD64_NX:
4026	rc2 = PGM_BTH_NAME_AMD64_AMD64(Enter)(pVCpu, GCPhysCR3);
4027	break;
4028	case PGMMODE_NESTED:
4029	rc2 = PGM_BTH_NAME_NESTED_AMD64(Enter)(pVCpu, GCPhysCR3);
4030	break;
4031	case PGMMODE_EPT:
4032	rc2 = PGM_BTH_NAME_EPT_AMD64(Enter)(pVCpu, GCPhysCR3);
4033	break;
4034	case PGMMODE_32_BIT:
4035	case PGMMODE_PAE:
4036	case PGMMODE_PAE_NX:
4037	AssertMsgFailed(("Should use AMD64 shadow mode!\n"));
4038	default: AssertFailed(); break;
4039	}
4040	break;
4041	#endif
4042
4043	default:
4044	AssertReleaseMsgFailed(("enmGuestMode=%d\n", enmGuestMode));
4045	rc = VERR_NOT_IMPLEMENTED;
4046	break;
4047	}
4048
4049	/* status codes. */
4050	AssertRC(rc);
4051	AssertRC(rc2);
4052	if (RT_SUCCESS(rc))
4053	{
4054	rc = rc2;
4055	if (RT_SUCCESS(rc)) /* no informational status codes. */
4056	rc = VINF_SUCCESS;
4057	}
4058
4059	/* Notify HWACCM as well. */
4060	HWACCMR3PagingModeChanged(pVM, pVCpu, pVCpu->pgm.s.enmShadowMode, pVCpu->pgm.s.enmGuestMode);
4061	return rc;
4062	}
4063
4064	/**
4065	* Release the pgm lock if owned by the current VCPU
4066	*
4067	* @param pVM The VM to operate on.
4068	*/
4069	VMMR3DECL(void) PGMR3ReleaseOwnedLocks(PVM pVM)
4070	{
4071	while (PDMCritSectIsOwner(&pVM->pgm.s.CritSect))
4072	PDMCritSectLeave(&pVM->pgm.s.CritSect);
4073	}
4074
4075	/**
4076	* Called by pgmPoolFlushAllInt prior to flushing the pool.
4077	*
4078	* @returns VBox status code, fully asserted.
4079	* @param pVM The VM handle.
4080	* @param pVCpu The VMCPU to operate on.
4081	*/
4082	int pgmR3ExitShadowModeBeforePoolFlush(PVM pVM, PVMCPU pVCpu)
4083	{
4084	/* Unmap the old CR3 value before flushing everything. */
4085	int rc = PGM_BTH_PFN(UnmapCR3, pVCpu)(pVCpu);
4086	AssertRC(rc);
4087
4088	/* Exit the current shadow paging mode as well; nested paging and EPT use a root CR3 which will get flushed here. */
4089	rc = PGM_SHW_PFN(Exit, pVCpu)(pVCpu);
4090	AssertRC(rc);
4091	Assert(pVCpu->pgm.s.pShwPageCR3R3 == NULL);
4092	return rc;
4093	}
4094
4095
4096	/**
4097	* Called by pgmPoolFlushAllInt after flushing the pool.
4098	*
4099	* @returns VBox status code, fully asserted.
4100	* @param pVM The VM handle.
4101	* @param pVCpu The VMCPU to operate on.
4102	*/
4103	int pgmR3ReEnterShadowModeAfterPoolFlush(PVM pVM, PVMCPU pVCpu)
4104	{
4105	pVCpu->pgm.s.enmShadowMode = PGMMODE_INVALID;
4106	int rc = PGMR3ChangeMode(pVM, pVCpu, PGMGetGuestMode(pVCpu));
4107	Assert(VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
4108	AssertRCReturn(rc, rc);
4109	AssertRCSuccessReturn(rc, VERR_IPE_UNEXPECTED_INFO_STATUS);
4110
4111	Assert(pVCpu->pgm.s.pShwPageCR3R3 != NULL);
4112	AssertMsg( pVCpu->pgm.s.enmShadowMode >= PGMMODE_NESTED
4113	\|\| CPUMGetHyperCR3(pVCpu) == PGMGetHyperCR3(pVCpu),
4114	("%RHp != %RHp %s\n", (RTHCPHYS)CPUMGetHyperCR3(pVCpu), PGMGetHyperCR3(pVCpu), PGMGetModeName(pVCpu->pgm.s.enmShadowMode)));
4115	return rc;
4116	}
4117
4118
4119	/**
4120	* Dumps a PAE shadow page table.
4121	*
4122	* @returns VBox status code (VINF_SUCCESS).
4123	* @param pVM The VM handle.
4124	* @param pPT Pointer to the page table.
4125	* @param u64Address The virtual address of the page table starts.
4126	* @param fLongMode Set if this a long mode table; clear if it's a legacy mode table.
4127	* @param cMaxDepth The maxium depth.
4128	* @param pHlp Pointer to the output functions.
4129	*/
4130	static int pgmR3DumpHierarchyHCPaePT(PVM pVM, PX86PTPAE pPT, uint64_t u64Address, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
4131	{
4132	for (unsigned i = 0; i < RT_ELEMENTS(pPT->a); i++)
4133	{
4134	X86PTEPAE Pte = pPT->a[i];
4135	if (Pte.n.u1Present)
4136	{
4137	pHlp->pfnPrintf(pHlp,
4138	fLongMode /P R S A D G WT CD AT NX 4M a p ? /
4139	? "%016llx 3 \| P %c %c %c %c %c %s %s %s %s 4K %c%c%c %016llx\n"
4140	: "%08llx 2 \| P %c %c %c %c %c %s %s %s %s 4K %c%c%c %016llx\n",
4141	u64Address + ((uint64_t)i << X86_PT_PAE_SHIFT),
4142	Pte.n.u1Write ? 'W' : 'R',
4143	Pte.n.u1User ? 'U' : 'S',
4144	Pte.n.u1Accessed ? 'A' : '-',
4145	Pte.n.u1Dirty ? 'D' : '-',
4146	Pte.n.u1Global ? 'G' : '-',
4147	Pte.n.u1WriteThru ? "WT" : "--",
4148	Pte.n.u1CacheDisable? "CD" : "--",
4149	Pte.n.u1PAT ? "AT" : "--",
4150	Pte.n.u1NoExecute ? "NX" : "--",
4151	Pte.u & PGM_PTFLAGS_TRACK_DIRTY ? 'd' : '-',
4152	Pte.u & RT_BIT(10) ? '1' : '0',
4153	Pte.u & PGM_PTFLAGS_CSAM_VALIDATED? 'v' : '-',
4154	Pte.u & X86_PTE_PAE_PG_MASK);
4155	}
4156	}
4157	return VINF_SUCCESS;
4158	}
4159
4160
4161	/**
4162	* Dumps a PAE shadow page directory table.
4163	*
4164	* @returns VBox status code (VINF_SUCCESS).
4165	* @param pVM The VM handle.
4166	* @param HCPhys The physical address of the page directory table.
4167	* @param u64Address The virtual address of the page table starts.
4168	* @param cr4 The CR4, PSE is currently used.
4169	* @param fLongMode Set if this a long mode table; clear if it's a legacy mode table.
4170	* @param cMaxDepth The maxium depth.
4171	* @param pHlp Pointer to the output functions.
4172	*/
4173	static int pgmR3DumpHierarchyHCPaePD(PVM pVM, RTHCPHYS HCPhys, uint64_t u64Address, uint32_t cr4, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
4174	{
4175	PX86PDPAE pPD = (PX86PDPAE)MMPagePhys2Page(pVM, HCPhys);
4176	if (!pPD)
4177	{
4178	pHlp->pfnPrintf(pHlp, "%0*llx error! Page directory at HCPhys=%RHp was not found in the page pool!\n",
4179	fLongMode ? 16 : 8, u64Address, HCPhys);
4180	return VERR_INVALID_PARAMETER;
4181	}
4182	const bool fBigPagesSupported = fLongMode \|\| !!(cr4 & X86_CR4_PSE);
4183
4184	int rc = VINF_SUCCESS;
4185	for (unsigned i = 0; i < RT_ELEMENTS(pPD->a); i++)
4186	{
4187	X86PDEPAE Pde = pPD->a[i];
4188	if (Pde.n.u1Present)
4189	{
4190	if (fBigPagesSupported && Pde.b.u1Size)
4191	pHlp->pfnPrintf(pHlp,
4192	fLongMode /P R S A D G WT CD AT NX 4M a p ? /
4193	? "%016llx 2 \| P %c %c %c %c %c %s %s %s %s 4M %c%c%c %016llx\n"
4194	: "%08llx 1 \| P %c %c %c %c %c %s %s %s %s 4M %c%c%c %016llx\n",
4195	u64Address + ((uint64_t)i << X86_PD_PAE_SHIFT),
4196	Pde.b.u1Write ? 'W' : 'R',
4197	Pde.b.u1User ? 'U' : 'S',
4198	Pde.b.u1Accessed ? 'A' : '-',
4199	Pde.b.u1Dirty ? 'D' : '-',
4200	Pde.b.u1Global ? 'G' : '-',
4201	Pde.b.u1WriteThru ? "WT" : "--",
4202	Pde.b.u1CacheDisable? "CD" : "--",
4203	Pde.b.u1PAT ? "AT" : "--",
4204	Pde.b.u1NoExecute ? "NX" : "--",
4205	Pde.u & RT_BIT_64(9) ? '1' : '0',
4206	Pde.u & PGM_PDFLAGS_MAPPING ? 'm' : '-',
4207	Pde.u & PGM_PDFLAGS_TRACK_DIRTY ? 'd' : '-',
4208	Pde.u & X86_PDE_PAE_PG_MASK);
4209	else
4210	{
4211	pHlp->pfnPrintf(pHlp,
4212	fLongMode /P R S A D G WT CD AT NX 4M a p ? /
4213	? "%016llx 2 \| P %c %c %c %c %c %s %s .. %s 4K %c%c%c %016llx\n"
4214	: "%08llx 1 \| P %c %c %c %c %c %s %s .. %s 4K %c%c%c %016llx\n",
4215	u64Address + ((uint64_t)i << X86_PD_PAE_SHIFT),
4216	Pde.n.u1Write ? 'W' : 'R',
4217	Pde.n.u1User ? 'U' : 'S',
4218	Pde.n.u1Accessed ? 'A' : '-',
4219	Pde.n.u1Reserved0 ? '?' : '.', /* ignored */
4220	Pde.n.u1Reserved1 ? '?' : '.', /* ignored */
4221	Pde.n.u1WriteThru ? "WT" : "--",
4222	Pde.n.u1CacheDisable? "CD" : "--",
4223	Pde.n.u1NoExecute ? "NX" : "--",
4224	Pde.u & RT_BIT_64(9) ? '1' : '0',
4225	Pde.u & PGM_PDFLAGS_MAPPING ? 'm' : '-',
4226	Pde.u & PGM_PDFLAGS_TRACK_DIRTY ? 'd' : '-',
4227	Pde.u & X86_PDE_PAE_PG_MASK);
4228	if (cMaxDepth >= 1)
4229	{
4230	/** @todo what about using the page pool for mapping PTs? */
4231	uint64_t u64AddressPT = u64Address + ((uint64_t)i << X86_PD_PAE_SHIFT);
4232	RTHCPHYS HCPhysPT = Pde.u & X86_PDE_PAE_PG_MASK;
4233	PX86PTPAE pPT = NULL;
4234	if (!(Pde.u & PGM_PDFLAGS_MAPPING))
4235	pPT = (PX86PTPAE)MMPagePhys2Page(pVM, HCPhysPT);
4236	else
4237	{
4238	for (PPGMMAPPING pMap = pVM->pgm.s.pMappingsR3; pMap; pMap = pMap->pNextR3)
4239	{
4240	uint64_t off = u64AddressPT - pMap->GCPtr;
4241	if (off < pMap->cb)
4242	{
4243	const int iPDE = (uint32_t)(off >> X86_PD_SHIFT);
4244	const int iSub = (int)((off >> X86_PD_PAE_SHIFT) & 1); /* MSC is a pain sometimes */
4245	if ((iSub ? pMap->aPTs[iPDE].HCPhysPaePT1 : pMap->aPTs[iPDE].HCPhysPaePT0) != HCPhysPT)
4246	pHlp->pfnPrintf(pHlp, "%0*llx error! Mapping error! PT %d has HCPhysPT=%RHp not %RHp is in the PD.\n",
4247	fLongMode ? 16 : 8, u64AddressPT, iPDE,
4248	iSub ? pMap->aPTs[iPDE].HCPhysPaePT1 : pMap->aPTs[iPDE].HCPhysPaePT0, HCPhysPT);
4249	pPT = &pMap->aPTs[iPDE].paPaePTsR3[iSub];
4250	}
4251	}
4252	}
4253	int rc2 = VERR_INVALID_PARAMETER;
4254	if (pPT)
4255	rc2 = pgmR3DumpHierarchyHCPaePT(pVM, pPT, u64AddressPT, fLongMode, cMaxDepth - 1, pHlp);
4256	else
4257	pHlp->pfnPrintf(pHlp, "%0*llx error! Page table at HCPhys=%RHp was not found in the page pool!\n",
4258	fLongMode ? 16 : 8, u64AddressPT, HCPhysPT);
4259	if (rc2 < rc && RT_SUCCESS(rc))
4260	rc = rc2;
4261	}
4262	}
4263	}
4264	}
4265	return rc;
4266	}
4267
4268
4269	/**
4270	* Dumps a PAE shadow page directory pointer table.
4271	*
4272	* @returns VBox status code (VINF_SUCCESS).
4273	* @param pVM The VM handle.
4274	* @param HCPhys The physical address of the page directory pointer table.
4275	* @param u64Address The virtual address of the page table starts.
4276	* @param cr4 The CR4, PSE is currently used.
4277	* @param fLongMode Set if this a long mode table; clear if it's a legacy mode table.
4278	* @param cMaxDepth The maxium depth.
4279	* @param pHlp Pointer to the output functions.
4280	*/
4281	static int pgmR3DumpHierarchyHCPaePDPT(PVM pVM, RTHCPHYS HCPhys, uint64_t u64Address, uint32_t cr4, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
4282	{
4283	PX86PDPT pPDPT = (PX86PDPT)MMPagePhys2Page(pVM, HCPhys);
4284	if (!pPDPT)
4285	{
4286	pHlp->pfnPrintf(pHlp, "%0*llx error! Page directory pointer table at HCPhys=%RHp was not found in the page pool!\n",
4287	fLongMode ? 16 : 8, u64Address, HCPhys);
4288	return VERR_INVALID_PARAMETER;
4289	}
4290
4291	int rc = VINF_SUCCESS;
4292	const unsigned c = fLongMode ? RT_ELEMENTS(pPDPT->a) : X86_PG_PAE_PDPE_ENTRIES;
4293	for (unsigned i = 0; i < c; i++)
4294	{
4295	X86PDPE Pdpe = pPDPT->a[i];
4296	if (Pdpe.n.u1Present)
4297	{
4298	if (fLongMode)
4299	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a p ? /
4300	"%016llx 1 \| P %c %c %c %c %c %s %s %s %s .. %c%c%c %016llx\n",
4301	u64Address + ((uint64_t)i << X86_PDPT_SHIFT),
4302	Pdpe.lm.u1Write ? 'W' : 'R',
4303	Pdpe.lm.u1User ? 'U' : 'S',
4304	Pdpe.lm.u1Accessed ? 'A' : '-',
4305	Pdpe.lm.u3Reserved & 1? '?' : '.', /* ignored */
4306	Pdpe.lm.u3Reserved & 4? '!' : '.', /* mbz */
4307	Pdpe.lm.u1WriteThru ? "WT" : "--",
4308	Pdpe.lm.u1CacheDisable? "CD" : "--",
4309	Pdpe.lm.u3Reserved & 2? "!" : "..",/* mbz */
4310	Pdpe.lm.u1NoExecute ? "NX" : "--",
4311	Pdpe.u & RT_BIT(9) ? '1' : '0',
4312	Pdpe.u & PGM_PLXFLAGS_PERMANENT ? 'p' : '-',
4313	Pdpe.u & RT_BIT(11) ? '1' : '0',
4314	Pdpe.u & X86_PDPE_PG_MASK);
4315	else
4316	pHlp->pfnPrintf(pHlp, /P G WT CD AT NX 4M a p ? /
4317	"%08x 0 \| P %c %s %s %s %s .. %c%c%c %016llx\n",
4318	i << X86_PDPT_SHIFT,
4319	Pdpe.n.u4Reserved & 1? '!' : '.', /* mbz */
4320	Pdpe.n.u4Reserved & 4? '!' : '.', /* mbz */
4321	Pdpe.n.u1WriteThru ? "WT" : "--",
4322	Pdpe.n.u1CacheDisable? "CD" : "--",
4323	Pdpe.n.u4Reserved & 2? "!" : "..",/* mbz */
4324	Pdpe.u & RT_BIT(9) ? '1' : '0',
4325	Pdpe.u & PGM_PLXFLAGS_PERMANENT ? 'p' : '-',
4326	Pdpe.u & RT_BIT(11) ? '1' : '0',
4327	Pdpe.u & X86_PDPE_PG_MASK);
4328	if (cMaxDepth >= 1)
4329	{
4330	int rc2 = pgmR3DumpHierarchyHCPaePD(pVM, Pdpe.u & X86_PDPE_PG_MASK, u64Address + ((uint64_t)i << X86_PDPT_SHIFT),
4331	cr4, fLongMode, cMaxDepth - 1, pHlp);
4332	if (rc2 < rc && RT_SUCCESS(rc))
4333	rc = rc2;
4334	}
4335	}
4336	}
4337	return rc;
4338	}
4339
4340
4341	/**
4342	* Dumps a 32-bit shadow page table.
4343	*
4344	* @returns VBox status code (VINF_SUCCESS).
4345	* @param pVM The VM handle.
4346	* @param HCPhys The physical address of the table.
4347	* @param cr4 The CR4, PSE is currently used.
4348	* @param cMaxDepth The maxium depth.
4349	* @param pHlp Pointer to the output functions.
4350	*/
4351	static int pgmR3DumpHierarchyHcPaePML4(PVM pVM, RTHCPHYS HCPhys, uint32_t cr4, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
4352	{
4353	PX86PML4 pPML4 = (PX86PML4)MMPagePhys2Page(pVM, HCPhys);
4354	if (!pPML4)
4355	{
4356	pHlp->pfnPrintf(pHlp, "Page map level 4 at HCPhys=%RHp was not found in the page pool!\n", HCPhys);
4357	return VERR_INVALID_PARAMETER;
4358	}
4359
4360	int rc = VINF_SUCCESS;
4361	for (unsigned i = 0; i < RT_ELEMENTS(pPML4->a); i++)
4362	{
4363	X86PML4E Pml4e = pPML4->a[i];
4364	if (Pml4e.n.u1Present)
4365	{
4366	uint64_t u64Address = ((uint64_t)i << X86_PML4_SHIFT) \| (((uint64_t)i >> (X86_PML4_SHIFT - X86_PDPT_SHIFT - 1)) * 0xffff000000000000ULL);
4367	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a p ? /
4368	"%016llx 0 \| P %c %c %c %c %c %s %s %s %s .. %c%c%c %016llx\n",
4369	u64Address,
4370	Pml4e.n.u1Write ? 'W' : 'R',
4371	Pml4e.n.u1User ? 'U' : 'S',
4372	Pml4e.n.u1Accessed ? 'A' : '-',
4373	Pml4e.n.u3Reserved & 1? '?' : '.', /* ignored */
4374	Pml4e.n.u3Reserved & 4? '!' : '.', /* mbz */
4375	Pml4e.n.u1WriteThru ? "WT" : "--",
4376	Pml4e.n.u1CacheDisable? "CD" : "--",
4377	Pml4e.n.u3Reserved & 2? "!" : "..",/* mbz */
4378	Pml4e.n.u1NoExecute ? "NX" : "--",
4379	Pml4e.u & RT_BIT(9) ? '1' : '0',
4380	Pml4e.u & PGM_PLXFLAGS_PERMANENT ? 'p' : '-',
4381	Pml4e.u & RT_BIT(11) ? '1' : '0',
4382	Pml4e.u & X86_PML4E_PG_MASK);
4383
4384	if (cMaxDepth >= 1)
4385	{
4386	int rc2 = pgmR3DumpHierarchyHCPaePDPT(pVM, Pml4e.u & X86_PML4E_PG_MASK, u64Address, cr4, true, cMaxDepth - 1, pHlp);
4387	if (rc2 < rc && RT_SUCCESS(rc))
4388	rc = rc2;
4389	}
4390	}
4391	}
4392	return rc;
4393	}
4394
4395
4396	/**
4397	* Dumps a 32-bit shadow page table.
4398	*
4399	* @returns VBox status code (VINF_SUCCESS).
4400	* @param pVM The VM handle.
4401	* @param pPT Pointer to the page table.
4402	* @param u32Address The virtual address this table starts at.
4403	* @param pHlp Pointer to the output functions.
4404	*/
4405	int pgmR3DumpHierarchyHC32BitPT(PVM pVM, PX86PT pPT, uint32_t u32Address, PCDBGFINFOHLP pHlp)
4406	{
4407	for (unsigned i = 0; i < RT_ELEMENTS(pPT->a); i++)
4408	{
4409	X86PTE Pte = pPT->a[i];
4410	if (Pte.n.u1Present)
4411	{
4412	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a m d /
4413	"%08x 1 \| P %c %c %c %c %c %s %s %s .. 4K %c%c%c %08x\n",
4414	u32Address + (i << X86_PT_SHIFT),
4415	Pte.n.u1Write ? 'W' : 'R',
4416	Pte.n.u1User ? 'U' : 'S',
4417	Pte.n.u1Accessed ? 'A' : '-',
4418	Pte.n.u1Dirty ? 'D' : '-',
4419	Pte.n.u1Global ? 'G' : '-',
4420	Pte.n.u1WriteThru ? "WT" : "--",
4421	Pte.n.u1CacheDisable? "CD" : "--",
4422	Pte.n.u1PAT ? "AT" : "--",
4423	Pte.u & PGM_PTFLAGS_TRACK_DIRTY ? 'd' : '-',
4424	Pte.u & RT_BIT(10) ? '1' : '0',
4425	Pte.u & PGM_PTFLAGS_CSAM_VALIDATED ? 'v' : '-',
4426	Pte.u & X86_PDE_PG_MASK);
4427	}
4428	}
4429	return VINF_SUCCESS;
4430	}
4431
4432
4433	/**
4434	* Dumps a 32-bit shadow page directory and page tables.
4435	*
4436	* @returns VBox status code (VINF_SUCCESS).
4437	* @param pVM The VM handle.
4438	* @param cr3 The root of the hierarchy.
4439	* @param cr4 The CR4, PSE is currently used.
4440	* @param cMaxDepth How deep into the hierarchy the dumper should go.
4441	* @param pHlp Pointer to the output functions.
4442	*/
4443	int pgmR3DumpHierarchyHC32BitPD(PVM pVM, uint32_t cr3, uint32_t cr4, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
4444	{
4445	PX86PD pPD = (PX86PD)MMPagePhys2Page(pVM, cr3 & X86_CR3_PAGE_MASK);
4446	if (!pPD)
4447	{
4448	pHlp->pfnPrintf(pHlp, "Page directory at %#x was not found in the page pool!\n", cr3 & X86_CR3_PAGE_MASK);
4449	return VERR_INVALID_PARAMETER;
4450	}
4451
4452	int rc = VINF_SUCCESS;
4453	for (unsigned i = 0; i < RT_ELEMENTS(pPD->a); i++)
4454	{
4455	X86PDE Pde = pPD->a[i];
4456	if (Pde.n.u1Present)
4457	{
4458	const uint32_t u32Address = i << X86_PD_SHIFT;
4459	if ((cr4 & X86_CR4_PSE) && Pde.b.u1Size)
4460	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a m d /
4461	"%08x 0 \| P %c %c %c %c %c %s %s %s .. 4M %c%c%c %08x\n",
4462	u32Address,
4463	Pde.b.u1Write ? 'W' : 'R',
4464	Pde.b.u1User ? 'U' : 'S',
4465	Pde.b.u1Accessed ? 'A' : '-',
4466	Pde.b.u1Dirty ? 'D' : '-',
4467	Pde.b.u1Global ? 'G' : '-',
4468	Pde.b.u1WriteThru ? "WT" : "--",
4469	Pde.b.u1CacheDisable? "CD" : "--",
4470	Pde.b.u1PAT ? "AT" : "--",
4471	Pde.u & RT_BIT_64(9) ? '1' : '0',
4472	Pde.u & PGM_PDFLAGS_MAPPING ? 'm' : '-',
4473	Pde.u & PGM_PDFLAGS_TRACK_DIRTY ? 'd' : '-',
4474	Pde.u & X86_PDE4M_PG_MASK);
4475	else
4476	{
4477	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a m d /
4478	"%08x 0 \| P %c %c %c %c %c %s %s .. .. 4K %c%c%c %08x\n",
4479	u32Address,
4480	Pde.n.u1Write ? 'W' : 'R',
4481	Pde.n.u1User ? 'U' : 'S',
4482	Pde.n.u1Accessed ? 'A' : '-',
4483	Pde.n.u1Reserved0 ? '?' : '.', /* ignored */
4484	Pde.n.u1Reserved1 ? '?' : '.', /* ignored */
4485	Pde.n.u1WriteThru ? "WT" : "--",
4486	Pde.n.u1CacheDisable? "CD" : "--",
4487	Pde.u & RT_BIT_64(9) ? '1' : '0',
4488	Pde.u & PGM_PDFLAGS_MAPPING ? 'm' : '-',
4489	Pde.u & PGM_PDFLAGS_TRACK_DIRTY ? 'd' : '-',
4490	Pde.u & X86_PDE_PG_MASK);
4491	if (cMaxDepth >= 1)
4492	{
4493	/** @todo what about using the page pool for mapping PTs? */
4494	RTHCPHYS HCPhys = Pde.u & X86_PDE_PG_MASK;
4495	PX86PT pPT = NULL;
4496	if (!(Pde.u & PGM_PDFLAGS_MAPPING))
4497	pPT = (PX86PT)MMPagePhys2Page(pVM, HCPhys);
4498	else
4499	{
4500	for (PPGMMAPPING pMap = pVM->pgm.s.pMappingsR3; pMap; pMap = pMap->pNextR3)
4501	if (u32Address - pMap->GCPtr < pMap->cb)
4502	{
4503	int iPDE = (u32Address - pMap->GCPtr) >> X86_PD_SHIFT;
4504	if (pMap->aPTs[iPDE].HCPhysPT != HCPhys)
4505	pHlp->pfnPrintf(pHlp, "%08x error! Mapping error! PT %d has HCPhysPT=%RHp not %RHp is in the PD.\n",
4506	u32Address, iPDE, pMap->aPTs[iPDE].HCPhysPT, HCPhys);
4507	pPT = pMap->aPTs[iPDE].pPTR3;
4508	}
4509	}
4510	int rc2 = VERR_INVALID_PARAMETER;
4511	if (pPT)
4512	rc2 = pgmR3DumpHierarchyHC32BitPT(pVM, pPT, u32Address, pHlp);
4513	else
4514	pHlp->pfnPrintf(pHlp, "%08x error! Page table at %#x was not found in the page pool!\n", u32Address, HCPhys);
4515	if (rc2 < rc && RT_SUCCESS(rc))
4516	rc = rc2;
4517	}
4518	}
4519	}
4520	}
4521
4522	return rc;
4523	}
4524
4525
4526	/**
4527	* Dumps a 32-bit shadow page table.
4528	*
4529	* @returns VBox status code (VINF_SUCCESS).
4530	* @param pVM The VM handle.
4531	* @param pPT Pointer to the page table.
4532	* @param u32Address The virtual address this table starts at.
4533	* @param PhysSearch Address to search for.
4534	*/
4535	int pgmR3DumpHierarchyGC32BitPT(PVM pVM, PX86PT pPT, uint32_t u32Address, RTGCPHYS PhysSearch)
4536	{
4537	for (unsigned i = 0; i < RT_ELEMENTS(pPT->a); i++)
4538	{
4539	X86PTE Pte = pPT->a[i];
4540	if (Pte.n.u1Present)
4541	{
4542	Log(( /P R S A D G WT CD AT NX 4M a m d /
4543	"%08x 1 \| P %c %c %c %c %c %s %s %s .. 4K %c%c%c %08x\n",
4544	u32Address + (i << X86_PT_SHIFT),
4545	Pte.n.u1Write ? 'W' : 'R',
4546	Pte.n.u1User ? 'U' : 'S',
4547	Pte.n.u1Accessed ? 'A' : '-',
4548	Pte.n.u1Dirty ? 'D' : '-',
4549	Pte.n.u1Global ? 'G' : '-',
4550	Pte.n.u1WriteThru ? "WT" : "--",
4551	Pte.n.u1CacheDisable? "CD" : "--",
4552	Pte.n.u1PAT ? "AT" : "--",
4553	Pte.u & PGM_PTFLAGS_TRACK_DIRTY ? 'd' : '-',
4554	Pte.u & RT_BIT(10) ? '1' : '0',
4555	Pte.u & PGM_PTFLAGS_CSAM_VALIDATED ? 'v' : '-',
4556	Pte.u & X86_PDE_PG_MASK));
4557
4558	if ((Pte.u & X86_PDE_PG_MASK) == PhysSearch)
4559	{
4560	uint64_t fPageShw = 0;
4561	RTHCPHYS pPhysHC = 0;
4562
4563	/** @todo SMP support!! */
4564	PGMShwGetPage(&pVM->aCpus[0], (RTGCPTR)(u32Address + (i << X86_PT_SHIFT)), &fPageShw, &pPhysHC);
4565	Log(("Found %RGp at %RGv -> flags=%llx\n", PhysSearch, (RTGCPTR)(u32Address + (i << X86_PT_SHIFT)), fPageShw));
4566	}
4567	}
4568	}
4569	return VINF_SUCCESS;
4570	}
4571
4572
4573	/**
4574	* Dumps a 32-bit guest page directory and page tables.
4575	*
4576	* @returns VBox status code (VINF_SUCCESS).
4577	* @param pVM The VM handle.
4578	* @param cr3 The root of the hierarchy.
4579	* @param cr4 The CR4, PSE is currently used.
4580	* @param PhysSearch Address to search for.
4581	*/
4582	VMMR3DECL(int) PGMR3DumpHierarchyGC(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCPHYS PhysSearch)
4583	{
4584	bool fLongMode = false;
4585	const unsigned cch = fLongMode ? 16 : 8; NOREF(cch);
4586	PX86PD pPD = 0;
4587
4588	int rc = PGM_GCPHYS_2_PTR(pVM, cr3 & X86_CR3_PAGE_MASK, &pPD);
4589	if (RT_FAILURE(rc) \|\| !pPD)
4590	{
4591	Log(("Page directory at %#x was not found in the page pool!\n", cr3 & X86_CR3_PAGE_MASK));
4592	return VERR_INVALID_PARAMETER;
4593	}
4594
4595	Log(("cr3=%08x cr4=%08x%s\n"
4596	"%-*s P - Present\n"
4597	"%-*s \| R/W - Read (0) / Write (1)\n"
4598	"%-*s \| \| U/S - User (1) / Supervisor (0)\n"
4599	"%-*s \| \| \| A - Accessed\n"
4600	"%-*s \| \| \| \| D - Dirty\n"
4601	"%-*s \| \| \| \| \| G - Global\n"
4602	"%-*s \| \| \| \| \| \| WT - Write thru\n"
4603	"%-*s \| \| \| \| \| \| \| CD - Cache disable\n"
4604	"%-*s \| \| \| \| \| \| \| \| AT - Attribute table (PAT)\n"
4605	"%-*s \| \| \| \| \| \| \| \| \| NX - No execute (K8)\n"
4606	"%-*s \| \| \| \| \| \| \| \| \| \| 4K/4M/2M - Page size.\n"
4607	"%-*s \| \| \| \| \| \| \| \| \| \| \| AVL - a=allocated; m=mapping; d=track dirty;\n"
4608	"%-*s \| \| \| \| \| \| \| \| \| \| \| \| p=permanent; v=validated;\n"
4609	"%-*s Level \| \| \| \| \| \| \| \| \| \| \| \| Page\n"
4610	/* xxxx n **** P R S A D G WT CD AT NX 4M AVL xxxxxxxxxxxxx
4611	- W U - - - -- -- -- -- -- 010 */
4612	, cr3, cr4, fLongMode ? " Long Mode" : "",
4613	cch, "", cch, "", cch, "", cch, "", cch, "", cch, "", cch, "",
4614	cch, "", cch, "", cch, "", cch, "", cch, "", cch, "", cch, "Address"));
4615
4616	for (unsigned i = 0; i < RT_ELEMENTS(pPD->a); i++)
4617	{
4618	X86PDE Pde = pPD->a[i];
4619	if (Pde.n.u1Present)
4620	{
4621	const uint32_t u32Address = i << X86_PD_SHIFT;
4622
4623	if ((cr4 & X86_CR4_PSE) && Pde.b.u1Size)
4624	Log(( /P R S A D G WT CD AT NX 4M a m d /
4625	"%08x 0 \| P %c %c %c %c %c %s %s %s .. 4M %c%c%c %08x\n",
4626	u32Address,
4627	Pde.b.u1Write ? 'W' : 'R',
4628	Pde.b.u1User ? 'U' : 'S',
4629	Pde.b.u1Accessed ? 'A' : '-',
4630	Pde.b.u1Dirty ? 'D' : '-',
4631	Pde.b.u1Global ? 'G' : '-',
4632	Pde.b.u1WriteThru ? "WT" : "--",
4633	Pde.b.u1CacheDisable? "CD" : "--",
4634	Pde.b.u1PAT ? "AT" : "--",
4635	Pde.u & RT_BIT(9) ? '1' : '0',
4636	Pde.u & RT_BIT(10) ? '1' : '0',
4637	Pde.u & RT_BIT(11) ? '1' : '0',
4638	pgmGstGet4MBPhysPage(&pVM->pgm.s, Pde)));
4639	/** @todo PhysSearch */
4640	else
4641	{
4642	Log(( /P R S A D G WT CD AT NX 4M a m d /
4643	"%08x 0 \| P %c %c %c %c %c %s %s .. .. 4K %c%c%c %08x\n",
4644	u32Address,
4645	Pde.n.u1Write ? 'W' : 'R',
4646	Pde.n.u1User ? 'U' : 'S',
4647	Pde.n.u1Accessed ? 'A' : '-',
4648	Pde.n.u1Reserved0 ? '?' : '.', /* ignored */
4649	Pde.n.u1Reserved1 ? '?' : '.', /* ignored */
4650	Pde.n.u1WriteThru ? "WT" : "--",
4651	Pde.n.u1CacheDisable? "CD" : "--",
4652	Pde.u & RT_BIT(9) ? '1' : '0',
4653	Pde.u & RT_BIT(10) ? '1' : '0',
4654	Pde.u & RT_BIT(11) ? '1' : '0',
4655	Pde.u & X86_PDE_PG_MASK));
4656	////if (cMaxDepth >= 1)
4657	{
4658	/** @todo what about using the page pool for mapping PTs? */
4659	RTGCPHYS GCPhys = Pde.u & X86_PDE_PG_MASK;
4660	PX86PT pPT = NULL;
4661
4662	rc = PGM_GCPHYS_2_PTR(pVM, GCPhys, &pPT);
4663
4664	int rc2 = VERR_INVALID_PARAMETER;
4665	if (pPT)
4666	rc2 = pgmR3DumpHierarchyGC32BitPT(pVM, pPT, u32Address, PhysSearch);
4667	else
4668	Log(("%08x error! Page table at %#x was not found in the page pool!\n", u32Address, GCPhys));
4669	if (rc2 < rc && RT_SUCCESS(rc))
4670	rc = rc2;
4671	}
4672	}
4673	}
4674	}
4675
4676	return rc;
4677	}
4678
4679
4680	/**
4681	* Dumps a page table hierarchy use only physical addresses and cr4/lm flags.
4682	*
4683	* @returns VBox status code (VINF_SUCCESS).
4684	* @param pVM The VM handle.
4685	* @param cr3 The root of the hierarchy.
4686	* @param cr4 The cr4, only PAE and PSE is currently used.
4687	* @param fLongMode Set if long mode, false if not long mode.
4688	* @param cMaxDepth Number of levels to dump.
4689	* @param pHlp Pointer to the output functions.
4690	*/
4691	VMMR3DECL(int) PGMR3DumpHierarchyHC(PVM pVM, uint64_t cr3, uint64_t cr4, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
4692	{
4693	if (!pHlp)
4694	pHlp = DBGFR3InfoLogHlp();
4695	if (!cMaxDepth)
4696	return VINF_SUCCESS;
4697	const unsigned cch = fLongMode ? 16 : 8;
4698	pHlp->pfnPrintf(pHlp,
4699	"cr3=%08x cr4=%08x%s\n"
4700	"%-*s P - Present\n"
4701	"%-*s \| R/W - Read (0) / Write (1)\n"
4702	"%-*s \| \| U/S - User (1) / Supervisor (0)\n"
4703	"%-*s \| \| \| A - Accessed\n"
4704	"%-*s \| \| \| \| D - Dirty\n"
4705	"%-*s \| \| \| \| \| G - Global\n"
4706	"%-*s \| \| \| \| \| \| WT - Write thru\n"
4707	"%-*s \| \| \| \| \| \| \| CD - Cache disable\n"
4708	"%-*s \| \| \| \| \| \| \| \| AT - Attribute table (PAT)\n"
4709	"%-*s \| \| \| \| \| \| \| \| \| NX - No execute (K8)\n"
4710	"%-*s \| \| \| \| \| \| \| \| \| \| 4K/4M/2M - Page size.\n"
4711	"%-*s \| \| \| \| \| \| \| \| \| \| \| AVL - a=allocated; m=mapping; d=track dirty;\n"
4712	"%-*s \| \| \| \| \| \| \| \| \| \| \| \| p=permanent; v=validated;\n"
4713	"%-*s Level \| \| \| \| \| \| \| \| \| \| \| \| Page\n"
4714	/* xxxx n **** P R S A D G WT CD AT NX 4M AVL xxxxxxxxxxxxx
4715	- W U - - - -- -- -- -- -- 010 */
4716	, cr3, cr4, fLongMode ? " Long Mode" : "",
4717	cch, "", cch, "", cch, "", cch, "", cch, "", cch, "", cch, "",
4718	cch, "", cch, "", cch, "", cch, "", cch, "", cch, "", cch, "Address");
4719	if (cr4 & X86_CR4_PAE)
4720	{
4721	if (fLongMode)
4722	return pgmR3DumpHierarchyHcPaePML4(pVM, cr3 & X86_CR3_PAGE_MASK, cr4, cMaxDepth, pHlp);
4723	return pgmR3DumpHierarchyHCPaePDPT(pVM, cr3 & X86_CR3_PAE_PAGE_MASK, 0, cr4, false, cMaxDepth, pHlp);
4724	}
4725	return pgmR3DumpHierarchyHC32BitPD(pVM, cr3 & X86_CR3_PAGE_MASK, cr4, cMaxDepth, pHlp);
4726	}
4727
4728	#ifdef VBOX_WITH_DEBUGGER
4729
4730	/**
4731	* The '.pgmram' command.
4732	*
4733	* @returns VBox status.
4734	* @param pCmd Pointer to the command descriptor (as registered).
4735	* @param pCmdHlp Pointer to command helper functions.
4736	* @param pVM Pointer to the current VM (if any).
4737	* @param paArgs Pointer to (readonly) array of arguments.
4738	* @param cArgs Number of arguments in the array.
4739	*/
4740	static DECLCALLBACK(int) pgmR3CmdRam(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4741	{
4742	/*
4743	* Validate input.
4744	*/
4745	if (!pVM)
4746	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4747	if (!pVM->pgm.s.pRamRangesRC)
4748	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Sorry, no Ram is registered.\n");
4749
4750	/*
4751	* Dump the ranges.
4752	*/
4753	int rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL, "From - To (incl) pvHC\n");
4754	PPGMRAMRANGE pRam;
4755	for (pRam = pVM->pgm.s.pRamRangesR3; pRam; pRam = pRam->pNextR3)
4756	{
4757	rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL,
4758	"%RGp - %RGp %p\n",
4759	pRam->GCPhys, pRam->GCPhysLast, pRam->pvR3);
4760	if (RT_FAILURE(rc))
4761	return rc;
4762	}
4763
4764	return VINF_SUCCESS;
4765	}
4766
4767
4768	/**
4769	* The '.pgmmap' command.
4770	*
4771	* @returns VBox status.
4772	* @param pCmd Pointer to the command descriptor (as registered).
4773	* @param pCmdHlp Pointer to command helper functions.
4774	* @param pVM Pointer to the current VM (if any).
4775	* @param paArgs Pointer to (readonly) array of arguments.
4776	* @param cArgs Number of arguments in the array.
4777	*/
4778	static DECLCALLBACK(int) pgmR3CmdMap(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4779	{
4780	/*
4781	* Validate input.
4782	*/
4783	if (!pVM)
4784	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4785	if (!pVM->pgm.s.pMappingsR3)
4786	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Sorry, no mappings are registered.\n");
4787
4788	/*
4789	* Print message about the fixedness of the mappings.
4790	*/
4791	int rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL, pVM->pgm.s.fMappingsFixed ? "The mappings are FIXED.\n" : "The mappings are FLOATING.\n");
4792	if (RT_FAILURE(rc))
4793	return rc;
4794
4795	/*
4796	* Dump the ranges.
4797	*/
4798	PPGMMAPPING pCur;
4799	for (pCur = pVM->pgm.s.pMappingsR3; pCur; pCur = pCur->pNextR3)
4800	{
4801	rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL,
4802	"%08x - %08x %s\n",
4803	pCur->GCPtr, pCur->GCPtrLast, pCur->pszDesc);
4804	if (RT_FAILURE(rc))
4805	return rc;
4806	}
4807
4808	return VINF_SUCCESS;
4809	}
4810
4811
4812	/**
4813	* The '.pgmerror' and '.pgmerroroff' commands.
4814	*
4815	* @returns VBox status.
4816	* @param pCmd Pointer to the command descriptor (as registered).
4817	* @param pCmdHlp Pointer to command helper functions.
4818	* @param pVM Pointer to the current VM (if any).
4819	* @param paArgs Pointer to (readonly) array of arguments.
4820	* @param cArgs Number of arguments in the array.
4821	*/
4822	static DECLCALLBACK(int) pgmR3CmdError(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4823	{
4824	/*
4825	* Validate input.
4826	*/
4827	if (!pVM)
4828	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4829	AssertReturn(cArgs == 0 \|\| (cArgs == 1 && paArgs[0].enmType == DBGCVAR_TYPE_STRING),
4830	pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: Hit bug in the parser.\n"));
4831
4832	if (!cArgs)
4833	{
4834	/*
4835	* Print the list of error injection locations with status.
4836	*/
4837	pCmdHlp->pfnPrintf(pCmdHlp, NULL, "PGM error inject locations:\n");
4838	pCmdHlp->pfnPrintf(pCmdHlp, NULL, " handy - %RTbool\n", pVM->pgm.s.fErrInjHandyPages);
4839	}
4840	else
4841	{
4842
4843	/*
4844	* String switch on where to inject the error.
4845	*/
4846	bool const fNewState = !strcmp(pCmd->pszCmd, "pgmerror");
4847	const char *pszWhere = paArgs[0].u.pszString;
4848	if (!strcmp(pszWhere, "handy"))
4849	ASMAtomicWriteBool(&pVM->pgm.s.fErrInjHandyPages, fNewState);
4850	else
4851	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: Invalid 'where' value: %s.\n", pszWhere);
4852	pCmdHlp->pfnPrintf(pCmdHlp, NULL, "done\n");
4853	}
4854	return VINF_SUCCESS;
4855	}
4856
4857
4858	/**
4859	* The '.pgmsync' command.
4860	*
4861	* @returns VBox status.
4862	* @param pCmd Pointer to the command descriptor (as registered).
4863	* @param pCmdHlp Pointer to command helper functions.
4864	* @param pVM Pointer to the current VM (if any).
4865	* @param paArgs Pointer to (readonly) array of arguments.
4866	* @param cArgs Number of arguments in the array.
4867	*/
4868	static DECLCALLBACK(int) pgmR3CmdSync(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4869	{
4870	/** @todo SMP support */
4871	PVMCPU pVCpu = &pVM->aCpus[0];
4872
4873	/*
4874	* Validate input.
4875	*/
4876	if (!pVM)
4877	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4878
4879	/*
4880	* Force page directory sync.
4881	*/
4882	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
4883
4884	int rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Forcing page directory sync.\n");
4885	if (RT_FAILURE(rc))
4886	return rc;
4887
4888	return VINF_SUCCESS;
4889	}
4890
4891
4892	#ifdef VBOX_STRICT
4893	/**
4894	* The '.pgmassertcr3' command.
4895	*
4896	* @returns VBox status.
4897	* @param pCmd Pointer to the command descriptor (as registered).
4898	* @param pCmdHlp Pointer to command helper functions.
4899	* @param pVM Pointer to the current VM (if any).
4900	* @param paArgs Pointer to (readonly) array of arguments.
4901	* @param cArgs Number of arguments in the array.
4902	*/
4903	static DECLCALLBACK(int) pgmR3CmdAssertCR3(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4904	{
4905	/** @todo SMP support!! */
4906	PVMCPU pVCpu = &pVM->aCpus[0];
4907
4908	/*
4909	* Validate input.
4910	*/
4911	if (!pVM)
4912	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4913
4914	int rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Checking shadow CR3 page tables for consistency.\n");
4915	if (RT_FAILURE(rc))
4916	return rc;
4917
4918	PGMAssertCR3(pVM, pVCpu, CPUMGetGuestCR3(pVCpu), CPUMGetGuestCR4(pVCpu));
4919
4920	return VINF_SUCCESS;
4921	}
4922	#endif /* VBOX_STRICT */
4923
4924
4925	/**
4926	* The '.pgmsyncalways' command.
4927	*
4928	* @returns VBox status.
4929	* @param pCmd Pointer to the command descriptor (as registered).
4930	* @param pCmdHlp Pointer to command helper functions.
4931	* @param pVM Pointer to the current VM (if any).
4932	* @param paArgs Pointer to (readonly) array of arguments.
4933	* @param cArgs Number of arguments in the array.
4934	*/
4935	static DECLCALLBACK(int) pgmR3CmdSyncAlways(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4936	{
4937	/** @todo SMP support!! */
4938	PVMCPU pVCpu = &pVM->aCpus[0];
4939
4940	/*
4941	* Validate input.
4942	*/
4943	if (!pVM)
4944	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4945
4946	/*
4947	* Force page directory sync.
4948	*/
4949	if (pVCpu->pgm.s.fSyncFlags & PGM_SYNC_ALWAYS)
4950	{
4951	ASMAtomicAndU32(&pVCpu->pgm.s.fSyncFlags, ~PGM_SYNC_ALWAYS);
4952	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Disabled permanent forced page directory syncing.\n");
4953	}
4954	else
4955	{
4956	ASMAtomicOrU32(&pVCpu->pgm.s.fSyncFlags, PGM_SYNC_ALWAYS);
4957	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
4958	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Enabled permanent forced page directory syncing.\n");
4959	}
4960	}
4961
4962	#endif /* VBOX_WITH_DEBUGGER */
4963
4964	/**
4965	* pvUser argument of the pgmR3CheckIntegrity*Node callbacks.
4966	*/
4967	typedef struct PGMCHECKINTARGS
4968	{
4969	bool fLeftToRight; /*< true: left-to-right; false: right-to-left. /
4970	PPGMPHYSHANDLER pPrevPhys;
4971	PPGMVIRTHANDLER pPrevVirt;
4972	PPGMPHYS2VIRTHANDLER pPrevPhys2Virt;
4973	PVM pVM;
4974	} PGMCHECKINTARGS, *PPGMCHECKINTARGS;
4975
4976	/**
4977	* Validate a node in the physical handler tree.
4978	*
4979	* @returns 0 on if ok, other wise 1.
4980	* @param pNode The handler node.
4981	* @param pvUser pVM.
4982	*/
4983	static DECLCALLBACK(int) pgmR3CheckIntegrityPhysHandlerNode(PAVLROGCPHYSNODECORE pNode, void *pvUser)
4984	{
4985	PPGMCHECKINTARGS pArgs = (PPGMCHECKINTARGS)pvUser;
4986	PPGMPHYSHANDLER pCur = (PPGMPHYSHANDLER)pNode;
4987	AssertReleaseReturn(!((uintptr_t)pCur & 7), 1);
4988	AssertReleaseMsg(pCur->Core.Key <= pCur->Core.KeyLast,("pCur=%p %RGp-%RGp %s\n", pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
4989	AssertReleaseMsg( !pArgs->pPrevPhys
4990	\|\| (pArgs->fLeftToRight ? pArgs->pPrevPhys->Core.KeyLast < pCur->Core.Key : pArgs->pPrevPhys->Core.KeyLast > pCur->Core.Key),
4991	("pPrevPhys=%p %RGp-%RGp %s\n"
4992	" pCur=%p %RGp-%RGp %s\n",
4993	pArgs->pPrevPhys, pArgs->pPrevPhys->Core.Key, pArgs->pPrevPhys->Core.KeyLast, pArgs->pPrevPhys->pszDesc,
4994	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
4995	pArgs->pPrevPhys = pCur;
4996	return 0;
4997	}
4998
4999
5000	/**
5001	* Validate a node in the virtual handler tree.
5002	*
5003	* @returns 0 on if ok, other wise 1.
5004	* @param pNode The handler node.
5005	* @param pvUser pVM.
5006	*/
5007	static DECLCALLBACK(int) pgmR3CheckIntegrityVirtHandlerNode(PAVLROGCPTRNODECORE pNode, void *pvUser)
5008	{
5009	PPGMCHECKINTARGS pArgs = (PPGMCHECKINTARGS)pvUser;
5010	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)pNode;
5011	AssertReleaseReturn(!((uintptr_t)pCur & 7), 1);
5012	AssertReleaseMsg(pCur->Core.Key <= pCur->Core.KeyLast,("pCur=%p %RGv-%RGv %s\n", pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
5013	AssertReleaseMsg( !pArgs->pPrevVirt
5014	\|\| (pArgs->fLeftToRight ? pArgs->pPrevVirt->Core.KeyLast < pCur->Core.Key : pArgs->pPrevVirt->Core.KeyLast > pCur->Core.Key),
5015	("pPrevVirt=%p %RGv-%RGv %s\n"
5016	" pCur=%p %RGv-%RGv %s\n",
5017	pArgs->pPrevVirt, pArgs->pPrevVirt->Core.Key, pArgs->pPrevVirt->Core.KeyLast, pArgs->pPrevVirt->pszDesc,
5018	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
5019	for (unsigned iPage = 0; iPage < pCur->cPages; iPage++)
5020	{
5021	AssertReleaseMsg(pCur->aPhysToVirt[iPage].offVirtHandler == -RT_OFFSETOF(PGMVIRTHANDLER, aPhysToVirt[iPage]),
5022	("pCur=%p %RGv-%RGv %s\n"
5023	"iPage=%d offVirtHandle=%#x expected %#x\n",
5024	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc,
5025	iPage, pCur->aPhysToVirt[iPage].offVirtHandler, -RT_OFFSETOF(PGMVIRTHANDLER, aPhysToVirt[iPage])));
5026	}
5027	pArgs->pPrevVirt = pCur;
5028	return 0;
5029	}
5030
5031
5032	/**
5033	* Validate a node in the virtual handler tree.
5034	*
5035	* @returns 0 on if ok, other wise 1.
5036	* @param pNode The handler node.
5037	* @param pvUser pVM.
5038	*/
5039	static DECLCALLBACK(int) pgmR3CheckIntegrityPhysToVirtHandlerNode(PAVLROGCPHYSNODECORE pNode, void *pvUser)
5040	{
5041	PPGMCHECKINTARGS pArgs = (PPGMCHECKINTARGS)pvUser;
5042	PPGMPHYS2VIRTHANDLER pCur = (PPGMPHYS2VIRTHANDLER)pNode;
5043	AssertReleaseMsgReturn(!((uintptr_t)pCur & 3), ("\n"), 1);
5044	AssertReleaseMsgReturn(!(pCur->offVirtHandler & 3), ("\n"), 1);
5045	AssertReleaseMsg(pCur->Core.Key <= pCur->Core.KeyLast,("pCur=%p %RGp-%RGp\n", pCur, pCur->Core.Key, pCur->Core.KeyLast));
5046	AssertReleaseMsg( !pArgs->pPrevPhys2Virt
5047	\|\| (pArgs->fLeftToRight ? pArgs->pPrevPhys2Virt->Core.KeyLast < pCur->Core.Key : pArgs->pPrevPhys2Virt->Core.KeyLast > pCur->Core.Key),
5048	("pPrevPhys2Virt=%p %RGp-%RGp\n"
5049	" pCur=%p %RGp-%RGp\n",
5050	pArgs->pPrevPhys2Virt, pArgs->pPrevPhys2Virt->Core.Key, pArgs->pPrevPhys2Virt->Core.KeyLast,
5051	pCur, pCur->Core.Key, pCur->Core.KeyLast));
5052	AssertReleaseMsg( !pArgs->pPrevPhys2Virt
5053	\|\| (pArgs->fLeftToRight ? pArgs->pPrevPhys2Virt->Core.KeyLast < pCur->Core.Key : pArgs->pPrevPhys2Virt->Core.KeyLast > pCur->Core.Key),
5054	("pPrevPhys2Virt=%p %RGp-%RGp\n"
5055	" pCur=%p %RGp-%RGp\n",
5056	pArgs->pPrevPhys2Virt, pArgs->pPrevPhys2Virt->Core.Key, pArgs->pPrevPhys2Virt->Core.KeyLast,
5057	pCur, pCur->Core.Key, pCur->Core.KeyLast));
5058	AssertReleaseMsg((pCur->offNextAlias & (PGMPHYS2VIRTHANDLER_IN_TREE \| PGMPHYS2VIRTHANDLER_IS_HEAD)) == (PGMPHYS2VIRTHANDLER_IN_TREE \| PGMPHYS2VIRTHANDLER_IS_HEAD),
5059	("pCur=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
5060	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias));
5061	if (pCur->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK)
5062	{
5063	PPGMPHYS2VIRTHANDLER pCur2 = pCur;
5064	for (;;)
5065	{
5066	pCur2 = (PPGMPHYS2VIRTHANDLER)((intptr_t)pCur + (pCur->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK));
5067	AssertReleaseMsg(pCur2 != pCur,
5068	(" pCur=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
5069	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias));
5070	AssertReleaseMsg((pCur2->offNextAlias & (PGMPHYS2VIRTHANDLER_IN_TREE \| PGMPHYS2VIRTHANDLER_IS_HEAD)) == PGMPHYS2VIRTHANDLER_IN_TREE,
5071	(" pCur=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
5072	"pCur2=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
5073	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias,
5074	pCur2, pCur2->Core.Key, pCur2->Core.KeyLast, pCur2->offVirtHandler, pCur2->offNextAlias));
5075	AssertReleaseMsg((pCur2->Core.Key ^ pCur->Core.Key) < PAGE_SIZE,
5076	(" pCur=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
5077	"pCur2=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
5078	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias,
5079	pCur2, pCur2->Core.Key, pCur2->Core.KeyLast, pCur2->offVirtHandler, pCur2->offNextAlias));
5080	AssertReleaseMsg((pCur2->Core.KeyLast ^ pCur->Core.KeyLast) < PAGE_SIZE,
5081	(" pCur=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
5082	"pCur2=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
5083	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias,
5084	pCur2, pCur2->Core.Key, pCur2->Core.KeyLast, pCur2->offVirtHandler, pCur2->offNextAlias));
5085	if (!(pCur2->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK))
5086	break;
5087	}
5088	}
5089
5090	pArgs->pPrevPhys2Virt = pCur;
5091	return 0;
5092	}
5093
5094
5095	/**
5096	* Perform an integrity check on the PGM component.
5097	*
5098	* @returns VINF_SUCCESS if everything is fine.
5099	* @returns VBox error status after asserting on integrity breach.
5100	* @param pVM The VM handle.
5101	*/
5102	VMMR3DECL(int) PGMR3CheckIntegrity(PVM pVM)
5103	{
5104	AssertReleaseReturn(pVM->pgm.s.offVM, VERR_INTERNAL_ERROR);
5105
5106	/*
5107	* Check the trees.
5108	*/
5109	int cErrors = 0;
5110	const static PGMCHECKINTARGS s_LeftToRight = { true, NULL, NULL, NULL, pVM };
5111	const static PGMCHECKINTARGS s_RightToLeft = { false, NULL, NULL, NULL, pVM };
5112	PGMCHECKINTARGS Args = s_LeftToRight;
5113	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysHandlers, true, pgmR3CheckIntegrityPhysHandlerNode, &Args);
5114	Args = s_RightToLeft;
5115	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysHandlers, false, pgmR3CheckIntegrityPhysHandlerNode, &Args);
5116	Args = s_LeftToRight;
5117	cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesR3->VirtHandlers, true, pgmR3CheckIntegrityVirtHandlerNode, &Args);
5118	Args = s_RightToLeft;
5119	cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesR3->VirtHandlers, false, pgmR3CheckIntegrityVirtHandlerNode, &Args);
5120	Args = s_LeftToRight;
5121	cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesR3->HyperVirtHandlers, true, pgmR3CheckIntegrityVirtHandlerNode, &Args);
5122	Args = s_RightToLeft;
5123	cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesR3->HyperVirtHandlers, false, pgmR3CheckIntegrityVirtHandlerNode, &Args);
5124	Args = s_LeftToRight;
5125	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysToVirtHandlers, true, pgmR3CheckIntegrityPhysToVirtHandlerNode, &Args);
5126	Args = s_RightToLeft;
5127	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysToVirtHandlers, false, pgmR3CheckIntegrityPhysToVirtHandlerNode, &Args);
5128
5129	return !cErrors ? VINF_SUCCESS : VERR_INTERNAL_ERROR;
5130	}
5131
5132

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source: vbox/trunk/src/VBox/VMM/PGM.cpp@ 21982

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