PGM.cpp@ 22017

Last change on this file since 22017 was 21994, checked in by vboxsync, 15 years ago
PGM: Added '.pgmphystofile <file> [nozero]' for getting more representative input for tstCompressionBenchmark.
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1	/* $Id: PGM.cpp 21994 2009-08-05 12:44:59Z vboxsync $ */
2	/** @file
3	* PGM - Page Manager and Monitor. (Mixing stuff here, not good?)
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Sun Microsystems, Inc.
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*
17	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa
18	* Clara, CA 95054 USA or visit http://www.sun.com if you need
19	* additional information or have any questions.
20	*/
21
22
23	/** @page pg_pgm PGM - The Page Manager and Monitor
24	*
25	* @see grp_pgm,
26	* @ref pg_pgm_pool,
27	* @ref pg_pgm_phys.
28	*
29	*
30	* @section sec_pgm_modes Paging Modes
31	*
32	* There are three memory contexts: Host Context (HC), Guest Context (GC)
33	* and intermediate context. When talking about paging HC can also be refered to
34	* as "host paging", and GC refered to as "shadow paging".
35	*
36	* We define three basic paging modes: 32-bit, PAE and AMD64. The host paging mode
37	* is defined by the host operating system. The mode used in the shadow paging mode
38	* depends on the host paging mode and what the mode the guest is currently in. The
39	* following relation between the two is defined:
40	*
41	* @verbatim
42	Host > 32-bit \| PAE \| AMD64 \|
43	Guest \| \| \| \|
44	==v================================
45	32-bit 32-bit PAE PAE
46	-------\|--------\|--------\|--------\|
47	PAE PAE PAE PAE
48	-------\|--------\|--------\|--------\|
49	AMD64 AMD64 AMD64 AMD64
50	-------\|--------\|--------\|--------\| @endverbatim
51	*
52	* All configuration except those in the diagonal (upper left) are expected to
53	* require special effort from the switcher (i.e. a bit slower).
54	*
55	*
56	*
57	*
58	* @section sec_pgm_shw The Shadow Memory Context
59	*
60	*
61	* [..]
62	*
63	* Because of guest context mappings requires PDPT and PML4 entries to allow
64	* writing on AMD64, the two upper levels will have fixed flags whatever the
65	* guest is thinking of using there. So, when shadowing the PD level we will
66	* calculate the effective flags of PD and all the higher levels. In legacy
67	* PAE mode this only applies to the PWT and PCD bits (the rest are
68	* ignored/reserved/MBZ). We will ignore those bits for the present.
69	*
70	*
71	*
72	* @section sec_pgm_int The Intermediate Memory Context
73	*
74	* The world switch goes thru an intermediate memory context which purpose it is
75	* to provide different mappings of the switcher code. All guest mappings are also
76	* present in this context.
77	*
78	* The switcher code is mapped at the same location as on the host, at an
79	* identity mapped location (physical equals virtual address), and at the
80	* hypervisor location. The identity mapped location is for when the world
81	* switches that involves disabling paging.
82	*
83	* PGM maintain page tables for 32-bit, PAE and AMD64 paging modes. This
84	* simplifies switching guest CPU mode and consistency at the cost of more
85	* code to do the work. All memory use for those page tables is located below
86	* 4GB (this includes page tables for guest context mappings).
87	*
88	*
89	* @subsection subsec_pgm_int_gc Guest Context Mappings
90	*
91	* During assignment and relocation of a guest context mapping the intermediate
92	* memory context is used to verify the new location.
93	*
94	* Guest context mappings are currently restricted to below 4GB, for reasons
95	* of simplicity. This may change when we implement AMD64 support.
96	*
97	*
98	*
99	*
100	* @section sec_pgm_misc Misc
101	*
102	* @subsection subsec_pgm_misc_diff Differences Between Legacy PAE and Long Mode PAE
103	*
104	* The differences between legacy PAE and long mode PAE are:
105	* -# PDPE bits 1, 2, 5 and 6 are defined differently. In leagcy mode they are
106	* all marked down as must-be-zero, while in long mode 1, 2 and 5 have the
107	* usual meanings while 6 is ignored (AMD). This means that upon switching to
108	* legacy PAE mode we'll have to clear these bits and when going to long mode
109	* they must be set. This applies to both intermediate and shadow contexts,
110	* however we don't need to do it for the intermediate one since we're
111	* executing with CR0.WP at that time.
112	* -# CR3 allows a 32-byte aligned address in legacy mode, while in long mode
113	* a page aligned one is required.
114	*
115	*
116	* @section sec_pgm_handlers Access Handlers
117	*
118	* Placeholder.
119	*
120	*
121	* @subsection sec_pgm_handlers_virt Virtual Access Handlers
122	*
123	* Placeholder.
124	*
125	*
126	* @subsection sec_pgm_handlers_virt Virtual Access Handlers
127	*
128	* We currently implement three types of virtual access handlers: ALL, WRITE
129	* and HYPERVISOR (WRITE). See PGMVIRTHANDLERTYPE for some more details.
130	*
131	* The HYPERVISOR access handlers is kept in a separate tree since it doesn't apply
132	* to physical pages (PGMTREES::HyperVirtHandlers) and only needs to be consulted in
133	* a special \#PF case. The ALL and WRITE are in the PGMTREES::VirtHandlers tree, the
134	* rest of this section is going to be about these handlers.
135	*
136	* We'll go thru the life cycle of a handler and try make sense of it all, don't know
137	* how successfull this is gonna be...
138	*
139	* 1. A handler is registered thru the PGMR3HandlerVirtualRegister and
140	* PGMHandlerVirtualRegisterEx APIs. We check for conflicting virtual handlers
141	* and create a new node that is inserted into the AVL tree (range key). Then
142	* a full PGM resync is flagged (clear pool, sync cr3, update virtual bit of PGMPAGE).
143	*
144	* 2. The following PGMSyncCR3/SyncCR3 operation will first make invoke HandlerVirtualUpdate.
145	*
146	* 2a. HandlerVirtualUpdate will will lookup all the pages covered by virtual handlers
147	* via the current guest CR3 and update the physical page -> virtual handler
148	* translation. Needless to say, this doesn't exactly scale very well. If any changes
149	* are detected, it will flag a virtual bit update just like we did on registration.
150	* PGMPHYS pages with changes will have their virtual handler state reset to NONE.
151	*
152	* 2b. The virtual bit update process will iterate all the pages covered by all the
153	* virtual handlers and update the PGMPAGE virtual handler state to the max of all
154	* virtual handlers on that page.
155	*
156	* 2c. Back in SyncCR3 we will now flush the entire shadow page cache to make sure
157	* we don't miss any alias mappings of the monitored pages.
158	*
159	* 2d. SyncCR3 will then proceed with syncing the CR3 table.
160	*
161	* 3. \#PF(np,read) on a page in the range. This will cause it to be synced
162	* read-only and resumed if it's a WRITE handler. If it's an ALL handler we
163	* will call the handlers like in the next step. If the physical mapping has
164	* changed we will - some time in the future - perform a handler callback
165	* (optional) and update the physical -> virtual handler cache.
166	*
167	* 4. \#PF(,write) on a page in the range. This will cause the handler to
168	* be invoked.
169	*
170	* 5. The guest invalidates the page and changes the physical backing or
171	* unmaps it. This should cause the invalidation callback to be invoked
172	* (it might not yet be 100% perfect). Exactly what happens next... is
173	* this where we mess up and end up out of sync for a while?
174	*
175	* 6. The handler is deregistered by the client via PGMHandlerVirtualDeregister.
176	* We will then set all PGMPAGEs in the physical -> virtual handler cache for
177	* this handler to NONE and trigger a full PGM resync (basically the same
178	* as int step 1). Which means 2 is executed again.
179	*
180	*
181	* @subsubsection sub_sec_pgm_handler_virt_todo TODOs
182	*
183	* There is a bunch of things that needs to be done to make the virtual handlers
184	* work 100% correctly and work more efficiently.
185	*
186	* The first bit hasn't been implemented yet because it's going to slow the
187	* whole mess down even more, and besides it seems to be working reliably for
188	* our current uses. OTOH, some of the optimizations might end up more or less
189	* implementing the missing bits, so we'll see.
190	*
191	* On the optimization side, the first thing to do is to try avoid unnecessary
192	* cache flushing. Then try team up with the shadowing code to track changes
193	* in mappings by means of access to them (shadow in), updates to shadows pages,
194	* invlpg, and shadow PT discarding (perhaps).
195	*
196	* Some idea that have popped up for optimization for current and new features:
197	* - bitmap indicating where there are virtual handlers installed.
198	* (4KB => 220 pages, page 212 => covers 32-bit address space 1:1!)
199	* - Further optimize this by min/max (needs min/max avl getters).
200	* - Shadow page table entry bit (if any left)?
201	*
202	*/
203
204
205	/** @page pg_pgm_phys PGM Physical Guest Memory Management
206	*
207	*
208	* Objectives:
209	* - Guest RAM over-commitment using memory ballooning,
210	* zero pages and general page sharing.
211	* - Moving or mirroring a VM onto a different physical machine.
212	*
213	*
214	* @subsection subsec_pgmPhys_Definitions Definitions
215	*
216	* Allocation chunk - A RTR0MemObjAllocPhysNC object and the tracking
217	* machinery assoicated with it.
218	*
219	*
220	*
221	*
222	* @subsection subsec_pgmPhys_AllocPage Allocating a page.
223	*
224	* Initially we map all guest memory to the (per VM) zero page, which
225	* means that none of the read functions will cause pages to be allocated.
226	*
227	* Exception, access bit in page tables that have been shared. This must
228	* be handled, but we must also make sure PGMGst*Modify doesn't make
229	* unnecessary modifications.
230	*
231	* Allocation points:
232	* - PGMPhysSimpleWriteGCPhys and PGMPhysWrite.
233	* - Replacing a zero page mapping at \#PF.
234	* - Replacing a shared page mapping at \#PF.
235	* - ROM registration (currently MMR3RomRegister).
236	* - VM restore (pgmR3Load).
237	*
238	* For the first three it would make sense to keep a few pages handy
239	* until we've reached the max memory commitment for the VM.
240	*
241	* For the ROM registration, we know exactly how many pages we need
242	* and will request these from ring-0. For restore, we will save
243	* the number of non-zero pages in the saved state and allocate
244	* them up front. This would allow the ring-0 component to refuse
245	* the request if the isn't sufficient memory available for VM use.
246	*
247	* Btw. for both ROM and restore allocations we won't be requiring
248	* zeroed pages as they are going to be filled instantly.
249	*
250	*
251	* @subsection subsec_pgmPhys_FreePage Freeing a page
252	*
253	* There are a few points where a page can be freed:
254	* - After being replaced by the zero page.
255	* - After being replaced by a shared page.
256	* - After being ballooned by the guest additions.
257	* - At reset.
258	* - At restore.
259	*
260	* When freeing one or more pages they will be returned to the ring-0
261	* component and replaced by the zero page.
262	*
263	* The reasoning for clearing out all the pages on reset is that it will
264	* return us to the exact same state as on power on, and may thereby help
265	* us reduce the memory load on the system. Further it might have a
266	* (temporary) positive influence on memory fragmentation (@see subsec_pgmPhys_Fragmentation).
267	*
268	* On restore, as mention under the allocation topic, pages should be
269	* freed / allocated depending on how many is actually required by the
270	* new VM state. The simplest approach is to do like on reset, and free
271	* all non-ROM pages and then allocate what we need.
272	*
273	* A measure to prevent some fragmentation, would be to let each allocation
274	* chunk have some affinity towards the VM having allocated the most pages
275	* from it. Also, try make sure to allocate from allocation chunks that
276	* are almost full. Admittedly, both these measures might work counter to
277	* our intentions and its probably not worth putting a lot of effort,
278	* cpu time or memory into this.
279	*
280	*
281	* @subsection subsec_pgmPhys_SharePage Sharing a page
282	*
283	* The basic idea is that there there will be a idle priority kernel
284	* thread walking the non-shared VM pages hashing them and looking for
285	* pages with the same checksum. If such pages are found, it will compare
286	* them byte-by-byte to see if they actually are identical. If found to be
287	* identical it will allocate a shared page, copy the content, check that
288	* the page didn't change while doing this, and finally request both the
289	* VMs to use the shared page instead. If the page is all zeros (special
290	* checksum and byte-by-byte check) it will request the VM that owns it
291	* to replace it with the zero page.
292	*
293	* To make this efficient, we will have to make sure not to try share a page
294	* that will change its contents soon. This part requires the most work.
295	* A simple idea would be to request the VM to write monitor the page for
296	* a while to make sure it isn't modified any time soon. Also, it may
297	* make sense to skip pages that are being write monitored since this
298	* information is readily available to the thread if it works on the
299	* per-VM guest memory structures (presently called PGMRAMRANGE).
300	*
301	*
302	* @subsection subsec_pgmPhys_Fragmentation Fragmentation Concerns and Counter Measures
303	*
304	* The pages are organized in allocation chunks in ring-0, this is a necessity
305	* if we wish to have an OS agnostic approach to this whole thing. (On Linux we
306	* could easily work on a page-by-page basis if we liked. Whether this is possible
307	* or efficient on NT I don't quite know.) Fragmentation within these chunks may
308	* become a problem as part of the idea here is that we wish to return memory to
309	* the host system.
310	*
311	* For instance, starting two VMs at the same time, they will both allocate the
312	* guest memory on-demand and if permitted their page allocations will be
313	* intermixed. Shut down one of the two VMs and it will be difficult to return
314	* any memory to the host system because the page allocation for the two VMs are
315	* mixed up in the same allocation chunks.
316	*
317	* To further complicate matters, when pages are freed because they have been
318	* ballooned or become shared/zero the whole idea is that the page is supposed
319	* to be reused by another VM or returned to the host system. This will cause
320	* allocation chunks to contain pages belonging to different VMs and prevent
321	* returning memory to the host when one of those VM shuts down.
322	*
323	* The only way to really deal with this problem is to move pages. This can
324	* either be done at VM shutdown and or by the idle priority worker thread
325	* that will be responsible for finding sharable/zero pages. The mechanisms
326	* involved for coercing a VM to move a page (or to do it for it) will be
327	* the same as when telling it to share/zero a page.
328	*
329	*
330	* @subsection subsec_pgmPhys_Tracking Tracking Structures And Their Cost
331	*
332	* There's a difficult balance between keeping the per-page tracking structures
333	* (global and guest page) easy to use and keeping them from eating too much
334	* memory. We have limited virtual memory resources available when operating in
335	* 32-bit kernel space (on 64-bit there'll it's quite a different story). The
336	* tracking structures will be attemted designed such that we can deal with up
337	* to 32GB of memory on a 32-bit system and essentially unlimited on 64-bit ones.
338	*
339	*
340	* @subsubsection subsubsec_pgmPhys_Tracking_Kernel Kernel Space
341	*
342	* @see pg_GMM
343	*
344	* @subsubsection subsubsec_pgmPhys_Tracking_PerVM Per-VM
345	*
346	* Fixed info is the physical address of the page (HCPhys) and the page id
347	* (described above). Theoretically we'll need 48(-12) bits for the HCPhys part.
348	* Today we've restricting ourselves to 40(-12) bits because this is the current
349	* restrictions of all AMD64 implementations (I think Barcelona will up this
350	* to 48(-12) bits, not that it really matters) and I needed the bits for
351	* tracking mappings of a page. 48-12 = 36. That leaves 28 bits, which means a
352	* decent range for the page id: 2^(28+12) = 1024TB.
353	*
354	* In additions to these, we'll have to keep maintaining the page flags as we
355	* currently do. Although it wouldn't harm to optimize these quite a bit, like
356	* for instance the ROM shouldn't depend on having a write handler installed
357	* in order for it to become read-only. A RO/RW bit should be considered so
358	* that the page syncing code doesn't have to mess about checking multiple
359	* flag combinations (ROM \|\| RW handler \|\| write monitored) in order to
360	* figure out how to setup a shadow PTE. But this of course, is second
361	* priority at present. Current this requires 12 bits, but could probably
362	* be optimized to ~8.
363	*
364	* Then there's the 24 bits used to track which shadow page tables are
365	* currently mapping a page for the purpose of speeding up physical
366	* access handlers, and thereby the page pool cache. More bit for this
367	* purpose wouldn't hurt IIRC.
368	*
369	* Then there is a new bit in which we need to record what kind of page
370	* this is, shared, zero, normal or write-monitored-normal. This'll
371	* require 2 bits. One bit might be needed for indicating whether a
372	* write monitored page has been written to. And yet another one or
373	* two for tracking migration status. 3-4 bits total then.
374	*
375	* Whatever is left will can be used to record the sharabilitiy of a
376	* page. The page checksum will not be stored in the per-VM table as
377	* the idle thread will not be permitted to do modifications to it.
378	* It will instead have to keep its own working set of potentially
379	* shareable pages and their check sums and stuff.
380	*
381	* For the present we'll keep the current packing of the
382	* PGMRAMRANGE::aHCPhys to keep the changes simple, only of course,
383	* we'll have to change it to a struct with a total of 128-bits at
384	* our disposal.
385	*
386	* The initial layout will be like this:
387	* @verbatim
388	RTHCPHYS HCPhys; The current stuff.
389	63:40 Current shadow PT tracking stuff.
390	39:12 The physical page frame number.
391	11:0 The current flags.
392	uint32_t u28PageId : 28; The page id.
393	uint32_t u2State : 2; The page state { zero, shared, normal, write monitored }.
394	uint32_t fWrittenTo : 1; Whether a write monitored page was written to.
395	uint32_t u1Reserved : 1; Reserved for later.
396	uint32_t u32Reserved; Reserved for later, mostly sharing stats.
397	@endverbatim
398	*
399	* The final layout will be something like this:
400	* @verbatim
401	RTHCPHYS HCPhys; The current stuff.
402	63:48 High page id (12+).
403	47:12 The physical page frame number.
404	11:0 Low page id.
405	uint32_t fReadOnly : 1; Whether it's readonly page (rom or monitored in some way).
406	uint32_t u3Type : 3; The page type {RESERVED, MMIO, MMIO2, ROM, shadowed ROM, RAM}.
407	uint32_t u2PhysMon : 2; Physical access handler type {none, read, write, all}.
408	uint32_t u2VirtMon : 2; Virtual access handler type {none, read, write, all}..
409	uint32_t u2State : 2; The page state { zero, shared, normal, write monitored }.
410	uint32_t fWrittenTo : 1; Whether a write monitored page was written to.
411	uint32_t u20Reserved : 20; Reserved for later, mostly sharing stats.
412	uint32_t u32Tracking; The shadow PT tracking stuff, roughly.
413	@endverbatim
414	*
415	* Cost wise, this means we'll double the cost for guest memory. There isn't anyway
416	* around that I'm afraid. It means that the cost of dealing out 32GB of memory
417	* to one or more VMs is: (32GB >> PAGE_SHIFT) * 16 bytes, or 128MBs. Or another
418	* example, the VM heap cost when assigning 1GB to a VM will be: 4MB.
419	*
420	* A couple of cost examples for the total cost per-VM + kernel.
421	* 32-bit Windows and 32-bit linux:
422	* 1GB guest ram, 256K pages: 4MB + 2MB(+) = 6MB
423	* 4GB guest ram, 1M pages: 16MB + 8MB(+) = 24MB
424	* 32GB guest ram, 8M pages: 128MB + 64MB(+) = 192MB
425	* 64-bit Windows and 64-bit linux:
426	* 1GB guest ram, 256K pages: 4MB + 3MB(+) = 7MB
427	* 4GB guest ram, 1M pages: 16MB + 12MB(+) = 28MB
428	* 32GB guest ram, 8M pages: 128MB + 96MB(+) = 224MB
429	*
430	* UPDATE - 2007-09-27:
431	* Will need a ballooned flag/state too because we cannot
432	* trust the guest 100% and reporting the same page as ballooned more
433	* than once will put the GMM off balance.
434	*
435	*
436	* @subsection subsec_pgmPhys_Serializing Serializing Access
437	*
438	* Initially, we'll try a simple scheme:
439	*
440	* - The per-VM RAM tracking structures (PGMRAMRANGE) is only modified
441	* by the EMT thread of that VM while in the pgm critsect.
442	* - Other threads in the VM process that needs to make reliable use of
443	* the per-VM RAM tracking structures will enter the critsect.
444	* - No process external thread or kernel thread will ever try enter
445	* the pgm critical section, as that just won't work.
446	* - The idle thread (and similar threads) doesn't not need 100% reliable
447	* data when performing it tasks as the EMT thread will be the one to
448	* do the actual changes later anyway. So, as long as it only accesses
449	* the main ram range, it can do so by somehow preventing the VM from
450	* being destroyed while it works on it...
451	*
452	* - The over-commitment management, including the allocating/freeing
453	* chunks, is serialized by a ring-0 mutex lock (a fast one since the
454	* more mundane mutex implementation is broken on Linux).
455	* - A separeate mutex is protecting the set of allocation chunks so
456	* that pages can be shared or/and freed up while some other VM is
457	* allocating more chunks. This mutex can be take from under the other
458	* one, but not the otherway around.
459	*
460	*
461	* @subsection subsec_pgmPhys_Request VM Request interface
462	*
463	* When in ring-0 it will become necessary to send requests to a VM so it can
464	* for instance move a page while defragmenting during VM destroy. The idle
465	* thread will make use of this interface to request VMs to setup shared
466	* pages and to perform write monitoring of pages.
467	*
468	* I would propose an interface similar to the current VMReq interface, similar
469	* in that it doesn't require locking and that the one sending the request may
470	* wait for completion if it wishes to. This shouldn't be very difficult to
471	* realize.
472	*
473	* The requests themselves are also pretty simple. They are basically:
474	* -# Check that some precondition is still true.
475	* -# Do the update.
476	* -# Update all shadow page tables involved with the page.
477	*
478	* The 3rd step is identical to what we're already doing when updating a
479	* physical handler, see pgmHandlerPhysicalSetRamFlagsAndFlushShadowPTs.
480	*
481	*
482	*
483	* @section sec_pgmPhys_MappingCaches Mapping Caches
484	*
485	* In order to be able to map in and out memory and to be able to support
486	* guest with more RAM than we've got virtual address space, we'll employing
487	* a mapping cache. There is already a tiny one for GC (see PGMGCDynMapGCPageEx)
488	* and we'll create a similar one for ring-0 unless we decide to setup a dedicate
489	* memory context for the HWACCM execution.
490	*
491	*
492	* @subsection subsec_pgmPhys_MappingCaches_R3 Ring-3
493	*
494	* We've considered implementing the ring-3 mapping cache page based but found
495	* that this was bother some when one had to take into account TLBs+SMP and
496	* portability (missing the necessary APIs on several platforms). There were
497	* also some performance concerns with this approach which hadn't quite been
498	* worked out.
499	*
500	* Instead, we'll be mapping allocation chunks into the VM process. This simplifies
501	* matters greatly quite a bit since we don't need to invent any new ring-0 stuff,
502	* only some minor RTR0MEMOBJ mapping stuff. The main concern here is that mapping
503	* compared to the previous idea is that mapping or unmapping a 1MB chunk is more
504	* costly than a single page, although how much more costly is uncertain. We'll
505	* try address this by using a very big cache, preferably bigger than the actual
506	* VM RAM size if possible. The current VM RAM sizes should give some idea for
507	* 32-bit boxes, while on 64-bit we can probably get away with employing an
508	* unlimited cache.
509	*
510	* The cache have to parts, as already indicated, the ring-3 side and the
511	* ring-0 side.
512	*
513	* The ring-0 will be tied to the page allocator since it will operate on the
514	* memory objects it contains. It will therefore require the first ring-0 mutex
515	* discussed in @ref subsec_pgmPhys_Serializing. We
516	* some double house keeping wrt to who has mapped what I think, since both
517	* VMMR0.r0 and RTR0MemObj will keep track of mapping relataions
518	*
519	* The ring-3 part will be protected by the pgm critsect. For simplicity, we'll
520	* require anyone that desires to do changes to the mapping cache to do that
521	* from within this critsect. Alternatively, we could employ a separate critsect
522	* for serializing changes to the mapping cache as this would reduce potential
523	* contention with other threads accessing mappings unrelated to the changes
524	* that are in process. We can see about this later, contention will show
525	* up in the statistics anyway, so it'll be simple to tell.
526	*
527	* The organization of the ring-3 part will be very much like how the allocation
528	* chunks are organized in ring-0, that is in an AVL tree by chunk id. To avoid
529	* having to walk the tree all the time, we'll have a couple of lookaside entries
530	* like in we do for I/O ports and MMIO in IOM.
531	*
532	* The simplified flow of a PGMPhysRead/Write function:
533	* -# Enter the PGM critsect.
534	* -# Lookup GCPhys in the ram ranges and get the Page ID.
535	* -# Calc the Allocation Chunk ID from the Page ID.
536	* -# Check the lookaside entries and then the AVL tree for the Chunk ID.
537	* If not found in cache:
538	* -# Call ring-0 and request it to be mapped and supply
539	* a chunk to be unmapped if the cache is maxed out already.
540	* -# Insert the new mapping into the AVL tree (id + R3 address).
541	* -# Update the relevant lookaside entry and return the mapping address.
542	* -# Do the read/write according to monitoring flags and everything.
543	* -# Leave the critsect.
544	*
545	*
546	* @section sec_pgmPhys_Fallback Fallback
547	*
548	* Current all the "second tier" hosts will not support the RTR0MemObjAllocPhysNC
549	* API and thus require a fallback.
550	*
551	* So, when RTR0MemObjAllocPhysNC returns VERR_NOT_SUPPORTED the page allocator
552	* will return to the ring-3 caller (and later ring-0) and asking it to seed
553	* the page allocator with some fresh pages (VERR_GMM_SEED_ME). Ring-3 will
554	* then perform an SUPR3PageAlloc(cbChunk >> PAGE_SHIFT) call and make a
555	* "SeededAllocPages" call to ring-0.
556	*
557	* The first time ring-0 sees the VERR_NOT_SUPPORTED failure it will disable
558	* all page sharing (zero page detection will continue). It will also force
559	* all allocations to come from the VM which seeded the page. Both these
560	* measures are taken to make sure that there will never be any need for
561	* mapping anything into ring-3 - everything will be mapped already.
562	*
563	* Whether we'll continue to use the current MM locked memory management
564	* for this I don't quite know (I'd prefer not to and just ditch that all
565	* togther), we'll see what's simplest to do.
566	*
567	*
568	*
569	* @section sec_pgmPhys_Changes Changes
570	*
571	* Breakdown of the changes involved?
572	*/
573
574	/*******************************************************************************
575	* Header Files *
576	*******************************************************************************/
577	#define LOG_GROUP LOG_GROUP_PGM
578	#include <VBox/dbgf.h>
579	#include <VBox/pgm.h>
580	#include <VBox/cpum.h>
581	#include <VBox/iom.h>
582	#include <VBox/sup.h>
583	#include <VBox/mm.h>
584	#include <VBox/em.h>
585	#include <VBox/stam.h>
586	#include <VBox/rem.h>
587	#include <VBox/dbgf.h>
588	#include <VBox/rem.h>
589	#include <VBox/selm.h>
590	#include <VBox/ssm.h>
591	#include <VBox/hwaccm.h>
592	#include "PGMInternal.h"
593	#include <VBox/vm.h>
594
595	#include <VBox/dbg.h>
596	#include <VBox/param.h>
597	#include <VBox/err.h>
598
599	#include <iprt/asm.h>
600	#include <iprt/assert.h>
601	#include <iprt/env.h>
602	#include <iprt/mem.h>
603	#include <iprt/file.h>
604	#include <iprt/string.h>
605	#include <iprt/thread.h>
606
607
608	/*******************************************************************************
609	* Defined Constants And Macros *
610	*******************************************************************************/
611	/** Saved state data unit version for 2.5.x and later. */
612	#define PGM_SAVED_STATE_VERSION 9
613	/** Saved state data unit version for 2.2.2 and later. */
614	#define PGM_SAVED_STATE_VERSION_2_2_2 8
615	/** Saved state data unit version for 2.2.0. */
616	#define PGM_SAVED_STATE_VERSION_RR_DESC 7
617	/** Saved state data unit version. */
618	#define PGM_SAVED_STATE_VERSION_OLD_PHYS_CODE 6
619
620
621	/*******************************************************************************
622	* Internal Functions *
623	*******************************************************************************/
624	static int pgmR3InitPaging(PVM pVM);
625	static void pgmR3InitStats(PVM pVM);
626	static DECLCALLBACK(void) pgmR3PhysInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
627	static DECLCALLBACK(void) pgmR3InfoMode(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
628	static DECLCALLBACK(void) pgmR3InfoCr3(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
629	static DECLCALLBACK(int) pgmR3RelocatePhysHandler(PAVLROGCPHYSNODECORE pNode, void *pvUser);
630	static DECLCALLBACK(int) pgmR3RelocateVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser);
631	static DECLCALLBACK(int) pgmR3RelocateHyperVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser);
632	#ifdef VBOX_STRICT
633	static DECLCALLBACK(void) pgmR3ResetNoMorePhysWritesFlag(PVM pVM, VMSTATE enmState, VMSTATE enmOldState, void *pvUser);
634	#endif
635	static DECLCALLBACK(int) pgmR3Save(PVM pVM, PSSMHANDLE pSSM);
636	static DECLCALLBACK(int) pgmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version);
637	static int pgmR3ModeDataInit(PVM pVM, bool fResolveGCAndR0);
638	static void pgmR3ModeDataSwitch(PVM pVM, PVMCPU pVCpu, PGMMODE enmShw, PGMMODE enmGst);
639	static PGMMODE pgmR3CalcShadowMode(PVM pVM, PGMMODE enmGuestMode, SUPPAGINGMODE enmHostMode, PGMMODE enmShadowMode, VMMSWITCHER *penmSwitcher);
640
641	#ifdef VBOX_WITH_DEBUGGER
642	/** @todo Convert the first two commands to 'info' items. */
643	static DECLCALLBACK(int) pgmR3CmdRam(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
644	static DECLCALLBACK(int) pgmR3CmdMap(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
645	static DECLCALLBACK(int) pgmR3CmdError(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
646	static DECLCALLBACK(int) pgmR3CmdSync(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
647	static DECLCALLBACK(int) pgmR3CmdSyncAlways(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
648	# ifdef VBOX_STRICT
649	static DECLCALLBACK(int) pgmR3CmdAssertCR3(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
650	# endif
651	static DECLCALLBACK(int) pgmR3CmdPhysToFile(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult);
652	#endif
653
654
655	/*******************************************************************************
656	* Global Variables *
657	*******************************************************************************/
658	#ifdef VBOX_WITH_DEBUGGER
659	/** Argument descriptors for '.pgmerror' and '.pgmerroroff'. */
660	static const DBGCVARDESC g_aPgmErrorArgs[] =
661	{
662	/* cTimesMin, cTimesMax, enmCategory, fFlags, pszName, pszDescription */
663	{ 0, 1, DBGCVAR_CAT_STRING, 0, "where", "Error injection location." },
664	};
665
666	static const DBGCVARDESC g_aPgmPhysToFileArgs[] =
667	{
668	/* cTimesMin, cTimesMax, enmCategory, fFlags, pszName, pszDescription */
669	{ 1, 1, DBGCVAR_CAT_STRING, 0, "file", "The file name." },
670	{ 0, 1, DBGCVAR_CAT_STRING, 0, "nozero", "If present, zero pages are skipped." },
671	};
672
673	/** Command descriptors. */
674	static const DBGCCMD g_aCmds[] =
675	{
676	/* pszCmd, cArgsMin, cArgsMax, paArgDesc, cArgDescs, pResultDesc, fFlags, pfnHandler pszSyntax, ....pszDescription */
677	{ "pgmram", 0, 0, NULL, 0, NULL, 0, pgmR3CmdRam, "", "Display the ram ranges." },
678	{ "pgmmap", 0, 0, NULL, 0, NULL, 0, pgmR3CmdMap, "", "Display the mapping ranges." },
679	{ "pgmsync", 0, 0, NULL, 0, NULL, 0, pgmR3CmdSync, "", "Sync the CR3 page." },
680	{ "pgmerror", 0, 1, &g_aPgmErrorArgs[0], 1, NULL, 0, pgmR3CmdError, "", "Enables inject runtime of errors into parts of PGM." },
681	{ "pgmerroroff", 0, 1, &g_aPgmErrorArgs[0], 1, NULL, 0, pgmR3CmdError, "", "Disables inject runtime errors into parts of PGM." },
682	#ifdef VBOX_STRICT
683	{ "pgmassertcr3", 0, 0, NULL, 0, NULL, 0, pgmR3CmdAssertCR3, "", "Check the shadow CR3 mapping." },
684	#endif
685	{ "pgmsyncalways", 0, 0, NULL, 0, NULL, 0, pgmR3CmdSyncAlways, "", "Toggle permanent CR3 syncing." },
686	{ "pgmphystofile", 1, 2, &g_aPgmPhysToFileArgs[0], 2, NULL, 0, pgmR3CmdPhysToFile, "", "Save the physical memory to file." },
687	};
688	#endif
689
690
691
692
693	/*
694	* Shadow - 32-bit mode
695	*/
696	#define PGM_SHW_TYPE PGM_TYPE_32BIT
697	#define PGM_SHW_NAME(name) PGM_SHW_NAME_32BIT(name)
698	#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_32BIT_STR(name)
699	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_32BIT_STR(name)
700	#include "PGMShw.h"
701
702	/* Guest - real mode */
703	#define PGM_GST_TYPE PGM_TYPE_REAL
704	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
705	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_REAL_STR(name)
706	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
707	#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_REAL(name)
708	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_32BIT_REAL_STR(name)
709	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_32BIT_REAL_STR(name)
710	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_PHYS
711	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_32BIT_PD_PHYS
712	#include "PGMBth.h"
713	#include "PGMGstDefs.h"
714	#include "PGMGst.h"
715	#undef BTH_PGMPOOLKIND_PT_FOR_PT
716	#undef BTH_PGMPOOLKIND_ROOT
717	#undef PGM_BTH_NAME
718	#undef PGM_BTH_NAME_RC_STR
719	#undef PGM_BTH_NAME_R0_STR
720	#undef PGM_GST_TYPE
721	#undef PGM_GST_NAME
722	#undef PGM_GST_NAME_RC_STR
723	#undef PGM_GST_NAME_R0_STR
724
725	/* Guest - protected mode */
726	#define PGM_GST_TYPE PGM_TYPE_PROT
727	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
728	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PROT_STR(name)
729	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
730	#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_PROT(name)
731	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_32BIT_PROT_STR(name)
732	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_32BIT_PROT_STR(name)
733	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_PHYS
734	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_32BIT_PD_PHYS
735	#include "PGMBth.h"
736	#include "PGMGstDefs.h"
737	#include "PGMGst.h"
738	#undef BTH_PGMPOOLKIND_PT_FOR_PT
739	#undef BTH_PGMPOOLKIND_ROOT
740	#undef PGM_BTH_NAME
741	#undef PGM_BTH_NAME_RC_STR
742	#undef PGM_BTH_NAME_R0_STR
743	#undef PGM_GST_TYPE
744	#undef PGM_GST_NAME
745	#undef PGM_GST_NAME_RC_STR
746	#undef PGM_GST_NAME_R0_STR
747
748	/* Guest - 32-bit mode */
749	#define PGM_GST_TYPE PGM_TYPE_32BIT
750	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
751	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_32BIT_STR(name)
752	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
753	#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_32BIT(name)
754	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_32BIT_32BIT_STR(name)
755	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_32BIT_32BIT_STR(name)
756	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT
757	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB
758	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_32BIT_PD
759	#include "PGMBth.h"
760	#include "PGMGstDefs.h"
761	#include "PGMGst.h"
762	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
763	#undef BTH_PGMPOOLKIND_PT_FOR_PT
764	#undef BTH_PGMPOOLKIND_ROOT
765	#undef PGM_BTH_NAME
766	#undef PGM_BTH_NAME_RC_STR
767	#undef PGM_BTH_NAME_R0_STR
768	#undef PGM_GST_TYPE
769	#undef PGM_GST_NAME
770	#undef PGM_GST_NAME_RC_STR
771	#undef PGM_GST_NAME_R0_STR
772
773	#undef PGM_SHW_TYPE
774	#undef PGM_SHW_NAME
775	#undef PGM_SHW_NAME_RC_STR
776	#undef PGM_SHW_NAME_R0_STR
777
778
779	/*
780	* Shadow - PAE mode
781	*/
782	#define PGM_SHW_TYPE PGM_TYPE_PAE
783	#define PGM_SHW_NAME(name) PGM_SHW_NAME_PAE(name)
784	#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_PAE_STR(name)
785	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_PAE_STR(name)
786	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_REAL(name)
787	#include "PGMShw.h"
788
789	/* Guest - real mode */
790	#define PGM_GST_TYPE PGM_TYPE_REAL
791	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
792	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_REAL_STR(name)
793	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
794	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_REAL(name)
795	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_PAE_REAL_STR(name)
796	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_REAL_STR(name)
797	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
798	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT_PHYS
799	#include "PGMGstDefs.h"
800	#include "PGMBth.h"
801	#undef BTH_PGMPOOLKIND_PT_FOR_PT
802	#undef BTH_PGMPOOLKIND_ROOT
803	#undef PGM_BTH_NAME
804	#undef PGM_BTH_NAME_RC_STR
805	#undef PGM_BTH_NAME_R0_STR
806	#undef PGM_GST_TYPE
807	#undef PGM_GST_NAME
808	#undef PGM_GST_NAME_RC_STR
809	#undef PGM_GST_NAME_R0_STR
810
811	/* Guest - protected mode */
812	#define PGM_GST_TYPE PGM_TYPE_PROT
813	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
814	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PROT_STR(name)
815	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
816	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_PROT(name)
817	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_PAE_PROT_STR(name)
818	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_PROT_STR(name)
819	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
820	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT_PHYS
821	#include "PGMGstDefs.h"
822	#include "PGMBth.h"
823	#undef BTH_PGMPOOLKIND_PT_FOR_PT
824	#undef BTH_PGMPOOLKIND_ROOT
825	#undef PGM_BTH_NAME
826	#undef PGM_BTH_NAME_RC_STR
827	#undef PGM_BTH_NAME_R0_STR
828	#undef PGM_GST_TYPE
829	#undef PGM_GST_NAME
830	#undef PGM_GST_NAME_RC_STR
831	#undef PGM_GST_NAME_R0_STR
832
833	/* Guest - 32-bit mode */
834	#define PGM_GST_TYPE PGM_TYPE_32BIT
835	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
836	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_32BIT_STR(name)
837	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
838	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_32BIT(name)
839	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_PAE_32BIT_STR(name)
840	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_32BIT_STR(name)
841	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_32BIT_PT
842	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB
843	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT_FOR_32BIT
844	#include "PGMGstDefs.h"
845	#include "PGMBth.h"
846	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
847	#undef BTH_PGMPOOLKIND_PT_FOR_PT
848	#undef BTH_PGMPOOLKIND_ROOT
849	#undef PGM_BTH_NAME
850	#undef PGM_BTH_NAME_RC_STR
851	#undef PGM_BTH_NAME_R0_STR
852	#undef PGM_GST_TYPE
853	#undef PGM_GST_NAME
854	#undef PGM_GST_NAME_RC_STR
855	#undef PGM_GST_NAME_R0_STR
856
857	/* Guest - PAE mode */
858	#define PGM_GST_TYPE PGM_TYPE_PAE
859	#define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
860	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PAE_STR(name)
861	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PAE_STR(name)
862	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_PAE(name)
863	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_PAE_PAE_STR(name)
864	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_PAE_STR(name)
865	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
866	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
867	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT
868	#include "PGMBth.h"
869	#include "PGMGstDefs.h"
870	#include "PGMGst.h"
871	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
872	#undef BTH_PGMPOOLKIND_PT_FOR_PT
873	#undef BTH_PGMPOOLKIND_ROOT
874	#undef PGM_BTH_NAME
875	#undef PGM_BTH_NAME_RC_STR
876	#undef PGM_BTH_NAME_R0_STR
877	#undef PGM_GST_TYPE
878	#undef PGM_GST_NAME
879	#undef PGM_GST_NAME_RC_STR
880	#undef PGM_GST_NAME_R0_STR
881
882	#undef PGM_SHW_TYPE
883	#undef PGM_SHW_NAME
884	#undef PGM_SHW_NAME_RC_STR
885	#undef PGM_SHW_NAME_R0_STR
886
887
888	/*
889	* Shadow - AMD64 mode
890	*/
891	#define PGM_SHW_TYPE PGM_TYPE_AMD64
892	#define PGM_SHW_NAME(name) PGM_SHW_NAME_AMD64(name)
893	#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_AMD64_STR(name)
894	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_AMD64_STR(name)
895	#include "PGMShw.h"
896
897	#ifdef VBOX_WITH_64_BITS_GUESTS
898	/* Guest - AMD64 mode */
899	# define PGM_GST_TYPE PGM_TYPE_AMD64
900	# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
901	# define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_AMD64_STR(name)
902	# define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_AMD64_STR(name)
903	# define PGM_BTH_NAME(name) PGM_BTH_NAME_AMD64_AMD64(name)
904	# define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_AMD64_AMD64_STR(name)
905	# define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_AMD64_AMD64_STR(name)
906	# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
907	# define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
908	# define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_64BIT_PML4
909	# include "PGMBth.h"
910	# include "PGMGstDefs.h"
911	# include "PGMGst.h"
912	# undef BTH_PGMPOOLKIND_PT_FOR_BIG
913	# undef BTH_PGMPOOLKIND_PT_FOR_PT
914	# undef BTH_PGMPOOLKIND_ROOT
915	# undef PGM_BTH_NAME
916	# undef PGM_BTH_NAME_RC_STR
917	# undef PGM_BTH_NAME_R0_STR
918	# undef PGM_GST_TYPE
919	# undef PGM_GST_NAME
920	# undef PGM_GST_NAME_RC_STR
921	# undef PGM_GST_NAME_R0_STR
922	#endif /* VBOX_WITH_64_BITS_GUESTS */
923
924	#undef PGM_SHW_TYPE
925	#undef PGM_SHW_NAME
926	#undef PGM_SHW_NAME_RC_STR
927	#undef PGM_SHW_NAME_R0_STR
928
929
930	/*
931	* Shadow - Nested paging mode
932	*/
933	#define PGM_SHW_TYPE PGM_TYPE_NESTED
934	#define PGM_SHW_NAME(name) PGM_SHW_NAME_NESTED(name)
935	#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_NESTED_STR(name)
936	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_NESTED_STR(name)
937	#include "PGMShw.h"
938
939	/* Guest - real mode */
940	#define PGM_GST_TYPE PGM_TYPE_REAL
941	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
942	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_REAL_STR(name)
943	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
944	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_REAL(name)
945	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_REAL_STR(name)
946	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_REAL_STR(name)
947	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
948	#include "PGMGstDefs.h"
949	#include "PGMBth.h"
950	#undef BTH_PGMPOOLKIND_PT_FOR_PT
951	#undef PGM_BTH_NAME
952	#undef PGM_BTH_NAME_RC_STR
953	#undef PGM_BTH_NAME_R0_STR
954	#undef PGM_GST_TYPE
955	#undef PGM_GST_NAME
956	#undef PGM_GST_NAME_RC_STR
957	#undef PGM_GST_NAME_R0_STR
958
959	/* Guest - protected mode */
960	#define PGM_GST_TYPE PGM_TYPE_PROT
961	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
962	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PROT_STR(name)
963	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
964	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_PROT(name)
965	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_PROT_STR(name)
966	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_PROT_STR(name)
967	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
968	#include "PGMGstDefs.h"
969	#include "PGMBth.h"
970	#undef BTH_PGMPOOLKIND_PT_FOR_PT
971	#undef PGM_BTH_NAME
972	#undef PGM_BTH_NAME_RC_STR
973	#undef PGM_BTH_NAME_R0_STR
974	#undef PGM_GST_TYPE
975	#undef PGM_GST_NAME
976	#undef PGM_GST_NAME_RC_STR
977	#undef PGM_GST_NAME_R0_STR
978
979	/* Guest - 32-bit mode */
980	#define PGM_GST_TYPE PGM_TYPE_32BIT
981	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
982	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_32BIT_STR(name)
983	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
984	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_32BIT(name)
985	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_32BIT_STR(name)
986	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_32BIT_STR(name)
987	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_32BIT_PT
988	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB
989	#include "PGMGstDefs.h"
990	#include "PGMBth.h"
991	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
992	#undef BTH_PGMPOOLKIND_PT_FOR_PT
993	#undef PGM_BTH_NAME
994	#undef PGM_BTH_NAME_RC_STR
995	#undef PGM_BTH_NAME_R0_STR
996	#undef PGM_GST_TYPE
997	#undef PGM_GST_NAME
998	#undef PGM_GST_NAME_RC_STR
999	#undef PGM_GST_NAME_R0_STR
1000
1001	/* Guest - PAE mode */
1002	#define PGM_GST_TYPE PGM_TYPE_PAE
1003	#define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
1004	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PAE_STR(name)
1005	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PAE_STR(name)
1006	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_PAE(name)
1007	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_PAE_STR(name)
1008	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_PAE_STR(name)
1009	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
1010	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
1011	#include "PGMGstDefs.h"
1012	#include "PGMBth.h"
1013	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
1014	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1015	#undef PGM_BTH_NAME
1016	#undef PGM_BTH_NAME_RC_STR
1017	#undef PGM_BTH_NAME_R0_STR
1018	#undef PGM_GST_TYPE
1019	#undef PGM_GST_NAME
1020	#undef PGM_GST_NAME_RC_STR
1021	#undef PGM_GST_NAME_R0_STR
1022
1023	#ifdef VBOX_WITH_64_BITS_GUESTS
1024	/* Guest - AMD64 mode */
1025	# define PGM_GST_TYPE PGM_TYPE_AMD64
1026	# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
1027	# define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_AMD64_STR(name)
1028	# define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_AMD64_STR(name)
1029	# define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_AMD64(name)
1030	# define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_AMD64_STR(name)
1031	# define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_AMD64_STR(name)
1032	# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
1033	# define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
1034	# include "PGMGstDefs.h"
1035	# include "PGMBth.h"
1036	# undef BTH_PGMPOOLKIND_PT_FOR_BIG
1037	# undef BTH_PGMPOOLKIND_PT_FOR_PT
1038	# undef PGM_BTH_NAME
1039	# undef PGM_BTH_NAME_RC_STR
1040	# undef PGM_BTH_NAME_R0_STR
1041	# undef PGM_GST_TYPE
1042	# undef PGM_GST_NAME
1043	# undef PGM_GST_NAME_RC_STR
1044	# undef PGM_GST_NAME_R0_STR
1045	#endif /* VBOX_WITH_64_BITS_GUESTS */
1046
1047	#undef PGM_SHW_TYPE
1048	#undef PGM_SHW_NAME
1049	#undef PGM_SHW_NAME_RC_STR
1050	#undef PGM_SHW_NAME_R0_STR
1051
1052
1053	/*
1054	* Shadow - EPT
1055	*/
1056	#define PGM_SHW_TYPE PGM_TYPE_EPT
1057	#define PGM_SHW_NAME(name) PGM_SHW_NAME_EPT(name)
1058	#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_EPT_STR(name)
1059	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_EPT_STR(name)
1060	#include "PGMShw.h"
1061
1062	/* Guest - real mode */
1063	#define PGM_GST_TYPE PGM_TYPE_REAL
1064	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
1065	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_REAL_STR(name)
1066	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
1067	#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_REAL(name)
1068	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_REAL_STR(name)
1069	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_REAL_STR(name)
1070	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
1071	#include "PGMGstDefs.h"
1072	#include "PGMBth.h"
1073	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1074	#undef PGM_BTH_NAME
1075	#undef PGM_BTH_NAME_RC_STR
1076	#undef PGM_BTH_NAME_R0_STR
1077	#undef PGM_GST_TYPE
1078	#undef PGM_GST_NAME
1079	#undef PGM_GST_NAME_RC_STR
1080	#undef PGM_GST_NAME_R0_STR
1081
1082	/* Guest - protected mode */
1083	#define PGM_GST_TYPE PGM_TYPE_PROT
1084	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
1085	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PROT_STR(name)
1086	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
1087	#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_PROT(name)
1088	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_PROT_STR(name)
1089	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_PROT_STR(name)
1090	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
1091	#include "PGMGstDefs.h"
1092	#include "PGMBth.h"
1093	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1094	#undef PGM_BTH_NAME
1095	#undef PGM_BTH_NAME_RC_STR
1096	#undef PGM_BTH_NAME_R0_STR
1097	#undef PGM_GST_TYPE
1098	#undef PGM_GST_NAME
1099	#undef PGM_GST_NAME_RC_STR
1100	#undef PGM_GST_NAME_R0_STR
1101
1102	/* Guest - 32-bit mode */
1103	#define PGM_GST_TYPE PGM_TYPE_32BIT
1104	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
1105	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_32BIT_STR(name)
1106	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
1107	#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_32BIT(name)
1108	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_32BIT_STR(name)
1109	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_32BIT_STR(name)
1110	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_32BIT_PT
1111	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB
1112	#include "PGMGstDefs.h"
1113	#include "PGMBth.h"
1114	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
1115	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1116	#undef PGM_BTH_NAME
1117	#undef PGM_BTH_NAME_RC_STR
1118	#undef PGM_BTH_NAME_R0_STR
1119	#undef PGM_GST_TYPE
1120	#undef PGM_GST_NAME
1121	#undef PGM_GST_NAME_RC_STR
1122	#undef PGM_GST_NAME_R0_STR
1123
1124	/* Guest - PAE mode */
1125	#define PGM_GST_TYPE PGM_TYPE_PAE
1126	#define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
1127	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PAE_STR(name)
1128	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PAE_STR(name)
1129	#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_PAE(name)
1130	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_PAE_STR(name)
1131	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_PAE_STR(name)
1132	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
1133	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
1134	#include "PGMGstDefs.h"
1135	#include "PGMBth.h"
1136	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
1137	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1138	#undef PGM_BTH_NAME
1139	#undef PGM_BTH_NAME_RC_STR
1140	#undef PGM_BTH_NAME_R0_STR
1141	#undef PGM_GST_TYPE
1142	#undef PGM_GST_NAME
1143	#undef PGM_GST_NAME_RC_STR
1144	#undef PGM_GST_NAME_R0_STR
1145
1146	#ifdef VBOX_WITH_64_BITS_GUESTS
1147	/* Guest - AMD64 mode */
1148	# define PGM_GST_TYPE PGM_TYPE_AMD64
1149	# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
1150	# define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_AMD64_STR(name)
1151	# define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_AMD64_STR(name)
1152	# define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_AMD64(name)
1153	# define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_AMD64_STR(name)
1154	# define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_AMD64_STR(name)
1155	# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
1156	# define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
1157	# include "PGMGstDefs.h"
1158	# include "PGMBth.h"
1159	# undef BTH_PGMPOOLKIND_PT_FOR_BIG
1160	# undef BTH_PGMPOOLKIND_PT_FOR_PT
1161	# undef PGM_BTH_NAME
1162	# undef PGM_BTH_NAME_RC_STR
1163	# undef PGM_BTH_NAME_R0_STR
1164	# undef PGM_GST_TYPE
1165	# undef PGM_GST_NAME
1166	# undef PGM_GST_NAME_RC_STR
1167	# undef PGM_GST_NAME_R0_STR
1168	#endif /* VBOX_WITH_64_BITS_GUESTS */
1169
1170	#undef PGM_SHW_TYPE
1171	#undef PGM_SHW_NAME
1172	#undef PGM_SHW_NAME_RC_STR
1173	#undef PGM_SHW_NAME_R0_STR
1174
1175
1176
1177	/**
1178	* Initiates the paging of VM.
1179	*
1180	* @returns VBox status code.
1181	* @param pVM Pointer to VM structure.
1182	*/
1183	VMMR3DECL(int) PGMR3Init(PVM pVM)
1184	{
1185	LogFlow(("PGMR3Init:\n"));
1186	PCFGMNODE pCfgPGM = CFGMR3GetChild(CFGMR3GetRoot(pVM), "/PGM");
1187	int rc;
1188
1189	/*
1190	* Assert alignment and sizes.
1191	*/
1192	AssertCompile(sizeof(pVM->pgm.s) <= sizeof(pVM->pgm.padding));
1193	AssertCompileMemberAlignment(PGM, CritSect, sizeof(uintptr_t));
1194
1195	/*
1196	* Init the structure.
1197	*/
1198	pVM->pgm.s.offVM = RT_OFFSETOF(VM, pgm.s);
1199	pVM->pgm.s.offVCpuPGM = RT_OFFSETOF(VMCPU, pgm.s);
1200
1201	/* Init the per-CPU part. */
1202	for (unsigned i=0;i<pVM->cCPUs;i++)
1203	{
1204	PVMCPU pVCpu = &pVM->aCpus[i];
1205	PPGMCPU pPGM = &pVCpu->pgm.s;
1206
1207	pPGM->offVM = (uintptr_t)&pVCpu->pgm.s - (uintptr_t)pVM;
1208	pPGM->offVCpu = RT_OFFSETOF(VMCPU, pgm.s);
1209	pPGM->offPGM = (uintptr_t)&pVCpu->pgm.s - (uintptr_t)&pVM->pgm.s;
1210
1211	pPGM->enmShadowMode = PGMMODE_INVALID;
1212	pPGM->enmGuestMode = PGMMODE_INVALID;
1213
1214	pPGM->GCPhysCR3 = NIL_RTGCPHYS;
1215
1216	pPGM->pGstPaePdptR3 = NULL;
1217	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
1218	pPGM->pGstPaePdptR0 = NIL_RTR0PTR;
1219	#endif
1220	pPGM->pGstPaePdptRC = NIL_RTRCPTR;
1221	for (unsigned i = 0; i < RT_ELEMENTS(pVCpu->pgm.s.apGstPaePDsR3); i++)
1222	{
1223	pPGM->apGstPaePDsR3[i] = NULL;
1224	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
1225	pPGM->apGstPaePDsR0[i] = NIL_RTR0PTR;
1226	#endif
1227	pPGM->apGstPaePDsRC[i] = NIL_RTRCPTR;
1228	pPGM->aGCPhysGstPaePDs[i] = NIL_RTGCPHYS;
1229	pPGM->aGCPhysGstPaePDsMonitored[i] = NIL_RTGCPHYS;
1230	}
1231
1232	pPGM->fA20Enabled = true;
1233	}
1234
1235	pVM->pgm.s.enmHostMode = SUPPAGINGMODE_INVALID;
1236	pVM->pgm.s.GCPhys4MBPSEMask = RT_BIT_64(32) - 1; /* default; checked later */
1237	pVM->pgm.s.GCPtrPrevRamRangeMapping = MM_HYPER_AREA_ADDRESS;
1238
1239	rc = CFGMR3QueryBoolDef(CFGMR3GetRoot(pVM), "RamPreAlloc", &pVM->pgm.s.fRamPreAlloc,
1240	#ifdef VBOX_WITH_PREALLOC_RAM_BY_DEFAULT
1241	true
1242	#else
1243	false
1244	#endif
1245	);
1246	AssertLogRelRCReturn(rc, rc);
1247
1248	#if HC_ARCH_BITS == 64 \|\| 1 /** @todo 4GB/32-bit: remove \|\| 1 later and adjust the limit. */
1249	rc = CFGMR3QueryU32Def(pCfgPGM, "MaxRing3Chunks", &pVM->pgm.s.ChunkR3Map.cMax, UINT32_MAX);
1250	#else
1251	rc = CFGMR3QueryU32Def(pCfgPGM, "MaxRing3Chunks", &pVM->pgm.s.ChunkR3Map.cMax, _1G / GMM_CHUNK_SIZE);
1252	#endif
1253	AssertLogRelRCReturn(rc, rc);
1254	for (uint32_t i = 0; i < RT_ELEMENTS(pVM->pgm.s.ChunkR3Map.Tlb.aEntries); i++)
1255	pVM->pgm.s.ChunkR3Map.Tlb.aEntries[i].idChunk = NIL_GMM_CHUNKID;
1256
1257	/*
1258	* Get the configured RAM size - to estimate saved state size.
1259	*/
1260	uint64_t cbRam;
1261	rc = CFGMR3QueryU64(CFGMR3GetRoot(pVM), "RamSize", &cbRam);
1262	if (rc == VERR_CFGM_VALUE_NOT_FOUND)
1263	cbRam = 0;
1264	else if (RT_SUCCESS(rc))
1265	{
1266	if (cbRam < PAGE_SIZE)
1267	cbRam = 0;
1268	cbRam = RT_ALIGN_64(cbRam, PAGE_SIZE);
1269	}
1270	else
1271	{
1272	AssertMsgFailed(("Configuration error: Failed to query integer \"RamSize\", rc=%Rrc.\n", rc));
1273	return rc;
1274	}
1275
1276	/*
1277	* Register callbacks, string formatters and the saved state data unit.
1278	*/
1279	#ifdef VBOX_STRICT
1280	VMR3AtStateRegister(pVM, pgmR3ResetNoMorePhysWritesFlag, NULL);
1281	#endif
1282	PGMRegisterStringFormatTypes();
1283
1284	rc = SSMR3RegisterInternal(pVM, "pgm", 1, PGM_SAVED_STATE_VERSION, (size_t)cbRam + sizeof(PGM),
1285	NULL, pgmR3Save, NULL,
1286	NULL, pgmR3Load, NULL);
1287	if (RT_FAILURE(rc))
1288	return rc;
1289
1290	/*
1291	* Initialize the PGM critical section and flush the phys TLBs
1292	*/
1293	rc = PDMR3CritSectInit(pVM, &pVM->pgm.s.CritSect, "PGM");
1294	AssertRCReturn(rc, rc);
1295
1296	PGMR3PhysChunkInvalidateTLB(pVM);
1297	PGMPhysInvalidatePageR3MapTLB(pVM);
1298	PGMPhysInvalidatePageR0MapTLB(pVM);
1299	PGMPhysInvalidatePageGCMapTLB(pVM);
1300
1301	/*
1302	* For the time being we sport a full set of handy pages in addition to the base
1303	* memory to simplify things.
1304	*/
1305	rc = MMR3ReserveHandyPages(pVM, RT_ELEMENTS(pVM->pgm.s.aHandyPages)); /** @todo this should be changed to PGM_HANDY_PAGES_MIN but this needs proper testing... */
1306	AssertRCReturn(rc, rc);
1307
1308	/*
1309	* Trees
1310	*/
1311	rc = MMHyperAlloc(pVM, sizeof(PGMTREES), 0, MM_TAG_PGM, (void **)&pVM->pgm.s.pTreesR3);
1312	if (RT_SUCCESS(rc))
1313	{
1314	pVM->pgm.s.pTreesR0 = MMHyperR3ToR0(pVM, pVM->pgm.s.pTreesR3);
1315	pVM->pgm.s.pTreesRC = MMHyperR3ToRC(pVM, pVM->pgm.s.pTreesR3);
1316
1317	/*
1318	* Alocate the zero page.
1319	*/
1320	rc = MMHyperAlloc(pVM, PAGE_SIZE, PAGE_SIZE, MM_TAG_PGM, &pVM->pgm.s.pvZeroPgR3);
1321	}
1322	if (RT_SUCCESS(rc))
1323	{
1324	pVM->pgm.s.pvZeroPgRC = MMHyperR3ToRC(pVM, pVM->pgm.s.pvZeroPgR3);
1325	pVM->pgm.s.pvZeroPgR0 = MMHyperR3ToR0(pVM, pVM->pgm.s.pvZeroPgR3);
1326	pVM->pgm.s.HCPhysZeroPg = MMR3HyperHCVirt2HCPhys(pVM, pVM->pgm.s.pvZeroPgR3);
1327	AssertRelease(pVM->pgm.s.HCPhysZeroPg != NIL_RTHCPHYS);
1328
1329	/*
1330	* Init the paging.
1331	*/
1332	rc = pgmR3InitPaging(pVM);
1333	}
1334	if (RT_SUCCESS(rc))
1335	{
1336	/*
1337	* Init the page pool.
1338	*/
1339	rc = pgmR3PoolInit(pVM);
1340	}
1341	if (RT_SUCCESS(rc))
1342	{
1343	for (unsigned i=0;i<pVM->cCPUs;i++)
1344	{
1345	PVMCPU pVCpu = &pVM->aCpus[i];
1346
1347	rc = PGMR3ChangeMode(pVM, pVCpu, PGMMODE_REAL);
1348	if (RT_FAILURE(rc))
1349	break;
1350	}
1351	}
1352
1353	if (RT_SUCCESS(rc))
1354	{
1355	/*
1356	* Info & statistics
1357	*/
1358	DBGFR3InfoRegisterInternal(pVM, "mode",
1359	"Shows the current paging mode. "
1360	"Recognizes 'all', 'guest', 'shadow' and 'host' as arguments, defaulting to 'all' if nothing's given.",
1361	pgmR3InfoMode);
1362	DBGFR3InfoRegisterInternal(pVM, "pgmcr3",
1363	"Dumps all the entries in the top level paging table. No arguments.",
1364	pgmR3InfoCr3);
1365	DBGFR3InfoRegisterInternal(pVM, "phys",
1366	"Dumps all the physical address ranges. No arguments.",
1367	pgmR3PhysInfo);
1368	DBGFR3InfoRegisterInternal(pVM, "handlers",
1369	"Dumps physical, virtual and hyper virtual handlers. "
1370	"Pass 'phys', 'virt', 'hyper' as argument if only one kind is wanted."
1371	"Add 'nost' if the statistics are unwanted, use together with 'all' or explicit selection.",
1372	pgmR3InfoHandlers);
1373	DBGFR3InfoRegisterInternal(pVM, "mappings",
1374	"Dumps guest mappings.",
1375	pgmR3MapInfo);
1376
1377	pgmR3InitStats(pVM);
1378
1379	#ifdef VBOX_WITH_DEBUGGER
1380	/*
1381	* Debugger commands.
1382	*/
1383	static bool s_fRegisteredCmds = false;
1384	if (!s_fRegisteredCmds)
1385	{
1386	int rc = DBGCRegisterCommands(&g_aCmds[0], RT_ELEMENTS(g_aCmds));
1387	if (RT_SUCCESS(rc))
1388	s_fRegisteredCmds = true;
1389	}
1390	#endif
1391	return VINF_SUCCESS;
1392	}
1393
1394	/* Almost no cleanup necessary, MM frees all memory. */
1395	PDMR3CritSectDelete(&pVM->pgm.s.CritSect);
1396
1397	return rc;
1398	}
1399
1400
1401	/**
1402	* Initializes the per-VCPU PGM.
1403	*
1404	* @returns VBox status code.
1405	* @param pVM The VM to operate on.
1406	*/
1407	VMMR3DECL(int) PGMR3InitCPU(PVM pVM)
1408	{
1409	LogFlow(("PGMR3InitCPU\n"));
1410	return VINF_SUCCESS;
1411	}
1412
1413
1414	/**
1415	* Init paging.
1416	*
1417	* Since we need to check what mode the host is operating in before we can choose
1418	* the right paging functions for the host we have to delay this until R0 has
1419	* been initialized.
1420	*
1421	* @returns VBox status code.
1422	* @param pVM VM handle.
1423	*/
1424	static int pgmR3InitPaging(PVM pVM)
1425	{
1426	/*
1427	* Force a recalculation of modes and switcher so everyone gets notified.
1428	*/
1429	for (unsigned i=0;i<pVM->cCPUs;i++)
1430	{
1431	PVMCPU pVCpu = &pVM->aCpus[i];
1432
1433	pVCpu->pgm.s.enmShadowMode = PGMMODE_INVALID;
1434	pVCpu->pgm.s.enmGuestMode = PGMMODE_INVALID;
1435	}
1436
1437	pVM->pgm.s.enmHostMode = SUPPAGINGMODE_INVALID;
1438
1439	/*
1440	* Allocate static mapping space for whatever the cr3 register
1441	* points to and in the case of PAE mode to the 4 PDs.
1442	*/
1443	int rc = MMR3HyperReserve(pVM, PAGE_SIZE * 5, "CR3 mapping", &pVM->pgm.s.GCPtrCR3Mapping);
1444	if (RT_FAILURE(rc))
1445	{
1446	AssertMsgFailed(("Failed to reserve two pages for cr mapping in HMA, rc=%Rrc\n", rc));
1447	return rc;
1448	}
1449	MMR3HyperReserve(pVM, PAGE_SIZE, "fence", NULL);
1450
1451	/*
1452	* Allocate pages for the three possible intermediate contexts
1453	* (AMD64, PAE and plain 32-Bit). We maintain all three contexts
1454	* for the sake of simplicity. The AMD64 uses the PAE for the
1455	* lower levels, making the total number of pages 11 (3 + 7 + 1).
1456	*
1457	* We assume that two page tables will be enought for the core code
1458	* mappings (HC virtual and identity).
1459	*/
1460	pVM->pgm.s.pInterPD = (PX86PD)MMR3PageAllocLow(pVM); AssertReturn(pVM->pgm.s.pInterPD, VERR_NO_PAGE_MEMORY);
1461	pVM->pgm.s.apInterPTs[0] = (PX86PT)MMR3PageAllocLow(pVM); AssertReturn(pVM->pgm.s.apInterPTs[0], VERR_NO_PAGE_MEMORY);
1462	pVM->pgm.s.apInterPTs[1] = (PX86PT)MMR3PageAllocLow(pVM); AssertReturn(pVM->pgm.s.apInterPTs[1], VERR_NO_PAGE_MEMORY);
1463	pVM->pgm.s.apInterPaePTs[0] = (PX86PTPAE)MMR3PageAlloc(pVM); AssertReturn(pVM->pgm.s.apInterPaePTs[0], VERR_NO_PAGE_MEMORY);
1464	pVM->pgm.s.apInterPaePTs[1] = (PX86PTPAE)MMR3PageAlloc(pVM); AssertReturn(pVM->pgm.s.apInterPaePTs[1], VERR_NO_PAGE_MEMORY);
1465	pVM->pgm.s.apInterPaePDs[0] = (PX86PDPAE)MMR3PageAlloc(pVM); AssertReturn(pVM->pgm.s.apInterPaePDs[0], VERR_NO_PAGE_MEMORY);
1466	pVM->pgm.s.apInterPaePDs[1] = (PX86PDPAE)MMR3PageAlloc(pVM); AssertReturn(pVM->pgm.s.apInterPaePDs[1], VERR_NO_PAGE_MEMORY);
1467	pVM->pgm.s.apInterPaePDs[2] = (PX86PDPAE)MMR3PageAlloc(pVM); AssertReturn(pVM->pgm.s.apInterPaePDs[2], VERR_NO_PAGE_MEMORY);
1468	pVM->pgm.s.apInterPaePDs[3] = (PX86PDPAE)MMR3PageAlloc(pVM); AssertReturn(pVM->pgm.s.apInterPaePDs[3], VERR_NO_PAGE_MEMORY);
1469	pVM->pgm.s.pInterPaePDPT = (PX86PDPT)MMR3PageAllocLow(pVM); AssertReturn(pVM->pgm.s.pInterPaePDPT, VERR_NO_PAGE_MEMORY);
1470	pVM->pgm.s.pInterPaePDPT64 = (PX86PDPT)MMR3PageAllocLow(pVM); AssertReturn(pVM->pgm.s.pInterPaePDPT64, VERR_NO_PAGE_MEMORY);
1471	pVM->pgm.s.pInterPaePML4 = (PX86PML4)MMR3PageAllocLow(pVM); AssertReturn(pVM->pgm.s.pInterPaePML4, VERR_NO_PAGE_MEMORY);
1472
1473	pVM->pgm.s.HCPhysInterPD = MMPage2Phys(pVM, pVM->pgm.s.pInterPD);
1474	AssertRelease(pVM->pgm.s.HCPhysInterPD != NIL_RTHCPHYS && !(pVM->pgm.s.HCPhysInterPD & PAGE_OFFSET_MASK));
1475	pVM->pgm.s.HCPhysInterPaePDPT = MMPage2Phys(pVM, pVM->pgm.s.pInterPaePDPT);
1476	AssertRelease(pVM->pgm.s.HCPhysInterPaePDPT != NIL_RTHCPHYS && !(pVM->pgm.s.HCPhysInterPaePDPT & PAGE_OFFSET_MASK));
1477	pVM->pgm.s.HCPhysInterPaePML4 = MMPage2Phys(pVM, pVM->pgm.s.pInterPaePML4);
1478	AssertRelease(pVM->pgm.s.HCPhysInterPaePML4 != NIL_RTHCPHYS && !(pVM->pgm.s.HCPhysInterPaePML4 & PAGE_OFFSET_MASK) && pVM->pgm.s.HCPhysInterPaePML4 < 0xffffffff);
1479
1480	/*
1481	* Initialize the pages, setting up the PML4 and PDPT for repetitive 4GB action.
1482	*/
1483	ASMMemZeroPage(pVM->pgm.s.pInterPD);
1484	ASMMemZeroPage(pVM->pgm.s.apInterPTs[0]);
1485	ASMMemZeroPage(pVM->pgm.s.apInterPTs[1]);
1486
1487	ASMMemZeroPage(pVM->pgm.s.apInterPaePTs[0]);
1488	ASMMemZeroPage(pVM->pgm.s.apInterPaePTs[1]);
1489
1490	ASMMemZeroPage(pVM->pgm.s.pInterPaePDPT);
1491	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.apInterPaePDs); i++)
1492	{
1493	ASMMemZeroPage(pVM->pgm.s.apInterPaePDs[i]);
1494	pVM->pgm.s.pInterPaePDPT->a[i].u = X86_PDPE_P \| PGM_PLXFLAGS_PERMANENT
1495	\| MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[i]);
1496	}
1497
1498	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.pInterPaePDPT64->a); i++)
1499	{
1500	const unsigned iPD = i % RT_ELEMENTS(pVM->pgm.s.apInterPaePDs);
1501	pVM->pgm.s.pInterPaePDPT64->a[i].u = X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_A \| PGM_PLXFLAGS_PERMANENT
1502	\| MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[iPD]);
1503	}
1504
1505	RTHCPHYS HCPhysInterPaePDPT64 = MMPage2Phys(pVM, pVM->pgm.s.pInterPaePDPT64);
1506	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.pInterPaePML4->a); i++)
1507	pVM->pgm.s.pInterPaePML4->a[i].u = X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_A \| PGM_PLXFLAGS_PERMANENT
1508	\| HCPhysInterPaePDPT64;
1509
1510	/*
1511	* Initialize paging workers and mode from current host mode
1512	* and the guest running in real mode.
1513	*/
1514	pVM->pgm.s.enmHostMode = SUPR3GetPagingMode();
1515	switch (pVM->pgm.s.enmHostMode)
1516	{
1517	case SUPPAGINGMODE_32_BIT:
1518	case SUPPAGINGMODE_32_BIT_GLOBAL:
1519	case SUPPAGINGMODE_PAE:
1520	case SUPPAGINGMODE_PAE_GLOBAL:
1521	case SUPPAGINGMODE_PAE_NX:
1522	case SUPPAGINGMODE_PAE_GLOBAL_NX:
1523	break;
1524
1525	case SUPPAGINGMODE_AMD64:
1526	case SUPPAGINGMODE_AMD64_GLOBAL:
1527	case SUPPAGINGMODE_AMD64_NX:
1528	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
1529	#ifndef VBOX_WITH_HYBRID_32BIT_KERNEL
1530	if (ARCH_BITS != 64)
1531	{
1532	AssertMsgFailed(("Host mode %d (64-bit) is not supported by non-64bit builds\n", pVM->pgm.s.enmHostMode));
1533	LogRel(("Host mode %d (64-bit) is not supported by non-64bit builds\n", pVM->pgm.s.enmHostMode));
1534	return VERR_PGM_UNSUPPORTED_HOST_PAGING_MODE;
1535	}
1536	#endif
1537	break;
1538	default:
1539	AssertMsgFailed(("Host mode %d is not supported\n", pVM->pgm.s.enmHostMode));
1540	return VERR_PGM_UNSUPPORTED_HOST_PAGING_MODE;
1541	}
1542	rc = pgmR3ModeDataInit(pVM, false /* don't resolve GC and R0 syms yet */);
1543	if (RT_SUCCESS(rc))
1544	{
1545	LogFlow(("pgmR3InitPaging: returns successfully\n"));
1546	#if HC_ARCH_BITS == 64
1547	LogRel(("Debug: HCPhysInterPD=%RHp HCPhysInterPaePDPT=%RHp HCPhysInterPaePML4=%RHp\n",
1548	pVM->pgm.s.HCPhysInterPD, pVM->pgm.s.HCPhysInterPaePDPT, pVM->pgm.s.HCPhysInterPaePML4));
1549	LogRel(("Debug: apInterPTs={%RHp,%RHp} apInterPaePTs={%RHp,%RHp} apInterPaePDs={%RHp,%RHp,%RHp,%RHp} pInterPaePDPT64=%RHp\n",
1550	MMPage2Phys(pVM, pVM->pgm.s.apInterPTs[0]), MMPage2Phys(pVM, pVM->pgm.s.apInterPTs[1]),
1551	MMPage2Phys(pVM, pVM->pgm.s.apInterPaePTs[0]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePTs[1]),
1552	MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[0]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[1]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[2]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[3]),
1553	MMPage2Phys(pVM, pVM->pgm.s.pInterPaePDPT64)));
1554	#endif
1555
1556	return VINF_SUCCESS;
1557	}
1558
1559	LogFlow(("pgmR3InitPaging: returns %Rrc\n", rc));
1560	return rc;
1561	}
1562
1563
1564	/**
1565	* Init statistics
1566	*/
1567	static void pgmR3InitStats(PVM pVM)
1568	{
1569	PPGM pPGM = &pVM->pgm.s;
1570	int rc;
1571
1572	/* Common - misc variables */
1573	STAM_REL_REG(pVM, &pPGM->cAllPages, STAMTYPE_U32, "/PGM/Page/cAllPages", STAMUNIT_OCCURENCES, "The total number of pages.");
1574	STAM_REL_REG(pVM, &pPGM->cPrivatePages, STAMTYPE_U32, "/PGM/Page/cPrivatePages", STAMUNIT_OCCURENCES, "The number of private pages.");
1575	STAM_REL_REG(pVM, &pPGM->cSharedPages, STAMTYPE_U32, "/PGM/Page/cSharedPages", STAMUNIT_OCCURENCES, "The number of shared pages.");
1576	STAM_REL_REG(pVM, &pPGM->cZeroPages, STAMTYPE_U32, "/PGM/Page/cZeroPages", STAMUNIT_OCCURENCES, "The number of zero backed pages.");
1577	STAM_REL_REG(pVM, &pPGM->cHandyPages, STAMTYPE_U32, "/PGM/Page/cHandyPages", STAMUNIT_OCCURENCES, "The number of handy pages (not included in cAllPages).");
1578	STAM_REL_REG(pVM, &pPGM->cRelocations, STAMTYPE_COUNTER, "/PGM/cRelocations", STAMUNIT_OCCURENCES, "Number of hypervisor relocations.");
1579	STAM_REL_REG(pVM, &pPGM->ChunkR3Map.c, STAMTYPE_U32, "/PGM/ChunkR3Map/c", STAMUNIT_OCCURENCES, "Number of mapped chunks.");
1580	STAM_REL_REG(pVM, &pPGM->ChunkR3Map.cMax, STAMTYPE_U32, "/PGM/ChunkR3Map/cMax", STAMUNIT_OCCURENCES, "Maximum number of mapped chunks.");
1581
1582	#ifdef VBOX_WITH_STATISTICS
1583
1584	# define PGM_REG_COUNTER(a, b, c) \
1585	rc = STAMR3RegisterF(pVM, a, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, c, b); \
1586	AssertRC(rc);
1587
1588	# define PGM_REG_COUNTER_BYTES(a, b, c) \
1589	rc = STAMR3RegisterF(pVM, a, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_BYTES, c, b); \
1590	AssertRC(rc);
1591
1592	# define PGM_REG_PROFILE(a, b, c) \
1593	rc = STAMR3RegisterF(pVM, a, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, c, b); \
1594	AssertRC(rc);
1595
1596	PGM_REG_COUNTER(&pPGM->StatR3DetectedConflicts, "/PGM/R3/DetectedConflicts", "The number of times PGMR3CheckMappingConflicts() detected a conflict.");
1597	PGM_REG_PROFILE(&pPGM->StatR3ResolveConflict, "/PGM/R3/ResolveConflict", "pgmR3SyncPTResolveConflict() profiling (includes the entire relocation).");
1598	PGM_REG_COUNTER(&pPGM->StatR3PhysRead, "/PGM/R3/Phys/Read", "The number of times PGMPhysRead was called.");
1599	PGM_REG_COUNTER_BYTES(&pPGM->StatR3PhysReadBytes, "/PGM/R3/Phys/Read/Bytes", "The number of bytes read by PGMPhysRead.");
1600	PGM_REG_COUNTER(&pPGM->StatR3PhysWrite, "/PGM/R3/Phys/Write", "The number of times PGMPhysWrite was called.");
1601	PGM_REG_COUNTER_BYTES(&pPGM->StatR3PhysWriteBytes, "/PGM/R3/Phys/Write/Bytes", "The number of bytes written by PGMPhysWrite.");
1602	PGM_REG_COUNTER(&pPGM->StatR3PhysSimpleRead, "/PGM/R3/Phys/Simple/Read", "The number of times PGMPhysSimpleReadGCPtr was called.");
1603	PGM_REG_COUNTER_BYTES(&pPGM->StatR3PhysSimpleReadBytes, "/PGM/R3/Phys/Simple/Read/Bytes", "The number of bytes read by PGMPhysSimpleReadGCPtr.");
1604	PGM_REG_COUNTER(&pPGM->StatR3PhysSimpleWrite, "/PGM/R3/Phys/Simple/Write", "The number of times PGMPhysSimpleWriteGCPtr was called.");
1605	PGM_REG_COUNTER_BYTES(&pPGM->StatR3PhysSimpleWriteBytes, "/PGM/R3/Phys/Simple/Write/Bytes", "The number of bytes written by PGMPhysSimpleWriteGCPtr.");
1606
1607	PGM_REG_COUNTER(&pPGM->StatRZChunkR3MapTlbHits, "/PGM/ChunkR3Map/TlbHitsRZ", "TLB hits.");
1608	PGM_REG_COUNTER(&pPGM->StatRZChunkR3MapTlbMisses, "/PGM/ChunkR3Map/TlbMissesRZ", "TLB misses.");
1609	PGM_REG_COUNTER(&pPGM->StatRZPageMapTlbHits, "/PGM/RZ/Page/MapTlbHits", "TLB hits.");
1610	PGM_REG_COUNTER(&pPGM->StatRZPageMapTlbMisses, "/PGM/RZ/Page/MapTlbMisses", "TLB misses.");
1611	PGM_REG_COUNTER(&pPGM->StatR3ChunkR3MapTlbHits, "/PGM/ChunkR3Map/TlbHitsR3", "TLB hits.");
1612	PGM_REG_COUNTER(&pPGM->StatR3ChunkR3MapTlbMisses, "/PGM/ChunkR3Map/TlbMissesR3", "TLB misses.");
1613	PGM_REG_COUNTER(&pPGM->StatR3PageMapTlbHits, "/PGM/R3/Page/MapTlbHits", "TLB hits.");
1614	PGM_REG_COUNTER(&pPGM->StatR3PageMapTlbMisses, "/PGM/R3/Page/MapTlbMisses", "TLB misses.");
1615
1616	PGM_REG_PROFILE(&pPGM->StatRZSyncCR3HandlerVirtualUpdate, "/PGM/RZ/SyncCR3/Handlers/VirtualUpdate", "Profiling of the virtual handler updates.");
1617	PGM_REG_PROFILE(&pPGM->StatRZSyncCR3HandlerVirtualReset, "/PGM/RZ/SyncCR3/Handlers/VirtualReset", "Profiling of the virtual handler resets.");
1618	PGM_REG_PROFILE(&pPGM->StatR3SyncCR3HandlerVirtualUpdate, "/PGM/R3/SyncCR3/Handlers/VirtualUpdate", "Profiling of the virtual handler updates.");
1619	PGM_REG_PROFILE(&pPGM->StatR3SyncCR3HandlerVirtualReset, "/PGM/R3/SyncCR3/Handlers/VirtualReset", "Profiling of the virtual handler resets.");
1620
1621	PGM_REG_COUNTER(&pPGM->StatRZPhysHandlerReset, "/PGM/RZ/PhysHandlerReset", "The number of times PGMHandlerPhysicalReset is called.");
1622	PGM_REG_COUNTER(&pPGM->StatR3PhysHandlerReset, "/PGM/R3/PhysHandlerReset", "The number of times PGMHandlerPhysicalReset is called.");
1623	PGM_REG_PROFILE(&pPGM->StatRZVirtHandlerSearchByPhys, "/PGM/RZ/VirtHandlerSearchByPhys", "Profiling of pgmHandlerVirtualFindByPhysAddr.");
1624	PGM_REG_PROFILE(&pPGM->StatR3VirtHandlerSearchByPhys, "/PGM/R3/VirtHandlerSearchByPhys", "Profiling of pgmHandlerVirtualFindByPhysAddr.");
1625
1626	PGM_REG_COUNTER(&pPGM->StatRZPageReplaceShared, "/PGM/RZ/Page/ReplacedShared", "Times a shared page was replaced.");
1627	PGM_REG_COUNTER(&pPGM->StatRZPageReplaceZero, "/PGM/RZ/Page/ReplacedZero", "Times the zero page was replaced.");
1628	/// @todo PGM_REG_COUNTER(&pPGM->StatRZPageHandyAllocs, "/PGM/RZ/Page/HandyAllocs", "Number of times we've allocated more handy pages.");
1629	PGM_REG_COUNTER(&pPGM->StatR3PageReplaceShared, "/PGM/R3/Page/ReplacedShared", "Times a shared page was replaced.");
1630	PGM_REG_COUNTER(&pPGM->StatR3PageReplaceZero, "/PGM/R3/Page/ReplacedZero", "Times the zero page was replaced.");
1631	/// @todo PGM_REG_COUNTER(&pPGM->StatR3PageHandyAllocs, "/PGM/R3/Page/HandyAllocs", "Number of times we've allocated more handy pages.");
1632
1633	PGM_REG_COUNTER(&pPGM->StatRZPhysRead, "/PGM/RZ/Phys/Read", "The number of times PGMPhysRead was called.");
1634	PGM_REG_COUNTER_BYTES(&pPGM->StatRZPhysReadBytes, "/PGM/RZ/Phys/Read/Bytes", "The number of bytes read by PGMPhysRead.");
1635	PGM_REG_COUNTER(&pPGM->StatRZPhysWrite, "/PGM/RZ/Phys/Write", "The number of times PGMPhysWrite was called.");
1636	PGM_REG_COUNTER_BYTES(&pPGM->StatRZPhysWriteBytes, "/PGM/RZ/Phys/Write/Bytes", "The number of bytes written by PGMPhysWrite.");
1637	PGM_REG_COUNTER(&pPGM->StatRZPhysSimpleRead, "/PGM/RZ/Phys/Simple/Read", "The number of times PGMPhysSimpleReadGCPtr was called.");
1638	PGM_REG_COUNTER_BYTES(&pPGM->StatRZPhysSimpleReadBytes, "/PGM/RZ/Phys/Simple/Read/Bytes", "The number of bytes read by PGMPhysSimpleReadGCPtr.");
1639	PGM_REG_COUNTER(&pPGM->StatRZPhysSimpleWrite, "/PGM/RZ/Phys/Simple/Write", "The number of times PGMPhysSimpleWriteGCPtr was called.");
1640	PGM_REG_COUNTER_BYTES(&pPGM->StatRZPhysSimpleWriteBytes, "/PGM/RZ/Phys/Simple/Write/Bytes", "The number of bytes written by PGMPhysSimpleWriteGCPtr.");
1641
1642	/* GC only: */
1643	PGM_REG_COUNTER(&pPGM->StatRCDynMapCacheHits, "/PGM/RC/DynMapCache/Hits" , "Number of dynamic page mapping cache hits.");
1644	PGM_REG_COUNTER(&pPGM->StatRCDynMapCacheMisses, "/PGM/RC/DynMapCache/Misses" , "Number of dynamic page mapping cache misses.");
1645	PGM_REG_COUNTER(&pPGM->StatRCInvlPgConflict, "/PGM/RC/InvlPgConflict", "Number of times PGMInvalidatePage() detected a mapping conflict.");
1646	PGM_REG_COUNTER(&pPGM->StatRCInvlPgSyncMonCR3, "/PGM/RC/InvlPgSyncMonitorCR3", "Number of times PGMInvalidatePage() ran into PGM_SYNC_MONITOR_CR3.");
1647
1648	PGM_REG_COUNTER(&pPGM->StatRCPhysRead, "/PGM/RC/Phys/Read", "The number of times PGMPhysRead was called.");
1649	PGM_REG_COUNTER_BYTES(&pPGM->StatRCPhysReadBytes, "/PGM/RC/Phys/Read/Bytes", "The number of bytes read by PGMPhysRead.");
1650	PGM_REG_COUNTER(&pPGM->StatRCPhysWrite, "/PGM/RC/Phys/Write", "The number of times PGMPhysWrite was called.");
1651	PGM_REG_COUNTER_BYTES(&pPGM->StatRCPhysWriteBytes, "/PGM/RC/Phys/Write/Bytes", "The number of bytes written by PGMPhysWrite.");
1652	PGM_REG_COUNTER(&pPGM->StatRCPhysSimpleRead, "/PGM/RC/Phys/Simple/Read", "The number of times PGMPhysSimpleReadGCPtr was called.");
1653	PGM_REG_COUNTER_BYTES(&pPGM->StatRCPhysSimpleReadBytes, "/PGM/RC/Phys/Simple/Read/Bytes", "The number of bytes read by PGMPhysSimpleReadGCPtr.");
1654	PGM_REG_COUNTER(&pPGM->StatRCPhysSimpleWrite, "/PGM/RC/Phys/Simple/Write", "The number of times PGMPhysSimpleWriteGCPtr was called.");
1655	PGM_REG_COUNTER_BYTES(&pPGM->StatRCPhysSimpleWriteBytes, "/PGM/RC/Phys/Simple/Write/Bytes", "The number of bytes written by PGMPhysSimpleWriteGCPtr.");
1656
1657	# ifdef PGMPOOL_WITH_GCPHYS_TRACKING
1658	PGM_REG_COUNTER(&pPGM->StatTrackVirgin, "/PGM/Track/Virgin", "The number of first time shadowings");
1659	PGM_REG_COUNTER(&pPGM->StatTrackAliased, "/PGM/Track/Aliased", "The number of times switching to cRef2, i.e. the page is being shadowed by two PTs.");
1660	PGM_REG_COUNTER(&pPGM->StatTrackAliasedMany, "/PGM/Track/AliasedMany", "The number of times we're tracking using cRef2.");
1661	PGM_REG_COUNTER(&pPGM->StatTrackAliasedLots, "/PGM/Track/AliasedLots", "The number of times we're hitting pages which has overflowed cRef2");
1662	PGM_REG_COUNTER(&pPGM->StatTrackOverflows, "/PGM/Track/Overflows", "The number of times the extent list grows too long.");
1663	PGM_REG_PROFILE(&pPGM->StatTrackDeref, "/PGM/Track/Deref", "Profiling of SyncPageWorkerTrackDeref (expensive).");
1664	# endif
1665
1666	# undef PGM_REG_COUNTER
1667	# undef PGM_REG_PROFILE
1668	#endif
1669
1670	/*
1671	* Note! The layout below matches the member layout exactly!
1672	*/
1673
1674	/*
1675	* Common - stats
1676	*/
1677	for (unsigned i=0;i<pVM->cCPUs;i++)
1678	{
1679	PVMCPU pVCpu = &pVM->aCpus[i];
1680	PPGMCPU pPGM = &pVCpu->pgm.s;
1681
1682	#define PGM_REG_COUNTER(a, b, c) \
1683	rc = STAMR3RegisterF(pVM, a, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, c, b, i); \
1684	AssertRC(rc);
1685	#define PGM_REG_PROFILE(a, b, c) \
1686	rc = STAMR3RegisterF(pVM, a, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, c, b, i); \
1687	AssertRC(rc);
1688
1689	PGM_REG_COUNTER(&pPGM->cGuestModeChanges, "/PGM/CPU%d/cGuestModeChanges", "Number of guest mode changes.");
1690
1691	#ifdef VBOX_WITH_STATISTICS
1692	for (unsigned j = 0; j < RT_ELEMENTS(pPGM->StatSyncPtPD); j++)
1693	STAMR3RegisterF(pVM, &pPGM->StatSyncPtPD[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
1694	"The number of SyncPT per PD n.", "/PGM/CPU%d/PDSyncPT/%04X", i, j);
1695	for (unsigned j = 0; j < RT_ELEMENTS(pPGM->StatSyncPagePD); j++)
1696	STAMR3RegisterF(pVM, &pPGM->StatSyncPagePD[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
1697	"The number of SyncPage per PD n.", "/PGM/CPU%d/PDSyncPage/%04X", i, j);
1698
1699	/* R0 only: */
1700	PGM_REG_COUNTER(&pPGM->StatR0DynMapMigrateInvlPg, "/PGM/CPU%d/R0/DynMapMigrateInvlPg", "invlpg count in PGMDynMapMigrateAutoSet.");
1701	PGM_REG_PROFILE(&pPGM->StatR0DynMapGCPageInl, "/PGM/CPU%d/R0/DynMapPageGCPageInl", "Calls to pgmR0DynMapGCPageInlined.");
1702	PGM_REG_COUNTER(&pPGM->StatR0DynMapGCPageInlHits, "/PGM/CPU%d/R0/DynMapPageGCPageInl/Hits", "Hash table lookup hits.");
1703	PGM_REG_COUNTER(&pPGM->StatR0DynMapGCPageInlMisses, "/PGM/CPU%d/R0/DynMapPageGCPageInl/Misses", "Misses that falls back to code common with PGMDynMapHCPage.");
1704	PGM_REG_COUNTER(&pPGM->StatR0DynMapGCPageInlRamHits, "/PGM/CPU%d/R0/DynMapPageGCPageInl/RamHits", "1st ram range hits.");
1705	PGM_REG_COUNTER(&pPGM->StatR0DynMapGCPageInlRamMisses, "/PGM/CPU%d/R0/DynMapPageGCPageInl/RamMisses", "1st ram range misses, takes slow path.");
1706	PGM_REG_PROFILE(&pPGM->StatR0DynMapHCPageInl, "/PGM/CPU%d/R0/DynMapPageHCPageInl", "Calls to pgmR0DynMapHCPageInlined.");
1707	PGM_REG_COUNTER(&pPGM->StatR0DynMapHCPageInlHits, "/PGM/CPU%d/R0/DynMapPageHCPageInl/Hits", "Hash table lookup hits.");
1708	PGM_REG_COUNTER(&pPGM->StatR0DynMapHCPageInlMisses, "/PGM/CPU%d/R0/DynMapPageHCPageInl/Misses", "Misses that falls back to code common with PGMDynMapHCPage.");
1709	PGM_REG_COUNTER(&pPGM->StatR0DynMapPage, "/PGM/CPU%d/R0/DynMapPage", "Calls to pgmR0DynMapPage");
1710	PGM_REG_COUNTER(&pPGM->StatR0DynMapSetOptimize, "/PGM/CPU%d/R0/DynMapPage/SetOptimize", "Calls to pgmDynMapOptimizeAutoSet.");
1711	PGM_REG_COUNTER(&pPGM->StatR0DynMapSetSearchFlushes, "/PGM/CPU%d/R0/DynMapPage/SetSearchFlushes","Set search restorting to subset flushes.");
1712	PGM_REG_COUNTER(&pPGM->StatR0DynMapSetSearchHits, "/PGM/CPU%d/R0/DynMapPage/SetSearchHits", "Set search hits.");
1713	PGM_REG_COUNTER(&pPGM->StatR0DynMapSetSearchMisses, "/PGM/CPU%d/R0/DynMapPage/SetSearchMisses", "Set search misses.");
1714	PGM_REG_PROFILE(&pPGM->StatR0DynMapHCPage, "/PGM/CPU%d/R0/DynMapPage/HCPage", "Calls to PGMDynMapHCPage (ring-0).");
1715	PGM_REG_COUNTER(&pPGM->StatR0DynMapPageHits0, "/PGM/CPU%d/R0/DynMapPage/Hits0", "Hits at iPage+0");
1716	PGM_REG_COUNTER(&pPGM->StatR0DynMapPageHits1, "/PGM/CPU%d/R0/DynMapPage/Hits1", "Hits at iPage+1");
1717	PGM_REG_COUNTER(&pPGM->StatR0DynMapPageHits2, "/PGM/CPU%d/R0/DynMapPage/Hits2", "Hits at iPage+2");
1718	PGM_REG_COUNTER(&pPGM->StatR0DynMapPageInvlPg, "/PGM/CPU%d/R0/DynMapPage/InvlPg", "invlpg count in pgmR0DynMapPageSlow.");
1719	PGM_REG_COUNTER(&pPGM->StatR0DynMapPageSlow, "/PGM/CPU%d/R0/DynMapPage/Slow", "Calls to pgmR0DynMapPageSlow - subtract this from pgmR0DynMapPage to get 1st level hits.");
1720	PGM_REG_COUNTER(&pPGM->StatR0DynMapPageSlowLoopHits, "/PGM/CPU%d/R0/DynMapPage/SlowLoopHits" , "Hits in the loop path.");
1721	PGM_REG_COUNTER(&pPGM->StatR0DynMapPageSlowLoopMisses, "/PGM/CPU%d/R0/DynMapPage/SlowLoopMisses", "Misses in the loop path. NonLoopMisses = Slow - SlowLoopHit - SlowLoopMisses");
1722	//PGM_REG_COUNTER(&pPGM->StatR0DynMapPageSlowLostHits, "/PGM/CPU%d/R0/DynMapPage/SlowLostHits", "Lost hits.");
1723	PGM_REG_COUNTER(&pPGM->StatR0DynMapSubsets, "/PGM/CPU%d/R0/Subsets", "Times PGMDynMapPushAutoSubset was called.");
1724	PGM_REG_COUNTER(&pPGM->StatR0DynMapPopFlushes, "/PGM/CPU%d/R0/SubsetPopFlushes", "Times PGMDynMapPopAutoSubset flushes the subset.");
1725	PGM_REG_COUNTER(&pPGM->aStatR0DynMapSetSize[0], "/PGM/CPU%d/R0/SetSize000..09", "00-09% filled");
1726	PGM_REG_COUNTER(&pPGM->aStatR0DynMapSetSize[1], "/PGM/CPU%d/R0/SetSize010..19", "10-19% filled");
1727	PGM_REG_COUNTER(&pPGM->aStatR0DynMapSetSize[2], "/PGM/CPU%d/R0/SetSize020..29", "20-29% filled");
1728	PGM_REG_COUNTER(&pPGM->aStatR0DynMapSetSize[3], "/PGM/CPU%d/R0/SetSize030..39", "30-39% filled");
1729	PGM_REG_COUNTER(&pPGM->aStatR0DynMapSetSize[4], "/PGM/CPU%d/R0/SetSize040..49", "40-49% filled");
1730	PGM_REG_COUNTER(&pPGM->aStatR0DynMapSetSize[5], "/PGM/CPU%d/R0/SetSize050..59", "50-59% filled");
1731	PGM_REG_COUNTER(&pPGM->aStatR0DynMapSetSize[6], "/PGM/CPU%d/R0/SetSize060..69", "60-69% filled");
1732	PGM_REG_COUNTER(&pPGM->aStatR0DynMapSetSize[7], "/PGM/CPU%d/R0/SetSize070..79", "70-79% filled");
1733	PGM_REG_COUNTER(&pPGM->aStatR0DynMapSetSize[8], "/PGM/CPU%d/R0/SetSize080..89", "80-89% filled");
1734	PGM_REG_COUNTER(&pPGM->aStatR0DynMapSetSize[9], "/PGM/CPU%d/R0/SetSize090..99", "90-99% filled");
1735	PGM_REG_COUNTER(&pPGM->aStatR0DynMapSetSize[10], "/PGM/CPU%d/R0/SetSize100", "100% filled");
1736
1737	/* RZ only: */
1738	PGM_REG_PROFILE(&pPGM->StatRZTrap0e, "/PGM/CPU%d/RZ/Trap0e", "Profiling of the PGMTrap0eHandler() body.");
1739	PGM_REG_PROFILE(&pPGM->StatRZTrap0eTimeCheckPageFault, "/PGM/CPU%d/RZ/Trap0e/Time/CheckPageFault", "Profiling of checking for dirty/access emulation faults.");
1740	PGM_REG_PROFILE(&pPGM->StatRZTrap0eTimeSyncPT, "/PGM/CPU%d/RZ/Trap0e/Time/SyncPT", "Profiling of lazy page table syncing.");
1741	PGM_REG_PROFILE(&pPGM->StatRZTrap0eTimeMapping, "/PGM/CPU%d/RZ/Trap0e/Time/Mapping", "Profiling of checking virtual mappings.");
1742	PGM_REG_PROFILE(&pPGM->StatRZTrap0eTimeOutOfSync, "/PGM/CPU%d/RZ/Trap0e/Time/OutOfSync", "Profiling of out of sync page handling.");
1743	PGM_REG_PROFILE(&pPGM->StatRZTrap0eTimeHandlers, "/PGM/CPU%d/RZ/Trap0e/Time/Handlers", "Profiling of checking handlers.");
1744	PGM_REG_PROFILE(&pPGM->StatRZTrap0eTime2CSAM, "/PGM/CPU%d/RZ/Trap0e/Time2/CSAM", "Profiling of the Trap0eHandler body when the cause is CSAM.");
1745	PGM_REG_PROFILE(&pPGM->StatRZTrap0eTime2DirtyAndAccessed, "/PGM/CPU%d/RZ/Trap0e/Time2/DirtyAndAccessedBits", "Profiling of the Trap0eHandler body when the cause is dirty and/or accessed bit emulation.");
1746	PGM_REG_PROFILE(&pPGM->StatRZTrap0eTime2GuestTrap, "/PGM/CPU%d/RZ/Trap0e/Time2/GuestTrap", "Profiling of the Trap0eHandler body when the cause is a guest trap.");
1747	PGM_REG_PROFILE(&pPGM->StatRZTrap0eTime2HndPhys, "/PGM/CPU%d/RZ/Trap0e/Time2/HandlerPhysical", "Profiling of the Trap0eHandler body when the cause is a physical handler.");
1748	PGM_REG_PROFILE(&pPGM->StatRZTrap0eTime2HndVirt, "/PGM/CPU%d/RZ/Trap0e/Time2/HandlerVirtual", "Profiling of the Trap0eHandler body when the cause is a virtual handler.");
1749	PGM_REG_PROFILE(&pPGM->StatRZTrap0eTime2HndUnhandled, "/PGM/CPU%d/RZ/Trap0e/Time2/HandlerUnhandled", "Profiling of the Trap0eHandler body when the cause is access outside the monitored areas of a monitored page.");
1750	PGM_REG_PROFILE(&pPGM->StatRZTrap0eTime2Misc, "/PGM/CPU%d/RZ/Trap0e/Time2/Misc", "Profiling of the Trap0eHandler body when the cause is not known.");
1751	PGM_REG_PROFILE(&pPGM->StatRZTrap0eTime2OutOfSync, "/PGM/CPU%d/RZ/Trap0e/Time2/OutOfSync", "Profiling of the Trap0eHandler body when the cause is an out-of-sync page.");
1752	PGM_REG_PROFILE(&pPGM->StatRZTrap0eTime2OutOfSyncHndPhys, "/PGM/CPU%d/RZ/Trap0e/Time2/OutOfSyncHndPhys", "Profiling of the Trap0eHandler body when the cause is an out-of-sync physical handler page.");
1753	PGM_REG_PROFILE(&pPGM->StatRZTrap0eTime2OutOfSyncHndVirt, "/PGM/CPU%d/RZ/Trap0e/Time2/OutOfSyncHndVirt", "Profiling of the Trap0eHandler body when the cause is an out-of-sync virtual handler page.");
1754	PGM_REG_PROFILE(&pPGM->StatRZTrap0eTime2OutOfSyncHndObs, "/PGM/CPU%d/RZ/Trap0e/Time2/OutOfSyncObsHnd", "Profiling of the Trap0eHandler body when the cause is an obsolete handler page.");
1755	PGM_REG_PROFILE(&pPGM->StatRZTrap0eTime2SyncPT, "/PGM/CPU%d/RZ/Trap0e/Time2/SyncPT", "Profiling of the Trap0eHandler body when the cause is lazy syncing of a PT.");
1756	PGM_REG_COUNTER(&pPGM->StatRZTrap0eConflicts, "/PGM/CPU%d/RZ/Trap0e/Conflicts", "The number of times #PF was caused by an undetected conflict.");
1757	PGM_REG_COUNTER(&pPGM->StatRZTrap0eHandlersMapping, "/PGM/CPU%d/RZ/Trap0e/Handlers/Mapping", "Number of traps due to access handlers in mappings.");
1758	PGM_REG_COUNTER(&pPGM->StatRZTrap0eHandlersOutOfSync, "/PGM/CPU%d/RZ/Trap0e/Handlers/OutOfSync", "Number of traps due to out-of-sync handled pages.");
1759	PGM_REG_COUNTER(&pPGM->StatRZTrap0eHandlersPhysical, "/PGM/CPU%d/RZ/Trap0e/Handlers/Physical", "Number of traps due to physical access handlers.");
1760	PGM_REG_COUNTER(&pPGM->StatRZTrap0eHandlersVirtual, "/PGM/CPU%d/RZ/Trap0e/Handlers/Virtual", "Number of traps due to virtual access handlers.");
1761	PGM_REG_COUNTER(&pPGM->StatRZTrap0eHandlersVirtualByPhys, "/PGM/CPU%d/RZ/Trap0e/Handlers/VirtualByPhys", "Number of traps due to virtual access handlers by physical address.");
1762	PGM_REG_COUNTER(&pPGM->StatRZTrap0eHandlersVirtualUnmarked,"/PGM/CPU%d/RZ/Trap0e/Handlers/VirtualUnmarked","Number of traps due to virtual access handlers by virtual address (without proper physical flags).");
1763	PGM_REG_COUNTER(&pPGM->StatRZTrap0eHandlersUnhandled, "/PGM/CPU%d/RZ/Trap0e/Handlers/Unhandled", "Number of traps due to access outside range of monitored page(s).");
1764	PGM_REG_COUNTER(&pPGM->StatRZTrap0eHandlersInvalid, "/PGM/CPU%d/RZ/Trap0e/Handlers/Invalid", "Number of traps due to access to invalid physical memory.");
1765	PGM_REG_COUNTER(&pPGM->StatRZTrap0eUSNotPresentRead, "/PGM/CPU%d/RZ/Trap0e/Err/User/NPRead", "Number of user mode not present read page faults.");
1766	PGM_REG_COUNTER(&pPGM->StatRZTrap0eUSNotPresentWrite, "/PGM/CPU%d/RZ/Trap0e/Err/User/NPWrite", "Number of user mode not present write page faults.");
1767	PGM_REG_COUNTER(&pPGM->StatRZTrap0eUSWrite, "/PGM/CPU%d/RZ/Trap0e/Err/User/Write", "Number of user mode write page faults.");
1768	PGM_REG_COUNTER(&pPGM->StatRZTrap0eUSReserved, "/PGM/CPU%d/RZ/Trap0e/Err/User/Reserved", "Number of user mode reserved bit page faults.");
1769	PGM_REG_COUNTER(&pPGM->StatRZTrap0eUSNXE, "/PGM/CPU%d/RZ/Trap0e/Err/User/NXE", "Number of user mode NXE page faults.");
1770	PGM_REG_COUNTER(&pPGM->StatRZTrap0eUSRead, "/PGM/CPU%d/RZ/Trap0e/Err/User/Read", "Number of user mode read page faults.");
1771	PGM_REG_COUNTER(&pPGM->StatRZTrap0eSVNotPresentRead, "/PGM/CPU%d/RZ/Trap0e/Err/Supervisor/NPRead", "Number of supervisor mode not present read page faults.");
1772	PGM_REG_COUNTER(&pPGM->StatRZTrap0eSVNotPresentWrite, "/PGM/CPU%d/RZ/Trap0e/Err/Supervisor/NPWrite", "Number of supervisor mode not present write page faults.");
1773	PGM_REG_COUNTER(&pPGM->StatRZTrap0eSVWrite, "/PGM/CPU%d/RZ/Trap0e/Err/Supervisor/Write", "Number of supervisor mode write page faults.");
1774	PGM_REG_COUNTER(&pPGM->StatRZTrap0eSVReserved, "/PGM/CPU%d/RZ/Trap0e/Err/Supervisor/Reserved", "Number of supervisor mode reserved bit page faults.");
1775	PGM_REG_COUNTER(&pPGM->StatRZTrap0eSNXE, "/PGM/CPU%d/RZ/Trap0e/Err/Supervisor/NXE", "Number of supervisor mode NXE page faults.");
1776	PGM_REG_COUNTER(&pPGM->StatRZTrap0eGuestPF, "/PGM/CPU%d/RZ/Trap0e/GuestPF", "Number of real guest page faults.");
1777	PGM_REG_COUNTER(&pPGM->StatRZTrap0eGuestPFUnh, "/PGM/CPU%d/RZ/Trap0e/GuestPF/Unhandled", "Number of real guest page faults from the 'unhandled' case.");
1778	PGM_REG_COUNTER(&pPGM->StatRZTrap0eGuestPFMapping, "/PGM/CPU%d/RZ/Trap0e/GuestPF/InMapping", "Number of real guest page faults in a mapping.");
1779	PGM_REG_COUNTER(&pPGM->StatRZTrap0eWPEmulInRZ, "/PGM/CPU%d/RZ/Trap0e/WP/InRZ", "Number of guest page faults due to X86_CR0_WP emulation.");
1780	PGM_REG_COUNTER(&pPGM->StatRZTrap0eWPEmulToR3, "/PGM/CPU%d/RZ/Trap0e/WP/ToR3", "Number of guest page faults due to X86_CR0_WP emulation (forward to R3 for emulation).");
1781	for (unsigned j = 0; j < RT_ELEMENTS(pPGM->StatRZTrap0ePD); j++)
1782	STAMR3RegisterF(pVM, &pPGM->StatRZTrap0ePD[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
1783	"The number of traps in page directory n.", "/PGM/CPU%d/RZ/Trap0e/PD/%04X", i, j);
1784
1785	PGM_REG_COUNTER(&pPGM->StatRZGuestCR3WriteHandled, "/PGM/CPU%d/RZ/CR3WriteHandled", "The number of times the Guest CR3 change was successfully handled.");
1786	PGM_REG_COUNTER(&pPGM->StatRZGuestCR3WriteUnhandled, "/PGM/CPU%d/RZ/CR3WriteUnhandled", "The number of times the Guest CR3 change was passed back to the recompiler.");
1787	PGM_REG_COUNTER(&pPGM->StatRZGuestCR3WriteConflict, "/PGM/CPU%d/RZ/CR3WriteConflict", "The number of times the Guest CR3 monitoring detected a conflict.");
1788	PGM_REG_COUNTER(&pPGM->StatRZGuestROMWriteHandled, "/PGM/CPU%d/RZ/ROMWriteHandled", "The number of times the Guest ROM change was successfully handled.");
1789	PGM_REG_COUNTER(&pPGM->StatRZGuestROMWriteUnhandled, "/PGM/CPU%d/RZ/ROMWriteUnhandled", "The number of times the Guest ROM change was passed back to the recompiler.");
1790
1791	/* HC only: */
1792
1793	/* RZ & R3: */
1794	PGM_REG_PROFILE(&pPGM->StatRZSyncCR3, "/PGM/CPU%d/RZ/SyncCR3", "Profiling of the PGMSyncCR3() body.");
1795	PGM_REG_PROFILE(&pPGM->StatRZSyncCR3Handlers, "/PGM/CPU%d/RZ/SyncCR3/Handlers", "Profiling of the PGMSyncCR3() update handler section.");
1796	PGM_REG_COUNTER(&pPGM->StatRZSyncCR3Global, "/PGM/CPU%d/RZ/SyncCR3/Global", "The number of global CR3 syncs.");
1797	PGM_REG_COUNTER(&pPGM->StatRZSyncCR3NotGlobal, "/PGM/CPU%d/RZ/SyncCR3/NotGlobal", "The number of non-global CR3 syncs.");
1798	PGM_REG_COUNTER(&pPGM->StatRZSyncCR3DstCacheHit, "/PGM/CPU%d/RZ/SyncCR3/DstChacheHit", "The number of times we got some kind of a cache hit.");
1799	PGM_REG_COUNTER(&pPGM->StatRZSyncCR3DstFreed, "/PGM/CPU%d/RZ/SyncCR3/DstFreed", "The number of times we've had to free a shadow entry.");
1800	PGM_REG_COUNTER(&pPGM->StatRZSyncCR3DstFreedSrcNP, "/PGM/CPU%d/RZ/SyncCR3/DstFreedSrcNP", "The number of times we've had to free a shadow entry for which the source entry was not present.");
1801	PGM_REG_COUNTER(&pPGM->StatRZSyncCR3DstNotPresent, "/PGM/CPU%d/RZ/SyncCR3/DstNotPresent", "The number of times we've encountered a not present shadow entry for a present guest entry.");
1802	PGM_REG_COUNTER(&pPGM->StatRZSyncCR3DstSkippedGlobalPD, "/PGM/CPU%d/RZ/SyncCR3/DstSkippedGlobalPD", "The number of times a global page directory wasn't flushed.");
1803	PGM_REG_COUNTER(&pPGM->StatRZSyncCR3DstSkippedGlobalPT, "/PGM/CPU%d/RZ/SyncCR3/DstSkippedGlobalPT", "The number of times a page table with only global entries wasn't flushed.");
1804	PGM_REG_PROFILE(&pPGM->StatRZSyncPT, "/PGM/CPU%d/RZ/SyncPT", "Profiling of the pfnSyncPT() body.");
1805	PGM_REG_COUNTER(&pPGM->StatRZSyncPTFailed, "/PGM/CPU%d/RZ/SyncPT/Failed", "The number of times pfnSyncPT() failed.");
1806	PGM_REG_COUNTER(&pPGM->StatRZSyncPT4K, "/PGM/CPU%d/RZ/SyncPT/4K", "Nr of 4K PT syncs");
1807	PGM_REG_COUNTER(&pPGM->StatRZSyncPT4M, "/PGM/CPU%d/RZ/SyncPT/4M", "Nr of 4M PT syncs");
1808	PGM_REG_COUNTER(&pPGM->StatRZSyncPagePDNAs, "/PGM/CPU%d/RZ/SyncPagePDNAs", "The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit.");
1809	PGM_REG_COUNTER(&pPGM->StatRZSyncPagePDOutOfSync, "/PGM/CPU%d/RZ/SyncPagePDOutOfSync", "The number of time we've encountered an out-of-sync PD in SyncPage.");
1810	PGM_REG_COUNTER(&pPGM->StatRZAccessedPage, "/PGM/CPU%d/RZ/AccessedPage", "The number of pages marked not present for accessed bit emulation.");
1811	PGM_REG_PROFILE(&pPGM->StatRZDirtyBitTracking, "/PGM/CPU%d/RZ/DirtyPage", "Profiling the dirty bit tracking in CheckPageFault().");
1812	PGM_REG_COUNTER(&pPGM->StatRZDirtyPage, "/PGM/CPU%d/RZ/DirtyPage/Mark", "The number of pages marked read-only for dirty bit tracking.");
1813	PGM_REG_COUNTER(&pPGM->StatRZDirtyPageBig, "/PGM/CPU%d/RZ/DirtyPage/MarkBig", "The number of 4MB pages marked read-only for dirty bit tracking.");
1814	PGM_REG_COUNTER(&pPGM->StatRZDirtyPageSkipped, "/PGM/CPU%d/RZ/DirtyPage/Skipped", "The number of pages already dirty or readonly.");
1815	PGM_REG_COUNTER(&pPGM->StatRZDirtyPageTrap, "/PGM/CPU%d/RZ/DirtyPage/Trap", "The number of traps generated for dirty bit tracking.");
1816	PGM_REG_COUNTER(&pPGM->StatRZDirtyPageStale, "/PGM/CPU%d/RZ/DirtyPage/Stale", "The number of traps generated for dirty bit tracking (stale tlb entries).");
1817	PGM_REG_COUNTER(&pPGM->StatRZDirtiedPage, "/PGM/CPU%d/RZ/DirtyPage/SetDirty", "The number of pages marked dirty because of write accesses.");
1818	PGM_REG_COUNTER(&pPGM->StatRZDirtyTrackRealPF, "/PGM/CPU%d/RZ/DirtyPage/RealPF", "The number of real pages faults during dirty bit tracking.");
1819	PGM_REG_COUNTER(&pPGM->StatRZPageAlreadyDirty, "/PGM/CPU%d/RZ/DirtyPage/AlreadySet", "The number of pages already marked dirty because of write accesses.");
1820	PGM_REG_PROFILE(&pPGM->StatRZInvalidatePage, "/PGM/CPU%d/RZ/InvalidatePage", "PGMInvalidatePage() profiling.");
1821	PGM_REG_COUNTER(&pPGM->StatRZInvalidatePage4KBPages, "/PGM/CPU%d/RZ/InvalidatePage/4KBPages", "The number of times PGMInvalidatePage() was called for a 4KB page.");
1822	PGM_REG_COUNTER(&pPGM->StatRZInvalidatePage4MBPages, "/PGM/CPU%d/RZ/InvalidatePage/4MBPages", "The number of times PGMInvalidatePage() was called for a 4MB page.");
1823	PGM_REG_COUNTER(&pPGM->StatRZInvalidatePage4MBPagesSkip, "/PGM/CPU%d/RZ/InvalidatePage/4MBPagesSkip","The number of times PGMInvalidatePage() skipped a 4MB page.");
1824	PGM_REG_COUNTER(&pPGM->StatRZInvalidatePagePDMappings, "/PGM/CPU%d/RZ/InvalidatePage/PDMappings", "The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict).");
1825	PGM_REG_COUNTER(&pPGM->StatRZInvalidatePagePDNAs, "/PGM/CPU%d/RZ/InvalidatePage/PDNAs", "The number of times PGMInvalidatePage() was called for a not accessed page directory.");
1826	PGM_REG_COUNTER(&pPGM->StatRZInvalidatePagePDNPs, "/PGM/CPU%d/RZ/InvalidatePage/PDNPs", "The number of times PGMInvalidatePage() was called for a not present page directory.");
1827	PGM_REG_COUNTER(&pPGM->StatRZInvalidatePagePDOutOfSync, "/PGM/CPU%d/RZ/InvalidatePage/PDOutOfSync", "The number of times PGMInvalidatePage() was called for an out of sync page directory.");
1828	PGM_REG_COUNTER(&pPGM->StatRZInvalidatePageSkipped, "/PGM/CPU%d/RZ/InvalidatePage/Skipped", "The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3.");
1829	PGM_REG_COUNTER(&pPGM->StatRZPageOutOfSyncSupervisor, "/PGM/CPU%d/RZ/OutOfSync/SuperVisor", "Number of traps due to pages out of sync and times VerifyAccessSyncPage calls SyncPage.");
1830	PGM_REG_COUNTER(&pPGM->StatRZPageOutOfSyncUser, "/PGM/CPU%d/RZ/OutOfSync/User", "Number of traps due to pages out of sync and times VerifyAccessSyncPage calls SyncPage.");
1831	PGM_REG_PROFILE(&pPGM->StatRZPrefetch, "/PGM/CPU%d/RZ/Prefetch", "PGMPrefetchPage profiling.");
1832	PGM_REG_PROFILE(&pPGM->StatRZFlushTLB, "/PGM/CPU%d/RZ/FlushTLB", "Profiling of the PGMFlushTLB() body.");
1833	PGM_REG_COUNTER(&pPGM->StatRZFlushTLBNewCR3, "/PGM/CPU%d/RZ/FlushTLB/NewCR3", "The number of times PGMFlushTLB was called with a new CR3, non-global. (switch)");
1834	PGM_REG_COUNTER(&pPGM->StatRZFlushTLBNewCR3Global, "/PGM/CPU%d/RZ/FlushTLB/NewCR3Global", "The number of times PGMFlushTLB was called with a new CR3, global. (switch)");
1835	PGM_REG_COUNTER(&pPGM->StatRZFlushTLBSameCR3, "/PGM/CPU%d/RZ/FlushTLB/SameCR3", "The number of times PGMFlushTLB was called with the same CR3, non-global. (flush)");
1836	PGM_REG_COUNTER(&pPGM->StatRZFlushTLBSameCR3Global, "/PGM/CPU%d/RZ/FlushTLB/SameCR3Global", "The number of times PGMFlushTLB was called with the same CR3, global. (flush)");
1837	PGM_REG_PROFILE(&pPGM->StatRZGstModifyPage, "/PGM/CPU%d/RZ/GstModifyPage", "Profiling of the PGMGstModifyPage() body.");
1838
1839	PGM_REG_PROFILE(&pPGM->StatR3SyncCR3, "/PGM/CPU%d/R3/SyncCR3", "Profiling of the PGMSyncCR3() body.");
1840	PGM_REG_PROFILE(&pPGM->StatR3SyncCR3Handlers, "/PGM/CPU%d/R3/SyncCR3/Handlers", "Profiling of the PGMSyncCR3() update handler section.");
1841	PGM_REG_COUNTER(&pPGM->StatR3SyncCR3Global, "/PGM/CPU%d/R3/SyncCR3/Global", "The number of global CR3 syncs.");
1842	PGM_REG_COUNTER(&pPGM->StatR3SyncCR3NotGlobal, "/PGM/CPU%d/R3/SyncCR3/NotGlobal", "The number of non-global CR3 syncs.");
1843	PGM_REG_COUNTER(&pPGM->StatR3SyncCR3DstCacheHit, "/PGM/CPU%d/R3/SyncCR3/DstChacheHit", "The number of times we got some kind of a cache hit.");
1844	PGM_REG_COUNTER(&pPGM->StatR3SyncCR3DstFreed, "/PGM/CPU%d/R3/SyncCR3/DstFreed", "The number of times we've had to free a shadow entry.");
1845	PGM_REG_COUNTER(&pPGM->StatR3SyncCR3DstFreedSrcNP, "/PGM/CPU%d/R3/SyncCR3/DstFreedSrcNP", "The number of times we've had to free a shadow entry for which the source entry was not present.");
1846	PGM_REG_COUNTER(&pPGM->StatR3SyncCR3DstNotPresent, "/PGM/CPU%d/R3/SyncCR3/DstNotPresent", "The number of times we've encountered a not present shadow entry for a present guest entry.");
1847	PGM_REG_COUNTER(&pPGM->StatR3SyncCR3DstSkippedGlobalPD, "/PGM/CPU%d/R3/SyncCR3/DstSkippedGlobalPD", "The number of times a global page directory wasn't flushed.");
1848	PGM_REG_COUNTER(&pPGM->StatR3SyncCR3DstSkippedGlobalPT, "/PGM/CPU%d/R3/SyncCR3/DstSkippedGlobalPT", "The number of times a page table with only global entries wasn't flushed.");
1849	PGM_REG_PROFILE(&pPGM->StatR3SyncPT, "/PGM/CPU%d/R3/SyncPT", "Profiling of the pfnSyncPT() body.");
1850	PGM_REG_COUNTER(&pPGM->StatR3SyncPTFailed, "/PGM/CPU%d/R3/SyncPT/Failed", "The number of times pfnSyncPT() failed.");
1851	PGM_REG_COUNTER(&pPGM->StatR3SyncPT4K, "/PGM/CPU%d/R3/SyncPT/4K", "Nr of 4K PT syncs");
1852	PGM_REG_COUNTER(&pPGM->StatR3SyncPT4M, "/PGM/CPU%d/R3/SyncPT/4M", "Nr of 4M PT syncs");
1853	PGM_REG_COUNTER(&pPGM->StatR3SyncPagePDNAs, "/PGM/CPU%d/R3/SyncPagePDNAs", "The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit.");
1854	PGM_REG_COUNTER(&pPGM->StatR3SyncPagePDOutOfSync, "/PGM/CPU%d/R3/SyncPagePDOutOfSync", "The number of time we've encountered an out-of-sync PD in SyncPage.");
1855	PGM_REG_COUNTER(&pPGM->StatR3AccessedPage, "/PGM/CPU%d/R3/AccessedPage", "The number of pages marked not present for accessed bit emulation.");
1856	PGM_REG_PROFILE(&pPGM->StatR3DirtyBitTracking, "/PGM/CPU%d/R3/DirtyPage", "Profiling the dirty bit tracking in CheckPageFault().");
1857	PGM_REG_COUNTER(&pPGM->StatR3DirtyPage, "/PGM/CPU%d/R3/DirtyPage/Mark", "The number of pages marked read-only for dirty bit tracking.");
1858	PGM_REG_COUNTER(&pPGM->StatR3DirtyPageBig, "/PGM/CPU%d/R3/DirtyPage/MarkBig", "The number of 4MB pages marked read-only for dirty bit tracking.");
1859	PGM_REG_COUNTER(&pPGM->StatR3DirtyPageSkipped, "/PGM/CPU%d/R3/DirtyPage/Skipped", "The number of pages already dirty or readonly.");
1860	PGM_REG_COUNTER(&pPGM->StatR3DirtyPageTrap, "/PGM/CPU%d/R3/DirtyPage/Trap", "The number of traps generated for dirty bit tracking.");
1861	PGM_REG_COUNTER(&pPGM->StatR3DirtiedPage, "/PGM/CPU%d/R3/DirtyPage/SetDirty", "The number of pages marked dirty because of write accesses.");
1862	PGM_REG_COUNTER(&pPGM->StatR3DirtyTrackRealPF, "/PGM/CPU%d/R3/DirtyPage/RealPF", "The number of real pages faults during dirty bit tracking.");
1863	PGM_REG_COUNTER(&pPGM->StatR3PageAlreadyDirty, "/PGM/CPU%d/R3/DirtyPage/AlreadySet", "The number of pages already marked dirty because of write accesses.");
1864	PGM_REG_PROFILE(&pPGM->StatR3InvalidatePage, "/PGM/CPU%d/R3/InvalidatePage", "PGMInvalidatePage() profiling.");
1865	PGM_REG_COUNTER(&pPGM->StatR3InvalidatePage4KBPages, "/PGM/CPU%d/R3/InvalidatePage/4KBPages", "The number of times PGMInvalidatePage() was called for a 4KB page.");
1866	PGM_REG_COUNTER(&pPGM->StatR3InvalidatePage4MBPages, "/PGM/CPU%d/R3/InvalidatePage/4MBPages", "The number of times PGMInvalidatePage() was called for a 4MB page.");
1867	PGM_REG_COUNTER(&pPGM->StatR3InvalidatePage4MBPagesSkip, "/PGM/CPU%d/R3/InvalidatePage/4MBPagesSkip","The number of times PGMInvalidatePage() skipped a 4MB page.");
1868	PGM_REG_COUNTER(&pPGM->StatR3InvalidatePagePDMappings, "/PGM/CPU%d/R3/InvalidatePage/PDMappings", "The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict).");
1869	PGM_REG_COUNTER(&pPGM->StatR3InvalidatePagePDNAs, "/PGM/CPU%d/R3/InvalidatePage/PDNAs", "The number of times PGMInvalidatePage() was called for a not accessed page directory.");
1870	PGM_REG_COUNTER(&pPGM->StatR3InvalidatePagePDNPs, "/PGM/CPU%d/R3/InvalidatePage/PDNPs", "The number of times PGMInvalidatePage() was called for a not present page directory.");
1871	PGM_REG_COUNTER(&pPGM->StatR3InvalidatePagePDOutOfSync, "/PGM/CPU%d/R3/InvalidatePage/PDOutOfSync", "The number of times PGMInvalidatePage() was called for an out of sync page directory.");
1872	PGM_REG_COUNTER(&pPGM->StatR3InvalidatePageSkipped, "/PGM/CPU%d/R3/InvalidatePage/Skipped", "The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3.");
1873	PGM_REG_COUNTER(&pPGM->StatR3PageOutOfSyncSupervisor, "/PGM/CPU%d/R3/OutOfSync/SuperVisor", "Number of traps due to pages out of sync and times VerifyAccessSyncPage calls SyncPage.");
1874	PGM_REG_COUNTER(&pPGM->StatR3PageOutOfSyncUser, "/PGM/CPU%d/R3/OutOfSync/User", "Number of traps due to pages out of sync and times VerifyAccessSyncPage calls SyncPage.");
1875	PGM_REG_PROFILE(&pPGM->StatR3Prefetch, "/PGM/CPU%d/R3/Prefetch", "PGMPrefetchPage profiling.");
1876	PGM_REG_PROFILE(&pPGM->StatR3FlushTLB, "/PGM/CPU%d/R3/FlushTLB", "Profiling of the PGMFlushTLB() body.");
1877	PGM_REG_COUNTER(&pPGM->StatR3FlushTLBNewCR3, "/PGM/CPU%d/R3/FlushTLB/NewCR3", "The number of times PGMFlushTLB was called with a new CR3, non-global. (switch)");
1878	PGM_REG_COUNTER(&pPGM->StatR3FlushTLBNewCR3Global, "/PGM/CPU%d/R3/FlushTLB/NewCR3Global", "The number of times PGMFlushTLB was called with a new CR3, global. (switch)");
1879	PGM_REG_COUNTER(&pPGM->StatR3FlushTLBSameCR3, "/PGM/CPU%d/R3/FlushTLB/SameCR3", "The number of times PGMFlushTLB was called with the same CR3, non-global. (flush)");
1880	PGM_REG_COUNTER(&pPGM->StatR3FlushTLBSameCR3Global, "/PGM/CPU%d/R3/FlushTLB/SameCR3Global", "The number of times PGMFlushTLB was called with the same CR3, global. (flush)");
1881	PGM_REG_PROFILE(&pPGM->StatR3GstModifyPage, "/PGM/CPU%d/R3/GstModifyPage", "Profiling of the PGMGstModifyPage() body.");
1882	#endif /* VBOX_WITH_STATISTICS */
1883
1884	#undef PGM_REG_PROFILE
1885	#undef PGM_REG_COUNTER
1886
1887	}
1888	}
1889
1890
1891	/**
1892	* Init the PGM bits that rely on VMMR0 and MM to be fully initialized.
1893	*
1894	* The dynamic mapping area will also be allocated and initialized at this
1895	* time. We could allocate it during PGMR3Init of course, but the mapping
1896	* wouldn't be allocated at that time preventing us from setting up the
1897	* page table entries with the dummy page.
1898	*
1899	* @returns VBox status code.
1900	* @param pVM VM handle.
1901	*/
1902	VMMR3DECL(int) PGMR3InitDynMap(PVM pVM)
1903	{
1904	RTGCPTR GCPtr;
1905	int rc;
1906
1907	/*
1908	* Reserve space for the dynamic mappings.
1909	*/
1910	rc = MMR3HyperReserve(pVM, MM_HYPER_DYNAMIC_SIZE, "Dynamic mapping", &GCPtr);
1911	if (RT_SUCCESS(rc))
1912	pVM->pgm.s.pbDynPageMapBaseGC = GCPtr;
1913
1914	if ( RT_SUCCESS(rc)
1915	&& (pVM->pgm.s.pbDynPageMapBaseGC >> X86_PD_PAE_SHIFT) != ((pVM->pgm.s.pbDynPageMapBaseGC + MM_HYPER_DYNAMIC_SIZE - 1) >> X86_PD_PAE_SHIFT))
1916	{
1917	rc = MMR3HyperReserve(pVM, MM_HYPER_DYNAMIC_SIZE, "Dynamic mapping not crossing", &GCPtr);
1918	if (RT_SUCCESS(rc))
1919	pVM->pgm.s.pbDynPageMapBaseGC = GCPtr;
1920	}
1921	if (RT_SUCCESS(rc))
1922	{
1923	AssertRelease((pVM->pgm.s.pbDynPageMapBaseGC >> X86_PD_PAE_SHIFT) == ((pVM->pgm.s.pbDynPageMapBaseGC + MM_HYPER_DYNAMIC_SIZE - 1) >> X86_PD_PAE_SHIFT));
1924	MMR3HyperReserve(pVM, PAGE_SIZE, "fence", NULL);
1925	}
1926	return rc;
1927	}
1928
1929
1930	/**
1931	* Ring-3 init finalizing.
1932	*
1933	* @returns VBox status code.
1934	* @param pVM The VM handle.
1935	*/
1936	VMMR3DECL(int) PGMR3InitFinalize(PVM pVM)
1937	{
1938	int rc;
1939
1940	/*
1941	* Reserve space for the dynamic mappings.
1942	* Initialize the dynamic mapping pages with dummy pages to simply the cache.
1943	*/
1944	/* get the pointer to the page table entries. */
1945	PPGMMAPPING pMapping = pgmGetMapping(pVM, pVM->pgm.s.pbDynPageMapBaseGC);
1946	AssertRelease(pMapping);
1947	const uintptr_t off = pVM->pgm.s.pbDynPageMapBaseGC - pMapping->GCPtr;
1948	const unsigned iPT = off >> X86_PD_SHIFT;
1949	const unsigned iPG = (off >> X86_PT_SHIFT) & X86_PT_MASK;
1950	pVM->pgm.s.paDynPageMap32BitPTEsGC = pMapping->aPTs[iPT].pPTRC + iPG * sizeof(pMapping->aPTs[0].pPTR3->a[0]);
1951	pVM->pgm.s.paDynPageMapPaePTEsGC = pMapping->aPTs[iPT].paPaePTsRC + iPG * sizeof(pMapping->aPTs[0].paPaePTsR3->a[0]);
1952
1953	/* init cache */
1954	RTHCPHYS HCPhysDummy = MMR3PageDummyHCPhys(pVM);
1955	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.aHCPhysDynPageMapCache); i++)
1956	pVM->pgm.s.aHCPhysDynPageMapCache[i] = HCPhysDummy;
1957
1958	for (unsigned i = 0; i < MM_HYPER_DYNAMIC_SIZE; i += PAGE_SIZE)
1959	{
1960	rc = PGMMap(pVM, pVM->pgm.s.pbDynPageMapBaseGC + i, HCPhysDummy, PAGE_SIZE, 0);
1961	AssertRCReturn(rc, rc);
1962	}
1963
1964	/*
1965	* Note that AMD uses all the 8 reserved bits for the address (so 40 bits in total);
1966	* Intel only goes up to 36 bits, so we stick to 36 as well.
1967	*/
1968	/** @todo How to test for the 40 bits support? Long mode seems to be the test criterium. */
1969	uint32_t u32Dummy, u32Features;
1970	CPUMGetGuestCpuId(VMMGetCpu(pVM), 1, &u32Dummy, &u32Dummy, &u32Dummy, &u32Features);
1971
1972	if (u32Features & X86_CPUID_FEATURE_EDX_PSE36)
1973	pVM->pgm.s.GCPhys4MBPSEMask = RT_BIT_64(36) - 1;
1974	else
1975	pVM->pgm.s.GCPhys4MBPSEMask = RT_BIT_64(32) - 1;
1976
1977	/*
1978	* Allocate memory if we're supposed to do that.
1979	*/
1980	if (pVM->pgm.s.fRamPreAlloc)
1981	rc = pgmR3PhysRamPreAllocate(pVM);
1982
1983	LogRel(("PGMR3InitFinalize: 4 MB PSE mask %RGp\n", pVM->pgm.s.GCPhys4MBPSEMask));
1984	return rc;
1985	}
1986
1987
1988	/**
1989	* Applies relocations to data and code managed by this component.
1990	*
1991	* This function will be called at init and whenever the VMM need to relocate it
1992	* self inside the GC.
1993	*
1994	* @param pVM The VM.
1995	* @param offDelta Relocation delta relative to old location.
1996	*/
1997	VMMR3DECL(void) PGMR3Relocate(PVM pVM, RTGCINTPTR offDelta)
1998	{
1999	LogFlow(("PGMR3Relocate %RGv to %RGv\n", pVM->pgm.s.GCPtrCR3Mapping, pVM->pgm.s.GCPtrCR3Mapping + offDelta));
2000
2001	/*
2002	* Paging stuff.
2003	*/
2004	pVM->pgm.s.GCPtrCR3Mapping += offDelta;
2005
2006	pgmR3ModeDataInit(pVM, true /* resolve GC/R0 symbols */);
2007
2008	/* Shadow, guest and both mode switch & relocation for each VCPU. */
2009	for (unsigned i=0;i<pVM->cCPUs;i++)
2010	{
2011	PVMCPU pVCpu = &pVM->aCpus[i];
2012
2013	pgmR3ModeDataSwitch(pVM, pVCpu, pVCpu->pgm.s.enmShadowMode, pVCpu->pgm.s.enmGuestMode);
2014
2015	PGM_SHW_PFN(Relocate, pVCpu)(pVCpu, offDelta);
2016	PGM_GST_PFN(Relocate, pVCpu)(pVCpu, offDelta);
2017	PGM_BTH_PFN(Relocate, pVCpu)(pVCpu, offDelta);
2018	}
2019
2020	/*
2021	* Trees.
2022	*/
2023	pVM->pgm.s.pTreesRC = MMHyperR3ToRC(pVM, pVM->pgm.s.pTreesR3);
2024
2025	/*
2026	* Ram ranges.
2027	*/
2028	if (pVM->pgm.s.pRamRangesR3)
2029	{
2030	/* Update the pSelfRC pointers and relink them. */
2031	for (PPGMRAMRANGE pCur = pVM->pgm.s.pRamRangesR3; pCur; pCur = pCur->pNextR3)
2032	if (!(pCur->fFlags & PGM_RAM_RANGE_FLAGS_FLOATING))
2033	pCur->pSelfRC = MMHyperCCToRC(pVM, pCur);
2034	pgmR3PhysRelinkRamRanges(pVM);
2035	}
2036
2037	/*
2038	* Update the two page directories with all page table mappings.
2039	* (One or more of them have changed, that's why we're here.)
2040	*/
2041	pVM->pgm.s.pMappingsRC = MMHyperR3ToRC(pVM, pVM->pgm.s.pMappingsR3);
2042	for (PPGMMAPPING pCur = pVM->pgm.s.pMappingsR3; pCur->pNextR3; pCur = pCur->pNextR3)
2043	pCur->pNextRC = MMHyperR3ToRC(pVM, pCur->pNextR3);
2044
2045	/* Relocate GC addresses of Page Tables. */
2046	for (PPGMMAPPING pCur = pVM->pgm.s.pMappingsR3; pCur; pCur = pCur->pNextR3)
2047	{
2048	for (RTHCUINT i = 0; i < pCur->cPTs; i++)
2049	{
2050	pCur->aPTs[i].pPTRC = MMHyperR3ToRC(pVM, pCur->aPTs[i].pPTR3);
2051	pCur->aPTs[i].paPaePTsRC = MMHyperR3ToRC(pVM, pCur->aPTs[i].paPaePTsR3);
2052	}
2053	}
2054
2055	/*
2056	* Dynamic page mapping area.
2057	*/
2058	pVM->pgm.s.paDynPageMap32BitPTEsGC += offDelta;
2059	pVM->pgm.s.paDynPageMapPaePTEsGC += offDelta;
2060	pVM->pgm.s.pbDynPageMapBaseGC += offDelta;
2061
2062	/*
2063	* The Zero page.
2064	*/
2065	pVM->pgm.s.pvZeroPgR0 = MMHyperR3ToR0(pVM, pVM->pgm.s.pvZeroPgR3);
2066	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
2067	AssertRelease(pVM->pgm.s.pvZeroPgR0 != NIL_RTR0PTR \|\| !VMMIsHwVirtExtForced(pVM));
2068	#else
2069	AssertRelease(pVM->pgm.s.pvZeroPgR0 != NIL_RTR0PTR);
2070	#endif
2071
2072	/*
2073	* Physical and virtual handlers.
2074	*/
2075	RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysHandlers, true, pgmR3RelocatePhysHandler, &offDelta);
2076	RTAvlroGCPtrDoWithAll(&pVM->pgm.s.pTreesR3->VirtHandlers, true, pgmR3RelocateVirtHandler, &offDelta);
2077	RTAvlroGCPtrDoWithAll(&pVM->pgm.s.pTreesR3->HyperVirtHandlers, true, pgmR3RelocateHyperVirtHandler, &offDelta);
2078
2079	/*
2080	* The page pool.
2081	*/
2082	pgmR3PoolRelocate(pVM);
2083	}
2084
2085
2086	/**
2087	* Callback function for relocating a physical access handler.
2088	*
2089	* @returns 0 (continue enum)
2090	* @param pNode Pointer to a PGMPHYSHANDLER node.
2091	* @param pvUser Pointer to the offDelta. This is a pointer to the delta since we're
2092	* not certain the delta will fit in a void pointer for all possible configs.
2093	*/
2094	static DECLCALLBACK(int) pgmR3RelocatePhysHandler(PAVLROGCPHYSNODECORE pNode, void *pvUser)
2095	{
2096	PPGMPHYSHANDLER pHandler = (PPGMPHYSHANDLER)pNode;
2097	RTGCINTPTR offDelta = *(PRTGCINTPTR)pvUser;
2098	if (pHandler->pfnHandlerRC)
2099	pHandler->pfnHandlerRC += offDelta;
2100	if (pHandler->pvUserRC >= 0x10000)
2101	pHandler->pvUserRC += offDelta;
2102	return 0;
2103	}
2104
2105
2106	/**
2107	* Callback function for relocating a virtual access handler.
2108	*
2109	* @returns 0 (continue enum)
2110	* @param pNode Pointer to a PGMVIRTHANDLER node.
2111	* @param pvUser Pointer to the offDelta. This is a pointer to the delta since we're
2112	* not certain the delta will fit in a void pointer for all possible configs.
2113	*/
2114	static DECLCALLBACK(int) pgmR3RelocateVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser)
2115	{
2116	PPGMVIRTHANDLER pHandler = (PPGMVIRTHANDLER)pNode;
2117	RTGCINTPTR offDelta = *(PRTGCINTPTR)pvUser;
2118	Assert( pHandler->enmType == PGMVIRTHANDLERTYPE_ALL
2119	\|\| pHandler->enmType == PGMVIRTHANDLERTYPE_WRITE);
2120	Assert(pHandler->pfnHandlerRC);
2121	pHandler->pfnHandlerRC += offDelta;
2122	return 0;
2123	}
2124
2125
2126	/**
2127	* Callback function for relocating a virtual access handler for the hypervisor mapping.
2128	*
2129	* @returns 0 (continue enum)
2130	* @param pNode Pointer to a PGMVIRTHANDLER node.
2131	* @param pvUser Pointer to the offDelta. This is a pointer to the delta since we're
2132	* not certain the delta will fit in a void pointer for all possible configs.
2133	*/
2134	static DECLCALLBACK(int) pgmR3RelocateHyperVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser)
2135	{
2136	PPGMVIRTHANDLER pHandler = (PPGMVIRTHANDLER)pNode;
2137	RTGCINTPTR offDelta = *(PRTGCINTPTR)pvUser;
2138	Assert(pHandler->enmType == PGMVIRTHANDLERTYPE_HYPERVISOR);
2139	Assert(pHandler->pfnHandlerRC);
2140	pHandler->pfnHandlerRC += offDelta;
2141	return 0;
2142	}
2143
2144
2145	/**
2146	* The VM is being reset.
2147	*
2148	* For the PGM component this means that any PD write monitors
2149	* needs to be removed.
2150	*
2151	* @param pVM VM handle.
2152	*/
2153	VMMR3DECL(void) PGMR3Reset(PVM pVM)
2154	{
2155	int rc;
2156
2157	LogFlow(("PGMR3Reset:\n"));
2158	VM_ASSERT_EMT(pVM);
2159
2160	pgmLock(pVM);
2161
2162	/*
2163	* Unfix any fixed mappings and disable CR3 monitoring.
2164	*/
2165	pVM->pgm.s.fMappingsFixed = false;
2166	pVM->pgm.s.GCPtrMappingFixed = 0;
2167	pVM->pgm.s.cbMappingFixed = 0;
2168
2169	/* Exit the guest paging mode before the pgm pool gets reset.
2170	* Important to clean up the amd64 case.
2171	*/
2172	for (unsigned i=0;i<pVM->cCPUs;i++)
2173	{
2174	PVMCPU pVCpu = &pVM->aCpus[i];
2175
2176	rc = PGM_GST_PFN(Exit, pVCpu)(pVCpu);
2177	AssertRC(rc);
2178	}
2179
2180	#ifdef DEBUG
2181	DBGFR3InfoLog(pVM, "mappings", NULL);
2182	DBGFR3InfoLog(pVM, "handlers", "all nostat");
2183	#endif
2184
2185	/*
2186	* Switch mode back to real mode. (before resetting the pgm pool!)
2187	*/
2188	for (unsigned i=0;i<pVM->cCPUs;i++)
2189	{
2190	PVMCPU pVCpu = &pVM->aCpus[i];
2191
2192	rc = PGMR3ChangeMode(pVM, pVCpu, PGMMODE_REAL);
2193	AssertRC(rc);
2194
2195	STAM_REL_COUNTER_RESET(&pVCpu->pgm.s.cGuestModeChanges);
2196	}
2197
2198	/*
2199	* Reset the shadow page pool.
2200	*/
2201	pgmR3PoolReset(pVM);
2202
2203	for (unsigned i=0;i<pVM->cCPUs;i++)
2204	{
2205	PVMCPU pVCpu = &pVM->aCpus[i];
2206
2207	/*
2208	* Re-init other members.
2209	*/
2210	pVCpu->pgm.s.fA20Enabled = true;
2211
2212	/*
2213	* Clear the FFs PGM owns.
2214	*/
2215	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
2216	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL);
2217	}
2218
2219	/*
2220	* Reset (zero) RAM pages.
2221	*/
2222	rc = pgmR3PhysRamReset(pVM);
2223	if (RT_SUCCESS(rc))
2224	{
2225	/*
2226	* Reset (zero) shadow ROM pages.
2227	*/
2228	rc = pgmR3PhysRomReset(pVM);
2229	}
2230
2231	pgmUnlock(pVM);
2232	//return rc;
2233	AssertReleaseRC(rc);
2234	}
2235
2236
2237	#ifdef VBOX_STRICT
2238	/**
2239	* VM state change callback for clearing fNoMorePhysWrites after
2240	* a snapshot has been created.
2241	*/
2242	static DECLCALLBACK(void) pgmR3ResetNoMorePhysWritesFlag(PVM pVM, VMSTATE enmState, VMSTATE enmOldState, void *pvUser)
2243	{
2244	if (enmState == VMSTATE_RUNNING)
2245	pVM->pgm.s.fNoMorePhysWrites = false;
2246	}
2247	#endif
2248
2249
2250	/**
2251	* Terminates the PGM.
2252	*
2253	* @returns VBox status code.
2254	* @param pVM Pointer to VM structure.
2255	*/
2256	VMMR3DECL(int) PGMR3Term(PVM pVM)
2257	{
2258	PGMDeregisterStringFormatTypes();
2259	return PDMR3CritSectDelete(&pVM->pgm.s.CritSect);
2260	}
2261
2262
2263	/**
2264	* Terminates the per-VCPU PGM.
2265	*
2266	* Termination means cleaning up and freeing all resources,
2267	* the VM it self is at this point powered off or suspended.
2268	*
2269	* @returns VBox status code.
2270	* @param pVM The VM to operate on.
2271	*/
2272	VMMR3DECL(int) PGMR3TermCPU(PVM pVM)
2273	{
2274	return 0;
2275	}
2276
2277
2278	/**
2279	* Find the ROM tracking structure for the given page.
2280	*
2281	* @returns Pointer to the ROM page structure. NULL if the caller didn't check
2282	* that it's a ROM page.
2283	* @param pVM The VM handle.
2284	* @param GCPhys The address of the ROM page.
2285	*/
2286	static PPGMROMPAGE pgmR3GetRomPage(PVM pVM, RTGCPHYS GCPhys)
2287	{
2288	for (PPGMROMRANGE pRomRange = pVM->pgm.s.CTX_SUFF(pRomRanges);
2289	pRomRange;
2290	pRomRange = pRomRange->CTX_SUFF(pNext))
2291	{
2292	RTGCPHYS off = GCPhys - pRomRange->GCPhys;
2293	if (GCPhys - pRomRange->GCPhys < pRomRange->cb)
2294	return &pRomRange->aPages[off >> PAGE_SHIFT];
2295	}
2296	return NULL;
2297	}
2298
2299
2300	/**
2301	* Save zero indicator + bits for the specified page.
2302	*
2303	* @returns VBox status code, errors are logged/asserted before returning.
2304	* @param pVM The VM handle.
2305	* @param pSSH The saved state handle.
2306	* @param pPage The page to save.
2307	* @param GCPhys The address of the page.
2308	* @param pRam The ram range (for error logging).
2309	*/
2310	static int pgmR3SavePage(PVM pVM, PSSMHANDLE pSSM, PPGMPAGE pPage, RTGCPHYS GCPhys, PPGMRAMRANGE pRam)
2311	{
2312	int rc;
2313	if (PGM_PAGE_IS_ZERO(pPage))
2314	rc = SSMR3PutU8(pSSM, 0);
2315	else
2316	{
2317	void const *pvPage;
2318	rc = pgmPhysGCPhys2CCPtrInternalReadOnly(pVM, pPage, GCPhys, &pvPage);
2319	AssertLogRelMsgRCReturn(rc, ("pPage=%R[pgmpage] GCPhys=%#x %s\n", pPage, GCPhys, pRam->pszDesc), rc);
2320
2321	SSMR3PutU8(pSSM, 1);
2322	rc = SSMR3PutMem(pSSM, pvPage, PAGE_SIZE);
2323	}
2324	return rc;
2325	}
2326
2327
2328	/**
2329	* Save a shadowed ROM page.
2330	*
2331	* Format: Type, protection, and two pages with zero indicators.
2332	*
2333	* @returns VBox status code, errors are logged/asserted before returning.
2334	* @param pVM The VM handle.
2335	* @param pSSH The saved state handle.
2336	* @param pPage The page to save.
2337	* @param GCPhys The address of the page.
2338	* @param pRam The ram range (for error logging).
2339	*/
2340	static int pgmR3SaveShadowedRomPage(PVM pVM, PSSMHANDLE pSSM, PPGMPAGE pPage, RTGCPHYS GCPhys, PPGMRAMRANGE pRam)
2341	{
2342	/* Need to save both pages and the current state. */
2343	PPGMROMPAGE pRomPage = pgmR3GetRomPage(pVM, GCPhys);
2344	AssertLogRelMsgReturn(pRomPage, ("GCPhys=%RGp %s\n", GCPhys, pRam->pszDesc), VERR_INTERNAL_ERROR);
2345
2346	SSMR3PutU8(pSSM, PGMPAGETYPE_ROM_SHADOW);
2347	SSMR3PutU8(pSSM, pRomPage->enmProt);
2348
2349	int rc = pgmR3SavePage(pVM, pSSM, pPage, GCPhys, pRam);
2350	if (RT_SUCCESS(rc))
2351	{
2352	PPGMPAGE pPagePassive = PGMROMPROT_IS_ROM(pRomPage->enmProt) ? &pRomPage->Shadow : &pRomPage->Virgin;
2353	rc = pgmR3SavePage(pVM, pSSM, pPagePassive, GCPhys, pRam);
2354	}
2355	return rc;
2356	}
2357
2358	/** PGM fields to save/load. */
2359	static const SSMFIELD s_aPGMFields[] =
2360	{
2361	SSMFIELD_ENTRY( PGM, fMappingsFixed),
2362	SSMFIELD_ENTRY_GCPTR( PGM, GCPtrMappingFixed),
2363	SSMFIELD_ENTRY( PGM, cbMappingFixed),
2364	SSMFIELD_ENTRY_TERM()
2365	};
2366
2367	static const SSMFIELD s_aPGMCpuFields[] =
2368	{
2369	SSMFIELD_ENTRY( PGMCPU, fA20Enabled),
2370	SSMFIELD_ENTRY_GCPHYS( PGMCPU, GCPhysA20Mask),
2371	SSMFIELD_ENTRY( PGMCPU, enmGuestMode),
2372	SSMFIELD_ENTRY_TERM()
2373	};
2374
2375	/* For loading old saved states. (pre-smp) */
2376	typedef struct
2377	{
2378	/** If set no conflict checks are required. (boolean) */
2379	bool fMappingsFixed;
2380	/** Size of fixed mapping */
2381	uint32_t cbMappingFixed;
2382	/** Base address (GC) of fixed mapping */
2383	RTGCPTR GCPtrMappingFixed;
2384	/** A20 gate mask.
2385	* Our current approach to A20 emulation is to let REM do it and don't bother
2386	* anywhere else. The interesting Guests will be operating with it enabled anyway.
2387	* But whould need arrise, we'll subject physical addresses to this mask. */
2388	RTGCPHYS GCPhysA20Mask;
2389	/** A20 gate state - boolean! */
2390	bool fA20Enabled;
2391	/** The guest paging mode. */
2392	PGMMODE enmGuestMode;
2393	} PGMOLD;
2394
2395	static const SSMFIELD s_aPGMFields_Old[] =
2396	{
2397	SSMFIELD_ENTRY( PGMOLD, fMappingsFixed),
2398	SSMFIELD_ENTRY_GCPTR( PGMOLD, GCPtrMappingFixed),
2399	SSMFIELD_ENTRY( PGMOLD, cbMappingFixed),
2400	SSMFIELD_ENTRY( PGMOLD, fA20Enabled),
2401	SSMFIELD_ENTRY_GCPHYS( PGMOLD, GCPhysA20Mask),
2402	SSMFIELD_ENTRY( PGMOLD, enmGuestMode),
2403	SSMFIELD_ENTRY_TERM()
2404	};
2405
2406
2407	/**
2408	* Execute state save operation.
2409	*
2410	* @returns VBox status code.
2411	* @param pVM VM Handle.
2412	* @param pSSM SSM operation handle.
2413	*/
2414	static DECLCALLBACK(int) pgmR3Save(PVM pVM, PSSMHANDLE pSSM)
2415	{
2416	int rc;
2417	unsigned i;
2418	PPGM pPGM = &pVM->pgm.s;
2419
2420	/*
2421	* Lock PGM and set the no-more-writes indicator.
2422	*/
2423	pgmLock(pVM);
2424	pVM->pgm.s.fNoMorePhysWrites = true;
2425
2426	/*
2427	* Save basic data (required / unaffected by relocation).
2428	*/
2429	SSMR3PutStruct(pSSM, pPGM, &s_aPGMFields[0]);
2430
2431	for (i=0;i<pVM->cCPUs;i++)
2432	{
2433	PVMCPU pVCpu = &pVM->aCpus[i];
2434
2435	SSMR3PutStruct(pSSM, &pVCpu->pgm.s, &s_aPGMCpuFields[0]);
2436	}
2437
2438	/*
2439	* The guest mappings.
2440	*/
2441	i = 0;
2442	for (PPGMMAPPING pMapping = pPGM->pMappingsR3; pMapping; pMapping = pMapping->pNextR3, i++)
2443	{
2444	SSMR3PutU32( pSSM, i);
2445	SSMR3PutStrZ( pSSM, pMapping->pszDesc); /* This is the best unique id we have... */
2446	SSMR3PutGCPtr( pSSM, pMapping->GCPtr);
2447	SSMR3PutGCUIntPtr(pSSM, pMapping->cPTs);
2448	}
2449	rc = SSMR3PutU32(pSSM, ~0); /* terminator. */
2450
2451	/*
2452	* Ram ranges and the memory they describe.
2453	*/
2454	i = 0;
2455	for (PPGMRAMRANGE pRam = pPGM->pRamRangesR3; pRam; pRam = pRam->pNextR3, i++)
2456	{
2457	/*
2458	* Save the ram range details.
2459	*/
2460	SSMR3PutU32(pSSM, i);
2461	SSMR3PutGCPhys(pSSM, pRam->GCPhys);
2462	SSMR3PutGCPhys(pSSM, pRam->GCPhysLast);
2463	SSMR3PutGCPhys(pSSM, pRam->cb);
2464	SSMR3PutU8(pSSM, !!pRam->pvR3); /* Boolean indicating memory or not. */
2465	SSMR3PutStrZ(pSSM, pRam->pszDesc); /* This is the best unique id we have... */
2466
2467	/*
2468	* Iterate the pages, only two special case.
2469	*/
2470	uint32_t const cPages = pRam->cb >> PAGE_SHIFT;
2471	for (uint32_t iPage = 0; iPage < cPages; iPage++)
2472	{
2473	RTGCPHYS GCPhysPage = pRam->GCPhys + ((RTGCPHYS)iPage << PAGE_SHIFT);
2474	PPGMPAGE pPage = &pRam->aPages[iPage];
2475	uint8_t uType = PGM_PAGE_GET_TYPE(pPage);
2476
2477	if (uType == PGMPAGETYPE_ROM_SHADOW)
2478	rc = pgmR3SaveShadowedRomPage(pVM, pSSM, pPage, GCPhysPage, pRam);
2479	else if (uType == PGMPAGETYPE_MMIO2_ALIAS_MMIO)
2480	{
2481	/* MMIO2 alias -> MMIO; the device will just have to deal with this. */
2482	SSMR3PutU8(pSSM, PGMPAGETYPE_MMIO);
2483	rc = SSMR3PutU8(pSSM, 0 /* ZERO */);
2484	}
2485	else
2486	{
2487	SSMR3PutU8(pSSM, uType);
2488	rc = pgmR3SavePage(pVM, pSSM, pPage, GCPhysPage, pRam);
2489	}
2490	if (RT_FAILURE(rc))
2491	break;
2492	}
2493	if (RT_FAILURE(rc))
2494	break;
2495	}
2496
2497	pgmUnlock(pVM);
2498	return SSMR3PutU32(pSSM, ~0); /* terminator. */
2499	}
2500
2501
2502	/**
2503	* Load an ignored page.
2504	*
2505	* @returns VBox status code.
2506	* @param pSSM The saved state handle.
2507	*/
2508	static int pgmR3LoadPageToDevNull(PSSMHANDLE pSSM)
2509	{
2510	uint8_t abPage[PAGE_SIZE];
2511	return SSMR3GetMem(pSSM, &abPage[0], sizeof(abPage));
2512	}
2513
2514
2515	/**
2516	* Loads a page without any bits in the saved state, i.e. making sure it's
2517	* really zero.
2518	*
2519	* @returns VBox status code.
2520	* @param pVM The VM handle.
2521	* @param uType The page type or PGMPAGETYPE_INVALID (old saved
2522	* state).
2523	* @param pPage The guest page tracking structure.
2524	* @param GCPhys The page address.
2525	* @param pRam The ram range (logging).
2526	*/
2527	static int pgmR3LoadPageZero(PVM pVM, uint8_t uType, PPGMPAGE pPage, RTGCPHYS GCPhys, PPGMRAMRANGE pRam)
2528	{
2529	if ( PGM_PAGE_GET_TYPE(pPage) != uType
2530	&& uType != PGMPAGETYPE_INVALID)
2531	return VERR_SSM_UNEXPECTED_DATA;
2532
2533	/* I think this should be sufficient. */
2534	if (!PGM_PAGE_IS_ZERO(pPage))
2535	return VERR_SSM_UNEXPECTED_DATA;
2536
2537	NOREF(pVM);
2538	NOREF(GCPhys);
2539	NOREF(pRam);
2540	return VINF_SUCCESS;
2541	}
2542
2543
2544	/**
2545	* Loads a page from the saved state.
2546	*
2547	* @returns VBox status code.
2548	* @param pVM The VM handle.
2549	* @param pSSM The SSM handle.
2550	* @param uType The page type or PGMPAGETYEP_INVALID (old saved
2551	* state).
2552	* @param pPage The guest page tracking structure.
2553	* @param GCPhys The page address.
2554	* @param pRam The ram range (logging).
2555	*/
2556	static int pgmR3LoadPageBits(PVM pVM, PSSMHANDLE pSSM, uint8_t uType, PPGMPAGE pPage, RTGCPHYS GCPhys, PPGMRAMRANGE pRam)
2557	{
2558	int rc;
2559
2560	/*
2561	* Match up the type, dealing with MMIO2 aliases (dropped).
2562	*/
2563	AssertLogRelMsgReturn( PGM_PAGE_GET_TYPE(pPage) == uType
2564	\|\| uType == PGMPAGETYPE_INVALID,
2565	("pPage=%R[pgmpage] GCPhys=%#x %s\n", pPage, GCPhys, pRam->pszDesc),
2566	VERR_SSM_UNEXPECTED_DATA);
2567
2568	/*
2569	* Load the page.
2570	*/
2571	void *pvPage;
2572	rc = pgmPhysGCPhys2CCPtrInternal(pVM, pPage, GCPhys, &pvPage);
2573	if (RT_SUCCESS(rc))
2574	rc = SSMR3GetMem(pSSM, pvPage, PAGE_SIZE);
2575
2576	return rc;
2577	}
2578
2579
2580	/**
2581	* Loads a page (counter part to pgmR3SavePage).
2582	*
2583	* @returns VBox status code, fully bitched errors.
2584	* @param pVM The VM handle.
2585	* @param pSSM The SSM handle.
2586	* @param uType The page type.
2587	* @param pPage The page.
2588	* @param GCPhys The page address.
2589	* @param pRam The RAM range (for error messages).
2590	*/
2591	static int pgmR3LoadPage(PVM pVM, PSSMHANDLE pSSM, uint8_t uType, PPGMPAGE pPage, RTGCPHYS GCPhys, PPGMRAMRANGE pRam)
2592	{
2593	uint8_t uState;
2594	int rc = SSMR3GetU8(pSSM, &uState);
2595	AssertLogRelMsgRCReturn(rc, ("pPage=%R[pgmpage] GCPhys=%#x %s rc=%Rrc\n", pPage, GCPhys, pRam->pszDesc, rc), rc);
2596	if (uState == 0 /* zero */)
2597	rc = pgmR3LoadPageZero(pVM, uType, pPage, GCPhys, pRam);
2598	else if (uState == 1)
2599	rc = pgmR3LoadPageBits(pVM, pSSM, uType, pPage, GCPhys, pRam);
2600	else
2601	rc = VERR_INTERNAL_ERROR;
2602	AssertLogRelMsgRCReturn(rc, ("pPage=%R[pgmpage] uState=%d uType=%d GCPhys=%RGp %s rc=%Rrc\n",
2603	pPage, uState, uType, GCPhys, pRam->pszDesc, rc),
2604	rc);
2605	return VINF_SUCCESS;
2606	}
2607
2608
2609	/**
2610	* Loads a shadowed ROM page.
2611	*
2612	* @returns VBox status code, errors are fully bitched.
2613	* @param pVM The VM handle.
2614	* @param pSSM The saved state handle.
2615	* @param pPage The page.
2616	* @param GCPhys The page address.
2617	* @param pRam The RAM range (for error messages).
2618	*/
2619	static int pgmR3LoadShadowedRomPage(PVM pVM, PSSMHANDLE pSSM, PPGMPAGE pPage, RTGCPHYS GCPhys, PPGMRAMRANGE pRam)
2620	{
2621	/*
2622	* Load and set the protection first, then load the two pages, the first
2623	* one is the active the other is the passive.
2624	*/
2625	PPGMROMPAGE pRomPage = pgmR3GetRomPage(pVM, GCPhys);
2626	AssertLogRelMsgReturn(pRomPage, ("GCPhys=%RGp %s\n", GCPhys, pRam->pszDesc), VERR_INTERNAL_ERROR);
2627
2628	uint8_t uProt;
2629	int rc = SSMR3GetU8(pSSM, &uProt);
2630	AssertLogRelMsgRCReturn(rc, ("pPage=%R[pgmpage] GCPhys=%#x %s\n", pPage, GCPhys, pRam->pszDesc), rc);
2631	PGMROMPROT enmProt = (PGMROMPROT)uProt;
2632	AssertLogRelMsgReturn( enmProt >= PGMROMPROT_INVALID
2633	&& enmProt < PGMROMPROT_END,
2634	("enmProt=%d pPage=%R[pgmpage] GCPhys=%#x %s\n", enmProt, pPage, GCPhys, pRam->pszDesc),
2635	VERR_SSM_UNEXPECTED_DATA);
2636
2637	if (pRomPage->enmProt != enmProt)
2638	{
2639	rc = PGMR3PhysRomProtect(pVM, GCPhys, PAGE_SIZE, enmProt);
2640	AssertLogRelRCReturn(rc, rc);
2641	AssertLogRelReturn(pRomPage->enmProt == enmProt, VERR_INTERNAL_ERROR);
2642	}
2643
2644	PPGMPAGE pPageActive = PGMROMPROT_IS_ROM(enmProt) ? &pRomPage->Virgin : &pRomPage->Shadow;
2645	PPGMPAGE pPagePassive = PGMROMPROT_IS_ROM(enmProt) ? &pRomPage->Shadow : &pRomPage->Virgin;
2646	uint8_t u8ActiveType = PGMROMPROT_IS_ROM(enmProt) ? PGMPAGETYPE_ROM : PGMPAGETYPE_ROM_SHADOW;
2647	uint8_t u8PassiveType= PGMROMPROT_IS_ROM(enmProt) ? PGMPAGETYPE_ROM_SHADOW : PGMPAGETYPE_ROM;
2648
2649	rc = pgmR3LoadPage(pVM, pSSM, u8ActiveType, pPage, GCPhys, pRam);
2650	if (RT_SUCCESS(rc))
2651	{
2652	pPageActive = pPage;
2653	rc = pgmR3LoadPage(pVM, pSSM, u8PassiveType, pPagePassive, GCPhys, pRam);
2654	}
2655	return rc;
2656	}
2657
2658
2659	/**
2660	* Worker for pgmR3Load.
2661	*
2662	* @returns VBox status code.
2663	*
2664	* @param pVM The VM handle.
2665	* @param pSSM The SSM handle.
2666	* @param u32Version The saved state version.
2667	*/
2668	static int pgmR3LoadLocked(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version)
2669	{
2670	PPGM pPGM = &pVM->pgm.s;
2671	int rc;
2672	uint32_t u32Sep;
2673
2674	/*
2675	* Load basic data (required / unaffected by relocation).
2676	*/
2677	if (u32Version >= PGM_SAVED_STATE_VERSION)
2678	{
2679	rc = SSMR3GetStruct(pSSM, pPGM, &s_aPGMFields[0]);
2680	AssertLogRelRCReturn(rc, rc);
2681
2682	for (VMCPUID i = 0; i < pVM->cCPUs; i++)
2683	{
2684	rc = SSMR3GetStruct(pSSM, &pVM->aCpus[i].pgm.s, &s_aPGMCpuFields[0]);
2685	AssertLogRelRCReturn(rc, rc);
2686	}
2687	}
2688	else if (u32Version >= PGM_SAVED_STATE_VERSION_RR_DESC)
2689	{
2690	AssertRelease(pVM->cCPUs == 1);
2691
2692	PGMOLD pgmOld;
2693	rc = SSMR3GetStruct(pSSM, &pgmOld, &s_aPGMFields_Old[0]);
2694	AssertLogRelRCReturn(rc, rc);
2695
2696	pPGM->fMappingsFixed = pgmOld.fMappingsFixed;
2697	pPGM->GCPtrMappingFixed = pgmOld.GCPtrMappingFixed;
2698	pPGM->cbMappingFixed = pgmOld.cbMappingFixed;
2699
2700	pVM->aCpus[0].pgm.s.fA20Enabled = pgmOld.fA20Enabled;
2701	pVM->aCpus[0].pgm.s.GCPhysA20Mask = pgmOld.GCPhysA20Mask;
2702	pVM->aCpus[0].pgm.s.enmGuestMode = pgmOld.enmGuestMode;
2703	}
2704	else
2705	{
2706	AssertRelease(pVM->cCPUs == 1);
2707
2708	SSMR3GetBool(pSSM, &pPGM->fMappingsFixed);
2709	SSMR3GetGCPtr(pSSM, &pPGM->GCPtrMappingFixed);
2710	SSMR3GetU32(pSSM, &pPGM->cbMappingFixed);
2711
2712	uint32_t cbRamSizeIgnored;
2713	rc = SSMR3GetU32(pSSM, &cbRamSizeIgnored);
2714	if (RT_FAILURE(rc))
2715	return rc;
2716	SSMR3GetGCPhys(pSSM, &pVM->aCpus[0].pgm.s.GCPhysA20Mask);
2717
2718	uint32_t u32 = 0;
2719	SSMR3GetUInt(pSSM, &u32);
2720	pVM->aCpus[0].pgm.s.fA20Enabled = !!u32;
2721	SSMR3GetUInt(pSSM, &pVM->aCpus[0].pgm.s.fSyncFlags);
2722	RTUINT uGuestMode;
2723	SSMR3GetUInt(pSSM, &uGuestMode);
2724	pVM->aCpus[0].pgm.s.enmGuestMode = (PGMMODE)uGuestMode;
2725
2726	/* check separator. */
2727	SSMR3GetU32(pSSM, &u32Sep);
2728	if (RT_FAILURE(rc))
2729	return rc;
2730	if (u32Sep != (uint32_t)~0)
2731	{
2732	AssertMsgFailed(("u32Sep=%#x (first)\n", u32Sep));
2733	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2734	}
2735	}
2736
2737	/*
2738	* The guest mappings.
2739	*/
2740	uint32_t i = 0;
2741	for (;; i++)
2742	{
2743	/* Check the seqence number / separator. */
2744	rc = SSMR3GetU32(pSSM, &u32Sep);
2745	if (RT_FAILURE(rc))
2746	return rc;
2747	if (u32Sep == ~0U)
2748	break;
2749	if (u32Sep != i)
2750	{
2751	AssertMsgFailed(("u32Sep=%#x (last)\n", u32Sep));
2752	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2753	}
2754
2755	/* get the mapping details. */
2756	char szDesc[256];
2757	szDesc[0] = '\0';
2758	rc = SSMR3GetStrZ(pSSM, szDesc, sizeof(szDesc));
2759	if (RT_FAILURE(rc))
2760	return rc;
2761	RTGCPTR GCPtr;
2762	SSMR3GetGCPtr(pSSM, &GCPtr);
2763	RTGCPTR cPTs;
2764	rc = SSMR3GetGCUIntPtr(pSSM, &cPTs);
2765	if (RT_FAILURE(rc))
2766	return rc;
2767
2768	/* find matching range. */
2769	PPGMMAPPING pMapping;
2770	for (pMapping = pPGM->pMappingsR3; pMapping; pMapping = pMapping->pNextR3)
2771	if ( pMapping->cPTs == cPTs
2772	&& !strcmp(pMapping->pszDesc, szDesc))
2773	break;
2774	AssertLogRelMsgReturn(pMapping, ("Couldn't find mapping: cPTs=%#x szDesc=%s (GCPtr=%RGv)\n",
2775	cPTs, szDesc, GCPtr),
2776	VERR_SSM_LOAD_CONFIG_MISMATCH);
2777
2778	/* relocate it. */
2779	if (pMapping->GCPtr != GCPtr)
2780	{
2781	AssertMsg((GCPtr >> X86_PD_SHIFT << X86_PD_SHIFT) == GCPtr, ("GCPtr=%RGv\n", GCPtr));
2782	pgmR3MapRelocate(pVM, pMapping, pMapping->GCPtr, GCPtr);
2783	}
2784	else
2785	Log(("pgmR3Load: '%s' needed no relocation (%RGv)\n", szDesc, GCPtr));
2786	}
2787
2788	/*
2789	* Ram range flags and bits.
2790	*/
2791	i = 0;
2792	for (PPGMRAMRANGE pRam = pPGM->pRamRangesR3; ; pRam = pRam->pNextR3, i++)
2793	{
2794	/* Check the seqence number / separator. */
2795	rc = SSMR3GetU32(pSSM, &u32Sep);
2796	if (RT_FAILURE(rc))
2797	return rc;
2798	if (u32Sep == ~0U)
2799	break;
2800	if (u32Sep != i)
2801	{
2802	AssertMsgFailed(("u32Sep=%#x (last)\n", u32Sep));
2803	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2804	}
2805	AssertLogRelReturn(pRam, VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2806
2807	/* Get the range details. */
2808	RTGCPHYS GCPhys;
2809	SSMR3GetGCPhys(pSSM, &GCPhys);
2810	RTGCPHYS GCPhysLast;
2811	SSMR3GetGCPhys(pSSM, &GCPhysLast);
2812	RTGCPHYS cb;
2813	SSMR3GetGCPhys(pSSM, &cb);
2814	uint8_t fHaveBits;
2815	rc = SSMR3GetU8(pSSM, &fHaveBits);
2816	if (RT_FAILURE(rc))
2817	return rc;
2818	if (fHaveBits & ~1)
2819	{
2820	AssertMsgFailed(("u32Sep=%#x (last)\n", u32Sep));
2821	return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
2822	}
2823	size_t cchDesc = 0;
2824	char szDesc[256];
2825	szDesc[0] = '\0';
2826	if (u32Version >= PGM_SAVED_STATE_VERSION_RR_DESC)
2827	{
2828	rc = SSMR3GetStrZ(pSSM, szDesc, sizeof(szDesc));
2829	if (RT_FAILURE(rc))
2830	return rc;
2831	/* Since we've modified the description strings in r45878, only compare
2832	them if the saved state is more recent. */
2833	if (u32Version != PGM_SAVED_STATE_VERSION_RR_DESC)
2834	cchDesc = strlen(szDesc);
2835	}
2836
2837	/*
2838	* Match it up with the current range.
2839	*
2840	* Note there is a hack for dealing with the high BIOS mapping
2841	* in the old saved state format, this means we might not have
2842	* a 1:1 match on success.
2843	*/
2844	if ( ( GCPhys != pRam->GCPhys
2845	\|\| GCPhysLast != pRam->GCPhysLast
2846	\|\| cb != pRam->cb
2847	\|\| ( cchDesc
2848	&& strcmp(szDesc, pRam->pszDesc)) )
2849	/* Hack for PDMDevHlpPhysReserve(pDevIns, 0xfff80000, 0x80000, "High ROM Region"); */
2850	&& ( u32Version != PGM_SAVED_STATE_VERSION_OLD_PHYS_CODE
2851	\|\| GCPhys != UINT32_C(0xfff80000)
2852	\|\| GCPhysLast != UINT32_C(0xffffffff)
2853	\|\| pRam->GCPhysLast != GCPhysLast
2854	\|\| pRam->GCPhys < GCPhys
2855	\|\| !fHaveBits)
2856	)
2857	{
2858	LogRel(("Ram range: %RGp-%RGp %RGp bytes %s %s\n"
2859	"State : %RGp-%RGp %RGp bytes %s %s\n",
2860	pRam->GCPhys, pRam->GCPhysLast, pRam->cb, pRam->pvR3 ? "bits" : "nobits", pRam->pszDesc,
2861	GCPhys, GCPhysLast, cb, fHaveBits ? "bits" : "nobits", szDesc));
2862	/*
2863	* If we're loading a state for debugging purpose, don't make a fuss if
2864	* the MMIO and ROM stuff isn't 100% right, just skip the mismatches.
2865	*/
2866	if ( SSMR3HandleGetAfter(pSSM) != SSMAFTER_DEBUG_IT
2867	\|\| GCPhys < 8 * _1M)
2868	AssertFailedReturn(VERR_SSM_LOAD_CONFIG_MISMATCH);
2869
2870	AssertMsgFailed(("debug skipping not implemented, sorry\n"));
2871	continue;
2872	}
2873
2874	uint32_t cPages = (GCPhysLast - GCPhys + 1) >> PAGE_SHIFT;
2875	if (u32Version >= PGM_SAVED_STATE_VERSION_RR_DESC)
2876	{
2877	/*
2878	* Load the pages one by one.
2879	*/
2880	for (uint32_t iPage = 0; iPage < cPages; iPage++)
2881	{
2882	RTGCPHYS const GCPhysPage = ((RTGCPHYS)iPage << PAGE_SHIFT) + pRam->GCPhys;
2883	PPGMPAGE pPage = &pRam->aPages[iPage];
2884	uint8_t uType;
2885	rc = SSMR3GetU8(pSSM, &uType);
2886	AssertLogRelMsgRCReturn(rc, ("pPage=%R[pgmpage] iPage=%#x GCPhysPage=%#x %s\n", pPage, iPage, GCPhysPage, pRam->pszDesc), rc);
2887	if (uType == PGMPAGETYPE_ROM_SHADOW)
2888	rc = pgmR3LoadShadowedRomPage(pVM, pSSM, pPage, GCPhysPage, pRam);
2889	else
2890	rc = pgmR3LoadPage(pVM, pSSM, uType, pPage, GCPhysPage, pRam);
2891	AssertLogRelMsgRCReturn(rc, ("rc=%Rrc iPage=%#x GCPhysPage=%#x %s\n", rc, iPage, GCPhysPage, pRam->pszDesc), rc);
2892	}
2893	}
2894	else
2895	{
2896	/*
2897	* Old format.
2898	*/
2899	AssertLogRelReturn(!pVM->pgm.s.fRamPreAlloc, VERR_NOT_SUPPORTED); /* can't be detected. */
2900
2901	/* Of the page flags, pick up MMIO2 and ROM/RESERVED for the !fHaveBits case.
2902	The rest is generally irrelevant and wrong since the stuff have to match registrations. */
2903	uint32_t fFlags = 0;
2904	for (uint32_t iPage = 0; iPage < cPages; iPage++)
2905	{
2906	uint16_t u16Flags;
2907	rc = SSMR3GetU16(pSSM, &u16Flags);
2908	AssertLogRelMsgRCReturn(rc, ("rc=%Rrc iPage=%#x GCPhys=%#x %s\n", rc, iPage, pRam->GCPhys, pRam->pszDesc), rc);
2909	fFlags \|= u16Flags;
2910	}
2911
2912	/* Load the bits */
2913	if ( !fHaveBits
2914	&& GCPhysLast < UINT32_C(0xe0000000))
2915	{
2916	/*
2917	* Dynamic chunks.
2918	*/
2919	const uint32_t cPagesInChunk = (110241024) >> PAGE_SHIFT;
2920	AssertLogRelMsgReturn(cPages % cPagesInChunk == 0,
2921	("cPages=%#x cPagesInChunk=%#x\n", cPages, cPagesInChunk, pRam->GCPhys, pRam->pszDesc),
2922	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2923
2924	for (uint32_t iPage = 0; iPage < cPages; /* incremented by inner loop */ )
2925	{
2926	uint8_t fPresent;
2927	rc = SSMR3GetU8(pSSM, &fPresent);
2928	AssertLogRelMsgRCReturn(rc, ("rc=%Rrc iPage=%#x GCPhys=%#x %s\n", rc, iPage, pRam->GCPhys, pRam->pszDesc), rc);
2929	AssertLogRelMsgReturn(fPresent == (uint8_t)true \|\| fPresent == (uint8_t)false,
2930	("fPresent=%#x iPage=%#x GCPhys=%#x %s\n", fPresent, iPage, pRam->GCPhys, pRam->pszDesc),
2931	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2932
2933	for (uint32_t iChunkPage = 0; iChunkPage < cPagesInChunk; iChunkPage++, iPage++)
2934	{
2935	RTGCPHYS const GCPhysPage = ((RTGCPHYS)iPage << PAGE_SHIFT) + pRam->GCPhys;
2936	PPGMPAGE pPage = &pRam->aPages[iPage];
2937	if (fPresent)
2938	{
2939	if (PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_MMIO)
2940	rc = pgmR3LoadPageToDevNull(pSSM);
2941	else
2942	rc = pgmR3LoadPageBits(pVM, pSSM, PGMPAGETYPE_INVALID, pPage, GCPhysPage, pRam);
2943	}
2944	else
2945	rc = pgmR3LoadPageZero(pVM, PGMPAGETYPE_INVALID, pPage, GCPhysPage, pRam);
2946	AssertLogRelMsgRCReturn(rc, ("rc=%Rrc iPage=%#x GCPhysPage=%#x %s\n", rc, iPage, GCPhysPage, pRam->pszDesc), rc);
2947	}
2948	}
2949	}
2950	else if (pRam->pvR3)
2951	{
2952	/*
2953	* MMIO2.
2954	*/
2955	AssertLogRelMsgReturn((fFlags & 0x0f) == RT_BIT(3) /MM_RAM_FLAGS_MMIO2/,
2956	("fFlags=%#x GCPhys=%#x %s\n", fFlags, pRam->GCPhys, pRam->pszDesc),
2957	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2958	AssertLogRelMsgReturn(pRam->pvR3,
2959	("GCPhys=%#x %s\n", pRam->GCPhys, pRam->pszDesc),
2960	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2961
2962	rc = SSMR3GetMem(pSSM, pRam->pvR3, pRam->cb);
2963	AssertLogRelMsgRCReturn(rc, ("GCPhys=%#x %s\n", pRam->GCPhys, pRam->pszDesc), rc);
2964	}
2965	else if (GCPhysLast < UINT32_C(0xfff80000))
2966	{
2967	/*
2968	* PCI MMIO, no pages saved.
2969	*/
2970	}
2971	else
2972	{
2973	/*
2974	* Load the 0xfff80000..0xffffffff BIOS range.
2975	* It starts with X reserved pages that we have to skip over since
2976	* the RAMRANGE create by the new code won't include those.
2977	*/
2978	AssertLogRelMsgReturn( !(fFlags & RT_BIT(3) /MM_RAM_FLAGS_MMIO2/)
2979	&& (fFlags & RT_BIT(0) /MM_RAM_FLAGS_RESERVED/),
2980	("fFlags=%#x GCPhys=%#x %s\n", fFlags, pRam->GCPhys, pRam->pszDesc),
2981	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2982	AssertLogRelMsgReturn(GCPhys == UINT32_C(0xfff80000),
2983	("GCPhys=%RGp pRamRange{GCPhys=%#x %s}\n", GCPhys, pRam->GCPhys, pRam->pszDesc),
2984	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
2985
2986	/* Skip wasted reserved pages before the ROM. */
2987	while (GCPhys < pRam->GCPhys)
2988	{
2989	rc = pgmR3LoadPageToDevNull(pSSM);
2990	GCPhys += PAGE_SIZE;
2991	}
2992
2993	/* Load the bios pages. */
2994	cPages = pRam->cb >> PAGE_SHIFT;
2995	for (uint32_t iPage = 0; iPage < cPages; iPage++)
2996	{
2997	RTGCPHYS const GCPhysPage = ((RTGCPHYS)iPage << PAGE_SHIFT) + pRam->GCPhys;
2998	PPGMPAGE pPage = &pRam->aPages[iPage];
2999
3000	AssertLogRelMsgReturn(PGM_PAGE_GET_TYPE(pPage) == PGMPAGETYPE_ROM,
3001	("GCPhys=%RGp pPage=%R[pgmpage]\n", GCPhys, GCPhys),
3002	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
3003	rc = pgmR3LoadPageBits(pVM, pSSM, PGMPAGETYPE_ROM, pPage, GCPhysPage, pRam);
3004	AssertLogRelMsgRCReturn(rc, ("rc=%Rrc iPage=%#x GCPhys=%#x %s\n", rc, iPage, pRam->GCPhys, pRam->pszDesc), rc);
3005	}
3006	}
3007	}
3008	}
3009
3010	return rc;
3011	}
3012
3013
3014	/**
3015	* Execute state load operation.
3016	*
3017	* @returns VBox status code.
3018	* @param pVM VM Handle.
3019	* @param pSSM SSM operation handle.
3020	* @param u32Version Data layout version.
3021	*/
3022	static DECLCALLBACK(int) pgmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t u32Version)
3023	{
3024	int rc;
3025	PPGM pPGM = &pVM->pgm.s;
3026
3027	/*
3028	* Validate version.
3029	*/
3030	if ( u32Version != PGM_SAVED_STATE_VERSION
3031	&& u32Version != PGM_SAVED_STATE_VERSION_2_2_2
3032	&& u32Version != PGM_SAVED_STATE_VERSION_RR_DESC
3033	&& u32Version != PGM_SAVED_STATE_VERSION_OLD_PHYS_CODE)
3034	{
3035	AssertMsgFailed(("pgmR3Load: Invalid version u32Version=%d (current %d)!\n", u32Version, PGM_SAVED_STATE_VERSION));
3036	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
3037	}
3038
3039	/*
3040	* Call the reset function to make sure all the memory is cleared.
3041	*/
3042	PGMR3Reset(pVM);
3043
3044	/*
3045	* Do the loading while owning the lock because a bunch of the functions
3046	* we're using requires this.
3047	*/
3048	pgmLock(pVM);
3049	rc = pgmR3LoadLocked(pVM, pSSM, u32Version);
3050	pgmUnlock(pVM);
3051	if (RT_SUCCESS(rc))
3052	{
3053	/*
3054	* We require a full resync now.
3055	*/
3056	for (unsigned i=0;i<pVM->cCPUs;i++)
3057	{
3058	PVMCPU pVCpu = &pVM->aCpus[i];
3059	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL);
3060	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
3061
3062	pVCpu->pgm.s.fSyncFlags \|= PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL;
3063	}
3064
3065	pgmR3HandlerPhysicalUpdateAll(pVM);
3066
3067	for (unsigned i=0;i<pVM->cCPUs;i++)
3068	{
3069	PVMCPU pVCpu = &pVM->aCpus[i];
3070
3071	/*
3072	* Change the paging mode.
3073	*/
3074	rc = PGMR3ChangeMode(pVM, pVCpu, pVCpu->pgm.s.enmGuestMode);
3075
3076	/* Restore pVM->pgm.s.GCPhysCR3. */
3077	Assert(pVCpu->pgm.s.GCPhysCR3 == NIL_RTGCPHYS);
3078	RTGCPHYS GCPhysCR3 = CPUMGetGuestCR3(pVCpu);
3079	if ( pVCpu->pgm.s.enmGuestMode == PGMMODE_PAE
3080	\|\| pVCpu->pgm.s.enmGuestMode == PGMMODE_PAE_NX
3081	\|\| pVCpu->pgm.s.enmGuestMode == PGMMODE_AMD64
3082	\|\| pVCpu->pgm.s.enmGuestMode == PGMMODE_AMD64_NX)
3083	GCPhysCR3 = (GCPhysCR3 & X86_CR3_PAE_PAGE_MASK);
3084	else
3085	GCPhysCR3 = (GCPhysCR3 & X86_CR3_PAGE_MASK);
3086	pVCpu->pgm.s.GCPhysCR3 = GCPhysCR3;
3087	}
3088	}
3089
3090	return rc;
3091	}
3092
3093
3094	/**
3095	* Show paging mode.
3096	*
3097	* @param pVM VM Handle.
3098	* @param pHlp The info helpers.
3099	* @param pszArgs "all" (default), "guest", "shadow" or "host".
3100	*/
3101	static DECLCALLBACK(void) pgmR3InfoMode(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3102	{
3103	/* digest argument. */
3104	bool fGuest, fShadow, fHost;
3105	if (pszArgs)
3106	pszArgs = RTStrStripL(pszArgs);
3107	if (!pszArgs \|\| !*pszArgs \|\| strstr(pszArgs, "all"))
3108	fShadow = fHost = fGuest = true;
3109	else
3110	{
3111	fShadow = fHost = fGuest = false;
3112	if (strstr(pszArgs, "guest"))
3113	fGuest = true;
3114	if (strstr(pszArgs, "shadow"))
3115	fShadow = true;
3116	if (strstr(pszArgs, "host"))
3117	fHost = true;
3118	}
3119
3120	/** @todo SMP support! */
3121	/* print info. */
3122	if (fGuest)
3123	pHlp->pfnPrintf(pHlp, "Guest paging mode: %s, changed %RU64 times, A20 %s\n",
3124	PGMGetModeName(pVM->aCpus[0].pgm.s.enmGuestMode), pVM->aCpus[0].pgm.s.cGuestModeChanges.c,
3125	pVM->aCpus[0].pgm.s.fA20Enabled ? "enabled" : "disabled");
3126	if (fShadow)
3127	pHlp->pfnPrintf(pHlp, "Shadow paging mode: %s\n", PGMGetModeName(pVM->aCpus[0].pgm.s.enmShadowMode));
3128	if (fHost)
3129	{
3130	const char *psz;
3131	switch (pVM->pgm.s.enmHostMode)
3132	{
3133	case SUPPAGINGMODE_INVALID: psz = "invalid"; break;
3134	case SUPPAGINGMODE_32_BIT: psz = "32-bit"; break;
3135	case SUPPAGINGMODE_32_BIT_GLOBAL: psz = "32-bit+G"; break;
3136	case SUPPAGINGMODE_PAE: psz = "PAE"; break;
3137	case SUPPAGINGMODE_PAE_GLOBAL: psz = "PAE+G"; break;
3138	case SUPPAGINGMODE_PAE_NX: psz = "PAE+NX"; break;
3139	case SUPPAGINGMODE_PAE_GLOBAL_NX: psz = "PAE+G+NX"; break;
3140	case SUPPAGINGMODE_AMD64: psz = "AMD64"; break;
3141	case SUPPAGINGMODE_AMD64_GLOBAL: psz = "AMD64+G"; break;
3142	case SUPPAGINGMODE_AMD64_NX: psz = "AMD64+NX"; break;
3143	case SUPPAGINGMODE_AMD64_GLOBAL_NX: psz = "AMD64+G+NX"; break;
3144	default: psz = "unknown"; break;
3145	}
3146	pHlp->pfnPrintf(pHlp, "Host paging mode: %s\n", psz);
3147	}
3148	}
3149
3150
3151	/**
3152	* Dump registered MMIO ranges to the log.
3153	*
3154	* @param pVM VM Handle.
3155	* @param pHlp The info helpers.
3156	* @param pszArgs Arguments, ignored.
3157	*/
3158	static DECLCALLBACK(void) pgmR3PhysInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3159	{
3160	NOREF(pszArgs);
3161	pHlp->pfnPrintf(pHlp,
3162	"RAM ranges (pVM=%p)\n"
3163	"%.s %.s\n",
3164	pVM,
3165	sizeof(RTGCPHYS) * 4 + 1, "GC Phys Range ",
3166	sizeof(RTHCPTR) * 2, "pvHC ");
3167
3168	for (PPGMRAMRANGE pCur = pVM->pgm.s.pRamRangesR3; pCur; pCur = pCur->pNextR3)
3169	pHlp->pfnPrintf(pHlp,
3170	"%RGp-%RGp %RHv %s\n",
3171	pCur->GCPhys,
3172	pCur->GCPhysLast,
3173	pCur->pvR3,
3174	pCur->pszDesc);
3175	}
3176
3177	/**
3178	* Dump the page directory to the log.
3179	*
3180	* @param pVM VM Handle.
3181	* @param pHlp The info helpers.
3182	* @param pszArgs Arguments, ignored.
3183	*/
3184	static DECLCALLBACK(void) pgmR3InfoCr3(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3185	{
3186	/** @todo SMP support!! */
3187	PVMCPU pVCpu = &pVM->aCpus[0];
3188
3189	/** @todo fix this! Convert the PGMR3DumpHierarchyHC functions to do guest stuff. */
3190	/* Big pages supported? */
3191	const bool fPSE = !!(CPUMGetGuestCR4(pVCpu) & X86_CR4_PSE);
3192
3193	/* Global pages supported? */
3194	const bool fPGE = !!(CPUMGetGuestCR4(pVCpu) & X86_CR4_PGE);
3195
3196	NOREF(pszArgs);
3197
3198	/*
3199	* Get page directory addresses.
3200	*/
3201	PX86PD pPDSrc = pgmGstGet32bitPDPtr(&pVCpu->pgm.s);
3202	Assert(pPDSrc);
3203	Assert(PGMPhysGCPhys2R3PtrAssert(pVM, (RTGCPHYS)(CPUMGetGuestCR3(pVCpu) & X86_CR3_PAGE_MASK), sizeof(*pPDSrc)) == pPDSrc);
3204
3205	/*
3206	* Iterate the page directory.
3207	*/
3208	for (unsigned iPD = 0; iPD < RT_ELEMENTS(pPDSrc->a); iPD++)
3209	{
3210	X86PDE PdeSrc = pPDSrc->a[iPD];
3211	if (PdeSrc.n.u1Present)
3212	{
3213	if (PdeSrc.b.u1Size && fPSE)
3214	pHlp->pfnPrintf(pHlp,
3215	"%04X - %RGp P=%d U=%d RW=%d G=%d - BIG\n",
3216	iPD,
3217	pgmGstGet4MBPhysPage(&pVM->pgm.s, PdeSrc),
3218	PdeSrc.b.u1Present, PdeSrc.b.u1User, PdeSrc.b.u1Write, PdeSrc.b.u1Global && fPGE);
3219	else
3220	pHlp->pfnPrintf(pHlp,
3221	"%04X - %RGp P=%d U=%d RW=%d [G=%d]\n",
3222	iPD,
3223	(RTGCPHYS)(PdeSrc.u & X86_PDE_PG_MASK),
3224	PdeSrc.n.u1Present, PdeSrc.n.u1User, PdeSrc.n.u1Write, PdeSrc.b.u1Global && fPGE);
3225	}
3226	}
3227	}
3228
3229
3230	/**
3231	* Service a VMMCALLRING3_PGM_LOCK call.
3232	*
3233	* @returns VBox status code.
3234	* @param pVM The VM handle.
3235	*/
3236	VMMR3DECL(int) PGMR3LockCall(PVM pVM)
3237	{
3238	int rc = PDMR3CritSectEnterEx(&pVM->pgm.s.CritSect, true /* fHostCall */);
3239	AssertRC(rc);
3240	return rc;
3241	}
3242
3243
3244	/**
3245	* Converts a PGMMODE value to a PGM_TYPE_* \#define.
3246	*
3247	* @returns PGM_TYPE_*.
3248	* @param pgmMode The mode value to convert.
3249	*/
3250	DECLINLINE(unsigned) pgmModeToType(PGMMODE pgmMode)
3251	{
3252	switch (pgmMode)
3253	{
3254	case PGMMODE_REAL: return PGM_TYPE_REAL;
3255	case PGMMODE_PROTECTED: return PGM_TYPE_PROT;
3256	case PGMMODE_32_BIT: return PGM_TYPE_32BIT;
3257	case PGMMODE_PAE:
3258	case PGMMODE_PAE_NX: return PGM_TYPE_PAE;
3259	case PGMMODE_AMD64:
3260	case PGMMODE_AMD64_NX: return PGM_TYPE_AMD64;
3261	case PGMMODE_NESTED: return PGM_TYPE_NESTED;
3262	case PGMMODE_EPT: return PGM_TYPE_EPT;
3263	default:
3264	AssertFatalMsgFailed(("pgmMode=%d\n", pgmMode));
3265	}
3266	}
3267
3268
3269	/**
3270	* Gets the index into the paging mode data array of a SHW+GST mode.
3271	*
3272	* @returns PGM::paPagingData index.
3273	* @param uShwType The shadow paging mode type.
3274	* @param uGstType The guest paging mode type.
3275	*/
3276	DECLINLINE(unsigned) pgmModeDataIndex(unsigned uShwType, unsigned uGstType)
3277	{
3278	Assert(uShwType >= PGM_TYPE_32BIT && uShwType <= PGM_TYPE_MAX);
3279	Assert(uGstType >= PGM_TYPE_REAL && uGstType <= PGM_TYPE_AMD64);
3280	return (uShwType - PGM_TYPE_32BIT) * (PGM_TYPE_AMD64 - PGM_TYPE_REAL + 1)
3281	+ (uGstType - PGM_TYPE_REAL);
3282	}
3283
3284
3285	/**
3286	* Gets the index into the paging mode data array of a SHW+GST mode.
3287	*
3288	* @returns PGM::paPagingData index.
3289	* @param enmShw The shadow paging mode.
3290	* @param enmGst The guest paging mode.
3291	*/
3292	DECLINLINE(unsigned) pgmModeDataIndexByMode(PGMMODE enmShw, PGMMODE enmGst)
3293	{
3294	Assert(enmShw >= PGMMODE_32_BIT && enmShw <= PGMMODE_MAX);
3295	Assert(enmGst > PGMMODE_INVALID && enmGst < PGMMODE_MAX);
3296	return pgmModeDataIndex(pgmModeToType(enmShw), pgmModeToType(enmGst));
3297	}
3298
3299
3300	/**
3301	* Calculates the max data index.
3302	* @returns The number of entries in the paging data array.
3303	*/
3304	DECLINLINE(unsigned) pgmModeDataMaxIndex(void)
3305	{
3306	return pgmModeDataIndex(PGM_TYPE_MAX, PGM_TYPE_AMD64) + 1;
3307	}
3308
3309
3310	/**
3311	* Initializes the paging mode data kept in PGM::paModeData.
3312	*
3313	* @param pVM The VM handle.
3314	* @param fResolveGCAndR0 Indicate whether or not GC and Ring-0 symbols can be resolved now.
3315	* This is used early in the init process to avoid trouble with PDM
3316	* not being initialized yet.
3317	*/
3318	static int pgmR3ModeDataInit(PVM pVM, bool fResolveGCAndR0)
3319	{
3320	PPGMMODEDATA pModeData;
3321	int rc;
3322
3323	/*
3324	* Allocate the array on the first call.
3325	*/
3326	if (!pVM->pgm.s.paModeData)
3327	{
3328	pVM->pgm.s.paModeData = (PPGMMODEDATA)MMR3HeapAllocZ(pVM, MM_TAG_PGM, sizeof(PGMMODEDATA) * pgmModeDataMaxIndex());
3329	AssertReturn(pVM->pgm.s.paModeData, VERR_NO_MEMORY);
3330	}
3331
3332	/*
3333	* Initialize the array entries.
3334	*/
3335	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_32BIT, PGM_TYPE_REAL)];
3336	pModeData->uShwType = PGM_TYPE_32BIT;
3337	pModeData->uGstType = PGM_TYPE_REAL;
3338	rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3339	rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3340	rc = PGM_BTH_NAME_32BIT_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3341
3342	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_32BIT, PGMMODE_PROTECTED)];
3343	pModeData->uShwType = PGM_TYPE_32BIT;
3344	pModeData->uGstType = PGM_TYPE_PROT;
3345	rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3346	rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3347	rc = PGM_BTH_NAME_32BIT_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3348
3349	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_32BIT, PGM_TYPE_32BIT)];
3350	pModeData->uShwType = PGM_TYPE_32BIT;
3351	pModeData->uGstType = PGM_TYPE_32BIT;
3352	rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3353	rc = PGM_GST_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3354	rc = PGM_BTH_NAME_32BIT_32BIT(InitData)(pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3355
3356	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_REAL)];
3357	pModeData->uShwType = PGM_TYPE_PAE;
3358	pModeData->uGstType = PGM_TYPE_REAL;
3359	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3360	rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3361	rc = PGM_BTH_NAME_PAE_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3362
3363	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_PROT)];
3364	pModeData->uShwType = PGM_TYPE_PAE;
3365	pModeData->uGstType = PGM_TYPE_PROT;
3366	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3367	rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3368	rc = PGM_BTH_NAME_PAE_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3369
3370	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_32BIT)];
3371	pModeData->uShwType = PGM_TYPE_PAE;
3372	pModeData->uGstType = PGM_TYPE_32BIT;
3373	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3374	rc = PGM_GST_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3375	rc = PGM_BTH_NAME_PAE_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3376
3377	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_PAE)];
3378	pModeData->uShwType = PGM_TYPE_PAE;
3379	pModeData->uGstType = PGM_TYPE_PAE;
3380	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3381	rc = PGM_GST_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3382	rc = PGM_BTH_NAME_PAE_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3383
3384	#ifdef VBOX_WITH_64_BITS_GUESTS
3385	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_AMD64, PGM_TYPE_AMD64)];
3386	pModeData->uShwType = PGM_TYPE_AMD64;
3387	pModeData->uGstType = PGM_TYPE_AMD64;
3388	rc = PGM_SHW_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3389	rc = PGM_GST_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3390	rc = PGM_BTH_NAME_AMD64_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3391	#endif
3392
3393	/* The nested paging mode. */
3394	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_REAL)];
3395	pModeData->uShwType = PGM_TYPE_NESTED;
3396	pModeData->uGstType = PGM_TYPE_REAL;
3397	rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3398	rc = PGM_BTH_NAME_NESTED_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3399
3400	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGMMODE_PROTECTED)];
3401	pModeData->uShwType = PGM_TYPE_NESTED;
3402	pModeData->uGstType = PGM_TYPE_PROT;
3403	rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3404	rc = PGM_BTH_NAME_NESTED_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3405
3406	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_32BIT)];
3407	pModeData->uShwType = PGM_TYPE_NESTED;
3408	pModeData->uGstType = PGM_TYPE_32BIT;
3409	rc = PGM_GST_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3410	rc = PGM_BTH_NAME_NESTED_32BIT(InitData)(pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3411
3412	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_PAE)];
3413	pModeData->uShwType = PGM_TYPE_NESTED;
3414	pModeData->uGstType = PGM_TYPE_PAE;
3415	rc = PGM_GST_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3416	rc = PGM_BTH_NAME_NESTED_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3417
3418	#ifdef VBOX_WITH_64_BITS_GUESTS
3419	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_AMD64)];
3420	pModeData->uShwType = PGM_TYPE_NESTED;
3421	pModeData->uGstType = PGM_TYPE_AMD64;
3422	rc = PGM_GST_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3423	rc = PGM_BTH_NAME_NESTED_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3424	#endif
3425
3426	/* The shadow part of the nested callback mode depends on the host paging mode (AMD-V only). */
3427	switch (pVM->pgm.s.enmHostMode)
3428	{
3429	#if HC_ARCH_BITS == 32
3430	case SUPPAGINGMODE_32_BIT:
3431	case SUPPAGINGMODE_32_BIT_GLOBAL:
3432	for (unsigned i = PGM_TYPE_REAL; i <= PGM_TYPE_PAE; i++)
3433	{
3434	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, i)];
3435	rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3436	}
3437	# ifdef VBOX_WITH_64_BITS_GUESTS
3438	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_AMD64)];
3439	rc = PGM_SHW_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3440	# endif
3441	break;
3442
3443	case SUPPAGINGMODE_PAE:
3444	case SUPPAGINGMODE_PAE_NX:
3445	case SUPPAGINGMODE_PAE_GLOBAL:
3446	case SUPPAGINGMODE_PAE_GLOBAL_NX:
3447	for (unsigned i = PGM_TYPE_REAL; i <= PGM_TYPE_PAE; i++)
3448	{
3449	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, i)];
3450	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3451	}
3452	# ifdef VBOX_WITH_64_BITS_GUESTS
3453	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_AMD64)];
3454	rc = PGM_SHW_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3455	# endif
3456	break;
3457	#endif /* HC_ARCH_BITS == 32 */
3458
3459	#if HC_ARCH_BITS == 64 \|\| defined(RT_OS_DARWIN)
3460	case SUPPAGINGMODE_AMD64:
3461	case SUPPAGINGMODE_AMD64_GLOBAL:
3462	case SUPPAGINGMODE_AMD64_NX:
3463	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
3464	# ifdef VBOX_WITH_64_BITS_GUESTS
3465	for (unsigned i = PGM_TYPE_REAL; i <= PGM_TYPE_AMD64; i++)
3466	# else
3467	for (unsigned i = PGM_TYPE_REAL; i <= PGM_TYPE_PAE; i++)
3468	# endif
3469	{
3470	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, i)];
3471	rc = PGM_SHW_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3472	}
3473	break;
3474	#endif /* HC_ARCH_BITS == 64 \|\| RT_OS_DARWIN */
3475
3476	default:
3477	AssertFailed();
3478	break;
3479	}
3480
3481	/* Extended paging (EPT) / Intel VT-x */
3482	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_REAL)];
3483	pModeData->uShwType = PGM_TYPE_EPT;
3484	pModeData->uGstType = PGM_TYPE_REAL;
3485	rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3486	rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3487	rc = PGM_BTH_NAME_EPT_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3488
3489	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_PROT)];
3490	pModeData->uShwType = PGM_TYPE_EPT;
3491	pModeData->uGstType = PGM_TYPE_PROT;
3492	rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3493	rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3494	rc = PGM_BTH_NAME_EPT_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3495
3496	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_32BIT)];
3497	pModeData->uShwType = PGM_TYPE_EPT;
3498	pModeData->uGstType = PGM_TYPE_32BIT;
3499	rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3500	rc = PGM_GST_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3501	rc = PGM_BTH_NAME_EPT_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3502
3503	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_PAE)];
3504	pModeData->uShwType = PGM_TYPE_EPT;
3505	pModeData->uGstType = PGM_TYPE_PAE;
3506	rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3507	rc = PGM_GST_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3508	rc = PGM_BTH_NAME_EPT_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3509
3510	#ifdef VBOX_WITH_64_BITS_GUESTS
3511	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_AMD64)];
3512	pModeData->uShwType = PGM_TYPE_EPT;
3513	pModeData->uGstType = PGM_TYPE_AMD64;
3514	rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3515	rc = PGM_GST_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3516	rc = PGM_BTH_NAME_EPT_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3517	#endif
3518	return VINF_SUCCESS;
3519	}
3520
3521
3522	/**
3523	* Switch to different (or relocated in the relocate case) mode data.
3524	*
3525	* @param pVM The VM handle.
3526	* @param pVCpu The VMCPU to operate on.
3527	* @param enmShw The the shadow paging mode.
3528	* @param enmGst The the guest paging mode.
3529	*/
3530	static void pgmR3ModeDataSwitch(PVM pVM, PVMCPU pVCpu, PGMMODE enmShw, PGMMODE enmGst)
3531	{
3532	PPGMMODEDATA pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndexByMode(enmShw, enmGst)];
3533
3534	Assert(pModeData->uGstType == pgmModeToType(enmGst));
3535	Assert(pModeData->uShwType == pgmModeToType(enmShw));
3536
3537	/* shadow */
3538	pVCpu->pgm.s.pfnR3ShwRelocate = pModeData->pfnR3ShwRelocate;
3539	pVCpu->pgm.s.pfnR3ShwExit = pModeData->pfnR3ShwExit;
3540	pVCpu->pgm.s.pfnR3ShwGetPage = pModeData->pfnR3ShwGetPage;
3541	Assert(pVCpu->pgm.s.pfnR3ShwGetPage);
3542	pVCpu->pgm.s.pfnR3ShwModifyPage = pModeData->pfnR3ShwModifyPage;
3543
3544	pVCpu->pgm.s.pfnRCShwGetPage = pModeData->pfnRCShwGetPage;
3545	pVCpu->pgm.s.pfnRCShwModifyPage = pModeData->pfnRCShwModifyPage;
3546
3547	pVCpu->pgm.s.pfnR0ShwGetPage = pModeData->pfnR0ShwGetPage;
3548	pVCpu->pgm.s.pfnR0ShwModifyPage = pModeData->pfnR0ShwModifyPage;
3549
3550
3551	/* guest */
3552	pVCpu->pgm.s.pfnR3GstRelocate = pModeData->pfnR3GstRelocate;
3553	pVCpu->pgm.s.pfnR3GstExit = pModeData->pfnR3GstExit;
3554	pVCpu->pgm.s.pfnR3GstGetPage = pModeData->pfnR3GstGetPage;
3555	Assert(pVCpu->pgm.s.pfnR3GstGetPage);
3556	pVCpu->pgm.s.pfnR3GstModifyPage = pModeData->pfnR3GstModifyPage;
3557	pVCpu->pgm.s.pfnR3GstGetPDE = pModeData->pfnR3GstGetPDE;
3558	pVCpu->pgm.s.pfnRCGstGetPage = pModeData->pfnRCGstGetPage;
3559	pVCpu->pgm.s.pfnRCGstModifyPage = pModeData->pfnRCGstModifyPage;
3560	pVCpu->pgm.s.pfnRCGstGetPDE = pModeData->pfnRCGstGetPDE;
3561	pVCpu->pgm.s.pfnR0GstGetPage = pModeData->pfnR0GstGetPage;
3562	pVCpu->pgm.s.pfnR0GstModifyPage = pModeData->pfnR0GstModifyPage;
3563	pVCpu->pgm.s.pfnR0GstGetPDE = pModeData->pfnR0GstGetPDE;
3564
3565	/* both */
3566	pVCpu->pgm.s.pfnR3BthRelocate = pModeData->pfnR3BthRelocate;
3567	pVCpu->pgm.s.pfnR3BthInvalidatePage = pModeData->pfnR3BthInvalidatePage;
3568	pVCpu->pgm.s.pfnR3BthSyncCR3 = pModeData->pfnR3BthSyncCR3;
3569	Assert(pVCpu->pgm.s.pfnR3BthSyncCR3);
3570	pVCpu->pgm.s.pfnR3BthSyncPage = pModeData->pfnR3BthSyncPage;
3571	pVCpu->pgm.s.pfnR3BthPrefetchPage = pModeData->pfnR3BthPrefetchPage;
3572	pVCpu->pgm.s.pfnR3BthVerifyAccessSyncPage = pModeData->pfnR3BthVerifyAccessSyncPage;
3573	#ifdef VBOX_STRICT
3574	pVCpu->pgm.s.pfnR3BthAssertCR3 = pModeData->pfnR3BthAssertCR3;
3575	#endif
3576	pVCpu->pgm.s.pfnR3BthMapCR3 = pModeData->pfnR3BthMapCR3;
3577	pVCpu->pgm.s.pfnR3BthUnmapCR3 = pModeData->pfnR3BthUnmapCR3;
3578
3579	pVCpu->pgm.s.pfnRCBthTrap0eHandler = pModeData->pfnRCBthTrap0eHandler;
3580	pVCpu->pgm.s.pfnRCBthInvalidatePage = pModeData->pfnRCBthInvalidatePage;
3581	pVCpu->pgm.s.pfnRCBthSyncCR3 = pModeData->pfnRCBthSyncCR3;
3582	pVCpu->pgm.s.pfnRCBthSyncPage = pModeData->pfnRCBthSyncPage;
3583	pVCpu->pgm.s.pfnRCBthPrefetchPage = pModeData->pfnRCBthPrefetchPage;
3584	pVCpu->pgm.s.pfnRCBthVerifyAccessSyncPage = pModeData->pfnRCBthVerifyAccessSyncPage;
3585	#ifdef VBOX_STRICT
3586	pVCpu->pgm.s.pfnRCBthAssertCR3 = pModeData->pfnRCBthAssertCR3;
3587	#endif
3588	pVCpu->pgm.s.pfnRCBthMapCR3 = pModeData->pfnRCBthMapCR3;
3589	pVCpu->pgm.s.pfnRCBthUnmapCR3 = pModeData->pfnRCBthUnmapCR3;
3590
3591	pVCpu->pgm.s.pfnR0BthTrap0eHandler = pModeData->pfnR0BthTrap0eHandler;
3592	pVCpu->pgm.s.pfnR0BthInvalidatePage = pModeData->pfnR0BthInvalidatePage;
3593	pVCpu->pgm.s.pfnR0BthSyncCR3 = pModeData->pfnR0BthSyncCR3;
3594	pVCpu->pgm.s.pfnR0BthSyncPage = pModeData->pfnR0BthSyncPage;
3595	pVCpu->pgm.s.pfnR0BthPrefetchPage = pModeData->pfnR0BthPrefetchPage;
3596	pVCpu->pgm.s.pfnR0BthVerifyAccessSyncPage = pModeData->pfnR0BthVerifyAccessSyncPage;
3597	#ifdef VBOX_STRICT
3598	pVCpu->pgm.s.pfnR0BthAssertCR3 = pModeData->pfnR0BthAssertCR3;
3599	#endif
3600	pVCpu->pgm.s.pfnR0BthMapCR3 = pModeData->pfnR0BthMapCR3;
3601	pVCpu->pgm.s.pfnR0BthUnmapCR3 = pModeData->pfnR0BthUnmapCR3;
3602	}
3603
3604
3605	/**
3606	* Calculates the shadow paging mode.
3607	*
3608	* @returns The shadow paging mode.
3609	* @param pVM VM handle.
3610	* @param enmGuestMode The guest mode.
3611	* @param enmHostMode The host mode.
3612	* @param enmShadowMode The current shadow mode.
3613	* @param penmSwitcher Where to store the switcher to use.
3614	* VMMSWITCHER_INVALID means no change.
3615	*/
3616	static PGMMODE pgmR3CalcShadowMode(PVM pVM, PGMMODE enmGuestMode, SUPPAGINGMODE enmHostMode, PGMMODE enmShadowMode, VMMSWITCHER *penmSwitcher)
3617	{
3618	VMMSWITCHER enmSwitcher = VMMSWITCHER_INVALID;
3619	switch (enmGuestMode)
3620	{
3621	/*
3622	* When switching to real or protected mode we don't change
3623	* anything since it's likely that we'll switch back pretty soon.
3624	*
3625	* During pgmR3InitPaging we'll end up here with PGMMODE_INVALID
3626	* and is supposed to determine which shadow paging and switcher to
3627	* use during init.
3628	*/
3629	case PGMMODE_REAL:
3630	case PGMMODE_PROTECTED:
3631	if ( enmShadowMode != PGMMODE_INVALID
3632	&& !HWACCMIsEnabled(pVM) /* always switch in hwaccm mode! */)
3633	break; /* (no change) */
3634
3635	switch (enmHostMode)
3636	{
3637	case SUPPAGINGMODE_32_BIT:
3638	case SUPPAGINGMODE_32_BIT_GLOBAL:
3639	enmShadowMode = PGMMODE_32_BIT;
3640	enmSwitcher = VMMSWITCHER_32_TO_32;
3641	break;
3642
3643	case SUPPAGINGMODE_PAE:
3644	case SUPPAGINGMODE_PAE_NX:
3645	case SUPPAGINGMODE_PAE_GLOBAL:
3646	case SUPPAGINGMODE_PAE_GLOBAL_NX:
3647	enmShadowMode = PGMMODE_PAE;
3648	enmSwitcher = VMMSWITCHER_PAE_TO_PAE;
3649	#ifdef DEBUG_bird
3650	if (RTEnvExist("VBOX_32BIT"))
3651	{
3652	enmShadowMode = PGMMODE_32_BIT;
3653	enmSwitcher = VMMSWITCHER_PAE_TO_32;
3654	}
3655	#endif
3656	break;
3657
3658	case SUPPAGINGMODE_AMD64:
3659	case SUPPAGINGMODE_AMD64_GLOBAL:
3660	case SUPPAGINGMODE_AMD64_NX:
3661	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
3662	enmShadowMode = PGMMODE_PAE;
3663	enmSwitcher = VMMSWITCHER_AMD64_TO_PAE;
3664	#ifdef DEBUG_bird
3665	if (RTEnvExist("VBOX_32BIT"))
3666	{
3667	enmShadowMode = PGMMODE_32_BIT;
3668	enmSwitcher = VMMSWITCHER_AMD64_TO_32;
3669	}
3670	#endif
3671	break;
3672
3673	default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
3674	}
3675	break;
3676
3677	case PGMMODE_32_BIT:
3678	switch (enmHostMode)
3679	{
3680	case SUPPAGINGMODE_32_BIT:
3681	case SUPPAGINGMODE_32_BIT_GLOBAL:
3682	enmShadowMode = PGMMODE_32_BIT;
3683	enmSwitcher = VMMSWITCHER_32_TO_32;
3684	break;
3685
3686	case SUPPAGINGMODE_PAE:
3687	case SUPPAGINGMODE_PAE_NX:
3688	case SUPPAGINGMODE_PAE_GLOBAL:
3689	case SUPPAGINGMODE_PAE_GLOBAL_NX:
3690	enmShadowMode = PGMMODE_PAE;
3691	enmSwitcher = VMMSWITCHER_PAE_TO_PAE;
3692	#ifdef DEBUG_bird
3693	if (RTEnvExist("VBOX_32BIT"))
3694	{
3695	enmShadowMode = PGMMODE_32_BIT;
3696	enmSwitcher = VMMSWITCHER_PAE_TO_32;
3697	}
3698	#endif
3699	break;
3700
3701	case SUPPAGINGMODE_AMD64:
3702	case SUPPAGINGMODE_AMD64_GLOBAL:
3703	case SUPPAGINGMODE_AMD64_NX:
3704	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
3705	enmShadowMode = PGMMODE_PAE;
3706	enmSwitcher = VMMSWITCHER_AMD64_TO_PAE;
3707	#ifdef DEBUG_bird
3708	if (RTEnvExist("VBOX_32BIT"))
3709	{
3710	enmShadowMode = PGMMODE_32_BIT;
3711	enmSwitcher = VMMSWITCHER_AMD64_TO_32;
3712	}
3713	#endif
3714	break;
3715
3716	default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
3717	}
3718	break;
3719
3720	case PGMMODE_PAE:
3721	case PGMMODE_PAE_NX: /** @todo This might require more switchers and guest+both modes. */
3722	switch (enmHostMode)
3723	{
3724	case SUPPAGINGMODE_32_BIT:
3725	case SUPPAGINGMODE_32_BIT_GLOBAL:
3726	enmShadowMode = PGMMODE_PAE;
3727	enmSwitcher = VMMSWITCHER_32_TO_PAE;
3728	break;
3729
3730	case SUPPAGINGMODE_PAE:
3731	case SUPPAGINGMODE_PAE_NX:
3732	case SUPPAGINGMODE_PAE_GLOBAL:
3733	case SUPPAGINGMODE_PAE_GLOBAL_NX:
3734	enmShadowMode = PGMMODE_PAE;
3735	enmSwitcher = VMMSWITCHER_PAE_TO_PAE;
3736	break;
3737
3738	case SUPPAGINGMODE_AMD64:
3739	case SUPPAGINGMODE_AMD64_GLOBAL:
3740	case SUPPAGINGMODE_AMD64_NX:
3741	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
3742	enmShadowMode = PGMMODE_PAE;
3743	enmSwitcher = VMMSWITCHER_AMD64_TO_PAE;
3744	break;
3745
3746	default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
3747	}
3748	break;
3749
3750	case PGMMODE_AMD64:
3751	case PGMMODE_AMD64_NX:
3752	switch (enmHostMode)
3753	{
3754	case SUPPAGINGMODE_32_BIT:
3755	case SUPPAGINGMODE_32_BIT_GLOBAL:
3756	enmShadowMode = PGMMODE_AMD64;
3757	enmSwitcher = VMMSWITCHER_32_TO_AMD64;
3758	break;
3759
3760	case SUPPAGINGMODE_PAE:
3761	case SUPPAGINGMODE_PAE_NX:
3762	case SUPPAGINGMODE_PAE_GLOBAL:
3763	case SUPPAGINGMODE_PAE_GLOBAL_NX:
3764	enmShadowMode = PGMMODE_AMD64;
3765	enmSwitcher = VMMSWITCHER_PAE_TO_AMD64;
3766	break;
3767
3768	case SUPPAGINGMODE_AMD64:
3769	case SUPPAGINGMODE_AMD64_GLOBAL:
3770	case SUPPAGINGMODE_AMD64_NX:
3771	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
3772	enmShadowMode = PGMMODE_AMD64;
3773	enmSwitcher = VMMSWITCHER_AMD64_TO_AMD64;
3774	break;
3775
3776	default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
3777	}
3778	break;
3779
3780
3781	default:
3782	AssertReleaseMsgFailed(("enmGuestMode=%d\n", enmGuestMode));
3783	return PGMMODE_INVALID;
3784	}
3785	/* Override the shadow mode is nested paging is active. */
3786	if (HWACCMIsNestedPagingActive(pVM))
3787	enmShadowMode = HWACCMGetShwPagingMode(pVM);
3788
3789	*penmSwitcher = enmSwitcher;
3790	return enmShadowMode;
3791	}
3792
3793
3794	/**
3795	* Performs the actual mode change.
3796	* This is called by PGMChangeMode and pgmR3InitPaging().
3797	*
3798	* @returns VBox status code. May suspend or power off the VM on error, but this
3799	* will trigger using FFs and not status codes.
3800	*
3801	* @param pVM VM handle.
3802	* @param pVCpu The VMCPU to operate on.
3803	* @param enmGuestMode The new guest mode. This is assumed to be different from
3804	* the current mode.
3805	*/
3806	VMMR3DECL(int) PGMR3ChangeMode(PVM pVM, PVMCPU pVCpu, PGMMODE enmGuestMode)
3807	{
3808	Log(("PGMR3ChangeMode: Guest mode: %s -> %s\n", PGMGetModeName(pVCpu->pgm.s.enmGuestMode), PGMGetModeName(enmGuestMode)));
3809	STAM_REL_COUNTER_INC(&pVCpu->pgm.s.cGuestModeChanges);
3810
3811	/*
3812	* Calc the shadow mode and switcher.
3813	*/
3814	VMMSWITCHER enmSwitcher;
3815	PGMMODE enmShadowMode = pgmR3CalcShadowMode(pVM, enmGuestMode, pVM->pgm.s.enmHostMode, pVCpu->pgm.s.enmShadowMode, &enmSwitcher);
3816	if (enmSwitcher != VMMSWITCHER_INVALID)
3817	{
3818	/*
3819	* Select new switcher.
3820	*/
3821	int rc = VMMR3SelectSwitcher(pVM, enmSwitcher);
3822	if (RT_FAILURE(rc))
3823	{
3824	AssertReleaseMsgFailed(("VMMR3SelectSwitcher(%d) -> %Rrc\n", enmSwitcher, rc));
3825	return rc;
3826	}
3827	}
3828
3829	/*
3830	* Exit old mode(s).
3831	*/
3832	/* shadow */
3833	if (enmShadowMode != pVCpu->pgm.s.enmShadowMode)
3834	{
3835	LogFlow(("PGMR3ChangeMode: Shadow mode: %s -> %s\n", PGMGetModeName(pVCpu->pgm.s.enmShadowMode), PGMGetModeName(enmShadowMode)));
3836	if (PGM_SHW_PFN(Exit, pVCpu))
3837	{
3838	int rc = PGM_SHW_PFN(Exit, pVCpu)(pVCpu);
3839	if (RT_FAILURE(rc))
3840	{
3841	AssertMsgFailed(("Exit failed for shadow mode %d: %Rrc\n", pVCpu->pgm.s.enmShadowMode, rc));
3842	return rc;
3843	}
3844	}
3845
3846	}
3847	else
3848	LogFlow(("PGMR3ChangeMode: Shadow mode remains: %s\n", PGMGetModeName(pVCpu->pgm.s.enmShadowMode)));
3849
3850	/* guest */
3851	if (PGM_GST_PFN(Exit, pVCpu))
3852	{
3853	int rc = PGM_GST_PFN(Exit, pVCpu)(pVCpu);
3854	if (RT_FAILURE(rc))
3855	{
3856	AssertMsgFailed(("Exit failed for guest mode %d: %Rrc\n", pVCpu->pgm.s.enmGuestMode, rc));
3857	return rc;
3858	}
3859	}
3860
3861	/*
3862	* Load new paging mode data.
3863	*/
3864	pgmR3ModeDataSwitch(pVM, pVCpu, enmShadowMode, enmGuestMode);
3865
3866	/*
3867	* Enter new shadow mode (if changed).
3868	*/
3869	if (enmShadowMode != pVCpu->pgm.s.enmShadowMode)
3870	{
3871	int rc;
3872	pVCpu->pgm.s.enmShadowMode = enmShadowMode;
3873	switch (enmShadowMode)
3874	{
3875	case PGMMODE_32_BIT:
3876	rc = PGM_SHW_NAME_32BIT(Enter)(pVCpu);
3877	break;
3878	case PGMMODE_PAE:
3879	case PGMMODE_PAE_NX:
3880	rc = PGM_SHW_NAME_PAE(Enter)(pVCpu);
3881	break;
3882	case PGMMODE_AMD64:
3883	case PGMMODE_AMD64_NX:
3884	rc = PGM_SHW_NAME_AMD64(Enter)(pVCpu);
3885	break;
3886	case PGMMODE_NESTED:
3887	rc = PGM_SHW_NAME_NESTED(Enter)(pVCpu);
3888	break;
3889	case PGMMODE_EPT:
3890	rc = PGM_SHW_NAME_EPT(Enter)(pVCpu);
3891	break;
3892	case PGMMODE_REAL:
3893	case PGMMODE_PROTECTED:
3894	default:
3895	AssertReleaseMsgFailed(("enmShadowMode=%d\n", enmShadowMode));
3896	return VERR_INTERNAL_ERROR;
3897	}
3898	if (RT_FAILURE(rc))
3899	{
3900	AssertReleaseMsgFailed(("Entering enmShadowMode=%d failed: %Rrc\n", enmShadowMode, rc));
3901	pVCpu->pgm.s.enmShadowMode = PGMMODE_INVALID;
3902	return rc;
3903	}
3904	}
3905
3906	/*
3907	* Always flag the necessary updates
3908	*/
3909	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
3910
3911	/*
3912	* Enter the new guest and shadow+guest modes.
3913	*/
3914	int rc = -1;
3915	int rc2 = -1;
3916	RTGCPHYS GCPhysCR3 = NIL_RTGCPHYS;
3917	pVCpu->pgm.s.enmGuestMode = enmGuestMode;
3918	switch (enmGuestMode)
3919	{
3920	case PGMMODE_REAL:
3921	rc = PGM_GST_NAME_REAL(Enter)(pVCpu, NIL_RTGCPHYS);
3922	switch (pVCpu->pgm.s.enmShadowMode)
3923	{
3924	case PGMMODE_32_BIT:
3925	rc2 = PGM_BTH_NAME_32BIT_REAL(Enter)(pVCpu, NIL_RTGCPHYS);
3926	break;
3927	case PGMMODE_PAE:
3928	case PGMMODE_PAE_NX:
3929	rc2 = PGM_BTH_NAME_PAE_REAL(Enter)(pVCpu, NIL_RTGCPHYS);
3930	break;
3931	case PGMMODE_NESTED:
3932	rc2 = PGM_BTH_NAME_NESTED_REAL(Enter)(pVCpu, NIL_RTGCPHYS);
3933	break;
3934	case PGMMODE_EPT:
3935	rc2 = PGM_BTH_NAME_EPT_REAL(Enter)(pVCpu, NIL_RTGCPHYS);
3936	break;
3937	case PGMMODE_AMD64:
3938	case PGMMODE_AMD64_NX:
3939	AssertMsgFailed(("Should use PAE shadow mode!\n"));
3940	default: AssertFailed(); break;
3941	}
3942	break;
3943
3944	case PGMMODE_PROTECTED:
3945	rc = PGM_GST_NAME_PROT(Enter)(pVCpu, NIL_RTGCPHYS);
3946	switch (pVCpu->pgm.s.enmShadowMode)
3947	{
3948	case PGMMODE_32_BIT:
3949	rc2 = PGM_BTH_NAME_32BIT_PROT(Enter)(pVCpu, NIL_RTGCPHYS);
3950	break;
3951	case PGMMODE_PAE:
3952	case PGMMODE_PAE_NX:
3953	rc2 = PGM_BTH_NAME_PAE_PROT(Enter)(pVCpu, NIL_RTGCPHYS);
3954	break;
3955	case PGMMODE_NESTED:
3956	rc2 = PGM_BTH_NAME_NESTED_PROT(Enter)(pVCpu, NIL_RTGCPHYS);
3957	break;
3958	case PGMMODE_EPT:
3959	rc2 = PGM_BTH_NAME_EPT_PROT(Enter)(pVCpu, NIL_RTGCPHYS);
3960	break;
3961	case PGMMODE_AMD64:
3962	case PGMMODE_AMD64_NX:
3963	AssertMsgFailed(("Should use PAE shadow mode!\n"));
3964	default: AssertFailed(); break;
3965	}
3966	break;
3967
3968	case PGMMODE_32_BIT:
3969	GCPhysCR3 = CPUMGetGuestCR3(pVCpu) & X86_CR3_PAGE_MASK;
3970	rc = PGM_GST_NAME_32BIT(Enter)(pVCpu, GCPhysCR3);
3971	switch (pVCpu->pgm.s.enmShadowMode)
3972	{
3973	case PGMMODE_32_BIT:
3974	rc2 = PGM_BTH_NAME_32BIT_32BIT(Enter)(pVCpu, GCPhysCR3);
3975	break;
3976	case PGMMODE_PAE:
3977	case PGMMODE_PAE_NX:
3978	rc2 = PGM_BTH_NAME_PAE_32BIT(Enter)(pVCpu, GCPhysCR3);
3979	break;
3980	case PGMMODE_NESTED:
3981	rc2 = PGM_BTH_NAME_NESTED_32BIT(Enter)(pVCpu, GCPhysCR3);
3982	break;
3983	case PGMMODE_EPT:
3984	rc2 = PGM_BTH_NAME_EPT_32BIT(Enter)(pVCpu, GCPhysCR3);
3985	break;
3986	case PGMMODE_AMD64:
3987	case PGMMODE_AMD64_NX:
3988	AssertMsgFailed(("Should use PAE shadow mode!\n"));
3989	default: AssertFailed(); break;
3990	}
3991	break;
3992
3993	case PGMMODE_PAE_NX:
3994	case PGMMODE_PAE:
3995	{
3996	uint32_t u32Dummy, u32Features;
3997
3998	CPUMGetGuestCpuId(pVCpu, 1, &u32Dummy, &u32Dummy, &u32Dummy, &u32Features);
3999	if (!(u32Features & X86_CPUID_FEATURE_EDX_PAE))
4000	return VMSetRuntimeError(pVM, VMSETRTERR_FLAGS_FATAL, "PAEmode",
4001	N_("The guest is trying to switch to the PAE mode which is currently disabled by default in VirtualBox. PAE support can be enabled using the VM settings (General/Advanced)"));
4002
4003	GCPhysCR3 = CPUMGetGuestCR3(pVCpu) & X86_CR3_PAE_PAGE_MASK;
4004	rc = PGM_GST_NAME_PAE(Enter)(pVCpu, GCPhysCR3);
4005	switch (pVCpu->pgm.s.enmShadowMode)
4006	{
4007	case PGMMODE_PAE:
4008	case PGMMODE_PAE_NX:
4009	rc2 = PGM_BTH_NAME_PAE_PAE(Enter)(pVCpu, GCPhysCR3);
4010	break;
4011	case PGMMODE_NESTED:
4012	rc2 = PGM_BTH_NAME_NESTED_PAE(Enter)(pVCpu, GCPhysCR3);
4013	break;
4014	case PGMMODE_EPT:
4015	rc2 = PGM_BTH_NAME_EPT_PAE(Enter)(pVCpu, GCPhysCR3);
4016	break;
4017	case PGMMODE_32_BIT:
4018	case PGMMODE_AMD64:
4019	case PGMMODE_AMD64_NX:
4020	AssertMsgFailed(("Should use PAE shadow mode!\n"));
4021	default: AssertFailed(); break;
4022	}
4023	break;
4024	}
4025
4026	#ifdef VBOX_WITH_64_BITS_GUESTS
4027	case PGMMODE_AMD64_NX:
4028	case PGMMODE_AMD64:
4029	GCPhysCR3 = CPUMGetGuestCR3(pVCpu) & UINT64_C(0xfffffffffffff000); /** @todo define this mask! */
4030	rc = PGM_GST_NAME_AMD64(Enter)(pVCpu, GCPhysCR3);
4031	switch (pVCpu->pgm.s.enmShadowMode)
4032	{
4033	case PGMMODE_AMD64:
4034	case PGMMODE_AMD64_NX:
4035	rc2 = PGM_BTH_NAME_AMD64_AMD64(Enter)(pVCpu, GCPhysCR3);
4036	break;
4037	case PGMMODE_NESTED:
4038	rc2 = PGM_BTH_NAME_NESTED_AMD64(Enter)(pVCpu, GCPhysCR3);
4039	break;
4040	case PGMMODE_EPT:
4041	rc2 = PGM_BTH_NAME_EPT_AMD64(Enter)(pVCpu, GCPhysCR3);
4042	break;
4043	case PGMMODE_32_BIT:
4044	case PGMMODE_PAE:
4045	case PGMMODE_PAE_NX:
4046	AssertMsgFailed(("Should use AMD64 shadow mode!\n"));
4047	default: AssertFailed(); break;
4048	}
4049	break;
4050	#endif
4051
4052	default:
4053	AssertReleaseMsgFailed(("enmGuestMode=%d\n", enmGuestMode));
4054	rc = VERR_NOT_IMPLEMENTED;
4055	break;
4056	}
4057
4058	/* status codes. */
4059	AssertRC(rc);
4060	AssertRC(rc2);
4061	if (RT_SUCCESS(rc))
4062	{
4063	rc = rc2;
4064	if (RT_SUCCESS(rc)) /* no informational status codes. */
4065	rc = VINF_SUCCESS;
4066	}
4067
4068	/* Notify HWACCM as well. */
4069	HWACCMR3PagingModeChanged(pVM, pVCpu, pVCpu->pgm.s.enmShadowMode, pVCpu->pgm.s.enmGuestMode);
4070	return rc;
4071	}
4072
4073	/**
4074	* Release the pgm lock if owned by the current VCPU
4075	*
4076	* @param pVM The VM to operate on.
4077	*/
4078	VMMR3DECL(void) PGMR3ReleaseOwnedLocks(PVM pVM)
4079	{
4080	while (PDMCritSectIsOwner(&pVM->pgm.s.CritSect))
4081	PDMCritSectLeave(&pVM->pgm.s.CritSect);
4082	}
4083
4084	/**
4085	* Called by pgmPoolFlushAllInt prior to flushing the pool.
4086	*
4087	* @returns VBox status code, fully asserted.
4088	* @param pVM The VM handle.
4089	* @param pVCpu The VMCPU to operate on.
4090	*/
4091	int pgmR3ExitShadowModeBeforePoolFlush(PVM pVM, PVMCPU pVCpu)
4092	{
4093	/* Unmap the old CR3 value before flushing everything. */
4094	int rc = PGM_BTH_PFN(UnmapCR3, pVCpu)(pVCpu);
4095	AssertRC(rc);
4096
4097	/* Exit the current shadow paging mode as well; nested paging and EPT use a root CR3 which will get flushed here. */
4098	rc = PGM_SHW_PFN(Exit, pVCpu)(pVCpu);
4099	AssertRC(rc);
4100	Assert(pVCpu->pgm.s.pShwPageCR3R3 == NULL);
4101	return rc;
4102	}
4103
4104
4105	/**
4106	* Called by pgmPoolFlushAllInt after flushing the pool.
4107	*
4108	* @returns VBox status code, fully asserted.
4109	* @param pVM The VM handle.
4110	* @param pVCpu The VMCPU to operate on.
4111	*/
4112	int pgmR3ReEnterShadowModeAfterPoolFlush(PVM pVM, PVMCPU pVCpu)
4113	{
4114	pVCpu->pgm.s.enmShadowMode = PGMMODE_INVALID;
4115	int rc = PGMR3ChangeMode(pVM, pVCpu, PGMGetGuestMode(pVCpu));
4116	Assert(VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
4117	AssertRCReturn(rc, rc);
4118	AssertRCSuccessReturn(rc, VERR_IPE_UNEXPECTED_INFO_STATUS);
4119
4120	Assert(pVCpu->pgm.s.pShwPageCR3R3 != NULL);
4121	AssertMsg( pVCpu->pgm.s.enmShadowMode >= PGMMODE_NESTED
4122	\|\| CPUMGetHyperCR3(pVCpu) == PGMGetHyperCR3(pVCpu),
4123	("%RHp != %RHp %s\n", (RTHCPHYS)CPUMGetHyperCR3(pVCpu), PGMGetHyperCR3(pVCpu), PGMGetModeName(pVCpu->pgm.s.enmShadowMode)));
4124	return rc;
4125	}
4126
4127
4128	/**
4129	* Dumps a PAE shadow page table.
4130	*
4131	* @returns VBox status code (VINF_SUCCESS).
4132	* @param pVM The VM handle.
4133	* @param pPT Pointer to the page table.
4134	* @param u64Address The virtual address of the page table starts.
4135	* @param fLongMode Set if this a long mode table; clear if it's a legacy mode table.
4136	* @param cMaxDepth The maxium depth.
4137	* @param pHlp Pointer to the output functions.
4138	*/
4139	static int pgmR3DumpHierarchyHCPaePT(PVM pVM, PX86PTPAE pPT, uint64_t u64Address, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
4140	{
4141	for (unsigned i = 0; i < RT_ELEMENTS(pPT->a); i++)
4142	{
4143	X86PTEPAE Pte = pPT->a[i];
4144	if (Pte.n.u1Present)
4145	{
4146	pHlp->pfnPrintf(pHlp,
4147	fLongMode /P R S A D G WT CD AT NX 4M a p ? /
4148	? "%016llx 3 \| P %c %c %c %c %c %s %s %s %s 4K %c%c%c %016llx\n"
4149	: "%08llx 2 \| P %c %c %c %c %c %s %s %s %s 4K %c%c%c %016llx\n",
4150	u64Address + ((uint64_t)i << X86_PT_PAE_SHIFT),
4151	Pte.n.u1Write ? 'W' : 'R',
4152	Pte.n.u1User ? 'U' : 'S',
4153	Pte.n.u1Accessed ? 'A' : '-',
4154	Pte.n.u1Dirty ? 'D' : '-',
4155	Pte.n.u1Global ? 'G' : '-',
4156	Pte.n.u1WriteThru ? "WT" : "--",
4157	Pte.n.u1CacheDisable? "CD" : "--",
4158	Pte.n.u1PAT ? "AT" : "--",
4159	Pte.n.u1NoExecute ? "NX" : "--",
4160	Pte.u & PGM_PTFLAGS_TRACK_DIRTY ? 'd' : '-',
4161	Pte.u & RT_BIT(10) ? '1' : '0',
4162	Pte.u & PGM_PTFLAGS_CSAM_VALIDATED? 'v' : '-',
4163	Pte.u & X86_PTE_PAE_PG_MASK);
4164	}
4165	}
4166	return VINF_SUCCESS;
4167	}
4168
4169
4170	/**
4171	* Dumps a PAE shadow page directory table.
4172	*
4173	* @returns VBox status code (VINF_SUCCESS).
4174	* @param pVM The VM handle.
4175	* @param HCPhys The physical address of the page directory table.
4176	* @param u64Address The virtual address of the page table starts.
4177	* @param cr4 The CR4, PSE is currently used.
4178	* @param fLongMode Set if this a long mode table; clear if it's a legacy mode table.
4179	* @param cMaxDepth The maxium depth.
4180	* @param pHlp Pointer to the output functions.
4181	*/
4182	static int pgmR3DumpHierarchyHCPaePD(PVM pVM, RTHCPHYS HCPhys, uint64_t u64Address, uint32_t cr4, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
4183	{
4184	PX86PDPAE pPD = (PX86PDPAE)MMPagePhys2Page(pVM, HCPhys);
4185	if (!pPD)
4186	{
4187	pHlp->pfnPrintf(pHlp, "%0*llx error! Page directory at HCPhys=%RHp was not found in the page pool!\n",
4188	fLongMode ? 16 : 8, u64Address, HCPhys);
4189	return VERR_INVALID_PARAMETER;
4190	}
4191	const bool fBigPagesSupported = fLongMode \|\| !!(cr4 & X86_CR4_PSE);
4192
4193	int rc = VINF_SUCCESS;
4194	for (unsigned i = 0; i < RT_ELEMENTS(pPD->a); i++)
4195	{
4196	X86PDEPAE Pde = pPD->a[i];
4197	if (Pde.n.u1Present)
4198	{
4199	if (fBigPagesSupported && Pde.b.u1Size)
4200	pHlp->pfnPrintf(pHlp,
4201	fLongMode /P R S A D G WT CD AT NX 4M a p ? /
4202	? "%016llx 2 \| P %c %c %c %c %c %s %s %s %s 4M %c%c%c %016llx\n"
4203	: "%08llx 1 \| P %c %c %c %c %c %s %s %s %s 4M %c%c%c %016llx\n",
4204	u64Address + ((uint64_t)i << X86_PD_PAE_SHIFT),
4205	Pde.b.u1Write ? 'W' : 'R',
4206	Pde.b.u1User ? 'U' : 'S',
4207	Pde.b.u1Accessed ? 'A' : '-',
4208	Pde.b.u1Dirty ? 'D' : '-',
4209	Pde.b.u1Global ? 'G' : '-',
4210	Pde.b.u1WriteThru ? "WT" : "--",
4211	Pde.b.u1CacheDisable? "CD" : "--",
4212	Pde.b.u1PAT ? "AT" : "--",
4213	Pde.b.u1NoExecute ? "NX" : "--",
4214	Pde.u & RT_BIT_64(9) ? '1' : '0',
4215	Pde.u & PGM_PDFLAGS_MAPPING ? 'm' : '-',
4216	Pde.u & PGM_PDFLAGS_TRACK_DIRTY ? 'd' : '-',
4217	Pde.u & X86_PDE_PAE_PG_MASK);
4218	else
4219	{
4220	pHlp->pfnPrintf(pHlp,
4221	fLongMode /P R S A D G WT CD AT NX 4M a p ? /
4222	? "%016llx 2 \| P %c %c %c %c %c %s %s .. %s 4K %c%c%c %016llx\n"
4223	: "%08llx 1 \| P %c %c %c %c %c %s %s .. %s 4K %c%c%c %016llx\n",
4224	u64Address + ((uint64_t)i << X86_PD_PAE_SHIFT),
4225	Pde.n.u1Write ? 'W' : 'R',
4226	Pde.n.u1User ? 'U' : 'S',
4227	Pde.n.u1Accessed ? 'A' : '-',
4228	Pde.n.u1Reserved0 ? '?' : '.', /* ignored */
4229	Pde.n.u1Reserved1 ? '?' : '.', /* ignored */
4230	Pde.n.u1WriteThru ? "WT" : "--",
4231	Pde.n.u1CacheDisable? "CD" : "--",
4232	Pde.n.u1NoExecute ? "NX" : "--",
4233	Pde.u & RT_BIT_64(9) ? '1' : '0',
4234	Pde.u & PGM_PDFLAGS_MAPPING ? 'm' : '-',
4235	Pde.u & PGM_PDFLAGS_TRACK_DIRTY ? 'd' : '-',
4236	Pde.u & X86_PDE_PAE_PG_MASK);
4237	if (cMaxDepth >= 1)
4238	{
4239	/** @todo what about using the page pool for mapping PTs? */
4240	uint64_t u64AddressPT = u64Address + ((uint64_t)i << X86_PD_PAE_SHIFT);
4241	RTHCPHYS HCPhysPT = Pde.u & X86_PDE_PAE_PG_MASK;
4242	PX86PTPAE pPT = NULL;
4243	if (!(Pde.u & PGM_PDFLAGS_MAPPING))
4244	pPT = (PX86PTPAE)MMPagePhys2Page(pVM, HCPhysPT);
4245	else
4246	{
4247	for (PPGMMAPPING pMap = pVM->pgm.s.pMappingsR3; pMap; pMap = pMap->pNextR3)
4248	{
4249	uint64_t off = u64AddressPT - pMap->GCPtr;
4250	if (off < pMap->cb)
4251	{
4252	const int iPDE = (uint32_t)(off >> X86_PD_SHIFT);
4253	const int iSub = (int)((off >> X86_PD_PAE_SHIFT) & 1); /* MSC is a pain sometimes */
4254	if ((iSub ? pMap->aPTs[iPDE].HCPhysPaePT1 : pMap->aPTs[iPDE].HCPhysPaePT0) != HCPhysPT)
4255	pHlp->pfnPrintf(pHlp, "%0*llx error! Mapping error! PT %d has HCPhysPT=%RHp not %RHp is in the PD.\n",
4256	fLongMode ? 16 : 8, u64AddressPT, iPDE,
4257	iSub ? pMap->aPTs[iPDE].HCPhysPaePT1 : pMap->aPTs[iPDE].HCPhysPaePT0, HCPhysPT);
4258	pPT = &pMap->aPTs[iPDE].paPaePTsR3[iSub];
4259	}
4260	}
4261	}
4262	int rc2 = VERR_INVALID_PARAMETER;
4263	if (pPT)
4264	rc2 = pgmR3DumpHierarchyHCPaePT(pVM, pPT, u64AddressPT, fLongMode, cMaxDepth - 1, pHlp);
4265	else
4266	pHlp->pfnPrintf(pHlp, "%0*llx error! Page table at HCPhys=%RHp was not found in the page pool!\n",
4267	fLongMode ? 16 : 8, u64AddressPT, HCPhysPT);
4268	if (rc2 < rc && RT_SUCCESS(rc))
4269	rc = rc2;
4270	}
4271	}
4272	}
4273	}
4274	return rc;
4275	}
4276
4277
4278	/**
4279	* Dumps a PAE shadow page directory pointer table.
4280	*
4281	* @returns VBox status code (VINF_SUCCESS).
4282	* @param pVM The VM handle.
4283	* @param HCPhys The physical address of the page directory pointer table.
4284	* @param u64Address The virtual address of the page table starts.
4285	* @param cr4 The CR4, PSE is currently used.
4286	* @param fLongMode Set if this a long mode table; clear if it's a legacy mode table.
4287	* @param cMaxDepth The maxium depth.
4288	* @param pHlp Pointer to the output functions.
4289	*/
4290	static int pgmR3DumpHierarchyHCPaePDPT(PVM pVM, RTHCPHYS HCPhys, uint64_t u64Address, uint32_t cr4, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
4291	{
4292	PX86PDPT pPDPT = (PX86PDPT)MMPagePhys2Page(pVM, HCPhys);
4293	if (!pPDPT)
4294	{
4295	pHlp->pfnPrintf(pHlp, "%0*llx error! Page directory pointer table at HCPhys=%RHp was not found in the page pool!\n",
4296	fLongMode ? 16 : 8, u64Address, HCPhys);
4297	return VERR_INVALID_PARAMETER;
4298	}
4299
4300	int rc = VINF_SUCCESS;
4301	const unsigned c = fLongMode ? RT_ELEMENTS(pPDPT->a) : X86_PG_PAE_PDPE_ENTRIES;
4302	for (unsigned i = 0; i < c; i++)
4303	{
4304	X86PDPE Pdpe = pPDPT->a[i];
4305	if (Pdpe.n.u1Present)
4306	{
4307	if (fLongMode)
4308	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a p ? /
4309	"%016llx 1 \| P %c %c %c %c %c %s %s %s %s .. %c%c%c %016llx\n",
4310	u64Address + ((uint64_t)i << X86_PDPT_SHIFT),
4311	Pdpe.lm.u1Write ? 'W' : 'R',
4312	Pdpe.lm.u1User ? 'U' : 'S',
4313	Pdpe.lm.u1Accessed ? 'A' : '-',
4314	Pdpe.lm.u3Reserved & 1? '?' : '.', /* ignored */
4315	Pdpe.lm.u3Reserved & 4? '!' : '.', /* mbz */
4316	Pdpe.lm.u1WriteThru ? "WT" : "--",
4317	Pdpe.lm.u1CacheDisable? "CD" : "--",
4318	Pdpe.lm.u3Reserved & 2? "!" : "..",/* mbz */
4319	Pdpe.lm.u1NoExecute ? "NX" : "--",
4320	Pdpe.u & RT_BIT(9) ? '1' : '0',
4321	Pdpe.u & PGM_PLXFLAGS_PERMANENT ? 'p' : '-',
4322	Pdpe.u & RT_BIT(11) ? '1' : '0',
4323	Pdpe.u & X86_PDPE_PG_MASK);
4324	else
4325	pHlp->pfnPrintf(pHlp, /P G WT CD AT NX 4M a p ? /
4326	"%08x 0 \| P %c %s %s %s %s .. %c%c%c %016llx\n",
4327	i << X86_PDPT_SHIFT,
4328	Pdpe.n.u4Reserved & 1? '!' : '.', /* mbz */
4329	Pdpe.n.u4Reserved & 4? '!' : '.', /* mbz */
4330	Pdpe.n.u1WriteThru ? "WT" : "--",
4331	Pdpe.n.u1CacheDisable? "CD" : "--",
4332	Pdpe.n.u4Reserved & 2? "!" : "..",/* mbz */
4333	Pdpe.u & RT_BIT(9) ? '1' : '0',
4334	Pdpe.u & PGM_PLXFLAGS_PERMANENT ? 'p' : '-',
4335	Pdpe.u & RT_BIT(11) ? '1' : '0',
4336	Pdpe.u & X86_PDPE_PG_MASK);
4337	if (cMaxDepth >= 1)
4338	{
4339	int rc2 = pgmR3DumpHierarchyHCPaePD(pVM, Pdpe.u & X86_PDPE_PG_MASK, u64Address + ((uint64_t)i << X86_PDPT_SHIFT),
4340	cr4, fLongMode, cMaxDepth - 1, pHlp);
4341	if (rc2 < rc && RT_SUCCESS(rc))
4342	rc = rc2;
4343	}
4344	}
4345	}
4346	return rc;
4347	}
4348
4349
4350	/**
4351	* Dumps a 32-bit shadow page table.
4352	*
4353	* @returns VBox status code (VINF_SUCCESS).
4354	* @param pVM The VM handle.
4355	* @param HCPhys The physical address of the table.
4356	* @param cr4 The CR4, PSE is currently used.
4357	* @param cMaxDepth The maxium depth.
4358	* @param pHlp Pointer to the output functions.
4359	*/
4360	static int pgmR3DumpHierarchyHcPaePML4(PVM pVM, RTHCPHYS HCPhys, uint32_t cr4, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
4361	{
4362	PX86PML4 pPML4 = (PX86PML4)MMPagePhys2Page(pVM, HCPhys);
4363	if (!pPML4)
4364	{
4365	pHlp->pfnPrintf(pHlp, "Page map level 4 at HCPhys=%RHp was not found in the page pool!\n", HCPhys);
4366	return VERR_INVALID_PARAMETER;
4367	}
4368
4369	int rc = VINF_SUCCESS;
4370	for (unsigned i = 0; i < RT_ELEMENTS(pPML4->a); i++)
4371	{
4372	X86PML4E Pml4e = pPML4->a[i];
4373	if (Pml4e.n.u1Present)
4374	{
4375	uint64_t u64Address = ((uint64_t)i << X86_PML4_SHIFT) \| (((uint64_t)i >> (X86_PML4_SHIFT - X86_PDPT_SHIFT - 1)) * 0xffff000000000000ULL);
4376	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a p ? /
4377	"%016llx 0 \| P %c %c %c %c %c %s %s %s %s .. %c%c%c %016llx\n",
4378	u64Address,
4379	Pml4e.n.u1Write ? 'W' : 'R',
4380	Pml4e.n.u1User ? 'U' : 'S',
4381	Pml4e.n.u1Accessed ? 'A' : '-',
4382	Pml4e.n.u3Reserved & 1? '?' : '.', /* ignored */
4383	Pml4e.n.u3Reserved & 4? '!' : '.', /* mbz */
4384	Pml4e.n.u1WriteThru ? "WT" : "--",
4385	Pml4e.n.u1CacheDisable? "CD" : "--",
4386	Pml4e.n.u3Reserved & 2? "!" : "..",/* mbz */
4387	Pml4e.n.u1NoExecute ? "NX" : "--",
4388	Pml4e.u & RT_BIT(9) ? '1' : '0',
4389	Pml4e.u & PGM_PLXFLAGS_PERMANENT ? 'p' : '-',
4390	Pml4e.u & RT_BIT(11) ? '1' : '0',
4391	Pml4e.u & X86_PML4E_PG_MASK);
4392
4393	if (cMaxDepth >= 1)
4394	{
4395	int rc2 = pgmR3DumpHierarchyHCPaePDPT(pVM, Pml4e.u & X86_PML4E_PG_MASK, u64Address, cr4, true, cMaxDepth - 1, pHlp);
4396	if (rc2 < rc && RT_SUCCESS(rc))
4397	rc = rc2;
4398	}
4399	}
4400	}
4401	return rc;
4402	}
4403
4404
4405	/**
4406	* Dumps a 32-bit shadow page table.
4407	*
4408	* @returns VBox status code (VINF_SUCCESS).
4409	* @param pVM The VM handle.
4410	* @param pPT Pointer to the page table.
4411	* @param u32Address The virtual address this table starts at.
4412	* @param pHlp Pointer to the output functions.
4413	*/
4414	int pgmR3DumpHierarchyHC32BitPT(PVM pVM, PX86PT pPT, uint32_t u32Address, PCDBGFINFOHLP pHlp)
4415	{
4416	for (unsigned i = 0; i < RT_ELEMENTS(pPT->a); i++)
4417	{
4418	X86PTE Pte = pPT->a[i];
4419	if (Pte.n.u1Present)
4420	{
4421	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a m d /
4422	"%08x 1 \| P %c %c %c %c %c %s %s %s .. 4K %c%c%c %08x\n",
4423	u32Address + (i << X86_PT_SHIFT),
4424	Pte.n.u1Write ? 'W' : 'R',
4425	Pte.n.u1User ? 'U' : 'S',
4426	Pte.n.u1Accessed ? 'A' : '-',
4427	Pte.n.u1Dirty ? 'D' : '-',
4428	Pte.n.u1Global ? 'G' : '-',
4429	Pte.n.u1WriteThru ? "WT" : "--",
4430	Pte.n.u1CacheDisable? "CD" : "--",
4431	Pte.n.u1PAT ? "AT" : "--",
4432	Pte.u & PGM_PTFLAGS_TRACK_DIRTY ? 'd' : '-',
4433	Pte.u & RT_BIT(10) ? '1' : '0',
4434	Pte.u & PGM_PTFLAGS_CSAM_VALIDATED ? 'v' : '-',
4435	Pte.u & X86_PDE_PG_MASK);
4436	}
4437	}
4438	return VINF_SUCCESS;
4439	}
4440
4441
4442	/**
4443	* Dumps a 32-bit shadow page directory and page tables.
4444	*
4445	* @returns VBox status code (VINF_SUCCESS).
4446	* @param pVM The VM handle.
4447	* @param cr3 The root of the hierarchy.
4448	* @param cr4 The CR4, PSE is currently used.
4449	* @param cMaxDepth How deep into the hierarchy the dumper should go.
4450	* @param pHlp Pointer to the output functions.
4451	*/
4452	int pgmR3DumpHierarchyHC32BitPD(PVM pVM, uint32_t cr3, uint32_t cr4, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
4453	{
4454	PX86PD pPD = (PX86PD)MMPagePhys2Page(pVM, cr3 & X86_CR3_PAGE_MASK);
4455	if (!pPD)
4456	{
4457	pHlp->pfnPrintf(pHlp, "Page directory at %#x was not found in the page pool!\n", cr3 & X86_CR3_PAGE_MASK);
4458	return VERR_INVALID_PARAMETER;
4459	}
4460
4461	int rc = VINF_SUCCESS;
4462	for (unsigned i = 0; i < RT_ELEMENTS(pPD->a); i++)
4463	{
4464	X86PDE Pde = pPD->a[i];
4465	if (Pde.n.u1Present)
4466	{
4467	const uint32_t u32Address = i << X86_PD_SHIFT;
4468	if ((cr4 & X86_CR4_PSE) && Pde.b.u1Size)
4469	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a m d /
4470	"%08x 0 \| P %c %c %c %c %c %s %s %s .. 4M %c%c%c %08x\n",
4471	u32Address,
4472	Pde.b.u1Write ? 'W' : 'R',
4473	Pde.b.u1User ? 'U' : 'S',
4474	Pde.b.u1Accessed ? 'A' : '-',
4475	Pde.b.u1Dirty ? 'D' : '-',
4476	Pde.b.u1Global ? 'G' : '-',
4477	Pde.b.u1WriteThru ? "WT" : "--",
4478	Pde.b.u1CacheDisable? "CD" : "--",
4479	Pde.b.u1PAT ? "AT" : "--",
4480	Pde.u & RT_BIT_64(9) ? '1' : '0',
4481	Pde.u & PGM_PDFLAGS_MAPPING ? 'm' : '-',
4482	Pde.u & PGM_PDFLAGS_TRACK_DIRTY ? 'd' : '-',
4483	Pde.u & X86_PDE4M_PG_MASK);
4484	else
4485	{
4486	pHlp->pfnPrintf(pHlp, /P R S A D G WT CD AT NX 4M a m d /
4487	"%08x 0 \| P %c %c %c %c %c %s %s .. .. 4K %c%c%c %08x\n",
4488	u32Address,
4489	Pde.n.u1Write ? 'W' : 'R',
4490	Pde.n.u1User ? 'U' : 'S',
4491	Pde.n.u1Accessed ? 'A' : '-',
4492	Pde.n.u1Reserved0 ? '?' : '.', /* ignored */
4493	Pde.n.u1Reserved1 ? '?' : '.', /* ignored */
4494	Pde.n.u1WriteThru ? "WT" : "--",
4495	Pde.n.u1CacheDisable? "CD" : "--",
4496	Pde.u & RT_BIT_64(9) ? '1' : '0',
4497	Pde.u & PGM_PDFLAGS_MAPPING ? 'm' : '-',
4498	Pde.u & PGM_PDFLAGS_TRACK_DIRTY ? 'd' : '-',
4499	Pde.u & X86_PDE_PG_MASK);
4500	if (cMaxDepth >= 1)
4501	{
4502	/** @todo what about using the page pool for mapping PTs? */
4503	RTHCPHYS HCPhys = Pde.u & X86_PDE_PG_MASK;
4504	PX86PT pPT = NULL;
4505	if (!(Pde.u & PGM_PDFLAGS_MAPPING))
4506	pPT = (PX86PT)MMPagePhys2Page(pVM, HCPhys);
4507	else
4508	{
4509	for (PPGMMAPPING pMap = pVM->pgm.s.pMappingsR3; pMap; pMap = pMap->pNextR3)
4510	if (u32Address - pMap->GCPtr < pMap->cb)
4511	{
4512	int iPDE = (u32Address - pMap->GCPtr) >> X86_PD_SHIFT;
4513	if (pMap->aPTs[iPDE].HCPhysPT != HCPhys)
4514	pHlp->pfnPrintf(pHlp, "%08x error! Mapping error! PT %d has HCPhysPT=%RHp not %RHp is in the PD.\n",
4515	u32Address, iPDE, pMap->aPTs[iPDE].HCPhysPT, HCPhys);
4516	pPT = pMap->aPTs[iPDE].pPTR3;
4517	}
4518	}
4519	int rc2 = VERR_INVALID_PARAMETER;
4520	if (pPT)
4521	rc2 = pgmR3DumpHierarchyHC32BitPT(pVM, pPT, u32Address, pHlp);
4522	else
4523	pHlp->pfnPrintf(pHlp, "%08x error! Page table at %#x was not found in the page pool!\n", u32Address, HCPhys);
4524	if (rc2 < rc && RT_SUCCESS(rc))
4525	rc = rc2;
4526	}
4527	}
4528	}
4529	}
4530
4531	return rc;
4532	}
4533
4534
4535	/**
4536	* Dumps a 32-bit shadow page table.
4537	*
4538	* @returns VBox status code (VINF_SUCCESS).
4539	* @param pVM The VM handle.
4540	* @param pPT Pointer to the page table.
4541	* @param u32Address The virtual address this table starts at.
4542	* @param PhysSearch Address to search for.
4543	*/
4544	int pgmR3DumpHierarchyGC32BitPT(PVM pVM, PX86PT pPT, uint32_t u32Address, RTGCPHYS PhysSearch)
4545	{
4546	for (unsigned i = 0; i < RT_ELEMENTS(pPT->a); i++)
4547	{
4548	X86PTE Pte = pPT->a[i];
4549	if (Pte.n.u1Present)
4550	{
4551	Log(( /P R S A D G WT CD AT NX 4M a m d /
4552	"%08x 1 \| P %c %c %c %c %c %s %s %s .. 4K %c%c%c %08x\n",
4553	u32Address + (i << X86_PT_SHIFT),
4554	Pte.n.u1Write ? 'W' : 'R',
4555	Pte.n.u1User ? 'U' : 'S',
4556	Pte.n.u1Accessed ? 'A' : '-',
4557	Pte.n.u1Dirty ? 'D' : '-',
4558	Pte.n.u1Global ? 'G' : '-',
4559	Pte.n.u1WriteThru ? "WT" : "--",
4560	Pte.n.u1CacheDisable? "CD" : "--",
4561	Pte.n.u1PAT ? "AT" : "--",
4562	Pte.u & PGM_PTFLAGS_TRACK_DIRTY ? 'd' : '-',
4563	Pte.u & RT_BIT(10) ? '1' : '0',
4564	Pte.u & PGM_PTFLAGS_CSAM_VALIDATED ? 'v' : '-',
4565	Pte.u & X86_PDE_PG_MASK));
4566
4567	if ((Pte.u & X86_PDE_PG_MASK) == PhysSearch)
4568	{
4569	uint64_t fPageShw = 0;
4570	RTHCPHYS pPhysHC = 0;
4571
4572	/** @todo SMP support!! */
4573	PGMShwGetPage(&pVM->aCpus[0], (RTGCPTR)(u32Address + (i << X86_PT_SHIFT)), &fPageShw, &pPhysHC);
4574	Log(("Found %RGp at %RGv -> flags=%llx\n", PhysSearch, (RTGCPTR)(u32Address + (i << X86_PT_SHIFT)), fPageShw));
4575	}
4576	}
4577	}
4578	return VINF_SUCCESS;
4579	}
4580
4581
4582	/**
4583	* Dumps a 32-bit guest page directory and page tables.
4584	*
4585	* @returns VBox status code (VINF_SUCCESS).
4586	* @param pVM The VM handle.
4587	* @param cr3 The root of the hierarchy.
4588	* @param cr4 The CR4, PSE is currently used.
4589	* @param PhysSearch Address to search for.
4590	*/
4591	VMMR3DECL(int) PGMR3DumpHierarchyGC(PVM pVM, uint64_t cr3, uint64_t cr4, RTGCPHYS PhysSearch)
4592	{
4593	bool fLongMode = false;
4594	const unsigned cch = fLongMode ? 16 : 8; NOREF(cch);
4595	PX86PD pPD = 0;
4596
4597	int rc = PGM_GCPHYS_2_PTR(pVM, cr3 & X86_CR3_PAGE_MASK, &pPD);
4598	if (RT_FAILURE(rc) \|\| !pPD)
4599	{
4600	Log(("Page directory at %#x was not found in the page pool!\n", cr3 & X86_CR3_PAGE_MASK));
4601	return VERR_INVALID_PARAMETER;
4602	}
4603
4604	Log(("cr3=%08x cr4=%08x%s\n"
4605	"%-*s P - Present\n"
4606	"%-*s \| R/W - Read (0) / Write (1)\n"
4607	"%-*s \| \| U/S - User (1) / Supervisor (0)\n"
4608	"%-*s \| \| \| A - Accessed\n"
4609	"%-*s \| \| \| \| D - Dirty\n"
4610	"%-*s \| \| \| \| \| G - Global\n"
4611	"%-*s \| \| \| \| \| \| WT - Write thru\n"
4612	"%-*s \| \| \| \| \| \| \| CD - Cache disable\n"
4613	"%-*s \| \| \| \| \| \| \| \| AT - Attribute table (PAT)\n"
4614	"%-*s \| \| \| \| \| \| \| \| \| NX - No execute (K8)\n"
4615	"%-*s \| \| \| \| \| \| \| \| \| \| 4K/4M/2M - Page size.\n"
4616	"%-*s \| \| \| \| \| \| \| \| \| \| \| AVL - a=allocated; m=mapping; d=track dirty;\n"
4617	"%-*s \| \| \| \| \| \| \| \| \| \| \| \| p=permanent; v=validated;\n"
4618	"%-*s Level \| \| \| \| \| \| \| \| \| \| \| \| Page\n"
4619	/* xxxx n **** P R S A D G WT CD AT NX 4M AVL xxxxxxxxxxxxx
4620	- W U - - - -- -- -- -- -- 010 */
4621	, cr3, cr4, fLongMode ? " Long Mode" : "",
4622	cch, "", cch, "", cch, "", cch, "", cch, "", cch, "", cch, "",
4623	cch, "", cch, "", cch, "", cch, "", cch, "", cch, "", cch, "Address"));
4624
4625	for (unsigned i = 0; i < RT_ELEMENTS(pPD->a); i++)
4626	{
4627	X86PDE Pde = pPD->a[i];
4628	if (Pde.n.u1Present)
4629	{
4630	const uint32_t u32Address = i << X86_PD_SHIFT;
4631
4632	if ((cr4 & X86_CR4_PSE) && Pde.b.u1Size)
4633	Log(( /P R S A D G WT CD AT NX 4M a m d /
4634	"%08x 0 \| P %c %c %c %c %c %s %s %s .. 4M %c%c%c %08x\n",
4635	u32Address,
4636	Pde.b.u1Write ? 'W' : 'R',
4637	Pde.b.u1User ? 'U' : 'S',
4638	Pde.b.u1Accessed ? 'A' : '-',
4639	Pde.b.u1Dirty ? 'D' : '-',
4640	Pde.b.u1Global ? 'G' : '-',
4641	Pde.b.u1WriteThru ? "WT" : "--",
4642	Pde.b.u1CacheDisable? "CD" : "--",
4643	Pde.b.u1PAT ? "AT" : "--",
4644	Pde.u & RT_BIT(9) ? '1' : '0',
4645	Pde.u & RT_BIT(10) ? '1' : '0',
4646	Pde.u & RT_BIT(11) ? '1' : '0',
4647	pgmGstGet4MBPhysPage(&pVM->pgm.s, Pde)));
4648	/** @todo PhysSearch */
4649	else
4650	{
4651	Log(( /P R S A D G WT CD AT NX 4M a m d /
4652	"%08x 0 \| P %c %c %c %c %c %s %s .. .. 4K %c%c%c %08x\n",
4653	u32Address,
4654	Pde.n.u1Write ? 'W' : 'R',
4655	Pde.n.u1User ? 'U' : 'S',
4656	Pde.n.u1Accessed ? 'A' : '-',
4657	Pde.n.u1Reserved0 ? '?' : '.', /* ignored */
4658	Pde.n.u1Reserved1 ? '?' : '.', /* ignored */
4659	Pde.n.u1WriteThru ? "WT" : "--",
4660	Pde.n.u1CacheDisable? "CD" : "--",
4661	Pde.u & RT_BIT(9) ? '1' : '0',
4662	Pde.u & RT_BIT(10) ? '1' : '0',
4663	Pde.u & RT_BIT(11) ? '1' : '0',
4664	Pde.u & X86_PDE_PG_MASK));
4665	////if (cMaxDepth >= 1)
4666	{
4667	/** @todo what about using the page pool for mapping PTs? */
4668	RTGCPHYS GCPhys = Pde.u & X86_PDE_PG_MASK;
4669	PX86PT pPT = NULL;
4670
4671	rc = PGM_GCPHYS_2_PTR(pVM, GCPhys, &pPT);
4672
4673	int rc2 = VERR_INVALID_PARAMETER;
4674	if (pPT)
4675	rc2 = pgmR3DumpHierarchyGC32BitPT(pVM, pPT, u32Address, PhysSearch);
4676	else
4677	Log(("%08x error! Page table at %#x was not found in the page pool!\n", u32Address, GCPhys));
4678	if (rc2 < rc && RT_SUCCESS(rc))
4679	rc = rc2;
4680	}
4681	}
4682	}
4683	}
4684
4685	return rc;
4686	}
4687
4688
4689	/**
4690	* Dumps a page table hierarchy use only physical addresses and cr4/lm flags.
4691	*
4692	* @returns VBox status code (VINF_SUCCESS).
4693	* @param pVM The VM handle.
4694	* @param cr3 The root of the hierarchy.
4695	* @param cr4 The cr4, only PAE and PSE is currently used.
4696	* @param fLongMode Set if long mode, false if not long mode.
4697	* @param cMaxDepth Number of levels to dump.
4698	* @param pHlp Pointer to the output functions.
4699	*/
4700	VMMR3DECL(int) PGMR3DumpHierarchyHC(PVM pVM, uint64_t cr3, uint64_t cr4, bool fLongMode, unsigned cMaxDepth, PCDBGFINFOHLP pHlp)
4701	{
4702	if (!pHlp)
4703	pHlp = DBGFR3InfoLogHlp();
4704	if (!cMaxDepth)
4705	return VINF_SUCCESS;
4706	const unsigned cch = fLongMode ? 16 : 8;
4707	pHlp->pfnPrintf(pHlp,
4708	"cr3=%08x cr4=%08x%s\n"
4709	"%-*s P - Present\n"
4710	"%-*s \| R/W - Read (0) / Write (1)\n"
4711	"%-*s \| \| U/S - User (1) / Supervisor (0)\n"
4712	"%-*s \| \| \| A - Accessed\n"
4713	"%-*s \| \| \| \| D - Dirty\n"
4714	"%-*s \| \| \| \| \| G - Global\n"
4715	"%-*s \| \| \| \| \| \| WT - Write thru\n"
4716	"%-*s \| \| \| \| \| \| \| CD - Cache disable\n"
4717	"%-*s \| \| \| \| \| \| \| \| AT - Attribute table (PAT)\n"
4718	"%-*s \| \| \| \| \| \| \| \| \| NX - No execute (K8)\n"
4719	"%-*s \| \| \| \| \| \| \| \| \| \| 4K/4M/2M - Page size.\n"
4720	"%-*s \| \| \| \| \| \| \| \| \| \| \| AVL - a=allocated; m=mapping; d=track dirty;\n"
4721	"%-*s \| \| \| \| \| \| \| \| \| \| \| \| p=permanent; v=validated;\n"
4722	"%-*s Level \| \| \| \| \| \| \| \| \| \| \| \| Page\n"
4723	/* xxxx n **** P R S A D G WT CD AT NX 4M AVL xxxxxxxxxxxxx
4724	- W U - - - -- -- -- -- -- 010 */
4725	, cr3, cr4, fLongMode ? " Long Mode" : "",
4726	cch, "", cch, "", cch, "", cch, "", cch, "", cch, "", cch, "",
4727	cch, "", cch, "", cch, "", cch, "", cch, "", cch, "", cch, "Address");
4728	if (cr4 & X86_CR4_PAE)
4729	{
4730	if (fLongMode)
4731	return pgmR3DumpHierarchyHcPaePML4(pVM, cr3 & X86_CR3_PAGE_MASK, cr4, cMaxDepth, pHlp);
4732	return pgmR3DumpHierarchyHCPaePDPT(pVM, cr3 & X86_CR3_PAE_PAGE_MASK, 0, cr4, false, cMaxDepth, pHlp);
4733	}
4734	return pgmR3DumpHierarchyHC32BitPD(pVM, cr3 & X86_CR3_PAGE_MASK, cr4, cMaxDepth, pHlp);
4735	}
4736
4737	#ifdef VBOX_WITH_DEBUGGER
4738
4739	/**
4740	* The '.pgmram' command.
4741	*
4742	* @returns VBox status.
4743	* @param pCmd Pointer to the command descriptor (as registered).
4744	* @param pCmdHlp Pointer to command helper functions.
4745	* @param pVM Pointer to the current VM (if any).
4746	* @param paArgs Pointer to (readonly) array of arguments.
4747	* @param cArgs Number of arguments in the array.
4748	*/
4749	static DECLCALLBACK(int) pgmR3CmdRam(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4750	{
4751	/*
4752	* Validate input.
4753	*/
4754	if (!pVM)
4755	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4756	if (!pVM->pgm.s.pRamRangesRC)
4757	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Sorry, no Ram is registered.\n");
4758
4759	/*
4760	* Dump the ranges.
4761	*/
4762	int rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL, "From - To (incl) pvHC\n");
4763	PPGMRAMRANGE pRam;
4764	for (pRam = pVM->pgm.s.pRamRangesR3; pRam; pRam = pRam->pNextR3)
4765	{
4766	rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL,
4767	"%RGp - %RGp %p\n",
4768	pRam->GCPhys, pRam->GCPhysLast, pRam->pvR3);
4769	if (RT_FAILURE(rc))
4770	return rc;
4771	}
4772
4773	return VINF_SUCCESS;
4774	}
4775
4776
4777	/**
4778	* The '.pgmmap' command.
4779	*
4780	* @returns VBox status.
4781	* @param pCmd Pointer to the command descriptor (as registered).
4782	* @param pCmdHlp Pointer to command helper functions.
4783	* @param pVM Pointer to the current VM (if any).
4784	* @param paArgs Pointer to (readonly) array of arguments.
4785	* @param cArgs Number of arguments in the array.
4786	*/
4787	static DECLCALLBACK(int) pgmR3CmdMap(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4788	{
4789	/*
4790	* Validate input.
4791	*/
4792	if (!pVM)
4793	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4794	if (!pVM->pgm.s.pMappingsR3)
4795	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Sorry, no mappings are registered.\n");
4796
4797	/*
4798	* Print message about the fixedness of the mappings.
4799	*/
4800	int rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL, pVM->pgm.s.fMappingsFixed ? "The mappings are FIXED.\n" : "The mappings are FLOATING.\n");
4801	if (RT_FAILURE(rc))
4802	return rc;
4803
4804	/*
4805	* Dump the ranges.
4806	*/
4807	PPGMMAPPING pCur;
4808	for (pCur = pVM->pgm.s.pMappingsR3; pCur; pCur = pCur->pNextR3)
4809	{
4810	rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL,
4811	"%08x - %08x %s\n",
4812	pCur->GCPtr, pCur->GCPtrLast, pCur->pszDesc);
4813	if (RT_FAILURE(rc))
4814	return rc;
4815	}
4816
4817	return VINF_SUCCESS;
4818	}
4819
4820
4821	/**
4822	* The '.pgmerror' and '.pgmerroroff' commands.
4823	*
4824	* @returns VBox status.
4825	* @param pCmd Pointer to the command descriptor (as registered).
4826	* @param pCmdHlp Pointer to command helper functions.
4827	* @param pVM Pointer to the current VM (if any).
4828	* @param paArgs Pointer to (readonly) array of arguments.
4829	* @param cArgs Number of arguments in the array.
4830	*/
4831	static DECLCALLBACK(int) pgmR3CmdError(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4832	{
4833	/*
4834	* Validate input.
4835	*/
4836	if (!pVM)
4837	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4838	AssertReturn(cArgs == 0 \|\| (cArgs == 1 && paArgs[0].enmType == DBGCVAR_TYPE_STRING),
4839	pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: Hit bug in the parser.\n"));
4840
4841	if (!cArgs)
4842	{
4843	/*
4844	* Print the list of error injection locations with status.
4845	*/
4846	pCmdHlp->pfnPrintf(pCmdHlp, NULL, "PGM error inject locations:\n");
4847	pCmdHlp->pfnPrintf(pCmdHlp, NULL, " handy - %RTbool\n", pVM->pgm.s.fErrInjHandyPages);
4848	}
4849	else
4850	{
4851
4852	/*
4853	* String switch on where to inject the error.
4854	*/
4855	bool const fNewState = !strcmp(pCmd->pszCmd, "pgmerror");
4856	const char *pszWhere = paArgs[0].u.pszString;
4857	if (!strcmp(pszWhere, "handy"))
4858	ASMAtomicWriteBool(&pVM->pgm.s.fErrInjHandyPages, fNewState);
4859	else
4860	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: Invalid 'where' value: %s.\n", pszWhere);
4861	pCmdHlp->pfnPrintf(pCmdHlp, NULL, "done\n");
4862	}
4863	return VINF_SUCCESS;
4864	}
4865
4866
4867	/**
4868	* The '.pgmsync' command.
4869	*
4870	* @returns VBox status.
4871	* @param pCmd Pointer to the command descriptor (as registered).
4872	* @param pCmdHlp Pointer to command helper functions.
4873	* @param pVM Pointer to the current VM (if any).
4874	* @param paArgs Pointer to (readonly) array of arguments.
4875	* @param cArgs Number of arguments in the array.
4876	*/
4877	static DECLCALLBACK(int) pgmR3CmdSync(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4878	{
4879	/** @todo SMP support */
4880	PVMCPU pVCpu = &pVM->aCpus[0];
4881
4882	/*
4883	* Validate input.
4884	*/
4885	if (!pVM)
4886	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4887
4888	/*
4889	* Force page directory sync.
4890	*/
4891	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
4892
4893	int rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Forcing page directory sync.\n");
4894	if (RT_FAILURE(rc))
4895	return rc;
4896
4897	return VINF_SUCCESS;
4898	}
4899
4900
4901	#ifdef VBOX_STRICT
4902	/**
4903	* The '.pgmassertcr3' command.
4904	*
4905	* @returns VBox status.
4906	* @param pCmd Pointer to the command descriptor (as registered).
4907	* @param pCmdHlp Pointer to command helper functions.
4908	* @param pVM Pointer to the current VM (if any).
4909	* @param paArgs Pointer to (readonly) array of arguments.
4910	* @param cArgs Number of arguments in the array.
4911	*/
4912	static DECLCALLBACK(int) pgmR3CmdAssertCR3(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4913	{
4914	/** @todo SMP support!! */
4915	PVMCPU pVCpu = &pVM->aCpus[0];
4916
4917	/*
4918	* Validate input.
4919	*/
4920	if (!pVM)
4921	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4922
4923	int rc = pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Checking shadow CR3 page tables for consistency.\n");
4924	if (RT_FAILURE(rc))
4925	return rc;
4926
4927	PGMAssertCR3(pVM, pVCpu, CPUMGetGuestCR3(pVCpu), CPUMGetGuestCR4(pVCpu));
4928
4929	return VINF_SUCCESS;
4930	}
4931	#endif /* VBOX_STRICT */
4932
4933
4934	/**
4935	* The '.pgmsyncalways' command.
4936	*
4937	* @returns VBox status.
4938	* @param pCmd Pointer to the command descriptor (as registered).
4939	* @param pCmdHlp Pointer to command helper functions.
4940	* @param pVM Pointer to the current VM (if any).
4941	* @param paArgs Pointer to (readonly) array of arguments.
4942	* @param cArgs Number of arguments in the array.
4943	*/
4944	static DECLCALLBACK(int) pgmR3CmdSyncAlways(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4945	{
4946	/** @todo SMP support!! */
4947	PVMCPU pVCpu = &pVM->aCpus[0];
4948
4949	/*
4950	* Validate input.
4951	*/
4952	if (!pVM)
4953	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4954
4955	/*
4956	* Force page directory sync.
4957	*/
4958	if (pVCpu->pgm.s.fSyncFlags & PGM_SYNC_ALWAYS)
4959	{
4960	ASMAtomicAndU32(&pVCpu->pgm.s.fSyncFlags, ~PGM_SYNC_ALWAYS);
4961	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Disabled permanent forced page directory syncing.\n");
4962	}
4963	else
4964	{
4965	ASMAtomicOrU32(&pVCpu->pgm.s.fSyncFlags, PGM_SYNC_ALWAYS);
4966	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
4967	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Enabled permanent forced page directory syncing.\n");
4968	}
4969	}
4970
4971
4972	/**
4973	* The '.pgmsyncalways' command.
4974	*
4975	* @returns VBox status.
4976	* @param pCmd Pointer to the command descriptor (as registered).
4977	* @param pCmdHlp Pointer to command helper functions.
4978	* @param pVM Pointer to the current VM (if any).
4979	* @param paArgs Pointer to (readonly) array of arguments.
4980	* @param cArgs Number of arguments in the array.
4981	*/
4982	static DECLCALLBACK(int) pgmR3CmdPhysToFile(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PVM pVM, PCDBGCVAR paArgs, unsigned cArgs, PDBGCVAR pResult)
4983	{
4984	/*
4985	* Validate input.
4986	*/
4987	if (!pVM)
4988	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: The command requires a VM to be selected.\n");
4989	if ( cArgs < 1
4990	\|\| cArgs > 2
4991	\|\| paArgs[0].enmType != DBGCVAR_TYPE_STRING
4992	\|\| ( cArgs > 1
4993	&& paArgs[1].enmType != DBGCVAR_TYPE_STRING))
4994	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: parser error, invalid arguments.\n");
4995	if ( cArgs >= 2
4996	&& strcmp(paArgs[1].u.pszString, "nozero"))
4997	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: Invalid 2nd argument '%s', must be 'nozero'.\n", paArgs[1].u.pszString);
4998	bool fIncZeroPgs = cArgs < 2;
4999
5000	/*
5001	* Open the output file and get the ram parameters.
5002	*/
5003	RTFILE hFile;
5004	int rc = RTFileOpen(&hFile, paArgs[0].u.pszString, RTFILE_O_WRITE \| RTFILE_O_CREATE_REPLACE \| RTFILE_O_DENY_WRITE);
5005	if (RT_FAILURE(rc))
5006	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: RTFileOpen(,'%s',) -> %Rrc.\n", paArgs[0].u.pszString, rc);
5007
5008	uint32_t cbRamHole = 0;
5009	CFGMR3QueryU32Def(CFGMR3GetRoot(pVM), "RamHoleSize", &cbRamHole, MM_RAM_HOLE_SIZE_DEFAULT);
5010	uint64_t cbRam = 0;
5011	CFGMR3QueryU64Def(CFGMR3GetRoot(pVM), "RamSize", &cbRam, 0);
5012	RTGCPHYS GCPhysEnd = cbRam + cbRamHole;
5013
5014	/*
5015	* Dump the physical memory, page by page.
5016	*/
5017	RTGCPHYS GCPhys = 0;
5018	char abZeroPg[PAGE_SIZE];
5019	RT_ZERO(abZeroPg);
5020
5021	pgmLock(pVM);
5022	for (PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesR3;
5023	pRam && pRam->GCPhys < GCPhysEnd && RT_SUCCESS(rc);
5024	pRam = pRam->pNextR3)
5025	{
5026	/* fill the gap */
5027	if (pRam->GCPhys > GCPhys && fIncZeroPgs)
5028	{
5029	while (pRam->GCPhys > GCPhys && RT_SUCCESS(rc))
5030	{
5031	rc = RTFileWrite(hFile, abZeroPg, PAGE_SIZE, NULL);
5032	GCPhys += PAGE_SIZE;
5033	}
5034	}
5035
5036	PCPGMPAGE pPage = &pRam->aPages[0];
5037	while (GCPhys < pRam->GCPhysLast && RT_SUCCESS(rc))
5038	{
5039	if (PGM_PAGE_IS_ZERO(pPage))
5040	{
5041	if (fIncZeroPgs)
5042	{
5043	rc = RTFileWrite(hFile, abZeroPg, PAGE_SIZE, NULL);
5044	if (RT_FAILURE(rc))
5045	pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: RTFileWrite -> %Rrc at GCPhys=%RGp.\n", rc, GCPhys);
5046	}
5047	}
5048	else
5049	{
5050	switch (PGM_PAGE_GET_TYPE(pPage))
5051	{
5052	case PGMPAGETYPE_RAM:
5053	case PGMPAGETYPE_ROM_SHADOW: /* trouble?? */
5054	case PGMPAGETYPE_ROM:
5055	case PGMPAGETYPE_MMIO2:
5056	{
5057	void const *pvPage;
5058	PGMPAGEMAPLOCK Lock;
5059	rc = PGMPhysGCPhys2CCPtrReadOnly(pVM, GCPhys, &pvPage, &Lock);
5060	if (RT_SUCCESS(rc))
5061	{
5062	rc = RTFileWrite(hFile, pvPage, PAGE_SIZE, NULL);
5063	PGMPhysReleasePageMappingLock(pVM, &Lock);
5064	if (RT_FAILURE(rc))
5065	pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: RTFileWrite -> %Rrc at GCPhys=%RGp.\n", rc, GCPhys);
5066	}
5067	else
5068	pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: PGMPhysGCPhys2CCPtrReadOnly -> %Rrc at GCPhys=%RGp.\n", rc, GCPhys);
5069	break;
5070	}
5071
5072	default:
5073	AssertFailed();
5074	case PGMPAGETYPE_MMIO2_ALIAS_MMIO:
5075	case PGMPAGETYPE_MMIO:
5076	if (fIncZeroPgs)
5077	{
5078	rc = RTFileWrite(hFile, abZeroPg, PAGE_SIZE, NULL);
5079	if (RT_FAILURE(rc))
5080	pCmdHlp->pfnPrintf(pCmdHlp, NULL, "error: RTFileWrite -> %Rrc at GCPhys=%RGp.\n", rc, GCPhys);
5081	}
5082	break;
5083	}
5084	}
5085
5086
5087	/* advance */
5088	GCPhys += PAGE_SIZE;
5089	pPage++;
5090	}
5091	}
5092	pgmUnlock(pVM);
5093
5094	RTFileClose(hFile);
5095	if (RT_SUCCESS(rc))
5096	return pCmdHlp->pfnPrintf(pCmdHlp, NULL, "Successfully saved physical memory to '%s'.\n", paArgs[0].u.pszString);
5097	return VINF_SUCCESS;
5098	}
5099
5100	#endif /* VBOX_WITH_DEBUGGER */
5101
5102	/**
5103	* pvUser argument of the pgmR3CheckIntegrity*Node callbacks.
5104	*/
5105	typedef struct PGMCHECKINTARGS
5106	{
5107	bool fLeftToRight; /*< true: left-to-right; false: right-to-left. /
5108	PPGMPHYSHANDLER pPrevPhys;
5109	PPGMVIRTHANDLER pPrevVirt;
5110	PPGMPHYS2VIRTHANDLER pPrevPhys2Virt;
5111	PVM pVM;
5112	} PGMCHECKINTARGS, *PPGMCHECKINTARGS;
5113
5114	/**
5115	* Validate a node in the physical handler tree.
5116	*
5117	* @returns 0 on if ok, other wise 1.
5118	* @param pNode The handler node.
5119	* @param pvUser pVM.
5120	*/
5121	static DECLCALLBACK(int) pgmR3CheckIntegrityPhysHandlerNode(PAVLROGCPHYSNODECORE pNode, void *pvUser)
5122	{
5123	PPGMCHECKINTARGS pArgs = (PPGMCHECKINTARGS)pvUser;
5124	PPGMPHYSHANDLER pCur = (PPGMPHYSHANDLER)pNode;
5125	AssertReleaseReturn(!((uintptr_t)pCur & 7), 1);
5126	AssertReleaseMsg(pCur->Core.Key <= pCur->Core.KeyLast,("pCur=%p %RGp-%RGp %s\n", pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
5127	AssertReleaseMsg( !pArgs->pPrevPhys
5128	\|\| (pArgs->fLeftToRight ? pArgs->pPrevPhys->Core.KeyLast < pCur->Core.Key : pArgs->pPrevPhys->Core.KeyLast > pCur->Core.Key),
5129	("pPrevPhys=%p %RGp-%RGp %s\n"
5130	" pCur=%p %RGp-%RGp %s\n",
5131	pArgs->pPrevPhys, pArgs->pPrevPhys->Core.Key, pArgs->pPrevPhys->Core.KeyLast, pArgs->pPrevPhys->pszDesc,
5132	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
5133	pArgs->pPrevPhys = pCur;
5134	return 0;
5135	}
5136
5137
5138	/**
5139	* Validate a node in the virtual handler tree.
5140	*
5141	* @returns 0 on if ok, other wise 1.
5142	* @param pNode The handler node.
5143	* @param pvUser pVM.
5144	*/
5145	static DECLCALLBACK(int) pgmR3CheckIntegrityVirtHandlerNode(PAVLROGCPTRNODECORE pNode, void *pvUser)
5146	{
5147	PPGMCHECKINTARGS pArgs = (PPGMCHECKINTARGS)pvUser;
5148	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)pNode;
5149	AssertReleaseReturn(!((uintptr_t)pCur & 7), 1);
5150	AssertReleaseMsg(pCur->Core.Key <= pCur->Core.KeyLast,("pCur=%p %RGv-%RGv %s\n", pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
5151	AssertReleaseMsg( !pArgs->pPrevVirt
5152	\|\| (pArgs->fLeftToRight ? pArgs->pPrevVirt->Core.KeyLast < pCur->Core.Key : pArgs->pPrevVirt->Core.KeyLast > pCur->Core.Key),
5153	("pPrevVirt=%p %RGv-%RGv %s\n"
5154	" pCur=%p %RGv-%RGv %s\n",
5155	pArgs->pPrevVirt, pArgs->pPrevVirt->Core.Key, pArgs->pPrevVirt->Core.KeyLast, pArgs->pPrevVirt->pszDesc,
5156	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
5157	for (unsigned iPage = 0; iPage < pCur->cPages; iPage++)
5158	{
5159	AssertReleaseMsg(pCur->aPhysToVirt[iPage].offVirtHandler == -RT_OFFSETOF(PGMVIRTHANDLER, aPhysToVirt[iPage]),
5160	("pCur=%p %RGv-%RGv %s\n"
5161	"iPage=%d offVirtHandle=%#x expected %#x\n",
5162	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc,
5163	iPage, pCur->aPhysToVirt[iPage].offVirtHandler, -RT_OFFSETOF(PGMVIRTHANDLER, aPhysToVirt[iPage])));
5164	}
5165	pArgs->pPrevVirt = pCur;
5166	return 0;
5167	}
5168
5169
5170	/**
5171	* Validate a node in the virtual handler tree.
5172	*
5173	* @returns 0 on if ok, other wise 1.
5174	* @param pNode The handler node.
5175	* @param pvUser pVM.
5176	*/
5177	static DECLCALLBACK(int) pgmR3CheckIntegrityPhysToVirtHandlerNode(PAVLROGCPHYSNODECORE pNode, void *pvUser)
5178	{
5179	PPGMCHECKINTARGS pArgs = (PPGMCHECKINTARGS)pvUser;
5180	PPGMPHYS2VIRTHANDLER pCur = (PPGMPHYS2VIRTHANDLER)pNode;
5181	AssertReleaseMsgReturn(!((uintptr_t)pCur & 3), ("\n"), 1);
5182	AssertReleaseMsgReturn(!(pCur->offVirtHandler & 3), ("\n"), 1);
5183	AssertReleaseMsg(pCur->Core.Key <= pCur->Core.KeyLast,("pCur=%p %RGp-%RGp\n", pCur, pCur->Core.Key, pCur->Core.KeyLast));
5184	AssertReleaseMsg( !pArgs->pPrevPhys2Virt
5185	\|\| (pArgs->fLeftToRight ? pArgs->pPrevPhys2Virt->Core.KeyLast < pCur->Core.Key : pArgs->pPrevPhys2Virt->Core.KeyLast > pCur->Core.Key),
5186	("pPrevPhys2Virt=%p %RGp-%RGp\n"
5187	" pCur=%p %RGp-%RGp\n",
5188	pArgs->pPrevPhys2Virt, pArgs->pPrevPhys2Virt->Core.Key, pArgs->pPrevPhys2Virt->Core.KeyLast,
5189	pCur, pCur->Core.Key, pCur->Core.KeyLast));
5190	AssertReleaseMsg( !pArgs->pPrevPhys2Virt
5191	\|\| (pArgs->fLeftToRight ? pArgs->pPrevPhys2Virt->Core.KeyLast < pCur->Core.Key : pArgs->pPrevPhys2Virt->Core.KeyLast > pCur->Core.Key),
5192	("pPrevPhys2Virt=%p %RGp-%RGp\n"
5193	" pCur=%p %RGp-%RGp\n",
5194	pArgs->pPrevPhys2Virt, pArgs->pPrevPhys2Virt->Core.Key, pArgs->pPrevPhys2Virt->Core.KeyLast,
5195	pCur, pCur->Core.Key, pCur->Core.KeyLast));
5196	AssertReleaseMsg((pCur->offNextAlias & (PGMPHYS2VIRTHANDLER_IN_TREE \| PGMPHYS2VIRTHANDLER_IS_HEAD)) == (PGMPHYS2VIRTHANDLER_IN_TREE \| PGMPHYS2VIRTHANDLER_IS_HEAD),
5197	("pCur=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
5198	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias));
5199	if (pCur->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK)
5200	{
5201	PPGMPHYS2VIRTHANDLER pCur2 = pCur;
5202	for (;;)
5203	{
5204	pCur2 = (PPGMPHYS2VIRTHANDLER)((intptr_t)pCur + (pCur->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK));
5205	AssertReleaseMsg(pCur2 != pCur,
5206	(" pCur=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
5207	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias));
5208	AssertReleaseMsg((pCur2->offNextAlias & (PGMPHYS2VIRTHANDLER_IN_TREE \| PGMPHYS2VIRTHANDLER_IS_HEAD)) == PGMPHYS2VIRTHANDLER_IN_TREE,
5209	(" pCur=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
5210	"pCur2=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
5211	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias,
5212	pCur2, pCur2->Core.Key, pCur2->Core.KeyLast, pCur2->offVirtHandler, pCur2->offNextAlias));
5213	AssertReleaseMsg((pCur2->Core.Key ^ pCur->Core.Key) < PAGE_SIZE,
5214	(" pCur=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
5215	"pCur2=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
5216	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias,
5217	pCur2, pCur2->Core.Key, pCur2->Core.KeyLast, pCur2->offVirtHandler, pCur2->offNextAlias));
5218	AssertReleaseMsg((pCur2->Core.KeyLast ^ pCur->Core.KeyLast) < PAGE_SIZE,
5219	(" pCur=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
5220	"pCur2=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
5221	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias,
5222	pCur2, pCur2->Core.Key, pCur2->Core.KeyLast, pCur2->offVirtHandler, pCur2->offNextAlias));
5223	if (!(pCur2->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK))
5224	break;
5225	}
5226	}
5227
5228	pArgs->pPrevPhys2Virt = pCur;
5229	return 0;
5230	}
5231
5232
5233	/**
5234	* Perform an integrity check on the PGM component.
5235	*
5236	* @returns VINF_SUCCESS if everything is fine.
5237	* @returns VBox error status after asserting on integrity breach.
5238	* @param pVM The VM handle.
5239	*/
5240	VMMR3DECL(int) PGMR3CheckIntegrity(PVM pVM)
5241	{
5242	AssertReleaseReturn(pVM->pgm.s.offVM, VERR_INTERNAL_ERROR);
5243
5244	/*
5245	* Check the trees.
5246	*/
5247	int cErrors = 0;
5248	const static PGMCHECKINTARGS s_LeftToRight = { true, NULL, NULL, NULL, pVM };
5249	const static PGMCHECKINTARGS s_RightToLeft = { false, NULL, NULL, NULL, pVM };
5250	PGMCHECKINTARGS Args = s_LeftToRight;
5251	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysHandlers, true, pgmR3CheckIntegrityPhysHandlerNode, &Args);
5252	Args = s_RightToLeft;
5253	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysHandlers, false, pgmR3CheckIntegrityPhysHandlerNode, &Args);
5254	Args = s_LeftToRight;
5255	cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesR3->VirtHandlers, true, pgmR3CheckIntegrityVirtHandlerNode, &Args);
5256	Args = s_RightToLeft;
5257	cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesR3->VirtHandlers, false, pgmR3CheckIntegrityVirtHandlerNode, &Args);
5258	Args = s_LeftToRight;
5259	cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesR3->HyperVirtHandlers, true, pgmR3CheckIntegrityVirtHandlerNode, &Args);
5260	Args = s_RightToLeft;
5261	cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesR3->HyperVirtHandlers, false, pgmR3CheckIntegrityVirtHandlerNode, &Args);
5262	Args = s_LeftToRight;
5263	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysToVirtHandlers, true, pgmR3CheckIntegrityPhysToVirtHandlerNode, &Args);
5264	Args = s_RightToLeft;
5265	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysToVirtHandlers, false, pgmR3CheckIntegrityPhysToVirtHandlerNode, &Args);
5266
5267	return !cErrors ? VINF_SUCCESS : VERR_INTERNAL_ERROR;
5268	}
5269
5270

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source: vbox/trunk/src/VBox/VMM/PGM.cpp@ 22017

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